lib/libc/arch/or1k/gen/fpgetround.c

48

#define FPCSR_RND __BITS(2,1)

lib/libc/locale/c16rtomb.c

180

c32 = __SHIFTIN(__SHIFTOUT(w1, __BITS(9,0)), __BITS(19,10)) |

lib/libc/locale/c16rtomb.c

181

__SHIFTIN(__SHIFTOUT(w2, __BITS(9,0)), __BITS(9,0));

lib/libc/locale/c8rtomb.c

196

state = __SHIFTOUT(S->state_c32, __BITS(31,24));

lib/libc/locale/c8rtomb.c

197

c32 = __SHIFTOUT(S->state_c32, __BITS(23,0));

lib/libc/locale/c8rtomb.c

216

__SHIFTIN(state, __BITS(31,24)) |

lib/libc/locale/c8rtomb.c

217

__SHIFTIN(c32, __BITS(23,0));

lib/libc/locale/mbrtoc16.c

199

const char16_t w1 = 0xd800 | __SHIFTOUT(c32, __BITS(19,10));

lib/libc/locale/mbrtoc16.c

200

const char16_t w2 = 0xdc00 | __SHIFTOUT(c32, __BITS(9,0));

lib/libc/locale/mbrtoc8.c

198

*pc8 = 0xc0 | __SHIFTOUT(c32, __BITS(10,6));

lib/libc/locale/mbrtoc8.c

199

S->buf[2] = 0x80 | __SHIFTOUT(c32, __BITS(5,0));

lib/libc/locale/mbrtoc8.c

204

*pc8 = 0xe0 | __SHIFTOUT(c32, __BITS(15,12));

lib/libc/locale/mbrtoc8.c

205

S->buf[1] = 0x80 | __SHIFTOUT(c32, __BITS(11,6));

lib/libc/locale/mbrtoc8.c

206

S->buf[2] = 0x80 | __SHIFTOUT(c32, __BITS(5,0));

lib/libc/locale/mbrtoc8.c

211

*pc8 = 0xf0 | __SHIFTOUT(c32, __BITS(20,18));

lib/libc/locale/mbrtoc8.c

212

S->buf[0] = 0x80 | __SHIFTOUT(c32, __BITS(17,12));

lib/libc/locale/mbrtoc8.c

213

S->buf[1] = 0x80 | __SHIFTOUT(c32, __BITS(11,6));

lib/libc/locale/mbrtoc8.c

214

S->buf[2] = 0x80 | __SHIFTOUT(c32, __BITS(5,0));

lib/libkvm/kvm_aarch64.c

112

const uint64_t page_mask = __BITS(page_shift - 1, 0);

lib/libkvm/kvm_aarch64.c

113

const uint64_t page_addr = __BITS(47, page_shift);

lib/libkvm/kvm_aarch64.c

120

va &= __BITS(inputsz - 1, 0);

lib/libkvm/kvm_aarch64.c

131

const uint64_t idx_mask = __BITS(addr_shift + pte_shift - 1,

lib/libkvm/kvm_aarch64.c

150

const uint64_t blk_mask = __BITS(addr_shift - 1, 0);

lib/libm/complex/catrigl.c

98

u.extu_exp &= __BITS(0, EXT_EXPBITS - 1); \

lib/libnvmm/libnvmm_x86.c

118

#define CR3_FRAME_32BIT __BITS(31, 12)

lib/libnvmm/libnvmm_x86.c

191

#define CR3_FRAME_32BIT_PAE __BITS(31, 5)

lib/libnvmm/libnvmm_x86.c

283

#define CR3_FRAME_64BIT __BITS(51, 12)

sbin/efi/bootvar.h

42

#define LOAD_OPTION_CATEGORY __BITS(12,8)

sbin/efi/defs.h

41

#define DEBUG_MASK __BITS(15,0)

sbin/efi/devpath2.c

67

text[0] = (char)__SHIFTOUT(u.b[0], __BITS(4,0));

sbin/efi/devpath2.c

68

text[1] = (char)__SHIFTOUT(u.b[0], __BITS(7,5));

sbin/efi/devpath2.c

69

text[1] |= (char)__SHIFTOUT(u.b[1], __BITS(1,0)) << 3;

sbin/efi/devpath2.c

70

text[2] = (char)__SHIFTOUT(u.b[1], __BITS(7,2));

sbin/efi/devpath3.c

1040

switch (__SHIFTOUT(LoginOptions, __BITS(1,0))) {

sbin/efi/devpath3.c

1051

switch (__SHIFTOUT(LoginOptions, __BITS(3,2))) {

sbin/efi/devpath3.c

1062

switch (__SHIFTOUT(LoginOptions, __BITS(12,10))) {

sbin/efi/devpath3.c

417

#define SASINFO_BYTES_MASK __BITS(3,0)

sbin/efi/devpath5.c

65

#define BIOS_STATUS_OLD_POSITION __BITS(3,0)

sbin/efi/devpath5.c

68

#define BIOS_STATUS_MEDIA __BITS(11,10)

sbin/efi/devpath5.c

73

#define BIOS_STATUS_RESERVED (__BITS(15,12) | __BITS(7,4))

sbin/efi/showvar.c

86

#define EFI_BOOT_OPTION_SUPPORT_COUNT __BITS(8,9) // 0x00000300

sbin/nvmectl/nvme.h

114

#define NVME_FW_PAGE_AFI_SLOT_RST __BITS(4, 6)

sbin/nvmectl/nvme.h

115

#define NVME_FW_PAGE_AFI_SLOT __BITS(0, 2)

sbin/nvmectl/nvme.h

138

#define NVME_CE_PAGE_CS_CSE __BITS(16, 18)

sys/arch/aarch64/aarch64/aarch64_tlb.c

111

mapp[0] ^= __BITS(0, KERNEL_PID);

sys/arch/aarch64/aarch64/db_machdep.c

460

(va & __BITS(PAR_PA_SHIFT - 1, 0));

sys/arch/aarch64/aarch64/kobj_machdep.c

106

const Elf_Addr mask = ~__BITS(bitwidth - 1, 0);

sys/arch/aarch64/aarch64/kobj_machdep.c

257

(le32toh(*insn) & ~__BITS(21,10)) | (val << 10));

sys/arch/aarch64/aarch64/kobj_machdep.c

279

~(__BITS(30,29) | __BITS(23,5))) |

sys/arch/aarch64/aarch64/kobj_machdep.c

302

*insn = htole32((le32toh(*insn) & ~__BITS(25,0)) | val);

sys/arch/aarch64/aarch64/pmap.c

747

(va & __BITS(PAR_PA_SHIFT - 1, 0));

sys/arch/aarch64/include/armreg.h

1026

#define SCTLR_TCF0 __BITS(39,38)

sys/arch/aarch64/include/armreg.h

1027

#define SCTLR_TCF __BITS(41,40)

sys/arch/aarch64/include/armreg.h

1056

#define SPSR_NZCV __BITS(31,28) // mask of N Z C V

sys/arch/aarch64/include/armreg.h

1068

#define SPSR_GE __BITS(19,16) // A32: SIMD GE

sys/arch/aarch64/include/armreg.h

1075

#define SPSR_A64_BTYPE __BITS(11,10) // A64: BTYPE

sys/arch/aarch64/include/armreg.h

1083

#define SPSR_M __BITS(4,0) // Execution State

sys/arch/aarch64/include/armreg.h

1129

#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */

sys/arch/aarch64/include/armreg.h

1137

#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */

sys/arch/aarch64/include/armreg.h

1141

#define TCR_SH1 __BITS(29,28)

sys/arch/aarch64/include/armreg.h

1145

#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */

sys/arch/aarch64/include/armreg.h

115

#define CTR_EL0_TMIN_LINE __BITS(37,32) // Tag MIN LINE size

sys/arch/aarch64/include/armreg.h

1150

#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */

sys/arch/aarch64/include/armreg.h

1157

#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */

sys/arch/aarch64/include/armreg.h

1158

#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */

sys/arch/aarch64/include/armreg.h

1162

#define TCR_SH0 __BITS(13,12)

sys/arch/aarch64/include/armreg.h

1166

#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */

sys/arch/aarch64/include/armreg.h

1171

#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */

sys/arch/aarch64/include/armreg.h

1177

#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */

sys/arch/aarch64/include/armreg.h

118

#define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule

sys/arch/aarch64/include/armreg.h

119

#define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule

sys/arch/aarch64/include/armreg.h

1199

#define TCR_EL2_PS __BITS(18,16) // Physical Address Size

sys/arch/aarch64/include/armreg.h

120

#define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2)

sys/arch/aarch64/include/armreg.h

1200

#define TCR_EL2_TG0 __BITS(15,14) // TTBR0_EL2 Granule size

sys/arch/aarch64/include/armreg.h

1204

#define TCR_EL2_SH0 __BITS(13,12) // TTBR0_EL2 Shareability attribute

sys/arch/aarch64/include/armreg.h

1208

#define TCR_EL2_ORGN0 __BITS(11,10) // TTBR0_EL2 Outer cacheability attribute

sys/arch/aarch64/include/armreg.h

121

#define CTR_EL0_L1IP_MASK __BITS(15,14)

sys/arch/aarch64/include/armreg.h

1213

#define TCR_EL2_IRGN0 __BITS(9,8) // TTBR0_EL2 Inner cacheability attribute

sys/arch/aarch64/include/armreg.h

1218

#define TCR_EL2_T0SZ __BITS(5,0) // TTBR0_EL2 Size offset

sys/arch/aarch64/include/armreg.h

1235

#define TTBR_ASID __BITS(63,48)

sys/arch/aarch64/include/armreg.h

1236

#define TTBR_BADDR __BITS(47,0)

sys/arch/aarch64/include/armreg.h

126

#define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2)

sys/arch/aarch64/include/armreg.h

1273

#define VTCR_EL2_PS __BITS(18,16) // Physical address Size

sys/arch/aarch64/include/armreg.h

1274

#define VTCR_EL2_TG0 __BITS(15,14) // VTTBR_EL2 Granule size

sys/arch/aarch64/include/armreg.h

1275

#define VTCR_EL2_SH0 __BITS(13,12) // V{,S}TTBR_EL2 shareability attribute

sys/arch/aarch64/include/armreg.h

1276

#define VTCR_EL2_ORGN0 __BITS(11,10) // V{,S}TTBR_EL2 outer cacheability

sys/arch/aarch64/include/armreg.h

1277

#define VTCR_EL2_IRGN0 __BITS(9,8) // V{,S}TTBR_EL2 inner cacheability

sys/arch/aarch64/include/armreg.h

1278

#define VTCR_EL2_SL0 __BITS(7,6) // Start Level of S2 translation lookup.

sys/arch/aarch64/include/armreg.h

1279

#define VTCR_EL2_T0SZ __BITS(5,0) // VTTBR_EL2 Size offset

sys/arch/aarch64/include/armreg.h

1285

#define VTTBR_VIMD __BITS(55,48)

sys/arch/aarch64/include/armreg.h

1286

#define VTTBR_BADDR __BITS(47,0)

sys/arch/aarch64/include/armreg.h

131

#define DCZID_BS __BITS(3,0) // Block Size (log2 - 2)

sys/arch/aarch64/include/armreg.h

1324

#define DBGBCR_BT __BITS(23,20)

sys/arch/aarch64/include/armreg.h

1325

#define DBGBCR_LBN __BITS(19,16)

sys/arch/aarch64/include/armreg.h

1326

#define DBGBCR_SSC __BITS(15,14)

sys/arch/aarch64/include/armreg.h

1328

#define DBGBCR_BAS __BITS(8,5)

sys/arch/aarch64/include/armreg.h

1329

#define DBGBCR_PMC __BITS(2,1)

sys/arch/aarch64/include/armreg.h

1365

#define DBGBVR_MASK __BITS(63,2)

sys/arch/aarch64/include/armreg.h

139

#define FPCR_RMODE __BITS(23,22) // Rounding Mode

sys/arch/aarch64/include/armreg.h

1400

#define DBGWCR_MASK __BITS(28,24)

sys/arch/aarch64/include/armreg.h

1402

#define DBGWCR_LBN __BITS(19,16)

sys/arch/aarch64/include/armreg.h

1403

#define DBGWCR_SSC __BITS(15,14)

sys/arch/aarch64/include/armreg.h

1405

#define DBGWCR_BAS __BITS(12,5)

sys/arch/aarch64/include/armreg.h

1406

#define DBGWCR_LSC __BITS(4,3)

sys/arch/aarch64/include/armreg.h

1407

#define DBGWCR_PAC __BITS(2,1)

sys/arch/aarch64/include/armreg.h

144

#define FPCR_STRIDE __BITS(21,20)

sys/arch/aarch64/include/armreg.h

1443

#define DBGWVR_MASK __BITS(63,2)

sys/arch/aarch64/include/armreg.h

1453

#define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis

sys/arch/aarch64/include/armreg.h

146

#define FPCR_LEN __BITS(18,16)

sys/arch/aarch64/include/armreg.h

1489

#define PMCNTEN_P __BITS(30,0) // Enable event counter bits

sys/arch/aarch64/include/armreg.h

1494

#define PMCR_IMP __BITS(31,24) // Implementor code

sys/arch/aarch64/include/armreg.h

1495

#define PMCR_IDCODE __BITS(23,16) // Identification code

sys/arch/aarch64/include/armreg.h

1496

#define PMCR_N __BITS(15,11) // Number of event counters

sys/arch/aarch64/include/armreg.h

1522

#define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count

sys/arch/aarch64/include/armreg.h

1528

#define PMINTEN_P __BITS(30,0) // for event counters (0-30)

sys/arch/aarch64/include/armreg.h

1535

#define PMOVS_P __BITS(30,0) // for event counters (0-30)

sys/arch/aarch64/include/armreg.h

1571

#define CNTKCTL_ELNTI __BITS(7,4)

sys/arch/aarch64/include/armreg.h

1609

#define ID_AA64PFR0_EL1_CSV3 __BITS(63,60) // Speculative fault data

sys/arch/aarch64/include/armreg.h

1612

#define ID_AA64PFR0_EL1_CSV2 __BITS(59,56) // Speculative branches

sys/arch/aarch64/include/armreg.h

1616

#define ID_AA64PFR0_EL1_DIT __BITS(51,48) // Data-indep. timing

sys/arch/aarch64/include/armreg.h

1619

#define ID_AA64PFR0_EL1_AMU __BITS(47,44) // Activity monitors ext.

sys/arch/aarch64/include/armreg.h

1623

#define ID_AA64PFR0_EL1_MPAM __BITS(43,40) // MPAM Extension

sys/arch/aarch64/include/armreg.h

1626

#define ID_AA64PFR0_EL1_SEL2 __BITS(39,36) // Secure EL2

sys/arch/aarch64/include/armreg.h

1629

#define ID_AA64PFR0_EL1_SVE __BITS(35,32) // Scalable Vector

sys/arch/aarch64/include/armreg.h

1632

#define ID_AA64PFR0_EL1_RAS __BITS(31,28) // RAS Extension

sys/arch/aarch64/include/armreg.h

1636

#define ID_AA64PFR0_EL1_GIC __BITS(27,24) // GIC CPU IF

sys/arch/aarch64/include/armreg.h

1640

#define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD

sys/arch/aarch64/include/armreg.h

1644

#define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP

sys/arch/aarch64/include/armreg.h

1648

#define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling

sys/arch/aarch64/include/armreg.h

1652

#define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling

sys/arch/aarch64/include/armreg.h

1656

#define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling

sys/arch/aarch64/include/armreg.h

1659

#define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling

sys/arch/aarch64/include/armreg.h

1690

#define ICC_BPR_EL1_BinaryPoint __BITS(2,0)

sys/arch/aarch64/include/armreg.h

1695

#define ICC_CTLR_EL1_IDbits __BITS(13,11)

sys/arch/aarch64/include/armreg.h

1696

#define ICC_CTLR_EL1_PRIbits __BITS(10,8)

sys/arch/aarch64/include/armreg.h

1705

#define ICC_SGIR_EL1_Aff3 __BITS(55,48)

sys/arch/aarch64/include/armreg.h

1707

#define ICC_SGIR_EL1_Aff2 __BITS(39,32)

sys/arch/aarch64/include/armreg.h

1708

#define ICC_SGIR_EL1_INTID __BITS(27,24)

sys/arch/aarch64/include/armreg.h

1709

#define ICC_SGIR_EL1_Aff1 __BITS(23,16)

sys/arch/aarch64/include/armreg.h

1710

#define ICC_SGIR_EL1_TargetList __BITS(15,0)

sys/arch/aarch64/include/armreg.h

1714

#define ICC_IAR_INTID __BITS(23,0)

sys/arch/aarch64/include/armreg.h

195

#define CBAR_PA __BITS(47,18)

sys/arch/aarch64/include/armreg.h

204

#define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1

sys/arch/aarch64/include/armreg.h

205

#define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1

sys/arch/aarch64/include/armreg.h

206

#define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line

sys/arch/aarch64/include/armreg.h

209

#define CCSIDR64_NUMSET __BITS(55,32) // (Number of sets in cache) - 1

sys/arch/aarch64/include/armreg.h

210

#define CCSIDR64_ASSOC __BITS(23,3) // (Associativity of cache) - 1

sys/arch/aarch64/include/armreg.h

211

#define CCSIDR64_LINESIZE __BITS(2,0) // Number of bytes in cache line

sys/arch/aarch64/include/armreg.h

215

#define CLIDR_ICB __BITS(32,30) // Inner cache boundary

sys/arch/aarch64/include/armreg.h

216

#define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor

sys/arch/aarch64/include/armreg.h

217

#define CLIDR_LOC __BITS(26,24) // Level of Coherency

sys/arch/aarch64/include/armreg.h

218

#define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/

sys/arch/aarch64/include/armreg.h

219

#define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7

sys/arch/aarch64/include/armreg.h

220

#define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6

sys/arch/aarch64/include/armreg.h

221

#define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5

sys/arch/aarch64/include/armreg.h

222

#define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4

sys/arch/aarch64/include/armreg.h

223

#define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3

sys/arch/aarch64/include/armreg.h

224

#define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2

sys/arch/aarch64/include/armreg.h

225

#define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1

sys/arch/aarch64/include/armreg.h

237

#define CURRENTEL_EL __BITS(3,2) // Current exception Level

sys/arch/aarch64/include/armreg.h

243

#define ID_AA64DFR0_EL1_TRACEFILT __BITS(43,40)

sys/arch/aarch64/include/armreg.h

246

#define ID_AA64DFR0_EL1_DBLLOCK __BITS(39,36)

sys/arch/aarch64/include/armreg.h

249

#define ID_AA64DFR0_EL1_PMSVER __BITS(35,32)

sys/arch/aarch64/include/armreg.h

250

#define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28)

sys/arch/aarch64/include/armreg.h

251

#define ID_AA64DFR0_EL1_WRPS __BITS(20,23)

sys/arch/aarch64/include/armreg.h

252

#define ID_AA64DFR0_EL1_BRPS __BITS(12,15)

sys/arch/aarch64/include/armreg.h

253

#define ID_AA64DFR0_EL1_PMUVER __BITS(8,11)

sys/arch/aarch64/include/armreg.h

263

#define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)

sys/arch/aarch64/include/armreg.h

266

#define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3)

sys/arch/aarch64/include/armreg.h

273

#define ID_AA64ISAR0_EL1_RNDR __BITS(63,60)

sys/arch/aarch64/include/armreg.h

276

#define ID_AA64ISAR0_EL1_TLB __BITS(59,56)

sys/arch/aarch64/include/armreg.h

280

#define ID_AA64ISAR0_EL1_TS __BITS(55,52)

sys/arch/aarch64/include/armreg.h

284

#define ID_AA64ISAR0_EL1_FHM __BITS(51,48)

sys/arch/aarch64/include/armreg.h

287

#define ID_AA64ISAR0_EL1_DP __BITS(47,44)

sys/arch/aarch64/include/armreg.h

290

#define ID_AA64ISAR0_EL1_SM4 __BITS(43,40)

sys/arch/aarch64/include/armreg.h

293

#define ID_AA64ISAR0_EL1_SM3 __BITS(39,36)

sys/arch/aarch64/include/armreg.h

296

#define ID_AA64ISAR0_EL1_SHA3 __BITS(35,32)

sys/arch/aarch64/include/armreg.h

299

#define ID_AA64ISAR0_EL1_RDM __BITS(31,28)

sys/arch/aarch64/include/armreg.h

302

#define ID_AA64ISAR0_EL1_ATOMIC __BITS(23,20)

sys/arch/aarch64/include/armreg.h

305

#define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16)

sys/arch/aarch64/include/armreg.h

308

#define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12)

sys/arch/aarch64/include/armreg.h

312

#define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8)

sys/arch/aarch64/include/armreg.h

315

#define ID_AA64ISAR0_EL1_AES __BITS(7,4)

sys/arch/aarch64/include/armreg.h

322

#define ID_AA64ISAR1_EL1_I8MM __BITS(55,52)

sys/arch/aarch64/include/armreg.h

325

#define ID_AA64ISAR1_EL1_DGH __BITS(51,48)

sys/arch/aarch64/include/armreg.h

328

#define ID_AA64ISAR1_EL1_BF16 __BITS(47,44)

sys/arch/aarch64/include/armreg.h

331

#define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)

sys/arch/aarch64/include/armreg.h

334

#define ID_AA64ISAR1_EL1_SB __BITS(39,36)

sys/arch/aarch64/include/armreg.h

337

#define ID_AA64ISAR1_EL1_FRINTTS __BITS(35,32)

sys/arch/aarch64/include/armreg.h

340

#define ID_AA64ISAR1_EL1_GPI __BITS(31,28)

sys/arch/aarch64/include/armreg.h

343

#define ID_AA64ISAR1_EL1_GPA __BITS(27,24)

sys/arch/aarch64/include/armreg.h

346

#define ID_AA64ISAR1_EL1_LRCPC __BITS(23,20)

sys/arch/aarch64/include/armreg.h

350

#define ID_AA64ISAR1_EL1_FCMA __BITS(19,16)

sys/arch/aarch64/include/armreg.h

353

#define ID_AA64ISAR1_EL1_JSCVT __BITS(15,12)

sys/arch/aarch64/include/armreg.h

356

#define ID_AA64ISAR1_EL1_API __BITS(11,8)

sys/arch/aarch64/include/armreg.h

360

#define ID_AA64ISAR1_EL1_APA __BITS(7,4)

sys/arch/aarch64/include/armreg.h

364

#define ID_AA64ISAR1_EL1_DPB __BITS(3,0)

sys/arch/aarch64/include/armreg.h

371

#define ID_AA64MMFR0_EL1_EXS __BITS(43,40)

sys/arch/aarch64/include/armreg.h

372

#define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28)

sys/arch/aarch64/include/armreg.h

375

#define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27)

sys/arch/aarch64/include/armreg.h

378

#define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23)

sys/arch/aarch64/include/armreg.h

381

#define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19)

sys/arch/aarch64/include/armreg.h

384

#define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15)

sys/arch/aarch64/include/armreg.h

387

#define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11)

sys/arch/aarch64/include/armreg.h

390

#define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7)

sys/arch/aarch64/include/armreg.h

393

#define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3)

sys/arch/aarch64/include/armreg.h

404

#define ID_AA64MMFR1_EL1_XNX __BITS(31,28)

sys/arch/aarch64/include/armreg.h

407

#define ID_AA64MMFR1_EL1_SPECSEI __BITS(27,24)

sys/arch/aarch64/include/armreg.h

410

#define ID_AA64MMFR1_EL1_PAN __BITS(23,20)

sys/arch/aarch64/include/armreg.h

414

#define ID_AA64MMFR1_EL1_LO __BITS(19,16)

sys/arch/aarch64/include/armreg.h

417

#define ID_AA64MMFR1_EL1_HPDS __BITS(15,12)

sys/arch/aarch64/include/armreg.h

421

#define ID_AA64MMFR1_EL1_VH __BITS(11,8)

sys/arch/aarch64/include/armreg.h

424

#define ID_AA64MMFR1_EL1_VMIDBITS __BITS(7,4)

sys/arch/aarch64/include/armreg.h

427

#define ID_AA64MMFR1_EL1_HAFDBS __BITS(3,0)

sys/arch/aarch64/include/armreg.h

435

#define ID_AA64MMFR2_EL1_E0PD __BITS(63,60)

sys/arch/aarch64/include/armreg.h

438

#define ID_AA64MMFR2_EL1_EVT __BITS(59,56)

sys/arch/aarch64/include/armreg.h

442

#define ID_AA64MMFR2_EL1_BBM __BITS(55,52)

sys/arch/aarch64/include/armreg.h

446

#define ID_AA64MMFR2_EL1_TTL __BITS(51,48)

sys/arch/aarch64/include/armreg.h

449

#define ID_AA64MMFR2_EL1_FWB __BITS(43,40)

sys/arch/aarch64/include/armreg.h

452

#define ID_AA64MMFR2_EL1_IDS __BITS(39,36)

sys/arch/aarch64/include/armreg.h

455

#define ID_AA64MMFR2_EL1_AT __BITS(35,32)

sys/arch/aarch64/include/armreg.h

458

#define ID_AA64MMFR2_EL1_ST __BITS(31,28)

sys/arch/aarch64/include/armreg.h

461

#define ID_AA64MMFR2_EL1_NV __BITS(27,24)

sys/arch/aarch64/include/armreg.h

465

#define ID_AA64MMFR2_EL1_CCIDX __BITS(23,20)

sys/arch/aarch64/include/armreg.h

468

#define ID_AA64MMFR2_EL1_VARANGE __BITS(19,16)

sys/arch/aarch64/include/armreg.h

471

#define ID_AA64MMFR2_EL1_IESB __BITS(15,12)

sys/arch/aarch64/include/armreg.h

474

#define ID_AA64MMFR2_EL1_LSM __BITS(11,8)

sys/arch/aarch64/include/armreg.h

477

#define ID_AA64MMFR2_EL1_UAO __BITS(7,4)

sys/arch/aarch64/include/armreg.h

480

#define ID_AA64MMFR2_EL1_CNP __BITS(3,0)

sys/arch/aarch64/include/armreg.h

488

#define ID_AA64PFR1_EL1_RASFRAC __BITS(15,12)

sys/arch/aarch64/include/armreg.h

491

#define ID_AA64PFR1_EL1_MTE __BITS(11,8)

sys/arch/aarch64/include/armreg.h

495

#define ID_AA64PFR1_EL1_SSBS __BITS(7,4)

sys/arch/aarch64/include/armreg.h

499

#define ID_AA64PFR1_EL1_BT __BITS(3,0)

sys/arch/aarch64/include/armreg.h

509

#define MIDR_EL1_IMPL __BITS(31,24) // Implementor

sys/arch/aarch64/include/armreg.h

510

#define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant

sys/arch/aarch64/include/armreg.h

511

#define MIDR_EL1_ARCH __BITS(19,16) // Architecture

sys/arch/aarch64/include/armreg.h

512

#define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum

sys/arch/aarch64/include/armreg.h

513

#define MIDR_EL1_REVISION __BITS(3,0) // Revision

sys/arch/aarch64/include/armreg.h

515

#define MPIDR_AFF3 __BITS(32,39)

sys/arch/aarch64/include/armreg.h

519

#define MPIDR_AFF2 __BITS(16,23)

sys/arch/aarch64/include/armreg.h

520

#define MPIDR_AFF1 __BITS(8,15)

sys/arch/aarch64/include/armreg.h

521

#define MPIDR_AFF0 __BITS(0,7)

sys/arch/aarch64/include/armreg.h

525

#define MVFR0_FPROUND __BITS(31,28)

sys/arch/aarch64/include/armreg.h

528

#define MVFR0_FPSHVEC __BITS(27,24)

sys/arch/aarch64/include/armreg.h

531

#define MVFR0_FPSQRT __BITS(23,20)

sys/arch/aarch64/include/armreg.h

534

#define MVFR0_FPDIVIDE __BITS(19,16)

sys/arch/aarch64/include/armreg.h

537

#define MVFR0_FPTRAP __BITS(15,12)

sys/arch/aarch64/include/armreg.h

540

#define MVFR0_FPDP __BITS(11,8)

sys/arch/aarch64/include/armreg.h

544

#define MVFR0_FPSP __BITS(7,4)

sys/arch/aarch64/include/armreg.h

548

#define MVFR0_SIMDREG __BITS(3,0)

sys/arch/aarch64/include/armreg.h

555

#define MVFR1_SIMDFMAC __BITS(31,28)

sys/arch/aarch64/include/armreg.h

558

#define MVFR1_FPHP __BITS(27,24)

sys/arch/aarch64/include/armreg.h

563

#define MVFR1_SIMDHP __BITS(23,20)

sys/arch/aarch64/include/armreg.h

567

#define MVFR1_SIMDSP __BITS(19,16)

sys/arch/aarch64/include/armreg.h

570

#define MVFR1_SIMDINT __BITS(15,12)

sys/arch/aarch64/include/armreg.h

573

#define MVFR1_SIMDLS __BITS(11,8)

sys/arch/aarch64/include/armreg.h

576

#define MVFR1_FPDNAN __BITS(7,4)

sys/arch/aarch64/include/armreg.h

579

#define MVFR1_FPFTZ __BITS(3,0)

sys/arch/aarch64/include/armreg.h

585

#define MVFR2_FPMISC __BITS(7,4)

sys/arch/aarch64/include/armreg.h

591

#define MVFR2_SIMDMISC __BITS(3,0)

sys/arch/aarch64/include/armreg.h

634

#define CPACR_FPEN __BITS(21,20)

sys/arch/aarch64/include/armreg.h

643

#define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache

sys/arch/aarch64/include/armreg.h

663

#define ESR_EC __BITS(31,26) // Exception Cause

sys/arch/aarch64/include/armreg.h

721

#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome

sys/arch/aarch64/include/armreg.h

723

#define ESR_ISS_COND __BITS(23,20) // common

sys/arch/aarch64/include/armreg.h

725

#define ESR_ISS_SYSREG_OP0 __BITS(21,20) // for ESR_EC_SYS_REG

sys/arch/aarch64/include/armreg.h

726

#define ESR_ISS_SYSREG_OP2 __BITS(19,17) // for ESR_EC_SYS_REG

sys/arch/aarch64/include/armreg.h

727

#define ESR_ISS_SYSREG_OP1 __BITS(16,14) // for ESR_EC_SYS_REG

sys/arch/aarch64/include/armreg.h

728

#define ESR_ISS_SYSREG_CRN __BITS(13,10) // for ESR_EC_SYS_REG

sys/arch/aarch64/include/armreg.h

729

#define ESR_ISS_SYSREG_RT __BITS(9,5) // for ESR_EC_SYS_REG

sys/arch/aarch64/include/armreg.h

730

#define ESR_ISS_SYSREG_CRM __BITS(4,1) // for ESR_EC_SYS_REG

sys/arch/aarch64/include/armreg.h

732

#define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT

sys/arch/aarch64/include/armreg.h

733

#define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT

sys/arch/aarch64/include/armreg.h

734

#define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT

sys/arch/aarch64/include/armreg.h

735

#define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT

sys/arch/aarch64/include/armreg.h

736

#define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT

sys/arch/aarch64/include/armreg.h

738

#define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT

sys/arch/aarch64/include/armreg.h

739

#define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT

sys/arch/aarch64/include/armreg.h

740

#define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT

sys/arch/aarch64/include/armreg.h

741

#define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT

sys/arch/aarch64/include/armreg.h

743

#define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC}

sys/arch/aarch64/include/armreg.h

747

#define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01]

sys/arch/aarch64/include/armreg.h

749

#define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01]

sys/arch/aarch64/include/armreg.h

751

#define ESR_ISS_DATAABORT_SRT __BITS(20,16) // for ESC_RC_DATA_ABT_EL[01]

sys/arch/aarch64/include/armreg.h

758

#define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01]

sys/arch/aarch64/include/armreg.h

802

#define HCR_EL2_TWEDEL __BITS(63,60) // TWE Delay (FEAT_TWED)

sys/arch/aarch64/include/armreg.h

851

#define HCR_EL2_BSU __BITS(11,10) // barrier shareability upgrade

sys/arch/aarch64/include/armreg.h

867

#define HPFAR_EL2_FIPA_D128 __BITS(47,4) // Faulting Intermediate Physical Address Bits [55:12]

sys/arch/aarch64/include/armreg.h

868

#define HPFAR_EL2_FIPA __BITS(43,4) // Faulting Intermediate Physical Address Bits [51:12]

sys/arch/aarch64/include/armreg.h

902

#define MDCR_EL2_E2TB __BITS(25, 24) // EL2 Trace Buffer. (FEAT_TRBE)

sys/arch/aarch64/include/armreg.h

910

#define MDCR_EL2_E2PM __BITS(13, 12) // EL2 Profiling Buffer. (FEAT_SPE)

sys/arch/aarch64/include/armreg.h

923

#define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores

sys/arch/aarch64/include/armreg.h

938

#define MAIR_ATTR0 __BITS(7,0)

sys/arch/aarch64/include/armreg.h

939

#define MAIR_ATTR1 __BITS(15,8)

sys/arch/aarch64/include/armreg.h

940

#define MAIR_ATTR2 __BITS(23,16)

sys/arch/aarch64/include/armreg.h

941

#define MAIR_ATTR3 __BITS(31,24)

sys/arch/aarch64/include/armreg.h

942

#define MAIR_ATTR4 __BITS(39,32)

sys/arch/aarch64/include/armreg.h

943

#define MAIR_ATTR5 __BITS(47,40)

sys/arch/aarch64/include/armreg.h

944

#define MAIR_ATTR6 __BITS(55,48)

sys/arch/aarch64/include/armreg.h

945

#define MAIR_ATTR7 __BITS(63,56)

sys/arch/aarch64/include/armreg.h

955

#define PAR_ATTR __BITS(63,56) // F=0 memory attributes

sys/arch/aarch64/include/armreg.h

956

#define PAR_PA __BITS(51,12) // F=0 physical address

sys/arch/aarch64/include/armreg.h

958

#define PAR_PA_LOWMASK __BITS(11,0)

sys/arch/aarch64/include/armreg.h

960

#define PAR_SH __BITS(8,7) // F=0 shareability attribute

sys/arch/aarch64/include/armreg.h

967

#define PAR_FST __BITS(6,1) // F=1 fault status code

sys/arch/aarch64/include/cpufunc.h

145

#define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */

sys/arch/aarch64/include/cpufunc.h

146

#define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */

sys/arch/aarch64/include/pmap.h

184

#define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT)

sys/arch/aarch64/include/pte.h

112

#define L1_BLK_OA __BITS(47, 30) /* 1GB */

sys/arch/aarch64/include/pte.h

113

#define L2_BLK_OA __BITS(47, 21) /* 2MB */

sys/arch/aarch64/include/pte.h

114

#define L3_PAG_OA __BITS(47, 12) /* 4KB */

sys/arch/aarch64/include/pte.h

120

#define L0_ADDR_BITS __BITS(47,39)

sys/arch/aarch64/include/pte.h

129

#define L1_ADDR_BITS __BITS(38,30)

sys/arch/aarch64/include/pte.h

138

#define L2_ADDR_BITS __BITS(29,21)

sys/arch/aarch64/include/pte.h

144

#define L2_BLOCK_MASK __BITS(47,21)

sys/arch/aarch64/include/pte.h

148

#define L3_ADDR_BITS __BITS(20,12)

sys/arch/aarch64/include/pte.h

52

#define LX_TBL_APTABLE __BITS(62,61) /* inherited next level */

sys/arch/aarch64/include/pte.h

59

#define LX_BLKPAG_OS __BITS(58, 55)

sys/arch/aarch64/include/pte.h

67

#define LX_S2_BLKPAG_XN __BITS(54,53) /* Execute Never (stage2) */

sys/arch/aarch64/include/pte.h

72

#define LX_TBL_PA __BITS(47, 12)

sys/arch/aarch64/include/pte.h

73

#define LX_BLKPAG_OA __BITS(47, 12)

sys/arch/aarch64/include/pte.h

77

#define LX_BLKPAG_SH __BITS(9,8) /* Shareability */

sys/arch/aarch64/include/pte.h

86

#define LX_S2_BLKPAG_S2AP __BITS(7,6)

sys/arch/aarch64/include/pte.h

92

#define LX_BLKPAG_ATTR_INDX __BITS(4,2) /* refer MAIR_EL1 attr<n> */

sys/arch/aarch64/include/pte.h

97

#define LX_S2_BLKPAG_MEMATTR __BITS(5,2)

sys/arch/alpha/alpha/qemu.c

195

tc->tc_counter_mask = __BITS(0,31);

sys/arch/alpha/include/fpu.h

118

#define FP_C_ALLBITS __BITS(1,22)

sys/arch/alpha/include/fpu.h

55

#define FPCR_DYN_RM __BITS(58,59) /* Dynamic Rounding Mode */

sys/arch/alpha/include/proc.h

64

#define MDLWP_FP_C __BITS(1,22) /* Extended FP_C Quadword bits */

sys/arch/alpha/pci/lcareg.h

71

#define MEMC_CAR_BCS __BITS(5,7) /* Bcache size */

sys/arch/alpha/pci/lcareg.h

72

#define MEMC_CAR_RCC __BITS(8,10) /* Read Cycle Count */

sys/arch/alpha/pci/lcareg.h

73

#define MEMC_CAR_WCC __BITS(11,13) /* Write Cycle Count */

sys/arch/alpha/pci/lcareg.h

76

#define MEMC_CAR_TAG __BITS(16,30) /* latched Bcache tag value */

sys/arch/alpha/pci/pci_6600.c

151

__BITS(0,63);

sys/arch/alpha/pci/pci_machdep.c

457

#define ALPHA_PCI_INTR_HANDLE_IRQ __BITS(0,31)

sys/arch/alpha/pci/pci_machdep.c

458

#define ALPHA_PCI_INTR_HANDLE_FLAGS __BITS(32,63)

sys/arch/alpha/pci/sioreg.h

91

#define PIRQ_RTCTRL_IRQ __BITS(0,3) /* PIRQ routed to this ISA IRQ */

sys/arch/alpha/pci/tsreg.h

193

#define PCTL_PRIGRP __BITS(8,14) /* arbiter priority group */

sys/arch/alpha/pci/tsreg.h

197

#define PCTL_CDQMAX __BITS(20,23) /* see manual */

sys/arch/alpha/pci/tsreg.h

198

#define PCTL_REV __BITS(24,31) /* Pchip revision */

sys/arch/alpha/pci/tsreg.h

199

#define PCTL_CRQMAX __BITS(32,35) /* see manual */

sys/arch/alpha/pci/tsreg.h

200

#define PCTL_PTPMAX __BITS(36,39) /* see manual */

sys/arch/alpha/pci/tsreg.h

201

#define PCTL_PCLKX __BITS(40,41) /* PCI clock freq multiplier */

sys/arch/alpha/pci/tsreg.h

206

#define PCTL_PID __BITS(46,47) /* Pchip ID */

sys/arch/amd64/include/msan.h

68

#define __MD_ORIG_TYPE __BITS(31,28)

sys/arch/arm/acpi/acpi_machdep.c

536

dma_mask = __BITS(nc->MemoryAddressLimit - 1, 0);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

60

#define PAB_CTRL_PAGE_SEL __BITS(18,13)

sys/arch/arm/altera/cycv_reg.h

48

#define CYCV_CLKMGR_PLL_VCO_NUMER __BITS(3, 15)

sys/arch/arm/altera/cycv_reg.h

49

#define CYCV_CLKMGR_PLL_VCO_DENOM __BITS(16, 21)

sys/arch/arm/altera/cycv_reg.h

52

#define CYCV_CLKMGR_MAIN_PLL_MPUCLK_CNT __BITS(0, 8)

sys/arch/arm/altera/cycv_reg.h

54

#define CYCV_CLKMGR_MAIN_PLL_MAINCLK_CNT __BITS(0, 8)

sys/arch/arm/altera/cycv_reg.h

61

#define CYCV_CLKMGR_MAIN_PLL_MAINDIV_L4SP __BITS(7, 9)

sys/arch/arm/altera/cycv_reg.h

76

#define CYCV_CLKMGR_PERI_PLL_PERBASECLK_CNT __BITS(0, 8)

sys/arch/arm/amlogic/gxlphy.c

53

#define TSTCNTL_REG_BANK_SEL __BITS(12,11)

sys/arch/arm/amlogic/gxlphy.c

55

#define TSTCNTL_READ_ADDR __BITS(9,5)

sys/arch/arm/amlogic/gxlphy.c

56

#define TSTCNTL_WRITE_ADDR __BITS(4,0)

sys/arch/arm/amlogic/meson6_timer.c

71

#define MESON_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK __BITS(10, 8)

sys/arch/arm/amlogic/meson6_timer.c

77

#define MESON_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK __BITS(7, 6)

sys/arch/arm/amlogic/meson6_timer.c

78

#define MESON_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK __BITS(5, 4)

sys/arch/arm/amlogic/meson6_timer.c

79

#define MESON_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK __BITS(3, 2)

sys/arch/arm/amlogic/meson6_timer.c

80

#define MESON_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK __BITS(1, 0)

sys/arch/arm/amlogic/meson8b_clkc.c

186

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */

sys/arch/arm/amlogic/meson8b_clkc.c

187

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */

sys/arch/arm/amlogic/meson8b_clkc.c

196

__BITS(17,16), /* div */

sys/arch/arm/amlogic/meson8b_clkc.c

209

__BITS(29,20), /* div */

sys/arch/arm/amlogic/meson8b_clkc.c

214

__BITS(3,2), /* sel */

sys/arch/arm/amlogic/meson8b_clkc.c

232

__BITS(8,6), /* sel */

sys/arch/arm/amlogic/meson8b_clkc.c

241

MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */

sys/arch/arm/amlogic/meson8b_clkc.c

242

MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */

sys/arch/arm/amlogic/meson8b_clkc.c

243

MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */

sys/arch/arm/amlogic/meson8b_clkc.c

250

__BITS(17,16), /* div */

sys/arch/arm/amlogic/meson8b_clkc.c

259

MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */

sys/arch/arm/amlogic/meson8b_clkc.c

261

MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */

sys/arch/arm/amlogic/meson8b_clkc.c

265

MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */

sys/arch/arm/amlogic/meson8b_clkc.c

267

MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */

sys/arch/arm/amlogic/meson8b_clkc.c

271

MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(13,0)), /* sdm */

sys/arch/arm/amlogic/meson8b_clkc.c

273

MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(24,16)), /* n2 */

sys/arch/arm/amlogic/meson8b_clkc.c

295

__BITS(14,12), /* sel */

sys/arch/arm/amlogic/meson8b_clkc.c

300

__BITS(6,0), /* div */

sys/arch/arm/amlogic/meson8b_clkc.c

58

#define HHI_SYS_CPU_CLK_CNTL0_SOUTSEL __BITS(3,2)

sys/arch/arm/amlogic/meson8b_clkc.c

59

#define HHI_SYS_CPU_CLK_CNTL0_PLLSEL __BITS(1,0)

sys/arch/arm/amlogic/meson8b_clkc.c

69

#define HHI_SYS_PLL_CNTL_OD __BITS(17,16)

sys/arch/arm/amlogic/meson8b_clkc.c

70

#define HHI_SYS_PLL_CNTL_DIV __BITS(14,9)

sys/arch/arm/amlogic/meson8b_clkc.c

71

#define HHI_SYS_PLL_CNTL_MUL __BITS(8,0)

sys/arch/arm/amlogic/meson_canvasreg.h

38

#define DC_CAV_LUT_DATAL_FBADDR __BITS(28,0)

sys/arch/arm/amlogic/meson_canvasreg.h

39

#define DC_CAV_LUT_DATAL_WIDTH_L __BITS(31,29)

sys/arch/arm/amlogic/meson_canvasreg.h

41

#define DC_CAV_LUT_DATAH_BLKMODE __BITS(25,24)

sys/arch/arm/amlogic/meson_canvasreg.h

47

#define DC_CAV_LUT_DATAH_HEIGHT __BITS(21,9)

sys/arch/arm/amlogic/meson_canvasreg.h

48

#define DC_CAV_LUT_DATAH_WIDTH_H __BITS(8,0)

sys/arch/arm/amlogic/meson_canvasreg.h

52

#define DC_CAV_LUT_ADDR_INDEX __BITS(2,0)

sys/arch/arm/amlogic/meson_dwmac.c

57

#define MP2_CLK_OUT_DIV __BITS(9,7)

sys/arch/arm/amlogic/meson_dwmac.c

58

#define TX_CLK_DELAY __BITS(6,5)

sys/arch/arm/amlogic/meson_i2c.c

389

mesoni2c_set_mask(sc, MESONI2C_CTRL_REG, MESONI2C_CTRL_CLKDIV_MASK, (div & __BITS(9, 0)) << MESONI2C_CTRL_CLKDIV_SHIFT);

sys/arch/arm/amlogic/meson_i2c.c

423

mesoni2c_set_mask(sc, MESONI2C_CTRL_REG, MESONI2C_CTRL_CLKDIV_MASK, (divh & __BITS(9, 0)) << MESONI2C_CTRL_CLKDIV_SHIFT);

sys/arch/arm/amlogic/meson_i2c.c

52

#define MESONI2C_CTRL_READ_DATA_MASK __BITS(11, MESONI2C_CTRL_READ_DATA_SHIFT)

sys/arch/arm/amlogic/meson_i2c.c

54

#define MESONI2C_CTRL_CLKDIV_MASK __BITS(21, MESONI2C_CTRL_CLKDIV_SHIFT)

sys/arch/arm/amlogic/meson_i2c.c

56

#define MESONI2C_CTRL_CLKDIVEXT_MASK __BITS(29, MESONI2C_CTRL_CLKDIVEXT_SHIFT)

sys/arch/arm/amlogic/meson_i2c.c

59

#define MESONI2C_SLAVE_ADDR_MASK __BITS(7, 0)

sys/arch/arm/amlogic/meson_i2c.c

60

#define MESONI2C_SLAVE_SDA_FILTER_MASK __BITS(10, 8)

sys/arch/arm/amlogic/meson_i2c.c

61

#define MESONI2C_SLAVE_SCL_FILTER_MASK __BITS(13, 11)

sys/arch/arm/amlogic/meson_i2c.c

63

#define MESONI2C_SLAVE_SCL_LOW_MASK __BITS(27, MESONI2C_SLAVE_SCL_LOW_SHIFT)

sys/arch/arm/amlogic/meson_platform.c

402

ctrl |= __BITS(cpuno,0);

sys/arch/arm/amlogic/meson_platform.c

77

#define MESON8B_WATCHDOG_TC_CPUS __BITS(27,24)

sys/arch/arm/amlogic/meson_platform.c

79

#define MESON8B_WATCHDOG_TC_TCNT __BITS(15,0)

sys/arch/arm/amlogic/meson_platform.c

81

#define MESON8B_WATCHDOG_RESET_COUNT __BITS(15,0)

sys/arch/arm/amlogic/meson_platform.c

91

#define MESONGX_WATCHDOG_TCNT_COUNT __BITS(15,0)

sys/arch/arm/amlogic/meson_pwm.c

44

#define MESON_PWM_DUTYCYCLE_HIGH __BITS(31,16)

sys/arch/arm/amlogic/meson_pwm.c

45

#define MESON_PWM_DUTYCYCLE_LOW __BITS(15,0)

sys/arch/arm/amlogic/meson_pwm.c

48

#define MESON_PWM_MISC_AB_B_CLK_DIV __BITS(22,16)

sys/arch/arm/amlogic/meson_pwm.c

50

#define MESON_PWM_MISC_AB_A_CLK_DIV __BITS(14,8)

sys/arch/arm/amlogic/meson_pwm.c

51

#define MESON_PWM_MISC_AB_B_CLK_SEL __BITS(7,6)

sys/arch/arm/amlogic/meson_pwm.c

52

#define MESON_PWM_MISC_AB_A_CLK_SEL __BITS(5,4)

sys/arch/arm/amlogic/meson_rtcreg.h

38

#define AO_RTC_REG0_STATIC_REG_LSB __BITS(31,24)

sys/arch/arm/amlogic/meson_rtcreg.h

43

#define AO_RTC_REG0_UNUSED_19_18 __BITS(19,18)

sys/arch/arm/amlogic/meson_rtcreg.h

47

#define AO_RTC_REG0_UNUSED_10_8 __BITS(10,8)

sys/arch/arm/amlogic/meson_rtcreg.h

56

#define AO_RTC_REG1_UNUSED_31_16 __BITS(31,16)

sys/arch/arm/amlogic/meson_rtcreg.h

57

#define AO_RTC_REG1_RESERVED __BITS(15,12)

sys/arch/arm/amlogic/meson_rtcreg.h

58

#define AO_RTC_REG1_UNUSED_11_4 __BITS(11,4)

sys/arch/arm/amlogic/meson_rtcreg.h

64

#define AO_RTC_REG2_OSC_CLK_COUNT __BITS(31,0)

sys/arch/arm/amlogic/meson_rtcreg.h

66

#define AO_RTC_REG3_UNUSED_31_30 __BITS(31,30)

sys/arch/arm/amlogic/meson_rtcreg.h

69

#define AO_RTC_REG3_AUTO_TB_SEL __BITS(27,26)

sys/arch/arm/amlogic/meson_rtcreg.h

70

#define AO_RTC_REG3_FILTER_SEL __BITS(25,23)

sys/arch/arm/amlogic/meson_rtcreg.h

71

#define AO_RTC_REG3_FILTER_TB __BITS(22,21)

sys/arch/arm/amlogic/meson_rtcreg.h

79

#define AO_RTC_REG4_UNUSED __BITS(31,8)

sys/arch/arm/amlogic/meson_rtcreg.h

80

#define AO_RTC_REG4_STATIC_REG_MSB __BITS(7,0)

sys/arch/arm/amlogic/meson_rtcreg.h

92

#define RTC_COUNTER_VALUE __BITS(31,0)

sys/arch/arm/amlogic/meson_rtcreg.h

98

#define RTC_SEC_ADJUST_CTRL __BITS(20,19)

sys/arch/arm/amlogic/meson_rtcreg.h

99

#define RTC_SEC_ADJUST_COUNTER __BITS(18,0)

sys/arch/arm/amlogic/meson_sdhcreg.h

101

#define SD_MISC_TXSTART_THRESHOLD __BITS(31,29)

sys/arch/arm/amlogic/meson_sdhcreg.h

103

#define SD_MISC_THREAD_ID __BITS(27,22)

sys/arch/arm/amlogic/meson_sdhcreg.h

104

#define SD_MISC_BURST_NUMBER __BITS(21,16)

sys/arch/arm/amlogic/meson_sdhcreg.h

105

#define SD_MISC_WCRC_OK_PATTERN __BITS(9,7)

sys/arch/arm/amlogic/meson_sdhcreg.h

106

#define SD_MISC_WCRC_ERR_PATTERN __BITS(6,4)

sys/arch/arm/amlogic/meson_sdhcreg.h

108

#define SD_ICTL_SDIO_DAT1 __BITS(17,16)

sys/arch/arm/amlogic/meson_sdhcreg.h

138

#define SD_ENHC_RX_TIMEOUT __BITS(7,0)

sys/arch/arm/amlogic/meson_sdhcreg.h

139

#define SD_ENHC_SDIO_IRQ_PERIOD __BITS(15,8)

sys/arch/arm/amlogic/meson_sdhcreg.h

142

#define SD_ENHC_RXFIFO_THRESHOLD __BITS(24,18)

sys/arch/arm/amlogic/meson_sdhcreg.h

143

#define SD_ENHC_TXFIFO_THRESHOLD __BITS(31,25)

sys/arch/arm/amlogic/meson_sdhcreg.h

145

#define SD_ESTA_BUSY __BITS(13,11) /* XXX ??? */

sys/arch/arm/amlogic/meson_sdhcreg.h

147

#define SD_CLK2_RX_CLK_PHASE __BITS(11,0)

sys/arch/arm/amlogic/meson_sdhcreg.h

148

#define SD_CLK2_SD_CLK_PHASE __BITS(23,12)

sys/arch/arm/amlogic/meson_sdhcreg.h

48

#define SD_SEND_TOTAL_PACK __BITS(31,16)

sys/arch/arm/amlogic/meson_sdhcreg.h

56

#define SD_SEND_COMMAND_INDEX __BITS(5,0)

sys/arch/arm/amlogic/meson_sdhcreg.h

58

#define SD_CNTL_TX_ENDIAN_CTRL __BITS(31,29)

sys/arch/arm/amlogic/meson_sdhcreg.h

61

#define SD_CNTL_RX_ENDIAN_CTRL __BITS(26,24)

sys/arch/arm/amlogic/meson_sdhcreg.h

62

#define SD_CNTL_RX_PERIOD __BITS(23,20)

sys/arch/arm/amlogic/meson_sdhcreg.h

63

#define SD_CNTL_RX_TIMEOUT __BITS(19,13)

sys/arch/arm/amlogic/meson_sdhcreg.h

64

#define SD_CNTL_PACK_LEN __BITS(12,4)

sys/arch/arm/amlogic/meson_sdhcreg.h

67

#define SD_CNTL_DAT_TYPE __BITS(1,0)

sys/arch/arm/amlogic/meson_sdhcreg.h

69

#define SD_STAT_DAT_HI __BITS(23,20)

sys/arch/arm/amlogic/meson_sdhcreg.h

70

#define SD_STAT_TXFIFO_COUNT __BITS(19,13)

sys/arch/arm/amlogic/meson_sdhcreg.h

71

#define SD_STAT_RXFIFO_COUNT __BITS(12,6)

sys/arch/arm/amlogic/meson_sdhcreg.h

73

#define SD_STAT_DAT_LO __BITS(4,1)

sys/arch/arm/amlogic/meson_sdhcreg.h

76

#define SD_CLKC_MEM_PWR __BITS(26,25)

sys/arch/arm/amlogic/meson_sdhcreg.h

80

#define SD_CLKC_CLK_IN_SEL __BITS(17,16)

sys/arch/arm/amlogic/meson_sdhcreg.h

89

#define SD_CLKC_CLK_DIV __BITS(11,0)

sys/arch/arm/amlogic/meson_sdhcreg.h

92

#define SD_PDMA_RXFIFO_MANUAL_FLUSH __BITS(30,29)

sys/arch/arm/amlogic/meson_sdhcreg.h

93

#define SD_PDMA_TXFIFO_THRESHOLD __BITS(28,22)

sys/arch/arm/amlogic/meson_sdhcreg.h

94

#define SD_PDMA_RXFIFO_THRESHOLD __BITS(21,15)

sys/arch/arm/amlogic/meson_sdhcreg.h

95

#define SD_PDMA_RX_BURST_LEN __BITS(14,10)

sys/arch/arm/amlogic/meson_sdhcreg.h

96

#define SD_PDMA_TX_BURST_LEN __BITS(9,5)

sys/arch/arm/amlogic/meson_sdhcreg.h

98

#define SD_PDMA_PIO_RDRESP __BITS(3,1)

sys/arch/arm/amlogic/meson_sdioreg.h

103

#define SDIO_MULT_DATA_CATCH_LEVEL __BITS(7,6)

sys/arch/arm/amlogic/meson_sdioreg.h

108

#define SDIO_MULT_RESPONSE_READ_INDEX __BITS(15,12)

sys/arch/arm/amlogic/meson_sdioreg.h

109

#define SDIO_MULT_DATA_CATCH_FINISH_PT __BITS(27,16)

sys/arch/arm/amlogic/meson_sdioreg.h

111

#define SDIO_EXT_CMD_ARG_EXT __BITS(15,0)

sys/arch/arm/amlogic/meson_sdioreg.h

112

#define SDIO_EXT_DATA_RW_NUMBER __BITS(29,16)

sys/arch/arm/amlogic/meson_sdioreg.h

43

#define SDIO_SEND_COMMAND_INDEX __BITS(7,0)

sys/arch/arm/amlogic/meson_sdioreg.h

44

#define SDIO_SEND_RESPONSE_BITS __BITS(15,8)

sys/arch/arm/amlogic/meson_sdioreg.h

51

#define SDIO_SEND_REPEAT_PACKAGE __BITS(31,24)

sys/arch/arm/amlogic/meson_sdioreg.h

53

#define SDIO_CONF_COMMAND_CLK_DIV __BITS(9,0)

sys/arch/arm/amlogic/meson_sdioreg.h

56

#define SDIO_CONF_COMMAND_ARG_BITS __BITS(17,12)

sys/arch/arm/amlogic/meson_sdioreg.h

60

#define SDIO_CONF_M_ENDIAN __BITS(22,21)

sys/arch/arm/amlogic/meson_sdioreg.h

61

#define SDIO_CONF_WRITE_NWR __BITS(28,23)

sys/arch/arm/amlogic/meson_sdioreg.h

62

#define SDIO_CONF_WRITE_CRC_OK_STATUS __BITS(31,29)

sys/arch/arm/amlogic/meson_sdioreg.h

64

#define SDIO_IRQS_STATUS __BITS(3,0)

sys/arch/arm/amlogic/meson_sdioreg.h

77

#define SDIO_IRQS_TIMING_OUT_COUNT __BITS(31,19)

sys/arch/arm/amlogic/meson_sdioreg.h

88

#define SDIO_IRQC_IF_INT_CONFIG __BITS(7,6)

sys/arch/arm/amlogic/meson_sdioreg.h

89

#define SDIO_IRQC_FORCE_DATA __BITS(13,8)

sys/arch/arm/amlogic/meson_sdioreg.h

92

#define SDIO_IRQC_FORCE_OUTEN __BITS(21,16)

sys/arch/arm/amlogic/meson_sdioreg.h

93

#define SDIO_IRQC_DISABLE_MEM_HALT __BITS(23,22)

sys/arch/arm/amlogic/meson_sdioreg.h

94

#define SDIO_IRQC_FORCE_DATA_READ __BITS(29,24)

sys/arch/arm/amlogic/meson_sdioreg.h

98

#define SDIO_MULT_PORT_SEL __BITS(1,0)

sys/arch/arm/amlogic/meson_thermal.c

125

#define TS_AO_CALIB_VERSION_MASK __BITS(31,24)

sys/arch/arm/amlogic/meson_thermal.c

127

#define TS_AO_CALIB_TEMP_MASK __BITS(14,0)

sys/arch/arm/amlogic/meson_thermal.c

45

#define TS_CFG_REG1_ANA_CH_SEL __BITS(2,0)

sys/arch/arm/amlogic/meson_thermal.c

53

#define TS_STAT0_FILTER_OUT __BITS(15,0)

sys/arch/arm/amlogic/meson_uart.h

54

#define UART_MISC_TX_IRQ_CNT __BITS(15,8)

sys/arch/arm/amlogic/meson_uart.h

55

#define UART_MISC_RX_IRQ_CNT __BITS(7,0)

sys/arch/arm/amlogic/meson_usbctrl.c

63

#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK __BITS(30,29)

sys/arch/arm/amlogic/meson_usbctrl.c

64

#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK __BITS(28,19)

sys/arch/arm/amlogic/meson_usbctrl.c

68

#define USB_R1_P30_PCS_TX_SWING_FULL_MASK __BITS(31,25)

sys/arch/arm/amlogic/meson_usbctrl.c

69

#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK __BITS(24,19)

sys/arch/arm/amlogic/meson_usbctrl.c

73

#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK __BITS(13,12)

sys/arch/arm/amlogic/meson_usbctrl.c

74

#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK __BITS(9,7)

sys/arch/arm/amlogic/meson_usbctrl.c

75

#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK __BITS(4,2)

sys/arch/arm/amlogic/meson_usbctrl.c

79

#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK __BITS(31,26)

sys/arch/arm/amlogic/meson_usbctrl.c

80

#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK __BITS(25,20)

sys/arch/arm/amlogic/meson_usbctrl.c

83

#define USB_R3_P30_SSC_REF_CLK_SEL_MASK __BITS(12,4)

sys/arch/arm/amlogic/meson_usbctrl.c

84

#define USB_R3_P30_SSC_RANGE_MASK __BITS(3,1)

sys/arch/arm/amlogic/meson_usbctrl.c

88

#define USB_R4_MEM_PD_MASK __BITS(3,2)

sys/arch/arm/amlogic/meson_usbctrl.c

92

#define USB_R5_ID_DIG_CNT_MASK __BITS(23,16)

sys/arch/arm/amlogic/meson_usbctrl.c

93

#define USB_R5_ID_DIG_TH_MASK __BITS(15,8)

sys/arch/arm/amlogic/meson_usbctrl.c

98

#define USB_R5_ID_DIG_CFG_MASK __BITS(3,2)

sys/arch/arm/amlogic/meson_usbphy.c

46

#define PREI_USB_PHY_CTRL_FSEL __BITS(24,22)

sys/arch/arm/amlogic/meson_vpureg.h

100

#define VIU_OSD_BLK_CFG_W3_H_START __BITS(11,0)

sys/arch/arm/amlogic/meson_vpureg.h

102

#define VIU_OSD_BLK_CFG_W4_V_END __BITS(27,16)

sys/arch/arm/amlogic/meson_vpureg.h

103

#define VIU_OSD_BLK_CFG_W4_V_START __BITS(11,0)

sys/arch/arm/amlogic/meson_vpureg.h

112

#define VPP_OSD_VSC_PHASE_STEP_FORMAT __BITS(27,0)

sys/arch/arm/amlogic/meson_vpureg.h

114

#define VPP_OSD_VSC_INI_PHASE_0 __BITS(31,16)

sys/arch/arm/amlogic/meson_vpureg.h

115

#define VPP_OSD_VSC_INI_PHASE_1 __BITS(15,0)

sys/arch/arm/amlogic/meson_vpureg.h

119

#define VPP_OSD_VSC_CTRL0_BOT_RPT_P0_NUM0 __BITS(17,16)

sys/arch/arm/amlogic/meson_vpureg.h

120

#define VPP_OSD_VSC_CTRL0_BOT_INI_RCV_NUM0 __BITS(14,11)

sys/arch/arm/amlogic/meson_vpureg.h

121

#define VPP_OSD_VSC_CTRL0_TOP_RPT_P0_NUM0 __BITS(9,8)

sys/arch/arm/amlogic/meson_vpureg.h

122

#define VPP_OSD_VSC_CTRL0_TOP_INI_RCV_NUM0 __BITS(6,3)

sys/arch/arm/amlogic/meson_vpureg.h

123

#define VPP_OSD_VSC_CTRL0_BANK_LENGTH __BITS(2,0)

sys/arch/arm/amlogic/meson_vpureg.h

125

#define VPP_OSD_HSC_PHASE_STEP_FORMAT __BITS(27,0)

sys/arch/arm/amlogic/meson_vpureg.h

127

#define VPP_OSD_HSC_INI_PHASE_0 __BITS(31,16)

sys/arch/arm/amlogic/meson_vpureg.h

128

#define VPP_OSD_HSC_INI_PHASE_1 __BITS(15,0)

sys/arch/arm/amlogic/meson_vpureg.h

131

#define VPP_OSD_HSC_CTRL0_RPT_P0_NUM0 __BITS(9,8)

sys/arch/arm/amlogic/meson_vpureg.h

132

#define VPP_OSD_HSC_CTRL0_INI_RCV_NUM0 __BITS(6,3)

sys/arch/arm/amlogic/meson_vpureg.h

133

#define VPP_OSD_HSC_CTRL0_BANK_LENGTH __BITS(2,0)

sys/arch/arm/amlogic/meson_vpureg.h

138

#define VPP_OSD_SC_CTRL0_DEFAULT_ALPHA __BITS(11,4)

sys/arch/arm/amlogic/meson_vpureg.h

140

#define VPP_OSD_SC_CTRL0_OSD_SC_SEL __BITS(1,0)

sys/arch/arm/amlogic/meson_vpureg.h

142

#define VPP_OSD_SCI_WH_M1_WIDTH __BITS(28,16)

sys/arch/arm/amlogic/meson_vpureg.h

143

#define VPP_OSD_SCI_WH_M1_HEIGHT __BITS(12,0)

sys/arch/arm/amlogic/meson_vpureg.h

145

#define VPP_OSD_SCO_H_START __BITS(28,16)

sys/arch/arm/amlogic/meson_vpureg.h

146

#define VPP_OSD_SCO_H_END __BITS(12,0)

sys/arch/arm/amlogic/meson_vpureg.h

148

#define VPP_OSD_SCO_V_START __BITS(28,16)

sys/arch/arm/amlogic/meson_vpureg.h

149

#define VPP_OSD_SCO_V_END __BITS(12,0)

sys/arch/arm/amlogic/meson_vpureg.h

58

#define VIU_OSD_CTRL_STAT_GLOBAL_ALPHA __BITS(20,12)

sys/arch/arm/amlogic/meson_vpureg.h

64

#define VIU_OSD_TCOLOR_R __BITS(31,24)

sys/arch/arm/amlogic/meson_vpureg.h

65

#define VIU_OSD_TCOLOR_G __BITS(23,16)

sys/arch/arm/amlogic/meson_vpureg.h

66

#define VIU_OSD_TCOLOR_B __BITS(15,8)

sys/arch/arm/amlogic/meson_vpureg.h

67

#define VIU_OSD_TCOLOR_A __BITS(7,0)

sys/arch/arm/amlogic/meson_vpureg.h

69

#define VIU_OSD_BLK_CFG_W0_TBL_ADDR __BITS(23,16)

sys/arch/arm/amlogic/meson_vpureg.h

72

#define VIU_OSD_BLK_CFG_W0_INTERP_CTRL __BITS(13,12)

sys/arch/arm/amlogic/meson_vpureg.h

73

#define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE __BITS(11,8)

sys/arch/arm/amlogic/meson_vpureg.h

83

#define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX __BITS(5,2)

sys/arch/arm/amlogic/meson_vpureg.h

93

#define VIU_OSD_BLK_CFG_W1_X_END __BITS(28,16)

sys/arch/arm/amlogic/meson_vpureg.h

94

#define VIU_OSD_BLK_CFG_W1_X_START __BITS(12,0)

sys/arch/arm/amlogic/meson_vpureg.h

96

#define VIU_OSD_BLK_CFG_W2_Y_END __BITS(28,16)

sys/arch/arm/amlogic/meson_vpureg.h

97

#define VIU_OSD_BLK_CFG_W2_Y_START __BITS(12,0)

sys/arch/arm/amlogic/meson_vpureg.h

99

#define VIU_OSD_BLK_CFG_W3_H_END __BITS(27,16)

sys/arch/arm/amlogic/meson_wdt.c

45

#define WATCHDOG_TC_CPUS __BITS(27,24)

sys/arch/arm/amlogic/meson_wdt.c

47

#define WATCHDOG_TC_TCNT __BITS(15,0)

sys/arch/arm/amlogic/meson_wdt.c

50

#define WATCHDOG_RESET_COUNT __BITS(15,0)

sys/arch/arm/amlogic/mesong12_clkc.c

100

#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGR_ADJ __BITS(24,20)

sys/arch/arm/amlogic/mesong12_clkc.c

102

#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGR_VREF __BITS(16,12)

sys/arch/arm/amlogic/mesong12_clkc.c

103

#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BY_IMP_IN __BITS(11,8)

sys/arch/arm/amlogic/mesong12_clkc.c

1302

m = __SHIFTOUT(val, __BITS(7,0));

sys/arch/arm/amlogic/mesong12_clkc.c

1303

n = __SHIFTOUT(val, __BITS(14,10));

sys/arch/arm/amlogic/mesong12_clkc.c

1304

div_shift = __SHIFTOUT(val, __BITS(18,16));

sys/arch/arm/amlogic/mesong12_clkc.c

1374

val &= ~__BITS(7,0);

sys/arch/arm/amlogic/mesong12_clkc.c

1375

val |= __SHIFTIN(new_m, __BITS(7,0));

sys/arch/arm/amlogic/mesong12_clkc.c

1376

val &= ~__BITS(14,10);

sys/arch/arm/amlogic/mesong12_clkc.c

1377

val |= __SHIFTIN(new_n, __BITS(14,10));

sys/arch/arm/amlogic/mesong12_clkc.c

1378

val &= ~__BITS(18,16);

sys/arch/arm/amlogic/mesong12_clkc.c

1379

val |= __SHIFTIN(new_div, __BITS(18,16));

sys/arch/arm/amlogic/mesong12_clkc.c

188

MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(7,0)), /* m */ \

sys/arch/arm/amlogic/mesong12_clkc.c

189

MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(14,10)),/* n */ \

sys/arch/arm/amlogic/mesong12_clkc.c

190

MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL1, __BITS(16,0)), /* frac */ \

sys/arch/arm/amlogic/mesong12_clkc.c

198

__BITS(17,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

206

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(7,0)), /* m */ \

sys/arch/arm/amlogic/mesong12_clkc.c

207

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(14,10)),/* n */ \

sys/arch/arm/amlogic/mesong12_clkc.c

216

__BITS(18,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

224

MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(7,0)), /* m */ \

sys/arch/arm/amlogic/mesong12_clkc.c

225

MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(14,10)),/* n */ \

sys/arch/arm/amlogic/mesong12_clkc.c

234

__BITS(18,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

305

MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(13,0)), /* sdm */ \

sys/arch/arm/amlogic/mesong12_clkc.c

307

MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(28,20)), /* n2 */ \

sys/arch/arm/amlogic/mesong12_clkc.c

313

MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(13,0)), /* sdm */ \

sys/arch/arm/amlogic/mesong12_clkc.c

315

MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(28,20)), /* n2 */ \

sys/arch/arm/amlogic/mesong12_clkc.c

321

MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(13,0)), /* sdm */ \

sys/arch/arm/amlogic/mesong12_clkc.c

323

MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(28,20)), /* n2 */ \

sys/arch/arm/amlogic/mesong12_clkc.c

359

__BITS(11,9), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

366

__BITS(27,25), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

373

__BITS(11,9), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

379

__BITS(6,0), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

385

__BITS(22,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

391

__BITS(6,0), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

415

__BITS(14,12), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

421

__BITS(6,0), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

60

#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_OD __BITS(20,16)

sys/arch/arm/amlogic/mesong12_clkc.c

61

#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_PREDIV_SEL __BITS(14,10)

sys/arch/arm/amlogic/mesong12_clkc.c

62

#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_FBKDIV __BITS(7,0)

sys/arch/arm/amlogic/mesong12_clkc.c

65

#define HHI_PCIE_PLL_CNTL1_PCIE_APLL_SDM_FRAC __BITS(11,0)

sys/arch/arm/amlogic/mesong12_clkc.c

67

#define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_DEP_SEL __BITS(31,28)

sys/arch/arm/amlogic/mesong12_clkc.c

68

#define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_FREF_SEL __BITS(25,24)

sys/arch/arm/amlogic/mesong12_clkc.c

69

#define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_MODE __BITS(23,22)

sys/arch/arm/amlogic/mesong12_clkc.c

70

#define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_OFFSET __BITS(21,20)

sys/arch/arm/amlogic/mesong12_clkc.c

71

#define HHI_PCIE_PLL_CNTL2_PCIE_APLL_STR_M __BITS(19,18)

sys/arch/arm/amlogic/mesong12_clkc.c

72

#define HHI_PCIE_PLL_CNTL2_PCIE_APLL_RESERVE __BITS(15,0)

sys/arch/arm/amlogic/mesong12_clkc.c

75

#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_HOLD_T __BITS(29,28)

sys/arch/arm/amlogic/mesong12_clkc.c

76

#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_IN __BITS(26,20)

sys/arch/arm/amlogic/mesong12_clkc.c

779

__BITS(1,0), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

78

#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_DIV __BITS(18,17)

sys/arch/arm/amlogic/mesong12_clkc.c

785

__BITS(17,16), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

797

__BITS(25,20), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

80

#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_ICAP __BITS(15,12)

sys/arch/arm/amlogic/mesong12_clkc.c

81

#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_IRES __BITS(11,8)

sys/arch/arm/amlogic/mesong12_clkc.c

82

#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_CPI __BITS(5,4)

sys/arch/arm/amlogic/mesong12_clkc.c

839

__BITS(1,0), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

845

__BITS(9,4), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

85

#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_SHIFT_T __BITS(27,26)

sys/arch/arm/amlogic/mesong12_clkc.c

857

__BITS(17,16), /* sel */ \

sys/arch/arm/amlogic/mesong12_clkc.c

86

#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_SHIFT_V __BITS(25,24)

sys/arch/arm/amlogic/mesong12_clkc.c

863

__BITS(25,20), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

88

#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_CAP __BITS(21,20)

sys/arch/arm/amlogic/mesong12_clkc.c

89

#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_CAPADJ __BITS(19,16)

sys/arch/arm/amlogic/mesong12_clkc.c

891

__BITS(7,0), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

90

#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_RES __BITS(13,12)

sys/arch/arm/amlogic/mesong12_clkc.c

904

MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(7,0)), /* m */ \

sys/arch/arm/amlogic/mesong12_clkc.c

905

MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(14,10)),/* n */ \

sys/arch/arm/amlogic/mesong12_clkc.c

906

MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL1, __BITS(15,0)),/* frac */ \

sys/arch/arm/amlogic/mesong12_clkc.c

914

__BITS(17,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

920

__BITS(19,18), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

926

__BITS(21,20), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

933

__BITS(17,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

952

MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(7,0)), /* m */ \

sys/arch/arm/amlogic/mesong12_clkc.c

953

MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(14,10)),/* n */ \

sys/arch/arm/amlogic/mesong12_clkc.c

954

MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL1, __BITS(11,0)),/* frac */ \

sys/arch/arm/amlogic/mesong12_clkc.c

969

__BITS(20,16), /* div */ \

sys/arch/arm/amlogic/mesong12_clkc.c

98

#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_ADJ_LDO __BITS(30,28)

sys/arch/arm/amlogic/mesong12_usb2phy.c

101

#define USB2PHY_R16_USB2_MPLL_N __BITS(14,10)

sys/arch/arm/amlogic/mesong12_usb2phy.c

102

#define USB2PHY_R16_USB2_MPLL_M __BITS(8,0)

sys/arch/arm/amlogic/mesong12_usb2phy.c

104

#define USB2PHY_R17_USB2_MPLL_FILTER_PVT1 __BITS(31,28)

sys/arch/arm/amlogic/mesong12_usb2phy.c

105

#define USB2PHY_R17_USB2_MPLL_FILTER_PVT2 __BITS(27,24)

sys/arch/arm/amlogic/mesong12_usb2phy.c

107

#define USB2PHY_R17_USB2_MPLL_LAMBDA0 __BITS(22,20)

sys/arch/arm/amlogic/mesong12_usb2phy.c

108

#define USB2PHY_R17_USB2_MPLL_LAMBDA1 __BITS(19,17)

sys/arch/arm/amlogic/mesong12_usb2phy.c

110

#define USB2PHY_R17_USB2_MPLL_FRAC_IN __BITS(13,0)

sys/arch/arm/amlogic/mesong12_usb2phy.c

113

#define USB2PHY_R18_USB2_MPLL_ADJ_LDO __BITS(30,29)

sys/arch/arm/amlogic/mesong12_usb2phy.c

114

#define USB2PHY_R18_USB2_MPLL_ALPHA __BITS(28,26)

sys/arch/arm/amlogic/mesong12_usb2phy.c

115

#define USB2PHY_R18_USB2_MPLL_BB_MODE __BITS(25,24)

sys/arch/arm/amlogic/mesong12_usb2phy.c

116

#define USB2PHY_R18_USB2_MPLL_BIAS_ADJ __BITS(23,22)

sys/arch/arm/amlogic/mesong12_usb2phy.c

117

#define USB2PHY_R18_USB2_MPLL_DATA_SEL __BITS(21,19)

sys/arch/arm/amlogic/mesong12_usb2phy.c

118

#define USB2PHY_R18_USB2_MPLL_ROU __BITS(18,16)

sys/arch/arm/amlogic/mesong12_usb2phy.c

119

#define USB2PHY_R18_USB2_MPLL_PFD_GAIN __BITS(15,14)

sys/arch/arm/amlogic/mesong12_usb2phy.c

122

#define USB2PHY_R18_USB2_MPLL_LK_S __BITS(11,6)

sys/arch/arm/amlogic/mesong12_usb2phy.c

123

#define USB2PHY_R18_USB2_MPLL_LK_W __BITS(5,2)

sys/arch/arm/amlogic/mesong12_usb2phy.c

124

#define USB2PHY_R18_USB2_MPLL_LKW_SEL __BITS(1,0)

sys/arch/arm/amlogic/mesong12_usb2phy.c

128

#define USB2PHY_R20_USB2_BGR_DBG_1_0 __BITS(30,29)

sys/arch/arm/amlogic/mesong12_usb2phy.c

129

#define USB2PHY_R20_USB2_BGR_VREF_4_0 __BITS(28,24)

sys/arch/arm/amlogic/mesong12_usb2phy.c

131

#define USB2PHY_R20_USB2_BGR_ADJ_4_0 __BITS(20,16)

sys/arch/arm/amlogic/mesong12_usb2phy.c

132

#define USB2PHY_R20_USB2_EDGE_DRV_TRIM_1_0 __BITS(15,14)

sys/arch/arm/amlogic/mesong12_usb2phy.c

134

#define USB2PHY_R20_USB2_DMON_SEL_3_0 __BITS(12,9)

sys/arch/arm/amlogic/mesong12_usb2phy.c

140

#define USB2PHY_R20_USB2_OTG_VBUS_TRIM_2_0 __BITS(3,1)

sys/arch/arm/amlogic/mesong12_usb2phy.c

143

#define USB2PHY_R21_BYPASS_UTMI_REG __BITS(25,20)

sys/arch/arm/amlogic/mesong12_usb2phy.c

144

#define USB2PHY_R21_BYPASS_UTMI_CNTR __BITS(15,6)

sys/arch/arm/amlogic/mesong12_usb2phy.c

145

#define USB2PHY_R21_USB2_OTG_ACA_TRIM_1_0 __BITS(5,4)

sys/arch/arm/amlogic/mesong12_usb2phy.c

47

#define USB2PHY_R03_DISC_THRESH __BITS(7,4)

sys/arch/arm/amlogic/mesong12_usb2phy.c

48

#define USB2PHY_R03_HSDIC_REF __BITS(3,2)

sys/arch/arm/amlogic/mesong12_usb2phy.c

49

#define USB2PHY_R03_SQUELCH_REF __BITS(1,0)

sys/arch/arm/amlogic/mesong12_usb2phy.c

51

#define USB2PHY_R04_I_C2L_BIAS_TRIM __BITS(31,28)

sys/arch/arm/amlogic/mesong12_usb2phy.c

56

#define USB2PHY_R04_CALIBRATION_CODE_VALUE __BITS(23,0)

sys/arch/arm/amlogic/mesong12_usb2phy.c

76

#define USB2PHY_R13_MINIMUM_COUNT_FOR_SYNC_DETECTION __BITS(20,16)

sys/arch/arm/amlogic/mesong12_usb2phy.c

79

#define USB2PHY_R13_CUSTOM_PATTERN_19 __BITS(7,0)

sys/arch/arm/amlogic/mesong12_usb2phy.c

81

#define USB2PHY_R14_BYPASS_CTRL __BITS(23,8)

sys/arch/arm/amlogic/mesong12_usb2phy.c

85

#define USB2PHY_R14_I_RPU_SW2_EN __BITS(3,2)

sys/arch/arm/amlogic/mesong12_usb2phy.c

96

#define USB2PHY_R16_USB2_MPLL_LOCK_LONG __BITS(25,24)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

240

val &= ~__BITS(11,4);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

241

val |= __SHIFTIN(2, __BITS(11,4));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

247

val &= ~__BITS(7,6);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

248

val |= __SHIFTIN(2, __BITS(7,6));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

249

val &= ~__BITS(10,8);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

250

val |= __SHIFTIN(3, __BITS(10,8));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

257

val &= ~__BITS(13,7);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

258

val |= __SHIFTIN(0x16, __BITS(13,7));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

259

val &= ~__BITS(6,0);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

260

val |= __SHIFTIN(0x7f, __BITS(6,0));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

266

val &= ~__BITS(7,4);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

267

val |= __SHIFTIN(8, __BITS(7,4));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

40

#define USB3PCIEPHY_R0_PCIE_USB3_SWITCH __BITS(6,5)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

41

#define USB3PCIEPHY_R0_PCIE_POWER_STATE __BITS(4,0)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

43

#define USB3PCIEPHY_R1_PHY_MPLL_MULTIPLIER __BITS(31,25)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

45

#define USB3PCIEPHY_R1_PHY_LOS_BIAS __BITS(23,21)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

46

#define USB3PCIEPHY_R1_PHY_LOS_LEVEL __BITS(20,16)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

47

#define USB3PCIEPHY_R1_PHY_RX0_EQ __BITS(15,13)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

48

#define USB3PCIEPHY_R1_PHY_RX1_EQ __BITS(12,10)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

49

#define USB3PCIEPHY_R1_PHY_TX0_TERM_OFFSET __BITS(9,5)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

50

#define USB3PCIEPHY_R1_PHY_TX1_TERM_OFFSET __BITS(4,0)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

52

#define USB3PCIEPHY_R2_PHY_TX_VBOOST_LVL __BITS(20,18)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

53

#define USB3PCIEPHY_R2_PCS_TX_DEEMPH_GEN1 __BITS(17,12)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

54

#define USB3PCIEPHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB __BITS(11,6)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

55

#define USB3PCIEPHY_R2_PCS_TX_DEEMPH_GEN2_6DB __BITS(5,0)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

59

#define USB3PCIEPHY_R4_PHY_CR_DATA_IN __BITS(17,2)

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

65

#define USB3PCIEPHY_R5_PHY_CR_DATA_OUT __BITS(15,0)

sys/arch/arm/amlogic/mesongx_mmc.c

107

#define STATUS_DAT_I __BITS(23,16)

sys/arch/arm/amlogic/mesongx_mmc.c

116

#define STATUS_RXD_ERR __BITS(7,0)

sys/arch/arm/amlogic/mesongx_mmc.c

129

#define IRQ_EN_RXD_ERR __BITS(7,0)

sys/arch/arm/amlogic/mesongx_mmc.c

142

#define MESONGX_MMC_FLAGS_CMD_INDEX __BITS(29,24)

sys/arch/arm/amlogic/mesongx_mmc.c

151

#define MESONGX_MMC_FLAGS_TIMEOUT __BITS(15,12)

sys/arch/arm/amlogic/mesongx_mmc.c

155

#define MESONGX_MMC_FLAGS_LENGTH __BITS(8,0)

sys/arch/arm/amlogic/mesongx_mmc.c

50

#define CLOCK_CFG_V2_RX_DELAY __BITS(23,20)

sys/arch/arm/amlogic/mesongx_mmc.c

51

#define CLOCK_CFG_V2_TX_DELAY __BITS(19,16)

sys/arch/arm/amlogic/mesongx_mmc.c

54

#define CLOCK_CFG_V3_RX_DELAY __BITS(27,22)

sys/arch/arm/amlogic/mesongx_mmc.c

55

#define CLOCK_CFG_V3_TX_DELAY __BITS(21,16)

sys/arch/arm/amlogic/mesongx_mmc.c

56

#define CLOCK_CFG_SRAM_PD __BITS(15,14)

sys/arch/arm/amlogic/mesongx_mmc.c

57

#define CLOCK_CFG_RX_PHASE __BITS(13,12)

sys/arch/arm/amlogic/mesongx_mmc.c

58

#define CLOCK_CFG_TX_PHASE __BITS(11,10)

sys/arch/arm/amlogic/mesongx_mmc.c

59

#define CLOCK_CFG_CO_PHASE __BITS(9,8)

sys/arch/arm/amlogic/mesongx_mmc.c

60

#define CLOCK_CFG_SRC __BITS(7,6)

sys/arch/arm/amlogic/mesongx_mmc.c

61

#define CLOCK_CFG_DIV __BITS(5,0)

sys/arch/arm/amlogic/mesongx_mmc.c

64

#define ADJUST_ADJ_DELAY __BITS(21,16)

sys/arch/arm/amlogic/mesongx_mmc.c

68

#define ADJUST_CALI_SEL __BITS(11,8)

sys/arch/arm/amlogic/mesongx_mmc.c

70

#define CALOUT_CALI_SETUP __BITS(15,8)

sys/arch/arm/amlogic/mesongx_mmc.c

72

#define CALOUT_CALI_IDX __BITS(5,0)

sys/arch/arm/amlogic/mesongx_mmc.c

75

#define START_DESC_ADDR __BITS(31,2)

sys/arch/arm/amlogic/mesongx_mmc.c

79

#define CFG_IP_TXD_ADJ __BITS(31,28)

sys/arch/arm/amlogic/mesongx_mmc.c

92

#define CFG_RC_CC __BITS(15,12)

sys/arch/arm/amlogic/mesongx_mmc.c

94

#define CFG_BL_LEN __BITS(7,4)

sys/arch/arm/amlogic/mesongx_mmc.c

97

#define CFG_BUS_WIDTH __BITS(1,0)

sys/arch/arm/amlogic/mesongx_wdt.c

49

#define CNTL_CLK_DIV_TCNT __BITS(17,0)

sys/arch/arm/amlogic/mesongxbb_clkc.c

106

__BITS(17,16), /* div */

sys/arch/arm/amlogic/mesongxbb_clkc.c

111

MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */

sys/arch/arm/amlogic/mesongxbb_clkc.c

112

MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */

sys/arch/arm/amlogic/mesongxbb_clkc.c

113

MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */

sys/arch/arm/amlogic/mesongxbb_clkc.c

120

__BITS(17,16), /* div */

sys/arch/arm/amlogic/mesongxbb_clkc.c

129

MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */

sys/arch/arm/amlogic/mesongxbb_clkc.c

131

MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */

sys/arch/arm/amlogic/mesongxbb_clkc.c

135

MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */

sys/arch/arm/amlogic/mesongxbb_clkc.c

137

MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */

sys/arch/arm/amlogic/mesongxbb_clkc.c

141

MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */

sys/arch/arm/amlogic/mesongxbb_clkc.c

143

MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */

sys/arch/arm/amlogic/mesongxbb_clkc.c

164

__BITS(14,12), /* sel */

sys/arch/arm/amlogic/mesongxbb_clkc.c

169

__BITS(6,0), /* div */

sys/arch/arm/amlogic/mesongxbb_clkc.c

174

__BITS(11,9), /* sel */

sys/arch/arm/amlogic/mesongxbb_clkc.c

178

__BITS(27,25), /* sel */

sys/arch/arm/amlogic/mesongxbb_clkc.c

182

__BITS(11,9), /* sel */

sys/arch/arm/amlogic/mesongxbb_clkc.c

187

__BITS(6,0), /* div */

sys/arch/arm/amlogic/mesongxbb_clkc.c

191

__BITS(22,16), /* div */

sys/arch/arm/amlogic/mesongxbb_clkc.c

195

__BITS(6,0), /* div */

sys/arch/arm/amlogic/mesongxbb_clkc.c

62

#define HHI_SYS_PLL_CNTL_OD __BITS(17,16)

sys/arch/arm/amlogic/mesongxbb_clkc.c

63

#define HHI_SYS_PLL_CNTL_DIV __BITS(14,9)

sys/arch/arm/amlogic/mesongxbb_clkc.c

64

#define HHI_SYS_PLL_CNTL_MUL __BITS(8,0)

sys/arch/arm/amlogic/mesongxbb_clkc.c

97

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */

sys/arch/arm/amlogic/mesongxbb_clkc.c

98

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */

sys/arch/arm/amlogic/mesongxl_usb3phy.c

46

#define REG1_U3H_FLADJ_30MHZ_REG __BITS(24,19)

sys/arch/arm/amlogic/mesongxl_usb3phy.c

52

#define REG5_ID_DIG_TH __BITS(15,8)

sys/arch/arm/apple/apple_dart.c

233

addr = __SHIFTIN(DART_READ(sc, DART_ERR_ADDRL), __BITS(31, 0));

sys/arch/arm/apple/apple_dart.c

234

addr |= __SHIFTIN(DART_READ(sc, DART_ERR_ADDRH), __BITS(63, 32));

sys/arch/arm/apple/apple_dart.c

57

#define DART_ERR_STREAM_MASK __BITS(27, 24)

sys/arch/arm/apple/apple_dart.c

58

#define DART_ERR_CODE_MASK __BITS(11, 0)

sys/arch/arm/apple/apple_dart.c

665

KASSERTMSG(__SHIFTOUT(pa, __BITS(DART_TTBR_SHIFT - 1, 0)) == 0,

sys/arch/arm/apple/apple_dart.c

96

#define DART_L2_START_MASK __BITS(63, 52)

sys/arch/arm/apple/apple_dart.c

97

#define DART_L2_END_MASK __BITS(51, 40)

sys/arch/arm/apple/apple_dart.c

98

#define DART_L2_SUBPAGE(addr) __SHIFTOUT((addr), __BITS(13, 2))

sys/arch/arm/apple/apple_iic.c

60

#define I2C_MTXFIFO_DATA_MASK __BITS(7,0)

sys/arch/arm/apple/apple_iic.c

65

#define I2C_MRXFIFO_DATA_MASK __BITS(7,0)

sys/arch/arm/apple/apple_iic.c

72

#define I2C_CTL_CLK_MASK __BITS(7,0)

sys/arch/arm/apple/apple_intc.c

64

#define AIC_INFO_NIRQ __BITS(15,0)

sys/arch/arm/apple/apple_intc.c

67

#define AIC_EVENT_TYPE __BITS(31,16)

sys/arch/arm/apple/apple_intc.c

71

#define AIC_EVENT_DATA __BITS(15,0)

sys/arch/arm/apple/apple_pcie.c

158

u_int portno = __SHIFTOUT(be32toh(reg[0]), __BITS(13,11));

sys/arch/arm/apple/apple_pcie.c

198

__SHIFTOUT(sc->sc_msi_addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

491

__SHIFTOUT(addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

493

__SHIFTOUT(addr, __BITS(63, 32)));

sys/arch/arm/apple/apple_pcie.c

497

__SHIFTOUT(addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

543

__SHIFTOUT(addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

545

__SHIFTOUT(addr, __BITS(63, 32)));

sys/arch/arm/apple/apple_pcie.c

81

#define PCIE_PORT_MSI_CTRL_32 __SHIFTIN(5U, __BITS(7,4))

sys/arch/arm/apple/apple_pinctrl.c

61

#define APPLE_PIN(pinmux) __SHIFTOUT((pinmux), __BITS(15, 0))

sys/arch/arm/apple/apple_pinctrl.c

62

#define APPLE_FUNC(pinmux) __SHIFTOUT((pinmux), __BITS(31, 16))

sys/arch/arm/apple/apple_pinctrl.c

65

#define GPIO_PIN_GROUP_MASK __BITS(18, 16)

sys/arch/arm/apple/apple_pinctrl.c

67

#define GPIO_PIN_FUNC_MASK __BITS(6, 5)

sys/arch/arm/apple/apple_pinctrl.c

68

#define GPIO_PIN_MODE_MASK __BITS(3, 1)

sys/arch/arm/apple/apple_pmgr.c

47

#define PMGR_PS_TARGET_MASK __BITS(3, 0)

sys/arch/arm/apple/apple_pmgr.c

48

#define PMGR_PS_ACTUAL_MASK __BITS(7, 4)

sys/arch/arm/apple/apple_rtkit.c

37

#define RTKIT_MGMT_TYPE_MASK __BITS(59, 52)

sys/arch/arm/apple/apple_rtkit.c

40

#define RTKIT_MGMT_PWR_STATE_MASK __BITS(7, 0)

sys/arch/arm/apple/apple_rtkit.c

51

#define RTKIT_MGMT_HELLO_MINVER_MASK __BITS(15, 0)

sys/arch/arm/apple/apple_rtkit.c

53

#define RTKIT_MGMT_HELLO_MAXVER_MASK __BITS(31, 16)

sys/arch/arm/apple/apple_rtkit.c

57

#define RTKIT_MGMT_STARTEP_EP_MASK __BITS(39, 32)

sys/arch/arm/apple/apple_rtkit.c

61

#define RTKIT_MGMT_EPMAP_BASE_MASK __BITS(34, 32)

sys/arch/arm/apple/apple_rtkit.c

63

#define RTKIT_MGMT_EPMAP_BITMAP_MASK __BITS(31, 0)

sys/arch/arm/apple/apple_rtkit.c

68

#define RTKIT_BUFFER_ADDR_MASK __BITS(41, 0)

sys/arch/arm/apple/apple_rtkit.c

70

#define RTKIT_BUFFER_SIZE_MASK __BITS(51, 44)

sys/arch/arm/apple/apple_smc.c

283

key |= __SHIFTIN(digits[__SHIFTOUT(pn, __BITS(3, 0))], __BITS(7, 0));

sys/arch/arm/apple/apple_smc.c

284

key |= __SHIFTIN(digits[__SHIFTOUT(pn, __BITS(7, 4))], __BITS(15, 8));

sys/arch/arm/apple/apple_smc.c

73

#define SMC_DATA __BITS(63, 32)

sys/arch/arm/apple/apple_smc.c

74

#define SMC_WLEN __BITS(31, 24)

sys/arch/arm/apple/apple_smc.c

75

#define SMC_LENGTH __BITS(23, 16)

sys/arch/arm/apple/apple_smc.c

76

#define SMC_ID __BITS(15, 12)

sys/arch/arm/apple/apple_smc.c

77

#define SMC_CMD __BITS(7, 0)

sys/arch/arm/apple/apple_smc.c

80

#define SMC_ERROR_MASK __BITS(7, 0)

sys/arch/arm/arm/cpufunc.c

3015

__SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_VARIANT_MASK), __BITS(7,4)) |

sys/arch/arm/arm/cpufunc.c

3016

__SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_REVISION_MASK), __BITS(3,0)) |

sys/arch/arm/arm/cpufunc.c

3027

diagset |= __BITS(11,10);

sys/arch/arm/arm/psci.h

111

#define PSCI_VERSION_MAJOR __BITS(31,16)

sys/arch/arm/arm/psci.h

112

#define PSCI_VERSION_MINOR __BITS(15,0)

sys/arch/arm/arm/syscall.c

201

const uint32_t swi = __SHIFTOUT(insn, __BITS(23,0));

sys/arch/arm/arm32/cpu.c

890

if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) {

sys/arch/arm/arm32/pmap.c

7810

if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) {

sys/arch/arm/arm32/pmap.c

7833

if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) {

sys/arch/arm/arm32/pmap.c

7835

} else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) {

sys/arch/arm/broadcom/bcm2835_bscreg.h

35

#define __BITS32(x, y) ((uint32_t)__BITS((x), (y)))

sys/arch/arm/broadcom/bcm2835_cm.h

33

#define CM_CTL_PASSWD __BITS(24,31)

sys/arch/arm/broadcom/bcm2835_cm.h

34

#define CM_CTL_MASH __BITS(9,10)

sys/arch/arm/broadcom/bcm2835_cm.h

41

#define CM_DIV_PASSWD __BITS(24,31)

sys/arch/arm/broadcom/bcm2835_cm.h

42

#define CM_DIV_DIVI __BITS(12,23)

sys/arch/arm/broadcom/bcm2835_cm.h

43

#define CM_DIV_DIVF __BITS(0,11)

sys/arch/arm/broadcom/bcm2835_dmac.h

39

#define DMAC_CS_PANIC_PRIORITY __BITS(23,20)

sys/arch/arm/broadcom/bcm2835_dmac.h

40

#define DMAC_CS_PRIORITY __BITS(19,16)

sys/arch/arm/broadcom/bcm2835_dmac.h

59

#define DMAC_DEBUG_VERSION __BITS(27,25)

sys/arch/arm/broadcom/bcm2835_dmac.h

60

#define DMAC_DEBUG_DMA_STATE __BITS(24,16)

sys/arch/arm/broadcom/bcm2835_dmac.h

61

#define DMAC_DEBUG_DMA_ID __BITS(15,8)

sys/arch/arm/broadcom/bcm2835_dmac.h

62

#define DMAC_DEBUG_OUTSTANDING_WRITES __BITS(7,4)

sys/arch/arm/broadcom/bcm2835_dmac.h

73

#define DMAC_TI_WAITS __BITS(25,21)

sys/arch/arm/broadcom/bcm2835_dmac.h

74

#define DMAC_TI_PERMAP __BITS(20,16)

sys/arch/arm/broadcom/bcm2835_dmac.h

75

#define DMAC_TI_BURST_LENGTH __BITS(15,12)

sys/arch/arm/broadcom/bcm2835_dmac.h

90

#define DMAC_TXFR_LEN_YLENGTH __BITS(29,16)

sys/arch/arm/broadcom/bcm2835_dmac.h

91

#define DMAC_TXFR_LEN_XLENGTH __BITS(15,0)

sys/arch/arm/broadcom/bcm2835_dmac.h

93

#define DMAC_STRIDE_D_STRIDE __BITS(31,16)

sys/arch/arm/broadcom/bcm2835_dmac.h

94

#define DMAC_STRIDE_S_STRIDE __BITS(15,0)

sys/arch/arm/broadcom/bcm2835_intr.c

299

#define BCM2835_INTBIT_ARM __BITS(0,7)

sys/arch/arm/broadcom/bcm2835_intr.c

300

#define BCM2835_INTBIT_GPU0 __BITS(10,14)

sys/arch/arm/broadcom/bcm2835_intr.c

301

#define BCM2835_INTBIT_GPU1 __BITS(15,20)

sys/arch/arm/broadcom/bcm2835_intr.c

686

#define BCM2836MP_TIMER_IRQS __BITS(3,0)

sys/arch/arm/broadcom/bcm2835_intr.c

687

#define BCM2836MP_MAILBOX_IRQS __BITS(4,7)

sys/arch/arm/broadcom/bcm2835_pwm.h

48

#define PWM_CTL_WRITEZERO (__BITS(16,31)|__BIT(14))

sys/arch/arm/broadcom/bcm2835_pwm.h

63

#define PWM_STA_WRITEZERO __BITS(13,31)

sys/arch/arm/broadcom/bcm2835_pwm.h

66

#define PWM_DMAC_PANIC __BITS(8,15)

sys/arch/arm/broadcom/bcm2835_pwm.h

67

#define PWM_DMAC_DREQ __BITS(0,7)

sys/arch/arm/broadcom/bcm2835_pwm.h

68

#define PWM_DMAC_WRITEZERO __BITS(16,30)

sys/arch/arm/broadcom/bcm2835_rng.c

50

#define RNG_STATUS_CNT __BITS(31,24)

sys/arch/arm/broadcom/bcm2835_sdhost.c

65

#define SDCDIV_MASK __BITS(10,0)

sys/arch/arm/broadcom/bcm2835_sdhost.c

83

#define SDEDM_RD_FIFO __BITS(18,14)

sys/arch/arm/broadcom/bcm2835_sdhost.c

84

#define SDEDM_WR_FIFO __BITS(13,9)

sys/arch/arm/broadcom/bcm2835_spireg.h

35

#define __BITS32(x, y) ((uint32_t)__BITS((x), (y)))

sys/arch/arm/broadcom/bcm2838_pcie.c

53

#define PHYS_HI_SPACE __BITS(25,24)

sys/arch/arm/broadcom/bcm2838_pcie.h

102

#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT __BITS(20,31)

sys/arch/arm/broadcom/bcm2838_pcie.h

103

#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE __BITS(4,15)

sys/arch/arm/broadcom/bcm2838_pcie.h

106

#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE __BITS(0,7)

sys/arch/arm/broadcom/bcm2838_pcie.h

109

#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT __BITS(0,7)

sys/arch/arm/broadcom/bcm2838_pcie.h

132

#define PCIE_EXT_CFG_INDEX_BUSNUM __BITS(20,27)

sys/arch/arm/broadcom/bcm2838_pcie.h

133

#define PCIE_EXT_CFG_INDEX_SLOT __BITS(15,19)

sys/arch/arm/broadcom/bcm2838_pcie.h

134

#define PCIE_EXT_CFG_INDEX_FUNC __BITS(12,14)

sys/arch/arm/broadcom/bcm2838_pcie.h

37

#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1 __BITS(0,1)

sys/arch/arm/broadcom/bcm2838_pcie.h

38

#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2 __BITS(2,3)

sys/arch/arm/broadcom/bcm2838_pcie.h

39

#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3 __BITS(4,5)

sys/arch/arm/broadcom/bcm2838_pcie.h

42

#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE __BITS(0,23)

sys/arch/arm/broadcom/bcm2838_pcie.h

45

#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT __BITS(10,11)

sys/arch/arm/broadcom/bcm2838_pcie.h

50

#define PCIE_RC_DL_MDIO_DATA __BITS(0,30)

sys/arch/arm/broadcom/bcm2838_pcie.h

51

#define PCIE_RC_DL_MDIO_PORT __BITS(16,19)

sys/arch/arm/broadcom/bcm2838_pcie.h

52

#define PCIE_RC_DL_MDIO_REGAD __BITS(0,15)

sys/arch/arm/broadcom/bcm2838_pcie.h

53

#define PCIE_RC_DL_MDIO_CMD __BITS(20,31)

sys/arch/arm/broadcom/bcm2838_pcie.h

61

#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE __BITS(20,21)

sys/arch/arm/broadcom/bcm2838_pcie.h

62

#define PCIE_MISC_MISC_CTRL_SCB0_SIZE __BITS(27,31)

sys/arch/arm/broadcom/bcm2838_pcie.h

63

#define PCIE_MISC_MISC_CTRL_SCB1_SIZE __BITS(22,26)

sys/arch/arm/broadcom/bcm2838_pcie.h

64

#define PCIE_MISC_MISC_CTRL_SCB2_SIZE __BITS(0,4)

sys/arch/arm/broadcom/bcm2838_pcie.h

67

#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED __BITS(0,3)

sys/arch/arm/broadcom/bcm2838_pcie.h

69

#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH __BITS(24,29)

sys/arch/arm/broadcom/bcm2838_pcie.h

70

#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED __BITS(16,19)

sys/arch/arm/broadcom/bcm2838_pcie.h

72

#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN __BITS(4,7)

sys/arch/arm/broadcom/bcm2838_pcie.h

74

#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED __BITS(0,3)

sys/arch/arm/broadcom/bcm2838_pcie.h

80

#define PCIE_MISC_RC_BARx_CONFIG_LO_MATCH_ADDRESS __BITS(12,31)

sys/arch/arm/broadcom/bcm2838_pcie.h

81

#define PCIE_MISC_RC_BARx_CONFIG_LO_SIZE __BITS(0,5)

sys/arch/arm/broadcom/bcm2838_pcie.h

99

#define PCIE_MISC_REVISION_MAJMIN __BITS(0,15)

sys/arch/arm/broadcom/bcm53xx_cca.c

231

sc->sc_gpiopins &= ~__BITS(15,12);

sys/arch/arm/broadcom/bcm53xx_reg.h

1022

#define NAND_CMD_START_OPCODE __BITS(28,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

1046

#define NAND_CMD_START_CSEL __BITS(18,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

1047

#define NAND_CMD_EXT_ADDRESS __BITS(15,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

165

#define CHIPID_REV __BITS(19,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

166

#define CHIPID_ID __BITS(15,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

175

#define CAPABILITY_UART_CLKSEL __BITS(4,3)

sys/arch/arm/broadcom/bcm53xx_reg.h

180

#define CAPABILITY_UART_COUNT __BITS(1,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

206

#define TIMERVAL_ONCOUNT __BITS(31,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

207

#define TIMERVAL_OFFCOUNT __BITS(15,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

214

#define CLKDIV_JTAG_MASTER_CLKDIV __BITS(13,9)

sys/arch/arm/broadcom/bcm53xx_reg.h

215

#define CLKDIV_UART_CLKDIV __BITS(7,1)

sys/arch/arm/broadcom/bcm53xx_reg.h

226

#define GSIOCTL_NUM_DATABYTES __BITS(17,16) // actual is + 1

sys/arch/arm/broadcom/bcm53xx_reg.h

227

#define GSIOCTL_NUM_WAITCYCLES __BITS(15,14) // actual is + 1

sys/arch/arm/broadcom/bcm53xx_reg.h

228

#define GSIOCTL_NUM_ADDRESSBYTES __BITS(13,12) // actual is + 1

sys/arch/arm/broadcom/bcm53xx_reg.h

229

#define GSIOCTL_GSIOCODE __BITS(10,8)

sys/arch/arm/broadcom/bcm53xx_reg.h

235

#define GSIOCTL_GSIOOP __BITS(7,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

241

#define CLKDIV2_GSIODIV __BITS(20,5)

sys/arch/arm/broadcom/bcm53xx_reg.h

258

#define SRA_PAGE __BITS(31,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

259

#define SRA_OFFSET __BITS(23,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

260

#define SRA_PAGEOFFSET __BITS(31,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

277

#define MIIMGT_MDCDIV __BITS(6,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

279

#define MIICMD_SB __BITS(31,30)

sys/arch/arm/broadcom/bcm53xx_reg.h

281

#define MIICMD_OP __BITS(29,28)

sys/arch/arm/broadcom/bcm53xx_reg.h

284

#define MIICMD_PHY __BITS(27,23)

sys/arch/arm/broadcom/bcm53xx_reg.h

285

#define MIICMD_REG __BITS(22,18)

sys/arch/arm/broadcom/bcm53xx_reg.h

286

#define MIICMD_TA __BITS(17,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

288

#define MIICMD_DATA __BITS(15,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

299

#define RNG_COMBLK2_OSC_DIS __BITS(27,22)

sys/arch/arm/broadcom/bcm53xx_reg.h

300

#define RNG_COMBLK1_OSC_DIS __BITS(21,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

301

#define RNG_ICLK_BYP_DIV_CNT __BITS(15,8)

sys/arch/arm/broadcom/bcm53xx_reg.h

307

#define RNG_VAL __BITS(31,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

308

#define RNG_WARM_CNT __BITS(19,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

328

#define CRUCTL_QSPI_CLK_SEL __BITS(2,1)

sys/arch/arm/broadcom/bcm53xx_reg.h

336

#define GENPLL_CONTROL5_NDIV_INT __BITS(29,20) // = (n ? n : 1024)

sys/arch/arm/broadcom/bcm53xx_reg.h

337

#define GENPLL_CONTROL5_NDIV_FRAC __BITS(19,0) // = 1 / n

sys/arch/arm/broadcom/bcm53xx_reg.h

339

#define GENPLL_CONTROL6_PDIV __BITS(26,24) // = (n ? n : 8)

sys/arch/arm/broadcom/bcm53xx_reg.h

340

#define GENPLL_CONTROL6_CH0_MDIV __BITS(23,16) // = (n ? n : 256), clk_mac

sys/arch/arm/broadcom/bcm53xx_reg.h

341

#define GENPLL_CONTROL6_CH1_MDIV __BITS(15,8) // = (n ? n : 256), clk_robo

sys/arch/arm/broadcom/bcm53xx_reg.h

342

#define GENPLL_CONTROL6_CH2_MDIV __BITS(7,0) // = (n ? n : 256), clf_usb2

sys/arch/arm/broadcom/bcm53xx_reg.h

344

#define GENPLL_CONTROL7_CH3_MDIV __BITS(23,16) // = (n ? n : 256), clk_iproc

sys/arch/arm/broadcom/bcm53xx_reg.h

348

#define USB2_CONTROL_KA __BITS(24,22)

sys/arch/arm/broadcom/bcm53xx_reg.h

349

#define USB2_CONTROL_KI __BITS(31,19)

sys/arch/arm/broadcom/bcm53xx_reg.h

350

#define USB2_CONTROL_KP __BITS(18,15)

sys/arch/arm/broadcom/bcm53xx_reg.h

351

#define USB2_CONTROL_PDIV __BITS(14,12) // = (n ? n : 8)

sys/arch/arm/broadcom/bcm53xx_reg.h

352

#define USB2_CONTROL_NDIV_INT __BITS(11,2) // = (n ? n : 1024)

sys/arch/arm/broadcom/bcm53xx_reg.h

370

#define STRAP_BOOT_DEV __BITS(17,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

371

#define STRAP_NAND_TYPE __BITS(15,12)

sys/arch/arm/broadcom/bcm53xx_reg.h

372

#define STRAP_NAND_PAGE __BITS(11,10)

sys/arch/arm/broadcom/bcm53xx_reg.h

375

#define STRAP_P5_MODE __BITS(7,6)

sys/arch/arm/broadcom/bcm53xx_reg.h

389

#define LCPLL_CONTROL1_PDIV __BITS(30,28) // = (n ? n : 8)

sys/arch/arm/broadcom/bcm53xx_reg.h

390

#define LCPLL_CONTROL1_NDIV_INT __BITS(27,20) // = (n ? n : 256)

sys/arch/arm/broadcom/bcm53xx_reg.h

391

#define LCPLL_CONTROL1_NDIV_FRAC __BITS(19,0) // = 1 / n

sys/arch/arm/broadcom/bcm53xx_reg.h

396

#define LCPLL_CONTROL2_CH0_MDIV __BITS(31,24) // = (n ? n : 256), clk_pcie_ref

sys/arch/arm/broadcom/bcm53xx_reg.h

397

#define LCPLL_CONTROL2_CH1_MDIV __BITS(23,16) // = (n ? n : 256), clk_sdio

sys/arch/arm/broadcom/bcm53xx_reg.h

398

#define LCPLL_CONTROL2_CH2_MDIV __BITS(15,8) // = (n ? n : 256), clk_ddr

sys/arch/arm/broadcom/bcm53xx_reg.h

399

#define LCPLL_CONTROL2_CH3_MDIV __BITS(7,0) // = (n ? n : 256), clf_dft

sys/arch/arm/broadcom/bcm53xx_reg.h

412

#define CTL_01_MAX_CHIP_SEL __BITS(18,16) // not documented as such

sys/arch/arm/broadcom/bcm53xx_reg.h

413

#define CTL_01_MAX_COL __BITS(11,8)

sys/arch/arm/broadcom/bcm53xx_reg.h

414

#define CTL_01_MAX_ROW __BITS(4,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

417

#define CTL_82_COL_DIFF __BITS(26,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

418

#define CTL_82_ROW_DIFF __BITS(18,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

419

#define CTL_82_BANK_DIFF __BITS(9,8)

sys/arch/arm/broadcom/bcm53xx_reg.h

423

#define CTL_86_CS_MAP __BITS(27,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

426

#define CTL_86_NUM_QENT_ACT_DIS __BITS(2,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

430

#define CTL_87_Q_FULLNESS __BITS(18,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

432

#define CTL_87_BURST_ON_FLY_BIT __BITS(3,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

436

#define PLL_STATUS_MHZ __BITS(25,14)

sys/arch/arm/broadcom/bcm53xx_reg.h

438

#define PLL_STATUS_STATUS __BITS(12,1)

sys/arch/arm/broadcom/bcm53xx_reg.h

442

#define PLL_DIVIDERS_POST_DIV __BITS(13,11)

sys/arch/arm/broadcom/bcm53xx_reg.h

443

#define PLL_DIVIDERS_PDIV __BITS(10,8) // 4x: (n ? n : 8), n = n - 4, 4x

sys/arch/arm/broadcom/bcm53xx_reg.h

444

#define PLL_DIVIDERS_NDIV __BITS(7,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

453

#define PCIE_AWCACHE_CONFIG __BITS(17,14)

sys/arch/arm/broadcom/bcm53xx_reg.h

454

#define PCIE_AWUSER_CONFIG __BITS(13,9)

sys/arch/arm/broadcom/bcm53xx_reg.h

455

#define PCIE_ARCACHE_CONFIG __BITS(8,5)

sys/arch/arm/broadcom/bcm53xx_reg.h

456

#define PCIE_ARUSER_CONFIG __BITS(4,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

459

#define CFG_IND_ADDR_FUNC __BITS(15,13)

sys/arch/arm/broadcom/bcm53xx_reg.h

460

#define CFG_IND_ADDR_LAYER __BITS(12,11)

sys/arch/arm/broadcom/bcm53xx_reg.h

461

#define CFG_IND_ADDR_REG __BITS(10,2)

sys/arch/arm/broadcom/bcm53xx_reg.h

464

#define CFG_ADDR_BUS __BITS(27,20)

sys/arch/arm/broadcom/bcm53xx_reg.h

465

#define CFG_ADDR_DEV __BITS(19,15)

sys/arch/arm/broadcom/bcm53xx_reg.h

466

#define CFG_ADDR_FUNC __BITS(14,12)

sys/arch/arm/broadcom/bcm53xx_reg.h

467

#define CFG_ADDR_REG __BITS(11,2)

sys/arch/arm/broadcom/bcm53xx_reg.h

468

#define CFG_ADDR_TYPE __BITS(1,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

522

#define PCIE_OARR_ADDR __BITS(31,26)

sys/arch/arm/broadcom/bcm53xx_reg.h

529

#define PCIE_OMAP_ADDRL __BITS(31,26)

sys/arch/arm/broadcom/bcm53xx_reg.h

544

#define STRAP_PCIE_REPLAY_BUF_TM __BITS(8,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

569

#define INT_N_DELAY __BITS(9,6)

sys/arch/arm/broadcom/bcm53xx_reg.h

570

#define INT_N_EVENT __BITS(1,1)

sys/arch/arm/broadcom/bcm53xx_reg.h

574

#define HEAD_PTR __BITS(5,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

578

#define TAIL_PTR __BITS(5,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

636

#define CLK_POLICY_FREQ_POLICY3 __BITS(26,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

637

#define CLK_POLICY_FREQ_POLICY2 __BITS(18,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

638

#define CLK_POLICY_FREQ_POLICY1 __BITS(10,8)

sys/arch/arm/broadcom/bcm53xx_reg.h

639

#define CLK_POLICY_FREQ_POLICY0 __BITS(2,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

647

#define CLK_APB_DIV_VALUE __BITS(1,0) // n = n + 1

sys/arch/arm/broadcom/bcm53xx_reg.h

654

#define CLK_PLLARMA_PDIV __BITS(26,24) // = (n ? n : 16(?))

sys/arch/arm/broadcom/bcm53xx_reg.h

655

#define CLK_PLLARMA_NDIV_INT __BITS(17,8) // = (n ? n : 1024)

sys/arch/arm/broadcom/bcm53xx_reg.h

658

#define CLK_PLLARMB_NDIV_FRAC __BITS(19,0) // = 1 / n

sys/arch/arm/broadcom/bcm53xx_reg.h

699

#define IO_CONTROL_DIRECT_ARUSER __BITS(29,25)

sys/arch/arm/broadcom/bcm53xx_reg.h

700

#define IO_CONTROL_DIRECT_AWUSER __BITS(24,20)

sys/arch/arm/broadcom/bcm53xx_reg.h

701

#define IO_CONTROL_DIRECT_ARCACHE __BITS(19,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

702

#define IO_CONTROL_DIRECT_AWCACHE __BITS(10,7)

sys/arch/arm/broadcom/bcm53xx_reg.h

750

#define RXSTS_FRAMELEN __BITS(15,0) // # of bytes (including padding)

sys/arch/arm/broadcom/bcm53xx_reg.h

751

#define RXSTS_PKTTYPE __BITS(17,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

761

#define RXSTS_DESC_COUNT __BITS(27,24) // # of descriptors - 1

sys/arch/arm/broadcom/bcm53xx_reg.h

766

#define TXC_DRNG __BITS(19,18)

sys/arch/arm/broadcom/bcm53xx_reg.h

767

#define RXC_DRNG __BITS(17,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

770

#define FLOW_CTRL_MODE __BITS(6,5)

sys/arch/arm/broadcom/bcm53xx_reg.h

807

#define INTRCVLAZY_FRAMECOUNT __BITS(31,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

808

#define INTRCVLAZY_TIMEOUT __BITS(23,0)

sys/arch/arm/broadcom/bcm53xx_reg.h

830

#define XMTCTL_PREFETCH_THRESH __BITS(25,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

831

#define XMTCTL_PREFETCH_CTL __BITS(23,21)

sys/arch/arm/broadcom/bcm53xx_reg.h

832

#define XMTCTL_BURSTLEN __BITS(20,18)

sys/arch/arm/broadcom/bcm53xx_reg.h

833

#define XMTCTL_ADDREXT __BITS(17,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

836

#define XMTCTL_OUTSTANDING_READS __BITS(7,6)

sys/arch/arm/broadcom/bcm53xx_reg.h

842

#define XMT_LASTDSCR __BITS(11,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

846

#define XMTSTATE __BITS(31,28)

sys/arch/arm/broadcom/bcm53xx_reg.h

852

#define XMT_CURRDSCR __BITS(11,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

854

#define XMTERR __BITS(31,28)

sys/arch/arm/broadcom/bcm53xx_reg.h

855

#define XMT_ACTIVEDSCR __BITS(11,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

857

#define RCVCTL_PREFETCH_THRESH __BITS(25,24)

sys/arch/arm/broadcom/bcm53xx_reg.h

858

#define RCVCTL_PREFETCH_CTL __BITS(23,21)

sys/arch/arm/broadcom/bcm53xx_reg.h

859

#define RCVCTL_BURSTLEN __BITS(20,18)

sys/arch/arm/broadcom/bcm53xx_reg.h

860

#define RCVCTL_ADDREXT __BITS(17,16)

sys/arch/arm/broadcom/bcm53xx_reg.h

865

#define RCVCTL_RCVOFFSET __BITS(7,1)

sys/arch/arm/broadcom/bcm53xx_reg.h

868

#define RCVPTR __BITS(11,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

872

#define RCVSTATE __BITS(31,28)

sys/arch/arm/broadcom/bcm53xx_reg.h

878

#define RCV_CURRDSCR __BITS(11,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

880

#define RCV_ACTIVEDSCR __BITS(11,4)

sys/arch/arm/broadcom/bcm53xx_reg.h

912

#define ETH_SPEED __BITS(3,2)

sys/arch/arm/cortex/a9tmr_reg.h

63

#define TMR_CTL_PRESCALER __BITS(15,8)

sys/arch/arm/cortex/gic.c

455

uint32_t old_cfg = (cfg >> twopair_shift) & __BITS(1, 0);

sys/arch/arm/cortex/gic.c

457

new_cfg &= ~(__BITS(1, 0) << twopair_shift);

sys/arch/arm/cortex/gic_reg.h

101

#define GICC_IAR_CPUID __BITS(12,10)

sys/arch/arm/cortex/gic_reg.h

102

#define GICC_IAR_IRQ __BITS(9,0)

sys/arch/arm/cortex/gic_reg.h

106

#define GICC_EOIR_CPUID __BITS(12,10)

sys/arch/arm/cortex/gic_reg.h

107

#define GICC_EOIR_InterruptID __BITS(9,0)

sys/arch/arm/cortex/gic_reg.h

109

#define GICC_HPPIR_CPUID __BITS(12,10)

sys/arch/arm/cortex/gic_reg.h

110

#define GICC_HPPIR_PendIntID __BITS(9,0)

sys/arch/arm/cortex/gic_reg.h

112

#define GICC_IIDR_ProductID __BITS(31,20)

sys/arch/arm/cortex/gic_reg.h

113

#define GICC_IIDR_ArchVersion __BITS(19,16)

sys/arch/arm/cortex/gic_reg.h

114

#define GICC_IIDR_Revision __BITS(15,12)

sys/arch/arm/cortex/gic_reg.h

115

#define GICC_IIDR_Implementer __BITS(11,0)

sys/arch/arm/cortex/gic_reg.h

117

#define GICC_DIR_CPUID __BITS(12,10)

sys/arch/arm/cortex/gic_reg.h

118

#define GICC_DIR_InterruptID __BITS(9,0)

sys/arch/arm/cortex/gic_reg.h

153

#define GICD_TYPER_IDbits __BITS(23,19) // GICv3

sys/arch/arm/cortex/gic_reg.h

157

#define GICD_TYPER_LSPI __BITS(15,11)

sys/arch/arm/cortex/gic_reg.h

159

#define GICD_TYPER_CPUNumber __BITS(7,5)

sys/arch/arm/cortex/gic_reg.h

160

#define GICD_TYPER_ITLinesNumber __BITS(4,0) // 32*(N+1)

sys/arch/arm/cortex/gic_reg.h

163

#define GICD_IIDR_ProductID __BITS(31,24)

sys/arch/arm/cortex/gic_reg.h

164

#define GICD_IIDR_Variant __BITS(19,16)

sys/arch/arm/cortex/gic_reg.h

165

#define GICD_IIDR_Revision __BITS(15,12)

sys/arch/arm/cortex/gic_reg.h

166

#define GICD_IIDR_Implementer __BITS(11,0)

sys/arch/arm/cortex/gic_reg.h

171

#define GICD_IPRIORITYR_Byte3 __BITS(31,24)

sys/arch/arm/cortex/gic_reg.h

172

#define GICD_IPRIORITYR_Byte1 __BITS(23,16)

sys/arch/arm/cortex/gic_reg.h

173

#define GICD_IPRIORITYR_Byte2 __BITS(15,8)

sys/arch/arm/cortex/gic_reg.h

174

#define GICD_IPRIORITYR_Byte0 __BITS(7,0)

sys/arch/arm/cortex/gic_reg.h

179

#define GICD_ITARGETSR_Byte3 __BITS(31,24)

sys/arch/arm/cortex/gic_reg.h

180

#define GICD_ITARGETSR_Byte1 __BITS(23,16)

sys/arch/arm/cortex/gic_reg.h

181

#define GICD_ITARGETSR_Byte2 __BITS(15,8)

sys/arch/arm/cortex/gic_reg.h

182

#define GICD_ITARGETSR_Byte0 __BITS(7,0)

sys/arch/arm/cortex/gic_reg.h

184

#define GICD_SGIR_TargetListFilter __BITS(25,24)

sys/arch/arm/cortex/gic_reg.h

188

#define GICD_SGIR_TargetList __BITS(23,16)

sys/arch/arm/cortex/gic_reg.h

190

#define GICD_SGIR_SGIINTID __BITS(3,0)

sys/arch/arm/cortex/gic_reg.h

192

#define GICD_IROUTER_Aff3 __BITS(39,32)

sys/arch/arm/cortex/gic_reg.h

194

#define GICD_IROUTER_Aff2 __BITS(23,16)

sys/arch/arm/cortex/gic_reg.h

195

#define GICD_IROUTER_Aff1 __BITS(15,8)

sys/arch/arm/cortex/gic_reg.h

196

#define GICD_IROUTER_Aff0 __BITS(7,0)

sys/arch/arm/cortex/gic_reg.h

230

#define GICR_TYPER_Affinity_Value __BITS(63,32)

sys/arch/arm/cortex/gic_reg.h

231

#define GICR_TYPER_Affinity_Value_Aff3 __BITS(63,56)

sys/arch/arm/cortex/gic_reg.h

232

#define GICR_TYPER_Affinity_Value_Aff2 __BITS(55,48)

sys/arch/arm/cortex/gic_reg.h

233

#define GICR_TYPER_Affinity_Value_Aff1 __BITS(47,40)

sys/arch/arm/cortex/gic_reg.h

234

#define GICR_TYPER_Affinity_Value_Aff0 __BITS(39,32)

sys/arch/arm/cortex/gic_reg.h

235

#define GICR_TYPER_CommonLPIAff __BITS(25,24)

sys/arch/arm/cortex/gic_reg.h

236

#define GICR_TYPER_Processor_Number __BITS(23,8)

sys/arch/arm/cortex/gic_reg.h

246

#define GICR_PROPBASER_OuterCache __BITS(58,56)

sys/arch/arm/cortex/gic_reg.h

247

#define GICR_PROPBASER_Physical_Address __BITS(51,12)

sys/arch/arm/cortex/gic_reg.h

248

#define GICR_PROPBASER_Shareability __BITS(11,10)

sys/arch/arm/cortex/gic_reg.h

249

#define GICR_PROPBASER_InnerCache __BITS(9,7)

sys/arch/arm/cortex/gic_reg.h

250

#define GICR_PROPBASER_IDbits __BITS(4,0)

sys/arch/arm/cortex/gic_reg.h

253

#define GICR_PENDBASER_OuterCache __BITS(58,56)

sys/arch/arm/cortex/gic_reg.h

254

#define GICR_PENDBASER_Physical_Address __BITS(51,16)

sys/arch/arm/cortex/gic_reg.h

255

#define GICR_PENDBASER_Shareability __BITS(11,10)

sys/arch/arm/cortex/gic_reg.h

256

#define GICR_PENDBASER_InnerCache __BITS(9,7)

sys/arch/arm/cortex/gic_reg.h

277

#define GIC_LPICONF_Priority __BITS(7,2)

sys/arch/arm/cortex/gic_reg.h

317

#define GIC_MSI_TYPER_BASE __BITS(25,16) // Starting SPI of MSIs

sys/arch/arm/cortex/gic_reg.h

318

#define GIC_MSI_TYPER_NUMBER __BITS(9,0) // Count of MSIs

sys/arch/arm/cortex/gic_reg.h

335

#define GITS_CTLR_ITS_Number __BITS(7,4)

sys/arch/arm/cortex/gic_reg.h

339

#define GITS_IIDR_ProductID __BITS(31,24)

sys/arch/arm/cortex/gic_reg.h

340

#define GITS_IIDR_Variant __BITS(19,16)

sys/arch/arm/cortex/gic_reg.h

341

#define GITS_IIDR_Revision __BITS(15,12)

sys/arch/arm/cortex/gic_reg.h

342

#define GITS_IIDR_Implementor __BITS(11,0)

sys/arch/arm/cortex/gic_reg.h

346

#define GITS_TYPER_CIDbits __BITS(35,32)

sys/arch/arm/cortex/gic_reg.h

347

#define GITS_TYPER_HCC __BITS(31,24)

sys/arch/arm/cortex/gic_reg.h

350

#define GITS_TYPER_Devbits __BITS(17,13)

sys/arch/arm/cortex/gic_reg.h

351

#define GITS_TYPER_ID_bits __BITS(12,8)

sys/arch/arm/cortex/gic_reg.h

352

#define GITS_TYPER_ITT_entry_size __BITS(7,4)

sys/arch/arm/cortex/gic_reg.h

358

#define GITS_CBASER_InnerCache __BITS(61,59)

sys/arch/arm/cortex/gic_reg.h

359

#define GITS_CBASER_OuterCache __BITS(55,53)

sys/arch/arm/cortex/gic_reg.h

360

#define GITS_CBASER_Physical_Address __BITS(51,12)

sys/arch/arm/cortex/gic_reg.h

361

#define GITS_CBASER_Shareability __BITS(11,10)

sys/arch/arm/cortex/gic_reg.h

362

#define GITS_CBASER_Size __BITS(7,0)

sys/arch/arm/cortex/gic_reg.h

364

#define GITS_CWRITER_Offset __BITS(19,5)

sys/arch/arm/cortex/gic_reg.h

367

#define GITS_CREADR_Offset __BITS(19,5)

sys/arch/arm/cortex/gic_reg.h

372

#define GITS_BASER_InnerCache __BITS(61,59)

sys/arch/arm/cortex/gic_reg.h

373

#define GITS_BASER_Type __BITS(58,56)

sys/arch/arm/cortex/gic_reg.h

374

#define GITS_BASER_OuterCache __BITS(55,53)

sys/arch/arm/cortex/gic_reg.h

375

#define GITS_BASER_Entry_Size __BITS(52,48)

sys/arch/arm/cortex/gic_reg.h

376

#define GITS_BASER_Physical_Address __BITS(47,12)

sys/arch/arm/cortex/gic_reg.h

377

#define GITS_BASER_Shareability __BITS(11,10)

sys/arch/arm/cortex/gic_reg.h

378

#define GITS_BASER_Page_Size __BITS(9,8)

sys/arch/arm/cortex/gic_reg.h

379

#define GITS_BASER_Size __BITS(7,0)

sys/arch/arm/cortex/gic_reg.h

91

#define GICC_PMR_PRIORITY __BITS(7,0)

sys/arch/arm/cortex/gtmr.c

196

bits = val & __BITS(9,0);

sys/arch/arm/cortex/gtmr.c

197

} while (bits == 0 || bits == __BITS(9,0));

sys/arch/arm/cortex/pl310_reg.h

40

#define CACHE_ID_IMPL __BITS(31,24)

sys/arch/arm/cortex/pl310_reg.h

41

#define CACHE_ID_ID __BITS(15,10)

sys/arch/arm/cortex/pl310_reg.h

42

#define CACHE_ID_PART __BITS(9,6)

sys/arch/arm/cortex/pl310_reg.h

44

#define CACHE_ID_REV __BITS(5,0)

sys/arch/arm/cortex/pl310_reg.h

50

#define CACHE_TYPE_CTYPE __BITS(28,25)

sys/arch/arm/cortex/pl310_reg.h

52

#define CACHE_TYPE_DSIZE __BITS(23,12)

sys/arch/arm/cortex/pl310_reg.h

53

#define CACHE_TYPE_ISIZE __BITS(11,0)

sys/arch/arm/cortex/pl310_reg.h

54

#define CACHE_TYPE_xWAYSIZE __BITS(10,8)

sys/arch/arm/cortex/pl310_reg.h

56

#define CACHE_TYPE_xLINESIZE __BITS(5,0)

sys/arch/arm/cortex/pl310_reg.h

68

#define AUXCTL_FORCE_WA __BITS(24,23)

sys/arch/arm/cortex/pl310_reg.h

76

#define AUXCTL_WAY_SIZE __BITS(19,17)

sys/arch/arm/cortex/scu_reg.h

61

#define SCU_CFG_TAG_RAM_SIZE_CPUn(n) __BITS(9+2*(n),8+2*(n))

sys/arch/arm/cortex/scu_reg.h

62

#define SCU_CFG_TAG_RAM_SIZE_CPU3 __BITS(15,14)

sys/arch/arm/cortex/scu_reg.h

63

#define SCU_CFG_TAG_RAM_SIZE_CPU2 __BITS(13,12)

sys/arch/arm/cortex/scu_reg.h

64

#define SCU_CFG_TAG_RAM_SIZE_CPU1 __BITS(11,10)

sys/arch/arm/cortex/scu_reg.h

65

#define SCU_CFG_TAG_RAM_SIZE_CPU0 __BITS(9,8)

sys/arch/arm/cortex/scu_reg.h

74

#define SCU_CFG_CPUMAX __BITS(0,1) // # of CPU - 1

sys/arch/arm/fdt/pcihost_fdtvar.h

33

#define PHYS_HI_SPACE __BITS(25,24)

sys/arch/arm/fdt/pcihost_fdtvar.h

38

#define PHYS_HI_BUS __BITS(23,16)

sys/arch/arm/fdt/pcihost_fdtvar.h

39

#define PHYS_HI_DEVICE __BITS(15,11)

sys/arch/arm/fdt/pcihost_fdtvar.h

40

#define PHYS_HI_FUNCTION __BITS(10,8)

sys/arch/arm/fdt/pcihost_fdtvar.h

41

#define PHYS_HI_REGISTER __BITS(7,0)

sys/arch/arm/fdt/plfb_fdt.c

54

#define LCDTIMING0_HBP __BITS(31,24)

sys/arch/arm/fdt/plfb_fdt.c

55

#define LCDTIMING0_HFP __BITS(23,16)

sys/arch/arm/fdt/plfb_fdt.c

56

#define LCDTIMING0_HSW __BITS(15,8)

sys/arch/arm/fdt/plfb_fdt.c

57

#define LCDTIMING0_PPL __BITS(7,2)

sys/arch/arm/fdt/plfb_fdt.c

59

#define LCDTIMING1_VBP __BITS(31,24)

sys/arch/arm/fdt/plfb_fdt.c

60

#define LCDTIMING1_VFP __BITS(23,16)

sys/arch/arm/fdt/plfb_fdt.c

61

#define LCDTIMING1_VSW __BITS(15,10)

sys/arch/arm/fdt/plfb_fdt.c

62

#define LCDTIMING1_LPP __BITS(9,0)

sys/arch/arm/fdt/plfb_fdt.c

68

#define LCDCONTROL_BPP __BITS(3,1)

sys/arch/arm/gemini/gemini_gmacreg.h

205

#define INT4_GMAC0 __BITS(16,23)

sys/arch/arm/gemini/gemini_gmacreg.h

206

#define INT4_GMAC1 (__BITS(24,31)|INT4_HW_FREEQ_EMPTY)

sys/arch/arm/gemini/gemini_gmacreg.h

209

#define QFE_TOEQ_THRESHOLD_MASK __BITS(24,31)

sys/arch/arm/gemini/gemini_gmacreg.h

212

#define QFE_INTQ_THRESHOLD_MASK __BITS(16,23)

sys/arch/arm/gemini/gemini_gmacreg.h

215

#define QFE_HWFQ_THRESHOLD_MASK __BITS(8,15)

sys/arch/arm/gemini/gemini_gmacreg.h

218

#define QFE_SWFQ_THRESHOLD_MASK __BITS(0,7)

sys/arch/arm/gemini/gemini_gmacreg.h

249

#define DMAVR_EXTRABYTES_MASK __BITS(16,17)

sys/arch/arm/gemini/gemini_gmacreg.h

252

#define DMAVR_RXBURSTSIZE_MASK __BITS(10,11)

sys/arch/arm/gemini/gemini_gmacreg.h

255

#define DMAVR_RXBUSWIDTH_MASK __BITS(8,9)

sys/arch/arm/gemini/gemini_gmacreg.h

258

#define DMAVR_TXBURSTSIZE_MASK __BITS(2,3)

sys/arch/arm/gemini/gemini_gmacreg.h

261

#define DMAVR_TXBUSWIDTH_MASK __BITS(0,1)

sys/arch/arm/gemini/gemini_gmacreg.h

316

#define HRT_AHB_TQDV_START __BITS(20,24)

sys/arch/arm/gemini/gemini_gmacreg.h

317

#define HRT_AHB_RX_PREREQ __BITS(15,19)

sys/arch/arm/gemini/gemini_gmacreg.h

318

#define HRT_AHB_TX_WEIGHT __BITS(10,14)

sys/arch/arm/gemini/gemini_gmacreg.h

319

#define HRT_AHB_RX_WEIGHT __BITS(5,9)

sys/arch/arm/gemini/gemini_gmacreg.h

320

#define HRT_AHB_HASH_WEIGHT __BITS(0,4)

sys/arch/arm/gemini/gemini_gmacreg.h

360

#define CONFIG0_BACKOFF_MASK __BITS(11,12)

sys/arch/arm/gemini/gemini_gmacreg.h

367

#define CONFIG0_MAXLEN_MASK __BITS(8,10)

sys/arch/arm/gemini/gemini_gmacreg.h

375

#define CONFIG0_IFG_ADJUST_MASK __BITS(4,7)

sys/arch/arm/gemini/gemini_gmacreg.h

384

#define STATUS_PHYMODE_MASK __BITS(5,6)

sys/arch/arm/gemini/gemini_gmacreg.h

390

#define STATUS_SPEED_MASK __BITS(1,2)

sys/arch/arm/gemini/gemini_gmacreg.h

399

#define DESC0_STATUS __BITS(22, 28)

sys/arch/arm/gemini/gemini_gmacreg.h

400

#define DESC0_DESC_CNT __BITS(16, 21)

sys/arch/arm/gemini/gemini_gmacreg.h

401

#define DESC0_BUF_SIZE __BITS(0, 15)

sys/arch/arm/gemini/gemini_gmacreg.h

429

#define DESC1_RX_SWID __BITS(16, 31)

sys/arch/arm/gemini/gemini_gmacreg.h

430

#define DESC1_TX_FLAG __BITS(16, 31)

sys/arch/arm/gemini/gemini_gmacreg.h

431

#define DESC1_BUFLEN __BITS(0, 15)

sys/arch/arm/gemini/gemini_gmacreg.h

433

#define DESC1_TX_IPLEN_FIXED __BITS(22) /* IPLEN is fixed */

sys/arch/arm/gemini/gemini_gmacreg.h

434

#define DESC1_TX_TSS_BYPASS __BITS(21) /* TSS Bypass */

sys/arch/arm/gemini/gemini_gmacreg.h

435

#define DESC1_TX_UDP_CSUM_EN __BITS(20) /* Calc UDP CSUM */

sys/arch/arm/gemini/gemini_gmacreg.h

436

#define DESC1_TX_TCP_CSUM_EN __BITS(19) /* Calc TCP CSUM */

sys/arch/arm/gemini/gemini_gmacreg.h

437

#define DESC1_TX_IPV6_EN __BITS(18) /* Calc UDP CSUM */

sys/arch/arm/gemini/gemini_gmacreg.h

438

#define DESC1_TX_IPV4_CSUM_EN __BITS(17) /* Calc IP HDR CSUM */

sys/arch/arm/gemini/gemini_gmacreg.h

439

#define DESC1_TX_SEG_OFFLOAD_EN __BITS(16) /* TSS Bypass */

sys/arch/arm/gemini/gemini_gmacreg.h

441

#define DESC2_BUFADDR __BITS(2,31)

sys/arch/arm/gemini/gemini_gmacreg.h

452

#define DESC3_RX_L3_OFF __BITS(16, 32)

sys/arch/arm/gemini/gemini_gmacreg.h

453

#define DESC3_RX_L4_OFF __BITS(8, 15)

sys/arch/arm/gemini/gemini_gmacreg.h

454

#define DESC3_RX_L7_OFF __BITS(0, 7)

sys/arch/arm/gemini/gemini_gmacreg.h

456

#define DESC3_TX_TSS_MTU __BITS(0, 10)

sys/arch/arm/gemini/gemini_gmacreg.h

71

#define INT0_SWTXQ1_FIN __BITS(18,23)

sys/arch/arm/gemini/gemini_gmacreg.h

79

#define INT0_SWTXQ0_FIN __BITS(12,17)

sys/arch/arm/gemini/gemini_gmacreg.h

80

#define INT0_SWTXQ_FIN __BITS(12,23)

sys/arch/arm/gemini/gemini_gmacreg.h

88

#define INT0_SWTXQ1_EOF __BITS(6,11)

sys/arch/arm/gemini/gemini_gmacreg.h

96

#define INT0_SWTXQ0_EOF __BITS(0,5)

sys/arch/arm/gemini/gemini_gmacreg.h

97

#define INT0_SWTXQ_EOF __BITS(0,11)

sys/arch/arm/gemini/gemini_lpc.c

24

# define CSCV_VERSION __BITS(3,0);

sys/arch/arm/gemini/gemini_reg.h

104

#define WDT_WDSTATUS_Resv __BITS(31,1)

sys/arch/arm/gemini/gemini_reg.h

107

#define WDT_WDCLEAR_Resv __BITS(31,1)

sys/arch/arm/gemini/gemini_reg.h

128

#define TIMER_TMCR_Resv __BITS(31,12)

sys/arch/arm/gemini/gemini_reg.h

139

#define TIMER_INTRSTATE_Resv __BITS(31,9)

sys/arch/arm/gemini/gemini_reg.h

144

#define TIMER_INTRMASK_Resv __BITS(31,9)

sys/arch/arm/gemini/gemini_reg.h

176

#define ICU_INPUT_NUM_RESV __BITS(31,16)

sys/arch/arm/gemini/gemini_reg.h

177

#define ICU_INPUT_NUM_IRQ __BITS(15,8)

sys/arch/arm/gemini/gemini_reg.h

178

#define ICU_INPUT_NUM_FIQ __BITS(7,0)

sys/arch/arm/gemini/gemini_reg.h

187

# define LPCHC_ID_DEVICE __BITS(31,8) /* Device ID */

sys/arch/arm/gemini/gemini_reg.h

188

# define LPCHC_ID_REV __BITS(7,0) /* Revision */

sys/arch/arm/gemini/gemini_reg.h

192

# define LPCHC_CSR_RESa __BITS(31,24)

sys/arch/arm/gemini/gemini_reg.h

195

# define LPCHC_CSR_RESb __BITS(21,8)

sys/arch/arm/gemini/gemini_reg.h

198

# define LPCHC_CSR_RESc __BITS(5,1)

sys/arch/arm/gemini/gemini_reg.h

201

# define LPCHC_IRQCTL_RESV __BITS(31,8)

sys/arch/arm/gemini/gemini_reg.h

204

# define LPCHC_IRQCTL_SIRQFN __BITS(5,2) /* Serial IRQ Frame Number */

sys/arch/arm/gemini/gemini_reg.h

205

# define LPCHC_IRQCTL_SIRQFW __BITS(1,0) /* Serial IRQ Frame Width */

sys/arch/arm/gemini/gemini_reg.h

211

# define LPCHC_SERIRQSTS_RESV __BITS(31,17)

sys/arch/arm/gemini/gemini_reg.h

213

# define LPCHC_SERIRQTYP_RESV __BITS(31,17)

sys/arch/arm/gemini/gemini_reg.h

217

# define LPCHC_SERIRQPOLARITY_RESV __BITS(31,17)

sys/arch/arm/gemini/gemini_reg.h

254

#define GPIO_BOUNCESCALE_RESV __BITS(31,16)

sys/arch/arm/gemini/gemini_reg.h

255

#define GPIO_BOUNCESCALE_VAL __BITS(15,0) /* NOTE:

sys/arch/arm/gemini/gemini_reg.h

272

#define PCI_CFG_CMD_RESa __BITS(30,24)

sys/arch/arm/gemini/gemini_reg.h

273

#define PCI_CFG_CMD_BUSNO __BITS(23,16) /* Bus Number */

sys/arch/arm/gemini/gemini_reg.h

275

#define PCI_CFG_CMD_DEVNO __BITS(15,11) /* Device Number */

sys/arch/arm/gemini/gemini_reg.h

277

#define PCI_CFG_CMD_FUNCNO __BITS(10,8) /* Function Number */

sys/arch/arm/gemini/gemini_reg.h

279

#define PCI_CFG_CMD_REGNO __BITS(7,2) /* Register Number */

sys/arch/arm/gemini/gemini_reg.h

281

#define PCI_CFG_CMD_RESb __BITS(1,0)

sys/arch/arm/gemini/gemini_reg.h

293

#define PCI_CFG_REG_CTL2_INTSTS __BITS(31,28)

sys/arch/arm/gemini/gemini_reg.h

298

#define PCI_CFG_REG_CTL2_INTMASK __BITS(27,16)

sys/arch/arm/gemini/gemini_reg.h

305

#define CFG_REG_CTL2_INTMASK_INT_ABCD __BITS(16+9,16+6)

sys/arch/arm/gemini/gemini_reg.h

313

#define PCI_CFG_REG_CTL2_MSTPRI __BITS(14,8)

sys/arch/arm/gemini/gemini_reg.h

315

#define PCI_CFG_REG_CTL2_RESb __BITS(7,4)

sys/arch/arm/gemini/gemini_reg.h

316

#define PCI_CFG_REG_CTL2_TRDYW __BITS(3,0)

sys/arch/arm/gemini/gemini_reg.h

322

#define PCI_CFG_REG_MEM_BASE_MASK __BITS(31,20)

sys/arch/arm/gemini/gemini_reg.h

324

#define PCI_CFG_REG_MEM_SIZE_MASK __BITS(19,16)

sys/arch/arm/gemini/gemini_reg.h

337

#define PCI_CFG_REG_MEM_RESV __BITS(19,16)

sys/arch/arm/gemini/gemini_reg.h

390

#define DRAMC_RMCR_RESa __BITS(31,29)

sys/arch/arm/gemini/gemini_reg.h

391

#define DRAMC_RMCR_RMBAR __BITS(28,20) /* Remap Base Address */

sys/arch/arm/gemini/gemini_reg.h

393

#define DRAMC_RMCR_RESb __BITS(19,9)

sys/arch/arm/gemini/gemini_reg.h

394

#define DRAMC_RMCR_RMSZR __BITS(8,0) /* Remap Size Address */

sys/arch/arm/gemini/gemini_reg.h

71

#define GLOBAL_ID_CHIP_ID __BITS(31,8)

sys/arch/arm/gemini/gemini_reg.h

72

#define GLOBAL_ID_CHIP_REV __BITS(7,0)

sys/arch/arm/gemini/gemini_reg.h

91

#define WDT_WDRESTART_Resv __BITS(31,16)

sys/arch/arm/gemini/gemini_reg.h

92

#define WDT_WDRESTART_RST __BITS(15,0)

sys/arch/arm/gemini/gemini_reg.h

95

#define WDT_WDCR_Resv __BITS(31,5)

sys/arch/arm/imx/if_enet.c

744

hashidx = __SHIFTOUT(crc, __BITS(30,26));

sys/arch/arm/imx/if_enetreg.h

108

# define ENET_RCR_MAX_FL(n) __SHIFTIN(n, __BITS(29, 16))

sys/arch/arm/imx/if_enetreg.h

143

# define ENET_TFWR_FIFO(n) __SHIFTIN(((n) / 64), __BITS(5, 0))

sys/arch/arm/imx/if_enetreg.h

319

#define RXFLAGS2_VPCP __BITS(15, 31) /* VLAN prio pts (imx7) */

sys/arch/arm/imx/if_enetreg.h

92

# define ENET_MMFR_PHY_ADDR(phy) __SHIFTIN(phy, __BITS(27, 23))

sys/arch/arm/imx/if_enetreg.h

93

# define ENET_MMFR_PHY_REG(reg) __SHIFTIN(reg, __BITS(22, 18))

sys/arch/arm/imx/if_enetreg.h

98

# define ENET_MSCR_MII_SPEED __BITS(6, 1)

sys/arch/arm/imx/imx23_apbdma.c

49

#define APBDMA_CMD_XFER_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_apbdma.c

50

#define APBDMA_CMD_CMDPIOWORDS __BITS(15, 12)

sys/arch/arm/imx/imx23_apbdma.c

51

#define APBDMA_CMD_RESERVED __BITS(11, 9)

sys/arch/arm/imx/imx23_apbdma.c

59

#define APBDMA_CMD_COMMAND __BITS(1, 0)

sys/arch/arm/imx/imx23_apbdma.h

61

#define NEXTCMDADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbdma.h

66

#define XFER_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_apbdma.h

67

#define CMDPIOWORDS __BITS(15, 12)

sys/arch/arm/imx/imx23_apbdma.h

68

#define CMDWORD1_RSVD0 __BITS(11, 8)

sys/arch/arm/imx/imx23_apbdma.h

75

#define COMMAND __BITS(1, 0)

sys/arch/arm/imx/imx23_apbdma.h

80

#define BUF_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbdma.h

85

#define PIOWORD __BITS(31, 0)

sys/arch/arm/imx/imx23_apbdmareg.h

51

#define HW_APB_CTRL0_RSVD0 __BITS(29, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

101

#define HW_APBH_CTRL2_RSVD0 __BITS(15, 8)

sys/arch/arm/imx/imx23_apbhdmareg.h

116

#define HW_APBH_DEVSEL_CH7 __BITS(31, 28)

sys/arch/arm/imx/imx23_apbhdmareg.h

117

#define HW_APBH_DEVSEL_CH6 __BITS(27, 24)

sys/arch/arm/imx/imx23_apbhdmareg.h

118

#define HW_APBH_DEVSEL_CH5 __BITS(23, 20)

sys/arch/arm/imx/imx23_apbhdmareg.h

119

#define HW_APBH_DEVSEL_CH4 __BITS(19, 16)

sys/arch/arm/imx/imx23_apbhdmareg.h

120

#define HW_APBH_DEVSEL_CH3 __BITS(15, 12)

sys/arch/arm/imx/imx23_apbhdmareg.h

121

#define HW_APBH_DEVSEL_CH2 __BITS(11, 8)

sys/arch/arm/imx/imx23_apbhdmareg.h

122

#define HW_APBH_DEVSEL_CH1 __BITS(7, 4)

sys/arch/arm/imx/imx23_apbhdmareg.h

123

#define HW_APBH_DEVSEL_CH0 __BITS(3, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

130

#define HW_APBH_CH0_CURCMDAR_CMD_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

137

#define HW_APBH_CH0_NXTCMDAR_CMD_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

144

#define HW_APBH_CH0_SEMA_RSVD2 __BITS(31, 24)

sys/arch/arm/imx/imx23_apbhdmareg.h

145

#define HW_APBH_CH0_SEMA_PHORE __BITS(23, 16)

sys/arch/arm/imx/imx23_apbhdmareg.h

146

#define HW_APBH_CH0_SEMA_RSVD1 __BITS(15, 8)

sys/arch/arm/imx/imx23_apbhdmareg.h

147

#define HW_APBH_CH0_SEMA_INCREMENT_SEMA __BITS(7, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

154

#define HW_APBH_CH1_CURCMDAR_CMD_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

161

#define HW_APBH_CH1_NXTCMDAR_CMD_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

168

#define HW_APBH_CH1_CMD_XFER_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_apbhdmareg.h

169

#define HW_APBH_CH1_CMD_CMDWORDS __BITS(15, 12)

sys/arch/arm/imx/imx23_apbhdmareg.h

170

#define HW_APBH_CH1_CMD_RSVD1 __BITS(11, 9)

sys/arch/arm/imx/imx23_apbhdmareg.h

178

#define HW_APBH_CH1_CMD_COMMAND __BITS(1, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

185

#define HW_APBH_CH1_BAR_ADDRESS __BITS(31, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

192

#define HW_APBH_CH1_SEMA_RSVD2 __BITS(31, 24)

sys/arch/arm/imx/imx23_apbhdmareg.h

193

#define HW_APBH_CH1_SEMA_PHORE __BITS(23, 16)

sys/arch/arm/imx/imx23_apbhdmareg.h

194

#define HW_APBH_CH1_SEMA_RSVD1 __BITS(15, 8)

sys/arch/arm/imx/imx23_apbhdmareg.h

195

#define HW_APBH_CH1_SEMA_INCREMENT_SEMA __BITS(7, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

214

#define HW_APBH_CH1_DEBUG1_RSVD1 __BITS(19, 5)

sys/arch/arm/imx/imx23_apbhdmareg.h

215

#define HW_APBH_CH1_DEBUG1_STATEMACHINE __BITS(4, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

222

#define HW_APBH_CH1_DEBUG2_APB_BYTES __BITS(31, 16)

sys/arch/arm/imx/imx23_apbhdmareg.h

223

#define HW_APBH_CH1_DEBUG2_AHB_BYTES __BITS(15, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

52

#define HW_APBH_CTRL0_RSVD0 __BITS(27, 24)

sys/arch/arm/imx/imx23_apbhdmareg.h

53

#define HW_APBH_CTRL0_RESET_CHANNEL __BITS(23, 16)

sys/arch/arm/imx/imx23_apbhdmareg.h

54

#define HW_APBH_CTRL0_CLKGATE_CHANNEL __BITS(15, 8)

sys/arch/arm/imx/imx23_apbhdmareg.h

55

#define HW_APBH_CTRL0_FREEZE_CHANNEL __BITS(7, 0)

sys/arch/arm/imx/imx23_apbhdmareg.h

65

#define HW_APBH_CTRL1_RSVD1 __BITS(31, 24)

sys/arch/arm/imx/imx23_apbhdmareg.h

74

#define HW_APBH_CTRL1_RSVD0 __BITS(15, 8)

sys/arch/arm/imx/imx23_apbhdmareg.h

92

#define HW_APBH_CTRL2_RSVD1 __BITS(31, 24)

sys/arch/arm/imx/imx23_apbxdmareg.h

45

#define HW_APBX_CH0_CURCMDAR_CMD_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbxdmareg.h

52

#define HW_APBX_CH0_NXTCMDAR_CMD_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_apbxdmareg.h

59

#define HW_APBX_CH0_SEMA_RSVD2 __BITS(31, 24)

sys/arch/arm/imx/imx23_apbxdmareg.h

60

#define HW_APBX_CH0_SEMA_PHORE __BITS(23, 16)

sys/arch/arm/imx/imx23_apbxdmareg.h

61

#define HW_APBX_CH0_SEMA_RSVD1 __BITS(15, 8)

sys/arch/arm/imx/imx23_apbxdmareg.h

62

#define HW_APBX_CH0_SEMA_INCREMENT_SEMA __BITS(7, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

111

#define HW_CLKCTRL_HBUS_SLOW_DIV __BITS(18, 16)

sys/arch/arm/imx/imx23_clkctrlreg.h

112

#define HW_CLKCTRL_HBUS_RSRVD1 __BITS(15, 6)

sys/arch/arm/imx/imx23_clkctrlreg.h

114

#define HW_CLKCTRL_HBUS_DIV __BITS(4, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

122

#define HW_CLKCTRL_XBUS_RSVD2 __BITS(30, 11)

sys/arch/arm/imx/imx23_clkctrlreg.h

124

#define HW_CLKCTRL_XBUS_DIV __BITS(9, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

140

#define HW_CLKCTRL_XTAL_RSRVD1 __BITS(25, 2)

sys/arch/arm/imx/imx23_clkctrlreg.h

141

#define HW_CLKCTRL_XTAL_DIV_UART __BITS(1, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

151

#define HW_CLKCTRL_PIX_RSRVD1 __BITS(28, 13)

sys/arch/arm/imx/imx23_clkctrlreg.h

153

#define HW_CLKCTRL_PIX_DIV __BITS(11, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

163

#define HW_CLKCTRL_SSP_RSVD2 __BITS(28, 10)

sys/arch/arm/imx/imx23_clkctrlreg.h

165

#define HW_CLKCTRL_SSP_DIV __BITS(8, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

175

#define HW_CLKCTRL_GPMI_RSVD2 __BITS(28, 11)

sys/arch/arm/imx/imx23_clkctrlreg.h

185

#define HW_CLKCTRL_SPDIF_RSRVD __BITS(30, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

198

#define HW_CLKCTRL_EMI_RSVD5 __BITS(25, 18)

sys/arch/arm/imx/imx23_clkctrlreg.h

201

#define HW_CLKCTRL_EMI_RSVD2 __BITS(15, 12)

sys/arch/arm/imx/imx23_clkctrlreg.h

202

#define HW_CLKCTRL_EMI_DIV_XTAL __BITS(11, 8)

sys/arch/arm/imx/imx23_clkctrlreg.h

203

#define HW_CLKCTRL_EMI_RSVD1 __BITS(7, 6)

sys/arch/arm/imx/imx23_clkctrlreg.h

204

#define HW_CLKCTRL_EMI_DIV_EMI __BITS(5, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

214

#define HW_CLKCTRL_SAIF_RSRVD1 __BITS(28, 17)

sys/arch/arm/imx/imx23_clkctrlreg.h

216

#define HW_CLKCTRL_SAIF_DIV __BITS(15, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

225

#define HW_CLKCTRL_TV_RSRVD __BITS(29, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

235

#define HW_CLKCTRL_ETM_RSRVD1 __BITS(28, 7)

sys/arch/arm/imx/imx23_clkctrlreg.h

249

#define HW_CLKCTRL_FRAC_IOFRAC __BITS(29, 24)

sys/arch/arm/imx/imx23_clkctrlreg.h

252

#define HW_CLKCTRL_FRAC_PIXFRAC __BITS(21, 16)

sys/arch/arm/imx/imx23_clkctrlreg.h

255

#define HW_CLKCTRL_FRAC_EMIFRAC __BITS(13, 8)

sys/arch/arm/imx/imx23_clkctrlreg.h

258

#define HW_CLKCTRL_FRAC_CPUFRAC __BITS(5, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

270

#define HW_CLKCTRL_FRAC1_RSRVD1 __BITS(29, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

280

#define HW_CLKCTRL_CLKSEQ_RSRVD1 __BITS(31, 9)

sys/arch/arm/imx/imx23_clkctrlreg.h

296

#define HW_CLKCTRL_RESET_RSRVD __BITS(31, 2)

sys/arch/arm/imx/imx23_clkctrlreg.h

305

#define HW_CLKCTRL_STATUS_CPU_LIMIT __BITS(31, 30)

sys/arch/arm/imx/imx23_clkctrlreg.h

306

#define HW_CLKCTRL_STATUS_RSRVD __BITS(29, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

313

#define HW_CLKCTRL_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_clkctrlreg.h

314

#define HW_CLKCTRL_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_clkctrlreg.h

315

#define HW_CLKCTRL_VERSION_STEP __BITS(15, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

48

#define HW_CLKCTRL_PLLCTRL0_RSRVD6 __BITS(31, 30)

sys/arch/arm/imx/imx23_clkctrlreg.h

49

#define HW_CLKCTRL_PLLCTRL0_LFR_SEL __BITS(29, 28)

sys/arch/arm/imx/imx23_clkctrlreg.h

50

#define HW_CLKCTRL_PLLCTRL0_RSRVD5 __BITS(27, 26)

sys/arch/arm/imx/imx23_clkctrlreg.h

51

#define HW_CLKCTRL_PLLCTRL0_CP_SEL __BITS(25, 24)

sys/arch/arm/imx/imx23_clkctrlreg.h

52

#define HW_CLKCTRL_PLLCTRL0_RSRVD4 __BITS(23, 22)

sys/arch/arm/imx/imx23_clkctrlreg.h

53

#define HW_CLKCTRL_PLLCTRL0_DIV_SEL __BITS(21, 20)

sys/arch/arm/imx/imx23_clkctrlreg.h

58

#define HW_CLKCTRL_PLLCTRL0_RSRVD1 __BITS(15, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

67

#define HW_CLKCTRL_PLLCTRL1_RSRVD1 __BITS(29, 16)

sys/arch/arm/imx/imx23_clkctrlreg.h

68

#define HW_CLKCTRL_PLLCTRL1_LOCK_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

78

#define HW_CLKCTRL_CPU_RSVD6 __BITS(31, 30)

sys/arch/arm/imx/imx23_clkctrlreg.h

83

#define HW_CLKCTRL_CPU_DIV_XTAL __BITS(25, 16)

sys/arch/arm/imx/imx23_clkctrlreg.h

84

#define HW_CLKCTRL_CPU_RSVD4 __BITS(15, 13)

sys/arch/arm/imx/imx23_clkctrlreg.h

88

#define HW_CLKCTRL_CPU_RSVD1 __BITS(9, 6)

sys/arch/arm/imx/imx23_clkctrlreg.h

89

#define HW_CLKCTRL_CPU_DIV_CPU __BITS(5, 0)

sys/arch/arm/imx/imx23_clkctrlreg.h

99

#define HW_CLKCTRL_HBUS_RSRVD4 __BITS(31, 30)

sys/arch/arm/imx/imx23_digctlreg.h

110

#define HW_DIGCTL_HCLKCOUNT_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

120

#define HW_DIGCTL_RAMCTRL_RSVD1 __BITS(31, 12)

sys/arch/arm/imx/imx23_digctlreg.h

121

#define HW_DIGCTL_RAMCTRL_SPEED_SELECT __BITS(11, 8)

sys/arch/arm/imx/imx23_digctlreg.h

122

#define HW_DIGCTL_RAMCTRL_RSVD0 __BITS(7, 1)

sys/arch/arm/imx/imx23_digctlreg.h

133

#define HW_DIGCTL_RAMREPAIR_RSVD1 __BITS(31, 16)

sys/arch/arm/imx/imx23_digctlreg.h

134

#define HW_DIGCTL_RAMREPAIR_ADDR __BITS(15, 0)

sys/arch/arm/imx/imx23_digctlreg.h

144

#define HW_DIGCTL_ROMCTRL_RSVD0 __BITS(31, 4)

sys/arch/arm/imx/imx23_digctlreg.h

145

#define HW_DIGCTL_ROMCTRL_RD_MARGIN __BITS(3, 0)

sys/arch/arm/imx/imx23_digctlreg.h

152

#define HW_DIGCTL_WRITEONCE_BITS __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

159

#define HW_DIGCTL_ENTROPY_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

166

#define HW_DIGCTL_ENTROPY_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

176

#define HW_DIGCTL_SJTAGDBG_RSVD2 __BITS(31, 27)

sys/arch/arm/imx/imx23_digctlreg.h

177

#define HW_DIGCTL_SJTAGDBG_SJTAG_STATE __BITS(26, 16)

sys/arch/arm/imx/imx23_digctlreg.h

178

#define HW_DIGCTL_SJTAGDBG_RSVD1 __BITS(15, 11)

sys/arch/arm/imx/imx23_digctlreg.h

182

#define HW_DIGCTL_SJTAGDBG_DELAYED_ACTIVE __BITS(7, 4)

sys/arch/arm/imx/imx23_digctlreg.h

196

#define HW_DIGCTL_MICROSECONDS_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

203

#define HW_DIGCTL_DBGRD_COMPLEMENT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

210

#define HW_DIGCTL_DBG_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

220

#define HW_DIGCTL_OCRAM_BIST_CSR_RSVD1 __BITS(31, 11)

sys/arch/arm/imx/imx23_digctlreg.h

224

#define HW_DIGCTL_OCRAM_BIST_CSR_RSVD0 __BITS(7, 4)

sys/arch/arm/imx/imx23_digctlreg.h

238

#define HW_DIGCTL_OCRAM_STATUS0_FAILDATA00 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

248

#define HW_DIGCTL_OCRAM_STATUS1_FAILDATA01 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

258

#define HW_DIGCTL_OCRAM_STATUS2_FAILDATA10 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

268

#define HW_DIGCTL_OCRAM_STATUS3_FAILDATA20 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

278

#define HW_DIGCTL_OCRAM_STATUS4_FAILDATA20 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

288

#define HW_DIGCTL_OCRAM_STATUS5_FAILDATA21 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

298

#define HW_DIGCTL_OCRAM_STATUS6_FAILDATA30 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

308

#define HW_DIGCTL_OCRAM_STATUS7_FAILDATA31 __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

318

#define HW_DIGCTL_OCRAM_STATUS8_RSVD3 __BITS(31, 29)

sys/arch/arm/imx/imx23_digctlreg.h

319

#define HW_DIGCTL_OCRAM_STATUS8_FAILADDR01 __BITS(28, 16)

sys/arch/arm/imx/imx23_digctlreg.h

320

#define HW_DIGCTL_OCRAM_STATUS8_RSVD2 __BITS(15, 13)

sys/arch/arm/imx/imx23_digctlreg.h

321

#define HW_DIGCTL_OCRAM_STATUS8_FAILADDR00 __BITS(12, 0)

sys/arch/arm/imx/imx23_digctlreg.h

331

#define HW_DIGCTL_OCRAM_STATUS9_RSVD3 __BITS(31, 29)

sys/arch/arm/imx/imx23_digctlreg.h

332

#define HW_DIGCTL_OCRAM_STATUS9_FAILADDR11 __BITS(28, 16)

sys/arch/arm/imx/imx23_digctlreg.h

333

#define HW_DIGCTL_OCRAM_STATUS9_RSVD2 __BITS(15, 13)

sys/arch/arm/imx/imx23_digctlreg.h

334

#define HW_DIGCTL_OCRAM_STATUS9_FAILADDR10 __BITS(12, 0)

sys/arch/arm/imx/imx23_digctlreg.h

344

#define HW_DIGCTL_OCRAM_STATUS10_RSVD3 __BITS(31, 29)

sys/arch/arm/imx/imx23_digctlreg.h

345

#define HW_DIGCTL_OCRAM_STATUS10_FAILADDR21 __BITS(28, 16)

sys/arch/arm/imx/imx23_digctlreg.h

346

#define HW_DIGCTL_OCRAM_STATUS10_RSVD2 __BITS(15, 13)

sys/arch/arm/imx/imx23_digctlreg.h

347

#define HW_DIGCTL_OCRAM_STATUS10_FAILADDR20 __BITS(12, 0)

sys/arch/arm/imx/imx23_digctlreg.h

357

#define HW_DIGCTL_OCRAM_STATUS11_RSVD3 __BITS(31, 29)

sys/arch/arm/imx/imx23_digctlreg.h

358

#define HW_DIGCTL_OCRAM_STATUS11_FAILADDR31 __BITS(28, 16)

sys/arch/arm/imx/imx23_digctlreg.h

359

#define HW_DIGCTL_OCRAM_STATUS11_RSVD2 __BITS(15, 13)

sys/arch/arm/imx/imx23_digctlreg.h

360

#define HW_DIGCTL_OCRAM_STATUS11_FAILADDR30 __BITS(12, 0)

sys/arch/arm/imx/imx23_digctlreg.h

370

#define HW_DIGCTL_OCRAM_STATUS12_RSVD3 __BITS(31, 28)

sys/arch/arm/imx/imx23_digctlreg.h

371

#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE11 __BITS(27, 24)

sys/arch/arm/imx/imx23_digctlreg.h

372

#define HW_DIGCTL_OCRAM_STATUS12_RSVD2 __BITS(23, 20)

sys/arch/arm/imx/imx23_digctlreg.h

373

#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE10 __BITS(19, 16)

sys/arch/arm/imx/imx23_digctlreg.h

374

#define HW_DIGCTL_OCRAM_STATUS12_RSVD1 __BITS(15, 12)

sys/arch/arm/imx/imx23_digctlreg.h

375

#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE01 __BITS(11, 8)

sys/arch/arm/imx/imx23_digctlreg.h

376

#define HW_DIGCTL_OCRAM_STATUS12_RSVD0 __BITS(7, 4)

sys/arch/arm/imx/imx23_digctlreg.h

377

#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE00 __BITS(3, 0)

sys/arch/arm/imx/imx23_digctlreg.h

387

#define HW_DIGCTL_OCRAM_STATUS13_RSVD3 __BITS(31, 28)

sys/arch/arm/imx/imx23_digctlreg.h

388

#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE31 __BITS(27, 24)

sys/arch/arm/imx/imx23_digctlreg.h

389

#define HW_DIGCTL_OCRAM_STATUS13_RSVD2 __BITS(23, 20)

sys/arch/arm/imx/imx23_digctlreg.h

390

#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE30 __BITS(19, 16)

sys/arch/arm/imx/imx23_digctlreg.h

391

#define HW_DIGCTL_OCRAM_STATUS13_RSVD1 __BITS(15, 12)

sys/arch/arm/imx/imx23_digctlreg.h

392

#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE21 __BITS(11, 8)

sys/arch/arm/imx/imx23_digctlreg.h

393

#define HW_DIGCTL_OCRAM_STATUS13_RSVD0 __BITS(7, 4)

sys/arch/arm/imx/imx23_digctlreg.h

394

#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE20 __BITS(3, 0)

sys/arch/arm/imx/imx23_digctlreg.h

401

#define HW_DIGCTL_SCRATCH0_PTR __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

408

#define HW_DIGCTL_SCRATCH1_PTR __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

415

#define HW_DIGCTL_ARMCACHE_RSVD4 __BITS(31, 18)

sys/arch/arm/imx/imx23_digctlreg.h

416

#define HW_DIGCTL_ARMCACHE_VALID_SS __BITS(17, 16)

sys/arch/arm/imx/imx23_digctlreg.h

417

#define HW_DIGCTL_ARMCACHE_RSVD3 __BITS(15, 14)

sys/arch/arm/imx/imx23_digctlreg.h

418

#define HW_DIGCTL_ARMCACHE_DRTY_SS __BITS(13, 12)

sys/arch/arm/imx/imx23_digctlreg.h

419

#define HW_DIGCTL_ARMCACHE_RSVD2 __BITS(11, 10)

sys/arch/arm/imx/imx23_digctlreg.h

420

#define HW_DIGCTL_ARMCACHE_CACHE_SS __BITS(9, 8)

sys/arch/arm/imx/imx23_digctlreg.h

421

#define HW_DIGCTL_ARMCACHE_RSVD1 __BITS(7, 6)

sys/arch/arm/imx/imx23_digctlreg.h

422

#define HW_DIGCTL_ARMCACHE_DTAG_SS __BITS(5, 4)

sys/arch/arm/imx/imx23_digctlreg.h

423

#define HW_DIGCTL_ARMCACHE_RSVD0 __BITS(3, 2)

sys/arch/arm/imx/imx23_digctlreg.h

424

#define HW_DIGCTL_ARMCACHE_ITAG_SS __BITS(1, 0)

sys/arch/arm/imx/imx23_digctlreg.h

431

#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

438

#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

445

#define HW_DIGCTL_SGTL_COPYRIGHT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

452

#define HW_DIGCTL_CHIPID_PRODUCT_CODE __BITS(31, 16)

sys/arch/arm/imx/imx23_digctlreg.h

453

#define HW_DIGCTL_CHIPID_RSVD0 __BITS(16, 8)

sys/arch/arm/imx/imx23_digctlreg.h

454

#define HW_DIGCTL_CHIPID_REVISION __BITS(7, 0)

sys/arch/arm/imx/imx23_digctlreg.h

461

#define HW_DIGCTL_AHB_STATS_SELECT_RSVD3 __BITS(31, 28)

sys/arch/arm/imx/imx23_digctlreg.h

462

#define HW_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT __BITS(27, 24)

sys/arch/arm/imx/imx23_digctlreg.h

463

#define HW_DIGCTL_AHB_STATS_SELECT_RSVD2 __BITS(23, 20)

sys/arch/arm/imx/imx23_digctlreg.h

464

#define HW_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT __BITS(19, 16)

sys/arch/arm/imx/imx23_digctlreg.h

465

#define HW_DIGCTL_AHB_STATS_SELECT_RSVD1 __BITS(15, 12)

sys/arch/arm/imx/imx23_digctlreg.h

466

#define HW_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT __BITS(11, 8)

sys/arch/arm/imx/imx23_digctlreg.h

467

#define HW_DIGCTL_AHB_STATS_SELECT_RSVD0 __BITS(7, 4)

sys/arch/arm/imx/imx23_digctlreg.h

468

#define HW_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT __BITS(3, 0)

sys/arch/arm/imx/imx23_digctlreg.h

475

#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

482

#define HW_DIGCTL_L0_AHB_DATA_STALLED_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

489

#define HW_DIGCTL_L0_AHB_DATA_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

496

#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

503

#define HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

51

#define HW_DIGCTL_CTRL_RSVD2 __BITS(28, 27)

sys/arch/arm/imx/imx23_digctlreg.h

510

#define HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

517

#define HW_DIGCTL_L1_AHB_DATA_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

524

#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

531

#define HW_DIGCTL_L2_AHB_DATA_STALLED_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

538

#define HW_DIGCTL_L2_AHB_DATA_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

545

#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

552

#define HW_DIGCTL_L3_AHB_DATA_STALLED_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

559

#define HW_DIGCTL_L3_AHB_DATA_CYCLES_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_digctlreg.h

566

#define HW_DIGCTL_EMICLK_DELAY_RSVD0 __BITS(31, 5)

sys/arch/arm/imx/imx23_digctlreg.h

567

#define HW_DIGCTL_EMICLK_DELAY_NUM_TAPS __BITS(4, 0)

sys/arch/arm/imx/imx23_digctlreg.h

64

#define HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL __BITS(14, 13)

sys/arch/arm/imx/imx23_digctlreg.h

91

#define HW_DIGCTL_STATUS_RSVD2 __BITS(27, 11)

sys/arch/arm/imx/imx23_digctlreg.h

99

#define HW_DIGCTL_STATUS_PACKAGE_TYPE __BITS(3, 1)

sys/arch/arm/imx/imx23_digfiltreg.h

106

#define HW_AUDIOOUT_STAT_RSRVD1 __BITS(30, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

117

#define HW_AUDIOOUT_DACSRR_BASEMULT __BITS(30, 28)

sys/arch/arm/imx/imx23_digfiltreg.h

119

#define HW_AUDIOOUT_DACSRR_SRC_HOLD __BITS(26, 24)

sys/arch/arm/imx/imx23_digfiltreg.h

120

#define HW_AUDIOOUT_DACSRR_RSRVD1 __BITS(23, 21)

sys/arch/arm/imx/imx23_digfiltreg.h

121

#define HW_AUDIOOUT_DACSRR_SRC_INT __BITS(20, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

122

#define HW_AUDIOOUT_DACSRR_RSRVD0 __BITS(15, 13)

sys/arch/arm/imx/imx23_digfiltreg.h

123

#define HW_AUDIOOUT_DACSRR_SRC_FRAC __BITS(12, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

133

#define HW_AUDIOOUT_DACVOLUME_RSRVD4 __BITS(31, 29)

sys/arch/arm/imx/imx23_digfiltreg.h

135

#define HW_AUDIOOUT_DACVOLUME_RSRVD3 __BITS(27, 26)

sys/arch/arm/imx/imx23_digfiltreg.h

138

#define HW_AUDIOOUT_DACVOLUME_VOLUME_LEFT __BITS(23, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

139

#define HW_AUDIOOUT_DACVOLUME_RSRVD2 __BITS(15, 13)

sys/arch/arm/imx/imx23_digfiltreg.h

141

#define HW_AUDIOOUT_DACVOLUME_RSRVD1 __BITS(11, 9)

sys/arch/arm/imx/imx23_digfiltreg.h

143

#define HW_AUDIOOUT_DACVOLUME_VOLUME_RIGHT __BITS(7, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

154

#define HW_AUDIOOUT_DACDEBUG_RSRVD2 __BITS(30, 12)

sys/arch/arm/imx/imx23_digfiltreg.h

155

#define HW_AUDIOOUT_DACDEBUG_RAM_SS __BITS(11, 8)

sys/arch/arm/imx/imx23_digfiltreg.h

156

#define HW_AUDIOOUT_DACDEBUG_RSRVD1 __BITS(7, 6)

sys/arch/arm/imx/imx23_digfiltreg.h

172

#define HW_AUDIOOUT_HPVOL_RSRVD5 __BITS(31, 29)

sys/arch/arm/imx/imx23_digfiltreg.h

174

#define HW_AUDIOOUT_HPVOL_RSRVD4 __BITS(27, 26)

sys/arch/arm/imx/imx23_digfiltreg.h

177

#define HW_AUDIOOUT_HPVOL_RSRVD3 __BITS(23, 17)

sys/arch/arm/imx/imx23_digfiltreg.h

180

#define HW_AUDIOOUT_HPVOL_VOL_LEFT __BITS(14, 8)

sys/arch/arm/imx/imx23_digfiltreg.h

182

#define HW_AUDIOOUT_HPVOL_VOL_RIGHT __BITS(6, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

192

#define HW_AUDIOOUT_RESERVED_RSRVD1 __BITS(31, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

202

#define HW_AUDIOOUT_PWRDN_RSRVD7 __BITS(31, 25)

sys/arch/arm/imx/imx23_digfiltreg.h

204

#define HW_AUDIOOUT_PWRDN_RSRVD6 __BITS(23, 21)

sys/arch/arm/imx/imx23_digfiltreg.h

206

#define HW_AUDIOOUT_PWRDN_RSRVD5 __BITS(19, 17)

sys/arch/arm/imx/imx23_digfiltreg.h

208

#define HW_AUDIOOUT_PWRDN_RSRVD4 __BITS(15, 13)

sys/arch/arm/imx/imx23_digfiltreg.h

210

#define HW_AUDIOOUT_PWRDN_RSRVD3 __BITS(11, 9)

sys/arch/arm/imx/imx23_digfiltreg.h

212

#define HW_AUDIOOUT_PWRDN_RSRVD2 __BITS(7, 5)

sys/arch/arm/imx/imx23_digfiltreg.h

214

#define HW_AUDIOOUT_PWRDN_RSRVD1 __BITS(3, 1)

sys/arch/arm/imx/imx23_digfiltreg.h

225

#define HW_AUDIOOUT_REFCTRL_RSRVD4 __BITS(31, 27)

sys/arch/arm/imx/imx23_digfiltreg.h

230

#define HW_AUDIOOUT_REFCTRL_VBG_ADJ __BITS(22, 20)

sys/arch/arm/imx/imx23_digfiltreg.h

233

#define HW_AUDIOOUT_REFCTRL_BIAS_CTRL __BITS(17, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

238

#define HW_AUDIOOUT_REFCTRL_ADC_REFVAL __BITS(11, 8)

sys/arch/arm/imx/imx23_digfiltreg.h

239

#define HW_AUDIOOUT_REFCTRL_VAG_VAL __BITS(7, 4)

sys/arch/arm/imx/imx23_digfiltreg.h

251

#define HW_AUDIOOUT_ANACTRL_RSRVD8 __BITS(31, 29)

sys/arch/arm/imx/imx23_digfiltreg.h

253

#define HW_AUDIOOUT_ANACTRL_RSRVD7 __BITS(27, 25)

sys/arch/arm/imx/imx23_digfiltreg.h

255

#define HW_AUDIOOUT_ANACTRL_RSRVD6 __BITS(23, 22)

sys/arch/arm/imx/imx23_digfiltreg.h

258

#define HW_AUDIOOUT_ANACTRL_SHORTMODE_LR __BITS(18, 17)

sys/arch/arm/imx/imx23_digfiltreg.h

259

#define HW_AUDIOOUT_ANACTRL_RSRVD4 __BITS(16, 15)

sys/arch/arm/imx/imx23_digfiltreg.h

260

#define HW_AUDIOOUT_ANACTRL_SHORT_LVLADJL __BITS(14, 12)

sys/arch/arm/imx/imx23_digfiltreg.h

262

#define HW_AUDIOOUT_ANACTRL_SHORT_LVLADJR __BITS(10, 8)

sys/arch/arm/imx/imx23_digfiltreg.h

263

#define HW_AUDIOOUT_ANACTRL_RSRVD2 __BITS(7, 6)

sys/arch/arm/imx/imx23_digfiltreg.h

266

#define HW_AUDIOOUT_ANACTRL_RSRVD1 __BITS(3, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

277

#define HW_AUDIOOUT_TEST_HP_ANTIPOP __BITS(30, 28)

sys/arch/arm/imx/imx23_digfiltreg.h

282

#define HW_AUDIOOUT_TEST_HP_I1_ADJ __BITS(23, 22)

sys/arch/arm/imx/imx23_digfiltreg.h

283

#define HW_AUDIOOUT_TEST_HP_IALL_ADJ __BITS(21, 20)

sys/arch/arm/imx/imx23_digfiltreg.h

284

#define HW_AUDIOOUT_TEST_RSRVD2 __BITS(19, 14)

sys/arch/arm/imx/imx23_digfiltreg.h

287

#define HW_AUDIOOUT_TEST_RSRVD1 __BITS(11, 4)

sys/arch/arm/imx/imx23_digfiltreg.h

301

#define HW_AUDIOOUT_BISTCTRL_RSVD0 __BITS(31, 4)

sys/arch/arm/imx/imx23_digfiltreg.h

315

#define HW_AUDIOOUT_BISTSTAT0_RSVD0 __BITS(31, 24)

sys/arch/arm/imx/imx23_digfiltreg.h

316

#define HW_AUDIOOUT_BISTSTAT0_DATA __BITS(23, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

326

#define HW_AUDIOOUT_BISTSTAT1_RSVD1 __BITS(31, 29)

sys/arch/arm/imx/imx23_digfiltreg.h

327

#define HW_AUDIOOUT_BISTSTAT1_STATE __BITS(28, 24)

sys/arch/arm/imx/imx23_digfiltreg.h

328

#define HW_AUDIOOUT_BISTSTAT1_RSVD0 __BITS(23, 8)

sys/arch/arm/imx/imx23_digfiltreg.h

329

#define HW_AUDIOOUT_BISTSTAT1_ADDR __BITS(7, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

340

#define HW_AUDIOOUT_ANACLKCTRL_RSRVD3 __BITS(30, 5)

sys/arch/arm/imx/imx23_digfiltreg.h

343

#define HW_AUDIOOUT_ANACLKCTRL_DACDIV __BITS(2, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

353

#define HW_AUDIOOUT_DATA_HIGH __BITS(31, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

354

#define HW_AUDIOOUT_DATA_LOW __BITS(15, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

364

#define HW_AUDIOOUT_SPEAKERCTRL_RSRVD2 __BITS(31, 25)

sys/arch/arm/imx/imx23_digfiltreg.h

366

#define HW_AUDIOOUT_SPEAKERCTRL_I1_ADJ __BITS(23, 22)

sys/arch/arm/imx/imx23_digfiltreg.h

367

#define HW_AUDIOOUT_SPEAKERCTRL_IALL_ADJ __BITS(21, 20)

sys/arch/arm/imx/imx23_digfiltreg.h

368

#define HW_AUDIOOUT_SPEAKERCTRL_RSRVD1 __BITS(19, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

369

#define HW_AUDIOOUT_SPEAKERCTRL_POSDRIVER __BITS(15, 14)

sys/arch/arm/imx/imx23_digfiltreg.h

370

#define HW_AUDIOOUT_SPEAKERCTRL_NEGDRIVER __BITS(13, 12)

sys/arch/arm/imx/imx23_digfiltreg.h

371

#define HW_AUDIOOUT_SPEAKERCTRL_RSRVD0 __BITS(11, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

378

#define HW_AUDIOOUT_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_digfiltreg.h

379

#define HW_AUDIOOUT_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

380

#define HW_AUDIOOUT_VERSION_STEP __BITS(15, 0)

sys/arch/arm/imx/imx23_digfiltreg.h

56

#define HW_AUDIOIN_CTRL_RSRVD3 __BITS(29, 21)

sys/arch/arm/imx/imx23_digfiltreg.h

57

#define HW_AUDIOIN_CTRL_DMAWAIT_COUNT __BITS(20, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

58

#define HW_AUDIOIN_CTRL_RSRVD1 __BITS(15, 11)

sys/arch/arm/imx/imx23_digfiltreg.h

80

#define HW_AUDIOOUT_CTRL_RSRVD4 __BITS(29, 21)

sys/arch/arm/imx/imx23_digfiltreg.h

81

#define HW_AUDIOOUT_CTRL_DMAWAIT_COUNT __BITS(20, 16)

sys/arch/arm/imx/imx23_digfiltreg.h

86

#define HW_AUDIOOUT_CTRL_RSRVD2 __BITS(11, 10)

sys/arch/arm/imx/imx23_digfiltreg.h

87

#define HW_AUDIOOUT_CTRL_SS3D_EFFECT __BITS(9, 8)

sys/arch/arm/imx/imx23_icollreg.h

139

#define HW_ICOLL_VECTOR_IRQVECTOR __BITS(32, 2)

sys/arch/arm/imx/imx23_icollreg.h

140

#define HW_ICOLL_VECTOR_RSRVD1 __BITS(1, 0)

sys/arch/arm/imx/imx23_icollreg.h

147

#define HW_ICOLL_LEVELACK_RSRVD1 __BITS(31, 4)

sys/arch/arm/imx/imx23_icollreg.h

160

#define HW_ICOLL_CTRL_RSRVD3 __BITS(29, 24)

sys/arch/arm/imx/imx23_icollreg.h

161

#define HW_ICOLL_CTRL_VECTOR_PITCH __BITS(23, 21)

sys/arch/arm/imx/imx23_icollreg.h

167

#define HW_ICOLL_CTRL_RSRVD1 __BITS(15, 0)

sys/arch/arm/imx/imx23_icollreg.h

177

#define HW_ICOLL_VBASE_TABLE_ADDRESS __BITS(32, 2)

sys/arch/arm/imx/imx23_icollreg.h

178

#define HW_ICOLL_VBASE_RSRVD1 __BITS(1, 0)

sys/arch/arm/imx/imx23_icollreg.h

185

#define HW_ICOLL_STAT_RSRVD1 __BITS(31, 7)

sys/arch/arm/imx/imx23_icollreg.h

186

#define HW_ICOLL_STAT_VECTOR_NUMBER __BITS(6, 0)

sys/arch/arm/imx/imx23_icollreg.h

196

#define HW_ICOLL_RAW0_RAW_IRQS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

206

#define HW_ICOLL_RAW1_RAW_IRQS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

216

#define HW_ICOLL_RAW2_RAW_IRQS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

226

#define HW_ICOLL_RAW3_RAW_IRQS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

231

#define HW_ICOLL_INTERRUPT_RSRVD1 __BITS(31, 5)

sys/arch/arm/imx/imx23_icollreg.h

235

#define HW_ICOLL_INTERRUPT_PRIORITY __BITS(1, 0)

sys/arch/arm/imx/imx23_icollreg.h

245

#define HW_ICOLL_INTERRUPT0_RSRVD1 __BITS(31, 5)

sys/arch/arm/imx/imx23_icollreg.h

249

#define HW_ICOLL_INTERRUPT0_PRIORITY __BITS(1, 0)

sys/arch/arm/imx/imx23_icollreg.h

259

#define HW_ICOLL_INTERRUPT127_RSRVD1 __BITS(31, 5)

sys/arch/arm/imx/imx23_icollreg.h

263

#define HW_ICOLL_INTERRUPT127_PRIORITY __BITS(1, 0)

sys/arch/arm/imx/imx23_icollreg.h

273

#define HW_ICOLL_DEBUG_INSERVICE __BITS(31, 28)

sys/arch/arm/imx/imx23_icollreg.h

274

#define HW_ICOLL_DEBUG_LEVEL_REQUESTS __BITS(27, 24)

sys/arch/arm/imx/imx23_icollreg.h

275

#define HW_ICOLL_DEBUG_REQUESTS_BY_LEVEL __BITS(23, 20)

sys/arch/arm/imx/imx23_icollreg.h

276

#define HW_ICOLL_DEBUG_RSRVD2 __BITS(19, 18)

sys/arch/arm/imx/imx23_icollreg.h

279

#define HW_ICOLL_DEBUG_RSRVD1 __BITS(15, 10)

sys/arch/arm/imx/imx23_icollreg.h

280

#define HW_ICOLL_DEBUG_VECTOR_FSM __BITS(9, 0)

sys/arch/arm/imx/imx23_icollreg.h

290

#define HW_ICOLL_DBGREAD0_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

300

#define HW_ICOLL_DBGREAD1_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

310

#define HW_ICOLL_DBGFLAG_RSRVD1 __BITS(31, 16)

sys/arch/arm/imx/imx23_icollreg.h

311

#define HW_ICOLL_DBGFLAG_FLAG __BITS(15, 0)

sys/arch/arm/imx/imx23_icollreg.h

321

#define HW_ICOLL_DBGREQUEST0_BITS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

331

#define HW_ICOLL_DBGREQUEST1_BITS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

341

#define HW_ICOLL_DBGREQUEST2_BITS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

351

#define HW_ICOLL_DBGREQUEST3_BITS __BITS(31, 0)

sys/arch/arm/imx/imx23_icollreg.h

358

#define HW_ICOLL_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_icollreg.h

359

#define HW_ICOLL_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_icollreg.h

360

#define HW_ICOLL_VERSION_STEP __BITS(15, 0)

sys/arch/arm/imx/imx23_mmcreg.h

103

#define HW_SSP_COMPMASK_MASK __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

110

#define HW_SSP_TIMING_TIMEOUT __BITS(31, 16)

sys/arch/arm/imx/imx23_mmcreg.h

111

#define HW_SSP_TIMING_CLOCK_DIVIDE __BITS(15, 8)

sys/arch/arm/imx/imx23_mmcreg.h

112

#define HW_SSP_TIMING_CLOCK_RATE __BITS(7, 0)

sys/arch/arm/imx/imx23_mmcreg.h

146

#define HW_SSP_CTRL1_WORD_LENGTH __BITS(7, 4)

sys/arch/arm/imx/imx23_mmcreg.h

147

#define HW_SSP_CTRL1_SSP_MODE __BITS(3, 0)

sys/arch/arm/imx/imx23_mmcreg.h

154

#define HW_SSP_DATA_DATA __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

161

#define HW_SSP_SDRESP0_RESP0 __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

168

#define HW_SSP_SDRESP1_RESP1 __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

175

#define HW_SSP_SDRESP2_RESP2 __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

182

#define HW_SSP_SDRESP3_RESP3 __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

193

#define HW_SSP_STATUS_RSVD4 __BITS(27, 22)

sys/arch/arm/imx/imx23_mmcreg.h

221

#define HW_SSP_DEBUG_DATACRC_ERR __BITS(31, 28)

sys/arch/arm/imx/imx23_mmcreg.h

223

#define HW_SSP_DEBUG_DAT_SM __BITS(26, 24)

sys/arch/arm/imx/imx23_mmcreg.h

224

#define HW_SSP_DEBUG_RSVD1 __BITS(23, 20)

sys/arch/arm/imx/imx23_mmcreg.h

226

#define HW_SSP_DEBUG_DMA_SM __BITS(18, 16)

sys/arch/arm/imx/imx23_mmcreg.h

227

#define HW_SSP_DEBUG_MMC_SM __BITS(15, 12)

sys/arch/arm/imx/imx23_mmcreg.h

228

#define HW_SSP_DEBUG_CMD_SM __BITS(11, 10)

sys/arch/arm/imx/imx23_mmcreg.h

231

#define HW_SSP_DEBUG_SSP_RXD __BITS(7, 0)

sys/arch/arm/imx/imx23_mmcreg.h

238

#define HW_SSP_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_mmcreg.h

239

#define HW_SSP_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_mmcreg.h

240

#define HW_SSP_VERSION_STEP __BITS(15, 0)

sys/arch/arm/imx/imx23_mmcreg.h

59

#define HW_SSP_CTRL0_BUS_WIDTH __BITS(23, 22)

sys/arch/arm/imx/imx23_mmcreg.h

66

#define HW_SSP_CTRL0_XFER_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_mmcreg.h

76

#define HW_SSP_CMD0_RSVD0 __BITS(31, 23)

sys/arch/arm/imx/imx23_mmcreg.h

80

#define HW_SSP_CMD0_BLOCK_SIZE __BITS(19, 16)

sys/arch/arm/imx/imx23_mmcreg.h

81

#define HW_SSP_CMD0_BLOCK_COUNT __BITS(15, 8)

sys/arch/arm/imx/imx23_mmcreg.h

82

#define HW_SSP_CMD0_CMD __BITS(7, 0)

sys/arch/arm/imx/imx23_mmcreg.h

89

#define HW_SSP_CMD1_CMD_ARG __BITS(31, 0)

sys/arch/arm/imx/imx23_mmcreg.h

96

#define HW_SSP_COMPREF_REFERENCE __BITS(31, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1000

#define HW_PINCTRL_DRIVE8_RSRVD7 __BITS(31, 30)

sys/arch/arm/imx/imx23_pinctrlreg.h

1001

#define HW_PINCTRL_DRIVE8_BANK2_PIN07_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

1002

#define HW_PINCTRL_DRIVE8_RSRVD6 __BITS(27, 26)

sys/arch/arm/imx/imx23_pinctrlreg.h

1003

#define HW_PINCTRL_DRIVE8_BANK2_PIN06_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1004

#define HW_PINCTRL_DRIVE8_RSRVD5 __BITS(23, 22)

sys/arch/arm/imx/imx23_pinctrlreg.h

1005

#define HW_PINCTRL_DRIVE8_BANK2_PIN05_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1006

#define HW_PINCTRL_DRIVE8_RSRVD4 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

1007

#define HW_PINCTRL_DRIVE8_BANK2_PIN04_MA __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

1008

#define HW_PINCTRL_DRIVE8_RSRVD3 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

1009

#define HW_PINCTRL_DRIVE8_BANK2_PIN03_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1010

#define HW_PINCTRL_DRIVE8_RSRVD2 __BITS(11, 10)

sys/arch/arm/imx/imx23_pinctrlreg.h

1011

#define HW_PINCTRL_DRIVE8_BANK2_PIN02_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1012

#define HW_PINCTRL_DRIVE8_RSRVD1 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

1013

#define HW_PINCTRL_DRIVE8_BANK2_PIN01_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1014

#define HW_PINCTRL_DRIVE8_RSRVD0 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

1015

#define HW_PINCTRL_DRIVE8_BANK2_PIN00_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1027

#define HW_PINCTRL_DRIVE9_BANK2_PIN15_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

1030

#define HW_PINCTRL_DRIVE9_BANK2_PIN14_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1033

#define HW_PINCTRL_DRIVE9_BANK2_PIN13_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1036

#define HW_PINCTRL_DRIVE9_BANK2_PIN12_MA __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

1039

#define HW_PINCTRL_DRIVE9_BANK2_PIN11_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1042

#define HW_PINCTRL_DRIVE9_BANK2_PIN10_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1045

#define HW_PINCTRL_DRIVE9_BANK2_PIN09_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1046

#define HW_PINCTRL_DRIVE9_RSRVD0 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

1047

#define HW_PINCTRL_DRIVE9_BANK2_PIN08_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1059

#define HW_PINCTRL_DRIVE10_BANK2_PIN23_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

1062

#define HW_PINCTRL_DRIVE10_BANK2_PIN22_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1065

#define HW_PINCTRL_DRIVE10_BANK2_PIN21_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1068

#define HW_PINCTRL_DRIVE10_BANK2_PIN20_MA __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

1071

#define HW_PINCTRL_DRIVE10_BANK2_PIN19_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1074

#define HW_PINCTRL_DRIVE10_BANK2_PIN18_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1077

#define HW_PINCTRL_DRIVE10_BANK2_PIN17_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1080

#define HW_PINCTRL_DRIVE10_BANK2_PIN16_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1092

#define HW_PINCTRL_DRIVE11_BANK2_PIN31_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

1095

#define HW_PINCTRL_DRIVE11_BANK2_PIN30_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1098

#define HW_PINCTRL_DRIVE11_BANK2_PIN29_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1099

#define HW_PINCTRL_DRIVE11_RSRVD4 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

1101

#define HW_PINCTRL_DRIVE11_RSRVD3 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

1102

#define HW_PINCTRL_DRIVE11_BANK2_PIN27_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1105

#define HW_PINCTRL_DRIVE11_BANK2_PIN26_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1108

#define HW_PINCTRL_DRIVE11_BANK2_PIN25_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1111

#define HW_PINCTRL_DRIVE11_BANK2_PIN24_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1123

#define HW_PINCTRL_DRIVE12_BANK3_PIN07_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

1126

#define HW_PINCTRL_DRIVE12_BANK3_PIN06_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1129

#define HW_PINCTRL_DRIVE12_BANK3_PIN05_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1132

#define HW_PINCTRL_DRIVE12_BANK3_PIN04_MA __BITS(17, 15)

sys/arch/arm/imx/imx23_pinctrlreg.h

1135

#define HW_PINCTRL_DRIVE12_BANK3_PIN03_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1138

#define HW_PINCTRL_DRIVE12_BANK3_PIN02_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1141

#define HW_PINCTRL_DRIVE12_BANK3_PIN01_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1144

#define HW_PINCTRL_DRIVE12_BANK3_PIN00_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1156

#define HW_PINCTRL_DRIVE13_BANK3_PIN15_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

1159

#define HW_PINCTRL_DRIVE13_BANK3_PIN14_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1162

#define HW_PINCTRL_DRIVE13_BANK3_PIN13_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1165

#define HW_PINCTRL_DRIVE13_BANK3_PIN12_MA __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

1168

#define HW_PINCTRL_DRIVE13_BANK3_PIN11_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1171

#define HW_PINCTRL_DRIVE13_BANK3_PIN10_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1174

#define HW_PINCTRL_DRIVE13_BANK3_PIN09_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1177

#define HW_PINCTRL_DRIVE13_BANK3_PIN08_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1187

#define HW_PINCTRL_DRIVE14_RSRVD6 __BITS(31, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

1190

#define HW_PINCTRL_DRIVE14_BANK3_PIN21_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

1193

#define HW_PINCTRL_DRIVE14_BANK3_PIN20_MA __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

1196

#define HW_PINCTRL_DRIVE14_BANK3_PIN19_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

1199

#define HW_PINCTRL_DRIVE14_BANK3_PIN18_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

1202

#define HW_PINCTRL_DRIVE14_BANK3_PIN17_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

1205

#define HW_PINCTRL_DRIVE14_BANK3_PIN16_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1223

#define HW_PINCTRL_PULL2_RSRVD2 __BITS(31, 29)

sys/arch/arm/imx/imx23_pinctrlreg.h

1226

#define HW_PINCTRL_PULL2_RSRVD1 __BITS(26, 9)

sys/arch/arm/imx/imx23_pinctrlreg.h

1228

#define HW_PINCTRL_PULL2_RSRVD0 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

1244

#define HW_PINCTRL_PULL3_RSRVD0 __BITS(31, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

1272

#define HW_PINCTRL_DOUT0_DOUT __BITS(31, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1282

#define HW_PINCTRL_DOUT1_DOUT __BITS(31, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

1300

#define HW_PINCTRL_DOE0_DOE __BITS(31, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

189

#define HW_PINCTRL_MUXSEL1_BANK0_PIN31 __BITS(31, 30)

sys/arch/arm/imx/imx23_pinctrlreg.h

190

#define HW_PINCTRL_MUXSEL1_BANK0_PIN30 __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

191

#define HW_PINCTRL_MUXSEL1_BANK0_PIN29 __BITS(27, 26)

sys/arch/arm/imx/imx23_pinctrlreg.h

192

#define HW_PINCTRL_MUXSEL1_BANK0_PIN28 __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

193

#define HW_PINCTRL_MUXSEL1_BANK0_PIN27 __BITS(23, 22)

sys/arch/arm/imx/imx23_pinctrlreg.h

194

#define HW_PINCTRL_MUXSEL1_BANK0_PIN26 __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

195

#define HW_PINCTRL_MUXSEL1_BANK0_PIN25 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

196

#define HW_PINCTRL_MUXSEL1_BANK0_PIN24 __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

197

#define HW_PINCTRL_MUXSEL1_BANK0_PIN23 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

198

#define HW_PINCTRL_MUXSEL1_BANK0_PIN22 __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

199

#define HW_PINCTRL_MUXSEL1_BANK0_PIN21 __BITS(11, 10)

sys/arch/arm/imx/imx23_pinctrlreg.h

200

#define HW_PINCTRL_MUXSEL1_BANK0_PIN20 __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

201

#define HW_PINCTRL_MUXSEL1_BANK0_PIN19 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

202

#define HW_PINCTRL_MUXSEL1_BANK0_PIN18 __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

203

#define HW_PINCTRL_MUXSEL1_BANK0_PIN17 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

204

#define HW_PINCTRL_MUXSEL1_BANK0_PIN16 __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

310

#define HW_PINCTRL_MUXSEL2_BANK1_PIN15 __BITS(31, 30)

sys/arch/arm/imx/imx23_pinctrlreg.h

311

#define HW_PINCTRL_MUXSEL2_BANK1_PIN14 __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

312

#define HW_PINCTRL_MUXSEL2_BANK1_PIN13 __BITS(27, 26)

sys/arch/arm/imx/imx23_pinctrlreg.h

313

#define HW_PINCTRL_MUXSEL2_BANK1_PIN12 __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

314

#define HW_PINCTRL_MUXSEL2_BANK1_PIN11 __BITS(23, 22)

sys/arch/arm/imx/imx23_pinctrlreg.h

315

#define HW_PINCTRL_MUXSEL2_BANK1_PIN10 __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

316

#define HW_PINCTRL_MUXSEL2_BANK1_PIN09 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

317

#define HW_PINCTRL_MUXSEL2_BANK1_PIN08 __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

318

#define HW_PINCTRL_MUXSEL2_BANK1_PIN07 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

319

#define HW_PINCTRL_MUXSEL2_BANK1_PIN06 __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

320

#define HW_PINCTRL_MUXSEL2_BANK1_PIN05 __BITS(11, 10)

sys/arch/arm/imx/imx23_pinctrlreg.h

321

#define HW_PINCTRL_MUXSEL2_BANK1_PIN04 __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

322

#define HW_PINCTRL_MUXSEL2_BANK1_PIN03 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

323

#define HW_PINCTRL_MUXSEL2_BANK1_PIN02 __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

324

#define HW_PINCTRL_MUXSEL2_BANK1_PIN01 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

325

#define HW_PINCTRL_MUXSEL2_BANK1_PIN00 __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

431

#define HW_PINCTRL_MUXSEL3_RSRVD0 __BITS(31, 30)

sys/arch/arm/imx/imx23_pinctrlreg.h

432

#define HW_PINCTRL_MUXSEL3_BANK1_PIN30 __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

433

#define HW_PINCTRL_MUXSEL3_BANK1_PIN29 __BITS(27, 26)

sys/arch/arm/imx/imx23_pinctrlreg.h

434

#define HW_PINCTRL_MUXSEL3_BANK1_PIN28 __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

435

#define HW_PINCTRL_MUXSEL3_BANK1_PIN27 __BITS(23, 22)

sys/arch/arm/imx/imx23_pinctrlreg.h

436

#define HW_PINCTRL_MUXSEL3_BANK1_PIN26 __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

437

#define HW_PINCTRL_MUXSEL3_BANK1_PIN25 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

438

#define HW_PINCTRL_MUXSEL3_BANK1_PIN24 __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

439

#define HW_PINCTRL_MUXSEL3_BANK1_PIN23 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

440

#define HW_PINCTRL_MUXSEL3_BANK1_PIN22 __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

441

#define HW_PINCTRL_MUXSEL3_BANK1_PIN21 __BITS(11, 10)

sys/arch/arm/imx/imx23_pinctrlreg.h

442

#define HW_PINCTRL_MUXSEL3_BANK1_PIN20 __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

443

#define HW_PINCTRL_MUXSEL3_BANK1_PIN19 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

444

#define HW_PINCTRL_MUXSEL3_BANK1_PIN18 __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

445

#define HW_PINCTRL_MUXSEL3_BANK1_PIN17 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

446

#define HW_PINCTRL_MUXSEL3_BANK1_PIN16 __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

50

#define HW_PINCTRL_CTRL_RSRVD2 __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

549

#define HW_PINCTRL_MUXSEL4_BANK2_PIN15 __BITS(31,30)

sys/arch/arm/imx/imx23_pinctrlreg.h

550

#define HW_PINCTRL_MUXSEL4_BANK2_PIN14 __BITS(29,28)

sys/arch/arm/imx/imx23_pinctrlreg.h

551

#define HW_PINCTRL_MUXSEL4_BANK2_PIN13 __BITS(27,26)

sys/arch/arm/imx/imx23_pinctrlreg.h

552

#define HW_PINCTRL_MUXSEL4_BANK2_PIN12 __BITS(25,24)

sys/arch/arm/imx/imx23_pinctrlreg.h

553

#define HW_PINCTRL_MUXSEL4_BANK2_PIN11 __BITS(23,22)

sys/arch/arm/imx/imx23_pinctrlreg.h

554

#define HW_PINCTRL_MUXSEL4_BANK2_PIN10 __BITS(21,20)

sys/arch/arm/imx/imx23_pinctrlreg.h

555

#define HW_PINCTRL_MUXSEL4_BANK2_PIN09 __BITS(19,18)

sys/arch/arm/imx/imx23_pinctrlreg.h

556

#define HW_PINCTRL_MUXSEL4_BANK2_PIN08 __BITS(17,16)

sys/arch/arm/imx/imx23_pinctrlreg.h

557

#define HW_PINCTRL_MUXSEL4_BANK2_PIN07 __BITS(15,14)

sys/arch/arm/imx/imx23_pinctrlreg.h

558

#define HW_PINCTRL_MUXSEL4_BANK2_PIN06 __BITS(13,12)

sys/arch/arm/imx/imx23_pinctrlreg.h

559

#define HW_PINCTRL_MUXSEL4_BANK2_PIN05 __BITS(11,10)

sys/arch/arm/imx/imx23_pinctrlreg.h

56

#define HW_PINCTRL_CTRL_IRQOUT2 __BITS(2)

sys/arch/arm/imx/imx23_pinctrlreg.h

560

#define HW_PINCTRL_MUXSEL4_BANK2_PIN04 __BITS(9,8)

sys/arch/arm/imx/imx23_pinctrlreg.h

561

#define HW_PINCTRL_MUXSEL4_BANK2_PIN03 __BITS(7,6)

sys/arch/arm/imx/imx23_pinctrlreg.h

562

#define HW_PINCTRL_MUXSEL4_BANK2_PIN02 __BITS(5,4)

sys/arch/arm/imx/imx23_pinctrlreg.h

563

#define HW_PINCTRL_MUXSEL4_BANK2_PIN01 __BITS(3,2)

sys/arch/arm/imx/imx23_pinctrlreg.h

564

#define HW_PINCTRL_MUXSEL4_BANK2_PIN00 __BITS(1,0)

sys/arch/arm/imx/imx23_pinctrlreg.h

670

#define HW_PINCTRL_MUXSEL5_BANK2_PIN31 __BITS(31,30)

sys/arch/arm/imx/imx23_pinctrlreg.h

671

#define HW_PINCTRL_MUXSEL5_BANK2_PIN30 __BITS(29,28)

sys/arch/arm/imx/imx23_pinctrlreg.h

672

#define HW_PINCTRL_MUXSEL5_BANK2_PIN29 __BITS(27,26)

sys/arch/arm/imx/imx23_pinctrlreg.h

673

#define HW_PINCTRL_MUXSEL5_BANK2_PIN28 __BITS(25,24)

sys/arch/arm/imx/imx23_pinctrlreg.h

674

#define HW_PINCTRL_MUXSEL5_BANK2_PIN27 __BITS(23,22)

sys/arch/arm/imx/imx23_pinctrlreg.h

675

#define HW_PINCTRL_MUXSEL5_BANK2_PIN26 __BITS(21,20)

sys/arch/arm/imx/imx23_pinctrlreg.h

676

#define HW_PINCTRL_MUXSEL5_BANK2_PIN25 __BITS(19,18)

sys/arch/arm/imx/imx23_pinctrlreg.h

677

#define HW_PINCTRL_MUXSEL5_BANK2_PIN24 __BITS(17,16)

sys/arch/arm/imx/imx23_pinctrlreg.h

678

#define HW_PINCTRL_MUXSEL5_BANK2_PIN23 __BITS(15,14)

sys/arch/arm/imx/imx23_pinctrlreg.h

679

#define HW_PINCTRL_MUXSEL5_BANK2_PIN22 __BITS(13,12)

sys/arch/arm/imx/imx23_pinctrlreg.h

68

#define HW_PINCTRL_MUXSEL0_BANK0_PIN15 __BITS(31, 30)

sys/arch/arm/imx/imx23_pinctrlreg.h

680

#define HW_PINCTRL_MUXSEL5_BANK2_PIN21 __BITS(11,10)

sys/arch/arm/imx/imx23_pinctrlreg.h

681

#define HW_PINCTRL_MUXSEL5_BANK2_PIN20 __BITS(9,8)

sys/arch/arm/imx/imx23_pinctrlreg.h

682

#define HW_PINCTRL_MUXSEL5_BANK2_PIN19 __BITS(7,6)

sys/arch/arm/imx/imx23_pinctrlreg.h

683

#define HW_PINCTRL_MUXSEL5_BANK2_PIN18 __BITS(5,4)

sys/arch/arm/imx/imx23_pinctrlreg.h

684

#define HW_PINCTRL_MUXSEL5_BANK2_PIN17 __BITS(3,2)

sys/arch/arm/imx/imx23_pinctrlreg.h

685

#define HW_PINCTRL_MUXSEL5_BANK2_PIN16 __BITS(1,0)

sys/arch/arm/imx/imx23_pinctrlreg.h

69

#define HW_PINCTRL_MUXSEL0_BANK0_PIN14 __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

70

#define HW_PINCTRL_MUXSEL0_BANK0_PIN13 __BITS(27, 26)

sys/arch/arm/imx/imx23_pinctrlreg.h

71

#define HW_PINCTRL_MUXSEL0_BANK0_PIN12 __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

72

#define HW_PINCTRL_MUXSEL0_BANK0_PIN11 __BITS(23, 22)

sys/arch/arm/imx/imx23_pinctrlreg.h

73

#define HW_PINCTRL_MUXSEL0_BANK0_PIN10 __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

74

#define HW_PINCTRL_MUXSEL0_BANK0_PIN09 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

75

#define HW_PINCTRL_MUXSEL0_BANK0_PIN08 __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

76

#define HW_PINCTRL_MUXSEL0_BANK0_PIN07 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

77

#define HW_PINCTRL_MUXSEL0_BANK0_PIN06 __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

78

#define HW_PINCTRL_MUXSEL0_BANK0_PIN05 __BITS(11, 10)

sys/arch/arm/imx/imx23_pinctrlreg.h

79

#define HW_PINCTRL_MUXSEL0_BANK0_PIN04 __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

791

#define HW_PINCTRL_MUXSEL6_BANK3_PIN15 __BITS(31,30)

sys/arch/arm/imx/imx23_pinctrlreg.h

792

#define HW_PINCTRL_MUXSEL6_BANK3_PIN14 __BITS(29,28)

sys/arch/arm/imx/imx23_pinctrlreg.h

793

#define HW_PINCTRL_MUXSEL6_BANK3_PIN13 __BITS(27,26)

sys/arch/arm/imx/imx23_pinctrlreg.h

794

#define HW_PINCTRL_MUXSEL6_BANK3_PIN12 __BITS(25,24)

sys/arch/arm/imx/imx23_pinctrlreg.h

795

#define HW_PINCTRL_MUXSEL6_BANK3_PIN11 __BITS(23,22)

sys/arch/arm/imx/imx23_pinctrlreg.h

796

#define HW_PINCTRL_MUXSEL6_BANK3_PIN10 __BITS(21,20)

sys/arch/arm/imx/imx23_pinctrlreg.h

797

#define HW_PINCTRL_MUXSEL6_BANK3_PIN09 __BITS(19,18)

sys/arch/arm/imx/imx23_pinctrlreg.h

798

#define HW_PINCTRL_MUXSEL6_BANK3_PIN08 __BITS(17,16)

sys/arch/arm/imx/imx23_pinctrlreg.h

799

#define HW_PINCTRL_MUXSEL6_BANK3_PIN07 __BITS(15,14)

sys/arch/arm/imx/imx23_pinctrlreg.h

80

#define HW_PINCTRL_MUXSEL0_BANK0_PIN03 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

800

#define HW_PINCTRL_MUXSEL6_BANK3_PIN06 __BITS(13,12)

sys/arch/arm/imx/imx23_pinctrlreg.h

801

#define HW_PINCTRL_MUXSEL6_BANK3_PIN05 __BITS(11,10)

sys/arch/arm/imx/imx23_pinctrlreg.h

802

#define HW_PINCTRL_MUXSEL6_BANK3_PIN04 __BITS(9,8)

sys/arch/arm/imx/imx23_pinctrlreg.h

803

#define HW_PINCTRL_MUXSEL6_BANK3_PIN03 __BITS(7,6)

sys/arch/arm/imx/imx23_pinctrlreg.h

804

#define HW_PINCTRL_MUXSEL6_BANK3_PIN02 __BITS(5,4)

sys/arch/arm/imx/imx23_pinctrlreg.h

805

#define HW_PINCTRL_MUXSEL6_BANK3_PIN01 __BITS(3,2)

sys/arch/arm/imx/imx23_pinctrlreg.h

806

#define HW_PINCTRL_MUXSEL6_BANK3_PIN00 __BITS(1,0)

sys/arch/arm/imx/imx23_pinctrlreg.h

81

#define HW_PINCTRL_MUXSEL0_BANK0_PIN02 __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

82

#define HW_PINCTRL_MUXSEL0_BANK0_PIN01 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

83

#define HW_PINCTRL_MUXSEL0_BANK0_PIN00 __BITS(1, 0)

sys/arch/arm/imx/imx23_pinctrlreg.h

912

#define HW_PINCTRL_MUXSEL7_RSRVD0 __BITS(31,12)

sys/arch/arm/imx/imx23_pinctrlreg.h

913

#define HW_PINCTRL_MUXSEL7_BANK3_PIN21 __BITS(11,10)

sys/arch/arm/imx/imx23_pinctrlreg.h

914

#define HW_PINCTRL_MUXSEL7_BANK3_PIN20 __BITS(9,8)

sys/arch/arm/imx/imx23_pinctrlreg.h

915

#define HW_PINCTRL_MUXSEL7_BANK3_PIN19 __BITS(7,6)

sys/arch/arm/imx/imx23_pinctrlreg.h

916

#define HW_PINCTRL_MUXSEL7_BANK3_PIN18 __BITS(5,4)

sys/arch/arm/imx/imx23_pinctrlreg.h

917

#define HW_PINCTRL_MUXSEL7_BANK3_PIN17 __BITS(3,2)

sys/arch/arm/imx/imx23_pinctrlreg.h

918

#define HW_PINCTRL_MUXSEL7_BANK3_PIN16 __BITS(1,0)

sys/arch/arm/imx/imx23_pinctrlreg.h

975

#define HW_PINCTRL_DRIVE2_RSRVD7 __BITS(31, 30)

sys/arch/arm/imx/imx23_pinctrlreg.h

976

#define HW_PINCTRL_DRIVE2_BANK0_PIN23_MA __BITS(29, 28)

sys/arch/arm/imx/imx23_pinctrlreg.h

977

#define HW_PINCTRL_DRIVE2_RSRVD6 __BITS(27, 26)

sys/arch/arm/imx/imx23_pinctrlreg.h

978

#define HW_PINCTRL_DRIVE2_BANK0_PIN22_MA __BITS(25, 24)

sys/arch/arm/imx/imx23_pinctrlreg.h

979

#define HW_PINCTRL_DRIVE2_RSRVD5 __BITS(23, 22)

sys/arch/arm/imx/imx23_pinctrlreg.h

980

#define HW_PINCTRL_DRIVE2_BANK0_PIN21_MA __BITS(21, 20)

sys/arch/arm/imx/imx23_pinctrlreg.h

981

#define HW_PINCTRL_DRIVE2_RSRVD4 __BITS(19, 18)

sys/arch/arm/imx/imx23_pinctrlreg.h

982

#define HW_PINCTRL_DRIVE2_BANK0_PIN20_MA __BITS(17, 16)

sys/arch/arm/imx/imx23_pinctrlreg.h

983

#define HW_PINCTRL_DRIVE2_RSRVD3 __BITS(15, 14)

sys/arch/arm/imx/imx23_pinctrlreg.h

984

#define HW_PINCTRL_DRIVE2_BANK0_PIN19_MA __BITS(13, 12)

sys/arch/arm/imx/imx23_pinctrlreg.h

985

#define HW_PINCTRL_DRIVE2_RSRVD2 __BITS(11, 10)

sys/arch/arm/imx/imx23_pinctrlreg.h

986

#define HW_PINCTRL_DRIVE2_BANK0_PIN18_MA __BITS(9, 8)

sys/arch/arm/imx/imx23_pinctrlreg.h

987

#define HW_PINCTRL_DRIVE2_RSRVD1 __BITS(7, 6)

sys/arch/arm/imx/imx23_pinctrlreg.h

988

#define HW_PINCTRL_DRIVE2_BANK0_PIN17_MA __BITS(5, 4)

sys/arch/arm/imx/imx23_pinctrlreg.h

989

#define HW_PINCTRL_DRIVE2_RSRVD0 __BITS(3, 2)

sys/arch/arm/imx/imx23_pinctrlreg.h

990

#define HW_PINCTRL_DRIVE2_BANK0_PIN16_MA __BITS(1, 0)

sys/arch/arm/imx/imx23_rtcreg.h

105

#define HW_RTC_ALARM_VALUE __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

115

#define HW_RTC_WATCHDOG_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

125

#define HW_RTC_PERSISTENT0_SPARE_ANALOG __BITS(31, 18)

sys/arch/arm/imx/imx23_rtcreg.h

128

#define HW_RTC_PERSISTENT0_LOWERBIAS __BITS(15, 14)

sys/arch/arm/imx/imx23_rtcreg.h

130

#define HW_RTC_PERSISTENT0_MSEC_RES __BITS(12, 8)

sys/arch/arm/imx/imx23_rtcreg.h

148

#define HW_RTC_PERSISTENT1_GENERAL __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

158

#define HW_RTC_PERSISTENT2_GENERAL __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

168

#define HW_RTC_PERSISTENT3_GENERAL __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

178

#define HW_RTC_PERSISTENT4_GENERAL __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

188

#define HW_RTC_PERSISTENT5_GENERAL __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

198

#define HW_RTC_DEBUG_RSVD0 __BITS(31, 2)

sys/arch/arm/imx/imx23_rtcreg.h

207

#define HW_RTC_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_rtcreg.h

208

#define HW_RTC_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_rtcreg.h

209

#define HW_RTC_VERSION_STEP __BITS(15, 9)

sys/arch/arm/imx/imx23_rtcreg.h

50

#define HW_RTC_CTRL_RSVD0 __BITS(29, 7)

sys/arch/arm/imx/imx23_rtcreg.h

72

#define HW_RTC_STAT_RSVD1 __BITS(26, 24)

sys/arch/arm/imx/imx23_rtcreg.h

85

#define HW_RTC_MILLISECONDS_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_rtcreg.h

95

#define HW_RTC_SECONDS_COUNT __BITS(31, 0)

sys/arch/arm/imx/imx23_timrotreg.h

109

#define HW_TIMROT_TIMCTRL1_RSRVD2 __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

112

#define HW_TIMROT_TIMCTRL1_RSRVD1 __BITS(13, 9)

sys/arch/arm/imx/imx23_timrotreg.h

116

#define HW_TIMROT_TIMCTRL1_PRESCALE __BITS(5, 4)

sys/arch/arm/imx/imx23_timrotreg.h

117

#define HW_TIMROT_TIMCTRL1_SELECT __BITS(3, 0)

sys/arch/arm/imx/imx23_timrotreg.h

124

#define HW_TIMROT_TIMCOUNT1_RUNNING_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

125

#define HW_TIMROT_TIMCOUNT1_FIXED_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_timrotreg.h

135

#define HW_TIMROT_TIMCTRL2_RSRVD2 __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

138

#define HW_TIMROT_TIMCTRL2_RSRVD1 __BITS(13, 9)

sys/arch/arm/imx/imx23_timrotreg.h

142

#define HW_TIMROT_TIMCTRL2_PRESCALE __BITS(5, 4)

sys/arch/arm/imx/imx23_timrotreg.h

150

#define HW_TIMROT_TIMCOUNT2_RUNNING_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

151

#define HW_TIMROT_TIMCOUNT2_FIXED_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_timrotreg.h

161

#define HW_TIMROT_TIMCTRL3_RSRVD2 __BITS(31, 20)

sys/arch/arm/imx/imx23_timrotreg.h

162

#define HW_TIMROT_TIMCTRL3_TEST_SIGNAL __BITS(19, 16)

sys/arch/arm/imx/imx23_timrotreg.h

165

#define HW_TIMROT_TIMCTRL3_RSRVD1 __BITS(13, 11)

sys/arch/arm/imx/imx23_timrotreg.h

171

#define HW_TIMROT_TIMCTRL3_PRESCALE __BITS(5, 4)

sys/arch/arm/imx/imx23_timrotreg.h

172

#define HW_TIMROT_TIMCTRL3_SELECT __BITS(3, 0)

sys/arch/arm/imx/imx23_timrotreg.h

179

#define HW_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

180

#define HW_TIMROT_TIMCOUNT3IHIGH_FIXED_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_timrotreg.h

187

#define HW_TIMROT_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_timrotreg.h

188

#define HW_TIMROT_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_timrotreg.h

189

#define HW_TIMROT_VERSION_STEP __BITS(15, 0)

sys/arch/arm/imx/imx23_timrotreg.h

55

#define HW_TIMROT_ROTCTRL_STATE __BITS(24, 22)

sys/arch/arm/imx/imx23_timrotreg.h

56

#define HW_TIMROT_ROTCTRL_DIVIDER __BITS(21, 16)

sys/arch/arm/imx/imx23_timrotreg.h

57

#define HW_TIMROT_ROTCTRL_RSRVD3 __BITS(15, 13)

sys/arch/arm/imx/imx23_timrotreg.h

59

#define HW_TIMROT_ROTCTRL_OVERSAMPLE __BITS(11, 10)

sys/arch/arm/imx/imx23_timrotreg.h

63

#define HW_TIMROT_ROTCTRL_SELECT_B __BITS(6, 4)

sys/arch/arm/imx/imx23_timrotreg.h

65

#define HW_TIMROT_ROTCTRL_SELECT_A __BITS(2, 0)

sys/arch/arm/imx/imx23_timrotreg.h

72

#define HW_TIMROT_ROTCOUNT_RSRVD1 __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

73

#define HW_TIMROT_ROTCOUNT_UPDOWN __BITS(15, 0)

sys/arch/arm/imx/imx23_timrotreg.h

83

#define HW_TIMROT_TIMCTRL0_RSRVD2 __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

86

#define HW_TIMROT_TIMCTRL0_RSRVD1 __BITS(13, 9)

sys/arch/arm/imx/imx23_timrotreg.h

90

#define HW_TIMROT_TIMCTRL0_PRESCALE __BITS(5, 4)

sys/arch/arm/imx/imx23_timrotreg.h

91

#define HW_TIMROT_TIMCTRL0_SELECT __BITS(3, 0)

sys/arch/arm/imx/imx23_timrotreg.h

98

#define HW_TIMROT_TIMCOUNT0_RUNNING_COUNT __BITS(31, 16)

sys/arch/arm/imx/imx23_timrotreg.h

99

#define HW_TIMROT_TIMCOUNT0_FIXED_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

130

#define HW_USBPHY_STATUS_RSVD4 __BITS(31, 11)

sys/arch/arm/imx/imx23_usbphyreg.h

136

#define HW_USBPHY_STATUS_RSVD1 __BITS(5, 4)

sys/arch/arm/imx/imx23_usbphyreg.h

138

#define HW_USBPHY_STATUS_RSVD0 __BITS(2, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

151

#define HW_USBPHY_DEBUG_SQUELCHRESETLENGTH __BITS(28, 25)

sys/arch/arm/imx/imx23_usbphyreg.h

153

#define HW_USBPHY_DEBUG_RSVD2 __BITS(23, 21)

sys/arch/arm/imx/imx23_usbphyreg.h

154

#define HW_USBPHY_DEBUG_SQUELCHRESETCOUNT __BITS(20, 16)

sys/arch/arm/imx/imx23_usbphyreg.h

155

#define HW_USBPHY_DEBUG_RSVD1 __BITS(15, 13)

sys/arch/arm/imx/imx23_usbphyreg.h

157

#define HW_USBPHY_DEBUG_TX2RXCOUNT __BITS(11, 8)

sys/arch/arm/imx/imx23_usbphyreg.h

158

#define HW_USBPHY_DEBUG_RSVD0 __BITS(7, 6)

sys/arch/arm/imx/imx23_usbphyreg.h

159

#define HW_USBPHY_DEBUG_ENHSTPULLDOWN __BITS(5, 4)

sys/arch/arm/imx/imx23_usbphyreg.h

160

#define HW_USBPHY_DEBUG_HSTPULLDOWN __BITS(3, 2)

sys/arch/arm/imx/imx23_usbphyreg.h

169

#define HW_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT __BITS(31, 26)

sys/arch/arm/imx/imx23_usbphyreg.h

170

#define HW_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT __BITS(25, 16)

sys/arch/arm/imx/imx23_usbphyreg.h

171

#define HW_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT __BITS(15, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

181

#define HW_USBPHY_DEBUG1_RSVD1 __BITS(31, 15)

sys/arch/arm/imx/imx23_usbphyreg.h

182

#define HW_USBPHY_DEBUG1_ENTAILADJVD __BITS(14, 13)

sys/arch/arm/imx/imx23_usbphyreg.h

184

#define HW_USBPHY_DEBUG1_RSVD0 __BITS(11, 4)

sys/arch/arm/imx/imx23_usbphyreg.h

185

#define HW_USBPHY_DEBUG1_DBG_ADDRESS __BITS(3, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

192

#define HW_USBPHY_VERSION_MAJOR __BITS(31, 24)

sys/arch/arm/imx/imx23_usbphyreg.h

193

#define HW_USBPHY_VERSION_MINOR __BITS(23, 16)

sys/arch/arm/imx/imx23_usbphyreg.h

194

#define HW_USBPHY_VERSION_STEP __BITS(15, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

204

#define HW_USBPHY_IP_RSVD1 __BITS(31, 25)

sys/arch/arm/imx/imx23_usbphyreg.h

205

#define HW_USBPHY_IP_DIV_SEL __BITS(24, 23)

sys/arch/arm/imx/imx23_usbphyreg.h

206

#define HW_USBPHY_IP_LFR_SEL __BITS(22, 21)

sys/arch/arm/imx/imx23_usbphyreg.h

207

#define HW_USBPHY_IP_CP_SEL __BITS(20, 19)

sys/arch/arm/imx/imx23_usbphyreg.h

211

#define HW_USBPHY_IP_RSVD0 __BITS(15, 3)

sys/arch/arm/imx/imx23_usbphyreg.h

48

#define HW_USBPHY_PWD_RSVD2 __BITS(31, 21)

sys/arch/arm/imx/imx23_usbphyreg.h

53

#define HW_USBPHY_PWD_RSVD1 __BITS(16, 13)

sys/arch/arm/imx/imx23_usbphyreg.h

57

#define HW_USBPHY_PWD_RSVD0 __BITS(9, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

67

#define HW_USBPHY_TX_RSVD5 __BITS(31, 29)

sys/arch/arm/imx/imx23_usbphyreg.h

68

#define HW_USBPHY_TX_USBPHY_TX_EDGECTRL __BITS(28, 26)

sys/arch/arm/imx/imx23_usbphyreg.h

71

#define HW_USBPHY_TX_RSVD4 __BITS(23, 22)

sys/arch/arm/imx/imx23_usbphyreg.h

74

#define HW_USBPHY_TX_TXCAL45DP __BITS(19, 16)

sys/arch/arm/imx/imx23_usbphyreg.h

75

#define HW_USBPHY_TX_RSVD2 __BITS(15, 14)

sys/arch/arm/imx/imx23_usbphyreg.h

78

#define HW_USBPHY_TX_TXCAL45DN __BITS(11, 8)

sys/arch/arm/imx/imx23_usbphyreg.h

79

#define HW_USBPHY_TX_RSVD0 __BITS(7, 3)

sys/arch/arm/imx/imx23_usbphyreg.h

80

#define HW_USBPHY_TX_D_CAL __BITS(3, 0)

sys/arch/arm/imx/imx23_usbphyreg.h

90

#define HW_USBPHY_RX_RSVD2 __BITS(31, 23)

sys/arch/arm/imx/imx23_usbphyreg.h

92

#define HW_USBPHY_RX_RSVD1 __BITS(21, 7)

sys/arch/arm/imx/imx23_usbphyreg.h

93

#define HW_USBPHY_RX_DISCONADJ __BITS(6, 4)

sys/arch/arm/imx/imx23_usbphyreg.h

95

#define HW_USBPHY_RX_ENVADJ __BITS(2, 0)

sys/arch/arm/imx/imx51_ccm.c

521

mfn = (int32_t)(__BITS(31,27) | dp_mfn);

sys/arch/arm/imx/imx51_ccmreg.h

103

#define CDCDR_PERIPH_CLK2 __BITS(29, 27)

sys/arch/arm/imx/imx51_ccmreg.h

106

#define CSCDR2_ECSPI_CLK_PRED __BITS(27, 25)

sys/arch/arm/imx/imx51_ccmreg.h

107

#define CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)

sys/arch/arm/imx/imx51_ccmreg.h

114

#define CDCR_PERIPH_CLK_DVFS_PODF __BITS(1, 0)

sys/arch/arm/imx/imx51_ccmreg.h

140

#define CLKSEQ_ELCDIF_PIX_CLK __BITS(15, 14)

sys/arch/arm/imx/imx51_ccmreg.h

141

#define CLKSEQ_EPDC_PIX_CLK __BITS(13, 12)

sys/arch/arm/imx/imx51_ccmreg.h

142

#define CLKSEQ_MSHC_XMSCKI_CLK __BITS(11, 10)

sys/arch/arm/imx/imx51_ccmreg.h

143

#define CLKSEQ_BCH_CLK __BITS(9, 8)

sys/arch/arm/imx/imx51_ccmreg.h

144

#define CLKSEQ_GPMI_CLK __BITS(7, 6)

sys/arch/arm/imx/imx51_ccmreg.h

145

#define CLKSEQ_EPDC_AXI_CLK __BITS(5, 4)

sys/arch/arm/imx/imx51_ccmreg.h

146

#define CLKSEQ_DISPLAY_AXI_CLK __BITS(3, 2)

sys/arch/arm/imx/imx51_ccmreg.h

147

#define CLKSEQ_SYS_CLK __BITS(1, 0)

sys/arch/arm/imx/imx51_ccmreg.h

153

#define EPDC_PIX_CLKGATE __BITS(31, 30)

sys/arch/arm/imx/imx51_ccmreg.h

158

#define EPDC_PIX_CLK_PRED __BITS(13, 12)

sys/arch/arm/imx/imx51_ccmreg.h

159

#define EPDC_PIX_CLK_PODF __BITS(11, 0)

sys/arch/arm/imx/imx51_ccmreg.h

161

#define EPDC_AXI_CLKGATE __BITS(31, 30)

sys/arch/arm/imx/imx51_ccmreg.h

167

#define EPDC_ASM_SLOW_DIV __BITS(8, 6)

sys/arch/arm/imx/imx51_ccmreg.h

168

#define EPDC_AXI_DIV __BITS(5, 0)

sys/arch/arm/imx/imx51_ccmreg.h

43

#define CCSR_STEP_SEL __BITS(8, 7)

sys/arch/arm/imx/imx51_ccmreg.h

44

#define CCSR_PLL2_DIV_PODF __BITS(6, 5)

sys/arch/arm/imx/imx51_ccmreg.h

45

#define CCSR_PLL3_DIV_PODF __BITS(4, 3)

sys/arch/arm/imx/imx51_ccmreg.h

52

#define CBCDR_DDR_CLK_PODF __BITS(29, 27)

sys/arch/arm/imx/imx51_ccmreg.h

54

#define CBCDR_PERIPH_CLK_SEL __BITS(26, 25)

sys/arch/arm/imx/imx51_ccmreg.h

59

#define CBCDR_EMI_SLOW_PODF __BITS(24, 22)

sys/arch/arm/imx/imx51_ccmreg.h

60

#define CBCDR_AXI_B_PODF __BITS(21, 19)

sys/arch/arm/imx/imx51_ccmreg.h

61

#define CBCDR_AXI_A_PODF __BITS(18, 16)

sys/arch/arm/imx/imx51_ccmreg.h

62

#define CBCDR_NFC_PODF __BITS(15, 13)

sys/arch/arm/imx/imx51_ccmreg.h

63

#define CBCDR_AHB_PODF __BITS(12, 10)

sys/arch/arm/imx/imx51_ccmreg.h

64

#define CBCDR_IPG_PODF __BITS(9, 8)

sys/arch/arm/imx/imx51_ccmreg.h

65

#define CBCDR_PERCLK_PRED1 __BITS(7, 6)

sys/arch/arm/imx/imx51_ccmreg.h

66

#define CBCDR_PERCLK_PRED2 __BITS(5, 3)

sys/arch/arm/imx/imx51_ccmreg.h

67

#define CBCDR_PERCLK_PODF __BITS(2, 0)

sys/arch/arm/imx/imx51_ccmreg.h

69

#define CBCMR_PERIPH_APM_SEL __BITS(13, 12)

sys/arch/arm/imx/imx51_ccmreg.h

70

#define CBCMR_IPU_HSP_CLK_SEL __BITS(7, 6)

sys/arch/arm/imx/imx51_ccmreg.h

74

#define CSCMR1_UART_CLK_SEL __BITS(25, 24)

sys/arch/arm/imx/imx51_ccmreg.h

76

#define CSCMR1_ESDHC1_CLK_SEL __BITS(22, 21)

sys/arch/arm/imx/imx51_ccmreg.h

79

#define CSCMR1_ESDHC3_CLK_SEL __BITS(18, 16)

sys/arch/arm/imx/imx51_ccmreg.h

81

#define CSCMR1_ESDHC1_CLK_SEL __BITS(21, 20)

sys/arch/arm/imx/imx51_ccmreg.h

84

#define CSCMR1_ESDHC2_CLK_SEL __BITS(17, 16)

sys/arch/arm/imx/imx51_ccmreg.h

86

#define CSCMR1_CSPI_CLK_SEL __BITS(5, 4)

sys/arch/arm/imx/imx51_ccmreg.h

90

#define CSCDR1_ESDHC3_CLK_PRED __BITS(24, 22)

sys/arch/arm/imx/imx51_ccmreg.h

91

#define CSCDR1_ESDHC3_CLK_PODF __BITS(21, 19)

sys/arch/arm/imx/imx51_ccmreg.h

93

#define CSCDR1_ESDHC2_CLK_PRED __BITS(24, 22)

sys/arch/arm/imx/imx51_ccmreg.h

94

#define CSCDR1_ESDHC2_CLK_PODF __BITS(21, 19)

sys/arch/arm/imx/imx51_ccmreg.h

96

#define CSCDR1_ESDHC1_CLK_PRED __BITS(18, 16)

sys/arch/arm/imx/imx51_ccmreg.h

97

#define CSCDR1_ESDHC1_CLK_PODF __BITS(13, 11)

sys/arch/arm/imx/imx51_ccmreg.h

98

#define CSCDR1_UART_CLK_PRED __BITS(5, 3)

sys/arch/arm/imx/imx51_ccmreg.h

99

#define CSCDR1_UART_CLK_PODF __BITS(2, 0)

sys/arch/arm/imx/imx51_dpllreg.h

38

#define DP_CTL_REF_CLK_SEL __BITS(8,9)

sys/arch/arm/imx/imx51_dpllreg.h

45

#define DP_OP_PDF __BITS(3, 0)

sys/arch/arm/imx/imx51_dpllreg.h

46

#define DP_OP_MFI __BITS(7, 4)

sys/arch/arm/imx/imx51_ipuv3reg.h

102

#define CM_DISP_GEN_MCU_T __BITS(18, 21)

sys/arch/arm/imx/imx51_ipuv3reg.h

110

#define CM_MEM_EN __BITS(22, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

258

#define DI_GENERAL_DISP_Y_SEL __BITS(30, 28)

sys/arch/arm/imx/imx51_ipuv3reg.h

259

#define DI_GENERAL_CLOCK_STOP_MODE __BITS(27, 24)

sys/arch/arm/imx/imx51_ipuv3reg.h

264

#define DI_GENERAL_WATCHDOG_MODE __BITS(19, 18)

sys/arch/arm/imx/imx51_ipuv3reg.h

266

#define DI_GENERAL_SYNC_COUNT_SEL __BITS(15, 12)

sys/arch/arm/imx/imx51_ipuv3reg.h

273

#define DI_BS_CLKGEN0_OFFSET __BITS(24, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

274

#define DI_BS_CLKGEN0_PERIOD __BITS(11, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

276

#define DI_BS_CLKGEN1_DOWN __BITS(24, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

277

#define DI_BS_CLKGEN1_UP __BITS(8, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

279

#define DI_SW_GEN0_RUN_VAL __BITS(30, 19)

sys/arch/arm/imx/imx51_ipuv3reg.h

280

#define DI_SW_GEN0_RUN_RESOL __BITS(18, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

281

#define DI_SW_GEN0_OFFSET_VAL __BITS(14, 3)

sys/arch/arm/imx/imx51_ipuv3reg.h

282

#define DI_SW_GEN0_OFFSET_RESOL __BITS( 2, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

287

#define DI_SW_GEN1_CNT_POL_GEN_EN __BITS(30, 29)

sys/arch/arm/imx/imx51_ipuv3reg.h

289

#define DI_SW_GEN1_CNT_CLR_SEL __BITS(27, 25)

sys/arch/arm/imx/imx51_ipuv3reg.h

290

#define DI_SW_GEN1_CNT_DOWN __BITS(24, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

291

#define DI_SW_GEN1_CNT_POL_TRIG_SEL __BITS(14, 12)

sys/arch/arm/imx/imx51_ipuv3reg.h

292

#define DI_SW_GEN1_CNT_POL_CLR_SEL __BITS(11, 9)

sys/arch/arm/imx/imx51_ipuv3reg.h

293

#define DI_SW_GEN1_CNT_UP __BITS( 8, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

301

#define DI_SYNC_AS_GEN_VSYNC_SEL __BITS(15, 13)

sys/arch/arm/imx/imx51_ipuv3reg.h

302

#define DI_SYNC_AS_GEN_SYNC_START __BITS(11, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

304

#define DI_DW_GEN_ACCESS_SIZE __BITS(31, 24)

sys/arch/arm/imx/imx51_ipuv3reg.h

305

#define DI_DW_GEN_COMPONNENT_SIZE __BITS(23, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

306

#define DI_DW_GEN_PIN(n) __BITS((((n) - 11) * 2) + 1, \

sys/arch/arm/imx/imx51_ipuv3reg.h

309

#define DI_DW_SET_DOWN __BITS(24, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

310

#define DI_DW_SET_UP __BITS(8, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

312

#define DI_STP_REP(n) (__BITS(11, 0) << (((n - 1) % 2) * 16))

sys/arch/arm/imx/imx51_ipuv3reg.h

47

#define CM_CONF_IPU_DIAGBUS_MODE __BITS(20, 16)

sys/arch/arm/imx/imx51_ipuv3reg.h

487

#define DMFC_RD_CHAN_PPW_C __BITS(25,24)

sys/arch/arm/imx/imx51_ipuv3reg.h

488

#define DMFC_RD_CHAN_WM_DR_0 __BITS(23,21)

sys/arch/arm/imx/imx51_ipuv3reg.h

489

#define DMFC_RD_CHAN_WM_SET_0 __BITS(20,18)

sys/arch/arm/imx/imx51_ipuv3reg.h

491

#define DMFC_RD_CHAN_BURST_SIZE_0 __BITS( 7, 6)

sys/arch/arm/imx/imx51_ipuv3reg.h

493

#define DMFC_WR_CHAN_BUSRT_SIZE_2C __BITS(31,30)

sys/arch/arm/imx/imx51_ipuv3reg.h

494

#define DMFC_WR_CHAN_FIFO_SIZE_2C __BITS(29,27)

sys/arch/arm/imx/imx51_ipuv3reg.h

495

#define DMFC_WR_CHAN_ST_ADDR_2C __BITS(26,24)

sys/arch/arm/imx/imx51_ipuv3reg.h

496

#define DMFC_WR_CHAN_BURST_SIZE_1C __BITS(23,22)

sys/arch/arm/imx/imx51_ipuv3reg.h

497

#define DMFC_WR_CHAN_FIFO_SIZE_1C __BITS(21,19)

sys/arch/arm/imx/imx51_ipuv3reg.h

498

#define DMFC_WR_CHAN_ST_ADDR_1C __BITS(18,16)

sys/arch/arm/imx/imx51_ipuv3reg.h

499

#define DMFC_WR_CHAN_BURST_SIZE_2 __BITS(15,14)

sys/arch/arm/imx/imx51_ipuv3reg.h

500

#define DMFC_WR_CHAN_FIFO_SIZE_2 __BITS(13,11)

sys/arch/arm/imx/imx51_ipuv3reg.h

501

#define DMFC_WR_CHAN_ST_ADDR_2 __BITS(10, 8)

sys/arch/arm/imx/imx51_ipuv3reg.h

502

#define DMFC_WR_CHAN_BURST_SIZE_1 __BITS( 7, 6)

sys/arch/arm/imx/imx51_ipuv3reg.h

503

#define DMFC_WR_CHAN_FIFO_SIZE_1 __BITS( 5, 3)

sys/arch/arm/imx/imx51_ipuv3reg.h

504

#define DMFC_WR_CHAN_ST_ADDR_1 __BITS( 2, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

506

#define DMFC_WR_CHAN_DEF_WM_CLR_2C __BITS(31,29)

sys/arch/arm/imx/imx51_ipuv3reg.h

507

#define DMFC_WR_CHAN_DEF_WM_SET_2C __BITS(28,26)

sys/arch/arm/imx/imx51_ipuv3reg.h

509

#define DMFC_WR_CHAN_DEF_WM_CLR_1C __BITS(23,21)

sys/arch/arm/imx/imx51_ipuv3reg.h

510

#define DMFC_WR_CHAN_DEF_WM_SET_1C __BITS(20,18)

sys/arch/arm/imx/imx51_ipuv3reg.h

512

#define DMFC_WR_CHAN_DEF_WM_CLR_2 __BITS(15,13)

sys/arch/arm/imx/imx51_ipuv3reg.h

513

#define DMFC_WR_CHAN_DEF_WM_SET_2 __BITS(12,10)

sys/arch/arm/imx/imx51_ipuv3reg.h

515

#define DMFC_WR_CHAN_DEF_WM_CLR_1 __BITS( 7, 5)

sys/arch/arm/imx/imx51_ipuv3reg.h

516

#define DMFC_WR_CHAN_DEF_WM_SET_1 __BITS( 3, 2)

sys/arch/arm/imx/imx51_ipuv3reg.h

519

#define DMFC_DP_CHAN_BUSRT_SIZE_6F __BITS(31,30)

sys/arch/arm/imx/imx51_ipuv3reg.h

520

#define DMFC_DP_CHAN_FIFO_SIZE_6F __BITS(29,27)

sys/arch/arm/imx/imx51_ipuv3reg.h

521

#define DMFC_DP_CHAN_ST_ADDR_6F __BITS(26,24)

sys/arch/arm/imx/imx51_ipuv3reg.h

522

#define DMFC_DP_CHAN_BURST_SIZE_6B __BITS(23,22)

sys/arch/arm/imx/imx51_ipuv3reg.h

523

#define DMFC_DP_CHAN_FIFO_SIZE_6B __BITS(21,19)

sys/arch/arm/imx/imx51_ipuv3reg.h

524

#define DMFC_DP_CHAN_ST_ADDR_6B __BITS(18,16)

sys/arch/arm/imx/imx51_ipuv3reg.h

525

#define DMFC_DP_CHAN_BURST_SIZE_5F __BITS(15,14)

sys/arch/arm/imx/imx51_ipuv3reg.h

526

#define DMFC_DP_CHAN_FIFO_SIZE_5F __BITS(13,11)

sys/arch/arm/imx/imx51_ipuv3reg.h

527

#define DMFC_DP_CHAN_ST_ADDR_5F __BITS(10, 8)

sys/arch/arm/imx/imx51_ipuv3reg.h

528

#define DMFC_DP_CHAN_BURST_SIZE_5B __BITS( 7, 6)

sys/arch/arm/imx/imx51_ipuv3reg.h

529

#define DMFC_DP_CHAN_FIFO_SIZE_5B __BITS( 5, 3)

sys/arch/arm/imx/imx51_ipuv3reg.h

530

#define DMFC_DP_CHAN_ST_ADDR_5B __BITS( 2, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

532

#define DMFC_DP_CHAN_DEF_WM_CLR_6F __BITS(31,29)

sys/arch/arm/imx/imx51_ipuv3reg.h

533

#define DMFC_DP_CHAN_DEF_WM_SET_6F __BITS(28,26)

sys/arch/arm/imx/imx51_ipuv3reg.h

535

#define DMFC_DP_CHAN_DEF_WM_CLR_6B __BITS(23,21)

sys/arch/arm/imx/imx51_ipuv3reg.h

536

#define DMFC_DP_CHAN_DEF_WM_SET_6B __BITS(20,18)

sys/arch/arm/imx/imx51_ipuv3reg.h

538

#define DMFC_DP_CHAN_DEF_WM_CLR_5F __BITS(15,13)

sys/arch/arm/imx/imx51_ipuv3reg.h

539

#define DMFC_DP_CHAN_DEF_WM_SET_5F __BITS(12,10)

sys/arch/arm/imx/imx51_ipuv3reg.h

541

#define DMFC_DP_CHAN_DEF_WM_CLR_5B __BITS( 7, 5)

sys/arch/arm/imx/imx51_ipuv3reg.h

542

#define DMFC_DP_CHAN_DEF_WM_SET_5B __BITS( 4, 2)

sys/arch/arm/imx/imx51_ipuv3reg.h

554

#define DMFC_GENERAL1_WM_CLR_9 __BITS(15,13)

sys/arch/arm/imx/imx51_ipuv3reg.h

555

#define DMFC_GENERAL1_WM_SET_9 __BITS(12,10)

sys/arch/arm/imx/imx51_ipuv3reg.h

556

#define DMFC_GENERAL1_BURST_SIZE_9 __BITS( 6, 5)

sys/arch/arm/imx/imx51_ipuv3reg.h

557

#define DMFC_GENERAL1_DCDP_SYNC_PR __BITS( 1, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

563

#define DMFC_GENERAL2_FRAME_HEIGHT_RD __BITS(28,16)

sys/arch/arm/imx/imx51_ipuv3reg.h

564

#define DMFC_GENERAL2_FRAME_WIDTH_RD __BITS(12, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

566

#define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD __BITS(31,19)

sys/arch/arm/imx/imx51_ipuv3reg.h

567

#define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD __BITS(18, 6)

sys/arch/arm/imx/imx51_ipuv3reg.h

568

#define DMFC_IC_CTRL_IC_PPW_C __BITS( 5, 4)

sys/arch/arm/imx/imx51_ipuv3reg.h

569

#define DMFC_IC_CTRL_IC_IN_PORT __BITS( 2, 0)

sys/arch/arm/imx/imx51_ipuv3reg.h

581

#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT __BITS(31,29)

sys/arch/arm/imx/imx51_ipuv3reg.h

582

#define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT __BITS(28,26)

sys/arch/arm/imx/imx51_ipuv3reg.h

584

#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT __BITS(23,21)

sys/arch/arm/imx/imx51_ipuv3reg.h

585

#define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT __BITS(20,18)

sys/arch/arm/imx/imx51_ipuv3reg.h

587

#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT __BITS( 7, 5)

sys/arch/arm/imx/imx51_ipuv3reg.h

588

#define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT __BITS( 4, 2)

sys/arch/arm/imx/imx51reg.h

180

#define USBCTRL_OSIC __BITS(29,30) /* OTG Serial interface configuration */

sys/arch/arm/imx/imx51reg.h

182

#define USBCTRL_OBPAL __BITS(25,26) /* OTG Bypass value */

sys/arch/arm/imx/imx51reg.h

190

#define USBCTRL_H1SIC __BITS(13,14) /* Host1 serial interface config */

sys/arch/arm/imx/imx51reg.h

193

#define USBCTRL_H1BPVAL __BITS(9,10) /* Host1 bypass value */

sys/arch/arm/imx/imx51reg.h

203

#define PHYCTRL0_VCONTROL __BITS(27,30)

sys/arch/arm/imx/imx51reg.h

208

#define PHYCTRL0_VSTATUS __BITS(15,22)

sys/arch/arm/imx/imx51reg.h

223

#define PHYCTRL1_PLLDIVVALUE_MASK __BITS(0,1)

sys/arch/arm/imx/imx51reg.h

298

#define PAD_CTL_PUS_MASK __BITS(5, 4)

sys/arch/arm/imx/imx51reg.h

304

#define PAD_CTL_DSE_MASK __BITS(2, 1)

sys/arch/arm/imx/imxcspireg.h

35

#define CSPI_IMX31_CON_CS __BITS(25, 24)

sys/arch/arm/imx/imxcspireg.h

36

#define CSPI_IMX31_CON_DRCTL __BITS(21, 20)

sys/arch/arm/imx/imxcspireg.h

37

#define CSPI_IMX31_CON_BITCOUNT __BITS(12, 8)

sys/arch/arm/imx/imxcspireg.h

38

#define CSPI_IMX35_CON_CS __BITS(13, 12)

sys/arch/arm/imx/imxcspireg.h

39

#define CSPI_IMX35_CON_DRCTL __BITS( 9, 8)

sys/arch/arm/imx/imxcspireg.h

40

#define CSPI_IMX35_CON_BITCOUNT __BITS(31, 20)

sys/arch/arm/imx/imxcspireg.h

41

#define CSPI_CON_DIV __BITS(18, 16)

sys/arch/arm/imx/imxecspireg.h

35

#define ECSPI_CON_BITCOUNT __BITS(31,20)

sys/arch/arm/imx/imxecspireg.h

36

#define ECSPI_CON_CS __BITS(19,18)

sys/arch/arm/imx/imxecspireg.h

37

#define ECSPI_CON_DRCTL __BITS(17,16)

sys/arch/arm/imx/imxecspireg.h

38

#define ECSPI_CON_PREDIV __BITS(15,12) /* PRE DIVIDER */

sys/arch/arm/imx/imxecspireg.h

39

#define ECSPI_CON_DIV __BITS(11, 8) /* POST DIVIDER */

sys/arch/arm/imx/imxecspireg.h

40

#define ECSPI_CON_MODE __BITS( 7, 4) /* MODE */

sys/arch/arm/imx/imxecspireg.h

46

#define ECSPI_CONFIG_HT_LEN __BITS(28,24) /* HT LENGTH */

sys/arch/arm/imx/imxecspireg.h

47

#define ECSPI_CONFIG_SCLK_CTL __BITS(23,20) /* SCLK CTL */

sys/arch/arm/imx/imxecspireg.h

48

#define ECSPI_CONFIG_DATA_CTL __BITS(19,16) /* DATA CTL */

sys/arch/arm/imx/imxecspireg.h

49

#define ECSPI_CONFIG_SSB_POL __BITS(15,12) /* SSB POL */

sys/arch/arm/imx/imxecspireg.h

50

#define ECSPI_CONFIG_SSB_CTL __BITS(11, 8) /* SSB CTL */

sys/arch/arm/imx/imxecspireg.h

51

#define ECSPI_CONFIG_SCLK_POL __BITS( 7, 4) /* SCLK POL */

sys/arch/arm/imx/imxecspireg.h

52

#define ECSPI_CONFIG_SCLK_PHA __BITS( 3, 0) /* SCLK PHA */

sys/arch/arm/imx/imxecspireg.h

54

#define ECSPI_INTR_ALL_EN __BITS( 7, 0) /* All Interrupts Enabled */

sys/arch/arm/imx/imxepitreg.h

35

#define EPITCR_PRESCALER __BITS(4,15)

sys/arch/arm/imx/imxepitreg.h

42

#define EPITCR_OM __BITS(22,23)

sys/arch/arm/imx/imxepitreg.h

44

#define EPITCR_CLKSRC_MASK __BITS(25, EPITCR_CLKSRC_SHIFT)

sys/arch/arm/imx/imxpciereg.h

122

#define PCIE_PL_PFLR_LOW_POWER_ENTRANCE_COUNT __BITS(31, 24)

sys/arch/arm/imx/imxpciereg.h

123

#define PCIE_PL_PFLR_LINK_STATE __BITS(21, 16)

sys/arch/arm/imx/imxpciereg.h

125

#define PCIE_PL_PFLR_LINK_NUMBER __BITS(7, 0)

sys/arch/arm/imx/imxpciereg.h

128

#define PCIE_PL_PLCR_LINK_MODE_ENABLE __BITS(21, 16)

sys/arch/arm/imx/imxpciereg.h

135

#define PCIE_PL_DEBUG0_XMLH_LTSSM_STATE __BITS(0, 5)

sys/arch/arm/imx/imxpciereg.h

159

#define PCIE_PL_G2CR_PREDETERMINED_NUMBER_OF_LANES __BITS(16, 8)

sys/arch/arm/imx/imxpciereg.h

162

#define PCIE_PL_PHY_STATUS_DATA __BITS(0, 15)

sys/arch/arm/imx/imxpciereg.h

168

#define PCIE_PL_PHY_CTRL_DATA __BITS(0, 15)

sys/arch/arm/imx/imxpciereg.h

184

#define PCIE_PL_IATURC1_FUNC __BITS(22, 20)

sys/arch/arm/imx/imxpciereg.h

185

#define PCIE_PL_IATURC1_AT __BITS(17, 16)

sys/arch/arm/imx/imxpciereg.h

186

#define PCIE_PL_IATURC1_ATTR __BITS(10, 9)

sys/arch/arm/imx/imxpciereg.h

188

#define PCIE_PL_IATURC1_TC __BITS(7, 5)

sys/arch/arm/imx/imxpciereg.h

189

#define PCIE_PL_IATURC1_TYPE __BITS(4, 0)

sys/arch/arm/imx/imxpciereg.h

235

#define MPLL_MULTIPLIER __BITS(8, 2)

sys/arch/arm/imx/imxpciereg.h

86

#define PCIE_RC_LCR_MAX_LINK_SPEEDS __BITS(3, 0)

sys/arch/arm/imx/imxpciereg.h

90

#define PCIE_RC_LCSR_LINK_SPEED __BITS(19, 16)

sys/arch/arm/imx/imxpwmreg.h

33

#define PWM_CR_FWM __BITS(27, 26)

sys/arch/arm/imx/imxpwmreg.h

40

#define PWM_CR_POUTC __BITS(19, 18)

sys/arch/arm/imx/imxpwmreg.h

41

#define PWM_CR_CLKSRC __BITS(17, 16)

sys/arch/arm/imx/imxpwmreg.h

45

#define PWM_CR_PRESCALER __BITS(15, 4)

sys/arch/arm/imx/imxpwmreg.h

47

#define PWM_CR_REPEAT __BITS(2, 1)

sys/arch/arm/imx/imxpwmreg.h

54

#define PWM_SR_FIFOAV __BITS(2, 0)

sys/arch/arm/imx/imxpwmreg.h

60

#define PWM_SAR_SAMPLE __BITS(15, 0)

sys/arch/arm/imx/imxpwmreg.h

62

#define PWM_PR_PERIOD __BITS(15, 0)

sys/arch/arm/imx/imxpwmreg.h

64

#define PWM_CNR_COUNT __BITS(15, 0)

sys/arch/arm/imx/imxsnvsreg.h

50

#define SNVS_LPCR_ON_TIME __BITS(21, 20)

sys/arch/arm/imx/imxsnvsreg.h

51

#define SNVS_LPCR_DEBOUNCE __BITS(19, 18)

sys/arch/arm/imx/imxsnvsreg.h

52

#define SNVS_LPCR_BTN_PRESS_TIME __BITS(17, 16)

sys/arch/arm/imx/imxsnvsreg.h

53

#define SNVS_LPCR_LPCALB_VAL __BITS(14, 10)

sys/arch/arm/imx/imxsnvsreg.h

70

#define SNVS_LPSRTCMR_SRTC __BITS(14, 0)

sys/arch/arm/imx/imxsnvsreg.h

74

#define SNVS_LPSMCMR_MC_ERA_BIT __BITS(31, 16)

sys/arch/arm/imx/imxsnvsreg.h

75

#define SNVS_LPSMCMR_MON_COUNTER __BITS(15, 0)

sys/arch/arm/imx/imxsnvsreg.h

79

#define SNVS_HPVIDR1_IP_ID __BITS(31, 16)

sys/arch/arm/imx/imxsnvsreg.h

80

#define SNVS_HPVIDR1_MAJOR_REV __BITS(15, 8)

sys/arch/arm/imx/imxsnvsreg.h

81

#define SNVS_HPVIDR1_MINOR_REV __BITS(7, 0)

sys/arch/arm/imx/imxsnvsreg.h

83

#define SNVS_HPVIDR2_IP_ERA __BITS(31, 24)

sys/arch/arm/imx/imxsnvsreg.h

84

#define SNVS_HPVIDR2_INTG_OPT __BITS(23, 16)

sys/arch/arm/imx/imxsnvsreg.h

85

#define SNVS_HPVIDR2_ECO_REV __BITS(15, 8)

sys/arch/arm/imx/imxsnvsreg.h

86

#define SNVS_HPVIDR2_CONFIG_OPT __BITS(7, 0)

sys/arch/arm/imx/imxuartreg.h

112

#define IMX_UCR2_RTEC __BITS(10,9) /* rw */

sys/arch/arm/imx/imxuartreg.h

136

#define IMX_UCR3_DPEC __BITS(15,14) /* rw */

sys/arch/arm/imx/imxuartreg.h

151

#define IMX_UCR4_CTSTL __BITS(15,10) /* rw */

sys/arch/arm/imx/imxuartreg.h

157

#define IMX_UFCR_RXTL __BITS(5,IMX_UFCR_RXTL_SHIFT) /* rw */

sys/arch/arm/imx/imxuartreg.h

160

#define IMX_UFCR_RFDIV __BITS(9,IMX_UFCR_RFDIV_SHIFT) /* rw */

sys/arch/arm/imx/imxuartreg.h

162

#define IMX_UFCR_TXTL __BITS(15,IMX_UFCR_TXTL_SHIFT) /* rw */

sys/arch/arm/imx/imxuartreg.h

170

#define IMX_USR1_RESV __BITS(3,0)

sys/arch/arm/imx/imxuartreg.h

207

#define IMX_UESC_ESC_CHAR __BITS(7,0) /* rw */

sys/arch/arm/imx/imxuartreg.h

208

#define IMX_UESC_RESV __BITS(15,8)

sys/arch/arm/imx/imxuartreg.h

213

#define IMX_UTIM_TIM __BITS(11,0) /* rw */

sys/arch/arm/imx/imxuartreg.h

214

#define IMX_UTIM_RESV __BITS(15,12)

sys/arch/arm/imx/imxuartreg.h

219

#define IMX_UBIR_INC __BITS(15,0) /* rw */

sys/arch/arm/imx/imxuartreg.h

224

#define IMX_UBMR_MOD __BITS(15,0) /* rw */

sys/arch/arm/imx/imxuartreg.h

229

#define IMX_UBRC_BCNT __BITS(15,0) /* ro */

sys/arch/arm/imx/imxuartreg.h

234

#define IMX_ONEMS_ONEMS __BITS(15,0) /* rw */

sys/arch/arm/imx/imxuartreg.h

240

#define IMX_UTS_RESVa __BITS(2,1)

sys/arch/arm/imx/imxuartreg.h

245

#define IMX_UTS_RESVb __BITS(8,7)

sys/arch/arm/imx/imxuartreg.h

251

#define IMX_UTS_RESVc __BITS(15,14)

sys/arch/arm/imx/imxuartreg.h

66

#define IMX_URXD_RX_DATA __BITS(7,0) /* ro */

sys/arch/arm/imx/imxuartreg.h

67

#define IMX_URXD_RESV __BITS(9,8) /* ro */

sys/arch/arm/imx/imxuartreg.h

78

#define IMX_UTXD_TX_DATA __BITS(7,0) /* wo */

sys/arch/arm/imx/imxuartreg.h

79

#define IMX_UTXD_RESV __BITS(15,8)

sys/arch/arm/imx/imxuartreg.h

94

#define IMX_UCR1_ICD __BITS(11,10) /* rw */

sys/arch/arm/imx/imxusbreg.h

108

#define PORTSC_PSPD __BITS(26,27) /* port speed (RO) */

sys/arch/arm/imx/imxusbreg.h

32

#define IMXUSB_ID_ID __BITS(5,0)

sys/arch/arm/imx/imxusbreg.h

33

#define IMXUSB_ID_REVISION __BITS(23,16)

sys/arch/arm/imx/imxusbreg.h

37

#define HWHOST_NPORT __BITS(3,1)

sys/arch/arm/imx/imxusbreg.h

40

#define HWDEVICE_DEVEP __BITS(5,1)

sys/arch/arm/imx/imxusbreg.h

51

#define ULPI_PORT __BITS(26,24)

sys/arch/arm/imx/imxusbreg.h

52

#define ULPI_ADDR __BITS(23,16)

sys/arch/arm/imx/imxusbreg.h

53

#define ULPI_DATRD __BITS(15,8)

sys/arch/arm/imx/imxusbreg.h

54

#define ULPI_DATWR __BITS(7,0)

sys/arch/arm/imx/imxusbreg.h

88

#define USBMODE_CM __BITS(1,0) /* Controller mode */

sys/arch/arm/imx/imxusbreg.h

97

#define PORTSC_PTS __BITS(31,30)

sys/arch/arm/imx/imxwdogreg.h

64

#define WCR_WT __BITS(15, 8)

sys/arch/arm/imx/imxwdogreg.h

86

#define WICR_WICT __BITS(7,0) /* interrupt count timeout */

sys/arch/arm/include/armreg.h

457

#define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */

sys/arch/arm/include/armreg.h

458

#define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */

sys/arch/arm/include/armreg.h

459

#define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */

sys/arch/arm/include/armreg.h

489

#define PMCR_N __BITS(15,11)

sys/arch/arm/include/armreg.h

495

#define PMINTEN_P __BITS(30,0)

sys/arch/arm/include/armreg.h

497

#define PMCNTEN_P __BITS(30,0)

sys/arch/arm/include/armreg.h

501

#define PMOVS_P __BITS(30,0)

sys/arch/arm/include/armreg.h

506

#define PMEVTYPER_EVTCOUNT __BITS(7,0)

sys/arch/arm/include/armreg.h

514

#define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1

sys/arch/arm/include/armreg.h

521

#define TTBR_RGN_MASK __BITS(4,3)

sys/arch/arm/include/armreg.h

537

#define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0

sys/arch/arm/include/armreg.h

540

#define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability

sys/arch/arm/include/armreg.h

541

#define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability

sys/arch/arm/include/armreg.h

542

#define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability

sys/arch/arm/include/armreg.h

545

#define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset

sys/arch/arm/include/armreg.h

546

#define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability

sys/arch/arm/include/armreg.h

547

#define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability

sys/arch/arm/include/armreg.h

548

#define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability

sys/arch/arm/include/armreg.h

550

#define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset

sys/arch/arm/include/armreg.h

552

#define NMRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings

sys/arch/arm/include/armreg.h

553

#define NMRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings

sys/arch/arm/include/armreg.h

558

#define PRRR_NOSn(n) __BITS(24+(n)) // Memory region is Inner Shareable only

sys/arch/arm/include/armreg.h

563

#define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n))

sys/arch/arm/include/armreg.h

573

#define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */

sys/arch/arm/include/armreg.h

574

#define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */

sys/arch/arm/include/armreg.h

575

#define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */

sys/arch/arm/include/armreg.h

580

#define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */

sys/arch/arm/include/armreg.h

581

#define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = physical core id */

sys/arch/arm/include/armreg.h

587

#define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */

sys/arch/arm/include/armreg.h

588

#define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */

sys/arch/arm/include/armreg.h

597

#define CNTKCTL_EVNTI __BITS(7,4) /* CNTVCT Event Bit Select */

sys/arch/arm/include/armreg.h

604

#define CNTHCTL_EVNTI __BITS(7,4)

sys/arch/arm/include/armreg.h

610

#define ARM_A5_TLBDATA_DOM __BITS(62,59)

sys/arch/arm/include/armreg.h

611

#define ARM_A5_TLBDATA_AP __BITS(58,56)

sys/arch/arm/include/armreg.h

615

#define ARM_A5_TLBDATA_TEX __BITS(52,50)

sys/arch/arm/include/armreg.h

619

#define ARM_A5_TLBDATA_ASID __BITS(46,39)

sys/arch/arm/include/armreg.h

620

#define ARM_A5_TLBDATA_SIZE __BITS(38,37)

sys/arch/arm/include/armreg.h

625

#define ARM_A5_TLBDATA_VA __BITS(36,22)

sys/arch/arm/include/armreg.h

626

#define ARM_A5_TLBDATA_PA __BITS(21,2)

sys/arch/arm/include/armreg.h

630

#define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64)

sys/arch/arm/include/armreg.h

631

#define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64)

sys/arch/arm/include/armreg.h

636

#define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64)

sys/arch/arm/include/armreg.h

637

#define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64)

sys/arch/arm/include/armreg.h

643

#define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64)

sys/arch/arm/include/armreg.h

646

#define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64)

sys/arch/arm/include/armreg.h

651

#define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64)

sys/arch/arm/include/armreg.h

660

#define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32)

sys/arch/arm/include/armreg.h

663

#define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32)

sys/arch/arm/include/armreg.h

664

#define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32)

sys/arch/arm/include/armreg.h

667

#define ARM_A7_TLBDATA01_ASID __BITS(33,26)

sys/arch/arm/include/armreg.h

669

#define ARM_A7_TLBDATA0_VMID __BITS(25,18)

sys/arch/arm/include/armreg.h

670

#define ARM_A7_TLBDATA0_VA __BITS(17,5)

sys/arch/arm/include/armreg.h

672

#define ARM_A7_TLBDATA0_SIZE __BITS(3,1)

sys/arch/arm/include/armreg.h

685

#define ARM_A5_TLBDATAOP_INDEX __BITS(5,0)

sys/arch/arm/include/armreg.h

686

#define ARM_A7_TLBDATAOP_INDEX __BITS(6,0)

sys/arch/arm/marvell/armadaxpreg.h

123

#define ARMADAXP_ATTR_CRYPT_SWAP_MASK __BITS(1,0)

sys/arch/arm/marvell/armadaxpreg.h

128

#define ARMADAXP_ATTR_CRYPT_UNIT_MASK __BITS(3,2)

sys/arch/arm/marvell/armadaxpreg.h

367

#define L2_AUX_WBWT_MODE_MASK __BITS(1,0)

sys/arch/arm/marvell/armadaxpreg.h

375

#define L2_AUX_FORCE_WA_MASK __BITS(24,23)

sys/arch/arm/nvidia/tegra124_carreg.h

103

#define CAR_PLLU_BASE_DIVN __BITS(17,8)

sys/arch/arm/nvidia/tegra124_carreg.h

104

#define CAR_PLLU_BASE_DIVM __BITS(4,0)

sys/arch/arm/nvidia/tegra124_carreg.h

114

#define CAR_PLLD_BASE_DIVP __BITS(22,20)

sys/arch/arm/nvidia/tegra124_carreg.h

115

#define CAR_PLLD_BASE_DIVN __BITS(18,8)

sys/arch/arm/nvidia/tegra124_carreg.h

116

#define CAR_PLLD_BASE_DIVM __BITS(4,0)

sys/arch/arm/nvidia/tegra124_carreg.h

125

#define CAR_PLLX_BASE_DIVP __BITS(23,20)

sys/arch/arm/nvidia/tegra124_carreg.h

126

#define CAR_PLLX_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

127

#define CAR_PLLX_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

132

#define CAR_PLLX_MISC_PTS __BITS(23,22)

sys/arch/arm/nvidia/tegra124_carreg.h

139

#define CAR_PLLE_BASE_DIVP_CML __BITS(27,24)

sys/arch/arm/nvidia/tegra124_carreg.h

140

#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16)

sys/arch/arm/nvidia/tegra124_carreg.h

141

#define CAR_PLLE_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

142

#define CAR_PLLE_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

156

#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25)

sys/arch/arm/nvidia/tegra124_carreg.h

160

#define CAR_PLLD2_BASE_DIVP __BITS(23,20)

sys/arch/arm/nvidia/tegra124_carreg.h

163

#define CAR_PLLD2_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

164

#define CAR_PLLD2_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

169

#define CAR_PLLD2_MISC_MON_TEST_OUT __BITS(29,27)

sys/arch/arm/nvidia/tegra124_carreg.h

170

#define CAR_PLLD2_MISC_KCP __BITS(26,25)

sys/arch/arm/nvidia/tegra124_carreg.h

172

#define CAR_PLLD2_MISC_SETUP __BITS(23,0)

sys/arch/arm/nvidia/tegra124_carreg.h

181

#define CAR_CLKSRC_I2C_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

188

#define CAR_CLKSRC_I2C_DIV __BITS(15,0)

sys/arch/arm/nvidia/tegra124_carreg.h

197

#define CAR_CLKSRC_SPI_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

204

#define CAR_CLKSRC_SPI_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

211

#define CAR_CLKSRC_UART_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

219

#define CAR_CLKSRC_UART_DIV __BITS(15,0)

sys/arch/arm/nvidia/tegra124_carreg.h

226

#define CAR_CLKSRC_SDMMC_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

234

#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

237

#define CAR_CLKSRC_HDMI_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

245

#define CAR_CLKSRC_HDMI_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

249

#define CAR_CLKSRC_DISP_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

259

#define CAR_CLKSRC_HOST1X_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

266

#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

267

#define CAR_CLKSRC_HOST1X_CLK_DIVISOR __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

423

#define CAR_CCLKG_BURST_POLICY_CPU_STATE __BITS(31,28)

sys/arch/arm/nvidia/tegra124_carreg.h

426

#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0)

sys/arch/arm/nvidia/tegra124_carreg.h

431

#define CAR_CLKSRC_MSELECT_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

432

#define CAR_CLKSRC_MSELECT_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

435

#define CAR_CLKSRC_TSENSOR_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

437

#define CAR_CLKSRC_TSENSOR_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

440

#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

447

#define CAR_CLKSRC_HDA2CODEC_2X_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

450

#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

455

#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

458

#define CAR_CLKSRC_SATA_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

46

#define CAR_PLL_LFSR_RND __BITS(15,0)

sys/arch/arm/nvidia/tegra124_carreg.h

464

#define CAR_CLKSRC_SATA_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

467

#define CAR_CLKSRC_HDA_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

474

#define CAR_CLKSRC_HDA_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

479

#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT __BITS(31,27)

sys/arch/arm/nvidia/tegra124_carreg.h

484

#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT __BITS(11,0)

sys/arch/arm/nvidia/tegra124_carreg.h

487

#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT __BITS(23,18)

sys/arch/arm/nvidia/tegra124_carreg.h

488

#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT __BITS(17,6)

sys/arch/arm/nvidia/tegra124_carreg.h

499

#define CAR_PLLE_AUX_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra124_carreg.h

502

#define CAR_PLLE_AUX_SS_DLY __BITS(23,16)

sys/arch/arm/nvidia/tegra124_carreg.h

503

#define CAR_PLLE_AUX_LOCK_DLY __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

514

#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra124_carreg.h

526

#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)

sys/arch/arm/nvidia/tegra124_carreg.h

527

#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)

sys/arch/arm/nvidia/tegra124_carreg.h

528

#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

529

#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

535

#define CAR_PLLREFE_BASE_KCP __BITS(28,27)

sys/arch/arm/nvidia/tegra124_carreg.h

537

#define CAR_PLLREFE_BASE_DIVP __BITS(19,16)

sys/arch/arm/nvidia/tegra124_carreg.h

538

#define CAR_PLLREFE_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

539

#define CAR_PLLREFE_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

54

#define CAR_PLLP_BASE_DIVP __BITS(22,20)

sys/arch/arm/nvidia/tegra124_carreg.h

548

#define CAR_XUSBIO_PLL_CFG0_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra124_carreg.h

55

#define CAR_PLLP_BASE_DIVN __BITS(17,8)

sys/arch/arm/nvidia/tegra124_carreg.h

56

#define CAR_PLLP_BASE_DIVM __BITS(4,0)

sys/arch/arm/nvidia/tegra124_carreg.h

560

#define CAR_CLKSRC_XUSB_HOST_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

561

#define CAR_CLKSRC_XUSB_HOST_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

564

#define CAR_CLKSRC_XUSB_FALCON_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

565

#define CAR_CLKSRC_XUSB_FALCON_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

568

#define CAR_CLKSRC_XUSB_FS_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

569

#define CAR_CLKSRC_XUSB_FS_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

572

#define CAR_CLKSRC_XUSB_SS_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

575

#define CAR_CLKSRC_XUSB_SS_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

578

#define CAR_CLKSRC_SOC_THERM_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

580

#define CAR_CLKSRC_SOC_THERM_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

583

#define CAR_CLKSRC_HDMI_AUDIO_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra124_carreg.h

588

#define CAR_CLKSRC_HDMI_AUDIO_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra124_carreg.h

59

#define CAR_PLLP_OUTA_OUT2_RATIO __BITS(31,24)

sys/arch/arm/nvidia/tegra124_carreg.h

63

#define CAR_PLLP_OUTA_OUT1_RATIO __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

68

#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24)

sys/arch/arm/nvidia/tegra124_carreg.h

72

#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

77

#define CAR_PLLP_OUTC_OUT5_RATIO __BITS(31,24)

sys/arch/arm/nvidia/tegra124_carreg.h

88

#define CAR_PLLC_BASE_DIVP __BITS(23,20)

sys/arch/arm/nvidia/tegra124_carreg.h

89

#define CAR_PLLC_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra124_carreg.h

90

#define CAR_PLLC_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

145

#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW __BITS(15,14)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

147

#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW __BITS(11,6)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

149

#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL __BITS(5,0)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

151

#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP __BITS(10,9)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

152

#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ __BITS(6,3)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

159

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL __BITS(4,2)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

161

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL __BITS(1,0)

sys/arch/arm/nvidia/tegra124_xusbpadreg.h

163

#define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0 __BITS(27,26)

sys/arch/arm/nvidia/tegra210_carreg.h

108

#define CAR_PLLU_BASE_DIVP __BITS(20,16)

sys/arch/arm/nvidia/tegra210_carreg.h

109

#define CAR_PLLU_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

110

#define CAR_PLLU_BASE_DIVM __BITS(4,0)

sys/arch/arm/nvidia/tegra210_carreg.h

113

#define CAR_PLLU_OUTA_OUT2_RATIO __BITS(31,24)

sys/arch/arm/nvidia/tegra210_carreg.h

117

#define CAR_PLLU_OUTA_OUT1_RATIO __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

126

#define CAR_PLLU_MISC_PTS __BITS(28,27)

sys/arch/arm/nvidia/tegra210_carreg.h

127

#define CAR_PLLU_MISC_KCP __BITS(26,25)

sys/arch/arm/nvidia/tegra210_carreg.h

129

#define CAR_PLLU_MISC_SETUP __BITS(23,0)

sys/arch/arm/nvidia/tegra210_carreg.h

138

#define CAR_PLLD_BASE_DIVP __BITS(22,20)

sys/arch/arm/nvidia/tegra210_carreg.h

139

#define CAR_PLLD_BASE_DIVN __BITS(18,11)

sys/arch/arm/nvidia/tegra210_carreg.h

140

#define CAR_PLLD_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

149

#define CAR_PLLX_BASE_DIVP __BITS(24,20)

sys/arch/arm/nvidia/tegra210_carreg.h

150

#define CAR_PLLX_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

151

#define CAR_PLLX_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

155

#define CAR_PLLX_MISC_PTS __BITS(23,22)

sys/arch/arm/nvidia/tegra210_carreg.h

162

#define CAR_PLLE_BASE_DIVP_CML __BITS(28,24)

sys/arch/arm/nvidia/tegra210_carreg.h

163

#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16)

sys/arch/arm/nvidia/tegra210_carreg.h

164

#define CAR_PLLE_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

165

#define CAR_PLLE_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

168

#define CAR_PLLE_MISC_SETUP __BITS(31,16)

sys/arch/arm/nvidia/tegra210_carreg.h

175

#define CAR_PLLE_MISC_KCP __BITS(7,6)

sys/arch/arm/nvidia/tegra210_carreg.h

176

#define CAR_PLLE_MISC_VREG_BG_CTRL __BITS(5,4)

sys/arch/arm/nvidia/tegra210_carreg.h

177

#define CAR_PLLE_MISC_VREG_CTRL __BITS(3,2)

sys/arch/arm/nvidia/tegra210_carreg.h

186

#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25)

sys/arch/arm/nvidia/tegra210_carreg.h

190

#define CAR_PLLD2_BASE_DIVP __BITS(23,19)

sys/arch/arm/nvidia/tegra210_carreg.h

193

#define CAR_PLLD2_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

194

#define CAR_PLLD2_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

198

#define CAR_PLLD2_MISC_KCP __BITS(26,25)

sys/arch/arm/nvidia/tegra210_carreg.h

200

#define CAR_PLLD2_MISC_SETUP __BITS(23,0)

sys/arch/arm/nvidia/tegra210_carreg.h

209

#define CAR_CLKSRC_I2C_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

217

#define CAR_CLKSRC_I2C_DIV __BITS(15,0)

sys/arch/arm/nvidia/tegra210_carreg.h

226

#define CAR_CLKSRC_SPI_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

234

#define CAR_CLKSRC_SPI_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

241

#define CAR_CLKSRC_UART_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

250

#define CAR_CLKSRC_UART_DIV __BITS(15,0)

sys/arch/arm/nvidia/tegra210_carreg.h

257

#define CAR_CLKSRC_SDMMC_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

259

#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

263

#define CAR_CLKSRC_DISP_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

271

#define CAR_CLKSRC_HOST1X_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

272

#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

273

#define CAR_CLKSRC_HOST1X_CLK_DIVISOR __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

46

#define CAR_PLLE_SS_CNTL_INTEGOFFSET __BITS(31,30)

sys/arch/arm/nvidia/tegra210_carreg.h

47

#define CAR_PLLE_SS_CNTL_SSCINCINTRV __BITS(29,24)

sys/arch/arm/nvidia/tegra210_carreg.h

478

#define CAR_CCLKG_BURST_POLICY_CPU_STATE __BITS(31,28)

sys/arch/arm/nvidia/tegra210_carreg.h

48

#define CAR_PLLE_SS_CNTL_SSCINC __BITS(23,16)

sys/arch/arm/nvidia/tegra210_carreg.h

481

#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0)

sys/arch/arm/nvidia/tegra210_carreg.h

486

#define CAR_CLKSRC_MSELECT_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

487

#define CAR_CLKSRC_MSELECT_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

490

#define CAR_CLKSRC_TSENSOR_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

492

#define CAR_CLKSRC_TSENSOR_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

495

#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

496

#define CAR_CLKSRC_HDA2CODEC_2X_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

499

#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

500

#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

503

#define CAR_CLKSRC_SATA_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

505

#define CAR_CLKSRC_SATA_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

508

#define CAR_CLKSRC_HDA_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

509

#define CAR_CLKSRC_HDA_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

514

#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT __BITS(31,27)

sys/arch/arm/nvidia/tegra210_carreg.h

519

#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT __BITS(11,0)

sys/arch/arm/nvidia/tegra210_carreg.h

525

#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT __BITS(23,18)

sys/arch/arm/nvidia/tegra210_carreg.h

526

#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT __BITS(17,6)

sys/arch/arm/nvidia/tegra210_carreg.h

537

#define CAR_PLLE_AUX_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra210_carreg.h

540

#define CAR_PLLE_AUX_SS_DLY __BITS(23,16)

sys/arch/arm/nvidia/tegra210_carreg.h

541

#define CAR_PLLE_AUX_LOCK_DLY __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

55

#define CAR_PLLE_SS_CNTL_SSCMAX __BITS(8,0)

sys/arch/arm/nvidia/tegra210_carreg.h

552

#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra210_carreg.h

565

#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24)

sys/arch/arm/nvidia/tegra210_carreg.h

566

#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16)

sys/arch/arm/nvidia/tegra210_carreg.h

567

#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

568

#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

574

#define CAR_UTMIP_PLL_CFG3_SETUP __BITS(23,0)

sys/arch/arm/nvidia/tegra210_carreg.h

580

#define CAR_PLLREFE_BASE_KCP __BITS(28,27)

sys/arch/arm/nvidia/tegra210_carreg.h

582

#define CAR_PLLREFE_BASE_DIVP __BITS(20,16)

sys/arch/arm/nvidia/tegra210_carreg.h

583

#define CAR_PLLREFE_BASE_DIVN __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

584

#define CAR_PLLREFE_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

591

#define CAR_PLLREFE_MISC_PTS __BITS(26,25)

sys/arch/arm/nvidia/tegra210_carreg.h

593

#define CAR_PLLREFE_MISC_SETUP __BITS(23,0)

sys/arch/arm/nvidia/tegra210_carreg.h

596

#define CAR_XUSBIO_PLL_CFG0_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra210_carreg.h

610

#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra210_carreg.h

624

#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_STATE __BITS(27,26)

sys/arch/arm/nvidia/tegra210_carreg.h

63

#define CAR_PLLP_BASE_DIVP __BITS(24,20)

sys/arch/arm/nvidia/tegra210_carreg.h

636

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_CLK_SWITCH_DLY __BITS(31,24)

sys/arch/arm/nvidia/tegra210_carreg.h

637

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY __BITS(23,14)

sys/arch/arm/nvidia/tegra210_carreg.h

638

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_IDDQ2_ENABLE_DLY __BITS(13,10)

sys/arch/arm/nvidia/tegra210_carreg.h

639

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY __BITS(9,0)

sys/arch/arm/nvidia/tegra210_carreg.h

64

#define CAR_PLLP_BASE_DIVN __BITS(17,10)

sys/arch/arm/nvidia/tegra210_carreg.h

642

#define CAR_CLKSRC_XUSB_HOST_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

643

#define CAR_CLKSRC_XUSB_HOST_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

646

#define CAR_CLKSRC_XUSB_FALCON_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

647

#define CAR_CLKSRC_XUSB_FALCON_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

65

#define CAR_PLLP_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

650

#define CAR_CLKSRC_XUSB_FS_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

651

#define CAR_CLKSRC_XUSB_FS_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

654

#define CAR_CLKSRC_XUSB_SS_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

657

#define CAR_CLKSRC_XUSB_SS_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

660

#define CAR_CLKSRC_SOC_THERM_SRC __BITS(31,29)

sys/arch/arm/nvidia/tegra210_carreg.h

662

#define CAR_CLKSRC_SOC_THERM_DDLL_SEL __BITS(11,10)

sys/arch/arm/nvidia/tegra210_carreg.h

663

#define CAR_CLKSRC_SOC_THERM_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

666

#define CAR_CLKSRC_USB2_HSIC_TRK_DIV __BITS(7,0)

sys/arch/arm/nvidia/tegra210_carreg.h

68

#define CAR_PLLP_OUTA_OUT1_RATIO __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

73

#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24)

sys/arch/arm/nvidia/tegra210_carreg.h

77

#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8)

sys/arch/arm/nvidia/tegra210_carreg.h

82

#define CAR_PLLP_OUTC_OUT5_RATIO __BITS(31,24)

sys/arch/arm/nvidia/tegra210_carreg.h

94

#define CAR_PLLC_BASE_DIVP __BITS(24,20)

sys/arch/arm/nvidia/tegra210_carreg.h

95

#define CAR_PLLC_BASE_DIVN __BITS(17,10)

sys/arch/arm/nvidia/tegra210_carreg.h

96

#define CAR_PLLC_BASE_DIVM __BITS(7,0)

sys/arch/arm/nvidia/tegra210_pinmux.c

227

TEGRA_PINGROUP("pa6", 0x9c0, __BITS(16, 12), __BITS(24, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

228

TEGRA_PINGROUP("pcc7", 0x9c4, __BITS(16, 12), __BITS(24, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

229

TEGRA_PINGROUP("pe6", 0x9c8, __BITS(16, 12), __BITS(24, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

230

TEGRA_PINGROUP("pe7", 0x9cc, __BITS(16, 12), __BITS(24, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

231

TEGRA_PINGROUP("ph6", 0x9d0, __BITS(16, 12), __BITS(24, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

232

TEGRA_PINGROUP("pk0", 0x9d4, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

233

TEGRA_PINGROUP("pk1", 0x9d8, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

234

TEGRA_PINGROUP("pk2", 0x9dc, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

235

TEGRA_PINGROUP("pk3", 0x9e0, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

236

TEGRA_PINGROUP("pk4", 0x9e4, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

237

TEGRA_PINGROUP("pk5", 0x9e8, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

238

TEGRA_PINGROUP("pk6", 0x9ec, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

239

TEGRA_PINGROUP("pk7", 0x9f0, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

240

TEGRA_PINGROUP("pl0", 0x9f4, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

241

TEGRA_PINGROUP("pl1", 0x9f8, 0, 0, __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

242

TEGRA_PINGROUP("pz0", 0x9fc, __BITS(18, 12), __BITS(26, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

243

TEGRA_PINGROUP("pz1", 0xa00, __BITS(18, 12), __BITS(26, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

244

TEGRA_PINGROUP("pz2", 0xa04, __BITS(18, 12), __BITS(26, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

245

TEGRA_PINGROUP("pz3", 0xa08, __BITS(18, 12), __BITS(26, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

246

TEGRA_PINGROUP("pz4", 0xa0c, __BITS(18, 12), __BITS(26, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

247

TEGRA_PINGROUP("pz5", 0xa10, __BITS(18, 12), __BITS(26, 20), 0, 0),

sys/arch/arm/nvidia/tegra210_pinmux.c

248

TEGRA_PINGROUP("sdmmc1",0xa98, __BITS(18, 12), __BITS(26, 20), __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

249

TEGRA_PINGROUP("sdmmc2",0xa9c, __BITS(7, 2), __BITS(13, 8), __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

250

TEGRA_PINGROUP("sdmmc3",0xab0, __BITS(18, 12), __BITS(26, 20), __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_pinmux.c

251

TEGRA_PINGROUP("sdmmc4",0xab4, __BITS(7, 2), __BITS(13, 8), __BITS(30, 28), __BITS(31, 30)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

101

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_MODE __BITS(9,8)

sys/arch/arm/nvidia/tegra210_xusbpad.c

106

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_SLEEP __BITS(2,1)

sys/arch/arm/nvidia/tegra210_xusbpad.c

109

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL __BITS(27,4)

sys/arch/arm/nvidia/tegra210_xusbpad.c

115

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_LOCKDET_CTRL __BITS(27,4)

sys/arch/arm/nvidia/tegra210_xusbpad.c

119

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_CLKDIST_CTRL __BITS(23,20)

sys/arch/arm/nvidia/tegra210_xusbpad.c

121

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL __BITS(13,12)

sys/arch/arm/nvidia/tegra210_xusbpad.c

123

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL __BITS(7,4)

sys/arch/arm/nvidia/tegra210_xusbpad.c

125

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL __BITS(23,16)

sys/arch/arm/nvidia/tegra210_xusbpad.c

138

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV __BITS(29,28)

sys/arch/arm/nvidia/tegra210_xusbpad.c

139

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV __BITS(27,20)

sys/arch/arm/nvidia/tegra210_xusbpad.c

140

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV __BITS(17,16)

sys/arch/arm/nvidia/tegra210_xusbpad.c

142

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_MODE __BITS(9,8)

sys/arch/arm/nvidia/tegra210_xusbpad.c

147

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_SLEEP __BITS(2,1)

sys/arch/arm/nvidia/tegra210_xusbpad.c

150

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL __BITS(27,4)

sys/arch/arm/nvidia/tegra210_xusbpad.c

156

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_LOCKDET_CTRL __BITS(27,4)

sys/arch/arm/nvidia/tegra210_xusbpad.c

160

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_CLKDIST_CTRL __BITS(23,20)

sys/arch/arm/nvidia/tegra210_xusbpad.c

162

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL __BITS(13,12)

sys/arch/arm/nvidia/tegra210_xusbpad.c

164

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL __BITS(7,4)

sys/arch/arm/nvidia/tegra210_xusbpad.c

166

#define XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL __BITS(23,16)

sys/arch/arm/nvidia/tegra210_xusbpad.c

176

#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL __BITS(19,18)

sys/arch/arm/nvidia/tegra210_xusbpad.c

179

#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_RX_CTLE __BITS(15,0)

sys/arch/arm/nvidia/tegra210_xusbpad.c

184

#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_RX_CDR_CTRL __BITS(31,16)

sys/arch/arm/nvidia/tegra210_xusbpad.c

190

((n) == 0 ? __BITS(6,0) : __BITS(((n) - 1) * 6 + 17, ((n) - 1) * 6 + 11))

sys/arch/arm/nvidia/tegra210_xusbpad.c

191

#define FUSE_SKUCALIB_HS_TERM_RANGE_ADJ __BITS(10,7)

sys/arch/arm/nvidia/tegra210_xusbpad.c

194

#define FUSE_USBCALIB_EXT_RPD_CTRL __BITS(4,0)

sys/arch/arm/nvidia/tegra210_xusbpad.c

46

#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD __BITS(19,18)

sys/arch/arm/nvidia/tegra210_xusbpad.c

593

XUSBPAD_LANE("usb2-0", 0, 0x04, __BITS(1,0), tegra210_xusbpad_usb2_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

595

XUSBPAD_LANE("usb2-1", 1, 0x04, __BITS(3,2), tegra210_xusbpad_usb2_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

597

XUSBPAD_LANE("usb2-2", 2, 0x04, __BITS(5,4), tegra210_xusbpad_usb2_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

599

XUSBPAD_LANE("usb2-3", 3, 0x04, __BITS(7,6), tegra210_xusbpad_usb2_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

607

XUSBPAD_LANE("pcie-0", 0, 0x28, __BITS(13,12), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

609

XUSBPAD_LANE("pcie-1", 1, 0x28, __BITS(15,14), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

611

XUSBPAD_LANE("pcie-2", 2, 0x28, __BITS(17,16), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

613

XUSBPAD_LANE("pcie-3", 3, 0x28, __BITS(19,18), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

615

XUSBPAD_LANE("pcie-4", 4, 0x28, __BITS(21,20), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

617

XUSBPAD_LANE("pcie-5", 5, 0x28, __BITS(23,22), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

619

XUSBPAD_LANE("pcie-6", 6, 0x28, __BITS(25,24), tegra210_xusbpad_pcie_func,

sys/arch/arm/nvidia/tegra210_xusbpad.c

622

XUSBPAD_LANE("sata-0", 0, XUSB_PADCTL_USB3_PAD_MUX_REG, __BITS(31,30),

sys/arch/arm/nvidia/tegra210_xusbpad.c

644

XUSBPAD_PORT("usb2-0", 0, 0x08, __BITS(1,0), __BIT(2)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

645

XUSBPAD_PORT("usb2-1", 1, 0x08, __BITS(5,4), __BIT(6)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

646

XUSBPAD_PORT("usb2-2", 2, 0x08, __BITS(9,8), __BIT(10)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

647

XUSBPAD_PORT("usb2-3", 3, 0x08, __BITS(13,12), __BIT(14)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

651

XUSBPAD_PORT("usb3-0", 0, 0x14, __BITS(3,0), __BIT(4)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

652

XUSBPAD_PORT("usb3-1", 1, 0x14, __BITS(8,5), __BIT(9)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

653

XUSBPAD_PORT("usb3-2", 2, 0x14, __BITS(13,10), __BIT(14)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

654

XUSBPAD_PORT("usb3-3", 3, 0x14, __BITS(18,15), __BIT(19)),

sys/arch/arm/nvidia/tegra210_xusbpad.c

70

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_VREG_LEV __BITS(8,7)

sys/arch/arm/nvidia/tegra210_xusbpad.c

77

#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_HS_CURR_LEVEL __BITS(5,0)

sys/arch/arm/nvidia/tegra210_xusbpad.c

80

#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_RPD_CTRL __BITS(30,26)

sys/arch/arm/nvidia/tegra210_xusbpad.c

81

#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_TERM_RANGE_ADJ __BITS(6,3)

sys/arch/arm/nvidia/tegra210_xusbpad.c

88

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_DISCON_LEVEL __BITS(5,3)

sys/arch/arm/nvidia/tegra210_xusbpad.c

89

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_SQUELCH_LEVEL __BITS(2,0)

sys/arch/arm/nvidia/tegra210_xusbpad.c

93

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_DONE_RESET_TIMER __BITS(25,19)

sys/arch/arm/nvidia/tegra210_xusbpad.c

94

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_START_TIMER __BITS(18,12)

sys/arch/arm/nvidia/tegra210_xusbpad.c

97

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV __BITS(29,28)

sys/arch/arm/nvidia/tegra210_xusbpad.c

98

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV __BITS(27,20)

sys/arch/arm/nvidia/tegra210_xusbpad.c

99

#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV __BITS(17,16)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

105

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_DRV_CNTL __BITS(27,24)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

106

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_PRE __BITS(23,20)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

107

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_CMADJ __BITS(19,16)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

108

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK __BITS(15,8)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

109

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP __BITS(7,0)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

112

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_DRV_CNTL __BITS(27,24)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

113

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_PRE __BITS(23,20)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

114

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK __BITS(19,12)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

115

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_CMADJ __BITS(11,8)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

116

#define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP __BITS(7,0)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

119

#define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN3 __BITS(23,16)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

120

#define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN2 __BITS(15,8)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

121

#define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 __BITS(7,0)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

124

#define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ __BITS(31,16)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

125

#define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN1_RX_EQ __BITS(15,0)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

34

#define TEGRA_SATA_FPCI_BAR_START __BITS(31,4)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

55

#define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

67

#define TEGRA_T_SATA0_NVOOB_COMMA_CNT __BITS(30,28)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

68

#define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH __BITS(27,26)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

69

#define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE __BITS(25,24)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

80

#define TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW __BITS(26,18)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

89

#define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE __BITS(31,16)

sys/arch/arm/nvidia/tegra_ahcisatareg.h

90

#define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF __BITS(15,8)

sys/arch/arm/nvidia/tegra_apbdmareg.h

66

#define APBDMACHAN_CSR_REQ_SEL __BITS(20,16)

sys/arch/arm/nvidia/tegra_apbdmareg.h

71

#define APBDMACHAN_AHB_PTR_MASK __BITS(31,2)

sys/arch/arm/nvidia/tegra_apbdmareg.h

74

#define APBDMACHAN_AHB_SEQ_BUS_WIDTH __BITS(30,28)

sys/arch/arm/nvidia/tegra_apbdmareg.h

77

#define APBDMACHAN_AHB_SEQ_BURST __BITS(26,24)

sys/arch/arm/nvidia/tegra_apbdmareg.h

82

#define APBDMACHAN_AHB_SEQ_WRAP __BITS(18,16)

sys/arch/arm/nvidia/tegra_apbdmareg.h

92

#define APBDMACHAN_APB_PTR_MASK __BITS(31,2)

sys/arch/arm/nvidia/tegra_apbdmareg.h

94

#define APBDMACHAN_APB_SEQ_BUS_WIDTH __BITS(30,28)

sys/arch/arm/nvidia/tegra_apbdmareg.h

99

#define APBDMACHAN_APB_SEQ_WRAP __BITS(18,16)

sys/arch/arm/nvidia/tegra_apbreg.h

82

#define APB_MISC_GP_HIDREV_0_MINORREV __BITS(19,16)

sys/arch/arm/nvidia/tegra_apbreg.h

83

#define APB_MISC_GP_HIDREV_0_CHIPID __BITS(15,8)

sys/arch/arm/nvidia/tegra_apbreg.h

84

#define APB_MISC_GP_HIDREV_0_MAJORREV __BITS(7,4)

sys/arch/arm/nvidia/tegra_apbreg.h

85

#define APB_MISC_GP_HIDREV_0_HIDFAM __BITS(3,0)

sys/arch/arm/nvidia/tegra_cecreg.h

43

#define CEC_HW_CONTROL_RX_LOGICAL_ADDRS __BITS(14,0)

sys/arch/arm/nvidia/tegra_cecreg.h

47

#define CEC_INPUT_FILTER_FIFO_LENGTH __BITS(5,0)

sys/arch/arm/nvidia/tegra_cecreg.h

56

#define CEC_TX_REGISTER_DATA __BITS(7,0)

sys/arch/arm/nvidia/tegra_cecreg.h

61

#define CEC_RX_REGISTER_DATA __BITS(7,0)

sys/arch/arm/nvidia/tegra_dcreg.h

161

#define DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS __BITS(11,0)

sys/arch/arm/nvidia/tegra_dcreg.h

164

#define DC_DISP_REF_TO_SYNC_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

165

#define DC_DISP_REF_TO_SYNC_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

168

#define DC_DISP_SYNC_WIDTH_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

169

#define DC_DISP_SYNC_WIDTH_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

172

#define DC_DISP_BACK_PORCH_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

173

#define DC_DISP_BACK_PORCH_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

176

#define DC_DISP_DISP_ACTIVE_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

177

#define DC_DISP_DISP_ACTIVE_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

180

#define DC_DISP_FRONT_PORCH_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

181

#define DC_DISP_FRONT_PORCH_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

195

#define DC_DISP_H_PULSE2_CONTROL_LAST __BITS(11,8)

sys/arch/arm/nvidia/tegra_dcreg.h

197

#define DC_DISP_H_PULSE2_CONTROL_V_QUAL __BITS(7,6)

sys/arch/arm/nvidia/tegra_dcreg.h

203

#define DC_DISP_H_PULSE2_POSITION_A_END __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

204

#define DC_DISP_H_PULSE2_POSITION_A_START __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

223

#define DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER __BITS(11,8)

sys/arch/arm/nvidia/tegra_dcreg.h

224

#define DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER __BITS(7,0)

sys/arch/arm/nvidia/tegra_dcreg.h

229

#define DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE __BITS(3,0)

sys/arch/arm/nvidia/tegra_dcreg.h

240

#define DC_DISP_CURSOR_START_ADDR_CLIPPING __BITS(29,28)

sys/arch/arm/nvidia/tegra_dcreg.h

245

#define DC_DISP_CURSOR_START_ADDR_SIZE __BITS(25,24)

sys/arch/arm/nvidia/tegra_dcreg.h

250

#define DC_DISP_CURSOR_START_ADDR_ADDRESS_LO __BITS(21,0)

sys/arch/arm/nvidia/tegra_dcreg.h

255

#define DC_DISP_CURSOR_POSITION_V __BITS(29,16)

sys/arch/arm/nvidia/tegra_dcreg.h

256

#define DC_DISP_CURSOR_POSITION_H __BITS(13,0)

sys/arch/arm/nvidia/tegra_dcreg.h

295

#define DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL __BITS(17,16)

sys/arch/arm/nvidia/tegra_dcreg.h

296

#define DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL __BITS(9,8)

sys/arch/arm/nvidia/tegra_dcreg.h

297

#define DC_DISP_BLEND_CURSOR_CONTROL_ALPHA __BITS(7,0)

sys/arch/arm/nvidia/tegra_dcreg.h

387

#define DC_WINC_A_BYTE_SWAP_SWAP __BITS(2,0)

sys/arch/arm/nvidia/tegra_dcreg.h

391

#define DC_WINC_A_COLOR_DEPTH_DEPTH __BITS(6,0)

sys/arch/arm/nvidia/tegra_dcreg.h

396

#define DC_WINC_A_POSITION_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

397

#define DC_WINC_A_POSITION_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

400

#define DC_WINC_A_SIZE_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

401

#define DC_WINC_A_SIZE_H __BITS(12,0)

sys/arch/arm/nvidia/tegra_dcreg.h

404

#define DC_WINC_A_PRESCALED_SIZE_V __BITS(28,16)

sys/arch/arm/nvidia/tegra_dcreg.h

405

#define DC_WINC_A_PRESCALED_SIZE_H __BITS(14,0)

sys/arch/arm/nvidia/tegra_dcreg.h

412

#define DC_WINC_A_LINE_STRIDE_UV_LINE_STRIDE __BITS(31,16)

sys/arch/arm/nvidia/tegra_dcreg.h

413

#define DC_WINC_A_LINE_STRIDE_LINE_STRIDE __BITS(15,0)

sys/arch/arm/nvidia/tegra_dcreg.h

437

#define DC_WINBUF_A_SURFACE_KIND_BLOCK_HEIGHT __BITS(6,4)

sys/arch/arm/nvidia/tegra_dcreg.h

438

#define DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND __BITS(1,0)

sys/arch/arm/nvidia/tegra_dcreg.h

52

#define DC_CMD_DISPLAY_COMMAND_RAISE_CHANNEL_ID __BITS(30,27)

sys/arch/arm/nvidia/tegra_dcreg.h

53

#define DC_CMD_DISPLAY_COMMAND_RAISE_VECTOR __BITS(26,22)

sys/arch/arm/nvidia/tegra_dcreg.h

54

#define DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE __BITS(6,5)

sys/arch/arm/nvidia/tegra_gpioreg.h

50

#define GPIO_CNF_LOCK __BITS(15,8)

sys/arch/arm/nvidia/tegra_gpioreg.h

51

#define GPIO_CNF_MODE __BITS(7,0)

sys/arch/arm/nvidia/tegra_hdmireg.h

127

#define HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET __BITS(20,16)

sys/arch/arm/nvidia/tegra_hdmireg.h

131

#define HDMI_NV_PDISP_HDMI_CTRL_REKEY __BITS(6,0)

sys/arch/arm/nvidia/tegra_hdmireg.h

147

#define HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL __BITS(18,16)

sys/arch/arm/nvidia/tegra_hdmireg.h

199

#define HDMI_NV_PDISP_SOR_PLL0_TX_REG_LOAD __BITS(29,28)

sys/arch/arm/nvidia/tegra_hdmireg.h

200

#define HDMI_NV_PDISP_SOR_PLL0_ICHPMP __BITS(27,24)

sys/arch/arm/nvidia/tegra_hdmireg.h

201

#define HDMI_NV_PDISP_SOR_PLL0_FILTER __BITS(19,16)

sys/arch/arm/nvidia/tegra_hdmireg.h

202

#define HDMI_NV_PDISP_SOR_PLL0_BG_V17_S __BITS(15,12)

sys/arch/arm/nvidia/tegra_hdmireg.h

203

#define HDMI_NV_PDISP_SOR_PLL0_VCOCAP __BITS(11,8)

sys/arch/arm/nvidia/tegra_hdmireg.h

215

#define HDMI_NV_PDISP_SOR_CSTM_ROTDAT __BITS(30,28)

sys/arch/arm/nvidia/tegra_hdmireg.h

216

#define HDMI_NV_PDISP_SOR_CSTM_ROTCLK __BITS(27,24)

sys/arch/arm/nvidia/tegra_hdmireg.h

224

#define HDMI_NV_PDISP_SOR_CSTM_MODE __BITS(13,12)

sys/arch/arm/nvidia/tegra_hdmireg.h

251

#define HDMI_NV_PDISP_SOR_SEQ_CTL_PC __BITS(19,16)

sys/arch/arm/nvidia/tegra_hdmireg.h

252

#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC_ALT __BITS(15,12)

sys/arch/arm/nvidia/tegra_hdmireg.h

253

#define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC __BITS(11,8)

sys/arch/arm/nvidia/tegra_hdmireg.h

254

#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC_ALT __BITS(7,4)

sys/arch/arm/nvidia/tegra_hdmireg.h

255

#define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC __BITS(3,0)

sys/arch/arm/nvidia/tegra_hdmireg.h

285

#define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS __BITS(13,12)

sys/arch/arm/nvidia/tegra_hdmireg.h

286

#define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME __BITS(9,0)

sys/arch/arm/nvidia/tegra_hdmireg.h

291

#define HDMI_NV_PDISP_SOR_REFCLK_DIV_INT __BITS(15,8)

sys/arch/arm/nvidia/tegra_hdmireg.h

292

#define HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC __BITS(7,6)

sys/arch/arm/nvidia/tegra_hdmireg.h

305

#define HDMI_NV_PDISP_AUDIO_N_VALUE __BITS(19,0)

sys/arch/arm/nvidia/tegra_hdmireg.h

310

#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT __BITS(21,20)

sys/arch/arm/nvidia/tegra_hdmireg.h

314

#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ __BITS(19,16)

sys/arch/arm/nvidia/tegra_hdmireg.h

44

#define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE __BITS(1,0)

sys/arch/arm/nvidia/tegra_hdmireg.h

53

#define HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL __BITS(11,8)

sys/arch/arm/nvidia/tegra_hdmireg.h

54

#define HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE __BITS(7,6)

sys/arch/arm/nvidia/tegra_hdmireg.h

55

#define HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER __BITS(5,4)

sys/arch/arm/nvidia/tegra_hdmireg.h

56

#define HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER __BITS(3,0)

sys/arch/arm/nvidia/tegra_i2creg.h

101

#define I2C_FIFO_STATUS_SLV_TX_FIFO_EMPTY_CNT __BITS(23,20)

sys/arch/arm/nvidia/tegra_i2creg.h

102

#define I2C_FIFO_STATUS_SLV_RX_FIFO_FULL_CNT __BITS(19,16)

sys/arch/arm/nvidia/tegra_i2creg.h

103

#define I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT __BITS(7,4)

sys/arch/arm/nvidia/tegra_i2creg.h

104

#define I2C_FIFO_STATUS_RX_FIFO_FULL_CNT __BITS(3,0)

sys/arch/arm/nvidia/tegra_i2creg.h

125

#define I2C_CLK_DIVISOR_STD_FAST_MODE __BITS(31,16)

sys/arch/arm/nvidia/tegra_i2creg.h

126

#define I2C_CLK_DIVISOR_HSMODE __BITS(15,0)

sys/arch/arm/nvidia/tegra_i2creg.h

142

#define I2C_INTERFACE_TIMING0_THIGH __BITS(13,8)

sys/arch/arm/nvidia/tegra_i2creg.h

143

#define I2C_INTERFACE_TIMING0_TLOW __BITS(5,0)

sys/arch/arm/nvidia/tegra_i2creg.h

152

#define I2C_IOPACKET_WORD0_PROTHDRSZ __BITS(29,28)

sys/arch/arm/nvidia/tegra_i2creg.h

155

#define I2C_IOPACKET_WORD0_PKTID __BITS(23,16)

sys/arch/arm/nvidia/tegra_i2creg.h

156

#define I2C_IOPACKET_WORD0_CONTROLLERID __BITS(15,12)

sys/arch/arm/nvidia/tegra_i2creg.h

157

#define I2C_IOPACKET_WORD0_PROTOCOL __BITS(7,4)

sys/arch/arm/nvidia/tegra_i2creg.h

159

#define I2C_IOPACKET_WORD0_PKTTYPE __BITS(2,0)

sys/arch/arm/nvidia/tegra_i2creg.h

165

#define I2C_IOPACKET_WORD1_PAYLOADSIZE __BITS(11,0)

sys/arch/arm/nvidia/tegra_i2creg.h

177

#define I2C_IOPACKET_XMITHDR_HS_MASTER_ADDR __BITS(14,12)

sys/arch/arm/nvidia/tegra_i2creg.h

178

#define I2C_IOPACKET_XMITHDR_SLAVE_ADDR __BITS(9,0)

sys/arch/arm/nvidia/tegra_i2creg.h

183

#define I2C_IOPACKET_RESPHDR_TRANSFER_PKT_ID __BITS(23,16)

sys/arch/arm/nvidia/tegra_i2creg.h

184

#define I2C_IOPACKET_RESPHDR_TRANSFER_BYTENUM __BITS(15,4)

sys/arch/arm/nvidia/tegra_i2creg.h

34

#define I2C_CNFG_DEBOUNCE_CNT __BITS(14,12)

sys/arch/arm/nvidia/tegra_i2creg.h

43

#define I2C_CNFG_LENGTH __BITS(3,1)

sys/arch/arm/nvidia/tegra_i2creg.h

53

#define I2C_STATUS_CMD2_STAT __BITS(7,4)

sys/arch/arm/nvidia/tegra_i2creg.h

54

#define I2C_STATUS_CMD1_STAT __BITS(3,0)

sys/arch/arm/nvidia/tegra_i2creg.h

58

#define I2C_SL_CNFG_BUFFER_SIZE __BITS(19,8)

sys/arch/arm/nvidia/tegra_i2creg.h

82

#define I2C_PACKET_TRANSFER_STATUS_TRANSFER_PKT_ID __BITS(23,16)

sys/arch/arm/nvidia/tegra_i2creg.h

83

#define I2C_PACKET_TRANSFER_STATUS_TRANSFER_BYTENUM __BITS(15,4)

sys/arch/arm/nvidia/tegra_i2creg.h

90

#define I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG __BITS(15,13)

sys/arch/arm/nvidia/tegra_i2creg.h

91

#define I2C_FIFO_CONTROL_SLV_RX_FIFO_TRIG __BITS(12,10)

sys/arch/arm/nvidia/tegra_i2creg.h

94

#define I2C_FIFO_CONTROL_TX_FIFO_TRIG __BITS(7,5)

sys/arch/arm/nvidia/tegra_i2creg.h

95

#define I2C_FIFO_CONTROL_RX_FIFO_TRIG __BITS(4,2)

sys/arch/arm/nvidia/tegra_mcreg.h

51

#define MC_ERR_TYPE __BITS(30,28)

sys/arch/arm/nvidia/tegra_mcreg.h

55

#define MC_ERR_ADDR_HI __BITS(21,20)

sys/arch/arm/nvidia/tegra_mcreg.h

61

#define MC_ERR_ADR1 __BITS(14,12)

sys/arch/arm/nvidia/tegra_mcreg.h

62

#define MC_ERR_ID __BITS(6,0)

sys/arch/arm/nvidia/tegra_mcreg.h

79

#define MC_EMEM_CFG_0_EMEM_SIZE_MB __BITS(13,0)

sys/arch/arm/nvidia/tegra_mpioreg.h

271

#define PINMUX_AUX_PUPD __BITS(3,2)

sys/arch/arm/nvidia/tegra_mpioreg.h

275

#define PINMUX_AUX_PM __BITS(1,0)

sys/arch/arm/nvidia/tegra_pciereg.h

68

#define AFI_INTR_CODE_INT_CODE __BITS(4,0)

sys/arch/arm/nvidia/tegra_pciereg.h

71

#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG __BITS(23,20)

sys/arch/arm/nvidia/tegra_pciereg.h

86

#define AFI_MSG_INT1 __BITS(27,24)

sys/arch/arm/nvidia/tegra_pciereg.h

88

#define AFI_MSG_INT0 __BITS(11,8)

sys/arch/arm/nvidia/tegra_pinmux.c

50

#define PINMUX_DRV_TYPE __BITS(14,13)

sys/arch/arm/nvidia/tegra_pinmux.c

59

#define PINMUX_PUPD __BITS(3,2)

sys/arch/arm/nvidia/tegra_pinmux.c

60

#define PINMUX_PM __BITS(1,0)

sys/arch/arm/nvidia/tegra_pmcreg.h

34

#define PMC_CNTRL_0_CPUPWRGOOD_SEL __BITS(21,20)

sys/arch/arm/nvidia/tegra_pmcreg.h

59

#define PMC_PWRGATE_TOGGLE_0_PARTID __BITS(4,0)

sys/arch/arm/nvidia/tegra_soctherm.c

48

#define FUSE_TSENSOR_CALIB_CP_TS_BASE __BITS(12,0)

sys/arch/arm/nvidia/tegra_soctherm.c

49

#define FUSE_TSENSOR_CALIB_FT_TS_BASE __BITS(25,13)

sys/arch/arm/nvidia/tegra_soctherm.c

52

#define FUSE_TSENSOR8_CALIB_CP_TS_BASE __BITS(9,0)

sys/arch/arm/nvidia/tegra_soctherm.c

53

#define FUSE_TSENSOR8_CALIB_FT_TS_BASE __BITS(20,10)

sys/arch/arm/nvidia/tegra_soctherm.c

56

#define FUSE_SPARE_REALIGNMENT_CP __BITS(5,0)

sys/arch/arm/nvidia/tegra_soctherm.c

57

#define FUSE_SPARE_REALIGNMENT_FT __BITS(25,21)

sys/arch/arm/nvidia/tegra_socthermreg.h

38

#define SOC_THERM_TSENSOR_CONFIG0_TALL __BITS(27,8)

sys/arch/arm/nvidia/tegra_socthermreg.h

48

#define SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT __BITS(29,24)

sys/arch/arm/nvidia/tegra_socthermreg.h

49

#define SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN __BITS(20,15)

sys/arch/arm/nvidia/tegra_socthermreg.h

50

#define SOC_THERM_TSENSOR_CONFIG1_TSAMPLE __BITS(9,0)

sys/arch/arm/nvidia/tegra_socthermreg.h

53

#define SOC_THERM_TSENSOR_CONFIG2_THERM_A __BITS(31,16)

sys/arch/arm/nvidia/tegra_socthermreg.h

54

#define SOC_THERM_TSENSOR_CONFIG2_THERM_B __BITS(15,0)

sys/arch/arm/nvidia/tegra_socthermreg.h

58

#define SOC_THERM_TSENSOR_STATUS0_CAPTURE __BITS(15,0)

sys/arch/arm/nvidia/tegra_socthermreg.h

62

#define SOC_THERM_TSENSOR_STATUS1_TEMP __BITS(15,0)

sys/arch/arm/nvidia/tegra_socthermreg.h

65

#define SOC_THERM_TSENSOR_STATUS2_TEMP_MAX __BITS(31,16)

sys/arch/arm/nvidia/tegra_socthermreg.h

66

#define SOC_THERM_TSENSOR_STATUS2_TEMP_MIN __BITS(15,0)

sys/arch/arm/nvidia/tegra_timerreg.h

58

#define TMR_PTV_VAL __BITS(28,0)

sys/arch/arm/nvidia/tegra_timerreg.h

61

#define TMR_PCR_VAL __BITS(28,0)

sys/arch/arm/nvidia/tegra_usbreg.h

111

#define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_B __BITS(31,16)

sys/arch/arm/nvidia/tegra_usbreg.h

112

#define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A __BITS(15,0)

sys/arch/arm/nvidia/tegra_usbreg.h

120

#define TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ __BITS(21,18)

sys/arch/arm/nvidia/tegra_usbreg.h

126

#define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT __BITS(7,3)

sys/arch/arm/nvidia/tegra_usbreg.h

130

#define TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT __BITS(19,15)

sys/arch/arm/nvidia/tegra_usbreg.h

131

#define TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT __BITS(14,10)

sys/arch/arm/nvidia/tegra_usbreg.h

134

#define TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY __BITS(5,1)

sys/arch/arm/nvidia/tegra_usbreg.h

33

#define TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES __BITS(21,16)

sys/arch/arm/nvidia/tegra_usbreg.h

37

#define TEGRA_EHCI_ICUSB_CTRL_VDD1 __BITS(2,0)

sys/arch/arm/nvidia/tegra_usbreg.h

40

#define TEGRA_EHCI_HOSTPC1_DEVLC_PTS __BITS(31,29)

sys/arch/arm/nvidia/tegra_usbreg.h

46

#define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD __BITS(26,25)

sys/arch/arm/nvidia/tegra_usbreg.h

53

#define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMX __BITS(21,20)

sys/arch/arm/nvidia/tegra_usbreg.h

54

#define TEGRA_EHCI_HOSTPC1_DEVLC_H_EPLPM __BITS(19,16)

sys/arch/arm/nvidia/tegra_usbreg.h

55

#define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMFRM __BITS(15,12)

sys/arch/arm/nvidia/tegra_usbreg.h

58

#define TEGRA_EHCI_HOSTPC1_DEVLC_BA __BITS(11,1)

sys/arch/arm/nvidia/tegra_usbreg.h

61

#define TEGRA_EHCI_USBMODE_CM __BITS(1,0)

sys/arch/arm/nvidia/tegra_usbreg.h

88

#define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB __BITS(31,25)

sys/arch/arm/nvidia/tegra_usbreg.h

89

#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB __BITS(24,22)

sys/arch/arm/nvidia/tegra_usbreg.h

91

#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP __BITS(3,0)

sys/arch/arm/nvidia/tegra_usbreg.h

99

#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL __BITS(3,2)

sys/arch/arm/nvidia/tegra_xusbreg.h

40

#define MAILBOX_DATA_DATA __BITS(23,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

41

#define MAILBOX_DATA_TYPE __BITS(31,24)

sys/arch/arm/nvidia/tegra_xusbreg.h

44

#define T_XUSB_CFG_ARU_MAILBOX_OWNER_ID __BITS(7,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

49

#define T_XUSB_CFG_ARU_C11_CSBRANGE_RANGE __BITS(31-9,9-9)

sys/arch/arm/nvidia/tegra_xusbreg.h

55

#define XUSB_CSB_RANGE __BITS(31,9)

sys/arch/arm/nvidia/tegra_xusbreg.h

56

#define XUSB_CSB_OFFSET __BITS(8,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

66

#define XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI __BITS(31,16)

sys/arch/arm/nvidia/tegra_xusbreg.h

67

#define XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO __BITS(15,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

69

#define XUSB_CSB_FALCON_IMFILLCTL_NBLOCKS __BITS(7,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

76

#define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_SRC_ADDR __BITS(7,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

78

#define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_SRC_ADDR __BITS(7,0)

sys/arch/arm/nvidia/tegra_xusbreg.h

80

#define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT __BITS(31,24)

sys/arch/arm/nvidia/tegra_xusbreg.h

81

#define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET __BITS(19,8)

sys/arch/arm/nvidia/tegra_xusbreg.h

83

#define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION __BITS(31,24)

sys/arch/arm/nxp/imx6_ccm.c

317

uint32_t n = __SHIFTOUT(v, __BITS(5, 0) << (pfd->index * 8));

sys/arch/arm/nxp/imx6_ccmreg.h

100

#define CCM_CBCDR_AXI_SEL __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

101

#define CCM_CBCDR_MMDC_CH1_AXI_PODF __BITS(5, 3)

sys/arch/arm/nxp/imx6_ccmreg.h

102

#define CCM_CBCDR_PERIPH2_CLK2_PODF __BITS(2, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

105

#define CCM_CBCMR_GPU3D_SHADER_PODF __BITS(31, 29)

sys/arch/arm/nxp/imx6_ccmreg.h

106

#define CCM_CBCMR_GPU3D_CORE_PODF __BITS(28, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

107

#define CCM_CBCMR_GPU2D_CORE_CLK_PODF __BITS(25, 23)

sys/arch/arm/nxp/imx6_ccmreg.h

108

#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL __BITS(22, 21)

sys/arch/arm/nxp/imx6_ccmreg.h

110

#define CCM_CBCMR_PRE_PERIPH_CLK_SEL __BITS(19, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

111

#define CCM_CBCMR_GPU2D_CLK_SEL __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

112

#define CCM_CBCMR_VPU_AXI_CLK_SEL __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

113

#define CCM_CBCMR_PERIPH_CLK2_SEL __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

116

#define CCM_CBCMR_GPU3D_SHADER_CLK_SEL __BITS(9, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

117

#define CCM_CBCMR_GPU3D_CORE_CLK_SEL __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

122

#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL __BITS(30, 29)

sys/arch/arm/nxp/imx6_ccmreg.h

123

#define CCM_CSCMR1_ACLK_SEL __BITS(28, 27)

sys/arch/arm/nxp/imx6_ccmreg.h

124

#define CCM_CSCMR1_QSPI1_PODF __BITS(28, 26) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

125

#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF __BITS(25, 23)

sys/arch/arm/nxp/imx6_ccmreg.h

126

#define CCM_CSCMR1_ACLK_PODF __BITS(22, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

131

#define CCM_CSCMR1_SSI3_CLK_SEL __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

132

#define CCM_CSCMR1_SSI2_CLK_SEL __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

133

#define CCM_CSCMR1_SSI1_CLK_SEL __BITS(11, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

134

#define CCM_CSCMR1_QSOI1_SEL __BITS(9, 7) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

136

#define CCM_CSCMR1_PERCLK_PODF __BITS(5, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

139

#define CCM_CSCMR2_VID_CLK_PODF __BITS(25, 24) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

140

#define CCM_CSCMR2_VID_CLK_SEL __BITS(23, 21) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

141

#define CCM_CSCMR2_ESAI_CLK_SEL __BITS(20, 19)

sys/arch/arm/nxp/imx6_ccmreg.h

144

#define CCM_CSCMR2_CAN_CLK_SEL __BITS(9, 8) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

145

#define CCM_CSCMR2_CAN_CLK_PODF __BITS(7, 2)

sys/arch/arm/nxp/imx6_ccmreg.h

148

#define CCM_CSCDR1_VPU_AXI_PODF __BITS(27, 25)

sys/arch/arm/nxp/imx6_ccmreg.h

149

#define CCM_CSCDR1_USDHC4_PODF __BITS(24, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

150

#define CCM_CSCDR1_USDHC3_PODF __BITS(21, 19)

sys/arch/arm/nxp/imx6_ccmreg.h

151

#define CCM_CSCDR1_USDHC2_PODF __BITS(18, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

152

#define CCM_CSCDR1_USDHC1_PODF __BITS(13, 11)

sys/arch/arm/nxp/imx6_ccmreg.h

153

#define CCM_CSCDR1_UART_CLK_PODF __BITS(5, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

157

#define CCM_CS1CDR_ESAI_CLK_PODF __BITS(27, 25)

sys/arch/arm/nxp/imx6_ccmreg.h

158

#define CCM_CS1CDR_SSI3_CLK_PRED __BITS(24, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

159

#define CCM_CS1CDR_SSI3_CLK_PODF __BITS(21, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

160

#define CCM_CS1CDR_ESAI_CLK_PRED __BITS(11, 9)

sys/arch/arm/nxp/imx6_ccmreg.h

161

#define CCM_CS1CDR_SSI1_CLK_PRED __BITS(8, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

162

#define CCM_CS1CDR_SSI1_CLK_PODF __BITS(5, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

165

#define CCM_CS2CDR_ENFC_CLK_PODF __BITS(26, 21)

sys/arch/arm/nxp/imx6_ccmreg.h

166

#define CCM_CS2CDR_ENFC_CLK_PRED __BITS(20, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

167

#define CCM_CS2CDR_ENFC_CLK_SEL __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

168

#define CCM_CS2CDR_QSPI2_CLK_SEL __BITS(17, 15) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

169

#define CCM_CS2CDR_LDB_DI1_CLK_SEL __BITS(14, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

170

#define CCM_CS2CDR_LDB_DI0_CLK_SEL __BITS(11, 9)

sys/arch/arm/nxp/imx6_ccmreg.h

171

#define CCM_CS2CDR_SSI2_CLK_PRED __BITS(8, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

172

#define CCM_CS2CDR_SSI2_CLK_PODF __BITS(5, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

175

#define CCM_CDCDR_HSI_TX_PODF __BITS(31, 29)

sys/arch/arm/nxp/imx6_ccmreg.h

177

#define CCM_CDCDR_SPDIF0_CLK_PRED __BITS(27, 25)

sys/arch/arm/nxp/imx6_ccmreg.h

178

#define CCM_CDCDR_SPDIF0_CLK_PODF __BITS(24, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

179

#define CCM_CDCDR_SPDIF0_CLK_SEL __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

180

#define CCM_CDCDR_SPDIF1_CLK_PRED __BITS(14, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

181

#define CCM_CDCDR_SPDIF1_CLK_PODF __BITS(11, 9)

sys/arch/arm/nxp/imx6_ccmreg.h

182

#define CCM_CDCDR_SPDIF1_CLK_SEL __BITS(8, 7)

sys/arch/arm/nxp/imx6_ccmreg.h

185

#define CCM_CHSCCDR_ENET_PRE_CLK_SEL __BITS(17, 15) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

186

#define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL __BITS(17, 15)

sys/arch/arm/nxp/imx6_ccmreg.h

187

#define CCM_CHSCCDR_IPU1_DI1_PODF __BITS(14, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

188

#define CCM_CHSCCDR_ENET_CLK_SEL __BITS(11, 9) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

189

#define CCM_CHSCCDR_IPU1_DI1_CLK_SEL __BITS(11, 9)

sys/arch/arm/nxp/imx6_ccmreg.h

190

#define CCM_CHSCCDR_M4_PRE_CLK_SEL __BITS(8, 6) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

191

#define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL __BITS(8, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

192

#define CCM_CHSCCDR_IPU1_DI0_PODF __BITS(5, 3)

sys/arch/arm/nxp/imx6_ccmreg.h

193

#define CCM_CHSCCDR_M4_CLK_SEL __BITS(2, 0) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

194

#define CCM_CHSCCDR_IPU1_DI0_CLK_SEL __BITS(2, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

197

#define CCM_CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)

sys/arch/arm/nxp/imx6_ccmreg.h

199

#define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL __BITS(17, 15)

sys/arch/arm/nxp/imx6_ccmreg.h

200

#define CCM_CSCDR2_IPU2_DI1_PODF __BITS(14, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

201

#define CCM_CSCDR2_IPU2_DI1_CLK_SEL __BITS(11, 9)

sys/arch/arm/nxp/imx6_ccmreg.h

202

#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL __BITS(8, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

203

#define CCM_CSCDR2_IPU2_DI0_PODF __BITS(5, 3)

sys/arch/arm/nxp/imx6_ccmreg.h

204

#define CCM_CSCDR2_IPU2_DI0_CLK_SEL __BITS(2, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

216

#define CCM_CSCDR3_IPU2_HSP_PODF __BITS(18, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

217

#define CCM_CSCDR3_IPU2_HSP_CLK_SEL __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

218

#define CCM_CSCDR3_IPU1_HSP_PODF __BITS(13, 11)

sys/arch/arm/nxp/imx6_ccmreg.h

219

#define CCM_CSCDR3_IPU1_HSP_CLK_SEL __BITS(10, 9)

sys/arch/arm/nxp/imx6_ccmreg.h

223

#define CCM_CCOSR_CLKO2_DIV __BITS(23, 21)

sys/arch/arm/nxp/imx6_ccmreg.h

224

#define CCM_CCOSR_CLKO2_SEL __BITS(20, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

227

#define CCM_CCOSR_CLKO1_DIV __BITS(6, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

228

#define CCM_CCOSR_CLKO1_SEL __BITS(3, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

231

#define CCM_CCGR0_TZ3_CLK_ENABLE __BITS(31, 30)

sys/arch/arm/nxp/imx6_ccmreg.h

232

#define CCM_CCGR0_DTCP_CLK_ENABLE __BITS(29, 28)

sys/arch/arm/nxp/imx6_ccmreg.h

233

#define CCM_CCGR0_DCIC2_CLK_ENABLE __BITS(27, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

234

#define CCM_CCGR0_DCIC1_CLK_ENABLE __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

235

#define CCM_CCGR0_ARM_DBG_CLK_ENABLE __BITS(23, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

236

#define CCM_CCGR0_CAN2_SERIAL_CLK_ENABLE __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

237

#define CCM_CCGR0_CAN2_CLK_ENABLE __BITS(19, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

238

#define CCM_CCGR0_CAN1_SERIAL_CLK_ENABLE __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

239

#define CCM_CCGR0_CAN1_CLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

240

#define CCM_CCGR0_CAAM_WRAPPER_IPG_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

241

#define CCM_CCGR0_CAAM_WRAPPER_ACLK_ENABLE __BITS(11, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

242

#define CCM_CCGR0_CAAM_SECURE_MEM_CLK_ENABLE __BITS(9, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

243

#define CCM_CCGR0_ASRC_CLK_ENABLE __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

244

#define CCM_CCGR0_APBHDMA_HCLK_ENABLE __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

245

#define CCM_CCGR0_AIPS_TZ2_CLK_ENABLE __BITS(3, 2)

sys/arch/arm/nxp/imx6_ccmreg.h

246

#define CCM_CCGR0_AIPS_TZ1_CLK_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

248

#define CCM_CCGR1_CANFD_CLK_ENABLE __BITS(31, 30) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

249

#define CCM_CCGR1_OCRAM_CLK_ENABLE __BITS(29, 28) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

250

#define CCM_CCGR1_GPU3D_CLK_ENABLE __BITS(27, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

251

#define CCM_CCGR1_GPU2D_CLK_ENABLE __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

252

#define CCM_CCGR1_GPT_SERIAL_CLK_ENABLE __BITS(23, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

253

#define CCM_CCGR1_GPT_CLK_ENABLE __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

254

#define CCM_CCGR1_WAKEUP_CLK_ENABLE __BITS(19, 18) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

255

#define CCM_CCGR1_ESAI_CLK_ENABLE __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

256

#define CCM_CCGR1_EPIT2_CLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

257

#define CCM_CCGR1_EPIT1_CLK_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

258

#define CCM_CCGR1_ENET_CLK_ENABLE __BITS(11, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

259

#define CCM_CCGR1_I2C4_CLK_ENABLE __BITS(9, 8) /* i.MX6DL */

sys/arch/arm/nxp/imx6_ccmreg.h

260

#define CCM_CCGR1_ECSPI5_CLK_ENABLE __BITS(9, 8) /* i.MX6Q */

sys/arch/arm/nxp/imx6_ccmreg.h

261

#define CCM_CCGR1_ECSPI4_CLK_ENABLE __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

262

#define CCM_CCGR1_ECSPI3_CLK_ENABLE __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

263

#define CCM_CCGR1_ECSPI2_CLK_ENABLE __BITS(3, 2)

sys/arch/arm/nxp/imx6_ccmreg.h

264

#define CCM_CCGR1_ECSPI1_CLK_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

266

#define CCM_CCGR2_PXP_AXI_CLK_ENABLE __BITS(31, 30)

sys/arch/arm/nxp/imx6_ccmreg.h

267

#define CCM_CCGR2_LCDIF_APB_CLK_ENABLE __BITS(29, 28)

sys/arch/arm/nxp/imx6_ccmreg.h

268

#define CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE __BITS(27, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

269

#define CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

270

#define CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE __BITS(23, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

271

#define CCM_CCGR2_IPMUX3_CLK_ENABLE __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

272

#define CCM_CCGR2_IPMUX2_CLK_ENABLE __BITS(19, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

273

#define CCM_CCGR2_IPMUX1_CLK_ENABLE __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

274

#define CCM_CCGR2_IOMUX_IPT_CLK_IO_CLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

275

#define CCM_CCGR2_IIM_CLK_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

276

#define CCM_CCGR2_I2C3_SERIAL_CLK_ENABLE __BITS(11, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

277

#define CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE __BITS(9, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

278

#define CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

279

#define CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

280

#define CCM_CCGR2_CSI_CLK_ENABLE __BITS(3, 2) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

281

#define CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

283

#define CCM_CCGR3_OPENVGAXICLK_CLK_ROOT_ENABLE __BITS(31, 30)

sys/arch/arm/nxp/imx6_ccmreg.h

284

#define CCM_CCGR3_OCRAM_CLK_ENABLE __BITS(29, 28)

sys/arch/arm/nxp/imx6_ccmreg.h

285

#define CCM_CCGR3_MMDC_P1_IPG_CLK_ENABLE __BITS(27, 26) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

286

#define CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_ENABLE __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

287

#define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_ENABLE __BITS(23, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

288

#define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

289

#define CCM_CCGR3_MLB_CLK_ENABLE __BITS(19, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

290

#define CCM_CCGR3_MIPI_CORE_CFG_CLK_ENABLE __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

291

#define CCM_CCGR3_LDB_DI1_CLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

292

#define CCM_CCGR3_LDB_DI0_CLK_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

293

#define CCM_CCGR3_IPU2_IPU_DI1_CLK_ENABLE __BITS(11, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

294

#define CCM_CCGR3_IPU2_IPU_DI0_CLK_ENABLE __BITS(9, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

295

#define CCM_CCGR3_IPU2_IPU_CLK_ENABLE __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

296

#define CCM_CCGR3_IPU1_IPU_DI1_CLK_ENABLE __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

297

#define CCM_CCGR3_IPU1_IPU_DI0_CLK_ENABLE __BITS(3, 2)

sys/arch/arm/nxp/imx6_ccmreg.h

298

#define CCM_CCGR3_IPU1_IPU_CLK_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

300

#define CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE __BITS(31, 30)

sys/arch/arm/nxp/imx6_ccmreg.h

301

#define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE __BITS(29, 28)

sys/arch/arm/nxp/imx6_ccmreg.h

302

#define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE __BITS(27, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

303

#define CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

304

#define CCM_CCGR4_PWM4_CLK_ENABLE __BITS(23, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

305

#define CCM_CCGR4_PWM3_CLK_ENABLE __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

306

#define CCM_CCGR4_PWM2_CLK_ENABLE __BITS(19, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

307

#define CCM_CCGR4_PWM1_CLK_ENABLE __BITS(17, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

308

#define CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

309

#define CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

310

#define CCM_CCGR4_QSPI2_ENABLE __BITS(11, 10) /*6sx*/

sys/arch/arm/nxp/imx6_ccmreg.h

311

#define CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE __BITS(9, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

312

#define CCM_CCGR4_PCIE_ROOT_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

314

#define CCM_CCGR5_SAI2_ENABLE __BITS(31, 30) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

315

#define CCM_CCGR5_SAI1_ENABLE __BITS(29, 28) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

316

#define CCM_CCGR5_UART_SERIAL_CLK_ENABLE __BITS(27, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

317

#define CCM_CCGR5_UART_CLK_ENABLE __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

318

#define CCM_CCGR5_SSI3_CLK_ENABLE __BITS(23, 22)

sys/arch/arm/nxp/imx6_ccmreg.h

319

#define CCM_CCGR5_SSI2_CLK_ENABLE __BITS(21, 20)

sys/arch/arm/nxp/imx6_ccmreg.h

320

#define CCM_CCGR5_SSI1_CLK_ENABLE __BITS(19, 18)

sys/arch/arm/nxp/imx6_ccmreg.h

321

#define CCM_CCGR5_SPDIF_CLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

322

#define CCM_CCGR5_SPBA_CLK_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

323

#define CCM_CCGR5_SDMA_CLK_ENABLE __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

324

#define CCM_CCGR5_SATA_CLK_ENABLE __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

325

#define CCM_CCGR5_ROM_CLK_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

327

#define CCM_CCGR6_PWM7_CLK_ENABLE __BITS(31, 30) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

328

#define CCM_CCGR6_PWM6_CLK_ENABLE __BITS(29, 28) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

329

#define CCM_CCGR6_PWM5_CLK_ENABLE __BITS(27, 26) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

330

#define CCM_CCGR6_I2CS4_CLK_ENABLE __BITS(25, 24) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

331

#define CCM_CCGR6_GIS_CLK_ENABLE __BITS(23, 22) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

332

#define CCM_CCGR6_VADC_CLK_ENABLE __BITS(21, 20) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

333

#define CCM_CCGR6_PWM8_CLK_ENABLE __BITS(17, 16) /* 6sx */

sys/arch/arm/nxp/imx6_ccmreg.h

334

#define CCM_CCGR6_VPU_CLK_ENABLE __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

335

#define CCM_CCGR6_VDOAXICLK_CLK_ENABLE __BITS(13, 12)

sys/arch/arm/nxp/imx6_ccmreg.h

336

#define CCM_CCGR6_EIM_SLOW_CLK_ENABLE __BITS(11, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

337

#define CCM_CCGR6_USDHC4_CLK_ENABLE __BITS(9, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

338

#define CCM_CCGR6_USDHC3_CLK_ENABLE __BITS(7, 6)

sys/arch/arm/nxp/imx6_ccmreg.h

339

#define CCM_CCGR6_USDHC2_CLK_ENABLE __BITS(5, 4)

sys/arch/arm/nxp/imx6_ccmreg.h

340

#define CCM_CCGR6_USDHC1_CLK_ENABLE __BITS(3, 2)

sys/arch/arm/nxp/imx6_ccmreg.h

341

#define CCM_CCGR6_USBOH3_CLK_ENABLE __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

355

#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

359

#define CCM_ANALOG_PLL_ARM_DIV_SELECT __BITS(6, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

363

#define CCM_ANALOG_PLL_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

368

#define CCM_ANALOG_PLL_DIV_SELECT __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

377

#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

382

#define CCM_ANALOG_PLL_USB1_DIV_SELECT __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

391

#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

396

#define CCM_ANALOG_PLL_USB2_DIV_SELECT __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

403

#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

415

#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT __BITS(20, 19)

sys/arch/arm/nxp/imx6_ccmreg.h

417

#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

421

#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT __BITS(6, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

425

#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT __BITS(20, 19)

sys/arch/arm/nxp/imx6_ccmreg.h

427

#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

431

#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT __BITS(6, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

452

#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC __BITS(15, 14)

sys/arch/arm/nxp/imx6_ccmreg.h

457

#define CCM_ANALOG_PLL_ENET_DIV2_SELECT __BITS(3, 2)

sys/arch/arm/nxp/imx6_ccmreg.h

458

#define CCM_ANALOG_PLL_ENET_DIV_SELECT __BITS(1, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

465

#define CCM_ANALOG_PFD_480_PFD3_FRAC __BITS(29, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

468

#define CCM_ANALOG_PFD_480_PFD2_FRAC __BITS(21, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

471

#define CCM_ANALOG_PFD_480_PFD1_FRAC __BITS(13, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

474

#define CCM_ANALOG_PFD_480_PFD0_FRAC __BITS(5, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

481

#define CCM_ANALOG_PFD_528_PFD2_FRAC __BITS(21, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

484

#define CCM_ANALOG_PFD_528_PFD1_FRAC __BITS(13, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

487

#define CCM_ANALOG_PFD_528_PFD0_FRAC __BITS(5, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

496

#define CCM_ANALOG_MISC1_LVDS_CLK1_SRC __BITS(4, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

499

#define CCM_ANALOG_MISC1_LVDS_CLK2_SRC __BITS(9, 5)

sys/arch/arm/nxp/imx6_ccmreg.h

508

#define CCM_ANALOG_MISC2_VIDEO_DIV __BITS(31, 30)

sys/arch/arm/nxp/imx6_ccmreg.h

509

#define CCM_ANALOG_MISC2_REG2_STEP_TIME __BITS(29, 28)

sys/arch/arm/nxp/imx6_ccmreg.h

510

#define CCM_ANALOG_MISC2_REG1_STEP_TIME __BITS(27, 26)

sys/arch/arm/nxp/imx6_ccmreg.h

511

#define CCM_ANALOG_MISC2_REG0_STEP_TIME __BITS(25, 24)

sys/arch/arm/nxp/imx6_ccmreg.h

516

#define CCM_ANALOG_MISC2_REG2_BO_OFFSET __BITS(18, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

520

#define CCM_ANALOG_MISC2_REG1_BO_OFFSET __BITS(10, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

524

#define CCM_ANALOG_MISC2_REG0_BO_OFFSET __BITS(2, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

528

#define CCM_TEMPMON_TEMPSENSE0_TEMP_CNT __BITS(19, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

533

#define CCM_TEMPMON_TEMPSENSE1_MEASURE_FREQ __BITS(15, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

551

#define USB_ANALOG_DIGPROG_MAJOR __BITS(23, 8)

sys/arch/arm/nxp/imx6_ccmreg.h

552

#define USB_ANALOG_DIGPROG_MINOR __BITS(7, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

68

#define CCM_CCR_REG_BYPASS_COUNT __BITS(26, 21)

sys/arch/arm/nxp/imx6_ccmreg.h

69

#define CCM_CCR_WB_COUNT __BITS(18, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

71

#define CCM_CCR_OSCNT __BITS(7, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

87

#define CCM_CACRR_ARM_PODF __BITS(2, 0)

sys/arch/arm/nxp/imx6_ccmreg.h

90

#define CCM_CBCDR_PERIPH_CLK2_PODF __BITS(29, 27)

sys/arch/arm/nxp/imx6_ccmreg.h

95

#define CCM_CBCDR_MMDC_CH0_AXI_PODF __BITS(21, 19)

sys/arch/arm/nxp/imx6_ccmreg.h

96

#define CCM_CBCDR_AXI_PODF __BITS(18, 16)

sys/arch/arm/nxp/imx6_ccmreg.h

97

#define CCM_CBCDR_AHB_PODF __BITS(12, 10)

sys/arch/arm/nxp/imx6_ccmreg.h

98

#define CCM_CBCDR_IPG_PODF __BITS(9, 8)

sys/arch/arm/nxp/imx6_iomux.c

94

if (__SHIFTOUT(input_val, __BITS(31, 24)) == 0xff) {

sys/arch/arm/nxp/imx6_iomux.c

95

uint8_t sel = __SHIFTOUT(input_val, __BITS(7, 0));

sys/arch/arm/nxp/imx6_iomux.c

96

uint8_t width = __SHIFTOUT(input_val, __BITS(15, 8));

sys/arch/arm/nxp/imx6_iomux.c

97

uint8_t shift = __SHIFTOUT(input_val, __BITS(23, 16));

sys/arch/arm/nxp/imx6_iomux.c

98

uint32_t mask = __BITS(shift + (width - 1), shift);

sys/arch/arm/nxp/imx6_iomuxreg.h

102

#define IOMUX_GPR13_SATA_PHY_4 __BITS(13, 11)

sys/arch/arm/nxp/imx6_iomuxreg.h

103

#define IOMUX_GPR13_SATA_PHY_3 __BITS(10, 7)

sys/arch/arm/nxp/imx6_iomuxreg.h

104

#define IOMUX_GPR13_SATA_PHY_2 __BITS(6, 2)

sys/arch/arm/nxp/imx6_iomuxreg.h

2237

#define PAD_CTL_DDR_SEL_MASK __BITS(19, 18)

sys/arch/arm/nxp/imx6_iomuxreg.h

2243

#define PAD_CTL_PUS_MASK __BITS(15, 14)

sys/arch/arm/nxp/imx6_iomuxreg.h

2253

#define PAD_CTL_ODT __BITS(10, 8)

sys/arch/arm/nxp/imx6_iomuxreg.h

2254

#define PAD_CTL_SPEED_MASK __BITS(7, 6)

sys/arch/arm/nxp/imx6_iomuxreg.h

2259

#define PAD_CTL_DSE_MASK __BITS(5, 3)

sys/arch/arm/nxp/imx6_iomuxreg.h

53

#define IOMUX_GPR1_ADDRS3 __BITS(11, 10)

sys/arch/arm/nxp/imx6_iomuxreg.h

55

#define IOMUX_GPR1_ADDRS2 __BITS(8, 7)

sys/arch/arm/nxp/imx6_iomuxreg.h

57

#define IOMUX_GPR1_ADDRS1 __BITS(5, 4)

sys/arch/arm/nxp/imx6_iomuxreg.h

59

#define IOMUX_GPR1_ADDRS0 __BITS(2, 1)

sys/arch/arm/nxp/imx6_iomuxreg.h

68

#define IOMUX_GPR8_PCS_TX_SWING_LOW __BITS(31, 25)

sys/arch/arm/nxp/imx6_iomuxreg.h

69

#define IOMUX_GPR8_PCS_TX_SWING_FULL __BITS(24, 18)

sys/arch/arm/nxp/imx6_iomuxreg.h

70

#define IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_6DB __BITS(17, 12)

sys/arch/arm/nxp/imx6_iomuxreg.h

71

#define IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB __BITS(11, 6)

sys/arch/arm/nxp/imx6_iomuxreg.h

72

#define IOMUX_GPR8_PCS_TX_DEEMPH_GEN1 __BITS(5, 0)

sys/arch/arm/nxp/imx6_iomuxreg.h

81

#define IOMUX_GPR12_PCIE_CTL_7 __BITS(23, 21)

sys/arch/arm/nxp/imx6_iomuxreg.h

82

#define IOMUX_GPR12_DIA_STATUS_BUS_SELECT __BITS(20, 17)

sys/arch/arm/nxp/imx6_iomuxreg.h

84

#define IOMUX_GPR12_DEVICE_TYPE __BITS(15, 12)

sys/arch/arm/nxp/imx6_iomuxreg.h

90

#define IOMUX_GPR12_LOS_LEVEL __BITS(8, 4)

sys/arch/arm/nxp/imx6_iomuxreg.h

91

#define IOMUX_GPR12_USDHC_DBG_MUX __BITS(3, 2)

sys/arch/arm/nxp/imx6_iomuxreg.h

97

#define IOMUX_GPR13_SATA_PHY_8 __BITS(26, 24)

sys/arch/arm/nxp/imx6_iomuxreg.h

98

#define IOMUX_GPR13_SATA_PHY_7 __BITS(23, 19)

sys/arch/arm/nxp/imx6_iomuxreg.h

99

#define IOMUX_GPR13_SATA_PHY_6 __BITS(18, 16)

sys/arch/arm/nxp/imx6_srcreg.h

55

#define SRC_SCR_MASK_WDOG_RST __BITS(10, 7)

sys/arch/arm/nxp/imx6_srcreg.h

56

#define SRC_SCR_WARM_RST_BYPASS_COUNT __BITS(6, 5)

sys/arch/arm/nxp/imx6_srcreg.h

65

#define SRC_SRSR_RESERVED7 __BITS(15, 7)

sys/arch/arm/nxp/imx6_usbphyreg.h

42

#define USBPHY_TX_USBPHY_TX_EDGECTRL __BITS(28, 26)

sys/arch/arm/nxp/imx6_usbphyreg.h

43

#define USBPHY_TX_TXCAL45DP __BITS(19, 16)

sys/arch/arm/nxp/imx6_usbphyreg.h

44

#define USBPHY_TX_TXCAL45DN __BITS(11, 8)

sys/arch/arm/nxp/imx6_usbphyreg.h

45

#define USBPHY_TX_D_CAL __BITS(3, 0)

sys/arch/arm/nxp/imx6_usbreg.h

40

#define USBC_UOG_USBMODE_CM __BITS(1, 0)

sys/arch/arm/nxp/imx6_usbreg.h

43

#define USBC_UH_PORTSC1_PTS_1 __BITS(31, 30)

sys/arch/arm/nxp/imx6_usbreg.h

46

#define USBC_UH_PORTSC1_PTS_MASK (__BITS(31, 30) | __BIT(25))

sys/arch/arm/nxp/imx6_usbreg.h

55

#define USBC_UH_USBMODE_CM __BITS(1, 0)

sys/arch/arm/nxp/imx7d_ccm.c

117

ANATOP_MUX(PLL_SYS_MAIN_SRC, "pll_sys_main_src", pll_bypass_p, 0xb0, __BITS(15,14)),

sys/arch/arm/nxp/imx7d_ccm.c

118

ANATOP_MUX(PLL_ENET_MAIN_SRC, "pll_enet_main_src", pll_bypass_p, 0xe0, __BITS(15,14)),

sys/arch/arm/nxp/imx7d_ccm.c

157

IMX_MUX(UART1_ROOT_SRC, "uart1_src", uart1357_p, 0xaf80, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

158

IMX_MUX(UART2_ROOT_SRC, "uart2_src", uart246_p, 0xb000, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

159

IMX_MUX(UART3_ROOT_SRC, "uart3_src", uart1357_p, 0xb080, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

160

IMX_MUX(UART4_ROOT_SRC, "uart4_src", uart246_p, 0xb100, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

161

IMX_MUX(UART5_ROOT_SRC, "uart5_src", uart1357_p, 0xb180, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

162

IMX_MUX(UART6_ROOT_SRC, "uart6_src", uart246_p, 0xb200, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

163

IMX_MUX(UART7_ROOT_SRC, "uart7_src", uart1357_p, 0xb280, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

173

IMX_DIV(UART1_ROOT_PRE_DIV, "uart1_pre_div", "uart1_cg", 0xaf80, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

174

IMX_DIV(UART2_ROOT_PRE_DIV, "uart2_pre_div", "uart2_cg", 0xb000, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

175

IMX_DIV(UART3_ROOT_PRE_DIV, "uart3_pre_div", "uart3_cg", 0xb080, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

176

IMX_DIV(UART4_ROOT_PRE_DIV, "uart4_pre_div", "uart4_cg", 0xb100, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

177

IMX_DIV(UART5_ROOT_PRE_DIV, "uart5_pre_div", "uart5_cg", 0xb100, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

178

IMX_DIV(UART6_ROOT_PRE_DIV, "uart6_pre_div", "uart6_cg", 0xb200, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

179

IMX_DIV(UART7_ROOT_PRE_DIV, "uart7_pre_div", "uart7_cg", 0xb280, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

181

IMX_DIV(UART1_ROOT_DIV, "uart1_post_div", "uart1_pre_div", 0xaf80, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

182

IMX_DIV(UART2_ROOT_DIV, "uart2_post_div", "uart2_pre_div", 0xb000, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

183

IMX_DIV(UART3_ROOT_DIV, "uart3_post_div", "uart3_pre_div", 0xb080, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

184

IMX_DIV(UART4_ROOT_DIV, "uart4_post_div", "uart4_pre_div", 0xb100, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

185

IMX_DIV(UART5_ROOT_DIV, "uart5_post_div", "uart5_pre_div", 0xb100, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

186

IMX_DIV(UART6_ROOT_DIV, "uart6_post_div", "uart6_pre_div", 0xb200, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

187

IMX_DIV(UART7_ROOT_DIV, "uart7_post_div", "uart7_pre_div", 0xb280, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

197

IMX_MUX(I2C1_ROOT_SRC, "i2c1_src", i2c_p, 0xad80, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

198

IMX_MUX(I2C2_ROOT_SRC, "i2c2_src", i2c_p, 0xae00, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

199

IMX_MUX(I2C3_ROOT_SRC, "i2c3_src", i2c_p, 0xae80, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

200

IMX_MUX(I2C4_ROOT_SRC, "i2c4_src", i2c_p, 0xaf00, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

207

IMX_DIV(I2C1_ROOT_PRE_DIV, "i2c1_pre_div", "i2c1_cg", 0xad80, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

208

IMX_DIV(I2C2_ROOT_PRE_DIV, "i2c2_pre_div", "i2c2_cg", 0xae00, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

209

IMX_DIV(I2C3_ROOT_PRE_DIV, "i2c3_pre_div", "i2c3_cg", 0xae80, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

210

IMX_DIV(I2C4_ROOT_PRE_DIV, "i2c4_pre_div", "i2c4_cg", 0xaf00, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

212

IMX_DIV(I2C1_ROOT_DIV, "i2c1_post_div", "i2c1_pre_div", 0xad80, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

213

IMX_DIV(I2C2_ROOT_DIV, "i2c2_post_div", "i2c2_pre_div", 0xae00, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

214

IMX_DIV(I2C3_ROOT_DIV, "i2c3_post_div", "i2c3_pre_div", 0xae80, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

215

IMX_DIV(I2C4_ROOT_DIV, "i2c4_post_div", "i2c4_pre_div", 0xaf00, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

222

IMX_MUX(ENET_AXI_ROOT_SRC, "enet_axi_src", enet_axi_p, 0x8900, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

224

IMX_DIV(ENET_AXI_ROOT_PRE_DIV, "enet_axi_pre_div", "enet_axi_cg", 0x8900, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

225

IMX_DIV(ENET_AXI_ROOT_DIV, "enet_axi_post_div", "enet_axi_pre_div", 0x8900, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

227

IMX_MUX(ENET1_TIME_ROOT_SRC, "enet1_time_src", enet_time_p, 0xa780, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

228

IMX_MUX(ENET2_TIME_ROOT_SRC, "enet2_time_src", enet_time_p, 0xa880, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

231

IMX_DIV(ENET1_TIME_ROOT_PRE_DIV, "enet1_time_pre_div", "enet1_time_cg", 0xa780, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

232

IMX_DIV(ENET2_TIME_ROOT_PRE_DIV, "enet2_time_pre_div", "enet2_time_cg", 0xa880, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

233

IMX_DIV(ENET1_TIME_ROOT_DIV, "enet1_time_post_div", "enet1_time_pre_div", 0xa780, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

234

IMX_DIV(ENET2_TIME_ROOT_DIV, "enet2_time_post_div", "enet2_time_pre_div", 0xa880, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

241

IMX_MUX(ENET_PHY_REF_ROOT_SRC, "enet_phy_ref_src", enet_phy_ref_p, 0xa900, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

243

IMX_DIV(ENET_PHY_REF_ROOT_PRE_DIV, "enet_phy_ref_pre_div", "enet_phy_ref_cg", 0xa900, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

244

IMX_DIV(ENET_PHY_REF_ROOT_CLK, "enet_phy_ref_root_clk", "enet_phy_ref_pre_div", 0xa900, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

246

IMX_MUX(AHB_CHANNEL_ROOT_SRC, "ahb_src", ahb_channel_p, 0x9000, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

248

IMX_DIV(AHB_CHANNEL_ROOT_PRE_DIV, "ahb_pre_div", "ahb_cg", 0x9000, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

249

IMX_DIV(AHB_CHANNEL_ROOT_DIV, "ahb_root_clk", "ahb_pre_div", 0x9000, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

250

IMX_DIV(IPG_ROOT_CLK, "ipg_root_clk", "ahb_root_clk", 0x9080, __BITS(1,0), IMX_DIV_SET_RATE_PARENT),

sys/arch/arm/nxp/imx7d_ccm.c

252

IMX_MUX(NAND_USDHC_BUS_ROOT_SRC, "nand_usdhc_src", nand_usdhc_p, 0x8980, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

254

IMX_DIV(NAND_USDHC_BUS_ROOT_PRE_DIV, "nand_usdhc_pre_div", "nand_usdhc_cg", 0x8980, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

255

IMX_DIV(NAND_USDHC_BUS_ROOT_CLK, "nand_usdhc_root_clk", "nand_usdhc_pre_div", 0x8980, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

257

IMX_MUX(USDHC1_ROOT_SRC, "usdhc1_src", usdhc_p, 0xab00, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

258

IMX_MUX(USDHC2_ROOT_SRC, "usdhc2_src", usdhc_p, 0xab80, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

259

IMX_MUX(USDHC3_ROOT_SRC, "usdhc3_src", usdhc_p, 0xac00, __BITS(26,24)),

sys/arch/arm/nxp/imx7d_ccm.c

263

IMX_DIV(USDHC1_ROOT_PRE_DIV, "usdhc1_pre_div", "usdhc1_cg", 0xab00, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

264

IMX_DIV(USDHC1_ROOT_PRE_DIV, "usdhc2_pre_div", "usdhc2_cg", 0xab80, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

265

IMX_DIV(USDHC1_ROOT_PRE_DIV, "usdhc3_pre_div", "usdhc3_cg", 0xac00, __BITS(18,16), 0),

sys/arch/arm/nxp/imx7d_ccm.c

266

IMX_DIV(USDHC1_ROOT_DIV, "usdhc1_post_div", "usdhc1_pre_div", 0xab00, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

267

IMX_DIV(USDHC2_ROOT_DIV, "usdhc2_post_div", "usdhc2_pre_div", 0xab80, __BITS(5,0), 0),

sys/arch/arm/nxp/imx7d_ccm.c

268

IMX_DIV(USDHC3_ROOT_DIV, "usdhc3_post_div", "usdhc3_pre_div", 0xac00, __BITS(5,0), 0),

sys/arch/arm/nxp/imx_ahcisatareg.h

48

#define SATA_P0DMACR_RXTS(n) __SHIFTIN(n, __BITS(7, 4))

sys/arch/arm/nxp/imx_ahcisatareg.h

49

#define SATA_P0DMACR_TXTS(n) __SHIFTIN(n, __BITS(3, 0))

sys/arch/arm/nxp/imx_ahcisatareg.h

71

#define SATA_PHY_LANE0_TX_OVRD_TX_EN(n) __SHIFTIN(n, __BITS(3, 1))

sys/arch/arm/nxp/imx_ccm.h

105

IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, __BITS(1,0))

sys/arch/arm/nxp/imx_ccm_composite.c

43

#define TARGET_ROOT_MUX __BITS(26,24)

sys/arch/arm/nxp/imx_ccm_composite.c

44

#define TARGET_ROOT_PRE_PODF __BITS(18,16)

sys/arch/arm/nxp/imx_ccm_composite.c

45

#define TARGET_ROOT_POST_PODF __BITS(5,0)

sys/arch/arm/pci/pci_smccc.c

47

#define GET_SEG_INFO_BUS_START __BITS(7,0)

sys/arch/arm/pci/pci_smccc.c

48

#define GET_SEG_INFO_BUS_END __BITS(15,8)

sys/arch/arm/rockchip/rk3288_cru.c

103

__BITS(7,3), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

107

__BITS(9,8), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

113

__BITS(14,12), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

119

__BITS(9,8), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

126

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

132

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

138

__BITS(13,12), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

146

__BITS(14,13), /* mux_mask */

sys/arch/arm/rockchip/rk3288_cru.c

147

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

157

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

167

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

177

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

187

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

199

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3288_cru.c

200

__BITS(5,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

206

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3288_cru.c

207

__BITS(5,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

213

__BITS(15,14), /* mux_mask */

sys/arch/arm/rockchip/rk3288_cru.c

214

__BITS(13,8), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

220

__BITS(15,14), /* mux_mask */

sys/arch/arm/rockchip/rk3288_cru.c

221

__BITS(13,8), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

229

__BITS(1,0), /* mux_mask */

sys/arch/arm/rockchip/rk3288_cru.c

230

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

238

__BITS(7,6), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

247

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

254

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

261

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

269

__BITS(5,0), /* div_mask */

sys/arch/arm/rockchip/rk3288_cru.c

274

RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(2,0), 0),

sys/arch/arm/rockchip/rk3288_cru.c

275

RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0),

sys/arch/arm/rockchip/rk3288_cru.c

276

RK_DIV(0, "pclk_pd_alive", "gpll", CLKSEL_CON(33), __BITS(12,8), 0),

sys/arch/arm/rockchip/rk3288_cru.c

278

RK_MUX(RK3288_SCLK_UART0, "sclk_uart0", uart0_parents, CLKSEL_CON(13), __BITS(9,8)),

sys/arch/arm/rockchip/rk3288_cru.c

279

RK_MUX(RK3288_SCLK_UART1, "sclk_uart1", uart1_parents, CLKSEL_CON(14), __BITS(9,8)),

sys/arch/arm/rockchip/rk3288_cru.c

280

RK_MUX(RK3288_SCLK_UART2, "sclk_uart2", uart2_parents, CLKSEL_CON(15), __BITS(9,8)),

sys/arch/arm/rockchip/rk3288_cru.c

281

RK_MUX(RK3288_SCLK_UART3, "sclk_uart3", uart3_parents, CLKSEL_CON(16), __BITS(9,8)),

sys/arch/arm/rockchip/rk3288_cru.c

282

RK_MUX(RK3288_SCLK_UART4, "sclk_uart4", uart4_parents, CLKSEL_CON(3), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

196

__BITS(7,6), 3, 1, /* mux_mask, mux_main, mux_alt */

sys/arch/arm/rockchip/rk3328_cru.c

197

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

202

__BITS(14,13), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

203

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

210

__BITS(9,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

217

__BITS(14,12), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

224

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

231

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

237

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

238

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

244

__BITS(1,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

251

__BITS(6,4), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

257

__BITS(9,8), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

258

__BITS(7,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

264

__BITS(9,8), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

265

__BITS(7,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

271

__BITS(9,8), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

272

__BITS(7,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

278

__BITS(13,12), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

279

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

285

__BITS(13,12), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

286

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

292

__BITS(13,12), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

293

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

299

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3328_cru.c

300

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

307

__BITS(10,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

314

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

321

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

328

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

335

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

342

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

349

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

356

__BITS(9,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

363

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

368

RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0),

sys/arch/arm/rockchip/rk3328_cru.c

415

RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, CLKSEL_CON(14), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

416

RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, CLKSEL_CON(16), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

417

RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, CLKSEL_CON(18), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

425

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

432

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

439

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

446

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3328_cru.c

462

RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(6), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

463

RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(8), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

464

RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(10), __BITS(9,8)),

sys/arch/arm/rockchip/rk3328_cru.c

465

RK_MUX(0, "clk_spdif_mux", mux_spdif_parents, CLKSEL_CON(10), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

1002

__BITS(15,14), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1003

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1009

__BITS(14,10), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1016

__BITS(9,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1027

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1034

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1041

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1054

RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

1055

RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

1056

RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

1063

RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)),

sys/arch/arm/rockchip/rk3399_cru.c

1076

__BITS(13,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1085

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1086

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1094

__BITS(7,5), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1095

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

1137

write_mask = __BITS(7,0) << 16;

sys/arch/arm/rockchip/rk3399_cru.c

142

#define RK3399_ACLKM_MASK __BITS(12,8)

sys/arch/arm/rockchip/rk3399_cru.c

143

#define RK3399_ATCLK_MASK __BITS(4,0)

sys/arch/arm/rockchip/rk3399_cru.c

144

#define RK3399_PDBG_MASK __BITS(12,8)

sys/arch/arm/rockchip/rk3399_cru.c

212

#define PLL_FBDIV __BITS(11,0)

sys/arch/arm/rockchip/rk3399_cru.c

215

#define PLL_POSTDIV2 __BITS(14,12)

sys/arch/arm/rockchip/rk3399_cru.c

216

#define PLL_POSTDIV1 __BITS(10,8)

sys/arch/arm/rockchip/rk3399_cru.c

217

#define PLL_REFDIV __BITS(5,0)

sys/arch/arm/rockchip/rk3399_cru.c

221

#define PLL_FRACDIV __BITS(23,0)

sys/arch/arm/rockchip/rk3399_cru.c

224

#define PLL_WORK_MODE __BITS(9,8)

sys/arch/arm/rockchip/rk3399_cru.c

446

__BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */

sys/arch/arm/rockchip/rk3399_cru.c

448

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

458

__BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */

sys/arch/arm/rockchip/rk3399_cru.c

460

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

471

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

477

__BITS(10,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

483

__BITS(14,12), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

495

__BITS(10,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

496

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

500

__BITS(10,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

513

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

519

__BITS(10,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

525

__BITS(14,12), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

539

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

540

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

552

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

563

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

571

RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0),

sys/arch/arm/rockchip/rk3399_cru.c

583

RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)),

sys/arch/arm/rockchip/rk3399_cru.c

587

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

593

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

599

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

605

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

609

RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

610

RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

611

RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

612

RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)),

sys/arch/arm/rockchip/rk3399_cru.c

624

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

630

__BITS(10,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

631

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

637

__BITS(10,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

638

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

650

__BITS(10,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

651

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

660

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

671

__BITS(15,14), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

672

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

686

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

693

__BITS(10,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

717

__BITS(9,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

724

__BITS(9,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

730

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

731

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

744

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

750

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

751

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

758

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

764

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

765

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

776

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

783

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

790

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

797

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

804

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

811

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

828

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

835

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

842

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

849

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

856

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

875

__BITS(10,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

876

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

882

__BITS(15,11), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

889

__BITS(9,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

890

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

899

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

900

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

906

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

907

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

921

__BITS(9,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

930

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

931

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

937

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

943

__BITS(9,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

944

__BITS(7,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

958

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

959

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

965

__BITS(12,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

971

__BITS(9,8), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

972

__BITS(7,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

986

__BITS(7,6), /* mux_mask */

sys/arch/arm/rockchip/rk3399_cru.c

987

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_cru.c

993

__BITS(4,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_iomux.c

466

#define GRF_GPIO4B_IOMUX_TCK __BITS(5,4)

sys/arch/arm/rockchip/rk3399_iomux.c

467

#define GRF_GPIO4B_IOMUX_TMS __BITS(7,6)

sys/arch/arm/rockchip/rk3399_pcie.c

54

#define PCBSC_LANE_COUNT __BITS(5,4)

sys/arch/arm/rockchip/rk3399_pcie.c

64

#define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20))

sys/arch/arm/rockchip/rk3399_pcie.c

83

#define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8)

sys/arch/arm/rockchip/rk3399_pcie.c

99

#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20)

sys/arch/arm/rockchip/rk3399_pmucru.c

140

#define PLL_FBDIV __BITS(11,0)

sys/arch/arm/rockchip/rk3399_pmucru.c

143

#define PLL_POSTDIV2 __BITS(14,12)

sys/arch/arm/rockchip/rk3399_pmucru.c

144

#define PLL_POSTDIV1 __BITS(10,8)

sys/arch/arm/rockchip/rk3399_pmucru.c

145

#define PLL_REFDIV __BITS(5,0)

sys/arch/arm/rockchip/rk3399_pmucru.c

149

#define PLL_FRACDIV __BITS(23,0)

sys/arch/arm/rockchip/rk3399_pmucru.c

152

#define PLL_WORK_MODE __BITS(9,8)

sys/arch/arm/rockchip/rk3399_pmucru.c

298

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_pmucru.c

304

__BITS(6,0), /* div_mask */

sys/arch/arm/rockchip/rk3399_pmucru.c

310

__BITS(14,8), /* div_mask */

sys/arch/arm/rockchip/rk3399_pmucru.c

315

RK_DIV(RK3399_PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLKSEL_CON(0), __BITS(4,0), 0),

sys/arch/arm/rockchip/rk3588_cru.c

1003

CLKSEL_CON(0, 28), __BITS(3,2)),

sys/arch/arm/rockchip/rk3588_cru.c

1008

CLKSEL_CON(0, 36), __BITS(8,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1015

CLKSEL_CON(0, 32), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

1023

CLKSEL_CON(0, 34), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1030

CLKSEL_CON(0, 34), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1038

CLKSEL_CON(0, 36), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1043

CLKSEL_CON(0, 163), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1048

CLKSEL_CON(0, 163), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

1053

CLKSEL_CON(0, 38), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1074

CLKSEL_CON(0, 59), __BITS(13,12),

sys/arch/arm/rockchip/rk3588_cru.c

1083

CLKSEL_CON(0, 59), __BITS(15,14),

sys/arch/arm/rockchip/rk3588_cru.c

1092

CLKSEL_CON(0, 60), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1103

CLKSEL_CON(0, 60), __BITS(2,2),

sys/arch/arm/rockchip/rk3588_cru.c

1138

CLKSEL_CON(0, 39), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1145

CLKSEL_CON(0, 39), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

1152

CLKSEL_CON(0, 40), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1161

CLKSEL_CON(0, 62), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1176

CLKSEL_CON(0, 60), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

1183

CLKSEL_CON(0, 60), __BITS(14,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

1190

CLKSEL_CON(0, 61), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1197

CLKSEL_CON(0, 61), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

1218

CLKSEL_CON(0, 38), __BITS(6,6),

sys/arch/arm/rockchip/rk3588_cru.c

1223

CLKSEL_CON(0, 38), __BITS(7,7),

sys/arch/arm/rockchip/rk3588_cru.c

1228

CLKSEL_CON(0, 38), __BITS(8,8),

sys/arch/arm/rockchip/rk3588_cru.c

1233

CLKSEL_CON(0, 38), __BITS(9,9),

sys/arch/arm/rockchip/rk3588_cru.c

1238

CLKSEL_CON(0, 38), __BITS(10,10),

sys/arch/arm/rockchip/rk3588_cru.c

1243

CLKSEL_CON(0, 38), __BITS(11,11),

sys/arch/arm/rockchip/rk3588_cru.c

1248

CLKSEL_CON(0, 38), __BITS(12,12),

sys/arch/arm/rockchip/rk3588_cru.c

1253

CLKSEL_CON(0, 38), __BITS(13,13),

sys/arch/arm/rockchip/rk3588_cru.c

1270

CLKSEL_CON(0, 40), __BITS(14,14), __BITS(13,6),

sys/arch/arm/rockchip/rk3588_cru.c

1285

CLKSEL_CON(0, 59), __BITS(3,2),

sys/arch/arm/rockchip/rk3588_cru.c

1290

CLKSEL_CON(0, 59), __BITS(5,4),

sys/arch/arm/rockchip/rk3588_cru.c

1295

CLKSEL_CON(0, 59), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

1300

CLKSEL_CON(0, 59), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

1305

CLKSEL_CON(0, 59), __BITS(11,10),

sys/arch/arm/rockchip/rk3588_cru.c

1314

CLKSEL_CON(0, 41), __BITS(8,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

1337

CLKSEL_CON(0, 41), __BITS(14,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

1345

CLKSEL_CON(0, 43), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1350

CLKSEL_CON(0, 43), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1358

CLKSEL_CON(0, 45), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1363

CLKSEL_CON(0, 45), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1371

CLKSEL_CON(0, 47), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1376

CLKSEL_CON(0, 47), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1384

CLKSEL_CON(0, 49), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1389

CLKSEL_CON(0, 49), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1397

CLKSEL_CON(0, 51), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1402

CLKSEL_CON(0, 51), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1410

CLKSEL_CON(0, 53), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1415

CLKSEL_CON(0, 53), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1423

CLKSEL_CON(0, 55), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1428

CLKSEL_CON(0, 55), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1436

CLKSEL_CON(0, 57), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1441

CLKSEL_CON(0, 57), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1449

CLKSEL_CON(0, 59), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

1454

CLKSEL_CON(0, 165), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1459

CLKSEL_CON(0, 165), __BITS(3,2),

sys/arch/arm/rockchip/rk3588_cru.c

1464

CLKSEL_CON(0, 165), __BITS(5,4),

sys/arch/arm/rockchip/rk3588_cru.c

1469

CLKSEL_CON(0, 165), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

1480

CLKSEL_CON(0, 165), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

1485

CLKSEL_CON(0, 165), __BITS(11,10),

sys/arch/arm/rockchip/rk3588_cru.c

1493

CLKSEL_CON(0, 165), __BITS(12,12),

sys/arch/arm/rockchip/rk3588_cru.c

1504

CLKSEL_CON(0, 166), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1517

CLKSEL_CON(0, 158), __BITS(7,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1526

CLKSEL_CON(0, 159), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1535

CLKSEL_CON(0, 67), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1540

CLKSEL_CON(0, 67), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

1545

CLKSEL_CON(0, 67), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

1556

CLKSEL_CON(0, 73), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1561

CLKSEL_CON(0, 73), __BITS(9,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1566

CLKSEL_CON(0, 74), __BITS(2,1),

sys/arch/arm/rockchip/rk3588_cru.c

1579

CLKSEL_CON(0, 74), __BITS(6,5),

sys/arch/arm/rockchip/rk3588_cru.c

1587

CLKSEL_CON(0, 74), __BITS(12,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

1606

CLKSEL_CON(0, 74), __BITS(3,3),

sys/arch/arm/rockchip/rk3588_cru.c

1619

CLKSEL_CON(0, 77), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1624

CLKSEL_CON(0, 77), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1631

CLKSEL_CON(0, 77), __BITS(15,14), __BITS(13,8),

sys/arch/arm/rockchip/rk3588_cru.c

1636

CLKSEL_CON(0, 78), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1643

CLKSEL_CON(0, 78), __BITS(13,12), __BITS(11,6),

sys/arch/arm/rockchip/rk3588_cru.c

1648

CLKSEL_CON(0, 81), __BITS(6,6), __BITS(5,0),

sys/arch/arm/rockchip/rk3588_cru.c

1653

CLKSEL_CON(0, 81), __BITS(13,13), __BITS(12,7),

sys/arch/arm/rockchip/rk3588_cru.c

1658

CLKSEL_CON(0, 83), __BITS(15,15), __BITS(14,8),

sys/arch/arm/rockchip/rk3588_cru.c

1663

CLKSEL_CON(0, 84), __BITS(7,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

1668

CLKSEL_CON(0, 80), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1673

CLKSEL_CON(0, 80), __BITS(13,13), __BITS(12,8),

sys/arch/arm/rockchip/rk3588_cru.c

1678

CLKSEL_CON(0, 80), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1770

CLKSEL_CON(0, 82), __BITS(7,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

1775

CLKSEL_CON(0, 82), __BITS(15,15), __BITS(14,8),

sys/arch/arm/rockchip/rk3588_cru.c

1780

CLKSEL_CON(0, 83), __BITS(7,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

1791

CLKSEL_CON(0, 84), __BITS(13,12), __BITS(11,8),

sys/arch/arm/rockchip/rk3588_cru.c

1808

CLKSEL_CON(0, 174), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

1813

CLKSEL_CON(0, 174), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1818

CLKSEL_CON(0, 174), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

1827

CLKSEL_CON(0, 89), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1832

CLKSEL_CON(0, 89), __BITS(8,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1837

CLKSEL_CON(0, 89), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

1842

CLKSEL_CON(0, 90), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1847

CLKSEL_CON(0, 90), __BITS(12,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

1852

CLKSEL_CON(0, 91), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1857

CLKSEL_CON(0, 93), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1862

CLKSEL_CON(0, 93), __BITS(8,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1867

CLKSEL_CON(0, 93), __BITS(14,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

1872

CLKSEL_CON(0, 94), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1877

CLKSEL_CON(0, 94), __BITS(12,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

1882

CLKSEL_CON(0, 172), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1887

CLKSEL_CON(0, 172), __BITS(9,8), __BITS(7,2),

sys/arch/arm/rockchip/rk3588_cru.c

189

#define RK3588_CLK_CORE_B_SEL_MASK __BITS(14,13)

sys/arch/arm/rockchip/rk3588_cru.c

1892

CLKSEL_CON(0, 96), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1897

CLKSEL_CON(0, 96), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

190

#define RK3588_CLK_CORE_B_GPLL_DIV_MASK __BITS(5,1)

sys/arch/arm/rockchip/rk3588_cru.c

1910

CLKSEL_CON(0, 98), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1915

CLKSEL_CON(0, 98), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

1920

CLKSEL_CON(0, 98), __BITS(10,9),

sys/arch/arm/rockchip/rk3588_cru.c

1925

CLKSEL_CON(0, 99), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1932

CLKSEL_CON(0, 99), __BITS(12,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

1955

CLKSEL_CON(0, 100), __BITS(7,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

1964

CLKSEL_CON(0, 100), __BITS(15,13), __BITS(12,8),

sys/arch/arm/rockchip/rk3588_cru.c

1971

CLKSEL_CON(0, 104), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1976

CLKSEL_CON(0, 104), __BITS(8,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1981

CLKSEL_CON(0, 102), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

1986

CLKSEL_CON(0, 102), __BITS(8,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

1995

CLKSEL_CON(0, 102), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

2000

CLKSEL_CON(0, 104), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

2005

CLKSEL_CON(0, 106), __BITS(7,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2010

CLKSEL_CON(0, 106), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

2015

CLKSEL_CON(0, 106), __BITS(11,10),

sys/arch/arm/rockchip/rk3588_cru.c

2020

CLKSEL_CON(0, 108), __BITS(15,14),

sys/arch/arm/rockchip/rk3588_cru.c

2045

CLKSEL_CON(0, 108), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2054

CLKSEL_CON(0, 108), __BITS(13,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

2059

CLKSEL_CON(0, 107), __BITS(12,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

2074

CLKSEL_CON(0, 107), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2083

CLKSEL_CON(0, 116), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2088

CLKSEL_CON(0, 116), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

2093

CLKSEL_CON(0, 116), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

2098

CLKSEL_CON(0, 116), __BITS(11,10),

sys/arch/arm/rockchip/rk3588_cru.c

2103

CLKSEL_CON(0, 116), __BITS(13,12),

sys/arch/arm/rockchip/rk3588_cru.c

2130

CLKSEL_CON(0, 118), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2139

CLKSEL_CON(0, 120), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2144

CLKSEL_CON(0, 120), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

2153

CLKSEL_CON(0, 122), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2158

CLKSEL_CON(0, 122), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

2166

CLKSEL_CON(0, 124), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2173

CLKSEL_CON(0, 124), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2181

CLKSEL_CON(0, 126), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2187

CLKSEL_CON(0, 117), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

2191

CLKSEL_CON(0, 117), __BITS(15,8),

sys/arch/arm/rockchip/rk3588_cru.c

2196

CLKSEL_CON(0, 157), __BITS(7,7),

sys/arch/arm/rockchip/rk3588_cru.c

2197

__BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2202

CLKSEL_CON(0, 128), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2207

CLKSEL_CON(0, 128), __BITS(12,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

2212

CLKSEL_CON(0, 128), __BITS(14,13),

sys/arch/arm/rockchip/rk3588_cru.c

2217

CLKSEL_CON(0, 129), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

2222

CLKSEL_CON(0, 129), __BITS(3,2),

sys/arch/arm/rockchip/rk3588_cru.c

2227

CLKSEL_CON(0, 129), __BITS(5,4),

sys/arch/arm/rockchip/rk3588_cru.c

2232

CLKSEL_CON(0, 110), __BITS(7,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2237

CLKSEL_CON(0, 110), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

2242

CLKSEL_CON(0, 110), __BITS(11,10),

sys/arch/arm/rockchip/rk3588_cru.c

2247

CLKSEL_CON(0, 110), __BITS(13,12),

sys/arch/arm/rockchip/rk3588_cru.c

2252

CLKSEL_CON(0, 170), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2257

CLKSEL_CON(0, 170), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

2262

CLKSEL_CON(0, 115), __BITS(9,9)),

sys/arch/arm/rockchip/rk3588_cru.c

2269

CLKSEL_CON(0, 140), __BITS(2,1),

sys/arch/arm/rockchip/rk3588_cru.c

2278

CLKSEL_CON(0, 140), __BITS(4,3),

sys/arch/arm/rockchip/rk3588_cru.c

2293

CLKSEL_CON(0, 138), __BITS(8,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

2306

CLKSEL_CON(0, 133), __BITS(6,6), __BITS(5,1),

sys/arch/arm/rockchip/rk3588_cru.c

2315

CLKSEL_CON(0, 136), __BITS(6,6), __BITS(5,1),

sys/arch/arm/rockchip/rk3588_cru.c

2334

CLKSEL_CON(0, 155), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

2343

CLKSEL_CON(0, 157), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2349

CLKSEL_CON(0, 129), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

2358

CLKSEL_CON(0, 131), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2363

CLKSEL_CON(0, 153), __BITS(12,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

2372

CLKSEL_CON(0, 155), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2377

CLKSEL_CON(0, 140), __BITS(10,10), __BITS(9,5),

sys/arch/arm/rockchip/rk3588_cru.c

2386

CLKSEL_CON(0, 142), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2391

CLKSEL_CON(0, 144), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

2400

CLKSEL_CON(0, 146), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2405

CLKSEL_CON(0, 146), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2414

CLKSEL_CON(0, 148), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2419

CLKSEL_CON(0, 148), __BITS(3,2)),

sys/arch/arm/rockchip/rk3588_cru.c

2422

CLKSEL_CON(0, 148), __BITS(9,9), __BITS(8,4),

sys/arch/arm/rockchip/rk3588_cru.c

2430

CLKSEL_CON(0, 150), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2435

CLKSEL_CON(0, 150), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2443

CLKSEL_CON(0, 152), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2448

CLKSEL_CON(0, 152), __BITS(8,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2453

CLKSEL_CON(0, 152), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

2458

CLKSEL_CON(0, 153), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2479

CLKSEL_CON(0, 111), __BITS(8,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

2484

CLKSEL_CON(0, 111), __BITS(15,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

2489

CLKSEL_CON(0, 112), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2494

CLKSEL_CON(0, 112), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

2499

CLKSEL_CON(0, 112), __BITS(10,9),

sys/arch/arm/rockchip/rk3588_cru.c

2504

CLKSEL_CON(0, 112), __BITS(12,11),

sys/arch/arm/rockchip/rk3588_cru.c

2509

CLKSEL_CON(0, 113), __BITS(8,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

2518

CLKSEL_CON(0, 114), __BITS(8,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

2523

CLKSEL_CON(0, 115), __BITS(8,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

2547

CLKSEL_CON(0, 176), __BITS(5,0),

sys/arch/arm/rockchip/rk3588_cru.c

2552

CLKSEL_CON(0, 176), __BITS(11,6),

sys/arch/arm/rockchip/rk3588_cru.c

2557

CLKSEL_CON(0, 177), __BITS(5,0),

sys/arch/arm/rockchip/rk3588_cru.c

2562

CLKSEL_CON(0, 177), __BITS(6,6)),

sys/arch/arm/rockchip/rk3588_cru.c

2565

CLKSEL_CON(0, 177), __BITS(7,7)),

sys/arch/arm/rockchip/rk3588_cru.c

2568

CLKSEL_CON(0, 177), __BITS(8,8)),

sys/arch/arm/rockchip/rk3588_cru.c

2571

CLKSEL_CON(PMU, 0), __BITS(15,15), __BITS(14,10),

sys/arch/arm/rockchip/rk3588_cru.c

2576

CLKSEL_CON(PMU, 1), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2581

CLKSEL_CON(PMU, 0), __BITS(3,0),

sys/arch/arm/rockchip/rk3588_cru.c

2586

CLKSEL_CON(PMU, 0), __BITS(6,4),

sys/arch/arm/rockchip/rk3588_cru.c

2591

CLKSEL_CON(PMU, 0), __BITS(9,7),

sys/arch/arm/rockchip/rk3588_cru.c

2596

CLKSEL_CON(PMU, 1), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

2601

CLKSEL_CON(PMU, 1), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

2608

CLKSEL_CON(PMU, 1), __BITS(11,10),

sys/arch/arm/rockchip/rk3588_cru.c

2621

CLKSEL_CON(PMU, 17), __BITS(0,0),

sys/arch/arm/rockchip/rk3588_cru.c

2628

CLKSEL_CON(PMU, 3), __BITS(6,6),

sys/arch/arm/rockchip/rk3588_cru.c

2635

CLKSEL_CON(PMU, 5), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2644

CLKSEL_CON(PMU, 7), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2649

CLKSEL_CON(PMU, 7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

2658

CLKSEL_CON(PMU, 9), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2663

CLKSEL_CON(PMU, 9), __BITS(3,2)),

sys/arch/arm/rockchip/rk3588_cru.c

2674

CLKSEL_CON(PMU, 9), __BITS(4,4),

sys/arch/arm/rockchip/rk3588_cru.c

2684

CLKSEL_CON(PMU, 2), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2693

CLKSEL_CON(PMU, 2), __BITS(10,9),

sys/arch/arm/rockchip/rk3588_cru.c

2702

CLKSEL_CON(PMU, 2), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

2710

CLKSEL_CON(PMU, 3), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

2718

CLKSEL_CON(PMU, 5), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

2727

CLKSEL_CON(PMU, 2), __BITS(6,6),

sys/arch/arm/rockchip/rk3588_cru.c

2732

CLKSEL_CON(PMU, 15), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

2737

CLKSEL_CON(PMU, 14), __BITS(14,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

2742

CLKSEL_CON(PMU, 14), __BITS(8,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

621

__BITS(15,14), 2, 1, /* mux_mask, mux_main, mux_alt */

sys/arch/arm/rockchip/rk3588_cru.c

623

__BITS(4,0), /* div0_mask */

sys/arch/arm/rockchip/rk3588_cru.c

625

__BITS(11,7), /* div1_mask */

sys/arch/arm/rockchip/rk3588_cru.c

627

__BITS(4,0), /* div2_mask */

sys/arch/arm/rockchip/rk3588_cru.c

629

__BITS(11,7), /* div3_mask */

sys/arch/arm/rockchip/rk3588_cru.c

633

__BITS(7,6), 2, 1, /* mux_mask, mux_main, mux_alt */

sys/arch/arm/rockchip/rk3588_cru.c

635

__BITS(12,8), /* div0_mask */

sys/arch/arm/rockchip/rk3588_cru.c

637

__BITS(4,0), /* div1_mask */

sys/arch/arm/rockchip/rk3588_cru.c

641

__BITS(7,6), 2, 1, /* mux_mask, mux_main, mux_alt */

sys/arch/arm/rockchip/rk3588_cru.c

643

__BITS(12,8), /* div0_mask */

sys/arch/arm/rockchip/rk3588_cru.c

645

__BITS(4,0), /* div1_mask */

sys/arch/arm/rockchip/rk3588_cru.c

65

#define RK3588_CLK_CORE_L_SEL_MASK __BITS(6,5)

sys/arch/arm/rockchip/rk3588_cru.c

650

CLKSEL_CON(BIGCORE0, 2), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

664

CLKSEL_CON(BIGCORE1, 2), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

67

#define RK3588_CLK_DSU_DF_SRC_MASK __BITS(6,5)

sys/arch/arm/rockchip/rk3588_cru.c

678

CLKSEL_CON(0, 0), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

68

#define RK3588_CLK_DSU_DF_DIV_MASK __BITS(4,0)

sys/arch/arm/rockchip/rk3588_cru.c

683

CLKSEL_CON(0, 0), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

688

CLKSEL_CON(0, 1), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

69

#define RK3588_ACLKM_DSU_DIV_MASK __BITS(5,1)

sys/arch/arm/rockchip/rk3588_cru.c

693

CLKSEL_CON(0, 1), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

698

CLKSEL_CON(0, 2), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

70

#define RK3588_ACLKS_DSU_DIV_MASK __BITS(10,6)

sys/arch/arm/rockchip/rk3588_cru.c

703

CLKSEL_CON(0, 2), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

708

CLKSEL_CON(0, 3), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

71

#define RK3588_ACLKMP_DSU_DIV_MASK __BITS(15,11)

sys/arch/arm/rockchip/rk3588_cru.c

713

CLKSEL_CON(0, 3), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

718

CLKSEL_CON(0, 4), __BITS(5,5),

sys/arch/arm/rockchip/rk3588_cru.c

719

__BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

72

#define RK3588_PERIPH_DSU_DIV_MASK __BITS(4,0)

sys/arch/arm/rockchip/rk3588_cru.c

724

CLKSEL_CON(0, 4), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

729

CLKSEL_CON(0, 5), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

73

#define RK3588_ATCLK_DSU_DIV_MASK __BITS(4,0)

sys/arch/arm/rockchip/rk3588_cru.c

734

CLKSEL_CON(0, 5), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

739

CLKSEL_CON(0, 6), __BITS(5,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

74

#define RK3588_GICCLK_DSU_DIV_MASK __BITS(9,5)

sys/arch/arm/rockchip/rk3588_cru.c

744

CLKSEL_CON(0, 6), __BITS(11,11), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

749

CLKSEL_CON(0, 7), __BITS(6,5),

sys/arch/arm/rockchip/rk3588_cru.c

750

__BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

755

CLKSEL_CON(0, 7), __BITS(12,12), __BITS(11,7),

sys/arch/arm/rockchip/rk3588_cru.c

760

CLKSEL_CON(0, 9), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

765

CLKSEL_CON(0, 9), __BITS(3,2),

sys/arch/arm/rockchip/rk3588_cru.c

770

CLKSEL_CON(0, 9), __BITS(5,4),

sys/arch/arm/rockchip/rk3588_cru.c

775

CLKSEL_CON(0, 9), __BITS(7,6),

sys/arch/arm/rockchip/rk3588_cru.c

780

CLKSEL_CON(0, 9), __BITS(9,8),

sys/arch/arm/rockchip/rk3588_cru.c

785

CLKSEL_CON(0, 8), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

790

CLKSEL_CON(0, 8), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

795

CLKSEL_CON(0, 8), __BITS(14,14), __BITS(13,9),

sys/arch/arm/rockchip/rk3588_cru.c

800

CLKSEL_CON(0, 18), __BITS(9,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

805

CLKSEL_CON(0, 19), __BITS(9,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

810

CLKSEL_CON(0, 20), __BITS(9,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

815

CLKSEL_CON(0, 21), __BITS(9,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

820

CLKSEL_CON(0, 22), __BITS(9,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

825

CLKSEL_CON(0, 15), __BITS(7,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

830

CLKSEL_CON(0, 15), __BITS(15,15), __BITS(14,8),

sys/arch/arm/rockchip/rk3588_cru.c

835

CLKSEL_CON(0, 16), __BITS(7,7), __BITS(6,0),

sys/arch/arm/rockchip/rk3588_cru.c

840

CLKSEL_CON(0, 17), __BITS(9,8), __BITS(7,0),

sys/arch/arm/rockchip/rk3588_cru.c

855

CLKSEL_CON(DSU, 0), __BITS(13,12), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

859

CLKSEL_CON(DSU, 3), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

863

CLKSEL_CON(DSU, 3), __BITS(9,5),

sys/arch/arm/rockchip/rk3588_cru.c

867

CLKSEL_CON(DSU, 1), __BITS(15,11),

sys/arch/arm/rockchip/rk3588_cru.c

871

CLKSEL_CON(DSU, 1), __BITS(5,1),

sys/arch/arm/rockchip/rk3588_cru.c

875

CLKSEL_CON(DSU, 1), __BITS(10,6),

sys/arch/arm/rockchip/rk3588_cru.c

879

CLKSEL_CON(DSU, 2), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

883

CLKSEL_CON(DSU, 2), __BITS(9,5),

sys/arch/arm/rockchip/rk3588_cru.c

887

CLKSEL_CON(DSU, 2), __BITS(14,10),

sys/arch/arm/rockchip/rk3588_cru.c

892

CLKSEL_CON(DSU, 4), __BITS(12,11),

sys/arch/arm/rockchip/rk3588_cru.c

897

CLKSEL_CON(DSU, 4), __BITS(6,5), __BITS(4,0),

sys/arch/arm/rockchip/rk3588_cru.c

902

CLKSEL_CON(DSU, 4), __BITS(8,7),

sys/arch/arm/rockchip/rk3588_cru.c

923

CLKSEL_CON(0, 24), __BITS(1,0),

sys/arch/arm/rockchip/rk3588_cru.c

928

CLKSEL_CON(0, 24), __BITS(3,2),

sys/arch/arm/rockchip/rk3588_cru.c

937

CLKSEL_CON(0, 28), __BITS(9,9), __BITS(8,4),

sys/arch/arm/rockchip/rk3588_cru.c

945

CLKSEL_CON(0, 30), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

950

CLKSEL_CON(0, 30), __BITS(2,2)),

sys/arch/arm/rockchip/rk3588_cru.c

953

CLKSEL_CON(0, 30), __BITS(8,8), __BITS(7,3),

sys/arch/arm/rockchip/rk3588_cru.c

961

CLKSEL_CON(0, 32), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

968

CLKSEL_CON(0, 32), __BITS(2,2)),

sys/arch/arm/rockchip/rk3588_cru.c

975

CLKSEL_CON(0, 24), __BITS(9,9), __BITS(8,4),

sys/arch/arm/rockchip/rk3588_cru.c

984

CLKSEL_CON(0, 26), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_cru.c

989

CLKSEL_CON(0, 26), __BITS(7,7), __BITS(6,2),

sys/arch/arm/rockchip/rk3588_cru.c

998

CLKSEL_CON(0, 28), __BITS(1,0)),

sys/arch/arm/rockchip/rk3588_iomux.c

100

{ RK3588_PMU2_IOC_REG + 0x0014, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

101

{ RK3588_PMU2_IOC_REG + 0x0014, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

103

{ RK3588_PMU2_IOC_REG + 0x0018, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

104

{ RK3588_PMU2_IOC_REG + 0x0018, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

105

{ RK3588_PMU2_IOC_REG + 0x0018, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

106

{ RK3588_PMU2_IOC_REG + 0x0018, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

107

{ RK3588_PMU2_IOC_REG + 0x001c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

108

{ RK3588_PMU2_IOC_REG + 0x001c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

109

{ RK3588_PMU2_IOC_REG + 0x001c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

110

{ RK3588_PMU2_IOC_REG + 0x001c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

112

{ RK3588_PMU2_IOC_REG + 0x0020, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

113

{ RK3588_PMU2_IOC_REG + 0x0020, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

114

{ RK3588_PMU2_IOC_REG + 0x0020, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

115

{ RK3588_PMU2_IOC_REG + 0x0020, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

116

{ RK3588_PMU2_IOC_REG + 0x0024, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

117

{ RK3588_PMU2_IOC_REG + 0x0024, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

118

{ RK3588_PMU2_IOC_REG + 0x0024, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

119

{ RK3588_PMU2_IOC_REG + 0x0024, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

122

{ RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

123

{ RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

124

{ RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

125

{ RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

126

{ RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

127

{ RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

128

{ RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

129

{ RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

131

{ RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

132

{ RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

133

{ RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

134

{ RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

135

{ RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

136

{ RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

137

{ RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

138

{ RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

140

{ RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

141

{ RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

142

{ RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

143

{ RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

144

{ RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

145

{ RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

146

{ RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

147

{ RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

149

{ RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

150

{ RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

151

{ RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

152

{ RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

153

{ RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

154

{ RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

155

{ RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

156

{ RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

159

{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

160

{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

161

{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

162

{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

163

{ RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

164

{ RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

165

{ RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

166

{ RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

168

{ RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

169

{ RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

170

{ RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

171

{ RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

172

{ RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

173

{ RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

174

{ RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

175

{ RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

177

{ RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

178

{ RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

179

{ RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

180

{ RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

181

{ RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

182

{ RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

183

{ RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

184

{ RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

186

{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

187

{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

188

{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

189

{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

190

{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

191

{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

192

{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

193

{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

196

{ RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

197

{ RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

198

{ RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

199

{ RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

200

{ RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

201

{ RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

202

{ RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

203

{ RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

205

{ RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

206

{ RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

207

{ RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

208

{ RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

209

{ RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

210

{ RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

211

{ RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

212

{ RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

214

{ RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

215

{ RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

216

{ RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

217

{ RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

218

{ RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

219

{ RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

220

{ RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

221

{ RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

223

{ RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

224

{ RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

225

{ RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

226

{ RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

227

{ RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

228

{ RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

229

{ RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

230

{ RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

233

{ RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

234

{ RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

235

{ RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

236

{ RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

237

{ RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

238

{ RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

239

{ RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

240

{ RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

242

{ RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

243

{ RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

244

{ RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

245

{ RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

246

{ RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

247

{ RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

248

{ RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

249

{ RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

251

{ RK3588_VCCIO6_IOC_REG + 0x0090, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

252

{ RK3588_VCCIO6_IOC_REG + 0x0090, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

253

{ RK3588_VCCIO3_5_IOC_REG + 0x0090, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

254

{ RK3588_VCCIO3_5_IOC_REG + 0x0090, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

255

{ RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

256

{ RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

257

{ RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

258

{ RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

260

{ RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

261

{ RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

262

{ RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

263

{ RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

264

{ RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

265

{ RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

266

{ RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

267

{ RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(15,12) }

sys/arch/arm/rockchip/rk3588_iomux.c

277

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

278

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

279

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

280

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

281

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

282

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

283

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

284

{ RK3588_PMU1_IOC_REG + 0x0020, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

286

{ RK3588_PMU1_IOC_REG + 0x0024, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

287

{ RK3588_PMU1_IOC_REG + 0x0024, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

288

{ RK3588_PMU1_IOC_REG + 0x0024, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

289

{ RK3588_PMU1_IOC_REG + 0x0024, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

290

{ RK3588_PMU1_IOC_REG + 0x0024, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

291

{ RK3588_PMU2_IOC_REG + 0x0028, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

292

{ RK3588_PMU2_IOC_REG + 0x0028, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

293

{ RK3588_PMU2_IOC_REG + 0x0028, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

295

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

296

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

297

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

298

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

299

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

300

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

301

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

302

{ RK3588_PMU2_IOC_REG + 0x002c, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

304

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

305

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

306

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

307

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

308

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

309

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

310

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

311

{ RK3588_PMU2_IOC_REG + 0x0030, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

314

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

315

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

316

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

317

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

318

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

319

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

320

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

321

{ RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

323

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

324

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

325

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

326

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

327

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

328

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

329

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

330

{ RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

332

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

333

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

334

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

335

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

336

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

337

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

338

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

339

{ RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

341

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

342

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

343

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

344

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

345

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

346

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

347

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

348

{ RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

351

{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

352

{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

353

{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

354

{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

355

{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

356

{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

357

{ RK3588_VCCIO3_5_IOC_REG + 0x0120, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

358

{ RK3588_VCCIO3_5_IOC_REG + 0x0120, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

360

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

361

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

362

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

363

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

364

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

365

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

366

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

367

{ RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

369

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

370

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

371

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

372

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

373

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

374

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

375

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

376

{ RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

378

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

379

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

380

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

381

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

382

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

383

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

384

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

385

{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

388

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

389

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

390

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

391

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

392

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

393

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

394

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

395

{ RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

397

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

398

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

399

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

400

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

401

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

402

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

403

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

404

{ RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

406

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

407

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

408

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

409

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

410

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

411

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

412

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

413

{ RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

415

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

416

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

417

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

418

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

419

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

420

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

421

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

422

{ RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

425

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

426

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

427

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

428

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

429

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

430

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

431

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

432

{ RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

434

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

435

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

436

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

437

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

438

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

439

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

440

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

441

{ RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

443

{ RK3588_VCCIO6_IOC_REG + 0x0148, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

444

{ RK3588_VCCIO6_IOC_REG + 0x0148, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

445

{ RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

446

{ RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

447

{ RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

448

{ RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

449

{ RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

450

{ RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(15,14) },

sys/arch/arm/rockchip/rk3588_iomux.c

452

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(1,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

453

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(3,2) },

sys/arch/arm/rockchip/rk3588_iomux.c

454

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(5,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

455

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(7,6) },

sys/arch/arm/rockchip/rk3588_iomux.c

456

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(9,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

457

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(11,10) },

sys/arch/arm/rockchip/rk3588_iomux.c

458

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(13,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

459

{ RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(15,14) }

sys/arch/arm/rockchip/rk3588_iomux.c

653

{ RK3588_PMU1_IOC_REG + 0x0000, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

654

{ RK3588_PMU1_IOC_REG + 0x0000, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

655

{ RK3588_PMU1_IOC_REG + 0x0000, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

656

{ RK3588_PMU1_IOC_REG + 0x0000, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

657

{ RK3588_PMU1_IOC_REG + 0x0004, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

658

{ RK3588_PMU1_IOC_REG + 0x0004, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

659

{ RK3588_PMU1_IOC_REG + 0x0004, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

660

{ RK3588_PMU1_IOC_REG + 0x0004, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

662

{ RK3588_PMU1_IOC_REG + 0x0008, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

663

{ RK3588_PMU1_IOC_REG + 0x0008, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

664

{ RK3588_PMU1_IOC_REG + 0x0008, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

665

{ RK3588_PMU1_IOC_REG + 0x0008, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

666

{ RK3588_BUS_IOC_REG + 0x000c, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0000 },

sys/arch/arm/rockchip/rk3588_iomux.c

667

{ RK3588_BUS_IOC_REG + 0x000c, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0000 },

sys/arch/arm/rockchip/rk3588_iomux.c

668

{ RK3588_BUS_IOC_REG + 0x000c, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0000 },

sys/arch/arm/rockchip/rk3588_iomux.c

669

{ RK3588_BUS_IOC_REG + 0x000c, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0000 },

sys/arch/arm/rockchip/rk3588_iomux.c

671

{ RK3588_BUS_IOC_REG + 0x0010, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0004 },

sys/arch/arm/rockchip/rk3588_iomux.c

672

{ RK3588_BUS_IOC_REG + 0x0010, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0004 },

sys/arch/arm/rockchip/rk3588_iomux.c

673

{ RK3588_BUS_IOC_REG + 0x0010, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0004 },

sys/arch/arm/rockchip/rk3588_iomux.c

674

{ RK3588_BUS_IOC_REG + 0x0010, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0004 },

sys/arch/arm/rockchip/rk3588_iomux.c

675

{ RK3588_BUS_IOC_REG + 0x0014, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0008 },

sys/arch/arm/rockchip/rk3588_iomux.c

676

{ RK3588_BUS_IOC_REG + 0x0014, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0008 },

sys/arch/arm/rockchip/rk3588_iomux.c

677

{ RK3588_BUS_IOC_REG + 0x0014, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0008 },

sys/arch/arm/rockchip/rk3588_iomux.c

678

{ RK3588_BUS_IOC_REG + 0x0014, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0008 },

sys/arch/arm/rockchip/rk3588_iomux.c

680

{ RK3588_BUS_IOC_REG + 0x0018, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x000c },

sys/arch/arm/rockchip/rk3588_iomux.c

681

{ RK3588_BUS_IOC_REG + 0x0018, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x000c },

sys/arch/arm/rockchip/rk3588_iomux.c

682

{ RK3588_BUS_IOC_REG + 0x0018, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x000c },

sys/arch/arm/rockchip/rk3588_iomux.c

683

{ RK3588_BUS_IOC_REG + 0x0018, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x000c },

sys/arch/arm/rockchip/rk3588_iomux.c

684

{ RK3588_BUS_IOC_REG + 0x001c, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0010 },

sys/arch/arm/rockchip/rk3588_iomux.c

685

{ RK3588_BUS_IOC_REG + 0x001c, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0010 },

sys/arch/arm/rockchip/rk3588_iomux.c

686

{ RK3588_BUS_IOC_REG + 0x001c, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0010 },

sys/arch/arm/rockchip/rk3588_iomux.c

687

{ RK3588_BUS_IOC_REG + 0x001c, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0010 },

sys/arch/arm/rockchip/rk3588_iomux.c

690

{ RK3588_BUS_IOC_REG + 0x0020, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

691

{ RK3588_BUS_IOC_REG + 0x0020, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

692

{ RK3588_BUS_IOC_REG + 0x0020, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

693

{ RK3588_BUS_IOC_REG + 0x0020, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

694

{ RK3588_BUS_IOC_REG + 0x0024, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

695

{ RK3588_BUS_IOC_REG + 0x0024, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

696

{ RK3588_BUS_IOC_REG + 0x0024, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

697

{ RK3588_BUS_IOC_REG + 0x0024, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

699

{ RK3588_BUS_IOC_REG + 0x0028, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

700

{ RK3588_BUS_IOC_REG + 0x0028, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

701

{ RK3588_BUS_IOC_REG + 0x0028, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

702

{ RK3588_BUS_IOC_REG + 0x0028, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

703

{ RK3588_BUS_IOC_REG + 0x002c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

704

{ RK3588_BUS_IOC_REG + 0x002c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

705

{ RK3588_BUS_IOC_REG + 0x002c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

706

{ RK3588_BUS_IOC_REG + 0x002c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

708

{ RK3588_BUS_IOC_REG + 0x0030, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

709

{ RK3588_BUS_IOC_REG + 0x0030, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

710

{ RK3588_BUS_IOC_REG + 0x0030, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

711

{ RK3588_BUS_IOC_REG + 0x0030, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

712

{ RK3588_BUS_IOC_REG + 0x0034, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

713

{ RK3588_BUS_IOC_REG + 0x0034, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

714

{ RK3588_BUS_IOC_REG + 0x0034, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

715

{ RK3588_BUS_IOC_REG + 0x0034, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

717

{ RK3588_BUS_IOC_REG + 0x0038, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

718

{ RK3588_BUS_IOC_REG + 0x0038, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

719

{ RK3588_BUS_IOC_REG + 0x0038, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

720

{ RK3588_BUS_IOC_REG + 0x0038, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

721

{ RK3588_BUS_IOC_REG + 0x003c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

722

{ RK3588_BUS_IOC_REG + 0x003c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

723

{ RK3588_BUS_IOC_REG + 0x003c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

724

{ RK3588_BUS_IOC_REG + 0x003c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

727

{ RK3588_BUS_IOC_REG + 0x0040, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

728

{ RK3588_BUS_IOC_REG + 0x0040, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

729

{ RK3588_BUS_IOC_REG + 0x0040, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

730

{ RK3588_BUS_IOC_REG + 0x0040, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

731

{ RK3588_BUS_IOC_REG + 0x0044, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

732

{ RK3588_BUS_IOC_REG + 0x0044, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

733

{ RK3588_BUS_IOC_REG + 0x0044, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

734

{ RK3588_BUS_IOC_REG + 0x0044, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

736

{ RK3588_BUS_IOC_REG + 0x0048, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

737

{ RK3588_BUS_IOC_REG + 0x0048, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

738

{ RK3588_BUS_IOC_REG + 0x0048, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

739

{ RK3588_BUS_IOC_REG + 0x0048, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

740

{ RK3588_BUS_IOC_REG + 0x004c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

741

{ RK3588_BUS_IOC_REG + 0x004c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

742

{ RK3588_BUS_IOC_REG + 0x004c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

743

{ RK3588_BUS_IOC_REG + 0x004c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

745

{ RK3588_BUS_IOC_REG + 0x0050, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

746

{ RK3588_BUS_IOC_REG + 0x0050, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

747

{ RK3588_BUS_IOC_REG + 0x0050, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

748

{ RK3588_BUS_IOC_REG + 0x0050, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

749

{ RK3588_BUS_IOC_REG + 0x0054, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

750

{ RK3588_BUS_IOC_REG + 0x0054, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

751

{ RK3588_BUS_IOC_REG + 0x0054, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

752

{ RK3588_BUS_IOC_REG + 0x0054, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

754

{ RK3588_BUS_IOC_REG + 0x0058, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

755

{ RK3588_BUS_IOC_REG + 0x0058, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

756

{ RK3588_BUS_IOC_REG + 0x0058, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

757

{ RK3588_BUS_IOC_REG + 0x0058, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

758

{ RK3588_BUS_IOC_REG + 0x005c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

759

{ RK3588_BUS_IOC_REG + 0x005c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

760

{ RK3588_BUS_IOC_REG + 0x005c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

761

{ RK3588_BUS_IOC_REG + 0x005c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

764

{ RK3588_BUS_IOC_REG + 0x0060, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

765

{ RK3588_BUS_IOC_REG + 0x0060, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

766

{ RK3588_BUS_IOC_REG + 0x0060, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

767

{ RK3588_BUS_IOC_REG + 0x0060, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

768

{ RK3588_BUS_IOC_REG + 0x0064, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

769

{ RK3588_BUS_IOC_REG + 0x0064, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

770

{ RK3588_BUS_IOC_REG + 0x0064, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

771

{ RK3588_BUS_IOC_REG + 0x0064, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

773

{ RK3588_BUS_IOC_REG + 0x0068, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

774

{ RK3588_BUS_IOC_REG + 0x0068, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

775

{ RK3588_BUS_IOC_REG + 0x0068, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

776

{ RK3588_BUS_IOC_REG + 0x0068, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

777

{ RK3588_BUS_IOC_REG + 0x006c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

778

{ RK3588_BUS_IOC_REG + 0x006c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

779

{ RK3588_BUS_IOC_REG + 0x006c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

780

{ RK3588_BUS_IOC_REG + 0x006c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

782

{ RK3588_BUS_IOC_REG + 0x0070, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

783

{ RK3588_BUS_IOC_REG + 0x0070, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

784

{ RK3588_BUS_IOC_REG + 0x0070, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

785

{ RK3588_BUS_IOC_REG + 0x0070, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

786

{ RK3588_BUS_IOC_REG + 0x0074, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

787

{ RK3588_BUS_IOC_REG + 0x0074, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

788

{ RK3588_BUS_IOC_REG + 0x0074, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

789

{ RK3588_BUS_IOC_REG + 0x0074, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

791

{ RK3588_BUS_IOC_REG + 0x0078, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

792

{ RK3588_BUS_IOC_REG + 0x0078, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

793

{ RK3588_BUS_IOC_REG + 0x0078, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

794

{ RK3588_BUS_IOC_REG + 0x0078, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

795

{ RK3588_BUS_IOC_REG + 0x007c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

796

{ RK3588_BUS_IOC_REG + 0x007c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

797

{ RK3588_BUS_IOC_REG + 0x007c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

798

{ RK3588_BUS_IOC_REG + 0x007c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

801

{ RK3588_BUS_IOC_REG + 0x0080, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

802

{ RK3588_BUS_IOC_REG + 0x0080, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

803

{ RK3588_BUS_IOC_REG + 0x0080, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

804

{ RK3588_BUS_IOC_REG + 0x0080, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

805

{ RK3588_BUS_IOC_REG + 0x0084, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

806

{ RK3588_BUS_IOC_REG + 0x0084, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

807

{ RK3588_BUS_IOC_REG + 0x0084, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

808

{ RK3588_BUS_IOC_REG + 0x0084, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

810

{ RK3588_BUS_IOC_REG + 0x0088, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

811

{ RK3588_BUS_IOC_REG + 0x0088, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

812

{ RK3588_BUS_IOC_REG + 0x0088, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

813

{ RK3588_BUS_IOC_REG + 0x0088, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

814

{ RK3588_BUS_IOC_REG + 0x008c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

815

{ RK3588_BUS_IOC_REG + 0x008c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

816

{ RK3588_BUS_IOC_REG + 0x008c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

817

{ RK3588_BUS_IOC_REG + 0x008c, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

819

{ RK3588_BUS_IOC_REG + 0x0090, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

820

{ RK3588_BUS_IOC_REG + 0x0090, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

821

{ RK3588_BUS_IOC_REG + 0x0090, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

822

{ RK3588_BUS_IOC_REG + 0x0090, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

823

{ RK3588_BUS_IOC_REG + 0x0094, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

824

{ RK3588_BUS_IOC_REG + 0x0094, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

825

{ RK3588_BUS_IOC_REG + 0x0094, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

826

{ RK3588_BUS_IOC_REG + 0x0094, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

828

{ RK3588_BUS_IOC_REG + 0x0098, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

829

{ RK3588_BUS_IOC_REG + 0x0098, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

830

{ RK3588_BUS_IOC_REG + 0x0098, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

831

{ RK3588_BUS_IOC_REG + 0x0098, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

832

{ RK3588_BUS_IOC_REG + 0x009c, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

833

{ RK3588_BUS_IOC_REG + 0x009c, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

834

{ RK3588_BUS_IOC_REG + 0x009c, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

835

{ RK3588_BUS_IOC_REG + 0x009c, __BITS(15,12) }

sys/arch/arm/rockchip/rk3588_iomux.c

85

{ RK3588_PMU1_IOC_REG + 0x0010, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

86

{ RK3588_PMU1_IOC_REG + 0x0010, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

87

{ RK3588_PMU1_IOC_REG + 0x0010, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

88

{ RK3588_PMU1_IOC_REG + 0x0010, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

89

{ RK3588_PMU1_IOC_REG + 0x0014, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

90

{ RK3588_PMU1_IOC_REG + 0x0014, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

91

{ RK3588_PMU1_IOC_REG + 0x0014, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

92

{ RK3588_PMU1_IOC_REG + 0x0014, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

94

{ RK3588_PMU1_IOC_REG + 0x0018, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

95

{ RK3588_PMU1_IOC_REG + 0x0018, __BITS(7,4) },

sys/arch/arm/rockchip/rk3588_iomux.c

96

{ RK3588_PMU1_IOC_REG + 0x0018, __BITS(11,8) },

sys/arch/arm/rockchip/rk3588_iomux.c

97

{ RK3588_PMU1_IOC_REG + 0x0018, __BITS(15,12) },

sys/arch/arm/rockchip/rk3588_iomux.c

98

{ RK3588_PMU2_IOC_REG + 0x0014, __BITS(3,0) },

sys/arch/arm/rockchip/rk3588_iomux.c

99

{ RK3588_PMU2_IOC_REG + 0x0014, __BITS(7,4) },

sys/arch/arm/rockchip/rk_cru_pll.c

41

#define PLL_POSTDIV1 __BITS(14,12)

sys/arch/arm/rockchip/rk_cru_pll.c

42

#define PLL_FBDIV __BITS(11,0)

sys/arch/arm/rockchip/rk_cru_pll.c

50

#define PLL_POSTDIV2 __BITS(8,6)

sys/arch/arm/rockchip/rk_cru_pll.c

51

#define PLL_REFDIV __BITS(5,0)

sys/arch/arm/rockchip/rk_cru_pll.c

58

#define PLL_FRACDIV __BITS(23,0)

sys/arch/arm/rockchip/rk_cru_pll.c

66

#define RK3288_CLKR __BITS(13,8)

sys/arch/arm/rockchip/rk_cru_pll.c

67

#define RK3288_CLKOD __BITS(3,0)

sys/arch/arm/rockchip/rk_cru_pll.c

70

#define RK3288_CLKF __BITS(12,0)

sys/arch/arm/rockchip/rk_cru_pll.c

72

#define RK3288_BWADJ __BITS(11,0)

sys/arch/arm/rockchip/rk_cru_pll.c

76

#define RK3588_PLLCON0_M __BITS(9,0)

sys/arch/arm/rockchip/rk_cru_pll.c

77

#define RK3588_PLLCON1_P __BITS(5,0)

sys/arch/arm/rockchip/rk_cru_pll.c

78

#define RK3588_PLLCON1_S __BITS(8,6)

sys/arch/arm/rockchip/rk_cru_pll.c

79

#define RK3588_PLLCON2_K __BITS(15,0)

sys/arch/arm/rockchip/rk_emmcphy.c

44

#define PHYCTRL_FRQSEL __BITS(13,12)

sys/arch/arm/rockchip/rk_emmcphy.c

50

#define PHYCTRL_OTAPDLYSEL __BITS(10,7)

sys/arch/arm/rockchip/rk_emmcphy.c

52

#define PHYCTRL_ITAPDLYSEL __BITS(5,1)

sys/arch/arm/rockchip/rk_emmcphy.c

55

#define PHYCTRL_CLKBUFSEL __BITS(8,6)

sys/arch/arm/rockchip/rk_emmcphy.c

58

#define PHYCTRL_STRBSEL __BITS(3,0)

sys/arch/arm/rockchip/rk_emmcphy.c

62

#define PHYCTRL_REN_DAT __BITS(7,0)

sys/arch/arm/rockchip/rk_emmcphy.c

66

#define PHYCTRL_PU_DAT __BITS(7,0)

sys/arch/arm/rockchip/rk_emmcphy.c

70

#define PHYCTRL_OD_RELEASE_DAT __BITS(7,0)

sys/arch/arm/rockchip/rk_emmcphy.c

74

#define PHYCTRL_ODEN_DAT __BITS(7,0)

sys/arch/arm/rockchip/rk_emmcphy.c

76

#define PHYCTRL_DLL_TRM_ICP __BITS(12,9)

sys/arch/arm/rockchip/rk_emmcphy.c

79

#define PHYCTRL_DR_TY __BITS(6,4)

sys/arch/arm/rockchip/rk_emmcphy.c

87

#define PHYCTRL_RTRIM __BITS(4,1)

sys/arch/arm/rockchip/rk_eqos.c

81

#define RK3588_GMAC_RXCLK_DELAY_CFG __BITS(15,8)

sys/arch/arm/rockchip/rk_eqos.c

82

#define RK3588_GMAC_TXCLK_DELAY_CFG __BITS(7,0)

sys/arch/arm/rockchip/rk_eqos.c

86

#define RK3588_GMAC_PHY_IFACE_SEL(id) (__BITS(5,3) << ((id) * 6))

sys/arch/arm/rockchip/rk_eqos.c

97

#define RK3588_GMAC_CLK_RGMII_DIV(id) (__BITS(3,2) << ((id) * 5))

sys/arch/arm/rockchip/rk_gmac.c

100

#define RK3288_GRF_SOC_CON3_CLK_RX_DL_CFG_GMAC __BITS(13,7)

sys/arch/arm/rockchip/rk_gmac.c

101

#define RK3288_GRF_SOC_CON3_CLK_TX_DL_CFG_GMAC __BITS(6,0)

sys/arch/arm/rockchip/rk_gmac.c

173

#define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7)

sys/arch/arm/rockchip/rk_gmac.c

174

#define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0)

sys/arch/arm/rockchip/rk_gmac.c

177

#define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11)

sys/arch/arm/rockchip/rk_gmac.c

182

#define RK3328_GRF_MAC_CON1_SEL __BITS(6,4)

sys/arch/arm/rockchip/rk_gmac.c

256

#define RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL __BITS(11,9)

sys/arch/arm/rockchip/rk_gmac.c

260

#define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL __BITS(5,4)

sys/arch/arm/rockchip/rk_gmac.c

267

#define RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG __BITS(14,8)

sys/arch/arm/rockchip/rk_gmac.c

269

#define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0)

sys/arch/arm/rockchip/rk_gmac.c

82

#define RK3288_GRF_SOC_CON1_GMAC_CLK_SEL __BITS(13,12)

sys/arch/arm/rockchip/rk_gmac.c

93

#define RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL __BITS(8,6)

sys/arch/arm/rockchip/rk_i2c.c

50

#define RKI2C_CON_I2C_MODE __BITS(2,1)

sys/arch/arm/rockchip/rk_i2c.c

58

#define RKI2C_CLKDIV_CLKDIVH __BITS(31,16)

sys/arch/arm/rockchip/rk_i2c.c

59

#define RKI2C_CLKDIV_CLKDIVL __BITS(15,0)

sys/arch/arm/rockchip/rk_i2c.c

65

#define RKI2C_MRXADDR_SADDR __BITS(23,0)

sys/arch/arm/rockchip/rk_i2c.c

71

#define RKI2C_MRXRADDR_SADDR __BITS(23,0)

sys/arch/arm/rockchip/rk_i2c.c

74

#define RKI2C_MTXCNT_MTXCNT __BITS(5,0)

sys/arch/arm/rockchip/rk_i2c.c

77

#define RKI2C_MRXCNT_MRXCNT __BITS(5,0)

sys/arch/arm/rockchip/rk_i2c.c

98

#define RKI2C_FCNT_FCNT __BITS(5,0)

sys/arch/arm/rockchip/rk_i2s.c

106

#define RXFIFOLR_RFL(n) __BITS((n) * 6 + 5, (n) * 6)

sys/arch/arm/rockchip/rk_i2s.c

116

.oe_mask = __BITS(13,11),

sys/arch/arm/rockchip/rk_i2s.c

49

#define TXCR_RCNT __BITS(22,17)

sys/arch/arm/rockchip/rk_i2s.c

50

#define TXCR_TCSR __BITS(16,15)

sys/arch/arm/rockchip/rk_i2s.c

54

#define TXCR_IBM __BITS(10,9)

sys/arch/arm/rockchip/rk_i2s.c

55

#define TXCR_PBM __BITS(8,7)

sys/arch/arm/rockchip/rk_i2s.c

57

#define TXCR_VDW __BITS(4,0)

sys/arch/arm/rockchip/rk_i2s.c

59

#define RXCR_RCSR __BITS(16,15)

sys/arch/arm/rockchip/rk_i2s.c

63

#define RXCR_IBM __BITS(10,9)

sys/arch/arm/rockchip/rk_i2s.c

64

#define RXCR_PBM __BITS(8,7)

sys/arch/arm/rockchip/rk_i2s.c

66

#define RXCR_VDW __BITS(4,0)

sys/arch/arm/rockchip/rk_i2s.c

68

#define CKR_TRCM __BITS(29,28)

sys/arch/arm/rockchip/rk_i2s.c

73

#define CKR_MDIV __BITS(23,16)

sys/arch/arm/rockchip/rk_i2s.c

74

#define CKR_RSD __BITS(15,8)

sys/arch/arm/rockchip/rk_i2s.c

75

#define CKR_TSD __BITS(7,0)

sys/arch/arm/rockchip/rk_i2s.c

77

#define TXFIFOLR_TFL(n) __BITS((n) * 6 + 5, (n) * 6)

sys/arch/arm/rockchip/rk_i2s.c

80

#define DMACR_RDL __BITS(20,16)

sys/arch/arm/rockchip/rk_i2s.c

82

#define DMACR_TDL __BITS(4,0)

sys/arch/arm/rockchip/rk_i2s.c

84

#define INTCR_RFT __BITS(24,20)

sys/arch/arm/rockchip/rk_i2s.c

88

#define INTCR_TFT __BITS(8,4)

sys/arch/arm/rockchip/rk_pwm.c

48

#define CTRL_RPT __BITS(31,24)

sys/arch/arm/rockchip/rk_pwm.c

49

#define CTRL_SCALE __BITS(23,16)

sys/arch/arm/rockchip/rk_pwm.c

50

#define CTRL_PRESCALE __BITS(14,12)

sys/arch/arm/rockchip/rk_pwm.c

56

#define CTRL_PWM_MODE __BITS(2,1)

sys/arch/arm/rockchip/rk_spi.c

126

#define SPI_ICR_ALL __BITS(3, 0)

sys/arch/arm/rockchip/rk_spi.c

133

#define SPI_DMATDLR_TDL __BITS(4, 0)

sys/arch/arm/rockchip/rk_spi.c

136

#define SPI_DMARDLR_RDL __BITS(4, 0)

sys/arch/arm/rockchip/rk_spi.c

139

#define SPI_TXDR_TXDR __BITS(15, 0)

sys/arch/arm/rockchip/rk_spi.c

142

#define SPI_RXDR_RXDR __BITS(15, 0)

sys/arch/arm/rockchip/rk_spi.c

49

#define SPI_CTRLR0_XFM __BITS(19, 18)

sys/arch/arm/rockchip/rk_spi.c

50

#define SPI_CTRLR0_FRF __BITS(17, 16)

sys/arch/arm/rockchip/rk_spi.c

51

#define SPI_CTRLR0_RSD __BITS(15, 14)

sys/arch/arm/rockchip/rk_spi.c

56

#define SPI_CTRLR0_CSM __BITS(9, 8)

sys/arch/arm/rockchip/rk_spi.c

59

#define SPI_CTRLR0_CFS __BITS(5, 2)

sys/arch/arm/rockchip/rk_spi.c

60

#define SPI_CTRLR0_DFS __BITS(1, 0)

sys/arch/arm/rockchip/rk_spi.c

66

#define SPI_CTRLR1_NDM __BITS(15, 0)

sys/arch/arm/rockchip/rk_spi.c

76

#define SPI_BAUDR_BAUDR __BITS(15, 0)

sys/arch/arm/rockchip/rk_spi.c

79

#define SPI_TXFTLR_TXFLTR __BITS(4, 0)

sys/arch/arm/rockchip/rk_spi.c

82

#define SPI_RXFLTR_RXFLTR __BITS(4, 0)

sys/arch/arm/rockchip/rk_spi.c

85

#define SPI_TXFLR_TXFLR __BITS(5, 0)

sys/arch/arm/rockchip/rk_spi.c

88

#define SPI_RXFLR_RXFLR __BITS(5, 0)

sys/arch/arm/rockchip/rk_tsadc.c

103

#define TSADC_DATA0_ADC_DATA __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

105

#define TSADC_DATA1_ADC_DATA __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

107

#define TSADC_COMP0_INT_COMP_SRC0 __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

109

#define TSADC_COMP1_INT_COMP_SRC1 __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

111

#define TSADC_COMP0_SHUT_COMP_SRC0 __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

113

#define TSADC_COMP1_SHUT_COMP_SRC1 __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

115

#define TSADC_HIGH_INT_DEBOUNCE_TEMP __BITS(7,0)

sys/arch/arm/rockchip/rk_tsadc.c

117

#define TSADC_HIGH_TSHUT_DEBOUNCE_TEMP __BITS(7,0)

sys/arch/arm/rockchip/rk_tsadc.c

119

#define TSADC_AUTO_PERIOD_TEMP __BITS(31,0)

sys/arch/arm/rockchip/rk_tsadc.c

121

#define TSADC_AUTO_PERIOD_HT_TEMP __BITS(31,0)

sys/arch/arm/rockchip/rk_tsadc.c

123

#define TSADC_COMP0_LOW_INT_COMP_SRC0 __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

125

#define TSADC_COMP1_LOW_INT_COMP_SRC1 __BITS(11,0)

sys/arch/arm/rockchip/rk_tsadc.c

66

#define TSADC_USER_CON_INTER_PD_SOC __BITS(11,6)

sys/arch/arm/rockchip/rk_tsadc.c

70

#define TSADC_USER_CON_ADC_INPUT_SRC_SEL __BITS(2,0)

sys/arch/arm/rockchip/rk_v1crypto.h

147

#define RK_V1CRYPTO_HASH_SELECT __BITS(1,0)

sys/arch/arm/rockchip/rk_v1crypto.h

162

#define RK_V1CRYPTO_TRNG_CTRL_CYCLES __BITS(15,0)

sys/arch/arm/rockchip/rk_v1crypto.h

168

#define RK_V1CRYPTO_PKA_CTRL_SIZE __BITS(1,0)

sys/arch/arm/rockchip/rk_v1crypto.h

52

#define RK_V1CRYPTO_CTRL_MASK __BITS(31,16)

sys/arch/arm/rockchip/rk_v1crypto.h

76

#define RK_V1CRYPTO_CONF_HASHINSEL __BITS(1,0)

sys/arch/arm/rockchip/rk_v1crypto.h

95

#define RK_V1CRYPTO_AES_CTRL_MODE __BITS(5,4)

sys/arch/arm/rockchip/rk_v1crypto.h

99

#define RK_V1CRYPTO_AES_CTRL_KEYSIZE __BITS(3,2)

sys/arch/arm/rockchip/rk_vop.c

100

#define DSP_HACT_ST __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

101

#define DSP_HACT_END __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

103

#define DSP_VS_END __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

104

#define DSP_VTOTAL __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

106

#define DSP_VACT_ST __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

107

#define DSP_VACT_END __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

215

#define RK3399_VOP_MIPI_POL __BITS(31,28)

sys/arch/arm/rockchip/rk_vop.c

216

#define RK3399_VOP_EDP_POL __BITS(27,24)

sys/arch/arm/rockchip/rk_vop.c

217

#define RK3399_VOP_HDMI_POL __BITS(23,20)

sys/arch/arm/rockchip/rk_vop.c

218

#define RK3399_VOP_DP_POL __BITS(19,16)

sys/arch/arm/rockchip/rk_vop.c

64

#define DSP_OUT_MODE __BITS(3,0)

sys/arch/arm/rockchip/rk_vop.c

69

#define WIN0_LB_MODE __BITS(7,5)

sys/arch/arm/rockchip/rk_vop.c

74

#define WIN0_DATA_FMT __BITS(3,1)

sys/arch/arm/rockchip/rk_vop.c

79

#define WIN0_VIR_STRIDE __BITS(13,0)

sys/arch/arm/rockchip/rk_vop.c

82

#define WIN0_ACT_HEIGHT __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

83

#define WIN0_ACT_WIDTH __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

85

#define WIN0_DSP_HEIGHT __BITS(27,16)

sys/arch/arm/rockchip/rk_vop.c

86

#define WIN0_DSP_WIDTH __BITS(11,0)

sys/arch/arm/rockchip/rk_vop.c

88

#define WIN0_DSP_YST __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

89

#define WIN0_DSP_XST __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

91

#define DSP_HACT_ST_POST __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

92

#define DSP_HACT_END_POST __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

94

#define DSP_VACT_ST_POST __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

95

#define DSP_VACT_END_POST __BITS(12,0)

sys/arch/arm/rockchip/rk_vop.c

97

#define DSP_HS_END __BITS(28,16)

sys/arch/arm/rockchip/rk_vop.c

98

#define DSP_HTOTAL __BITS(12,0)

sys/arch/arm/samsung/exynos4_reg.h

285

#define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1)

sys/arch/arm/samsung/exynos4_reg.h

286

#define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3)

sys/arch/arm/samsung/exynos4_reg.h

287

#define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3)

sys/arch/arm/samsung/exynos4_reg.h

288

#define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3)

sys/arch/arm/samsung/exynos4_reg.h

294

#define RSTCON_DEVPHY_SWRST __BITS(0,3)

sys/arch/arm/samsung/exynos4_reg.h

295

#define RSTCON_HOSTPHY_SWRST __BITS(3,4)

sys/arch/arm/samsung/exynos4_reg.h

296

#define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4)

sys/arch/arm/samsung/exynos5410_clock.c

331

CLK_MUX("mout_mmc0", EXYNOS5410_SRC_FSYS, __BITS(3,0), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

332

CLK_MUX("mout_mmc1", EXYNOS5410_SRC_FSYS, __BITS(7,4), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

333

CLK_MUX("mout_mmc2", EXYNOS5410_SRC_FSYS, __BITS(11,8), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

336

CLK_MUX("mout_uart0", EXYNOS5410_SRC_PERIC0, __BITS(3,0), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

337

CLK_MUX("mout_uart1", EXYNOS5410_SRC_PERIC0, __BITS(7,4), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

338

CLK_MUX("mout_uart2", EXYNOS5410_SRC_PERIC0, __BITS(11,8), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

339

CLK_MUX("mout_uart3", EXYNOS5410_SRC_PERIC0, __BITS(15,12), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

340

CLK_MUX("mout_pwm", EXYNOS5410_SRC_PERIC0, __BITS(27,24), mout_group2_p),

sys/arch/arm/samsung/exynos5410_clock.c

344

CLK_DIV("div_arm", "mout_cpu", EXYNOS5410_DIV_CPU0, __BITS(2,0)),

sys/arch/arm/samsung/exynos5410_clock.c

345

CLK_DIV("div_arm2", "div_arm", EXYNOS5410_DIV_CPU0, __BITS(30,28)),

sys/arch/arm/samsung/exynos5410_clock.c

347

CLK_DIV("div_acp", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(10,8)),

sys/arch/arm/samsung/exynos5410_clock.c

348

CLK_DIV("div_cpud", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(6,4)),

sys/arch/arm/samsung/exynos5410_clock.c

349

CLK_DIV("div_atb", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(18,16)),

sys/arch/arm/samsung/exynos5410_clock.c

350

CLK_DIV("pclk_dbg", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(22,20)),

sys/arch/arm/samsung/exynos5410_clock.c

352

CLK_DIV("div_kfc", "mout_kfc", EXYNOS5410_DIV_KFC0, __BITS(2,0)),

sys/arch/arm/samsung/exynos5410_clock.c

353

CLK_DIV("div_aclk", "div_kfc", EXYNOS5410_DIV_KFC0, __BITS(6,4)),

sys/arch/arm/samsung/exynos5410_clock.c

354

CLK_DIV("div_pclk", "div_kfc", EXYNOS5410_DIV_KFC0, __BITS(22,20)),

sys/arch/arm/samsung/exynos5410_clock.c

356

CLK_DIV("aclk66_pre", "sclk_mpll_muxed", EXYNOS5410_DIV_TOP1, __BITS(26,24)),

sys/arch/arm/samsung/exynos5410_clock.c

357

CLK_DIV("aclk66", "aclk66_pre", EXYNOS5410_DIV_TOP0, __BITS(2,0)),

sys/arch/arm/samsung/exynos5410_clock.c

359

CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5410_DIV_FSYS0, __BITS(19,16)),

sys/arch/arm/samsung/exynos5410_clock.c

360

CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5410_DIV_FSYS0, __BITS(23,20)),

sys/arch/arm/samsung/exynos5410_clock.c

361

CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5410_DIV_FSYS0, __BITS(27,24)),

sys/arch/arm/samsung/exynos5410_clock.c

362

CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5410_DIV_FSYS0, __BITS(31,28)),

sys/arch/arm/samsung/exynos5410_clock.c

364

CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5410_DIV_FSYS1, __BITS(3,0)),

sys/arch/arm/samsung/exynos5410_clock.c

365

CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5410_DIV_FSYS1, __BITS(19,16)),

sys/arch/arm/samsung/exynos5410_clock.c

366

CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5410_DIV_FSYS2, __BITS(3,0)),

sys/arch/arm/samsung/exynos5410_clock.c

368

CLK_DIVF("dout_mmc_pre0", "dout_mmc0", EXYNOS5410_DIV_FSYS1, __BITS(15,8),

sys/arch/arm/samsung/exynos5410_clock.c

370

CLK_DIVF("dout_mmc_pre1", "dout_mmc1", EXYNOS5410_DIV_FSYS1, __BITS(31,24),

sys/arch/arm/samsung/exynos5410_clock.c

372

CLK_DIVF("dout_mmc_pre2", "dout_mmc2", EXYNOS5410_DIV_FSYS2, __BITS(15,8),

sys/arch/arm/samsung/exynos5410_clock.c

375

CLK_DIV("div_uart0", "mout_uart0", EXYNOS5410_DIV_PERIC0, __BITS(3,0)),

sys/arch/arm/samsung/exynos5410_clock.c

376

CLK_DIV("div_uart1", "mout_uart1", EXYNOS5410_DIV_PERIC0, __BITS(7,4)),

sys/arch/arm/samsung/exynos5410_clock.c

377

CLK_DIV("div_uart2", "mout_uart2", EXYNOS5410_DIV_PERIC0, __BITS(11,8)),

sys/arch/arm/samsung/exynos5410_clock.c

378

CLK_DIV("div_uart3", "mout_uart3", EXYNOS5410_DIV_PERIC0, __BITS(15,12)),

sys/arch/arm/samsung/exynos5410_clock.c

380

CLK_DIV("dout_pwm", "mout_pwm", EXYNOS5410_DIV_PERIC3, __BITS(3,0)),

sys/arch/arm/samsung/exynos5410_clock.c

382

CLK_DIV("aclk200", "mout_aclk200", EXYNOS5410_DIV_TOP0, __BITS(14,12)),

sys/arch/arm/samsung/exynos5410_clock.c

383

CLK_DIV("aclk266", "sclk_mpll_muxed", EXYNOS5410_DIV_TOP0, __BITS(18,16)),

sys/arch/arm/samsung/exynos5410_clock.c

384

CLK_DIV("aclk400", "mout_aclk400", EXYNOS5410_DIV_TOP0, __BITS(26,24)),

sys/arch/arm/samsung/exynos5422_clock.c

467

CLK_MUX("mout_aclk66", EXYNOS5422_SRC_TOP1, __BITS(9,8),

sys/arch/arm/samsung/exynos5422_clock.c

469

CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24),

sys/arch/arm/samsung/exynos5422_clock.c

471

CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12),

sys/arch/arm/samsung/exynos5422_clock.c

479

CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4),

sys/arch/arm/samsung/exynos5422_clock.c

481

CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20),

sys/arch/arm/samsung/exynos5422_clock.c

483

CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8),

sys/arch/arm/samsung/exynos5422_clock.c

485

CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12),

sys/arch/arm/samsung/exynos5422_clock.c

487

CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16),

sys/arch/arm/samsung/exynos5422_clock.c

489

CLK_MUX("mout_uart0", EXYNOS5422_SRC_PERIC0, __BITS(6,4),

sys/arch/arm/samsung/exynos5422_clock.c

491

CLK_MUX("mout_uart1", EXYNOS5422_SRC_PERIC0, __BITS(10,8),

sys/arch/arm/samsung/exynos5422_clock.c

493

CLK_MUX("mout_uart2", EXYNOS5422_SRC_PERIC0, __BITS(14,12),

sys/arch/arm/samsung/exynos5422_clock.c

495

CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16),

sys/arch/arm/samsung/exynos5422_clock.c

498

CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)),

sys/arch/arm/samsung/exynos5422_clock.c

499

CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),

sys/arch/arm/samsung/exynos5422_clock.c

500

CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),

sys/arch/arm/samsung/exynos5422_clock.c

502

CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)),

sys/arch/arm/samsung/exynos5422_clock.c

503

CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)),

sys/arch/arm/samsung/exynos5422_clock.c

504

CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)),

sys/arch/arm/samsung/exynos5422_clock.c

505

CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(27,24)),

sys/arch/arm/samsung/exynos5422_clock.c

506

CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),

sys/arch/arm/samsung/exynos5422_clock.c

507

CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)),

sys/arch/arm/samsung/exynos5422_clock.c

508

CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)),

sys/arch/arm/samsung/exynos5422_clock.c

510

__BITS(11,8)),

sys/arch/arm/samsung/exynos5422_clock.c

512

__BITS(15,12)),

sys/arch/arm/samsung/exynos5422_clock.c

514

__BITS(19,16)),

sys/arch/arm/samsung/exynos5422_clock.c

516

__BITS(23,20)),

sys/arch/arm/samsung/exynos5_reg.h

387

#define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */

sys/arch/arm/samsung/exynos5_reg.h

388

#define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20)

sys/arch/arm/samsung/exynos5_reg.h

405

#define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22)

sys/arch/arm/samsung/exynos5_reg.h

411

#define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24)

sys/arch/arm/samsung/exynos5_reg.h

431

#define OTG_SYS_FSEL_MASK __BITS(4, 6) /* holds FSEL_CLKSEL_ */

sys/arch/arm/samsung/exynos5_reg.h

434

#define OTG_SYS_REFCLKSEL_MASK __BITS(9, 10)

sys/arch/arm/samsung/exynos_reg.h

123

#define PLL35XX_CON0_M __BITS(16,25) /* PLL M divide value */

sys/arch/arm/samsung/exynos_reg.h

124

#define PLL35XX_CON0_P __BITS( 8,13) /* PLL P divide value */

sys/arch/arm/samsung/exynos_reg.h

125

#define PLL35XX_CON0_S __BITS( 0, 2) /* PLL S divide value */

sys/arch/arm/samsung/exynos_reg.h

127

#define PLL2650X_CON0_M __BITS(24, 16) /* PLL M divide value */

sys/arch/arm/samsung/exynos_reg.h

128

#define PLL2650X_CON0_P __BITS(13, 8) /* PLL P divide value */

sys/arch/arm/samsung/exynos_reg.h

129

#define PLL2650X_CON0_S __BITS( 2, 0) /* PLL S divide value */

sys/arch/arm/samsung/exynos_reg.h

130

#define PLL2650X_CON1_K __BITS(15, 0) /* PLL K divide value */

sys/arch/arm/samsung/exynos_reg.h

154

#define WTCON_PRESCALER __BITS(15,8)

sys/arch/arm/samsung/exynos_reg.h

156

#define WTCON_CLOCK_SELECT __BITS(4,3)

sys/arch/arm/samsung/exynos_reg.h

164

#define WTDAT_RELOAD __BITS(15,0)

sys/arch/arm/samsung/exynos_reg.h

166

#define WTCNT_COUNT __BITS(15,0)

sys/arch/arm/samsung/exynos_usbdrdphy.c

48

#define PHY_LINK_SYSTEM_FLADJ __BITS(6,1)

sys/arch/arm/samsung/exynos_usbdrdphy.c

52

#define PHY_CLK_RST_SSC_REFCLKSEL __BITS(30,23)

sys/arch/arm/samsung/exynos_usbdrdphy.c

55

#define PHY_CLK_RST_MPLL_MULT __BITS(17,11)

sys/arch/arm/samsung/exynos_usbdrdphy.c

57

#define PHY_CLK_RST_FSEL __BITS(10,5)

sys/arch/arm/samsung/exynos_usbdrdphy.c

60

#define PHY_CLK_RST_REFCLKSEL __BITS(3,2)

sys/arch/arm/samsung/exynos_usbdrdphy.c

67

#define PHY_PARAM0_REF_LOSLEVEL __BITS(30,26)

sys/arch/arm/samsung/exynos_usbdrdphy.c

69

#define PHY_PARAM1_TXDEEMPH __BITS(4,0)

sys/arch/arm/samsung/exynos_var.h

47

#define EXYNOS_PRODUCT_FAMILY(soc) __SHIFTOUT((soc), __BITS(24,31))

sys/arch/arm/samsung/exynos_var.h

50

#define EXYNOS_PRODUCT_ID(soc) __SHIFTOUT((soc), __BITS(12,31))

sys/arch/arm/samsung/exynos_var.h

51

#define EXYNOS_PRODUCT_PACKAGE(soc) __SHIFTOUT((soc), __BITS(8,11))

sys/arch/arm/samsung/exynos_var.h

52

#define EXYNOS_PRODUCT_REV(soc) __SHIFTOUT((soc), __BITS(4,7))

sys/arch/arm/samsung/exynos_var.h

53

#define EXYNOS_PRODUCT_SUBREV(soc) __SHIFTOUT((soc), __BITS(0,3))

sys/arch/arm/samsung/sscom_reg.h

101

#define UMCON_RTSTRIGGER __BITS(7,5)

sys/arch/arm/samsung/sscom_reg.h

106

#define UTRSTAT_RXFIFOCNT __BITS(23,16)

sys/arch/arm/samsung/sscom_reg.h

107

#define UTRSTAT_TXDMA_FSM __BITS(15,12)

sys/arch/arm/samsung/sscom_reg.h

108

#define UTRSTAT_RXDMA_FSM __BITS(11,8)

sys/arch/arm/samsung/sscom_reg.h

124

#define UFSTAT_TXCOUNT __BITS(23,16) /* TX FIFO count */

sys/arch/arm/samsung/sscom_reg.h

129

#define UFSTAT_RXCOUNT __BITS(7,0) /* RX FIFO count */

sys/arch/arm/samsung/sscom_reg.h

130

#define UFSTAT_S5L_RXCOUNT __BITS(3,0) /* RX FIFO count (Apple) */

sys/arch/arm/samsung/sscom_reg.h

45

#define ULCON_PARITY __BITS(5,3)

sys/arch/arm/samsung/sscom_reg.h

52

#define ULCON_LENGTH __BITS(1,0)

sys/arch/arm/samsung/sscom_reg.h

58

#define UCON_TXDMA_BRST __BITS(22,20)

sys/arch/arm/samsung/sscom_reg.h

63

#define UCON_RXDMA_BRST __BITS(18,16)

sys/arch/arm/samsung/sscom_reg.h

68

#define UCON_RXTO __BITS(15,12)

sys/arch/arm/samsung/sscom_reg.h

84

#define UCON_TXMODE __BITS(3,2)

sys/arch/arm/samsung/sscom_reg.h

89

#define UCON_RXMODE __BITS(1,0)

sys/arch/arm/samsung/sscom_reg.h

95

#define UFCON_TXTRIGGER __BITS(10,8)

sys/arch/arm/samsung/sscom_reg.h

96

#define UFCON_RXTRIGGER __BITS(6,4)

sys/arch/arm/sociox/if_scx.c

2031

mtype = (hwfea & __BITS(30,28)) >> 28;

sys/arch/arm/sociox/if_scx.c

2039

if ((txchan = (hwfea & __BITS(23,22)) >> 22) != 0)

sys/arch/arm/sociox/if_scx.c

2041

if ((rxchan = (hwfea & __BITS(21,20)) >> 20) != 0)

sys/arch/arm/sociox/if_scx.c

896

sc->sc_miigmii = ((dwfea & __BITS(30,28) >> 28) == 0);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

173

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

174

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

175

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

176

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

185

__BITS(14,8), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

187

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

188

__BITS(29,26), /* p */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

196

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

197

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

210

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

224

__BITS(12, 8), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

225

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

227

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

233

__BITS(12, 8), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

234

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

235

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

243

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

248

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

254

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

255

__BITS(7,6), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

260

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

266

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

267

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

268

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

274

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

275

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

276

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

282

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

283

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

284

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

290

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

291

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

292

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

298

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

299

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

300

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

306

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

307

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

308

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

314

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

315

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

316

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

320

SD0_SCLK_CFG_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

322

SD0_SCLK_CFG_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

325

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

326

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

327

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

331

SD1_SCLK_CFG_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

333

SD1_SCLK_CFG_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

336

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

337

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

338

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

342

SD2_SCLK_CFG_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

344

SD2_SCLK_CFG_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

347

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

348

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

349

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

353

SD3_SCLK_CFG_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

355

SD3_SCLK_CFG_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

359

__BITS(7,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

371

__BITS(7,0), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

390

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

391

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

397

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

398

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

404

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

405

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

411

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

412

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

423

.u.div.sel = __BITS(25,24),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

440

.u.div.sel = __BITS(25,24),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

456

.u.div.div = __BITS(3,0),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

457

.u.div.sel = __BITS(25,24),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

472

.u.div.div = __BITS(3,0),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

473

.u.div.sel = __BITS(25,24),

sys/arch/arm/sunxi/sun4i_a10_ccu.c

484

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

485

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

493

__BITS(21,20), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

494

__BITS(12,8), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

495

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

501

__BITS(21,20), /* n */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

502

__BITS(12,8), /* m */

sys/arch/arm/sunxi/sun4i_a10_ccu.c

503

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun4i_a10_codec.c

51

#define A10_FMG __BITS(25,23)

sys/arch/arm/sunxi/sun4i_a10_codec.c

52

#define A10_MICG __BITS(22,20)

sys/arch/arm/sunxi/sun4i_a10_codec.c

65

#define A10_PAVOL __BITS(5,0)

sys/arch/arm/sunxi/sun4i_a10_codec.c

73

#define A10_PREG1 __BITS(26,25)

sys/arch/arm/sunxi/sun4i_a10_codec.c

74

#define A10_PREG2 __BITS(24,23)

sys/arch/arm/sunxi/sun4i_a10_codec.c

75

#define A10_ADCG __BITS(22,20)

sys/arch/arm/sunxi/sun4i_a10_codec.c

76

#define A10_ADCIS __BITS(19,17)

sys/arch/arm/sunxi/sun4i_a10_codec.c

78

#define A10_LNPREG __BITS(15,13)

sys/arch/arm/sunxi/sun4i_a10_codec.c

84

#define A10_PTDBS __BITS(1,0)

sys/arch/arm/sunxi/sun4i_dma.c

59

#define NDMA_CTRL_WAIT_STATE __BITS(29,27)

sys/arch/arm/sunxi/sun4i_dma.c

60

#define NDMA_CTRL_DST_DATA_WIDTH __BITS(26,25)

sys/arch/arm/sunxi/sun4i_dma.c

61

#define NDMA_CTRL_DST_BST_LEN __BITS(24,23)

sys/arch/arm/sunxi/sun4i_dma.c

63

#define NDMA_CTRL_DST_DRQ_TYPE __BITS(20,16)

sys/arch/arm/sunxi/sun4i_dma.c

65

#define NDMA_CTRL_SRC_DATA_WIDTH __BITS(10,9)

sys/arch/arm/sunxi/sun4i_dma.c

66

#define NDMA_CTRL_SRC_BST_LEN __BITS(8,7)

sys/arch/arm/sunxi/sun4i_dma.c

68

#define NDMA_CTRL_SRC_DRQ_TYPE __BITS(4,0)

sys/arch/arm/sunxi/sun4i_dma.c

76

#define DDMA_CTRL_DST_DATA_WIDTH __BITS(26,25)

sys/arch/arm/sunxi/sun4i_dma.c

77

#define DDMA_CTRL_DST_BST_LEN __BITS(24,23)

sys/arch/arm/sunxi/sun4i_dma.c

78

#define DDMA_CTRL_DST_ADDR_MODE __BITS(22,21)

sys/arch/arm/sunxi/sun4i_dma.c

79

#define DDMA_CTRL_DST_DRQ_TYPE __BITS(20,16)

sys/arch/arm/sunxi/sun4i_dma.c

81

#define DDMA_CTRL_SRC_DATA_WIDTH __BITS(10,9)

sys/arch/arm/sunxi/sun4i_dma.c

82

#define DDMA_CTRL_SRC_BST_LEN __BITS(8,7)

sys/arch/arm/sunxi/sun4i_dma.c

83

#define DDMA_CTRL_SRC_ADDR_MODE __BITS(6,5)

sys/arch/arm/sunxi/sun4i_dma.c

84

#define DDMA_CTRL_SRC_DRQ_TYPE __BITS(4,0)

sys/arch/arm/sunxi/sun4i_dma.c

89

#define DDMA_PARA_DST_DATA_BLK_SIZE __BITS(31,24)

sys/arch/arm/sunxi/sun4i_dma.c

90

#define DDMA_PARA_DST_WAIT_CLK_CYC __BITS(23,16)

sys/arch/arm/sunxi/sun4i_dma.c

91

#define DDMA_PARA_SRC_DATA_BLK_SIZE __BITS(15,8)

sys/arch/arm/sunxi/sun4i_dma.c

92

#define DDMA_PARA_SRC_WAIT_CLK_CYC __BITS(7,0)

sys/arch/arm/sunxi/sun4i_emac.c

138

#define EMAC_MAC_IPGR_IPG1 __BITS(15,8)

sys/arch/arm/sunxi/sun4i_emac.c

139

#define EMAC_MAC_IPGR_IPG2 __BITS(7,0)

sys/arch/arm/sunxi/sun4i_emac.c

141

#define EMAC_MAC_CLRT_CW __BITS(15,8)

sys/arch/arm/sunxi/sun4i_emac.c

142

#define EMAC_MAC_CLRT_RM __BITS(7,0)

sys/arch/arm/sunxi/sun4i_emac.c

148

#define EMAC_MAC_MCFG_CLK __BITS(5,2)

sys/arch/arm/sunxi/sun4i_emac.c

159

#define EMAC_RXHDR_STS __BITS(31,16)

sys/arch/arm/sunxi/sun4i_emac.c

160

#define EMAC_RXHDR_LEN __BITS(15,0)

sys/arch/arm/sunxi/sun4i_spireg.h

110

#define SPI_WAIT_WCC __BITS(15, 0)

sys/arch/arm/sunxi/sun4i_spireg.h

114

#define SPI_CCTL_CDR1 __BITS(11, 8)

sys/arch/arm/sunxi/sun4i_spireg.h

115

#define SPI_CCTL_CDR2 __BITS(7, 0)

sys/arch/arm/sunxi/sun4i_spireg.h

118

#define SPI_BC_BC __BITS(23, 0)

sys/arch/arm/sunxi/sun4i_spireg.h

121

#define SPI_TC_WTC __BITS(23, 0)

sys/arch/arm/sunxi/sun4i_spireg.h

124

#define SPI_FIFO_STA_TF_CNT __BITS(22, 16)

sys/arch/arm/sunxi/sun4i_spireg.h

125

#define SPI_FIFO_STA_RF_CNT __BITS(6, 0)

sys/arch/arm/sunxi/sun4i_spireg.h

46

#define SPI_CTL_SS __BITS(13, 12)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

46

#define A64_AC_PR_ADDR __BITS(20,16)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

47

#define A64_ACDA_PR_WDAT __BITS(15,8)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

48

#define A64_ACDA_PR_RDAT __BITS(7,0)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

52

#define A64_HPVOL __BITS(5,0)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

62

#define A64_LINEOUT_VOL __BITS(4,0)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

64

#define A64_MIC1G __BITS(6,4)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

66

#define A64_MIC1BOOST __BITS(2,0)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

69

#define A64_MIC2G __BITS(6,4)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

71

#define A64_MIC2BOOST __BITS(2,0)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

73

#define A64_LINEING __BITS(6,4)

sys/arch/arm/sunxi/sun50i_a64_acodec.c

92

#define A64_ADCG __BITS(2,0)

sys/arch/arm/sunxi/sun50i_a64_ccu.c

253

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

254

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

255

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

256

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

264

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

265

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

267

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

274

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

275

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

277

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

284

__BITS(14,8), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

286

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

287

__BITS(19,16), /* p */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

300

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

306

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

315

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

321

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

328

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

334

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

341

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

347

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

354

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

359

__BITS(7,6), /* prediv */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

361

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

362

__BITS(13,12), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

370

__BITS(1,0), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

375

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

381

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

382

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

383

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

389

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

390

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

391

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

396

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

397

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

398

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

403

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

404

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

405

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

411

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

412

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

413

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

419

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

420

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

426

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

427

__BITS(26,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

438

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

439

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

449

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

455

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

461

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

467

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

468

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

469

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

475

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

476

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

477

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

484

__BITS(26,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

490

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

491

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_ccu.c

497

__BITS(2,0), /* div */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

105

__BITS(3,0), /* n */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

106

__BITS(17,16), /* m */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

107

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

75

__BITS(12,8), /* prediv */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

77

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

78

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun50i_a64_r_ccu.c

85

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

226

__BITS(15,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

228

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

229

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

237

__BITS(15,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

248

__BITS(9,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

249

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

250

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

256

__BITS(9,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

257

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

258

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

264

__BITS(9,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

265

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

266

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

271

__BITS(9,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

272

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

273

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

278

__BITS(9,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

279

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

280

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

351

__BITS(9,8), /* n */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

352

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

353

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

358

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun50i_h6_ccu.c

364

__BITS(4,0), /* div */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

112

__BITS(4,0), /* n */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

113

__BITS(9,8), /* m */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

120

__BITS(4,0), /* n */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

121

__BITS(9,8), /* m */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

79

__BITS(4,0), /* prediv */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

81

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

82

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

89

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

95

__BITS(4,0), /* prediv */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

97

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun50i_h6_r_ccu.c

98

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

119

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

120

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

121

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

122

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

128

__BITS(14,8), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

130

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

131

__BITS(29,26), /* p */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

139

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

140

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

141

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

152

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

157

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

164

__BITS(5,4), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

169

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

175

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

176

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

177

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

183

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

184

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

185

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

190

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

191

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

192

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

197

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

198

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

199

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

205

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

206

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun5i_a13_ccu.c

207

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

153

__BITS(14,8), /* n */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

155

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

156

__BITS(19,16), /* p */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

164

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

165

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

173

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

179

__BITS(7,6), /* prediv */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

181

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

182

__BITS(13,12), /* sel */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

187

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

188

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

189

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun6i_a31_ccu.c

194

SD0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun6i_a31_ccu.c

197

SD1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun6i_a31_ccu.c

200

SD2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun6i_a31_ccu.c

203

SD3_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun6i_a31_codec.c

100

#define PHONEOUTG __BITS(7,5)

sys/arch/arm/sunxi/sun6i_a31_codec.c

110

#define ADCRG __BITS(29,27)

sys/arch/arm/sunxi/sun6i_a31_codec.c

111

#define ADCLG __BITS(26,24)

sys/arch/arm/sunxi/sun6i_a31_codec.c

112

#define RADCMIXMUTE __BITS(13,7)

sys/arch/arm/sunxi/sun6i_a31_codec.c

120

#define LADCMIXMUTE __BITS(6,0)

sys/arch/arm/sunxi/sun6i_a31_codec.c

51

#define RMIXMUTE __BITS(23,17)

sys/arch/arm/sunxi/sun6i_a31_codec.c

59

#define LMIXMUTE __BITS(16,10)

sys/arch/arm/sunxi/sun6i_a31_codec.c

71

#define HPVOL __BITS(5,0)

sys/arch/arm/sunxi/sun6i_a31_codec.c

75

#define HPCOM_CTL __BITS(30,29)

sys/arch/arm/sunxi/sun6i_a31_codec.c

77

#define PA_ANTI_POP_CTRL __BITS(27,26)

sys/arch/arm/sunxi/sun6i_a31_codec.c

78

#define MIC1G __BITS(17,15)

sys/arch/arm/sunxi/sun6i_a31_codec.c

79

#define MIC2G __BITS(14,12)

sys/arch/arm/sunxi/sun6i_a31_codec.c

80

#define LINEING __BITS(11,9)

sys/arch/arm/sunxi/sun6i_a31_codec.c

81

#define PHONEG __BITS(8,6)

sys/arch/arm/sunxi/sun6i_a31_codec.c

82

#define PHONEPG __BITS(5,3)

sys/arch/arm/sunxi/sun6i_a31_codec.c

83

#define PHONENG __BITS(2,0)

sys/arch/arm/sunxi/sun6i_a31_codec.c

90

#define MIC1BOOST __BITS(27,25)

sys/arch/arm/sunxi/sun6i_a31_codec.c

92

#define MIC2BOOST __BITS(23,21)

sys/arch/arm/sunxi/sun6i_a31_codec.c

98

#define LINEOUTVC __BITS(15,11)

sys/arch/arm/sunxi/sun6i_a31_codec.c

99

#define PHONEPREG __BITS(10,8)

sys/arch/arm/sunxi/sun6i_dma.c

111

#define IL2B_RANGE(x, y) __BITS(ilog2(x), ilog2(y))

sys/arch/arm/sunxi/sun6i_dma.c

119

.burst_mask = __BITS(8,7),

sys/arch/arm/sunxi/sun6i_dma.c

129

.burst_mask = __BITS(8,7),

sys/arch/arm/sunxi/sun6i_dma.c

139

.burst_mask = __BITS(7,6),

sys/arch/arm/sunxi/sun6i_dma.c

149

.burst_mask = __BITS(8,7),

sys/arch/arm/sunxi/sun6i_dma.c

159

.burst_mask = __BITS(7,6),

sys/arch/arm/sunxi/sun6i_dma.c

169

.burst_mask = __BITS(7,6),

sys/arch/arm/sunxi/sun6i_dma.c

65

#define DMA_CFG_DEST_DATA_WIDTH __BITS(26,25)

sys/arch/arm/sunxi/sun6i_dma.c

68

#define DMA_CFG_DEST_ADDR_MODE __BITS(22,21)

sys/arch/arm/sunxi/sun6i_dma.c

71

#define DMA_CFG_DEST_DRQ_TYPE __BITS(20,16)

sys/arch/arm/sunxi/sun6i_dma.c

73

#define DMA_CFG_SRC_DATA_WIDTH __BITS(10,9)

sys/arch/arm/sunxi/sun6i_dma.c

74

#define DMA_CFG_SRC_ADDR_MODE __BITS(6,5)

sys/arch/arm/sunxi/sun6i_dma.c

75

#define DMA_CFG_SRC_DRQ_TYPE __BITS(4,0)

sys/arch/arm/sunxi/sun6i_dma.c

80

#define DMA_PARA_DATA_BLK_SIZE __BITS(15,8)

sys/arch/arm/sunxi/sun6i_dma.c

81

#define DMA_PARA_WAIT_CYC __BITS(7,0)

sys/arch/arm/sunxi/sun6i_spireg.h

100

#define SPI_FSR_TB_CNT __BITS(30,28)

sys/arch/arm/sunxi/sun6i_spireg.h

101

#define SPI_FSR_TF_CNT __BITS(23,16)

sys/arch/arm/sunxi/sun6i_spireg.h

103

#define SPI_FSR_RB_CNT __BITS(14,12)

sys/arch/arm/sunxi/sun6i_spireg.h

104

#define SPI_FSR_RF_CNT __BITS(7,0)

sys/arch/arm/sunxi/sun6i_spireg.h

107

#define SPI_WCR_SWC __BITS(19,16)

sys/arch/arm/sunxi/sun6i_spireg.h

108

#define SPI_WCR_WCC __BITS(15,0)

sys/arch/arm/sunxi/sun6i_spireg.h

112

#define SPI_CCTL_CDR1 __BITS(11,8)

sys/arch/arm/sunxi/sun6i_spireg.h

113

#define SPI_CCTL_CDR2 __BITS(7,0)

sys/arch/arm/sunxi/sun6i_spireg.h

116

#define SPI_BC_MBC __BITS(23,0)

sys/arch/arm/sunxi/sun6i_spireg.h

119

#define SPI_TC_MWTC __BITS(23,0)

sys/arch/arm/sunxi/sun6i_spireg.h

123

#define SPI_BCC_DBC __BITS(27,24)

sys/arch/arm/sunxi/sun6i_spireg.h

124

#define SPI_BCC_STC __BITS(23,0)

sys/arch/arm/sunxi/sun6i_spireg.h

127

#define SPI_NDMA_CTL_NDMA_MODE_CTL __BITS(7,0)

sys/arch/arm/sunxi/sun6i_spireg.h

130

#define SPI_TXD_TDATA_4 __BITS(31,0)

sys/arch/arm/sunxi/sun6i_spireg.h

133

#define SPI_RXD_RDATA_4 __BITS(31,0)

sys/arch/arm/sunxi/sun6i_spireg.h

53

#define SPI_TCR_SS_SEL __BITS(5,4)

sys/arch/arm/sunxi/sun6i_spireg.h

91

#define SPI_FCR_TX_TRIG_LEVEL __BITS(23,16)

sys/arch/arm/sunxi/sun6i_spireg.h

96

#define SPI_FCR_RX_TRIG_LEVEL __BITS(7,0)

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

42

#define APB0_DIV __BITS(1,0)

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

180

.u.nkmp.n = __BITS(15,8),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

182

.u.nkmp.m = __BITS(1,0),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

201

.u.nkmp.n = __BITS(15,8),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

203

.u.nkmp.m = __BITS(1,0),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

219

__BITS(15,8), /* n */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

228

__BITS(7,6), /* prediv */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

230

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

231

__BITS(13,12), /* sel */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

239

__BITS(1,0), /* sel */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

244

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

250

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

251

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

252

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

257

SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

260

SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

263

SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

46

#define PLL_CxCPUX_CTRL_PLL_FACTOR_N __BITS(15,8)

sys/arch/arm/sunxi/sun8i_codec.c

105

#define DACL_MXR_SRC __BITS(15,12)

sys/arch/arm/sunxi/sun8i_codec.c

107

#define DACR_MXR_SRC __BITS(11,8)

sys/arch/arm/sunxi/sun8i_codec.c

47

#define AIF1CLK_SRC __BITS(9,8)

sys/arch/arm/sunxi/sun8i_codec.c

59

#define AIF1_FS __BITS(15,12)

sys/arch/arm/sunxi/sun8i_codec.c

66

#define AIF1_BCLK_DIV __BITS(12,9)

sys/arch/arm/sunxi/sun8i_codec.c

68

#define AIF1_LRCK_DIV __BITS(8,6)

sys/arch/arm/sunxi/sun8i_codec.c

71

#define AIF1_WORD_SIZ __BITS(5,4)

sys/arch/arm/sunxi/sun8i_codec.c

73

#define AIF1_DATA_FMT __BITS(3,2)

sys/arch/arm/sunxi/sun8i_codec.c

87

#define HMIC_CTRL1_N __BITS(11,8)

sys/arch/arm/sunxi/sun8i_codec.c

93

#define HMIC_CTRL2_MDATA_THRES __BITS(12,8)

sys/arch/arm/sunxi/sun8i_crypto.h

110

#define SUN8I_CRYPTO_CTR_DIE_ID __BITS(2,0)

sys/arch/arm/sunxi/sun8i_crypto.h

112

#define SUN8I_CRYPTO_ICR_INTR_EN __BITS(3,0)

sys/arch/arm/sunxi/sun8i_crypto.h

115

#define SUN8I_CRYPTO_ISR_DONE __BITS(3,0)

sys/arch/arm/sunxi/sun8i_crypto.h

120

#define SUN8I_CRYPTO_TSR_TASK __BITS(1,0)

sys/arch/arm/sunxi/sun8i_crypto.h

123

#define SUN8I_CRYPTO_ESR_CHAN(n) (__BITS(3,0) << (n))

sys/arch/arm/sunxi/sun8i_crypto.h

48

#define SUN8I_CRYPTO_TDQC_METHOD __BITS(6,0)

sys/arch/arm/sunxi/sun8i_crypto.h

63

#define SUN8I_CRYPTO_TDQS_SKEY_SELECT __BITS(23,20)

sys/arch/arm/sunxi/sun8i_crypto.h

70

#define SUN8I_CRYPTO_TDQS_OP_MODE __BITS(11,8)

sys/arch/arm/sunxi/sun8i_crypto.h

75

#define SUN8I_CRYPTO_TDQS_CTR_WIDTH __BITS(3,2)

sys/arch/arm/sunxi/sun8i_crypto.h

80

#define SUN8I_CRYPTO_TDQS_AES_KEYSIZE __BITS(1,0)

sys/arch/arm/sunxi/sun8i_crypto.h

86

#define SUN8I_CRYPTO_TDQA_RSA_MODSIZE __BITS(30,28)

sys/arch/arm/sunxi/sun8i_h3_ccu.c

247

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

248

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

249

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

250

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

258

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

259

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

261

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

269

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

275

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

282

__BITS(14,8), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

284

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

285

__BITS(19,16), /* p */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

293

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

299

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

306

__BITS(7,6), /* prediv */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

308

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

309

__BITS(13,12), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

317

__BITS(1,0), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

322

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

328

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

329

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

330

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

336

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

337

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

338

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

344

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

345

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

351

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

352

__BITS(26,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

357

SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

360

SDMMC0_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

362

SDMMC0_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

364

SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

367

SDMMC1_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

369

SDMMC1_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

371

SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

374

SDMMC2_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

376

SDMMC2_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

380

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

381

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

382

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

387

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

388

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

389

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

398

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

399

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

408

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

409

__BITS(26,24), /* sel */

sys/arch/arm/sunxi/sun8i_h3_ccu.c

52

#define AHB2_CLK_CFG __BITS(1,0)

sys/arch/arm/sunxi/sun8i_h3_codec.c

47

#define H3_AC_PR_ADDR __BITS(20,16)

sys/arch/arm/sunxi/sun8i_h3_codec.c

48

#define H3_ACDA_PR_WDAT __BITS(15,8)

sys/arch/arm/sunxi/sun8i_h3_codec.c

49

#define H3_ACDA_PR_RDAT __BITS(7,0)

sys/arch/arm/sunxi/sun8i_h3_codec.c

61

#define H3_LINEING __BITS(6,4)

sys/arch/arm/sunxi/sun8i_h3_codec.c

63

#define H3_MIC1_GAIN __BITS(6,4)

sys/arch/arm/sunxi/sun8i_h3_codec.c

64

#define H3_MIC2_GAIN __BITS(2,0)

sys/arch/arm/sunxi/sun8i_h3_codec.c

68

#define H3_LINEOUTVOL __BITS(7,3)

sys/arch/arm/sunxi/sun8i_h3_codec.c

77

#define H3_ADCMIXSC_OMIXER __BITS(1,0)

sys/arch/arm/sunxi/sun8i_h3_codec.c

81

#define H3_ADCG __BITS(2,0)

sys/arch/arm/sunxi/sun8i_h3_r_ccu.c

72

__BITS(12,8), /* prediv */

sys/arch/arm/sunxi/sun8i_h3_r_ccu.c

74

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun8i_h3_r_ccu.c

75

__BITS(17,16), /* sel */

sys/arch/arm/sunxi/sun8i_h3_r_ccu.c

82

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

209

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

210

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

211

__BITS(1,0), /* m */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

212

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

220

__BITS(12,8), /* n */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

221

__BITS(5,4), /* k */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

223

__BITS(17,16), /* p */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

231

__BITS(14,8), /* m */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

237

__BITS(3,0), /* prediv */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

244

__BITS(14,8), /* n */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

246

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

247

__BITS(19,16), /* p */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

255

__BITS(7,6), /* prediv */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

257

__BITS(5,4), /* div */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

258

__BITS(13,12), /* sel */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

266

__BITS(1,0), /* sel */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

271

__BITS(9,8), /* div */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

277

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

278

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

279

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

284

SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

287

SDMMC0_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

289

SDMMC0_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

291

SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

294

SDMMC1_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

296

SDMMC1_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

298

SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

301

SDMMC2_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

303

SDMMC2_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

307

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

308

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

309

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

318

__BITS(3,0), /* div */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

319

__BITS(26,24), /* sel */

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

52

#define AHB2_CLK_CFG __BITS(1,0)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

48

#define V3S_PR_ADDR __BITS(20,16)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

49

#define V3S_ADDA_PR_WDAT __BITS(15,8)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

50

#define V3S_ADDA_PR_RDAT __BITS(7,0)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

53

#define V3S_HPVOL __BITS(5,0)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

67

#define V3S_MIC_GAIN __BITS(6,4)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

73

#define V3S_ADCMIXMUTE_MIXER __BITS(1,0)

sys/arch/arm/sunxi/sun8i_v3s_codec.c

77

#define V3S_ADCG __BITS(2,0)

sys/arch/arm/sunxi/sun9i_a80_ccu.c

182

.u.nkmp.n = __BITS(15,8),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

184

.u.nkmp.m = __BITS(1,0),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

203

.u.nkmp.n = __BITS(15,8),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

205

.u.nkmp.m = __BITS(1,0),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

221

__BITS(15,8), /* n */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

229

__BITS(15,8), /* n */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

238

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

239

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

244

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

245

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

250

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

251

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

256

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

257

__BITS(25,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

262

__BITS(1,0), /* div */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

268

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

269

__BITS(4,0), /* m */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

276

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

277

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

278

__BITS(27,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

282

SDMMC0_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

284

SDMMC0_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

287

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

288

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

289

__BITS(27,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

293

SDMMC1_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

295

SDMMC1_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

298

__BITS(17,16), /* n */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

299

__BITS(3,0), /* m */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

300

__BITS(27,24), /* sel */

sys/arch/arm/sunxi/sun9i_a80_ccu.c

304

SDMMC2_CLK_REG, __BITS(22,20)),

sys/arch/arm/sunxi/sun9i_a80_ccu.c

306

SDMMC2_CLK_REG, __BITS(10,8)),

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

42

#define CPUS_CLK_SRC_SEL __BITS(17,16)

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

44

#define CPUS_POST_DIV __BITS(12,8)

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

45

#define CPUS_CLK_RATIO __BITS(5,4)

sys/arch/arm/sunxi/sunxi_can.h

101

#define SUNXI_CAN_RMSGC_RX_MSG_CNT __BITS(7,0)

sys/arch/arm/sunxi/sunxi_can.h

105

#define SUNXI_CAN_RSADDR_RX_BUF_SADDR __BITS(5,0)

sys/arch/arm/sunxi/sunxi_can.h

111

#define SUNXI_CAN_TXBUF0_DL __BITS(3,0)

sys/arch/arm/sunxi/sunxi_can.h

51

#define SUNXI_CAN_STA_ERR_CODE __BITS(23,22)

sys/arch/arm/sunxi/sunxi_can.h

57

#define SUNXI_CAN_STA_ERR_SEG_CODE __BITS(20,16)

sys/arch/arm/sunxi/sunxi_can.h

58

#define SUNXI_CAN_STA_ARB_LOST __BITS(12,8)

sys/arch/arm/sunxi/sunxi_can.h

85

#define SUNXI_CAN_BUS_TIME_PHSEG2 __BITS(22,20)

sys/arch/arm/sunxi/sunxi_can.h

86

#define SUNXI_CAN_BUS_TIME_PHSEG1 __BITS(19,16)

sys/arch/arm/sunxi/sunxi_can.h

87

#define SUNXI_CAN_BUS_TIME_SJW __BITS(15,14)

sys/arch/arm/sunxi/sunxi_can.h

88

#define SUNXI_CAN_BUS_TIME_TQ_BRP __BITS(9,0)

sys/arch/arm/sunxi/sunxi_can.h

92

#define SUNXI_CAN_EWL_ERR_WRN_LMT __BITS(7,0)

sys/arch/arm/sunxi/sunxi_can.h

96

#define SUNXI_CAN_REC_RX_ERR_CNT __BITS(23,16)

sys/arch/arm/sunxi/sunxi_can.h

97

#define SUNXI_CAN_REC_TX_ERR_CNT __BITS(7,0)

sys/arch/arm/sunxi/sunxi_codec.c

55

#define DAC_FIFOC_FS __BITS(31,29)

sys/arch/arm/sunxi/sunxi_codec.c

64

#define DAC_FIFOC_FIFO_MODE __BITS(25,24)

sys/arch/arm/sunxi/sunxi_codec.c

68

#define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21)

sys/arch/arm/sunxi/sunxi_codec.c

69

#define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8)

sys/arch/arm/sunxi/sunxi_codec.c

77

#define ADC_FIFOC_FS __BITS(31,29)

sys/arch/arm/sunxi/sunxi_codec.c

81

#define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8)

sys/arch/arm/sunxi/sunxi_de2_ccu.c

68

0x0c, __BITS(3,0), 0, SUNXI_CCU_DIV_SET_RATE_PARENT),

sys/arch/arm/sunxi/sunxi_de2_ccu.c

70

0x0c, __BITS(7,4), 0, SUNXI_CCU_DIV_SET_RATE_PARENT),

sys/arch/arm/sunxi/sunxi_de2_ccu.c

72

0x0c, __BITS(11,8), 0, SUNXI_CCU_DIV_SET_RATE_PARENT),

sys/arch/arm/sunxi/sunxi_debereg.h

115

#define SUNXI_DEBE_ATTCTL1_LAY_FBPS __BITS(1,0)

sys/arch/arm/sunxi/sunxi_debereg.h

122

#define SUNXI_DEBE_HWCCTL_YCOOR __BITS(31,16)

sys/arch/arm/sunxi/sunxi_debereg.h

123

#define SUNXI_DEBE_HWCCTL_XCOOR __BITS(15,0)

sys/arch/arm/sunxi/sunxi_debereg.h

125

#define SUNXI_DEBE_HWCFBCTL_YCOOROFF __BITS(31,24)

sys/arch/arm/sunxi/sunxi_debereg.h

126

#define SUNXI_DEBE_HWCFBCTL_XCOOROFF __BITS(23,16)

sys/arch/arm/sunxi/sunxi_debereg.h

127

#define SUNXI_DEBE_HWCFBCTL_YSIZE __BITS(5,4)

sys/arch/arm/sunxi/sunxi_debereg.h

130

#define SUNXI_DEBE_HWCFBCTL_XSIZE __BITS(3,2)

sys/arch/arm/sunxi/sunxi_debereg.h

133

#define SUNXI_DEBE_HWCFBCTL_FBFMT __BITS(1,0)

sys/arch/arm/sunxi/sunxi_debereg.h

72

#define SUNXI_DEBE_MODCTL_OUT_SEL __BITS(22,20)

sys/arch/arm/sunxi/sunxi_debereg.h

86

#define SUNXI_DEBE_ATTCTL0_LAY_GLBALPHA __BITS(31,24)

sys/arch/arm/sunxi/sunxi_debereg.h

87

#define SUNXI_DEBE_ATTCTL0_LAY_WORKMOD __BITS(23,22)

sys/arch/arm/sunxi/sunxi_debereg.h

89

#define SUNXI_DEBE_ATTCTL0_CKEN __BITS(19,18)

sys/arch/arm/sunxi/sunxi_debereg.h

91

#define SUNXI_DEBE_ATTCTL0_LAY_PRISEL __BITS(11,10)

sys/arch/arm/sunxi/sunxi_debereg.h

97

#define SUNXI_DEBE_ATTCTL1_LAY_HSCAFCT __BITS(15,14)

sys/arch/arm/sunxi/sunxi_debereg.h

98

#define SUNXI_DEBE_ATTCTL1_LAY_WSCAFCT __BITS(13,12)

sys/arch/arm/sunxi/sunxi_debereg.h

99

#define SUNXI_DEBE_ATTCTL1_LAY_FBFMT __BITS(11,8)

sys/arch/arm/sunxi/sunxi_gmacclk.c

45

#define GMAC_CLK_SRC __BITS(1,0)

sys/arch/arm/sunxi/sunxi_gpio.c

76

#define SUNXI_GPIO_INT_DEBOUNCE_CLK_PRESCALE __BITS(6,4)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

44

#define DBG_CTRL_POL __BITS(15,8)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

58

#define ANA_CFG1_TXEN __BITS(15,12)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

59

#define ANA_CFG1_BIASEN __BITS(11,8)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

60

#define ANA_CFG1_ENP2S __BITS(7,4)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

67

#define ANA_CFG2_REG_RESDI __BITS(5,0)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

78

#define PLL_CFG1_B_IN __BITS(5,0)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

81

#define PLL_CFG2_PREDIV __BITS(3,0)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

87

#define ANA_STS_B_OUT __BITS(16,11)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

89

#define ANA_STS_RESDO2D __BITS(5,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

100

#define SUNXI_HDMI_VID_CTRL_COLOR_MODE __BITS(3,2)

sys/arch/arm/sunxi/sunxi_hdmireg.h

105

#define SUNXI_HDMI_VID_CTRL_REPEATER_SEL __BITS(1,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

110

#define SUNXI_HDMI_VID_TIMING_0_ACT_V __BITS(27,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

111

#define SUNXI_HDMI_VID_TIMING_0_ACT_H __BITS(11,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

113

#define SUNXI_HDMI_VID_TIMING_1_VBP __BITS(27,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

114

#define SUNXI_HDMI_VID_TIMING_1_HBP __BITS(11,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

116

#define SUNXI_HDMI_VID_TIMING_2_VFP __BITS(27,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

117

#define SUNXI_HDMI_VID_TIMING_2_HFP __BITS(11,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

119

#define SUNXI_HDMI_VID_TIMING_3_VSPW __BITS(27,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

120

#define SUNXI_HDMI_VID_TIMING_3_HSPW __BITS(11,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

122

#define SUNXI_HDMI_VID_TIMING_4_TX_CLOCK __BITS(25,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

150

#define SUNXI_HDMI_PAD_CTRL1_REG_EMP __BITS(12,10)

sys/arch/arm/sunxi/sunxi_hdmireg.h

151

#define SUNXI_HDMI_PAD_CTRL1_REG_CD __BITS(9,8)

sys/arch/arm/sunxi/sunxi_hdmireg.h

152

#define SUNXI_HDMI_PAD_CTRL1_REG_CKSS __BITS(7,6)

sys/arch/arm/sunxi/sunxi_hdmireg.h

153

#define SUNXI_HDMI_PAD_CTRL1_REG_AMP __BITS(5,3)

sys/arch/arm/sunxi/sunxi_hdmireg.h

154

#define SUNXI_HDMI_PAD_CTRL1_REG_PLR __BITS(2,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

165

#define SUNXI_HDMI_PLL_CTRL_VCO_GAIN __BITS(22,20)

sys/arch/arm/sunxi/sunxi_hdmireg.h

166

#define SUNXI_HDMI_PLL_CTRL_S __BITS(19,17)

sys/arch/arm/sunxi/sunxi_hdmireg.h

167

#define SUNXI_HDMI_PLL_CTRL_CP_S __BITS(16,12)

sys/arch/arm/sunxi/sunxi_hdmireg.h

168

#define SUNXI_HDMI_PLL_CTRL_CS __BITS(11,8)

sys/arch/arm/sunxi/sunxi_hdmireg.h

169

#define SUNXI_HDMI_PLL_CTRL_PREDIV __BITS(7,4)

sys/arch/arm/sunxi/sunxi_hdmireg.h

170

#define SUNXI_HDMI_PLL_CTRL_VCO_S __BITS(3,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

176

#define SUNXI_HDMI_ADMA_CTRL_DMA_REQ_CTRL __BITS(25,24)

sys/arch/arm/sunxi/sunxi_hdmireg.h

179

#define SUNXI_HDMI_ADMA_CTRL_SRC_WORD_LEN __BITS(17,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

184

#define SUNXI_HDMI_AUD_FMT_SEL __BITS(26,24)

sys/arch/arm/sunxi/sunxi_hdmireg.h

187

#define SUNXI_HDMI_AUD_FMT_SRC_CH_CFG __BITS(2,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

189

#define SUNXI_HDMI_AUD_CH_STATUS0_CHNL_BIT1 __BITS(31,30)

sys/arch/arm/sunxi/sunxi_hdmireg.h

190

#define SUNXI_HDMI_AUD_CH_STATUS0_CLK_ACCUR __BITS(29,28)

sys/arch/arm/sunxi/sunxi_hdmireg.h

191

#define SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ __BITS(27,24)

sys/arch/arm/sunxi/sunxi_hdmireg.h

199

#define SUNXI_HDMI_AUD_CH_STATUS0_CH_NUM __BITS(23,20)

sys/arch/arm/sunxi/sunxi_hdmireg.h

200

#define SUNXI_HDMI_AUD_CH_STATUS0_SOURCE_NUM __BITS(19,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

201

#define SUNXI_HDMI_AUD_CH_STATUS0_CATEGORY_CODE __BITS(15,8)

sys/arch/arm/sunxi/sunxi_hdmireg.h

202

#define SUNXI_HDMI_AUD_CH_STATUS0_MODE __BITS(7,6)

sys/arch/arm/sunxi/sunxi_hdmireg.h

203

#define SUNXI_HDMI_AUD_CH_STATUS0_EMPHASIS __BITS(5,3)

sys/arch/arm/sunxi/sunxi_hdmireg.h

208

#define SUNXI_HDMI_AUD_CH_STATUS1_CGMS_A __BITS(9,8)

sys/arch/arm/sunxi/sunxi_hdmireg.h

209

#define SUNXI_HDMI_AUD_CH_STATUS1_ORIGINAL_FS __BITS(7,4)

sys/arch/arm/sunxi/sunxi_hdmireg.h

210

#define SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN __BITS(3,1)

sys/arch/arm/sunxi/sunxi_hdmireg.h

220

#define SUNXI_HDMI_DDC_SLAVE_ADDR_0 __BITS(31,24)

sys/arch/arm/sunxi/sunxi_hdmireg.h

221

#define SUNXI_HDMI_DDC_SLAVE_ADDR_1 __BITS(23,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

222

#define SUNXI_HDMI_DDC_SLAVE_ADDR_2 __BITS(15,8)

sys/arch/arm/sunxi/sunxi_hdmireg.h

223

#define SUNXI_HDMI_DDC_SLAVE_ADDR_3 __BITS(6,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

237

#define SUNXI_HDMI_DDC_FIFO_CTRL_RX_TRIGGER_THRESH __BITS(7,4)

sys/arch/arm/sunxi/sunxi_hdmireg.h

238

#define SUNXI_HDMI_DDC_FIFO_CTRL_TX_TRIGGER_THRESH __BITS(3,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

243

#define SUNXI_HDMI_DDC_FIFO_STATUS_LEVEL __BITS(4,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

245

#define SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD __BITS(2,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

255

#define SUNXI_HDMI_DDC_CLOCK_M __BITS(6,3)

sys/arch/arm/sunxi/sunxi_hdmireg.h

256

#define SUNXI_HDMI_DDC_CLOCK_N __BITS(2,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

290

#define SUNXI_A31_HDMI_DDC_COMMAND_DTC __BITS(25,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

291

#define SUNXI_A31_HDMI_DDC_COMMAND_CMD __BITS(2,0)

sys/arch/arm/sunxi/sunxi_hdmireg.h

295

#define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR __BITS(31,24)

sys/arch/arm/sunxi/sunxi_hdmireg.h

296

#define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD __BITS(23,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

297

#define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR __BITS(15,8)

sys/arch/arm/sunxi/sunxi_hdmireg.h

298

#define SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR __BITS(7,1)

sys/arch/arm/sunxi/sunxi_hdmireg.h

80

#define SUNXI_HDMI_VERSION_ID_H __BITS(31,16)

sys/arch/arm/sunxi/sunxi_hdmireg.h

81

#define SUNXI_HDMI_VERSION_ID_L __BITS(15,0)

sys/arch/arm/sunxi/sunxi_hstimer.c

45

#define HS_TMR0_CTRL_CLK_PRESCALE __BITS(6,4)

sys/arch/arm/sunxi/sunxi_hstimer.c

54

#define HS_TMR1_CTRL_CLK_PRESCALE __BITS(6,4)

sys/arch/arm/sunxi/sunxi_hstimer.c

63

#define HS_TMR2_CTRL_CLK_PRESCALE __BITS(6,4)

sys/arch/arm/sunxi/sunxi_hstimer.c

72

#define HS_TMR3_CTRL_CLK_PRESCALE __BITS(6,4)

sys/arch/arm/sunxi/sunxi_i2s.c

103

#define DA_CHCFG_RX_SLOT_NUM __BITS(6,4)

sys/arch/arm/sunxi/sunxi_i2s.c

104

#define DA_CHCFG_TX_SLOT_NUM __BITS(2,0)

sys/arch/arm/sunxi/sunxi_i2s.c

106

#define DA_CHSEL_OFFSET __BITS(13,12) /* sun8i */

sys/arch/arm/sunxi/sunxi_i2s.c

107

#define DA_CHSEL_EN __BITS(11,4)

sys/arch/arm/sunxi/sunxi_i2s.c

108

#define DA_CHSEL_SEL __BITS(2,0)

sys/arch/arm/sunxi/sunxi_i2s.c

54

#define DA_CTL_MODE_SEL __BITS(5,4) /* sun8i */

sys/arch/arm/sunxi/sunxi_i2s.c

62

#define DA_FAT0_LRCK_PERIOD __BITS(17,8) /* sun8i */

sys/arch/arm/sunxi/sunxi_i2s.c

69

#define DA_FAT0_SR __BITS(5,4)

sys/arch/arm/sunxi/sunxi_i2s.c

70

#define DA_FAT0_WSS __BITS(3,2)

sys/arch/arm/sunxi/sunxi_i2s.c

71

#define DA_FAT0_FMT __BITS(1,0)

sys/arch/arm/sunxi/sunxi_i2s.c

83

#define DA_FCTL_RXIM __BITS(1,0)

sys/arch/arm/sunxi/sunxi_i2s.c

92

#define DA_CLKD_BCLKDIV_SUN8I __BITS(7,4)

sys/arch/arm/sunxi/sunxi_i2s.c

93

#define DA_CLKD_BCLKDIV_SUN4I __BITS(6,4)

sys/arch/arm/sunxi/sunxi_i2s.c

96

#define DA_CLKD_MCLKDIV __BITS(3,0)

sys/arch/arm/sunxi/sunxi_lcdc.c

59

#define TCON_GINT1_TCON1_LINE_INT_NUM __BITS(11,0)

sys/arch/arm/sunxi/sunxi_lcdc.c

63

#define TCON0_CTL_START_DELAY __BITS(8,4)

sys/arch/arm/sunxi/sunxi_lcdc.c

64

#define TCON0_CTL_TCON0_SRC_SEL __BITS(2,0)

sys/arch/arm/sunxi/sunxi_lcdc.c

66

#define TCON0_DCLK_EN __BITS(31,28)

sys/arch/arm/sunxi/sunxi_lcdc.c

67

#define TCON0_DCLK_DIV __BITS(6,0)

sys/arch/arm/sunxi/sunxi_lcdc.c

74

#define TCON0_IO_POL_DCLK_SEL __BITS(30,28)

sys/arch/arm/sunxi/sunxi_lcdc.c

79

#define TCON0_IO_POL_DATA_INV __BITS(23,0)

sys/arch/arm/sunxi/sunxi_lcdc.c

84

#define TCON1_CTL_START_DELAY __BITS(8,4)

sys/arch/arm/sunxi/sunxi_lcdc.c

85

#define TCON1_CTL_TCON1_SRC_SEL __BITS(1,0)

sys/arch/arm/sunxi/sunxi_lcdc.c

97

#define TCON1_IO_POL_DATA_INV __BITS(23,0)

sys/arch/arm/sunxi/sunxi_lradc.h

30

#define AWIN_LRADC_CTRL_FIRSTCONV_MASK __BITS(31,24)

sys/arch/arm/sunxi/sunxi_lradc.h

32

#define AWIN_LRADC_CTRL_CHAN_MASK __BITS(23,22)

sys/arch/arm/sunxi/sunxi_lradc.h

34

#define AWIN_LRADC_CTRL_CONT_MASK __BITS(19,16)

sys/arch/arm/sunxi/sunxi_lradc.h

36

#define AWIN_LRADC_CTRL_KMODE_MASK __BITS(13,12)

sys/arch/arm/sunxi/sunxi_lradc.h

40

#define AWIN_LRADC_CTRL_LV_A_B_CNT_MASK __BITS(11,8)

sys/arch/arm/sunxi/sunxi_lradc.h

43

#define AWIN_LRADC_CTRL_LEVEL_B_MASK __BITS(5,4)

sys/arch/arm/sunxi/sunxi_lradc.h

48

#define AWIN_LRADC_CTRL_RATE_MASK __BITS(3,2)

sys/arch/arm/sunxi/sunxi_mixer.c

126

#define OVL_V_TOP_HADD_LAYER0 __BITS(7,0)

sys/arch/arm/sunxi/sunxi_mixer.c

135

#define OVL_UI_ATTR_CTL_LAY_FBFMT __BITS(12,8)

sys/arch/arm/sunxi/sunxi_mixer.c

150

#define OVL_UI_TOP_HADD_LAYER1 __BITS(15,8)

sys/arch/arm/sunxi/sunxi_mixer.c

151

#define OVL_UI_TOP_HADD_LAYER0 __BITS(7,0)

sys/arch/arm/sunxi/sunxi_mixer.c

88

#define BLD_CH_RTCTL_P3 __BITS(15,12)

sys/arch/arm/sunxi/sunxi_mixer.c

89

#define BLD_CH_RTCTL_P2 __BITS(11,8)

sys/arch/arm/sunxi/sunxi_mixer.c

90

#define BLD_CH_RTCTL_P1 __BITS(7,4)

sys/arch/arm/sunxi/sunxi_mixer.c

91

#define BLD_CH_RTCTL_P0 __BITS(3,0)

sys/arch/arm/sunxi/sunxi_mixer.c

98

#define OVL_V_ATTCTL_LAY_FBFMT __BITS(12,8)

sys/arch/arm/sunxi/sunxi_mmc.h

144

#define SUNXI_MMC_NTSR_SAMPLE_PHASE __BITS(30,6)

sys/arch/arm/sunxi/sunxi_mmc.h

145

#define SUNXI_MMC_NTSR_OUTPUT_PHASE __BITS(1,0)

sys/arch/arm/sunxi/sunxi_mmc.h

79

#define SUNXI_MMC_CLKCR_DIV __BITS(7,0)

sys/arch/arm/sunxi/sunxi_nand.c

46

#define NDFC_CTL_CE_SEL __BITS(27,24)

sys/arch/arm/sunxi/sunxi_nand.c

47

#define NDFC_CTL_PAGE_SIZE __BITS(11,8)

sys/arch/arm/sunxi/sunxi_nand.c

48

#define NDFC_CTL_RB_SEL __BITS(4,3)

sys/arch/arm/sunxi/sunxi_nand.c

57

#define NDFC_ST_INT_MASK __BITS(2,0)

sys/arch/arm/sunxi/sunxi_nand.c

66

#define NDFC_CNT_DATA_CNT __BITS(9,0)

sys/arch/arm/sunxi/sunxi_nand.c

73

#define NDFC_CMD_ADR_NUM __BITS(18,16)

sys/arch/arm/sunxi/sunxi_nmi.c

55

#define NMI_CTRL_IRQ_TYPE __BITS(1,0)

sys/arch/arm/sunxi/sunxi_platform.c

74

#define SUN4I_TIMER_1_CTRL_CLK_SRC __BITS(3,2)

sys/arch/arm/sunxi/sunxi_pwm.c

52

#define PWM_CH0_PRESCAL __BITS(3,0)

sys/arch/arm/sunxi/sunxi_pwm.c

54

#define PWM_CH0_ENTIRE_CYS __BITS(31,16)

sys/arch/arm/sunxi/sunxi_pwm.c

55

#define PWM_CH0_ENTIRE_ACT_CYS __BITS(15,0)

sys/arch/arm/sunxi/sunxi_rsb.h

38

#define RSB_CCR_SDA_ODLY __BITS(10,8)

sys/arch/arm/sunxi/sunxi_rsb.h

39

#define RSB_CCR_CLK_DIV __BITS(7,0)

sys/arch/arm/sunxi/sunxi_rsb.h

45

#define RSB_STAT_TRANS_ERR_ID __BITS(15,8)

sys/arch/arm/sunxi/sunxi_rsb.h

57

#define RSB_DLEN_ACCESS_LENGTH __BITS(2,0)

sys/arch/arm/sunxi/sunxi_rsb.h

69

#define RSB_PMCR_PMU_INIT_DATA __BITS(23,16)

sys/arch/arm/sunxi/sunxi_rsb.h

70

#define RSB_PMCR_PMU_MODE_CTRL_REG_ADDR __BITS(15,8)

sys/arch/arm/sunxi/sunxi_rsb.h

71

#define RSB_PMCR_PMU_DEVICE_ADDR __BITS(7,0)

sys/arch/arm/sunxi/sunxi_rsb.h

73

#define RSB_CMD_IDX __BITS(7,0)

sys/arch/arm/sunxi/sunxi_rsb.h

82

#define RSB_DAR_RTA __BITS(23,16)

sys/arch/arm/sunxi/sunxi_rsb.h

83

#define RSB_DAR_DA __BITS(15,0)

sys/arch/arm/sunxi/sunxi_rtc.c

46

#define SUN4I_RTC_YEAR __BITS(21,16)

sys/arch/arm/sunxi/sunxi_rtc.c

47

#define SUN4I_RTC_MONTH __BITS(11,8)

sys/arch/arm/sunxi/sunxi_rtc.c

48

#define SUN4I_RTC_DAY __BITS(4,0)

sys/arch/arm/sunxi/sunxi_rtc.c

50

#define SUN4I_RTC_WK_NO __BITS(31,29)

sys/arch/arm/sunxi/sunxi_rtc.c

51

#define SUN4I_RTC_HOUR __BITS(20,16)

sys/arch/arm/sunxi/sunxi_rtc.c

52

#define SUN4I_RTC_MINUTE __BITS(13,8)

sys/arch/arm/sunxi/sunxi_rtc.c

53

#define SUN4I_RTC_SECOND __BITS(5,0)

sys/arch/arm/sunxi/sunxi_rtc.c

58

#define SUN7I_RTC_YEAR __BITS(23,16)

sys/arch/arm/sunxi/sunxi_rtc.c

59

#define SUN7I_RTC_MONTH __BITS(11,8)

sys/arch/arm/sunxi/sunxi_rtc.c

60

#define SUN7I_RTC_DAY __BITS(4,0)

sys/arch/arm/sunxi/sunxi_rtc.c

62

#define SUN7I_RTC_WK_NO __BITS(31,29)

sys/arch/arm/sunxi/sunxi_rtc.c

63

#define SUN7I_RTC_HOUR __BITS(20,16)

sys/arch/arm/sunxi/sunxi_rtc.c

64

#define SUN7I_RTC_MINUTE __BITS(13,8)

sys/arch/arm/sunxi/sunxi_rtc.c

65

#define SUN7I_RTC_SECOND __BITS(5,0)

sys/arch/arm/sunxi/sunxi_rtc.c

78

#define SUN6I_INTOSC_CLK_PRESCAL __BITS(0,4)

sys/arch/arm/sunxi/sunxi_rtc.c

82

#define SUN6I_RTC_YEAR __BITS(21,16)

sys/arch/arm/sunxi/sunxi_rtc.c

83

#define SUN6I_RTC_MONTH __BITS(11,8)

sys/arch/arm/sunxi/sunxi_rtc.c

84

#define SUN6I_RTC_DAY __BITS(4,0)

sys/arch/arm/sunxi/sunxi_rtc.c

86

#define SUN6I_RTC_WK_NO __BITS(31,29)

sys/arch/arm/sunxi/sunxi_rtc.c

87

#define SUN6I_RTC_HOUR __BITS(20,16)

sys/arch/arm/sunxi/sunxi_rtc.c

88

#define SUN6I_RTC_MINUTE __BITS(13,8)

sys/arch/arm/sunxi/sunxi_rtc.c

89

#define SUN6I_RTC_SECOND __BITS(5,0)

sys/arch/arm/sunxi/sunxi_sramc.c

67

.mask = __BITS(5,4),

sys/arch/arm/sunxi/sunxi_tconreg.h

103

#define SUNXI_TCON0_DCLK_DIV __BITS(6,0)

sys/arch/arm/sunxi/sunxi_tconreg.h

120

#define SUNXI_TCON_IO_TRI_DATA __BITS(23,0)

sys/arch/arm/sunxi/sunxi_tconreg.h

122

#define SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC __BITS(9,8)

sys/arch/arm/sunxi/sunxi_tconreg.h

81

#define SUNXI_TCON_GINT1_TCON0_LINENO __BITS(27,16)

sys/arch/arm/sunxi/sunxi_tconreg.h

82

#define SUNXI_TCON_GINT1_TCON1_LINENO __BITS(11,0)

sys/arch/arm/sunxi/sunxi_tconreg.h

90

#define SUNXI_TCON0_CTL0_IF __BITS(25,24)

sys/arch/arm/sunxi/sunxi_tconreg.h

97

#define SUNXI_TCONx_CTL_START_DELAY __BITS(8,4)

sys/arch/arm/sunxi/sunxi_tconreg.h

98

#define SUNXI_TCONx_CTL_SRC_SEL __BITS(1,0)

sys/arch/arm/sunxi/sunxi_timer.c

53

#define TMR0_CTRL_CLK_PRESCALE __BITS(6,4)

sys/arch/arm/sunxi/sunxi_timer.c

54

#define TMR0_CTRL_CLK_SRC __BITS(3,2)

sys/arch/arm/sunxi/sunxi_timer.c

67

#define TMR2_CTRL_CLK_SRC __BITS(3,2)

sys/arch/arm/sunxi/sunxi_timer.c

89

#define LOSC_CTRL_KEY_FIELD __BITS(31,16)

sys/arch/arm/sunxi/sunxi_ts.c

100

#define TP_DATA_MASK __BITS(11,0)

sys/arch/arm/sunxi/sunxi_ts.c

103

#define TP_PORT_DATA_MASK __BITS(3,0)

sys/arch/arm/sunxi/sunxi_ts.c

52

#define TP_CTRL0_ADC_FIRST_DLY __BITS(31,24)

sys/arch/arm/sunxi/sunxi_ts.c

55

#define TP_CTRL0_ADC_CLK_DIVIDER __BITS(21,20)

sys/arch/arm/sunxi/sunxi_ts.c

56

#define TP_CTRL0_FS_DIV __BITS(19,16)

sys/arch/arm/sunxi/sunxi_ts.c

57

#define TP_CTRL0_T_ACQ __BITS(15,0)

sys/arch/arm/sunxi/sunxi_ts.c

59

#define TP_CTRL1_STYLUS_UP_DEBOUNCE __BITS(19,12)

sys/arch/arm/sunxi/sunxi_ts.c

65

#define TP_CTRL1_ADC_CHAN_SELECT __BITS(2,0)

sys/arch/arm/sunxi/sunxi_ts.c

67

#define TP_CTRL2_SENSITIVE_ADJUST __BITS(31,28)

sys/arch/arm/sunxi/sunxi_ts.c

68

#define TP_CTRL2_MODE_SELECT __BITS(27,26)

sys/arch/arm/sunxi/sunxi_ts.c

70

#define TP_CTRL2_PRE_MEA_THRE_CNT __BITS(23,0)

sys/arch/arm/sunxi/sunxi_ts.c

73

#define TP_CTRL3_FILTER_TYPE __BITS(1,0)

sys/arch/arm/sunxi/sunxi_ts.c

79

#define TP_INT_FIFO_TRIG_LEVEL __BITS(12,8)

sys/arch/arm/sunxi/sunxi_ts.c

88

#define TP_FIFOCS_RXA_CNT __BITS(12,8)

sys/arch/arm/sunxi/sunxi_ts.c

94

#define TP_TPR_TEMP_PER __BITS(15,0)

sys/arch/arm/sunxi/sunxi_ts.c

96

#define TP_CDAT_MASK __BITS(11,0)

sys/arch/arm/sunxi/sunxi_ts.c

98

#define TEMP_DATA_MASK __BITS(11,0)

sys/arch/arm/sunxi/sunxi_twi.c

47

#define TWI_CCR_CLK_M __BITS(6,3)

sys/arch/arm/sunxi/sunxi_twi.c

48

#define TWI_CCR_CLK_N __BITS(2,0)

sys/arch/arm/sunxi/sunxi_usb3phy.c

43

#define APP_FORCE_VBUS __BITS(13,12)

sys/arch/arm/sunxi/sunxi_usb3phy.c

52

#define PTH_TX_DEEMPH_3P5DB __BITS(24,19)

sys/arch/arm/sunxi/sunxi_usb3phy.c

53

#define PTH_TX_DEEMPH_6DB __BITS(18,13)

sys/arch/arm/sunxi/sunxi_usb3phy.c

54

#define PTH_TX_SWING_FULL __BITS(12,6)

sys/arch/arm/sunxi/sunxi_usb3phy.c

55

#define PTH_LOS_BIAS __BITS(5,3)

sys/arch/arm/sunxi/sunxi_usb3phy.c

56

#define PTH_TX_BOOST_LVL __BITS(2,0)

sys/arch/arm/sunxi/sunxi_usb3phy.c

61

#define PEC_EXTERN_VBUS __BITS(2,1)

sys/arch/arm/sunxi/sunxi_usbphy.c

46

#define PHYCTL_ICR_FORCE_ID __BITS(15,14)

sys/arch/arm/sunxi/sunxi_usbphy.c

49

#define PHYCTL_ICR_FORCE_VBUS __BITS(13,12)

sys/arch/arm/sunxi/sunxi_usbphy.c

54

#define PHYCTL_ADDR __BITS(15,8)

sys/arch/arm/sunxi/sunxi_wdt.c

47

#define SUN4I_WDT_CTRL_KEY_FIELD __BITS(12,1)

sys/arch/arm/sunxi/sunxi_wdt.c

51

#define SUN4I_WDT_MODE_INTV __BITS(6,3)

sys/arch/arm/sunxi/sunxi_wdt.c

60

#define SUN6I_WDT_CTRL_KEY_FIELD __BITS(12,1)

sys/arch/arm/sunxi/sunxi_wdt.c

64

#define SUN6I_WDT_CFG_CONFIG __BITS(1,0)

sys/arch/arm/sunxi/sunxi_wdt.c

68

#define SUN6I_WDT_MODE_INTV __BITS(7,4)

sys/arch/arm/sunxi/sunxi_wdt.c

71

#define SUNXI_WDT_KEY_FIELD __BITS(31,16)

sys/arch/arm/ti/am18xx_pllc.c

93

#define AM18XX_PLLC_PLLM_MULTIPLIER __BITS(4,0)

sys/arch/arm/ti/am18xx_pllc.c

94

#define AM18XX_PLLC_PREDIV_RATIO __BITS(4,0)

sys/arch/arm/ti/am18xx_pllc.c

95

#define AM18XX_PLLC_POSTDIV_RATIO __BITS(4,0)

sys/arch/arm/ti/am18xx_pllc.c

96

#define AM18XX_PLLC_PLLDIV_RATIO __BITS(4,0)

sys/arch/arm/ti/am18xx_usbphyclk.c

110

#define AM18XX_CFGCHIP2_PHYREFFREQ __BITS(3, 0)

sys/arch/arm/ti/am3_prcm.c

52

#define AM3_PRCM_CLKCTRL_MODULEMODE __BITS(1,0)

sys/arch/arm/ti/am3_prcm.c

59

#define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT __BITS(18,8)

sys/arch/arm/ti/am3_prcm.c

60

#define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV __BITS(6,0)

sys/arch/arm/ti/am3_prcm.c

62

#define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN __BITS(2,0)

sys/arch/arm/ti/if_cpsw.c

1202

off = __SHIFTOUT(dw[2], (uint32_t)__BITS(26, 16));

sys/arch/arm/ti/if_cpsw.c

1203

len = __SHIFTOUT(dw[3], (uint32_t)__BITS(10, 0));

sys/arch/arm/ti/if_cpswreg.h

129

#define __BITS32(x, y) ((uint32_t)__BITS((x), (y)))

sys/arch/arm/ti/omap2_gpmcreg.h

188

#define GPMC_REVISION_REV __BITS(7,0)

sys/arch/arm/ti/omap2_gpmcreg.h

195

#define GPMC_CONFIG7_BASEADDRESS __BITS(5,0)

sys/arch/arm/ti/omap2_gpmcreg.h

197

#define GPMC_CONFIG7_MASKADDRESS __BITS(11,8)

sys/arch/arm/ti/omap2_nand.c

66

#define ECCPOINTER __BITS(3,0)

sys/arch/arm/ti/omap2_nand.c

70

#define ECCCS __BITS(3,1)

sys/arch/arm/ti/omap2_nand.c

74

#define ECCSIZE1 __BITS(29,22)

sys/arch/arm/ti/omap2_nand.c

77

#define DEVICETYPE __BITS(11,10)

sys/arch/arm/ti/omap2_nand.c

78

#define DEVICESIZE __BITS(13,12)

sys/arch/arm/ti/omap3_platform.c

114

#define OMAP4_SYS_CLKSEL_CLKIN __BITS(2,0)

sys/arch/arm/ti/omap3_platform.c

122

#define OMAP4_DPLL_MULT __BITS(18,8)

sys/arch/arm/ti/omap3_platform.c

123

#define OMAP4_DPLL_DIV __BITS(6,0)

sys/arch/arm/ti/omap3_platform.c

124

#define OMAP4_DPLL_CLKOUT_DIV __BITS(4,0)

sys/arch/arm/ti/omap4_prcm.c

52

#define CLKCTRL_MODULEMODE __BITS(1,0)

sys/arch/arm/ti/omap4_prcm.c

57

#define CLKCTRL_IDLEST __BITS(17,16)

sys/arch/arm/ti/ti_dpll_clock.c

42

#define DPLL_MULT __BITS(18,8)

sys/arch/arm/ti/ti_dpll_clock.c

43

#define DPLL_DIV __BITS(6,0)

sys/arch/arm/ti/ti_dpll_clock.c

44

#define DPLL_CLKOUT_DIV __BITS(4,0)

sys/arch/arm/ti/ti_dpll_clock.c

49

#define AM3_DPLL_EN __BITS(2,0)

sys/arch/arm/ti/ti_dpll_clock.c

55

#define OMAP3_EN_MPU_DPLL __BITS(2,0)

sys/arch/arm/ti/ti_dpll_clock.c

59

#define OMAP3_CORE_DPLL_CLKOUT_DIV __BITS(31,27)

sys/arch/arm/ti/ti_dpll_clock.c

60

#define OMAP3_CORE_DPLL_MULT __BITS(26,16)

sys/arch/arm/ti/ti_dpll_clock.c

61

#define OMAP3_CORE_DPLL_DIV __BITS(14,8)

sys/arch/arm/ti/ti_edma.h

109

#define EDMA_PARAM_OPT_PRIVID __BITS(27,24)

sys/arch/arm/ti/ti_edma.h

114

#define EDMA_PARAM_OPT_TCC __BITS(17,12)

sys/arch/arm/ti/ti_edma.h

116

#define EDMA_PARAM_OPT_FWID __BITS(10,8)

sys/arch/arm/ti/ti_edma.h

123

#define EDMA_PARAM_CNT_BCNT __BITS(31,16)

sys/arch/arm/ti/ti_edma.h

124

#define EDMA_PARAM_CNT_ACNT __BITS(15,0)

sys/arch/arm/ti/ti_edma.h

127

#define EDMA_PARAM_BIDX_DSTBIDX __BITS(31,16)

sys/arch/arm/ti/ti_edma.h

128

#define EDMA_PARAM_BIDX_SRCBIDX __BITS(15,0)

sys/arch/arm/ti/ti_edma.h

130

#define EDMA_PARAM_LNK_BCNTRLD __BITS(31,16)

sys/arch/arm/ti/ti_edma.h

131

#define EDMA_PARAM_LNK_LINK __BITS(15,0)

sys/arch/arm/ti/ti_edma.h

133

#define EDMA_PARAM_CIDX_DSTCIDX __BITS(31,16)

sys/arch/arm/ti/ti_edma.h

134

#define EDMA_PARAM_CIDX_SRCCIDX __BITS(15,0)

sys/arch/arm/ti/ti_edma.h

136

#define EDMA_PARAM_CCNT_CCNT __BITS(15,0)

sys/arch/arm/ti/ti_edma.h

35

#define EDMA_CCCFG_NUM_REGN __BITS(21,20)

sys/arch/arm/ti/ti_edma.h

36

#define EDMA_CCCFG_NUM_EVQUEUE __BITS(18,16)

sys/arch/arm/ti/ti_edma.h

37

#define EDMA_CCCFG_NUM_PAENTRY __BITS(14,12)

sys/arch/arm/ti/ti_edma.h

38

#define EDMA_CCCFG_NUM_INTCH __BITS(10,8)

sys/arch/arm/ti/ti_edma.h

39

#define EDMA_CCCFG_NUM_QDMACH __BITS(6,4)

sys/arch/arm/ti/ti_edma.h

40

#define EDMA_CCCFG_NUM_DMACH __BITS(2,0)

sys/arch/arm/ti/ti_edma.h

43

#define EDMA_DCHMAP_PAENTRY __BITS(13,5)

sys/arch/arm/ti/ti_omapmusb.c

50

#define OTG_SYSCONFIG_MIDLEMODE __BITS(13,12)

sys/arch/arm/ti/ti_omapmusb.c

51

#define OTG_SYSCONFIG_SIDLEMODE __BITS(4,3)

sys/arch/arm/ti/ti_rngreg.h

38

#define TRNG_CONTROL_STARTUP_CYCLES __BITS(31,16)

sys/arch/arm/ti/ti_rngreg.h

41

#define TRNG_CONFIG_MAX_REFILL __BITS(31,16)

sys/arch/arm/ti/ti_rngreg.h

42

#define TRNG_CONFIG_MIN_REFILL __BITS(7,0)

sys/arch/arm/ti/ti_usb.c

49

#define UHH_SYSCONFIG_IDLEMODE_MASK __BITS(3, 2)

sys/arch/arm/ti/ti_usb.c

51

#define UHH_SYSCONFIG_STANDBYMODE_MASK __BITS(5, 4)

sys/arch/arm/ti/ti_usb.c

54

#define UHH_SYSCONFIG_MIDLEMODE_MASK __BITS(13,12)

sys/arch/arm/ti/ti_usb.c

57

#define UHH_SYSCONFIG_SIDLEMODE_MASK __BITS(4,3)

sys/arch/arm/ti/ti_usb.c

66

#define UHH_HOSTCONFIG_PN_MODE_MASK(p) __BITS(1 + 16 + 2 * (p), 16 + 2 * (p))

sys/arch/arm/ti/ti_wdt.c

51

#define WCLR_PTV __BITS(4,2)

sys/arch/arm/ti/ti_wdt.c

62

#define WWPS_W_PEND_MASK __BITS(5,0)

sys/arch/arm/vexpress/vexpress_platform.c

76

#define SYS_CFGCTRL_DCC __BITS(29,26)

sys/arch/arm/vexpress/vexpress_platform.c

77

#define SYS_CFGCTRL_FUNCTION __BITS(25,20)

sys/arch/arm/vexpress/vexpress_platform.c

80

#define SYS_CFGCTRL_SITE __BITS(17,16)

sys/arch/arm/vexpress/vexpress_platform.c

81

#define SYS_CFGCTRL_POSITION __BITS(15,12)

sys/arch/arm/vexpress/vexpress_platform.c

82

#define SYS_CFGCTRL_DEVICE __BITS(11,0)

sys/arch/arm/vexpress/vexpress_sysreg.c

44

#define SYS_CFGCTRL_FUNCTION __BITS(25,20)

sys/arch/arm/vexpress/vexpress_sysreg.c

47

#define SYS_CFGCTRL_SITE __BITS(17,16)

sys/arch/arm/vfp/vfp_init.c

256

const uint32_t nsacr_vfp = __BITS(VFP_COPROC,VFP_COPROC2);

sys/arch/arm/xilinx/zynq7000_clkc.c

49

#define PLL_FDIV __BITS(18,12)

sys/arch/arm/xilinx/zynq7000_clkc.c

55

#define ARM_CLK_CTRL_DIVISOR __BITS(13,8)

sys/arch/arm/xilinx/zynq7000_clkc.c

66

#define CLK_CTRL_DIVISOR __BITS(13,8)

sys/arch/arm/xilinx/zynq7000_clkc.c

67

#define CLK_CTRL_SRCSEL __BITS(5,4)

sys/arch/arm/xilinx/zynq_uartreg.h

43

#define MR_CHMODE __BITS(9, 8)

sys/arch/arm/xilinx/zynq_uartreg.h

44

#define MR_NBSTOP __BITS(7, 6)

sys/arch/arm/xilinx/zynq_uartreg.h

48

#define MR_PAR __BITS(5, 3)

sys/arch/arm/xilinx/zynq_uartreg.h

54

#define MR_CHRL __BITS(2, 1)

sys/arch/arm/xilinx/zynq_uartvar.h

34

#define ERROR_BITS __BITS(31, 16)

sys/arch/arm/xilinx/zynq_usbreg.h

108

#define PORTSC_PSPD __BITS(26,27) /* port speed (RO) */

sys/arch/arm/xilinx/zynq_usbreg.h

32

#define ZYNQUSB_ID_ID __BITS(5,0)

sys/arch/arm/xilinx/zynq_usbreg.h

33

#define ZYNQUSB_ID_NID __BITS(13,8)

sys/arch/arm/xilinx/zynq_usbreg.h

34

#define ZYNQUSB_ID_TAG __BITS(20,16)

sys/arch/arm/xilinx/zynq_usbreg.h

35

#define ZYNQUSB_ID_REVISION __BITS(24,21)

sys/arch/arm/xilinx/zynq_usbreg.h

36

#define ZYNQUSB_ID_VERSION __BITS(28,25)

sys/arch/arm/xilinx/zynq_usbreg.h

37

#define ZYNQUSB_ID_CIVERSION __BITS(31,29)

sys/arch/arm/xilinx/zynq_usbreg.h

41

#define HWHOST_NPORT __BITS(3,1)

sys/arch/arm/xilinx/zynq_usbreg.h

44

#define HWDEVICE_DEVEP __BITS(5,1)

sys/arch/arm/xilinx/zynq_usbreg.h

55

#define ULPI_PORT __BITS(26,24)

sys/arch/arm/xilinx/zynq_usbreg.h

56

#define ULPI_ADDR __BITS(23,16)

sys/arch/arm/xilinx/zynq_usbreg.h

57

#define ULPI_DATRD __BITS(15,8)

sys/arch/arm/xilinx/zynq_usbreg.h

58

#define ULPI_DATWR __BITS(7,0)

sys/arch/arm/xilinx/zynq_usbreg.h

91

#define USBMODE_CM __BITS(1,0)

sys/arch/arm/xilinx/zynq_usbreg.h

99

#define PORTSC_PTS __BITS(31,30)

sys/arch/arm/xilinx/zynq_xadc.c

58

#define CFG_TCKRATE __BITS(9,8)

sys/arch/arm/xilinx/zynq_xadc.c

82

#define CONF1_SEQ __BITS(15,12)

sys/arch/arm/xilinx/zynq_xadc.c

86

#define SEQ0_ALL __BITS(5,14)

sys/arch/arm/xilinx/zynq_xadc.c

90

#define XADC_COMMAND_CMD __BITS(29,26)

sys/arch/arm/xilinx/zynq_xadc.c

91

#define XADC_COMMAND_DRP_ADDR __BITS(25,16)

sys/arch/arm/xilinx/zynq_xadc.c

92

#define XADC_COMMAND_DRP_DATA __BITS(15,0)

sys/arch/evbarm/rpi/vcprop.h

223

#define VCPROP_REV_PCBREV __BITS(3,0)

sys/arch/evbarm/rpi/vcprop.h

224

#define VCPROP_REV_MODEL __BITS(11,4)

sys/arch/evbarm/rpi/vcprop.h

240

#define VCPROP_REV_PROCESSOR __BITS(15,12)

sys/arch/evbarm/rpi/vcprop.h

245

#define VCPROP_REV_MANUF __BITS(19,16)

sys/arch/evbarm/rpi/vcprop.h

251

#define VCPROP_REV_MEMSIZE __BITS(22,20)

sys/arch/evbarm/rpi/vcprop.h

258

#define VCPROP_REV_WARRANTY __BITS(25,24)

sys/arch/evbmips/rmixl/machdep.c

423

rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0));

sys/arch/evbppc/include/wii.h

130

#define VIDIM_Y __BITS(5,3)

sys/arch/evbppc/include/wii.h

131

#define VIDIM_C __BITS(2,0)

sys/arch/evbppc/include/wii.h

157

#define HWVER_MASK __BITS(7,4)

sys/arch/evbppc/include/wii.h

158

#define HWREV_MASK __BITS(3,0)

sys/arch/evbppc/include/wiiu.h

77

#define LT_CHIPREVID_MAGIC __BITS(31, 16)

sys/arch/evbppc/include/wiiu.h

79

#define LT_CHIPREVID_VERHI __BITS(7, 4)

sys/arch/evbppc/include/wiiu.h

80

#define LT_CHIPREVID_VERLO __BITS(3, 0)

sys/arch/evbppc/mpc85xx/cadmusreg.h

43

#define CM_VER_ID __BITS(4,7)

sys/arch/evbppc/mpc85xx/cadmusreg.h

45

#define CM_VER_REV __BITS(0,3)

sys/arch/evbppc/mpc85xx/cadmusreg.h

48

#define CM_CSR_USER __BITS(6,7)

sys/arch/evbppc/mpc85xx/cadmusreg.h

50

#define CM_CSR_EPHY __BITS(1,3)

sys/arch/evbppc/mpc85xx/cadmusreg.h

68

#define CM_PCI_PSPEED __BITS(2,3) /* detected PCI speed */

sys/arch/evbppc/mpc85xx/pixisreg.h

37

#define PX_VER_ID __BITS(4,7)

sys/arch/evbppc/mpc85xx/pixisreg.h

39

#define PX_VER_REV __BITS(0,3)

sys/arch/evbppc/mpc85xx/pixisreg.h

44

#define PX_CSR_EVES __BITS(2,3)

sys/arch/evbppc/mpc85xx/pixisreg.h

62

#define PX_SPD_SYSCLK __BITS(0,2)

sys/arch/evbppc/mpc85xx/pixisreg.h

72

#define PX_SPD_DDRCLK __BITS(3,5)

sys/arch/evbppc/nintendo/dev/avenc.c

54

#define AVENC_VOLUME_RIGHT __BITS(15,8)

sys/arch/evbppc/nintendo/dev/avenc.c

55

#define AVENC_VOLUME_LEFT __BITS(7,0)

sys/arch/evbppc/nintendo/dev/bwdsp.c

54

#define DSP_DMA_CONTROL_LENGTH_NUM_CLS __BITS(14,0)

sys/arch/evbppc/nintendo/dev/exireg.h

35

#define EXI_CSR_CS __BITS(9,7)

sys/arch/evbppc/nintendo/dev/exireg.h

36

#define EXI_CSR_CLK __BITS(6,4)

sys/arch/evbppc/nintendo/dev/exireg.h

40

#define EXI_CR_TLEN __BITS(5,4)

sys/arch/evbppc/nintendo/dev/exireg.h

41

#define EXI_CR_RW __BITS(3,2)

sys/arch/evbppc/nintendo/dev/hwaes.c

65

#define AES_CTRL_BLOCKS __BITS(11, 0)

sys/arch/evbppc/nintendo/dev/si.c

57

#define SIPOLL_X __BITS(25, 16)

sys/arch/evbppc/nintendo/dev/si.c

58

#define SIPOLL_Y __BITS(15, 8)

sys/arch/evbppc/nintendo/dev/si.c

65

#define SICOMCSR_OUTLNGTH __BITS(22, 16)

sys/arch/evbppc/nintendo/dev/si.c

66

#define SICOMCSR_INLNGTH __BITS(14, 8)

sys/arch/evbppc/nintendo/dev/vireg.h

100

#define VI_TFBR_FBB __BITS(23,0)

sys/arch/evbppc/nintendo/dev/vireg.h

105

#define VI_BFBL_XOF __BITS(27,24)

sys/arch/evbppc/nintendo/dev/vireg.h

106

#define VI_BFBL_FBB __BITS(23,0)

sys/arch/evbppc/nintendo/dev/vireg.h

110

#define VI_BFBR_FBB __BITS(23,0)

sys/arch/evbppc/nintendo/dev/vireg.h

114

#define VI_DPV_VCT __BITS(10,0)

sys/arch/evbppc/nintendo/dev/vireg.h

118

#define VI_DPH_HCT __BITS(10,0)

sys/arch/evbppc/nintendo/dev/vireg.h

127

#define VI_DI_VCT __BITS(25,16)

sys/arch/evbppc/nintendo/dev/vireg.h

128

#define VI_DI_HCT __BITS(9,0)

sys/arch/evbppc/nintendo/dev/vireg.h

134

#define VI_DL_VCT __BITS(26,16)

sys/arch/evbppc/nintendo/dev/vireg.h

135

#define VI_DL_HCT __BITS(10,0)

sys/arch/evbppc/nintendo/dev/vireg.h

139

#define VI_PICCONF_READS __BITS(15,8)

sys/arch/evbppc/nintendo/dev/vireg.h

140

#define VI_PICCONF_STRIDES __BITS(7,0)

sys/arch/evbppc/nintendo/dev/vireg.h

145

#define VI_HSR_STP __BITS(8,0)

sys/arch/evbppc/nintendo/dev/vireg.h

172

#define VI_HSCALINGW_WIDTH __BITS(9,0)

sys/arch/evbppc/nintendo/dev/vireg.h

177

#define VI_HBE_HBE656 __BITS(9,0)

sys/arch/evbppc/nintendo/dev/vireg.h

181

#define VI_HBS_HBS656 __BITS(9,0)

sys/arch/evbppc/nintendo/dev/vireg.h

39

#define VI_VTR_ACV __BITS(13,4)

sys/arch/evbppc/nintendo/dev/vireg.h

40

#define VI_VTR_EQU __BITS(3,0)

sys/arch/evbppc/nintendo/dev/vireg.h

44

#define VI_DCR_FMT __BITS(9,8)

sys/arch/evbppc/nintendo/dev/vireg.h

49

#define VI_DCR_LE1 __BITS(7,6)

sys/arch/evbppc/nintendo/dev/vireg.h

50

#define VI_DCR_LE0 __BITS(5,4)

sys/arch/evbppc/nintendo/dev/vireg.h

58

#define VI_HTR0_HCS __BITS(30,24)

sys/arch/evbppc/nintendo/dev/vireg.h

59

#define VI_HTR0_HCE __BITS(22,16)

sys/arch/evbppc/nintendo/dev/vireg.h

60

#define VI_HTR0_HLW __BITS(8,0)

sys/arch/evbppc/nintendo/dev/vireg.h

64

#define VI_HTR1_HBS __BITS(26,17)

sys/arch/evbppc/nintendo/dev/vireg.h

65

#define VI_HTR1_HBE __BITS(16,7)

sys/arch/evbppc/nintendo/dev/vireg.h

66

#define VI_HTR1_HSY __BITS(6,0)

sys/arch/evbppc/nintendo/dev/vireg.h

70

#define VI_VTO_PSB __BITS(25,16)

sys/arch/evbppc/nintendo/dev/vireg.h

71

#define VI_VTO_PRB __BITS(9,0)

sys/arch/evbppc/nintendo/dev/vireg.h

75

#define VI_VTE_PSB __BITS(25,16)

sys/arch/evbppc/nintendo/dev/vireg.h

76

#define VI_VTE_PRB __BITS(9,0)

sys/arch/evbppc/nintendo/dev/vireg.h

80

#define VI_BBOI_BE3 __BITS(31,21)

sys/arch/evbppc/nintendo/dev/vireg.h

81

#define VI_BBOI_BS3 __BITS(20,16)

sys/arch/evbppc/nintendo/dev/vireg.h

82

#define VI_BBOI_BE1 __BITS(15,5)

sys/arch/evbppc/nintendo/dev/vireg.h

83

#define VI_BBOI_BS1 __BITS(4,0)

sys/arch/evbppc/nintendo/dev/vireg.h

87

#define VI_BBEI_BE4 __BITS(31,21)

sys/arch/evbppc/nintendo/dev/vireg.h

88

#define VI_BBEI_BS4 __BITS(20,16)

sys/arch/evbppc/nintendo/dev/vireg.h

89

#define VI_BBEI_BE2 __BITS(15,5)

sys/arch/evbppc/nintendo/dev/vireg.h

90

#define VI_BBEI_BS2 __BITS(4,0)

sys/arch/evbppc/nintendo/dev/vireg.h

95

#define VI_TFBL_XOF __BITS(27,24)

sys/arch/evbppc/nintendo/dev/vireg.h

96

#define VI_TFBL_FBB __BITS(23,0)

sys/arch/evbppc/nintendo/dev/wiiufb.c

67

#define DGRPH_SWAP_ENDIAN_SWAP __BITS(1, 0)

sys/arch/evbppc/nintendo/dev/wiiufb.c

73

#define DCUR_CONTROL_MODE __BITS(9, 8)

sys/arch/evbppc/stand/wii/gecko.c

40

#define EXI_CSR_CS __BITS(9,7)

sys/arch/evbppc/stand/wii/gecko.c

41

#define EXI_CSR_CLK __BITS(6,4)

sys/arch/evbppc/stand/wii/gecko.c

43

#define EXI_CR_TLEN __BITS(5,4)

sys/arch/evbppc/stand/wii/gecko.c

44

#define EXI_CR_RW __BITS(3,2)

sys/arch/evbppc/stand/wii/miniipc.c

42

#define HW_IPC_PPCMSG_INDEX_OUT_MASK __BITS(31, 16)

sys/arch/evbppc/stand/wii/miniipc.c

43

#define HW_IPC_PPCMSG_INDEX_IN_MASK __BITS(15, 0)

sys/arch/evbppc/stand/wii/miniipc.c

48

#define HW_IPC_ARMMSG_INDEX_OUT_MASK __BITS(15, 0)

sys/arch/hppa/hppa/db_disasm.c

868

#define Ima5(i) (Ima5S(i) ? Ima5M(i) | (int)(~__BITS(3,0)) : Ima5M(i))

sys/arch/hppa/hppa/db_disasm.c

870

#define Imc5(i) (Imc5S(i) ? Imc5M(i) | (int)(~__BITS(3,0)) : Imc5M(i))

sys/arch/hppa/hppa/db_disasm.c

872

#define Disp(i) (DispS(i) ? DispM(i) | (int)(~__BITS(12,0)) : DispM(i))

sys/arch/hppa/hppa/db_disasm.c

877

#define Im11(i) (Im11S(i) ? Im11M(i) | (int)(~__BITS(9,0)) : Im11M(i))

sys/arch/hppa/hppa/db_disasm.c

880

/* branch displacement (bytes) */ | (int)(~__BITS(15,0)) \

sys/arch/hppa/hppa/db_disasm.c

884

/* compare/branch disp (bytes) */ | (int)(~__BITS(10,0)) \

sys/arch/hppa/hppa/trap.c

480

#define __PABITS(x, y) __BITS(31 - (x), 31 - (y))

sys/arch/hppa/hppa/trap.c

508

#define PLMASK __BITS(1, 0)

sys/arch/i386/pci/elan520reg.h

102

#define MMCR_HBMSTIRQCTL_RSVD0 __BITS(15, 14)

sys/arch/i386/pci/elan520reg.h

121

#define MMCR_HBMSTIRQCTL_RSVD1 __BITS(7, 6)

sys/arch/i386/pci/elan520reg.h

140

#define MMCR_HBTGTIRQCTL_RSVD0 __BITS(15, 11)

sys/arch/i386/pci/elan520reg.h

150

#define MMCR_HBTGTIRQCTL_RSVD1 __BITS(7, 3)

sys/arch/i386/pci/elan520reg.h

166

#define MMCR_HBMSTIRQSTA_RSVD0 __BITS(15, 12)

sys/arch/i386/pci/elan520reg.h

167

#define MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID __BITS(11, 8)

sys/arch/i386/pci/elan520reg.h

168

#define MMCR_HBMSTIRQSTA_RSVD1 __BITS(7, 6)

sys/arch/i386/pci/elan520reg.h

187

#define MMCR_HBTGTIRQSTA_RSVD0 __BITS(15, 12)

sys/arch/i386/pci/elan520reg.h

189

#define MMCR_HBTGTIRQSTA_T_IRQ_ID __BITS(11, 8)

sys/arch/i386/pci/elan520reg.h

190

#define MMCR_HBTGTIRQSTA_RSVD1 __BITS(7, 3)

sys/arch/i386/pci/elan520reg.h

204

#define MMCR_PCIHOSTMAP_PCI_IRQ_MAP __BITS(4, 0)

sys/arch/i386/pci/elan520reg.h

210

#define MMCR_PICICR_RSVD0 __BITS(5, 3)

sys/arch/i386/pci/elan520reg.h

220

#define MMCR_WPVMAP_RSVD0 __BITS(7, 5)

sys/arch/i386/pci/elan520reg.h

224

#define MMCR_WPVMAP_INT_MAP __BITS(4, 0)

sys/arch/i386/pci/elan520reg.h

235

#define MMCR_WPVSTA_WPV_RSVD0 __BITS(14, 10)

sys/arch/i386/pci/elan520reg.h

236

#define MMCR_WPVSTA_WPV_MSTR __BITS(9, 8)

sys/arch/i386/pci/elan520reg.h

241

#define MMCR_WPVSTA_WPV_RSVD1 __BITS(7, 4)

sys/arch/i386/pci/elan520reg.h

242

#define MMCR_WPVSTA_WPV_WINDOW __BITS(3, 0)

sys/arch/i386/pci/elan520reg.h

245

#define MMCR_PAR_TARGET __BITS(31, 29)

sys/arch/i386/pci/elan520reg.h

254

#define MMCR_PAR_ATTR __BITS(28, 26)

sys/arch/i386/pci/elan520reg.h

259

#define MMCR_PAR_SZ_ST_ADR __BITS(24, 0)

sys/arch/i386/pci/elan520reg.h

260

#define MMCR_PAR_4KB_SZ __BITS(24, 18)

sys/arch/i386/pci/elan520reg.h

261

#define MMCR_PAR_4KB_ST_ADR __BITS(17, 0)

sys/arch/i386/pci/elan520reg.h

262

#define MMCR_PAR_64KB_SZ __BITS(24, 14)

sys/arch/i386/pci/elan520reg.h

263

#define MMCR_PAR_64KB_ST_ADR __BITS(13, 0)

sys/arch/i386/pci/elan520reg.h

264

#define MMCR_PAR_IO_SZ __BITS(24, 16)

sys/arch/i386/pci/elan520reg.h

265

#define MMCR_PAR_IO_ST_ADR __BITS(15, 0)

sys/arch/i386/pci/elan520reg.h

66

#define MMCR_DBCTL_WB_WM_MASK __BITS(3,2) /* write buffer watermark */

sys/arch/i386/pci/elan520reg.h

76

#define MMCR_HBCTL_T_DLYTR_ENB_MASK __BITS(9,8)

sys/arch/i386/pci/elan520reg.h

95

#define MMCR_PCIARBSTA_GNT_TO_ID __BITS(3, 0)

sys/arch/i386/pci/geodereg.h

54

#define SC1100_WDCNFG_RESERVED __BITS(15,9) /* write as read */

sys/arch/i386/pci/geodereg.h

66

#define SC1100_WDCNFG_WDTYPE2_MASK __BITS(7,6)

sys/arch/i386/pci/geodereg.h

67

#define SC1100_WDCNFG_WDTYPE1_MASK __BITS(5,4)

sys/arch/i386/pci/geodereg.h

84

#define SC1100_WDCNFG_WDPRES_MASK __BITS(3,0)

sys/arch/m68k/include/mmu_30.h

74

#define TT30_LAB __BITS(31,24) /* Logical Address Base */

sys/arch/m68k/include/mmu_30.h

75

#define TT30_LAM __BITS(16,23) /* Logical Address Mask */

sys/arch/m68k/include/mmu_30.h

80

#define TT30_FCBASE __BITS(4,6) /* Function Code base */

sys/arch/m68k/include/mmu_30.h

81

#define TT30_FCMASK __BITS(0,2) /* Function Code bits to ignore */

sys/arch/m68k/include/mmu_40.h

101

#define UTE40_PTA __BITS(9,31) /* Pointer Table Address (L1 PTE) */

sys/arch/m68k/include/mmu_40.h

103

#define UTE40_PGTA __BITS(8 - (13 - PAGE_SHIFT),31)

sys/arch/m68k/include/mmu_40.h

106

#define UTE40_UDT __BITS(0,1) /* Upper Descriptor Type */

sys/arch/m68k/include/mmu_40.h

130

#define PTE40_PGA __BITS(PAGE_SHIFT,31) /* Page Physical Address */

sys/arch/m68k/include/mmu_40.h

137

#define PTE40_CM __BITS(5,6) /* Cache Mode */

sys/arch/m68k/include/mmu_40.h

145

#define PTE40_PDT __BITS(0,1) /* Page Descriptor Type */

sys/arch/m68k/include/mmu_40.h

184

#define TTR40_LAB __BITS(24,31) /* logical address base */

sys/arch/m68k/include/mmu_40.h

185

#define TTR40_LAM __BITS(16,23) /* logical address mask */

sys/arch/m68k/include/mmu_40.h

187

#define TTR40_SFIELD __BITS(13,14) /* Supervisor Mode field (see below) */

sys/arch/m68k/include/mmu_40.h

82

#define LA40_L1_MASK (__BITS(0,(LA40_L1_NBITS - 1)) << LA40_L1_SHIFT)

sys/arch/m68k/include/mmu_40.h

83

#define LA40_L2_MASK (__BITS(0,(LA40_L2_NBITS - 1)) << LA40_L2_SHIFT)

sys/arch/m68k/include/mmu_40.h

84

#define LA40_L3_MASK (__BITS(0,(LA40_L3_NBITS - 1)) << LA40_L3_SHIFT)

sys/arch/m68k/include/mmu_51.h

100

#define DTE51_WAL __BITS(10,12) /* L: Write Access Level */

sys/arch/m68k/include/mmu_51.h

142

#define PTE51_ADDR __BITS(8,31) /* page address mask */

sys/arch/m68k/include/mmu_51.h

143

#define PTE51_RAL __BITS(13,15) /* L: Read Access Level */

sys/arch/m68k/include/mmu_51.h

144

#define PTE51_WAL __BITS(10,12) /* L: Write Access Level */

sys/arch/m68k/include/mmu_51.h

208

#define PCSR51_TA __BITS(0,2) /* Task Alias (not '030) */

sys/arch/m68k/include/mmu_51.h

216

#define TCR51_PS __BITS(20,23) /* Page Size (see below) */

sys/arch/m68k/include/mmu_51.h

217

#define TCR51_IS __BITS(16,19) /* Initial Shift */

sys/arch/m68k/include/mmu_51.h

218

#define TCR51_TIA __BITS(12,15) /* Table A Index bits */

sys/arch/m68k/include/mmu_51.h

219

#define TCR51_TIB __BITS(8,11) /* Table B Index bits */

sys/arch/m68k/include/mmu_51.h

220

#define TCR51_TIC __BITS(4,7) /* Table C Index bits */

sys/arch/m68k/include/mmu_51.h

221

#define TCR51_TID __BITS(0,3) /* Table D Index bits */

sys/arch/m68k/include/mmu_51.h

240

#define CAL51_AL __BITS(5,7)

sys/arch/m68k/include/mmu_51.h

250

#define AC51_ALC __BITS(4,5) /* Access Level Control */

sys/arch/m68k/include/mmu_51.h

251

#define AC51_MDS __BITS(0,1) /* Module Descriptor Size */

sys/arch/m68k/include/mmu_51.h

265

#define PSR51_N __BITS(0,2) /* Number of levels */

sys/arch/m68k/include/mmu_51.h

69

#define DT51_TYPE __BITS(0,1)

sys/arch/m68k/include/mmu_51.h

96

#define DTE51_ADDR __BITS(4,31) /* table address mask */

sys/arch/m68k/include/mmu_51.h

98

#define DTE51_LIMIT __BITS(16,30) /* L: Index limit */

sys/arch/m68k/include/mmu_51.h

99

#define DTE51_RAL __BITS(13,15) /* L: Read Access Level */

sys/arch/m68k/include/pcr.h

39

#define PCR_mbz __BITS(2,6) /* reserved - must be zero */

sys/arch/m68k/include/pcr.h

41

#define PCR_REVMASK __BITS(8,15) /* revision number */

sys/arch/m68k/include/pcr.h

42

#define PCR_IDMASK __BITS(16,31)/* identification */

sys/arch/m68k/include/pmap_68k.h

293

#define LA2L_L1_MASK (__BITS(0,(LA2L_L1_NBITS - 1)) << LA2L_L1_SHIFT)

sys/arch/m68k/include/pmap_68k.h

294

#define LA2L_L2_MASK (__BITS(0,(LA2L_L2_NBITS - 1)) << LA2L_L2_SHIFT)

sys/arch/m68k/include/pmap_68k.h

355

#define PVH_UM_MASK __BITS(0,1)

sys/arch/m68k/include/pte_coldfire.h

43

#define MMUTR_VA __BITS(31,10) // Virtual Address

sys/arch/m68k/include/pte_coldfire.h

44

#define MMUTR_ID __BITS(9,2) // ASID

sys/arch/m68k/include/pte_coldfire.h

48

#define MMUDR_PA __BITS(31,10) // Physical Address

sys/arch/m68k/include/pte_coldfire.h

49

#define MMUDR_SZ __BITS(9,8) // Entry Size

sys/arch/m68k/include/pte_coldfire.h

54

#define MMUDR_CM __BITS(7,6) // Cache Mode

sys/arch/macppc/dev/ofw_i2c_machdep.c

51

#define OFW_I2C_ADDRESS_MASK __BITS(1,7)

sys/arch/mips/adm5120/adm5120_extio.c

320

if (gpio_pin_map(sc->sc_gpio, 0, __BITS(0, 4), &sc->sc_pm) != 0) {

sys/arch/mips/adm5120/dev/admpci.c

101

#define ADMPCI_TAG_BUS_MASK __BITS(23, 16)

sys/arch/mips/adm5120/dev/admpci.c

105

#define ADMPCI_TAG_DEVICE_MASK __BITS(15, 11)

sys/arch/mips/adm5120/dev/admpci.c

106

#define ADMPCI_TAG_DEVICE_SUBMASK __BITS(15, 12)

sys/arch/mips/adm5120/dev/admpci.c

108

#define ADMPCI_TAG_FUNCTION_MASK __BITS(10, 8)

sys/arch/mips/adm5120/dev/admpci.c

109

#define ADMPCI_TAG_REGISTER_MASK __BITS(7, 0)

sys/arch/mips/adm5120/dev/if_admswreg.h

74

#define ADMSW_SW_RES_SWR __BITS(31, 0)

sys/arch/mips/adm5120/dev/if_admswreg.h

78

#define ADMSW_INTR_RSVD __BITS(31, 25)

sys/arch/mips/adm5120/include/adm5120reg.h

145

#define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set:

sys/arch/mips/adm5120/include/adm5120reg.h

151

#define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer:

sys/arch/mips/adm5120/include/adm5120reg.h

158

#define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */

sys/arch/mips/adm5120/include/adm5120reg.h

159

#define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable,

sys/arch/mips/adm5120/include/adm5120reg.h

163

#define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */

sys/arch/mips/adm5120/include/adm5120reg.h

164

#define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */

sys/arch/mips/adm5120/include/adm5120reg.h

234

#define ADM5120_MPMC_SEW_RSVD __BITS(31, 10)

sys/arch/mips/adm5120/include/adm5120reg.h

235

#define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after

sys/arch/mips/adm5120/include/adm5120reg.h

241

#define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21)

sys/arch/mips/adm5120/include/adm5120reg.h

244

#define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9)

sys/arch/mips/adm5120/include/adm5120reg.h

258

#define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4)

sys/arch/mips/adm5120/include/adm5120reg.h

264

#define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */

sys/arch/mips/adm5120/include/adm5120reg.h

271

#define ADM5120_MPMC_SWW_RSVD __BITS(31, 4)

sys/arch/mips/adm5120/include/adm5120reg.h

272

#define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles

sys/arch/mips/adm5120/include/adm5120reg.h

279

#define ADM5120_MPMC_SWO_RSVD __BITS(31, 4)

sys/arch/mips/adm5120/include/adm5120reg.h

280

#define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles

sys/arch/mips/adm5120/include/adm5120reg.h

287

#define ADM5120_MPMC_SWR_RSVD __BITS(31, 5)

sys/arch/mips/adm5120/include/adm5120reg.h

288

#define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for

sys/arch/mips/adm5120/include/adm5120reg.h

295

#define ADM5120_MPMC_SWP_RSVD __BITS(31, 5)

sys/arch/mips/adm5120/include/adm5120reg.h

296

#define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for

sys/arch/mips/adm5120/include/adm5120reg.h

303

#define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5)

sys/arch/mips/adm5120/include/adm5120reg.h

304

#define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after

sys/arch/mips/adm5120/include/adm5120reg.h

310

#define ADM5120_MPMC_SWT_RSVD __BITS(31, 4)

sys/arch/mips/adm5120/include/adm5120reg.h

311

#define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time,

sys/arch/mips/atheros/dev/ehci_arbus.c

59

#define USBMODE_CM __BITS(0,1) /* Controller Mode */

sys/arch/mips/atheros/include/ar5312reg.h

135

#define AR5312_CLOCKCTL_PREDIVIDE __BITS(4,5)

sys/arch/mips/atheros/include/ar5312reg.h

136

#define AR5312_CLOCKCTL_MULTIPLIER __BITS(8,12)

sys/arch/mips/atheros/include/ar5312reg.h

140

#define AR2313_CLOCKCTL_PREDIVIDE __BITS(12,13)

sys/arch/mips/atheros/include/ar5312reg.h

141

#define AR2313_CLOCKCTL_MULTIPLIER __BITS(16,20)

sys/arch/mips/atheros/include/ar5312reg.h

147

#define AR5312_ENABLE_WLAN1 __BITS(7,8) /* both DMA and PIO */

sys/arch/mips/atheros/include/ar5312reg.h

168

#define AR5312_MEM_CFG1_BANK0 __BITS(8,10)

sys/arch/mips/atheros/include/ar5312reg.h

169

#define AR5312_MEM_CFG1_BANK1 __BITS(12,15)

sys/arch/mips/atheros/include/ar5312reg.h

70

#define AR5312_FLASHCTL_IDCY __BITS(0,3) /* idle cycle turn */

sys/arch/mips/atheros/include/ar5312reg.h

71

#define AR5312_FLASHCTL_WST1 __BITS(5,9) /* wait state 1 */

sys/arch/mips/atheros/include/ar5312reg.h

73

#define AR5312_FLASHCTL_WST2 __BITS(11,15) /* wait state 1 */

sys/arch/mips/atheros/include/ar5312reg.h

74

#define AR5312_FLASHCTL_AC __BITS(16,18) /* addr chk */

sys/arch/mips/atheros/include/ar5312reg.h

88

#define AR5312_FLASHCTL_MW __BITS(28,29) /* mem width */

sys/arch/mips/atheros/include/ar5312reg.h

89

#define AR5312_FLASHCTL_AT __BITS(31,30) /* access type */

sys/arch/mips/atheros/include/ar5315reg.h

160

#define AR5315_MEM_CFG_DATA_WIDTH __BITS(13,14)

sys/arch/mips/atheros/include/ar5315reg.h

161

#define AR5315_MEM_CFG_COL_WIDTH __BITS(9,12)

sys/arch/mips/atheros/include/ar5315reg.h

162

#define AR5315_MEM_CFG_ROW_WIDTH __BITS(5,8)

sys/arch/mips/atheros/include/ar5315reg.h

165

#define AR531X_MEM_CFG1_BANK0 __BITS(8,10)

sys/arch/mips/atheros/include/ar5315reg.h

166

#define AR531X_MEM_CFG1_BANK1 __BITS(12,14)

sys/arch/mips/atheros/include/ar9344reg.h

100

#define AR7100_CPU_PLL_AHB_DIV __BITS(22,20)

sys/arch/mips/atheros/include/ar9344reg.h

101

#define AR7100_CPU_PLL_DDR_DIV_SEL __BITS(19,18)

sys/arch/mips/atheros/include/ar9344reg.h

102

#define AR7100_CPU_PLL_CPU_DIV_SEL __BITS(17,16)

sys/arch/mips/atheros/include/ar9344reg.h

103

#define AR7100_PLL_PLL_LOOP_BW __BITS(15,12)

sys/arch/mips/atheros/include/ar9344reg.h

104

#define AR7100_PLL_PLL_DIV_IN __BITS(11,10)

sys/arch/mips/atheros/include/ar9344reg.h

105

#define AR7100_PLL_PLL_DIV_OUT __BITS(9,8)

sys/arch/mips/atheros/include/ar9344reg.h

106

#define AR7100_PLL_PLL_FB __BITS(7,3)

sys/arch/mips/atheros/include/ar9344reg.h

112

#define AR9344_DDR_PLL_CONFIG_OUTDIV __BITS(23,25)

sys/arch/mips/atheros/include/ar9344reg.h

113

#define AR9344_DDR_PLL_CONFIG_RANGE __BITS(21,22)

sys/arch/mips/atheros/include/ar9344reg.h

114

#define AR9344_DDR_PLL_CONFIG_REFDIV __BITS(16,20)

sys/arch/mips/atheros/include/ar9344reg.h

115

#define AR9344_DDR_PLL_CONFIG_NINT __BITS(10,15)

sys/arch/mips/atheros/include/ar9344reg.h

116

#define AR9344_DDR_PLL_CONFIG_NFRAC __BITS(0,9)

sys/arch/mips/atheros/include/ar9344reg.h

123

#define AR9344_CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV __BITS(15,19)

sys/arch/mips/atheros/include/ar9344reg.h

124

#define AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV __BITS(10,14)

sys/arch/mips/atheros/include/ar9344reg.h

125

#define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV __BITS(5,9)

sys/arch/mips/atheros/include/ar9344reg.h

278

#define AR9344_MEM_CFG1_BANK0 __BITS(8,10)

sys/arch/mips/atheros/include/ar9344reg.h

279

#define AR9344_MEM_CFG1_BANK1 __BITS(12,14)

sys/arch/mips/atheros/include/ar9344reg.h

300

#define AR7100_PCI_LCL_CFG_CMD_BE __BITS(20,23)

sys/arch/mips/atheros/include/ar9344reg.h

301

#define AR7100_PCI_LCL_CFG_CMD_CMD __BITS(16,19)

sys/arch/mips/atheros/include/ar9344reg.h

304

#define AR7100_PCI_LCL_CFG_CMD_ADDRESS __BITS(0,11)

sys/arch/mips/atheros/include/ar9344reg.h

309

#define AR7100_PCI_CFG_CMD_BE __BITS(4,7)

sys/arch/mips/atheros/include/ar9344reg.h

310

#define AR7100_PCI_CFG_CMD_CMD __BITS(0,3)

sys/arch/mips/atheros/include/ar9344reg.h

323

#define AR9344_SPI_CONTROL_TSHSL_CNT __BITS(8,13)

sys/arch/mips/atheros/include/ar9344reg.h

326

#define AR9344_SPI_CONTROL_CLOCK_DIVIDER __BITS(0,5)

sys/arch/mips/atheros/include/ar9344reg.h

342

#define AR9344_SPI_SHIFT_CNT_SHIFT_COUNT __BITS(0,6)

sys/arch/mips/atheros/include/ar9344reg.h

92

#define AR9344_CPU_PLL_CONFIG_OUTDIV __BITS(19,21)

sys/arch/mips/atheros/include/ar9344reg.h

93

#define AR9344_CPU_PLL_CONFIG_RANGE __BITS(18,17)

sys/arch/mips/atheros/include/ar9344reg.h

94

#define AR9344_CPU_PLL_CONFIG_REFDIV __BITS(12,16)

sys/arch/mips/atheros/include/ar9344reg.h

95

#define AR9344_CPU_PLL_CONFIG_NINT __BITS(6,11)

sys/arch/mips/atheros/include/ar9344reg.h

96

#define AR9344_CPU_PLL_CONFIG_NFRAC __BITS(0,5)

sys/arch/mips/cavium/dev/octeon_faureg.h

43

#define POW_LOAD_INCVAL __BITS(35,14)

sys/arch/mips/cavium/dev/octeon_faureg.h

46

#define POW_LOAD_REG __BITS(10,0)

sys/arch/mips/cavium/dev/octeon_faureg.h

53

#define POW_IOBDMA_SIZE __BITS(12,11)

sys/arch/mips/cavium/dev/octeon_faureg.h

60

#define POW_STORE_REG __BITS(10,0)

sys/arch/mips/cavium/octeon_cpunode.c

188

new_insns[0] &= __BITS(31,16);

sys/arch/mips/cavium/octeon_cpunode.c

189

new_insns[1] &= __BITS(31,16);

sys/arch/mips/cavium/octeon_intr.c

173

.ih_arg = (void *)(uintptr_t)__BITS(15,0),

sys/arch/mips/cavium/octeon_intr.c

179

.ih_arg = (void *)(uintptr_t)__BITS(31,16),

sys/arch/mips/cavium/octeon_intr.c

303

mips3_sd(cpu->cpu_mbox_clr, __BITS(31,0));

sys/arch/mips/cavium/octeon_intr.c

545

KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,

sys/arch/mips/cavium/octeonreg.h

115

#define IOBDMA_SCRADDR __BITS(63,56)

sys/arch/mips/cavium/octeonreg.h

116

#define IOBDMA_LEN __BITS(55,48)

sys/arch/mips/cavium/octeonreg.h

120

#define IOBDMA_NODE __BITS(37,36) /* Octeon 3 only */

sys/arch/mips/cavium/octeonreg.h

121

#define IOBDMA_OFFSET __BITS(35,0)

sys/arch/mips/cavium/octeonreg.h

69

#define OCTEON_ADDR_MAJOR_DID __BITS(47,43)

sys/arch/mips/cavium/octeonreg.h

70

#define OCTEON_ADDR_SUB_DID __BITS(42,40)

sys/arch/mips/cavium/octeonreg.h

71

#define OCTEON_ADDR_NODE __BITS(37,36)

sys/arch/mips/cavium/octeonreg.h

72

#define OCTEON_ADDR_OFFSET __BITS(35,0)

sys/arch/mips/cavium/octeonreg.h

87

#define MIO_RST_BOOT_C_MUL __BITS(36,30)

sys/arch/mips/cavium/octeonreg.h

88

#define MIO_RST_BOOT_PNR_MUL __BITS(29,24)

sys/arch/mips/cavium/octeonreg.h

96

#define RST_BOOT_C_MUL __BITS(36,30)

sys/arch/mips/cavium/octeonreg.h

97

#define RST_BOOT_PNR_MUL __BITS(29,24)

sys/arch/mips/include/cpuregs.h

713

#define MIPS_FCSR_RM __BITS(1,0)

sys/arch/mips/include/cpuregs.h

718

#define MIPS_FCSR_FLAGS __BITS(6,2)

sys/arch/mips/include/cpuregs.h

724

#define MIPS_FCSR_ENABLES __BITS(11,7)

sys/arch/mips/include/cpuregs.h

730

#define MIPS_FCSR_CAUSE __BITS(17,12)

sys/arch/mips/include/cpuregs.h

740

#define MIPS_FCSR_FCC (MIPS_FPU_COND_BIT | __BITS(31,25))

sys/arch/mips/include/cpuregs.h

861

#define MIPS_WATCHLO_VADDR32 __BITS(31,3) /* 32-bit addr */

sys/arch/mips/include/cpuregs.h

862

#define MIPS_WATCHLO_VADDR64 __BITS(63,3) /* 64-bit addr */

sys/arch/mips/include/cpuregs.h

869

#define MIPS_WATCHHI_EAS __BITS(25,24) /* extended ASID */

sys/arch/mips/include/cpuregs.h

870

#define MIPS_WATCHHI_ASID __BITS(23,16)

sys/arch/mips/include/cpuregs.h

871

#define MIPS_WATCHHI_MASK __BITS(11,3)

sys/arch/mips/include/cpuregs.h

902

#define MIPS_EBASE_EXC_BASE __BITS(29, MIPS_EBASE_EXC_BASE_SHIFT)

sys/arch/mips/include/cpuregs.h

903

#define MIPS_EBASE_CPUNUM __BITS(9, 0)

sys/arch/mips/include/locore.h

885

#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)

sys/arch/mips/include/locore.h

889

#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3)

sys/arch/mips/include/locore.h

891

#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7)

sys/arch/mips/include/locore.h

906

#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11)

sys/arch/mips/include/mipsNN.h

309

#define MIPSNN_CFG4_IE __BITS(30,29)

sys/arch/mips/include/mipsNN.h

315

#define MIPSNN_CFG4_VTLB_SE __BITS(27,24)

sys/arch/mips/include/mipsNN.h

318

#define MIPSNN_CFG4_KSCR_EXIST __BITS(23,16)

sys/arch/mips/include/mipsNN.h

321

#define MIPSNN_CFG4_MMU_EXT_DEF __BITS(15,14)

sys/arch/mips/include/mipsNN.h

327

#define MIPSNN_CFG4_MMU_SIZE_EXT __BITS(7,0)

sys/arch/mips/include/mipsNN.h

330

#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE __BITS(10,8)

sys/arch/mips/include/mipsNN.h

339

#define MIPSNN_CFG4_FTLB_FTLB_WAYS __BITS(7,4)

sys/arch/mips/include/mipsNN.h

348

#define MIPSNN_CFG4_FTLB_FTLB_SETS __BITS(3,0)

sys/arch/mips/include/mipsNN.h

367

#define MIPSNN_CFG4_FVTLB_VTLB_SIZE_EXT __BITS(27,24)

sys/arch/mips/include/mipsNN.h

369

#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE __BITS(12,8)

sys/arch/mips/include/mipsNN.h

391

#define MIPSNN_CFG4_FVTLB_FTLB_WAYS __BITS(7,4)

sys/arch/mips/include/mipsNN.h

400

#define MIPSNN_CFG4_FVTLB_FTLB_SETS __BITS(3,0)

sys/arch/mips/include/mipsNN.h

486

#define MIPSNN_PERFCTL_IMPL __BITS(29,25)

sys/arch/mips/include/mipsNN.h

489

#define MIPSNN_PERFCTL_EC __BITS(24,23)

sys/arch/mips/include/mipsNN.h

499

#define MIPSNN_PERFCTL_EVENT __BITS(14,5)

sys/arch/mips/include/mipsNN.h

680

#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12,11)

sys/arch/mips/ingenic/ingenic_coreregs.h

62

#define REIM_ENTRY_M __BITS(31,16) /* reset exception entry if RPCn=1 */

sys/arch/mips/mips/cache_octeon.c

101

#define OCTEON_ICACHE_TAGLO_R(_taglo) (((_taglo) & __BITS(63, 62)) >> 62)

sys/arch/mips/mips/cache_octeon.c

102

#define OCTEON_ICACHE_TAGLO_ASID(_taglo) (((_taglo) & __BITS(59, 52)) >> 52)

sys/arch/mips/mips/cache_octeon.c

103

#define OCTEON_ICACHE_TAGLO_TAG(_taglo) (((_taglo) & __BITS(48, 13)) >> 13)

sys/arch/mips/mips/cache_octeon.c

104

#define OCTEON_ICACHE_TAGLO_INDEX(_taglo) (((_taglo) & __BITS(12, 7)) >> 7)

sys/arch/mips/mips/cache_octeon.c

105

#define OCTEON_ICACHE_TAGLO_G(_taglo) (((_taglo) & __BITS( 1, 1)) >> 1)

sys/arch/mips/mips/cache_octeon.c

106

#define OCTEON_ICACHE_TAGLO_VALID(_taglo) (((_taglo) & __BITS( 0, 0)) >> 0)

sys/arch/mips/mips/cache_octeon.c

110

#define OCTEON_DCACHE_VA_WAY(_va) (((_va) & __BITS(12, 7)) >> 7)

sys/arch/mips/mips/cache_octeon.c

111

#define OCTEON_DCACHE_VA_WORD(_va) (((_va) & __BITS( 6, 3)) >> 3)

sys/arch/mips/mips/cache_octeon.c

113

#define OCTEON_DCACHE_TAGLO_R(_taglo) (((_taglo) & __BITS(63, 62)) >> 62)

sys/arch/mips/mips/cache_octeon.c

114

#define OCTEON_DCACHE_TAGLO_ASID(_taglo) (((_taglo) & __BITS(59, 52)) >> 52)

sys/arch/mips/mips/cache_octeon.c

115

#define OCTEON_DCACHE_TAGLO_TAG(_taglo) (((_taglo) & __BITS(48, 7)) >> 7)

sys/arch/mips/mips/cache_octeon.c

116

#define OCTEON_DCACHE_TAGLO_G(_taglo) (((_taglo) & __BITS( 1, 1)) >> 1)

sys/arch/mips/mips/cache_octeon.c

117

#define OCTEON_DCACHE_TAGLO_VALID(_taglo) (((_taglo) & __BITS( 0, 0)) >> 0)

sys/arch/mips/mips/cache_octeon.c

119

#define OCTEON_DCACHE_TAGHI_PTAG(_taghi) (((_taghi) & __BITS(35, 7)) >> 7)

sys/arch/mips/mips/cache_octeon.c

120

#define OCTEON_DCACHE_TAGHI_VALID(_taghi) (((_taghi) & __BITS( 0, 0)) >> 0)

sys/arch/mips/mips/cache_octeon.c

188

(int)((taglo) & __BITS(48, 7)), /* (int)va */

sys/arch/mips/mips/cache_octeon.c

263

(int)((taglo) & __BITS(48, 13)), /* (int)va */

sys/arch/mips/mips/cache_octeon.c

97

#define OCTEON_ICACHE_VA_WAY(_va) (((_va) & __BITS(14, 13)) >> 13)

sys/arch/mips/mips/cache_octeon.c

98

#define OCTEON_ICACHE_VA_INDEX(_va) (((_va) & __BITS(12, 7)) >> 7)

sys/arch/mips/mips/cache_octeon.c

99

#define OCTEON_ICACHE_VA_WORD(_va) (((_va) & __BITS( 6, 3)) >> 3)

sys/arch/mips/mips/db_interface.c

716

mask = (register_t)(value & __BITS(11, 3));

sys/arch/mips/mips/db_interface.c

729

asid = (uint32_t)(value & __BITS(7,0));

sys/arch/mips/mips/kobj_machdep.c

123

addend &= __BITS(25, 0); /* mask off lower 26 bits */

sys/arch/mips/mips/mips_fixup.c

56

|| (ebase & __BITS(31,30)) != __BIT(31)) {

sys/arch/mips/ralink/ralink_reg.h

1338

#define PCICFG_P2P_BR_DEVNUM1 __BITS(23,20)

sys/arch/mips/ralink/ralink_reg.h

1339

#define PCICFG_P2P_BR_DEVNUM0 __BITS(19,16)

sys/arch/mips/ralink/ralink_reg.h

1348

#define CFGADDR_EXTREG __BITS(27,24)

sys/arch/mips/ralink/ralink_reg.h

1349

#define CFGADDR_BUS __BITS(23,16)

sys/arch/mips/ralink/ralink_reg.h

1350

#define CFGADDR_DEV __BITS(15,11)

sys/arch/mips/ralink/ralink_reg.h

1351

#define CFGADDR_FUN __BITS(10,8)

sys/arch/mips/ralink/ralink_reg.h

1352

#define CFGADDR_REG __BITS(7,0)

sys/arch/mips/ralink/ralink_reg.h

1355

#define MEMBASE_ADDR __BITS(31,16)

sys/arch/mips/ralink/ralink_reg.h

1357

#define IOBASE_ADDR __BITS(31,16)

sys/arch/mips/ralink/ralink_reg.h

1361

#define PHY0CFG_SPI_ADDR __BITS(15,8)

sys/arch/mips/ralink/ralink_reg.h

1362

#define PHY0CFG_SPI_DATA __BITS(7,0)

sys/arch/mips/ralink/ralink_reg.h

1366

#define BARSETUP_BARMSK __BITS(31,16)

sys/arch/mips/ralink/ralink_reg.h

1370

#define IMBASEBAR0 __BITS(31,16)

sys/arch/mips/ralink/ralink_reg.h

163

#define SYSCTL_CFG0_GE0_MODE __BITS(24,25)

sys/arch/mips/ralink/ralink_reg.h

167

#define SYSCTL_CFG0_BOOT_FROM __BITS(16,17)

sys/arch/mips/ralink/ralink_reg.h

168

#define SYSCTL_CFG0_TEST_CODE __BITS(8,15)

sys/arch/mips/ralink/ralink_reg.h

169

#define SYSCTL_CFG0_SRAM_CS_MODE __BITS(2,3)

sys/arch/mips/ralink/ralink_reg.h

173

#define SYSCTL_CFG0_DRAM_SIZE __BITS(12,14)

sys/arch/mips/ralink/ralink_reg.h

182

#define SYSCTL_CFG0_TEST_CODE __BITS(31,24)

sys/arch/mips/ralink/ralink_reg.h

183

#define SYSCTL_CFG0_BS_SHADOW __BITS(22,12)

sys/arch/mips/ralink/ralink_reg.h

187

#define SYSCTL_CFG0_DRAM_TYPE __BITS(5,4)

sys/arch/mips/ralink/ralink_reg.h

188

#define SYSCTL_CFG0_CHIP_MODE __BITS(3,0)

sys/arch/mips/ralink/ralink_reg.h

190

#define SYSCTL_CFG0_TEST_CODE __BITS(31,24)

sys/arch/mips/ralink/ralink_reg.h

191

#define SYSCTL_CFG0_BS_SHADOW __BITS(20,12)

sys/arch/mips/ralink/ralink_reg.h

197

#define SYSCTL_CFG0_CHIP_MODE __BITS(3,1)

sys/arch/mips/ralink/ralink_reg.h

202

#define SYSCTL_CFG1_GE2_MODE __BITS(15,14)

sys/arch/mips/ralink/ralink_reg.h

203

#define SYSCTL_CFG1_GE1_MODE __BITS(13,12)

sys/arch/mips/ralink/ralink_reg.h

216

#define SYSCTL_CLKCFG0_REFCLK0_RATE __BITS(11,9)

sys/arch/mips/ralink/ralink_reg.h

219

#define SYSCTL_CLKCFG0_OSC_1US_DIV_3883 __BITS(21,16)

sys/arch/mips/ralink/ralink_reg.h

220

#define SYSCTL_CLKCFG0_REFCLK1_RATE __BITS(15,13)

sys/arch/mips/ralink/ralink_reg.h

222

#define SYSCTL_CLKCFG0_CPU_FREQ_ADJ __BITS(3,0)

sys/arch/mips/ralink/ralink_reg.h

225

#define SYSCTL_CLKCFG0_OSC_1US_DIV_7620 __BITS(29,24)

sys/arch/mips/ralink/ralink_reg.h

226

#define SYSCTL_CLKCFG0_INT_CLK_FDIV __BITS(22,18)

sys/arch/mips/ralink/ralink_reg.h

227

#define SYSCTL_CLKCFG0_INT_CLK_FFRAC __BITS(16,12)

sys/arch/mips/ralink/ralink_reg.h

330

#define GPIO1MODE_PWM1 __BITS(31,30)

sys/arch/mips/ralink/ralink_reg.h

331

#define GPIO1MODE_PWM0 __BITS(29,18)

sys/arch/mips/ralink/ralink_reg.h

332

#define GPIO1MODE_UART2 __BITS(27,26)

sys/arch/mips/ralink/ralink_reg.h

333

#define GPIO1MODE_UART1 __BITS(25,24)

sys/arch/mips/ralink/ralink_reg.h

334

#define GPIO1MODE_I2C __BITS(21,20)

sys/arch/mips/ralink/ralink_reg.h

341

#define GPIO1MODE_SD __BITS(11,10)

sys/arch/mips/ralink/ralink_reg.h

342

#define GPIO1MODE_UART0 __BITS(9,8)

sys/arch/mips/ralink/ralink_reg.h

343

#define GPIO1MODE_I2S __BITS(7,6)

sys/arch/mips/ralink/ralink_reg.h

344

#define GPIO1MODE_SPI_CS1 __BITS(5,4)

sys/arch/mips/ralink/ralink_reg.h

345

#define GPIO1MODE_SPIS __BITS(3,2)

sys/arch/mips/ralink/ralink_reg.h

346

#define GPIO1MODE_GPIO __BITS(1,0)

sys/arch/mips/ralink/ralink_reg.h

347

#define GPIO2MODE_P4_LED_KN __BITS(27,26)

sys/arch/mips/ralink/ralink_reg.h

348

#define GPIO2MODE_P3_LED_KN __BITS(25,24)

sys/arch/mips/ralink/ralink_reg.h

349

#define GPIO2MODE_P2_LED_KN __BITS(23,22)

sys/arch/mips/ralink/ralink_reg.h

350

#define GPIO2MODE_P1_LED_KN __BITS(21,10)

sys/arch/mips/ralink/ralink_reg.h

351

#define GPIO2MODE_P0_LED_KN __BITS(19,18)

sys/arch/mips/ralink/ralink_reg.h

352

#define GPIO2MODE_WLED_KN __BITS(17,16)

sys/arch/mips/ralink/ralink_reg.h

353

#define GPIO2MODE_P4_LED_AN __BITS(11,10)

sys/arch/mips/ralink/ralink_reg.h

354

#define GPIO2MODE_P3_LED_AN __BITS(9,8)

sys/arch/mips/ralink/ralink_reg.h

355

#define GPIO2MODE_P2_LED_AN __BITS(7,6)

sys/arch/mips/ralink/ralink_reg.h

356

#define GPIO2MODE_P1_LED_AN __BITS(5,4)

sys/arch/mips/ralink/ralink_reg.h

357

#define GPIO2MODE_P0_LED_AN __BITS(3,2)

sys/arch/mips/ralink/ralink_reg.h

358

#define GPIO2MODE_WLED_AN __BITS(1,0)

sys/arch/mips/rmi/rmixl_cpu.c

257

ci->ci_cpuid = ebase & __BITS(9,0);

sys/arch/mips/rmi/rmixl_fmnvar.h

66

#define RMIXL_CPU_CORE(cpuid) ((uint32_t)((cpuid) & __BITS(9,0)) >> 2)

sys/arch/mips/rmi/rmixl_fmnvar.h

67

#define RMIXL_CPU_THREAD(cpuid) ((uint32_t)((cpuid) & __BITS(1,0)))

sys/arch/mips/rmi/rmixl_intr.c

598

irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0));

sys/arch/mips/rmi/rmixl_intr.c

599

irtc0 &= (__BITS(5,4) | __BITS(1,0));

sys/arch/mips/rmi/rmixl_intr.c

606

irtc0 = cpumask & __BITS(7,0);

sys/arch/mips/rmi/rmixl_intr.c

610

irtc0 = cpumask & __BITS(15,0);

sys/arch/mips/rmi/rmixl_intr.c

955

uint32_t thread = (uint32_t)(cpuid & __BITS(1,0));

sys/arch/mips/rmi/rmixl_iobus.c

179

cs->cs_mask |= __BITS(15,0);

sys/arch/mips/rmi/rmixl_obio.c

241

r |= ~(__BITS(19,16) | __BITS(10,9) | __BITS(7,5));

sys/arch/mips/rmi/rmixl_obio.c

250

(__BITS(31,21) | __BITS(15,14) | __BITS(10,9) | __BITS(7,2))

sys/arch/mips/rmi/rmixl_obio.c

251

#define _BITERR_INT_EN_RESV (__BITS(31,8) | __BIT(4))

sys/arch/mips/rmi/rmixl_obio.c

276

r |= __BITS(7,5);

sys/arch/mips/rmi/rmixl_pcie.c

102

#define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1))

sys/arch/mips/rmi/rmixl_pcie.c

106

#define PCIE_ECFG_RECR_RESV __BITS(31,3)

sys/arch/mips/rmi/rmixl_pcie.c

108

#define PCIE_ECFG_RESR_RESV __BITS(26,7)

sys/arch/mips/rmi/rmixl_pcie.c

116

{ RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) },

sys/arch/mips/rmi/rmixl_pcie.c

117

{ RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) },

sys/arch/mips/rmi/rmixl_pcie.c

122

{ RMIXL_PCIE_ECFG_RESR, __BITS(6,0) },

sys/arch/mips/rmi/rmixl_pcie.c

154

#define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4)

sys/arch/mips/rmi/rmixl_pcie.c

155

#define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0)

sys/arch/mips/rmi/rmixl_pcie.c

843

KASSERT((tag & __BITS(7,0)) == 0);

sys/arch/mips/rmi/rmixl_pcie.c

907

mask = __BITS(15,0);

sys/arch/mips/rmi/rmixl_pcie.c

928

mask = __BITS(14,0);

sys/arch/mips/rmi/rmixl_pcie.c

98

(__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0))

sys/arch/mips/rmi/rmixl_pcie.c

99

#define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1))

sys/arch/mips/rmi/rmixl_pcix.c

126

#define PCIX_INTR_CONTROL_RESV __BITS(31,8)

sys/arch/mips/rmi/rmixl_pcix.c

143

#define PCIX_INTR_STATUS_RESV __BITS(31,6)

sys/arch/mips/rmi/rmixl_pcix.c

154

#define PCIX_INTR_ERR_STATUS_RESa __BITS(31,5)

sys/arch/mips/rmi/rmixl_pcix.c

669

mask = __BITS(15,0);

sys/arch/mips/rmi/rmixlreg.h

1012

#define RMIXL_UG_CTRL3_RESa __BITS(31,11)

sys/arch/mips/rmi/rmixlreg.h

1013

#define RMIXL_UG_CTRL3_PREFETCH_SIZE __BITS(10,8) /* The pre-fetch size for a memory read transfer

sys/arch/mips/rmi/rmixlreg.h

1018

#define RMIXL_UG_CTRL3_DEV_UPPERADDR __BITS(6,1) /* Device controller address space selector */

sys/arch/mips/rmi/rmixlreg.h

1024

#define RMIXL_UB_PHY_STATUS_RESV __BITS(31,1)

sys/arch/mips/rmi/rmixlreg.h

1030

#define RMIXL_UB_INTERRUPT_RESV __BITS(31,6)

sys/arch/mips/rmi/rmixlreg.h

111

#define RMIXL_MSG_STS1_CCFCME __BITS(29,23) /* Credit Counter of Free Credit Message with Error */

sys/arch/mips/rmi/rmixlreg.h

113

#define RMIXL_MSG_STS1_SIDFCME __BITS(22,16) /* Source ID of Free Credit Message with Error */

sys/arch/mips/rmi/rmixlreg.h

1156

#define RMIXL_FMN_CC_RESV __BITS(31,8)

sys/arch/mips/rmi/rmixlreg.h

1157

#define RMIXL_FMN_CC_COUNT __BITS(7,0)

sys/arch/mips/rmi/rmixlreg.h

117

#define RMIXL_MSG_STS1_SIDE __BITS(13,7) /* Source ID of incoming msg with Error */

sys/arch/mips/rmi/rmixlreg.h

119

#define RMIXL_MSG_STS1_DIDE __BITS(6,0) /* Destination ID of the incoming message Message with Error */

sys/arch/mips/rmi/rmixlreg.h

127

#define RMIXL_MSG_CFG0_WM __BITS(31,24) /* Watermark level */

sys/arch/mips/rmi/rmixlreg.h

129

#define RMIXL_MSG_CFG0_RESa __BITS(23,22)

sys/arch/mips/rmi/rmixlreg.h

130

#define RMIXL_MSG_CFG0_IV __BITS(21,16) /* Interrupt Vector */

sys/arch/mips/rmi/rmixlreg.h

132

#define RMIXL_MSG_CFG0_RESb __BITS(15,12)

sys/arch/mips/rmi/rmixlreg.h

133

#define RMIXL_MSG_CFG0_ITM __BITS(11,8) /* Interrupt Thread Mask */

sys/arch/mips/rmi/rmixlreg.h

135

#define RMIXL_MSG_CFG0_RESc __BITS(7,2)

sys/arch/mips/rmi/rmixlreg.h

145

#define RMIXL_MSG_CFG1_RESV __BITS(63,3)

sys/arch/mips/rmi/rmixlreg.h

159

#define RMIXL_MSG_BSZ_RESV __BITS(63,8)

sys/arch/mips/rmi/rmixlreg.h

160

#define RMIXL_MSG_BSZ_SIZE __BITS(7,0)

sys/arch/mips/rmi/rmixlreg.h

359

#define RMIXL_FLASH_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */

sys/arch/mips/rmi/rmixlreg.h

362

#define RMIXL_FLASH_BAR_MASK __BITS(15,5) /* phys address mask bits 34:24 */

sys/arch/mips/rmi/rmixlreg.h

364

(((((r) & RMIXL_FLASH_BAR_MASK)) << (24 - 5)) | __BITS(23, 0))

sys/arch/mips/rmi/rmixlreg.h

365

#define RMIXL_FLASH_BAR_RESV __BITS(4,1) /* (reserved) */

sys/arch/mips/rmi/rmixlreg.h

372

#define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */

sys/arch/mips/rmi/rmixlreg.h

375

#define RMIXL_DRAM_BAR_ADDR_MASK __BITS(15,4) /* bits 35:24 of Address Mask */

sys/arch/mips/rmi/rmixlreg.h

378

#define RMIXL_DRAM_BAR_INTERLEAVE __BITS(3,1) /* Interleave Mode */

sys/arch/mips/rmi/rmixlreg.h

388

#define RMIXL_DRAM_DTR_RESa __BITS(31,14)

sys/arch/mips/rmi/rmixlreg.h

389

#define RMIXL_DRAM_DTR_PARTITION __BITS(13,12)

sys/arch/mips/rmi/rmixlreg.h

390

#define RMIXL_DRAM_DTR_RESb __BITS(11,10)

sys/arch/mips/rmi/rmixlreg.h

391

#define RMIXL_DRAM_DTR_DIVISIONS __BITS(9,8)

sys/arch/mips/rmi/rmixlreg.h

392

#define RMIXL_DRAM_DTR_RESc __BITS(7,6)

sys/arch/mips/rmi/rmixlreg.h

393

#define RMIXL_DRAM_DTR_POSITION __BITS(5,0)

sys/arch/mips/rmi/rmixlreg.h

400

#define RMIXL_DRAM_CFG_RESa __BITS(31,13)

sys/arch/mips/rmi/rmixlreg.h

403

#define RMIXL_DRAM_CFG_INTERLEAVE_MODE __BITS(10,8)

sys/arch/mips/rmi/rmixlreg.h

404

#define RMIXL_DRAM_CFG_RESc __BITS(7,5)

sys/arch/mips/rmi/rmixlreg.h

406

#define RMIXL_DRAM_CFG_RESd __BITS(3,2)

sys/arch/mips/rmi/rmixlreg.h

407

#define RMIXL_DRAM_CFG_DRAM_MODE __BITS(1,0) /* 1=DDR2 */

sys/arch/mips/rmi/rmixlreg.h

412

#define RMIXL_PCIX_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */

sys/arch/mips/rmi/rmixlreg.h

416

#define RMIXL_PCIX_CFG_BAR_RESV __BITS(16,1) /* (reserved) */

sys/arch/mips/rmi/rmixlreg.h

425

#define RMIXL_PCIX_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */

sys/arch/mips/rmi/rmixlreg.h

428

#define RMIXL_PCIX_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */

sys/arch/mips/rmi/rmixlreg.h

438

#define RMIXL_PCIX_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */

sys/arch/mips/rmi/rmixlreg.h

441

#define RMIXL_PCIX_IO_BAR_RESV __BITS(17,7) /* (reserve) */

sys/arch/mips/rmi/rmixlreg.h

442

#define RMIXL_PCIX_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */

sys/arch/mips/rmi/rmixlreg.h

452

#define RMIXL_PCIE_CFG_BAR_BASE __BITS(31,17) /* phys address bits 39:25 */

sys/arch/mips/rmi/rmixlreg.h

456

#define RMIXL_PCIE_CFG_BAR_RESV __BITS(16,1) /* (reserved) */

sys/arch/mips/rmi/rmixlreg.h

466

#define RMIXL_PCIE_ECFG_BAR_BASE __BITS(31,21) /* phys address bits 39:29 */

sys/arch/mips/rmi/rmixlreg.h

470

#define RMIXL_PCIE_ECFG_BAR_RESV __BITS(20,1) /* (reserved) */

sys/arch/mips/rmi/rmixlreg.h

479

#define RMIXL_PCIE_MEM_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */

sys/arch/mips/rmi/rmixlreg.h

482

#define RMIXL_PCIE_MEM_BAR_MASK __BITS(15,1) /* phys address mask bits 38:24 */

sys/arch/mips/rmi/rmixlreg.h

492

#define RMIXL_PCIE_IO_BAR_BASE __BITS(31,18) /* phys address bits 39:26 */

sys/arch/mips/rmi/rmixlreg.h

495

#define RMIXL_PCIE_IO_BAR_RESV __BITS(17,7) /* (reserve) */

sys/arch/mips/rmi/rmixlreg.h

496

#define RMIXL_PCIE_IO_BAR_MASK __BITS(6,1) /* phys address mask bits 31:26 */

sys/arch/mips/rmi/rmixlreg.h

530

#define RMIXL_PIC_CONTROL_GEN_NMI __BITS(2,1) /* do NMI after n WDog irpts */

sys/arch/mips/rmi/rmixlreg.h

532

#define RMIXL_PIC_CONTROL_RESa __BITS(7,3)

sys/arch/mips/rmi/rmixlreg.h

533

#define RMIXL_PIC_CONTROL_TIMER_ENB __BITS(15,8) /* per-Timer enable bits */

sys/arch/mips/rmi/rmixlreg.h

535

#define RMIXL_PIC_CONTROL_RESb __BITS(31,16)

sys/arch/mips/rmi/rmixlreg.h

542

#define RMIXL_PIC_IPIBASE_VECTORNUM __BITS(5,0)

sys/arch/mips/rmi/rmixlreg.h

546

#define RMIXL_PIC_IPIBASE_ID __BITS(31,16)

sys/arch/mips/rmi/rmixlreg.h

547

#define RMIXL_PIC_IPIBASE_ID_RESb __BITS(31,23)

sys/arch/mips/rmi/rmixlreg.h

548

#define RMIXL_PIC_IPIBASE_ID_CORE __BITS(22,20) /* Physical CPU ID */

sys/arch/mips/rmi/rmixlreg.h

550

#define RMIXL_PIC_IPIBASE_ID_RESc __BITS(19,18)

sys/arch/mips/rmi/rmixlreg.h

551

#define RMIXL_PIC_IPIBASE_ID_THREAD __BITS(17,16) /* Thread ID */

sys/arch/mips/rmi/rmixlreg.h

561

#define RMIXL_PIC_IRTENTRYC0_TMASK __BITS(7,0) /* Thread Mask */

sys/arch/mips/rmi/rmixlreg.h

562

#define RMIXL_PIC_IRTENTRYC0_RESa __BITS(3,2) /* write as 0 */

sys/arch/mips/rmi/rmixlreg.h

563

#define RMIXL_PIC_IRTENTRYC0_RESb __BITS(31,8) /* write as 0 */

sys/arch/mips/rmi/rmixlreg.h

571

#define RMIXL_PIC_IRTENTRYC1_INTVEC __BITS(5,0) /* maps to bit# in CPU's EIRR */

sys/arch/mips/rmi/rmixlreg.h

574

#define RMIXL_PIC_IRTENTRYC1_RESV __BITS(28,8)

sys/arch/mips/rmi/rmixlreg.h

602

#define RMIXL_GPIO_PGM_MASK (__BITS(13,0) | __BITS(22,20) | __BIT(24)) /* programmable pins */

sys/arch/mips/rmi/rmixlreg.h

603

#define RMIXL_GPIO_INTR_MASK (__BITS(13,0) | __BITS(24,20)) /* intr-capable pins */

sys/arch/mips/rmi/rmixlreg.h

609

#define RMIXL_GPIO_FLASH_CPUID __BITS(16,14) /* Flash CPU ID, output only */

sys/arch/mips/rmi/rmixlreg.h

672

#define RMIXL_GPIO_RESET_RESV __BITS(31,1)

sys/arch/mips/rmi/rmixlreg.h

698

#define RMIXL_GPIO_RESET_CFG_RESa __BITS(31,28)

sys/arch/mips/rmi/rmixlreg.h

699

#define RMIXL_GPIO_RESET_CFG_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select:

sys/arch/mips/rmi/rmixlreg.h

718

#define RMIXL_GPIO_RESET_CFG_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */

sys/arch/mips/rmi/rmixlreg.h

734

#define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */

sys/arch/mips/rmi/rmixlreg.h

735

#define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */

sys/arch/mips/rmi/rmixlreg.h

740

#define RMIXL_GPIO_EXT_INT_RESV __BITS(31,4)

sys/arch/mips/rmi/rmixlreg.h

760

#define RMIXL_GPIO_LOW_PWR_DIS_SAE __BITS(8,7) /* Security Acceleration Engine disable:

sys/arch/mips/rmi/rmixlreg.h

766

#define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9)

sys/arch/mips/rmi/rmixlreg.h

787

#define RMIXL_FLASH_CSDEV_RESV __BITS(31,16)

sys/arch/mips/rmi/rmixlreg.h

812

#define RMIXL_FLASH_CSDEV_DWIDTH __BITS(8,7) /* Data Bus Width:

sys/arch/mips/rmi/rmixlreg.h

831

#define RMIXL_FLASH_CSDEV_BURST __BITS(3,1) /* Burst Length:

sys/arch/mips/rmi/rmixlreg.h

839

#define RMIXL_FLASH_CSDEV_BURST_EN __BITS(0) /* Burst Enable */

sys/arch/mips/rmi/rmixlreg.h

84

#define RMIXL_MSG_STS0_RFBE __BITS(31,24) /* RX FIFO Buckets bit mask

sys/arch/mips/rmi/rmixlreg.h

90

#define RMIXL_MSG_STS0_RMSID __BITS(22,16) /* Source ID */

sys/arch/mips/rmi/rmixlreg.h

92

#define RMIXL_MSG_STS0_RMSC __BITS(15,8) /* RX Message Software Code */

sys/arch/mips/rmi/rmixlreg.h

94

#define RMIXL_MSG_STS0_RMS __BITS(7,6) /* RX Message Size (minus 1) */

sys/arch/mips/rmi/rmixlreg.h

954

#define RMIXL_UG_CTRL1_RESV __BITS(31,2)

sys/arch/mips/rmi/rmixlreg.h

967

#define RMIXL_UG_CTRL2_RESa __BITS(31,20)

sys/arch/mips/rmi/rmixlreg.h

968

#define RMIXL_UG_CTRL2_TX_TUNE_1 __BITS(19,18) /* Port_1 Transmitter Tuning for High-Speed Operation.

sys/arch/mips/rmi/rmixlreg.h

974

#define RMIXL_UG_CTRL2_TX_TUNE_0 __BITS(17,16) /* Port_0 Transmitter Tuning for High-Speed Operation

sys/arch/mips/rmi/rmixlreg.h

989

#define RMIXL_UG_CTRL2_RESc __BITS(7,6)

sys/arch/or1k/include/spr.h

35

#define SPR_GROUP __BITS(15,11)

sys/arch/or1k/include/spr.h

36

#define SPR_REG __BITS(10,0)

sys/arch/or1k/include/spr.h

56

#define SR_CID __BITS(31,28)

sys/arch/or1k/include/spr.h

85

#define FPCSR_RM __BITS(2,1)

sys/arch/powerpc/booke/dev/pq3ehci.c

64

#define USBMODE_CM __BITS(0,1) /* Controller Mode */

sys/arch/powerpc/booke/dev/pq3gpio.c

392

{ __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30),

sys/arch/powerpc/booke/dev/pq3gpio.c

393

__BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 },

sys/arch/powerpc/booke/dev/pq3gpio.c

394

{ __BITS(3,1), 0, 0, PMUXCR_QE3 },

sys/arch/powerpc/booke/dev/pq3gpio.c

395

{ 0, __BITS(17,14), 0, PMUXCR_QE8 },

sys/arch/powerpc/booke/dev/pq3gpio.c

396

{ __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 },

sys/arch/powerpc/booke/dev/pq3gpio.c

397

{ 0, __BITS(22,21), 0, PMUXCR_QE10 },

sys/arch/powerpc/booke/dev/pq3gpio.c

398

{ 0, __BITS(28,23), 0, PMUXCR_QE11 },

sys/arch/powerpc/fpu/fpu_emu.c

312

exp = __SHIFTOUT(reg, __BITS(62, 52)) - 1023;

sys/arch/powerpc/fpu/fpu_emu.c

322

__SHIFTOUT(reg, __BITS(58, 52) | __BITS(51, 29));

sys/arch/powerpc/fpu/fpu_emu.c

326

frac = __SHIFTOUT(__BIT(52) | reg, __BITS(52, 29 + shift));

sys/arch/powerpc/include/booke/e500reg.h

44

#define __PPCBITS(m,n) __BITS(31-(n),31-(m))

sys/arch/powerpc/mpc5200/cdm.c

78

#define PORCFG_PPC_PLL_CFG __BITS(0, 4) /* e300 core APLL config [0:4] */

sys/arch/powerpc/mpc5200/cdm.c

83

#define CFG_PCI_CLK_SEL __BITS(0, 1) /* PCI clock select [1:0] */

sys/arch/riscv/fdt/clint_fdt.c

98

__SHIFTIN(hi, __BITS(63, 32)) |

sys/arch/riscv/fdt/clint_fdt.c

99

__SHIFTIN(lo, __BITS(31, 0));

sys/arch/riscv/fdt/pcihost_fdtvar.h

33

#define PHYS_HI_SPACE __BITS(25,24)

sys/arch/riscv/fdt/pcihost_fdtvar.h

38

#define PHYS_HI_BUS __BITS(23,16)

sys/arch/riscv/fdt/pcihost_fdtvar.h

39

#define PHYS_HI_DEVICE __BITS(15,11)

sys/arch/riscv/fdt/pcihost_fdtvar.h

40

#define PHYS_HI_FUNCTION __BITS(10,8)

sys/arch/riscv/fdt/pcihost_fdtvar.h

41

#define PHYS_HI_REGISTER __BITS(7,0)

sys/arch/riscv/include/mutex.h

64

#define MTX_IPL __BITS(7,4) // only need 4 bits

sys/arch/riscv/include/pci_machdep.h

84

#define RISCV_PCI_INTR_MSI_VEC __BITS(42, 32)

sys/arch/riscv/include/pci_machdep.h

88

#define RISCV_PCI_INTR_FRAME __BITS(23, 16)

sys/arch/riscv/include/pci_machdep.h

89

#define RISCV_PCI_INTR_IRQ __BITS(15, 0)

sys/arch/riscv/include/pte.h

37

#define PTE_PPN __BITS(53, 10)

sys/arch/riscv/include/pte.h

38

#define PTE_PPN0 __BITS(18, 10)

sys/arch/riscv/include/pte.h

39

#define PTE_PPN1 __BITS(27, 19)

sys/arch/riscv/include/pte.h

40

#define PTE_PPN2 __BITS(53, 28)

sys/arch/riscv/include/pte.h

45

#define PTE_PPN __BITS(31, 10)

sys/arch/riscv/include/pte.h

46

#define PTE_PPN0 __BITS(19, 10)

sys/arch/riscv/include/pte.h

47

#define PTE_PPN1 __BITS(31, 20)

sys/arch/riscv/include/pte.h

62

#define PTE_PBMT __BITS(62, 61) // Svpbmt

sys/arch/riscv/include/pte.h

63

#define PTE_reserved0 __BITS(60, 54) //

sys/arch/riscv/include/pte.h

77

#define PTE_XMAE __BITS(63,59)

sys/arch/riscv/include/pte.h

96

#define PTE_RSW __BITS(9, 8)

sys/arch/riscv/include/sysreg.h

168

#define SR_WPRI __BITS(62, 34) | __BITS(31, 20) | \

sys/arch/riscv/include/sysreg.h

169

__BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \

sys/arch/riscv/include/sysreg.h

173

#define SR_UXL __BITS(33, 32) // U-mode XLEN

sys/arch/riscv/include/sysreg.h

179

#define SR_WPRI __BITS(30, 20) | \

sys/arch/riscv/include/sysreg.h

180

__BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \

sys/arch/riscv/include/sysreg.h

190

#define SR_XS __BITS(16, 15) // Vector extension state

sys/arch/riscv/include/sysreg.h

195

#define SR_FS __BITS(14, 13) // Floating-point unit state

sys/arch/riscv/include/sysreg.h

201

#define SR_VS __BITS(10, 9) // User-mode extension state

sys/arch/riscv/include/sysreg.h

245

#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN - 2, 0))

sys/arch/riscv/include/sysreg.h

298

__SHIFTIN(__hi0, __BITS(63, 32)) |

sys/arch/riscv/include/sysreg.h

299

__SHIFTIN(__lo0, __BITS(31, 0));

sys/arch/riscv/include/sysreg.h

304

#define SATP_MODE __BITS(63, 60) // Translation mode

sys/arch/riscv/include/sysreg.h

313

#define SATP_ASID __BITS(59, 44) // Address Space Identifier

sys/arch/riscv/include/sysreg.h

314

#define SATP_PPN __BITS(43, 0) // Physical Page Number

sys/arch/riscv/include/sysreg.h

319

#define SATP_ASID __BITS(30, 22) // Address Space Identifier

sys/arch/riscv/include/sysreg.h

320

#define SATP_PPN __BITS(21, 0) // Physical Page Number

sys/arch/riscv/include/sysreg.h

48

#define FCSR_FRM __BITS(7, 5)

sys/arch/riscv/include/sysreg.h

55

#define FCSR_FFLAGS __BITS(4, 0) // Sticky bits

sys/arch/riscv/riscv/kobj_machdep.c

257

addend = addend + (last_hi20.addend & __BITS(11,0));

sys/arch/riscv/riscv/kobj_machdep.c

292

const uint8_t mask = __BITS(5, 0);

sys/arch/riscv/riscv/kobj_machdep.c

343

const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 5));

sys/arch/riscv/riscv/kobj_machdep.c

344

const uint32_t immC = __SHIFTOUT(addend, __BITS( 4, 1));

sys/arch/riscv/riscv/kobj_machdep.c

348

__SHIFTIN(immB, __BITS(30, 25)) |

sys/arch/riscv/riscv/kobj_machdep.c

349

__SHIFTIN(immC, __BITS(11, 8)) |

sys/arch/riscv/riscv/kobj_machdep.c

351

const uint32_t mask = __BITS(31, 25) | __BITS(11, 7);

sys/arch/riscv/riscv/kobj_machdep.c

365

const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 1));

sys/arch/riscv/riscv/kobj_machdep.c

367

const uint32_t immD = __SHIFTOUT(addend, __BITS(19, 12));

sys/arch/riscv/riscv/kobj_machdep.c

370

__SHIFTIN(immB, __BITS(30, 21)) |

sys/arch/riscv/riscv/kobj_machdep.c

372

__SHIFTIN(immD, __BITS(19,12));

sys/arch/riscv/riscv/kobj_machdep.c

383

const uint32_t mask = __BITS(31, 12);

sys/arch/riscv/riscv/kobj_machdep.c

407

const uint32_t immA = __SHIFTOUT(addend, __BITS(11, 5));

sys/arch/riscv/riscv/kobj_machdep.c

408

const uint32_t immB = __SHIFTOUT(addend, __BITS( 4, 0));

sys/arch/riscv/riscv/kobj_machdep.c

409

const uint32_t mask = __BITS(31, 25) | __BITS(11, 7);

sys/arch/riscv/riscv/kobj_machdep.c

411

__SHIFTIN(immA, __BITS(31, 25)) |

sys/arch/riscv/riscv/kobj_machdep.c

412

__SHIFTIN(immB, __BITS(11, 7));

sys/arch/riscv/riscv/kobj_machdep.c

441

const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 1));

sys/arch/riscv/riscv/kobj_machdep.c

443

const uint32_t immD = __SHIFTOUT(addend, __BITS(19, 12));

sys/arch/riscv/riscv/kobj_machdep.c

446

__SHIFTIN(immB, __BITS(30, 21)) |

sys/arch/riscv/riscv/kobj_machdep.c

448

__SHIFTIN(immD, __BITS(19,12));

sys/arch/riscv/riscv/kobj_machdep.c

474

const uint16_t immB = __SHIFTOUT(addend, __BITS(4, 3));

sys/arch/riscv/riscv/kobj_machdep.c

475

const uint16_t immC = __SHIFTOUT(addend, __BITS(7, 6));

sys/arch/riscv/riscv/kobj_machdep.c

476

const uint16_t immD = __SHIFTOUT(addend, __BITS(2, 1));

sys/arch/riscv/riscv/kobj_machdep.c

478

const uint16_t mask = __BITS(12, 10) | __BITS(6, 2);

sys/arch/riscv/riscv/kobj_machdep.c

481

__SHIFTIN(immB, __BITS(11, 10)) |

sys/arch/riscv/riscv/kobj_machdep.c

482

__SHIFTIN(immC, __BITS( 6, 5)) |

sys/arch/riscv/riscv/kobj_machdep.c

483

__SHIFTIN(immD, __BITS( 4, 3)) |

sys/arch/riscv/riscv/kobj_machdep.c

499

const uint16_t immC = __SHIFTOUT(addend, __BITS(9, 8));

sys/arch/riscv/riscv/kobj_machdep.c

503

const uint16_t immG = __SHIFTOUT(addend, __BITS(3, 1));

sys/arch/riscv/riscv/kobj_machdep.c

505

const uint16_t mask = __BITS(12, 2);

sys/arch/riscv/riscv/kobj_machdep.c

509

__SHIFTIN(immC, __BITS(10, 9)) |

sys/arch/riscv/riscv/kobj_machdep.c

513

__SHIFTIN(immG, __BITS(5, 3)) |

sys/arch/riscv/riscv/kobj_machdep.c

528

const uint16_t immB = __SHIFTOUT(addend, __BITS(16,12));

sys/arch/riscv/riscv/kobj_machdep.c

529

const uint16_t mask = __BIT(12) | __BITS(6, 2);

sys/arch/riscv/riscv/kobj_machdep.c

532

__SHIFTIN(immB, __BITS(6, 2));

sys/arch/riscv/riscv/riscv_machdep.c

981

va |= __BITS(63, topbit);

sys/arch/riscv/sifive/fu540_ccache.c

44

#define CCACHE_CONFIG_BANKS_MASK __BITS( 7, 0)

sys/arch/riscv/sifive/fu540_ccache.c

45

#define CCACHE_CONFIG_WAYS_MASK __BITS(15, 8)

sys/arch/riscv/sifive/fu540_ccache.c

46

#define CCACHE_CONFIG_LGSETS_MASK __BITS(23, 16)

sys/arch/riscv/sifive/fu540_ccache.c

47

#define CCACHE_CONFIG_LGBLOCKBYTES_MASK __BITS(31, 24)

sys/arch/riscv/sifive/fu540_prci.c

50

#define PLL0_DIVQ __BITS(17,15)

sys/arch/riscv/sifive/fu540_prci.c

51

#define PLL0_DIVF __BITS(14,6)

sys/arch/riscv/sifive/fu540_prci.c

52

#define PLL0_DIVR __BITS(5,0)

sys/arch/riscv/starfive/jh7100_pinctrl.c

108

#define DT_GPIOMUX_DOUT_MASK __BITS(31, 24)

sys/arch/riscv/starfive/jh7100_pinctrl.c

109

#define DT_GPIOMUX_DOEN_MASK __BITS(23, 16)

sys/arch/riscv/starfive/jh7100_pinctrl.c

110

#define DT_GPIOMUX_DIN_MASK __BITS(15, 8)

sys/arch/riscv/starfive/jh7100_pinctrl.c

113

#define DT_GPIOMUX_GPIO_MASK __BITS( 5, 0)

sys/arch/riscv/starfive/jh7100_pinctrl.c

67

#define GPO_DOUT_MASK __BITS(30, 0)

sys/arch/riscv/starfive/jh7100_pinctrl.c

70

#define GPO_DOEN_MASK __BITS(30, 0)

sys/arch/riscv/starfive/jh7100_pinctrl.c

84

#define PAD_SLEW_RATE_MASK __BITS(11, 9)

sys/arch/riscv/starfive/jh7100_pinctrl.c

90

#define PAD_DRIVE_STRENGTH_MASK __BITS( 3, 0)

sys/arch/riscv/starfive/jh7110_pcie.c

110

#define PLDA_IMASK_INT_INTX __BITS(27, 24)

sys/arch/riscv/starfive/jh7110_pcie.c

117

#define PLDA_ISTATUS_INT_INTX __BITS(27, 24)

sys/arch/riscv/starfive/jh7110_pcie.c

136

#define PLDA_ATR_SIZE_SRC_MASK __BITS(31, 12)

sys/arch/riscv/starfive/jh7110_pcie.c

137

#define PLDA_ATR_SIZE_MASK __BITS(6, 1)

sys/arch/riscv/starfive/jh7110_pcie.c

153

#define STG_SYSCON_AXI4_SLVL_AR_MASK __BITS(22, 8)

sys/arch/riscv/starfive/jh7110_pcie.c

154

#define STG_SYSCON_AXI4_SLVL_PHY_AR_MASK __BITS(20,17)

sys/arch/riscv/starfive/jh7110_pcie.c

160

#define STG_SYSCON_CKREF_SRC_MASK __BITS(19, 18)

sys/arch/riscv/starfive/jh7110_pcie.c

161

#define STG_SYSCON_AXI4_SLVL_AW_MASK __BITS(14, 0)

sys/arch/riscv/starfive/jh7110_pcie.c

162

#define STG_SYSCON_AXI4_SLVL_PHY_AW_MASK __BITS(12, 9)

sys/arch/riscv/starfive/jh7110_pcie.c

172

#define ECAM_BUS_MASK __BITS(27, 20)

sys/arch/riscv/starfive/jh7110_pcie.c

173

#define ECAM_DEV_MASK __BITS(19, 15)

sys/arch/riscv/starfive/jh7110_pcie.c

174

#define ECAM_FUNC_MASK __BITS(14, 12)

sys/arch/riscv/starfive/jh7110_pcie.c

175

#define ECAM_OFFSET_MASK __BITS(11, 0)

sys/arch/riscv/starfive/jh7110_pcie.c

537

__SHIFTIN(be32toh(ranges[i + 1]), __BITS(63, 32)) |

sys/arch/riscv/starfive/jh7110_pcie.c

538

__SHIFTIN(be32toh(ranges[i + 2]), __BITS(31, 0));

sys/arch/riscv/starfive/jh7110_pcie.c

540

__SHIFTIN(be32toh(ranges[i + 3]), __BITS(63, 32)) |

sys/arch/riscv/starfive/jh7110_pcie.c

541

__SHIFTIN(be32toh(ranges[i + 4]), __BITS(31, 0));

sys/arch/riscv/starfive/jh7110_pcie.c

98

#define PLDA_PCI_IDS_REVISION_MASK __BITS( 7, 0)

sys/arch/riscv/starfive/jh7110_pcie.c

99

#define PLDA_PCI_IDS_CLASSCODE_MASK __BITS(31, 8)

sys/arch/riscv/starfive/jh7110_pinctrl.c

109

#define JH7110_PADCFG_DS_MASK __BITS(1, 2)

sys/arch/riscv/starfive/jh7110_pinctrl.c

233

[JH7110_SYS_PAD_GMAC1_RXC] = JH7110_FS(0x29c, __BITS( 1, 0), 1),

sys/arch/riscv/starfive/jh7110_pinctrl.c

234

[JH7110_SYS_PAD_GPIO10] = JH7110_FS(0x29c, __BITS( 4, 2), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

235

[JH7110_SYS_PAD_GPIO11] = JH7110_FS(0x29c, __BITS( 7, 5), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

236

[JH7110_SYS_PAD_GPIO12] = JH7110_FS(0x29c, __BITS(10, 8), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

237

[JH7110_SYS_PAD_GPIO13] = JH7110_FS(0x29c, __BITS(13,11), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

238

[JH7110_SYS_PAD_GPIO14] = JH7110_FS(0x29c, __BITS(16,14), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

239

[JH7110_SYS_PAD_GPIO15] = JH7110_FS(0x29c, __BITS(19,17), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

240

[JH7110_SYS_PAD_GPIO16] = JH7110_FS(0x29c, __BITS(22,20), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

241

[JH7110_SYS_PAD_GPIO17] = JH7110_FS(0x29c, __BITS(25,23), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

242

[JH7110_SYS_PAD_GPIO18] = JH7110_FS(0x29c, __BITS(28,26), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

243

[JH7110_SYS_PAD_GPIO19] = JH7110_FS(0x29c, __BITS(31,29), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

245

[JH7110_SYS_PAD_GPIO20] = JH7110_FS(0x2a0, __BITS( 2, 0), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

246

[JH7110_SYS_PAD_GPIO21] = JH7110_FS(0x2a0, __BITS( 5, 3), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

247

[JH7110_SYS_PAD_GPIO22] = JH7110_FS(0x2a0, __BITS( 8, 6), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

248

[JH7110_SYS_PAD_GPIO23] = JH7110_FS(0x2a0, __BITS(11, 9), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

249

[JH7110_SYS_PAD_GPIO24] = JH7110_FS(0x2a0, __BITS(14,12), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

250

[JH7110_SYS_PAD_GPIO25] = JH7110_FS(0x2a0, __BITS(17,15), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

251

[JH7110_SYS_PAD_GPIO26] = JH7110_FS(0x2a0, __BITS(20,18), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

252

[JH7110_SYS_PAD_GPIO27] = JH7110_FS(0x2a0, __BITS(23,21), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

253

[JH7110_SYS_PAD_GPIO28] = JH7110_FS(0x2a0, __BITS(26,24), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

254

[JH7110_SYS_PAD_GPIO29] = JH7110_FS(0x2a0, __BITS(29,27), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

256

[JH7110_SYS_PAD_GPIO30] = JH7110_FS(0x2a4, __BITS( 2, 0), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

257

[JH7110_SYS_PAD_GPIO31] = JH7110_FS(0x2a4, __BITS( 5, 3), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

258

[JH7110_SYS_PAD_GPIO32] = JH7110_FS(0x2a4, __BITS( 8, 6), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

259

[JH7110_SYS_PAD_GPIO33] = JH7110_FS(0x2a4, __BITS(11, 9), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

260

[JH7110_SYS_PAD_GPIO34] = JH7110_FS(0x2a4, __BITS(14,12), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

261

[JH7110_SYS_PAD_GPIO35] = JH7110_FS(0x2a4, __BITS(17,15), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

262

[JH7110_SYS_PAD_GPIO36] = JH7110_FS(0x2a4, __BITS(19,17), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

263

[JH7110_SYS_PAD_GPIO37] = JH7110_FS(0x2a4, __BITS(23,20), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

264

[JH7110_SYS_PAD_GPIO38] = JH7110_FS(0x2a4, __BITS(26,23), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

265

[JH7110_SYS_PAD_GPIO39] = JH7110_FS(0x2a4, __BITS(28,26), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

266

[JH7110_SYS_PAD_GPIO40] = JH7110_FS(0x2a4, __BITS(31,29), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

268

[JH7110_SYS_PAD_GPIO41] = JH7110_FS(0x2a8, __BITS( 2, 0), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

269

[JH7110_SYS_PAD_GPIO42] = JH7110_FS(0x2a8, __BITS( 5, 3), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

270

[JH7110_SYS_PAD_GPIO43] = JH7110_FS(0x2a8, __BITS( 8, 6), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

271

[JH7110_SYS_PAD_GPIO44] = JH7110_FS(0x2a8, __BITS(11, 9), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

272

[JH7110_SYS_PAD_GPIO45] = JH7110_FS(0x2a8, __BITS(14,12), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

273

[JH7110_SYS_PAD_GPIO46] = JH7110_FS(0x2a8, __BITS(17,15), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

274

[JH7110_SYS_PAD_GPIO47] = JH7110_FS(0x2a8, __BITS(20,18), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

275

[JH7110_SYS_PAD_GPIO48] = JH7110_FS(0x2a8, __BITS(23,21), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

276

[JH7110_SYS_PAD_GPIO49] = JH7110_FS(0x2a8, __BITS(26,24), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

277

[JH7110_SYS_PAD_GPIO50] = JH7110_FS(0x2a8, __BITS(29,27), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

278

[JH7110_SYS_PAD_GPIO51] = JH7110_FS(0x2a8, __BITS(31,30), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

280

[JH7110_SYS_PAD_GPIO52] = JH7110_FS(0x2ac, __BITS( 1, 0), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

281

[JH7110_SYS_PAD_GPIO53] = JH7110_FS(0x2ac, __BITS( 3, 2), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

282

[JH7110_SYS_PAD_GPIO54] = JH7110_FS(0x2ac, __BITS( 5, 4), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

283

[JH7110_SYS_PAD_GPIO55] = JH7110_FS(0x2ac, __BITS( 8, 6), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

284

[JH7110_SYS_PAD_GPIO56] = JH7110_FS(0x2ac, __BITS(11, 9), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

285

[JH7110_SYS_PAD_GPIO57] = JH7110_FS(0x2ac, __BITS(14,12), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

286

[JH7110_SYS_PAD_GPIO58] = JH7110_FS(0x2ac, __BITS(17,15), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

287

[JH7110_SYS_PAD_GPIO59] = JH7110_FS(0x2ac, __BITS(20,18), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

288

[JH7110_SYS_PAD_GPIO60] = JH7110_FS(0x2ac, __BITS(23,21), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

289

[JH7110_SYS_PAD_GPIO61] = JH7110_FS(0x2ac, __BITS(26,24), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

290

[JH7110_SYS_PAD_GPIO62] = JH7110_FS(0x2ac, __BITS(29,27), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

291

[JH7110_SYS_PAD_GPIO63] = JH7110_FS(0x2ac, __BITS(31,30), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

293

[JH7110_SYS_PAD_GPIO6] = JH7110_FS(0x2b0, __BITS( 1, 0), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

294

[JH7110_SYS_PAD_GPIO7] = JH7110_FS(0x2b0, __BITS( 4, 2), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

295

[JH7110_SYS_PAD_GPIO8] = JH7110_FS(0x2b0, __BITS( 7, 5), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

296

[JH7110_SYS_PAD_GPIO9] = JH7110_FS(0x2b0, __BITS(10, 8), 3),

sys/arch/riscv/starfive/jh7110_pinctrl.c

377

.jpd_doen_mask = __BITS(2, 0),

sys/arch/riscv/starfive/jh7110_pinctrl.c

379

.jpd_dout_mask = __BITS(3, 0),

sys/arch/riscv/starfive/jh7110_pinctrl.c

381

.jpd_gpi_mask = __BITS(3, 0),

sys/arch/riscv/starfive/jh7110_pinctrl.c

389

.jpd_doen_mask = __BITS(5, 0),

sys/arch/riscv/starfive/jh7110_pinctrl.c

391

.jpd_dout_mask = __BITS(6, 0),

sys/arch/riscv/starfive/jh7110_pinctrl.c

393

.jpd_gpi_mask = __BITS(6, 0),

sys/arch/riscv/starfive/jh7110_pinctrl.c

419

#define DT_PINMUX_DIN_MASK __BITS(31, 24)

sys/arch/riscv/starfive/jh7110_pinctrl.c

420

#define DT_PINMUX_DOUT_MASK __BITS(23, 16)

sys/arch/riscv/starfive/jh7110_pinctrl.c

421

#define DT_PINMUX_DOEN_MASK __BITS(15, 10)

sys/arch/riscv/starfive/jh7110_pinctrl.c

422

#define DT_PINMUX_FUNC_MASK __BITS( 9, 8)

sys/arch/riscv/starfive/jh7110_pinctrl.c

423

#define DT_PINMUX_PIN_MASK __BITS( 7, 0)

sys/arch/riscv/starfive/jh7110_trng.c

97

#define JH7110_TRNG_FEATURES_MAX_RAND_LENGTH __BITS(1,0)

sys/arch/riscv/starfive/jh71x0_clkc.h

46

#define JH71X0_CLK_MUX_MASK __BITS(27, 24)

sys/arch/riscv/starfive/jh71x0_clkc.h

47

#define JH71X0_CLK_DIV_MASK __BITS(23, 0)

sys/arch/riscv/starfive/jh71x0_clkc.h

48

#define JH71X0_CLK_FRAC_MASK __BITS(15, 8)

sys/arch/riscv/starfive/jh71x0_clkc.h

49

#define JH71X0_CLK_INT_MASK __BITS(7, 0)

sys/arch/riscv/starfive/jh71x0_eth.c

59

#define STARFIVE_GMAC_PHY_INFT_MASK __BITS(2, 0)

sys/arch/riscv/starfive/jh71x0_temp.c

61

#define JH71X0_TEMP_DOUT_MASK __BITS(27, 16)

sys/arch/riscv/starfive/jh71x0_usb.c

61

#define JH7100_USB0_MODE_STRAP_MASK __BITS(2, 0)

sys/arch/riscv/starfive/jh71x0_usb.c

75

#define JH7110_STRAP_MASK __BITS(18, 16)

sys/arch/riscv/starfive/jh71x0_usb.c

80

#define JH7110_MISC_CFG_MASK __BITS(23, 20)

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

230

__BITS(15,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

241

__BITS(15,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

252

__BITS(15,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

255

__BITS(18,16), /* p */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

263

__BITS(15,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

266

__BITS(22,20), /* p */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

276

__BITS(15,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

279

__BITS(18,16), /* p */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

287

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

288

__BITS(1,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

289

__BITS(25,24), /* sel */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

295

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

296

__BITS(4,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

297

__BITS(25,24), /* sel */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

303

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

304

__BITS(4,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

305

__BITS(25,24), /* sel */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

313

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

314

__BITS(1,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

315

__BITS(26,24), /* sel */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

321

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

322

__BITS(3,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

323

__BITS(26,24), /* sel */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

328

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

329

__BITS(3,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

330

__BITS(26,24), /* sel */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

335

__BITS(9,8), /* n */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

336

__BITS(3,0), /* m */

sys/arch/riscv/sunxi/sun20i_d1_ccu.c

337

__BITS(26,24), /* sel */

sys/arch/shark/ofw/vlpci.h

107

#define VLPCI_PCI_ARB_CPU_TIM_SLT __BITS(5, 4)

sys/arch/shark/ofw/vlpci.h

112

#define VLPCI_PCI_ARB_PCI_MST_TMO __BITS(3, 0)

sys/arch/shark/ofw/vlpci.h

132

#define VLPCI_CFG_MISC_CTL_INT_CTL __BITS(5, 6)

sys/arch/shark/ofw/vlpci.h

165

#define VLPCI_PCI_WND_ATTR_SZ __BITS(4, 2)

sys/arch/shark/ofw/vlpci.h

188

#define VLPCI_INT_CTL_INT2IRQ(int) __BITS((int) % 8 + 2, (int) % 8)

sys/arch/shark/ofw/vlpci.h

221

#define VLPCI_MISC_CTL_HIADDR (__BITS(7, 6) | __BIT(4))

sys/arch/shark/ofw/vlpci.h

262

#define VLPCI_IRQ_MODE_CTL(i) __BITS((i) + 1, (i))

sys/arch/shark/ofw/vlpci.h

269

#define VLPCI_OBD_MEM_EADDR_CA32_CA28 __BITS(4, 0)

sys/arch/shark/ofw/vlpci.h

61

#define VLPCI_DIP_SW_STRAP __BITS(7, 4)

sys/arch/shark/ofw/vlpci.h

62

#define VLPCI_DIP_SW_REV_ID __BITS(3, 0)

sys/arch/shark/ofw/vlpci.h

98

#define VLPCI_PCI_TIM_DEVSEL_DEC __BITS(1, 0)

sys/arch/vax/vsa/tc_vsbus.c

124

#define KA4x_TCA_CSR_BLK_SZ __BITS(0, 2) /* 0x00007 RW */

sys/arch/vax/vsa/tc_vsbus.c

126

#define KA4x_TCA_CSR_BAD_PAR __BITS(4, 7) /* 0x000f0 RW */

sys/arch/x86/acpi/acpi_cpu_md.c

100

#define ACPI_0FH_CONTROL_PLL __BITS(20, 26)

sys/arch/x86/acpi/acpi_cpu_md.c

101

#define ACPI_0FH_CONTROL_RVO __BITS(28, 29)

sys/arch/x86/acpi/acpi_cpu_md.c

102

#define ACPI_0FH_CONTROL_IRT __BITS(30, 31)

sys/arch/x86/acpi/acpi_cpu_md.c

524

msr.ps_control_mask = __BITS(0, 15);

sys/arch/x86/acpi/acpi_cpu_md.c

527

msr.ps_status_mask = __BITS(0, 15);

sys/arch/x86/acpi/acpi_cpu_md.c

550

msr.ps_control_mask = __BITS(0, 2);

sys/arch/x86/acpi/acpi_cpu_md.c

553

msr.ps_status_mask = __BITS(0, 2);

sys/arch/x86/acpi/acpi_cpu_md.c

84

#define MSR_0FH_STATUS_CFID __BITS( 0, 5)

sys/arch/x86/acpi/acpi_cpu_md.c

85

#define MSR_0FH_STATUS_CVID __BITS(32, 36)

sys/arch/x86/acpi/acpi_cpu_md.c

86

#define MSR_0FH_STATUS_PENDING __BITS(31, 31)

sys/arch/x86/acpi/acpi_cpu_md.c

88

#define MSR_0FH_CONTROL_FID __BITS( 0, 5)

sys/arch/x86/acpi/acpi_cpu_md.c

89

#define MSR_0FH_CONTROL_VID __BITS( 8, 12)

sys/arch/x86/acpi/acpi_cpu_md.c

90

#define MSR_0FH_CONTROL_CHG __BITS(16, 16)

sys/arch/x86/acpi/acpi_cpu_md.c

91

#define MSR_0FH_CONTROL_CNT __BITS(32, 51)

sys/arch/x86/acpi/acpi_cpu_md.c

93

#define ACPI_0FH_STATUS_FID __BITS( 0, 5)

sys/arch/x86/acpi/acpi_cpu_md.c

94

#define ACPI_0FH_STATUS_VID __BITS( 6, 10)

sys/arch/x86/acpi/acpi_cpu_md.c

96

#define ACPI_0FH_CONTROL_FID __BITS( 0, 5)

sys/arch/x86/acpi/acpi_cpu_md.c

97

#define ACPI_0FH_CONTROL_VID __BITS( 6, 10)

sys/arch/x86/acpi/acpi_cpu_md.c

977

val = val & __BITS(0, 4);

sys/arch/x86/acpi/acpi_cpu_md.c

98

#define ACPI_0FH_CONTROL_VST __BITS(11, 17)

sys/arch/x86/acpi/acpi_cpu_md.c

99

#define ACPI_0FH_CONTROL_MVS __BITS(18, 19)

sys/arch/x86/include/dbregs.h

48

#define X86_DR6_MBZ __BITS(32, 63)

sys/arch/x86/include/dbregs.h

71

#define X86_DR7_DR0_CONDITION_MASK __BITS(16, 17)

sys/arch/x86/include/dbregs.h

72

#define X86_DR7_DR0_LENGTH_MASK __BITS(18, 19)

sys/arch/x86/include/dbregs.h

73

#define X86_DR7_DR1_CONDITION_MASK __BITS(20, 21)

sys/arch/x86/include/dbregs.h

74

#define X86_DR7_DR1_LENGTH_MASK __BITS(22, 23)

sys/arch/x86/include/dbregs.h

75

#define X86_DR7_DR2_CONDITION_MASK __BITS(24, 25)

sys/arch/x86/include/dbregs.h

76

#define X86_DR7_DR2_LENGTH_MASK __BITS(26, 27)

sys/arch/x86/include/dbregs.h

77

#define X86_DR7_DR3_CONDITION_MASK __BITS(28, 29)

sys/arch/x86/include/dbregs.h

78

#define X86_DR7_DR3_LENGTH_MASK __BITS(30, 31)

sys/arch/x86/include/dbregs.h

79

#define X86_DR7_MBZ __BITS(32, 63)

sys/arch/x86/include/i82489reg.h

114

# define LAPIC_DEST_MASK __BITS(19, 18)

sys/arch/x86/include/i82489reg.h

123

# define LAPIC_LVT_TMM __BITS(18, 17)

sys/arch/x86/include/i82489reg.h

153

#define LAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)

sys/arch/x86/include/i82489reg.h

154

#define LAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)

sys/arch/x86/include/i82489reg.h

157

#define LAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)

sys/arch/x86/include/i82489reg.h

165

# define LEAPIC_FR_ELC __BITS(23,16) /* Ext. Lvt Count RO */

sys/arch/x86/include/i82489reg.h

176

# define LEAPIC_SEOI_VEC __BITS(7,0)

sys/arch/x86/include/i82489reg.h

202

# define LEAPIC_LVTR_MSGTYPE __BITS(10,8) /* Message type */

sys/arch/x86/include/i82489reg.h

203

# define LEAPIC_LVTR_VEC __BITS(7,0) /* the intr. vector */

sys/arch/x86/include/i82489reg.h

83

#define LAPIC_VECTOR_MASK __BITS(7, 0)

sys/arch/x86/include/i82489reg.h

84

#define LAPIC_DLMODE_MASK __BITS(10, 8) /* Delivery Mode */

sys/arch/x86/include/specialreg.h

1014

#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */

sys/arch/x86/include/specialreg.h

1015

#define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */

sys/arch/x86/include/specialreg.h

1016

#define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */

sys/arch/x86/include/specialreg.h

1024

#define CPUID_AMD_SVM_REV __BITS(7,0)

sys/arch/x86/include/specialreg.h

1115

#define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */

sys/arch/x86/include/specialreg.h

1116

#define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */

sys/arch/x86/include/specialreg.h

1119

#define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */

sys/arch/x86/include/specialreg.h

1120

#define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */

sys/arch/x86/include/specialreg.h

1239

#define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */

sys/arch/x86/include/specialreg.h

1240

#define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */

sys/arch/x86/include/specialreg.h

1241

#define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of NorthBridge PMCs */

sys/arch/x86/include/specialreg.h

1242

#define CPUID_AXPERF_NUMCPC __BITS(23, 16) /* Num of UMC PMCs */

sys/arch/x86/include/specialreg.h

1251

#define CPUID_HWC_NWC __BITS(3, 0) /* Number of Workload Class IDs */

sys/arch/x86/include/specialreg.h

401

#define CPUID_BRAND_INDEX __BITS(7,0)

sys/arch/x86/include/specialreg.h

402

#define CPUID_CLFLUSH_SIZE __BITS(15,8)

sys/arch/x86/include/specialreg.h

403

#define CPUID_HTT_CORES __BITS(23,16)

sys/arch/x86/include/specialreg.h

404

#define CPUID_LOCAL_APIC_ID __BITS(31,24)

sys/arch/x86/include/specialreg.h

412

#define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */

sys/arch/x86/include/specialreg.h

417

#define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */

sys/arch/x86/include/specialreg.h

420

#define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */

sys/arch/x86/include/specialreg.h

421

#define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */

sys/arch/x86/include/specialreg.h

424

#define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */

sys/arch/x86/include/specialreg.h

425

#define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */

sys/arch/x86/include/specialreg.h

426

#define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */

sys/arch/x86/include/specialreg.h

440

#define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */

sys/arch/x86/include/specialreg.h

442

#define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */

sys/arch/x86/include/specialreg.h

492

#define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */

sys/arch/x86/include/specialreg.h

572

#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */

sys/arch/x86/include/specialreg.h

678

#define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */

sys/arch/x86/include/specialreg.h

679

#define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */

sys/arch/x86/include/specialreg.h

680

#define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */

sys/arch/x86/include/specialreg.h

681

#define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */

sys/arch/x86/include/specialreg.h

707

#define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */

sys/arch/x86/include/specialreg.h

708

#define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */

sys/arch/x86/include/specialreg.h

724

#define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */

sys/arch/x86/include/specialreg.h

726

#define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */

sys/arch/x86/include/specialreg.h

727

#define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */

sys/arch/x86/include/specialreg.h

774

#define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */

sys/arch/x86/include/specialreg.h

779

#define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */

sys/arch/x86/include/specialreg.h

780

#define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */

sys/arch/x86/include/specialreg.h

785

#define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */

sys/arch/x86/include/specialreg.h

792

#define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */

sys/arch/x86/include/specialreg.h

794

#define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */

sys/arch/x86/include/specialreg.h

801

#define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */

sys/arch/x86/include/specialreg.h

802

#define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */

sys/arch/x86/include/specialreg.h

816

#define CPUID_TILE_P1_TOTAL_B __BITS(15, 0)

sys/arch/x86/include/specialreg.h

817

#define CPUID_TILE_P1_B_PERTILE __BITS(31, 16)

sys/arch/x86/include/specialreg.h

818

#define CPUID_TILE_P1_B_PERLOW __BITS(15, 0)

sys/arch/x86/include/specialreg.h

819

#define CPUID_TILE_P1_MAXNAMES __BITS(31, 16)

sys/arch/x86/include/specialreg.h

820

#define CPUID_TILE_P1_MAXROWS __BITS(15, 0)

sys/arch/x86/include/specialreg.h

828

#define CPUID_TMUL_MAXK __BITS(7, 0) /* Rows or columns */

sys/arch/x86/include/specialreg.h

829

#define CPUID_TMUL_MAXN __BITS(23, 8) /* Column bytes */

sys/arch/x86/include/specialreg.h

93

#define CR3_PCID __BITS(11,0)

sys/arch/x86/include/specialreg.h

94

#define CR3_PA __BITS(62,12)

sys/arch/x86/pci/amdtemp.c

111

#define F10_TEMP_CURTMP __BITS(31,21)

sys/arch/x86/pci/amdzentemp.c

77

#define F10_TEMP_CURTMP __BITS(31,21) /* XXX same as amdtemp.c */

sys/arch/x86/pci/amdzentemp.c

79

#define F15M60_CURTMP_TJSEL __BITS(17,16)

sys/arch/x86/pci/lpssreg.h

35

#define LPSS_RESET_CTRL __BITS(1,0)

sys/arch/x86/pci/lpssreg.h

40

#define LPSS_ACTIVELTR_SSCALE __BITS(12,10)

sys/arch/x86/pci/lpssreg.h

43

#define LPSS_ACTIVELTR_SVALUE __BITS(9,0)

sys/arch/x86/pci/lpssreg.h

46

#define LPSS_IDLELTR_SSCALE __BITS(12,10)

sys/arch/x86/pci/lpssreg.h

49

#define LPSS_IDLELTR_SVALUE __BITS(9,0)

sys/arch/x86/pci/lpssreg.h

53

#define LPSS_TXACK_CNT __BITS(23,0)

sys/arch/x86/pci/lpssreg.h

57

#define LPSS_RXACK_CNT __BITS(23,0)

sys/arch/x86/pci/lpssreg.h

67

#define LPSS_CLKGATE_DMA __BITS(3,2)

sys/arch/x86/pci/lpssreg.h

71

#define LPSS_CLKGATE_CTRL __BITS(1,0)

sys/arch/x86/pci/lpssreg.h

88

#define LPSS_CAP_TYPE __BITS(7,4)

sys/arch/x86/pci/lpssreg.h

92

#define LPSS_CAP_INSTANCE __BITS(3,0)

sys/arch/x86/pci/pci_ranges.c

285

base = base0 & __BITS(31, 2);

sys/arch/x86/pci/pci_ranges.c

286

limit = limit0 & __BITS(31, 2);

sys/arch/x86/x86/coretemp.c

100

#define MSR_THERM_INTR_TRIP2_VAL __BITS(16, 22)

sys/arch/x86/x86/coretemp.c

103

#define MSR_TEMP_TARGET_READOUT __BITS(16, 23)

sys/arch/x86/x86/coretemp.c

89

#define MSR_THERM_STATUS_READOUT __BITS(16, 22)

sys/arch/x86/x86/coretemp.c

90

#define MSR_THERM_STATUS_RESOLUTION __BITS(27, 30)

sys/arch/x86/x86/coretemp.c

98

#define MSR_THERM_INTR_TRIP1_VAL __BITS(8, 14)

sys/arch/x86/x86/cpu_rng.c

197

#define VIA_RNG_STATUS_NBYTES __BITS(3,0)

sys/arch/x86/x86/cpu_rng.c

198

#define VIA_RNG_STATUS_MSR110B __BITS(31,5)

sys/arch/x86/x86/cpu_topology.c

181

const u_int node_id = apic_id & __BITS(0, 2);

sys/arch/x86/x86/cpu_topology.c

207

u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1);

sys/arch/x86/x86/cpu_topology.c

211

u_int smt_mask = __BITS(0, smt_bits - 1);

sys/arch/x86/x86/pmap.c

6087

#define EPT_T __BITS(5,3) /* type */

sys/crypto/aes/aes_ccm.c

60

#define CCM_AFLAGS_M __BITS(5,3)

sys/crypto/aes/aes_ccm.c

61

#define CCM_AFLAGS_L __BITS(2,0)

sys/crypto/aes/aes_ccm.c

64

#define CCM_EFLAGS_L __BITS(2,0)

sys/dev/acpi/acpi_cpu.h

298

__BITS(reg->reg_bitoffset + reg->reg_bitwidth - 1,

sys/dev/acpi/acpi_cpu.h

333

__BITS(reg->reg_bitoffset + reg->reg_bitwidth - 1,

sys/dev/acpi/acpi_pcc.c

277

mask = __BITS(reg->BitOffset + reg->BitWidth - 1,

sys/dev/acpi/acpi_pcc.c

316

mask = __BITS(reg->BitOffset + reg->BitWidth - 1,

sys/dev/acpi/amdgpio.c

503

status &= __BITS(0, AMDGPIO_INTR_STATUS_NBITS - 1);

sys/dev/acpi/apei.c

633

dsr = __SHIFTOUT(dcsr, __BITS(31,16));

sys/dev/acpi/apei_cper.h

200

CPER_MEMORY_ERROR_BANK_ADDRESS = __BITS(7,0),

sys/dev/acpi/apei_cper.h

201

CPER_MEMORY_ERROR_BANK_GROUP = __BITS(15,8),

sys/dev/acpi/apei_cper.h

233

CPER_MEMORY_ERROR_EXTENDED_CHIPID = __BITS(7,5),

sys/dev/acpi/qcomgpioreg.h

27

#define TLMM_GPIO_CTL_MUX __BITS(5,2)

sys/dev/acpi/qcomgpioreg.h

35

#define TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK __BITS(7,5)

sys/dev/acpi/qcomgpioreg.h

38

#define TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK __BITS(3,2)

sys/dev/acpi/qcomipcc.c

34

#define IPCC_SIGNAL_ID_MASK __BITS(15,0)

sys/dev/acpi/qcomipcc.c

35

#define IPCC_CLIENT_ID_MASK __BITS(31,16)

sys/dev/audio/audio_dai.h

35

#define AUDIO_DAI_FORMAT_MASK __BITS(3,0)

sys/dev/audio/audio_dai.h

44

#define AUDIO_DAI_POLARITY_MASK __BITS(5,4)

sys/dev/audio/audio_dai.h

52

#define AUDIO_DAI_CLOCK_MASK __BITS(9,8)

sys/dev/cadence/cemacreg.h

101

#define GEM_DMA_CFG_AHB_FIXED_BURST_LEN __BITS(4, 0)

sys/dev/cadence/cemacreg.h

141

#define ETH_CFG_CLK __BITS(11, 10) /* clock */

sys/dev/cadence/cemacreg.h

157

#define GEM_CFG_CLK __BITS(20, 18)

sys/dev/cadence/cemacreg.h

166

#define GEM_CFG_DBW __BITS(22, 21)

sys/dev/cadence/cemacreg.h

219

#define ETH_MAN_RW __BITS(29, 28)

sys/dev/cadence/cemacreg.h

223

#define ETH_MAN_PHYA __BITS(27, 23) /* PHY address (normally 0) */

sys/dev/cadence/cemacreg.h

225

#define ETH_MAN_REGA __BITS(22, 18)

sys/dev/cadence/cemacreg.h

227

#define ETH_MAN_CODE __BITS(17, 16) /* must be 0b10 */

sys/dev/cadence/cemacreg.h

230

#define ETH_MAN_DATA __BITS(15, 0) /* data to be written to the PHY */

sys/dev/cadence/cemacreg.h

259

#define ETH_RDSC_I_CHKSUM __BITS(23, 22)

sys/dev/cadence/cemacreg.h

264

#define ETH_RDSC_I_LEN __BITS(13, 0)

sys/dev/cadence/cemacreg.h

271

#define ETH_TDSC_I_CHKSUM __BITS(22, 20)

sys/dev/cadence/cemacreg.h

282

#define ETH_TDSC_I_LEN __BITS(13, 0)

sys/dev/cadence/cemacreg.h

95

#define GEM_DMA_CFG_RX_BUF_SIZE __BITS(23, 16)

sys/dev/cadence/cemacreg.h

98

#define GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL __BITS(9, 8)

sys/dev/fdt/arasan_sdhc_fdt.c

49

#define RK3399_CORECFG_BASECLKFREQ __BITS(15,8)

sys/dev/fdt/arasan_sdhc_fdt.c

51

#define RK3399_CORECFG_TUNINGCOUNT __BITS(5,0)

sys/dev/fdt/arasan_sdhc_fdt.c

53

#define RK3399_CORECFG_CLOCKMULTIPLIER __BITS(7,0)

sys/dev/fdt/dwc3_fdt.c

49

#define GCTL_PRTCAP __BITS(13,12)

sys/dev/fdt/dwc3_fdt.c

59

#define DWC3_SNPSID_REV __BITS(15,0)

sys/dev/fdt/dwc3_fdt.c

64

#define GUSB2PHYCFG_USBTRDTIM __BITS(13,10)

sys/dev/fdt/dwc3_fdt.c

76

#define DCFG_SPEED __BITS(2,0)

sys/dev/i2c/act8846.c

66

#define ACT_VSET_VSET __BITS(5,0)

sys/dev/i2c/anxedp.c

59

#define ANX_AUX_LENGTH __BITS(7,4)

sys/dev/i2c/anxedp.c

60

#define ANX_AUX_TX_COMM __BITS(3,0)

sys/dev/i2c/as3722.c

64

#define AS3722_GPIO0_CTRL_IOSF __BITS(6,3)

sys/dev/i2c/as3722.c

67

#define AS3722_GPIO0_CTRL_MODE __BITS(2,0)

sys/dev/i2c/as3722.c

77

#define AS3722_WATCHDOG_CTRL_MODE __BITS(2,1)

sys/dev/i2c/as3722.c

81

#define AS3722_WATCHDOG_TIMER_TIMER __BITS(6,0)

sys/dev/i2c/as3722.c

84

#define AS3722_WATCHDOG_SIGNAL_PWM_DIV __BITS(7,6)

sys/dev/i2c/axp20x.c

105

#define AXP_LDO3_VOLT_MASK __BITS(0,6)

sys/dev/i2c/axp20x.c

113

#define AXP_BKUP_CTRL_VOLT_MASK __BITS(5,6)

sys/dev/i2c/axp20x.c

125

#define AXP_BKUP_CTRL_CURR_MASK __BITS(0,1)

sys/dev/i2c/axp20x.c

70

#define AXP_DCDC2_VOLT_MASK __BITS(0,5)

sys/dev/i2c/axp20x.c

76

#define AXP_DCDC3_VOLT_MASK __BITS(0,6)

sys/dev/i2c/axp20x.c

80

#define AXP_LDO2_VOLT_MASK __BITS(4,7)

sys/dev/i2c/axp20x.c

82

#define AXP_LDO4_VOLT_MASK __BITS(0,3)

sys/dev/i2c/axp809.c

82

GPIO1_CTRL, __BIT(0), GPIO1LDO_CTRL, __BITS(4,0)),

sys/dev/i2c/axppmic.c

108

#define AXP_BATT_CAP_WARN_LV1 __BITS(7,4)

sys/dev/i2c/axppmic.c

109

#define AXP_BATT_CAP_WARN_LV2 __BITS(3,0)

sys/dev/i2c/axppmic.c

176

0x12, __BIT(3), 0x15, __BITS(4,0)),

sys/dev/i2c/axppmic.c

178

0x12, __BIT(4), 0x16, __BITS(4,0)),

sys/dev/i2c/axppmic.c

180

0x12, __BIT(5), 0x17, __BITS(4,0)),

sys/dev/i2c/axppmic.c

182

0x12, __BIT(6), 0x18, __BITS(4,0)),

sys/dev/i2c/axppmic.c

184

0x12, __BIT(0), 0x19, __BITS(4,0)),

sys/dev/i2c/axppmic.c

186

0x12, __BIT(1), 0x1a, __BITS(4,0)),

sys/dev/i2c/axppmic.c

188

0x12, __BIT(2), 0x1b, __BITS(4,0)),

sys/dev/i2c/axppmic.c

190

0x13, __BIT(2), 0x1c, __BITS(3,0)),

sys/dev/i2c/axppmic.c

192

0x13, __BIT(3), 0x1d, __BITS(3,0)),

sys/dev/i2c/axppmic.c

194

0x10, __BIT(0), 0x20, __BITS(4,0)),

sys/dev/i2c/axppmic.c

196

0x10, __BIT(1), 0x21, __BITS(6,0)),

sys/dev/i2c/axppmic.c

198

0x10, __BIT(2), 0x22, __BITS(6,0)),

sys/dev/i2c/axppmic.c

200

0x10, __BIT(3), 0x23, __BITS(6,0)),

sys/dev/i2c/axppmic.c

202

0x10, __BIT(4), 0x24, __BITS(6,0)),

sys/dev/i2c/axppmic.c

204

0x10, __BIT(5), 0x25, __BITS(6,0)),

sys/dev/i2c/axppmic.c

206

0x13, __BIT(5), 0x28, __BITS(4,0)),

sys/dev/i2c/axppmic.c

208

0x13, __BIT(6), 0x29, __BITS(4,0)),

sys/dev/i2c/axppmic.c

210

0x13, __BIT(7), 0x2a, __BITS(4,0)),

sys/dev/i2c/axppmic.c

215

0x10, __BIT(0), 0x12, __BITS(6,0)),

sys/dev/i2c/axppmic.c

217

0x10, __BIT(1), 0x13, __BITS(4,0)),

sys/dev/i2c/axppmic.c

219

0x10, __BIT(2), 0x14, __BITS(6,0)),

sys/dev/i2c/axppmic.c

221

0x10, __BIT(3), 0x15, __BITS(5,0)),

sys/dev/i2c/axppmic.c

223

0x10, __BIT(4), 0x16, __BITS(4,0)),

sys/dev/i2c/axppmic.c

225

0x10, __BIT(5), 0x17, __BITS(4,0)),

sys/dev/i2c/axppmic.c

227

0x10, __BIT(6), 0x18, __BITS(4,0)),

sys/dev/i2c/axppmic.c

229

0x10, __BIT(7), 0x19, __BITS(4,0)),

sys/dev/i2c/axppmic.c

231

0x11, __BIT(0), 0x20, __BITS(3,0)),

sys/dev/i2c/axppmic.c

233

0x11, __BIT(1), 0x21, __BITS(3,0)),

sys/dev/i2c/axppmic.c

235

0x11, __BIT(2), 0x22, __BITS(3,0)),

sys/dev/i2c/axppmic.c

237

0x11, __BIT(3), 0x23, __BITS(3,0)),

sys/dev/i2c/axppmic.c

239

0x11, __BIT(4), 0x24, __BITS(4,0)),

sys/dev/i2c/axppmic.c

241

0x11, __BIT(5), 0x25, __BITS(4,0)),

sys/dev/i2c/axppmic.c

243

0x11, __BIT(6), 0x26, __BITS(4,0)),

sys/dev/i2c/axppmic.c

248

0x10, __BIT(0), 0x1c, __BITS(2,0)),

sys/dev/i2c/axppmic.c

250

0x10, __BIT(1), 0x21, __BITS(4,0)),

sys/dev/i2c/axppmic.c

252

0x10, __BIT(2), 0x22, __BITS(5,0)),

sys/dev/i2c/axppmic.c

254

0x10, __BIT(3), 0x23, __BITS(5,0)),

sys/dev/i2c/axppmic.c

256

0x10, __BIT(4), 0x24, __BITS(5,0)),

sys/dev/i2c/axppmic.c

258

0x10, __BIT(5), 0x25, __BITS(4,0)),

sys/dev/i2c/axppmic.c

260

0x10, __BIT(6), 0x28, __BITS(4,0)),

sys/dev/i2c/axppmic.c

262

0x10, __BIT(7), 0x29, __BITS(4,0)),

sys/dev/i2c/axppmic.c

264

0x12, __BIT(0), 0x19, __BITS(4,0)),

sys/dev/i2c/axppmic.c

266

0x12, __BIT(1), 0x1a, __BITS(4,0)),

sys/dev/i2c/axppmic.c

268

0x12, __BIT(2), 0x1b, __BITS(4,0)),

sys/dev/i2c/axppmic.c

270

0x12, __BIT(3), 0x15, __BITS(4,0)),

sys/dev/i2c/axppmic.c

272

0x12, __BIT(4), 0x16, __BITS(4,0)),

sys/dev/i2c/axppmic.c

274

0x12, __BIT(5), 0x2a, __BITS(4,0)),

sys/dev/i2c/axppmic.c

279

0x12, __BIT(7), 0x21, __BITS(4,0)),

sys/dev/i2c/axppmic.c

281

0x90, __BITS(3,0), 0x3, 0x7, 0x91, __BITS(4,0)),

sys/dev/i2c/axppmic.c

283

0x92, __BITS(3,0), 0x3, 0x7, 0x93, __BITS(4,0)),

sys/dev/i2c/axppmic.c

288

0x12, __BIT(3), 0x15, __BITS(4,0)),

sys/dev/i2c/axppmic.c

290

0x12, __BIT(4), 0x16, __BITS(4,0)),

sys/dev/i2c/axppmic.c

292

0x12, __BIT(5), 0x17, __BITS(4,0)),

sys/dev/i2c/axppmic.c

294

0x12, __BIT(6), 0x18, __BITS(4,0)),

sys/dev/i2c/axppmic.c

296

0x12, __BIT(0), 0x19, __BITS(4,0)),

sys/dev/i2c/axppmic.c

298

0x12, __BIT(1), 0x1a, __BITS(4,0)),

sys/dev/i2c/axppmic.c

300

0x12, __BIT(2), 0x1b, __BITS(4,0)),

sys/dev/i2c/axppmic.c

302

0x13, __BIT(2), 0x1c, __BITS(3,0)),

sys/dev/i2c/axppmic.c

304

0x13, __BIT(3), 0x1d, __BITS(3,0)),

sys/dev/i2c/axppmic.c

306

0x10, __BIT(0), 0x20, __BITS(4,0)),

sys/dev/i2c/axppmic.c

308

0x10, __BIT(1), 0x21, __BITS(6,0)),

sys/dev/i2c/axppmic.c

310

0x10, __BIT(2), 0x22, __BITS(6,0)),

sys/dev/i2c/axppmic.c

312

0x10, __BIT(3), 0x23, __BITS(6,0)),

sys/dev/i2c/axppmic.c

314

0x10, __BIT(4), 0x24, __BITS(6,0)),

sys/dev/i2c/axppmic.c

316

0x10, __BIT(5), 0x25, __BITS(6,0)),

sys/dev/i2c/axppmic.c

318

0x10, __BIT(6), 0x26, __BITS(6,0)),

sys/dev/i2c/axppmic.c

320

0x13, __BIT(5), 0x28, __BITS(4,0)),

sys/dev/i2c/axppmic.c

322

0x13, __BIT(6), 0x29, __BITS(4,0)),

sys/dev/i2c/axppmic.c

324

0x13, __BIT(7), 0x2a, __BITS(4,0)),

sys/dev/i2c/axppmic.c

329

0x13, __BITS(4, 0),

sys/dev/i2c/axppmic.c

334

0x14, __BITS(6, 0),

sys/dev/i2c/axppmic.c

339

0x15, __BITS(6, 0),

sys/dev/i2c/axppmic.c

344

0x16, __BITS(6, 0),

sys/dev/i2c/axppmic.c

351

0x17, __BITS(6, 0),

sys/dev/i2c/axppmic.c

354

0x18, __BITS(4, 0),

sys/dev/i2c/axppmic.c

357

0x19, __BITS(4, 0),

sys/dev/i2c/axppmic.c

360

0x20, __BITS(4, 0),

sys/dev/i2c/axppmic.c

363

0x21, __BITS(4, 0),

sys/dev/i2c/axppmic.c

366

0x22, __BITS(4, 0),

sys/dev/i2c/axppmic.c

369

0x23, __BITS(4, 0),

sys/dev/i2c/axppmic.c

372

0x24, __BITS(4, 0),

sys/dev/i2c/axppmic.c

375

0x25, __BITS(4, 0),

sys/dev/i2c/axppmic.c

378

0x26, __BITS(4, 0),

sys/dev/i2c/axppmic.c

381

0x27, __BITS(4, 0),

sys/dev/i2c/axppmic.c

384

0x28, __BITS(4, 0),

sys/dev/i2c/axppmic.c

387

0x29, __BITS(4, 0),

sys/dev/i2c/axppmic.c

390

0x2a, __BITS(4, 0),

sys/dev/i2c/axppmic.c

393

0x2b, __BITS(4, 0),

sys/dev/i2c/axppmic.c

396

0x2d, __BITS(5, 0),

sys/dev/i2c/axppmic.c

399

0x2e, __BITS(3, 0),

sys/dev/i2c/axppmic.c

511

.acinirq = AXPPMIC_IRQ(1, __BITS(6,5)),

sys/dev/i2c/axppmic.c

512

.vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)),

sys/dev/i2c/axppmic.c

513

.battirq = AXPPMIC_IRQ(2, __BITS(7,6)),

sys/dev/i2c/axppmic.c

514

.chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)),

sys/dev/i2c/axppmic.c

515

.chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)),

sys/dev/i2c/axppmic.c

558

.acinirq = AXPPMIC_IRQ(1, __BITS(6,5)),

sys/dev/i2c/axppmic.c

559

.vbusirq = AXPPMIC_IRQ(1, __BITS(3,2)),

sys/dev/i2c/axppmic.c

560

.battirq = AXPPMIC_IRQ(2, __BITS(7,6)),

sys/dev/i2c/axppmic.c

561

.chargeirq = AXPPMIC_IRQ(2, __BITS(3,2)),

sys/dev/i2c/axppmic.c

562

.chargestirq = AXPPMIC_IRQ(4, __BITS(1,0)),

sys/dev/i2c/axppmic.c

83

#define AXP_GPIO_CTRL_FUNC_MASK __BITS(2,0)

sys/dev/i2c/axppmic.c

94

#define AXP_BATT_CAP_PERCENT __BITS(6,0)

sys/dev/i2c/cwfg.c

49

#define VCELL_HI __BITS(5,0)

sys/dev/i2c/cwfg.c

51

#define VCELL_LO __BITS(7,0)

sys/dev/i2c/cwfg.c

56

#define RTT_HI __BITS(4,0)

sys/dev/i2c/cwfg.c

58

#define RTT_LO __BITS(7,0)

sys/dev/i2c/cwfg.c

60

#define CONFIG_ATHD __BITS(7,3)

sys/dev/i2c/cwfg.c

63

#define MODE_SLEEP __BITS(7,6)

sys/dev/i2c/cwfg.c

66

#define MODE_QSTRT __BITS(5,4)

sys/dev/i2c/cwfg.c

67

#define MODE_POR __BITS(3,0)

sys/dev/i2c/es8316ac.c

101

#define DACVOL_L_DACVOLUME __BITS(7,0)

sys/dev/i2c/es8316ac.c

103

#define DACVOL_R_DACVOLUME __BITS(7,0)

sys/dev/i2c/es8316ac.c

48

#define RESET_ALL __BITS(5,0)

sys/dev/i2c/es8316ac.c

63

#define SD_FMT_WL __BITS(4,2)

sys/dev/i2c/es8316ac.c

65

#define SD_FMT_MASK __BITS(1,0)

sys/dev/i2c/es8316ac.c

79

#define HPMIXVOL_LHPMIXVOL __BITS(7,4)

sys/dev/i2c/es8316ac.c

80

#define HPMIXVOL_RHPMIXVOL __BITS(3,0)

sys/dev/i2c/es8316ac.c

88

#define HPVOL_HPLVOL __BITS(5,4)

sys/dev/i2c/es8316ac.c

90

#define HPVOL_HPRVOL __BITS(1,0)

sys/dev/i2c/fan53555.c

48

#define VSEL_NSEL __BITS(5,0)

sys/dev/i2c/fan53555.c

51

#define CONTROL_SLEW __BITS(6,4)

sys/dev/i2c/fan53555.c

54

#define ID1_VENDOR __BITS(7,5)

sys/dev/i2c/fan53555.c

55

#define ID1_DIE_ID __BITS(3,0)

sys/dev/i2c/fan53555.c

59

#define ID2_DIE_REV __BITS(3,0)

sys/dev/i2c/i2cvar.h

53

#define I2C_F_SPEED __BITS(28,31) /* I2C transfer speed selector */

sys/dev/i2c/max77620.c

47

#define MAX_GPIO_DEBOUNCE __BITS(7,6)

sys/dev/i2c/max77620.c

48

#define MAX_GPIO_INT __BITS(5,4)

sys/dev/i2c/mcp980xreg.h

44

#define MCP980X_AMBIENT_TEMP_DEGREES __BITS(8,14)

sys/dev/i2c/mcp980xreg.h

50

#define MCP980X_CONFIG_ADC_RES __BITS(5,6)

sys/dev/i2c/rkpmic.c

103

.vsel_reg = 0x2f, .vsel_mask = __BITS(5,0),

sys/dev/i2c/rkpmic.c

107

.vsel_reg = 0x33, .vsel_mask = __BITS(5,0),

sys/dev/i2c/rkpmic.c

113

.vsel_reg = 0x38, .vsel_mask = __BITS(3,0),

sys/dev/i2c/rkpmic.c

119

.vsel_reg = 0x3b, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

123

.vsel_reg = 0x3d, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

127

.vsel_reg = 0x3f, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

141

.vsel_reg = 0x2f, .vsel_mask = __BITS(5,0),

sys/dev/i2c/rkpmic.c

145

.vsel_reg = 0x33, .vsel_mask = __BITS(5,0),

sys/dev/i2c/rkpmic.c

151

.vsel_reg = 0x38, .vsel_mask = __BITS(3,0),

sys/dev/i2c/rkpmic.c

157

.vsel_reg = 0x3b, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

161

.vsel_reg = 0x3d, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

165

.vsel_reg = 0x3f, .vsel_mask = __BITS(3,0),

sys/dev/i2c/rkpmic.c

169

.vsel_reg = 0x41, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

173

.vsel_reg = 0x43, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

177

.vsel_reg = 0x45, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

181

.vsel_reg = 0x47, .vsel_mask = __BITS(4,0),

sys/dev/i2c/rkpmic.c

185

.vsel_reg = 0x49, .vsel_mask = __BITS(4,0),

sys/dev/i2c/sy8106a.c

46

#define SEL_VOLTAGE __BITS(6,0)

sys/dev/i2c/tcakp.c

207

mask = __BITS(sc->sc_rows - 1, 0);

sys/dev/i2c/tcakp.c

208

mask += __BITS(sc->sc_cols - 1, 0) << 8;

sys/dev/i2c/tcakp.c

77

#define KEY_LCK_EC_KEC __BITS(3,0)

sys/dev/i2c/tcakp.c

80

#define TCA_EVENT_CODE __BITS(6,0)

sys/dev/i2c/tps65217pmicreg.h

109

#define TPS65217PMIC_DEFX_VOLTAGE_16 __BITS(0,3)

sys/dev/i2c/tps65217pmicreg.h

110

#define TPS65217PMIC_DEFX_VOLTAGE_32 __BITS(0,4)

sys/dev/i2c/tps65217pmicreg.h

111

#define TPS65217PMIC_DEFX_VOLTAGE_64 __BITS(0,5)

sys/dev/i2c/tps65217pmicreg.h

48

#define TPS65217PMIC_PPATH_IUSB __BITS(0,1)

sys/dev/i2c/tps65217pmicreg.h

53

#define TPS65217PMIC_PPATH_IAC __BITS(2,3)

sys/dev/i2c/tps65217pmicreg.h

71

#define TPS65217PMIC_WLEDCTRL1_FDIM __BITS(1,0)

sys/dev/i2c/tps65217pmicreg.h

80

#define TPS65217PMIC_WLEDCTRL2_DUTY __BITS(6,0)

sys/dev/i2c/twl4030.c

69

#define PUPD_BITS(pin) __BITS((pin) % 4 + 1, (pin) % 4)

sys/dev/ic/ahcisatareg.h

146

#define AHCI_VS_MJR(v) ((unsigned int)__SHIFTOUT(v, __BITS(31, 16)))

sys/dev/ic/ahcisatareg.h

147

#define AHCI_VS_MNR(v) ((unsigned int)__SHIFTOUT(v, __BITS(15, 8)) * 10 + (unsigned int)__SHIFTOUT(v, __BITS(7, 0) * 1))

sys/dev/ic/ahcisatareg.h

237

#define AHCI_P_CMD_CCS_MASK __BITS(12, 8) /* current command slot */

sys/dev/ic/al2210reg.h

103

#define AL2210_RECEIVER_AGCDET_N_MASK __BITS(14, 13)

sys/dev/ic/al2210reg.h

111

#define AL2210_RECEIVER_BW_SEL_MASK __BITS(4, 2)

sys/dev/ic/al2210reg.h

126

#define AL2210_TRANSMITTER_PABIAS2_MASK __BITS(7, 4)

sys/dev/ic/al2210reg.h

131

#define AL2210_TRANSMITTER_PABIAS1_MASK __BITS(3, 0)

sys/dev/ic/al2210reg.h

147

#define AL2210_CONFIG3_LNA_GAIN_PATT_1MHZ __BITS(15)

sys/dev/ic/al2210reg.h

148

#define AL2210_CONFIG3_LNA_GAIN_PATT_100KHZ __BITS(14)

sys/dev/ic/al2210reg.h

149

#define AL2210_CONFIG3_RXON_PATT_1MHZ __BITS(13)

sys/dev/ic/al2210reg.h

150

#define AL2210_CONFIG3_RXON_PATT_1OOKHZ __BITS(12)

sys/dev/ic/al2210reg.h

152

#define AL2210_CONFIG3_CNT_1M_AGC_MASK __BITS(11, 8)

sys/dev/ic/al2210reg.h

153

#define AL2210_CONFIG3_CNT_1M_LNA_MASK __BITS(7, 4)

sys/dev/ic/al2210reg.h

154

#define AL2210_CONFIG3_CNT_1M_RXON_MASK __BITS(3, 0)

sys/dev/ic/al2210reg.h

158

#define AL2210_CONFIG4_CNT_100K_AGC_MASK __BITS(11, 8)

sys/dev/ic/al2210reg.h

159

#define AL2210_CONFIG4_CNT_100K_LNA_MASK __BITS(7, 4)

sys/dev/ic/al2210reg.h

160

#define AL2210_CONFIG4_CNT_100K_RXON_MASK __BITS(3, 0)

sys/dev/ic/al2210reg.h

163

#define AL2210_CONFIG5_TXF_BW_MASK __BITS(9, 8)

sys/dev/ic/al2210reg.h

49

#define AL2210_TWI_DATA_MASK __BITS(23, 4)

sys/dev/ic/al2210reg.h

50

#define AL2210_TWI_ADDR_MASK __BITS(3, 0)

sys/dev/ic/al2210reg.h

60

#define AL2210_CHANNEL_B_MASK __BITS(10, 5) /* Counter B */

sys/dev/ic/al2210reg.h

75

#define AL2210_CHANNEL_A_MASK __BITS(4, 0) /* Counter A */

sys/dev/ic/al2210reg.h

92

#define AL2210_SYNTHESIZER_R_MASK __BITS(4, 0) /* Reference

sys/dev/ic/al2210reg.h

97

#define AL2210_RECEIVER_AGCDET_P_MASK __BITS(16, 15)

sys/dev/ic/anx_dp.c

110

#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) __SHIFTIN((x), __BITS(10,8))

sys/dev/ic/anx_dp.c

111

#define AUX_HW_RETRY_INTERVAL_600_US __SHIFTIN(0, __BITS(4,3))

sys/dev/ic/anx_dp.c

112

#define AUX_HW_RETRY_INTERVAL_800_US __SHIFTIN(1, __BITS(4,3))

sys/dev/ic/anx_dp.c

113

#define AUX_HW_RETRY_INTERVAL_1000_US __SHIFTIN(2, __BITS(4,3))

sys/dev/ic/anx_dp.c

114

#define AUX_HW_RETRY_INTERVAL_1800_US __SHIFTIN(3, __BITS(4,3))

sys/dev/ic/anx_dp.c

115

#define AUX_HW_RETRY_COUNT_SEL(x) __SHIFTIN((x), __BITS(2,0))

sys/dev/ic/anx_dp.c

146

#define SW_TRAINING_PATTERN_SET_PTN2 __SHIFTIN(2, __BITS(1,0))

sys/dev/ic/anx_dp.c

147

#define SW_TRAINING_PATTERN_SET_PTN1 __SHIFTIN(1, __BITS(1,0))

sys/dev/ic/anx_dp.c

150

#define PRE_EMPHASIS_SET(x) __SHIFTIN((x), __BITS(4,3))

sys/dev/ic/anx_dp.c

152

#define DRIVE_CURRENT_SET(x) __SHIFTIN((x), __BITS(1,0))

sys/dev/ic/anx_dp.c

166

#define AUX_STATUS(x) __SHIFTOUT((x), __BITS(3,0))

sys/dev/ic/anx_dp.c

170

#define DEFER_COUNT(x) __SHIFTIN((x), __BITS(6,0))

sys/dev/ic/anx_dp.c

176

#define BUF_DATA_COUNT(x) __SHIFTIN((x), __BITS(4,0))

sys/dev/ic/anx_dp.c

178

#define AUX_LENGTH(x) __SHIFTIN((x) - 1, __BITS(7,4))

sys/dev/ic/anx_dp.c

179

#define AUX_TX_COMM(x) __SHIFTOUT(x, __BITS(3,0))

sys/dev/ic/anx_dp.c

93

#define DP_ALL_PD __BITS(7,0)

sys/dev/ic/atw.c

1960

(ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0))

sys/dev/ic/atwreg.h

1000

#define ATW_RXSTAT_RXDR_MASK __BITS(15,12) /* RX data rate */

sys/dev/ic/atwreg.h

1001

#define ATW_RXSTAT_FL_MASK __BITS(11,0) /* RX frame length, last

sys/dev/ic/atwreg.h

143

#define ATW_PAR_RAP_MASK __BITS(17, 18) /* receive auto-polling in

sys/dev/ic/atwreg.h

146

#define ATW_PAR_CAL_MASK __BITS(14, 15) /* cache alignment */

sys/dev/ic/atwreg.h

154

#define ATW_PAR_PBL_MASK __BITS(8, 13) /* programmable burst length */

sys/dev/ic/atwreg.h

163

#define ATW_PAR_DSL_MASK __BITS(2, 6) /* descriptor skip length */

sys/dev/ic/atwreg.h

168

#define ATW_FRCTL_VER_MASK __BITS(29, 30) /* protocol version */

sys/dev/ic/atwreg.h

197

#define ATW_FRCTL_AID_MASK __BITS(0, 15) /* STA Association ID */

sys/dev/ic/atwreg.h

271

#define ATW_NAR_TR_MASK __BITS(14, 15) /* TX threshold */

sys/dev/ic/atwreg.h

279

#define ATW_NAR_OM_MASK __BITS(10, 11) /* operating mode */

sys/dev/ic/atwreg.h

331

#define ATW_LPC_LPC_MASK __BITS(0, 15) /* lost packet counter */

sys/dev/ic/atwreg.h

333

#define ATW_TEST1_RRA_MASK __BITS(20,12)

sys/dev/ic/atwreg.h

334

#define ATW_TEST1_RWA_MASK __BITS(10,2)

sys/dev/ic/atwreg.h

340

#define ATW_TEST1_DBGREAD_MASK __BITS(30,28) /* "control of read data,

sys/dev/ic/atwreg.h

343

#define ATW_TEST1_TXWP_MASK __BITS(27,25) /* select ATW_WTDP content? */

sys/dev/ic/atwreg.h

348

#define ATW_TEST1_RSVD0_MASK __BITS(24,6) /* reserved */

sys/dev/ic/atwreg.h

349

#define ATW_TEST1_TESTMODE_MASK __BITS(5,4)

sys/dev/ic/atwreg.h

359

#define ATW_TEST1_DUMP_MASK __BITS(3,0) /* select dump signal

sys/dev/ic/atwreg.h

369

#define ATW_TEST0_BE_MASK __BITS(31, 29) /* Bus error state */

sys/dev/ic/atwreg.h

370

#define ATW_TEST0_TS_MASK __BITS(28, 26) /* Transmit process state */

sys/dev/ic/atwreg.h

397

#define ATW_TEST0_RS_MASK __BITS(25, 23) /* Receive process state */

sys/dev/ic/atwreg.h

432

#define ATW_WCSR_BLN_MASK __BITS(21, 23) /* lose link after BLN lost

sys/dev/ic/atwreg.h

454

#define ATW_GPTMR_GTV_MASK __BITS(0, 15) /* set countdown in 204us ticks */

sys/dev/ic/atwreg.h

456

#define ATW_GPIO_EC1_MASK __BITS(25, 24) /* GPIO1 event configuration */

sys/dev/ic/atwreg.h

457

#define ATW_GPIO_LAT_MASK __BITS(21, 20) /* input latch */

sys/dev/ic/atwreg.h

458

#define ATW_GPIO_INTEN_MASK __BITS(19, 18) /* interrupt enable */

sys/dev/ic/atwreg.h

459

#define ATW_GPIO_EN_MASK __BITS(17, 12) /* output enable */

sys/dev/ic/atwreg.h

460

#define ATW_GPIO_O_MASK __BITS(11, 6) /* output value */

sys/dev/ic/atwreg.h

461

#define ATW_GPIO_I_MASK __BITS(5, 0) /* pin static input */

sys/dev/ic/atwreg.h

465

#define ATW_BBPCTL_RF3KADDR_MASK __BITS(30, 24) /* Address for RF3000 */

sys/dev/ic/atwreg.h

481

#define ATW_BBPCTL_TYPE_MASK __BITS(20, 18) /* BBP type */

sys/dev/ic/atwreg.h

487

#define ATW_BBPCTL_ADDR_MASK __BITS(15, 8) /* BBP address */

sys/dev/ic/atwreg.h

488

#define ATW_BBPCTL_DATA_MASK __BITS(7, 0) /* BBP data */

sys/dev/ic/atwreg.h

510

#define ATW_SYNCTL_RFTYPE_MASK __BITS(24, 22) /* RF type */

sys/dev/ic/atwreg.h

511

#define ATW_SYNCTL_DATA_MASK __BITS(21, 0) /* synthesizer setting */

sys/dev/ic/atwreg.h

513

#define ATW_PLCPHD_SIGNAL_MASK __BITS(31, 24) /* signal field in PLCP header,

sys/dev/ic/atwreg.h

517

#define ATW_PLCPHD_SERVICE_MASK __BITS(23, 16) /* service field in PLCP

sys/dev/ic/atwreg.h

524

#define ATW_MMIWADDR_LENLO_MASK __BITS(31,24) /* tx: written 4th */

sys/dev/ic/atwreg.h

525

#define ATW_MMIWADDR_LENHI_MASK __BITS(23,16) /* tx: written 3rd */

sys/dev/ic/atwreg.h

526

#define ATW_MMIWADDR_GAIN_MASK __BITS(15,8) /* tx: written 2nd */

sys/dev/ic/atwreg.h

527

#define ATW_MMIWADDR_RATE_MASK __BITS(7,0) /* tx: written 1st */

sys/dev/ic/atwreg.h

546

#define ATW_MMIRADDR1_RSVD_MASK __BITS(31, 24)

sys/dev/ic/atwreg.h

547

#define ATW_MMIRADDR1_PWRLVL_MASK __BITS(23, 16)

sys/dev/ic/atwreg.h

548

#define ATW_MMIRADDR1_RSSI_MASK __BITS(15, 8)

sys/dev/ic/atwreg.h

549

#define ATW_MMIRADDR1_RXSTAT_MASK __BITS(7, 0)

sys/dev/ic/atwreg.h

571

#define ATW_MMIRADDR2_ID_MASK __BITS(31, 24) /* 1st element ID in WEP table

sys/dev/ic/atwreg.h

575

#define ATW_MMIRADDR2_RXPECNT_MASK __BITS(23, 16)

sys/dev/ic/atwreg.h

580

#define ATW_MMIRADDR2_PRORLEN_MASK __BITS(14, 0) /* Probe Response

sys/dev/ic/atwreg.h

586

#define ATW_TXBR_TBCNT_MASK __BITS(16, 20) /* transmit burst count */

sys/dev/ic/atwreg.h

587

#define ATW_TXBR_ALCSET_MASK __BITS(8, 15) /* TX power level set point */

sys/dev/ic/atwreg.h

588

#define ATW_TXBR_ALCREF_MASK __BITS(0, 7) /* TX power level reference point */

sys/dev/ic/atwreg.h

592

#define ATW_ALCSTAT_MCNT_MASK __BITS(16, 25) /* MPDU count, unsigned integer */

sys/dev/ic/atwreg.h

593

#define ATW_ALCSTAT_ERSUM_MASK __BITS(0, 15) /* power error sum,

sys/dev/ic/atwreg.h

597

#define ATW_TOFS2_PWR1UP_MASK __BITS(31, 28) /* delay of Tx/Rx from PE1,

sys/dev/ic/atwreg.h

601

#define ATW_TOFS2_PWR0PAPE_MASK __BITS(27, 24) /* delay of PAPE going low

sys/dev/ic/atwreg.h

605

#define ATW_TOFS2_PWR1PAPE_MASK __BITS(23, 20) /* delay of PAPE going high

sys/dev/ic/atwreg.h

608

#define ATW_TOFS2_PWR0TRSW_MASK __BITS(19, 16) /* delay of TRSW going low

sys/dev/ic/atwreg.h

612

#define ATW_TOFS2_PWR1TRSW_MASK __BITS(15, 12) /* delay of TRSW going high

sys/dev/ic/atwreg.h

615

#define ATW_TOFS2_PWR0PE2_MASK __BITS(11, 8) /* delay of PE2 going low

sys/dev/ic/atwreg.h

619

#define ATW_TOFS2_PWR1PE2_MASK __BITS(7, 4) /* delay of PE2 going high

sys/dev/ic/atwreg.h

622

#define ATW_TOFS2_PWR0TXPE_MASK __BITS(3, 0) /* delay of TXPE going low

sys/dev/ic/atwreg.h

634

#define ATW_CMDR_DRT_MASK __BITS(3, 2) /* drain Rx FIFO threshold */

sys/dev/ic/atwreg.h

650

#define ATW_PAR0_PAB0_MASK __BITS(0, 7) /* MAC address byte 0 */

sys/dev/ic/atwreg.h

651

#define ATW_PAR0_PAB1_MASK __BITS(8, 15) /* MAC address byte 1 */

sys/dev/ic/atwreg.h

652

#define ATW_PAR0_PAB2_MASK __BITS(16, 23) /* MAC address byte 2 */

sys/dev/ic/atwreg.h

653

#define ATW_PAR0_PAB3_MASK __BITS(24, 31) /* MAC address byte 3 */

sys/dev/ic/atwreg.h

655

#define ATW_C_PAR1_CTD __BITS(16,31) /* Continuous Tx pattern */

sys/dev/ic/atwreg.h

656

#define ATW_PAR1_PAB5_MASK __BITS(8, 15) /* MAC address byte 5 */

sys/dev/ic/atwreg.h

657

#define ATW_PAR1_PAB4_MASK __BITS(0, 7) /* MAC address byte 4 */

sys/dev/ic/atwreg.h

659

#define ATW_MAR0_MAB3_MASK __BITS(31, 24) /* multicast table bits 31:24 */

sys/dev/ic/atwreg.h

660

#define ATW_MAR0_MAB2_MASK __BITS(23, 16) /* multicast table bits 23:16 */

sys/dev/ic/atwreg.h

661

#define ATW_MAR0_MAB1_MASK __BITS(15, 8) /* multicast table bits 15:8 */

sys/dev/ic/atwreg.h

662

#define ATW_MAR0_MAB0_MASK __BITS(7, 0) /* multicast table bits 7:0 */

sys/dev/ic/atwreg.h

664

#define ATW_MAR1_MAB7_MASK __BITS(31, 24) /* multicast table bits 63:56 */

sys/dev/ic/atwreg.h

665

#define ATW_MAR1_MAB6_MASK __BITS(23, 16) /* multicast table bits 55:48 */

sys/dev/ic/atwreg.h

666

#define ATW_MAR1_MAB5_MASK __BITS(15, 8) /* multicast table bits 47:40 */

sys/dev/ic/atwreg.h

667

#define ATW_MAR1_MAB4_MASK __BITS(7, 0) /* multicast table bits 39:32 */

sys/dev/ic/atwreg.h

670

#define ATW_ATIMDA0_ATIMB3_MASK __BITS(31,24)

sys/dev/ic/atwreg.h

671

#define ATW_ATIMDA0_ATIMB2_MASK __BITS(23,16)

sys/dev/ic/atwreg.h

672

#define ATW_ATIMDA0_ATIMB1_MASK __BITS(15,8)

sys/dev/ic/atwreg.h

673

#define ATW_ATIMDA0_ATIMB0_MASK __BITS(7,0)

sys/dev/ic/atwreg.h

676

#define ATW_ABDA1_BSSIDB5_MASK __BITS(31,24)

sys/dev/ic/atwreg.h

677

#define ATW_ABDA1_BSSIDB4_MASK __BITS(23,16)

sys/dev/ic/atwreg.h

678

#define ATW_ABDA1_ATIMB5_MASK __BITS(15,8)

sys/dev/ic/atwreg.h

679

#define ATW_ABDA1_ATIMB4_MASK __BITS(7,0)

sys/dev/ic/atwreg.h

682

#define ATW_BSSID0_BSSIDB3_MASK __BITS(31,24)

sys/dev/ic/atwreg.h

683

#define ATW_BSSID0_BSSIDB2_MASK __BITS(23,16)

sys/dev/ic/atwreg.h

684

#define ATW_BSSID0_BSSIDB1_MASK __BITS(15,8)

sys/dev/ic/atwreg.h

685

#define ATW_BSSID0_BSSIDB0_MASK __BITS(7,0)

sys/dev/ic/atwreg.h

687

#define ATW_TXLMT_MTMLT_MASK __BITS(31,16) /* max TX MSDU lifetime in TU */

sys/dev/ic/atwreg.h

688

#define ATW_TXLMT_SRTYLIM_MASK __BITS(7,0) /* short retry limit */

sys/dev/ic/atwreg.h

690

#define ATW_MIBCNT_FFCNT_MASK __BITS(31,24) /* FCS failure count */

sys/dev/ic/atwreg.h

691

#define ATW_MIBCNT_AFCNT_MASK __BITS(23,16) /* ACK failure count */

sys/dev/ic/atwreg.h

692

#define ATW_MIBCNT_RSCNT_MASK __BITS(15,8) /* RTS success count */

sys/dev/ic/atwreg.h

693

#define ATW_MIBCNT_RFCNT_MASK __BITS(7,0) /* RTS failure count */

sys/dev/ic/atwreg.h

695

#define ATW_BCNT_PLCPH_MASK __BITS(23,16) /* 11M PLCP length (us) */

sys/dev/ic/atwreg.h

696

#define ATW_BCNT_PLCPL_MASK __BITS(15,8) /* 5.5M PLCP length (us) */

sys/dev/ic/atwreg.h

697

#define ATW_BCNT_BCNT_MASK __BITS(7,0) /* byte count of beacon frame */

sys/dev/ic/atwreg.h

702

#define ATW_C_BCNT_BEANLEN1 __BITS(30,16) /* beacon length in us */

sys/dev/ic/atwreg.h

707

#define ATW_C_TSC_TIMOFS __BITS(31,24) /* I think this is the

sys/dev/ic/atwreg.h

710

#define ATW_C_TSC_TIMLEN __BITS(21,12) /* length of TIM */

sys/dev/ic/atwreg.h

712

#define ATW_TSC_TSC_MASK __BITS(3,0) /* TSFT countdown value, 0

sys/dev/ic/atwreg.h

763

#define ATW_BPLI_BP_MASK __BITS(31,16) /* beacon interval in TU */

sys/dev/ic/atwreg.h

764

#define ATW_BPLI_LI_MASK __BITS(15,0) /* STA listen interval in

sys/dev/ic/atwreg.h

768

#define ATW_C_CAP0_TIMLEN1 __BITS(31,24) /* TIM table 1 len in bytes

sys/dev/ic/atwreg.h

771

#define ATW_C_CAP0_TIMLEN0 __BITS(23,16) /* TIM table 0 len in bytes,

sys/dev/ic/atwreg.h

774

#define ATW_C_CAP0_CWMAX __BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW?

sys/dev/ic/atwreg.h

780

#define ATW_CAP0_CHN_MASK __BITS(3,0) /* current DSSS channel */

sys/dev/ic/atwreg.h

782

#define ATW_CAP1_CAPI_MASK __BITS(31,16) /* capability information */

sys/dev/ic/atwreg.h

783

#define ATW_CAP1_ATIMW_MASK __BITS(15,0) /* ATIM window in TU */

sys/dev/ic/atwreg.h

787

#define ATW_RMD_PCNT __BITS(27,16) /* idle time between

sys/dev/ic/atwreg.h

790

#define ATW_RMD_RMRD_MASK __BITS(15,0) /* max RX reception duration

sys/dev/ic/atwreg.h

794

#define ATW_CFPP_CFPP __BITS(31,24) /* CFP unit DTIM */

sys/dev/ic/atwreg.h

795

#define ATW_CFPP_CFPMD __BITS(23,8) /* CFP max duration in TU */

sys/dev/ic/atwreg.h

796

#define ATW_CFPP_DTIMP __BITS(7,0) /* DTIM period in beacon

sys/dev/ic/atwreg.h

799

#define ATW_TOFS0_USCNT_MASK __BITS(29,24) /* number of system clocks

sys/dev/ic/atwreg.h

803

#define ATW_C_TOFS0_TUCNT_MASK __BITS(14,10) /* PIFS (microseconds) */

sys/dev/ic/atwreg.h

804

#define ATW_TOFS0_TUCNT_MASK __BITS(9,0) /* TU counter in microseconds */

sys/dev/ic/atwreg.h

807

#define ATW_TOFS1_TSFTOFSR_MASK __BITS(31,24) /* RX TSFT offset in

sys/dev/ic/atwreg.h

811

#define ATW_TOFS1_TBTTPRE_MASK __BITS(23,8) /* prediction time, (next

sys/dev/ic/atwreg.h

816

#define ATW_TBTTPRE_MASK __BITS(25, 10)

sys/dev/ic/atwreg.h

817

#define ATW_TOFS1_TBTTOFS_MASK __BITS(7,0) /* wake-up time offset before

sys/dev/ic/atwreg.h

820

#define ATW_IFST_SLOT_MASK __BITS(27,23) /* SLOT time in us */

sys/dev/ic/atwreg.h

821

#define ATW_IFST_SIFS_MASK __BITS(22,15) /* SIFS time in us */

sys/dev/ic/atwreg.h

822

#define ATW_IFST_DIFS_MASK __BITS(14,9) /* DIFS time in us */

sys/dev/ic/atwreg.h

823

#define ATW_IFST_EIFS_MASK __BITS(8,0) /* EIFS time in us */

sys/dev/ic/atwreg.h

825

#define ATW_RSPT_MART_MASK __BITS(31,16) /* max response time in us */

sys/dev/ic/atwreg.h

826

#define ATW_RSPT_MIRT_MASK __BITS(15,8) /* min response time in us */

sys/dev/ic/atwreg.h

827

#define ATW_RSPT_TSFTOFST_MASK __BITS(7,0) /* TX TSFT offset in us */

sys/dev/ic/atwreg.h

844

#define ATW_WEPCTL_TBLADD_MASK __BITS(8,0) /* add to table */

sys/dev/ic/atwreg.h

852

#define ATW_WESK_DATA_MASK __BITS(15,0) /* data */

sys/dev/ic/atwreg.h

853

#define ATW_WEPCNT_WIEC_MASK __BITS(15,0) /* WEP ICV error count */

sys/dev/ic/atwreg.h

857

#define ATW_MACTEST_KEYID_MASK __BITS(21,20)

sys/dev/ic/atwreg.h

881

#define ATW_SR_MAJOR_MASK __BITS(7, 0)

sys/dev/ic/atwreg.h

882

#define ATW_SR_MINOR_MASK __BITS(15,8)

sys/dev/ic/atwreg.h

887

#define ATW_SR_ANT_MASK __BITS(12, 10)

sys/dev/ic/atwreg.h

888

#define ATW_SR_PWRSCALE_MASK __BITS(9, 8)

sys/dev/ic/atwreg.h

889

#define ATW_SR_CLKSAVE_MASK __BITS(7, 6)

sys/dev/ic/atwreg.h

890

#define ATW_SR_RFTYPE_MASK __BITS(5, 3)

sys/dev/ic/atwreg.h

891

#define ATW_SR_BBPTYPE_MASK __BITS(2, 0)

sys/dev/ic/atwreg.h

893

#define ATW_SR_CR28_MASK __BITS(15,8)

sys/dev/ic/atwreg.h

894

#define ATW_SR_CR03_MASK __BITS(7, 0)

sys/dev/ic/atwreg.h

896

#define ATW_SR_CTRY_MASK __BITS(15,8) /* country code */

sys/dev/ic/atwreg.h

904

#define ATW_SR_CR29_MASK __BITS(7, 0)

sys/dev/ic/atwreg.h

936

#define ATW_TXCTL_TXDR_MASK __BITS(27,20) /* TX data rate (?) */

sys/dev/ic/atwreg.h

937

#define ATW_TXCTL_TL_MASK __BITS(19,0) /* retry limit, 0 - 255 */

sys/dev/ic/atwreg.h

949

#define ATW_TXSTAT_ARC_MASK __BITS(11,0) /* accumulated retry count */

sys/dev/ic/atwreg.h

962

#define ATW_TXFLAG_TBS2_MASK __BITS(23,12) /* at_buf2 byte count */

sys/dev/ic/atwreg.h

963

#define ATW_TXFLAG_TBS1_MASK __BITS(11,0) /* at_buf1 byte count */

sys/dev/ic/atwreg.h

975

#define ATW_RXCTL_RBS2_MASK __BITS(23,12) /* ar_buf2 byte count */

sys/dev/ic/atwreg.h

976

#define ATW_RXCTL_RBS1_MASK __BITS(11,0) /* ar_buf1 byte count */

sys/dev/ic/atwvar.h

355

#define ATW_FRAGTHR_FRAGTHR_MASK __BITS(0, 11)

sys/dev/ic/atwvar.h

356

#define ATW_FRAGNUM_FRAGNUM_MASK __BITS(4, 7)

sys/dev/ic/bcmgenet.c

380

mdf_ctrl = __BITS(GENET_MAX_MDF_FILTER - 1,

sys/dev/ic/bcmgenetreg.h

107

#define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16)

sys/dev/ic/bcmgenetreg.h

108

#define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0)

sys/dev/ic/bcmgenetreg.h

115

#define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16)

sys/dev/ic/bcmgenetreg.h

116

#define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0)

sys/dev/ic/bcmgenetreg.h

126

#define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16)

sys/dev/ic/bcmgenetreg.h

127

#define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0)

sys/dev/ic/bcmgenetreg.h

138

#define GENET_RX_DESC_STATUS_BUFLEN __BITS(27,16)

sys/dev/ic/bcmgenetreg.h

142

#define GENET_RX_DESC_STATUS_ALL_ERRS __BITS(4,0)

sys/dev/ic/bcmgenetreg.h

152

#define GENET_TX_DESC_STATUS_BUFLEN __BITS(27,16)

sys/dev/ic/bcmgenetreg.h

156

#define GENET_TX_DESC_STATUS_QTAG __BITS(12,7)

sys/dev/ic/bcmgenetreg.h

176

#define GENET_INTR_THRESHOLD_MASK __BITS(0,8)

sys/dev/ic/bcmgenetreg.h

178

#define GENET_DMA_RING_TIMEOUT_MASK __BITS(0,15)

sys/dev/ic/bcmgenetreg.h

37

#define SYS_REV_MAJOR __BITS(27,24)

sys/dev/ic/bcmgenetreg.h

38

#define SYS_REV_MINOR __BITS(19,16)

sys/dev/ic/bcmgenetreg.h

67

#define GENET_UMAC_CMD_SPEED __BITS(3,2)

sys/dev/ic/bcmgenetreg.h

85

#define GENET_MDIO_PMD __BITS(25,21)

sys/dev/ic/bcmgenetreg.h

86

#define GENET_MDIO_REG __BITS(20,16)

sys/dev/ic/bwfmvar.h

100

#define BWFM_FWSEL_REV_LE(x) __BITS(0,x)

sys/dev/ic/bwfmvar.h

101

#define BWFM_FWSEL_REV_GE(x) __BITS(x,31)

sys/dev/ic/bwfmvar.h

102

#define BWFM_FWSEL_ALLREVS __BITS(0,31)

sys/dev/ic/cdnsiic.c

57

#define CR_DIV_A __BITS(15,14)

sys/dev/ic/cdnsiic.c

58

#define CR_DIV_B __BITS(13,8)

sys/dev/ic/comreg.h

170

#define UART_CPR_FIFO_MODE __BITS(23,16)

sys/dev/ic/dw_hdmi.c

101

#define HDMI_VP_CONF_OUTPUT_SELECT __BITS(1,0)

sys/dev/ic/dw_hdmi.c

165

#define HDMI_AUD_CONF0_I2S_IN_EN __BITS(3,0)

sys/dev/ic/dw_hdmi.c

167

#define HDMI_AUD_CONF1_I2S_WIDTH __BITS(4,0)

sys/dev/ic/dw_hdmi.c

182

#define HDMI_AUD_INPUTCLKFS_IFSFACTOR __BITS(2,0)

sys/dev/ic/dw_hdmi.c

240

#define HDMI_I2CM_SEGADDR_SEGADDR __BITS(6,0)

sys/dev/ic/dw_hdmi.c

71

#define HDMI_TX_INVID0_VIDEO_MAPPING __BITS(4,0)

sys/dev/ic/dw_hdmi.c

86

#define HDMI_VP_PR_CD_COLOR_DEPTH __BITS(7,4)

sys/dev/ic/dw_hdmi.c

88

#define HDMI_VP_PR_CD_DESIRED_PR_FACTOR __BITS(3,0)

sys/dev/ic/dw_hdmi.c

96

#define HDMI_VP_REMAP_YCC422_SIZE __BITS(1,0)

sys/dev/ic/dwc_eqos_reg.h

107

#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ __BITS(25,24)

sys/dev/ic/dwc_eqos_reg.h

112

#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE __BITS(10,6)

sys/dev/ic/dwc_eqos_reg.h

113

#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE __BITS(4,0)

sys/dev/ic/dwc_eqos_reg.h

151

#define GMAC_MAC_ADDRESS_HIGH_MB __BITS(29,24)

sys/dev/ic/dwc_eqos_reg.h

153

#define GMAC_MAC_ADDRESS_HIGH_ADDR __BITS(15,0)

sys/dev/ic/dwc_eqos_reg.h

233

#define GMAC_MTL_TXQ0_OPERATION_MODE_TQS __BITS(24,16)

sys/dev/ic/dwc_eqos_reg.h

234

#define GMAC_MTL_TXQ0_OPERATION_MODE_TTC __BITS(6,4)

sys/dev/ic/dwc_eqos_reg.h

248

#define GMAC_MTL_RXQ0_OPERATION_MODE_RQS __BITS(29,20)

sys/dev/ic/dwc_eqos_reg.h

249

#define GMAC_MTL_RXQ0_OPERATION_MODE_RFD __BITS(19,14)

sys/dev/ic/dwc_eqos_reg.h

250

#define GMAC_MTL_RXQ0_OPERATION_MODE_RFA __BITS(13,8)

sys/dev/ic/dwc_gmac_reg.h

141

#define GMAC_MII_PHY_MASK __BITS(15,11)

sys/dev/ic/dwc_gmac_reg.h

142

#define GMAC_MII_REG_MASK __BITS(10,6)

sys/dev/ic/dwc_gmac_reg.h

160

#define GMAC_MII_CLKMASK __BITS(5,2)

sys/dev/ic/dwc_gmac_reg.h

165

#define GMAC_BUSMODE_RPBL __BITS(22,17)

sys/dev/ic/dwc_gmac_reg.h

167

#define GMAC_BUSMODE_PRIORXTX __BITS(15,14)

sys/dev/ic/dwc_gmac_reg.h

172

#define GMAC_BUSMODE_PBL __BITS(13,8) /* possible DMA

sys/dev/ic/dwc_gmac_reg.h

174

#define GMAC_BUSMODE_DSL __BITS(6,2)

sys/dev/ic/dwc_gmac_reg.h

195

#define GMAC_DMA_OP_TTC __BITS(16,14) /* TX thresh control */

sys/dev/ic/dwc_gmac_reg.h

197

#define GMAC_DMA_OP_RFD __BITS(12,11) /* rx flwctl deactivate */

sys/dev/ic/dwc_gmac_reg.h

198

#define GMAC_DMA_OP_RFA __BITS(10,9) /* rx flwctl activate */

sys/dev/ic/dwc_gmac_reg.h

202

#define GMAC_DMA_OP_RTC __BITS(4,3) /* RX thres control */

sys/dev/ic/dwc_gmac_reg.h

224

#define GMAC_DMA_INT_MASK __BITS(0,16) /* all possible intr bits */

sys/dev/ic/dwc_gmac_reg.h

239

#define DDESC_STATUS_FRMLENMSK __BITS(29,16)

sys/dev/ic/dwc_gmac_reg.h

263

#define DDESC_CNTL_TXCHECKINSCTRL __BITS(27,28)

sys/dev/ic/dwc_gmac_reg.h

281

#define DDESC_CNTL_SIZE1MASK __BITS(10,0)

sys/dev/ic/dwc_gmac_reg.h

283

#define DDESC_CNTL_SIZE2MASK __BITS(21,11)

sys/dev/ic/dwc_gmac_reg.h

294

#define DDESC_DES1_SIZE2MASK __BITS(28,16)

sys/dev/ic/dwc_gmac_reg.h

295

#define DDESC_DES1_SIZE1MASK __BITS(12,0)

sys/dev/ic/dwc_gmac_reg.h

302

#define DDESC_TDES0_CIC __BITS(23,22)

sys/dev/ic/dwc_gmac_reg.h

308

#define DDESC_RDES0_FL __BITS(29,16)

sys/dev/ic/dwc_gmac_reg.h

41

#define AWIN_GMAC_MAC_VERSION_USERVER_MASK __BITS(15, 8)

sys/dev/ic/dwc_gmac_reg.h

42

#define AWIN_GMAC_MAC_VERSION_SNPSVER_MASK __BITS( 7, 0)

sys/dev/ic/dwc_gmac_reg.h

80

#define AWIN_GMAC_MAC_FLOWCTRL_PAUSE __BITS(31,16)

sys/dev/ic/dwc_mmc_reg.h

145

#define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE __BITS(30,28)

sys/dev/ic/dwc_mmc_reg.h

147

#define DWC_MMC_FIFOTH_RX_WMARK __BITS(27,16)

sys/dev/ic/dwc_mmc_reg.h

148

#define DWC_MMC_FIFOTH_TX_WMARK __BITS(11,0)

sys/dev/ic/dwc_mmc_reg.h

156

#define DWC_MMC_VERID_ID __BITS(15,0)

sys/dev/ic/dwc_mmc_reg.h

174

#define DWC_MMC_CARDTHRCTL_RDTHR __BITS(27,16)

sys/dev/ic/dwc_wdt.c

44

#define WDT_CR_RST_PULSE_LENGTH __BITS(4,2)

sys/dev/ic/dwc_wdt.c

49

#define WDT_TORR_TIMEOUT_PERIOD __BITS(3,0)

sys/dev/ic/dwc_wdt.c

54

#define WDT_CRR_CNT_RESTART __BITS(7,0)

sys/dev/ic/hfa3861areg.h

37

#define HFA3861A_CR5_RSVD0 __BITS(7, 4) /* reserved, set to 0 */

sys/dev/ic/hfa3861areg.h

42

#define HFA3861A_CR5_RATE_MASK __BITS(1, 0) /* Tx data rate */

sys/dev/ic/hfa3861areg.h

59

#define HFA3861A_CR49_RSVD __BITS(6, 0)

sys/dev/ic/hfa3861areg.h

64

#define HFA3861A_CR62_RSSI __BITS(7, 0) /* RSSI, sets 'a' & 'b' */

sys/dev/ic/hfa3861areg.h

67

#define HFA3861A_CR63_SIGNAL_MASK __BITS(7, 6) /* signal field value,

sys/dev/ic/i82801lpcreg.h

175

#define SMB_TCOBASE_TCOBA __BITS(15,5) /* TCO Base Address */

sys/dev/ic/i82801lpcreg.h

320

#define SB_PORTID __BITS(23,16)

sys/dev/ic/i82801lpcreg.h

330

#define SB_SMBUS_TCOCFG_IS __BITS(2,0) /* TCO IRQ Select */

sys/dev/ic/igpio.c

79

__BITS(3,7)|__BITS(14,16)|__BITS(21,22)|__BITS(27,31);

sys/dev/ic/igpioreg.h

39

#define IGPIO_PADCFG0_RXEVCFG_MASK __BITS(26, 25)

sys/dev/ic/igpioreg.h

51

#define IGPIO_PADCFG0_PMODE_MASK __BITS(13, 10)

sys/dev/ic/igpioreg.h

61

#define IGPIO_PADCFG1_TERM_MASK __BITS(12, 10)

sys/dev/ic/max2820reg.h

106

#define MAX2820_SYNTH_RSVD0 __BITS(11,7) /* reserved */

sys/dev/ic/max2820reg.h

111

#define MAX2820_SYNTH_R_MASK __BITS(5,0) /* Reference Frequency Divider

sys/dev/ic/max2820reg.h

121

#define MAX2820_CHANNEL_RSVD __BITS(11,7) /* reserved */

sys/dev/ic/max2820reg.h

122

#define MAX2820_CHANNEL_CF_MASK __BITS(6,0) /* Channel Frequency Select

sys/dev/ic/max2820reg.h

131

#define MAX2820_RECEIVE_2C_MASK __BITS(11,9) /* VGA DC Offset Nulling

sys/dev/ic/max2820reg.h

134

#define MAX2820_RECEIVE_1C_MASK __BITS(8,6) /* VGA DC Offset Nulling

sys/dev/ic/max2820reg.h

137

#define MAX2820_RECEIVE_DL_MASK __BITS(5,4) /* Rx Level Detector Midpoint

sys/dev/ic/max2820reg.h

147

#define MAX2820_RECEIVE_BW_MASK __BITS(2,0) /* Receive Filter -3dB Frequency

sys/dev/ic/max2820reg.h

168

#define MAX2820A_RECEIVE_2C_MASK __BITS(11,9)

sys/dev/ic/max2820reg.h

171

#define MAX2820A_RECEIVE_1C_MASK __BITS(8,6)

sys/dev/ic/max2820reg.h

173

#define MAX2820A_RECEIVE_RSVD0_MASK __BITS(5,3)

sys/dev/ic/max2820reg.h

175

#define MAX2820A_RECEIVE_RSVD1_MASK __BITS(2,0)

sys/dev/ic/max2820reg.h

179

#define MAX2820_TRANSMIT_RSVD_MASK __BITS(11,4) /* reserved */

sys/dev/ic/max2820reg.h

180

#define MAX2820_TRANSMIT_PA_MASK __BITS(3,0) /* PA Bias Select

sys/dev/ic/max2820reg.h

38

#define MAX2820_TWI_ADDR_MASK __BITS(15,12)

sys/dev/ic/max2820reg.h

39

#define MAX2820_TWI_DATA_MASK __BITS(11,0)

sys/dev/ic/max2820reg.h

46

#define MAX2820_TEST_DEFAULT __BITS(2,0) /* Always set to this value. */

sys/dev/ic/mpc106reg.h

109

#define MPC106_PICR2_DATA_RAM_TYPE __BITS(23,22) /* L2 data RAM type */

sys/dev/ic/mpc106reg.h

114

#define MPC106_PICR2_WMODE __BITS(21,20) /* SRAM write timing */

sys/dev/ic/mpc106reg.h

119

#define MPC106_PICR2_SNOOP_WS __BITS(19,18) /* Snoop wait states: */

sys/dev/ic/mpc106reg.h

133

#define MPC106_PICR2_L2_HIT_DELAY __BITS(10,9) /* L2 hit delay */

sys/dev/ic/mpc106reg.h

141

#define MPC106_PICR2_L2_SIZE __BITS(5,4) /* L2 cache size */

sys/dev/ic/mpc106reg.h

146

#define MPC106_PICR2_APHASE_WS __BITS(3,2) /* Addr. phase wait states: */

sys/dev/ic/mpc106reg.h

169

#define MPC106_MCCR1_ROMNAL __BITS(31,28) /* burst mode rom reads */

sys/dev/ic/mpc106reg.h

170

#define MPC106_MCCR1_ROMFAL __BITS(27,23) /* nonburst mode rom reads */

sys/dev/ic/mpc106reg.h

180

#define MPC106_MCRR2_TSWAIT __BITS(31,29)

sys/dev/ic/mpc106reg.h

181

#define MPC106_MCRR2_RESV0 __BITS(28,22) /* reserved */

sys/dev/ic/mpc106reg.h

188

#define MPC106_MCRR2_REFINT __BITS(15,2) /* refresh interval */

sys/dev/ic/mpc106reg.h

193

#define MPC106_MCRR4_PRETOACT __BITS(31,28)

sys/dev/ic/mpc106reg.h

194

#define MPC106_MCRR4_ACTOPRE __BITS(27,24)

sys/dev/ic/mpc106reg.h

195

#define MPC106_MCRR4_EXT_ECM_EN __BITS(23,22) /* ext ecm enable */

sys/dev/ic/mpc106reg.h

56

#define MPC106_PICR1_CBA_MASK __BITS(31,24) /* Copy-back addr mask */

sys/dev/ic/mpc106reg.h

57

#define MPC106_PICR1_BREAD_WS __BITS(23,22) /* Burst read wait states: */

sys/dev/ic/mpc106reg.h

65

#define MPC106_PICR1_PROC_TYPE __BITS(18,17) /* Processor type */

sys/dev/ic/mpc106reg.h

71

#define MPC106_PICR1_MP_ID __BITS(15,14) /* Multiprocessor identifier */

sys/dev/ic/mpc106reg.h

85

#define MPC106_PICR1_L2_MP __BITS(1,0) /* L2/multiproc config: */

sys/dev/ic/nvmereg.h

204

#define NVM_SQE_IO_LAT_MASK __BITS(4, 5) /* Access Latency */

sys/dev/ic/nvmereg.h

208

#define NVM_SQE_IO_LAT_LOW __BITS(4, 5) /* Latency: low */

sys/dev/ic/nvmereg.h

209

#define NVM_SQE_IO_FREQ_MASK __BITS(0, 3) /* Access Frequency */

sys/dev/ic/nvmereg.h

243

#define NVME_CQE_SCT_MASK __BITS(9, 11)

sys/dev/ic/nvmereg.h

249

#define NVME_CQE_SC_MASK __BITS(1, 8)

sys/dev/ic/nvmereg.h

388

#define NVME_PSD_RRT_MASK __BITS(0, 4)

sys/dev/ic/nvmereg.h

390

#define NVME_PSD_RRL_MASK __BITS(0, 4)

sys/dev/ic/nvmereg.h

392

#define NVME_PSD_RWT_MASK __BITS(0, 4)

sys/dev/ic/nvmereg.h

394

#define NVME_PSD_RWL_MASK __BITS(0, 4)

sys/dev/ic/nvmereg.h

398

#define NVME_PSD_IPS_MASK __BITS(0, 1)

sys/dev/ic/nvmereg.h

402

#define NVME_PSD_APW_MASK __BITS(0, 2)

sys/dev/ic/nvmereg.h

403

#define NVME_PSD_APS_MASK __BITS(6, 7)

sys/dev/ic/nvmereg.h

458

#define NVME_ID_CTRLR_FRMW_NSLOT __BITS(1, 3)

sys/dev/ic/nvmereg.h

510

#define NVME_ID_CTRLR_SQES_MAX __BITS(4, 7)

sys/dev/ic/nvmereg.h

511

#define NVME_ID_CTRLR_SQES_MIN __BITS(0, 3)

sys/dev/ic/nvmereg.h

513

#define NVME_ID_CTRLR_CQES_MAX __BITS(4, 7)

sys/dev/ic/nvmereg.h

514

#define NVME_ID_CTRLR_CQES_MIN __BITS(0, 3)

sys/dev/ic/pl041.c

50

#define AACITXCR_TSIZE __BITS(14,13)

sys/dev/ic/pl181reg.h

114

#define MMCI_FIFO_CNT __BITS(14,0)

sys/dev/ic/pl181reg.h

60

#define MMCI_POWER_CTRL __BITS(1,0)

sys/dev/ic/pl181reg.h

64

#define MMCI_POWER_VOLTAGE __BITS(5,2)

sys/dev/ic/pl181reg.h

68

#define MMCI_CLOCK_CLKDIV __BITS(7,0)

sys/dev/ic/pl181reg.h

73

#define MMCI_COMMAND_CMDINDEX __BITS(5,0)

sys/dev/ic/pl181reg.h

80

#define MMCI_RESP_CMD __BITS(5,0)

sys/dev/ic/pl181reg.h

82

#define MMCI_DATA_LENGTH __BITS(15,0)

sys/dev/ic/pl181reg.h

88

#define MMCI_DATA_CTRL_BLOCKSIZE __BITS(7,4)

sys/dev/ic/pl181reg.h

90

#define MMCI_DATA_CNT __BITS(15,0)

sys/dev/ic/rf3000reg.h

103

#define RF3000_OPTIONS1_RESERVED0_MASK __BITS(2,0)/* 0 */

sys/dev/ic/rf3000reg.h

108

#define RF3000_OPTIONS2_RESERVED0_MASK __BITS(6,3) /* 0 */

sys/dev/ic/rf3000reg.h

111

#define RF3000_OPTIONS2_RESERVED1_MASK __BITS(1,0) /* 0 */

sys/dev/ic/rf3000reg.h

46

#define RF3000_CTL_MODE_MASK __BITS(7, 4)

sys/dev/ic/rf3000reg.h

66

#define RF3000_CCACTL_MODE_MASK __BITS(7, 6)

sys/dev/ic/rf3000reg.h

71

#define RF3000_CCACTL_RSSIT_MASK __BITS(5, 0)

sys/dev/ic/rf3000reg.h

78

#define RF3000_RSSI_MASK __BITS(5, 0)

sys/dev/ic/rf3000reg.h

80

#define RF3000_GAINCTL_TXVGC_MASK __BITS(7, 2)

sys/dev/ic/rf3000reg.h

83

#define RF3000_LOGAINCAL_CAL_MASK __BITS(5, 0)

sys/dev/ic/rf3000reg.h

85

#define RF3000_HIGAINCAL_CAL_MASK __BITS(5, 0)

sys/dev/ic/rf3000reg.h

94

#define RF3000_OPTIONS1_SAT_THRESH __BITS(6,5)

sys/dev/ic/rng200reg.h

41

#define RNG200_RBG_MASK __BITS(0,12)

sys/dev/ic/rng200reg.h

52

#define RNG200_COUNT_MASK __BITS(0,7)

sys/dev/ic/rtw.c

1128

(*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7));

sys/dev/ic/rtw.c

1129

(*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15));

sys/dev/ic/rtw.c

1130

(*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23));

sys/dev/ic/rtw.c

1131

(*addr)[3] = __SHIFTOUT(idr0, __BITS(24, 31));

sys/dev/ic/rtw.c

1133

(*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7));

sys/dev/ic/rtw.c

1134

(*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15));

sys/dev/ic/rtwreg.h

1024

#define RTW_BBP_SYS2_RATE_MASK __BITS(5,4) /* loopback rate?

sys/dev/ic/rtwreg.h

1032

#define RTW_BBP_SYS3_CSTHRESH_MASK __BITS(0,3)

sys/dev/ic/rtwreg.h

157

#define RTW_TCR_HWVERID_MASK __BITS(29, 25)

sys/dev/ic/rtwreg.h

168

#define RTW_TCR_MXDMA_MASK __BITS(23,21)

sys/dev/ic/rtwreg.h

185

#define RTW_TCR_LBK_MASK __BITS(18,17)

sys/dev/ic/rtwreg.h

199

#define RTW_TCR_SRL_MASK __BITS(15,8) /* Short Retry Limit */

sys/dev/ic/rtwreg.h

200

#define RTW_TCR_LRL_MASK __BITS(7,0) /* Long Retry Limit */

sys/dev/ic/rtwreg.h

227

#define RTW_RCR_RXFTH_MASK __BITS(15,13)

sys/dev/ic/rtwreg.h

238

#define RTW_RCR_MXDMA_MASK __BITS(10,8)

sys/dev/ic/rtwreg.h

295

#define RTW_9346CR_EEM_MASK __BITS(7,6) /* Operating Mode */

sys/dev/ic/rtwreg.h

334

#define RTW_CONFIG0_GL_MASK __BITS(1,0)

sys/dev/ic/rtwreg.h

355

#define RTW_CONFIG1_LEDS_MASK __BITS(7,6)

sys/dev/ic/rtwreg.h

389

#define RTW_CONFIG2_PAPETIME_MASK __BITS(1,0) /* TBD, from EEPROM */

sys/dev/ic/rtwreg.h

392

#define RTW_ANAPARM_RFPOW0_MASK __BITS(30,28) /* undocumented bits

sys/dev/ic/rtwreg.h

404

#define RTW_ANAPARM_RFPOW1_MASK __BITS(26,20) /* undocumented bits

sys/dev/ic/rtwreg.h

451

#define RTW_ANAPARM_CARDSP_MASK __BITS(19,0) /* undocumented

sys/dev/ic/rtwreg.h

459

#define RTW_MSR_NETYPE_MASK __BITS(3,2)

sys/dev/ic/rtwreg.h

525

#define RTW_CONFIG4_RFTYPE_MASK __BITS(1,0)

sys/dev/ic/rtwreg.h

545

#define RTW_SCR_KM_MASK __BITS(5,4) /* Key Mode */

sys/dev/ic/rtwreg.h

558

#define RTW_BCNITV_BCNITV_MASK __BITS(9,0) /* TU between TBTT, written

sys/dev/ic/rtwreg.h

562

#define RTW_ATIMWND_ATIMWND __BITS(9,0) /* ATIM Window length in TU,

sys/dev/ic/rtwreg.h

567

#define RTW_BINTRITV_BINTRITV __BITS(9,0) /* RTL8180 wakes host with

sys/dev/ic/rtwreg.h

572

#define RTW_ATIMTRITV_ATIMTRITV __BITS(9,0) /* RTL8180 wakes host with

sys/dev/ic/rtwreg.h

582

#define RTW_PHYDELAY_PHYDELAY __BITS(2,0) /* microsecond Tx delay between

sys/dev/ic/rtwreg.h

592

#define RTW_BB_RD_MASK __BITS(23,16) /* data to read */

sys/dev/ic/rtwreg.h

593

#define RTW_BB_WR_MASK __BITS(15,8) /* data to write */

sys/dev/ic/rtwreg.h

595

#define RTW_BB_ADDR_MASK __BITS(6,0) /* address */

sys/dev/ic/rtwreg.h

609

#define RTW_PHYCFG_MAC_RFTYPE_MASK __BITS(29,28)

sys/dev/ic/rtwreg.h

614

#define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK __BITS(27,24)

sys/dev/ic/rtwreg.h

615

#define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK __BITS(23,0)

sys/dev/ic/rtwreg.h

616

#define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK __BITS(27,24)

sys/dev/ic/rtwreg.h

617

#define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK __BITS(11,8)

sys/dev/ic/rtwreg.h

618

#define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK __BITS(7,0)

sys/dev/ic/rtwreg.h

62

#define RTW_BRSR_MBR8180_MASK __BITS(1,0) /* Maximum Basic Service Rate */

sys/dev/ic/rtwreg.h

623

#define RTW_MAXIM_HIDATA_MASK __BITS(11,4)

sys/dev/ic/rtwreg.h

624

#define RTW_MAXIM_LODATA_MASK __BITS(3,0)

sys/dev/ic/rtwreg.h

742

#define RTW_CWR_CW __BITS(9,0)

sys/dev/ic/rtwreg.h

747

#define RTW_RETRYCTR_RETRYCT __BITS(7,0)

sys/dev/ic/rtwreg.h

820

#define RTW_SR_RFPARM_CS_MASK __BITS(2,3) /* carrier-sense type */

sys/dev/ic/rtwreg.h

850

#define RTW_TXCTL0_RATE_MASK __BITS(27,24) /* Tx rate */

sys/dev/ic/rtwreg.h

858

#define RTW_TXCTL0_RTSRATE_MASK __BITS(22,19) /* Tx rate */

sys/dev/ic/rtwreg.h

870

#define RTW_TXCTL0_KEYID_MASK __BITS(15,14) /* default key id */

sys/dev/ic/rtwreg.h

871

#define RTW_TXCTL0_RSVD1_MASK __BITS(13,12) /* reserved */

sys/dev/ic/rtwreg.h

872

#define RTW_TXCTL0_TPKTSIZE_MASK __BITS(11,0) /* Tx packet size

sys/dev/ic/rtwreg.h

880

#define RTW_TXSTAT_RSVD1_MASK __BITS(27,16)

sys/dev/ic/rtwreg.h

882

#define RTW_TXSTAT_RTSRETRY_MASK __BITS(14,8) /* RTS retry count */

sys/dev/ic/rtwreg.h

883

#define RTW_TXSTAT_DRC_MASK __BITS(7,0) /* Data retry count */

sys/dev/ic/rtwreg.h

889

#define RTW_TXCTL1_LENGTH_MASK __BITS(30,16) /* PLCP length (microseconds) */

sys/dev/ic/rtwreg.h

890

#define RTW_TXCTL1_RTSDUR_MASK __BITS(15,0) /* RTS Duration

sys/dev/ic/rtwreg.h

894

#define RTW_TXLEN_LENGTH_MASK __BITS(11,0) /* Tx buffer length in bytes */

sys/dev/ic/rtwreg.h

913

#define RTW_RXCTL_RSVD0_MASK __BITS(29,12) /* reserved */

sys/dev/ic/rtwreg.h

914

#define RTW_RXCTL_LENGTH_MASK __BITS(11,0) /* Rx buffer length */

sys/dev/ic/rtwreg.h

928

#define RTW_RXSTAT_RATE_MASK __BITS(23,20) /* Rx rate */

sys/dev/ic/rtwreg.h

948

#define RTW_RXSTAT_LENGTH_MASK __BITS(11,0) /* frame length, including

sys/dev/ic/rtwreg.h

962

#define RTW_RXRSSI_VLAN __BITS(31,16) /* XXX from reference driver */

sys/dev/ic/rtwreg.h

964

#define RTW_RXRSSI_RSSI __BITS(15,8) /* RF energy at the PHY */

sys/dev/ic/rtwreg.h

966

#define RTW_RXRSSI_IMR_RSSI __BITS(15,9) /* RF energy at the PHY */

sys/dev/ic/rtwreg.h

968

#define RTW_RXRSSI_SQ __BITS(7,0) /* Barker code-lock quality */

sys/dev/ic/sa2400reg.h

101

#define SA2400_SYND_ZERO2_MASK __BITS(14,3) /* always 0 */

sys/dev/ic/sa2400reg.h

113

#define SA2400_OPMODE_FILTTUNE_MASK __BITS(17,15)

sys/dev/ic/sa2400reg.h

143

#define SA2400_OPMODE_MODE_MASK __BITS(3,0)

sys/dev/ic/sa2400reg.h

161

#define SA2400_AGC_TARGET_MASK __BITS(22,20) /* ... plus 0dB - 7dB */

sys/dev/ic/sa2400reg.h

162

#define SA2400_AGC_MAXGAIN_MASK __BITS(19,15) /* maximum AGC gain, 0 to 31,

sys/dev/ic/sa2400reg.h

169

#define SA2400_AGC_BBPDELAY_MASK __BITS(14,10)

sys/dev/ic/sa2400reg.h

176

#define SA2400_AGC_LNADELAY_MASK __BITS(9,5)

sys/dev/ic/sa2400reg.h

183

#define SA2400_AGC_RXONDELAY_MASK __BITS(4,0)

sys/dev/ic/sa2400reg.h

201

#define SA2400_MANRX_RXOSQ_MASK __BITS(20,18)

sys/dev/ic/sa2400reg.h

205

#define SA2400_MANRX_RXOSI_MASK __BITS(15,13)

sys/dev/ic/sa2400reg.h

215

#define SA2400_MANRX_CORNERFREQ_MASK __BITS(11,10)

sys/dev/ic/sa2400reg.h

220

#define SA2400_MANRX_RXGAIN_MASK __BITS(9,0)

sys/dev/ic/sa2400reg.h

230

#define SA2400_TX_TXOSQ_MASK __BITS(17,15)

sys/dev/ic/sa2400reg.h

233

#define SA2400_TX_TXOSI_MASK __BITS(12,10)

sys/dev/ic/sa2400reg.h

235

#define SA2400_TX_RAMP_MASK __BITS(9,8) /* Ramp-up delay,

sys/dev/ic/sa2400reg.h

243

#define SA2400_TX_HIGAIN_MASK __BITS(7,4) /* Transmitter gain settings

sys/dev/ic/sa2400reg.h

246

#define SA2400_TX_LOGAIN_MASK __BITS(3,0) /* Transmitter gain settings

sys/dev/ic/sa2400reg.h

251

#define SA2400_VCO_ZERO __BITS(6,5) /* always zero */

sys/dev/ic/sa2400reg.h

256

#define SA2400_VCO_VCOBAND_MASK __BITS(3,0) /* VCO band,

sys/dev/ic/sa2400reg.h

37

#define SA2400_TWI_DATA_MASK __BITS(31,8)

sys/dev/ic/sa2400reg.h

39

#define SA2400_TWI_ADDR_MASK __BITS(6,0)

sys/dev/ic/sa2400reg.h

49

#define SA2400_SYNA_NF_MASK __BITS(20,18) /* fractional increment value,

sys/dev/ic/sa2400reg.h

52

#define SA2400_SYNA_N_MASK __BITS(17,2) /* main divider division ratio,

sys/dev/ic/sa2400reg.h

57

#define SA2400_SYNB_R_MASK __BITS(21,12) /* reference divider ratio,

sys/dev/ic/sa2400reg.h

60

#define SA2400_SYNB_L_MASK __BITS(11,10) /* lock detect mode */

sys/dev/ic/sa2400reg.h

72

#define SA2400_SYNB_FC_MASK __BITS(7,0) /* fractional compensation

sys/dev/ic/sa2400reg.h

78

#define SA2400_SYNC_CP_MASK __BITS(7,6) /* charge pump current

sys/dev/ic/sa2400reg.h

86

#define SA2400_SYNC_SM_MASK __BITS(5,3) /* comparison divider select,

sys/dev/ic/sa2400reg.h

93

#define SA2400_SYND_ZERO1_MASK __BITS(21,17) /* always 0 */

sys/dev/ic/si4136reg.h

37

#define SI4126_TWI_DATA_MASK __BITS(21, 4)

sys/dev/ic/si4136reg.h

38

#define SI4126_TWI_ADDR_MASK __BITS(3, 0)

sys/dev/ic/si4136reg.h

44

#define SI4126_MAIN_AUXSEL_MASK __BITS(13, 12) /* aux. output pin function */

sys/dev/ic/si4136reg.h

52

#define SI4126_MAIN_IFDIV_MASK __BITS(11, 10) /* IFOUT = IFVCO

sys/dev/ic/si4136reg.h

69

#define SI4126_GAIN_KPI_MASK __BITS(5, 4) /* IF phase detector gain */

sys/dev/ic/si4136reg.h

70

#define SI4126_GAIN_KP2_MASK __BITS(3, 2) /* RF2 phase detector gain */

sys/dev/ic/si4136reg.h

71

#define SI4126_GAIN_KP1_MASK __BITS(1, 0) /* RF1 phase detector gain */

sys/dev/ic/si470x_reg.h

33

#define __BITS16(x, y) ((uint16_t)__BITS((x), (y)))

sys/dev/ic/siisatareg.h

145

#define GR_GC_PXIE_MASK __BITS(SIISATA_MAX_PORTS - 1, 0)

sys/dev/ic/siisatareg.h

150

#define GR_GIS_PXIS_MASK __BITS(SIISATA_MAX_PORTS - 1, 0)

sys/dev/ic/siisatareg.h

191

#define PRO_PCR_SLOT(x) (((x) & __BITS(4, 0)) >> 0) /* Slot */

sys/dev/ic/siisatareg.h

192

#define PRO_PCR_PMP(x) (((x) & __BITS(8, 5)) >> 5) /* PM Port */

sys/dev/ic/siisatareg.h

254

#define PR_PS_ACTIVE_SLOT_MASK __BITS(20,16)

sys/dev/ic/siisatareg.h

260

#define PR_PSS_SLOT_MASK __BITS(30, 0)

sys/dev/ic/ssdfbvar.h

105

#define SSDFB_DISPLAY_CLOCK_DIVIDER_MASK __BITS(3, 0)

sys/dev/ic/ssdfbvar.h

106

#define SSDFB_DISPLAY_CLOCK_OSCILLATOR_MASK __BITS(7, 4)

sys/dev/ic/ssdfbvar.h

108

#define SSDFB_PRECHARGE_MASK __BITS(3, 0)

sys/dev/ic/ssdfbvar.h

109

#define SSDFB_DISCHARGE_MASK __BITS(7, 4)

sys/dev/ic/ssdfbvar.h

171

#define SSD1322_PHASE_LENGTH_PHASE_2_MASK __BITS(7, 4)

sys/dev/ic/ssdfbvar.h

173

#define SSD1322_PHASE_LENGTH_PHASE_1_MASK __BITS(3, 0)

sys/dev/ic/ssdfbvar.h

176

#define SSD1322_FREQUENCY_MASK __BITS(7, 4)

sys/dev/ic/ssdfbvar.h

178

#define SSD1322_DIVIDER_MASK __BITS(3, 0)

sys/dev/ic/ssdfbvar.h

187

#define SSD1322_GPIO0_HIGH __BITS(1, 0)

sys/dev/ic/ssdfbvar.h

191

#define SSD1322_GPIO1_HIGH __BITS(3, 2)

sys/dev/ic/ssdfbvar.h

245

#define SSD1353_REMAP_PIXEL_FORMAT_MASK __BITS(7, 6)

sys/dev/ic/tpmreg.h

148

#define TPM_TYPE_POLARITY __BITS(4,3)

sys/dev/ic/tpmreg.h

174

#define TPM_STS_BURST_COUNT __BITS(23,8)

sys/dev/ic/tpmreg.h

175

#define TPM_STS_STATUS_BITS __BITS(7,0)

sys/dev/ipmivar.h

152

#define IPMI_WDOG_USE_RSVD1 __BITS(5, 3)

sys/dev/ipmivar.h

153

#define IPMI_WDOG_USE_USE_MASK __BITS(2, 0)

sys/dev/ipmivar.h

162

#define IPMI_WDOG_ACT_PRE_MASK __BITS(6, 4)

sys/dev/ipmivar.h

168

#define IPMI_WDOG_ACT_MASK __BITS(2, 0)

sys/dev/ipmivar.h

174

#define IPMI_WDOG_FLAGS_RSVD1 __BITS(7, 6)

sys/dev/marvell/gtbrgreg.h

67

#define BRG_BCR_CDV __BITS(15,0) /* Count Down Value */

sys/dev/marvell/gtbrgreg.h

70

#define BRG_BCR_CLKS_MASK __BITS(22,18) /* Clock Source */

sys/dev/marvell/gtbrgreg.h

78

#define BRG_BCR_RES __BITS(31,23)

sys/dev/marvell/gtbrgreg.h

82

#define BRG_BTR_CUV __BITS(15,0) /* Count Up Value */

sys/dev/marvell/gtbrgreg.h

83

#define BRG_BTR_RES __BITS(31,16)

sys/dev/marvell/gtbrgreg.h

90

#define BRG_INTR_RES __BITS(31,3)

sys/dev/marvell/gtmpscreg.h

102

#define GTMPSC_CRR_RESa __BITS(7,4)

sys/dev/marvell/gtmpscreg.h

103

#define GTMPSC_CRR_RESb __BITS(31,12)

sys/dev/marvell/gtmpscreg.h

108

#define GTMPSC_MMCR_LO_MODE_MASK __BITS(2,0)

sys/dev/marvell/gtmpscreg.h

115

#define GTMPSC_MMCR_LO_LPBK_MASK __BITS(9,8) /* Loop Back */

sys/dev/marvell/gtmpscreg.h

124

#define GTMPSC_MMCR_LO_TSNS_MASK __BITS(15,14) /* Transmit Sense */

sys/dev/marvell/gtmpscreg.h

133

#define GTMPSC_MMCR_LO_CRCM_MASK __BITS(25,23) /* CRC Mode */

sys/dev/marvell/gtmpscreg.h

135

#define GTMPSC_MMCR_LO_RESe __BITS(27,26)

sys/dev/marvell/gtmpscreg.h

148

#define GTMPSC_MMCR_HI_TPL __BITS(4,2) /* TX Preable Length */

sys/dev/marvell/gtmpscreg.h

151

#define GTMPSC_MMCR_HI_TPPT_MASK __BITS(8,5) /* TX Preable Pattern */

sys/dev/marvell/gtmpscreg.h

153

#define GTMPSC_MMCR_HI_TCDV_MASK __BITS(10,9) /* TX Clock Divide */

sys/dev/marvell/gtmpscreg.h

158

#define GTMPSC_MMCR_HI_TDEC_MASK __BITS(13,11) /* TX Encoder */

sys/dev/marvell/gtmpscreg.h

165

#define GTMPSC_MMCR_HI_RESa __BITS(15,14)

sys/dev/marvell/gtmpscreg.h

167

#define GTMPSC_MMCR_HI_GDW __BITS(20,17) /* Clock Glitch Width */

sys/dev/marvell/gtmpscreg.h

170

#define GTMPSC_MMCR_HI_RSYL_MASK __BITS(24,23) /* Receive Sync Width */

sys/dev/marvell/gtmpscreg.h

175

#define GTMPSC_MMCR_HI_RCDV_MASK __BITS(26,25) /* Receive Clock Divider */

sys/dev/marvell/gtmpscreg.h

180

#define GTMPSC_MMCR_HI_RENC_MASK __BITS(29,27) /* Receive Encoder */

sys/dev/marvell/gtmpscreg.h

187

#define GTMPSC_MMCR_HI_SEDG_MASK __BITS(31,30) /* Sync Clock Edge */

sys/dev/marvell/gtmpscreg.h

201

#define SDMA_CSR_RX_RESb __BITS(5,4)

sys/dev/marvell/gtmpscreg.h

203

#define SDMA_CSR_RX_RESc __BITS(8,7)

sys/dev/marvell/gtmpscreg.h

213

#define SDMA_CSR_RX_RESd __BITS(22,18)

sys/dev/marvell/gtmpscreg.h

215

#define SDMA_CSR_RX_RESe __BITS(29,24)

sys/dev/marvell/gtmpscreg.h

225

#define SDMA_CSR_TX_RESb __BITS(14,2)

sys/dev/marvell/gtmpscreg.h

232

#define SDMA_CSR_TX_RESc __BITS(22,21)

sys/dev/marvell/gtmpscreg.h

234

#define SDMA_CSR_TX_RESd __BITS(29,24)

sys/dev/marvell/gtmpscreg.h

242

#define GTMPSC_MPCR_RESa __BITS(5,0)

sys/dev/marvell/gtmpscreg.h

247

#define GTMPSC_MPCR_UM_MASK __BITS(11,10) /* UART Mode mask */

sys/dev/marvell/gtmpscreg.h

251

#define GTMPSC_MPCR_CLMASK __BITS(13,12) /* Character Length mask */

sys/dev/marvell/gtmpscreg.h

260

#define GTMPSC_MPCR_RESb __BITS(31,16)

sys/dev/marvell/gtmpscreg.h

265

#define GTMPSC_CHR1_TCS __BITS(7,0) /* Constrol Stuff Character */

sys/dev/marvell/gtmpscreg.h

266

#define GTMPSC_CHR1_BRK __BITS(23,16) /* Break Count */

sys/dev/marvell/gtmpscreg.h

267

#define GTMPSC_CHR1_RES __BITS(15,8)|__BITS(31,24)

sys/dev/marvell/gtmpscreg.h

273

#define GTMPSC_CHR2_TPM_MASK __BITS(3,2) /* Tx Parity Mode mask */

sys/dev/marvell/gtmpscreg.h

278

#define GTMPSC_CHR2_RESb __BITS(6,4)

sys/dev/marvell/gtmpscreg.h

282

#define GTMPSC_CHR2_RESd __BITS(16,10)

sys/dev/marvell/gtmpscreg.h

284

#define GTMPSC_CHR2_RPM_MASK __BITS(19,18) /* Rx Parity Mode mask */

sys/dev/marvell/gtmpscreg.h

289

#define GTMPSC_CHR2_RESe __BITS(22,20)

sys/dev/marvell/gtmpscreg.h

293

#define GTMPSC_CHR2_RESg __BITS(30,26)

sys/dev/marvell/gtmpscreg.h

302

#define GTMPSC_CHR3_MIR __BITS(15,0) /* Max Idle Char count */

sys/dev/marvell/gtmpscreg.h

303

#define GTMPSC_CHR3_RES __BITS(31,16)

sys/dev/marvell/gtmpscreg.h

307

#define GTMPSC_CHR4_CFR __BITS(7,0) /* Control bit compare enable */

sys/dev/marvell/gtmpscreg.h

308

#define GTMPSC_CHR4_RES __BITS(31,8)

sys/dev/marvell/gtmpscreg.h

315

#define GTMPSC_CHRCC_CHAR __BITS(7,0) /* the control character */

sys/dev/marvell/gtmpscreg.h

316

#define GTMPSC_CHRCC_RES __BITS(11,8)

sys/dev/marvell/gtmpscreg.h

324

#define GTMPSC_CHR9_AD1 __BITS(7,0) /* address #1 */

sys/dev/marvell/gtmpscreg.h

325

#define GTMPSC_CHR9_RESa __BITS(14,8)

sys/dev/marvell/gtmpscreg.h

327

#define GTMPSC_CHR9_AD2 __BITS(23,16) /* address #2 */

sys/dev/marvell/gtmpscreg.h

328

#define GTMPSC_CHR9_RESb __BITS(30,24)

sys/dev/marvell/gtmpscreg.h

342

#define GTMPSC_CHR10_RESd __BITS(10,8)

sys/dev/marvell/gtmpscreg.h

344

#define GTMPSC_CHR10_RESe __BITS(15,12)

sys/dev/marvell/gtmpscreg.h

345

#define GTMPSC_CHR10_RCRn __BITS(23,16) /* Received Control Char # */

sys/dev/marvell/gtmpscreg.h

346

#define GTMPSC_CHR10_RESf __BITS(31,24)

sys/dev/marvell/gtmpscreg.h

82

#define GTMPSC_MRR_MR0_MASK __BITS(2,0) /* routing mask for MPSC0 */

sys/dev/marvell/gtmpscreg.h

83

#define GTMPSC_MRR_RESa __BITS(5,3)

sys/dev/marvell/gtmpscreg.h

84

#define GTMPSC_MRR_MR1_MASK __BITS(8,6) /* routing mask for MPSC1 */

sys/dev/marvell/gtmpscreg.h

85

#define GTMPSC_MRR_RESb __BITS(30,9)

sys/dev/marvell/gtsdmareg.h

111

#define SDMA_INTR_RESa __BITS(7,4)

sys/dev/marvell/gtsdmareg.h

112

#define SDMA_INTR_RESb __BITS(31,12)

sys/dev/marvell/gtsdmareg.h

114

#define SDMA_U_INTR_MASK(u) U__(__BITS(3,0),u)

sys/dev/marvell/gtsdmareg.h

136

#define SDMA_RX_CNT_BCNT_MASK __BITS(15,0) /* " " */

sys/dev/marvell/gtsdmareg.h

138

#define SDMA_RX_CNT_BUFSZNT_SIZE_MASK __BITS(31,19) /* " " */

sys/dev/marvell/gtsdmareg.h

139

#define SDMA_RX_CNT_BUFP_MASK __BITS(31,3) /* buffer pointer */

sys/dev/marvell/gtsdmareg.h

140

#define SDMA_RX_CNT_NEXT_MASK __BITS(31,4) /* next desc. pointer */

sys/dev/marvell/gtsdmareg.h

143

#define SDMA_TX_CNT_SBC_MASK __BITS(15,0) /* " " " */

sys/dev/marvell/gtsdmareg.h

145

#define SDMA_TX_CNT_BCNT_MASK __BITS(31,16 /* " " */

sys/dev/marvell/gtsdmareg.h

146

#define SDMA_TX_CNT_NEXT_MASK __BITS(31,4) /* next desc. pointer */

sys/dev/marvell/gtsdmareg.h

75

#define SDMA_SDC_RC_MASK __BITS(5,2) /* Re-TX count */

sys/dev/marvell/gtsdmareg.h

81

#define SDMA_SDC_RESa __BITS(11,10)

sys/dev/marvell/gtsdmareg.h

82

#define SDMA_SDC_BSZ_MASK __BITS(13,12) /* Maximum Burst Size */

sys/dev/marvell/gtsdmareg.h

87

#define SDMA_SDC_RESb __BITS(31,14)

sys/dev/marvell/gtsdmareg.h

92

#define SDMA_SDCM_RESa __BITS(6,0)

sys/dev/marvell/gtsdmareg.h

94

#define SDMA_SDCM_RESb __BITS(14,8)

sys/dev/marvell/gtsdmareg.h

97

#define SDMA_SDCM_RESc __BITS(22,17)

sys/dev/marvell/gtsdmareg.h

99

#define SDMA_SDCM_RESd __BITS(30,24)

sys/dev/marvell/mvgbereg.h

360

#define MVGBE_SDC_IPGINTRX_V1_MASK __BITS(21, 8)

sys/dev/marvell/mvgbereg.h

361

#define MVGBE_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7))

sys/dev/marvell/mvgbereg.h

453

#define MVGBE_PTFUT_IPGINTTX_V1_MASK __BITS(17, 4)

sys/dev/marvell/mvgbereg.h

454

#define MVGBE_PTFUT_IPGINTTX_V2_MASK __BITS(19, 4)

sys/dev/marvell/mvxpsecreg.h

203

#define MV_TDMA_BAR_BASE_MASK __BITS(31,16)

sys/dev/marvell/mvxpsecreg.h

206

#define MV_TDMA_ATTR_SIZE_MASK __BITS(31,16)

sys/dev/marvell/mvxpsecreg.h

207

#define MV_TDMA_ATTR_ATTR_MASK __BITS(31,16)

sys/dev/marvell/mvxpsecreg.h

219

#define MV_TDMA_CONTROL_DST_BURST_MASK __BITS(2,0)

sys/dev/marvell/mvxpsecreg.h

225

#define MV_TDMA_CONTROL_SRC_BURST_MASK __BITS(8,6)

sys/dev/marvell/mvxpsecreg.h

235

#define MV_TDMA_CONTROL_OUTS_MODE_MASK __BITS(17,16)

sys/dev/marvell/mvxpsecvar.h

496

#define MVXPSEC_DEBUG_ALL __BITS(11,0)

sys/dev/mii/atphy.c

138

PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3)));

sys/dev/mii/inbmphyreg.h

168

#define I82579_LPI_CTRL_ENABLE __BITS(14, 13)

sys/dev/mii/mcommphy.c

100

#define YT8531_RGMII_RXD_DS_LOMASK __BITS(5, 4)

sys/dev/mii/mcommphy.c

106

#define YT8531_RGMII_RXD_DS_LOBITS __BITS(1, 0)

sys/dev/mii/mcommphy.c

118

#define YT8531_CLK_SRC_SEL_MASK __BITS(3, 1)

sys/dev/mii/mcommphy.c

61

#define YT8511_TX_CLK_DELAY_SEL __BITS(7,4)

sys/dev/mii/mcommphy.c

62

#define YT8511_CLK_25M_SEL __BITS(2,1)

sys/dev/mii/mcommphy.c

67

#define YT8511_FE_TX_CLK_DELAY_SEL __BITS(15,12)

sys/dev/mii/mcommphy.c

80

#define YT8521_CFG_LDO_MASK __BITS(5, 4)

sys/dev/mii/mcommphy.c

89

#define YT8521_RX_DELAY_SEL_MASK __BITS(13, 10)

sys/dev/mii/mcommphy.c

90

#define YT8521_FE_TX_DELAY_SEL_MASK __BITS(7, 4)

sys/dev/mii/mcommphy.c

91

#define YT8521_GE_TX_DELAY_SEL_MASK __BITS(3, 0)

sys/dev/mii/mcommphy.c

98

#define YT8531_RGMII_RXC_DS_MASK __BITS(15, 13)

sys/dev/mii/rgephyreg.h

77

#define RGEPHY_PHYSR_SPEED __BITS(5,4)

sys/dev/nvmm/x86/nvmm_x86.c

461

if (__predict_false(pat[i] & ~__BITS(2,0)))

sys/dev/nvmm/x86/nvmm_x86.c

492

KASSERTMSG((xcr0 & ~__BITS(62, 0)) == 0, "xcr0=0x%"PRIx64, xcr0);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1182

#define SVM_EXIT_IO_PORT __BITS(31,16)

sys/dev/nvmm/x86/nvmm_x86_svm.c

1183

#define SVM_EXIT_IO_SEG __BITS(12,10)

sys/dev/nvmm/x86/nvmm_x86_svm.c

1944

#define SVM_SEG_ATTRIB_TYPE __BITS(3,0)

sys/dev/nvmm/x86/nvmm_x86_svm.c

1946

#define SVM_SEG_ATTRIB_DPL __BITS(6,5)

sys/dev/nvmm/x86/nvmm_x86_svm.c

2857

svm_xcr0_mask = x86_xsave_features & __BITS(62, 0);

sys/dev/nvmm/x86/nvmm_x86_svm.c

335

#define VMCB_CTRL_V_TPR __BITS(3,0)

sys/dev/nvmm/x86/nvmm_x86_svm.c

338

#define VMCB_CTRL_V_INTR_PRIO __BITS(19,16)

sys/dev/nvmm/x86/nvmm_x86_svm.c

343

#define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32)

sys/dev/nvmm/x86/nvmm_x86_svm.c

354

#define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0)

sys/dev/nvmm/x86/nvmm_x86_svm.c

355

#define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8)

sys/dev/nvmm/x86/nvmm_x86_svm.c

358

#define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32)

sys/dev/nvmm/x86/nvmm_x86_svm.c

368

#define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0)

sys/dev/nvmm/x86/nvmm_x86_svm.c

373

#define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0)

sys/dev/nvmm/x86/nvmm_x86_svm.c

374

#define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8)

sys/dev/nvmm/x86/nvmm_x86_svm.c

377

#define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32)

sys/dev/nvmm/x86/nvmm_x86_svm.c

408

#define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12)

sys/dev/nvmm/x86/nvmm_x86_svm.c

409

#define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1616

#define VMX_QUAL_CR_NUM __BITS(3,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1617

#define VMX_QUAL_CR_TYPE __BITS(5,4)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1623

#define VMX_QUAL_CR_GPR __BITS(11,8)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1820

#define VMX_QUAL_IO_SIZE __BITS(2,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1828

#define VMX_QUAL_IO_PORT __BITS(31,16)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1830

#define VMX_INFO_IO_ADRSIZE __BITS(9,7)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1834

#define VMX_INFO_IO_SEG __BITS(17,15)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

198

#define IA32_VMX_BASIC_IDENT __BITS(30,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

199

#define IA32_VMX_BASIC_DATA_SIZE __BITS(44,32)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

202

#define IA32_VMX_BASIC_MEM_TYPE __BITS(53,50)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2458

exitcode &= __BITS(15,0);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2655

#define VMX_SEG_ATTRIB_TYPE __BITS(3,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2657

#define VMX_SEG_ATTRIB_DPL __BITS(6,5)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

283

#define EPTP_TYPE __BITS(2,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

286

#define EPTP_WALKLEN __BITS(5,3)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

289

#define EPTP_PHYSADDR __BITS(63,12)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3844

vmx_xcr0_mask = x86_xsave_features & __BITS(62, 0);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

388

#define INTR_INFO_VECTOR __BITS(7,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

389

#define INTR_INFO_TYPE __BITS(10,8)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

614

#define VMXON_IDENT_REVISION __BITS(30,0)

sys/dev/nvmm/x86/nvmm_x86_vmx.c

630

#define VMCS_IDENT_REVISION __BITS(30,0)

sys/dev/pci/agp_i810.c

737

hi = __SHIFTOUT(addr, __BITS(63, 32));

sys/dev/pci/agp_i810.c

738

lo = __SHIFTOUT(addr, __BITS(31, 0));

sys/dev/pci/cx23885reg.h

102

#define CX_RISC_CNT_CTL __BITS(17,16)

sys/dev/pci/cxdtvreg.h

126

#define MPG_BAD_SOP_STAT __BITS(11,0)

sys/dev/pci/cxdtvreg.h

129

#define IPB_SOP_SEL __BITS(15, 14)

sys/dev/pci/cxdtvreg.h

153

#define CX_RISC_CNT_CTL __BITS(17,16)

sys/dev/pci/hdaudio_pci.h

41

#define HDAUDIO_INTEL_ICH_TCSEL_MASK __BITS(2,0)

sys/dev/pci/ichsmb.c

354

sbreg = ((uint64_t)sbreghi << 32) | (sbreglo & ~__BITS(0,3));

sys/dev/pci/if_aq.c

1086

#define PHYINFO1_FAULT_CODE __BITS(31,16)

sys/dev/pci/if_aq.c

1087

#define PHYINFO1_PHY_H_BIT __BITS(0,15)

sys/dev/pci/if_aq.c

1089

#define PHYINFO2_TEMPERATURE __BITS(15,0)

sys/dev/pci/if_aq.c

1090

#define PHYINFO2_CABLE_LEN __BITS(23,16)

sys/dev/pci/if_aq.c

1111

#define AQ_LINK_AUTO __BITS(31, 0)

sys/dev/pci/if_aq.c

1145

#define RXDESC_TYPE_RSSTYPE __BITS(3,0)

sys/dev/pci/if_aq.c

1153

#define RXDESC_TYPE_PKTTYPE_ETHER __BITS(5,4)

sys/dev/pci/if_aq.c

1158

#define RXDESC_TYPE_PKTTYPE_PROTO __BITS(8,6)

sys/dev/pci/if_aq.c

1167

#define RXDESC_TYPE_RESERVED __BITS(18,13)

sys/dev/pci/if_aq.c

1171

#define RXDESC_TYPE_HDR_LEN __BITS(31,22)

sys/dev/pci/if_aq.c

1181

#define RXDESC_STATUS_STAT __BITS(2,5)

sys/dev/pci/if_aq.c

1182

#define RXDESC_STATUS_ESTAT __BITS(6,11)

sys/dev/pci/if_aq.c

1183

#define RXDESC_STATUS_RSC_CNT __BITS(12,15)

sys/dev/pci/if_aq.c

1200

#define AQ_TXDESC_CTL1_BLEN __BITS(19,4) /* TXD */

sys/dev/pci/if_aq.c

1210

#define AQ_TXDESC_CTL1_VID __BITS(15,4) /* TXC */

sys/dev/pci/if_aq.c

1214

#define AQ_TXDESC_CTL2_LEN __BITS(31,14)

sys/dev/pci/if_aq.c

162

#define FW2X_LINKLED __BITS(0,1)

sys/dev/pci/if_aq.c

167

#define FW2X_STATUSLED __BITS(2,5)

sys/dev/pci/if_aq.c

179

#define FW1X_MPI_STATE_MODE __BITS(7,0)

sys/dev/pci/if_aq.c

180

#define FW1X_MPI_STATE_SPEED __BITS(32,16)

sys/dev/pci/if_aq.c

181

#define FW1X_MPI_STATE_DISABLE_DIRTYWAKE __BITS(25)

sys/dev/pci/if_aq.c

182

#define FW1X_MPI_STATE_DOWNSHIFT __BITS(31,28)

sys/dev/pci/if_aq.c

219

#define AQ_INTR_IRQ_MAP_TX_IRQMAP(i) (__BITS(28,24) >> (((i) & 1)*8))

sys/dev/pci/if_aq.c

222

#define AQ_INTR_IRQ_MAP_RX_IRQMAP(i) (__BITS(12,8) >> (((i) & 1)*8))

sys/dev/pci/if_aq.c

230

#define AQ_INTR_CTRL_IRQMODE __BITS(1,0)

sys/dev/pci/if_aq.c

252

#define RX_TCP_RSS_HASH_RPF2 __BITS(19,16)

sys/dev/pci/if_aq.c

253

#define RX_TCP_RSS_HASH_TYPE __BITS(15,0)

sys/dev/pci/if_aq.c

265

#define RPF_L2BC_ACTION __BITS(12,14)

sys/dev/pci/if_aq.c

266

#define RPF_L2BC_THRESHOLD __BITS(31,16)

sys/dev/pci/if_aq.c

271

#define RPF_L2UC_MSW_MACADDR_HI __BITS(15,0)

sys/dev/pci/if_aq.c

272

#define RPF_L2UC_MSW_ACTION __BITS(18,16)

sys/dev/pci/if_aq.c

273

#define RPF_L2UC_MSW_TAG __BITS(27,22) /* AQ2 */

sys/dev/pci/if_aq.c

291

#define RPF_VLAN_MODE_UNTAGGED_ACTION __BITS(5,3)

sys/dev/pci/if_aq.c

294

#define RPF_VLAN_TPID_OUTER __BITS(31,16)

sys/dev/pci/if_aq.c

295

#define RPF_VLAN_TPID_INNER __BITS(15,0)

sys/dev/pci/if_aq.c

302

#define RPF_VLAN_FILTER_RXQ __BITS(24,20)

sys/dev/pci/if_aq.c

303

#define RPF_VLAN_FILTER_ACTION __BITS(18,16)

sys/dev/pci/if_aq.c

304

#define RPF_VLAN_FILTER_TAG __BITS(15,12) /* AQ2 */

sys/dev/pci/if_aq.c

305

#define RPF_VLAN_FILTER_ID __BITS(11,0)

sys/dev/pci/if_aq.c

312

#define RPF_ETHERTYPE_FILTER_PRIO __BITS(28,26)

sys/dev/pci/if_aq.c

313

#define RPF_ETHERTYPE_FILTER_RXQF __BITS(24,20)

sys/dev/pci/if_aq.c

315

#define RPF_ETHERTYPE_FILTER_ACTION __BITS(18,16)

sys/dev/pci/if_aq.c

316

#define RPF_ETHERTYPE_FILTER_VAL __BITS(15,0)

sys/dev/pci/if_aq.c

330

#define RPF_L3_FILTER_L4_ACTION __BITS(16,18)

sys/dev/pci/if_aq.c

331

#define RPF_L3_FILTER_L4_RXQUEUE __BITS(12,8)

sys/dev/pci/if_aq.c

332

#define RPF_L3_FILTER_L4_PROTO __BITS(2,0)

sys/dev/pci/if_aq.c

3454

(int)__SHIFTOUT(v, __BITS(31, 24)),

sys/dev/pci/if_aq.c

3455

(int)__SHIFTOUT(v, __BITS(23, 16)),

sys/dev/pci/if_aq.c

3456

(int)__SHIFTOUT(v, __BITS(15, 8)),

sys/dev/pci/if_aq.c

3457

(int)__SHIFTOUT(v, __BITS(7, 0)));

sys/dev/pci/if_aq.c

350

#define RPF_RSS_KEY_ADDR __BITS(4,0)

sys/dev/pci/if_aq.c

356

#define RPF_RSS_REDIR_ADDR __BITS(3,0)

sys/dev/pci/if_aq.c

360

#define RPF_RSS_REDIR_WR_DATA __BITS(15,0)

sys/dev/pci/if_aq.c

369

#define RPO_LRO_CONF_QSESSION_LIMIT __BITS(13,12)

sys/dev/pci/if_aq.c

370

#define RPO_LRO_CONF_TOTAL_DESC_LIMIT __BITS(6,5)

sys/dev/pci/if_aq.c

372

#define RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT __BITS(4,0)

sys/dev/pci/if_aq.c

379

#define RPO_LRO_TB_DIV __BITS(20,31)

sys/dev/pci/if_aq.c

381

#define RPO_LRO_INACTIVE_IVAL __BITS(10,19)

sys/dev/pci/if_aq.c

383

#define RPO_LRO_MAX_COALESCING_IVAL __BITS(9,0)

sys/dev/pci/if_aq.c

387

#define RPB_RPF_RX_FC_MODE __BITS(5,4)

sys/dev/pci/if_aq.c

392

#define RPB_RXB_BUFSIZE __BITS(8,0)

sys/dev/pci/if_aq.c

395

#define RPB_RXB_XOFF_THRESH_HI __BITS(29,16)

sys/dev/pci/if_aq.c

396

#define RPB_RXB_XOFF_THRESH_LO __BITS(13,0)

sys/dev/pci/if_aq.c

408

#define RX_INTR_MODERATION_CTL_MIN __BITS(15,8)

sys/dev/pci/if_aq.c

409

#define RX_INTR_MODERATION_CTL_MAX __BITS(24,16)

sys/dev/pci/if_aq.c

415

#define RX_DMA_DESC_LEN __BITS(12,3) /* RXD_NUM/8 */

sys/dev/pci/if_aq.c

421

#define RX_DMA_DESC_HEAD_PTR __BITS(12,0)

sys/dev/pci/if_aq.c

424

#define RX_DMA_DESC_BUFSIZE_DATA __BITS(4,0)

sys/dev/pci/if_aq.c

425

#define RX_DMA_DESC_BUFSIZE_HDR __BITS(12,8)

sys/dev/pci/if_aq.c

429

#define RX_DMA_DCAD_CPUID __BITS(7,0)

sys/dev/pci/if_aq.c

436

#define RX_DMA_DCA_MODE __BITS(3,0)

sys/dev/pci/if_aq.c

457

#define TPS_DESC_RATE_LIM __BITS(10,0)

sys/dev/pci/if_aq.c

459

#define TPS_DESC_TC_ARB_MODE __BITS(1,0)

sys/dev/pci/if_aq.c

465

#define TPS_DATA_TCT_CREDIT_MAX __BITS(16,27)

sys/dev/pci/if_aq.c

466

#define TPS_DATA_TCT_WEIGHT __BITS(8,0)

sys/dev/pci/if_aq.c

469

#define TPS_DESC_TCT_CREDIT_MAX __BITS(16,27)

sys/dev/pci/if_aq.c

470

#define TPS_DESC_TCT_WEIGHT __BITS(8,0)

sys/dev/pci/if_aq.c

484

#define THM_LSO_TCP_FLAG1_FIRST __BITS(11,0)

sys/dev/pci/if_aq.c

485

#define THM_LSO_TCP_FLAG1_MID __BITS(27,16)

sys/dev/pci/if_aq.c

487

#define THM_LSO_TCP_FLAG2_LAST __BITS(11,0)

sys/dev/pci/if_aq.c

498

#define TPB_TXB_BUFSIZE __BITS(7,0)

sys/dev/pci/if_aq.c

500

#define TPB_TXB_THRESH_HI __BITS(16,28)

sys/dev/pci/if_aq.c

501

#define TPB_TXB_THRESH_LO __BITS(12,0)

sys/dev/pci/if_aq.c

512

#define TX_DMA_DESC_LEN __BITS(12, 3) /* TXD_NUM/8 */

sys/dev/pci/if_aq.c

515

#define TX_DMA_DESC_HEAD_PTR __BITS(12,0)

sys/dev/pci/if_aq.c

518

#define TX_DMA_DESC_WRWB_THRESH __BITS(14,8)

sys/dev/pci/if_aq.c

522

#define TDM_DCAD_CPUID __BITS(7,0)

sys/dev/pci/if_aq.c

527

#define TDM_DCA_MODE __BITS(3,0)

sys/dev/pci/if_aq.c

532

#define TX_INTR_MODERATION_CTL_MIN __BITS(15,8)

sys/dev/pci/if_aq.c

533

#define TX_INTR_MODERATION_CTL_MAX __BITS(24,16)

sys/dev/pci/if_aq.c

559

#define AQ2_ART_ACTION_ACT_MASK __BITS(9,8)

sys/dev/pci/if_aq.c

561

#define AQ2_ART_ACTION_INDEX_MASK __BITS(6,2)

sys/dev/pci/if_aq.c

573

#define AQ2_RPF_TAG_PCP_MASK __BITS(31,29)

sys/dev/pci/if_aq.c

574

#define AQ2_RPF_TAG_FLEX_MASK __BITS(28,27)

sys/dev/pci/if_aq.c

575

#define AQ2_RPF_TAG_UNKNOWN_MASK __BITS(26,24)

sys/dev/pci/if_aq.c

576

#define AQ2_RPF_TAG_L4_MASK __BITS(23,21)

sys/dev/pci/if_aq.c

577

#define AQ2_RPF_TAG_L3_V6_MASK __BITS(20,18)

sys/dev/pci/if_aq.c

578

#define AQ2_RPF_TAG_L3_V4_MASK __BITS(17,15)

sys/dev/pci/if_aq.c

580

#define AQ2_RPF_TAG_VLAN_MASK __BITS(13,10)

sys/dev/pci/if_aq.c

581

#define AQ2_RPF_TAG_ET_MASK __BITS(9,7)

sys/dev/pci/if_aq.c

583

#define AQ2_RPF_TAG_UC_MASK __BITS(5,0)

sys/dev/pci/if_aq.c

594

#define AQ2_RPF_L2BC_TAG_MASK __BITS(5,0)

sys/dev/pci/if_aq.c

600

#define AQ2_RPF_L2UC_TAG_MASK __BITS(27,22)

sys/dev/pci/if_aq.c

604

#define AQ2_RPF_REDIR2_HASHTYPE __BITS(8,0)

sys/dev/pci/if_aq.c

615

#define AQ2_RPF_REDIR2_HASHTYPE_ALL __BITS(8,0)

sys/dev/pci/if_aq.c

624

(__BITS(4,0) << (5 * ((tc) & 3)))

sys/dev/pci/if_aq.c

630

#define AQ2_RPF_REC_TAB_ENABLE_MASK __BITS(15,0)

sys/dev/pci/if_aq.c

635

#define AQ2_LAUNCHTIME_CTRL_RATIO __BITS(15,8)

sys/dev/pci/if_aq.c

643

#define AQ2_TX_INTR_MODERATION_CTL_MIN __BITS(15,8)

sys/dev/pci/if_aq.c

644

#define AQ2_TX_INTR_MODERATION_CTL_MAX __BITS(24,16)

sys/dev/pci/if_aq.c

660

#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE __BITS(3,0)

sys/dev/pci/if_aq.c

668

#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT_RETRY __BITS(31,28)

sys/dev/pci/if_aq.c

695

#define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_WARN_TEMP __BITS(24,31)

sys/dev/pci/if_aq.c

696

#define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_COLD_TEMP __BITS(16,23)

sys/dev/pci/if_aq.c

697

#define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_SHUTDOWN_TEMP __BITS(15,8)

sys/dev/pci/if_aq.c

709

#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX __BITS(22,18)

sys/dev/pci/if_aq.c

712

#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX __BITS(14,10)

sys/dev/pci/if_aq.c

715

#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX __BITS(6,2)

sys/dev/pci/if_aq.c

721

#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B __BITS(31,16)

sys/dev/pci/if_aq.c

722

#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A __BITS(15,0)

sys/dev/pci/if_aq.c

726

#define AQ2_FW_INTERFACE_OUT_VERSION_BUILD __BITS(31,16)

sys/dev/pci/if_aq.c

727

#define AQ2_FW_INTERFACE_OUT_VERSION_MINOR __BITS(8,15)

sys/dev/pci/if_aq.c

728

#define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR __BITS(7,0)

sys/dev/pci/if_aq.c

730

#define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER __BITS(3,0)

sys/dev/pci/if_aq.c

738

#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE __BITS(7,4)

sys/dev/pci/if_aq.c

746

#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_STATE __BITS(3,0)

sys/dev/pci/if_aq.c

757

#define HEALTH_MONITOR_DATA1_TEMPERATURE __BITS(15,8)

sys/dev/pci/if_aq.c

758

#define HEALTH_MONITOR_DATA1_HEARTBEAT __BITS(31,16)

sys/dev/pci/if_aq.c

760

#define HEALTH_MONITOR_DATA2_FAULTCODE __BITS(15,0)

sys/dev/pci/if_aq.c

765

#define AQ2_FW_INTERFACE_OUT_CABLE_DIAG_STATUS_IDSTAT_ID __BITS(7,0)

sys/dev/pci/if_aq.c

766

#define AQ2_FW_INTERFACE_OUT_CABLE_DIAG_STATUS_IDSTAT_STATUS __BITS(8,11)

sys/dev/pci/if_aq.c

845

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_ETHTYPE_FILTER_COUNT __BITS(24,31)

sys/dev/pci/if_aq.c

846

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_ETHTYPE_FILTER_BASE_INDEX __BITS(16,23)

sys/dev/pci/if_aq.c

847

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_L2_FILTER_COUNT __BITS(8,15)

sys/dev/pci/if_aq.c

848

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_FLEXIBLE_FILTER_MASK __BITS(6,7)

sys/dev/pci/if_aq.c

849

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_L2_FILTER_BASE_INDEX __BITS(0,5)

sys/dev/pci/if_aq.c

851

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP6_FILTER_COUNT __BITS(28,31)

sys/dev/pci/if_aq.c

852

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP6_FILTER_BASE_INDEX __BITS(24,27)

sys/dev/pci/if_aq.c

853

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP4_FILTER_COUNT __BITS(20,23)

sys/dev/pci/if_aq.c

854

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP4_FILTER_BASE_INDEX __BITS(16,19)

sys/dev/pci/if_aq.c

855

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_VLAN_FILTER_COUNT __BITS(8,15)

sys/dev/pci/if_aq.c

856

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_VLAN_FILTER_BASE_INDEX __BITS(0,7)

sys/dev/pci/if_aq.c

858

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_TABLE_COUNT __BITS(24,31)

sys/dev/pci/if_aq.c

859

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX __BITS(16,23)

sys/dev/pci/if_aq.c

860

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FLEX_FILTER_COUNT __BITS(12,15)

sys/dev/pci/if_aq.c

861

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FLEX_FILTER_BASE_INDEX __BITS(8,11)

sys/dev/pci/if_aq.c

862

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FILTER_COUNT __BITS(4,7)

sys/dev/pci/if_aq.c

863

#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FILTER_BASE_INDEX __BITS(0,3)

sys/dev/pci/if_skreg.h

1295

#define SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK __BITS(4, 3)

sys/dev/pci/if_skreg.h

1296

#define SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK __BITS(1, 0)

sys/dev/pci/if_wm.c

5121

tarc0 &= ~__BITS(30, 27);

sys/dev/pci/if_wm.c

5130

tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */

sys/dev/pci/if_wm.c

5133

tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */

sys/dev/pci/if_wm.c

5134

tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */

sys/dev/pci/if_wm.c

5231

tarc0 |= __BITS(29, 28);

sys/dev/pci/if_wm.c

5243

tarc0 |= __BITS(27, 26) | __BITS(24, 23);

sys/dev/pci/if_wmreg.h

1009

#define EXTCNFSIZE_LENGTH __BITS(23, 16)

sys/dev/pci/if_wmreg.h

1041

#define PBA_RXA_MASK __BITS(15, 0)

sys/dev/pci/if_wmreg.h

1099

#define EITR_ITR_INT_MASK __BITS(14,2)

sys/dev/pci/if_wmreg.h

1100

#define EITR_COUNTER_MASK_82575 __BITS(31,16)

sys/dev/pci/if_wmreg.h

1104

#define EITR_ITR_INT_MASK_82574 __BITS(15, 0)

sys/dev/pci/if_wmreg.h

1254

#define PCS_LCTL_FSV_MASK __BITS(2, 1) /* Forced Speed Value */

sys/dev/pci/if_wmreg.h

1273

#define PCS_LSTS_SPEED __BITS(2, 1)

sys/dev/pci/if_wmreg.h

1326

#define WUFC_FLX __BITS(23, 16) /* Flexible Filter [0-7] En */

sys/dev/pci/if_wmreg.h

1327

#define WUFC_FLXACT __BITS(27, 24) /* Flexible Filter [0-3] Action */

sys/dev/pci/if_wmreg.h

1345

#define MRQC_ENABLE_RSS_VMDQ __BITS(1, 0) /* enable RSS with VMDq */

sys/dev/pci/if_wmreg.h

1346

#define MRQC_DEFQ_MASK __BITS(5, 3)

sys/dev/pci/if_wmreg.h

1357

#define MRQC_DEFQ_NOT_MAC_ETH __SHFTIN(__BITS(1, 0), MRQC_DEFQ_MASK)

sys/dev/pci/if_wmreg.h

1368

#define MRQC_DEFQ_VMDQ __SHFTIN(__BITS(2, 1), MRQC_DEFQ_MASK)

sys/dev/pci/if_wmreg.h

1383

#define RETA_ENT_QINDEX_MASK __BITS(3,0) /*queue index for 82580 and newer */

sys/dev/pci/if_wmreg.h

1384

#define RETA_ENT_QINDEX0_MASK_82575 __BITS(3,2) /*queue index for pool0 */

sys/dev/pci/if_wmreg.h

1385

#define RETA_ENT_QINDEX1_MASK_82575 __BITS(7,6) /*queue index for pool1 and regular RSS */

sys/dev/pci/if_wmreg.h

1445

#define FWSM_MODE __BITS(1, 3)

sys/dev/pci/if_wmreg.h

1449

#define FWSM_WLOCK_MAC __BITS(7, 9)

sys/dev/pci/if_wmreg.h

159

#define EXTRXC_IP_ID_MASK __BITS(15,0)

sys/dev/pci/if_wmreg.h

160

#define EXTRXC_FRAG_CSUM_MASK __BITS(31,16)

sys/dev/pci/if_wmreg.h

1642

#define INVM_VER_1 __BITS(12,3)

sys/dev/pci/if_wmreg.h

1643

#define INVM_VER_2 __BITS(22,13)

sys/dev/pci/if_wmreg.h

1644

#define INVM_IMGTYPE __BITS(28,23)

sys/dev/pci/if_wmreg.h

1645

#define INVM_MINOR __BITS(3,0)

sys/dev/pci/if_wmreg.h

1646

#define INVM_MAJOR __BITS(9,4)

sys/dev/pci/if_wmreg.h

165

#define EXTRXC_RSS_TYPE_MASK __BITS(3,0)

sys/dev/pci/if_wmreg.h

167

#define EXTRXC_QUEUE_MASK __BITS(12,8)

sys/dev/pci/if_wmreg.h

180

#define EXTRXC_STATUS_MASK __BITS(19,0)

sys/dev/pci/if_wmreg.h

181

#define EXTRXC_ERROR_MASK __BITS(31,20)

sys/dev/pci/if_wmreg.h

208

#define EXTRXC_STATUS_PKTTYPE_MASK __BITS(19,16)

sys/dev/pci/if_wmreg.h

233

#define NQRXD_ADDR_MASK __BITS(63,1)

sys/dev/pci/if_wmreg.h

247

#define NQRXC_IP_ID_MASK __BITS(15,0)

sys/dev/pci/if_wmreg.h

248

#define NQRXC_FRAG_CSUM_MASK __BITS(31,16)

sys/dev/pci/if_wmreg.h

253

#define NQRXC_RSS_TYPE_MASK __BITS(3,0)

sys/dev/pci/if_wmreg.h

254

#define NQRXC_PKT_TYPE_ID_MASK __BITS(11,4)

sys/dev/pci/if_wmreg.h

255

#define NQRXC_PKT_TYPE_ETQF_INDEX_MASK __BITS(11,4)

sys/dev/pci/if_wmreg.h

258

#define NQRXC_PKT_TYPE_MASK __BITS(16,4)

sys/dev/pci/if_wmreg.h

260

#define NQRXC_HDRLEN_HIGH_MASK __BITS(20,19)

sys/dev/pci/if_wmreg.h

261

#define NQRXC_HDRLEN_LOW_MASK __BITS(30,21)

sys/dev/pci/if_wmreg.h

297

#define NQRXC_STATUS_MASK __BITS(19,0)

sys/dev/pci/if_wmreg.h

298

#define NQRXC_ERROR_MASK __BITS(31,20)

sys/dev/pci/if_wmreg.h

466

#define STATUS_SPEED __BITS(7, 6) /* speed indication */

sys/dev/pci/if_wmreg.h

489

#define STRAP_NVMSIZE __BITS(1, 6)

sys/dev/pci/if_wmreg.h

490

#define STRAP_FREQ __BITS(12, 13)

sys/dev/pci/if_wmreg.h

491

#define STRAP_SMBUSADDR __BITS(17, 23)

sys/dev/pci/if_wmreg.h

509

#define EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */

sys/dev/pci/if_wmreg.h

529

#define CTRL_EXT_NVMVS __BITS(0, 1) /* NVM valid sector */

sys/dev/pci/if_wmreg.h

567

#define MDIC_PHY_MASK __BITS(25, 21)

sys/dev/pci/if_wmreg.h

570

#define MDIC_OP_RW_MASK __BITS(27, 26)

sys/dev/pci/if_wmreg.h

590

#define FEXTNVM4_BEACON_DURATION __BITS(2, 0)

sys/dev/pci/if_wmreg.h

657

#define FEXTNVM3_PHY_CFG_COUNTER_MASK __BITS(27, 26)

sys/dev/pci/if_wmreg.h

730

#define IVAR_ALLOC_MASK __BITS(0, 6) /* Bit 5 and 6 are reserved */

sys/dev/pci/if_wmreg.h

741

#define IVAR_ALLOC_MASK_82574 __BITS(0, 2)

sys/dev/pci/if_wmreg.h

745

#define IVAR_OTHER_MASK __BITS(16, 19)

sys/dev/pci/if_wmreg.h

749

#define IVAR_MISC_TCPTIMER __BITS(0, 7)

sys/dev/pci/if_wmreg.h

750

#define IVAR_MISC_OTHER __BITS(8, 15)

sys/dev/pci/if_wmreg.h

757

#define SVT_OFF_HWM __BITS(4, 0)

sys/dev/pci/if_wmreg.h

760

#define LTRV_VALUE __BITS(9, 0)

sys/dev/pci/if_wmreg.h

761

#define LTRV_SCALE __BITS(12, 10)

sys/dev/pci/if_wmreg.h

765

#define LTRV_NONSNOOP __BITS(31, 16)

sys/dev/pci/if_wmreg.h

782

#define RCTL_DTYP_MASK __BITS(11,10) /* descriptor type. 82574 only */

sys/dev/pci/if_wmreg.h

787

#define RCTL_MO __BITS(13, 12) /* multicast offset */

sys/dev/pci/if_wmreg.h

923

#define TIPG_IPGT_MASK __BITS(0, 9) /* IPG transmit time MASK */

sys/dev/pci/if_wmreg.h

972

#define MDICNFG_PHY_MASK __BITS(25, 21)

sys/dev/pci/ixgbe/ixgbe_osdep.c

57

return pci_conf_read(pc, tag, reg) & __BITS(15, 0);

sys/dev/pci/ixgbe/ixgbe_osdep.c

60

__BITS(31, 16));

sys/dev/pci/ixgbe/ixgbe_osdep.c

76

old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);

sys/dev/pci/ixgbe/ixgbe_osdep.c

80

old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);

sys/dev/pci/ixgbe/ixgbe_osdep.c

82

__SHIFTIN(value, __BITS(31, 16)) | old);

sys/dev/pci/pci_subr.c

3027

(uint32_t)(reg & __BITS(arbsize - 1, 0)));

sys/dev/pci/pci_subr.c

4699

devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9));

sys/dev/pci/pci_subr.c

4862

pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16)));

sys/dev/pci/pci_subr.c

5037

PCIREG_SHIFTOUT(rval, __BITS(15, 0)));

sys/dev/pci/pci_subr.c

5038

pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16)));

sys/dev/pci/pcireg.h

1001

#define PCIE_DCAP_MAX_PAYLOAD __BITS(2, 0) /* Max Payload Size Supported */

sys/dev/pci/pcireg.h

1002

#define PCIE_DCAP_PHANTOM_FUNCS __BITS(4, 3) /* Phantom Functions Supported*/

sys/dev/pci/pcireg.h

1004

#define PCIE_DCAP_L0S_LATENCY __BITS(8, 6) /* Endpoint L0 Accptbl Latency*/

sys/dev/pci/pcireg.h

1005

#define PCIE_DCAP_L1_LATENCY __BITS(11, 9) /* Endpoint L1 Accptbl Latency*/

sys/dev/pci/pcireg.h

1010

#define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */

sys/dev/pci/pcireg.h

1011

#define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */

sys/dev/pci/pcireg.h

1019

#define PCIE_DCSR_MAX_PAYLOAD __BITS(7, 5) /* Max Payload Size */

sys/dev/pci/pcireg.h

1024

#define PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) /* Max Read Request Size */

sys/dev/pci/pcireg.h

1035

#define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */

sys/dev/pci/pcireg.h

1042

#define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */

sys/dev/pci/pcireg.h

1043

#define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */

sys/dev/pci/pcireg.h

1044

#define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */

sys/dev/pci/pcireg.h

1045

#define PCIE_LCAP_L1_EXIT __BITS(17, 15) /* L1 Exit Latency */

sys/dev/pci/pcireg.h

1051

#define PCIE_LCAP_PORT __BITS(31, 24) /* Port Number */

sys/dev/pci/pcireg.h

1064

#define PCIE_LCSR_DRSSGNL __BITS(15, 14) /* DRS Signaling */

sys/dev/pci/pcireg.h

1065

#define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */

sys/dev/pci/pcireg.h

1072

#define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */

sys/dev/pci/pcireg.h

1077

#define PCIE_LCSR_NLW_X12 __BITS(22, 23) /* Negotiated x12 */

sys/dev/pci/pcireg.h

1094

#define PCIE_SLCAP_SPLV __BITS(14, 7) /* Slot Power Limit Value */

sys/dev/pci/pcireg.h

1095

#define PCIE_SLCAP_SPLS __BITS(16, 15) /* Slot Power Limit Scale */

sys/dev/pci/pcireg.h

1098

#define PCIE_SLCAP_PSN __BITS(31, 19) /* Physical Slot Number */

sys/dev/pci/pcireg.h

1106

#define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/

sys/dev/pci/pcireg.h

1107

#define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */

sys/dev/pci/pcireg.h

1135

#define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */

sys/dev/pci/pcireg.h

1139

#define PCIE_DCAP2_COMPT_RANGE __BITS(3,0) /* Compl. Timeout Ranges Supp */

sys/dev/pci/pcireg.h

1148

#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */

sys/dev/pci/pcireg.h

1149

#define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */

sys/dev/pci/pcireg.h

1152

#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/

sys/dev/pci/pcireg.h

1155

#define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */

sys/dev/pci/pcireg.h

1156

#define PCIE_DCAP2_EMGPWRRED __BITS(25, 24) /* Emergency Power Reduc. Sup */

sys/dev/pci/pcireg.h

1160

#define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */

sys/dev/pci/pcireg.h

1170

#define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */

sys/dev/pci/pcireg.h

1173

#define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */

sys/dev/pci/pcireg.h

1181

#define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9)

sys/dev/pci/pcireg.h

1183

#define PCIE_LCAP2_LOWSKPOS_RECSUPPSV __BITS(22, 16)

sys/dev/pci/pcireg.h

1188

#define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */

sys/dev/pci/pcireg.h

1195

#define PCIE_LCSR2_TX_MARGIN __BITS(9, 7) /* Transmit Margin */

sys/dev/pci/pcireg.h

1198

#define PCIE_LCSR2_COMP_DEEMP __BITS(15, 12) /* Compliance Preset/De-emph */

sys/dev/pci/pcireg.h

1206

#define PCIE_LCSR2_DSCOMPN __BITS(30, 28) /* Downstream Component Pres. */

sys/dev/pci/pcireg.h

1246

#define PCI_MSIX_TBLOFFSET_MASK __BITS(31, 3)

sys/dev/pci/pcireg.h

1247

#define PCI_MSIX_TBLBIR_MASK __BITS(2, 0)

sys/dev/pci/pcireg.h

1252

#define PCI_MSIX_PBAOFFSET_MASK __BITS(31, 3)

sys/dev/pci/pcireg.h

1253

#define PCI_MSIX_PBABIR_MASK __BITS(2, 0)

sys/dev/pci/pcireg.h

1267

#define PCI_MSIX_VECTCTL_STLO __BITS(23, 16) /* ST lower */

sys/dev/pci/pcireg.h

1268

#define PCI_MSIX_VECTCTL_STUP __BITS(31, 24) /* ST upper */

sys/dev/pci/pcireg.h

1278

#define PCI_SATA_REV_MINOR __BITS(19, 16) /* Minor Revision */

sys/dev/pci/pcireg.h

1279

#define PCI_SATA_REV_MAJOR __BITS(23, 20) /* Major Revision */

sys/dev/pci/pcireg.h

1281

#define PCI_SATA_BAR_SPEC __BITS(3, 0) /* BAR Specifier */

sys/dev/pci/pcireg.h

1282

#define PCI_SATA_BAR_INCONF __BITS(3, 0) /* All 1 = in config space */

sys/dev/pci/pcireg.h

1284

#define PCI_SATA_BAR_OFFSET __BITS(23, 4) /* BAR Offset */

sys/dev/pci/pcireg.h

1291

#define PCI_AFCAPR_MASK __BITS(31, 24)

sys/dev/pci/pcireg.h

1292

#define PCI_AF_LENGTH __BITS(23, 16) /* Structure Length */

sys/dev/pci/pcireg.h

1355

#define PCI_BRIDGE_BUS_PRIMARY __BITS(0, 7)

sys/dev/pci/pcireg.h

1356

#define PCI_BRIDGE_BUS_SECONDARY __BITS(8, 15)

sys/dev/pci/pcireg.h

1357

#define PCI_BRIDGE_BUS_SUBORDINATE __BITS(16, 23)

sys/dev/pci/pcireg.h

1358

#define PCI_BRIDGE_BUS_SEC_LATTIMER __BITS(24, 31)

sys/dev/pci/pcireg.h

1373

#define PCI_BRIDGE_STATIO_IOBASE __BITS(0, 7)

sys/dev/pci/pcireg.h

1374

#define PCI_BRIDGE_STATIO_IOLIMIT __BITS(8, 15)

sys/dev/pci/pcireg.h

1375

#define PCI_BRIDGE_STATIO_STATUS __BITS(16, 31)

sys/dev/pci/pcireg.h

1389

#define PCI_BRIDGE_MEMORY_BASE __BITS(0, 15)

sys/dev/pci/pcireg.h

1390

#define PCI_BRIDGE_MEMORY_LIMIT __BITS(16, 31)

sys/dev/pci/pcireg.h

1400

#define PCI_BRIDGE_PREFETCHMEM_BASE __BITS(0, 15)

sys/dev/pci/pcireg.h

1401

#define PCI_BRIDGE_PREFETCHMEM_LIMIT __BITS(16, 31)

sys/dev/pci/pcireg.h

1415

#define PCI_BRIDGE_IOHIGH_BASE __BITS(0, 15)

sys/dev/pci/pcireg.h

1416

#define PCI_BRIDGE_IOHIGH_LIMIT __BITS(16, 31)

sys/dev/pci/pcireg.h

1421

#define PCI_BRIDGE_CONTROL __BITS(16, 31)

sys/dev/pci/pcireg.h

1638

#define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0)

sys/dev/pci/pcireg.h

1662

#define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27)

sys/dev/pci/pcireg.h

1664

#define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0)

sys/dev/pci/pcireg.h

1665

#define PCI_AER_ERRSRC_ID_ERR_UC __BITS(31, 16)

sys/dev/pci/pcireg.h

1675

#define PCI_VC_CAP1_EXT_COUNT __BITS(2, 0)

sys/dev/pci/pcireg.h

1676

#define PCI_VC_CAP1_LOWPRI_EXT_COUNT __BITS(6, 4)

sys/dev/pci/pcireg.h

1677

#define PCI_VC_CAP1_REFCLK __BITS(9, 8)

sys/dev/pci/pcireg.h

1679

#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE __BITS(11, 10)

sys/dev/pci/pcireg.h

1685

#define PCI_VC_CAP2_ARB_TABLE_OFFSET __BITS(31, 24)

sys/dev/pci/pcireg.h

1688

#define PCI_VC_CONTROL_VC_ARB_SELECT __BITS(3, 1)

sys/dev/pci/pcireg.h

1700

#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS __BITS(22, 16)

sys/dev/pci/pcireg.h

1701

#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET __BITS(31, 24)

sys/dev/pci/pcireg.h

1703

#define PCI_VC_RESOURCE_CTL_TCVC_MAP __BITS(7, 0)

sys/dev/pci/pcireg.h

1705

#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT __BITS(19, 17)

sys/dev/pci/pcireg.h

1706

#define PCI_VC_RESOURCE_CTL_VC_ID __BITS(26, 24)

sys/dev/pci/pcireg.h

1725

#define PCI_PWRBDGT_DATA_BASEPWR __BITS(7, 0) /* Base Power */

sys/dev/pci/pcireg.h

1726

#define PCI_PWRBDGT_DATA_SCALE __BITS(9, 8) /* Data Scale */

sys/dev/pci/pcireg.h

1727

#define PCI_PWRBDGT_PM_SUBSTAT __BITS(12, 10) /* PM Sub State */

sys/dev/pci/pcireg.h

1728

#define PCI_PWRBDGT_PM_STAT __BITS(14, 13) /* PM State */

sys/dev/pci/pcireg.h

1729

#define PCI_PWRBDGT_TYPE __BITS(17, 15) /* Type */

sys/dev/pci/pcireg.h

1730

#define PCI_PWRBDGT_PWRRAIL __BITS(20, 18) /* Power Rail */

sys/dev/pci/pcireg.h

1739

#define PCI_RCLINK_DCL_ESDESC_ELMTYPE __BITS(3, 0) /* Element Type */

sys/dev/pci/pcireg.h

1740

#define PCI_RCLINK_DCL_ESDESC_NUMLINKENT __BITS(15, 8) /* Num of Link Entries*/

sys/dev/pci/pcireg.h

1741

#define PCI_RCLINK_DCL_ESDESC_COMPID __BITS(23, 16) /* Component ID */

sys/dev/pci/pcireg.h

1742

#define PCI_RCLINK_DCL_ESDESC_PORTNUM __BITS(31, 24) /* Port Number */

sys/dev/pci/pcireg.h

1749

#define PCI_RCLINK_DCL_LINKDESC_TCOMPID __BITS(23, 16) /* Target Component ID*/

sys/dev/pci/pcireg.h

1750

#define PCI_RCLINK_DCL_LINKDESC_TPNUM __BITS(31, 24) /* Target Port Number */

sys/dev/pci/pcireg.h

1757

#define PCI_RCLINK_DCL_LINKADDR_LT1_N __BITS(2, 0) /* N */

sys/dev/pci/pcireg.h

1758

#define PCI_RCLINK_DCL_LINKADDR_LT1_FUNC __BITS(14, 12) /* Function Number */

sys/dev/pci/pcireg.h

1759

#define PCI_RCLINK_DCL_LINKADDR_LT1_DEV __BITS(19, 15) /* Device Number */

sys/dev/pci/pcireg.h

1760

#define PCI_RCLINK_DCL_LINKADDR_LT1_BUS(N) __BITS(19 + (N), 20) /* Bus Number*/

sys/dev/pci/pcireg.h

1761

#define PCI_RCLINK_DCL_LINKADDR_LT1_BAL(N) __BITS(31, 20 + (N)) /* BAddr(L) */

sys/dev/pci/pcireg.h

1776

#define PCI_RCEC_ASSOCBUSNUM_RCECNEXT __BITS(15, 8) /* RCEC Next Bus */

sys/dev/pci/pcireg.h

1777

#define PCI_RCEC_ASSOCBUSNUM_RCECLAST __BITS(23, 16) /* RCEC Last Bus */

sys/dev/pci/pcireg.h

1816

#define PCI_ACS_CAP_ECVSIZE __BITS(15, 8) /* Egress Control Vector Size */

sys/dev/pci/pcireg.h

1834

#define PCI_ARI_CAP_NXTFN __BITS(15, 8) /* Next Function Number */

sys/dev/pci/pcireg.h

1838

#define PCI_ARI_CTL_FUNCGRP __BITS(22, 20) /* Function Group */

sys/dev/pci/pcireg.h

1845

#define PCI_ATS_CAP_INVQDEPTH __BITS(4, 0) /* Invalidate Queue Depth */

sys/dev/pci/pcireg.h

1850

#define PCI_ATS_CTL_STU __BITS(20, 16) /* Smallest Translation Unit */

sys/dev/pci/pcireg.h

1860

#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N __BITS(31, 21)

sys/dev/pci/pcireg.h

1882

#define PCI_SRIOV_VF_MIG_STA_OFFSET __BITS(31, 3)

sys/dev/pci/pcireg.h

1883

#define PCI_SRIOV_VF_MIG_STA_BIR __BITS(2, 0)

sys/dev/pci/pcireg.h

1895

#define PCI_MCAST_CAP_MAXGRP __BITS(5, 0) /* Max Group */

sys/dev/pci/pcireg.h

1896

#define PCI_MCAST_CAP_WINSIZEREQ __BITS(13, 8) /* Window Size Requested */

sys/dev/pci/pcireg.h

1899

#define PCI_MCAST_CTL_NUMGRP __BITS(5+16, 16) /* Num Group */

sys/dev/pci/pcireg.h

1902

#define PCI_MCAST_BARL_INDPOS __BITS(5, 0) /* Index Position */

sys/dev/pci/pcireg.h

1903

#define PCI_MCAST_BARL_ADDR __BITS(31, 12) /* Base Address Register(low)*/

sys/dev/pci/pcireg.h

1912

#define PCI_MCAST_OVERLAYL_SIZE __BITS(5, 0) /* Overlay Size */

sys/dev/pci/pcireg.h

1913

#define PCI_MCAST_OVERLAYL_ADDR __BITS(31, 6) /* Overlay BAR (low) */

sys/dev/pci/pcireg.h

1936

#define PCI_EA_CAP1_NUMENTRIES __BITS(21, 16) /* Num Entries */

sys/dev/pci/pcireg.h

1938

#define PCI_EA_CAP2_SECONDARY __BITS(7, 0) /* Fixed Secondary Bus No. */

sys/dev/pci/pcireg.h

1939

#define PCI_EA_CAP2_SUBORDINATE __BITS(15, 8) /* Fixed Subordinate Bus No. */

sys/dev/pci/pcireg.h

1942

#define PCI_EA_ES __BITS(2, 0) /* Entry Size */

sys/dev/pci/pcireg.h

1943

#define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */

sys/dev/pci/pcireg.h

1960

#define PCI_EA_PP __BITS(15, 8) /* Primary Properties */

sys/dev/pci/pcireg.h

1961

#define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */

sys/dev/pci/pcireg.h

1977

#define PCI_EA_LOWMASK __BITS(31, 2) /* Low register's mask */

sys/dev/pci/pcireg.h

1988

#define PCI_RESIZBAR_CAP_SIZEMASK __BITS(23, 4) /* BAR size bitmask */

sys/dev/pci/pcireg.h

1991

#define PCI_RESIZBAR_CTL_BARIDX __BITS(2, 0)

sys/dev/pci/pcireg.h

1992

#define PCI_RESIZBAR_CTL_NUMBAR __BITS(7, 5)

sys/dev/pci/pcireg.h

1993

#define PCI_RESIZBAR_CTL_BARSIZ __BITS(12, 8)

sys/dev/pci/pcireg.h

2000

#define PCI_DPA_CAP_SUBSTMAX __BITS(4, 0) /* Substate Max */

sys/dev/pci/pcireg.h

2001

#define PCI_DPA_CAP_TLUINT __BITS(9, 8) /* Transition Latency Unit */

sys/dev/pci/pcireg.h

2002

#define PCI_DPA_CAP_PAS __BITS(13, 12) /* Power Allocation Scale */

sys/dev/pci/pcireg.h

2003

#define PCI_DPA_CAP_XLCY0 __BITS(23, 16) /* Transition Latency Value0 */

sys/dev/pci/pcireg.h

2004

#define PCI_DPA_CAP_XLCY1 __BITS(31, 24) /* Transition Latency Value1 */

sys/dev/pci/pcireg.h

2007

#define PCI_DPA_CS_SUBSTSTAT __BITS(4, 0) /* Substate Status */

sys/dev/pci/pcireg.h

2009

#define PCI_DPA_CS_SUBSTCTL __BITS(20, 16) /* Substate Control */

sys/dev/pci/pcireg.h

2022

#define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */

sys/dev/pci/pcireg.h

2026

#define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */

sys/dev/pci/pcireg.h

2028

#define PCI_TPH_REQ_CTL_STSEL __BITS(2, 0) /* ST Mode Select */

sys/dev/pci/pcireg.h

2032

#define PCI_TPH_REQ_CTL_TPHREQEN __BITS(9, 8) /* TPH Requester Enable */

sys/dev/pci/pcireg.h

2044

#define PCI_LTR_MAXSNOOPLAT_VAL __BITS(9, 0) /* Max Snoop LatencyValue */

sys/dev/pci/pcireg.h

2045

#define PCI_LTR_MAXSNOOPLAT_SCALE __BITS(12, 10) /* Max Snoop LatencyScale */

sys/dev/pci/pcireg.h

2047

#define PCI_LTR_MAXNOSNOOPLAT_VAL __BITS(25, 16) /* Max No-Snoop LatencyValue*/

sys/dev/pci/pcireg.h

2048

#define PCI_LTR_MAXNOSNOOPLAT_SCALE __BITS(28, 26) /*Max NoSnoop LatencyScale*/

sys/dev/pci/pcireg.h

2058

#define PCI_SECPCIE_LCTL3_ELSKPOSGENV __BITS(15, 9) /* En. Lo. SKP OS Gen V*/

sys/dev/pci/pcireg.h

2062

#define PCI_SECPCIE_EQCTL_DP_XMIT_PRESET __BITS(3, 0) /* DwnStPort Xmit Pres */

sys/dev/pci/pcireg.h

2063

#define PCI_SECPCIE_EQCTL_DP_RCV_HINT __BITS(6, 4) /* DwnStPort Rcv PreHnt */

sys/dev/pci/pcireg.h

2064

#define PCI_SECPCIE_EQCTL_UP_XMIT_PRESET __BITS(11, 8) /* UpStPort Xmit Pres */

sys/dev/pci/pcireg.h

2065

#define PCI_SECPCIE_EQCTL_UP_RCV_HINT __BITS(14, 12) /* UpStPort Rcv PreHnt*/

sys/dev/pci/pcireg.h

2079

#define PCI_PASID_CAP_MAXPASIDW __BITS(12, 8) /* Max PASID Width */

sys/dev/pci/pcireg.h

2092

#define PCI_LNR_CAP_REGISTMAX __BITS(12, 8) /* LNR Registration MAX */

sys/dev/pci/pcireg.h

2096

#define PCI_LNR_CTL_REGISTLIM __BITS(28, 24) /* LNR Registration Limit */

sys/dev/pci/pcireg.h

2104

#define PCI_DPCCAP_IMSGN __BITS(4, 0) /* Interrupt Message Number */

sys/dev/pci/pcireg.h

2108

#define PCI_DPCCAP_RPPIOLOGSZ __BITS(11, 8) /* RP PIO Log Size */

sys/dev/pci/pcireg.h

2110

#define PCI_DPCCTL_TIRGEN __BITS(17, 16) /* DPC Trigger Enable */

sys/dev/pci/pcireg.h

2120

#define PCI_DPCSTAT_TREASON __BITS(2, 1) /* DPC Trigger Reason */

sys/dev/pci/pcireg.h

2123

#define PCI_DPCSTAT_TRIGREXT __BITS(6, 5) /* DPC Trigger Reason Extntn. */

sys/dev/pci/pcireg.h

2124

#define PCI_DPCSTAT_RPPIOFEP __BITS(12, 8) /* RP PIO First Error Pointer */

sys/dev/pci/pcireg.h

2125

#define PCI_DPCESID __BITS(31, 16) /* DPC Error Source ID */

sys/dev/pci/pcireg.h

2161

#define PCI_L1PM_CAP_PCMRT __BITS(15, 8) /*Port Common Mode Restore Time*/

sys/dev/pci/pcireg.h

2162

#define PCI_L1PM_CAP_PTPOSCALE __BITS(17, 16) /* Port T_POWER_ON Scale */

sys/dev/pci/pcireg.h

2163

#define PCI_L1PM_CAP_PTPOVAL __BITS(23, 19) /* Port T_POWER_ON Value */

sys/dev/pci/pcireg.h

2171

#define PCI_L1PM_CTL1_CMRT __BITS(15, 8) /* Common Mode Restore Time */

sys/dev/pci/pcireg.h

2172

#define PCI_L1PM_CTL1_LTRTHVAL __BITS(25, 16) /* LTR L1.2 THRESHOLD Value */

sys/dev/pci/pcireg.h

2173

#define PCI_L1PM_CTL1_LTRTHSCALE __BITS(31, 29) /* LTR L1.2 THRESHOLD Scale */

sys/dev/pci/pcireg.h

2175

#define PCI_L1PM_CTL2_TPOSCALE __BITS(1, 0) /* T_POWER_ON Scale */

sys/dev/pci/pcireg.h

2176

#define PCI_L1PM_CTL2_TPOVAL __BITS(7, 3) /* T_POWER_ON Value */

sys/dev/pci/pcireg.h

2188

#define PCI_PTM_CAP_LCLCLKGRNL __BITS(15, 8) /* Local Clock Granularity */

sys/dev/pci/pcireg.h

2192

#define PCI_PTM_CTL_EFCTGRNL __BITS(15, 8) /* Effective Granularity */

sys/dev/pci/pcireg.h

2224

#define PCI_DLF_LFEAT __BITS(22, 0) /* Local DLF supported */

sys/dev/pci/pcireg.h

2258

#define PCI_LMR_LCTL_RNUM __BITS(2, 0) /* Receive Number */

sys/dev/pci/pcireg.h

2259

#define PCI_LMR_LCTL_MTYPE __BITS(5, 3) /* Margin Type */

sys/dev/pci/pcireg.h

2261

#define PCI_LMR_LCTL_MPAYLOAD __BITS(15, 8) /* Margin Payload */

sys/dev/pci/pcireg.h

2262

#define PCI_LMR_LSTAT_RNUM __BITS(18, 16) /* Receive Number */

sys/dev/pci/pcireg.h

2263

#define PCI_LMR_LSTAT_MTYPE __BITS(21, 19) /* Margin Type */

sys/dev/pci/pcireg.h

2265

#define PCI_LMR_LSTAT_MPAYLOAD __BITS(31, 24) /* Margin Payload */

sys/dev/pci/pcireg.h

521

#define PCI_MAPREG_ROM_VALID_STAT __BITS(3, 1) /* Validation Status */

sys/dev/pci/pcireg.h

530

#define PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */

sys/dev/pci/pcireg.h

531

#define PCI_MAPREG_ROM_ADDR_MASK __BITS(31, 11)

sys/dev/pci/pcireg.h

552

#define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0)

sys/dev/pci/pcireg.h

553

#define PCI_SUBSYS_ID_MASK __BITS(31, 16)

sys/dev/pci/pcireg.h

652

#define AGP_MODE_RQ __BITS(31, 24)

sys/dev/pci/pcireg.h

653

#define AGP_MODE_ARQSZ __BITS(15, 13)

sys/dev/pci/pcireg.h

654

#define AGP_MODE_CAL __BITS(12, 10)

sys/dev/pci/pcireg.h

661

#define AGP_MODE_RATE __BITS(2, 0)

sys/dev/pci/pcireg.h

712

#define PCI_MSI_CTL_MASK __BITS(31, 16)

sys/dev/pci/pcireg.h

717

#define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

719

#define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

74

#define PCI_CONF_TYPE0_FUNCTION __BITS(8,10)

sys/dev/pci/pcireg.h

75

#define PCI_CONF_TYPE0_OFFSET __BITS(0,7)

sys/dev/pci/pcireg.h

80

#define PCI_CONF_TYPE1_BUS __BITS(16,23)

sys/dev/pci/pcireg.h

81

#define PCI_CONF_TYPE1_DEVICE __BITS(11,15)

sys/dev/pci/pcireg.h

82

#define PCI_CONF_TYPE1_FUNCTION __BITS(8,10)

sys/dev/pci/pcireg.h

83

#define PCI_CONF_TYPE1_OFFSET __BITS(0,7)

sys/dev/pci/pcireg.h

860

#define PCI_HT_CMD_MASK __BITS(31, 16)

sys/dev/pci/pcireg.h

863

#define PCI_HT_CAPMASK __BITS(31, 27)

sys/dev/pci/pcireg.h

892

#define PCI_HT_MSI_ADDR_LO_MASK __BITS(31, 20)

sys/dev/pci/pcireg.h

944

#define PCI_SECURE_CAP_TYPE __BITS(18, 16) /* Capability block type */

sys/dev/pci/pcireg.h

946

#define PCI_SECURE_CAP_REV __BITS(23, 19) /* Capability revision */

sys/dev/pci/pcireg.h

956

#define PCI_SECURE_IOMMU_BAL_L __BITS(18, 14) /* Base Addr [18:14] */

sys/dev/pci/pcireg.h

957

#define PCI_SECURE_IOMMU_BAL_H __BITS(31, 19) /* Base Addr [31:19] */

sys/dev/pci/pcireg.h

960

#define PCI_SECURE_IOMMU_RANGE_UNITID __BITS(4, 0) /* HT UnitID */

sys/dev/pci/pcireg.h

962

#define PCI_SECURE_IOMMU_RANGE_BUSNUM __BITS(15, 8) /* bus number */

sys/dev/pci/pcireg.h

963

#define PCI_SECURE_IOMMU_RANGE_FIRSTDEV __BITS(23, 16) /* First device */

sys/dev/pci/pcireg.h

964

#define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24) /* Last device */

sys/dev/pci/pcireg.h

966

#define PCI_SECURE_IOMMU_MISC0_MSINUM __BITS(4, 0) /* MSI Message number */

sys/dev/pci/pcireg.h

967

#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr size */

sys/dev/pci/pcireg.h

969

#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address size */

sys/dev/pci/pcireg.h

970

#define PCI_SECURE_IOMMU_MISC0_VASIZE __BITS(21, 15)/* Virtual Address size */

sys/dev/pci/pcireg.h

972

#define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/

sys/dev/pci/pcireg.h

974

#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Message number(GA) */

sys/dev/pci/pcireg.h

981

#define PCIE_XCAP_MASK __BITS(31, 16)

sys/dev/pci/pcireg.h

983

#define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK)

sys/dev/pci/pcireg.h

987

#define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK)

sys/dev/pci/pcireg.h

999

#define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)

sys/dev/pci/piixpmreg.h

129

#define SB800_PM_SMBUS0_MASK_C __BITS(2, 1) /* Port mask (PMIO2C) */

sys/dev/pci/piixpmreg.h

130

#define SB800_PM_SMBUS0EN_BADDR __BITS(15, 5) /* Base address */

sys/dev/pci/piixpmreg.h

133

#define SB800_PM_SMBUS0_MASK_E __BITS(2, 1) /* Port mask (PMIO2E) */

sys/dev/pci/qat/qat_hw15reg.h

537

#define LA_FLAGS_PROTO __BITS(8, 6)

sys/dev/pci/qat/qat_hw15reg.h

546

#define LA_FLAGS_PARTIAL __BITS(1, 0)

sys/dev/pci/qat/qat_hw15reg.h

74

#define ARCH_IF_FLAGS_RESP_RING_TYPE __BITS(4, 3)

sys/dev/pci/qat/qat_hw15reg.h

79

#define ARCH_IF_FLAGS_RESP_TYPE __BITS(2, 0)

sys/dev/pci/qat/qat_hw17reg.h

1228

#define FW_LA_PRORO __BITS(7, 9)

sys/dev/pci/qat/qat_hw17reg.h

1261

#define FW_LA_PARTIAL __BITS(0, 1)

sys/dev/pci/qat/qatreg.h

1351

#define HW_AUTH_CONFIG_SHA3_ALGO __BITS(22, 23)

sys/dev/pci/qat/qatreg.h

1353

#define HW_AUTH_CONFIG_CMPLEN __BITS(14, 8)

sys/dev/pci/qat/qatreg.h

1355

#define HW_AUTH_CONFIG_MODE __BITS(7, 4)

sys/dev/pci/qat/qatreg.h

1356

#define HW_AUTH_CONFIG_ALGO __BITS(3, 0)

sys/dev/pci/qat/qatreg.h

1463

#define CIPHER_CONFIG_MODE __BITS(7, 4)

sys/dev/pci/qat/qatreg.h

1464

#define CIPHER_CONFIG_ALGO __BITS(3, 0)

sys/dev/pci/qat/qatreg.h

154

#define ETR_RING_CONFIG_NEAR_FULL_WM __BITS(14, 10)

sys/dev/pci/qat/qatreg.h

155

#define ETR_RING_CONFIG_NEAR_EMPTY_WM __BITS(9, 5)

sys/dev/pci/qat/qatreg.h

156

#define ETR_RING_CONFIG_RING_SIZE __BITS(4, 0)

sys/dev/pci/qat/qatreg.h

233

#define ETR_AP_DEST_AE __BITS(6, 2)

sys/dev/pci/qat/qatreg.h

234

#define ETR_AP_DEST_MAILBOX __BITS(1, 0)

sys/dev/pci/qat/qatreg.h

271

#define FCU_CTRL_AE __BITS(8, 31)

sys/dev/pci/qat/qatreg.h

274

#define FCU_STATUS_STS __BITS(0, 2)

sys/dev/pci/qat/qatreg.h

283

#define FCU_STATUS_LOADED_AE __BITS(22, 31)

sys/dev/pci/qat/qatreg.h

299

#define CAP_GLOBAL_CTL_RESET_MASK __BITS(31, 26)

sys/dev/pci/qat/qatreg.h

300

#define CAP_GLOBAL_CTL_RESET_ACCEL_MASK __BITS(25, 20)

sys/dev/pci/qat/qatreg.h

301

#define CAP_GLOBAL_CTL_RESET_AE_MASK __BITS(19, 0)

sys/dev/pci/qat/qatreg.h

303

#define CAP_GLOBAL_CTL_CLK_EN_ACCEL_MASK __BITS(25, 20)

sys/dev/pci/qat/qatreg.h

304

#define CAP_GLOBAL_CTL_CLK_EN_AE_MASK __BITS(19, 0)

sys/dev/pci/qat/qatreg.h

311

#define AE_LOCAL_AE_MASK __BITS(31, 12)

sys/dev/pci/qat/qatreg.h

312

#define AE_LOCAL_CSR_MASK __BITS(9, 0)

sys/dev/pci/qat/qatreg.h

350

#define CTX_ENABLES_ENABLE __BITS(15,8)

sys/dev/pci/qat/qatreg.h

366

#define CSR_CTX_POINTER_CONTEXT __BITS(2,0)

sys/dev/pci/qat/qatreg.h

376

#define ACTIVE_CTX_STATUS_ACNO __BITS(0, 2)

sys/dev/pci/qat/qatreg.h

448

#define AE_MISC_CONTROL_CS_RELOAD __BITS(21, 20)

sys/dev/pci/qat/qatreg.h

459

#define AE_XFER_AE_MASK __BITS(31, 12)

sys/dev/pci/qat/qatreg.h

460

#define AE_XFER_CSR_MASK __BITS(9, 2)

sys/dev/pci/qat/qatreg.h

972

#define AE_MODE_NN_MODE __BITS(7, 4)

sys/dev/pci/qat/qatreg.h

973

#define AE_MODE_CTX_MODE __BITS(3, 0)

sys/dev/pci/veritefbreg.h

225

#define VFB_PCLKPLL_M_MASK __BITS(8, 0)

sys/dev/pci/veritefbreg.h

226

#define VFB_PCLKPLL_P_MASK __BITS(12, 9)

sys/dev/pci/veritefbreg.h

227

#define VFB_PCLKPLL_N_MASK __BITS(18, 13)

sys/dev/pckbport/alps.c

320

if (resp[0] != 0x88 || (resp[1] & __BITS(7, 4)) != 0xb0)

sys/dev/pckbport/alps.c

398

nibble = (reg >> 12) & __BITS(3, 0);

sys/dev/pckbport/alps.c

402

nibble = (reg >> 8) & __BITS(3, 0);

sys/dev/pckbport/alps.c

406

nibble = (reg >> 4) & __BITS(3, 0);

sys/dev/pckbport/alps.c

410

nibble = (reg >> 0) & __BITS(3, 0);

sys/dev/pckbport/alps.c

467

nibble = __SHIFTOUT(val, __BITS(7, 4));

sys/dev/pckbport/alps.c

472

nibble = __SHIFTOUT(val, __BITS(3, 0));

sys/dev/pckbport/alps.c

508

x_pitch = __SHIFTOUT(ret, __BITS(7, 4)); /* Higher 4-bit */

sys/dev/pckbport/alps.c

512

y_pitch = ret & __BITS(3, 0); /* Lower 4-bit */

sys/dev/pckbport/alps.c

521

x_elec = __SHIFTOUT(ret, __BITS(7, 4)); /* Higher 4-bit */

sys/dev/pckbport/alps.c

525

y_elec = ret & __BITS(3, 0); /* Lower 4-bit */

sys/dev/pckbport/alps.c

678

nibble = __SHIFTOUT(val, __BITS(7, 4));

sys/dev/pckbport/alps.c

682

nibble = __SHIFTOUT(val, __BITS(3, 0));

sys/dev/pckbport/alps.c

729

if ((ecsig[0] == 0x88) && (__SHIFTOUT(ecsig[1], __BITS(7, 4)) == 0x0b)) {

sys/dev/pckbport/alps.c

917

cur_x2 &= ~__BITS(3, 0); /* Clear undefined locations */

sys/dev/pckbport/alps.c

918

cur_y2 |= __BITS(3, 0); /* Fill undefined locations */

sys/dev/pckbport/alps.c

921

cur_x2 &= ~__BITS(5, 0); /* Clear undefined locations */

sys/dev/pckbport/alps.c

924

cur_y2 |= __BITS(4, 0); /* Fill undefined locations */

sys/dev/pckbport/synapticsreg.h

81

#define SYN_CCAP_MULTIFINGER_MODE __BITS(13,14)

sys/dev/rasops/rasops.h

210

#define ATTR_MASK_BG __BITS(16, 23)

sys/dev/rasops/rasops.h

211

#define ATTR_MASK_FG __BITS(24, 31)

sys/dev/rasops/rasops1-4_putchar.h

46

#define COLOR_MASK __BITS(32 - PIXEL_BITS, 31)

sys/dev/sdmmc/if_bwfm_sdio.c

1392

mask = __BITS(11,13);

sys/dev/sdmmc/if_bwfm_sdio.c

1396

mask = __BITS(11,12);

sys/dev/sdmmc/if_bwfm_sdio.c

1400

mask = __BITS(0,3);

sys/dev/sdmmc/if_bwfm_sdio.c

1404

mask = __BITS(11,13);

sys/dev/sdmmc/sdmmcreg.h

412

#define SSR_PERFORMANCE_ENHANCE_COMMAND_QUEUE __BITS(7,3)

sys/dev/spi/mcp48x1.c

57

#define MCP48X1DAC_DATA __BITS(11,0) /* data */

sys/dev/tprof/tprof.c

542

dnum = sc_param->p_value2 & __BITS(31, 0);

sys/dev/tprof/tprof.c

553

__BITS(sc->sc_count[c].ctr_bitwidth - 1, 0)) {

sys/dev/tprof/tprof.c

555

__BITS(sc->sc_count[c].ctr_bitwidth - 1, 0);

sys/dev/tprof/tprof.c

565

__BITS(sc->sc_count[c].ctr_bitwidth - 1, 0);

sys/dev/tprof/tprof.c

618

__BITS(sc->sc_count[c].ctr_bitwidth - 1, 0));

sys/dev/tprof/tprof_types.h

44

#define TPROF_COUNTERMASK_ALL __BITS(31, 0)

sys/dev/tprof/tprof_types.h

65

#define TPROF_PARAM_VALUE2_MASK __BITS(63, 60)

sys/dev/tprof/tprof_x86_amd.c

88

#define PESR_EVENT_MASK_LO __BITS(0, 7)

sys/dev/tprof/tprof_x86_amd.c

89

#define PESR_UNIT_MASK __BITS(8, 15)

sys/dev/tprof/tprof_x86_amd.c

98

#define PESR_COUNTER_MASK __BITS(24, 31)

sys/dev/tprof/tprof_x86_amd.c

99

#define PESR_EVENT_MASK_HI __BITS(32, 35)

sys/dev/tprof/tprof_x86_intel.c

87

#define PERFEVTSEL_EVENT_SELECT __BITS(0, 7)

sys/dev/tprof/tprof_x86_intel.c

88

#define PERFEVTSEL_UNIT_MASK __BITS(8, 15)

sys/dev/tprof/tprof_x86_intel.c

96

#define PERFEVTSEL_COUNTER_MASK __BITS(24, 31)

sys/dev/usb/ehci.c

2065

EHCI_QH_SET_CMASK(__BITS(3,5)) /* CS Y[345] */

sys/dev/usb/ehcireg.h

212

#define EHCI_ITD_STATUS_MASK __BITS(31,28)

sys/dev/usb/ehcireg.h

219

#define EHCI_ITD_LEN_MASK __BITS(27,16)

sys/dev/usb/ehcireg.h

225

#define EHCI_ITD_PG_MASK __BITS(14,12)

sys/dev/usb/ehcireg.h

228

#define EHCI_ITD_OFFSET_MASK __BITS(11,0)

sys/dev/usb/ehcireg.h

232

#define EHCI_ITD_BPTR_MASK __BITS(31,12)

sys/dev/usb/ehcireg.h

235

#define EHCI_ITD_EP_MASK __BITS(11,8)

sys/dev/usb/ehcireg.h

238

#define EHCI_ITD_DADDR_MASK __BITS(6,0)

sys/dev/usb/ehcireg.h

244

#define EHCI_ITD_MAXPKT_MASK __BITS(10,0)

sys/dev/usb/ehcireg.h

247

#define EHCI_ITD_MULTI_MASK __BITS(1,0)

sys/dev/usb/ehcireg.h

262

#define EHCI_SITD_PORT_MASK __BITS(30,24)

sys/dev/usb/ehcireg.h

263

#define EHCI_SITD_HUBA_MASK __BITS(22,16)

sys/dev/usb/ehcireg.h

264

#define EHCI_SITD_ENDPT_MASK __BITS(11,8)

sys/dev/usb/ehcireg.h

265

#define EHCI_SITD_DADDR_MASK __BITS(6,0)

sys/dev/usb/ehcireg.h

272

#define EHCI_SITD_SMASK_MASK __BITS(7,0)

sys/dev/usb/ehcireg.h

273

#define EHCI_SITD_CMASK_MASK __BITS(15,8)

sys/dev/usb/ehcireg.h

279

#define EHCI_SITD_LENGTH_MASK __BITS(25,16)

sys/dev/usb/ehcireg.h

282

#define EHCI_SITD_STATUS_MASK __BITS(7,0)

sys/dev/usb/ehcireg.h

296

#define EHCI_SITD_TP_MASK __BITS(4,3)

sys/dev/usb/ehcireg.h

297

#define EHCI_SITD_TCOUNT_MASK __BITS(2,0)

sys/dev/usb/ehcireg.h

314

#define EHCI_QTD_STATUS_MASK __BITS(7,0)

sys/dev/usb/ehcireg.h

326

#define EHCI_QTD_PID_MASK __BITS(9,8)

sys/dev/usb/ehcireg.h

332

#define EHCI_QTD_CERR_MASK __BITS(11,10)

sys/dev/usb/ehcireg.h

335

#define EHCI_QTD_C_PAGE_MASK __BITS(14,12)

sys/dev/usb/ehcireg.h

340

#define EHCI_QTD_BYTES_MASK __BITS(30,16)

sys/dev/usb/ehcireg.h

358

#define EHCI_QH_ADDR_MASK __BITS(6,0) /* endpoint addr */

sys/dev/usb/ehcireg.h

363

#define EHCI_QH_ENDPT_MASK __BITS(11,8) /* endpoint no */

sys/dev/usb/ehcireg.h

366

#define EHCI_QH_EPS_MASK __BITS(13,12) /* endpoint speed */

sys/dev/usb/ehcireg.h

376

#define EHCI_QH_MPL_MASK __BITS(26,16) /* max packet len */

sys/dev/usb/ehcireg.h

381

#define EHCI_QH_NRL_MASK __BITS(31,28) /* NAK reload */

sys/dev/usb/ehcireg.h

385

#define EHCI_QH_SMASK_MASK __BITS(7,0) /* intr sched mask */

sys/dev/usb/ehcireg.h

388

#define EHCI_QH_CMASK_MASK __BITS(15,8) /* split completion mask */

sys/dev/usb/ehcireg.h

391

#define EHCI_QH_HUBA_MASK __BITS(22,16) /* hub address */

sys/dev/usb/ehcireg.h

394

#define EHCI_QH_PORT_MASK __BITS(29,23) /* hub port */

sys/dev/usb/ehcireg.h

397

#define EHCI_QH_MULTI_MASK __BITS(31,30) /* pipe multiplier */

sys/dev/usb/ehcireg.h

415

#define PCI_CAP_DEBUGPORT_OFFSET __BITS(28,16)

sys/dev/usb/ehcireg.h

416

#define PCI_CAP_DEBUGPORT_BAR __BITS(31,29)

sys/dev/usb/ehcireg.h

420

#define EHCI_DSC_DATA_LENGTH __BITS(3,0)

sys/dev/usb/ehcireg.h

424

#define EHCI_DSC_EXCEPTION __BITS(9,7)

sys/dev/usb/ehcireg.h

434

#define EHCI_DPR_TOKEN __BITS(7,0)

sys/dev/usb/ehcireg.h

435

#define EHCI_DPR_SEND __BITS(15,8)

sys/dev/usb/ehcireg.h

436

#define EHCI_DPR_RECEIVED __BITS(23,16)

sys/dev/usb/ehcireg.h

442

#define EHCI_DAR_ENDPOINT __BITS(3,0)

sys/dev/usb/ehcireg.h

443

#define EHCI_DAR_ADDRESS __BITS(14,8)

sys/dev/usb/ehcireg.h

91

#define EHCI_HCC_IST_THRESHOLD_MASK __BITS(6,4) /* isoc sched threshold */

sys/dev/usb/if_axereg.h

220

#define AXE_SW_RESET_IPPSL_MASK __BITS(9,8)

sys/dev/usb/if_muereg.h

88

#define MUE_ID_REV_ID __BITS(16,31)

sys/dev/usb/if_muereg.h

89

#define MUE_ID_REV_REV __BITS(0,15)

sys/dev/usb/if_muevar.h

34

#define MUE_RX_CMD_A_ERRORS __BITS(16, 21) /* non-checksum errors */

sys/dev/usb/if_muevar.h

36

#define MUE_RX_CMD_A_PID __BITS(28, 27)

sys/dev/usb/ohcireg.h

101

#define OHCI_FM_IVAL_MASK __BITS(13,0)

sys/dev/usb/ohcireg.h

103

#define OHCI_FM_FSMPS_MASK __BITS(30,16)

sys/dev/usb/ohcireg.h

112

#define OHCI_RHD_NDP_MASK __BITS(7,0)

sys/dev/usb/ohcireg.h

119

#define OHCI_RHD_POTPGT_MASK __BITS(31,24)

sys/dev/usb/ohcireg.h

158

#define OHCI_ED_ADDR_MASK __BITS(6,0)

sys/dev/usb/ohcireg.h

161

#define OHCI_ED_EN_MASK __BITS(10,7)

sys/dev/usb/ohcireg.h

164

#define OHCI_ED_DIR_MASK __BITS(12,11)

sys/dev/usb/ohcireg.h

177

#define OHCI_ED_MAXP_MASK __BITS(26,16)

sys/dev/usb/ohcireg.h

184

#define OHCI_HEADMASK __BITS(31,2)

sys/dev/usb/ohcireg.h

197

#define OHCI_TD_DP_MASK __BITS(20,19) /* Direction / PID */

sys/dev/usb/ohcireg.h

203

#define OHCI_TD_DI_MASK __BITS(23,21) /* Delay Interrupt */

sys/dev/usb/ohcireg.h

207

#define OHCI_TD_TOGGLE_MASK __BITS(25,24) /* Toggle */

sys/dev/usb/ohcireg.h

213

#define OHCI_TD_EC_MASK __BITS(27,26) /* Error Count */

sys/dev/usb/ohcireg.h

215

#define OHCI_TD_CC_MASK __BITS(31,28) /* Condition Code */

sys/dev/usb/ohcireg.h

235

#define OHCI_ITD_SF_MASK __BITS(15,0)

sys/dev/usb/ohcireg.h

238

#define OHCI_ITD_DI_MASK __BITS(23,21) /* Delay Interrupt */

sys/dev/usb/ohcireg.h

241

#define OHCI_ITD_FC_MASK __BITS(26,24) /* Frame Count */

sys/dev/usb/ohcireg.h

244

#define OHCI_ITD_CC_MASK __BITS(31,28) /* Condition Code */

sys/dev/usb/ohcireg.h

256

#define OHCI_ITD_PSW_SIZE_MASK __BITS(10,0) /* Transfer length */

sys/dev/usb/ohcireg.h

258

#define OHCI_ITD_PSW_CC_MASK __BITS(15,12) /* Condition Code */

sys/dev/usb/ohcireg.h

46

#define OHCI_REV_LO_MASK __BITS(3,0)

sys/dev/usb/ohcireg.h

47

#define OHCI_REV_HI_MASK __BITS(7,4)

sys/dev/usb/ohcireg.h

54

#define OHCI_CBSR_MASK __BITS(1,0) /* Control/Bulk Service Ratio */

sys/dev/usb/ohcireg.h

64

#define OHCI_HCFS_MASK __BITS(7,6) /* HostControllerFunctionalState */

sys/dev/usb/ohcireg.h

79

#define OHCI_SOC_MASK __BITS(17,16) /* Scheduling Overrun Count */

sys/dev/usb/uhcireg.h

104

#define UHCI_PORTSC_LS_MASK __BITS(5,4)

sys/dev/usb/uhcireg.h

149

#define UHCI_TD_ACTLEN_MASK __BITS(10,0)

sys/dev/usb/uhcireg.h

160

#define UHCI_TD_STATUS_MASK __BITS(16,23)

sys/dev/usb/uhcireg.h

164

#define UHCI_TD_ERRCNT_MASK __BITS(28,27)

sys/dev/usb/uhcireg.h

172

#define UHCI_TD_PID_MASK __BITS(7,0)

sys/dev/usb/uhcireg.h

175

#define UHCI_TD_DEVADDR_MASK __BITS(14,8)

sys/dev/usb/uhcireg.h

178

#define UHCI_TD_ENDPT_MASK __BITS(18,15)

sys/dev/usb/uhcireg.h

184

#define UHCI_TD_MAXLEN_MASK __BITS(31,21)

sys/dev/usb/uhcireg.h

81

#define UHCI_STS_ALLINTRS __BITS(5,0)

sys/dev/usb/uhcireg.h

90

#define UHCI_FRNUM_MASK __BITS(9,0)

sys/dev/usb/uhcireg.h

96

#define UHCI_SOF_MASK __BITS(6,0)

sys/dev/usb/ulpireg.h

46

#define FUNCTION_CONTROL_XCVRSELECT __BITS(0,1)

sys/dev/usb/ulpireg.h

52

#define FUNCTION_CONTROL_OPMODE __BITS(3,4)

sys/dev/usb/usb.h

318

#define UE_GET_BULK_STREAMS_MASK __BITS(4,0)

sys/dev/usb/usb.h

320

#define UE_GET_SS_ISO_MULT_MASK __BITS(1,0)

sys/dev/usb/usb.h

371

#define USB_DEVCAP_V2EXT_BESL_BASELINE_MASK __BITS(11, 8)

sys/dev/usb/usb.h

373

#define USB_DEVCAP_V2EXT_BESL_DEEP_MASK __BITS(15, 12)

sys/dev/usb/usb.h

423

#define USB_DEVCAP_SSP_SSAC(x) __SHIFTOUT(x, __BITS(4,0))

sys/dev/usb/usb.h

424

#define USB_DEVCAP_SSP_SSIC(x) __SHIFTOUT(x, __BITS(8,5))

sys/dev/usb/usb.h

426

#define USB_DEVCAP_SSP_SSID(x) __SHIFTOUT(x, __BITS(3,0))

sys/dev/usb/usb.h

427

#define USB_DEVCAP_SSP_MIN_RXLANE_COUNT(x) __SHIFTOUT(x, __BITS(11,8))

sys/dev/usb/usb.h

428

#define USB_DEVCAP_SSP_MIN_TXLANE_COUNT(x) __SHIFTOUT(x, __BITS(15,12))

sys/dev/usb/usb.h

431

#define USB_DEVCAP_SSP_SSID(x) __SHIFTOUT(x, __BITS(3,0))

sys/dev/usb/usb.h

432

#define USB_DEVCAP_SSP_LSE(x) __SHIFTOUT(x, __BITS(5,4))

sys/dev/usb/usb.h

433

#define USB_DEVCAP_SSP_ST(x) __SHIFTOUT(x, __BITS(7,6))

sys/dev/usb/usb.h

434

#define USB_DEVCAP_SSP_LP(x) __SHIFTOUT(x, __BITS(15,14))

sys/dev/usb/usb.h

435

#define USB_DEVCAP_SSP_LSM(x) __SHIFTOUT(x, __BITS(31,16))

sys/dev/usb/usb.h

598

#define UPS_PORT_LS_MASK __BITS(8,5)

sys/dev/usb/uslsareg.h

195

#define SERIAL_DTR_MASK __BITS(0, 1)

sys/dev/usb/uslsareg.h

206

#define SERIAL_RTS_MASK __BITS(6, 7)

sys/dev/usb/uslsareg.h

79

#define SLSA_RV_LINE_CTL_STOP __BITS(3,0)

sys/dev/usb/uslsareg.h

80

#define SLSA_RV_LINE_CTL_PARITY __BITS(7,4)

sys/dev/usb/uslsareg.h

81

#define SLSA_RV_LINE_CTL_LEN __BITS(15,8)

sys/dev/usb/xhci.c

1244

const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16));

sys/dev/usb/xhcireg.h

146

#define XHCI_STS_RSVDZ1 __BITS(7, 5) /* RsvdZ - 7:5 */

sys/dev/usb/xhcireg.h

152

#define XHCI_STS_RSVDP0 __BITS(13, 31) /* RsvdP - 31:13 */

sys/dev/usb/xhcireg.h

176

#define XHCI_CRCR_LO_MASK __BITS(31, 6)

sys/dev/usb/xhcireg.h

186

#define XHCI_CONFIG_SLOTS_MASK __BITS(7, 0) /* RW - number of device slots enabled */

sys/dev/usb/xhcireg.h

196

#define XHCI_PS_PLS_MASK __BITS(8, 5) /* RW - port link state */

sys/dev/usb/xhcireg.h

222

#define XHCI_PS_SPEED_MASK __BITS(13, 10) /* RO - port speed */

sys/dev/usb/xhcireg.h

228

#define XHCI_PS_PIC_MASK __BITS(15, 14) /* RW - port indicator */

sys/dev/usb/xhcireg.h

250

#define XHCI_PM3_U1TO_MASK __BITS(7, 0) /* RW - U1 timeout */

sys/dev/usb/xhcireg.h

253

#define XHCI_PM3_U2TO_MASK __BITS(15, 8) /* RW - U2 timeout */

sys/dev/usb/xhcireg.h

259

#define XHCI_PM2_L1S_MASK __BITS(2, 0) /* RO - L1 status */

sys/dev/usb/xhcireg.h

262

#define XHCI_PM2_BESL_MASK __BITS(7, 4) /* RW - Best Effort Service Latency */

sys/dev/usb/xhcireg.h

265

#define XHCI_PM2_L1SLOT_MASK __BITS(15, 8) /* RW - L1 device slot */

sys/dev/usb/xhcireg.h

269

#define XHCI_PM2_PTC_MASK __BITS(31, 28) /* RW - port test control */

sys/dev/usb/xhcireg.h

276

#define XHCI_PLI3_ERR_MASK __BITS(15, 0) /* RW - port link errors */

sys/dev/usb/xhcireg.h

278

#define XHCI_PLI3_RLC_MASK __BITS(19, 16) /* RO - Rx Lane Count */

sys/dev/usb/xhcireg.h

280

#define XHCI_PLI3_TLC_MASK __BITS(23, 20) /* RO - Tx Lane Count */

sys/dev/usb/xhcireg.h

286

#define XHCI_PLMC3_LSEC_MASK __BITS(15, 0) /* RW - Link Soft Error Count */

sys/dev/usb/xhcireg.h

292

#define XHCI_MFINDEX_MASK __BITS(13, 0) /* RO - microframe index */

sys/dev/usb/xhcireg.h

303

#define XHCI_IMOD_IVAL_MASK __BITS(15,0) /* 250ns unit */

sys/dev/usb/xhcireg.h

306

#define XHCI_IMOD_ICNT_MASK __BITS(31, 16) /* 250ns unit */

sys/dev/usb/xhcireg.h

315

#define XHCI_ERSTS_MASK __BITS(15, 0) /* Event Ring Segment Table Size */

sys/dev/usb/xhcireg.h

326

#define XHCI_ERDP_DESI_MASK __BITS(2,0) /* RO - dequeue segment index */

sys/dev/usb/xhcireg.h

334

#define XHCI_DB_TARGET_MASK __BITS(7, 0) /* RW - doorbell target */

sys/dev/usb/xhcireg.h

337

#define XHCI_DB_SID_MASK __BITS(31, 16) /* RW - doorbell stream ID */

sys/dev/usb/xhcireg.h

342

#define XHCI_XECP_ID_MASK __BITS(7, 0)

sys/dev/usb/xhcireg.h

344

#define XHCI_XECP_NEXT_MASK __BITS(15, 8)

sys/dev/usb/xhcireg.h

366

#define XHCI_XECP_SP_W0_MINOR_MASK __BITS(23, 16)

sys/dev/usb/xhcireg.h

368

#define XHCI_XECP_SP_W0_MAJOR_MASK __BITS(31, 24)

sys/dev/usb/xhcireg.h

371

#define XHCI_XECP_SP_W8_CPO_MASK __BITS(7, 0)

sys/dev/usb/xhcireg.h

373

#define XHCI_XECP_SP_W8_CPC_MASK __BITS(15, 8)

sys/dev/usb/xhcireg.h

375

#define XHCI_XECP_SP_W8_PD_MASK __BITS(27, 16)

sys/dev/usb/xhcireg.h

377

#define XHCI_XECP_SP_W8_PSIC_MASK __BITS(31, 28)

sys/dev/usb/xhcireg.h

403

#define XHCI_TRB_2_ERROR_MASK __BITS(31, 24)

sys/dev/usb/xhcireg.h

407

#define XHCI_TRB_2_TDSZ_MASK __BITS(21, 17) /* TD Size */

sys/dev/usb/xhcireg.h

410

#define XHCI_TRB_2_REM_MASK __BITS(23, 0)

sys/dev/usb/xhcireg.h

414

#define XHCI_TRB_2_BYTES_MASK __BITS(16, 0)

sys/dev/usb/xhcireg.h

417

#define XHCI_TRB_2_IRQ_MASK __BITS(31, 22)

sys/dev/usb/xhcireg.h

420

#define XHCI_TRB_2_STREAM_MASK __BITS(31, 16)

sys/dev/usb/xhcireg.h

424

#define XHCI_TRB_3_TYPE_MASK __BITS(15, 10)

sys/dev/usb/xhcireg.h

435

#define XHCI_TRB_3_TBC_MASK __BITS(8, 7)

sys/dev/usb/xhcireg.h

443

#define XHCI_TRB_3_TRT_MASK __BITS(17, 16)

sys/dev/usb/xhcireg.h

448

#define XHCI_TRB_3_TLBPC_MASK __BITS(19, 16)

sys/dev/usb/xhcireg.h

451

#define XHCI_TRB_3_EP_MASK __BITS(20, 16)

sys/dev/usb/xhcireg.h

454

#define XHCI_TRB_3_FRID_MASK __BITS(30, 20)

sys/dev/usb/xhcireg.h

459

#define XHCI_TRB_3_VFID_MASK __BITS(23, 16)

sys/dev/usb/xhcireg.h

462

#define XHCI_TRB_3_SLOT_MASK __BITS(31, 24)

sys/dev/usb/xhcireg.h

545

#define XHCI_SCTX_0_ROUTE_MASK __BITS(19, 0)

sys/dev/usb/xhcireg.h

548

#define XHCI_SCTX_0_SPEED_MASK __BITS(23, 20)

sys/dev/usb/xhcireg.h

557

#define XHCI_SCTX_0_CTX_NUM_MASK __BITS(31, 27)

sys/dev/usb/xhcireg.h

561

#define XHCI_SCTX_1_MAX_EL_MASK __BITS(15, 0)

sys/dev/usb/xhcireg.h

564

#define XHCI_SCTX_1_RH_PORT_MASK __BITS(23, 16)

sys/dev/usb/xhcireg.h

567

#define XHCI_SCTX_1_NUM_PORTS_MASK __BITS(31, 24)

sys/dev/usb/xhcireg.h

57

#define XHCI_HCS1_MAXSLOTS_MASK __BITS(7, 0)

sys/dev/usb/xhcireg.h

571

#define XHCI_SCTX_2_TT_HUB_SID_MASK __BITS(7, 0)

sys/dev/usb/xhcireg.h

574

#define XHCI_SCTX_2_TT_PORT_NUM_MASK __BITS(15, 8)

sys/dev/usb/xhcireg.h

577

#define XHCI_SCTX_2_TT_THINK_TIME_MASK __BITS(17, 16)

sys/dev/usb/xhcireg.h

580

#define XHCI_SCTX_2_IRQ_TARGET_MASK __BITS(31, 22)

sys/dev/usb/xhcireg.h

584

#define XHCI_SCTX_3_DEV_ADDR_MASK __BITS(7, 0)

sys/dev/usb/xhcireg.h

587

#define XHCI_SCTX_3_SLOT_STATE_MASK __BITS(31, 27)

sys/dev/usb/xhcireg.h

59

#define XHCI_HCS1_MAXINTRS_MASK __BITS(18, 8)

sys/dev/usb/xhcireg.h

599

#define XHCI_EPCTX_0_EPSTATE_MASK __BITS(2, 0)

sys/dev/usb/xhcireg.h

607

#define XHCI_EPCTX_0_MULT_MASK __BITS(9, 8)

sys/dev/usb/xhcireg.h

61

#define XHCI_HCS1_MAXPORTS_MASK __BITS(31, 24)

sys/dev/usb/xhcireg.h

610

#define XHCI_EPCTX_0_MAXP_STREAMS_MASK __BITS(14, 10)

sys/dev/usb/xhcireg.h

616

#define XHCI_EPCTX_0_IVAL_MASK __BITS(23, 16)

sys/dev/usb/xhcireg.h

619

#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK __BITS(31, 24)

sys/dev/usb/xhcireg.h

623

#define XHCI_EPCTX_1_CERR_MASK __BITS(2, 1)

sys/dev/usb/xhcireg.h

626

#define XHCI_EPCTX_1_EPTYPE_MASK __BITS(5, 3)

sys/dev/usb/xhcireg.h

632

#define XHCI_EPCTX_1_MAXB_MASK __BITS(15, 8)

sys/dev/usb/xhcireg.h

635

#define XHCI_EPCTX_1_MAXP_SIZE_MASK __BITS(31, 16)

sys/dev/usb/xhcireg.h

645

#define XHCI_EPCTX_4_AVG_TRB_LEN_MASK __BITS(15, 0)

sys/dev/usb/xhcireg.h

648

#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK __BITS(16, 31)

sys/dev/usb/xhcireg.h

65

#define XHCI_HCS2_IST_MASK __BITS(3, 0)

sys/dev/usb/xhcireg.h

67

#define XHCI_HCS2_ERSTMAX_MASK __BITS(7, 4)

sys/dev/usb/xhcireg.h

69

#define XHCI_HCS2_SPBUFHI_MASK __BITS(25, 21)

sys/dev/usb/xhcireg.h

72

#define XHCI_HCS2_SPBUFLO_MASK __BITS(31, 27)

sys/dev/usb/xhcireg.h

78

#define XHCI_HCS3_U1_DEL_MASK __BITS(7, 0)

sys/dev/usb/xhcireg.h

80

#define XHCI_HCS3_U2_DEL_MASK __BITS(15, 8)

sys/dev/usb/xhcireg.h

96

#define XHCI_HCC_MAXPSASIZE_MASK __BITS(15, 12) /* max pri. stream array size */

sys/dev/usb/xhcireg.h

98

#define XHCI_HCC_XECP_MASK __BITS(31, 16) /* extended capabilities pointer */

sys/dev/vmt/vmtvar.h

146

#define X86_IO_W7_SIZE_MASK __BITS(1, 0)

sys/dev/vmt/vmtvar.h

152

#define X86_IO_W7_IMM_MASK __BITS(12, 5)

sys/dev/vmt/vmtvar.h

40

#define VM_REG_LOW_MASK __BITS(15,0)

sys/dev/vmt/vmtvar.h

41

#define VM_REG_HIGH_MASK __BITS(31,16)

sys/dev/vmt/vmtvar.h

42

#define VM_REG_WORD_MASK __BITS(31,0)

sys/kern/subr_device.c

859

#define S8_MASK __BITS(7,63)

sys/kern/subr_device.c

861

#define S16_MASK __BITS(15,63)

sys/kern/subr_device.c

863

#define S32_MASK __BITS(31,63)

sys/kern/sys_futex.c

1440

KASSERT(arg == (arg & __BITS(11,0)));

sys/stand/efiboot/bootaa64/efibootaa64.c

86

return __SHIFTOUT(id_aa64mmfr0_el1, __BITS(11, 8)) == 1;

sys/sys/bus.h

253

#define BUS_ADDR_HI32(a) ((uint32_t) __SHIFTOUT(a, __BITS(32,63)))

sys/sys/bus.h

254

#define BUS_ADDR_LO32(a) ((uint32_t) __SHIFTOUT(a, __BITS(0,31)))

sys/sys/eventvar.h

59

#define KQ_MAXCOUNT __BITS(0,29)

sys/sys/futex.h

131

#define FUTEX_TID_MASK ((int)__BITS(0,27))

sys/sys/futex.h

133

#define FUTEX_BITSET_MATCH_ANY ((int)__BITS(0,31))

sys/sys/futex.h

95

#define FUTEX_OP_OP_MASK __BITS(28,31)

sys/sys/futex.h

96

#define FUTEX_OP_CMP_MASK __BITS(24,27)

sys/sys/futex.h

97

#define FUTEX_OP_OPARG_MASK __BITS(12,23)

sys/sys/futex.h

98

#define FUTEX_OP_CMPARG_MASK __BITS(0,11)

sys/uvm/pmap/pmap_tlb.c

172

.ti_asid_bitmap._b[0] = __BITS(0, KERNEL_PID),

sys/uvm/uvm_page.h

443

#define UVM_PHYSADDR_FREELIST __BITS(0,4)

sys/uvm/uvm_page.h

444

#define UVM_PHYSADDR_BUCKET __BITS(5,9)

tests/kernel/arch/hppa/execregs.c

63

(__BITS(63,59) /* all exception flags (VZOUI) set */

tests/kernel/arch/hppa/execregs.c

65

| __BITS(54,43) /* CQ (comparison queue) all set */

tests/kernel/arch/hppa/execregs.c

66

| __SHIFTIN(1, __BITS(42,41)) /* round toward zero */

tests/kernel/arch/hppa/execregs.c

69

| __SHIFTIN(0, __BITS(36,32)) /* exceptions masked */

tests/kernel/arch/x86/sig_fpu.c

255

#define MXCSR_RC __BITS(14,13) /* rounding control */

tests/kernel/arch/x86/sig_fpu.c

256

#define MXCSR_EXCMASK __BITS(12,7) /* exceptions masked */

tests/kernel/arch/x86/sig_fpu.c

258

#define MXCSR_EXCFLAG __BITS(5,0) /* exceptions raised */

tests/kernel/arch/x86/sig_fpu.c

57

#define X87_CW_RC __BITS(11,10) /* rounding control (mode) */

tests/kernel/arch/x86/sig_fpu.c

58

#define X87_CW_PC __BITS(9,8) /* precision control */

tests/kernel/arch/x86/sig_fpu.c

59

#define X87_CW_SW_EXC __BITS(5,0) /* exception bits */

usr.sbin/bta2dpd/bta2dpd/sbc_encode.c

408

tmp_cache = cache & __BITS((uintmax_t)(numbits + cache_pos),

usr.sbin/bta2dpd/bta2dpd/sbc_encode.c

439

cache |= sample & __BITS((uintmax_t)numbits, 0);

usr.sbin/bta2dpd/bta2dpd/sbc_encode.c

475

cache |= sample & __BITS((uintmax_t)numbits, 0);

usr.sbin/btconfig/btconfig.c

1008

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

1019

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

901

switch(__SHIFTOUT(class, __BITS(0, 1))) {

usr.sbin/btconfig/btconfig.c

913

switch (__SHIFTOUT(class, __BITS(8, 12))) {

usr.sbin/btconfig/btconfig.c

915

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

927

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

939

switch (__SHIFTOUT(class, __BITS(5, 7))) {

usr.sbin/btconfig/btconfig.c

952

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

974

switch (__SHIFTOUT(class, __BITS(2, 5))) {

usr.sbin/btconfig/btconfig.c

993

if ((class & __BITS(4, 7)) == 0) tag("Imaging");

usr.sbin/btconfig/btconfig.c

997

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/cpuctl/arch/i386.c

1799

__BITS(smt_bits, smt_bits + core_bits - 1));

usr.sbin/cpuctl/arch/i386.c

1803

__BITS((int)0, (int)(smt_bits - 1)));

usr.sbin/cpuctl/arch/i386.c

1855

__BITS(core_shift, pkg_shift - 1));

usr.sbin/cpuctl/arch/i386.c

1859

__BITS((int)0, core_shift - 1));

usr.sbin/cpuctl/arch/i386.c

1916

const u_int node_id = apic_id & __BITS(0, 2);

usr.sbin/cpuctl/arch/i386.c

1936

u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1);

usr.sbin/cpuctl/arch/i386.c

1940

u_int smt_mask = __BITS(0, smt_bits - 1);

usr.sbin/cpuctl/arch/i386.c

2348

descs[1] ^= __BITS(veclen - 1, 0);

usr.sbin/cpuctl/arch/i386.c

2353

descs[1] &= __BITS(veclen - 1, 0);

usr.sbin/cpuctl/arch/i386.c

2366

descs[2] = __BITS(ncounter - 1, 0);

usr.sbin/tprof/arch/tprof_x86.c

1063

{ "FpRetx87FpOps", 0x02, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1064

{ "FpRetSseAvxOps", 0x03, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1065

{ "FpRetiredSerOps", 0x05, __BITS(3,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1066

{ "LsL1DTlbMiss", 0x45, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1067

{ "LsTableWalker", 0x46, __BITS(3,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1069

{ "LsInefSwPref", 0x52, __BITS(1,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1075

{ "IcFetchStall", 0x87, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1076

{ "IcCacheInval", 0x8c, __BITS(1,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1121

{ "FpRetx87FpOps", 0x02, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1124

{ "FpRetSseAvxOps", 0x03, __BITS(4,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1126

{ "FpRetiredSerOps", 0x05, __BITS(3,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1129

{ "FpOpsRetiredByWidth", 0x08, __BITS(5,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1130

{ "FpOpsRetiredByType", 0x0a, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1131

{ "SseAvxOpsRetired", 0x0b, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1132

{ "FpPackOpsRetired", 0x0c, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1133

{ "PackedIntOpType", 0x0d, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1135

{ "FpDispFaults", 0x0e, __BITS(3,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1140

{ "LsDispatch", 0x29, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1153

{ "LsL1DTlbMiss", 0x45, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1156

{ "LsMisalLoads-all", 0x47, __BITS(1,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1157

{ "LsPrefInstrDisp", 0x4b, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1158

{ "LsInefSwPref", 0x52, __BITS(1,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1180

{ "BpL1TlbMissL2TlbMiss-all", 0x85, __BITS(3,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1188

{ "BpL1TlbFetchHit-all", 0x94, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1205

{ "DeSrcOpDisp", 0xaa, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1253

{ "ExTaggedIbsOps", 0x1cf, __BITS(2,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1257

{ "L2RequestG1", 0x60, __BITS(7,1), true },

usr.sbin/tprof/arch/tprof_x86.c

1259

{ "L2CacheReqStart", 0x64, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1260

{ "L2PfHitL2-L2", 0x70, __BITS(4,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1261

{ "L2PfHitL2-L1", 0x70, __BITS(7,5), true },

usr.sbin/tprof/arch/tprof_x86.c

1262

{ "L2PfHitL2-all", 0x70, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1263

{ "L2PfMissL2HitL3-L2", 0x71, __BITS(4,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1264

{ "L2PfMissL2HitL3-L1", 0x71, __BITS(7,5), true },

usr.sbin/tprof/arch/tprof_x86.c

1265

{ "L2PfMIssL2HitL3-all", 0x71, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1266

{ "L2PfMissL2L3-L2", 0x72, __BITS(4,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1267

{ "L2PfMissL2L3-L1", 0x72, __BITS(7,5), true },

usr.sbin/tprof/arch/tprof_x86.c

1268

{ "L2PfMIssL2L3-all", 0x72, __BITS(7,0), true },

usr.sbin/tprof/arch/tprof_x86.c

1271

{ "L3LookupState-L3Hit", 0x04, __BITS(7,1), true },

usr.sbin/tprof/arch/tprof_x86.c

1272

{ "L3LookupState-all", 0x04, __BITS(7,0), true },