arch/alpha/include/asm/io.h
260
extern u32 __raw_readl(const volatile void __iomem *addr);
arch/alpha/include/asm/io.h
268
#define __raw_readl __raw_readl
arch/alpha/include/asm/io.h
514
ret = __raw_readl(addr);
arch/alpha/include/asm/io.h
582
return __raw_readl(addr);
arch/alpha/kernel/io.c
165
EXPORT_SYMBOL(__raw_readl);
arch/alpha/kernel/io.c
194
ret = __raw_readl(addr);
arch/alpha/kernel/io.c
260
return __raw_readl(addr);
arch/alpha/kernel/io.c
503
*(u32 *)to = __raw_readl(from);
arch/arc/include/asm/io.h
223
__raw_readl(c)); __r; })
arch/arc/include/asm/io.h
40
#define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
arch/arc/include/asm/io.h
73
#define __raw_readl __raw_readl
arch/arm/boot/compressed/misc-ep93xx.h
37
v = __raw_readl(PHYS_ETH_SELF_CTL);
arch/arm/boot/compressed/misc-ep93xx.h
41
while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
arch/arm/include/asm/hardware/iomd.h
21
#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
arch/arm/include/asm/io.h
109
#define __raw_readl __raw_readl
arch/arm/include/asm/io.h
245
__raw_readl(__io(p))); __iormb(); __v; })
arch/arm/include/asm/io.h
278
__raw_readl(c)); __r; })
arch/arm/include/asm/io.h
391
#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
arch/arm/mach-at91/pm.c
167
__raw_readl(soc_pm.data.ramc[id] + field)
arch/arm/mach-davinci/common.c
39
soc_info->jtag_id = __raw_readl(base);
arch/arm/mach-davinci/mux.c
68
reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
arch/arm/mach-davinci/pm.c
50
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
57
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
63
val = __raw_readl(pm_config.deepsleep_reg);
arch/arm/mach-davinci/pm.c
74
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
79
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
87
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-davinci/pm.c
95
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
arch/arm/mach-lpc32xx/common.c
27
devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
arch/arm/mach-lpc32xx/common.c
43
savedval1 = __raw_readl(iramptr1);
arch/arm/mach-lpc32xx/common.c
44
savedval2 = __raw_readl(iramptr2);
arch/arm/mach-lpc32xx/common.c
48
if (__raw_readl(iramptr1) == savedval2 + 1)
arch/arm/mach-lpc32xx/common.c
67
u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
arch/arm/mach-lpc32xx/pm.c
129
__raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
arch/arm/mach-lpc32xx/serial.c
121
tmp = __raw_readl(
arch/arm/mach-lpc32xx/serial.c
135
tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
arch/arm/mach-lpc32xx/serial.c
140
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
arch/arm/mach-lpc32xx/serial.c
145
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
arch/arm/mach-mmp/common.c
53
mmp_chip_id = __raw_readl(MMP_CHIPID);
arch/arm/mach-mmp/time.c
151
uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
arch/arm/mach-mmp/time.c
53
val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
arch/arm/mach-mxs/mach-mxs.c
112
while ((__raw_readl(ocotp_base) &
arch/arm/mach-mxs/mach-mxs.c
127
while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
arch/arm/mach-mxs/mach-mxs.c
134
ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
arch/arm/mach-omap1/clock.c
194
regval32 = __raw_readl(clk->enable_reg);
arch/arm/mach-omap1/clock.c
395
val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit);
arch/arm/mach-omap1/clock.c
49
unsigned int val = __raw_readl(clk->enable_reg);
arch/arm/mach-omap1/clock.c
553
regval32 = __raw_readl(clk->enable_reg);
arch/arm/mach-omap1/clock.c
598
regval32 = __raw_readl(clk->enable_reg);
arch/arm/mach-omap1/io.c
89
return __raw_readl(OMAP1_IO_ADDRESS(pa));
arch/arm/mach-omap2/omap-wakeupgen.c
622
val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
arch/arm/mach-pxa/irq.c
188
saved_icmr[i] = __raw_readl(base + ICMR);
arch/arm/mach-pxa/irq.c
194
saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
arch/arm/mach-pxa/irq.c
69
uint32_t icmr = __raw_readl(base + ICMR);
arch/arm/mach-pxa/irq.c
79
uint32_t icmr = __raw_readl(base + ICMR);
arch/arm/mach-pxa/irq.c
97
icip = __raw_readl(pxa_irq_base + ICIP);
arch/arm/mach-pxa/irq.c
98
icmr = __raw_readl(pxa_irq_base + ICMR);
arch/arm/mach-pxa/pxa27x.c
105
sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
arch/arm/mach-pxa/smemc.c
23
msc[0] = __raw_readl(MSC0);
arch/arm/mach-pxa/smemc.c
24
msc[1] = __raw_readl(MSC1);
arch/arm/mach-pxa/smemc.c
25
sxcnfg = __raw_readl(SXCNFG);
arch/arm/mach-pxa/smemc.c
26
memclkcfg = __raw_readl(MEMCLKCFG);
arch/arm/mach-pxa/smemc.c
27
csadrcfg[0] = __raw_readl(CSADRCFG0);
arch/arm/mach-pxa/smemc.c
28
csadrcfg[1] = __raw_readl(CSADRCFG1);
arch/arm/mach-pxa/smemc.c
29
csadrcfg[2] = __raw_readl(CSADRCFG2);
arch/arm/mach-pxa/smemc.c
30
csadrcfg[3] = __raw_readl(CSADRCFG3);
arch/arm/mach-pxa/smemc.c
82
unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
arch/arm/mach-pxa/spitz.c
1082
uint32_t msc0 = __raw_readl(MSC0);
arch/arm/mach-s3c/cpuidle-s3c64xx.c
28
tmp = __raw_readl(S3C64XX_PWR_CFG);
arch/arm/mach-s3c/gpio-samsung.c
106
con = __raw_readl(chip->base);
arch/arm/mach-s3c/gpio-samsung.c
146
con = __raw_readl(reg);
arch/arm/mach-s3c/gpio-samsung.c
176
con = __raw_readl(reg);
arch/arm/mach-s3c/gpio-samsung.c
254
con = __raw_readl(base + 0x00);
arch/arm/mach-s3c/gpio-samsung.c
274
dat = __raw_readl(base + 0x04);
arch/arm/mach-s3c/gpio-samsung.c
280
con = __raw_readl(base + 0x00);
arch/arm/mach-s3c/gpio-samsung.c
314
con = __raw_readl(base + GPIOCON_OFF);
arch/arm/mach-s3c/gpio-samsung.c
334
con = __raw_readl(base + GPIOCON_OFF);
arch/arm/mach-s3c/gpio-samsung.c
338
dat = __raw_readl(base + GPIODAT_OFF);
arch/arm/mach-s3c/gpio-samsung.c
389
con = __raw_readl(regcon);
arch/arm/mach-s3c/gpio-samsung.c
413
con = __raw_readl(regcon);
arch/arm/mach-s3c/gpio-samsung.c
417
dat = __raw_readl(base + GPIODAT_OFF);
arch/arm/mach-s3c/gpio-samsung.c
443
dat = __raw_readl(base + 0x04);
arch/arm/mach-s3c/gpio-samsung.c
459
val = __raw_readl(ourchip->base + 0x04);
arch/arm/mach-s3c/gpio-samsung.c
47
pup = __raw_readl(reg);
arch/arm/mach-s3c/gpio-samsung.c
60
u32 pup = __raw_readl(reg);
arch/arm/mach-s3c/gpio-samsung.c
83
con = __raw_readl(reg);
arch/arm/mach-s3c/irq-pm-s3c64xx.c
71
irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
arch/arm/mach-s3c/irq-pm-s3c64xx.c
74
grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
arch/arm/mach-s3c/irq-pm-s3c64xx.c
75
grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
arch/arm/mach-s3c/irq-pm-s3c64xx.c
76
grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
arch/arm/mach-s3c/pm-core-s3c64xx.h
30
__raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
arch/arm/mach-s3c/pm-gpio.c
123
u32 old_gpcon = __raw_readl(base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
124
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
194
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
195
chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
196
chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
arch/arm/mach-s3c/pm-gpio.c
199
chip->pm_save[0] = __raw_readl(chip->base - 4);
arch/arm/mach-s3c/pm-gpio.c
244
u32 old_gpcon = __raw_readl(con);
arch/arm/mach-s3c/pm-gpio.c
260
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
266
old_gpcon[1] = __raw_readl(base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
270
old_gpcon[0] = __raw_readl(base - 4);
arch/arm/mach-s3c/pm-gpio.c
287
__raw_readl(base - 4),
arch/arm/mach-s3c/pm-gpio.c
288
__raw_readl(base + OFFS_CON),
arch/arm/mach-s3c/pm-gpio.c
29
chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
293
__raw_readl(base + OFFS_CON),
arch/arm/mach-s3c/pm-gpio.c
30
chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
36
u32 old_gpcon = __raw_readl(base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
37
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
66
chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
arch/arm/mach-s3c/pm-gpio.c
67
chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
arch/arm/mach-s3c/pm-gpio.c
68
chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
arch/arm/mach-s3c/pm-s3c64xx.c
232
tmp = __raw_readl(S3C64XX_PWR_CFG);
arch/arm/mach-s3c/pm-s3c64xx.c
239
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
arch/arm/mach-s3c/pm-s3c64xx.c
283
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
arch/arm/mach-s3c/pm-s3c64xx.c
48
val = __raw_readl(S3C64XX_NORMAL_CFG);
arch/arm/mach-s3c/pm-s3c64xx.c
63
val = __raw_readl(S3C64XX_NORMAL_CFG);
arch/arm/mach-s3c/pm-s3c64xx.c
71
if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
arch/arm/mach-s3c/s3c64xx.c
243
mask = __raw_readl(S3C64XX_EINT0MASK);
arch/arm/mach-s3c/s3c64xx.c
252
mask = __raw_readl(S3C64XX_EINT0MASK);
arch/arm/mach-s3c/s3c64xx.c
322
ctrl = __raw_readl(reg);
arch/arm/mach-s3c/s3c64xx.c
363
u32 status = __raw_readl(S3C64XX_EINT0PEND);
arch/arm/mach-s3c/s3c64xx.c
364
u32 mask = __raw_readl(S3C64XX_EINT0MASK);
arch/arm/mach-s3c/wakeup-mask.c
23
val = __raw_readl(reg);
arch/arm/mach-s3c/wakeup-mask.c
40
printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val);
arch/arm/mach-s5pv210/pm.c
117
tmp = __raw_readl(S5P_SLEEP_CFG);
arch/arm/mach-s5pv210/pm.c
122
tmp = __raw_readl(S5P_PWR_CFG);
arch/arm/mach-s5pv210/pm.c
128
tmp = __raw_readl(S5P_OTHERS);
arch/arm/mach-s5pv210/pm.c
167
__raw_readl(S5P_WAKEUP_STAT));
arch/arm/mach-s5pv210/pm.c
78
return __raw_readl(S5P_EINT_WAKEUP_MASK);
arch/arm/mm/cache-b15-rac.c
357
reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
arch/arm/mm/cache-b15-rac.c
65
u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
arch/arm/mm/cache-b15-rac.c
82
reg = __raw_readl(b15_rac_base + rac_flush_offset);
arch/arm64/include/asm/io.h
299
#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
arch/arm64/include/asm/io.h
76
#define __raw_readl __raw_readl
arch/hexagon/include/asm/io.h
75
#define __raw_readl __raw_readl
arch/m68k/coldfire/dma_timer.c
40
return __raw_readl(DTCN0);
arch/m68k/coldfire/dma_timer.c
79
unsigned long cycl = __raw_readl(DTCN0);
arch/m68k/coldfire/intc-2.c
64
val = __raw_readl(imraddr);
arch/m68k/coldfire/intc-2.c
86
val = __raw_readl(imraddr);
arch/m68k/coldfire/intc.c
72
imr = __raw_readl(MCFSIM_IMR);
arch/m68k/coldfire/intc.c
79
imr = __raw_readl(MCFSIM_IMR);
arch/m68k/coldfire/intc.c
86
imr = __raw_readl(MCFSIM_IMR);
arch/m68k/coldfire/m5441x.c
204
__raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
arch/m68k/coldfire/m5441x.c
209
__raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
arch/m68k/coldfire/pci.c
104
__raw_readl(PCICAR);
arch/m68k/coldfire/pci.c
120
__raw_readl(PCICAR);
arch/m68k/coldfire/pci.c
72
__raw_readl(PCICAR);
arch/m68k/coldfire/pci.c
83
*value = le32_to_cpu(__raw_readl(addr));
arch/m68k/coldfire/pci.c
88
__raw_readl(PCICAR);
arch/m68k/coldfire/sltimers.c
101
scnt = __raw_readl(TA(MCFSLT_SCNT));
arch/m68k/coldfire/sltimers.c
103
if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
arch/m68k/coldfire/sltimers.c
105
scnt = __raw_readl(TA(MCFSLT_SCNT));
arch/m68k/coldfire/timers.c
41
#define __raw_readtrr __raw_readl
arch/m68k/include/asm/io_no.h
103
#define readl __raw_readl
arch/m68k/include/asm/io_no.h
77
return __raw_readl(addr);
arch/m68k/include/asm/io_no.h
78
return swab32(__raw_readl(addr));
arch/m68k/include/asm/mcfgpio.h
116
#define mcfgpio_read(port) __raw_readl(port)
arch/microblaze/include/asm/io.h
41
#define in_be32(a) __raw_readl((const void __iomem __force *)(a))
arch/microblaze/include/asm/io.h
51
#define in_le32(a) __le32_to_cpu(__raw_readl(a))
arch/mips/alchemy/common/clock.c
315
v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
arch/mips/alchemy/common/clock.c
319
v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
arch/mips/alchemy/common/dbdma.c
1000
alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);
arch/mips/alchemy/common/dbdma.c
1001
alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);
arch/mips/alchemy/common/dbdma.c
1002
alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);
arch/mips/alchemy/common/dbdma.c
1003
alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);
arch/mips/alchemy/common/dbdma.c
1004
alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);
arch/mips/alchemy/common/dbdma.c
1009
while (!(__raw_readl(addr + 0x14) & 1))
arch/mips/alchemy/common/dbdma.c
991
alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);
arch/mips/alchemy/common/dbdma.c
992
alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);
arch/mips/alchemy/common/dbdma.c
993
alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);
arch/mips/alchemy/common/dbdma.c
994
alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);
arch/mips/alchemy/common/dbdma.c
999
alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);
arch/mips/alchemy/common/irq.c
520
l = __raw_readl(r + AU1300_GPIC_PINCFG);
arch/mips/alchemy/common/irq.c
586
r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
arch/mips/alchemy/common/irq.c
735
d[0] = __raw_readl(base + IC_CFG0RD);
arch/mips/alchemy/common/irq.c
736
d[1] = __raw_readl(base + IC_CFG1RD);
arch/mips/alchemy/common/irq.c
737
d[2] = __raw_readl(base + IC_CFG2RD);
arch/mips/alchemy/common/irq.c
738
d[3] = __raw_readl(base + IC_SRCRD);
arch/mips/alchemy/common/irq.c
739
d[4] = __raw_readl(base + IC_ASSIGNRD);
arch/mips/alchemy/common/irq.c
740
d[5] = __raw_readl(base + IC_WAKERD);
arch/mips/alchemy/common/irq.c
741
d[6] = __raw_readl(base + IC_MASKRD);
arch/mips/alchemy/common/irq.c
784
alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
arch/mips/alchemy/common/irq.c
785
alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
arch/mips/alchemy/common/irq.c
786
alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
arch/mips/alchemy/common/irq.c
787
alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
arch/mips/alchemy/common/irq.c
790
alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
arch/mips/alchemy/common/irq.c
802
alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
arch/mips/alchemy/common/irq.c
864
unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \
arch/mips/alchemy/common/irq.c
878
int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
arch/mips/alchemy/common/usb.c
102
r = __raw_readl(base + USB_DWC_CTRL2);
arch/mips/alchemy/common/usb.c
103
s = __raw_readl(base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
131
r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
arch/mips/alchemy/common/usb.c
139
r = __raw_readl(base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
148
r = __raw_readl(base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
153
r = __raw_readl(base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
168
r = __raw_readl(base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
173
r = __raw_readl(base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
180
r = __raw_readl(base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
185
r = __raw_readl(base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
190
r = __raw_readl(base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
195
r = __raw_readl(base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
209
r = __raw_readl(base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
216
r = __raw_readl(base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
221
r = __raw_readl(base + USB_INT_ENABLE);
arch/mips/alchemy/common/usb.c
226
r = __raw_readl(base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
239
r = __raw_readl(base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
244
r = __raw_readl(base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
251
r = __raw_readl(base + USB_DWC_CTRL1);
arch/mips/alchemy/common/usb.c
256
r = __raw_readl(base + USB_DWC_CTRL3);
arch/mips/alchemy/common/usb.c
318
unsigned long r = __raw_readl(base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
332
unsigned long r = __raw_readl(base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
348
unsigned long r = __raw_readl(base + AU1200_USBCFG);
arch/mips/alchemy/common/usb.c
395
unsigned long r = __raw_readl(base);
arch/mips/alchemy/common/usb.c
428
unsigned long r = __raw_readl(base + creg);
arch/mips/alchemy/common/usb.c
446
while (__raw_readl(base + creg),
arch/mips/alchemy/common/usb.c
447
!(__raw_readl(base + creg) & USBHEN_RD))
arch/mips/alchemy/common/usb.c
517
alchemy_usb_pmdata[0] = __raw_readl(base + creg);
arch/mips/alchemy/common/usb.c
536
alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
arch/mips/alchemy/common/usb.c
537
alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
arch/mips/alchemy/common/usb.c
555
alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
arch/mips/ath25/ar2315.c
265
memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
arch/mips/ath25/ar2315.c
40
return __raw_readl(ar2315_rst_base + reg);
arch/mips/ath25/ar5312.c
188
ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
arch/mips/ath25/ar5312.c
213
ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
arch/mips/ath25/ar5312.c
216
ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
arch/mips/ath25/ar5312.c
360
memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
arch/mips/ath25/ar5312.c
41
return __raw_readl(ar5312_rst_base + reg);
arch/mips/ath25/board.c
34
return __raw_readl(addr) != 0xffffffff;
arch/mips/ath25/board.c
40
if (__raw_readl(addr) == ATH25_BD_MAGIC)
arch/mips/ath25/early_printk.c
26
return __raw_readl(base + 4 * reg);
arch/mips/ath79/clock.c
105
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
arch/mips/ath79/clock.c
131
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
arch/mips/ath79/clock.c
165
clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
arch/mips/ath79/clock.c
178
cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
253
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
arch/mips/ath79/clock.c
257
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
arch/mips/ath79/clock.c
265
pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
280
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
arch/mips/ath79/clock.c
284
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
arch/mips/ath79/clock.c
292
pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
307
clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
arch/mips/ath79/clock.c
343
clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
arch/mips/ath79/clock.c
368
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
382
pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
396
clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
arch/mips/ath79/clock.c
451
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
465
pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
479
clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
arch/mips/ath79/clock.c
544
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
arch/mips/ath79/clock.c
550
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
arch/mips/ath79/clock.c
563
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
arch/mips/ath79/clock.c
568
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
arch/mips/ath79/clock.c
581
clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
arch/mips/ath79/common.c
62
while (__raw_readl(flush_reg) & 0x1)
arch/mips/ath79/common.c
67
while (__raw_readl(flush_reg) & 0x1)
arch/mips/ath79/early_printk.c
103
id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
arch/mips/ath79/early_printk.c
27
t = __raw_readl(reg);
arch/mips/ath79/early_printk.c
92
t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
arch/mips/bmips/dma.c
24
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/bmips/dma.c
26
__raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/bmips/setup.c
102
if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
arch/mips/generic/board-ocelot.c
33
rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
arch/mips/generic/board-sead3.c
39
rev = __raw_readl((void *)MIPS_REVISION);
arch/mips/generic/board-sead3.c
57
cfg = __raw_readl((uint32_t *)SEAD_CONFIG);
arch/mips/include/asm/io.h
363
be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
arch/mips/include/asm/io.h
494
#define __raw_readl __raw_readl
arch/mips/include/asm/mach-ath79/ath79.h
161
return __raw_readl(ath79_pll_base + reg);
arch/mips/include/asm/mach-ath79/ath79.h
167
(void) __raw_readl(ath79_reset_base + reg); /* flush */
arch/mips/include/asm/mach-ath79/ath79.h
172
return __raw_readl(ath79_reset_base + reg);
arch/mips/include/asm/mach-au1x00/au1000.h
608
return __raw_readl(b + regofs);
arch/mips/include/asm/mach-au1x00/au1000.h
624
return __raw_readl(b + regofs);
arch/mips/include/asm/mach-au1x00/au1000.h
732
if ((__raw_readl(addr + 0x100) & 3) != 3) {
arch/mips/include/asm/mach-au1x00/au1000.h
758
if (__raw_readl(base + 0x1c) & 0x20)
arch/mips/include/asm/mach-au1x00/au1000_dma.h
201
if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
arch/mips/include/asm/mach-au1x00/au1000_dma.h
226
return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
arch/mips/include/asm/mach-au1x00/au1000_dma.h
285
return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
arch/mips/include/asm/mach-au1x00/au1000_dma.h
412
return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
arch/mips/include/asm/mach-au1x00/au1000_dma.h
439
curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
arch/mips/include/asm/mach-au1x00/au1000_dma.h
442
count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
288
unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
310
return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
362
unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
114
v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
37
return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
arch/mips/include/asm/mach-lantiq/lantiq.h
14
#define ltq_r32(reg) __raw_readl(reg)
arch/mips/include/asm/mach-ralink/ralink_regs.h
42
return __raw_readl(rt_sysc_membase + reg);
arch/mips/include/asm/mach-ralink/ralink_regs.h
59
return __raw_readl(rt_memc_membase + reg);
arch/mips/include/asm/mach-rc32434/dma_v.h
29
if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
arch/mips/include/asm/mach-rc32434/dma_v.h
32
if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
arch/mips/include/asm/mips-cps.h
31
return __raw_readl(addr_##unit##_##name()); \
arch/mips/include/asm/mips-cps.h
37
val64 = __raw_readl(addr_##unit##_##name() + 4); \
arch/mips/include/asm/mips-cps.h
39
val64 |= __raw_readl(addr_##unit##_##name()); \
arch/mips/include/asm/mips-gic.h
112
val = __raw_readl(addr) >> intr % 32; \
arch/mips/include/asm/mips-gic.h
152
_val = __raw_readl(addr); \
arch/mips/include/asm/mips-gic.h
59
return __raw_readl(addr_gic_##name(intr)); \
arch/mips/include/asm/pci/bridge.h
818
#define bridge_read(bc, reg) __raw_readl(&bc->base->reg)
arch/mips/include/asm/pci/bridge.h
821
__raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
arch/mips/include/asm/pci/bridge.h
823
__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
arch/mips/include/asm/vdso/gettimeofday.h
176
hi = __raw_readl(gic + sizeof(lo));
arch/mips/include/asm/vdso/gettimeofday.h
177
lo = __raw_readl(gic);
arch/mips/include/asm/vdso/gettimeofday.h
178
hi2 = __raw_readl(gic + sizeof(lo));
arch/mips/kernel/cevt-txx9.c
34
return __raw_readl(&txx9_cs->tmrptr->trr);
arch/mips/kernel/cevt-txx9.c
52
return __raw_readl(&txx9_clocksource.tmrptr->trr);
arch/mips/kernel/gpio_txx9.c
21
return !!(__raw_readl(&txx9_pioptr->din) & (1 << offset));
arch/mips/kernel/gpio_txx9.c
27
val = __raw_readl(&txx9_pioptr->dout);
arch/mips/kernel/gpio_txx9.c
51
__raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset),
arch/mips/kernel/gpio_txx9.c
64
__raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset),
arch/mips/kernel/irq_txx9.c
118
cr = __raw_readl(crp);
arch/mips/kernel/irq_txx9.c
173
u32 csr = __raw_readl(&txx9_ircptr->csr);
arch/mips/kernel/irq_txx9.c
72
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
arch/mips/kernel/irq_txx9.c
83
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
arch/mips/kernel/smp-bmips.c
611
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
613
__raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
615
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
617
__raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
619
cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
arch/mips/kernel/smp-bmips.c
621
__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
arch/mips/kernel/smp-bmips.c
631
cfg = __raw_readl(cbr + rac_addr);
arch/mips/kernel/smp-bmips.c
633
__raw_readl(cbr + rac_addr);
arch/mips/kernel/smp-bmips.c
636
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
638
__raw_readl(cbr + BMIPS_RAC_CONFIG);
arch/mips/kernel/smp-bmips.c
648
cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
arch/mips/kernel/smp-bmips.c
650
__raw_readl(cbr + BMIPS_L2_CONFIG);
arch/mips/mti-malta/malta-dtshim.c
245
sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS);
arch/mips/mti-malta/malta-int.c
73
irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
arch/mips/mti-malta/malta-setup.c
119
cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
arch/mips/mti-malta/malta-setup.c
136
int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
arch/mips/pci/ops-bcm63xx.c
112
data = le32_to_cpu(__raw_readl(pci_iospace_start));
arch/mips/pci/ops-bcm63xx.c
134
data = le32_to_cpu(__raw_readl(pci_iospace_start));
arch/mips/pci/ops-tx4927.c
110
return __raw_readl(&pcicptr->g2pcfgdata);
arch/mips/pci/ops-tx4927.c
234
__raw_readl(&pcicptr->pciid) >> 16,
arch/mips/pci/ops-tx4927.c
235
__raw_readl(&pcicptr->pciid) & 0xffff,
arch/mips/pci/ops-tx4927.c
236
__raw_readl(&pcicptr->pciccrev) & 0xff,
arch/mips/pci/ops-tx4927.c
243
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
311
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
316
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
320
__raw_writel(__raw_readl(&pcicptr->pciccfg)
arch/mips/pci/ops-tx4927.c
327
__raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
arch/mips/pci/ops-tx4927.c
341
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/ops-tx4927.c
363
__raw_readl(&pcicptr->pcistatus) & 0xffff,
arch/mips/pci/ops-tx4927.c
364
__raw_readl(&pcicptr->pcimask) & 0xffff,
arch/mips/pci/ops-tx4927.c
365
__raw_readl(&pcicptr->g2ptocnt) & 0xff,
arch/mips/pci/ops-tx4927.c
366
(__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
arch/mips/pci/ops-tx4927.c
367
(__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
arch/mips/pci/ops-tx4927.c
372
__u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
arch/mips/pci/ops-tx4927.c
373
__u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
arch/mips/pci/ops-tx4927.c
374
__u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
arch/mips/pci/ops-tx4927.c
457
printk(KERN_CONT " %08x", __raw_readl(preg));
arch/mips/pci/ops-tx4927.c
485
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/ops-tx4927.c
505
if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
arch/mips/pci/ops-tx4927.c
522
__raw_readl(&pcicptr->pbareqport));
arch/mips/pci/ops-tx4927.c
69
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/ops-tx4927.c
80
while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
arch/mips/pci/ops-tx4927.c
82
if (__raw_readl(&pcicptr->pcistatus)
arch/mips/pci/ops-tx4927.c
84
__raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
arch/mips/pci/pci-alchemy.c
114
r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
arch/mips/pci/pci-alchemy.c
157
*data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
arch/mips/pci/pci-alchemy.c
164
status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
arch/mips/pci/pci-alchemy.c
313
ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
arch/mips/pci/pci-alchemy.c
314
ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
arch/mips/pci/pci-alchemy.c
315
ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
arch/mips/pci/pci-alchemy.c
316
ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
arch/mips/pci/pci-alchemy.c
317
ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
arch/mips/pci/pci-alchemy.c
318
ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
arch/mips/pci/pci-alchemy.c
319
ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
arch/mips/pci/pci-alchemy.c
320
ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
arch/mips/pci/pci-alchemy.c
321
ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
arch/mips/pci/pci-alchemy.c
322
ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
arch/mips/pci/pci-alchemy.c
323
ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
arch/mips/pci/pci-alchemy.c
324
ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
arch/mips/pci/pci-alchemy.c
438
val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
arch/mips/pci/pci-alchemy.c
476
val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
arch/mips/pci/pci-ar2315.c
193
return __raw_readl(apc->mmr_mem + reg);
arch/mips/pci/pci-ar2315.c
234
value = __raw_readl(apc->cfg_mem + addr);
arch/mips/pci/pci-ar71xx.c
113
pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
arch/mips/pci/pci-ar71xx.c
118
addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
arch/mips/pci/pci-ar71xx.c
127
ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
arch/mips/pci/pci-ar71xx.c
132
addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
arch/mips/pci/pci-ar71xx.c
193
data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
arch/mips/pci/pci-ar71xx.c
234
pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
arch/mips/pci/pci-ar71xx.c
235
__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
263
t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
267
__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
280
t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar71xx.c
284
__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
arch/mips/pci/pci-ar724x.c
108
__raw_readl(base + (where & ~3));
arch/mips/pci/pci-ar724x.c
128
data = __raw_readl(base + (where & ~3));
arch/mips/pci/pci-ar724x.c
197
data = __raw_readl(base + (where & ~3));
arch/mips/pci/pci-ar724x.c
219
__raw_readl(base + (where & ~3));
arch/mips/pci/pci-ar724x.c
238
pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
arch/mips/pci/pci-ar724x.c
239
__raw_readl(base + AR724X_PCI_REG_INT_MASK);
arch/mips/pci/pci-ar724x.c
261
t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
arch/mips/pci/pci-ar724x.c
265
__raw_readl(base + AR724X_PCI_REG_INT_MASK);
arch/mips/pci/pci-ar724x.c
282
t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
arch/mips/pci/pci-ar724x.c
287
__raw_readl(base + AR724X_PCI_REG_INT_MASK);
arch/mips/pci/pci-ar724x.c
289
t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
arch/mips/pci/pci-ar724x.c
294
__raw_readl(base + AR724X_PCI_REG_INT_STATUS);
arch/mips/pci/pci-ar724x.c
349
app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
arch/mips/pci/pci-ar724x.c
60
reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
arch/mips/pci/pci-ar724x.c
86
data = __raw_readl(base + (where & ~3));
arch/mips/pic32/common/reset.c
34
(void)__raw_readl(reg);
arch/mips/pic32/pic32mzda/early_clk.c
46
osccon = __raw_readl(osc_base + OSCCON);
arch/mips/pic32/pic32mzda/early_clk.c
47
spllcon = __raw_readl(osc_base + SPLLCON);
arch/mips/pic32/pic32mzda/early_clk.c
92
u32 pbdiv = (__raw_readl(osc_base + pbxdiv) & PB_MASK) + 1;
arch/mips/pic32/pic32mzda/early_console.c
156
while (__raw_readl(
arch/mips/ralink/early_printk.c
42
return __raw_readl(uart_membase + reg);
arch/mips/ralink/early_printk.c
48
(__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
arch/mips/ralink/irq.c
67
return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
arch/mips/ralink/mt7620.c
103
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1);
arch/mips/ralink/mt7620.c
126
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV);
arch/mips/ralink/mt7620.c
136
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG);
arch/mips/ralink/mt7620.c
231
cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0);
arch/mips/ralink/mt7620.c
247
pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG);
arch/mips/ralink/mt7620.c
248
pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG);
arch/mips/ralink/mt7620.c
98
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0);
arch/mips/ralink/mt7621.c
121
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
arch/mips/ralink/mt7621.c
71
if (__raw_readl(dm) != __raw_readl(dm + size))
arch/mips/ralink/mt7621.c
74
return __raw_readl(dm) == __raw_readl(dm + size);
arch/mips/ralink/mt7621.c
94
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
arch/mips/ralink/mt7621.c
99
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
arch/mips/ralink/rt288x.c
26
return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0);
arch/mips/ralink/rt288x.c
31
return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1);
arch/mips/ralink/rt288x.c
53
return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID);
arch/mips/ralink/rt305x.c
140
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_ID);
arch/mips/ralink/rt305x.c
31
t = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG);
arch/mips/ralink/rt305x.c
61
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0);
arch/mips/ralink/rt305x.c
66
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1);
arch/mips/ralink/rt3883.c
26
return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3);
arch/mips/ralink/rt3883.c
31
return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID4_7);
arch/mips/ralink/rt3883.c
53
return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_REVID);
arch/mips/ralink/timer.c
49
return __raw_readl(rt->membase + reg);
arch/mips/rb532/setup.c
59
val = __raw_readl(&pci_reg->pcic);
arch/mips/sgi-ip22/ip22-nvram.c
36
__raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
37
__raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
38
__raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
40
__raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
41
__raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
arch/mips/sgi-ip22/ip22-nvram.c
45
__raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
46
__raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
47
__raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
arch/mips/sgi-ip22/ip22-nvram.c
48
__raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
arch/mips/sgi-ip22/ip22-nvram.c
64
__raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
66
__raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
67
__raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
69
__raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
74
__raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
82
__raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
88
__raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
90
__raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
arch/mips/sgi-ip22/ip22-nvram.c
93
if (__raw_readl(ctrl) & EEPROM_DATI)
arch/mips/sgi-ip30/ip30-setup.c
58
memcfg = __raw_readl(&heart_regs->mem_cfg.l[i]);
arch/mips/sgi-ip30/ip30-xtalk.c
37
#define xtalk_read __raw_readl
arch/mips/txx9/generic/setup.c
412
while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
arch/parisc/lib/iomap.c
179
return __raw_readl(addr);
arch/parisc/lib/iomap.c
250
*(u32 *)dst = __raw_readl(addr);
arch/powerpc/kvm/book3s_xive.c
771
__raw_readl(tima + TM_SPC_PULL_OS_CTX);
arch/powerpc/platforms/powermac/feature.c
2491
if (__raw_readl(mach_id_ptr) & 0x20000000UL)
arch/riscv/include/asm/mmio.h
63
#define __raw_readl __raw_readl
arch/riscv/include/asm/mmio.h
90
#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
arch/sh/boards/board-magicpanelr2.c
33
#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
arch/sh/boards/mach-dreamcast/rtc.c
39
val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
arch/sh/boards/mach-dreamcast/rtc.c
40
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
arch/sh/boards/mach-dreamcast/rtc.c
42
val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
arch/sh/boards/mach-dreamcast/rtc.c
43
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
arch/sh/boards/mach-dreamcast/rtc.c
71
val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
arch/sh/boards/mach-dreamcast/rtc.c
72
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
arch/sh/boards/mach-dreamcast/rtc.c
74
val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
arch/sh/boards/mach-dreamcast/rtc.c
75
(__raw_readl(AICA_RTC_SECS_L) & 0xffff);
arch/sh/boards/mach-landisk/gio.c
105
data = __raw_readl(addr);
arch/sh/boards/mach-migor/setup.c
484
__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
arch/sh/boards/mach-sh7763rdp/irq.c
31
__raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
arch/sh/boards/mach-sh7763rdp/setup.c
204
__raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);
arch/sh/boards/mach-x3proto/setup.c
222
__raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
arch/sh/boot/romimage/mmcif-sh7724.c
42
__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
arch/sh/boot/romimage/mmcif-sh7724.c
75
__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
arch/sh/drivers/dma/dma-pvr2.c
40
if (__raw_readl(PVR2_DMA_MODE) != 0)
arch/sh/drivers/dma/dma-sh.c
105
u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
arch/sh/drivers/dma/dma-sh.c
123
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
arch/sh/drivers/dma/dma-sh.c
174
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
arch/sh/drivers/dma/dma-sh.c
198
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
arch/sh/drivers/dma/dma-sh.c
246
if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE))
arch/sh/drivers/dma/dma-sh.c
249
return __raw_readl(dma_base_addr(chan->chan) + TCR)
arch/sh/drivers/dma/dmabrg.c
112
dcr = __raw_readl(DMABRGCR);
arch/sh/drivers/dma/dmabrg.c
120
dcr = __raw_readl(DMABRGCR);
arch/sh/drivers/dma/dmabrg.c
172
or = __raw_readl(DMAOR);
arch/sh/drivers/dma/dmabrg.c
89
dcr = __raw_readl(DMABRGCR);
arch/sh/drivers/pci/fixups-landisk.c
43
bcr1 = __raw_readl(SH7751_BCR1);
arch/sh/drivers/pci/fixups-landisk.c
47
mcr = __raw_readl(SH7751_MCR);
arch/sh/drivers/pci/fixups-rts7751r2d.c
43
bcr1 = __raw_readl(SH7751_BCR1);
arch/sh/drivers/pci/fixups-rts7751r2d.c
54
mcr = __raw_readl(SH7751_MCR);
arch/sh/drivers/pci/pci-sh4.h
179
return __raw_readl(chan->reg_base + reg);
arch/sh/drivers/pci/pci-sh7751.c
156
word = __raw_readl(SH7751_WCR1);
arch/sh/drivers/pci/pci-sh7751.c
158
word = __raw_readl(SH7751_WCR2);
arch/sh/drivers/pci/pci-sh7751.c
160
word = __raw_readl(SH7751_WCR3);
arch/sh/drivers/pci/pci-sh7751.c
162
word = __raw_readl(SH7751_MCR);
arch/sh/drivers/pci/pci-sh7751.c
24
word = __raw_readl(SH7751_BCR1);
arch/sh/drivers/pci/pci-sh7751.c
94
reg = __raw_readl(SH7751_BCR1);
arch/sh/drivers/pci/pci-sh7780.c
100
addr = __raw_readl(hose->reg_base + SH4_PCIALR);
arch/sh/drivers/pci/pci-sh7780.c
119
status = __raw_readl(hose->reg_base + SH4_PCIAINT);
arch/sh/drivers/pci/pci-sh7780.c
132
status = __raw_readl(hose->reg_base + SH4_PCIINT);
arch/sh/drivers/pci/pci-sh7780.c
229
tmp = __raw_readl(hose->reg_base + SH4_PCICR);
arch/sh/drivers/pci/pci-sh7780.c
239
tmp = __raw_readl(hose->reg_base + SH4_PCICR);
arch/sh/drivers/pci/pcie-sh7786.h
574
return __raw_readl(chan->reg_base + reg);
arch/sh/include/asm/io.h
40
#define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
arch/sh/include/asm/mmu_context.h
163
cr = __raw_readl(MMUCR);
arch/sh/include/asm/mmu_context_32.h
13
return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK;
arch/sh/include/asm/mmu_context_32.h
49
return (pgd_t *)__raw_readl(MMU_TTB);
arch/sh/include/asm/watchdog.h
101
return __raw_readl(WTCSR_R);
arch/sh/include/asm/watchdog.h
68
return __raw_readl(WTCNT_R);
arch/sh/include/cpu-sh4/cpu/sh7786.h
135
return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7;
arch/sh/include/mach-common/mach/magicpanelr2.h
21
#define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
arch/sh/include/mach-common/mach/magicpanelr2.h
24
#define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
arch/sh/kernel/cpu/init.c
112
ccr = __raw_readl(SH_CCR);
arch/sh/kernel/cpu/init.c
62
__raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
arch/sh/kernel/cpu/init.c
65
(void)__raw_readl(CPUOPM);
arch/sh/kernel/cpu/init.c
80
unsigned long expmask = __raw_readl(EXPMASK);
arch/sh/kernel/cpu/sh2/smp-j2.c
105
return __raw_readl(sh2_cpuid_addr);
arch/sh/kernel/cpu/sh2/smp-j2.c
121
val = __raw_readl(j2_ipi_trigger + cpu);
arch/sh/kernel/cpu/sh3/probe.c
30
data0 = __raw_readl(addr0);
arch/sh/kernel/cpu/sh3/probe.c
32
data1 = __raw_readl(addr1);
arch/sh/kernel/cpu/sh3/probe.c
36
data0 = __raw_readl(addr0);
arch/sh/kernel/cpu/sh3/probe.c
39
data1 = __raw_readl(addr1);
arch/sh/kernel/cpu/sh3/probe.c
42
data3 = __raw_readl(addr0);
arch/sh/kernel/cpu/sh4/perf_event.c
204
return (u64)((u64)(__raw_readl(PMCTRH(idx)) & 0xffff) << 32) |
arch/sh/kernel/cpu/sh4/perf_event.c
205
__raw_readl(PMCTRL(idx));
arch/sh/kernel/cpu/sh4/probe.c
28
pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
arch/sh/kernel/cpu/sh4/probe.c
29
prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
arch/sh/kernel/cpu/sh4/probe.c
30
cvr = (__raw_readl(CCN_CVR));
arch/sh/kernel/cpu/sh4/sq.c
44
(void)__raw_readl(P4SEG_STORE_QUE); \
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
257
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
44
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
45
mult = __raw_readl(DLLFRQ);
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
66
if (__raw_readl(PLLCR) & 0x4000)
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
67
mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
250
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
44
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
45
mult = __raw_readl(DLLFRQ);
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
67
if (__raw_readl(PLLCR) & 0x4000)
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
68
mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
225
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
47
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
48
mult = __raw_readl(DLLFRQ);
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
70
if (__raw_readl(PLLCR) & 0x4000)
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
71
mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
273
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
48
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
49
mult = __raw_readl(DLLFRQ);
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
71
if (__raw_readl(PLLCR) & 0x4000)
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
72
mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
131
value = __raw_readl(FRQCRA);
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
347
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
52
if (__raw_readl(PLLCR) & 0x1000)
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
53
mult = __raw_readl(FLLFRQ) & 0x3ff;
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
55
if (__raw_readl(FLLFRQ) & 0x4000)
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
75
if (__raw_readl(PLLCR) & 0x4000)
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
76
mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
30
u32 r = __raw_readl(MODEMR);
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
24
clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
33
int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
43
int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
arch/sh/kernel/cpu/sh4a/clock-sh7763.c
70
int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
arch/sh/kernel/cpu/sh4a/clock-sh7770.c
21
clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
arch/sh/kernel/cpu/sh4a/clock-sh7770.c
30
int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
arch/sh/kernel/cpu/sh4a/clock-sh7770.c
40
int idx = (__raw_readl(FRQCR) & 0x000f);
arch/sh/kernel/cpu/sh4a/clock-sh7770.c
50
int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
24
clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
33
int idx = (__raw_readl(FRQCR) & 0x0003);
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
43
int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
53
int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
arch/sh/kernel/cpu/sh4a/clock-sh7780.c
76
int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
arch/sh/kernel/cpu/sh4a/intc-shx3.c
18
return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
arch/sh/kernel/cpu/sh4a/perf_event.c
229
return __raw_readl(PPC_PMCTR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
236
tmp = __raw_readl(PPC_CCBR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
245
tmp = __raw_readl(PPC_PMCAT);
arch/sh/kernel/cpu/sh4a/perf_event.c
250
tmp = __raw_readl(PPC_CCBR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
254
__raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
arch/sh/kernel/cpu/sh4a/perf_event.c
262
__raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
arch/sh/kernel/cpu/sh4a/perf_event.c
270
__raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1156
sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1158
sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1159
sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1160
sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1161
sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1162
sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1163
sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1164
sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1165
sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1166
sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1167
sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1168
sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1205
sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
1206
sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
592
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
595
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7734.c
605
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1197
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1200
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1210
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
1215
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
429
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
532
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
535
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
545
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
466
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
469
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
479
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
558
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
561
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
571
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
576
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
435
if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
743
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
753
__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
758
__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
arch/sh/kernel/cpu/sh4a/smp-shx3.c
103
return __raw_readl(0xff000048); /* CPIDR */
arch/sh/kernel/cpu/sh4a/smp-shx3.c
118
while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
arch/sh/kernel/cpu/sh4a/smp-shx3.c
34
x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
arch/sh/kernel/cpu/sh4a/smp-shx3.c
51
__raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
arch/sh/kernel/cpu/sh4a/smp-shx3.c
91
if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
arch/sh/kernel/cpu/sh4a/smp-shx3.c
94
while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
arch/sh/kernel/cpu/sh4a/ubc.c
121
(void)__raw_readl(UBC_CRR(i));
arch/sh/kernel/cpu/sh4a/ubc.c
50
__raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
arch/sh/kernel/cpu/sh4a/ubc.c
59
__raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
arch/sh/kernel/cpu/sh4a/ubc.c
69
if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
arch/sh/kernel/cpu/sh4a/ubc.c
77
return __raw_readl(UBC_CCMFR);
arch/sh/kernel/cpu/sh4a/ubc.c
82
__raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
arch/sh/kernel/dwarf.c
676
frame->cfa = __raw_readl(addr);
arch/sh/kernel/dwarf.c
708
frame->return_addr = __raw_readl(addr);
arch/sh/kernel/ftrace.c
269
if (old_addr != __raw_readl((unsigned long *)code))
arch/sh/kernel/io_trapped.c
196
tmp = __raw_readl(src_addr);
arch/sh/kernel/process_32.c
42
pr_cont("TEA : %08x\n", __raw_readl(MMU_TEA));
arch/sh/lib/io.c
19
*data++ = __raw_readl(addr);
arch/sh/lib/io.c
59
*data++ = __raw_readl(addr);
arch/sh/mm/cache-debugfs.c
39
ccr = __raw_readl(SH_CCR);
arch/sh/mm/cache-debugfs.c
77
unsigned long data = __raw_readl(addr);
arch/sh/mm/cache-j2.c
63
pr_info("Initial J2 CCR is %.8x\n", __raw_readl(j2_ccr_base));
arch/sh/mm/cache-sh2.c
30
unsigned long data = __raw_readl(addr | (way << 12));
arch/sh/mm/cache-sh2.c
65
ccr = __raw_readl(SH_CCR);
arch/sh/mm/cache-sh2a.c
136
__raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
arch/sh/mm/cache-sh2a.c
170
__raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
arch/sh/mm/cache-sh2a.c
31
data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
arch/sh/mm/cache-sh2a.c
71
unsigned long data = __raw_readl(v);
arch/sh/mm/cache-sh3.c
50
data = __raw_readl(addr);
arch/sh/mm/cache-sh4.c
146
ccr = __raw_readl(SH_CCR);
arch/sh/mm/cache-sh4.c
386
__raw_readl(CCN_PVR),
arch/sh/mm/cache-sh4.c
387
__raw_readl(CCN_CVR),
arch/sh/mm/cache-sh4.c
388
__raw_readl(CCN_PRR));
arch/sh/mm/cache-sh7705.c
117
data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
arch/sh/mm/cache-sh7705.c
50
data = __raw_readl(addr);
arch/sh/mm/cache-shx3.c
23
ccr = __raw_readl(SH_CCR);
arch/sh/mm/cache.c
304
cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
arch/sh/mm/pmb.c
316
addr_val = __raw_readl(addr);
arch/sh/mm/pmb.c
317
data_val = __raw_readl(data);
arch/sh/mm/pmb.c
587
addr_val = __raw_readl(addr);
arch/sh/mm/pmb.c
588
data_val = __raw_readl(data);
arch/sh/mm/pmb.c
812
return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
arch/sh/mm/pmb.c
828
addr = __raw_readl(mk_pmb_addr(i));
arch/sh/mm/pmb.c
829
data = __raw_readl(mk_pmb_data(i));
arch/sh/mm/tlb-debugfs.c
100
val = __raw_readl(addr1 | (entry << MMU_TLB_ENTRY_SHIFT));
arch/sh/mm/tlb-debugfs.c
105
val = __raw_readl(addr2 | (entry << MMU_TLB_ENTRY_SHIFT));
arch/sh/mm/tlb-debugfs.c
109
val = __raw_readl(data1 | (entry << MMU_TLB_ENTRY_SHIFT));
arch/sh/mm/tlb-debugfs.c
113
val = __raw_readl(data2 | (entry << MMU_TLB_ENTRY_SHIFT));
arch/sh/mm/tlb-debugfs.c
48
mmucr = __raw_readl(MMUCR);
arch/sh/mm/tlb-pteaex.c
91
status = __raw_readl(MMUCR);
arch/sh/mm/tlb-sh3.c
90
status = __raw_readl(MMUCR);
arch/sh/mm/tlb-sh4.c
93
status = __raw_readl(MMUCR);
arch/sh/mm/tlb-urb.c
27
status = __raw_readl(MMUCR);
arch/sh/mm/tlb-urb.c
50
status = __raw_readl(MMUCR);
arch/sh/mm/tlb-urb.c
76
status = __raw_readl(MMUCR);
arch/sh/mm/tlbflush_32.c
134
__raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
arch/sparc/include/asm/io.h
17
#define readl_be(__addr) __raw_readl(__addr)
arch/sparc/include/asm/io_64.h
316
return __raw_readl(addr);
arch/sparc/include/asm/io_64.h
443
#define ioread32be __raw_readl
arch/sparc/include/asm/io_64.h
45
#define __raw_readl __raw_readl
arch/sparc/kernel/leon_pci_grpci1.c
49
#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
arch/sparc/kernel/leon_pci_grpci2.c
94
#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
arch/sparc/lib/PeeCeeI.c
152
*pi++ = __raw_readl(addr);
arch/sparc/lib/PeeCeeI.c
162
l = __raw_readl(addr);
arch/sparc/lib/PeeCeeI.c
166
l2 = __raw_readl(addr);
arch/sparc/lib/PeeCeeI.c
177
l = __raw_readl(addr);
arch/sparc/lib/PeeCeeI.c
183
l2 = __raw_readl(addr);
arch/sparc/lib/PeeCeeI.c
194
l = __raw_readl(addr);
arch/sparc/lib/PeeCeeI.c
198
l2 = __raw_readl(addr);
arch/xtensa/platforms/xtfpga/setup.c
93
freq = __raw_readl(base);
drivers/ata/ahci_brcm.c
104
return __raw_readl(addr);
drivers/ata/pata_imx.c
213
priv->ata_ctl = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
drivers/ata/pata_imx.c
92
val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
drivers/bcma/host_soc.c
82
*buf = (__force __le32)__raw_readl(addr);
drivers/bus/mips_cdmm.c
484
acsr = __raw_readl(cdmm + drb * CDMM_DRB_SIZE);
drivers/bus/mips_cdmm.c
531
acsr = __raw_readl(cdmm + drb * CDMM_DRB_SIZE);
drivers/cdrom/gdrom.c
392
__raw_readl(count);
drivers/char/hw_random/bcm2835-rng.c
49
return __raw_readl(priv->base + offset);
drivers/char/hw_random/ixp4xx-rng.c
31
*buffer = __raw_readl(rng_base);
drivers/char/hw_random/mxc-rnga.c
106
ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/mxc-rnga.c
110
osc = __raw_readl(mxc_rng->mem + RNGA_STATUS);
drivers/char/hw_random/mxc-rnga.c
117
ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/mxc-rnga.c
128
ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/mxc-rnga.c
68
int level = (__raw_readl(mxc_rng->mem + RNGA_STATUS) &
drivers/char/hw_random/mxc-rnga.c
84
*data = __raw_readl(mxc_rng->mem + RNGA_OUTPUT_FIFO);
drivers/char/hw_random/mxc-rnga.c
87
err = __raw_readl(mxc_rng->mem + RNGA_STATUS) & RNGA_STATUS_ERROR_INT;
drivers/char/hw_random/mxc-rnga.c
92
ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL);
drivers/char/hw_random/nomadik-rng.c
25
*(u16 *)data = __raw_readl(base + 8) & 0xffff;
drivers/char/hw_random/omap-rng.c
163
return __raw_readl(priv->base + priv->pdata->regs[reg]);
drivers/clk/bcm/clk-bcm63268-timer.c
138
return !(__raw_readl(reset->regs) & BIT(id));
drivers/clk/bcm/clk-bcm63268-timer.c
91
val = __raw_readl(reset->regs);
drivers/clk/imx/clk-imx35.c
94
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
drivers/clk/imx/clk-imx6sl.c
175
while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
drivers/clk/imx/clk-pllv2.c
118
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
drivers/clk/imx/clk-pllv2.c
119
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
drivers/clk/imx/clk-pllv2.c
120
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
drivers/clk/imx/clk-pllv2.c
121
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
drivers/clk/imx/clk-pllv2.c
170
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
drivers/clk/imx/clk-pllv2.c
210
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
drivers/clk/imx/clk-pllv2.c
215
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
drivers/clk/imx/clk-pllv2.c
237
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
drivers/clk/tegra/clk-dfll.c
1350
__raw_readl(td->i2c_controller_base + offs));
drivers/clk/tegra/clk-dfll.c
1355
__raw_readl(td->lut_base + offs));
drivers/clk/tegra/clk-dfll.c
333
return __raw_readl(td->base + offs);
drivers/clk/tegra/clk-dfll.c
351
return __raw_readl(td->i2c_base + offs);
drivers/clk/ti/clk-dra7-atl.c
69
return __raw_readl(cinfo->iobase + reg);
drivers/clocksource/arm_arch_timer_mmio.c
125
cnt_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4));
drivers/clocksource/arm_arch_timer_mmio.c
126
cnt_lo = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo));
drivers/clocksource/arm_arch_timer_mmio.c
127
tmp_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4));
drivers/clocksource/mxs_timer.c
227
timrot_major_version = __raw_readl(mxs_timrot_base +
drivers/clocksource/mxs_timer.c
88
return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
drivers/clocksource/timer-ixp4xx.c
102
val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
116
val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
150
val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
drivers/clocksource/timer-ixp4xx.c
69
return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
372
#define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
drivers/crypto/omap-aes.c
51
_read_ret = __raw_readl(dd->io_base + offset); \
drivers/crypto/omap-aes.c
59
return __raw_readl(dd->io_base + offset);
drivers/crypto/omap-des.c
171
_read_ret = __raw_readl(dd->io_base + offset); \
drivers/crypto/omap-des.c
179
return __raw_readl(dd->io_base + offset);
drivers/crypto/omap-sham.c
251
return __raw_readl(dd->io_base + offset);
drivers/crypto/s5p-sss.c
144
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
drivers/crypto/s5p-sss.c
594
return __raw_readl(dd->io_hash_base + offset);
drivers/dma/at_hdmac.c
298
__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
drivers/dma/at_hdmac.c
362
__raw_readl((atdma)->regs + AT_DMA_##name)
drivers/dma/imx-dma.c
243
return __raw_readl(imxdma->base + offset);
drivers/dma/mmp_tdma.c
307
reg = __raw_readl(tdmac->reg_base + TDSAR);
drivers/dma/mmp_tdma.c
310
reg = __raw_readl(tdmac->reg_base + TDDAR);
drivers/dma/sh/shdmac.c
118
return __raw_readl(sh_dc->base + shdev->chcr_offset);
drivers/dma/sh/shdmac.c
84
return __raw_readl(sh_dc->base + reg);
drivers/dma/sh/shdmac.c
92
return __raw_readl(addr);
drivers/dma/ti/cppi41.c
285
return __raw_readl(mem);
drivers/dma/ti/edma.c
302
return (unsigned int)__raw_readl(ecc->base + offset);
drivers/dma/txx9dmac.c
113
__raw_readl(&(__txx9dmac_regs(ddev)->name))
drivers/dma/txx9dmac.c
118
__raw_readl(&(__txx9dmac_regs32(ddev)->name))
drivers/dma/txx9dmac.c
40
__raw_readl(&(__dma_regs(dc)->name))
drivers/dma/txx9dmac.c
45
__raw_readl(&(__dma_regs32(dc)->name))
drivers/edac/cpc925_edac.c
327
mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET +
drivers/edac/cpc925_edac.c
329
mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET +
drivers/edac/cpc925_edac.c
387
apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET);
drivers/edac/cpc925_edac.c
394
mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET);
drivers/edac/cpc925_edac.c
529
apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET);
drivers/edac/cpc925_edac.c
533
mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET);
drivers/edac/cpc925_edac.c
536
mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET);
drivers/edac/cpc925_edac.c
560
__raw_readl(pdata->vbase + REG_APIMASK_OFFSET));
drivers/edac/cpc925_edac.c
564
__raw_readl(pdata->vbase + REG_MSCR_OFFSET));
drivers/edac/cpc925_edac.c
566
__raw_readl(pdata->vbase + REG_MSRSR_OFFSET));
drivers/edac/cpc925_edac.c
568
__raw_readl(pdata->vbase + REG_MSRER_OFFSET));
drivers/edac/cpc925_edac.c
570
__raw_readl(pdata->vbase + REG_MSPR_OFFSET));
drivers/edac/cpc925_edac.c
572
__raw_readl(pdata->vbase + REG_MCCR_OFFSET));
drivers/edac/cpc925_edac.c
574
__raw_readl(pdata->vbase + REG_MCRER_OFFSET));
drivers/edac/cpc925_edac.c
620
apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
drivers/edac/cpc925_edac.c
660
apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET);
drivers/edac/cpc925_edac.c
667
apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
drivers/edac/cpc925_edac.c
682
ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
drivers/edac/cpc925_edac.c
694
ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
drivers/edac/cpc925_edac.c
703
u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET);
drivers/edac/cpc925_edac.c
704
u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET);
drivers/edac/cpc925_edac.c
705
u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
drivers/edac/cpc925_edac.c
706
u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET);
drivers/edac/cpc925_edac.c
870
mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
drivers/edac/cpc925_edac.c
891
mbcr = __raw_readl(vbase + REG_MBCR_OFFSET);
drivers/firmware/tegra/bpmp-tegra210.c
41
return __raw_readl(priv->arb_sema + STA_OFFSET) & CH_MASK(index);
drivers/fpga/socfpga.c
148
return __raw_readl(priv->fpga_base_addr + reg_offset);
drivers/gpio/gpio-ixp4xx.c
149
val = __raw_readl(g->base + int_reg);
drivers/gpio/gpio-ixp4xx.c
156
val = __raw_readl(g->base + int_reg);
drivers/gpio/gpio-ixp4xx.c
161
val = __raw_readl(g->base + IXP4XX_REG_GPOE);
drivers/gpio/gpio-ixp4xx.c
260
val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
drivers/gpio/gpio-loongson1.c
31
__raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset),
drivers/gpio/gpio-loongson1.c
43
__raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset),
drivers/gpio/gpio-lpc32xx.c
170
return __raw_readl(group->reg_base + offset);
drivers/gpio/gpio-stp-xway.c
75
#define xway_stp_r32(m, reg) __raw_readl(m + reg)
drivers/gpio/gpio-tegra186.c
200
value = __raw_readl(secure + TEGRA186_GPIO_SCR);
drivers/gpio/gpio-xilinx.c
40
# define xgpio_readreg(offset) __raw_readl(offset)
drivers/gpu/drm/omapdrm/dss/dispc.c
363
return __raw_readl(dispc->base + idx);
drivers/gpu/drm/omapdrm/dss/dsi.c
112
return __raw_readl(base + idx.idx);
drivers/gpu/drm/omapdrm/dss/dss.c
103
return __raw_readl(dss->base + idx.idx);
drivers/gpu/drm/omapdrm/dss/hdmi.h
274
return __raw_readl(base_addr + idx);
drivers/gpu/drm/omapdrm/dss/venc.c
275
u32 l = __raw_readl(venc->base + idx);
drivers/hwtracing/coresight/coresight-ctcu-core.c
25
#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
drivers/hwtracing/intel_th/msu.c
1682
reg = __raw_readl(msc->reg_base + REG_MSU_MSC0STS);
drivers/i2c/busses/i2c-au1550.c
52
return __raw_readl(a->psc_base + r);
drivers/i2c/busses/i2c-iop3xx.c
111
u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
233
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
259
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
281
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
297
*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
395
unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-iop3xx.c
95
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
drivers/i2c/busses/i2c-sh7760.c
109
return __raw_readl((unsigned long)cam->iobase + reg);
drivers/iio/adc/lpc32xx_adc.c
138
st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
drivers/iio/adc/spear_adc.c
128
return __raw_readl(&st->adc_base_spear6xx->average.msb) &
drivers/iio/adc/spear_adc.c
131
return __raw_readl(&st->adc_base_spear3xx->average) &
drivers/infiniband/hw/mthca/mthca_cmd.c
367
__raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
drivers/infiniband/hw/mthca/mthca_cmd.c
369
__raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
drivers/infiniband/hw/mthca/mthca_cmd.c
375
status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
drivers/input/keyboard/ep93xx_keypad.c
86
status = __raw_readl(keypad->mmio_base + KEY_REG);
drivers/input/keyboard/goldfish_events.c
126
keymapnamelen = __raw_readl(addr + REG_LEN);
drivers/input/keyboard/goldfish_events.c
41
type = __raw_readl(edev->addr + REG_READ);
drivers/input/keyboard/goldfish_events.c
42
code = __raw_readl(edev->addr + REG_READ);
drivers/input/keyboard/goldfish_events.c
43
value = __raw_readl(edev->addr + REG_READ);
drivers/input/keyboard/goldfish_events.c
60
size = __raw_readl(addr + REG_LEN) * 8;
drivers/input/keyboard/goldfish_events.c
83
count = __raw_readl(addr + REG_LEN) / sizeof(val);
drivers/input/keyboard/goldfish_events.c
94
val[j] = __raw_readl(edev->addr + REG_DATA + offset);
drivers/input/keyboard/omap4-keypad.c
104
return __raw_readl(keypad_data->base +
drivers/input/keyboard/omap4-keypad.c
290
rev = __raw_readl(keypad_data->base + OMAP4_KBD_REVISION);
drivers/input/keyboard/omap4-keypad.c
92
return __raw_readl(keypad_data->base +
drivers/input/keyboard/pxa27x_keypad.c
100
#define keypad_readl(off) __raw_readl(keypad->mmio_base + (off))
drivers/input/mouse/rpcmouse.c
42
b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70);
drivers/input/touchscreen/lpc32xx_ts.c
60
__raw_readl((dev)->tsc_base + (reg))
drivers/iommu/omap-iommu.h
256
return __raw_readl(obj->regbase + offs);
drivers/irqchip/irq-ath79-misc.c
43
pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
drivers/irqchip/irq-ath79-misc.c
44
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
68
t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
72
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
81
t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
85
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
drivers/irqchip/irq-ath79-misc.c
94
t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
drivers/irqchip/irq-ath79-misc.c
98
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
drivers/irqchip/irq-bcm6345-l1.c
130
pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
drivers/irqchip/irq-bcm6345-l1.c
131
pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
drivers/irqchip/irq-ixp4xx.c
102
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
drivers/irqchip/irq-ixp4xx.c
114
status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
drivers/irqchip/irq-ixp4xx.c
122
status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
drivers/irqchip/irq-ixp4xx.c
78
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
drivers/irqchip/irq-ixp4xx.c
82
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
drivers/irqchip/irq-ixp4xx.c
98
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
drivers/irqchip/irq-mxs.c
137
irqnr = __raw_readl(icoll_priv.stat);
drivers/mailbox/omap-mailbox.c
98
return __raw_readl(mdev->mbox_base + ofs);
drivers/media/pci/cx18/cx18-io.h
26
return __raw_readl(addr);
drivers/media/platform/intel/pxa_camera.c
1010
camera_status = __raw_readl(pcdev->base + CISR);
drivers/media/platform/intel/pxa_camera.c
1158
__raw_readl(pcdev->base + CISR));
drivers/media/platform/intel/pxa_camera.c
1161
cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
drivers/media/platform/intel/pxa_camera.c
1177
status = __raw_readl(pcdev->base + CISR);
drivers/media/platform/intel/pxa_camera.c
1187
cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
drivers/media/platform/intel/pxa_camera.c
1239
cicr0 = __raw_readl(pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
1735
reg->val = __raw_readl(pcdev->base + reg->reg);
drivers/media/platform/intel/pxa_camera.c
2161
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
drivers/media/platform/intel/pxa_camera.c
2162
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
drivers/media/platform/intel/pxa_camera.c
2163
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
drivers/media/platform/intel/pxa_camera.c
2164
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
drivers/media/platform/intel/pxa_camera.c
2165
pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
drivers/media/platform/intel/pxa_camera.c
921
__raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
drivers/media/platform/intel/pxa_camera.c
923
cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
drivers/media/platform/intel/pxa_camera.c
934
cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
drivers/media/platform/renesas/sh_vou.c
114
return __raw_readl(vou_dev->base + reg);
drivers/media/platform/renesas/sh_vou.c
120
u32 old = __raw_readl(vou_dev->base + reg);
drivers/media/platform/ti/omap3isp/isp.h
287
return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
drivers/media/rc/mtk-cir.c
175
tmp = __raw_readl(ir->base + reg);
drivers/media/rc/mtk-cir.c
187
return __raw_readl(ir->base + reg);
drivers/memory/renesas-rpc-if.c
806
*(u32 *)to = __raw_readl(from);
drivers/memory/ti-emif-pm.c
251
__raw_readl((void __iomem *)emif_instance->ti_emif_sram_virt);
drivers/memstick/host/jmb38x_ms.c
172
*(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
drivers/memstick/host/r592.c
71
u32 value = __raw_readl(dev->mmio + address);
drivers/memstick/host/tifm_ms.c
101
*(unsigned int *)(buf + off) = __raw_readl(sock->addr
drivers/misc/genwqe/card_utils.c
127
return be32_to_cpu((__force __be32)__raw_readl(cd->mmio + byte_offs));
drivers/mmc/host/atmel-mci.c
170
__raw_readl((port)->regs + reg)
drivers/mmc/host/au1xmmc.c
167
u32 val = __raw_readl(HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
175
u32 val = __raw_readl(HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
190
u32 val = __raw_readl(HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
203
config2 = __raw_readl(HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
310
while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
drivers/mmc/host/au1xmmc.c
330
status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
334
status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
371
u32 status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
403
status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
464
status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
486
val = __raw_readl(HOST_RXPORT(host));
drivers/mmc/host/au1xmmc.c
531
r[0] = __raw_readl(host->iobase + SD_RESP3);
drivers/mmc/host/au1xmmc.c
532
r[1] = __raw_readl(host->iobase + SD_RESP2);
drivers/mmc/host/au1xmmc.c
533
r[2] = __raw_readl(host->iobase + SD_RESP1);
drivers/mmc/host/au1xmmc.c
534
r[3] = __raw_readl(host->iobase + SD_RESP0);
drivers/mmc/host/au1xmmc.c
553
cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
drivers/mmc/host/au1xmmc.c
580
status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/au1xmmc.c
593
config = __raw_readl(HOST_CONFIG(host));
drivers/mmc/host/au1xmmc.c
757
config2 = __raw_readl(HOST_CONFIG2(host));
drivers/mmc/host/au1xmmc.c
783
status = __raw_readl(HOST_STATUS(host));
drivers/mmc/host/dw_mmc.h
470
#define mci_fifo_readl(__reg) __raw_readl(__reg)
drivers/mmc/host/omap_hsmmc.c
159
__raw_readl((base) + OMAP_HSMMC_##reg)
drivers/mtd/nand/raw/au1550nd.c
126
staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
drivers/mtd/nand/raw/brcmnand/brcmnand.c
862
return __raw_readl(ctrl->nand_fc + word * 4);
drivers/mtd/nand/raw/brcmnand/brcmnand.h
62
return __raw_readl(addr);
drivers/mtd/nand/raw/davinci_nand.c
142
return __raw_readl(info->base + offset);
drivers/mtd/nand/raw/mxc_nand.c
199
*t++ = __raw_readl(s++);
drivers/mtd/nand/raw/txx9ndfmc.c
127
*buf++ = __raw_readl(ndfdtr);
drivers/mtd/nand/raw/txx9ndfmc.c
92
return __raw_readl(ndregaddr(dev, reg));
drivers/mtd/nand/raw/vf610_nfc.c
236
u32 val = swab32(__raw_readl(src + i));
drivers/net/can/ti_hecc.c
214
return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
drivers/net/can/ti_hecc.c
225
return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
drivers/net/can/ti_hecc.c
235
return __raw_readl(priv->base + reg);
drivers/net/ethernet/aeroflex/greth.c
162
return be32_to_cpu(__raw_readl(bd));
drivers/net/ethernet/aeroflex/greth.c
81
#define GRETH_REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
drivers/net/ethernet/broadcom/genet/bcmgenet.c
82
return __raw_readl(offset);
drivers/net/ethernet/broadcom/genet/bcmgenet.h
703
return __raw_readl(priv->base + offset + off); \
drivers/net/ethernet/cadence/macb_main.c
197
return __raw_readl(bp->regs + offset);
drivers/net/ethernet/cadence/macb_main.c
224
value = __raw_readl(addr + MACB_NCR);
drivers/net/ethernet/cadence/macb_main.c
237
id = __raw_readl(addr + MACB_MID);
drivers/net/ethernet/cadence/macb_main.c
4473
queue_mask |= __raw_readl(mem + GEM_DCFG6) & 0xFF;
drivers/net/ethernet/calxeda/xgmac.c
1370
intr_status = __raw_readl(ioaddr + XGMAC_INT_STAT);
drivers/net/ethernet/calxeda/xgmac.c
1387
intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS);
drivers/net/ethernet/calxeda/xgmac.c
1388
intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/cirrus/ep93xx_eth.c
178
#define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
75
upper = __raw_readl(hw->port + ENETC4_PSIPMAR0(si));
drivers/net/ethernet/freescale/enetc/enetc4_pf.c
76
lower = __raw_readl(hw->port + ENETC4_PSIPMAR1(si));
drivers/net/ethernet/freescale/enetc/enetc_hw.h
716
upper = __raw_readl(hw->reg + ENETC_SIPMAR0);
drivers/net/ethernet/freescale/enetc/enetc_hw.h
717
lower = __raw_readl(hw->reg + ENETC_SIPMAR1);
drivers/net/ethernet/freescale/enetc/enetc_pf.c
17
u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
drivers/net/ethernet/freescale/fs_enet/fs_enet.h
200
#define __cbd_in32(addr) __raw_readl(addr)
drivers/net/ethernet/freescale/fs_enet/mac-fec.c
46
#define __fs_in32(addr) __raw_readl(addr)
drivers/net/ethernet/freescale/fs_enet/mac-scc.c
43
#define __fs_in32(addr) __raw_readl(addr)
drivers/net/ethernet/lantiq_xrx200.c
95
return __raw_readl(priv->pmac_reg + offset);
drivers/net/ethernet/mediatek/mtk_eth_soc.c
296
return __raw_readl(eth->base + reg);
drivers/net/ethernet/mediatek/mtk_eth_soc.c
3219
ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
drivers/net/ethernet/mellanox/mlx4/cmd.c
638
__raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
drivers/net/ethernet/mellanox/mlx4/cmd.c
640
__raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
drivers/net/ethernet/mellanox/mlx4/cmd.c
642
__raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
966
*wrptr32++ = __raw_readl(rdptr32++);
drivers/net/ethernet/sfc/falcon/io.h
173
value->u32[0] = (__force __le32)__raw_readl(membase + addr);
drivers/net/ethernet/sfc/falcon/io.h
174
value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
drivers/net/ethernet/sfc/falcon/io.h
85
return (__force __le32)__raw_readl(efx->membase + reg);
drivers/net/ethernet/sfc/io.h
78
return (__force __le32)__raw_readl(efx->membase + reg);
drivers/net/ethernet/sfc/siena/io.h
102
return (__force __le32)__raw_readl(efx->membase + reg);
drivers/net/ethernet/sfc/siena/io.h
190
value->u32[0] = (__force __le32)__raw_readl(membase + addr);
drivers/net/ethernet/sfc/siena/io.h
191
value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
drivers/net/ethernet/xscale/ixp4xx_eth.c
324
val = __raw_readl(®s->channel[ch].ch_event);
drivers/net/ethernet/xscale/ixp4xx_eth.c
329
lo = __raw_readl(®s->channel[ch].src_uuid_lo);
drivers/net/ethernet/xscale/ixp4xx_eth.c
330
hi = __raw_readl(®s->channel[ch].src_uuid_hi);
drivers/net/ethernet/xscale/ixp4xx_eth.c
338
lo = __raw_readl(®s->channel[ch].rx_snap_lo);
drivers/net/ethernet/xscale/ixp4xx_eth.c
339
hi = __raw_readl(®s->channel[ch].rx_snap_hi);
drivers/net/ethernet/xscale/ixp4xx_eth.c
374
val = __raw_readl(®s->channel[ch].ch_event);
drivers/net/ethernet/xscale/ixp4xx_eth.c
384
lo = __raw_readl(®s->channel[ch].tx_snap_lo);
drivers/net/ethernet/xscale/ixp4xx_eth.c
385
hi = __raw_readl(®s->channel[ch].tx_snap_hi);
drivers/net/ethernet/xscale/ixp4xx_eth.c
481
if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
drivers/net/ethernet/xscale/ixp4xx_eth.c
496
(__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
drivers/net/ethernet/xscale/ixp4xx_eth.c
515
if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
drivers/net/ethernet/xscale/ixp4xx_eth.c
523
return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
drivers/net/ethernet/xscale/ixp4xx_eth.c
524
((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
drivers/net/ethernet/xscale/ptp_ixp46x.c
46
lo = __raw_readl(®s->systime_lo);
drivers/net/ethernet/xscale/ptp_ixp46x.c
47
hi = __raw_readl(®s->systime_hi);
drivers/net/ethernet/xscale/ptp_ixp46x.c
79
val = __raw_readl(®s->event);
drivers/net/ethernet/xscale/ptp_ixp46x.c
84
hi = __raw_readl(®s->asms_hi);
drivers/net/ethernet/xscale/ptp_ixp46x.c
85
lo = __raw_readl(®s->asms_lo);
drivers/net/ethernet/xscale/ptp_ixp46x.c
98
hi = __raw_readl(®s->amms_hi);
drivers/net/ethernet/xscale/ptp_ixp46x.c
99
lo = __raw_readl(®s->amms_lo);
drivers/net/mdio/mdio-bcm-unimac.c
53
return __raw_readl(priv->base + offset);
drivers/net/wireless/ath/wil6210/main.c
148
*d++ = __raw_readl(s++);
drivers/net/wireless/ath/wil6210/main.c
152
u32 tmp = __raw_readl(s);
drivers/net/wireless/intersil/p54/p54pci.h
86
#define P54P_READ(r) (__force __le32)__raw_readl(&priv->map->r)
drivers/parisc/ccio-dma.c
91
#define READ_U32(addr) __raw_readl(addr)
drivers/parisc/dino.c
221
__raw_readl(base_addr + DINO_CONFIG_DATA);
drivers/parisc/dino.c
322
__raw_readl(dino_dev->hba.base_addr+DINO_IPR);
drivers/parisc/dino.c
337
tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
drivers/parisc/dino.c
397
mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
drivers/parisc/dino.c
419
mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
drivers/parisc/dino.c
710
status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
drivers/parisc/dino.c
777
io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
drivers/parisc/dino.c
887
__raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
drivers/parisc/lba_pci.c
130
#define READ_U32(addr) __raw_readl(addr)
drivers/pci/controller/pci-ixp4xx.c
126
return __raw_readl(p->base + reg);
drivers/phy/broadcom/phy-bcm63xx-usbh.c
232
return __raw_readl(usbh->base + usbh->variant->regs[reg]);
drivers/phy/broadcom/phy-brcm-usb-init.h
92
return __raw_readl(addr);
drivers/phy/ti/phy-omap-usb2.c
83
return __raw_readl(addr + offset);
drivers/phy/ti/phy-ti-pipe3.c
291
return __raw_readl(addr + offset);
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
61
tmp = __raw_readl(clk_base + S5P_OTHERS);
drivers/platform/x86/intel_scu_ipc.c
216
return __raw_readl(scu->ipc_base + IPC_STATUS);
drivers/pmdomain/bcm/bcm63xx-power.c
47
*is_on = !(__raw_readl(power->base) & pmd->mask);
drivers/pmdomain/bcm/bcm63xx-power.c
62
val = __raw_readl(power->base);
drivers/ptp/ptp_ines.c
103
#define ines_read32(s, r) __raw_readl((void __iomem *)&s->regs->r)
drivers/pwm/pwm-brcmstb.c
63
return __raw_readl(p->base + offset);
drivers/reset/reset-bcm6345.c
39
val = __raw_readl(bcm6345_reset->base);
drivers/reset/reset-bcm6345.c
86
return !(__raw_readl(bcm6345_reset->base) & BIT(id));
drivers/rtc/rtc-ds1286.c
27
return __raw_readl(&priv->rtcregs[reg]) & 0xff;
drivers/rtc/rtc-imxdi.c
334
return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));
drivers/rtc/rtc-imxdi.c
348
dcr = __raw_readl(imxdi->ioaddr + DCR);
drivers/rtc/rtc-lpc32xx.c
43
__raw_readl((dev)->rtc_base + (reg))
drivers/rtc/rtc-ma35d1.c
62
return __raw_readl(p->rtc_reg + offset);
drivers/rtc/rtc-msm6242.c
82
return __raw_readl(&priv->regs[reg]) & 0xf;
drivers/rtc/rtc-pxa.c
69
__raw_readl((pxa_rtc)->base + (reg))
drivers/rtc/rtc-rp5c01.c
73
return __raw_readl(&priv->regs[reg]) & 0xf;
drivers/scsi/ncr53c8xx.h
274
#define readl_l2b __raw_readl
drivers/scsi/ncr53c8xx.h
278
#define readl_raw __raw_readl
drivers/scsi/zalon.c
100
while (!(__raw_readl(zalon + IO_MODULE_IO_STATUS) & IOSTATUS_RY))
drivers/scsi/zalon.c
106
zalon_vers = (__raw_readl(zalon + IO_MODULE_II_CDATA) >> 24) & 0x07;
drivers/sh/clk/cpg.c
402
value = __raw_readl(clk->mapping->base);
drivers/sh/clk/cpg.c
425
value = __raw_readl(clk->mapping->base) >> 16;
drivers/sh/intc/access.c
119
(void)__raw_readl(ptr); /* Defeat write posting */
drivers/sh/intc/access.c
158
value = intc_set_field_from_handle(__raw_readl(ptr), data, h);
drivers/sh/intc/access.c
160
(void)__raw_readl(ptr); /* Defeat write posting */
drivers/sh/intc/access.c
93
return intc_get_field_from_handle(__raw_readl(ptr), h);
drivers/sh/intc/chip.c
107
__raw_readl(addr);
drivers/sh/intc/userimask.c
26
return sprintf(buf, "%d\n", (__raw_readl(uimask) >> 4) & 0xf);
drivers/sh/maple/maple.c
134
return (__raw_readl(MAPLE_STATE) & 1) == 0;
drivers/soc/bcm/brcmstb/pm/pm-mips.c
138
tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
141
(void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
144
(void)__raw_readl(base + AON_CTRL_PM_INITIATE);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
165
(void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
169
(void)__raw_readl(base + AON_CTRL_PM_CTRL);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
173
(void)__raw_readl(base + AON_CTRL_PM_CTRL);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
194
tmp = __raw_readl(ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL);
drivers/soc/bcm/brcmstb/pm/pm-mips.c
202
tmp = __raw_readl(ctrl.memcs[i].ddr_phy_base +
drivers/soc/bcm/brcmstb/pm/pm-mips.c
219
s3_context.memc0_rts[i] = __raw_readl(memc_arb_base);
drivers/soc/ixp4xx/ixp4xx-npe.c
167
return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
drivers/soc/ixp4xx/ixp4xx-npe.c
184
__raw_readl(&npe->regs->exec_data);
drivers/soc/ixp4xx/ixp4xx-npe.c
185
__raw_readl(&npe->regs->exec_data);
drivers/soc/ixp4xx/ixp4xx-npe.c
186
return __raw_readl(&npe->regs->exec_data);
drivers/soc/ixp4xx/ixp4xx-npe.c
239
wc = __raw_readl(&npe->regs->watch_count);
drivers/soc/ixp4xx/ixp4xx-npe.c
246
if (wc != __raw_readl(&npe->regs->watch_count))
drivers/soc/ixp4xx/ixp4xx-npe.c
292
ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
drivers/soc/ixp4xx/ixp4xx-npe.c
300
exec_count = __raw_readl(&npe->regs->exec_count);
drivers/soc/ixp4xx/ixp4xx-npe.c
309
while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
drivers/soc/ixp4xx/ixp4xx-npe.c
311
while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
drivers/soc/ixp4xx/ixp4xx-npe.c
314
__raw_readl(&npe->regs->in_out_fifo));
drivers/soc/ixp4xx/ixp4xx-npe.c
316
while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
drivers/soc/ixp4xx/ixp4xx-npe.c
420
if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
drivers/soc/ixp4xx/ixp4xx-npe.c
427
if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
drivers/soc/ixp4xx/ixp4xx-npe.c
435
(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
drivers/soc/ixp4xx/ixp4xx-npe.c
459
if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
drivers/soc/ixp4xx/ixp4xx-npe.c
460
recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
101
return (__raw_readl(&qmgr_regs->statf_h) >>
drivers/soc/ixp4xx/ixp4xx-qmgr.c
129
__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),
drivers/soc/ixp4xx/ixp4xx-qmgr.c
149
en_bitmap = __raw_readl(&qmgr_regs->irqen[0]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
153
src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
154
stat = __raw_readl(&qmgr_regs->stat1[i >> 3]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
174
req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) &
drivers/soc/ixp4xx/ixp4xx-qmgr.c
175
__raw_readl(&qmgr_regs->statne_h);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
189
u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
212
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
drivers/soc/ixp4xx/ixp4xx-qmgr.c
224
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
drivers/soc/ixp4xx/ixp4xx-qmgr.c
287
if (__raw_readl(&qmgr_regs->sram[queue])) {
drivers/soc/ixp4xx/ixp4xx-qmgr.c
336
cfg = __raw_readl(&qmgr_regs->sram[queue]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
43
val = __raw_readl(&qmgr_regs->acc[queue][0]);
drivers/soc/ixp4xx/ixp4xx-qmgr.c
55
return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
drivers/soc/ixp4xx/ixp4xx-qmgr.c
62
return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
drivers/soc/ixp4xx/ixp4xx-qmgr.c
87
return (__raw_readl(&qmgr_regs->statne_h) >>
drivers/soc/pxa/mfp.c
130
__raw_readl(mfpr_mmio_base + (off))
drivers/soc/pxa/mfp.c
142
#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback)
drivers/soc/ti/pm33xx.c
163
i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
drivers/soc/ti/smartreflex.c
63
reg_val = __raw_readl(sr->base + offset);
drivers/soc/ti/smartreflex.c
75
return __raw_readl(sr->base + offset);
drivers/spi/spi-bcm63xx-hsspi.c
250
reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0));
drivers/spi/spi-bcm63xx-hsspi.c
456
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcm63xx-hsspi.c
476
reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
drivers/spi/spi-bcm63xx-hsspi.c
485
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcm63xx-hsspi.c
572
reg = __raw_readl(bs->regs +
drivers/spi/spi-bcm63xx-hsspi.c
583
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcm63xx-hsspi.c
731
if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
drivers/spi/spi-bcm63xx-hsspi.c
854
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcmbca-hsspi.c
182
reg = __raw_readl(bs->spim_ctrl);
drivers/spi/spi-bcmbca-hsspi.c
203
reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
drivers/spi/spi-bcmbca-hsspi.c
212
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcmbca-hsspi.c
234
reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0));
drivers/spi/spi-bcmbca-hsspi.c
334
reg = __raw_readl(bs->regs +
drivers/spi/spi-bcmbca-hsspi.c
345
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-bcmbca-hsspi.c
358
reg = __raw_readl(bs->spim_ctrl);
drivers/spi/spi-bcmbca-hsspi.c
421
if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
drivers/spi/spi-bcmbca-hsspi.c
529
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
drivers/spi/spi-dw.h
207
return __raw_readl(dws->regs + offset);
drivers/spi/spi-hisi-sfc-v3xx.c
218
val = __raw_readl(from);
drivers/spi/spi-hisi-sfc-v3xx.c
225
u32 val = __raw_readl(from);
drivers/spi/spi-lantiq-ssc.c
191
return __raw_readl(spi->regbase + reg);
drivers/spi/spi-lantiq-ssc.c
203
u32 val = __raw_readl(spi->regbase + reg);
drivers/spi/spi-rb4xx.c
37
return __raw_readl(rbspi->base + reg);
drivers/spi/spi-xtensa-xtfpga.c
40
return __raw_readl(spi->regs + addr);
drivers/spmi/spmi-pmic-arb.c
288
u32 data = __raw_readl(pmic_arb->rd_base + reg);
drivers/ssb/host_soc.c
77
*buf = (__force __le32)__raw_readl(addr);
drivers/thermal/broadcom/brcmstb_thermal.c
159
val = __raw_readl(priv->tmon_base + AVS_TMON_STATUS);
drivers/thermal/broadcom/brcmstb_thermal.c
179
u32 val = __raw_readl(priv->tmon_base + trip->enable_offs);
drivers/thermal/broadcom/brcmstb_thermal.c
195
u32 val = __raw_readl(priv->tmon_base + trip->reg_offs);
drivers/thermal/broadcom/brcmstb_thermal.c
219
orig = __raw_readl(priv->tmon_base + trip->reg_offs);
drivers/thermal/broadcom/brcmstb_thermal.c
229
val = __raw_readl(priv->tmon_base + AVS_TMON_TEMP_INT_CODE);
drivers/tty/mips_ejtag_fdc.c
1197
stat = __raw_readl(regs + REG_FDSTAT);
drivers/tty/mips_ejtag_fdc.c
1206
data = __raw_readl(regs + REG_FDRX);
drivers/tty/mips_ejtag_fdc.c
1236
while (__raw_readl(regs + REG_FDSTAT) & REG_FDSTAT_TXF)
drivers/tty/mips_ejtag_fdc.c
180
return __raw_readl(priv->reg + offs);
drivers/tty/mips_ejtag_fdc.c
348
while (__raw_readl(regs + REG_FDSTAT) & REG_FDSTAT_TXF)
drivers/tty/serial/8250/8250_rt288x.c
42
return __raw_readl(p->membase + (offset << p->regshift));
drivers/tty/serial/8250/8250_rt288x.c
57
return __raw_readl(up->port.membase + RT288X_DL);
drivers/tty/serial/apbuart.h
53
#define UART_GET_CHAR(port) (__raw_readl(APBBASE_DATA_P(port)))
drivers/tty/serial/apbuart.h
55
#define UART_GET_STATUS(port) (__raw_readl(APBBASE_STATUS_P(port)))
drivers/tty/serial/apbuart.h
57
#define UART_GET_CTRL(port) (__raw_readl(APBBASE_CTRL_P(port)))
drivers/tty/serial/apbuart.h
59
#define UART_GET_SCAL(port) (__raw_readl(APBBASE_SCALAR_P(port)))
drivers/tty/serial/atmel_serial.c
210
return __raw_readl(port->membase + reg);
drivers/tty/serial/bcm63xx_uart.c
76
return __raw_readl(port->membase + offset);
drivers/tty/serial/lantiq.c
125
u32 tmp = __raw_readl(reg);
drivers/tty/serial/lantiq.c
144
u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT);
drivers/tty/serial/lantiq.c
176
fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
drivers/tty/serial/lantiq.c
181
rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
drivers/tty/serial/lantiq.c
305
status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
drivers/tty/serial/mux.c
213
data = __raw_readl(port->membase + IO_DATA_REG_OFFSET);
drivers/tty/serial/mux.c
64
#define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
drivers/tty/serial/pic32_uart.c
86
return __raw_readl(sport->port.membase + reg);
drivers/tty/serial/sa1100.c
45
#define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
drivers/tty/serial/sa1100.c
46
#define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
drivers/tty/serial/sa1100.c
47
#define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
drivers/tty/serial/sa1100.c
48
#define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
drivers/tty/serial/sa1100.c
49
#define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
drivers/tty/serial/sa1100.c
50
#define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
drivers/tty/serial/sa1100.c
51
#define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
drivers/tty/serial/serial_txx9.c
163
return __raw_readl(up->membase + offset);
drivers/usb/gadget/udc/aspeed-vhub/vhub.h
513
(void)__raw_readl((void __iomem *)addr);
drivers/usb/gadget/udc/at91_udc.c
1010
u32 csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
1035
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
1096
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
1189
if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL)
drivers/usb/gadget/udc/at91_udc.c
119
csr = __raw_readl(ep->creg);
drivers/usb/gadget/udc/at91_udc.c
1211
tmp = __raw_readl(ep->creg);
drivers/usb/gadget/udc/at91_udc.c
1234
tmp = __raw_readl(ep->creg);
drivers/usb/gadget/udc/at91_udc.c
1278
u32 csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
1288
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
1356
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
327
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
375
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
389
u32 csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
411
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
675
tmp = __raw_readl(ep->creg);
drivers/usb/gadget/udc/at91_udc.c
752
csr = __raw_readl(creg);
drivers/usb/gadget/udc/at91_udc.c
91
__raw_readl((udc)->udp_baseaddr + (reg))
drivers/usb/gadget/udc/fsl_udc_core.c
242
ctrl = __raw_readl(&usb_sys_regs->control);
drivers/usb/gadget/udc/fsl_udc_core.c
258
ctrl = __raw_readl(&usb_sys_regs->control);
drivers/usb/gadget/udc/fsl_udc_core.c
327
ctrl = __raw_readl(&usb_sys_regs->control);
drivers/usb/gadget/udc/pxa27x_udc.h
181
__raw_readl((ep)->dev->regs + ofs_##reg(ep))
drivers/usb/gadget/udc/pxa27x_udc.h
189
__raw_readl((dev)->regs + (reg))
drivers/usb/host/ehci.h
753
#define readl_be(addr) __raw_readl((__force unsigned *)addr)
drivers/usb/host/ohci-nxp.c
126
tmp = __raw_readl(usb_otg_stat_control) | HOST_EN;
drivers/usb/host/ohci-nxp.c
143
tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN;
drivers/usb/host/ohci-pxa27x.c
139
uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
drivers/usb/host/ohci-pxa27x.c
140
uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
drivers/usb/host/ohci-pxa27x.c
220
uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
221
uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
drivers/usb/host/ohci-pxa27x.c
259
uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
drivers/usb/host/ohci-pxa27x.c
280
uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
drivers/usb/host/ohci-pxa27x.c
283
while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
drivers/usb/host/ohci-pxa27x.c
296
uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
drivers/usb/host/ohci-pxa27x.c
318
uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
drivers/usb/isp1760/isp1760-hcd.c
338
*dst = __raw_readl(src);
drivers/usb/isp1760/isp1760-hcd.c
354
val = __raw_readl(src);
drivers/usb/musb/musb_core.c
421
u32 data = __raw_readl(addr + offset);
drivers/usb/phy/phy-fsl-usb.c
928
temp = __raw_readl(&p_otg->dr_mem_map->control);
drivers/video/fbdev/atmel_lcdfb.c
69
#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
drivers/video/fbdev/ep93xx-fb.c
125
return __raw_readl(fbi->mmio_base + off);
drivers/video/fbdev/grvga.c
483
__raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */
drivers/video/fbdev/mb862xx/mb862xxfb.h
105
#define gdc_read __raw_readl
drivers/video/fbdev/nvidia/nv_local.h
67
#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
258
return __raw_readl(dispc.base + idx);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
461
return __raw_readl(base + idx.idx);
drivers/video/fbdev/omap2/omapfb/dss/dss.c
121
return __raw_readl(dss.base + idx.idx);
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
255
return __raw_readl(base_addr + idx);
drivers/video/fbdev/omap2/omapfb/dss/venc.c
267
u32 l = __raw_readl(venc.base + idx);
drivers/video/fbdev/pxa3xx-gcu.c
106
return __raw_readl(priv->mmio_base + off);
drivers/video/fbdev/pxafb.c
99
return __raw_readl(fbi->mmio_base + off);
drivers/video/fbdev/riva/riva_hw.h
83
#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
drivers/w1/masters/omap_hdq.c
64
return __raw_readl(hdq_data->hdq_base + offset);
drivers/w1/masters/omap_hdq.c
75
u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
drivers/watchdog/bcm7038_wdt.c
52
return __raw_readl(addr);
drivers/watchdog/ixp4xx_wdt.c
174
if (__raw_readl(iwdt->base + IXP4XX_OSST_OFFSET) &
drivers/watchdog/lantiq_wdt.c
70
return __raw_readl(priv->membase + offset);
drivers/watchdog/m54xx_wdt.c
48
gms0 = __raw_readl(MCF_GPT_GMS0);
drivers/watchdog/m54xx_wdt.c
66
gms0 = __raw_readl(MCF_GPT_GMS0);
drivers/watchdog/m54xx_wdt.c
75
gms0 = __raw_readl(MCF_GPT_GMS0);
drivers/watchdog/txx9wdt.c
68
__raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE,
include/asm-generic/io.h
131
#ifndef __raw_readl
include/asm-generic/io.h
132
#define __raw_readl __raw_readl
include/asm-generic/io.h
231
val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
include/asm-generic/io.h
359
val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
include/asm-generic/io.h
474
u32 x = __raw_readl(addr);
include/asm-generic/io.h
619
val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
include/asm-generic/logic_io.h
45
#define __raw_readl __raw_readl
include/asm-generic/logic_io.h
46
u32 __raw_readl(const volatile void __iomem *addr);
include/asm-generic/video.h
63
return __raw_readl(addr);
include/linux/atmel-ssc.h
332
#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
include/linux/mtd/doc2000.h
83
return __raw_readl(addr + reg);
include/linux/mtd/map.h
400
r.x[0] = __raw_readl(map->virt + ofs);
include/linux/platform_data/sh_mmcif.h
81
return __raw_readl(addr + reg);
include/linux/pxa2xx_ssp.h
272
return __raw_readl(dev->mmio_base + reg);
lib/iomap.c
329
u32 data = __raw_readl(addr);
lib/iomap_copy.c
49
*dst++ = __raw_readl(src++);
lib/iomem_copy.c
75
long val = __raw_readl(src);
sound/atmel/ac97c.c
62
__raw_readl((chip)->regs + AC97C_##reg)
sound/mips/hal2.c
94
return __raw_readl(reg);
sound/parisc/harmony.c
97
return __raw_readl(h->iobase + r);
sound/pci/mixart/mixart_hwdep.h
16
#define readl_be(x) be32_to_cpu((__force __be32)__raw_readl(x))
sound/pci/mixart/mixart_hwdep.h
24
#define readl_le(x) le32_to_cpu((__force __le32)__raw_readl(x))
sound/soc/atmel/atmel-pcm.h
70
#define ssc_readx(base, reg) (__raw_readl((base) + (reg)))
sound/soc/au1x/ac97c.c
74
return __raw_readl(ctx->mmio + reg);
sound/soc/au1x/i2sc.c
72
return __raw_readl(ctx->mmio + reg);
sound/soc/au1x/psc-ac97.c
132
if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
sound/soc/au1x/psc-ac97.c
179
while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
sound/soc/au1x/psc-ac97.c
193
while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
sound/soc/au1x/psc-ac97.c
217
r = ro = __raw_readl(AC97_CFG(pscdata));
sound/soc/au1x/psc-ac97.c
218
stat = __raw_readl(AC97_STAT(pscdata));
sound/soc/au1x/psc-ac97.c
256
while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
sound/soc/au1x/psc-ac97.c
272
while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
sound/soc/au1x/psc-ac97.c
309
while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
sound/soc/au1x/psc-ac97.c
396
sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
sound/soc/au1x/psc-ac97.c
444
wd->pm[0] = __raw_readl(PSC_SEL(wd));
sound/soc/au1x/psc-ac97.c
92
if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
sound/soc/au1x/psc-ac97.c
96
data = __raw_readl(AC97_CDC(pscdata));
sound/soc/au1x/psc-i2s.c
120
stat = __raw_readl(I2S_STAT(pscdata));
sound/soc/au1x/psc-i2s.c
123
cfgbits = __raw_readl(I2S_CFG(pscdata));
sound/soc/au1x/psc-i2s.c
153
while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
sound/soc/au1x/psc-i2s.c
166
while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
sound/soc/au1x/psc-i2s.c
187
stat = __raw_readl(I2S_STAT(pscdata));
sound/soc/au1x/psc-i2s.c
201
while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
sound/soc/au1x/psc-i2s.c
222
while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
sound/soc/au1x/psc-i2s.c
226
stat = __raw_readl(I2S_STAT(pscdata));
sound/soc/au1x/psc-i2s.c
321
sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
sound/soc/au1x/psc-i2s.c
362
wd->pm[0] = __raw_readl(PSC_SEL(wd));
sound/soc/cirrus/ep93xx-i2s.c
91
return __raw_readl(info->regs + reg);
sound/soc/mxs/mxs-saif.c
177
scr = __raw_readl(master_saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
288
stat = __raw_readl(saif->base + SAIF_STAT);
sound/soc/mxs/mxs-saif.c
352
stat = __raw_readl(saif->base + SAIF_STAT);
sound/soc/mxs/mxs-saif.c
368
scr0 = __raw_readl(saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
47
ret = readx_poll_timeout(__raw_readl, saif->base + SAIF_STAT, stat,
sound/soc/mxs/mxs-saif.c
489
stat = __raw_readl(saif->base + SAIF_STAT);
sound/soc/mxs/mxs-saif.c
528
scr = __raw_readl(saif->base + SAIF_CTRL);
sound/soc/mxs/mxs-saif.c
638
__raw_readl(saif->base + SAIF_DATA);
sound/soc/mxs/mxs-saif.c
639
__raw_readl(saif->base + SAIF_DATA);
sound/soc/mxs/mxs-saif.c
646
__raw_readl(saif->base + SAIF_CTRL),
sound/soc/mxs/mxs-saif.c
647
__raw_readl(saif->base + SAIF_STAT));
sound/soc/mxs/mxs-saif.c
650
__raw_readl(master_saif->base + SAIF_CTRL),
sound/soc/mxs/mxs-saif.c
651
__raw_readl(master_saif->base + SAIF_STAT));
sound/soc/mxs/mxs-saif.c
731
stat = __raw_readl(saif->base + SAIF_STAT);
sound/soc/mxs/mxs-saif.c
749
__raw_readl(saif->base + SAIF_CTRL),
sound/soc/mxs/mxs-saif.c
750
__raw_readl(saif->base + SAIF_STAT));
sound/soc/mxs/mxs-saif.c
89
stat = __raw_readl(saif->base + SAIF_STAT);
sound/soc/pxa/mmp-sspa.c
422
if ((__raw_readl(sspa->tx_base + SSPA_SP) & SSPA_SP_S_EN) ||
sound/soc/pxa/mmp-sspa.c
423
(__raw_readl(sspa->rx_base + SSPA_SP) & SSPA_SP_S_EN)) {
sound/soc/pxa/pxa-ssp.c
126
priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
sound/soc/pxa/pxa-ssp.c
127
priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
sound/soc/pxa/pxa-ssp.c
128
priv->to = __raw_readl(ssp->mmio_base + SSTO);
sound/soc/pxa/pxa-ssp.c
129
priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
sound/soc/renesas/fsi.c
320
return __raw_readl(reg);
sound/soc/renesas/rcar/debugfs.c
51
seq_printf(m, " %08x", __raw_readl(base + offset + i + j));
sound/soc/renesas/siu.h
141
return __raw_readl(addr);
sound/soc/ti/davinci-i2s.c
177
return __raw_readl(dev->base + reg);
sound/soc/ti/davinci-mcasp.c
143
__raw_writel(__raw_readl(reg) | val, reg);
sound/soc/ti/davinci-mcasp.c
150
__raw_writel((__raw_readl(reg) & ~(val)), reg);
sound/soc/ti/davinci-mcasp.c
157
__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
sound/soc/ti/davinci-mcasp.c
168
return (u32)__raw_readl(mcasp->base + offset);
tools/include/asm-generic/io.h
187
val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
tools/include/asm-generic/io.h
295
val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
tools/include/asm-generic/io.h
399
u32 x = __raw_readl(addr);
tools/include/asm-generic/io.h
96
#ifndef __raw_readl
tools/include/asm-generic/io.h
97
#define __raw_readl __raw_readl
tools/testing/selftests/kvm/include/arm64/processor.h
242
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
