Symbol: k
arch/arc/include/asm/uaccess.h
28
#define __get_user_fn(sz, u, k) \
arch/arc/include/asm/uaccess.h
32
case 1: __arc_get_user_one(*(k), u, "ldb", __ret); break; \
arch/arc/include/asm/uaccess.h
33
case 2: __arc_get_user_one(*(k), u, "ldw", __ret); break; \
arch/arc/include/asm/uaccess.h
34
case 4: __arc_get_user_one(*(k), u, "ld", __ret); break; \
arch/arc/include/asm/uaccess.h
35
case 8: __arc_get_user_one_64(*(k), u, __ret); break; \
arch/arc/include/asm/uaccess.h
89
#define __put_user_fn(sz, u, k) \
arch/arc/include/asm/uaccess.h
93
case 1: __arc_put_user_one(*(k), u, "stb", __ret); break; \
arch/arc/include/asm/uaccess.h
94
case 2: __arc_put_user_one(*(k), u, "stw", __ret); break; \
arch/arc/include/asm/uaccess.h
95
case 4: __arc_put_user_one(*(k), u, "st", __ret); break; \
arch/arc/include/asm/uaccess.h
96
case 8: __arc_put_user_one_64(*(k), u, __ret); break; \
arch/arm/crypto/aes-neonbs-glue.c
135
aesbs_convert_key(ctx->key.rk, ctx->fallback.k.rndkeys,
arch/arm/crypto/ghash-ce-glue.c
128
static void ghash_reflect(u64 h[], const be128 *k)
arch/arm/crypto/ghash-ce-glue.c
130
u64 carry = be64_to_cpu(k->a) >> 63;
arch/arm/crypto/ghash-ce-glue.c
132
h[0] = (be64_to_cpu(k->b) << 1) | carry;
arch/arm/crypto/ghash-ce-glue.c
133
h[1] = (be64_to_cpu(k->a) << 1) | (be64_to_cpu(k->b) >> 63);
arch/arm/crypto/ghash-ce-glue.c
148
memcpy(&key->k, inkey, GHASH_BLOCK_SIZE);
arch/arm/crypto/ghash-ce-glue.c
149
ghash_reflect(key->h[0], &key->k);
arch/arm/crypto/ghash-ce-glue.c
152
be128 h = key->k;
arch/arm/crypto/ghash-ce-glue.c
154
gf128mul_lle(&h, &key->k);
arch/arm/crypto/ghash-ce-glue.c
157
gf128mul_lle(&h, &key->k);
arch/arm/crypto/ghash-ce-glue.c
160
gf128mul_lle(&h, &key->k);
arch/arm/crypto/ghash-ce-glue.c
187
struct gcm_key const *k, char *dst,
arch/arm/crypto/ghash-ce-glue.c
191
struct gcm_key const *k, char *head,
arch/arm/crypto/ghash-ce-glue.c
195
struct gcm_key const *k, char *dst,
arch/arm/crypto/ghash-ce-glue.c
199
struct gcm_key const *k, char *head,
arch/arm/crypto/ghash-ce-glue.c
208
be128 h, k;
arch/arm/crypto/ghash-ce-glue.c
215
aes_encrypt(&aes_key, (u8 *)&k, (u8[AES_BLOCK_SIZE]){});
arch/arm/crypto/ghash-ce-glue.c
221
memcpy(ctx->rk, aes_key.k.rndkeys, sizeof(ctx->rk));
arch/arm/crypto/ghash-ce-glue.c
226
ghash_reflect(ctx->h[0], &k);
arch/arm/crypto/ghash-ce-glue.c
228
h = k;
arch/arm/crypto/ghash-ce-glue.c
229
gf128mul_lle(&h, &k);
arch/arm/crypto/ghash-ce-glue.c
232
gf128mul_lle(&h, &k);
arch/arm/crypto/ghash-ce-glue.c
235
gf128mul_lle(&h, &k);
arch/arm/crypto/ghash-ce-glue.c
38
be128 k;
arch/arm/mach-pxa/sharpsl_pm.c
458
int i, j, k, temp, sum = 0;
arch/arm/mach-pxa/sharpsl_pm.c
472
k = 4;
arch/arm/mach-pxa/sharpsl_pm.c
476
k = i;
arch/arm/mach-pxa/sharpsl_pm.c
481
if (i != j && i != k)
arch/arm/mach-shmobile/platsmp-apmu.c
68
int k;
arch/arm/mach-shmobile/platsmp-apmu.c
70
for (k = 0; k < 1000; k++) {
arch/arm/mach-shmobile/platsmp-scu.c
75
int k;
arch/arm/mach-shmobile/platsmp-scu.c
81
for (k = 0; k < 1000; k++) {
arch/arm/net/bpf_jit_32.c
120
#define STACK_OFFSET(k) (-4 - (k) * 4)
arch/arm/net/bpf_jit_32.c
409
static u16 imm_offset(u32 k, struct jit_ctx *ctx)
arch/arm/net/bpf_jit_32.c
421
if (ctx->imms[i] == k)
arch/arm/net/bpf_jit_32.c
427
ctx->imms[i] = k;
arch/arm/net/bpf_jit_32.c
435
ctx->target[offset / 4] = k;
arch/arm/probes/kprobes/test-core.c
520
struct kprobe k = {
arch/arm/probes/kprobes/test-core.c
525
int ret = register_kprobe(&k);
arch/arm/probes/kprobes/test-core.c
533
unregister_kprobe(&k);
arch/arm64/crypto/ghash-ce-glue.c
143
static void ghash_reflect(u64 h[], const be128 *k)
arch/arm64/crypto/ghash-ce-glue.c
145
u64 carry = be64_to_cpu(k->a) & BIT(63) ? 1 : 0;
arch/arm64/crypto/ghash-ce-glue.c
147
h[0] = (be64_to_cpu(k->b) << 1) | carry;
arch/arm64/crypto/ghash-ce-glue.c
148
h[1] = (be64_to_cpu(k->a) << 1) | (be64_to_cpu(k->b) >> 63);
arch/arm64/crypto/ghash-ce-glue.c
163
memcpy(&key->k, inkey, GHASH_BLOCK_SIZE);
arch/arm64/crypto/ghash-ce-glue.c
165
ghash_reflect(key->h[0], &key->k);
arch/arm64/crypto/ghash-ce-glue.c
204
memcpy(&ctx->ghash_key.k, key, GHASH_BLOCK_SIZE);
arch/arm64/crypto/ghash-ce-glue.c
206
ghash_reflect(ctx->ghash_key.h[0], &ctx->ghash_key.k);
arch/arm64/crypto/ghash-ce-glue.c
208
h = ctx->ghash_key.k;
arch/arm64/crypto/ghash-ce-glue.c
209
gf128mul_lle(&h, &ctx->ghash_key.k);
arch/arm64/crypto/ghash-ce-glue.c
212
gf128mul_lle(&h, &ctx->ghash_key.k);
arch/arm64/crypto/ghash-ce-glue.c
215
gf128mul_lle(&h, &ctx->ghash_key.k);
arch/arm64/crypto/ghash-ce-glue.c
321
dg, iv, ctx->aes_key.k.rndkeys,
arch/arm64/crypto/ghash-ce-glue.c
34
be128 k;
arch/arm64/crypto/ghash-ce-glue.c
390
dg, iv, ctx->aes_key.k.rndkeys,
arch/arm64/include/asm/jump_label.h
34
char *k = &((char *)key)[branch];
arch/arm64/include/asm/jump_label.h
38
: : "i"(k) : : l_yes
arch/arm64/include/asm/jump_label.h
49
char *k = &((char *)key)[branch];
arch/arm64/include/asm/jump_label.h
54
: : "i"(k) : : l_yes
arch/arm64/include/asm/kvm_host.h
1506
#define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f))
arch/arm64/include/asm/kvm_host.h
1597
#define kvm_has_pauth(k, l) \
arch/arm64/include/asm/kvm_host.h
1601
pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \
arch/arm64/include/asm/kvm_host.h
1602
pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \
arch/arm64/include/asm/kvm_host.h
1603
pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \
arch/arm64/include/asm/kvm_host.h
1604
pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \
arch/arm64/include/asm/kvm_host.h
1605
pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \
arch/arm64/include/asm/kvm_host.h
1606
pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \
arch/arm64/include/asm/kvm_host.h
1611
#define kvm_has_fpmr(k) \
arch/arm64/include/asm/kvm_host.h
1613
kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
arch/arm64/include/asm/kvm_host.h
1615
#define kvm_has_tcr2(k) \
arch/arm64/include/asm/kvm_host.h
1616
(kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP))
arch/arm64/include/asm/kvm_host.h
1618
#define kvm_has_s1pie(k) \
arch/arm64/include/asm/kvm_host.h
1619
(kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP))
arch/arm64/include/asm/kvm_host.h
1621
#define kvm_has_s1poe(k) \
arch/arm64/include/asm/kvm_host.h
1623
kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP))
arch/arm64/include/asm/kvm_host.h
1625
#define kvm_has_ras(k) \
arch/arm64/include/asm/kvm_host.h
1626
(kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP))
arch/arm64/include/asm/kvm_host.h
1628
#define kvm_has_sctlr2(k) \
arch/arm64/include/asm/kvm_host.h
1629
(kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP))
arch/arm64/include/asm/kvm_host.h
648
#define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr))
arch/arm64/include/asm/kvm_host.h
656
#define kvm_set_sysreg_resx(k, sr, resx) \
arch/arm64/include/asm/kvm_host.h
657
__kvm_set_sysreg_resx(&(k)->arch, (sr), (resx))
arch/arm64/include/asm/pointer_auth.h
44
#define __ptrauth_key_install_nosync(k, v) \
arch/arm64/include/asm/pointer_auth.h
47
write_sysreg_s(__pki_v.lo, SYS_ ## k ## KEYLO_EL1); \
arch/arm64/include/asm/pointer_auth.h
48
write_sysreg_s(__pki_v.hi, SYS_ ## k ## KEYHI_EL1); \
arch/arm64/kernel/proton-pack.c
867
u8 k = 0;
arch/arm64/kernel/proton-pack.c
913
k = 132;
arch/arm64/kernel/proton-pack.c
915
k = 38;
arch/arm64/kernel/proton-pack.c
917
k = 32;
arch/arm64/kernel/proton-pack.c
919
k = 24;
arch/arm64/kernel/proton-pack.c
921
k = 11;
arch/arm64/kernel/proton-pack.c
923
k = 8;
arch/arm64/kernel/proton-pack.c
925
return k;
arch/arm64/kvm/config.c
330
#define check_pmu_revision(k, r) \
arch/arm64/kvm/config.c
332
(kvm_has_feat((k), ID_AA64DFR0_EL1, PMUVer, r) && \
arch/arm64/kvm/config.c
333
!kvm_has_feat((k), ID_AA64DFR0_EL1, PMUVer, IMP_DEF)); \
arch/arm64/kvm/config.c
356
#define has_feat_s2tgran(k, s) \
arch/arm64/kvm/sys_regs.c
1441
#define __PTRAUTH_KEY(k) \
arch/arm64/kvm/sys_regs.c
1442
{ SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
arch/arm64/kvm/sys_regs.c
1445
#define PTRAUTH_KEY(k) \
arch/arm64/kvm/sys_regs.c
1446
__PTRAUTH_KEY(k ## KEYLO_EL1), \
arch/arm64/kvm/sys_regs.c
1447
__PTRAUTH_KEY(k ## KEYHI_EL1)
arch/arm64/net/bpf_jit_comp.c
1008
if (k) {
arch/arm64/net/bpf_jit_comp.c
1009
emit_a64_mov_i64(r1, k, ctx);
arch/arm64/net/bpf_jit_comp.c
993
u8 k = get_spectre_bhb_loop_value();
arch/csky/mm/init.c
100
k = pmd_index(vaddr);
arch/csky/mm/init.c
107
for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
arch/csky/mm/init.c
120
k = 0;
arch/csky/mm/init.c
94
int i, j, k;
arch/loongarch/kernel/smp.c
174
int i, k, core_present;
arch/loongarch/kernel/smp.c
181
for_each_cpu(k, &temp_foreign_map)
arch/loongarch/kernel/smp.c
182
if (cpus_are_siblings(i, k))
arch/loongarch/lib/xor_simd.c
23
#define XOR(dj, k) "vxor.v $vr" #dj ", $vr" #dj ", $vr" #k "\n\t"
arch/loongarch/lib/xor_simd.c
66
#define XOR(dj, k) "xvxor.v $xr" #dj ", $xr" #dj ", $xr" #k "\n\t"
arch/m68k/fpsp040/fpsp.h
173
.set kfact_bit,12 | distinguishes static/dynamic k-factor
arch/microblaze/include/asm/cpuinfo.h
18
const unsigned k;
arch/microblaze/include/asm/cpuinfo.h
25
const unsigned k;
arch/microblaze/kernel/cpu/cpuinfo-static.c
131
ci->ver_code = cpu_ver_lookup[i].k;
arch/microblaze/kernel/cpu/cpuinfo-static.c
137
ci->fpga_family_code = family_string_lookup[i].k;
arch/microblaze/kernel/cpu/mb.c
36
if (cpuinfo.fpga_family_code == family_string_lookup[i].k) {
arch/microblaze/kernel/cpu/mb.c
44
if (cpuinfo.ver_code == cpu_ver_lookup[i].k) {
arch/mips/include/asm/sibyte/bcm1480_int.h
52
#define _BCM1480_INT_HIGH(k) (k)
arch/mips/include/asm/sibyte/bcm1480_int.h
53
#define _BCM1480_INT_LOW(k) ((k)+64)
arch/mips/kernel/cevt-r4k.c
51
unsigned int cnt, i, j, k, l;
arch/mips/kernel/cevt-r4k.c
70
for (k = 0; k < j; ++k) {
arch/mips/kernel/cevt-r4k.c
71
if (cnt < buf1[k]) {
arch/mips/kernel/cevt-r4k.c
74
for (; l > k; --l)
arch/mips/kernel/cevt-r4k.c
79
if (k < ARRAY_SIZE(buf1))
arch/mips/kernel/cevt-r4k.c
80
buf1[k] = cnt;
arch/mips/kernel/cevt-r4k.c
84
for (k = 0; k < i && k < ARRAY_SIZE(buf2); ++k) {
arch/mips/kernel/cevt-r4k.c
85
if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) {
arch/mips/kernel/cevt-r4k.c
88
for (; l > k; --l)
arch/mips/kernel/cevt-r4k.c
93
if (k < ARRAY_SIZE(buf2))
arch/mips/kernel/cevt-r4k.c
94
buf2[k] = buf1[ARRAY_SIZE(buf1) - 1];
arch/mips/kernel/smp.c
141
int i, k, core_present;
arch/mips/kernel/smp.c
148
for_each_cpu(k, &temp_foreign_map)
arch/mips/kernel/smp.c
149
if (cpus_are_siblings(i, k))
arch/mips/mm/init.c
235
int i, j, k;
arch/mips/mm/init.c
241
k = pmd_index(vaddr);
arch/mips/mm/init.c
248
for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
arch/mips/mm/init.c
262
k = 0;
arch/mips/net/bpf_jit_comp32.c
531
int exclude, k;
arch/mips/net/bpf_jit_comp32.c
539
for (k = 0; k < 2; k++) {
arch/mips/net/bpf_jit_comp32.c
540
emit(ctx, move, MIPS_R_T9, src[k]);
arch/mips/net/bpf_jit_comp32.c
541
emit(ctx, move, r1[k], dst[k]);
arch/mips/net/bpf_jit_comp32.c
542
emit(ctx, move, r2[k], MIPS_R_T9);
arch/mips/net/bpf_jit_comp64.c
135
int k;
arch/mips/net/bpf_jit_comp64.c
137
for (k = 0; k < 4; k++) {
arch/mips/net/bpf_jit_comp64.c
138
u16 half = imm64 >> (48 - 16 * k);
arch/mips/sibyte/bcm1480/irq.c
100
for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
arch/mips/sibyte/bcm1480/irq.c
101
cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
arch/mips/sibyte/bcm1480/irq.c
106
____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
arch/mips/sibyte/bcm1480/irq.c
111
cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
arch/mips/sibyte/bcm1480/irq.c
113
____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
arch/mips/sibyte/bcm1480/irq.c
144
int k;
arch/mips/sibyte/bcm1480/irq.c
156
for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
arch/mips/sibyte/bcm1480/irq.c
158
R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
arch/mips/sibyte/bcm1480/irq.c
169
R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
arch/mips/sibyte/bcm1480/irq.c
172
__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
arch/mips/sibyte/bcm1480/irq.c
81
int i = 0, old_cpu, cpu, int_on, k;
arch/parisc/kernel/drivers.c
895
int k;
arch/parisc/kernel/drivers.c
897
for (k = 0; k < dev->num_addrs; k++)
arch/parisc/kernel/drivers.c
898
pr_cont("0x%lx ", dev->addr[k]);
arch/parisc/kernel/irq.c
211
unsigned int k, avg, min, max;
arch/parisc/kernel/irq.c
215
for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
arch/parisc/kernel/irq.c
216
int hist = action->cr16_hist[k];
arch/parisc/kernel/irq.c
227
avg /= k;
arch/parisc/kernel/ptrace.c
417
const __u64 *k = kbuf;
arch/parisc/kernel/ptrace.c
426
regs->fr[pos++] = *k++;
arch/parisc/kernel/ptrace.c
434
kbuf = k;
arch/parisc/kernel/ptrace.c
537
const unsigned long *k = kbuf;
arch/parisc/kernel/ptrace.c
546
set_reg(regs, pos++, *k++);
arch/parisc/kernel/ptrace.c
554
kbuf = k;
arch/parisc/kernel/ptrace.c
601
const compat_ulong_t *k = kbuf;
arch/parisc/kernel/ptrace.c
610
set_reg(regs, pos++, *k++);
arch/parisc/kernel/ptrace.c
618
kbuf = k;
arch/parisc/net/bpf_jit_comp32.c
62
#define STACK_OFFSET(k) (- (NR_SAVED_REGISTERS + k + 1))
arch/powerpc/kernel/cacheinfo.c
134
static struct cache_index_dir *kobj_to_cache_index_dir(struct kobject *k)
arch/powerpc/kernel/cacheinfo.c
136
return container_of(k, struct cache_index_dir, kobj);
arch/powerpc/kernel/cacheinfo.c
571
static ssize_t cache_index_show(struct kobject *k, struct attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
577
return kobj_attr->show(k, kobj_attr, buf);
arch/powerpc/kernel/cacheinfo.c
580
static struct cache *index_kobj_to_cache(struct kobject *k)
arch/powerpc/kernel/cacheinfo.c
584
index = kobj_to_cache_index_dir(k);
arch/powerpc/kernel/cacheinfo.c
589
static ssize_t size_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
594
cache = index_kobj_to_cache(k);
arch/powerpc/kernel/cacheinfo.c
606
static ssize_t line_size_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
611
cache = index_kobj_to_cache(k);
arch/powerpc/kernel/cacheinfo.c
622
static ssize_t nr_sets_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
627
cache = index_kobj_to_cache(k);
arch/powerpc/kernel/cacheinfo.c
638
static ssize_t associativity_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
643
cache = index_kobj_to_cache(k);
arch/powerpc/kernel/cacheinfo.c
654
static ssize_t type_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
658
cache = index_kobj_to_cache(k);
arch/powerpc/kernel/cacheinfo.c
666
static ssize_t level_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
671
index = kobj_to_cache_index_dir(k);
arch/powerpc/kernel/cacheinfo.c
681
show_shared_cpumap(struct kobject *k, struct kobj_attribute *attr, char *buf, bool list)
arch/powerpc/kernel/cacheinfo.c
687
index = kobj_to_cache_index_dir(k);
arch/powerpc/kernel/cacheinfo.c
695
static ssize_t shared_cpu_map_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
697
return show_shared_cpumap(k, attr, buf, false);
arch/powerpc/kernel/cacheinfo.c
700
static ssize_t shared_cpu_list_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
arch/powerpc/kernel/cacheinfo.c
702
return show_shared_cpumap(k, attr, buf, true);
arch/powerpc/kernel/ptrace/ptrace-view.c
719
const compat_ulong_t *k = kbuf;
arch/powerpc/kernel/ptrace/ptrace-view.c
725
regs[pos++] = *k++;
arch/powerpc/kernel/ptrace/ptrace-view.c
728
set_user_msr(target, *k++);
arch/powerpc/kernel/ptrace/ptrace-view.c
734
regs[pos++] = *k++;
arch/powerpc/kernel/ptrace/ptrace-view.c
736
++k;
arch/powerpc/kernel/ptrace/ptrace-view.c
739
set_user_trap(target, *k++);
arch/powerpc/kernel/ptrace/ptrace-view.c
744
kbuf = k;
arch/powerpc/kernel/smp.c
740
int k;
arch/powerpc/kernel/smp.c
743
for_each_cpu(k, srcmask(i))
arch/powerpc/kernel/smp.c
744
cpumask_or(dstmask(k), dstmask(k), mask);
arch/powerpc/kernel/smp.c
750
for_each_cpu(k, srcmask(j))
arch/powerpc/kernel/smp.c
751
cpumask_or(dstmask(k), dstmask(k), mask);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
561
long int i, j, k, n, found, indexes[4];
arch/powerpc/kvm/book3s_hv_rm_mmu.c
657
for (k = 0; k < n; ++k) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
658
j = indexes[k];
arch/powerpc/kvm/book3s_hv_rm_mmu.c
660
hp = hptes[k];
arch/powerpc/kvm/book3s_hv_rm_mmu.c
661
rev = revs[k];
arch/powerpc/lib/test_emulate_step.c
1657
unsigned int i, j, k;
arch/powerpc/lib/test_emulate_step.c
1699
for (k = 0; k < 32; k++) {
arch/powerpc/lib/test_emulate_step.c
1700
ignore_gpr = flags & IGNORE_GPR(k);
arch/powerpc/lib/test_emulate_step.c
1701
if (!ignore_gpr && exp.gpr[k] != got.gpr[k]) {
arch/powerpc/lib/test_emulate_step.c
1703
gpr_mismatch(k, exp.gpr[k], got.gpr[k]);
arch/powerpc/mm/ptdump/bats.c
19
u32 k = upper & 3;
arch/powerpc/mm/ptdump/bats.c
24
if (k == 0) {
arch/powerpc/mm/ptdump/bats.c
37
if (k == 1)
arch/powerpc/mm/ptdump/bats.c
39
else if (k == 2)
arch/powerpc/perf/hv-gpci.c
469
size_t k, l, m;
arch/powerpc/perf/hv-gpci.c
485
k = j;
arch/powerpc/perf/hv-gpci.c
486
for (; k < j + element_size; k++)
arch/powerpc/perf/hv-gpci.c
487
*n += sprintf(buf + *n, "%02x", (u8)arg->bytes[k]);
arch/powerpc/perf/hv-gpci.c
490
total_affinity_domain_ele = (u8)arg->bytes[k - 2] << 8 | (u8)arg->bytes[k - 3];
arch/powerpc/perf/hv-gpci.c
491
size_of_each_affinity_domain_ele = (u8)arg->bytes[k] << 8 | (u8)arg->bytes[k - 1];
arch/powerpc/perf/hv-gpci.c
495
*n += sprintf(buf + *n, "%02x", (u8)arg->bytes[k]);
arch/powerpc/perf/hv-gpci.c
496
k++;
arch/powerpc/perf/hv-gpci.c
503
j = k;
arch/powerpc/perf/hv-gpci.c
506
*last_element = k;
arch/powerpc/platforms/powermac/udbg_adb.c
100
k = xmon_adb_keycode;
arch/powerpc/platforms/powermac/udbg_adb.c
103
if ((k & 0x7f) == 0x38 || (k & 0x7f) == 0x7b) {
arch/powerpc/platforms/powermac/udbg_adb.c
104
xmon_adb_shiftstate = (k & 0x80) == 0;
arch/powerpc/platforms/powermac/udbg_adb.c
107
if (k >= 0x80)
arch/powerpc/platforms/powermac/udbg_adb.c
109
k = (xmon_adb_shiftstate? xmon_shift_keytab: xmon_keytab)[k];
arch/powerpc/platforms/powermac/udbg_adb.c
110
if (k != 0)
arch/powerpc/platforms/powermac/udbg_adb.c
114
return k;
arch/powerpc/platforms/powermac/udbg_adb.c
77
int k, t, on;
arch/powerpc/platforms/powermac/udbg_adb.c
84
k = -1;
arch/powerpc/platforms/powermac/udbg_adb.c
94
k = udbg_adb_old_getc_poll();
arch/powerpc/platforms/powermac/udbg_adb.c
95
} while (k == -1 && xmon_adb_keycode == -1);
arch/powerpc/platforms/powermac/udbg_adb.c
98
if (k != -1)
arch/powerpc/platforms/powermac/udbg_adb.c
99
return k;
arch/riscv/include/asm/kvm_aia.h
78
#define kvm_riscv_aia_initialized(k) ((k)->arch.aia.initialized)
arch/riscv/include/asm/kvm_aia.h
80
#define irqchip_in_kernel(k) ((k)->arch.aia.in_kernel)
arch/riscv/kernel/cpufeature.c
947
for (int k = 0; k < ext.subset_ext_size; k++)
arch/riscv/kernel/cpufeature.c
948
set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);
arch/riscv/kvm/mmu.c
607
struct kvm_arch *k = &vcpu->kvm->arch;
arch/riscv/kvm/mmu.c
609
hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) & HGATP_VMID;
arch/riscv/kvm/mmu.c
610
hgatp |= (k->pgd_phys >> PAGE_SHIFT) & HGATP_PPN;
arch/riscv/net/bpf_jit_comp32.c
63
#define STACK_OFFSET(k) (-4 - (4 * NR_SAVED_REGISTERS) - (4 * (k)))
arch/s390/crypto/aes_s390.c
839
u8 k[AES_MAX_KEY_SIZE]; /* Key */
arch/s390/crypto/aes_s390.c
861
memcpy(param.k, ctx->key, ctx->key_len);
arch/s390/crypto/paes_s390.c
1280
unsigned int keylen, offset, nbytes, n, k;
arch/s390/crypto/paes_s390.c
1311
k = cpacf_km(ctx->fc | req_ctx->modifier, param->key + offset,
arch/s390/crypto/paes_s390.c
1313
if (k)
arch/s390/crypto/paes_s390.c
1314
rc = skcipher_walk_done(walk, nbytes - k);
arch/s390/crypto/paes_s390.c
1315
if (k < n) {
arch/s390/crypto/paes_s390.c
1377
unsigned int keylen, offset, nbytes, n, k;
arch/s390/crypto/paes_s390.c
1405
k = cpacf_km(ctx->fc | req_ctx->modifier, param->key + offset,
arch/s390/crypto/paes_s390.c
1407
if (k)
arch/s390/crypto/paes_s390.c
1408
rc = skcipher_walk_done(walk, nbytes - k);
arch/s390/crypto/paes_s390.c
1409
if (k < n) {
arch/s390/crypto/paes_s390.c
398
unsigned int nbytes, n, k;
arch/s390/crypto/paes_s390.c
433
k = cpacf_km(ctx->fc | req_ctx->modifier, param,
arch/s390/crypto/paes_s390.c
435
if (k)
arch/s390/crypto/paes_s390.c
436
rc = skcipher_walk_done(walk, nbytes - k);
arch/s390/crypto/paes_s390.c
437
if (k < n) {
arch/s390/crypto/paes_s390.c
660
unsigned int nbytes, n, k;
arch/s390/crypto/paes_s390.c
697
k = cpacf_kmc(ctx->fc | req_ctx->modifier, param,
arch/s390/crypto/paes_s390.c
699
if (k) {
arch/s390/crypto/paes_s390.c
701
rc = skcipher_walk_done(walk, nbytes - k);
arch/s390/crypto/paes_s390.c
703
if (k < n) {
arch/s390/crypto/paes_s390.c
942
unsigned int nbytes, n, k;
arch/s390/crypto/paes_s390.c
981
k = cpacf_kmctr(ctx->fc, param, walk->dst.virt.addr,
arch/s390/crypto/paes_s390.c
983
if (k) {
arch/s390/crypto/paes_s390.c
985
memcpy(walk->iv, ctrptr + k - AES_BLOCK_SIZE,
arch/s390/crypto/paes_s390.c
988
rc = skcipher_walk_done(walk, nbytes - k);
arch/s390/crypto/paes_s390.c
990
if (k < n) {
arch/s390/crypto/phmac_s390.c
416
unsigned int offset, k, n;
arch/s390/crypto/phmac_s390.c
438
k = _cpacf_kmac(&ctx->gr0.reg, ctx->param, ctx->buf, bs);
arch/s390/crypto/phmac_s390.c
439
if (likely(k == bs))
arch/s390/crypto/phmac_s390.c
441
if (unlikely(k > 0)) {
arch/s390/crypto/phmac_s390.c
477
k = _cpacf_kmac(&ctx->gr0.reg, ctx->param, hwh->walkaddr, n);
arch/s390/crypto/phmac_s390.c
478
if (likely(k > 0)) {
arch/s390/crypto/phmac_s390.c
479
ctx->buflen[0] += k;
arch/s390/crypto/phmac_s390.c
480
if (ctx->buflen[0] < k)
arch/s390/crypto/phmac_s390.c
482
rc = hwh_advance(hwh, k);
arch/s390/crypto/phmac_s390.c
486
if (unlikely(k < n)) {
arch/s390/crypto/phmac_s390.c
530
unsigned int k, n;
arch/s390/crypto/phmac_s390.c
537
k = _cpacf_kmac(&ctx->gr0.reg, ctx->param, ctx->buf, n);
arch/s390/crypto/phmac_s390.c
538
if (likely(k == n))
arch/s390/crypto/phmac_s390.c
540
if (unlikely(k > 0)) {
arch/s390/include/asm/kvm_host_types.h
51
unsigned long k : 1;
arch/s390/include/uapi/asm/runtime_instr.h
17
__u32 k : 1;
arch/s390/kernel/ptrace.c
533
const unsigned long *k = kbuf;
arch/s390/kernel/ptrace.c
535
rc = __poke_user(target, pos, *k++);
arch/s390/kernel/ptrace.c
536
count -= sizeof(*k);
arch/s390/kernel/ptrace.c
537
pos += sizeof(*k);
arch/s390/kernel/ptrace.c
818
cb->k == 1 &&
arch/s390/kernel/runtime_instr.c
57
cb->k = 1;
arch/s390/kvm/gaccess.c
120
unsigned short k : 1;
arch/s390/kvm/gaccess.c
128
unsigned short k : 1;
arch/s390/kvm/gaccess.c
154
if (old.k) {
arch/s390/kvm/gaccess.c
159
new.k = 1;
arch/s390/kvm/gaccess.c
177
new.k = 0;
arch/s390/kvm/gaccess.c
197
new.k = 1;
arch/s390/kvm/gaccess.c
212
new.k = 0;
arch/s390/kvm/gaccess.c
838
.oac1.k = !!dst_key,
arch/s390/kvm/gaccess.c
840
.oac2.k = !!src_key,
arch/sh/boards/mach-migor/lcd_qvga.c
117
int k;
arch/sh/boards/mach-migor/lcd_qvga.c
151
for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */
arch/sh/drivers/platform_early.c
305
int k, n, i;
arch/sh/drivers/platform_early.c
309
k = sh_early_platform_driver_probe_id(class_str, i, nr_probe - n);
arch/sh/drivers/platform_early.c
311
if (k < 0)
arch/sh/drivers/platform_early.c
314
n += k;
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
135
int k, ret = 0;
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
145
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
146
ret = clk_register(main_clks[k]);
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
167
int k, ret = 0;
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
169
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
170
ret = clk_register(main_clks[k]);
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
254
int k, ret = 0;
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
262
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
263
ret = clk_register(main_clks[k]);
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
247
int k, ret = 0;
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
255
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
256
ret = clk_register(main_clks[k]);
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
222
int k, ret = 0;
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
230
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
231
ret = clk_register(main_clks[k]);
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
270
int k, ret = 0;
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
278
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
279
ret |= clk_register(main_clks[k]);
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
344
int k, ret = 0;
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
352
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
353
ret = clk_register(main_clks[k]);
arch/sh/kernel/cpu/shmobile/cpuidle.c
31
int k;
arch/sh/kernel/cpu/shmobile/cpuidle.c
34
for (k = ARRAY_SIZE(cpuidle_mode) - 1; k > 0; k--)
arch/sh/kernel/cpu/shmobile/cpuidle.c
35
if (cpuidle_mode[k] == allowed_mode)
arch/sh/kernel/cpu/shmobile/cpuidle.c
38
allowed_state = k;
arch/sh/kernel/cpu/shmobile/cpuidle.c
44
k = min_t(int, allowed_state, requested_state);
arch/sh/kernel/cpu/shmobile/cpuidle.c
46
sh_mobile_call_standby(cpuidle_mode[k]);
arch/sh/kernel/cpu/shmobile/cpuidle.c
48
return k;
arch/sh/kernel/io_trapped.c
113
int k, len;
arch/sh/kernel/io_trapped.c
119
for (k = 0; k < tiop->num_resources; k++) {
arch/sh/kernel/io_trapped.c
120
res = tiop->resource + k;
arch/sh/kernel/io_trapped.c
171
int k;
arch/sh/kernel/io_trapped.c
173
for (k = 0; k < tiop->num_resources; k++) {
arch/sh/kernel/io_trapped.c
174
res = tiop->resource + k;
arch/sh/kernel/io_trapped.c
46
int k, n;
arch/sh/kernel/io_trapped.c
55
for (k = 0; k < tiop->num_resources; k++) {
arch/sh/kernel/io_trapped.c
56
res = tiop->resource + k;
arch/sh/kernel/io_trapped.c
70
for (k = 0; k < n; k++)
arch/sh/kernel/io_trapped.c
71
pages[k] = virt_to_page(tiop);
arch/sh/kernel/io_trapped.c
78
for (k = 0; k < tiop->num_resources; k++) {
arch/sh/kernel/io_trapped.c
79
res = tiop->resource + k;
arch/sh/mm/consistent.c
23
int k = strlen(name);
arch/sh/mm/consistent.c
27
if (!strncmp(name, p, k) && p[k] == '=') {
arch/sh/mm/consistent.c
28
p += k + 1;
arch/sh/mm/init.c
174
int i, j, k;
arch/sh/mm/init.c
180
k = pmd_index(vaddr);
arch/sh/mm/init.c
188
pmd += k;
arch/sh/mm/init.c
190
for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
arch/sh/mm/init.c
195
k = 0;
arch/sparc/kernel/ptrace_64.c
565
const compat_ulong_t *k = kbuf;
arch/sparc/kernel/ptrace_64.c
577
regs->u_regs[pos++] = *k++;
arch/sparc/kernel/ptrace_64.c
583
if (put_user(*k++, &reg_window[pos++]))
arch/sparc/kernel/ptrace_64.c
591
(void *) k,
arch/sparc/kernel/ptrace_64.c
592
sizeof(*k),
arch/sparc/kernel/ptrace_64.c
594
!= sizeof(*k))
arch/sparc/kernel/ptrace_64.c
596
k++;
arch/sparc/kernel/ptrace_64.c
635
reg = *k++;
arch/sparc/kernel/termios.c
101
err = put_user(k->c_iflag, &u->c_iflag);
arch/sparc/kernel/termios.c
102
err |= put_user(k->c_oflag, &u->c_oflag);
arch/sparc/kernel/termios.c
103
err |= put_user(k->c_cflag, &u->c_cflag);
arch/sparc/kernel/termios.c
104
err |= put_user(k->c_lflag, &u->c_lflag);
arch/sparc/kernel/termios.c
105
err |= put_user(k->c_line, &u->c_line);
arch/sparc/kernel/termios.c
106
err |= copy_to_user(u->c_cc, k->c_cc, NCCS);
arch/sparc/kernel/termios.c
107
if (!(k->c_lflag & ICANON)) {
arch/sparc/kernel/termios.c
108
err |= put_user(k->c_cc[VMIN], &u->c_cc[_VMIN]);
arch/sparc/kernel/termios.c
109
err |= put_user(k->c_cc[VTIME], &u->c_cc[_VTIME]);
arch/sparc/kernel/termios.c
111
err |= put_user(k->c_cc[VEOF], &u->c_cc[VEOF]);
arch/sparc/kernel/termios.c
112
err |= put_user(k->c_cc[VEOL], &u->c_cc[VEOL]);
arch/sparc/kernel/termios.c
33
int user_termios_to_kernel_termios(struct ktermios *k,
arch/sparc/kernel/termios.c
37
err = get_user(k->c_iflag, &u->c_iflag);
arch/sparc/kernel/termios.c
38
err |= get_user(k->c_oflag, &u->c_oflag);
arch/sparc/kernel/termios.c
39
err |= get_user(k->c_cflag, &u->c_cflag);
arch/sparc/kernel/termios.c
40
err |= get_user(k->c_lflag, &u->c_lflag);
arch/sparc/kernel/termios.c
41
err |= get_user(k->c_line, &u->c_line);
arch/sparc/kernel/termios.c
42
err |= copy_from_user(k->c_cc, u->c_cc, NCCS);
arch/sparc/kernel/termios.c
43
if (k->c_lflag & ICANON) {
arch/sparc/kernel/termios.c
44
err |= get_user(k->c_cc[VEOF], &u->c_cc[VEOF]);
arch/sparc/kernel/termios.c
45
err |= get_user(k->c_cc[VEOL], &u->c_cc[VEOL]);
arch/sparc/kernel/termios.c
47
err |= get_user(k->c_cc[VMIN], &u->c_cc[_VMIN]);
arch/sparc/kernel/termios.c
48
err |= get_user(k->c_cc[VTIME], &u->c_cc[_VTIME]);
arch/sparc/kernel/termios.c
50
err |= get_user(k->c_ispeed, &u->c_ispeed);
arch/sparc/kernel/termios.c
51
err |= get_user(k->c_ospeed, &u->c_ospeed);
arch/sparc/kernel/termios.c
56
struct ktermios *k)
arch/sparc/kernel/termios.c
59
err = put_user(k->c_iflag, &u->c_iflag);
arch/sparc/kernel/termios.c
60
err |= put_user(k->c_oflag, &u->c_oflag);
arch/sparc/kernel/termios.c
61
err |= put_user(k->c_cflag, &u->c_cflag);
arch/sparc/kernel/termios.c
62
err |= put_user(k->c_lflag, &u->c_lflag);
arch/sparc/kernel/termios.c
63
err |= put_user(k->c_line, &u->c_line);
arch/sparc/kernel/termios.c
64
err |= copy_to_user(u->c_cc, k->c_cc, NCCS);
arch/sparc/kernel/termios.c
65
if (!(k->c_lflag & ICANON)) {
arch/sparc/kernel/termios.c
66
err |= put_user(k->c_cc[VMIN], &u->c_cc[_VMIN]);
arch/sparc/kernel/termios.c
67
err |= put_user(k->c_cc[VTIME], &u->c_cc[_VTIME]);
arch/sparc/kernel/termios.c
69
err |= put_user(k->c_cc[VEOF], &u->c_cc[VEOF]);
arch/sparc/kernel/termios.c
70
err |= put_user(k->c_cc[VEOL], &u->c_cc[VEOL]);
arch/sparc/kernel/termios.c
72
err |= put_user(k->c_ispeed, &u->c_ispeed);
arch/sparc/kernel/termios.c
73
err |= put_user(k->c_ospeed, &u->c_ospeed);
arch/sparc/kernel/termios.c
77
int user_termios_to_kernel_termios_1(struct ktermios *k,
arch/sparc/kernel/termios.c
81
err = get_user(k->c_iflag, &u->c_iflag);
arch/sparc/kernel/termios.c
82
err |= get_user(k->c_oflag, &u->c_oflag);
arch/sparc/kernel/termios.c
83
err |= get_user(k->c_cflag, &u->c_cflag);
arch/sparc/kernel/termios.c
84
err |= get_user(k->c_lflag, &u->c_lflag);
arch/sparc/kernel/termios.c
85
err |= get_user(k->c_line, &u->c_line);
arch/sparc/kernel/termios.c
86
err |= copy_from_user(k->c_cc, u->c_cc, NCCS);
arch/sparc/kernel/termios.c
87
if (k->c_lflag & ICANON) {
arch/sparc/kernel/termios.c
88
err |= get_user(k->c_cc[VEOF], &u->c_cc[VEOF]);
arch/sparc/kernel/termios.c
89
err |= get_user(k->c_cc[VEOL], &u->c_cc[VEOL]);
arch/sparc/kernel/termios.c
91
err |= get_user(k->c_cc[VMIN], &u->c_cc[_VMIN]);
arch/sparc/kernel/termios.c
92
err |= get_user(k->c_cc[VTIME], &u->c_cc[_VTIME]);
arch/sparc/kernel/termios.c
98
struct ktermios *k)
arch/sparc/mm/io-unit.c
100
int i, j, k, npages;
arch/sparc/mm/io-unit.c
132
for (k = 1, scan++; k < npages; k++)
arch/sparc/mm/io-unit.c
139
for (k = 0; k < npages; k++, iopte = __iopte(iopte_val(iopte) + 0x100), scan++) {
arch/sparc/net/bpf_jit_comp_32.c
391
unsigned int K = filter[i].k;
arch/sparc/vdso/vdso2c.h
102
syms[k] = GET_BE(&sym->st_value);
arch/sparc/vdso/vdso2c.h
82
int k;
arch/sparc/vdso/vdso2c.h
89
for (k = 0; k < NSYMS; k++) {
arch/sparc/vdso/vdso2c.h
90
if (!strcmp(name, required_syms[k].name)) {
arch/sparc/vdso/vdso2c.h
91
if (syms[k]) {
arch/sparc/vdso/vdso2c.h
93
required_syms[k].name);
arch/x86/boot/compressed/kaslr.c
171
char *k = strchr(str, ',');
arch/x86/boot/compressed/kaslr.c
173
if (k)
arch/x86/boot/compressed/kaslr.c
174
*k++ = 0;
arch/x86/boot/compressed/kaslr.c
179
str = k;
arch/x86/crypto/aesni-intel_glue.c
1183
static_assert(offsetof(struct aes_gcm_key_aesni, base.aes_key.k.rndkeys) == 16);
arch/x86/crypto/aesni-intel_glue.c
1188
static_assert(offsetof(struct aes_gcm_key_vaes_avx2, base.aes_key.k.rndkeys) == 16);
arch/x86/crypto/aesni-intel_glue.c
1192
static_assert(offsetof(struct aes_gcm_key_vaes_avx512, base.aes_key.k.rndkeys) == 16);
arch/x86/crypto/aesni-intel_glue.c
1224
struct aes_gcm_key_vaes_avx512 *k =
arch/x86/crypto/aesni-intel_glue.c
1227
for (i = ARRAY_SIZE(k->h_powers) - 1; i >= 0; i--) {
arch/x86/crypto/aesni-intel_glue.c
1228
k->h_powers[i][0] = be64_to_cpu(h.b);
arch/x86/crypto/aesni-intel_glue.c
1229
k->h_powers[i][1] = be64_to_cpu(h.a);
arch/x86/crypto/aesni-intel_glue.c
1232
memset(k->padding, 0, sizeof(k->padding));
arch/x86/crypto/aesni-intel_glue.c
1234
struct aes_gcm_key_vaes_avx2 *k =
arch/x86/crypto/aesni-intel_glue.c
1238
for (i = ARRAY_SIZE(k->h_powers) - 1; i >= 0; i--) {
arch/x86/crypto/aesni-intel_glue.c
1239
k->h_powers[i][0] = be64_to_cpu(h.b);
arch/x86/crypto/aesni-intel_glue.c
1240
k->h_powers[i][1] = be64_to_cpu(h.a);
arch/x86/crypto/aesni-intel_glue.c
1243
for (i = 0; i < ARRAY_SIZE(k->h_powers_xored); i++) {
arch/x86/crypto/aesni-intel_glue.c
1246
k->h_powers_xored[i] = k->h_powers[j][0] ^
arch/x86/crypto/aesni-intel_glue.c
1247
k->h_powers[j][1];
arch/x86/crypto/aesni-intel_glue.c
1250
struct aes_gcm_key_aesni *k = AES_GCM_KEY_AESNI(key);
arch/x86/crypto/aesni-intel_glue.c
1252
for (i = ARRAY_SIZE(k->h_powers) - 1; i >= 0; i--) {
arch/x86/crypto/aesni-intel_glue.c
1253
k->h_powers[i][0] = be64_to_cpu(h.b);
arch/x86/crypto/aesni-intel_glue.c
1254
k->h_powers[i][1] = be64_to_cpu(h.a);
arch/x86/crypto/aesni-intel_glue.c
1255
k->h_powers_xored[i] = k->h_powers[i][0] ^
arch/x86/crypto/aesni-intel_glue.c
1256
k->h_powers[i][1];
arch/x86/crypto/aesni-intel_glue.c
1260
k->h_times_x64[0] = be64_to_cpu(h1.b);
arch/x86/crypto/aesni-intel_glue.c
1261
k->h_times_x64[1] = be64_to_cpu(h1.a);
arch/x86/include/asm/gsseg.h
24
_ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])
arch/x86/kernel/cpu/mce/amd.c
995
#define to_block(k) container_of(k, struct threshold_block, kobj)
arch/x86/kernel/dumpstack_64.c
117
k = (stk - begin) >> PAGE_SHIFT;
arch/x86/kernel/dumpstack_64.c
119
ep = &estack_pages[k];
arch/x86/kernel/dumpstack_64.c
99
unsigned int k;
arch/x86/kernel/e820.c
1000
*k++ = 0;
arch/x86/kernel/e820.c
1003
str = k;
arch/x86/kernel/e820.c
997
char *k = strchr(str, ',');
arch/x86/kernel/e820.c
999
if (k)
arch/x86/kernel/early_printk.c
34
int i, k, j;
arch/x86/kernel/early_printk.c
39
for (k = 1, j = 0; k < max_ypos; k++, j++) {
arch/x86/kernel/early_printk.c
41
writew(readw(VGABASE+2*(max_xpos*k+i)),
arch/x86/kernel/ptrace.c
1043
const compat_ulong_t *k = kbuf;
arch/x86/kernel/ptrace.c
1044
while (count >= sizeof(*k) && !ret) {
arch/x86/kernel/ptrace.c
1045
ret = putreg32(target, pos, *k++);
arch/x86/kernel/ptrace.c
1046
count -= sizeof(*k);
arch/x86/kernel/ptrace.c
1047
pos += sizeof(*k);
arch/x86/kernel/ptrace.c
450
const unsigned long *k = kbuf;
arch/x86/kernel/ptrace.c
451
while (count >= sizeof(*k) && !ret) {
arch/x86/kernel/ptrace.c
452
ret = putreg(target, pos, *k++);
arch/x86/kernel/ptrace.c
453
count -= sizeof(*k);
arch/x86/kernel/ptrace.c
454
pos += sizeof(*k);
arch/x86/kernel/smpboot.c
517
for (int k = 0; k < u; k++) {
arch/x86/kernel/smpboot.c
518
for (int l = k; l < u; l++) {
arch/x86/kernel/smpboot.c
519
if (node_distance(N + k, N + l) !=
arch/x86/kernel/smpboot.c
520
node_distance(N + l, N + k))
arch/x86/kvm/debugfs.c
119
for (k = 0; k < KVM_NR_PAGE_SIZES; k++) {
arch/x86/kvm/debugfs.c
120
rmap = slot->arch.rmap[k];
arch/x86/kvm/debugfs.c
121
lpage_size = kvm_mmu_slot_lpages(slot, k + 1);
arch/x86/kvm/debugfs.c
122
cur = log[k];
arch/x86/kvm/debugfs.c
139
k = (1 << i) - 1;
arch/x86/kvm/debugfs.c
140
seq_printf(m, "%d-%d\t", j, k);
arch/x86/kvm/debugfs.c
98
int i, j, k, l, ret;
arch/x86/kvm/x86.c
13848
u32 i, j, k;
arch/x86/kvm/x86.c
13861
k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
arch/x86/kvm/x86.c
13867
} while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
arch/x86/mm/pat/cpa-test.c
124
int i, k;
arch/x86/mm/pat/cpa-test.c
151
for (k = 0; k < len[i]; k++) {
arch/x86/mm/pat/cpa-test.c
152
pte = lookup_address(addr[i] + k*PAGE_SIZE, &level);
arch/x86/mm/pat/cpa-test.c
158
if (k == 0) {
arch/x86/mm/pat/cpa-test.c
163
len[i] = k;
arch/x86/mm/pat/cpa-test.c
167
if (test_bit(pfn + k, bm)) {
arch/x86/mm/pat/cpa-test.c
168
len[i] = k;
arch/x86/mm/pat/cpa-test.c
171
__set_bit(pfn + k, bm);
arch/x86/mm/pat/cpa-test.c
172
addrs[k] = addr[i] + k*PAGE_SIZE;
arch/x86/mm/pat/cpa-test.c
173
pages[k] = pfn_to_page(pfn + k);
arch/x86/mm/pat/cpa-test.c
175
if (!addr[i] || !pte || !k) {
arch/x86/net/bpf_jit_comp32.c
94
#define STACK_OFFSET(k) (k)
arch/x86/platform/uv/uv_nmi.c
621
int i, j, k, n = num_online_cpus();
arch/x86/platform/uv/uv_nmi.c
627
k = 0;
arch/x86/platform/uv/uv_nmi.c
629
k = n - cpumask_weight(uv_nmi_cpu_mask);
arch/x86/platform/uv/uv_nmi.c
635
return n - k - 1;
arch/x86/platform/uv/uv_nmi.c
645
if (++k >= n)
arch/x86/platform/uv/uv_nmi.c
649
if (k >= n) { /* all in? */
arch/x86/platform/uv/uv_nmi.c
650
k = n;
arch/x86/platform/uv/uv_nmi.c
653
if (last_k != k) { /* abort if no new CPU's coming in */
arch/x86/platform/uv/uv_nmi.c
654
last_k = k;
arch/x86/platform/uv/uv_nmi.c
660
if (waiting && (n - k) == 1 &&
arch/x86/platform/uv/uv_nmi.c
666
atomic_set(&uv_nmi_cpus_in_nmi, k);
arch/x86/platform/uv/uv_nmi.c
667
return n - k;
arch/x86/tools/vdso2c.h
128
unsigned int k;
arch/x86/tools/vdso2c.h
135
for (k = 0; k < NSYMS; k++) {
arch/x86/tools/vdso2c.h
136
if (!strcmp(sym_name, required_syms[k].name)) {
arch/x86/tools/vdso2c.h
137
if (syms[k]) {
arch/x86/tools/vdso2c.h
139
required_syms[k].name);
arch/x86/tools/vdso2c.h
148
syms[k] = GET_LE(&sym->st_value);
arch/x86/um/ptrace.c
187
const unsigned long *k = kbuf;
arch/x86/um/ptrace.c
189
while (count >= sizeof(*k) && !ret) {
arch/x86/um/ptrace.c
190
ret = putreg(target, pos, *k++);
arch/x86/um/ptrace.c
191
count -= sizeof(*k);
arch/x86/um/ptrace.c
192
pos += sizeof(*k);
arch/xtensa/mm/init.c
169
char *k = strchr(str, ',');
arch/xtensa/mm/init.c
171
if (k)
arch/xtensa/mm/init.c
172
*k++ = 0;
arch/xtensa/mm/init.c
175
str = k;
arch/xtensa/mm/kasan_init.c
47
int k;
arch/xtensa/mm/kasan_init.c
49
for (k = 0; k < PTRS_PER_PTE; ++k, ++j) {
block/bfq-iosched.c
2631
int i, j, k;
block/bfq-iosched.c
2633
for (k = 0; k < bfqd->num_actuators; k++) {
block/bfq-iosched.c
2636
if (bfqg->async_bfqq[i][j][k])
block/bfq-iosched.c
2637
bfq_bfqq_end_wr(bfqg->async_bfqq[i][j][k]);
block/bfq-iosched.c
2638
if (bfqg->async_idle_bfqq[k])
block/bfq-iosched.c
2639
bfq_bfqq_end_wr(bfqg->async_idle_bfqq[k]);
block/bfq-iosched.c
7097
int i, j, k;
block/bfq-iosched.c
7099
for (k = 0; k < bfqd->num_actuators; k++) {
block/bfq-iosched.c
7102
__bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j][k]);
block/bfq-iosched.c
7104
__bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq[k]);
block/blk-mq.c
4096
int k;
block/blk-mq.c
4100
for (k = HCTX_TYPE_DEFAULT; k < HCTX_MAX_TYPES; k++)
block/blk-mq.c
4101
INIT_LIST_HEAD(&__ctx->rq_lists[k]);
crypto/aegis128-neon-inner.c
145
uint8x16_t k = vld1q_u8(key);
crypto/aegis128-neon-inner.c
146
uint8x16_t kiv = k ^ vld1q_u8(iv);
crypto/aegis128-neon-inner.c
151
k ^ vld1q_u8(const0),
crypto/aegis128-neon-inner.c
152
k ^ vld1q_u8(const1),
crypto/aegis128-neon-inner.c
159
st = aegis128_update_neon(st, k);
crypto/cast5_generic.c
400
static void key_schedule(u32 *x, u32 *z, u32 *k)
crypto/cast5_generic.c
414
k[0] = s5[zi(8)] ^ s6[zi(9)] ^ s7[zi(7)] ^ sb8[zi(6)] ^ s5[zi(2)];
crypto/cast5_generic.c
415
k[1] = s5[zi(10)] ^ s6[zi(11)] ^ s7[zi(5)] ^ sb8[zi(4)] ^
crypto/cast5_generic.c
417
k[2] = s5[zi(12)] ^ s6[zi(13)] ^ s7[zi(3)] ^ sb8[zi(2)] ^
crypto/cast5_generic.c
419
k[3] = s5[zi(14)] ^ s6[zi(15)] ^ s7[zi(1)] ^ sb8[zi(0)] ^
crypto/cast5_generic.c
430
k[4] = s5[xi(3)] ^ s6[xi(2)] ^ s7[xi(12)] ^ sb8[xi(13)] ^
crypto/cast5_generic.c
432
k[5] = s5[xi(1)] ^ s6[xi(0)] ^ s7[xi(14)] ^ sb8[xi(15)] ^
crypto/cast5_generic.c
434
k[6] = s5[xi(7)] ^ s6[xi(6)] ^ s7[xi(8)] ^ sb8[xi(9)] ^ s7[xi(3)];
crypto/cast5_generic.c
435
k[7] = s5[xi(5)] ^ s6[xi(4)] ^ s7[xi(10)] ^ sb8[xi(11)] ^
crypto/cast5_generic.c
446
k[8] = s5[zi(3)] ^ s6[zi(2)] ^ s7[zi(12)] ^ sb8[zi(13)] ^
crypto/cast5_generic.c
448
k[9] = s5[zi(1)] ^ s6[zi(0)] ^ s7[zi(14)] ^ sb8[zi(15)] ^
crypto/cast5_generic.c
450
k[10] = s5[zi(7)] ^ s6[zi(6)] ^ s7[zi(8)] ^ sb8[zi(9)] ^ s7[zi(2)];
crypto/cast5_generic.c
451
k[11] = s5[zi(5)] ^ s6[zi(4)] ^ s7[zi(10)] ^ sb8[zi(11)] ^
crypto/cast5_generic.c
462
k[12] = s5[xi(8)] ^ s6[xi(9)] ^ s7[xi(7)] ^ sb8[xi(6)] ^ s5[xi(3)];
crypto/cast5_generic.c
463
k[13] = s5[xi(10)] ^ s6[xi(11)] ^ s7[xi(5)] ^ sb8[xi(4)] ^
crypto/cast5_generic.c
465
k[14] = s5[xi(12)] ^ s6[xi(13)] ^ s7[xi(3)] ^ sb8[xi(2)] ^
crypto/cast5_generic.c
467
k[15] = s5[xi(14)] ^ s6[xi(15)] ^ s7[xi(1)] ^ sb8[xi(0)] ^
crypto/cast5_generic.c
481
u32 k[16];
crypto/cast5_generic.c
495
key_schedule(x, z, k);
crypto/cast5_generic.c
497
c->Km[i] = k[i];
crypto/cast5_generic.c
498
key_schedule(x, z, k);
crypto/cast5_generic.c
500
c->Kr[i] = k[i] & 0x1f;
crypto/ecc.c
411
unsigned int i, k;
crypto/ecc.c
416
for (k = 0; k < ndigits * 2 - 1; k++) {
crypto/ecc.c
419
if (k < ndigits)
crypto/ecc.c
422
min = (k + 1) - ndigits;
crypto/ecc.c
424
for (i = min; i <= k && i < ndigits; i++) {
crypto/ecc.c
427
product = mul_64_64(left[i], right[k - i]);
crypto/ecc.c
433
result[k] = r01.m_low;
crypto/ecc.c
447
unsigned int k;
crypto/ecc.c
449
for (k = 0; k < ndigits; k++) {
crypto/ecc.c
452
product = mul_64_64(left[k], right);
crypto/ecc.c
455
result[k] = r01.m_low;
crypto/ecc.c
459
result[k] = r01.m_low;
crypto/ecc.c
460
for (++k; k < ndigits * 2; k++)
crypto/ecc.c
461
result[k] = 0;
crypto/ecc.c
468
int i, k;
crypto/ecc.c
470
for (k = 0; k < ndigits * 2 - 1; k++) {
crypto/ecc.c
473
if (k < ndigits)
crypto/ecc.c
476
min = (k + 1) - ndigits;
crypto/ecc.c
478
for (i = min; i <= k && i <= k - i; i++) {
crypto/ecc.c
481
product = mul_64_64(left[i], left[k - i]);
crypto/ecc.c
483
if (i < k - i) {
crypto/ecc.c
494
result[k] = r01.m_low;
crypto/fcrypt.c
308
u64 k; /* k holds all 56 non-parity bits */
crypto/fcrypt.c
311
k = (*key++) >> 1;
crypto/fcrypt.c
312
k <<= 7;
crypto/fcrypt.c
313
k |= (*key++) >> 1;
crypto/fcrypt.c
314
k <<= 7;
crypto/fcrypt.c
315
k |= (*key++) >> 1;
crypto/fcrypt.c
316
k <<= 7;
crypto/fcrypt.c
317
k |= (*key++) >> 1;
crypto/fcrypt.c
318
k <<= 7;
crypto/fcrypt.c
319
k |= (*key++) >> 1;
crypto/fcrypt.c
320
k <<= 7;
crypto/fcrypt.c
321
k |= (*key++) >> 1;
crypto/fcrypt.c
322
k <<= 7;
crypto/fcrypt.c
323
k |= (*key++) >> 1;
crypto/fcrypt.c
324
k <<= 7;
crypto/fcrypt.c
325
k |= (*key) >> 1;
crypto/fcrypt.c
328
ctx->sched[0x0] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
329
ctx->sched[0x1] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
330
ctx->sched[0x2] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
331
ctx->sched[0x3] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
332
ctx->sched[0x4] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
333
ctx->sched[0x5] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
334
ctx->sched[0x6] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
335
ctx->sched[0x7] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
336
ctx->sched[0x8] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
337
ctx->sched[0x9] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
338
ctx->sched[0xa] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
339
ctx->sched[0xb] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
340
ctx->sched[0xc] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
341
ctx->sched[0xd] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
342
ctx->sched[0xe] = cpu_to_be32(k); ror56_64(k, 11);
crypto/fcrypt.c
343
ctx->sched[0xf] = cpu_to_be32(k);
crypto/fcrypt.c
66
#define ror56_64(k, n) (k = (k >> n) | ((k & ((1 << n) - 1)) << (56 - n)))
crypto/ghash-generic.c
59
be128 k;
crypto/ghash-generic.c
67
BUILD_BUG_ON(sizeof(k) != GHASH_BLOCK_SIZE);
crypto/ghash-generic.c
68
memcpy(&k, key, GHASH_BLOCK_SIZE); /* avoid violating alignment rules */
crypto/ghash-generic.c
69
ctx->gf128 = gf128mul_init_4k_lle(&k);
crypto/ghash-generic.c
70
memzero_explicit(&k, GHASH_BLOCK_SIZE);
crypto/jitterentropy.c
559
unsigned int k = 0, safety_factor = 0;
crypto/jitterentropy.c
576
if (++k >= ((DATA_SIZE_BITS + safety_factor) * ec->osr))
crypto/krb5/rfc6803_camellia.c
36
u32 i = 0, k = result->len * 8;
crypto/krb5/rfc6803_camellia.c
73
tmp = htonl(k);
crypto/krb5/rfc8009_aes2.c
32
unsigned int k,
crypto/krb5/rfc8009_aes2.c
45
if (WARN_ON(result->len != k / 8))
crypto/krb5/rfc8009_aes2.c
56
if (WARN_ON(crypto_shash_digestsize(shash) * 8 < k))
crypto/krb5/rfc8009_aes2.c
84
tmp = htonl(k);
crypto/md4.c
63
#define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s))
crypto/md4.c
64
#define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (u32)0x5A827999,s))
crypto/md4.c
65
#define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (u32)0x6ED9EBA1,s))
crypto/rmd160.c
39
#define ROUND(a, b, c, d, e, f, k, x, s) { \
crypto/rmd160.c
40
(a) += f((b), (c), (d)) + le32_to_cpup(&(x)) + (k); \
crypto/serpent_generic.c
229
u32 r3, u32 r4, u32 *k)
crypto/serpent_generic.c
231
k += 100;
crypto/serpent_generic.c
246
k -= 50;
crypto/serpent_generic.c
25
({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; })
crypto/serpent_generic.c
258
k -= 50;
crypto/serpent_generic.c
272
u32 *k = ctx->expkey;
crypto/serpent_generic.c
273
u8 *k8 = (u8 *)k;
crypto/serpent_generic.c
28
({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
crypto/serpent_generic.c
287
lk = (__le32 *)k;
crypto/serpent_generic.c
288
k[0] = le32_to_cpu(lk[0]);
crypto/serpent_generic.c
289
k[1] = le32_to_cpu(lk[1]);
crypto/serpent_generic.c
290
k[2] = le32_to_cpu(lk[2]);
crypto/serpent_generic.c
291
k[3] = le32_to_cpu(lk[3]);
crypto/serpent_generic.c
292
k[4] = le32_to_cpu(lk[4]);
crypto/serpent_generic.c
293
k[5] = le32_to_cpu(lk[5]);
crypto/serpent_generic.c
294
k[6] = le32_to_cpu(lk[6]);
crypto/serpent_generic.c
295
k[7] = le32_to_cpu(lk[7]);
crypto/serpent_generic.c
299
r0 = k[3];
crypto/serpent_generic.c
300
r1 = k[4];
crypto/serpent_generic.c
301
r2 = k[5];
crypto/serpent_generic.c
302
r3 = k[6];
crypto/serpent_generic.c
303
r4 = k[7];
crypto/serpent_generic.c
305
keyiter(k[0], r0, r4, r2, 0, 0);
crypto/serpent_generic.c
306
keyiter(k[1], r1, r0, r3, 1, 1);
crypto/serpent_generic.c
307
keyiter(k[2], r2, r1, r4, 2, 2);
crypto/serpent_generic.c
308
keyiter(k[3], r3, r2, r0, 3, 3);
crypto/serpent_generic.c
309
keyiter(k[4], r4, r3, r1, 4, 4);
crypto/serpent_generic.c
31
({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
crypto/serpent_generic.c
310
keyiter(k[5], r0, r4, r2, 5, 5);
crypto/serpent_generic.c
311
keyiter(k[6], r1, r0, r3, 6, 6);
crypto/serpent_generic.c
312
keyiter(k[7], r2, r1, r4, 7, 7);
crypto/serpent_generic.c
314
keyiter(k[0], r3, r2, r0, 8, 8);
crypto/serpent_generic.c
315
keyiter(k[1], r4, r3, r1, 9, 9);
crypto/serpent_generic.c
316
keyiter(k[2], r0, r4, r2, 10, 10);
crypto/serpent_generic.c
317
keyiter(k[3], r1, r0, r3, 11, 11);
crypto/serpent_generic.c
318
keyiter(k[4], r2, r1, r4, 12, 12);
crypto/serpent_generic.c
319
keyiter(k[5], r3, r2, r0, 13, 13);
crypto/serpent_generic.c
320
keyiter(k[6], r4, r3, r1, 14, 14);
crypto/serpent_generic.c
321
keyiter(k[7], r0, r4, r2, 15, 15);
crypto/serpent_generic.c
322
keyiter(k[8], r1, r0, r3, 16, 16);
crypto/serpent_generic.c
323
keyiter(k[9], r2, r1, r4, 17, 17);
crypto/serpent_generic.c
324
keyiter(k[10], r3, r2, r0, 18, 18);
crypto/serpent_generic.c
325
keyiter(k[11], r4, r3, r1, 19, 19);
crypto/serpent_generic.c
326
keyiter(k[12], r0, r4, r2, 20, 20);
crypto/serpent_generic.c
327
keyiter(k[13], r1, r0, r3, 21, 21);
crypto/serpent_generic.c
328
keyiter(k[14], r2, r1, r4, 22, 22);
crypto/serpent_generic.c
329
keyiter(k[15], r3, r2, r0, 23, 23);
crypto/serpent_generic.c
330
keyiter(k[16], r4, r3, r1, 24, 24);
crypto/serpent_generic.c
331
keyiter(k[17], r0, r4, r2, 25, 25);
crypto/serpent_generic.c
332
keyiter(k[18], r1, r0, r3, 26, 26);
crypto/serpent_generic.c
333
keyiter(k[19], r2, r1, r4, 27, 27);
crypto/serpent_generic.c
334
keyiter(k[20], r3, r2, r0, 28, 28);
crypto/serpent_generic.c
335
keyiter(k[21], r4, r3, r1, 29, 29);
crypto/serpent_generic.c
336
keyiter(k[22], r0, r4, r2, 30, 30);
crypto/serpent_generic.c
337
keyiter(k[23], r1, r0, r3, 31, 31);
crypto/serpent_generic.c
339
k += 50;
crypto/serpent_generic.c
341
keyiter(k[-26], r2, r1, r4, 32, -18);
crypto/serpent_generic.c
342
keyiter(k[-25], r3, r2, r0, 33, -17);
crypto/serpent_generic.c
343
keyiter(k[-24], r4, r3, r1, 34, -16);
crypto/serpent_generic.c
344
keyiter(k[-23], r0, r4, r2, 35, -15);
crypto/serpent_generic.c
345
keyiter(k[-22], r1, r0, r3, 36, -14);
crypto/serpent_generic.c
346
keyiter(k[-21], r2, r1, r4, 37, -13);
crypto/serpent_generic.c
347
keyiter(k[-20], r3, r2, r0, 38, -12);
crypto/serpent_generic.c
348
keyiter(k[-19], r4, r3, r1, 39, -11);
crypto/serpent_generic.c
349
keyiter(k[-18], r0, r4, r2, 40, -10);
crypto/serpent_generic.c
350
keyiter(k[-17], r1, r0, r3, 41, -9);
crypto/serpent_generic.c
351
keyiter(k[-16], r2, r1, r4, 42, -8);
crypto/serpent_generic.c
352
keyiter(k[-15], r3, r2, r0, 43, -7);
crypto/serpent_generic.c
353
keyiter(k[-14], r4, r3, r1, 44, -6);
crypto/serpent_generic.c
354
keyiter(k[-13], r0, r4, r2, 45, -5);
crypto/serpent_generic.c
355
keyiter(k[-12], r1, r0, r3, 46, -4);
crypto/serpent_generic.c
356
keyiter(k[-11], r2, r1, r4, 47, -3);
crypto/serpent_generic.c
357
keyiter(k[-10], r3, r2, r0, 48, -2);
crypto/serpent_generic.c
358
keyiter(k[-9], r4, r3, r1, 49, -1);
crypto/serpent_generic.c
359
keyiter(k[-8], r0, r4, r2, 50, 0);
crypto/serpent_generic.c
360
keyiter(k[-7], r1, r0, r3, 51, 1);
crypto/serpent_generic.c
361
keyiter(k[-6], r2, r1, r4, 52, 2);
crypto/serpent_generic.c
362
keyiter(k[-5], r3, r2, r0, 53, 3);
crypto/serpent_generic.c
363
keyiter(k[-4], r4, r3, r1, 54, 4);
crypto/serpent_generic.c
364
keyiter(k[-3], r0, r4, r2, 55, 5);
crypto/serpent_generic.c
365
keyiter(k[-2], r1, r0, r3, 56, 6);
crypto/serpent_generic.c
366
keyiter(k[-1], r2, r1, r4, 57, 7);
crypto/serpent_generic.c
367
keyiter(k[0], r3, r2, r0, 58, 8);
crypto/serpent_generic.c
368
keyiter(k[1], r4, r3, r1, 59, 9);
crypto/serpent_generic.c
369
keyiter(k[2], r0, r4, r2, 60, 10);
crypto/serpent_generic.c
37
x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
crypto/serpent_generic.c
370
keyiter(k[3], r1, r0, r3, 61, 11);
crypto/serpent_generic.c
371
keyiter(k[4], r2, r1, r4, 62, 12);
crypto/serpent_generic.c
372
keyiter(k[5], r3, r2, r0, 63, 13);
crypto/serpent_generic.c
373
keyiter(k[6], r4, r3, r1, 64, 14);
crypto/serpent_generic.c
374
keyiter(k[7], r0, r4, r2, 65, 15);
crypto/serpent_generic.c
375
keyiter(k[8], r1, r0, r3, 66, 16);
crypto/serpent_generic.c
376
keyiter(k[9], r2, r1, r4, 67, 17);
crypto/serpent_generic.c
377
keyiter(k[10], r3, r2, r0, 68, 18);
crypto/serpent_generic.c
378
keyiter(k[11], r4, r3, r1, 69, 19);
crypto/serpent_generic.c
379
keyiter(k[12], r0, r4, r2, 70, 20);
crypto/serpent_generic.c
38
x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
crypto/serpent_generic.c
380
keyiter(k[13], r1, r0, r3, 71, 21);
crypto/serpent_generic.c
381
keyiter(k[14], r2, r1, r4, 72, 22);
crypto/serpent_generic.c
382
keyiter(k[15], r3, r2, r0, 73, 23);
crypto/serpent_generic.c
383
keyiter(k[16], r4, r3, r1, 74, 24);
crypto/serpent_generic.c
384
keyiter(k[17], r0, r4, r2, 75, 25);
crypto/serpent_generic.c
385
keyiter(k[18], r1, r0, r3, 76, 26);
crypto/serpent_generic.c
386
keyiter(k[19], r2, r1, r4, 77, 27);
crypto/serpent_generic.c
387
keyiter(k[20], r3, r2, r0, 78, 28);
crypto/serpent_generic.c
388
keyiter(k[21], r4, r3, r1, 79, 29);
crypto/serpent_generic.c
389
keyiter(k[22], r0, r4, r2, 80, 30);
crypto/serpent_generic.c
390
keyiter(k[23], r1, r0, r3, 81, 31);
crypto/serpent_generic.c
392
k += 50;
crypto/serpent_generic.c
394
keyiter(k[-26], r2, r1, r4, 82, -18);
crypto/serpent_generic.c
395
keyiter(k[-25], r3, r2, r0, 83, -17);
crypto/serpent_generic.c
396
keyiter(k[-24], r4, r3, r1, 84, -16);
crypto/serpent_generic.c
397
keyiter(k[-23], r0, r4, r2, 85, -15);
crypto/serpent_generic.c
398
keyiter(k[-22], r1, r0, r3, 86, -14);
crypto/serpent_generic.c
399
keyiter(k[-21], r2, r1, r4, 87, -13);
crypto/serpent_generic.c
400
keyiter(k[-20], r3, r2, r0, 88, -12);
crypto/serpent_generic.c
401
keyiter(k[-19], r4, r3, r1, 89, -11);
crypto/serpent_generic.c
402
keyiter(k[-18], r0, r4, r2, 90, -10);
crypto/serpent_generic.c
403
keyiter(k[-17], r1, r0, r3, 91, -9);
crypto/serpent_generic.c
404
keyiter(k[-16], r2, r1, r4, 92, -8);
crypto/serpent_generic.c
405
keyiter(k[-15], r3, r2, r0, 93, -7);
crypto/serpent_generic.c
406
keyiter(k[-14], r4, r3, r1, 94, -6);
crypto/serpent_generic.c
407
keyiter(k[-13], r0, r4, r2, 95, -5);
crypto/serpent_generic.c
408
keyiter(k[-12], r1, r0, r3, 96, -4);
crypto/serpent_generic.c
409
keyiter(k[-11], r2, r1, r4, 97, -3);
crypto/serpent_generic.c
410
keyiter(k[-10], r3, r2, r0, 98, -2);
crypto/serpent_generic.c
411
keyiter(k[-9], r4, r3, r1, 99, -1);
crypto/serpent_generic.c
412
keyiter(k[-8], r0, r4, r2, 100, 0);
crypto/serpent_generic.c
413
keyiter(k[-7], r1, r0, r3, 101, 1);
crypto/serpent_generic.c
414
keyiter(k[-6], r2, r1, r4, 102, 2);
crypto/serpent_generic.c
415
keyiter(k[-5], r3, r2, r0, 103, 3);
crypto/serpent_generic.c
416
keyiter(k[-4], r4, r3, r1, 104, 4);
crypto/serpent_generic.c
417
keyiter(k[-3], r0, r4, r2, 105, 5);
crypto/serpent_generic.c
418
keyiter(k[-2], r1, r0, r3, 106, 6);
crypto/serpent_generic.c
419
keyiter(k[-1], r2, r1, r4, 107, 7);
crypto/serpent_generic.c
420
keyiter(k[0], r3, r2, r0, 108, 8);
crypto/serpent_generic.c
421
keyiter(k[1], r4, r3, r1, 109, 9);
crypto/serpent_generic.c
422
keyiter(k[2], r0, r4, r2, 110, 10);
crypto/serpent_generic.c
423
keyiter(k[3], r1, r0, r3, 111, 11);
crypto/serpent_generic.c
424
keyiter(k[4], r2, r1, r4, 112, 12);
crypto/serpent_generic.c
425
keyiter(k[5], r3, r2, r0, 113, 13);
crypto/serpent_generic.c
426
keyiter(k[6], r4, r3, r1, 114, 14);
crypto/serpent_generic.c
427
keyiter(k[7], r0, r4, r2, 115, 15);
crypto/serpent_generic.c
428
keyiter(k[8], r1, r0, r3, 116, 16);
crypto/serpent_generic.c
429
keyiter(k[9], r2, r1, r4, 117, 17);
crypto/serpent_generic.c
430
keyiter(k[10], r3, r2, r0, 118, 18);
crypto/serpent_generic.c
431
keyiter(k[11], r4, r3, r1, 119, 19);
crypto/serpent_generic.c
432
keyiter(k[12], r0, r4, r2, 120, 20);
crypto/serpent_generic.c
433
keyiter(k[13], r1, r0, r3, 121, 21);
crypto/serpent_generic.c
434
keyiter(k[14], r2, r1, r4, 122, 22);
crypto/serpent_generic.c
435
keyiter(k[15], r3, r2, r0, 123, 23);
crypto/serpent_generic.c
436
keyiter(k[16], r4, r3, r1, 124, 24);
crypto/serpent_generic.c
437
keyiter(k[17], r0, r4, r2, 125, 25);
crypto/serpent_generic.c
438
keyiter(k[18], r1, r0, r3, 126, 26);
crypto/serpent_generic.c
439
keyiter(k[19], r2, r1, r4, 127, 27);
crypto/serpent_generic.c
440
keyiter(k[20], r3, r2, r0, 128, 28);
crypto/serpent_generic.c
441
keyiter(k[21], r4, r3, r1, 129, 29);
crypto/serpent_generic.c
442
keyiter(k[22], r0, r4, r2, 130, 30);
crypto/serpent_generic.c
443
keyiter(k[23], r1, r0, r3, 131, 31);
crypto/serpent_generic.c
461
const u32 *k = ctx->expkey;
crypto/serpent_generic.c
48
x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
crypto/serpent_generic.c
49
x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\
crypto/serpent_generic.c
50
x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \
crypto/serpent_generic.c
520
const u32 *k = ctx->expkey;
crypto/serpent_generic.c
54
x0 ^= k[4*i+0]; x1 ^= k[4*i+1]; x2 ^= k[4*i+2]; \
crypto/serpent_generic.c
55
x3 ^= k[4*i+3]; x0 = ror32(x0, 5); x2 = ror32(x2, 22);\
crypto/tcrypt.c
110
int k, rem;
crypto/tcrypt.c
1160
unsigned int k = bs;
crypto/tcrypt.c
1161
unsigned int pages = DIV_ROUND_UP(k, PAGE_SIZE);
crypto/tcrypt.c
1166
while (k > PAGE_SIZE) {
crypto/tcrypt.c
1171
k -= PAGE_SIZE;
crypto/tcrypt.c
1174
sg_set_buf(cur->sg + p, cur->xbuf[p], k);
crypto/tcrypt.c
1175
memset(cur->xbuf[p], 0xff, k);
crypto/tcrypt.c
125
for (k = 0; k < np; k++)
crypto/tcrypt.c
126
sg_set_buf(&sg[k + 1], xbuf[k], PAGE_SIZE);
crypto/tcrypt.c
129
sg_set_buf(&sg[k + 1], xbuf[k], rem);
crypto/tcrypt.c
1297
unsigned int ret, i, j, k, iv_len;
crypto/tcrypt.c
1371
k = *keysize + bs;
crypto/tcrypt.c
1372
sg_init_table(sg, DIV_ROUND_UP(k, PAGE_SIZE));
crypto/tcrypt.c
1374
if (k > PAGE_SIZE) {
crypto/tcrypt.c
1377
k -= PAGE_SIZE;
crypto/tcrypt.c
1379
while (k > PAGE_SIZE) {
crypto/tcrypt.c
1383
k -= PAGE_SIZE;
crypto/tcrypt.c
1385
sg_set_buf(sg + j, tvmem[j], k);
crypto/tcrypt.c
1386
memset(tvmem[j], 0xff, k);
crypto/testmgr.c
2718
unsigned int i, j, k;
crypto/testmgr.c
2772
for (k = 0; k < template[i].len;
crypto/testmgr.c
2773
k += crypto_cipher_blocksize(tfm)) {
crypto/testmgr.c
2775
crypto_cipher_encrypt_one(tfm, data + k,
crypto/testmgr.c
2776
data + k);
crypto/testmgr.c
2778
crypto_cipher_decrypt_one(tfm, data + k,
crypto/testmgr.c
2779
data + k);
crypto/twofish_common.c
535
#define CALC_K(a, j, k, l, m, n) \
crypto/twofish_common.c
536
x = CALC_K_2 (k, l, k, l, 0); \
crypto/twofish_common.c
548
#define CALC_K192(a, j, k, l, m, n) \
crypto/twofish_common.c
549
x = CALC_K192_2 (l, l, k, k, 0); \
crypto/twofish_common.c
561
#define CALC_K256(a, j, k, l, m, n) \
crypto/twofish_common.c
562
x = CALC_K256_2 (k, l, 0); \
crypto/twofish_common.c
572
int i, j, k;
crypto/twofish_common.c
634
for ( i = j = 0, k = 1; i < 256; i++, j += 2, k += 2 ) {
crypto/twofish_common.c
635
CALC_SB256_2( i, calc_sb_tbl[j], calc_sb_tbl[k] );
crypto/twofish_common.c
652
CALC_K256 (k, i, q0[i+8], q1[i+8], q0[i+9], q1[i+9]);
crypto/twofish_common.c
656
for ( i = j = 0, k = 1; i < 256; i++, j += 2, k += 2 ) {
crypto/twofish_common.c
657
CALC_SB192_2( i, calc_sb_tbl[j], calc_sb_tbl[k] );
crypto/twofish_common.c
665
CALC_K192 (k, i, q0[i+8], q1[i+8], q0[i+9], q1[i+9]);
crypto/twofish_common.c
669
for ( i = j = 0, k = 1; i < 256; i++, j += 2, k += 2 ) {
crypto/twofish_common.c
670
CALC_SB_2( i, calc_sb_tbl[j], calc_sb_tbl[k] );
crypto/twofish_common.c
678
CALC_K (k, i, q0[i+8], q1[i+8], q0[i+9], q1[i+9]);
crypto/twofish_generic.c
55
x += y; y += x + ctx->k[2 * (n) + 1]; \
crypto/twofish_generic.c
56
(c) ^= x + ctx->k[2 * (n)]; \
crypto/twofish_generic.c
63
(d) ^= y + ctx->k[2 * (n) + 1]; \
crypto/twofish_generic.c
66
(c) ^= (x + ctx->k[2 * (n)])
drivers/accel/habanalabs/gaudi2/gaudi2.c
3873
int i, j, k;
drivers/accel/habanalabs/gaudi2/gaudi2.c
3904
for (i = GAUDI2_IRQ_NUM_USER_FIRST, k = 0 ; k < prop->user_interrupt_count; i++, j++, k++)
drivers/accel/habanalabs/gaudi2/gaudi2.c
4811
int irq, i, j, k;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4829
for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
drivers/accel/habanalabs/gaudi2/gaudi2.c
4830
k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
drivers/accel/qaic/qaic_data.c
454
int i, j, k;
drivers/accel/qaic/qaic_data.c
523
for (k = 0; k < i; k++, sg = sg_next(sg)) {
drivers/accel/qaic/qaic_data.c
525
if (k < i - 1) {
drivers/accel/qaic/qaic_data.c
526
sg_set_page(sg, pages[k], PAGE_SIZE << pages_order[k], 0);
drivers/accel/qaic/qaic_data.c
528
sg_set_page(sg, pages[k], (PAGE_SIZE << pages_order[k]) - buf_extra, 0);
drivers/acpi/acpica/exconvrt.c
268
u32 k = 0;
drivers/acpi/acpica/exconvrt.c
319
string[k] = (u8) (ACPI_ASCII_ZERO + remainder);
drivers/acpi/acpica/exconvrt.c
320
k++;
drivers/acpi/acpica/exconvrt.c
344
string[k] = hex_char;
drivers/acpi/acpica/exconvrt.c
345
k++;
drivers/acpi/acpica/exconvrt.c
359
if (!k) {
drivers/acpi/acpica/exconvrt.c
361
k = 1;
drivers/acpi/acpica/exconvrt.c
364
string[k] = 0;
drivers/acpi/acpica/exconvrt.c
365
return ((u32) k);
drivers/acpi/acpica/utownerid.c
32
u32 k;
drivers/acpi/acpica/utownerid.c
63
for (k = acpi_gbl_next_owner_id_offset; k < 32; k++) {
drivers/acpi/acpica/utownerid.c
77
if (!(acpi_gbl_owner_id_mask[j] & ((u32)1 << k))) {
drivers/acpi/acpica/utownerid.c
83
acpi_gbl_owner_id_mask[j] |= ((u32)1 << k);
drivers/acpi/acpica/utownerid.c
86
acpi_gbl_next_owner_id_offset = (u8)(k + 1);
drivers/acpi/acpica/utownerid.c
95
(acpi_owner_id)((k + 1) + ACPI_MUL_32(j));
drivers/acpi/device_sysfs.c
58
#define to_data_node(k) container_of(k, struct acpi_data_node, kobj)
drivers/acpi/processor_idle.c
402
int i, j, k;
drivers/acpi/processor_idle.c
408
for (j = i - 1, k = i; j >= 0; j--) {
drivers/acpi/processor_idle.c
412
if (states[j].latency > states[k].latency)
drivers/acpi/processor_idle.c
413
swap(states[j].latency, states[k].latency);
drivers/acpi/processor_idle.c
415
k = j;
drivers/acpi/x86/apple.c
109
unsigned int k = 1 + numvalid + j * 2; /* index into newprops */
drivers/acpi/x86/apple.c
110
unsigned int v = k + 1;
drivers/acpi/x86/apple.c
114
newprops[1 + j].package.elements = &newprops[k];
drivers/acpi/x86/apple.c
116
newprops[k].type = ACPI_TYPE_STRING;
drivers/acpi/x86/apple.c
117
newprops[k].string.length = key->string.length;
drivers/acpi/x86/apple.c
118
newprops[k].string.pointer = free_space;
drivers/acpi/x86/s2idle.c
110
int i, j, k;
drivers/acpi/x86/s2idle.c
149
for (k = 0; k < info_obj->package.count; k++) {
drivers/acpi/x86/s2idle.c
150
union acpi_object *obj = &info_obj->package.elements[k];
drivers/acpi/x86/s2idle.c
152
switch (k) {
drivers/ata/pata_parport/aten.c
62
int k, a, b, c, d;
drivers/ata/pata_parport/aten.c
68
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/aten.c
72
buf[2 * k] = j44(c, d);
drivers/ata/pata_parport/aten.c
73
buf[2 * k + 1] = j44(a, b);
drivers/ata/pata_parport/aten.c
80
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/aten.c
83
buf[2 * k] = b;
drivers/ata/pata_parport/aten.c
84
buf[2 * k + 1] = a;
drivers/ata/pata_parport/aten.c
93
int k;
drivers/ata/pata_parport/aten.c
96
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/aten.c
97
w0(buf[2 * k + 1]); w2(0xe); w2(6);
drivers/ata/pata_parport/aten.c
98
w0(buf[2 * k]); w2(7); w2(6);
drivers/ata/pata_parport/bpck.c
384
int i, j, k, p, v, f, om, od;
drivers/ata/pata_parport/bpck.c
398
for (k = 0; k < 9; k++) {
drivers/ata/pata_parport/bpck.c
407
for (k = 0; k < 8; k++) {
drivers/ata/pata_parport/bpck6.c
290
u8 i, j, k;
drivers/ata/pata_parport/bpck6.c
318
k = parport_read_status(pi->pardev->port) & 0xB8;
drivers/ata/pata_parport/bpck6.c
319
if (j != k)
drivers/ata/pata_parport/bpck6.c
323
k = (parport_read_status(pi->pardev->port) & 0xB8) ^ 0xB8;
drivers/ata/pata_parport/bpck6.c
324
if (j != k)
drivers/ata/pata_parport/comm.c
145
int k;
drivers/ata/pata_parport/comm.c
151
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/comm.c
153
w0(buf[k ^ 1]);
drivers/ata/pata_parport/comm.c
160
for (k = 0; k < count; k++)
drivers/ata/pata_parport/comm.c
161
w4(buf[k ^ 1]);
drivers/ata/pata_parport/comm.c
165
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/comm.c
166
w4w(swab16(((u16 *)buf)[k]));
drivers/ata/pata_parport/comm.c
170
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/comm.c
171
w4l(swab16(((u16 *)buf)[2 * k]) |
drivers/ata/pata_parport/comm.c
172
swab16(((u16 *)buf)[2 * k + 1]) << 16);
drivers/ata/pata_parport/dstr.c
117
int k, a, b;
drivers/ata/pata_parport/dstr.c
128
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/dstr.c
131
buf[k] = j44(a, b);
drivers/ata/pata_parport/dstr.c
136
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/dstr.c
138
buf[k] = r0();
drivers/ata/pata_parport/dstr.c
145
for (k = 0; k < count; k++)
drivers/ata/pata_parport/dstr.c
146
buf[k] = r4();
drivers/ata/pata_parport/dstr.c
151
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/dstr.c
152
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/dstr.c
157
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/dstr.c
158
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/dstr.c
166
int k;
drivers/ata/pata_parport/dstr.c
178
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/dstr.c
180
w0(buf[k]);
drivers/ata/pata_parport/dstr.c
187
for (k = 0; k < count; k++)
drivers/ata/pata_parport/dstr.c
188
w4(buf[k]);
drivers/ata/pata_parport/dstr.c
193
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/dstr.c
194
w4w(((u16 *)buf)[k]);
drivers/ata/pata_parport/dstr.c
199
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/dstr.c
200
w4l(((u32 *)buf)[k]);
drivers/ata/pata_parport/epat.c
103
buf[k] = j44(a, b);
drivers/ata/pata_parport/epat.c
112
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epat.c
113
if (k == count - 1)
drivers/ata/pata_parport/epat.c
117
buf[k] = j53(a, b);
drivers/ata/pata_parport/epat.c
126
for (k = 0; k < count - 1; k++) {
drivers/ata/pata_parport/epat.c
128
buf[k] = r0();
drivers/ata/pata_parport/epat.c
138
for (k = 0; k < count - 1; k++)
drivers/ata/pata_parport/epat.c
139
buf[k] = r4();
drivers/ata/pata_parport/epat.c
147
for (k = 0; k < count / 2 - 1; k++)
drivers/ata/pata_parport/epat.c
148
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/epat.c
157
for (k = 0; k < count / 4 - 1; k++)
drivers/ata/pata_parport/epat.c
158
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/epat.c
159
for (k = count - 4; k < count - 1; k++)
drivers/ata/pata_parport/epat.c
160
buf[k] = r4();
drivers/ata/pata_parport/epat.c
170
int ph, k;
drivers/ata/pata_parport/epat.c
178
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epat.c
179
w0(buf[k]);
drivers/ata/pata_parport/epat.c
187
for (k = 0; k < count; k++)
drivers/ata/pata_parport/epat.c
188
w4(buf[k]);
drivers/ata/pata_parport/epat.c
193
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/epat.c
194
w4w(((u16 *)buf)[k]);
drivers/ata/pata_parport/epat.c
199
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/epat.c
200
w4l(((u32 *)buf)[k]);
drivers/ata/pata_parport/epat.c
274
int k, j, f, cc;
drivers/ata/pata_parport/epat.c
285
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/epat.c
286
WRi(2, k ^ 0xaa);
drivers/ata/pata_parport/epat.c
287
WRi(3, k ^ 0x55);
drivers/ata/pata_parport/epat.c
288
if (RRi(2) != (k ^ 0xaa))
drivers/ata/pata_parport/epat.c
299
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/epat.c
300
if ((scratch[2 * k] & 0xff) != k)
drivers/ata/pata_parport/epat.c
302
if ((scratch[2 * k + 1] & 0xff) != 0xff - k)
drivers/ata/pata_parport/epat.c
87
int k, ph, a, b;
drivers/ata/pata_parport/epat.c
94
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epat.c
95
if (k == count-1)
drivers/ata/pata_parport/epia.c
129
int k, ph, a, b;
drivers/ata/pata_parport/epia.c
135
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epia.c
138
buf[k] = j44(a, b);
drivers/ata/pata_parport/epia.c
147
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epia.c
150
buf[k] = j53(a, b);
drivers/ata/pata_parport/epia.c
158
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epia.c
160
buf[k] = r0();
drivers/ata/pata_parport/epia.c
169
for (k = 0; k < count; k++)
drivers/ata/pata_parport/epia.c
170
buf[k] = r4();
drivers/ata/pata_parport/epia.c
177
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/epia.c
178
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/epia.c
185
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/epia.c
186
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/epia.c
194
int ph, k, last, d;
drivers/ata/pata_parport/epia.c
202
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/epia.c
203
d = buf[k];
drivers/ata/pata_parport/epia.c
217
for (k = 0; k < count; k++)
drivers/ata/pata_parport/epia.c
218
w4(buf[k]);
drivers/ata/pata_parport/epia.c
226
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/epia.c
227
w4w(((u16 *)buf)[k]);
drivers/ata/pata_parport/epia.c
235
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/epia.c
236
w4l(((u32 *)buf)[k]);
drivers/ata/pata_parport/epia.c
245
int j, k, f;
drivers/ata/pata_parport/epia.c
252
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/epia.c
253
WR(2, k ^ 0xaa);
drivers/ata/pata_parport/epia.c
254
WR(3, k ^ 0x55);
drivers/ata/pata_parport/epia.c
255
if (RR(2) != (k ^ 0xaa))
drivers/ata/pata_parport/epia.c
266
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/epia.c
267
if ((scratch[2 * k] & 0xff) != ((k + 1) & 0xff))
drivers/ata/pata_parport/epia.c
269
if ((scratch[2 * k + 1] & 0xff) != ((-2 - k) & 0xff))
drivers/ata/pata_parport/fit2.c
65
int k, a, b, c, d;
drivers/ata/pata_parport/fit2.c
69
for (k = 0; k < count / 4; k++) {
drivers/ata/pata_parport/fit2.c
73
buf[4 * k + 0] = j44(a, b);
drivers/ata/pata_parport/fit2.c
74
buf[4 * k + 1] = j44(d, c);
drivers/ata/pata_parport/fit2.c
79
buf[4 * k + 2] = j44(d, c);
drivers/ata/pata_parport/fit2.c
80
buf[4 * k + 3] = j44(a, b);
drivers/ata/pata_parport/fit2.c
88
int k;
drivers/ata/pata_parport/fit2.c
91
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/fit2.c
92
w2(4); w0(buf[2 * k]);
drivers/ata/pata_parport/fit2.c
93
w2(5); w0(buf[2 * k + 1]);
drivers/ata/pata_parport/fit3.c
101
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/fit3.c
104
buf[2 * k] = a;
drivers/ata/pata_parport/fit3.c
105
buf[2 * k + 1] = b;
drivers/ata/pata_parport/fit3.c
113
for (k = 0; k < count; k++)
drivers/ata/pata_parport/fit3.c
114
buf[k] = r4();
drivers/ata/pata_parport/fit3.c
122
int k;
drivers/ata/pata_parport/fit3.c
128
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/fit3.c
129
w0(buf[2 * k]); w2(0xd);
drivers/ata/pata_parport/fit3.c
130
w0(buf[2 * k + 1]); w2(0xc);
drivers/ata/pata_parport/fit3.c
135
for (k = 0; k < count; k++)
drivers/ata/pata_parport/fit3.c
136
w4(buf[k]);
drivers/ata/pata_parport/fit3.c
83
int k, a, b, c, d;
drivers/ata/pata_parport/fit3.c
88
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/fit3.c
93
buf[2 * k] = j44(a, b);
drivers/ata/pata_parport/fit3.c
94
buf[2 * k + 1] = j44(c, d);
drivers/ata/pata_parport/friq.c
105
for (k = 0; k < count / 2 - 1; k++)
drivers/ata/pata_parport/friq.c
106
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/friq.c
114
for (k = 0; k < count / 4 - 1; k++)
drivers/ata/pata_parport/friq.c
115
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/friq.c
133
int k;
drivers/ata/pata_parport/friq.c
139
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/friq.c
140
w0(buf[k]);
drivers/ata/pata_parport/friq.c
147
for (k = 0; k < count; k++)
drivers/ata/pata_parport/friq.c
148
w4(buf[k]);
drivers/ata/pata_parport/friq.c
153
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/friq.c
154
w4w(((u16 *)buf)[k]);
drivers/ata/pata_parport/friq.c
159
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/friq.c
160
w4l(((u32 *)buf)[k]);
drivers/ata/pata_parport/friq.c
182
int j, k, r;
drivers/ata/pata_parport/friq.c
194
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/friq.c
195
friq_write_regr(pi, 0, 2, k ^ 0xaa);
drivers/ata/pata_parport/friq.c
196
friq_write_regr(pi, 0, 3, k ^ 0x55);
drivers/ata/pata_parport/friq.c
197
if (friq_read_regr(pi, 0, 2) != (k ^ 0xaa))
drivers/ata/pata_parport/friq.c
206
for (k = 0; k < 128; k++) {
drivers/ata/pata_parport/friq.c
207
if (scratch[k] != k)
drivers/ata/pata_parport/friq.c
71
int h, l, k, ph;
drivers/ata/pata_parport/friq.c
76
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/friq.c
79
buf[k] = j44(l, h);
drivers/ata/pata_parport/friq.c
87
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/friq.c
89
buf[k] = r0();
drivers/ata/pata_parport/friq.c
96
for (k = 0; k < count - 2; k++)
drivers/ata/pata_parport/friq.c
97
buf[k] = r4();
drivers/ata/pata_parport/frpw.c
104
for (k = 0; k < count / 2 - 1; k++)
drivers/ata/pata_parport/frpw.c
105
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/frpw.c
114
for (k = 0; k < count / 4 - 1; k++)
drivers/ata/pata_parport/frpw.c
115
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/frpw.c
133
int k;
drivers/ata/pata_parport/frpw.c
140
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/frpw.c
141
w0(buf[k]);
drivers/ata/pata_parport/frpw.c
149
for (k = 0; k < count; k++)
drivers/ata/pata_parport/frpw.c
150
w4(buf[k]);
drivers/ata/pata_parport/frpw.c
156
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/frpw.c
157
w4w(((u16 *)buf)[k]);
drivers/ata/pata_parport/frpw.c
163
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/frpw.c
164
w4l(((u32 *)buf)[k]);
drivers/ata/pata_parport/frpw.c
221
int j, k, r;
drivers/ata/pata_parport/frpw.c
242
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/frpw.c
243
frpw_write_regr(pi, 0, 2, k ^ 0xaa);
drivers/ata/pata_parport/frpw.c
244
frpw_write_regr(pi, 0, 3, k ^ 0x55);
drivers/ata/pata_parport/frpw.c
245
if (frpw_read_regr(pi, 0, 2) != (k ^ 0xaa))
drivers/ata/pata_parport/frpw.c
254
for (k = 0; k < 128; k++) {
drivers/ata/pata_parport/frpw.c
255
if (scratch[k] != k)
drivers/ata/pata_parport/frpw.c
59
int h, l, k, ph;
drivers/ata/pata_parport/frpw.c
64
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/frpw.c
67
buf[k] = j44(l, h);
drivers/ata/pata_parport/frpw.c
76
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/frpw.c
78
buf[k] = r0();
drivers/ata/pata_parport/frpw.c
86
for (k = 0; k < count; k++)
drivers/ata/pata_parport/frpw.c
87
buf[k] = r4();
drivers/ata/pata_parport/frpw.c
94
for (k = 0; k < count - 2; k++)
drivers/ata/pata_parport/frpw.c
95
buf[k] = r4();
drivers/ata/pata_parport/kbic.c
128
int k, a, b;
drivers/ata/pata_parport/kbic.c
133
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/kbic.c
138
buf[2 * k] = j44(a, b);
drivers/ata/pata_parport/kbic.c
143
buf[2 * k + 1] = j44(a, b);
drivers/ata/pata_parport/kbic.c
149
for (k = 0; k < count / 4; k++) {
drivers/ata/pata_parport/kbic.c
153
buf[4 * k] = j53(r12w());
drivers/ata/pata_parport/kbic.c
155
buf[4 * k + 1] = j53(r12w());
drivers/ata/pata_parport/kbic.c
157
buf[4 * k + 3] = j53(r12w());
drivers/ata/pata_parport/kbic.c
159
buf[4 * k + 2] = j53(r12w());
drivers/ata/pata_parport/kbic.c
165
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/kbic.c
167
buf[2 * k] = r0();
drivers/ata/pata_parport/kbic.c
169
buf[2 * k + 1] = r0();
drivers/ata/pata_parport/kbic.c
175
for (k = 0; k < count; k++)
drivers/ata/pata_parport/kbic.c
176
buf[k] = r4();
drivers/ata/pata_parport/kbic.c
181
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/kbic.c
182
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/kbic.c
187
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/kbic.c
188
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/kbic.c
196
int k;
drivers/ata/pata_parport/kbic.c
203
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/kbic.c
204
w0(buf[2 * k + 1]);
drivers/ata/pata_parport/kbic.c
206
w0(buf[2 * k]);
drivers/ata/pata_parport/kbic.c
212
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/kbic.c
213
w4(buf[2 * k + 1]);
drivers/ata/pata_parport/kbic.c
214
w4(buf[2 * k]);
drivers/ata/pata_parport/kbic.c
220
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/kbic.c
221
w4w(swab16(((u16 *)buf)[k]));
drivers/ata/pata_parport/kbic.c
226
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/kbic.c
227
w4l(swab16(((u16 *)buf)[2 * k]) |
drivers/ata/pata_parport/kbic.c
228
swab16(((u16 *)buf)[2 * k + 1]) << 16);
drivers/ata/pata_parport/ktti.c
49
int k, a, b;
drivers/ata/pata_parport/ktti.c
51
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/ktti.c
54
buf[2*k] = j44(a, b);
drivers/ata/pata_parport/ktti.c
56
buf[2*k+1] = j44(a, b);
drivers/ata/pata_parport/ktti.c
62
int k;
drivers/ata/pata_parport/ktti.c
64
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/ktti.c
66
w0(buf[2 * k]); w2(3);
drivers/ata/pata_parport/ktti.c
67
w0(buf[2 * k + 1]); w2(6);
drivers/ata/pata_parport/on20.c
101
buf[k] = j44(l, h);
drivers/ata/pata_parport/on20.c
109
int k;
drivers/ata/pata_parport/on20.c
113
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/on20.c
114
w2(5); w0(buf[k]); w2(7);
drivers/ata/pata_parport/on20.c
91
int k, l, h;
drivers/ata/pata_parport/on20.c
95
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/on20.c
97
w2(4); w2(0x26); buf[k] = r0();
drivers/ata/pata_parport/on26.c
193
int k, a, b;
drivers/ata/pata_parport/on26.c
199
for (k = 0; k < count; k++) {
drivers/ata/pata_parport/on26.c
202
buf[k] = j44(a, b);
drivers/ata/pata_parport/on26.c
209
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/on26.c
210
w2(0x26); buf[2 * k] = r0();
drivers/ata/pata_parport/on26.c
211
w2(0x24); buf[2 * k + 1] = r0();
drivers/ata/pata_parport/on26.c
219
for (k = 0; k < count; k++)
drivers/ata/pata_parport/on26.c
220
buf[k] = r4();
drivers/ata/pata_parport/on26.c
227
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/on26.c
228
((u16 *)buf)[k] = r4w();
drivers/ata/pata_parport/on26.c
235
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/on26.c
236
((u32 *)buf)[k] = r4l();
drivers/ata/pata_parport/on26.c
244
int k;
drivers/ata/pata_parport/on26.c
252
for (k = 0; k < count / 2; k++) {
drivers/ata/pata_parport/on26.c
253
w2(5); w0(buf[2 * k]);
drivers/ata/pata_parport/on26.c
254
w2(7); w0(buf[2 * k + 1]);
drivers/ata/pata_parport/on26.c
263
for (k = 0; k < count; k++)
drivers/ata/pata_parport/on26.c
264
w4(buf[k]);
drivers/ata/pata_parport/on26.c
271
for (k = 0; k < count / 2; k++)
drivers/ata/pata_parport/on26.c
272
w4w(((u16 *)buf)[k]);
drivers/ata/pata_parport/on26.c
279
for (k = 0; k < count / 4; k++)
drivers/ata/pata_parport/on26.c
280
w4l(((u32 *)buf)[k]);
drivers/ata/pata_parport/pata_parport.c
355
int j, k;
drivers/ata/pata_parport/pata_parport.c
362
for (k = 0; k < 256; k++) {
drivers/ata/pata_parport/pata_parport.c
363
pi->proto->write_regr(pi, 0, 2, k ^ 0xaa);
drivers/ata/pata_parport/pata_parport.c
364
pi->proto->write_regr(pi, 0, 3, k ^ 0x55);
drivers/ata/pata_parport/pata_parport.c
365
if (pi->proto->read_regr(pi, 0, 2) != (k ^ 0xaa))
drivers/ata/sata_highbank.c
314
u32 tmp, k = 0;
drivers/ata/sata_highbank.c
321
} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
drivers/atm/idt77252.c
3273
int i, k;
drivers/atm/idt77252.c
3392
for (k = 0, i = 1; k < card->vcibits; k++) {
drivers/auxdisplay/cfag12864b.c
250
unsigned short i, j, k, b;
drivers/auxdisplay/cfag12864b.c
261
for (k = 0; k < CFAG12864B_ADDRESSES; k++) {
drivers/auxdisplay/cfag12864b.c
265
+ k / 8 + (j * 8 + b) *
drivers/auxdisplay/cfag12864b.c
267
& bit(k % 8))
drivers/base/bus.c
1405
struct kobject *k;
drivers/base/bus.c
1411
k = kset_find_obj(sp->drivers_kset, name);
drivers/base/bus.c
1413
if (!k)
drivers/base/bus.c
1416
priv = to_driver(k);
drivers/base/bus.c
1419
kobject_put(k);
drivers/base/core.c
3252
struct kobject *k;
drivers/base/core.c
3272
list_for_each_entry(k, &sp->glue_dirs.list, entry)
drivers/base/core.c
3273
if (k->parent == parent_kobj) {
drivers/base/core.c
3274
kobj = kobject_get(k);
drivers/base/core.c
3285
k = class_dir_create_and_add(sp, parent_kobj);
drivers/base/core.c
3289
return k;
drivers/base/swnode.c
729
struct kobject *k;
drivers/base/swnode.c
736
list_for_each_entry(k, &swnode_kset->list, entry) {
drivers/base/swnode.c
737
swnode = kobj_to_swnode(k);
drivers/base/swnode.c
82
struct kobject *k;
drivers/base/swnode.c
89
list_for_each_entry(k, &swnode_kset->list, entry) {
drivers/base/swnode.c
90
swnode = kobj_to_swnode(k);
drivers/bcma/scan.c
276
u8 i, j, k;
drivers/bcma/scan.c
370
k = 0;
drivers/bcma/scan.c
380
} else if (k < ARRAY_SIZE(core->addr_s)) {
drivers/bcma/scan.c
381
core->addr_s[k] = tmp;
drivers/bcma/scan.c
382
k++;
drivers/block/aoe/aoe.h
232
int aoe_ktstart(struct ktstate *k);
drivers/block/aoe/aoe.h
233
void aoe_ktstop(struct ktstate *k);
drivers/block/aoe/aoecmd.c
1231
struct ktstate *k;
drivers/block/aoe/aoecmd.c
1235
k = vp;
drivers/block/aoe/aoecmd.c
1238
complete(&k->rendez); /* tell spawner we're running */
drivers/block/aoe/aoecmd.c
1240
spin_lock_irq(k->lock);
drivers/block/aoe/aoecmd.c
1241
more = k->fn(k->id);
drivers/block/aoe/aoecmd.c
1243
add_wait_queue(k->waitq, &wait);
drivers/block/aoe/aoecmd.c
1246
spin_unlock_irq(k->lock);
drivers/block/aoe/aoecmd.c
1249
remove_wait_queue(k->waitq, &wait);
drivers/block/aoe/aoecmd.c
1253
complete(&k->rendez); /* tell spawner we're stopping */
drivers/block/aoe/aoecmd.c
1258
aoe_ktstop(struct ktstate *k)
drivers/block/aoe/aoecmd.c
1260
kthread_stop(k->task);
drivers/block/aoe/aoecmd.c
1261
wait_for_completion(&k->rendez);
drivers/block/aoe/aoecmd.c
1265
aoe_ktstart(struct ktstate *k)
drivers/block/aoe/aoecmd.c
1269
init_completion(&k->rendez);
drivers/block/aoe/aoecmd.c
1270
task = kthread_run(kthread, k, "%s", k->name);
drivers/block/aoe/aoecmd.c
1273
k->task = task;
drivers/block/aoe/aoecmd.c
1274
wait_for_completion(&k->rendez); /* allow kthread to start */
drivers/block/aoe/aoecmd.c
1275
init_completion(&k->rendez); /* for waiting for exit later */
drivers/bus/omap_l3_noc.c
116
for (k = 0, master = l3->l3_masters; k < l3->num_masters;
drivers/bus/omap_l3_noc.c
117
k++, master++) {
drivers/bus/omap_l3_noc.c
53
int k;
drivers/char/agp/parisc-agp.c
127
int i, k;
drivers/char/agp/parisc-agp.c
158
for (k = 0;
drivers/char/agp/parisc-agp.c
159
k < info->io_pages_per_kpage;
drivers/char/agp/parisc-agp.c
160
k++, j++, paddr += info->io_page_size) {
drivers/char/hpet.c
124
unsigned long t, mc, base, k;
drivers/char/hpet.c
147
k = (mc - base + hpetp->hp_delta) / t;
drivers/char/hpet.c
148
write_counter(t * (k + 1) + base,
drivers/clk/berlin/bg2.c
646
int k;
drivers/clk/berlin/bg2.c
648
for (k = 0; k < dd->num_parents; k++)
drivers/clk/berlin/bg2.c
649
parent_names[k] = clk_names[dd->parent_ids[k]];
drivers/clk/berlin/bg2q.c
340
int k;
drivers/clk/berlin/bg2q.c
342
for (k = 0; k < dd->num_parents; k++)
drivers/clk/berlin/bg2q.c
343
parent_names[k] = clk_names[dd->parent_ids[k]];
drivers/clk/renesas/rzv2h-cpg.c
320
if (pll_k < limits->k.min ||
drivers/clk/renesas/rzv2h-cpg.c
321
pll_k > limits->k.max)
drivers/clk/renesas/rzv2h-cpg.c
324
p.k = pll_k;
drivers/clk/renesas/rzv2h-cpg.c
327
fvco = mul_u32_u32(p.m * 65536 + p.k, fref);
drivers/clk/renesas/rzv2h-cpg.c
335
output += p.k * RZ_V2H_OSC_CLK_IN_MEGA;
drivers/clk/renesas/rzv2h-cpg.c
610
writel(FIELD_PREP(CPG_PLL_CLK1_KDIV, (u16)params->k) |
drivers/clk/rockchip/clk-pll.c
900
rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
drivers/clk/rockchip/clk-pll.c
914
if (cur.k) {
drivers/clk/rockchip/clk-pll.c
916
u64 frac_rate64 = prate * cur.k;
drivers/clk/rockchip/clk-pll.c
941
__func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
drivers/clk/rockchip/clk-pll.c
967
writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
drivers/clk/rockchip/clk.h
523
.k = _k, \
drivers/clk/rockchip/clk.h
592
unsigned int k;
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
101
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
116
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
129
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
155
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
204
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
33
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
110
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
124
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
177
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
30
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun5i.c
101
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun5i.c
116
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun5i.c
143
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun5i.c
29
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
33
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
31
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
115
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
149
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
178
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
228
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
32
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
32
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
99
.k = _SUNXI_CCU_MULT(4, 2),
drivers/clk/sunxi-ng/ccu_nk.c
106
_nk.min_k = nk->k.min ?: 1;
drivers/clk/sunxi-ng/ccu_nk.c
107
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
drivers/clk/sunxi-ng/ccu_nk.c
130
_nk.min_k = nk->k.min ?: 1;
drivers/clk/sunxi-ng/ccu_nk.c
131
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
drivers/clk/sunxi-ng/ccu_nk.c
139
reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
drivers/clk/sunxi-ng/ccu_nk.c
141
reg |= (_nk.k - nk->k.offset) << nk->k.shift;
drivers/clk/sunxi-ng/ccu_nk.c
15
unsigned long k, min_k, max_k;
drivers/clk/sunxi-ng/ccu_nk.c
40
nk->k = best_k;
drivers/clk/sunxi-ng/ccu_nk.c
71
unsigned long rate, n, k;
drivers/clk/sunxi-ng/ccu_nk.c
82
k = reg >> nk->k.shift;
drivers/clk/sunxi-ng/ccu_nk.c
83
k &= (1 << nk->k.width) - 1;
drivers/clk/sunxi-ng/ccu_nk.c
84
k += nk->k.offset;
drivers/clk/sunxi-ng/ccu_nk.c
85
if (!k)
drivers/clk/sunxi-ng/ccu_nk.c
86
k++;
drivers/clk/sunxi-ng/ccu_nk.c
88
rate = parent_rate * n * k;
drivers/clk/sunxi-ng/ccu_nk.h
26
struct ccu_mult_internal k;
drivers/clk/sunxi-ng/ccu_nk.h
41
.k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
drivers/clk/sunxi-ng/ccu_nkm.c
103
nkm->k = best_k;
drivers/clk/sunxi-ng/ccu_nkm.c
134
unsigned long n, m, k, rate;
drivers/clk/sunxi-ng/ccu_nkm.c
145
k = reg >> nkm->k.shift;
drivers/clk/sunxi-ng/ccu_nkm.c
146
k &= (1 << nkm->k.width) - 1;
drivers/clk/sunxi-ng/ccu_nkm.c
147
k += nkm->k.offset;
drivers/clk/sunxi-ng/ccu_nkm.c
148
if (!k)
drivers/clk/sunxi-ng/ccu_nkm.c
149
k++;
drivers/clk/sunxi-ng/ccu_nkm.c
15
unsigned long k, min_k, max_k;
drivers/clk/sunxi-ng/ccu_nkm.c
157
rate = parent_rate * n * k / m;
drivers/clk/sunxi-ng/ccu_nkm.c
174
_nkm.min_k = nkm->k.min ?: 1;
drivers/clk/sunxi-ng/ccu_nkm.c
175
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
drivers/clk/sunxi-ng/ccu_nkm.c
219
_nkm.min_k = nkm->k.min ?: 1;
drivers/clk/sunxi-ng/ccu_nkm.c
220
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
drivers/clk/sunxi-ng/ccu_nkm.c
230
reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
drivers/clk/sunxi-ng/ccu_nkm.c
234
reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift;
drivers/clk/sunxi-ng/ccu_nkm.c
67
nkm->k = best_k;
drivers/clk/sunxi-ng/ccu_nkm.h
25
struct ccu_mult_internal k;
drivers/clk/sunxi-ng/ccu_nkm.h
45
.k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
drivers/clk/sunxi-ng/ccu_nkm.h
66
.k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
drivers/clk/sunxi-ng/ccu_nkmp.c
108
k = reg >> nkmp->k.shift;
drivers/clk/sunxi-ng/ccu_nkmp.c
109
k &= (1 << nkmp->k.width) - 1;
drivers/clk/sunxi-ng/ccu_nkmp.c
110
k += nkmp->k.offset;
drivers/clk/sunxi-ng/ccu_nkmp.c
111
if (!k)
drivers/clk/sunxi-ng/ccu_nkmp.c
112
k++;
drivers/clk/sunxi-ng/ccu_nkmp.c
123
rate = ccu_nkmp_calc_rate(parent_rate, n, k, m, 1 << p);
drivers/clk/sunxi-ng/ccu_nkmp.c
148
_nkmp.min_k = nkmp->k.min ?: 1;
drivers/clk/sunxi-ng/ccu_nkmp.c
149
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
drivers/clk/sunxi-ng/ccu_nkmp.c
15
unsigned long k, min_k, max_k;
drivers/clk/sunxi-ng/ccu_nkmp.c
178
_nkmp.min_k = nkmp->k.min ?: 1;
drivers/clk/sunxi-ng/ccu_nkmp.c
179
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
drivers/clk/sunxi-ng/ccu_nkmp.c
196
if (nkmp->k.width)
drivers/clk/sunxi-ng/ccu_nkmp.c
197
k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1,
drivers/clk/sunxi-ng/ccu_nkmp.c
198
nkmp->k.shift);
drivers/clk/sunxi-ng/ccu_nkmp.c
21
unsigned long n, unsigned long k,
drivers/clk/sunxi-ng/ccu_nkmp.c
212
reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask;
drivers/clk/sunxi-ng/ccu_nkmp.c
26
rate *= n * k;
drivers/clk/sunxi-ng/ccu_nkmp.c
65
nkmp->k = best_k;
drivers/clk/sunxi-ng/ccu_nkmp.c
97
unsigned long n, m, k, p, rate;
drivers/clk/sunxi-ng/ccu_nkmp.h
25
struct ccu_mult_internal k;
drivers/clk/sunxi-ng/ccu_nkmp.h
45
.k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
drivers/clk/sunxi/clk-factors.c
154
reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k);
drivers/clk/sunxi/clk-factors.c
43
u8 n = 1, k = 0, p = 0, m = 0;
drivers/clk/sunxi/clk-factors.c
56
k = FACTOR_GET(config->kshift, config->kwidth, reg);
drivers/clk/sunxi/clk-factors.c
66
.k = k,
drivers/clk/sunxi/clk-factors.c
83
rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
drivers/clk/sunxi/clk-factors.h
27
u8 k;
drivers/clk/sunxi/clk-sunxi.c
105
req->k = 3;
drivers/clk/sunxi/clk-sunxi.c
108
req->k = 2;
drivers/clk/sunxi/clk-sunxi.c
111
req->k = 1;
drivers/clk/sunxi/clk-sunxi.c
114
req->k = 0;
drivers/clk/sunxi/clk-sunxi.c
137
req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
drivers/clk/sunxi/clk-sunxi.c
171
req->k = 1;
drivers/clk/sunxi/clk-sunxi.c
173
req->k = 0;
drivers/clk/sunxi/clk-sunxi.c
190
div /= (req->k + 1);
drivers/clk/sunxi/clk-sunxi.c
210
req->k = 0;
drivers/clk/sunxi/clk-sunxi.c
212
req->k = 1;
drivers/clk/sunxi/clk-sunxi.c
214
req->k = 2;
drivers/clk/sunxi/clk-sunxi.c
216
req->k = 3;
drivers/clk/sunxi/clk-sunxi.c
218
req->n = DIV_ROUND_UP(div, (req->k + 1));
drivers/clk/sunxi/clk-sunxi.c
236
req->k = div / 32;
drivers/clk/sunxi/clk-sunxi.c
237
if (req->k > 3)
drivers/clk/sunxi/clk-sunxi.c
238
req->k = 3;
drivers/clk/sunxi/clk-sunxi.c
240
req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
drivers/clk/sunxi/clk-sunxi.c
47
req->k = 1;
drivers/clk/sunxi/clk-sunxi.c
49
req->k = 0;
drivers/clk/sunxi/clk-sunxi.c
70
div /= (req->k + 1);
drivers/clk/tegra/clk-tegra124-emc.c
121
int i, k, t;
drivers/clk/tegra/clk-tegra124-emc.c
125
for (k = 0; k < tegra->num_timings; k++) {
drivers/clk/tegra/clk-tegra124-emc.c
126
if (tegra->timings[k].ram_code == ram_code)
drivers/clk/tegra/clk-tegra124-emc.c
130
for (t = k; t < tegra->num_timings; t++) {
drivers/clk/tegra/clk-tegra124-emc.c
135
for (i = k; i < t; i++) {
drivers/clk/tegra/clk-tegra124-emc.c
142
i = max(i, k + 1);
drivers/comedi/drivers/jr3_pci.c
613
int k;
drivers/comedi/drivers/jr3_pci.c
626
for (k = 0; k < 7; k++) {
drivers/comedi/drivers/jr3_pci.c
627
spriv->range_table_list[j + k * 8] = &spriv->range[j].l;
drivers/comedi/drivers/jr3_pci.c
628
spriv->maxdata_list[j + k * 8] = 0x7fff;
drivers/cpufreq/cpufreq.c
991
#define to_policy(k) container_of(k, struct cpufreq_policy, kobj)
drivers/cpufreq/e_powersaver.c
184
int k, step, voltage;
drivers/cpufreq/e_powersaver.c
343
k = 0;
drivers/cpufreq/e_powersaver.c
347
voltage = (k * step) / 256 + min_voltage;
drivers/cpufreq/e_powersaver.c
348
f_table[k].frequency = fsb * i;
drivers/cpufreq/e_powersaver.c
349
f_table[k].driver_data = (i << 8) | voltage;
drivers/cpufreq/e_powersaver.c
350
k++;
drivers/cpufreq/e_powersaver.c
352
f_table[k].frequency = CPUFREQ_TABLE_END;
drivers/cpufreq/longhaul.c
427
unsigned int i, j, k = 0;
drivers/cpufreq/longhaul.c
488
longhaul_table[k].frequency = calc_speed(ratio);
drivers/cpufreq/longhaul.c
489
longhaul_table[k].driver_data = j;
drivers/cpufreq/longhaul.c
490
k++;
drivers/cpufreq/longhaul.c
492
if (k <= 1) {
drivers/cpufreq/longhaul.c
497
for (j = 0; j < k - 1; j++) {
drivers/cpufreq/longhaul.c
501
for (i = j + 1; i < k; i++) {
drivers/cpufreq/longhaul.c
515
longhaul_table[k].frequency = CPUFREQ_TABLE_END;
drivers/cpufreq/longhaul.c
518
for (j = 0; j < k; j++) {
drivers/cpufreq/powernow-k7.c
506
unsigned int k;
drivers/cpufreq/powernow-k7.c
508
for (k = 0; k < number_scales; k++)
drivers/cpufreq/vexpress-spc-cpufreq.c
249
int i, j, k = 0, count = 1;
drivers/cpufreq/vexpress-spc-cpufreq.c
262
for (i = MAX_CLUSTERS - 1; i >= 0; i--, count = k) {
drivers/cpufreq/vexpress-spc-cpufreq.c
268
table[k++].frequency =
drivers/cpufreq/vexpress-spc-cpufreq.c
273
table[k].driver_data = k;
drivers/cpufreq/vexpress-spc-cpufreq.c
274
table[k].frequency = CPUFREQ_TABLE_END;
drivers/cpuidle/sysfs.c
407
#define kobj_to_state_obj(k) container_of(k, struct cpuidle_state_kobj, kobj)
drivers/cpuidle/sysfs.c
408
#define kobj_to_state(k) (kobj_to_state_obj(k)->state)
drivers/cpuidle/sysfs.c
409
#define kobj_to_state_usage(k) (kobj_to_state_obj(k)->state_usage)
drivers/cpuidle/sysfs.c
410
#define kobj_to_device(k) (kobj_to_state_obj(k)->device)
drivers/cpuidle/sysfs.c
529
#define kobj_to_driver_kobj(k) container_of(k, struct cpuidle_driver_kobj, kobj)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
260
u64 fill, min_fill, j, k;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
278
k = j;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
284
for (; k < j; k++)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
285
buf[k] = 0;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
419
u64 fill, min_fill, j, k;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
437
k = j;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
443
for (; k < j; k++)
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
444
buf[k] = 0;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
493
int j, i, k, todo;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
578
for (k = 6; k >= 0; k--) {
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
579
rctx->t_src[k + 1].addr = rctx->t_src[k].addr;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
580
rctx->t_src[k + 1].len = rctx->t_src[k].len;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
581
rctx->t_dst[k + 1].addr = rctx->t_dst[k].addr;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
582
rctx->t_dst[k + 1].len = rctx->t_dst[k].len;
drivers/crypto/chelsio/chcr_algo.c
233
int i, j, k;
drivers/crypto/chelsio/chcr_algo.c
271
for (k = 0, j = i % nk; k < nk; k++) {
drivers/crypto/chelsio/chcr_algo.c
272
put_unaligned_be32(w_ring[j], &dec_key[k * 4]);
drivers/crypto/chelsio/chcr_algo.c
290
} k;
drivers/crypto/chelsio/chcr_algo.c
294
hmac_sha1_preparekey(&k.sha1, raw_key, raw_key_len);
drivers/crypto/chelsio/chcr_algo.c
295
for (int i = 0; i < ARRAY_SIZE(k.sha1.istate.h); i++) {
drivers/crypto/chelsio/chcr_algo.c
296
istate32[i] = cpu_to_be32(k.sha1.istate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
297
ostate32[i] = cpu_to_be32(k.sha1.ostate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
301
hmac_sha224_preparekey(&k.sha224, raw_key, raw_key_len);
drivers/crypto/chelsio/chcr_algo.c
302
for (int i = 0; i < ARRAY_SIZE(k.sha224.key.istate.h); i++) {
drivers/crypto/chelsio/chcr_algo.c
303
istate32[i] = cpu_to_be32(k.sha224.key.istate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
304
ostate32[i] = cpu_to_be32(k.sha224.key.ostate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
308
hmac_sha256_preparekey(&k.sha256, raw_key, raw_key_len);
drivers/crypto/chelsio/chcr_algo.c
309
for (int i = 0; i < ARRAY_SIZE(k.sha256.key.istate.h); i++) {
drivers/crypto/chelsio/chcr_algo.c
310
istate32[i] = cpu_to_be32(k.sha256.key.istate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
311
ostate32[i] = cpu_to_be32(k.sha256.key.ostate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
315
hmac_sha384_preparekey(&k.sha384, raw_key, raw_key_len);
drivers/crypto/chelsio/chcr_algo.c
316
for (int i = 0; i < ARRAY_SIZE(k.sha384.key.istate.h); i++) {
drivers/crypto/chelsio/chcr_algo.c
317
istate64[i] = cpu_to_be64(k.sha384.key.istate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
318
ostate64[i] = cpu_to_be64(k.sha384.key.ostate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
322
hmac_sha512_preparekey(&k.sha512, raw_key, raw_key_len);
drivers/crypto/chelsio/chcr_algo.c
323
for (int i = 0; i < ARRAY_SIZE(k.sha512.key.istate.h); i++) {
drivers/crypto/chelsio/chcr_algo.c
324
istate64[i] = cpu_to_be64(k.sha512.key.istate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
325
ostate64[i] = cpu_to_be64(k.sha512.key.ostate.h[i]);
drivers/crypto/chelsio/chcr_algo.c
331
memzero_explicit(&k, sizeof(k));
drivers/crypto/hisilicon/sec2/sec_crypto.c
479
int i, j, k;
drivers/crypto/hisilicon/sec2/sec_crypto.c
497
k = i * SEC_PBUF_NUM + j;
drivers/crypto/hisilicon/sec2/sec_crypto.c
498
if (k == q_depth)
drivers/crypto/hisilicon/sec2/sec_crypto.c
500
res[k].pbuf = res->pbuf +
drivers/crypto/hisilicon/sec2/sec_crypto.c
502
res[k].pbuf_dma = res->pbuf_dma +
drivers/crypto/rockchip/rk3288_crypto.c
254
unsigned int i, k;
drivers/crypto/rockchip/rk3288_crypto.c
281
for (k = 0; k < i; k++) {
drivers/crypto/rockchip/rk3288_crypto.c
283
crypto_engine_unregister_skcipher(&rk_cipher_algs[k]->alg.skcipher);
drivers/dma-buf/dma-resv.c
185
unsigned int i, j, k, max;
drivers/dma-buf/dma-resv.c
215
for (i = 0, j = 0, k = max; i < (old ? old->num_fences : 0); ++i) {
drivers/dma-buf/dma-resv.c
221
RCU_INIT_POINTER(new->table[--k], fence);
drivers/dma-buf/dma-resv.c
241
for (i = k; i < max; ++i) {
drivers/dma/ppc4xx/adma.c
3361
int k = 0, op = 0, lop = 0;
drivers/dma/ppc4xx/adma.c
3366
if (k == XOR_MAX_OPS) {
drivers/dma/ppc4xx/adma.c
3367
k = 0;
drivers/dma/ppc4xx/adma.c
3373
if ((xcb->ops[k++].h & (DMA_RXOR12 << DMA_CUED_REGION_OFF)) ==
drivers/dma/ppc4xx/adma.c
3380
BUG_ON(k < 1);
drivers/dma/ppc4xx/adma.c
3382
if (test_bit(k-1, desc->reverse_flags)) {
drivers/dma/ppc4xx/adma.c
3385
ppc440spe_rxor_set_src(desc, k - 1, addr);
drivers/dma/ppc4xx/adma.c
3389
ppc440spe_rxor_set_src(desc, k - 1, addr);
drivers/dma/ppc4xx/adma.c
3402
int k = 0, op = 0, lop = 0;
drivers/dma/ppc4xx/adma.c
3407
if (k == XOR_MAX_OPS) {
drivers/dma/ppc4xx/adma.c
3408
k = 0;
drivers/dma/ppc4xx/adma.c
3415
if ((xcb->ops[k++].h & (DMA_RXOR12 << DMA_CUED_REGION_OFF)) ==
drivers/dma/ppc4xx/adma.c
3422
BUG_ON(k < 1);
drivers/dma/ppc4xx/adma.c
3423
if (test_bit(k-1, desc->reverse_flags)) {
drivers/dma/ppc4xx/adma.c
3425
ppc440spe_rxor_set_mult(desc, k - 1, op - index - 1, mult);
drivers/dma/ppc4xx/adma.c
3428
ppc440spe_rxor_set_mult(desc, k - 1, index - lop, mult);
drivers/dma/qcom/gpi.c
107
#define GPII_n_EV_CH_k_CNTXT_0_OFFS(n, k) (0x21000 + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
138
#define GPII_n_EV_CH_k_DOORBELL_0_OFFS(n, k) (0x22100 + (0x4000 * (n)) + (0x8 * (k)))
drivers/dma/qcom/gpi.c
206
#define GPII_n_CH_k_QOS_OFFS(n, k) (0x2005C + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
209
#define GPII_n_CH_k_SCRATCH_0_OFFS(n, k) (0x20060 + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
217
#define GPII_n_CH_k_SCRATCH_1_OFFS(n, k) (0x20064 + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
218
#define GPII_n_CH_k_SCRATCH_2_OFFS(n, k) (0x20068 + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
219
#define GPII_n_CH_k_SCRATCH_3_OFFS(n, k) (0x2006C + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
71
#define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 * (k)))
drivers/dma/qcom/gpi.c
89
#define GPII_n_CH_k_DOORBELL_0_OFFS(n, k) (0x22000 + (0x4000 * (n)) + (0x8 * (k)))
drivers/dma/sa11x0-dma.c
608
unsigned i, j, k, sglen, sgperiod;
drivers/dma/sa11x0-dma.c
631
for (i = k = 0; i < size / period; i++) {
drivers/dma/sa11x0-dma.c
634
for (j = 0; j < sgperiod; j++, k++) {
drivers/dma/sa11x0-dma.c
642
txd->sg[k].addr = addr;
drivers/dma/sa11x0-dma.c
643
txd->sg[k].len = tlen;
drivers/dma/sa11x0-dma.c
651
WARN_ON(k != sglen);
drivers/dma/ti/edma.c
1628
int k = (j << 5) + i;
drivers/dma/ti/edma.c
1635
edma_error_handler(&ecc->slave_chans[k]);
drivers/edac/amd64_edac.h
484
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/edac_device_sysfs.c
113
#define to_ctl_info(k) container_of(k, struct edac_device_ctl_info, kobj)
drivers/edac/edac_device_sysfs.c
23
#define to_edacdev(k) container_of(k, struct edac_device_ctl_info, kobj)
drivers/edac/edac_device_sysfs.c
321
#define to_instance(k) container_of(k, struct edac_device_instance, kobj)
drivers/edac/edac_device_sysfs.c
408
#define to_block(k) container_of(k, struct edac_device_block, kobj)
drivers/edac/edac_mc.h
96
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/edac_mc_sysfs.c
122
#define to_dimm(k) container_of(k, struct dimm_info, dev)
drivers/edac/edac_mc_sysfs.c
309
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/edac_pci_sysfs.c
211
#define to_edacpci(k) container_of(k, struct edac_pci_ctl_info, kobj)
drivers/edac/edac_pci_sysfs.c
70
#define to_instance(k) container_of(k, struct edac_pci_ctl_info, kobj)
drivers/edac/fsl_ddr_edac.c
66
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/highbank_mc_edac.c
98
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/i5100_edac.c
820
int k;
drivers/edac/i5100_edac.c
826
for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
drivers/edac/i5100_edac.c
827
priv->dmir[i][j].rank[k] =
drivers/edac/i5100_edac.c
828
i5100_dmir_rank(dw, k);
drivers/edac/i5100_edac.c
926
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/i7core_edac.c
650
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/ie31200_edac.c
429
int i, j, k;
drivers/edac/ie31200_edac.c
447
for (k = 0; k < dimm_info.ranks; k++) {
drivers/edac/ie31200_edac.c
448
dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0);
drivers/edac/octeon_edac-lmc.c
26
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/sb_edac.c
1769
int i, j, k, n_sads, n_tads, sad_interl;
drivers/edac/sb_edac.c
1910
for (k = 0; k < rir_way; k++) {
drivers/edac/sb_edac.c
1912
rir_offset[j][k],
drivers/edac/sb_edac.c
1918
i, j, k,
drivers/edac/synopsys_edac.c
986
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/versal_edac.c
671
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/versalnet_edac.c
507
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
drivers/edac/versalnet_edac.c
594
int i, j, k, sec_sev;
drivers/edac/versalnet_edac.c
614
k = offset + i;
drivers/edac/versalnet_edac.c
616
mc_priv->regs[k] = result[j];
drivers/firewire/core-card.c
134
for (k = 0; k < desc->length; k++)
drivers/firewire/core-card.c
135
config_rom[i + k] = cpu_to_be32(desc->data[k]);
drivers/firewire/core-card.c
92
int i, j, k, length;
drivers/firmware/qemu_fw_cfg.c
302
static ssize_t fw_cfg_showrev(struct kobject *k, struct kobj_attribute *a,
drivers/firmware/qemu_fw_cfg.c
564
struct kobject *k, *next;
drivers/firmware/qemu_fw_cfg.c
566
list_for_each_entry_safe(k, next, &kset->list, entry)
drivers/firmware/qemu_fw_cfg.c
568
if (k->ktype == kset->kobj.ktype)
drivers/firmware/qemu_fw_cfg.c
569
fw_cfg_kset_unregister_recursive(to_kset(k));
drivers/gpib/ni_usb/ni_usb_gpib.c
378
int k;
drivers/gpib/ni_usb/ni_usb_gpib.c
384
for (k = 0; k < results_per_chunk && j < num_results; ++k)
drivers/gpib/ni_usb/ni_usb_gpib.c
435
int k;
drivers/gpib/ni_usb/ni_usb_gpib.c
455
for (k = 0; k < data_block_length; k++) {
drivers/gpib/ni_usb/ni_usb_gpib.c
477
for (k = 0; k < 2; k++)
drivers/gpib/ni_usb/ni_usb_gpib.c
494
for (k = 0; k < 3; k++)
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
323
int i, j, k, path_size, device_support;
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
393
for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
394
u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
398
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
421
for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
422
u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
426
le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
434
le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1400
int i, j, k;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1513
for (k = 0; k < num_base_address; k++) {
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1528
ip->base_address[k] =
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1529
lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1531
ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1532
DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
162
unsigned int i, j, k;
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
176
for (k = 0; k < src->num_types; ++k) {
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
177
r = src->funcs->set(adev, src, k,
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
594
int i, j, k;
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
608
for (k = 0; k < src->num_types; k++)
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
609
amdgpu_irq_update(adev, src, k);
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
1569
for (int k = 0; k < dst_num_links; k++) {
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
1570
mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num =
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
1571
node_info.port_num[k].dst_xgmi_port_num;
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
1572
mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num =
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
1573
node_info.port_num[k].src_xgmi_port_num;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
10110
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
10143
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4755
int i, j, k, r, ring_id = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4924
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4925
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4929
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4941
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4943
k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
4947
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5257
int i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5295
for (k = 0; k < max_wgp_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5296
if (!(wgp_active_bitmap & (1 << k))) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5297
gcrd_targets_disable_tcp |= 3 << (2 * k);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5298
gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5299
utcl_invreq_disable |= (3 << (2 * k)) |
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
5300
(3 << (2 * (max_wgp_per_sh + k)));
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9642
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9665
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9666
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9695
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9696
drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9711
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9731
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9733
nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9762
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
9763
nv_grbm_select(adev, i, j, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1586
int i, j, k, r, ring_id;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1791
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1792
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1796
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1810
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1812
k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1816
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
5013
int r, i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
5028
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
5029
soc21_grbm_select(adev, i, k, j, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
5038
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
5039
soc21_grbm_select(adev, i, k, j, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7026
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7049
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7050
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7079
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7080
drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7095
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7115
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7117
soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7148
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7149
soc21_grbm_select(adev, i, j, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7481
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
7521
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1398
int i, j, k, r, ring_id = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1512
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1513
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1517
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1531
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1533
0, i, k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
1537
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5100
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5123
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5124
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5148
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5149
drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5164
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5184
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5186
soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5210
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5211
soc24_grbm_select(adev, i, j, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5715
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
5755
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1140
int i, j, k, r, ring_id = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1206
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1208
xcc_id, i, k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
1212
xcc_id, i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
3959
int i, j, k, counter, xcc_id, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
3997
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
1548
int i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
1560
for (k = 0; k < 16; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
1561
mask <<= k;
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
3545
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
3573
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
3259
u32 i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
3266
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
3280
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
4343
int i, j, k, r, ring_id;
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
4412
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
4414
k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
4419
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
5053
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
5081
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1888
int i, j, k, r, ring_id;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1989
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1991
k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
1996
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3807
u32 i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3814
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3819
if (k == adev->usec_timeout) {
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
3836
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
7074
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
7102
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
1671
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
1689
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2216
int i, j, k, r, ring_id;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2393
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2395
k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2400
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2718
u32 i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2725
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2730
if (k == adev->usec_timeout) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
2747
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7010
int i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7019
for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7020
amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7068
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7081
for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7082
amdgpu_gfx_select_se_sh(adev, j, 0, k, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7088
j, k, reg_value,
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7338
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7361
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7362
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7383
uint32_t i, j, k, reg, index = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7403
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7405
soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7845
int i, j, k, counter, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
7888
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
870
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
883
for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
884
k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
885
gfx_v9_4_select_se_sh(adev, j, 0, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
891
j, k, reg_value, &sec_count,
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
909
int i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
917
for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
918
k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
919
gfx_v9_4_select_se_sh(adev, j, 0x0, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
1504
uint32_t i, j, k, data;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
1516
for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
1517
k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
1518
gfx_v9_4_2_select_se_sh(adev, j, 0, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
1535
j, k, data, &sec_cnt, &ded_cnt);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1041
int i, j, k, r, ring_id, xcc_id, num_xcc;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1112
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1113
k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1115
adev, xcc_id, i, k, j))
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1121
i, k, j);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1467
u32 i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1475
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1480
if (k == adev->usec_timeout) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1499
for (k = 0; k < adev->usec_timeout; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3135
int i, j, k, num_xcc;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3146
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3148
mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3175
int i, j, k, num_xcc;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3186
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
3188
mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4373
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4385
for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4389
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4415
for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4419
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4447
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4453
for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4457
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4475
for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4479
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4561
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4599
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4602
xcc_id, i, j, k);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4630
uint32_t i, j, k;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4661
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4663
soc15_grbm_select(adev, 1 + i, j, k, 0,
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4891
int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
4927
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1007
WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1020
WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1021
WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1023
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1024
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1025
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1026
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1027
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1028
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1031
WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1036
WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1040
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1044
WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1051
status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1060
DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1061
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1065
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1072
DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1076
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1081
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1092
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1095
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1098
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1102
WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1104
WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1108
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1110
ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1111
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1114
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1117
ring = &adev->uvd.inst[k].ring_enc[0];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1118
WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1119
WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1120
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1121
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1122
WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1124
ring = &adev->uvd.inst[k].ring_enc[1];
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1125
WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1126
WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1127
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1128
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
1129
WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
960
int i, j, k, r;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
962
for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
963
if (adev->uvd.harvest_config & (1 << k))
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
966
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
976
for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
977
if (adev->uvd.harvest_config & (1 << k))
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
979
ring = &adev->uvd.inst[k].ring;
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
981
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
985
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
989
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
995
WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1164
int j, k, r;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
1251
for (k = 0; k < 10; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1200
int j, k, r;
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
1289
for (k = 0; k < 100; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1143
int j, k, r;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
1234
for (k = 0; k < 100; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1196
int j, k, r, vcn_inst;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
1282
for (k = 0; k < 100; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1055
int j, k, r;
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
1146
for (k = 0; k < 100; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
812
int j, k, r;
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
874
for (k = 0; k < 100; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
1040
for (k = 0; k < 100; ++k) {
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
985
int j, k, r, vcn_inst;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1565
uint32_t k;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1568
k = 0;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1570
k++;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1571
if (k < 2)
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1578
k--;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1581
ret = kfd_create_indirect_link_prop(new_dev, k);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1598
ret = kfd_add_peer_prop(new_dev, dev, i, k);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1602
ret = kfd_add_peer_prop(dev, new_dev, k, i);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1686
int i, j, k, xcc, start, end;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1754
k = 0;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1759
pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1760
pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1761
pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1762
pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1763
k += 4;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1770
pcache->sibling_map_size = k;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1785
int i, j, k, xcc, start, end;
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1827
for (k = 0; k < gfx_info->max_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1831
cu_processor_id, k);
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1842
num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
1845
(gfx_info->max_cu_per_sh - k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3362
int k, m;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3371
for (k = 0; k < dc_state->stream_count; k++) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3372
bundle->stream_update.stream = dc_state->streams[k];
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3374
for (m = 0; m < dc_state->stream_status[k].plane_count; m++) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3376
dc_state->stream_status[k].plane_states[m];
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3383
dc_state->stream_status[k].plane_count,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3384
dc_state->streams[k],
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
139
uint8_t i, j, k;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
168
for (k = 0; k < mstb_lct - 1; k++) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
169
int shift = (k % 2) ? 0 : 4;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
170
int port_num = (rad[k / 2] >> shift) & 0xf;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
171
int next_port_num = (next_rad[k / 2] >> shift) & 0xf;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1009
if (vars[i + k].dsc_enabled) {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1011
kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1038
link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1098
int k)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1111
if (vars[i + k].dsc_enabled
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1112
&& vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1177
static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1183
i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1198
int i, k, ret;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1273
k = *link_vars_start_index;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1280
vars[i + k].aconnector = params[i].aconnector;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1281
vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1282
vars[i + k].dsc_enabled = false;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1283
vars[i + k].bpp_x16 = 0;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1285
vars[i + k].pbn);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1291
set_dsc_configs_from_fairness_vars(params, vars, count, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1297
log_dsc_params(count, vars, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1303
vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1304
vars[i + k].dsc_enabled = true;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1305
vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1307
params[i].port, vars[i + k].pbn);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1311
vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1312
vars[i + k].dsc_enabled = false;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1313
vars[i + k].bpp_x16 = 0;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1315
params[i].port, vars[i + k].pbn);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1324
log_dsc_params(count, vars, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1328
ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1334
log_dsc_params(count, vars, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1337
ret = try_disable_dsc(state, dc_link, params, vars, count, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1343
log_dsc_params(count, vars, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1345
set_dsc_configs_from_fairness_vars(params, vars, count, k);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
912
int k)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
925
if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
938
params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
948
params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
962
vars[i + k].pbn);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
995
int k)
drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h
186
int i, j, k;
drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h
538
for (k = 0; k < 8; k++) {
drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h
541
i, j, k, bw_fixed_to_int(data->line_source_transfer_time[i][j][k]));
drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h
543
i, j, k,
drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h
544
bw_fixed_to_int(data->dram_speed_change_line_source_transfer_time[i][j][k]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1205
for (k = 0; k <= 7; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1211
data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1258
data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1261
data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1267
data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1288
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1289
if (data->enable[k]) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1292
data->display_pstate_change_enable[k] = 0;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1328
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1329
if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1330
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1331
data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1332
data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k]))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1336
else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1337
data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1341
data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1342
data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1346
else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1347
data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1389
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1390
if (data->enable[k]) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1391
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1392
data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1397
data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k]))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1399
data->display_pstate_change_enable[k] = 1;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1406
data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1411
data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1413
data->display_pstate_change_enable[k] = 1;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1424
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1425
if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1433
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1434
if (data->enable[k]) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1435
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1436
data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1437
data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1440
data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1441
data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1798
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1799
if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1800
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1802
if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1803
data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1808
if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
1809
data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2012
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2013
data->output_bpphdmi[k] = bw_def_na;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2014
data->output_bppdp4_lane_hbr[k] = bw_def_na;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2015
data->output_bppdp4_lane_hbr2[k] = bw_def_na;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2016
data->output_bppdp4_lane_hbr3[k] = bw_def_na;
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2017
if (data->enable[k]) {
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2018
data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2020
data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2023
data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
2026
data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
98
int32_t i, j, k;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
133
int k;
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
140
for (k = 0; k < MAX_PIPES; k++)
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
141
if (stream == context->res_ctx.pipe_ctx[k].stream) {
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
142
pipe_ctx = &context->res_ctx.pipe_ctx[k];
drivers/gpu/drm/amd/display/dc/core/dc.c
1629
int i, j, k;
drivers/gpu/drm/amd/display/dc/core/dc.c
1702
for (k = 0; k < group_size; k++) {
drivers/gpu/drm/amd/display/dc/core/dc.c
1703
struct dc_stream_status *status = dc_state_get_stream_status(ctx, pipe_set[k]->stream);
drivers/gpu/drm/amd/display/dc/core/dc.c
1710
if (k == 0)
drivers/gpu/drm/amd/display/dc/core/dc.c
2129
int i, k, l;
drivers/gpu/drm/amd/display/dc/core/dc.c
2283
for (k = 0; k < MAX_PIPES; k++) {
drivers/gpu/drm/amd/display/dc/core/dc.c
2284
pipe = &context->res_ctx.pipe_ctx[k];
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4184
int i, j, k;
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4273
for (k = 0; k < del_streams[i]->num_wb_info; k++)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
4274
add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k];
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
451
int i = 0, k = 0;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
486
for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
497
config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
498
config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
499
config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
500
config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
501
dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
502
k++;
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
503
int k;
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
510
for (k = 0; k < MAX_PIPES; k++)
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
511
if (stream == context->res_ctx.pipe_ctx[k].stream) {
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
512
pipe_ctx = &context->res_ctx.pipe_ctx[k];
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
346
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
386
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
387
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
388
hw_points += (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
392
for (k = 0; k < (region_end - region_start); k++) {
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
393
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
394
start_index = (region_start + k + MAX_LOW_POINT) *
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
474
k = 0;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
476
if (seg_distr[k] != -1) {
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
477
lut_params->arr_curve_points[k].segments_num =
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
478
seg_distr[k];
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
480
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
482
k++;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
485
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
486
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
551
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
575
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
576
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
577
hw_points += (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
581
for (k = 0; k < (region_end - region_start); k++) {
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
582
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
583
start_index = (region_start + k + MAX_LOW_POINT) *
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
651
k = 0;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
653
if (seg_distr[k] != -1) {
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
654
lut_params->arr_curve_points[k].segments_num =
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
655
seg_distr[k];
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
657
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
659
k++;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
662
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
663
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
123
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
164
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
165
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
166
hw_points += (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
175
for (k = 0; k < (region_end - region_start); k++) {
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
176
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
177
start_index = (region_start + k + MAX_LOW_POINT) *
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
236
k = 0;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
238
if (seg_distr[k] != -1) {
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
239
lut_params->arr_curve_points[k].segments_num =
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
240
seg_distr[k];
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
242
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
244
k++;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
247
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
248
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1010
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1011
v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
102
v->vtaps[k] = v->acceptable_quality_vta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1020
int k;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1025
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1026
v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1037
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1038
v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
104
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1040
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1041
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1045
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1049
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
105
v->vta_pschroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1053
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
106
v->hta_pschroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1061
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1062
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1065
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1076
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1080
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1091
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1099
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
110
v->vta_pschroma[k] = v->override_vta_pschroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1100
if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1109
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
111
v->hta_pschroma[k] = v->override_hta_pschroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1113
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1122
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1136
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1137
v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
114
v->vta_pschroma[k] = v->acceptable_quality_vta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1140
v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1144
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
115
v->hta_pschroma[k] = v->acceptable_quality_hta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1150
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1155
v->swath_height_y[k] = v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1156
v->swath_height_c[k] = v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1159
v->swath_height_y[k] = v->minimum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1160
v->swath_height_c[k] = v->minimum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1162
if (v->swath_height_c[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1163
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1164
v->det_buffer_size_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1166
else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1167
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1168
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1171
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1172
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1178
int k;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1183
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1184
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1185
v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1188
v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1190
v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1191
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1192
v->pscl_throughput_chroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1196
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1197
v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1200
v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1202
v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1206
v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1207
v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1210
v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1211
v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1228
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1229
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1249
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
125
int k;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1250
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1251
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1254
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1257
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1258
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1259
v->byte_per_pixel_dety[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1260
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1262
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1263
v->byte_per_pixel_dety[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1264
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1266
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1267
v->byte_per_pixel_dety[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1268
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1270
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1271
v->byte_per_pixel_dety[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1272
v->byte_per_pixel_detc[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1275
v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1276
v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1280
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1281
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1282
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1283
v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1287
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1288
v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1289
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1290
v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1295
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1296
if (v->v_ratio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1297
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1300
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1302
v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1303
v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1304
if (v->byte_per_pixel_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1305
v->display_pipe_line_delivery_time_chroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1308
if (v->v_ratio[k] / 2.0 <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1309
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
131
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1312
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1314
v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1315
v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
132
if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1328
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1329
if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1341
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1342
v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1343
v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1344
v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1345
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1346
v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1347
v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1348
v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1351
v->lines_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1352
v->lines_in_detc_rounded_down_to_swath[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1353
v->full_det_buffering_time_c[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1357
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1358
if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1359
v->min_full_det_buffering_time = v->full_det_buffering_time_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1360
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1362
if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1363
v->min_full_det_buffering_time = v->full_det_buffering_time_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1364
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1368
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1369
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1370
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1373
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1375
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1376
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1379
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
139
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1391
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1393
v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
140
if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1403
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1404
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1405
v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1408
v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1410
v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1413
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1414
v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1422
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1423
v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1424
v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1425
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1426
v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1427
v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1428
v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1431
v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1435
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1436
v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1443
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1444
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1445
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1448
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1457
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
146
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1461
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
147
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1470
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1471
v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1472
v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1473
v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1475
v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
148
v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1480
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1481
v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1484
v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1492
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1496
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1500
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
151
v->swath_width_ysingle_dpp[k] = v->viewport_height[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1514
v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1515
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1516
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1518
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1519
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1522
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1528
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1529
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
153
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1530
v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1531
v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1532
v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1534
v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1539
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
154
v->byte_per_pixel_in_dety[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1540
v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1543
v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
155
v->byte_per_pixel_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1551
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1555
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1559
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
157
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1573
v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1574
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1575
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1577
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1578
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
158
v->byte_per_pixel_in_dety[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1581
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
159
v->byte_per_pixel_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1593
v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1594
v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1595
v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1596
v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1597
v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1598
if (v->v_init_pre_fill_y[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1599
v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1602
v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1605
v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1606
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1607
v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1608
v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1609
if (v->v_init_pre_fill_c[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
161
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1610
v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1613
v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1618
v->max_num_swath_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
162
v->byte_per_pixel_in_dety[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1621
v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1624
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1626
v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1629
v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
163
v->byte_per_pixel_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1642
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1643
v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1644
if (v->dpp_per_plane[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1645
v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1647
if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
165
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1653
v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1655
v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1656
v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1657
v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1658
v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
166
v->byte_per_pixel_in_dety[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1668
v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1669
if (v->destination_lines_for_prefetch[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
167
v->byte_per_pixel_in_detc[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1670
v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1673
v->prefetch_bandwidth[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1677
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1678
v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1681
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1682
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1683
v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1687
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1688
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1689
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1690
v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1693
v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1697
v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1699
v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
170
v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1700
if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1701
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1702
v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1705
v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1709
v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
171
v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1711
v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1712
v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1714
v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1715
if ((v->swath_height_y[k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1716
if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1717
v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1720
v->v_ratio_prefetch_y[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1725
v->v_ratio_prefetch_y[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1727
v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1729
v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1730
if ((v->swath_height_c[k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1731
if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1732
v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1735
v->v_ratio_prefetch_c[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1740
v->v_ratio_prefetch_c[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1742
v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1744
v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1749
v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
175
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1750
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1751
v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k]));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1753
if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1756
if (v->destination_lines_for_prefetch[k] < 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1759
if (v->max_vstartup_lines[k] > v->v_startup_lines) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
176
v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1760
if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1763
if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1766
if (v->destination_lines_for_prefetch[k] < 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
177
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
178
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1781
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1782
if (v->v_ratio_prefetch_y[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1783
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1786
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1788
if (v->byte_per_pixel_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1789
v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1792
if (v->v_ratio_prefetch_c[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1793
v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1796
v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
180
if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1802
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1804
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1805
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1806
v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1809
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
181
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1810
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1811
v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1814
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1815
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1816
v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1822
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1823
v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1825
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1826
v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1827
v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1828
v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1829
v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
183
else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1830
if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1831
v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1833
else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1839
if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
184
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1840
v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1842
else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1848
v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1849
v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1852
v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1854
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1855
v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1856
v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1859
v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1861
v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1864
v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1866
if (v->output_format[k] == dcn_bw_444) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1867
v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
187
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1870
v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1872
if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1873
v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1876
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1877
if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1878
v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1881
v->v_blank_dram_clock_change_latency_margin[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1887
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1888
if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
189
v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1890
v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1891
v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1893
else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1894
v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1898
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1899
if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1900
v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
192
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1924
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1925
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1926
v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1928
else if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1929
v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
193
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
194
v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
196
else if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
197
v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
200
v->write_bandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
202
v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
206
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
207
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
241
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
242
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
245
else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
262
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
263
if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
264
if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
265
v->required_output_bw = v->pixel_clock[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
268
v->required_output_bw = v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
271
else if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
272
v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
275
v->required_output_bw = v->pixel_clock[k] * 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
277
if (v->output[k] == dcn_bw_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
278
v->required_phyclk[k] = v->required_output_bw;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
279
switch (v->output_deep_color[k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
281
v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
284
v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
289
v->required_phyclk[k] = v->required_phyclk[k] / 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
291
else if (v->output[k] == dcn_bw_dp) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
292
v->required_phyclk[k] = v->required_output_bw / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
295
v->required_phyclk[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
300
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
301
if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
309
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
310
if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
322
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
323
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
324
v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
327
v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
329
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
330
v->pscl_factor_chroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
331
v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
334
if (v->h_ratio[k] / 2.0 > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
335
v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
338
v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
340
v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
343
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
344
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
345
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
346
v->read256_block_height_y[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
348
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
349
v->read256_block_height_y[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
352
v->read256_block_height_y[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
354
v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
355
v->read256_block_height_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
356
v->read256_block_width_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
359
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
360
v->read256_block_height_y[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
361
v->read256_block_height_c[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
363
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
364
v->read256_block_height_y[k] = 16.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
365
v->read256_block_height_c[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
368
v->read256_block_height_y[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
369
v->read256_block_height_c[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
371
v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
372
v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
374
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
375
v->max_swath_height_y[k] = v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
376
v->max_swath_height_c[k] = v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
379
v->max_swath_height_y[k] = v->read256_block_width_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
380
v->max_swath_height_c[k] = v->read256_block_width_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
382
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
383
if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
384
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
387
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
389
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
392
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
393
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
394
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
396
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
397
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
399
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
402
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
405
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
406
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
408
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
411
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
415
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
416
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
419
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
42
int k;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
425
v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
426
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
427
v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
43
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
430
v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
432
v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
439
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
440
v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
442
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
445
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
45
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
451
if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
452
v->no_of_dpp[i][j][k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
456
v->no_of_dpp[i][j][k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
46
v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
460
v->no_of_dpp[i][j][k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
464
v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
47
v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
470
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
471
v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
472
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
477
if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
478
v->no_of_dpp[i][j][k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
485
v->no_of_dpp[i][j][k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
491
v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
499
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
50
v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
500
if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
51
v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
518
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
521
v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
522
v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
523
v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
524
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
527
if (v->max_swath_height_c[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
528
v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
529
v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
530
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
535
v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
536
v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
539
v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
540
v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
542
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
543
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
546
else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
547
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
548
v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
55
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
551
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
552
v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
554
v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
555
v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
556
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
557
v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
56
v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
560
v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 / dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
561
v->effective_detlb_lines_chroma = dcn_bw_floor2(v->lines_in_det_chroma + dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
562
v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
570
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
571
if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
582
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
583
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
584
v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
59
v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
592
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
593
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
594
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
595
if (v->v_ratio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
596
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
599
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
603
if (v->v_ratio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
604
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
607
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
609
if (v->v_ratio[k] / 2.0 <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
61
v->v_ratio[k] = v->h_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
610
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
613
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
617
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
618
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
619
v->meta_req_height_y = 8.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
620
v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
621
v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
622
v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
624
v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
629
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
63
if (v->interlace_output[k] == 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
630
v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
633
v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
64
v->v_ratio[k] = 2.0 * v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
641
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
645
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
647
v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
649
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
651
v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
655
v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
66
if (v->underscan_output[k] == 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
661
v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
663
v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
664
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
665
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
667
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
668
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
67
v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
671
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
677
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
678
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
679
v->meta_req_height_c = 8.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
68
v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
680
v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
681
v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
682
v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
684
v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
689
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
690
v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
693
v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
701
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
705
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
707
v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
709
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
711
v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
715
v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
717
v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
722
v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
724
v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
725
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
726
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
728
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
729
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
73
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
732
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
74
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
744
v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
745
v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
746
v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
747
v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
748
v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
749
v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
75
v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
750
if (v->prefill_y[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
751
v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
754
v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
757
v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
758
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
759
v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
760
v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
761
v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
762
if (v->prefill_c[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
763
v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
766
v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
769
v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
77
else if (v->h_ratio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
772
v->prefetch_lines_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
774
v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
775
if (v->no_of_dpp[i][j][k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
776
v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
778
if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
785
v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
787
v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
788
v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
789
v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
795
v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
798
v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
802
v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
803
v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
804
v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
806
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
808
v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
810
v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
812
v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
815
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
817
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
818
v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
822
v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
826
v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
827
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
830
if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
836
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
837
v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
839
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
84
v->htaps[k] = v->override_hta_ps[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
840
v->total_immediate_flip_bytes[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
841
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
842
v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
845
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
846
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
847
v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
850
v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
852
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
853
v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
856
v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
858
v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
859
v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
860
v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
861
v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
863
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
864
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
865
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
866
v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
869
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
87
v->htaps[k] = v->acceptable_quality_hta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
872
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
873
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
874
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
875
v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
878
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
881
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
884
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
885
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
886
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
889
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
89
if (v->v_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
890
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
891
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
892
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
895
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
898
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
899
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
90
v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
900
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
901
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
904
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
907
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
910
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
911
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
912
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
916
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
917
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
918
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
92
else if (v->v_ratio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
921
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
925
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
926
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
932
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
933
if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
941
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
942
if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
951
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
952
if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
957
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
958
if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
99
v->vtaps[k] = v->override_vta_ps[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1085
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1086
if (v->source_scan[k] == dcn_bw_hor)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1087
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1089
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1091
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1092
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1093
v->byte_per_pixel_dety[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1094
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1095
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1096
v->byte_per_pixel_dety[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1097
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1098
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1099
v->byte_per_pixel_dety[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1100
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1101
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1102
v->byte_per_pixel_dety[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1103
v->byte_per_pixel_detc[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1105
v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1106
v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1111
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1112
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1113
dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1114
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1115
dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1117
v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
761
int i, input_idx, k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1034
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1038
for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1039
wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1040
wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2406
unsigned int i, closest_clk_lvl = 0, k = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2430
k++;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2432
s[k].state = k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2433
s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2434
s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2435
s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2436
s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2438
s[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2439
s[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2440
s[k].dram_bw_per_chan_gbps =
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2442
s[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2443
s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2444
s[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2445
s[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2447
k++;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1085
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1094
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1095
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1100
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1101
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1102
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1103
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1104
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1105
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1106
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1107
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1108
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1109
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1114
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1115
if (mode_lib->vba.HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1116
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1119
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1121
mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1125
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1131
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1133
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1136
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1138
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1139
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1140
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1143
if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1145
< 2 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1146
mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1149
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1150
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1151
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1152
mode_lib->vba.DPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1155
if (mode_lib->vba.HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1156
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1160
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1163
mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1167
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1172
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1174
mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1178
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1181
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1182
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1184
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1187
if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1189
< 2 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1191
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1194
mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1200
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1201
if (mode_lib->vba.BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1203
if (mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1207
mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1217
mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1221
} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1225
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1235
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1272
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1273
if (mode_lib->vba.DPPPerPlane[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1274
mode_lib->vba.DPPCLK_calculated[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1276
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1277
/ mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1282
mode_lib->vba.DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1287
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1288
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1290
mode_lib->vba.DPPCLK_calculated[k] * 255
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1293
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1298
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1299
if (mode_lib->vba.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1328
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1331
if (mode_lib->vba.SourceScan[k] == dm_horz)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1332
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1334
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1336
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1339
if (mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1340
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1344
mode_lib->vba.SwathWidthY[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1345
(double) mode_lib->vba.SwathWidthSingleDPPY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1347
mode_lib->vba.HActive[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1348
* mode_lib->vba.HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1350
if (mode_lib->vba.DPPPerPlane[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1351
mode_lib->vba.SwathWidthY[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1353
mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1354
/ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1359
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1360
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1361
mode_lib->vba.BytePerPixelDETY[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1362
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1363
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1364
mode_lib->vba.BytePerPixelDETY[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1365
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1366
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1367
mode_lib->vba.BytePerPixelDETY[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1368
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1369
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1370
mode_lib->vba.BytePerPixelDETY[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1371
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1372
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1373
mode_lib->vba.BytePerPixelDETY[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1374
mode_lib->vba.BytePerPixelDETC[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1376
mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1377
mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1382
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1383
mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1384
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1385
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1386
* mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1387
mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1388
/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1389
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1390
* mode_lib->vba.VRatio[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1393
k,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1394
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1395
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1396
mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1397
+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1402
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1404
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1405
if (mode_lib->vba.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1407
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1417
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1420
if (mode_lib->vba.VRatio[k] <= 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1421
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1422
(double) mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1423
* mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1424
/ mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1425
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1427
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1428
(double) mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1429
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1430
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1432
DataFabricLineDeliveryTimeLuma = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1433
* mode_lib->vba.SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1434
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1435
/ (mode_lib->vba.ReturnBW * mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1440
- mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1442
if (mode_lib->vba.BytePerPixelDETC[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1443
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1444
else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1445
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1446
mode_lib->vba.SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1447
* mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1448
/ (mode_lib->vba.HRatio[k] / 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1449
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1451
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1452
mode_lib->vba.SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1453
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1454
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1456
DataFabricLineDeliveryTimeChroma = mode_lib->vba.SwathWidthSingleDPPY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1457
* mode_lib->vba.SwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1458
* dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1460
* mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1466
- mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1489
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1490
if (mode_lib->vba.WritebackEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1491
mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1527
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1528
mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1529
/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1530
mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1531
mode_lib->vba.LinesInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1532
mode_lib->vba.SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1533
mode_lib->vba.FullDETBufferingTimeY[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1534
mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1535
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1536
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1537
/ mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1538
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1539
mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1540
/ mode_lib->vba.BytePerPixelDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1541
/ (mode_lib->vba.SwathWidthY[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1542
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1543
mode_lib->vba.LinesInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1544
mode_lib->vba.SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1545
mode_lib->vba.FullDETBufferingTimeC[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1546
mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1547
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1548
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1549
/ (mode_lib->vba.VRatio[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1551
mode_lib->vba.LinesInDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1552
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1553
mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1558
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1559
if (mode_lib->vba.FullDETBufferingTimeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1562
mode_lib->vba.FullDETBufferingTimeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1564
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1565
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1567
if (mode_lib->vba.FullDETBufferingTimeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1570
mode_lib->vba.FullDETBufferingTimeC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1572
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1573
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1578
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1579
if (mode_lib->vba.DCCEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1582
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1583
/ mode_lib->vba.DCCRate[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1585
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1586
/ mode_lib->vba.DCCRate[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1591
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1593
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1596
if (mode_lib->vba.DCCEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1599
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1601
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1607
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1609
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1638
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1640
mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1641
- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1642
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1660
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1661
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1662
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1664
1.1 * mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1666
mode_lib->vba.BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1668
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1669
1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1671
mode_lib->vba.BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1673
/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1675
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1676
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1677
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1678
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1679
mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1680
mode_lib->vba.PixelClock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1683
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1687
k,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1688
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1705
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1708
mode_lib->vba.LinesInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1710
mode_lib->vba.LinesInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1711
* mode_lib->vba.DPPCLK[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1712
* mode_lib->vba.BytePerPixelDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1713
* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1715
/ mode_lib->vba.DPPPerPlane[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1717
mode_lib->vba.SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1720
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1721
/ mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1723
* mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1724
* mode_lib->vba.BytePerPixelDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1726
/ mode_lib->vba.DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1728
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1731
mode_lib->vba.LinesInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1733
mode_lib->vba.LinesInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1734
* mode_lib->vba.DPPCLK[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1735
* mode_lib->vba.BytePerPixelDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1736
* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1738
/ mode_lib->vba.DPPPerPlane[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1740
mode_lib->vba.SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1743
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1744
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1745
/ (mode_lib->vba.VRatio[k] / 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1747
* (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1749
* mode_lib->vba.BytePerPixelDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1751
/ mode_lib->vba.DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1752
mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1756
mode_lib->vba.UrgentLatencySupportUs[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1762
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1765
mode_lib->vba.UrgentLatencySupportUs[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1773
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1774
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1775
mode_lib->vba.DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1777
if (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1778
|| mode_lib->vba.OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1782
if (mode_lib->vba.ODMCombineEnabled[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1783
mode_lib->vba.DSCCLK_calculated[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1784
mode_lib->vba.PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1790
mode_lib->vba.DSCCLK_calculated[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1791
mode_lib->vba.PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1801
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1802
double bpp = mode_lib->vba.OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1803
unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1805
if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1806
if (!mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1807
mode_lib->vba.DSCDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1809
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1812
(double) mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1813
/ mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1816
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1818
mode_lib->vba.OutputFormat[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1820
mode_lib->vba.DSCDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1823
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1826
(double) mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1827
/ mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1830
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1832
mode_lib->vba.OutputFormat[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1834
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1835
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1836
/ mode_lib->vba.PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1838
mode_lib->vba.DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1842
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1844
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1846
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1849
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1858
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1859
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1860
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1861
dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1862
&mode_lib->vba.BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1863
&mode_lib->vba.BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1864
&mode_lib->vba.BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1865
&mode_lib->vba.BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1868
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1869
mode_lib->vba.BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1870
mode_lib->vba.BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1871
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1872
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1873
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1874
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1875
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1876
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1877
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1882
mode_lib->vba.PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1883
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1884
&mode_lib->vba.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1888
&mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1889
&mode_lib->vba.meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1890
mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1892
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1893
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1894
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1896
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1897
mode_lib->vba.ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1898
&mode_lib->vba.VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1899
&mode_lib->vba.MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1901
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1902
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1903
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1904
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1908
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1909
mode_lib->vba.BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1910
mode_lib->vba.BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1911
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1912
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1914
mode_lib->vba.BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1916
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1917
mode_lib->vba.ViewportWidth[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1918
mode_lib->vba.ViewportHeight[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1919
mode_lib->vba.SwathWidthY[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1924
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1926
&mode_lib->vba.MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1930
&mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1931
&mode_lib->vba.meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1932
mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1934
mode_lib->vba.VRatio[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1935
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1936
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1938
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1939
mode_lib->vba.ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1940
&mode_lib->vba.VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1941
&mode_lib->vba.MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1946
mode_lib->vba.MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1947
mode_lib->vba.PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1950
mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1951
mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1953
mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1957
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1958
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1959
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1960
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1963
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1964
mode_lib->vba.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1967
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1968
mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1969
&mode_lib->vba.meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1970
&mode_lib->vba.dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1971
&mode_lib->vba.qual_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1976
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1977
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1978
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1979
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1982
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1983
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1984
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1985
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1986
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1987
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1988
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1989
mode_lib->vba.WritebackDestinationWidth[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1992
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1994
if (mode_lib->vba.BlendingAndTiming[j] == k
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1996
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1998
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2015
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2017
if (mode_lib->vba.BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2018
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2022
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2023
mode_lib->vba.MaxVStartupLines[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2024
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2028
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2029
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2030
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2034
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2037
mode_lib->vba.MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2039
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2040
mode_lib->vba.cursor_bw[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2041
for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2042
mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2043
* mode_lib->vba.CursorBPP[k][j] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2044
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2045
* mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2060
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2061
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2065
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2066
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2068
mode_lib->vba.BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2070
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2071
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2087
mode_lib->vba.ErrorResult[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2090
mode_lib->vba.DPPCLK[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2092
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2094
mode_lib->vba.DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2095
mode_lib->vba.DPPPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2096
mode_lib->vba.ScalerEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2097
mode_lib->vba.NumberOfCursors[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2104
(unsigned int) (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2105
/ mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2106
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2107
mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2108
- mode_lib->vba.VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2109
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2113
mode_lib->vba.MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2116
mode_lib->vba.DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2117
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2118
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2119
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2123
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2124
mode_lib->vba.MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2125
mode_lib->vba.PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2126
mode_lib->vba.PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2127
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2128
mode_lib->vba.BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2129
mode_lib->vba.VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2130
mode_lib->vba.MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2131
mode_lib->vba.PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2132
mode_lib->vba.BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2133
mode_lib->vba.VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2134
mode_lib->vba.MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2135
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2136
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2138
mode_lib->vba.XFCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2140
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2142
&mode_lib->vba.DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2143
&mode_lib->vba.DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2144
&mode_lib->vba.DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2145
&mode_lib->vba.PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2146
&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2147
&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2148
&mode_lib->vba.VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2149
&mode_lib->vba.VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2150
&mode_lib->vba.RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2152
&mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2153
&mode_lib->vba.VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2154
&mode_lib->vba.VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2155
&mode_lib->vba.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2156
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2157
mode_lib->vba.VStartup[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2159
mode_lib->vba.MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2162
mode_lib->vba.VStartup[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2166
mode_lib->vba.VStartup[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2169
mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2173
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2175
if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2176
mode_lib->vba.prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2177
else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2178
mode_lib->vba.prefetch_vm_bw[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2179
(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2180
/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2181
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2182
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2184
mode_lib->vba.prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2187
if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2189
mode_lib->vba.prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2190
else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2191
mode_lib->vba.prefetch_row_bw[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2192
(double) (mode_lib->vba.MetaRowByte[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2193
+ mode_lib->vba.PixelPTEBytesPerRow[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2194
/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2195
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2196
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2198
mode_lib->vba.prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2203
MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2205
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2207
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2209
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2210
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2211
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2212
+ mode_lib->vba.meta_row_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2213
+ mode_lib->vba.dpte_row_bw[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2215
if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2217
if (mode_lib->vba.VRatioPrefetchY[k] > 4
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2218
|| mode_lib->vba.VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2238
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2241
- mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2243
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2244
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2245
+ mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2246
mode_lib->vba.PrefetchBandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2249
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2250
ImmediateFlipBytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2251
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2252
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2253
ImmediateFlipBytes[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2254
mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2255
+ mode_lib->vba.MetaRowByte[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2256
+ mode_lib->vba.PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2260
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2261
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2262
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2265
+ ImmediateFlipBytes[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2268
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2277
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2278
ImmediateFlipBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2279
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2280
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2281
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2282
mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2283
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2284
mode_lib->vba.MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2285
mode_lib->vba.PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2286
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2287
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2288
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2289
mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2290
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2291
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2292
&final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2293
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2295
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2298
+ mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2300
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2302
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2303
final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2305
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2306
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2307
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2313
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2314
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2322
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2323
if (mode_lib->vba.ErrorResult[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2337
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2338
if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2339
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2340
mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2341
/ mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2342
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2344
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2345
mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2346
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2347
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2349
if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2350
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2352
if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2353
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2354
mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2355
* mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2356
/ mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2357
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2359
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2360
mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2361
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2362
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2368
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2370
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2371
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2372
mode_lib->vba.MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2378
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2379
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2380
mode_lib->vba.MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2384
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2385
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2386
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2388
if (!mode_lib->vba.DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2389
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2390
+ mode_lib->vba.MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2396
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2397
mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2400
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2414
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2415
/ (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2417
mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2419
1)) - (mode_lib->vba.vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2426
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2427
/ (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2430
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2434
- (mode_lib->vba.VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2437
/ mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2438
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2441
/ (mode_lib->vba.VRatio[k] / 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2442
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2444
if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2446
/ mode_lib->vba.SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2447
} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2453
if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2455
/ (mode_lib->vba.SwathWidthY[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2456
} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2462
DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2464
MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2465
+ (mode_lib->vba.LinesInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2466
- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2467
/ mode_lib->vba.SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2468
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2469
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2478
* mode_lib->vba.SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2479
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2480
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2483
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2484
double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2485
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2489
mode_lib->vba.FullDETBufferingTimeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2490
+ (mode_lib->vba.LinesInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2491
- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2492
/ mode_lib->vba.SwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2493
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2494
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2506
* mode_lib->vba.SwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2507
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2508
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2510
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2514
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2518
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2521
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2525
/ (mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2526
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2527
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2528
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2529
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2532
} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2540
/ (mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2541
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2542
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2543
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2544
/ mode_lib->vba.PixelClock[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2552
/ (mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2553
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2554
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2555
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2556
/ mode_lib->vba.PixelClock[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2559
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2560
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2566
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2567
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2570
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2585
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2586
if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2595
for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2597
mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2600
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2601
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2604
mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2605
mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2606
mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2614
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2615
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2616
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2617
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2630
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2633
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2634
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2636
mode_lib->vba.XFCTransferDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2639
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2640
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2642
mode_lib->vba.XFCPrechargeDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2647
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2648
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2653
(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2654
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2655
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2656
/ mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2668
mode_lib->vba.XFCPrefetchMargin[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2671
+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2672
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2673
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2674
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2676
mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2677
mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2678
mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2679
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2680
mode_lib->vba.XFCPrechargeDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2681
mode_lib->vba.XFCTransferDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2682
mode_lib->vba.XFCPrefetchMargin[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2689
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2690
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2691
unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2692
* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2702
if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2704
mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2728
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2730
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2733
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2736
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2739
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2742
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2745
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2753
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2754
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2755
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2756
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2757
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2759
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2761
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2762
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2772
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2775
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2788
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2796
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2797
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2798
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2799
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2800
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2801
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2802
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2804
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2806
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2808
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2810
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2812
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2814
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2816
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2818
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2819
&& mode_lib->vba.SourceScan[k] != dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2826
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2829
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2830
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2833
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2834
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2843
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2844
SwathWidth = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2846
SwathWidth = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2849
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2853
if (mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2854
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2862
mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2864
if (mode_lib->vba.DPPPerPlane[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2867
SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2875
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2886
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2896
mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2897
mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2899
mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2900
mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2903
if (mode_lib->vba.SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2904
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2905
mode_lib->vba.DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2906
} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2907
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2909
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2912
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2914
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3288
unsigned int j, k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3295
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3296
if (mode_lib->vba.ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3297
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3298
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3299
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3300
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3301
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3302
|| mode_lib->vba.HRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3303
|| mode_lib->vba.htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3304
|| mode_lib->vba.VRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3305
|| mode_lib->vba.vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3307
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3308
|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3309
|| (mode_lib->vba.htaps[k] > 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3310
&& (mode_lib->vba.htaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3311
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3312
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3313
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3314
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3315
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3316
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3317
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3318
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3319
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3320
&& (mode_lib->vba.HRatio[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3321
> mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3322
|| mode_lib->vba.VRatio[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3323
> mode_lib->vba.VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3330
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3331
if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3332
&& mode_lib->vba.SourceScan[k] != dm_horz)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3333
|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3334
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3335
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3336
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3337
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3338
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3339
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3340
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3341
|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3342
&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3343
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3345
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3347
|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3348
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3350
&& !((mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3352
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3354
&& mode_lib->vba.SourceScan[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3358
&& mode_lib->vba.DCCEnable[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3360
|| (mode_lib->vba.DCCEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3361
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3363
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3365
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3372
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3373
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3374
locals->BytePerPixelInDETY[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3375
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3376
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3377
locals->BytePerPixelInDETY[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3378
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3379
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3380
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3381
locals->BytePerPixelInDETY[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3382
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3383
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3384
locals->BytePerPixelInDETY[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3385
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3386
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3387
locals->BytePerPixelInDETY[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3388
locals->BytePerPixelInDETC[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3390
locals->BytePerPixelInDETY[k] = 4.0 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3391
locals->BytePerPixelInDETC[k] = 8.0 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3393
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3394
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3396
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3399
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3400
locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3401
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3402
locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3403
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3404
locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3406
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3407
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3408
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3409
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3410
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3411
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3412
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3413
/ mode_lib->vba.PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3414
} else if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3415
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3416
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3417
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3418
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3419
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3420
/ mode_lib->vba.PixelClock[k]) * 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3421
} else if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3422
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3423
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3424
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3425
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3426
/ mode_lib->vba.PixelClock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3428
locals->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3432
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3433
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3496
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3497
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3498
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3499
if (locals->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3506
if (locals->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3534
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3535
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3536
if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3537
mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3540
+ mode_lib->vba.ActiveWritebacksPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3547
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3548
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3550
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3557
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3558
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3560
&& (mode_lib->vba.WritebackHRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3561
|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3564
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3565
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3567
|| mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3569
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3571
|| mode_lib->vba.WritebackLumaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3573
|| mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3575
|| mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3576
> mode_lib->vba.WritebackLumaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3577
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3578
> mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3579
|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3580
&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3582
|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3583
&& (mode_lib->vba.WritebackChromaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3585
|| mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3588
* mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3589
> mode_lib->vba.WritebackChromaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3591
* mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3592
> mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3593
|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3594
&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3597
if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3599
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3603
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3604
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3608
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3610
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3611
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3613
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3615
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3616
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3619
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3623
if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3628
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3629
&& mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3631
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3633
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3634
&& mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3637
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3646
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3647
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3652
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3653
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3654
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3655
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3656
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3657
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3658
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3659
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3660
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3661
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3665
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3666
if (mode_lib->vba.HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3667
locals->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3670
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3672
mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3676
locals->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3680
if (locals->BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3681
locals->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3682
locals->MinDPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3683
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3685
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3688
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3689
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3690
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3691
/ locals->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3693
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3694
&& locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3695
< 2.0 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3696
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3697
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3700
if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3701
locals->PSCL_FACTOR_CHROMA[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3705
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3708
mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3712
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3716
locals->MinDPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3717
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3719
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3722
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3723
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3724
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3725
/ locals->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3726
mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3730
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3732
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3733
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3735
/ locals->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3737
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3738
|| mode_lib->vba.HTAPsChroma[k] > 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3739
|| mode_lib->vba.VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3740
&& locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3741
< 2.0 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3742
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3743
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3747
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3749
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3750
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3751
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3752
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3753
&locals->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3754
&locals->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3755
&locals->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3756
&locals->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3757
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3758
locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3759
locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3761
locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3762
locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3764
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3765
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3766
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3767
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3768
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3769
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3770
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3771
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3773
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3775
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3777
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3779
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3781
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3783
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3785
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3786
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3788
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3791
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3793
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3794
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3795
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3796
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3797
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3798
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3800
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3801
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3802
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3803
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3805
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3807
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3808
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3811
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3820
/ (locals->BytePerPixelInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3821
* locals->MinSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3822
+ locals->BytePerPixelInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3824
* locals->MinSwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3825
if (locals->BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3828
* dml_max(mode_lib->vba.HRatio[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3829
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3830
/ (mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3833
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3842
mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3844
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3845
/ (mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3848
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3854
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3857
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3858
/ (mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3861
mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3867
locals->MaximumSwathWidth[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3881
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3883
mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3887
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3890
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3894
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3897
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3901
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3903
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3904
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3909
if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3910
&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3911
&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3912
locals->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3913
locals->RequiredDPPCLK[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3914
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3916
locals->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3917
locals->RequiredDPPCLK[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3918
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3923
if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3930
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3931
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3940
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3941
if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3942
BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3943
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3956
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3957
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3958
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3959
locals->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3960
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3963
locals->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3964
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3969
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3973
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3979
if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3985
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3986
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4001
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4002
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4003
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4004
> locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4008
if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4027
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4028
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4041
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4042
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4043
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4044
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4049
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4050
locals->RequiresDSC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4051
locals->RequiresFEC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4052
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4053
if (mode_lib->vba.Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4054
locals->RequiresDSC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4055
locals->RequiresFEC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4056
locals->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4057
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4059
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4060
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4061
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4062
} else if (mode_lib->vba.Output[k] == dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4063
|| mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4064
if (mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4073
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4075
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4076
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4077
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4080
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4082
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4083
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4084
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4085
if (mode_lib->vba.DSCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4086
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4087
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4088
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4090
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4094
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4095
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4097
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4102
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4104
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4105
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4106
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4109
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4111
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4112
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4113
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4114
if (mode_lib->vba.DSCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4115
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4116
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4117
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4119
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4123
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4124
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4126
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4133
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4135
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4136
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4137
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4140
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4142
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4143
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4144
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4145
if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4146
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4147
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4148
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4150
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4154
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4155
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4157
locals->OutputBppPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4162
locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4168
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4169
if (!mode_lib->vba.skip_dio_check[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4170
&& (locals->OutputBppPerState[i][k] == BPP_INVALID
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4171
|| (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4172
&& mode_lib->vba.Interlace[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4179
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4181
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4182
if ((mode_lib->vba.Output[k] == dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4183
|| mode_lib->vba.Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4184
if (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4185
|| mode_lib->vba.OutputFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4191
if (locals->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4192
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4193
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4199
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4213
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4214
if (locals->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4215
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4231
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4232
if (mode_lib->vba.BlendingAndTiming[k] != k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4234
} else if (locals->RequiresDSC[i][k] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4235
|| locals->RequiresDSC[i][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4237
} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4239
mode_lib->vba.PixelClockBackEnd[k] / 400.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4241
} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4243
} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4245
} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4250
if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4251
|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4254
mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4256
if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4257
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4258
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4260
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4263
mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4267
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4269
mode_lib->vba.OutputFormat[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4271
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4273
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4275
dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4277
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4278
+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4280
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4281
locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4283
locals->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4286
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4289
if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4290
locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4299
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4300
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4301
locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4303
locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4304
locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4305
locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4306
+ locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4307
if (locals->SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4310
if (locals->MaxSwathHeightC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4311
locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4313
locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4314
+ locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4316
if (locals->SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4323
locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4324
locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4326
locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4327
locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4330
if (locals->BytePerPixelInDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4331
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4333
} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4334
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4335
locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4336
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4338
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4339
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4343
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4344
/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4347
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4348
/ (locals->SwathWidthYPerState[i][j][k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4349
/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4352
locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4353
locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4355
locals->SwathHeightYPerState[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4359
locals->BytePerPixelInDETC[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4360
locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i][0],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4362
locals->SwathHeightCPerState[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4367
if (locals->BytePerPixelInDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4368
locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4369
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4370
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4372
locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4373
locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4374
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4375
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4376
locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) -
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4377
locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4378
dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4387
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4388
if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4399
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4400
if (locals->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4402
locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4412
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4413
locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4414
locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4415
locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4416
locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4417
locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4420
mode_lib->vba.PixelClock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4421
if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4422
if (mode_lib->vba.VRatio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4428
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4431
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4432
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4433
/ mode_lib->vba.NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4440
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4443
* mode_lib->vba.PSCL_FACTOR[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4444
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4447
if (mode_lib->vba.VRatio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4453
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4456
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4457
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4458
/ mode_lib->vba.NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4465
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4468
* mode_lib->vba.PSCL_FACTOR[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4469
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4471
if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4477
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4480
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4482
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4483
/ mode_lib->vba.NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4490
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4493
* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4494
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4498
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4501
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4502
mode_lib->vba.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4503
mode_lib->vba.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4504
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4505
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4506
dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4507
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4508
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4509
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4510
mode_lib->vba.SwathWidthYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4515
mode_lib->vba.PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4516
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4517
&mode_lib->vba.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4520
&mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4521
&mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4522
&mode_lib->vba.meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4523
mode_lib->vba.PrefetchLinesY[0][0][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4525
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4526
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4527
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4529
mode_lib->vba.SwathHeightYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4530
mode_lib->vba.ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4531
&mode_lib->vba.PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4532
&mode_lib->vba.MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4533
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4534
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4535
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4536
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4537
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4540
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4541
mode_lib->vba.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4542
mode_lib->vba.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4543
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4544
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4545
dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4546
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4547
mode_lib->vba.ViewportWidth[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4548
mode_lib->vba.ViewportHeight[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4549
mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4554
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4556
&mode_lib->vba.MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4559
&mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4560
&mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4561
&mode_lib->vba.meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4562
mode_lib->vba.PrefetchLinesC[0][0][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4564
mode_lib->vba.VRatio[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4565
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4566
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4568
mode_lib->vba.SwathHeightCPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4569
mode_lib->vba.ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4570
&mode_lib->vba.PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4571
&mode_lib->vba.MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4576
locals->PrefetchLinesC[0][0][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4577
locals->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4580
locals->PDEAndMetaPTEBytesPerFrame[0][0][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4582
locals->MetaRowBytes[0][0][k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4583
locals->DPTEBytesPerRow[0][0][k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4587
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4588
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4589
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4590
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4593
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4594
mode_lib->vba.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4597
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4598
mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4599
&mode_lib->vba.meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4600
&mode_lib->vba.dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4601
&mode_lib->vba.qual_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4619
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4620
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4621
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4622
locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4624
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4625
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4626
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4627
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4628
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4629
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4630
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4631
mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4633
locals->WritebackDelay[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4636
if (mode_lib->vba.BlendingAndTiming[m] == k
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4639
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4653
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4655
if (mode_lib->vba.BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4656
locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4660
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4661
for (m = 0; m < locals->NumberOfCursors[k]; m++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4662
locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4663
/ 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4666
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4667
locals->MaximumVStartup[0][0][k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4668
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4681
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4683
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4687
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4688
locals->SwathWidthYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4689
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4690
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4706
mode_lib->vba.IsErrorResult[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4709
mode_lib->vba.RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4711
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4713
mode_lib->vba.DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4714
mode_lib->vba.NoOfDPP[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4715
mode_lib->vba.ScalerEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4716
mode_lib->vba.NumberOfCursors[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4723
mode_lib->vba.SwathWidthYPerState[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4724
/ mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4725
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4726
mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4727
- mode_lib->vba.VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4728
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4730
mode_lib->vba.MaximumVStartup[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4733
mode_lib->vba.DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4734
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4735
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4736
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4740
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4741
mode_lib->vba.MetaRowBytes[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4742
mode_lib->vba.DPTEBytesPerRow[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4743
mode_lib->vba.PrefetchLinesY[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4744
mode_lib->vba.SwathWidthYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4745
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4746
mode_lib->vba.PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4747
mode_lib->vba.MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4748
mode_lib->vba.PrefetchLinesC[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4749
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4750
mode_lib->vba.PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4751
mode_lib->vba.MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4752
mode_lib->vba.SwathHeightYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4753
mode_lib->vba.SwathHeightCPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4755
mode_lib->vba.XFCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4757
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4761
&mode_lib->vba.LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4762
&mode_lib->vba.PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4763
&mode_lib->vba.LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4764
&mode_lib->vba.LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4765
&mode_lib->vba.VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4766
&mode_lib->vba.VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4767
&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4769
&mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4770
&mode_lib->vba.VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4771
&mode_lib->vba.VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4772
&mode_lib->vba.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4778
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4779
if (locals->PDEAndMetaPTEBytesPerFrame[0][0][k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4780
locals->prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4781
else if (locals->LinesForMetaPTE[k] > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4782
locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[0][0][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4783
/ (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4785
locals->prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4788
if (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4789
locals->prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4790
else if (locals->LinesForMetaAndDPTERow[k] > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4791
locals->prefetch_row_bw[k] = (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4792
/ (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4794
locals->prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4799
+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4802
+ mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4804
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4805
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4806
dml_max(mode_lib->vba.ReadBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4807
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4808
+ mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4819
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4820
if (locals->LineTimesForPrefetch[k] < 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4821
|| locals->LinesForMetaPTE[k] >= 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4822
|| locals->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4823
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4828
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4829
if (locals->VRatioPreY[i][j][k] > 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4830
|| locals->VRatioPreC[i][j][k] > 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4831
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4842
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4845
- mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4847
mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4848
mode_lib->vba.PrefetchBW[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4850
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4851
mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4852
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4853
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4854
mode_lib->vba.ImmediateFlipBytes[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4855
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4856
+ mode_lib->vba.MetaRowBytes[0][0][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4857
+ mode_lib->vba.DPTEBytesPerRow[0][0][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4861
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4862
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4863
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4866
+ mode_lib->vba.ImmediateFlipBytes[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4870
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4879
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4880
mode_lib->vba.ImmediateFlipBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4881
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4882
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4883
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4884
mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4885
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4886
mode_lib->vba.MetaRowBytes[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4887
mode_lib->vba.DPTEBytesPerRow[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4888
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4889
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4890
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4891
mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4892
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4893
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4894
&mode_lib->vba.final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4895
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4898
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4901
+ mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4903
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4904
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4905
mode_lib->vba.final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4907
mode_lib->vba.ReadBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4908
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4915
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4916
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4928
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4929
mode_lib->vba.MaxTotalVActiveRDBandwidth = mode_lib->vba.MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4945
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4946
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4947
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4955
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4957
if (mode_lib->vba.CursorWidth[k][j] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4963
/ (mode_lib->vba.CursorWidth[k][j]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4964
* mode_lib->vba.CursorBPP[k][j]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4967
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4968
/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4969
|| (mode_lib->vba.CursorBPP[k][j] == 64.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4979
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4980
locals->AlignedYPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4981
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4982
locals->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4983
if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4986
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4987
locals->AlignedDCCMetaPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4989
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4990
mode_lib->vba.ViewportWidth[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4991
64.0 * locals->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4993
locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4995
if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4998
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4999
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5000
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5001
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5002
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5003
locals->AlignedCPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5005
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5006
mode_lib->vba.ViewportWidth[k] / 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5007
locals->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5009
locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5011
if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5090
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5091
mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5092
locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5103
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5104
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5105
mode_lib->vba.ODMCombineEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5106
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5108
mode_lib->vba.ODMCombineEnabled[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5110
mode_lib->vba.DSCEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5111
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5112
mode_lib->vba.OutputBpp[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5113
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1145
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1154
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1155
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1160
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1161
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1162
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1163
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1164
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1165
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1166
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1167
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1168
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1169
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1174
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1175
if (mode_lib->vba.HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1176
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1179
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1181
mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1185
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1191
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1193
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1196
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1198
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1199
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1200
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1203
if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1205
< 2 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1206
mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1209
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1210
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1211
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1212
mode_lib->vba.DPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1215
if (mode_lib->vba.HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1216
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1220
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1223
mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1227
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1232
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1234
mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1238
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1241
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1242
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1244
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1247
if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1249
< 2 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1251
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1254
mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1260
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1261
if (mode_lib->vba.BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1263
if (mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1267
mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1277
mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1281
} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1285
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1295
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1332
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1333
if (mode_lib->vba.DPPPerPlane[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1334
mode_lib->vba.DPPCLK_calculated[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1336
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1337
/ mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1342
mode_lib->vba.DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1347
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1348
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1350
mode_lib->vba.DPPCLK_calculated[k] * 255
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1353
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1358
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1359
if (mode_lib->vba.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1388
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1391
if (mode_lib->vba.SourceScan[k] == dm_horz)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1392
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1394
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1396
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1399
if (mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1400
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1404
mode_lib->vba.SwathWidthY[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1405
(double) mode_lib->vba.SwathWidthSingleDPPY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1407
mode_lib->vba.HActive[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1408
* mode_lib->vba.HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1410
if (mode_lib->vba.DPPPerPlane[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1411
mode_lib->vba.SwathWidthY[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1413
mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1414
/ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1419
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1420
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1421
mode_lib->vba.BytePerPixelDETY[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1422
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1423
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1424
mode_lib->vba.BytePerPixelDETY[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1425
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1426
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1427
mode_lib->vba.BytePerPixelDETY[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1428
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1429
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1430
mode_lib->vba.BytePerPixelDETY[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1431
mode_lib->vba.BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1432
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1433
mode_lib->vba.BytePerPixelDETY[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1434
mode_lib->vba.BytePerPixelDETC[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1436
mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1437
mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1442
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1443
mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1444
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1445
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1446
* mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1447
mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1448
/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1449
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1450
* mode_lib->vba.VRatio[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1453
k,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1454
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1455
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1456
mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1457
+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1462
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1464
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1465
if (mode_lib->vba.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1467
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1477
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1478
if (mode_lib->vba.VRatio[k] <= 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1479
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1480
(double) mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1481
* mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1482
/ mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1483
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1485
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1486
(double) mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1487
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1488
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1490
if (mode_lib->vba.BytePerPixelDETC[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1491
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1492
else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1493
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1494
mode_lib->vba.SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1495
* mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1496
/ (mode_lib->vba.HRatio[k] / 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1497
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1499
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1500
mode_lib->vba.SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1501
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1502
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1525
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1526
if (mode_lib->vba.WritebackEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1527
mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1563
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1564
mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1565
/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1566
mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1567
mode_lib->vba.LinesInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1568
mode_lib->vba.SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1569
mode_lib->vba.FullDETBufferingTimeY[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1570
mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1571
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1572
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1573
/ mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1574
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1575
mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1576
/ mode_lib->vba.BytePerPixelDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1577
/ (mode_lib->vba.SwathWidthY[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1578
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1579
mode_lib->vba.LinesInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1580
mode_lib->vba.SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1581
mode_lib->vba.FullDETBufferingTimeC[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1582
mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1583
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1584
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1585
/ (mode_lib->vba.VRatio[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1587
mode_lib->vba.LinesInDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1588
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1589
mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1594
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1595
if (mode_lib->vba.FullDETBufferingTimeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1598
mode_lib->vba.FullDETBufferingTimeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1600
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1601
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1603
if (mode_lib->vba.FullDETBufferingTimeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1606
mode_lib->vba.FullDETBufferingTimeC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1608
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1609
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1614
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1615
if (mode_lib->vba.DCCEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1618
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1619
/ mode_lib->vba.DCCRate[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1621
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1622
/ mode_lib->vba.DCCRate[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1627
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1629
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1632
if (mode_lib->vba.DCCEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1635
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1637
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1643
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1645
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1674
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1676
mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1677
- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1678
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1696
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1697
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1698
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1700
1.1 * mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1702
mode_lib->vba.BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1704
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1705
1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1707
mode_lib->vba.BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1709
/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1711
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1712
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1713
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1714
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1715
mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1716
mode_lib->vba.PixelClock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1719
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1723
k,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1724
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1741
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1744
mode_lib->vba.LinesInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1746
mode_lib->vba.LinesInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1747
* mode_lib->vba.DPPCLK[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1748
* mode_lib->vba.BytePerPixelDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1749
* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1751
/ mode_lib->vba.DPPPerPlane[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1753
mode_lib->vba.SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1756
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1757
/ mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1759
* mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1760
* mode_lib->vba.BytePerPixelDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1762
/ mode_lib->vba.DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1764
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1767
mode_lib->vba.LinesInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1769
mode_lib->vba.LinesInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1770
* mode_lib->vba.DPPCLK[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1771
* mode_lib->vba.BytePerPixelDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1772
* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1774
/ mode_lib->vba.DPPPerPlane[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1776
mode_lib->vba.SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1779
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1780
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1781
/ (mode_lib->vba.VRatio[k] / 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1783
* (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1785
* mode_lib->vba.BytePerPixelDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1787
/ mode_lib->vba.DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1788
mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1792
mode_lib->vba.UrgentLatencySupportUs[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1798
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1801
mode_lib->vba.UrgentLatencySupportUs[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1809
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1810
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1811
mode_lib->vba.DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1813
if (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1814
|| mode_lib->vba.OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1818
if (mode_lib->vba.ODMCombineEnabled[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1819
mode_lib->vba.DSCCLK_calculated[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1820
mode_lib->vba.PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1826
mode_lib->vba.DSCCLK_calculated[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1827
mode_lib->vba.PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1837
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1838
double bpp = mode_lib->vba.OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1839
unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1841
if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1842
if (!mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1843
mode_lib->vba.DSCDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1845
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1848
(double) mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1849
/ mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1852
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1854
mode_lib->vba.OutputFormat[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1856
mode_lib->vba.DSCDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1859
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1862
(double) mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1863
/ mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1866
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1868
mode_lib->vba.OutputFormat[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1870
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1871
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1872
/ mode_lib->vba.PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1874
mode_lib->vba.DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1878
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1880
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1882
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1885
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1894
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1895
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1896
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1897
dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1898
&mode_lib->vba.BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1899
&mode_lib->vba.BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1900
&mode_lib->vba.BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1901
&mode_lib->vba.BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1904
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1905
mode_lib->vba.BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1906
mode_lib->vba.BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1907
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1908
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1909
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1910
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1911
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1912
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1913
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1918
mode_lib->vba.PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1919
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1920
&mode_lib->vba.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1924
&mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1925
&mode_lib->vba.meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1926
mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1928
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1929
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1930
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1932
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1933
mode_lib->vba.ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1934
&mode_lib->vba.VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1935
&mode_lib->vba.MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1937
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1938
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1939
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1940
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1944
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1945
mode_lib->vba.BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1946
mode_lib->vba.BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1947
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1948
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1950
mode_lib->vba.BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1952
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1953
mode_lib->vba.ViewportWidth[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1954
mode_lib->vba.ViewportHeight[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1955
mode_lib->vba.SwathWidthY[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1960
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1962
&mode_lib->vba.MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1966
&mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1967
&mode_lib->vba.meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1968
mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1970
mode_lib->vba.VRatio[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1971
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1972
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1974
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1975
mode_lib->vba.ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1976
&mode_lib->vba.VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1977
&mode_lib->vba.MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1982
mode_lib->vba.MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1983
mode_lib->vba.PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1986
mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1987
mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1989
mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1993
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1994
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1995
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1996
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1999
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2000
mode_lib->vba.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2003
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2004
mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2005
&mode_lib->vba.meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2006
&mode_lib->vba.dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2007
&mode_lib->vba.qual_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2012
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2013
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2014
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2015
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2018
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2019
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2020
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2021
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2022
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2023
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2024
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2025
mode_lib->vba.WritebackDestinationWidth[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2028
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2030
if (mode_lib->vba.BlendingAndTiming[j] == k
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2032
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2034
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2051
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2053
if (mode_lib->vba.BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2054
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2058
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2059
mode_lib->vba.MaxVStartupLines[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2060
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2064
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2065
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2066
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2070
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2073
mode_lib->vba.MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2075
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2076
mode_lib->vba.cursor_bw[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2077
for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2078
mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2079
* mode_lib->vba.CursorBPP[k][j] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2080
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2081
* mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2096
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2097
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2101
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2102
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2104
mode_lib->vba.BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2106
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2107
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2124
CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBW, mode_lib->vba.ReadBandwidthPlaneLuma[k], mode_lib->vba.ReadBandwidthPlaneChroma[k], mode_lib->vba.TotalDataReadBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2125
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2126
mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2128
mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2129
mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2130
mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2132
mode_lib->vba.ErrorResult[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2135
mode_lib->vba.DPPCLK[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2137
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2139
mode_lib->vba.DPPPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2140
mode_lib->vba.NumberOfCursors[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2141
mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2142
- mode_lib->vba.VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2143
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2147
mode_lib->vba.MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2150
mode_lib->vba.DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2151
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2152
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2153
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2157
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2158
mode_lib->vba.MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2159
mode_lib->vba.PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2160
mode_lib->vba.PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2161
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2162
mode_lib->vba.BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2163
mode_lib->vba.VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2164
mode_lib->vba.MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2165
mode_lib->vba.PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2166
mode_lib->vba.BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2167
mode_lib->vba.VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2168
mode_lib->vba.MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2169
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2170
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2172
mode_lib->vba.XFCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2174
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2176
mode_lib->vba.DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2177
mode_lib->vba.DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2178
&mode_lib->vba.DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2179
&mode_lib->vba.PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2180
&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2181
&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2182
&mode_lib->vba.VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2183
&mode_lib->vba.VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2184
&mode_lib->vba.RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2185
&mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2186
&mode_lib->vba.VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2187
&mode_lib->vba.VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2188
&mode_lib->vba.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2190
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2191
mode_lib->vba.VStartup[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2193
mode_lib->vba.MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2196
mode_lib->vba.VStartup[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2200
mode_lib->vba.VStartup[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2203
mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2207
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2209
if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2210
mode_lib->vba.prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2211
else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2212
mode_lib->vba.prefetch_vm_bw[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2213
(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2214
/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2215
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2216
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2218
mode_lib->vba.prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2221
if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2223
mode_lib->vba.prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2224
else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2225
mode_lib->vba.prefetch_row_bw[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2226
(double) (mode_lib->vba.MetaRowByte[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2227
+ mode_lib->vba.PixelPTEBytesPerRow[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2228
/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2229
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2230
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2232
mode_lib->vba.prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2237
MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2239
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2241
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2243
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2244
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2245
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2246
+ mode_lib->vba.meta_row_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2247
+ mode_lib->vba.dpte_row_bw[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2249
if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2251
if (mode_lib->vba.VRatioPrefetchY[k] > 4
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2252
|| mode_lib->vba.VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2272
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2275
- mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2277
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2278
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2279
+ mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2280
mode_lib->vba.PrefetchBandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2283
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2284
ImmediateFlipBytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2285
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2286
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2287
ImmediateFlipBytes[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2288
mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2289
+ mode_lib->vba.MetaRowByte[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2290
+ mode_lib->vba.PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2294
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2295
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2296
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2299
+ ImmediateFlipBytes[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2302
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2311
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2312
ImmediateFlipBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2313
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2314
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2315
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2316
mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2317
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2318
mode_lib->vba.MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2319
mode_lib->vba.PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2320
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2321
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2322
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2323
mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2324
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2325
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2326
&final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2327
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2329
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2332
+ mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2334
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2336
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2337
final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2339
mode_lib->vba.ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2340
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2341
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2347
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2348
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2356
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2357
if (mode_lib->vba.ErrorResult[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2371
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2372
if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2373
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2374
mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2375
/ mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2376
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2378
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2379
mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2380
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2381
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2383
if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2384
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2386
if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2387
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2388
mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2389
* mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2390
/ mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2391
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2393
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2394
mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2395
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2396
/ mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2402
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2404
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2405
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2406
mode_lib->vba.MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2412
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2413
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2414
mode_lib->vba.MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2418
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2419
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2420
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2422
if (!mode_lib->vba.DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2423
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2424
+ mode_lib->vba.MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2430
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2431
mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2434
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2448
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2449
/ (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2451
mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2453
1)) - (mode_lib->vba.vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2460
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2461
/ (mode_lib->vba.SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2464
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2468
- (mode_lib->vba.VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2471
/ mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2472
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2475
/ (mode_lib->vba.VRatio[k] / 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2476
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2478
if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2480
/ mode_lib->vba.SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2481
} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2487
if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2489
/ (mode_lib->vba.SwathWidthY[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2490
} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2496
DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2498
MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2499
+ (mode_lib->vba.LinesInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2500
- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2501
/ mode_lib->vba.SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2502
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2503
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2512
* mode_lib->vba.SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2513
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2514
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2517
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2518
double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2519
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2523
mode_lib->vba.FullDETBufferingTimeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2524
+ (mode_lib->vba.LinesInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2525
- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2526
/ mode_lib->vba.SwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2527
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2528
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2540
* mode_lib->vba.SwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2541
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2542
/ mode_lib->vba.PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2544
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2548
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2552
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2555
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2559
/ (mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2560
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2561
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2562
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2563
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2566
} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2574
/ (mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2575
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2576
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2577
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2578
/ mode_lib->vba.PixelClock[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2586
/ (mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2587
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2588
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2589
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2590
/ mode_lib->vba.PixelClock[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2593
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2594
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2604
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2605
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2608
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2609
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2610
PlaneWithMinActiveDRAMClockChangeMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2613
if (mode_lib->vba.BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2624
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2625
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (mode_lib->vba.BlendingAndTiming[k] == k))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2626
&& !(mode_lib->vba.BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2627
&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2630
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2638
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2642
mode_lib->vba.MinTTUVBlank[k] += 25;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2657
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2658
if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2668
for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2670
mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2673
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2674
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2677
mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2678
mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2679
mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2687
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2688
mode_lib->vba.SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2689
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2690
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2703
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2706
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2707
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2709
mode_lib->vba.XFCTransferDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2712
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2713
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2715
mode_lib->vba.XFCPrechargeDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2720
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2721
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2726
(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2727
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2728
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2729
/ mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2741
mode_lib->vba.XFCPrefetchMargin[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2744
+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2745
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2746
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2747
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2749
mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2750
mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2751
mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2752
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2753
mode_lib->vba.XFCPrechargeDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2754
mode_lib->vba.XFCTransferDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2755
mode_lib->vba.XFCPrefetchMargin[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2762
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2763
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2764
unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2765
* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2775
if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2777
mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2801
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2803
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2806
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2809
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2812
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2815
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2818
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2826
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2827
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2828
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2829
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2830
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2832
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2834
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2835
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2845
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2848
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2861
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2869
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2870
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2871
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2872
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2873
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2874
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2875
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2877
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2879
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2881
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2883
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2885
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2887
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2889
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2891
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2892
&& mode_lib->vba.SourceScan[k] != dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2899
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2902
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2903
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2906
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2907
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2916
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2917
SwathWidth = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2919
SwathWidth = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2922
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2926
if (mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2927
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2935
mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2937
if (mode_lib->vba.DPPPerPlane[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2940
SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2948
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2959
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2969
mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2970
mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2972
mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2973
mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2976
if (mode_lib->vba.SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2977
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2978
mode_lib->vba.DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2979
} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2980
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2982
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2985
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2987
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3395
unsigned int j, k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3402
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3403
if (mode_lib->vba.ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3404
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3405
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3406
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3407
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3408
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3409
|| mode_lib->vba.HRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3410
|| mode_lib->vba.htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3411
|| mode_lib->vba.VRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3412
|| mode_lib->vba.vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3414
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3415
|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3416
|| (mode_lib->vba.htaps[k] > 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3417
&& (mode_lib->vba.htaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3418
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3419
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3420
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3421
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3422
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3423
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3424
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3425
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3426
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3427
&& (mode_lib->vba.HRatio[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3428
> mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3429
|| mode_lib->vba.VRatio[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3430
> mode_lib->vba.VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3437
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3438
if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3439
&& mode_lib->vba.SourceScan[k] != dm_horz)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3440
|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3441
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3442
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3443
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3444
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3445
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3446
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3447
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3448
|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3449
&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3450
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3452
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3454
|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3455
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3457
&& !((mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3459
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3461
&& mode_lib->vba.SourceScan[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3465
&& mode_lib->vba.DCCEnable[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3467
|| (mode_lib->vba.DCCEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3468
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3470
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3472
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3479
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3480
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3481
locals->BytePerPixelInDETY[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3482
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3483
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3484
locals->BytePerPixelInDETY[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3485
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3486
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3487
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3488
locals->BytePerPixelInDETY[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3489
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3490
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3491
locals->BytePerPixelInDETY[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3492
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3493
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3494
locals->BytePerPixelInDETY[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3495
locals->BytePerPixelInDETC[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3497
locals->BytePerPixelInDETY[k] = 4.0 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3498
locals->BytePerPixelInDETC[k] = 8.0 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3500
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3501
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3503
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3506
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3507
locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3508
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3509
locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3510
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3511
locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3513
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3514
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3515
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3516
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3517
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3518
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3519
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3520
/ mode_lib->vba.PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3521
} else if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3522
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3523
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3524
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3525
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3526
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3527
/ mode_lib->vba.PixelClock[k]) * 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3528
} else if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3529
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3530
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3531
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3532
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3533
/ mode_lib->vba.PixelClock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3535
locals->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3539
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3540
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3603
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3604
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3605
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3606
if (locals->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3613
if (locals->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3641
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3642
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3643
if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3644
mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3647
+ mode_lib->vba.ActiveWritebacksPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3654
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3655
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3657
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3664
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3665
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3667
&& (mode_lib->vba.WritebackHRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3668
|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3671
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3672
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3674
|| mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3676
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3678
|| mode_lib->vba.WritebackLumaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3680
|| mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3682
|| mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3683
> mode_lib->vba.WritebackLumaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3684
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3685
> mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3686
|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3687
&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3689
|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3690
&& (mode_lib->vba.WritebackChromaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3692
|| mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3695
* mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3696
> mode_lib->vba.WritebackChromaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3698
* mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3699
> mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3700
|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3701
&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3704
if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3706
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3710
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3711
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3715
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3717
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3718
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3720
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3722
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3723
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3726
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3730
if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3735
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3736
&& mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3738
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3740
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3741
&& mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3744
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3753
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3754
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3759
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3760
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3761
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3762
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3763
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3764
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3765
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3766
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3767
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3768
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3772
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3773
if (mode_lib->vba.HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3774
locals->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3777
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3779
mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3783
locals->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3787
if (locals->BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3788
locals->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3789
locals->MinDPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3790
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3792
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3795
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3796
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3797
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3798
/ locals->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3800
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3801
&& locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3802
< 2.0 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3803
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3804
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3807
if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3808
locals->PSCL_FACTOR_CHROMA[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3812
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3815
mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3819
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3823
locals->MinDPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3824
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3826
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3829
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3830
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3831
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3832
/ locals->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3833
mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3837
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3839
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3840
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3842
/ locals->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3844
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3845
|| mode_lib->vba.HTAPsChroma[k] > 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3846
|| mode_lib->vba.VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3847
&& locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3848
< 2.0 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3849
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3850
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3854
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3856
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3857
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3858
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3859
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3860
&locals->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3861
&locals->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3862
&locals->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3863
&locals->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3864
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3865
locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3866
locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3868
locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3869
locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3871
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3872
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3873
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3874
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3875
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3876
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3877
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3878
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3880
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3882
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3884
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3886
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3888
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3890
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3892
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3893
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3895
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3898
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3900
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3901
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3902
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3903
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3904
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3905
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3907
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3908
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3909
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3910
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3912
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3914
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3915
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3918
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3927
/ (locals->BytePerPixelInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3928
* locals->MinSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3929
+ locals->BytePerPixelInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3931
* locals->MinSwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3932
if (locals->BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3935
* dml_max(mode_lib->vba.HRatio[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3936
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3937
/ (mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3940
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3949
mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3951
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3952
/ (mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3955
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3961
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3964
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3965
/ (mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3968
mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3974
locals->MaximumSwathWidth[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3992
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3994
mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3998
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4001
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4005
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4008
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4012
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4014
} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4015
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4017
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4018
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4023
if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4024
&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4025
&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4026
locals->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4027
locals->RequiredDPPCLK[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4028
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4030
locals->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4031
locals->RequiredDPPCLK[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4032
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4037
if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4044
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4045
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4054
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4055
if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4056
BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4057
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4070
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4071
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4072
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4073
locals->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4074
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4077
locals->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4078
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4083
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4087
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4093
if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4099
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4100
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4115
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4116
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4117
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4118
> locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4122
if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4141
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4142
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4155
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4156
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4157
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4158
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4163
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4164
locals->RequiresDSC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4165
locals->RequiresFEC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4166
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4167
if (mode_lib->vba.Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4168
locals->RequiresDSC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4169
locals->RequiresFEC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4170
locals->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4171
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4172
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4174
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4175
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4176
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4177
} else if (mode_lib->vba.Output[k] == dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4178
|| mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4179
if (mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4188
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4189
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4191
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4192
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4193
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4196
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4197
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4199
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4200
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4201
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4202
if (mode_lib->vba.DSCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4203
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4204
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4205
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4207
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4211
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4212
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4214
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4219
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4220
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4222
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4223
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4224
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4227
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4228
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4230
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4231
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4232
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4233
if (mode_lib->vba.DSCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4234
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4235
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4236
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4238
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4242
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4243
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4245
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4252
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4253
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4255
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4256
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4257
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4260
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4261
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4263
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4264
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4265
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4266
if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4267
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4268
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4269
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4271
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4275
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4276
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4278
locals->OutputBppPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4283
locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4289
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4290
if (!mode_lib->vba.skip_dio_check[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4291
&& (locals->OutputBppPerState[i][k] == BPP_INVALID
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4292
|| (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4293
&& mode_lib->vba.Interlace[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4300
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4302
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4303
if ((mode_lib->vba.Output[k] == dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4304
|| mode_lib->vba.Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4305
if (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4306
|| mode_lib->vba.OutputFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4312
if (locals->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4313
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4314
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4320
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4334
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4335
if (locals->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4336
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4352
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4353
if (mode_lib->vba.BlendingAndTiming[k] != k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4355
} else if (locals->RequiresDSC[i][k] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4356
|| locals->RequiresDSC[i][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4358
} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4360
mode_lib->vba.PixelClockBackEnd[k] / 400.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4362
} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4364
} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4366
} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4371
if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4372
|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4375
mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4377
if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4378
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4379
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4381
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4384
mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4388
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4390
mode_lib->vba.OutputFormat[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4392
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4394
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4396
dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4398
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4399
+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4401
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4402
locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4404
locals->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4407
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4410
if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4411
locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4420
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4421
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4422
locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4424
locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4425
locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4426
locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4427
+ locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4428
if (locals->SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4431
if (locals->MaxSwathHeightC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4432
locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4434
locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4435
+ locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4437
if (locals->SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4444
locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4445
locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4447
locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4448
locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4451
if (locals->BytePerPixelInDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4452
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4454
} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4455
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4456
locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4457
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4459
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4460
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4464
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4465
/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4468
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4469
/ (locals->SwathWidthYPerState[i][j][k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4470
/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4473
locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4474
locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4476
locals->SwathHeightYPerState[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4479
if (locals->BytePerPixelInDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4480
locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4481
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4482
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4485
locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4486
locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i][0],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4488
locals->SwathHeightCPerState[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4489
locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4490
locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4491
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4492
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4493
locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) -
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4494
locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 *
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4495
dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4504
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4505
if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4516
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4517
if (locals->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4519
locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4528
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4529
locals->MaxTotalVActiveRDBandwidth = locals->MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4534
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4535
locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4536
locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4537
locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4538
locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4539
locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4542
mode_lib->vba.PixelClock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4543
if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4544
if (mode_lib->vba.VRatio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4550
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4553
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4554
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4555
/ mode_lib->vba.NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4562
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4565
* mode_lib->vba.PSCL_FACTOR[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4566
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4569
if (mode_lib->vba.VRatio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4575
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4578
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4579
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4580
/ mode_lib->vba.NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4587
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4590
* mode_lib->vba.PSCL_FACTOR[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4591
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4593
if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4599
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4602
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4604
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4605
/ mode_lib->vba.NoOfDPP[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4612
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4615
* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4616
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4620
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4623
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4624
mode_lib->vba.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4625
mode_lib->vba.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4626
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4627
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4628
dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4629
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4630
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4631
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4632
mode_lib->vba.SwathWidthYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4637
mode_lib->vba.PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4638
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4639
&mode_lib->vba.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4642
&mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4643
&mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4644
&mode_lib->vba.meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4645
mode_lib->vba.PrefetchLinesY[0][0][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4647
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4648
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4649
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4651
mode_lib->vba.SwathHeightYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4652
mode_lib->vba.ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4653
&mode_lib->vba.PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4654
&mode_lib->vba.MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4655
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4656
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4657
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4658
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4659
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4662
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4663
mode_lib->vba.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4664
mode_lib->vba.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4665
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4666
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4667
dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4668
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4669
mode_lib->vba.ViewportWidth[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4670
mode_lib->vba.ViewportHeight[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4671
mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4676
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4678
&mode_lib->vba.MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4681
&mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4682
&mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4683
&mode_lib->vba.meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4684
mode_lib->vba.PrefetchLinesC[0][0][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4686
mode_lib->vba.VRatio[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4687
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4688
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4690
mode_lib->vba.SwathHeightCPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4691
mode_lib->vba.ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4692
&mode_lib->vba.PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4693
&mode_lib->vba.MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4698
locals->PrefetchLinesC[0][0][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4699
locals->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4702
locals->PDEAndMetaPTEBytesPerFrame[0][0][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4704
locals->MetaRowBytes[0][0][k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4705
locals->DPTEBytesPerRow[0][0][k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4709
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4710
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4711
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4712
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4715
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4716
mode_lib->vba.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4719
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4720
mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4721
&mode_lib->vba.meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4722
&mode_lib->vba.dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4723
&mode_lib->vba.qual_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4741
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4742
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4743
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4744
locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4746
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4747
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4748
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4749
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4750
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4751
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4752
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4753
mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4755
locals->WritebackDelay[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4758
if (mode_lib->vba.BlendingAndTiming[m] == k
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4761
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4775
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4777
if (mode_lib->vba.BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4778
locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4782
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4783
for (m = 0; m < locals->NumberOfCursors[k]; m++)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4784
locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4785
/ 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4788
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4789
locals->MaximumVStartup[0][0][k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4790
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4803
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4805
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4809
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4810
locals->SwathWidthYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4811
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4812
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4829
CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i][0], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4830
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4831
mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4833
mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4834
mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4835
&mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4837
mode_lib->vba.IsErrorResult[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4840
mode_lib->vba.RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4842
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4844
mode_lib->vba.NoOfDPP[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4845
mode_lib->vba.NumberOfCursors[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4846
mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4847
- mode_lib->vba.VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4848
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4850
mode_lib->vba.MaximumVStartup[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4853
mode_lib->vba.DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4854
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4855
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4856
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4860
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4861
mode_lib->vba.MetaRowBytes[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4862
mode_lib->vba.DPTEBytesPerRow[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4863
mode_lib->vba.PrefetchLinesY[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4864
mode_lib->vba.SwathWidthYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4865
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4866
mode_lib->vba.PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4867
mode_lib->vba.MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4868
mode_lib->vba.PrefetchLinesC[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4869
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4870
mode_lib->vba.PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4871
mode_lib->vba.MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4872
mode_lib->vba.SwathHeightYPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4873
mode_lib->vba.SwathHeightCPerState[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4875
mode_lib->vba.XFCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4877
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4879
mode_lib->vba.DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4880
mode_lib->vba.DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4881
&mode_lib->vba.LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4882
&mode_lib->vba.PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4883
&mode_lib->vba.LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4884
&mode_lib->vba.LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4885
&mode_lib->vba.VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4886
&mode_lib->vba.VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4887
&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4888
&mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4889
&mode_lib->vba.VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4890
&mode_lib->vba.VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4891
&mode_lib->vba.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4897
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4898
if (locals->PDEAndMetaPTEBytesPerFrame[0][0][k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4899
locals->prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4900
else if (locals->LinesForMetaPTE[k] > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4901
locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[0][0][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4902
/ (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4904
locals->prefetch_vm_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4907
if (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4908
locals->prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4909
else if (locals->LinesForMetaAndDPTERow[k] > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4910
locals->prefetch_row_bw[k] = (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4911
/ (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4913
locals->prefetch_row_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4918
+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4921
+ mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4923
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4924
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4925
dml_max(mode_lib->vba.ReadBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4926
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4927
+ mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4938
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4939
if (locals->LineTimesForPrefetch[k] < 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4940
|| locals->LinesForMetaPTE[k] >= 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4941
|| locals->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4942
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4947
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4948
if (locals->VRatioPreY[i][j][k] > 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4949
|| locals->VRatioPreC[i][j][k] > 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4950
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4961
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4964
- mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4966
mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4967
mode_lib->vba.PrefetchBW[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4969
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4970
mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4971
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4972
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4973
mode_lib->vba.ImmediateFlipBytes[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4974
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4975
+ mode_lib->vba.MetaRowBytes[0][0][k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4976
+ mode_lib->vba.DPTEBytesPerRow[0][0][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4980
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4981
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4982
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4985
+ mode_lib->vba.ImmediateFlipBytes[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4989
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4998
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4999
mode_lib->vba.ImmediateFlipBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5000
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5001
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5002
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5003
mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5004
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5005
mode_lib->vba.MetaRowBytes[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5006
mode_lib->vba.DPTEBytesPerRow[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5007
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5008
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5009
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5010
mode_lib->vba.qual_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5011
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5012
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5013
&mode_lib->vba.final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5014
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5017
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5020
+ mode_lib->vba.cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5022
mode_lib->vba.prefetch_vm_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5023
mode_lib->vba.prefetch_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5024
mode_lib->vba.final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5026
mode_lib->vba.ReadBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5027
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]));
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5034
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5035
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5061
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5062
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5063
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5071
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5073
if (mode_lib->vba.CursorWidth[k][j] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5079
/ (mode_lib->vba.CursorWidth[k][j]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5080
* mode_lib->vba.CursorBPP[k][j]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5083
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5084
/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5085
|| (mode_lib->vba.CursorBPP[k][j] == 64.0
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5095
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5096
locals->AlignedYPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5097
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5098
locals->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5099
if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5102
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5103
locals->AlignedDCCMetaPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5105
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5106
mode_lib->vba.ViewportWidth[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5107
64.0 * locals->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5109
locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5111
if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5114
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5115
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5116
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5117
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5118
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5119
locals->AlignedCPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5121
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5122
mode_lib->vba.ViewportWidth[k] / 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5123
locals->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5125
locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5127
if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5206
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5207
mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5208
locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5219
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5220
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5221
mode_lib->vba.ODMCombineEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5222
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5224
mode_lib->vba.ODMCombineEnabled[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5226
mode_lib->vba.DSCEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5227
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5228
mode_lib->vba.OutputBpp[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5229
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1469
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1478
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1479
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1484
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1485
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1486
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1487
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1488
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1489
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1490
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1491
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1492
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1493
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1498
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1499
if (mode_lib->vba.HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1500
locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1503
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1505
mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1509
locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1515
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1517
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1520
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1522
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1523
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1524
/ locals->PSCL_THROUGHPUT_LUMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1527
if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1529
< 2 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1530
mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1533
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1534
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1535
locals->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1536
locals->DPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1539
if (mode_lib->vba.HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1540
locals->PSCL_THROUGHPUT_CHROMA[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1544
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1547
mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1551
locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1556
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1558
mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1562
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1565
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1566
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1568
/ locals->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1571
if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1573
< 2 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1575
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1578
locals->DPPCLKUsingSingleDPP[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1584
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1585
if (mode_lib->vba.BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1587
if (mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1591
mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1601
mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1605
} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1609
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1619
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1656
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1657
mode_lib->vba.DPPCLK_calculated[k] = locals->DPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1658
/ mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1662
mode_lib->vba.DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1667
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1668
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1670
mode_lib->vba.DPPCLK_calculated[k] * 255
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1673
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1681
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1684
if (mode_lib->vba.SourceScan[k] == dm_horz)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1685
locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1687
locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1689
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1692
if (mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1693
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1697
locals->SwathWidthY[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1698
(double) locals->SwathWidthSingleDPPY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1700
mode_lib->vba.HActive[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1701
* mode_lib->vba.HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1703
locals->SwathWidthY[k] = locals->SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1704
/ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1707
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1708
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1709
locals->BytePerPixelDETY[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1710
locals->BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1711
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1712
locals->BytePerPixelDETY[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1713
locals->BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1714
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1715
locals->BytePerPixelDETY[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1716
locals->BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1717
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1718
locals->BytePerPixelDETY[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1719
locals->BytePerPixelDETC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1720
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1721
locals->BytePerPixelDETY[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1722
locals->BytePerPixelDETC[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1724
locals->BytePerPixelDETY[k] = 4.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1725
locals->BytePerPixelDETC[k] = 8.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1730
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1731
locals->ReadBandwidthPlaneLuma[k] = locals->SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1732
* dml_ceil(locals->BytePerPixelDETY[k], 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1733
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1734
* mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1735
locals->ReadBandwidthPlaneChroma[k] = locals->SwathWidthSingleDPPY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1736
/ 2 * dml_ceil(locals->BytePerPixelDETC[k], 2)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1737
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1738
* mode_lib->vba.VRatio[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1741
k,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1742
locals->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1743
+ locals->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1744
mode_lib->vba.TotalDataReadBandwidth += locals->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1745
+ locals->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1765
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1766
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1767
locals->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1769
if (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1770
|| mode_lib->vba.OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1774
if (mode_lib->vba.ODMCombineEnabled[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1775
locals->DSCCLK_calculated[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1776
mode_lib->vba.PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1782
locals->DSCCLK_calculated[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1783
mode_lib->vba.PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1793
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1794
double bpp = mode_lib->vba.OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1795
unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1797
if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1798
if (!mode_lib->vba.ODMCombineEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1799
locals->DSCDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1801
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1804
(double) mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1805
/ mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1808
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1810
mode_lib->vba.OutputFormat[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1812
locals->DSCDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1815
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1818
(double) mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1819
/ mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1822
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1824
mode_lib->vba.OutputFormat[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1826
locals->DSCDelay[k] = locals->DSCDelay[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1827
* mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1828
/ mode_lib->vba.PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1830
locals->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1834
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1836
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1838
locals->DSCDelay[k] = locals->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1841
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1852
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1853
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1854
dml_ceil(locals->BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1855
dml_ceil(locals->BytePerPixelDETC[k], 2),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1856
&locals->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1857
&locals->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1858
&locals->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1859
&locals->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1861
locals->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1863
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1864
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1865
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1867
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1868
mode_lib->vba.ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1869
&locals->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1870
&locals->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1872
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1873
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1874
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1875
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1879
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1880
locals->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1881
locals->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1882
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1883
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1885
locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1887
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1888
mode_lib->vba.ViewportWidth[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1889
mode_lib->vba.ViewportHeight[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1890
locals->SwathWidthY[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1897
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1898
mode_lib->vba.DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1899
&locals->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1903
&locals->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1904
&locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1905
&locals->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1906
&locals->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1907
&locals->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1908
&locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1911
&locals->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1912
&locals->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1913
&locals->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1914
&locals->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1915
&locals->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1917
locals->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1919
mode_lib->vba.VRatio[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1920
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1921
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1923
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1924
mode_lib->vba.ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1925
&locals->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1926
&locals->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1931
locals->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1932
locals->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1938
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1939
locals->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1940
locals->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1941
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1942
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1943
dml_ceil(locals->BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1944
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1945
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1946
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1947
locals->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1954
mode_lib->vba.PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1955
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1956
&locals->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1960
&locals->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1961
&locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1962
&locals->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1963
&locals->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1964
&locals->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1965
&locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1966
&locals->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1967
&locals->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1968
&locals->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1969
&locals->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1970
&locals->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1971
&locals->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1972
&locals->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1974
locals->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1975
locals->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1977
locals->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1981
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1982
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1983
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1984
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1987
locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1988
locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1991
locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1992
locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1993
&locals->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1994
&locals->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1999
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2001
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2002
if (mode_lib->vba.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2004
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2038
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2039
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2040
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2041
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2044
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2045
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2046
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2047
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2048
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2049
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2050
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2051
mode_lib->vba.WritebackDestinationWidth[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2054
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2056
if (mode_lib->vba.BlendingAndTiming[j] == k
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2058
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2060
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2077
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2079
if (mode_lib->vba.BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2080
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2084
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2085
locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2088
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2089
locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2106
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2110
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2114
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2115
locals->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2117
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2119
mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2120
/ mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2137
myPipe.DPPCLK = locals->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2139
myPipe.PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2141
myPipe.DPPPerPlane = mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2142
myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2143
myPipe.SourceScan = mode_lib->vba.SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2144
myPipe.BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2145
myPipe.BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2146
myPipe.BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2147
myPipe.BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2148
myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2149
myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2150
myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2151
myPipe.HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2158
mode_lib->vba.ErrorResult[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2164
locals->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2171
(unsigned int) (locals->SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2172
/ mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2173
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2175
dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2176
locals->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2180
mode_lib->vba.DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2181
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2182
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2183
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2187
locals->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2188
locals->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2189
locals->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2190
locals->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2191
locals->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2192
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2193
locals->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2194
locals->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2195
locals->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2196
locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2197
locals->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2198
locals->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2199
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2200
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2202
mode_lib->vba.XFCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2205
&locals->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2206
&locals->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2207
&locals->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2208
&locals->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2209
&locals->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2210
&locals->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2211
&locals->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2212
&locals->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2213
&locals->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2214
&locals->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2216
&locals->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2217
&locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2218
&locals->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2219
&locals->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2220
&mode_lib->vba.VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2221
&mode_lib->vba.VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2222
&mode_lib->vba.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2223
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2224
locals->VStartup[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2226
locals->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2229
locals->VStartup[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2233
locals->VStartup[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2236
locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2240
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2243
locals->cursor_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2244
locals->cursor_bw_pre[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2245
for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2246
locals->cursor_bw[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2247
locals->cursor_bw_pre[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2252
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2253
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2254
locals->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2255
mode_lib->vba.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2256
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2259
mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2260
dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2261
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2262
locals->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2263
locals->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2264
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2265
locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2266
&locals->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2267
&locals->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2268
&locals->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2269
&locals->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2270
&locals->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2271
&locals->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2276
locals->UrgentBurstFactorLuma[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2277
locals->UrgentBurstFactorChroma[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2278
locals->UrgentBurstFactorCursor[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2279
locals->UrgentBurstFactorLumaPre[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2280
locals->UrgentBurstFactorChromaPre[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2281
locals->UrgentBurstFactorCursorPre[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2285
dml_max3(locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2286
locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2287
+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2288
* locals->UrgentBurstFactorCursor[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2289
locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixDataBWChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2290
* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2293
dml_max3(locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2294
locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2295
+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2296
locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2298
if (locals->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2300
if (locals->VRatioPrefetchY[k] > 4 || locals->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2317
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2321
locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2322
+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2323
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2324
locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2325
locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2326
locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2330
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2331
mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2333
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2345
locals->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2346
locals->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2347
locals->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2350
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2351
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2352
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2353
locals->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2354
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2355
locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2356
locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2357
locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2358
locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2359
&locals->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2360
&locals->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2361
&locals->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2362
&locals->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2366
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2369
locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2370
locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2371
+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2372
locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2373
+ locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2374
+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2377
dml_max3(locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2378
locals->final_flip_bw[k] + locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2379
locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2388
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2389
if (locals->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2397
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2398
if (mode_lib->vba.ErrorResult[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2561
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2563
locals->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2564
locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2565
locals->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2571
locals->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2572
locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2573
locals->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2577
locals->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2578
locals->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2579
locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2581
if (!mode_lib->vba.DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2582
locals->MinTTUVBlank[k] = mode_lib->vba.TCalc
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2583
+ locals->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2588
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2589
locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2590
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2592
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2593
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2595
locals->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2596
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2597
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2598
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2599
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2600
&locals->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2601
&locals->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2602
&locals->DCCYIndependent64ByteBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2606
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2607
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2610
locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2611
locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2612
locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2620
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2621
locals->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2622
dml_ceil(locals->BytePerPixelDETY[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2623
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2636
locals->XFCRemoteSurfaceFlipLatency[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2639
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2640
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2642
locals->XFCTransferDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2645
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2646
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2648
locals->XFCPrechargeDelay[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2653
/ (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2654
/ mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2659
(locals->DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2660
+ locals->DestinationLinesToRequestRowInVBlank[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2661
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2662
/ mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2674
locals->XFCPrefetchMargin[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2677
+ (locals->DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2678
+ locals->DestinationLinesToRequestRowInVBlank[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2679
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2680
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2682
locals->XFCSlaveVUpdateOffset[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2683
locals->XFCSlaveVupdateWidth[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2684
locals->XFCSlaveVReadyOffset[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2685
locals->XFCRemoteSurfaceFlipLatency[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2686
locals->XFCPrechargeDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2687
locals->XFCTransferDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2688
locals->XFCPrefetchMargin[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2693
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2696
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2697
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2698
&locals->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2699
&locals->DETBufferSizeC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2701
locals->LinesInDETY[k] = (double)locals->DETBufferSizeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2702
/ locals->BytePerPixelDETY[k] / locals->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2703
locals->LinesInDETYRoundedDownToSwath[k] = dml_floor(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2704
locals->LinesInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2705
mode_lib->vba.SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2706
locals->FullDETBufferingTimeY[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2707
locals->LinesInDETYRoundedDownToSwath[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2708
* (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2709
/ mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2710
/ mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2714
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2715
if (locals->FullDETBufferingTimeY[k] < mode_lib->vba.StutterPeriod) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2716
mode_lib->vba.StutterPeriod = locals->FullDETBufferingTimeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2718
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2719
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2720
locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2721
locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2723
mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2729
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2732
if (mode_lib->vba.DCCEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2733
if (locals->DCCYMaxCompressedBlock[k] == 256)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2740
+ (locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2741
dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2745
+ locals->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2746
+ locals->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2749
locals->meta_row_bw[k] + locals->dpte_row_bw[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2773
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2774
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2788
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2790
mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2791
- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2792
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2826
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2828
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2831
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2834
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2837
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2840
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2843
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2851
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2852
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2853
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2854
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2855
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2857
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2859
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2860
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2870
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2873
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2886
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2894
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2895
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2896
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2897
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2898
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2899
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2900
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2902
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2904
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2906
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2908
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2910
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2912
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2914
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2916
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2917
&& mode_lib->vba.SourceScan[k] != dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2924
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2927
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2928
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2931
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2932
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2941
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2942
SwathWidth = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2944
SwathWidth = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2947
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2951
if (mode_lib->vba.BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2952
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2960
mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2962
SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2970
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2981
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2991
mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2992
mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2994
mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2995
mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3000
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3001
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3002
&mode_lib->vba.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3003
&mode_lib->vba.DETBufferSizeC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3401
unsigned k)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3407
if (mode_lib->vba.XFCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3411
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3412
locals->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3413
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3414
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3431
myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3433
myPipe.PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3435
myPipe.DPPPerPlane = locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3436
myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3437
myPipe.SourceScan = mode_lib->vba.SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3438
myPipe.BlockWidth256BytesY = locals->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3439
myPipe.BlockHeight256BytesY = locals->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3440
myPipe.BlockWidth256BytesC = locals->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3441
myPipe.BlockHeight256BytesC = locals->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3442
myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3443
myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3444
myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3445
myPipe.HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3453
mode_lib->vba.IsErrorResult[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3458
locals->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3465
locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3466
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3468
dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3469
locals->MaximumVStartup[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3473
mode_lib->vba.DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3474
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3475
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3476
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3480
locals->PDEAndMetaPTEBytesPerFrame[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3481
locals->MetaRowBytes[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3482
locals->DPTEBytesPerRow[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3483
locals->PrefetchLinesY[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3484
locals->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3485
locals->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3486
locals->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3487
locals->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3488
locals->PrefetchLinesC[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3489
locals->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3490
locals->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3491
locals->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3492
locals->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3493
locals->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3495
mode_lib->vba.XFCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3500
&locals->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3501
&locals->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3502
&locals->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3503
&locals->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3504
&locals->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3505
&locals->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3506
&locals->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3507
&locals->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3509
&locals->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3510
&locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3513
&mode_lib->vba.VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3514
&mode_lib->vba.VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3515
&mode_lib->vba.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3522
unsigned int j, k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3529
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3530
if (mode_lib->vba.ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3531
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3532
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3533
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3534
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3535
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3536
|| mode_lib->vba.HRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3537
|| mode_lib->vba.htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3538
|| mode_lib->vba.VRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3539
|| mode_lib->vba.vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3541
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3542
|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3543
|| (mode_lib->vba.htaps[k] > 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3544
&& (mode_lib->vba.htaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3545
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3546
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3547
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3548
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3549
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3550
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3551
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3552
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3553
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3554
&& (mode_lib->vba.HRatio[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3555
> mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3556
|| mode_lib->vba.VRatio[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3557
> mode_lib->vba.VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3564
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3565
if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3566
&& mode_lib->vba.SourceScan[k] != dm_horz)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3567
|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3568
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3569
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3570
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3571
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3572
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3573
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3574
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3575
|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3576
&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3577
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3579
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3581
|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3582
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3584
&& !((mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3586
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3588
&& mode_lib->vba.SourceScan[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3592
&& mode_lib->vba.DCCEnable[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3594
|| (mode_lib->vba.DCCEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3595
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3597
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3599
|| mode_lib->vba.SourcePixelFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3606
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3607
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3608
locals->BytePerPixelInDETY[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3609
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3610
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3611
locals->BytePerPixelInDETY[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3612
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3613
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3614
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3615
locals->BytePerPixelInDETY[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3616
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3617
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3618
locals->BytePerPixelInDETY[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3619
locals->BytePerPixelInDETC[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3620
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3621
locals->BytePerPixelInDETY[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3622
locals->BytePerPixelInDETC[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3624
locals->BytePerPixelInDETY[k] = 4.0 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3625
locals->BytePerPixelInDETC[k] = 8.0 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3627
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3628
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3630
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3633
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3634
locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3635
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3636
locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3637
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3638
locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3640
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3641
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3642
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3643
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3644
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3645
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3646
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3647
/ mode_lib->vba.PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3648
} else if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3649
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3650
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3651
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3652
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3653
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3654
/ mode_lib->vba.PixelClock[k]) * 3.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3655
} else if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3656
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3657
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3658
/ (mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3659
* mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3660
/ mode_lib->vba.PixelClock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3662
locals->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3666
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3667
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3689
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3690
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3691
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3692
if (locals->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3699
if (locals->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3730
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3731
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3732
if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3733
mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3736
+ mode_lib->vba.ActiveWritebacksPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3743
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3744
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3746
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3753
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3754
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3756
&& (mode_lib->vba.WritebackHRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3757
|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3760
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3761
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3763
|| mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3765
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3767
|| mode_lib->vba.WritebackLumaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3769
|| mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3771
|| mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3772
> mode_lib->vba.WritebackLumaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3773
|| mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3774
> mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3775
|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3776
&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3778
|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3779
&& (mode_lib->vba.WritebackChromaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3781
|| mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3784
* mode_lib->vba.WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3785
> mode_lib->vba.WritebackChromaHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3787
* mode_lib->vba.WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3788
> mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3789
|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3790
&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3793
if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3795
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3799
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3800
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3804
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3806
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3807
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3809
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3811
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3812
&& mode_lib->vba.WritebackLumaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3815
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3819
if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3824
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3825
&& mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3827
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3829
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3830
&& mode_lib->vba.WritebackChromaVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3833
/ mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3842
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3843
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3848
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3849
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3850
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3851
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3852
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3853
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3854
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3855
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3856
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3857
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3861
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3862
if (mode_lib->vba.HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3863
locals->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3866
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3868
mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3872
locals->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3876
if (locals->BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3877
locals->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3878
locals->MinDPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3879
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3881
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3884
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3885
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3886
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3887
/ locals->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3889
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3890
&& locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3891
< 2.0 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3892
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3893
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3896
if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3897
locals->PSCL_FACTOR_CHROMA[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3901
* mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3904
mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3908
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3912
locals->MinDPPCLKUsingSingleDPP[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3913
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3915
mode_lib->vba.vtaps[k] / 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3918
mode_lib->vba.HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3919
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3920
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3921
/ locals->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3922
mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3926
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3928
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3929
* mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3931
/ locals->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3933
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3934
|| mode_lib->vba.HTAPsChroma[k] > 6.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3935
|| mode_lib->vba.VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3936
&& locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3937
< 2.0 * mode_lib->vba.PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3938
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3939
* mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3943
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3945
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3946
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3947
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3948
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3949
&locals->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3950
&locals->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3951
&locals->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3952
&locals->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3953
if (mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3954
locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3955
locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3957
locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3958
locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3960
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3961
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3962
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3963
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3964
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3965
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3966
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3967
&& (mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3969
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3971
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3973
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3975
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3977
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3979
|| mode_lib->vba.SurfaceTiling[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3981
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3982
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3984
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3987
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3989
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3990
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3991
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3992
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3993
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3994
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3996
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3997
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3998
&& mode_lib->vba.SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3999
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4001
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4003
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4004
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4007
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4016
/ (locals->BytePerPixelInDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4017
* locals->MinSwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4018
+ locals->BytePerPixelInDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4020
* locals->MinSwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4021
if (locals->BytePerPixelInDETC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4024
* dml_max(mode_lib->vba.HRatio[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4025
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4026
/ (mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4029
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4038
mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4040
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4041
/ (mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4044
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4050
mode_lib->vba.HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4053
/ mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4054
/ (mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4057
mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4063
locals->MaximumSwathWidth[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4081
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4083
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4092
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4095
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4099
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4102
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4106
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4108
} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4109
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4111
} else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4112
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4117
if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4118
&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4119
&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4120
locals->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4121
locals->RequiredDPPCLK[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4122
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4124
locals->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4125
locals->RequiredDPPCLK[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4126
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4131
if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4138
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4139
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4148
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4149
if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4150
BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4151
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4164
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4165
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4166
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4167
locals->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4168
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4171
locals->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4172
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4177
mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4181
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4187
if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4193
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4194
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4209
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4210
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4211
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4212
> locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4216
if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4235
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4236
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4249
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4250
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4251
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4252
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4257
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4258
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4259
locals->RequiresFEC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4260
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4261
if (mode_lib->vba.Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4262
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4263
locals->RequiresFEC[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4264
locals->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4265
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4266
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4268
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4269
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4270
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4271
} else if (mode_lib->vba.Output[k] == dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4272
|| mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4273
if (mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4282
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4283
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4285
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4286
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4287
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4290
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4291
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4293
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4294
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4295
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4296
if (mode_lib->vba.DSCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4297
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4298
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4299
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4301
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4305
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4306
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4308
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4313
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4314
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4316
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4317
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4318
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4321
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4322
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4324
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4325
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4326
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4327
if (mode_lib->vba.DSCEnabled[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4328
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4329
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4330
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4332
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4336
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4337
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4339
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4346
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4347
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4349
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4350
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4351
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4354
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4355
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4357
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4358
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4359
mode_lib->vba.DSCInputBitPerComponent[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4360
if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4361
locals->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4362
if (mode_lib->vba.Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4363
locals->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4365
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4369
locals->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4370
locals->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4372
locals->OutputBppPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4377
locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4383
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4384
if (!mode_lib->vba.skip_dio_check[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4385
&& (locals->OutputBppPerState[i][k] == BPP_INVALID
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4386
|| (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4387
&& mode_lib->vba.Interlace[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4394
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4396
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4397
if ((mode_lib->vba.Output[k] == dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4398
|| mode_lib->vba.Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4399
if (mode_lib->vba.OutputFormat[k] == dm_420
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4400
|| mode_lib->vba.OutputFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4406
if (locals->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4407
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4408
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4414
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4428
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4429
if (locals->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4430
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4446
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4447
if (mode_lib->vba.BlendingAndTiming[k] != k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4449
} else if (locals->RequiresDSC[i][k] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4450
|| locals->RequiresDSC[i][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4452
} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4454
mode_lib->vba.PixelClockBackEnd[k] / 400.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4456
} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4458
} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4460
} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4465
if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4466
|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4469
mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4471
if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4472
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4473
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4475
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4478
mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4482
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4484
mode_lib->vba.OutputFormat[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4486
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4488
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4490
dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4492
mode_lib->vba.OutputFormat[k])
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4493
+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4495
locals->DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4496
locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4498
locals->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4501
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4504
if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4505
locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4515
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4516
if (mode_lib->vba.DCCEnable[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4517
locals->TotalNumberOfDCCActiveDPP[i][j] = locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4533
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4534
locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4535
locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4536
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4537
locals->SwathWidthYThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4538
dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4540
locals->SwathWidthYThisState[k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4543
/ dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4544
/ locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4546
(dml_ceil(locals->SwathWidthYThisState[k] - 1.0, mode_lib->vba.SwathWidthGranularityY)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4547
+ mode_lib->vba.SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4548
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4553
if (locals->MaxSwathHeightC[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4554
mode_lib->vba.SwathWidthGranularityC = 256.0 / dml_ceil(locals->BytePerPixelInDETC[k], 2.0) / locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4555
mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYThisState[k] / 2.0 - 1.0, mode_lib->vba.SwathWidthGranularityC)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4556
+ mode_lib->vba.SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4557
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4565
locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4566
locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4568
locals->SwathHeightYThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4569
locals->MinSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4570
locals->SwathHeightCThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4571
locals->MinSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4590
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4591
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4592
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4593
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4594
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4595
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4598
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4599
locals->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4600
locals->Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4601
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4602
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4603
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4604
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4605
mode_lib->vba.ViewportWidth[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4606
mode_lib->vba.ViewportHeight[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4607
locals->SwathWidthYThisState[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4614
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4616
&locals->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4619
&locals->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4621
&locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4622
&locals->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4623
&locals->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4624
&locals->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4625
&locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4633
locals->PrefetchLinesC[0][0][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4635
mode_lib->vba.VRatio[k]/2,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4636
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4637
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4639
locals->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4640
mode_lib->vba.ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4641
&locals->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4642
&locals->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4648
locals->PrefetchLinesC[0][0][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4649
locals->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4654
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4655
locals->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4656
locals->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4657
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4658
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4659
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4660
mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4661
mode_lib->vba.ViewportWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4662
mode_lib->vba.ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4663
locals->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4670
mode_lib->vba.PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4671
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4672
&locals->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4675
&locals->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4677
&locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4678
&locals->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4679
&locals->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4680
&locals->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4681
&locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4682
&locals->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4683
&locals->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4689
locals->PrefetchLinesY[0][0][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4691
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4692
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4693
mode_lib->vba.Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4695
locals->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4696
mode_lib->vba.ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4697
&locals->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4698
&locals->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4699
locals->PDEAndMetaPTEBytesPerFrame[0][0][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4701
locals->MetaRowBytes[0][0][k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4702
locals->DPTEBytesPerRow[0][0][k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4706
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4707
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4708
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4709
mode_lib->vba.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4710
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4713
locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4714
locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4717
locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4718
locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4719
&locals->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4720
&locals->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4740
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4741
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4742
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4743
locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4745
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4746
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4747
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4748
mode_lib->vba.WritebackLumaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4749
mode_lib->vba.WritebackLumaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4750
mode_lib->vba.WritebackChromaHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4751
mode_lib->vba.WritebackChromaVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4752
mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4754
locals->WritebackDelay[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4757
if (mode_lib->vba.BlendingAndTiming[m] == k
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4760
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4774
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4776
if (mode_lib->vba.BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4777
locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4782
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4783
locals->MaximumVStartup[0][0][k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4784
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4785
mode_lib->vba.MaxMaxVStartup[0][0] = dml_max(mode_lib->vba.MaxMaxVStartup[0][0], locals->MaximumVStartup[0][0][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4799
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4800
CalculatePrefetchSchedulePerPlane(mode_lib, i, j, k);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4804
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4807
locals->cursor_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4808
locals->cursor_bw_pre[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4809
for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4810
locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4811
/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4812
locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4813
/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4818
locals->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4819
locals->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4820
locals->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4821
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4824
mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4825
dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4826
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4827
locals->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4828
locals->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4829
locals->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4830
locals->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4831
&locals->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4832
&locals->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4833
&locals->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4834
&locals->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4835
&locals->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4836
&locals->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4841
locals->UrgentBurstFactorCursor[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4842
locals->UrgentBurstFactorCursorPre[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4843
locals->UrgentBurstFactorLuma[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4844
locals->UrgentBurstFactorLumaPre[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4845
locals->UrgentBurstFactorChroma[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4846
locals->UrgentBurstFactorChromaPre[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4850
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] + locals->ReadBandwidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4851
* locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4852
* locals->UrgentBurstFactorChroma[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4854
+ dml_max3(locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4855
locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4856
* locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4857
+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4858
locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4859
+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4860
+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4874
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4875
if (locals->LineTimesForPrefetch[k] < 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4876
|| locals->LinesForMetaPTE[k] >= 32.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4877
|| locals->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4878
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4883
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4884
if (locals->VRatioPreY[i][j][k] > 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4885
|| locals->VRatioPreC[i][j][k] > 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4886
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4891
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4892
if (locals->LinesForMetaAndDPTERow[k] >= 16 || locals->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4909
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4911
- dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4912
+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4913
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4914
locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4915
+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4916
+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4919
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4921
+ locals->PDEAndMetaPTEBytesPerFrame[0][0][k] + locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4924
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4936
locals->PDEAndMetaPTEBytesPerFrame[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4937
locals->MetaRowBytes[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4938
locals->DPTEBytesPerRow[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4941
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4942
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4943
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4944
locals->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4945
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4946
locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4947
locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4948
locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4949
locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4950
&locals->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4951
&locals->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4952
&locals->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4953
&locals->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4956
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4958
locals->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4959
locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4960
+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4961
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4962
locals->final_flip_bw[k] + locals->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4963
* locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4964
* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4965
* locals->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4972
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4973
if (locals->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5047
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5048
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5073
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5074
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5075
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5084
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5085
if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5086
for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5087
if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5096
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5097
locals->AlignedYPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5098
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5099
locals->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5100
if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5103
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5104
locals->AlignedDCCMetaPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5106
mode_lib->vba.DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5107
mode_lib->vba.ViewportWidth[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5108
64.0 * locals->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5110
locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5112
if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5115
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5116
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5117
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5118
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5119
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5120
locals->AlignedCPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5122
mode_lib->vba.PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5123
mode_lib->vba.ViewportWidth[k] / 2.0),
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5124
locals->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5126
locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5128
if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5213
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5214
mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5215
locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5225
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5226
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5227
mode_lib->vba.ODMCombineEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5228
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5230
mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5232
mode_lib->vba.DSCEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5233
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5234
mode_lib->vba.OutputBpp[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5235
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5316
unsigned int k, j;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5320
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5321
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5322
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5323
mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5328
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5330
+ ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5338
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5339
if (WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5358
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5361
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1))
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5362
- (vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5365
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1))
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5366
- (VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5368
EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5369
* (HTotal[k] / PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5372
/ (VRatio[k] / 2) * (HTotal[k] / PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5374
if (SwathWidthY[k] > 2 * DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5375
DPPOutputBufferLinesY = (double) DPPOutputBufferPixels / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5376
} else if (SwathWidthY[k] > DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5382
if (SwathWidthY[k] / 2.0 > 2 * DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5384
/ (SwathWidthY[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5385
} else if (SwathWidthY[k] / 2.0 > DPPOutputBufferPixels) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5393
SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5394
SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5398
LinesInDETY[k] = (double)DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5399
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5400
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5401
* (HTotal[k] / PixelClock[k]) / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5402
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5403
LinesInDETC = (double)DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5404
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5406
* (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5412
ActiveDRAMClockChangeLatencyMarginY = HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5414
+ FullDETBufferingTimeY[k] - *DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5418
- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5421
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5422
ActiveDRAMClockChangeLatencyMarginC = HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5427
- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / (VRatio[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5429
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5433
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5436
if (WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5437
if (WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5439
+ WritebackInterfaceChromaBufferSize) / (WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5440
* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5441
/ PixelClock[k]) * 4) - *WritebackDRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5445
2 * WritebackInterfaceChromaBufferSize * 8.0 / 10) / (WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5446
* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5449
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5450
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5457
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5458
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5461
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5462
if (BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5463
PlaneWithMinActiveDRAMClockChangeMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5466
if (BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5477
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5478
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k))
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5479
&& !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5480
&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5483
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5488
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5489
if (BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5506
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5507
if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5508
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5509
- (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5510
* (HTotal[k] / PixelClock[k]) / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5538
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5543
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5544
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5545
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5546
/ HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5548
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5549
/ DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5551
if (BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5554
if (VRatio[k] / 2 <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5555
DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5556
* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5558
DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5559
/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5563
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5564
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5565
1.1 * SwathWidthY[k] * dml_ceil(BytePerPixelDETY[k], 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5567
1.1 * SwathWidthY[k] / 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5568
* dml_ceil(BytePerPixelDETC[k], 2) / 32.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5571
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5572
* dml_ceil(BytePerPixelDETY[k], 1) / 64.0
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5575
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5576
mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5577
PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5582
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5585
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5758
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5760
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5761
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5762
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5763
/ HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5765
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5766
/ PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5769
if (BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5770
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5772
if (VRatio[k] / 2 <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5773
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5774
* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5776
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5777
/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5781
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5782
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5783
* DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5785
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5786
/ PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5789
if (BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5790
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5792
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5793
DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5794
swath_width_chroma_ub[k] * DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5795
/ (HRatio[k] / 2) / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5797
DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5798
swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5803
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5804
if (SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5805
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5807
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5809
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5811
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5812
DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5813
if (BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5814
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5815
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5817
if (SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5818
req_per_swath_ub = swath_width_chroma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5819
/ BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5821
req_per_swath_ub = swath_width_chroma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5822
/ BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5824
DisplayPipeRequestDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5825
DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5826
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5827
DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5900
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5902
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5904
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5905
if (BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5906
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5908
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / (VRatio[k] / 2);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5911
DST_Y_PER_PTE_ROW_NOM_L[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5912
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5914
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5915
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5917
DST_Y_PER_META_ROW_NOM_L[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5921
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5922
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5924
/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5926
/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5927
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5928
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5929
if (SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5930
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5933
- meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5940
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5941
/ PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5942
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5943
* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5944
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5945
* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5947
TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5948
TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5949
TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5953
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5955
if (SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5956
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5957
* PixelPTEReqWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5959
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5960
* PixelPTEReqHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5963
(float) dpte_row_width_luma_ub[k] / dpte_group_width_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5965
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5966
/ PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5967
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5968
* HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5969
time_per_pte_group_flip_luma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5970
DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5971
/ PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5973
if (BytePerPixelDETC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5974
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5975
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5976
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5978
if (SourceScan[k] == dm_horz) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5979
dpte_group_width_chroma = dpte_group_bytes[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5980
/ PTERequestSizeC[k] * PixelPTEReqWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5982
dpte_group_width_chroma = dpte_group_bytes[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5983
/ PTERequestSizeC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5984
* PixelPTEReqHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5987
(float) dpte_row_width_chroma_ub[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5990
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5991
* HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5993
time_per_pte_group_vblank_chroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5994
DestinationLinesToRequestRowInVBlank[k] * HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5995
/ PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5997
time_per_pte_group_flip_chroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5998
DestinationLinesToRequestRowInImmediateFlip[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5999
* HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6003
time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6004
time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6005
time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6006
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6007
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6008
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6012
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6013
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6014
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6015
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6017
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6018
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6021
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6025
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6027
dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6028
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6031
dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6034
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6036
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6037
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6038
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6039
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6042
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6043
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6048
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6049
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6050
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6051
/ 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6053
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6058
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6059
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6060
+ meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6062
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6065
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6066
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6067
+ dpde0_bytes_per_frame_ub_c[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6068
+ meta_pte_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6069
+ meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6071
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6072
+ meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6077
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6078
/ PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6079
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6080
* HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6081
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6082
* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6083
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6084
* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6087
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6088
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6089
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6090
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6094
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6095
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6096
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6097
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6139
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6141
for (k = 0; k < NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6143
+ NumberOfDPP[k] * dpte_group_bytes[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1005
PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1016
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1027
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1038
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1062
Tvm_equ = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1136
*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * v->BytePerPixelC[k] * swath_width_chroma_ub / LineTime;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1152
dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1154
dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1185
v->prefetch_vmrow_bw[k] = dml_max(prefetch_vm_bw, prefetch_row_bw);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1751
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1778
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1779
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1782
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1783
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1784
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1785
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1786
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1787
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1788
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1789
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1790
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1795
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1796
if (v->HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1797
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1798
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1800
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1805
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1806
* dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1807
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1809
if ((v->htaps[k] > 6 || v->vtaps[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1810
&& v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1811
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1814
if ((v->SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1815
&& v->SourcePixelFormat[k] != dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1816
&& v->SourcePixelFormat[k] != dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1817
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1818
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1819
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1821
if (v->HRatioChroma[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1822
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1823
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1825
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1829
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1830
* dml_max3(v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1831
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1833
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1835
< 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1837
* v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1840
v->DPPCLKUsingSingleDPP[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1846
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1847
if (v->BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1849
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1851
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1854
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1855
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1857
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1860
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1863
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1866
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1901
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1902
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1903
/ v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1907
v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1912
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1913
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1915
v->DPPCLK_calculated[k] * 255.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1918
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1919
v->DPPCLK[k] = v->DPPCLK_calculated[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1926
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1928
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1929
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1930
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1931
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1932
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1933
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1934
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1935
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1936
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1937
&v->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1972
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1973
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1974
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k]) * v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1975
DTRACE("read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2002
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2003
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2004
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2006
if (v->OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2008
else if (v->OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2010
else if (v->OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2014
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2015
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2017
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2018
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2021
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2027
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2028
double BPP = v->OutputBppPerState[k][v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2030
if (v->DSCEnabled[k] && BPP != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2031
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2032
v->DSCDelay[k] = dscceComputeDelay(v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2034
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2035
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2036
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2037
v->Output[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2038
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2039
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2040
v->DSCDelay[k] = 2 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2042
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2043
v->NumberOfDSCSlices[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2044
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2045
v->Output[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2046
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2048
v->DSCDelay[k] = 4 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2050
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2051
v->NumberOfDSCSlices[k] / 4.0,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2052
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2053
v->Output[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2054
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2056
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2058
v->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2062
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2064
if (j != k && v->BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2066
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2069
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2080
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2081
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2091
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2092
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2093
v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2094
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2095
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2096
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2097
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2098
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2099
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2106
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2107
v->DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2108
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2112
&v->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2113
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2114
&v->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2115
&v->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2116
&v->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2117
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2120
&v->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2121
&v->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2122
&v->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2123
&v->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2124
&v->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2126
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2128
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2129
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2130
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2132
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2133
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2134
&v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2135
&v->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2142
v->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2143
v->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2148
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2149
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2150
v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2151
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2152
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2153
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2154
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2155
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2156
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2163
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2164
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2165
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2169
&v->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2170
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2171
&v->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2172
&v->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2173
&v->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2174
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2175
&v->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2176
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2177
&v->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2178
&v->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2179
&v->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2180
&v->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2181
&v->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2183
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2185
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2186
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2187
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2189
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2190
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2191
&v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2192
&v->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2193
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2194
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2196
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2200
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2201
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2202
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2203
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2204
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2207
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2208
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2211
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2212
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2213
&v->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2214
&v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2219
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2221
+ v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2222
if (v->DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2224
+ v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2254
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2255
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2256
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2257
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2258
CalculateWriteBackDelay(v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2259
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2260
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2261
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2262
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2263
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2264
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2265
v->HTotal[k]) / v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2267
v->WritebackDelay[v->VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2269
if (v->BlendingAndTiming[j] == k
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2271
v->WritebackDelay[v->VoltageLevel][k] = dml_max(v->WritebackDelay[v->VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2280
v->HTotal[k]) / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2286
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2288
if (v->BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2289
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2291
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2292
v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2296
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2297
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2323
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2326
myPipe.DPPCLK = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2328
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2330
myPipe.DPPPerPlane = v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2331
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2332
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2333
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2334
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2335
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2336
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2337
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2338
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2339
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2340
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2341
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2342
myPipe.ODMCombineEnabled = !!v->ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2344
v->ErrorResult[k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2346
k,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2348
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2349
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2350
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2351
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2355
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2356
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2357
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2358
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2359
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2360
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2361
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2362
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2363
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2364
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2365
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2366
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2367
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2368
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2369
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2370
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2372
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2373
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2374
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2375
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2376
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2377
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2378
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2379
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2380
&v->NotEnoughTimeForDynamicMetadata[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2381
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2382
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2383
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2384
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2385
v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[k] / 4.0, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2386
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2388
int x = v->BlendingAndTiming[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2389
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2390
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[x];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2391
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[x];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2392
v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[x] / 4.0, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2394
v->MaxVStartupLines[x] = v->MaxVStartupLines[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2395
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[x]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2402
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2403
v->cursor_bw[k] = v->NumberOfCursors[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2404
* v->CursorWidth[k][0] * v->CursorBPP[k][0]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2406
/ (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2407
* v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2408
v->cursor_bw_pre[k] = v->NumberOfCursors[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2409
* v->CursorWidth[k][0] * v->CursorBPP[k][0]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2411
/ (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2412
* v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2415
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2416
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2418
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2419
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2420
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2423
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2424
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2425
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2426
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2427
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2428
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2429
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2430
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2431
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2432
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2433
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2434
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2437
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2438
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2440
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2441
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2442
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2445
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2446
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2447
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2448
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2449
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2450
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2451
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2452
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2453
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2454
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2455
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2456
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2459
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2460
v->ReadBandwidthPlaneLuma[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2461
v->UrgentBurstFactorLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2462
v->ReadBandwidthPlaneChroma[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2463
v->UrgentBurstFactorChroma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2464
v->cursor_bw[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2465
v->UrgentBurstFactorCursor[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2466
v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2467
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2468
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2469
v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2472
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2473
v->ReadBandwidthPlaneLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2474
v->ReadBandwidthPlaneChroma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2475
v->cursor_bw[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2476
v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2477
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2479
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2481
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2483
if (v->NoUrgentLatencyHiding[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2486
if (v->NoUrgentLatencyHidingPre[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2506
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2510
v->ReadBandwidthPlaneLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2511
+ v->ReadBandwidthPlaneChroma[k] * v->UrgentBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2512
+ v->cursor_bw[k] * v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2513
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2514
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2515
v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2519
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2520
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2522
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2534
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2535
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2536
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2539
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2540
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2541
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2542
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2543
v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2544
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2545
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2546
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2547
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2548
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2549
&v->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2550
&v->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2551
&v->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2552
&v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2556
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2558
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2559
v->DPPPerPlane[k] * v->final_flip_bw[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2560
v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2561
v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2562
v->cursor_bw[k] * v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2563
v->DPPPerPlane[k] * (v->final_flip_bw[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2564
v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2565
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2566
v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2569
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2570
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2571
v->DPPPerPlane[k] * (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2581
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2582
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2590
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2591
if (v->ErrorResult[k] || v->NotEnoughTimeForDynamicMetadata[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2628
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2629
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2630
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2631
v->ThisVStartup = v->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2634
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2639
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2640
v->ThisVStartup * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2642
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2760
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2762
v->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2763
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2764
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2770
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2771
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2772
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2776
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2777
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2778
v->MinTTUVBlank[k] = v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2780
if (!v->DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2781
v->MinTTUVBlank[k] = v->TCalc
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2782
+ v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2787
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2788
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2789
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2790
v->SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2791
v->SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2792
v->SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2793
v->SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2795
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2796
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2797
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2798
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2799
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2800
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2801
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2802
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2803
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2804
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2805
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2806
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2807
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2808
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2814
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2816
+ v->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2817
+ v->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2824
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2825
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2826
double margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2827
/ v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2897
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2899
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2902
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2903
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2904
&BytePerPixY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2905
&BytePerPixC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2906
&BytePerPixDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2907
&BytePerPixDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2908
&Read256BytesBlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2909
&Read256BytesBlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2910
&Read256BytesBlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2911
&Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3372
unsigned int j, k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3394
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3395
if (v->ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3396
&& ((v->SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3397
&& v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3398
&& v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3399
&& v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3400
&& v->SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3401
&& v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3402
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3403
|| v->HRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3404
|| v->htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3405
|| v->VRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3406
|| v->vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3408
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3409
|| v->htaps[k] < 1.0 || v->htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3410
|| (v->htaps[k] > 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3411
&& (v->htaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3412
|| v->HRatio[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3413
|| v->VRatio[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3414
|| v->HRatio[k] > v->htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3415
|| v->VRatio[k] > v->vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3416
|| (v->SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3417
&& v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3418
&& v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3419
&& v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3420
&& v->SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3421
&& v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3422
&& (v->VTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3423
|| v->VTAPsChroma[k] > 8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3424
|| v->HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3425
|| v->HTAPsChroma[k] > 8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3426
|| (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3427
|| v->HRatioChroma[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3428
|| v->VRatioChroma[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3429
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3430
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3437
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3438
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3439
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t || v->SurfaceTiling[k] == dm_sw_64kb_d_x)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3440
&& !(v->SourcePixelFormat[k] == dm_444_64))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3446
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3448
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3449
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3450
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3451
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3452
&v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3453
&v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3454
&v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3455
&v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3456
&v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3457
&v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3459
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3460
if (v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3461
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3462
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3464
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3465
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3468
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3469
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3470
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0) / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3472
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3473
if (v->WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3474
&& v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3475
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3476
* v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3477
/ (v->WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3478
* v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3479
/ v->PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3480
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3481
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3482
* v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3483
/ (v->WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3484
* v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3485
/ v->PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3487
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3494
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3495
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3498
if (v->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3504
if (v->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3516
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3517
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3539
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3540
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3541
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3542
|| v->WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3544
|| v->WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3546
|| v->WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3548
|| v->WritebackHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3550
|| v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3552
|| v->WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3553
> v->WritebackHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3554
|| v->WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3555
> v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3556
|| (v->WritebackHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3557
&& ((v->WritebackHTaps[k] % 2)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3561
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3569
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3570
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3573
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3574
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3575
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3576
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3577
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3578
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3579
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3580
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3581
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3585
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3586
if (v->HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3587
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3589
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3591
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3592
v->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3593
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3594
* dml_max3(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3595
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3596
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3599
if (v->HRatioChroma[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3600
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3601
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3603
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3605
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k] * dml_max5(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3606
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3607
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3608
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3610
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3611
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3612
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3616
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3620
if (v->SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3622
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3628
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3633
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3634
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3635
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3638
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3639
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3641
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3642
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3691
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3692
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3696
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3698
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3702
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3704
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3708
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3712
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3715
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3719
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3722
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3725
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3728
if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3729
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3730
if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3731
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3734
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3738
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3739
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3740
if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3741
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3744
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3748
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3749
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3750
v->NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3751
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3752
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3753
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3754
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3755
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3757
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= v->MaxDppclkRoundedDownToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3758
&& v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3759
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3760
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3761
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3763
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3764
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3765
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3768
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3775
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3776
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3777
if (v->NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3786
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3787
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3788
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3789
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3790
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3804
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3805
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3806
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3807
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3808
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3809
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3811
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3812
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3813
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3816
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3819
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3822
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3828
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3829
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3853
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3854
if (!(v->DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3855
|| v->DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3856
|| v->DSCInputBitPerComponent[k] == 8.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3862
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3863
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3864
if (v->PixelClockBackEnd[k] > 3200) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3865
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3866
} else if (v->PixelClockBackEnd[k] > 1360) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3867
v->NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3868
} else if (v->PixelClockBackEnd[k] > 680) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3869
v->NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3870
} else if (v->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3871
v->NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3873
v->NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3876
v->NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3881
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3882
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3883
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3884
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3885
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3886
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3887
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3888
v->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3891
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3892
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3893
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3894
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3896
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3897
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3898
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3899
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3900
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3901
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3902
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3903
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3904
if (v->DSCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3905
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3907
if (v->Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3908
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3910
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3913
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3915
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3922
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3923
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3924
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3925
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3926
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3928
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3929
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3930
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3931
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3932
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3933
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3934
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3935
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3942
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3943
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3944
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3945
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3946
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3948
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3949
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3950
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3951
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3952
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3953
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3954
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3955
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3962
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3963
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3964
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3965
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3966
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3968
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3969
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3970
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3971
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3972
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3973
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3974
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3975
if (v->Outbpp == BPP_INVALID && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3977
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3979
if (v->Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3980
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3984
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3985
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3986
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3987
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3988
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3990
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3991
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3992
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3993
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3994
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3995
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3996
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3998
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4004
v->OutputBppPerState[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4010
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4011
if (!v->skip_dio_check[k] && v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4012
&& (v->OutputBppPerState[i][k] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4013
|| (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4021
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4022
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4023
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4034
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4035
if (v->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4036
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4038
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4052
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4053
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4056
v->BPP = v->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4058
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4059
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4060
v->DSCDelayPerState[i][k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4061
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4063
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4064
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4065
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4066
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4067
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4068
v->DSCDelayPerState[i][k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4070
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4072
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4073
v->NumberOfDSCSlices[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4074
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4075
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4077
v->DSCDelayPerState[i][k] = 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4079
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4081
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4082
v->NumberOfDSCSlices[k] / 4,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4083
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4084
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4086
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4088
v->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4091
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4093
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4094
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4104
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4105
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4106
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4107
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4151
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4152
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4153
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4154
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4155
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4156
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4157
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4158
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4163
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4164
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4169
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4170
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4171
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4172
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4173
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4174
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4175
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4176
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4177
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4181
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4182
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4183
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4187
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4188
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4189
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4191
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4201
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4202
v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4203
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4204
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4205
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4206
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4207
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4208
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4209
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4216
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4218
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4221
&v->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4223
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4227
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4236
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4238
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4239
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4240
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4242
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4243
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4244
&v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4245
&v->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4252
v->PrefetchLinesC[i][j][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4253
v->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4257
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4258
v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4259
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4260
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4261
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4262
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4263
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4264
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4265
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4272
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4273
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4274
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4277
&v->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4279
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4283
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4285
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4291
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4293
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4294
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4295
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4297
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4298
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4299
&v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4300
&v->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4301
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4302
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4303
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4307
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4308
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4309
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4310
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4311
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4314
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4315
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4318
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4319
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4320
&v->meta_row_bandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4321
&v->dpte_row_bandwidth[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4332
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4334
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4335
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4337
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4338
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4339
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4342
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4343
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4344
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4345
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4346
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4347
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4348
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4349
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4350
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4351
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4352
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4353
&NotUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4357
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4358
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4363
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4364
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4365
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4366
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4373
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4374
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4375
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4376
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4377
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4407
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4408
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4409
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4410
v->WritebackDelayTime[k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4412
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4413
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4414
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4415
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4416
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4417
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4418
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4419
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4421
v->WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4424
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4425
v->WritebackDelayTime[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4426
v->WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4441
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4443
if (v->BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4444
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4449
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4450
v->MaximumVStartup[i][j][k] = v->VTotal[k] - v->VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4451
- dml_max(1.0, dml_ceil(1.0 * v->WritebackDelayTime[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4452
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4517
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4518
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4549
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4550
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4551
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4552
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4553
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4554
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4555
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4556
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4557
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4558
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4559
v->ODMCombineEnabled[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4588
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4591
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4593
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4595
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4596
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4597
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4598
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4599
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4600
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4601
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4602
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4603
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4604
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4605
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4606
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4607
myPipe.ODMCombineEnabled = !!v->ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4609
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4611
k,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4613
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4614
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4615
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4616
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4620
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4621
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4622
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4623
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4624
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4625
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4626
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4627
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4628
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4629
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4630
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4631
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4632
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4633
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4634
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4635
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4637
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4638
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4639
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4640
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4641
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4642
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4643
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4644
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4645
&v->NoTimeForDynamicMetadata[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4648
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4650
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4651
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4653
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4654
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4655
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4658
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4659
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4660
v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4661
v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4662
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4663
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4664
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4665
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4666
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4667
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4668
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4669
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4673
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4674
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4675
* v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4679
v->VActivePixelBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4680
v->VActiveCursorBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4681
+ v->NoOfDPP[i][j][k] * (v->meta_row_bandwidth[i][j][k] + v->dpte_row_bandwidth[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4682
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4683
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4684
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k] * v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4685
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4686
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4687
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4691
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4692
if (v->NoUrgentLatencyHidingPre[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4702
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4703
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4704
|| v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4710
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4711
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4717
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4718
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4723
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4724
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4731
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4734
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4735
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4736
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k] * v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4737
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4738
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4739
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4742
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4743
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4744
+ v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4747
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4759
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4760
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4761
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4764
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4765
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4766
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4767
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4768
v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4769
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4770
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4771
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4772
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4773
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4774
&v->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4775
&v->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4776
&v->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4777
&v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4780
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4783
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4784
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4785
+ v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4786
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4787
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4788
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4789
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4790
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4791
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4792
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4798
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4799
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4845
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4846
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4855
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4856
if (v->CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4857
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4865
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4866
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4867
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4868
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4870
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4872
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4873
&& v->SourcePixelFormat[k] != dm_rgbe && v->SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4874
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4875
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4876
v->AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]), 64.0 * v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4878
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4881
v->AlignedCPitch[k] = v->PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4882
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4884
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k] || v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4885
|| v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4890
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4891
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4894
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4895
&& v->SourcePixelFormat[k] != dm_444_8 && v->SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4896
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k] || v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4937
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4938
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4939
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4988
unsigned int k, j;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4992
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4993
v->TotalActiveDPP = v->TotalActiveDPP + DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4994
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4995
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5004
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5005
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5022
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5024
v->LBLatencyHidingSourceLinesY = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5026
v->LBLatencyHidingSourceLinesC = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5028
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5030
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5032
LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5033
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5034
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5035
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5036
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5037
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5038
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5044
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5047
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5050
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5051
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5054
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5056
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5058
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5061
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5063
WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024 / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5064
if (v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5071
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5077
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5078
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5079
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5080
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5081
PlaneWithMinActiveDRAMClockChangeMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5084
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5095
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5096
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5097
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5102
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5103
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5117
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5118
if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5119
FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5120
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5152
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5156
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5158
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5159
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5161
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5163
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5166
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5167
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5169
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5173
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5174
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(1.1 * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma, 1.1 * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5176
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5178
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(mode_lib->vba.DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5182
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5183
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5188
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5189
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5304
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5306
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5307
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5308
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5310
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5313
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5314
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5316
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5317
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5319
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5323
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5324
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5326
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5329
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5330
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5332
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5333
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5335
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5340
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5341
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5342
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5344
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5346
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5347
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5348
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5349
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5350
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5352
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5353
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5355
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5357
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5358
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5362
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5364
cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5365
if (NumberOfCursors[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5366
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5367
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5369
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5371
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5372
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5374
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5377
CursorRequestDeliveryTime[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5378
CursorRequestDeliveryTimePrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5450
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5452
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5453
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5454
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5455
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5457
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5459
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5460
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5461
DST_Y_PER_META_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5463
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5467
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5468
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5469
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5470
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5471
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5472
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5473
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5474
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5476
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5483
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5484
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5485
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5486
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5487
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5488
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5489
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5491
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5492
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5493
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5494
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5495
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5496
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5498
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5505
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5506
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5507
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5510
TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5511
TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5512
TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5513
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5514
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5515
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5519
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5521
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5522
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5524
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5526
dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5527
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5528
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5529
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5530
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5531
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5532
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5533
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5535
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5536
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5538
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5540
dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5541
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5542
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5543
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5546
time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5547
time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5548
time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5549
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5550
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5551
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5580
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5582
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5583
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5584
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5585
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5586
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5587
/ (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5588
/ (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5590
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5591
/ (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5595
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5596
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5597
/ (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5598
/ (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5600
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5601
/ (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5604
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5605
num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5606
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5607
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5608
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5610
num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5611
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5616
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5617
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5618
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5620
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5624
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5625
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5626
+ meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5628
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5631
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5632
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5633
+ dpde0_bytes_per_frame_ub_c[k] / 64 + meta_pte_bytes_per_frame_ub_l[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5634
/ 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5636
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5637
+ meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5642
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5644
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5646
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5648
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5652
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5653
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5654
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5655
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5659
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5660
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5661
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5662
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5724
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5726
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5727
LinesInDETY[k] = DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5728
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5729
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5739
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5740
if (FullDETBufferingTimeY[k] < StutterPeriod) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5741
StutterPeriod = FullDETBufferingTimeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5742
FrameTimeForMinFullDETBufferingTime = VTotal[k] * HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5743
BytePerPixelYCriticalPlane = BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5744
SwathWidthYCriticalPlane = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5745
LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5746
- (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5752
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5753
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5754
if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5755
|| (SourceScan[k] != dm_vert
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5756
&& BlockHeight256BytesY[k] > SwathHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5757
|| DCCYMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5762
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(DCCRateLuma[k], MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5764
if (ReadBandwidthPlaneChroma[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5765
if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5766
|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5767
|| DCCCMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5772
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneChroma[k] / dml_min(DCCRateChroma[k], MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5775
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5777
TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5787
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5788
if (WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5805
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5807
VBlankTime = (VTotal[k] - VActive[k]) * HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5872
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5906
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5907
if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5908
|| SourcePixelFormat[k] == dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5909
|| SourcePixelFormat[k] == dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5910
|| SourcePixelFormat[k] == dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5911
|| SourcePixelFormat[k] == dm_rgbe)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5912
if (SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5913
|| (SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5914
&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5915
&& SourceScan[k] != dm_vert)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5916
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5917
} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5918
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5920
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5922
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5924
if (SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5925
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5926
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5927
} else if (SourcePixelFormat[k] == dm_rgbe_alpha
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5928
&& SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5929
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5930
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5931
} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5932
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5933
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5934
} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5935
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5936
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5938
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5939
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5943
RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5944
* MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5945
RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5947
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5951
RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5952
* MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5953
RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5955
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5962
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5963
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5969
SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5970
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5976
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5977
SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5981
SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5982
SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5987
if (SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5988
DETBufferSizeY[k] = DETBufferSizeInKByte * 1024;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5989
DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5991
DETBufferSizeY[k] = DETBufferSizeInKByte * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5992
DETBufferSizeC[k] = DETBufferSizeInKByte * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5994
DETBufferSizeY[k] = DETBufferSizeInKByte * 1024 * 2 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5995
DETBufferSizeC[k] = DETBufferSizeInKByte * 1024 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6000
|| SwathWidth[k] > MaximumSwathWidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6001
|| (SwathHeightC[k] > 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6002
&& SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6004
ViewportSizeSupportPerPlane[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6006
ViewportSizeSupportPerPlane[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6042
unsigned int k, j;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6048
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6051
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6052
SwathWidthSingleDPPY[k] = ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6054
SwathWidthSingleDPPY[k] = ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6057
MainPlaneODMCombine = ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6059
if (BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6065
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6067
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6068
} else if (DPPPerPlane[k] == 2) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6069
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6071
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6074
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6075
SwathWidthC[k] = SwathWidthY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6076
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6078
SwathWidthC[k] = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6079
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6083
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6084
SwathWidthC[k] = SwathWidthSingleDPPC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6087
surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6088
surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6090
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6091
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6092
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6093
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6094
Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6095
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6096
surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6097
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6098
Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6100
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6103
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6104
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6105
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6106
Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6107
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6108
surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6109
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6110
Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6112
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6176
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6195
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6196
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6230
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6253
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6255
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6258
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6259
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6275
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6280
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6281
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6282
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + v->PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6283
/ NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * v->DPTEBytesPerRow[i][j][k] / PTEEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6284
/ NormalEfficiency / v->ReturnBusWidth + 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6285
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6286
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k]) / (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6287
DynamicMetadataVMExtraLatency[k] = (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6289
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - v->UrgLatency[i] * ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6290
: v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6294
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6295
DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6298
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6299
+ NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6302
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6304
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6313
v->RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6316
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6317
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6318
v->VTotal[k] - v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6319
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6320
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6321
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6327
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TsetupPipe
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6328
- TdmbfPipe - TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6330
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(DCFCLKRequiredForPeakBandwidthPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6333
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6338
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6339
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6343
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6345
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6346
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6350
/ (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6351
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
745
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
82
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
830
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
831
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
844
v->Tdmdl[k] = TWait + Tvm_trips + trip_to_mem;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
846
v->Tdmdl[k] = TWait + UrgentExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
849
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
850
if (VStartup * LineTime < Tsetup + v->Tdmdl[k] + Tdmbf + Tdmec + Tdmsks) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
858
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
864
v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
878
v->DSTXAfterScaler[k] = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
881
v->DSTXAfterScaler[k] = v->DSTXAfterScaler[k] + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
883
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && v->ProgressiveToInterlaceUnitInOPP))
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
884
v->DSTYAfterScaler[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
886
v->DSTYAfterScaler[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
888
DSTTotalPixelsAfterScaler = v->DSTYAfterScaler[k] * myPipe->HTotal + v->DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
889
v->DSTYAfterScaler[k] = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
890
v->DSTXAfterScaler[k] = DSTTotalPixelsAfterScaler - ((double) (v->DSTYAfterScaler[k] * myPipe->HTotal));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
901
v->Tno_bw[k] = UrgentExtraLatency + trip_to_mem * ((v->GPUVMMaxPageTableLevels - 2) - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
903
v->Tno_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
905
v->Tno_bw[k] = LineTime;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
907
v->Tno_bw[k] = LineTime / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
909
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, v->Tdmdl[k])) / LineTime
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
910
- (v->DSTYAfterScaler[k] + v->DSTXAfterScaler[k] / myPipe->HTotal);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
916
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k]) / Tsw_oto;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
919
Tvm_oto = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
951
dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", v->Tdmdl_vm[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
952
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
953
dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", v->DSTXAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
954
dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)v->DSTYAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
968
if (Tpre_rounded - v->Tno_bw[k] > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
972
+ PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
973
/ (Tpre_rounded - v->Tno_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
977
if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]) > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
978
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
981
if (Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
986
v->BytePerPixelC[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
987
(Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
995
swath_width_chroma_ub * v->BytePerPixelC[k]) / (Tpre_rounded -
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1182
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1184
for (k = 0; k < num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1185
visited[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1186
pipe_index_in_combine[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1990
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2022
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2023
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2027
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2028
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2029
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2030
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2031
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2032
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2033
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2034
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2035
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2040
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2041
if (v->HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2042
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2044
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2046
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2049
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2052
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2054
if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2055
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2058
if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2059
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2060
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2061
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2063
if (v->HRatioChroma[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2064
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2066
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2068
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2070
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2072
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2073
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2076
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2077
v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2080
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2084
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2085
if (v->BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2087
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2090
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2094
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2095
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2098
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2102
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2106
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2109
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2132
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2133
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2134
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2137
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2138
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2139
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2142
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2143
v->DPPCLK[k] = v->DPPCLK_calculated[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2152
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2153
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2154
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2155
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2156
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2157
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2158
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2159
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2160
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2161
&v->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2195
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2196
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2197
* v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2198
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2199
* v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2200
DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2226
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2227
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2228
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2230
if (v->OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2232
else if (v->OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2234
else if (v->OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2238
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2239
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2241
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2242
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2245
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2251
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2252
double BPP = v->OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2254
if (v->DSCEnabled[k] && BPP != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2255
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2256
v->DSCDelay[k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2257
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2259
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2260
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2261
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2262
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2263
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2264
v->DSCDelay[k] = 2
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2266
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2268
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2269
v->NumberOfDSCSlices[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2270
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2271
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2273
v->DSCDelay[k] = 4
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2275
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2277
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2278
v->NumberOfDSCSlices[k] / 4.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2279
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2280
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2282
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2284
v->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2288
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2290
if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2291
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2294
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2304
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2305
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2306
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2316
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2317
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2318
v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2319
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2320
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2321
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2322
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2323
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2324
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2331
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2332
v->DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2333
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2337
&v->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2338
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2339
&v->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2340
&v->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2341
&v->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2342
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2345
&v->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2346
&v->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2347
&v->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2348
&v->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2349
&v->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2351
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2353
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2354
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2355
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2357
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2358
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2359
&v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2360
&v->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2367
v->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2368
v->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2373
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2374
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2375
v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2376
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2377
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2378
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2379
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2380
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2381
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2388
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2389
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2390
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2394
&v->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2395
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2396
&v->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2397
&v->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2398
&v->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2399
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2400
&v->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2401
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2402
&v->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2403
&v->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2404
&v->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2405
&v->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2406
&v->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2408
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2410
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2411
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2412
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2414
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2415
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2416
&v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2417
&v->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2418
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2419
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2420
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2424
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2425
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2426
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2427
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2428
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2431
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2432
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2435
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2436
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2437
&v->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2438
&v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2443
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2444
v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2445
if (v->DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2446
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2447
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2448
|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2501
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2502
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2503
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2504
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2506
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2507
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2508
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2509
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2510
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2511
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2512
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2513
v->HTotal[k]) / v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2515
v->WritebackDelay[v->VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2517
if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2518
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2519
v->WritebackDelay[v->VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2529
v->HTotal[k]) / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2535
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2537
if (v->BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2538
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2540
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2541
v->MaxVStartupLines[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2542
(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2543
dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2544
v->VTotal[k] - v->VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2548
(double) v->WritebackDelay[v->VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2549
/ (v->HTotal[k] / v->PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
255
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2551
if (v->MaxVStartupLines[k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2552
v->MaxVStartupLines[k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2555
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2556
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2557
dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2562
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2563
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2592
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2595
myPipe.DPPCLK = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2597
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2599
myPipe.DPPPerPlane = v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2600
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2601
myPipe.VRatio = v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2602
myPipe.VRatioChroma = v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2603
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2604
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2605
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2606
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2607
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2608
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2609
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2610
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2611
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2612
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2613
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2614
|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2615
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2616
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2617
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2619
v->ErrorResult[k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2623
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2629
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2630
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2632
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2633
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2639
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2641
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2642
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2646
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2647
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2648
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2649
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2650
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2651
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2652
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2653
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2654
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2655
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2656
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2657
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2658
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2659
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2660
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2662
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2663
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2664
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2665
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2666
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2667
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2668
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2669
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2670
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2671
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2672
&v->NotEnoughTimeForDynamicMetadata[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2673
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2674
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2675
&v->Tdmdl_vm[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2676
&v->Tdmdl[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2677
&v->TSetup[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2678
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2679
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2680
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2683
dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2685
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2691
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2692
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2693
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2694
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2695
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2698
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2699
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2700
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2701
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2702
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2705
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2706
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2707
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2708
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2709
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2710
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2711
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2712
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2713
&v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2714
&v->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2715
&v->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2716
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2719
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2720
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2721
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2722
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2723
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2726
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2727
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2728
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2729
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2730
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2731
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2732
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2733
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2734
&v->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2735
&v->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2736
&v->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2737
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2741
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2742
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2743
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2744
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2745
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2746
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2747
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2748
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2749
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2753
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2754
v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2755
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2756
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2757
+ v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2760
dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2761
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2762
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2763
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2764
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2766
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2767
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2769
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2770
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2771
dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2772
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2773
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2774
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2775
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2776
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2777
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2778
dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2781
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2784
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2787
if (v->NoUrgentLatencyHiding[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2790
if (v->NoUrgentLatencyHidingPre[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2816
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2817
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2825
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2828
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2829
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2830
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2831
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2832
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2833
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2834
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2838
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2840
+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2842
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2845
k,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2849
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2850
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2851
v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2856
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2859
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2860
v->DPPPerPlane[k] * v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2861
+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2862
+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2863
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2864
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2865
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2866
+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2867
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2868
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2871
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2872
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2873
+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2874
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2875
* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2876
+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2888
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2889
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2892
__func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2961
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2962
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2963
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2965
v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2967
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3082
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3084
v->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3085
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3086
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3090
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3091
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3092
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3094
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3095
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3096
v->MinTTUVBlank[k] = v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3098
if (!v->DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3099
v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3104
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3105
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3106
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3107
v->SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3108
v->SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3109
v->SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3110
v->SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3111
v->DETBufferSizeInKByte[k] * 1024,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3112
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3113
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3114
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3115
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3116
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3117
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3118
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3119
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3120
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3121
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3122
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3123
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3124
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3125
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3129
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3131
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3133
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3136
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3139
dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3140
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3141
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3142
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3145
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3146
if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3147
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3150
isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3152
v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3153
- v->VFrontPorch[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3154
+ dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0))
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3155
+ dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3157
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3159
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3161
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3162
(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3163
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3165
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3168
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3169
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3170
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3171
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3172
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3173
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3174
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3175
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3176
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3177
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3178
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3187
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3188
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3189
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3190
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3191
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3192
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3193
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3200
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3201
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3286
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3288
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3291
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3292
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3293
&BytePerPixY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3294
&BytePerPixC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3295
&BytePerPixDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3296
&BytePerPixDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3297
&Read256BytesBlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3298
&Read256BytesBlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3299
&Read256BytesBlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3300
&Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3484
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3498
double LineTime = v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3506
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3512
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3519
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3520
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3529
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3532
v->final_flip_bw[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3533
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3534
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3535
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3536
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3538
v->final_flip_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3541
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3542
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3543
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3544
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3545
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3548
v->dpte_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3549
v->meta_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3550
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3551
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3554
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3555
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3556
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3557
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3559
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3563
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3565
v->ImmediateFlipSupportedForPipe[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3567
v->ImmediateFlipSupportedForPipe[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3571
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3572
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3576
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3678
unsigned k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3683
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3685
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3687
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3688
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3689
myPipe.VRatio = mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3690
myPipe.VRatioChroma = mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3692
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3693
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3694
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3695
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3696
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3697
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3698
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3699
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3700
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3701
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3702
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3703
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3704
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3705
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3706
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3708
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3712
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3718
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3719
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3721
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3722
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3728
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3730
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3731
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3735
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3736
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3737
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3738
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3739
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3740
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3741
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3742
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3743
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3744
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3745
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3746
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3747
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3748
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3749
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3751
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3752
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3753
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3754
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3755
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3756
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3757
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3758
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3759
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3760
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3761
&v->NoTimeForDynamicMetadata[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3762
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3763
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3764
&v->dummy7[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3765
&v->dummy8[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3766
&v->dummy13[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3767
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3768
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3769
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3790
unsigned int k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3811
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3812
if (v->ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3813
&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3814
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3815
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3816
&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3817
|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3819
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3820
|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3821
|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3822
|| v->VRatio[k] > v->vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3823
|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3824
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3825
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3826
&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3827
|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3828
|| v->HRatioChroma[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3829
|| v->VRatioChroma[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3830
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3831
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3838
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3839
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3840
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3841
|| v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3847
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3849
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3850
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3851
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3852
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3853
&v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3854
&v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3855
&v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3856
&v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3857
&v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3858
&v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3860
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3861
if (v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3862
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3863
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3865
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3866
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3869
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3870
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3871
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3872
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3873
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3875
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3876
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3877
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3878
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3879
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3880
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3881
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3883
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3890
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3891
if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3899
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3900
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3912
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3913
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3914
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3915
|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3916
|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3917
|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3918
|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3919
|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3920
|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3923
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3931
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3932
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3936
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3937
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3938
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3939
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3940
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3941
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3942
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3943
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3944
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3948
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3949
if (v->HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3950
v->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3952
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3954
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3956
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3957
v->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3958
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3960
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3961
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3963
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3964
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3967
if (v->HRatioChroma[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3968
v->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3970
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3972
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3974
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3976
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3977
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3978
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3979
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3981
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3982
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3983
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3987
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3991
if (v->SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3993
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3995
} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4001
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4006
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4007
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4008
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4011
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4012
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4014
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4015
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4065
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4066
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4071
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4074
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4079
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4082
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4087
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4092
|| !(v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4093
v->Output[k] == dm_dp2p0 ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4094
v->Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4095
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4098
if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4101
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4105
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4108
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4111
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4114
if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4115
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4116
if (v->HActive[k] / 2 > DCN31_MAX_DSC_IMAGE_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4117
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4120
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4124
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4125
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4126
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4128
} else if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4129
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4132
if (v->HActive[k] / 4 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4135
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4139
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4140
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4141
v->NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4142
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4143
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4144
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4145
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4146
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4148
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4149
<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4150
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4151
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4152
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4154
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4155
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4156
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4159
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4164
if (mode_lib->project == DML_PROJECT_DCN315 && v->DETSizeOverride[k] > DCN3_15_MAX_DET_SIZE && v->NoOfDPP[i][j][k] < 2) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4165
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4166
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4171
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4172
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4173
if (v->NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4175
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4176
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4188
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4189
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4190
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4191
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4192
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4207
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4208
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4209
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4210
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4211
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4212
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4215
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4216
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4217
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4222
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4225
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4228
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4235
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4236
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4260
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4261
if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4262
|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4268
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4269
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4270
if (v->PixelClockBackEnd[k] > 3200) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4271
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4272
} else if (v->PixelClockBackEnd[k] > 1360) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4273
v->NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4274
} else if (v->PixelClockBackEnd[k] > 680) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4275
v->NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4276
} else if (v->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4277
v->NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4279
v->NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4282
v->NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4287
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4288
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4289
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4290
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4291
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4292
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4293
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4294
v->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4297
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4298
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4299
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4300
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4302
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4303
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4304
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4305
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4306
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4307
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4308
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4309
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4310
if (v->DSCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4311
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4313
if (v->Output[k] == dm_dp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4314
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4316
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4319
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4321
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4322
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4324
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4327
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4329
if ((v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr10) &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4330
v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4333
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4334
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4335
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4336
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4337
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4339
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4340
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4341
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4342
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4343
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4344
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4345
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4346
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4347
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4348
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4352
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4353
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4354
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4355
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4356
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4358
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4359
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4360
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4361
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4362
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4363
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4364
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4366
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4371
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5) &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4372
v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4375
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4376
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4377
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4378
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4379
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4381
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4382
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4383
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4384
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4385
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4386
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4387
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4388
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4389
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4390
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4394
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4395
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4396
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4397
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4398
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4400
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4401
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4402
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4403
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4404
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4405
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4406
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4408
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4413
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr20) &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4414
v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4417
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4418
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4419
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4420
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4421
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4423
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4424
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4425
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4426
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4427
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4428
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4429
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4430
if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4431
v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4432
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4436
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4437
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4438
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4439
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4440
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4442
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4443
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4444
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4445
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4446
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4447
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4448
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4450
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4459
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4460
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4461
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4462
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4463
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4465
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4466
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4467
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4468
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4469
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4470
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4471
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4472
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4479
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4480
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4481
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4482
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4483
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4485
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4486
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4487
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4488
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4489
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4490
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4491
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4492
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4499
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4500
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4501
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4502
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4503
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4505
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4506
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4507
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4508
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4509
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4510
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4511
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4512
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4519
v->OutputBppPerState[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4526
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4527
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4528
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4529
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4530
v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4537
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4538
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4539
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4540
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4541
v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4542
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4545
if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4554
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4555
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4556
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4557
|| v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4568
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4569
if (v->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4570
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4572
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4586
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4587
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4590
v->BPP = v->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4592
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4593
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4594
v->DSCDelayPerState[i][k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4595
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4597
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4598
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4599
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4600
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4601
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4602
v->DSCDelayPerState[i][k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4604
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4606
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4607
v->NumberOfDSCSlices[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4608
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4609
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4611
v->DSCDelayPerState[i][k] = 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4613
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4615
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4616
v->NumberOfDSCSlices[k] / 4,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4617
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4618
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4620
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4622
v->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4625
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4627
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4628
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4638
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4639
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4640
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4641
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4708
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4709
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4710
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4711
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4712
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4713
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4714
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4715
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4716
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4721
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4722
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4723
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4730
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4731
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4732
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4733
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4734
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4735
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4736
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4737
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4738
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4742
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4743
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4744
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4748
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4749
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4750
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4752
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4753
&& v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4764
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4765
v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4766
v->Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4767
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4768
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4769
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4770
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4771
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4772
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4779
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4781
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4784
&v->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4786
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4790
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4799
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4801
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4802
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4803
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4805
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4806
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4807
&v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4808
&v->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4815
v->PrefetchLinesC[i][j][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4816
v->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4820
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4821
v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4822
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4823
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4824
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4825
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4826
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4827
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4828
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4835
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4836
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4837
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4840
&v->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4842
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4846
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4848
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4854
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4856
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4857
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4858
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4860
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4861
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4862
&v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4863
&v->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4864
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4865
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4866
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4870
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4871
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4872
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4873
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4874
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4877
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4878
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4881
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4882
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4883
&v->meta_row_bandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4884
&v->dpte_row_bandwidth[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4893
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4894
if (v->MetaRowBytes[i][j][k] > 24064)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4906
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4908
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4909
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4910
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4911
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4912
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4915
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4916
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4917
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4918
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4919
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4920
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4921
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4922
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4923
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4924
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4925
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4926
&NotUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4930
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4931
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4936
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4937
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4938
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4939
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4946
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4947
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4948
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4949
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4950
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4958
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4959
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4960
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4961
v->WritebackDelayTime[k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4963
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4964
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4965
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4966
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4967
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4968
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4969
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4970
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4972
v->WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4975
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4976
v->WritebackDelayTime[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4977
v->WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4992
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4994
if (v->BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4995
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5000
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5001
v->MaximumVStartup[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5002
(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5003
dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5004
v->VTotal[k] - v->VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5008
1.0 * v->WritebackDelayTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5009
/ (v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5010
/ v->PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5012
if (v->MaximumVStartup[i][j][k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5013
v->MaximumVStartup[i][j][k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5014
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5070
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5071
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5118
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5119
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5120
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5121
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5122
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5123
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5124
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5125
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5126
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5127
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5169
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5172
i, j, k);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5175
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5177
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5178
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5179
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5180
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5181
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5184
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5185
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5186
v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5187
v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5188
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5189
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5190
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5191
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5192
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5193
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5194
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5195
&v->NotUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5199
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5200
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5201
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5206
v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5207
+ v->VActiveCursorBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5208
+ v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5209
* (v->meta_row_bandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5210
+ v->dpte_row_bandwidth[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5211
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5212
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5213
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5214
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5215
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5216
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5217
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5221
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5222
if (v->NotUrgentLatencyHidingPre[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5232
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5233
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5234
|| v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5240
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5241
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5247
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5248
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5253
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5254
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5263
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5266
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5267
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5268
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5269
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5270
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5271
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5272
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5275
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5277
+ v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5278
+ v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5281
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5284
k,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5288
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5289
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5290
v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5293
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5296
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5297
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5298
+ v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5299
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5300
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5301
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5302
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5303
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5304
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5305
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5311
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5312
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5377
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5378
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5387
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5388
if (v->CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5389
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5397
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5398
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5399
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5400
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5402
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5404
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5405
&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5406
&& v->SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5407
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5408
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5409
v->AlignedDCCMetaPitchC[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5410
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5411
64.0 * v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5413
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5416
v->AlignedCPitch[k] = v->PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5417
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5419
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5420
|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5425
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5426
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5428
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5429
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5430
&& v->SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5431
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5432
|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5530
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5531
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5532
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5585
int k, j;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5603
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5604
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5621
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5623
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5624
/ (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5627
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5628
double EffectiveDETBufferSizeY = DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5632
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5636
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5638
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5640
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5644
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5647
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5648
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5649
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5650
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5651
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5652
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5653
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5660
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5664
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5667
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5669
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5673
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5675
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5677
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5680
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5682
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5683
if (v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5687
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5693
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5694
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5695
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5696
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5697
PlaneWithMinActiveDRAMClockChangeMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5700
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5711
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5712
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5713
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5714
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5720
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5721
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5773
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5775
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5777
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5778
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5780
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5782
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5785
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5786
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5788
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5792
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5793
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5794
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5796
v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5798
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5802
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5803
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5808
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5809
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5923
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5925
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5926
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5927
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5929
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5932
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5933
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5935
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5936
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5938
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5942
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5943
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5945
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5948
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5949
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5951
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5952
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5954
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5959
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5960
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5961
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5963
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5965
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5966
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5967
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5968
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5969
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5971
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5972
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5974
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5976
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5977
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5980
dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5981
dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5982
dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5983
dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5984
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5985
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5986
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5987
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5988
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5989
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5990
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5991
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5995
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5997
cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5998
if (NumberOfCursors[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5999
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6000
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6002
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6004
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6005
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6007
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6010
CursorRequestDeliveryTime[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6011
CursorRequestDeliveryTimePrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6014
dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6015
dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6016
dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6088
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6090
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6091
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6092
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6093
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6095
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6097
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6098
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6099
DST_Y_PER_META_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6101
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6105
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6106
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6107
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6108
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6109
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6110
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6111
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6112
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6114
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6121
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6122
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6123
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6124
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6125
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6126
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6127
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6129
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6130
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6131
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6132
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6133
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6134
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6136
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6143
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6144
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6145
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6148
TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6149
TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6150
TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6151
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6152
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6153
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6157
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6159
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6160
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6162
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6164
dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6165
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6166
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6167
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6168
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6169
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6170
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6171
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6173
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6174
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6176
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6178
dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6179
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6180
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6181
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6184
time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6185
time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6186
time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6187
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6188
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6189
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6218
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6220
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6221
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6222
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6223
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6224
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6225
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6227
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6231
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6232
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6233
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6235
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6238
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6239
num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6240
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6241
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6242
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6244
num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6245
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6250
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6251
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6252
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6254
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6258
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6259
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6261
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6264
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6265
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6266
+ meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6268
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6273
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6274
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6275
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6276
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6279
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6280
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6281
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6282
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6286
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6287
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6288
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6289
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6380
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6387
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6388
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6389
if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6390
|| DCCYMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6395
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6396
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6398
+ ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6399
if (ReadBandwidthPlaneChroma[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6400
if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6401
|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6407
+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6408
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6410
+ ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6413
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6415
TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6464
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6465
LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6466
/ BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6467
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6468
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6470
dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6471
dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6472
dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6473
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6474
dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6475
dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6476
dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6477
dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6478
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6479
dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6480
dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6481
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6484
if (k == 0 || DETBufferingTimeY < *StutterPeriod) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6485
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6488
FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6489
VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6490
BytePerPixelYCriticalPlane = BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6491
SwathWidthYCriticalPlane = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6492
LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6493
MinTTUVBlankCriticalPlane = MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6539
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6540
if (WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6570
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6571
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6664
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6698
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6699
unsigned int DETBufferSizeInKByte = DETBufferSizeInKByteA[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6701
if (DETSharedByAllDPP && DPPPerPlane[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6702
DETBufferSizeInKByte /= DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6703
if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6704
|| SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6705
if (SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6706
|| (SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6707
&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6708
&& SourceScan[k] != dm_vert)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6709
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6710
} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6711
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6713
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6715
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6717
if (SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6718
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6719
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6720
} else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6721
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6722
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6723
} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6724
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6725
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6726
} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6727
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6728
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6730
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6731
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6735
RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6736
RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6737
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6741
RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6742
RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6743
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6749
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6750
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6755
SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6756
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6761
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6762
SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6766
SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6767
SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6773
if (SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6774
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6775
DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6777
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6778
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6780
DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6781
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6784
if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6785
|| (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6787
ViewportSizeSupportPerPlane[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6789
ViewportSizeSupportPerPlane[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6827
int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6833
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6834
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6835
SwathWidthSingleDPPY[k] = ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6837
SwathWidthSingleDPPY[k] = ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6841
dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6842
dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6845
MainPlaneODMCombine = ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6847
if (BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6853
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6855
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6856
} else if (DPPPerPlane[k] == 2) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6857
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6859
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6863
dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6864
dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6867
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6868
SwathWidthC[k] = SwathWidthY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6869
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6871
SwathWidthC[k] = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6872
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6876
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6877
SwathWidthC[k] = SwathWidthSingleDPPC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6880
int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6881
int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6884
dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6887
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6888
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6889
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6890
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6891
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6892
int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6894
swath_width_chroma_ub[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6896
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6898
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6901
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6902
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6903
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6904
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6905
int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6907
swath_width_chroma_ub[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6909
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6911
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6983
int HostVMDynamicLevels = 0, k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7000
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7001
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7031
int dummy1, i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7053
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7055
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7058
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7059
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7087
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7092
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7093
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7094
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7095
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7096
+ 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7097
+ 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7098
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7099
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7100
/ (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7101
DynamicMetadataVMExtraLatency[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7102
(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7104
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7108
- DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7112
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7113
/ (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7114
DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7117
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7118
+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7121
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7123
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7132
v->RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7135
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7136
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7137
v->VTotal[k] - v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7138
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7139
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7140
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7149
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7150
- TdmsksPipe - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7152
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7153
DCFCLKRequiredForPeakBandwidthPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7156
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7161
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7162
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7169
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7171
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7172
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7177
2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7178
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1057
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1059
for (k = 0; k < num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1060
visited[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1061
pipe_index_in_combine[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2007
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2040
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2041
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2045
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2046
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2047
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2048
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2049
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2050
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2051
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2052
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2053
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2058
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2059
if (v->HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2060
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2062
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2064
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2067
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2069
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2070
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2072
if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2073
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2076
if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2077
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2078
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2079
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2081
if (v->HRatioChroma[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2082
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2084
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2086
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2088
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2090
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2091
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2094
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2095
v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2098
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2102
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2103
if (v->BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2105
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2108
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2112
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2113
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2116
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2120
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2124
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2127
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2151
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2152
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2155
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2156
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2157
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2160
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2161
v->DPPCLK[k] = v->DPPCLK_calculated[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2168
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2170
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2171
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2172
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2173
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2174
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2175
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2176
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2177
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2178
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2179
&v->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2213
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2214
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2215
* v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2216
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2217
* v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2218
DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2244
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2245
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2246
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2248
if (v->OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2250
else if (v->OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2252
else if (v->OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2256
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2257
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2259
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2260
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2263
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2269
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2270
double BPP = v->OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2272
if (v->DSCEnabled[k] && BPP != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2273
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2274
v->DSCDelay[k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2275
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2277
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2278
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2279
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2280
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2281
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2282
v->DSCDelay[k] = 2
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2284
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2286
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2287
v->NumberOfDSCSlices[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2288
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2289
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2291
v->DSCDelay[k] = 4
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2293
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2295
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2296
v->NumberOfDSCSlices[k] / 4.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2297
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2298
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2300
v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2301
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2303
v->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2307
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2309
if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2310
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2313
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2323
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2324
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2325
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2335
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2336
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2337
v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2338
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2339
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2340
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2341
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2342
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2343
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2350
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2351
v->DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2352
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2356
&v->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2357
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2358
&v->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2359
&v->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2360
&v->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2361
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2364
&v->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2365
&v->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2366
&v->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2367
&v->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2368
&v->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2370
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2372
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2373
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2374
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2376
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2377
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2378
&v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2379
&v->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2386
v->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2387
v->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2392
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2393
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2394
v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2395
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2396
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2397
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2398
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2399
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2400
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2407
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2408
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2409
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2413
&v->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2414
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2415
&v->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2416
&v->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2417
&v->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2418
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2419
&v->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2420
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2421
&v->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2422
&v->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2423
&v->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2424
&v->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2425
&v->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2427
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2429
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2430
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2431
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2433
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2434
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2435
&v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2436
&v->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2437
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2438
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2439
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2443
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2444
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2445
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2446
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2447
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2450
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2451
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2454
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2455
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2456
&v->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2457
&v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2462
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2463
v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2464
if (v->DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2465
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2466
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2467
|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2520
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2521
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2522
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2523
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2525
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2526
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2527
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2528
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2529
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2530
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2531
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2532
v->HTotal[k]) / v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2534
v->WritebackDelay[v->VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2536
if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2537
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2538
v->WritebackDelay[v->VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2548
v->HTotal[k]) / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2554
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2556
if (v->BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2557
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2559
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2560
v->MaxVStartupLines[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2562
v->VTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2563
v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2564
v->VBlankNom[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2565
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2566
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2568
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2570
v->WritebackDelay[v->VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2573
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2574
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2575
dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2580
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2581
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2611
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2614
myPipe.DPPCLK = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2616
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2618
myPipe.DPPPerPlane = v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2619
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2620
myPipe.VRatio = v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2621
myPipe.VRatioChroma = v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2622
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2623
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2624
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2625
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2626
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2627
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2628
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2629
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2630
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2631
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2632
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2633
|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2634
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2635
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2636
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2638
v->ErrorResult[k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
264
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2642
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2648
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2649
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2651
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2652
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2658
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2660
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2661
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2665
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2666
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2667
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2668
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2669
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2670
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2671
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2672
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2673
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2674
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2675
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2676
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2677
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2678
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2679
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2681
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2682
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2683
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2684
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2685
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2686
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2687
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2688
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2689
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2690
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2691
&v->NotEnoughTimeForDynamicMetadata[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2692
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2693
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2694
&v->Tdmdl_vm[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2695
&v->Tdmdl[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2696
&v->TSetup[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2697
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2698
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2699
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2702
dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2704
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2710
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2711
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2712
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2713
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2714
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2717
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2718
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2719
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2720
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2721
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2724
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2725
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2726
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2727
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2728
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2729
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2730
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2731
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2732
&v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2733
&v->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2734
&v->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2735
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2738
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2739
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2740
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2741
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2742
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2745
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2746
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2747
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2748
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2749
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2750
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2751
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2752
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2753
&v->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2754
&v->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2755
&v->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2756
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2760
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2761
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2762
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2763
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2764
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2765
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2766
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2767
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2768
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2772
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2773
v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2774
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2775
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2776
+ v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2779
dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2780
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2781
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2782
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2783
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2785
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2786
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2788
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2789
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2790
dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2791
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2792
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2793
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2794
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2795
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2796
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2797
dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2800
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2803
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2806
if (v->NoUrgentLatencyHiding[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2809
if (v->NoUrgentLatencyHidingPre[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2835
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2836
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2844
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2847
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2848
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2849
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2850
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2851
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2852
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2853
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2857
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2859
+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2861
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2864
k,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2868
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2869
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2870
v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2875
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2878
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2879
v->DPPPerPlane[k] * v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2880
+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2881
+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2882
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2883
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2884
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2885
+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2886
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2887
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2890
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2891
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2892
+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2893
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2894
* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2895
+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2907
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2908
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2910
dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2980
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2981
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2982
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2984
v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2986
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3101
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3103
v->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3104
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3105
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3109
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3110
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3111
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3113
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3114
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3115
v->MinTTUVBlank[k] = v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3117
if (!v->DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3118
v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3123
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3124
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3125
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3126
v->SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3127
v->SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3128
v->SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3129
v->SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3131
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3132
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3133
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3134
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3135
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3136
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3137
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3138
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3139
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3140
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3141
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3142
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3143
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3144
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3148
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3150
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3152
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3155
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3158
dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3159
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3160
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3161
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3164
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3165
if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3166
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3169
isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3170
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3171
if (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3172
v->MIN_DST_Y_NEXT_START[k] = dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3174
v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3176
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3177
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3179
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3180
(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3181
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3183
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3186
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3187
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3188
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3189
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3190
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3191
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3192
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3193
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3194
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3195
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3196
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3206
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3207
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3208
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3209
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3210
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3211
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3212
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3219
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3220
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3305
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3307
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3310
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3311
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3312
&BytePerPixY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3313
&BytePerPixC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3314
&BytePerPixDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3315
&BytePerPixDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3316
&Read256BytesBlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3317
&Read256BytesBlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3318
&Read256BytesBlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3319
&Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3590
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3604
double LineTime = v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3612
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3618
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3625
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3626
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3635
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3638
v->final_flip_bw[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3639
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3640
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3641
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3642
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3644
v->final_flip_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3647
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3648
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3649
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3650
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3651
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3654
v->dpte_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3655
v->meta_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3656
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3657
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3660
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3661
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3662
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3663
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3665
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3669
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3671
v->ImmediateFlipSupportedForPipe[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3673
v->ImmediateFlipSupportedForPipe[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3677
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3678
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3682
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3784
unsigned int k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3789
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3791
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3793
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3794
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3795
myPipe.VRatio = mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3796
myPipe.VRatioChroma = mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3798
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3799
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3800
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3801
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3802
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3803
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3804
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3805
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3806
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3807
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3808
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3809
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3810
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3811
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3812
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3814
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3818
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3824
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3825
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3827
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3828
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3834
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3836
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3837
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3841
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3842
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3843
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3844
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3845
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3846
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3847
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3848
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3849
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3850
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3851
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3852
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3853
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3854
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3855
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3857
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3858
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3859
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3860
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3861
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3862
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3863
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3864
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3865
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3866
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3867
&v->NoTimeForDynamicMetadata[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3868
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3869
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3870
&v->dummy7[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3871
&v->dummy8[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3872
&v->dummy13[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3873
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3874
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3875
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3883
unsigned int k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3904
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3905
if (v->ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3906
&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3907
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3908
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3909
&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3910
|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3912
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3913
|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3914
|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3915
|| v->VRatio[k] > v->vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3916
|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3917
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3918
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3919
&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3920
|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3921
|| v->HRatioChroma[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3922
|| v->VRatioChroma[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3923
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3924
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3931
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3932
if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3938
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3940
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3941
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3942
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3943
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3944
&v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3945
&v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3946
&v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3947
&v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3948
&v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3949
&v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3951
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3952
if (v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3953
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3954
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3956
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3957
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3960
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3961
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3962
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3963
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3964
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3966
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3967
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3968
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3969
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3970
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3971
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3972
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3974
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3981
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3982
if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3990
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3991
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4003
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4004
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4005
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4006
|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4007
|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4008
|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4009
|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4010
|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4011
|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4014
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4022
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4023
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4027
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4028
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4029
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4030
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4031
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4032
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4033
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4034
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4035
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4039
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4040
if (v->HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4041
v->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4043
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4045
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4047
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4048
v->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4049
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4052
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4054
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4055
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4058
if (v->HRatioChroma[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4059
v->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4061
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4063
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4065
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4067
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4068
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4069
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4070
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4072
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4073
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4074
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4078
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4082
if (v->SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4084
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4086
} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4092
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4097
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4098
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4099
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4102
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4103
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4105
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4106
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4155
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4156
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4161
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4164
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4169
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4172
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4177
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4182
|| !(v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4183
v->Output[k] == dm_dp2p0 ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4184
v->Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4185
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4188
if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4191
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4195
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4198
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4201
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4204
if (v->DSCEnabled[k] && v->HActive[k] > DCN314_MAX_DSC_IMAGE_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4205
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4206
if (v->HActive[k] / 2 > DCN314_MAX_DSC_IMAGE_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4207
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4210
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4214
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN314_MAX_FMT_420_BUFFER_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4215
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4216
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4218
} else if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4219
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4222
if (v->HActive[k] / 4 > DCN314_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4225
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4229
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4230
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4231
v->NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4232
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4233
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4234
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4235
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4236
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4238
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4239
<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4240
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4241
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4242
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4244
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4245
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4246
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4249
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4257
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4258
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4259
if (v->NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4261
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4262
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4275
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4276
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4277
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4278
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4279
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4294
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4295
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4296
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4297
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4298
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4299
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4302
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4303
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4304
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4309
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4312
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4315
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4322
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4323
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4347
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4348
if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4349
|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4355
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4356
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4357
if (v->PixelClockBackEnd[k] > 3200) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4358
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4359
} else if (v->PixelClockBackEnd[k] > 1360) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4360
v->NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4361
} else if (v->PixelClockBackEnd[k] > 680) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4362
v->NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4363
} else if (v->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4364
v->NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4366
v->NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4369
v->NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4374
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4375
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4376
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4377
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4378
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4379
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4380
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4381
v->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4384
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4385
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4386
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4387
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4389
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4390
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4391
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4392
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4393
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4394
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4395
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4396
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4397
if (v->DSCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4398
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4400
if (v->Output[k] == dm_dp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4401
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4403
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4406
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4408
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4409
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4411
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4414
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4416
if ((v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr10) &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4417
v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4420
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4421
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4422
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4423
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4424
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4426
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4427
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4428
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4429
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4430
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4431
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4432
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4433
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4434
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4435
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4439
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4440
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4441
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4442
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4443
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4445
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4446
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4447
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4448
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4449
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4450
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4451
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4453
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4458
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5) &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4459
v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4462
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4463
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4464
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4465
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4466
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4468
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4469
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4470
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4471
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4472
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4473
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4474
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4475
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4476
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4477
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4481
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4482
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4483
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4484
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4485
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4487
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4488
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4489
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4490
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4491
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4492
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4493
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4495
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4500
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr20) &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4501
v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4504
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4505
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4506
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4507
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4508
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4510
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4511
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4512
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4513
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4514
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4515
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4516
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4517
if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4518
v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4519
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4523
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4524
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4525
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4526
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4527
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4529
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4530
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4531
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4532
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4533
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4534
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4535
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4537
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4546
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4547
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4548
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4549
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4550
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4552
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4553
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4554
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4555
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4556
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4557
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4558
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4559
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4566
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4567
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4568
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4569
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4570
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4572
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4573
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4574
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4575
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4576
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4577
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4578
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4579
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4586
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4587
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4588
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4589
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4590
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4592
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4593
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4594
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4595
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4596
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4597
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4598
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4599
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4606
v->OutputBppPerState[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4613
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4614
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4615
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4616
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4617
v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4624
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4625
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4626
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4627
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4628
v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4629
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4632
if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4642
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4643
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4644
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4645
|| v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4656
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4657
if (v->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4658
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4660
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4674
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4675
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4678
v->BPP = v->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4680
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4681
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4682
v->DSCDelayPerState[i][k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4683
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4685
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4686
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4687
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4688
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4689
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4690
v->DSCDelayPerState[i][k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4692
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4694
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4695
v->NumberOfDSCSlices[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4696
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4697
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4699
v->DSCDelayPerState[i][k] = 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4701
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4703
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4704
v->NumberOfDSCSlices[k] / 4,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4705
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4706
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4708
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelayPerState[i][k] / v->HActive[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4709
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4711
v->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4714
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4716
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4717
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4727
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4728
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4729
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4730
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4794
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4795
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4796
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4797
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4798
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4799
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4800
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4801
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4802
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4807
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4808
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4809
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4816
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4817
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4818
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4819
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4820
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4821
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4822
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4823
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4824
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4828
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4829
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4830
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4834
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4835
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4836
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4838
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4839
&& v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4850
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4851
v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4852
v->Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4853
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4854
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4855
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4856
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4857
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4858
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4865
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4867
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4870
&v->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4872
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4876
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4885
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4887
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4888
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4889
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4891
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4892
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4893
&v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4894
&v->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4901
v->PrefetchLinesC[i][j][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4902
v->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4906
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4907
v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4908
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4909
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4910
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4911
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4912
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4913
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4914
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4921
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4922
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4923
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4926
&v->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4928
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4932
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4934
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4940
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4942
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4943
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4944
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4946
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4947
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4948
&v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4949
&v->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4950
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4951
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4952
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4956
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4957
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4958
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4959
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4960
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4963
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4964
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4967
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4968
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4969
&v->meta_row_bandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4970
&v->dpte_row_bandwidth[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4981
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4982
if (v->MetaRowBytes[i][j][k] > 24064)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4994
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4996
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4997
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4998
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4999
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5000
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5003
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5004
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5005
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5006
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5007
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5008
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5009
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5010
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5011
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5012
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5013
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5014
&NotUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5018
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5019
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5024
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5025
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5026
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5027
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5034
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5035
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5036
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5037
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5038
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5046
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5047
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5048
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5049
v->WritebackDelayTime[k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5051
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5052
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5053
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5054
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5055
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5056
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5057
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5058
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5060
v->WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5063
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5064
v->WritebackDelayTime[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5065
v->WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5080
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5082
if (v->BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5083
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5088
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5089
v->MaximumVStartup[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5091
v->VTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5092
v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5093
v->VBlankNom[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5094
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5095
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5097
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5099
v->WritebackDelayTime[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5100
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5156
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5157
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5204
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5205
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5206
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5207
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5208
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5209
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5210
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5211
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5212
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5213
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5255
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5258
i, j, k);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5261
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5263
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5264
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5265
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5266
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5267
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5270
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5271
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5272
v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5273
v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5274
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5275
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5276
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5277
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5278
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5279
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5280
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5281
&v->NotUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5285
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5286
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5287
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5292
v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5293
+ v->VActiveCursorBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5294
+ v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5295
* (v->meta_row_bandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5296
+ v->dpte_row_bandwidth[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5297
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5298
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5299
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5300
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5301
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5302
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5303
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5307
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5308
if (v->NotUrgentLatencyHidingPre[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5318
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5319
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5320
|| v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5326
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5327
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5333
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5334
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5339
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5340
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5349
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5352
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5353
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5354
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5355
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5356
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5357
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5358
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5361
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5363
+ v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5364
+ v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5367
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5370
k,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5374
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5375
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5376
v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5379
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5382
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5383
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5384
+ v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5385
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5386
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5387
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5388
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5389
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5390
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5391
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5397
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5398
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5463
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5464
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5473
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5474
if (v->CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5475
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5483
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5484
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5485
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5486
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5488
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5490
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5491
&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5492
&& v->SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5493
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5494
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5495
v->AlignedDCCMetaPitchC[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5496
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5497
64.0 * v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5499
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5502
v->AlignedCPitch[k] = v->PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5503
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5505
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5506
|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5511
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5512
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5514
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5515
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5516
&& v->SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5517
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5518
|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5624
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5625
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5626
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5679
int k, j;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5697
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5698
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5715
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5717
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5718
/ (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5721
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5722
double EffectiveDETBufferSizeY = DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5726
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5730
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5732
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5734
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5738
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5741
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5742
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5743
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5744
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5745
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5746
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5747
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5754
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5758
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5761
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5763
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5767
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5769
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5771
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5774
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5776
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5777
if (v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5781
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5787
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5788
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5789
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5790
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5791
PlaneWithMinActiveDRAMClockChangeMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5794
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5805
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5806
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5807
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5808
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5814
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5815
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5867
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5869
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5871
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5872
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5874
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5876
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5879
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5880
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5882
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5886
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5887
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5888
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5890
v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5892
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5896
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5897
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5902
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5903
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6017
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6019
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6020
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6021
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6023
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6026
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6027
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6029
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6030
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6032
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6036
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6037
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6039
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6042
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6043
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6045
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6046
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6048
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6053
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6054
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6055
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6057
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6059
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6060
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6061
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6062
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6063
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6065
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6066
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6068
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6070
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6071
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6074
dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6075
dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6076
dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6077
dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6078
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6079
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6080
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6081
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6082
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6083
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6084
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6085
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6089
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6092
cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6093
if (NumberOfCursors[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6094
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6095
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6097
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6099
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6100
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6102
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6105
CursorRequestDeliveryTime[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6106
CursorRequestDeliveryTimePrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6109
dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6110
dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6111
dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6183
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6185
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6186
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6187
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6188
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6190
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6192
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6193
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6194
DST_Y_PER_META_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6196
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6200
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6201
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6202
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6203
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6204
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6205
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6206
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6207
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6209
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6216
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6217
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6218
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6219
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6220
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6221
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6222
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6224
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6225
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6226
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6227
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6228
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6229
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6231
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6238
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6239
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6240
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6243
TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6244
TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6245
TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6246
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6247
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6248
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6252
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6254
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6255
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6257
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6259
dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6260
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6261
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6262
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6263
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6264
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6265
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6266
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6268
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6269
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6271
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6273
dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6274
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6275
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6276
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6279
time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6280
time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6281
time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6282
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6283
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6284
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6313
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6315
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6316
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6317
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6318
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6319
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6320
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6322
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6326
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6327
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6328
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6330
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6333
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6334
num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6335
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6336
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6337
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6339
num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6340
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6345
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6346
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6347
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6349
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6353
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6354
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6356
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6359
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6360
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6361
+ meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6363
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6368
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6369
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6370
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6371
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6374
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6375
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6376
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6377
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6381
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6382
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6383
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6384
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6475
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6482
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6483
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6484
if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6485
|| DCCYMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6490
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6491
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6493
+ ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6494
if (ReadBandwidthPlaneChroma[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6495
if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6496
|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6502
+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6503
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6505
+ ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6508
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6510
TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6559
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6560
LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6561
/ BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6562
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6563
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6565
dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6566
dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6567
dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6568
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6569
dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6570
dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6571
dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6572
dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6573
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6574
dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6575
dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6576
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6579
if (k == 0 || DETBufferingTimeY < *StutterPeriod) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6580
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6583
FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6584
VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6585
BytePerPixelYCriticalPlane = BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6586
SwathWidthYCriticalPlane = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6587
LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6588
MinTTUVBlankCriticalPlane = MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6634
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6635
if (WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6665
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6666
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6758
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6792
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6793
if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6794
|| SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6795
if (SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6796
|| (SourcePixelFormat[k] == dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6797
&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6798
&& SourceScan[k] != dm_vert)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6799
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6800
} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6801
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6803
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6805
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6807
if (SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6808
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6809
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6810
} else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6811
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6812
MinimumSwathHeightC = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6813
} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6814
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6815
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6816
} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6817
MinimumSwathHeightY = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6818
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6820
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6821
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6825
RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6826
RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6827
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6831
RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6832
RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6833
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6839
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6840
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6845
SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6846
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6851
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6852
SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6856
SwathHeightY[k] = MinimumSwathHeightY;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6857
SwathHeightC[k] = MinimumSwathHeightC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6864
if (SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6865
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6866
DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6868
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6869
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6871
DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6872
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6875
if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6876
|| (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6878
ViewportSizeSupportPerPlane[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6880
ViewportSizeSupportPerPlane[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6918
int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6924
for (k = 0; k < NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6925
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6926
SwathWidthSingleDPPY[k] = ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6928
SwathWidthSingleDPPY[k] = ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6932
dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6933
dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6936
MainPlaneODMCombine = ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6938
if (BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6944
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6946
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6947
else if (DPPPerPlane[k] == 2)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6948
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6950
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6953
dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6954
dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6957
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6958
SwathWidthC[k] = SwathWidthY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6959
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6961
SwathWidthC[k] = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6962
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6966
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6967
SwathWidthC[k] = SwathWidthSingleDPPC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6970
int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6971
int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6974
dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6977
if (SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6978
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6979
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6980
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6981
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6982
int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6984
swath_width_chroma_ub[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6986
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6988
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6991
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6992
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6993
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6994
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6995
int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6997
swath_width_chroma_ub[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6999
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7001
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7073
int HostVMDynamicLevels = 0, k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7089
for (k = 0; k < NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7090
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7118
int dummy1, i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7140
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7142
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7145
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7146
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7173
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7178
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7179
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7180
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7181
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7182
+ 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7183
+ 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7184
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7185
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7186
/ (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7187
DynamicMetadataVMExtraLatency[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7188
(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7190
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7194
- DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7199
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7200
/ (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7201
DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7204
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7205
+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7208
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7210
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7219
v->RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7222
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7223
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7224
v->VTotal[k] - v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7225
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7226
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7227
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7236
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7237
- TdmsksPipe - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7239
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7240
DCFCLKRequiredForPeakBandwidthPerPlane[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7243
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7248
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7249
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7256
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7259
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7260
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7265
2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7266
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1144
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1146
for (k = 0; k < num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1147
visited[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1148
pipe_index_in_combine[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2738
for (int k = start_index; k < end_index; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2739
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2740
swap_table_entries(&table[k], &table[k+1]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1020
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1021
if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1023
+ mode_lib->vba.DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1024
* (v->PDEAndMetaPTEBytesFrame[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1025
+ v->MetaRowByte[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1026
if (v->use_one_row_for_frame_flip[k][0][0]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1029
+ 2 * v->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
103
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1033
+ v->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1037
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
104
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1046
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1047
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1048
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1051
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1052
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1053
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1054
mode_lib->vba.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1055
v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1056
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1057
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1058
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1059
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1060
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1061
v->Use_One_Row_For_Frame_Flip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1064
&v->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1065
&v->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1066
&v->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1067
&v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
107
mode_lib->vba.ODMCombineEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
108
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1124
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1125
if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1128
dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1143
for (uint k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1144
dml_print("DML::%s: ImmediateFlipRequirement[%d] = %d\n", __func__, k, mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
116
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
117
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
118
mode_lib->vba.HRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
119
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
120
mode_lib->vba.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
123
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1235
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1236
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1237
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1238
v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
124
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1240
v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1241
v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1244
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1245
v->WritebackAllowFCLKChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
125
mode_lib->vba.htaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
126
mode_lib->vba.HTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
127
mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
128
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
131
&v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
132
&v->DPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1366
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1368
v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1373
v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1377
v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1380
v->MinTTUVBlank[k] = v->Watermark.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1382
if (!mode_lib->vba.DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1383
v->MinTTUVBlank[k] = mode_lib->vba.TCalc + v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1387
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1389
dml_print("DML::%s: Calculate DCC configuration for surface k=%d\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1392
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1394
mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1395
mode_lib->vba.SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1396
mode_lib->vba.SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1397
mode_lib->vba.SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1399
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
140
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1400
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1401
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1402
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1403
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1404
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1405
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1406
(enum dm_rotation_angle) mode_lib->vba.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1408
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1409
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
141
v->DPPCLK_calculated[k] = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1410
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1411
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1412
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1413
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1417
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1419
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1420
/ mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1422
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1423
v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1426
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1429
dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1430
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1431
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1432
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1435
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1436
if (mode_lib->vba.DynamicMetadataEnable[k] && mode_lib->vba.DynamicMetadataVMEnabled)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1437
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1439
isInterlaceTiming = (mode_lib->vba.Interlace[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
144
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1442
v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1443
mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1444
mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1446
dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1447
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1448
+ dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1449
/ mode_lib->vba.PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1451
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1453
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1454
/ mode_lib->vba.HTotal[k]) <= (isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1455
- mode_lib->vba.VActive[k] - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1456
(int) (mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1457
- mode_lib->vba.VFrontPorch[k] - v->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1458
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
146
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1460
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1463
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1464
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1465
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1466
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1467
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, mode_lib->vba.HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1468
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, mode_lib->vba.VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1469
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, mode_lib->vba.VActive[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
147
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1470
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, mode_lib->vba.VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1471
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1472
dml_print("DML::%s: k=%d, TSetup = %f\n", __func__, k, v->TSetup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1473
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1474
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1475
v->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1481
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1482
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1483
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1484
WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1485
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1486
/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1487
/ mode_lib->vba.PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1488
} else if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1489
WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1490
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1491
/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1492
/ mode_lib->vba.PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1498
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1499
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthSurfaceLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
150
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1500
+ v->ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1503
__func__, k, v->TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1505
__func__, k, v->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1507
__func__, k, v->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
151
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
152
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
153
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
154
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
155
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
156
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
157
&v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
158
&v->BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
159
&v->BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
160
&v->BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
161
&v->BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1728
unsigned int k, m;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1748
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1749
if (mode_lib->vba.ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1750
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1751
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1752
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1753
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1754
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1755
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1756
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1757
|| mode_lib->vba.HRatio[k] != 1.0 || mode_lib->vba.htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1758
|| mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1760
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] < 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1761
|| mode_lib->vba.htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1762
|| (mode_lib->vba.htaps[k] > 1.0 && (mode_lib->vba.htaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1763
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1764
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1765
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1766
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1767
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1768
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1769
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1770
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1771
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1772
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1773
&& (mode_lib->vba.VTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1774
|| mode_lib->vba.VTAPsChroma[k] > 8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1775
|| mode_lib->vba.HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1776
|| mode_lib->vba.HTAPsChroma[k] > 8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1777
|| (mode_lib->vba.HTAPsChroma[k] > 1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1778
&& mode_lib->vba.HTAPsChroma[k] % 2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1780
|| mode_lib->vba.HRatioChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1782
|| mode_lib->vba.VRatioChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1784
|| mode_lib->vba.HRatioChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1785
> mode_lib->vba.HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1786
|| mode_lib->vba.VRatioChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1787
> mode_lib->vba.VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1794
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1795
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1796
&& (!(!IsVertical((enum dm_rotation_angle) mode_lib->vba.SourceScan[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1797
|| mode_lib->vba.DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1802
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1804
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1805
mode_lib->vba.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1808
&mode_lib->vba.BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1809
&mode_lib->vba.BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1810
&mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1811
&mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1812
&mode_lib->vba.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1813
&mode_lib->vba.Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1814
&mode_lib->vba.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1815
&mode_lib->vba.Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1816
&mode_lib->vba.MacroTileHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1817
&mode_lib->vba.MacroTileHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1818
&mode_lib->vba.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1819
&mode_lib->vba.MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1823
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1824
if (!IsVertical(mode_lib->vba.SourceRotation[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1825
v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1826
v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1828
v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1829
v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1832
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1833
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1834
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1835
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1836
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1839
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1840
if (mode_lib->vba.WritebackEnable[k] == true && mode_lib->vba.WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1841
v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1842
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1843
/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1844
/ mode_lib->vba.PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1845
} else if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1846
v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1847
* mode_lib->vba.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1848
/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1849
/ mode_lib->vba.PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1851
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1858
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1859
if (mode_lib->vba.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1860
&& (v->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1870
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1871
if (mode_lib->vba.WritebackEnable[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1880
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1881
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1882
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1883
|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackMaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1884
|| mode_lib->vba.WritebackHRatio[k] < mode_lib->vba.WritebackMinHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1885
|| mode_lib->vba.WritebackVRatio[k] < mode_lib->vba.WritebackMinVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1886
|| mode_lib->vba.WritebackHTaps[k] > mode_lib->vba.WritebackMaxHSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1887
|| mode_lib->vba.WritebackVTaps[k] > mode_lib->vba.WritebackMaxVSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1888
|| mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1889
|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1890
|| (mode_lib->vba.WritebackHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1891
&& ((mode_lib->vba.WritebackHTaps[k] % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1894
if (2.0 * mode_lib->vba.WritebackDestinationWidth[k] * (mode_lib->vba.WritebackVTaps[k] - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1901
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1902
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k], mode_lib->vba.HRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1903
mode_lib->vba.VRatio[k], mode_lib->vba.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1905
mode_lib->vba.PixelClock[k], mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1906
mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1907
mode_lib->vba.VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1909
&mode_lib->vba.PSCL_FACTOR[k], &mode_lib->vba.PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1910
&mode_lib->vba.MinDPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1913
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1915
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1917
} else if (!IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1918
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1920
} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1921
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1923
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1925
} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelY[k] == 8 &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1926
mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1932
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1933
|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1939
* dml_max(mode_lib->vba.HRatio[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1940
/ (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1941
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1945
* dml_max(mode_lib->vba.HRatioChroma[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1946
/ (mode_lib->vba.VTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1947
+ dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1950
v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1952
v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2024
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2025
if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_reduce_voltage_and_clocks)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2027
if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_always_when_possible)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2040
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2043
mode_lib->vba.HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2044
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2045
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2046
mode_lib->vba.ODMUse[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
205
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2052
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2056
mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
206
v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2066
mode_lib->vba.HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2067
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2068
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2069
mode_lib->vba.ODMUse[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
207
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2075
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2079
mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
208
v->ReadBandwidthSurfaceChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
209
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2092
(mode_lib->vba.BlendingAndTiming[k] == k),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2093
mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2094
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2095
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2096
mode_lib->vba.HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2097
mode_lib->vba.PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2098
mode_lib->vba.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2099
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
210
* mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2100
mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2101
mode_lib->vba.AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2102
mode_lib->vba.AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2105
mode_lib->vba.DSCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2106
mode_lib->vba.OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2107
mode_lib->vba.OutputLinkDPRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2110
&mode_lib->vba.RequiresDSC[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2111
&mode_lib->vba.RequiresFEC[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2112
&mode_lib->vba.OutputBppPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2113
&mode_lib->vba.OutputTypePerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2114
&mode_lib->vba.OutputRatePerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2115
&mode_lib->vba.RequiredSlots[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2117
if (mode_lib->vba.RequiresDSC[i][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2118
mode_lib->vba.ODMCombineEnablePerState[i][k] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2119
mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2126
mode_lib->vba.ODMCombineEnablePerState[i][k] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2127
mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
213
__func__, k, v->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2136
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2137
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2138
mode_lib->vba.MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2139
mode_lib->vba.NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2140
} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2141
mode_lib->vba.MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2142
mode_lib->vba.NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2143
} else if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2144
mode_lib->vba.MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2145
mode_lib->vba.NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2147
mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
215
__func__, k, v->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2151
mode_lib->vba.SingleDPPViewportSizeSupportPerSurface[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2152
mode_lib->vba.MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2153
mode_lib->vba.NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2155
mode_lib->vba.MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2156
mode_lib->vba.NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2160
mode_lib->vba.MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2161
mode_lib->vba.NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2169
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2170
if (mode_lib->vba.NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2173
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2174
|| mode_lib->vba.SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2175
|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2176
|| mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2198
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2199
if (mode_lib->vba.MPCCombineUse[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2201
mode_lib->vba.MPCCombineUse[k] != dm_mpc_reduce_voltage &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2202
mode_lib->vba.ReadBandwidthLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2203
mode_lib->vba.ReadBandwidthChroma[k] >
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2205
(mode_lib->vba.ODMCombineEnablePerState[i][k] !=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2207
mode_lib->vba.ODMCombineEnablePerState[i][k] !=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2209
mode_lib->vba.MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2211
mode_lib->vba.ReadBandwidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2212
+ mode_lib->vba.ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2213
NumberOfNonCombinedSurfaceOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2228
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2229
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2233
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2234
mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2235
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2236
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2237
mode_lib->vba.WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2238
mode_lib->vba.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2239
mode_lib->vba.WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2240
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2241
mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2248
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2250
mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2253
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2254
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2263
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2264
mode_lib->vba.RequiredDPPCLK[i][j][k] = mode_lib->vba.RequiredDPPCLKThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2281
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2282
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2284
if (mode_lib->vba.Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2286
if (mode_lib->vba.OutputMultistreamId[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2287
== k || mode_lib->vba.OutputMultistreamEn[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2301
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2302
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2303
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2304
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2305
|| mode_lib->vba.DSCInputBitPerComponent[k] > mode_lib->vba.MaximumDSCBitsPerComponent) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2312
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2313
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2314
TotalSlots = mode_lib->vba.RequiredSlots[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2316
if (mode_lib->vba.OutputMultistreamId[j] == k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2319
if (mode_lib->vba.Output[k] == dm_dp && TotalSlots > 63)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2321
if (mode_lib->vba.Output[k] == dm_dp2p0 && TotalSlots > 64)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2326
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2327
if (mode_lib->vba.BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2328
&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2329
|| mode_lib->vba.Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2330
|| mode_lib->vba.Output[k] == dm_hdmi)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2331
&& mode_lib->vba.OutputBppPerState[i][k] == 0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2332
(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2351
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2352
if (mode_lib->vba.BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2353
&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2354
|| mode_lib->vba.Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2355
|| mode_lib->vba.Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2356
if (mode_lib->vba.OutputFormat[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2357
== dm_420 && mode_lib->vba.Interlace[k] == 1 &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2361
if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2363
if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.OutputFormat[k] == dm_n422
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2367
if (((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2368
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2369
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr3)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2370
&& mode_lib->vba.Output[k] != dm_dp && mode_lib->vba.Output[k] != dm_edp)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2371
|| ((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr10
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2372
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2373
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr20)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2374
&& mode_lib->vba.Output[k] != dm_dp2p0))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2377
if (mode_lib->vba.OutputMultistreamEn[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2378
if (mode_lib->vba.OutputMultistreamId[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2379
&& mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_na)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2381
if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2384
if (mode_lib->vba.OutputMultistreamId[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2385
&& mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2390
if ((mode_lib->vba.Output[k] == dm_edp || mode_lib->vba.Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2391
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2394
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2399
if (mode_lib->vba.Output[k] != dm_dp
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2400
&& (mode_lib->vba.ODMUse[k] == dm_odm_split_policy_1to2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2401
|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2402
|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2405
if ((mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2406
&& mode_lib->vba.OutputLinkDPLanes[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2407
|| (mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2408
&& mode_lib->vba.OutputLinkDPLanes[k] < 4))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2415
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2416
if (mode_lib->vba.BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2417
&& dml32_RequiredDTBCLK(mode_lib->vba.RequiresDSC[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2418
mode_lib->vba.PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2419
mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2420
mode_lib->vba.OutputBppPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2421
mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2422
mode_lib->vba.HActive[k], mode_lib->vba.AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2423
mode_lib->vba.AudioSampleLayout[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2433
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2434
if (mode_lib->vba.BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2435
&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2436
&& mode_lib->vba.Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2439
if (mode_lib->vba.BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2440
&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2441
&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2442
|| mode_lib->vba.Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2450
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2451
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2452
if (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2453
|| mode_lib->vba.Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2454
if (mode_lib->vba.OutputFormat[k] == dm_420) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2456
} else if (mode_lib->vba.OutputFormat[k] == dm_444) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2458
} else if (mode_lib->vba.OutputFormat[k] == dm_n422) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2463
if (mode_lib->vba.RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2464
if (mode_lib->vba.ODMCombineEnablePerState[i][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2466
if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2468
} else if (mode_lib->vba.ODMCombineEnablePerState[i][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2470
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2473
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2490
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2491
if (mode_lib->vba.RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2492
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2493
if (mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2497
if (mode_lib->vba.NumberOfDSCSlices[k] > 16)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2499
} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2500
if (mode_lib->vba.HActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2504
if (mode_lib->vba.NumberOfDSCSlices[k] > 8)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2507
if (mode_lib->vba.HActive[k] > mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2510
if (mode_lib->vba.NumberOfDSCSlices[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2521
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2522
mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2523
mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2524
mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2525
mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2526
mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2527
mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2528
mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2532
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2535
if (mode_lib->vba.BlendingAndTiming[k] == m &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2537
mode_lib->vba.DSCDelayPerState[i][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2549
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2550
mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2551
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2552
mode_lib->vba.ODMCombineEnableThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2553
mode_lib->vba.ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2620
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2621
mode_lib->vba.swath_width_luma_ub_all_states[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2622
mode_lib->vba.swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2623
mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2624
mode_lib->vba.swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2625
mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2626
mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2627
mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2628
mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2633
mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2634
mode_lib->vba.DETBufferSizeInKByteThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2635
mode_lib->vba.DETBufferSizeYAllStates[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2636
mode_lib->vba.DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2637
mode_lib->vba.DETBufferSizeCAllStates[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2638
mode_lib->vba.DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2643
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2644
mode_lib->vba.cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2645
* mode_lib->vba.CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2646
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2687
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2688
mode_lib->vba.swath_width_luma_ub_this_state[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2689
mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2690
mode_lib->vba.swath_width_chroma_ub_this_state[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2691
mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2692
mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2693
mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2694
mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2695
mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2696
mode_lib->vba.DETBufferSizeInKByteThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2697
mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2698
mode_lib->vba.DETBufferSizeYThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2699
mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2700
mode_lib->vba.DETBufferSizeCThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2701
mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2702
mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2703
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2707
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2708
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2711
+ mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2716
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2717
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2718
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2719
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2720
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2721
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2722
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2723
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2724
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2725
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2726
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2727
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2728
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2729
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2730
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2731
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2732
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2733
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2734
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2735
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2736
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2737
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ProgressiveToInterlaceUnitInOPP =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2739
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatio = mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2740
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2741
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2742
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2743
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchY = mode_lib->vba.PitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2744
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2745
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchC = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2746
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2747
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2748
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2749
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2750
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2751
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2752
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2753
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightY = mode_lib->vba.SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2754
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightC = mode_lib->vba.SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2824
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2825
mode_lib->vba.PrefetchLinesY[i][j][k] = mode_lib->vba.PrefetchLinesYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2826
mode_lib->vba.PrefetchLinesC[i][j][k] = mode_lib->vba.PrefetchLinesCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2827
mode_lib->vba.meta_row_bandwidth[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2828
mode_lib->vba.meta_row_bandwidth_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2829
mode_lib->vba.dpte_row_bandwidth[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2830
mode_lib->vba.dpte_row_bandwidth_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2831
mode_lib->vba.DPTEBytesPerRow[i][j][k] = mode_lib->vba.DPTEBytesPerRowThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2832
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2833
mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2834
mode_lib->vba.MetaRowBytes[i][j][k] = mode_lib->vba.MetaRowBytesThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2835
mode_lib->vba.use_one_row_for_frame[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2836
mode_lib->vba.use_one_row_for_frame_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2837
mode_lib->vba.use_one_row_for_frame_flip[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2838
mode_lib->vba.use_one_row_for_frame_flip_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2842
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2843
if (mode_lib->vba.PTEBufferSizeNotExceededPerState[k] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2848
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2849
if (mode_lib->vba.DCCMetaBufferSizeNotExceededPerState[k] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2862
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2864
mode_lib->vba.UsesMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2865
mode_lib->vba.swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2866
mode_lib->vba.swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2867
mode_lib->vba.SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2868
mode_lib->vba.SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2869
(double) mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2872
mode_lib->vba.CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2873
mode_lib->vba.CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2874
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2875
mode_lib->vba.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2876
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2877
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2878
mode_lib->vba.DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2879
mode_lib->vba.DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2881
&mode_lib->vba.UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2882
&mode_lib->vba.UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2883
&mode_lib->vba.UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2884
&mode_lib->vba.NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2914
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2915
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2916
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2917
mode_lib->vba.WritebackDelayTime[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2920
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2921
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2922
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2923
mode_lib->vba.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2924
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2925
mode_lib->vba.WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2926
mode_lib->vba.WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2927
mode_lib->vba.HTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2930
mode_lib->vba.WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2934
== k && mode_lib->vba.WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2935
mode_lib->vba.WritebackDelayTime[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2936
dml_max(mode_lib->vba.WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2952
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2954
if (mode_lib->vba.BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2955
mode_lib->vba.WritebackDelayTime[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2961
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2962
mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2964
dml_floor((mode_lib->vba.VTotal[k] -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2965
mode_lib->vba.VActive[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2966
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2968
mode_lib->vba.WritebackDelayTime[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2969
(mode_lib->vba.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2970
mode_lib->vba.PixelClock[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2973
if (mode_lib->vba.MaximumVStartup[i][j][k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2974
mode_lib->vba.MaximumVStartup[i][j][k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2977
mode_lib->vba.MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2998
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3000
|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3004
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3007
|| ((mode_lib->vba.ImmediateFlipRequirement[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3009
&& (mode_lib->vba.ImmediateFlipRequirement[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3017
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3020
((mode_lib->vba.HostVMEnable == true || mode_lib->vba.ImmediateFlipRequirement[k] !=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3022
(mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3023
mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3027
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3030
|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3031
|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3032
&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3033
|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_disable
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3034
|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3035
&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3042
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3043
if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3045
if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3047
if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3139
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3140
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth += mode_lib->vba.ReadBandwidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3141
+ mode_lib->vba.ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3173
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3174
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3175
mode_lib->vba.swath_width_luma_ub_this_state[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3176
mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3177
mode_lib->vba.swath_width_chroma_ub_this_state[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3178
mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3179
mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3180
mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3181
mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3182
mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3187
mode_lib->vba.DETBufferSizeInKByteThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3188
mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3189
mode_lib->vba.DETBufferSizeYThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3190
mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3191
mode_lib->vba.DETBufferSizeCThisState[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3192
mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3257
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3260
mode_lib->vba.UsesMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3262
mode_lib->vba.DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3268
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3270
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3272
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3273
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3274
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3275
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3276
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3277
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3278
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3279
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3280
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3281
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3282
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3283
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.HActive = mode_lib->vba.HActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3284
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3285
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ODMMode = mode_lib->vba.ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3286
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3287
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3288
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3292
mode_lib->vba.NoTimeForPrefetch[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3295
k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3298
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3299
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3300
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3301
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3305
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3306
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3307
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3308
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3309
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3310
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3311
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3312
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3313
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3314
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3315
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3316
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3317
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3318
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3319
v->SwathHeightCThisState[k], v->TWait,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3325
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3326
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3327
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3328
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3329
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3330
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3331
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3332
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3333
&v->RequiredPrefetchPixelDataBWLuma[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3334
&v->RequiredPrefetchPixelDataBWChroma[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3335
&v->NoTimeForDynamicMetadata[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3336
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3337
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3346
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3348
mode_lib->vba.UsesMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3349
mode_lib->vba.swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
335
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3350
mode_lib->vba.swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3351
mode_lib->vba.SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3352
mode_lib->vba.SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3353
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3355
mode_lib->vba.CursorWidth[k][0], mode_lib->vba.CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3356
mode_lib->vba.VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3357
mode_lib->vba.VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3358
mode_lib->vba.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3359
mode_lib->vba.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
336
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3360
mode_lib->vba.DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3361
mode_lib->vba.DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3363
&mode_lib->vba.UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3364
&mode_lib->vba.UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3365
&mode_lib->vba.UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3366
&mode_lib->vba.NotUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3368
v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3369
8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
337
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
339
if (mode_lib->vba.OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3403
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3404
if (mode_lib->vba.LineTimesForPrefetch[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3405
< 2.0 || mode_lib->vba.LinesForMetaPTE[k] >= 32.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3406
|| mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3407
|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
341
else if (mode_lib->vba.OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3413
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3414
if (mode_lib->vba.NoTimeForDynamicMetadata[i][j][k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3419
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3420
if (mode_lib->vba.VRatioPreY[i][j][k] > mode_lib->vba.MaxVRatioPre
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3421
|| mode_lib->vba.VRatioPreC[i][j][k] > mode_lib->vba.MaxVRatioPre
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3422
|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3427
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3428
if (mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3429
|| mode_lib->vba.LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
343
else if (mode_lib->vba.OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3455
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3456
if (!(mode_lib->vba.ImmediateFlipRequirement[k] ==
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3460
+ mode_lib->vba.NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3461
* mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3462
+ mode_lib->vba.MetaRowBytes[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3463
if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3466
* mode_lib->vba.DPTEBytesPerRow[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
347
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3470
+ mode_lib->vba.DPTEBytesPerRow[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3475
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
348
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3484
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3485
mode_lib->vba.MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3486
mode_lib->vba.DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3489
mode_lib->vba.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3490
(mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3491
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3492
mode_lib->vba.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3493
mode_lib->vba.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3494
mode_lib->vba.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3495
mode_lib->vba.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3496
mode_lib->vba.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3497
mode_lib->vba.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3498
mode_lib->vba.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3499
mode_lib->vba.use_one_row_for_frame_flip[i][j][k], // 24
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3502
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3503
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3504
&mode_lib->vba.final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3505
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
351
else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
352
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3536
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3537
if (!(mode_lib->vba.ImmediateFlipRequirement[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3539
&& (mode_lib->vba.ImmediateFlipSupportedForPipe[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
356
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3566
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3567
mode_lib->vba.use_one_row_for_frame_this_state[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3568
mode_lib->vba.use_one_row_for_frame[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3621
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3622
if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3623
if (mode_lib->vba.CursorBPP[k][0] == 64 && mode_lib->vba.Cursor64BppSupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
363
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3630
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3631
mode_lib->vba.AlignedYPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3632
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.SurfaceWidthY[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3633
mode_lib->vba.MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3634
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3635
mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3636
dml_max(mode_lib->vba.DCCMetaPitchY[k], mode_lib->vba.SurfaceWidthY[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3637
64.0 * mode_lib->vba.Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3639
mode_lib->vba.AlignedDCCMetaPitchY[k] = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
364
v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3641
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 && mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3642
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3643
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3644
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3645
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3646
mode_lib->vba.AlignedCPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3647
dml_max(mode_lib->vba.PitchC[k], mode_lib->vba.SurfaceWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3648
mode_lib->vba.MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3649
if (mode_lib->vba.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
365
mode_lib->vba.ODMCombineEnabled[k], mode_lib->vba.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3650
mode_lib->vba.AlignedDCCMetaPitchC[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3651
dml_max(mode_lib->vba.DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3652
mode_lib->vba.SurfaceWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3653
64.0 * mode_lib->vba.Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3655
mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3658
mode_lib->vba.AlignedCPitch[k] = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3659
mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
366
mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3661
if (mode_lib->vba.AlignedYPitch[k] > mode_lib->vba.PitchY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3662
|| mode_lib->vba.AlignedCPitch[k] > mode_lib->vba.PitchC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3663
|| mode_lib->vba.AlignedDCCMetaPitchY[k] > mode_lib->vba.DCCMetaPitchY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3664
|| mode_lib->vba.AlignedDCCMetaPitchC[k] > mode_lib->vba.DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
367
mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3670
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3671
if (mode_lib->vba.ViewportWidth[k] > mode_lib->vba.SurfaceWidthY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3672
|| mode_lib->vba.ViewportHeight[k] > mode_lib->vba.SurfaceHeightY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3674
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3675
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3676
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3677
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3678
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3679
if (mode_lib->vba.ViewportWidthChroma[k] > mode_lib->vba.SurfaceWidthC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
368
mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3680
|| mode_lib->vba.ViewportHeightChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3681
> mode_lib->vba.SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
369
mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
370
mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3714
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3715
mode_lib->vba.MPCCombineEnable[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3716
mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3717
mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3718
mode_lib->vba.SwathHeightY[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3719
mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3720
mode_lib->vba.SwathHeightC[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3721
mode_lib->vba.SwathHeightCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3722
mode_lib->vba.DETBufferSizeInKByte[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3723
mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3724
mode_lib->vba.DETBufferSizeY[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3725
mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3726
mode_lib->vba.DETBufferSizeC[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3727
mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3728
mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3729
mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
373
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3740
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3741
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3742
mode_lib->vba.ODMCombineEnabled[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3743
mode_lib->vba.ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3745
mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3748
mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3749
mode_lib->vba.FECEnable[k] = mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
375
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3750
mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
376
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
379
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
380
v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
381
&& (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
423
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
424
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
425
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
426
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
427
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
428
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
429
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
430
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
431
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
432
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
433
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthY = v->BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
434
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightY = v->BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
435
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthC = v->BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
436
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightC = v->BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
437
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
438
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
439
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
440
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
441
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
442
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
443
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
444
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
445
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatio = mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
446
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
447
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
448
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
449
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchY = mode_lib->vba.PitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
450
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
451
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchC = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
452
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
453
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
454
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
455
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
456
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
457
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
458
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
459
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightY = mode_lib->vba.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
460
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightC = mode_lib->vba.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
572
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
573
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
574
if (mode_lib->vba.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
576
+ mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
599
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
600
if (mode_lib->vba.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
601
if (mode_lib->vba.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
602
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = mode_lib->vba.WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
604
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
605
mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
606
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
607
mode_lib->vba.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
608
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
609
mode_lib->vba.WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
610
mode_lib->vba.WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
611
mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
613
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
615
if (mode_lib->vba.BlendingAndTiming[j] == k &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
617
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
618
dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
62
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
628
mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
634
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
636
if (mode_lib->vba.BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
637
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
648
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
649
dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
650
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
651
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
652
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
653
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
654
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
657
mode_lib->vba.CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
658
mode_lib->vba.CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
659
mode_lib->vba.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
660
mode_lib->vba.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
661
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
662
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
663
mode_lib->vba.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
664
mode_lib->vba.DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
667
&v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
668
&v->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
669
&v->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
670
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
672
v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
695
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
696
v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
698
dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
699
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
700
dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
701
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
704
if (v->MaxVStartupLines[k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
705
v->MaxVStartupLines[k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
708
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
709
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, mode_lib->vba.VoltageLevel);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
711
k, v->WritebackDelay[mode_lib->vba.VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
716
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
717
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
721
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
723
|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
748
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
754
mode_lib->vba.UsesMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
756
mode_lib->vba.DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
763
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
765
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
767
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
768
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
769
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
770
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
771
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
772
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
773
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
774
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
775
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
776
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
777
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
778
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.HActive = mode_lib->vba.HActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
779
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
780
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ODMMode = mode_lib->vba.ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
781
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
782
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
783
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
785
v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
787
k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
790
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
791
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
792
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
793
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
797
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
798
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
799
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
800
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
801
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
802
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
803
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
804
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
805
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
806
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
807
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
808
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
809
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
810
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
811
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
819
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
820
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
821
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
822
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
823
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
824
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
825
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
826
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
827
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
828
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
829
&v->NotEnoughTimeForDynamicMetadata[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
830
&v->Tno_bw[k], &v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
831
&v->Tdmdl_vm[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
832
&v->Tdmdl[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
833
&v->TSetup[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
834
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
835
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
836
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
840
__func__, k, mode_lib->vba.ErrorResult[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
842
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
845
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
846
dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
847
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
848
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
849
mode_lib->vba.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
85
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
850
mode_lib->vba.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
851
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
854
mode_lib->vba.CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
855
mode_lib->vba.CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
856
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
857
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
858
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
859
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
86
if (mode_lib->vba.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
860
mode_lib->vba.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
861
mode_lib->vba.DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
863
&v->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
864
&v->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
865
&v->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
866
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
868
v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
869
8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
872
dml_print("DML::%s: k=%0d DPPPerSurface=%d\n", __func__, k, mode_lib->vba.DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
873
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
874
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
875
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
876
v->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
877
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
878
v->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
880
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
881
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, mode_lib->vba.VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
883
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
884
dml_print("DML::%s: k=%0d ReadBandwidthSurfaceLuma=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
885
v->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
886
dml_print("DML::%s: k=%0d ReadBandwidthSurfaceChroma=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
887
v->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
888
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
889
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
89
mode_lib->vba.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
890
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
891
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
892
v->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
893
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
894
v->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
895
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
896
dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
899
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
90
mode_lib->vba.PixelClock[k], mode_lib->vba.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
902
if (v->VRatioPrefetchY[k] > v->MaxVRatioPre
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
903
|| v->VRatioPrefetchC[k] > v->MaxVRatioPre)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
91
mode_lib->vba.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
92
mode_lib->vba.WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
93
mode_lib->vba.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
94
mode_lib->vba.WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
95
mode_lib->vba.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
958
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
959
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
96
mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
995
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
996
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1002
if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1003
DETBufferSizeInKByte[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1004
} else if (DETSizeOverride[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1005
DETBufferSizeInKByte[k] = DETSizeOverride[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1007
(ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1008
} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1009
DETBufferSizeInKByte[k] = minDET_pipe;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1011
(ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1015
dml_print("DML::%s: k=%d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1016
dml_print("DML::%s: k=%d DETSizeOverride = %d\n", __func__, k, DETSizeOverride[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1017
dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1023
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1024
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1025
TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1029
for (uint k = 0; k < NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1030
dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1035
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1037
if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1038
DETPieceAssignedToThisSurfaceAlready[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1039
} else if (DETSizeOverride[k] > 0 || (((double) (ForceSingleDPP ? 1 : DPPPerSurface[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1040
(double) DETBufferSizeInKByte[k] / (double) MaxTotalDETInKByte) >=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1041
((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1042
DETPieceAssignedToThisSurfaceAlready[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1044
ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1046
DETPieceAssignedToThisSurfaceAlready[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1049
dml_print("DML::%s: k=%d DETPieceAssignedToThisSurfaceAlready = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1050
DETPieceAssignedToThisSurfaceAlready[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1051
dml_print("DML::%s: k=%d BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1060
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1062
dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[k] = %f\n", __func__, j, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1063
ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1064
dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[k] = %f\n", __func__, j, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1065
ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1066
dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[Next] = %f\n", __func__, j, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1068
dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[Next] = %f\n", __func__, j, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1070
dml_print("DML::%s: j=%d k=%d, NextSurfaceToAssignDETPiece = %d\n", __func__, j, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1073
if (!DETPieceAssignedToThisSurfaceAlready[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1075
ReadBandwidthLuma[k] + ReadBandwidthChroma[k] <
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1078
NextSurfaceToAssignDETPiece = k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1083
__func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1085
__func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1122
if (NextDETBufferPieceInKByte > nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1124
nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1125
NextDETBufferPieceInKByte = nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1174
for (uint k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1176
__func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1562
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1564
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1565
Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1566
*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1569
for (k = 0; k < NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1570
Dppclk[k] = *GlobalDPPCLK / 255 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1805
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1810
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1811
if (ViewportStationary[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1812
SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1813
dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1814
ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1815
ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1816
ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1817
ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1818
dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1820
if (ReadBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1821
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1822
dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1823
dml_floor(ViewportXStartC[k] + ViewportWidthC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1824
ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1825
dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1826
dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1827
dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1828
ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1829
dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1830
BytesPerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1832
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1833
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1834
(dml_min(dml_ceil(DCCMetaPitchY[k], 8 * Read256BytesBlockWidthY[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1835
dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1836
Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1837
- dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1838
* dml_min(dml_ceil(SurfaceHeightY[k], 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1839
Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1840
ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1841
Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1842
Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256) + (64 * 1024);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1843
if (Read256BytesBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1844
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1845
dml_min(dml_ceil(DCCMetaPitchC[k], 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1846
Read256BytesBlockWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1847
dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1848
* Read256BytesBlockWidthC[k] - 1, 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1849
Read256BytesBlockWidthC[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1850
dml_floor(ViewportXStartC[k], 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1851
Read256BytesBlockWidthC[k])) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1852
dml_min(dml_ceil(SurfaceHeightC[k], 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1853
Read256BytesBlockHeightC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1854
dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1855
8 * Read256BytesBlockHeightC[k] - 1, 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1856
Read256BytesBlockHeightC[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1857
dml_floor(ViewportYStartC[k], 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1858
Read256BytesBlockHeightC[k])) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1859
BytesPerPixelC[k] / 256;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1863
SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1864
ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1865
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1866
ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1867
BytesPerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1868
if (ReadBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1869
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1870
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1871
ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1872
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1873
ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1874
BytesPerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1876
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1877
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1878
(dml_ceil(dml_min(DCCMetaPitchY[k], ViewportWidthY[k] + 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1879
Read256BytesBlockWidthY[k] - 1), 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1880
Read256BytesBlockWidthY[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1881
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1882
Read256BytesBlockHeightY[k] - 1), 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1883
Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1885
if (Read256BytesBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1886
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1887
dml_ceil(dml_min(DCCMetaPitchC[k], ViewportWidthC[k] + 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1888
Read256BytesBlockWidthC[k] - 1), 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1889
Read256BytesBlockWidthC[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1890
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1891
Read256BytesBlockHeightC[k] - 1), 8 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1892
Read256BytesBlockHeightC[k]) *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1893
BytesPerPixelC[k] / 256;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1899
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1901
if (UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1902
TotalSurfaceSizeInMALLForSubVP = TotalSurfaceSizeInMALLForSubVP + SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1903
else if (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1904
TotalSurfaceSizeInMALLForSS = TotalSurfaceSizeInMALLForSS + SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1975
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1992
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1994
vm_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1995
dpte_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1997
vm_group_bytes[k] = 2048;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1998
if (GPUVMMinPageSizeKBytes[k] >= 64 && IsVertical(myPipe[k].SourceRotation))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1999
dpte_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2001
dpte_group_bytes[k] = 2048;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2003
vm_group_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2004
dpte_group_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2007
if (myPipe[k].SourcePixelFormat == dm_420_8 || myPipe[k].SourcePixelFormat == dm_420_10 ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2008
myPipe[k].SourcePixelFormat == dm_420_12 ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2009
myPipe[k].SourcePixelFormat == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2010
if ((myPipe[k].SourcePixelFormat == dm_420_10 || myPipe[k].SourcePixelFormat == dm_420_12) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2011
!IsVertical(myPipe[k].SourceRotation)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2012
PTEBufferSizeInRequestsForLuma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2014
PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsForLuma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2016
PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2017
PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2021
myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2022
myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2023
myPipe[k].DPPPerSurface,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2024
myPipe[k].BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2025
myPipe[k].BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2026
myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2027
myPipe[k].SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2028
myPipe[k].BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2029
myPipe[k].SourceRotation,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2030
SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2031
myPipe[k].ViewportHeightChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2032
myPipe[k].ViewportXStartC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2033
myPipe[k].ViewportYStartC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2038
GPUVMMinPageSizeKBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2040
PTEBufferSizeInRequestsForChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2041
myPipe[k].PitchC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2042
myPipe[k].DCCMetaPitchC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2043
myPipe[k].BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2044
myPipe[k].BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2047
&MetaRowByteC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2048
&PixelPTEBytesPerRowC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2049
&dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2050
&dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2051
&dpte_row_height_linear_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2052
&PixelPTEBytesPerRowC_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2053
&dpte_row_width_chroma_ub_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2054
&dpte_row_height_chroma_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2055
&meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2056
&meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2057
&meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2058
&meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2059
&PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2060
&PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2061
&PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2062
&dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2063
&meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2065
PrefetchSourceLinesC[k] = dml32_CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2066
myPipe[k].VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2067
myPipe[k].VTapsChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2068
myPipe[k].InterlaceEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2069
myPipe[k].ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2070
myPipe[k].SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2071
myPipe[k].SourceRotation,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2072
myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2073
SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2074
myPipe[k].ViewportHeightChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2075
myPipe[k].ViewportXStartC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2076
myPipe[k].ViewportYStartC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2079
&VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2080
&MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2082
PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2083
PTEBufferSizeInRequestsForChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2084
PixelPTEBytesPerRowC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2086
MetaRowByteC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2087
MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2088
PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2089
dpte_row_height_chroma_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2090
dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2091
PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2095
myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2096
myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2097
myPipe[k].DPPPerSurface,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2098
myPipe[k].BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2099
myPipe[k].BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2100
myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2101
myPipe[k].SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2102
myPipe[k].BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2103
myPipe[k].SourceRotation,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2104
SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2105
myPipe[k].ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2106
myPipe[k].ViewportXStart,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2107
myPipe[k].ViewportYStart,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2112
GPUVMMinPageSizeKBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2114
PTEBufferSizeInRequestsForLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2115
myPipe[k].PitchY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2116
myPipe[k].DCCMetaPitchY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2117
myPipe[k].BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2118
myPipe[k].BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2121
&MetaRowByteY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2122
&PixelPTEBytesPerRowY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2123
&dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2124
&dpte_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2125
&dpte_row_height_linear_luma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2126
&PixelPTEBytesPerRowY_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2127
&dpte_row_width_luma_ub_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2128
&dpte_row_height_luma_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2129
&meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2130
&meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2131
&meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2132
&meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2133
&PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2134
&PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2135
&PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2136
&dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2137
&meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2139
PrefetchSourceLinesY[k] = dml32_CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2140
myPipe[k].VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2141
myPipe[k].VTaps,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2142
myPipe[k].InterlaceEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2143
myPipe[k].ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2144
myPipe[k].SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2145
myPipe[k].SourceRotation,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2146
myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2147
SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2148
myPipe[k].ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2149
myPipe[k].ViewportXStart,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2150
myPipe[k].ViewportYStart,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2153
&VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2154
&MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2156
PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2157
MetaRowByte[k] = MetaRowByteY[k] + MetaRowByteC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2159
if (PixelPTEBytesPerRowY[k] <= 64 * PTEBufferSizeInRequestsForLuma[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2160
PixelPTEBytesPerRowC[k] <= 64 * PTEBufferSizeInRequestsForChroma[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2161
PTEBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2163
PTEBufferSizeNotExceeded[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2166
one_row_per_frame_fits_in_buffer[k] = (PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2167
PTEBufferSizeInRequestsForLuma[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2168
PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * PTEBufferSizeInRequestsForChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2180
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2181
PTE_BUFFER_MODE[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2182
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2183
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2184
(GPUVMMinPageSizeKBytes[k] > 64);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2185
BIGK_FRAGMENT_SIZE[k] = dml_log2(GPUVMMinPageSizeKBytes[k] * 1024) - 12;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2188
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2190
dml_print("DML::%s: k=%d, SurfaceSizeInMALL = %d\n", __func__, k, SurfaceSizeInMALL[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2191
dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n", __func__, k, UsesMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2193
use_one_row_for_frame[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2194
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2195
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2196
(GPUVMMinPageSizeKBytes[k] > 64 && IsVertical(myPipe[k].SourceRotation));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2198
use_one_row_for_frame_flip[k] = use_one_row_for_frame[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2199
!(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2201
if (use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2202
dpte_row_height_luma[k] = dpte_row_height_luma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2203
dpte_row_width_luma_ub[k] = dpte_row_width_luma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2204
PixelPTEBytesPerRowY[k] = PixelPTEBytesPerRowY_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2205
dpte_row_height_chroma[k] = dpte_row_height_chroma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2206
dpte_row_width_chroma_ub[k] = dpte_row_width_chroma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2207
PixelPTEBytesPerRowC[k] = PixelPTEBytesPerRowC_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2208
PTEBufferSizeNotExceeded[k] = one_row_per_frame_fits_in_buffer[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2211
if (MetaRowByte[k] <= DCCMetaBufferSizeBytes)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2212
DCCMetaBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2214
DCCMetaBufferSizeNotExceeded[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2216
PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY[k] + PixelPTEBytesPerRowC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2217
if (use_one_row_for_frame[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2218
PixelPTEBytesPerRow[k] = PixelPTEBytesPerRow[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2222
myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2223
myPipe[k].VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2224
myPipe[k].VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2225
myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2226
myPipe[k].HTotal / myPipe[k].PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2227
MetaRowByteY[k], MetaRowByteC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2228
meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2229
meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2230
PixelPTEBytesPerRowY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2231
PixelPTEBytesPerRowC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2232
dpte_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2233
dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2236
&meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2237
&dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2239
dml_print("DML::%s: k=%d, use_one_row_for_frame = %d\n", __func__, k, use_one_row_for_frame[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2241
__func__, k, use_one_row_for_frame_flip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2243
__func__, k, UseMALLForPStateChange[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2244
dml_print("DML::%s: k=%d, dpte_row_height_luma = %d\n", __func__, k, dpte_row_height_luma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2246
__func__, k, dpte_row_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2247
dml_print("DML::%s: k=%d, PixelPTEBytesPerRowY = %d\n", __func__, k, PixelPTEBytesPerRowY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2249
__func__, k, dpte_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2251
__func__, k, dpte_row_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2252
dml_print("DML::%s: k=%d, PixelPTEBytesPerRowC = %d\n", __func__, k, PixelPTEBytesPerRowC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2253
dml_print("DML::%s: k=%d, PixelPTEBytesPerRow = %d\n", __func__, k, PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2255
__func__, k, PTEBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2256
dml_print("DML::%s: k=%d, PTE_BUFFER_MODE = %d\n", __func__, k, PTE_BUFFER_MODE[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2257
dml_print("DML::%s: k=%d, BIGK_FRAGMENT_SIZE = %d\n", __func__, k, BIGK_FRAGMENT_SIZE[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2618
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2624
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2625
UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2626
if (UsesMALLForStaticScreen[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2627
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2629
dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n", __func__, k, UsesMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2630
dml_print("DML::%s: k=%d, TotalSurfaceSizeInMALL = %d\n", __func__, k, TotalSurfaceSizeInMALL);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2638
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2639
if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2640
!UsesMALLForStaticScreen[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2641
UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2642
one_row_per_frame_fits_in_buffer[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2644
SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2646
SurfaceToAddToMALL = k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2649
__func__, k, UseMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2831
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2837
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2839
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2840
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2841
/ PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2843
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2845
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2848
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2849
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2850
DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2852
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2853
/ Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2857
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2858
DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2859
BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2860
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2863
DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2866
DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2869
dml_print("DML::%s: k=%d, PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2870
dml_print("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2874
for (k = 0; k < NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2875
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2886
for (k = 0; k < NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2887
*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2980
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3003
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3005
+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3006
/ (15.75 * HTotal[k] / PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3009
for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3010
NoOfDPPState[k] = NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3022
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3026
PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3027
* swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3028
+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3029
* BytePerPixelC[k]) / NormalEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3031
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3032
+ PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3035
+ 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3037
+ 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3038
+ PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3039
PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3040
* HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3041
DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3042
DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3047
UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3049
DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3055
PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3060
DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3065
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3066
PixelDCFCLKCyclesRequiredInPrefetch[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3068
DCFCLKRequiredForPeakBandwidthPerSurface[k] = NoOfDPPState[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3069
PixelDCFCLKCyclesRequiredInPrefetch[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3070
PrefetchPixelLinesTime[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3074
DCFCLKRequiredForPeakBandwidthPerSurface[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3075
DCFCLKRequiredForPeakBandwidthPerSurface[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3076
NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3080
DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3082
if (DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3091
RequiredDPPCLKPerSurface[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3094
PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3095
HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3096
VTotal[k] - VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3097
DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3098
DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3099
Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3110
AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3111
PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3112
TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3114
DCFCLKRequiredForPeakBandwidthPerSurface[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3115
dml_max(DCFCLKRequiredForPeakBandwidthPerSurface[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3118
DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3122
for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3124
DCFCLKRequiredForPeakBandwidthPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3129
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3132
MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3133
PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3134
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3140
PrefetchPixelLinesTime[k] / 4),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3142
PixelDCFCLKCyclesRequiredInPrefetch[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3166
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3185
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3186
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3401
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3507
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3508
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3531
if (v->DynamicMetadataEnable[k] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3535
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3555
*Tdmdl_vm = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3591
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4290
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4354
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4355
if (v->WritebackEnable[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4398
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4399
TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4400
SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) / (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4403
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4405
LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4406
LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4410
dml_print("DML::%s: k=%d, v->MaxLineBufferLines = %d\n", __func__, k, v->MaxLineBufferLines);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4411
dml_print("DML::%s: k=%d, v->LineBufferSizeFinal = %d\n", __func__, k, v->LineBufferSizeFinal);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4412
dml_print("DML::%s: k=%d, v->LBBitPerPixel = %d\n", __func__, k, v->LBBitPerPixel[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4413
dml_print("DML::%s: k=%d, v->HRatio = %f\n", __func__, k, v->HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4414
dml_print("DML::%s: k=%d, v->vtaps = %d\n", __func__, k, v->vtaps[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4417
EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4418
EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4419
EffectiveDETBufferSizeY = DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4424
* (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4425
/ (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4428
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4429
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4430
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4433
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4437
- (1.0 - 1.0 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4438
/ v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4441
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4442
LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4443
LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4444
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4445
/ v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4447
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4448
/ v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4451
- (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightC[k] * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4452
/ v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4460
ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4462
ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4464
USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.USRRetrainingWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4466
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4468
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4469
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4470
if (v->WritebackPixelFormat[k] == dm_444_64)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4479
ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4481
ActiveFCLKChangeLatencyMargin[k] = dml_min(ActiveFCLKChangeLatencyMargin[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4484
MaxActiveDRAMClockChangeLatencySupported[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4485
(v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4487
(ActiveDRAMClockChangeLatencyMargin[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4508
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4509
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4511
ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4513
MinActiveFCLKChangeMargin = ActiveFCLKChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4514
SurfaceWithMinActiveFCLKChangeMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4521
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4522
if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4523
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4525
ActiveFCLKChangeLatencyMargin[k] <
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4527
SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = ActiveFCLKChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4543
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4544
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4545
(USRRetrainingLatencyMargin[k] < 0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4550
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4551
if (v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4552
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4553
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4554
ActiveDRAMClockChangeLatencyMargin[k] < 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4559
LastSurfaceWithoutMargin = k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4561
!SynchronizedSurfaces[LastSurfaceWithoutMargin][k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4567
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4568
if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4570
else if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4597
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4603
dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4604
src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4605
src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4606
sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4609
dml_print("DML::%s: k=%d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4610
dml_print("DML::%s: k=%d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4611
dml_print("DML::%s: k=%d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4612
dml_print("DML::%s: k=%d, SwathHeightY = %d\n", __func__, k, SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4613
dml_print("DML::%s: k=%d, LBLatencyHidingSourceLinesY = %d\n", __func__, k, LBLatencyHidingSourceLinesY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4614
dml_print("DML::%s: k=%d, dst_y_pstate = %d\n", __func__, k, dst_y_pstate);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4615
dml_print("DML::%s: k=%d, src_y_pstate_l = %d\n", __func__, k, src_y_pstate_l);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4616
dml_print("DML::%s: k=%d, src_y_ahead_l = %d\n", __func__, k, src_y_ahead_l);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4617
dml_print("DML::%s: k=%d, v->meta_row_height = %d\n", __func__, k, v->meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4618
dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4620
SubViewportLinesNeededInMALL[k] = sub_vp_lines_l;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4622
if (BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4623
src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4624
src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4625
sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4626
SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4629
dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4630
dml_print("DML::%s: k=%d, src_y_ahead_c = %d\n", __func__, k, src_y_ahead_c);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4631
dml_print("DML::%s: k=%d, v->meta_row_height_chroma = %d\n", __func__, k, v->meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4632
dml_print("DML::%s: k=%d, sub_vp_lines_c = %d\n", __func__, k, sub_vp_lines_c);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
468
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4728
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4730
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4733
dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4734
dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4735
dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4736
dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4737
dml_print("DML::%s: k=%d : swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4738
dml_print("DML::%s: k=%d : swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4739
dml_print("DML::%s: k=%d : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4740
dml_print("DML::%s: k=%d : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4741
dml_print("DML::%s: k=%d : DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4742
dml_print("DML::%s: k=%d : PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4743
dml_print("DML::%s: k=%d : Dppclk = %f\n", __func__, k, Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4746
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4747
DisplayPipeLineDeliveryTimeLuma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4748
swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4750
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4753
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4754
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4756
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4757
DisplayPipeLineDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4758
swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4760
DisplayPipeLineDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4761
swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4765
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4766
DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4767
swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4769
DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4770
swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4773
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4774
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4776
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4777
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4778
DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4780
DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4781
swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4786
__func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4788
__func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4790
__func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4792
__func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4796
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4797
if (!IsVertical(SourceRotation[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4798
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4800
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4802
dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4805
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4806
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4807
DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4808
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4809
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4810
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4812
if (!IsVertical(SourceRotation[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4813
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4815
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4817
dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4819
DisplayPipeRequestDeliveryTimeChroma[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4820
DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4821
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4822
DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4826
__func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4828
__func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4830
__func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4832
__func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4836
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4839
cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4841
if (NumberOfCursors[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4842
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4843
CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4844
HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4846
CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4847
PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4849
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4850
CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4851
HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4853
CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4854
PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4857
CursorRequestDeliveryTime[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4858
CursorRequestDeliveryTimePrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4862
__func__, k, NumberOfCursors[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4864
__func__, k, CursorRequestDeliveryTime[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4866
__func__, k, CursorRequestDeliveryTimePrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4941
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4943
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4944
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4945
if (BytePerPixelC[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4946
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4948
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4949
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4950
if (BytePerPixelC[k] == 0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4951
DST_Y_PER_META_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4953
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4956
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4957
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4958
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4959
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4960
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4961
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4962
if (!IsVertical(SourceRotation[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4963
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4965
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4972
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4973
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4974
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4975
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4976
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4977
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4978
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4979
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4980
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4981
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4983
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4984
meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4985
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4986
meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4987
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4989
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4990
if (!IsVertical(SourceRotation[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4992
meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4995
meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5002
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5003
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5004
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5005
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5006
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5007
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5010
TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5011
TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5012
TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5013
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5014
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5015
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5019
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5021
if (!IsVertical(SourceRotation[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5022
dpte_group_width_luma = (double) dpte_group_bytes[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5023
(double) PTERequestSizeY[k] * PixelPTEReqWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5025
dpte_group_width_luma = (double) dpte_group_bytes[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5026
(double) PTERequestSizeY[k] * PixelPTEReqHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5029
if (use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5030
dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5033
dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5038
__func__, k, use_one_row_for_frame[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5040
__func__, k, dpte_group_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5042
__func__, k, PTERequestSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5044
__func__, k, PixelPTEReqWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5046
__func__, k, PixelPTEReqHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5048
__func__, k, dpte_row_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5050
__func__, k, dpte_group_width_luma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5052
__func__, k, dpte_groups_per_row_luma_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5055
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5056
HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5057
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5058
HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5059
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5060
HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5061
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5062
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5063
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5064
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5066
if (!IsVertical(SourceRotation[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5067
dpte_group_width_chroma = (double) dpte_group_bytes[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5068
(double) PTERequestSizeC[k] * PixelPTEReqWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5070
dpte_group_width_chroma = (double) dpte_group_bytes[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5071
(double) PTERequestSizeC[k] * PixelPTEReqHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5074
if (use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5075
dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5078
dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5083
__func__, k, dpte_row_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5085
__func__, k, dpte_group_width_chroma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5087
__func__, k, dpte_groups_per_row_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5089
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5090
HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5091
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5092
HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5093
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5094
HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5097
time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5098
time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5099
time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5100
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5101
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5102
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5106
__func__, k, DestinationLinesToRequestRowInVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5108
__func__, k, DestinationLinesToRequestRowInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5110
__func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5112
__func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5114
__func__, k, DST_Y_PER_META_ROW_NOM_L[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5116
__func__, k, DST_Y_PER_META_ROW_NOM_C[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5118
__func__, k, TimePerMetaChunkNominal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5120
__func__, k, TimePerMetaChunkVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5122
__func__, k, TimePerMetaChunkFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5124
__func__, k, TimePerChromaMetaChunkNominal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5126
__func__, k, TimePerChromaMetaChunkVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5128
__func__, k, TimePerChromaMetaChunkFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5130
__func__, k, time_per_pte_group_nom_luma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5132
__func__, k, time_per_pte_group_vblank_luma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5134
__func__, k, time_per_pte_group_flip_luma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5136
__func__, k, time_per_pte_group_nom_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5138
__func__, k, time_per_pte_group_vblank_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5140
__func__, k, time_per_pte_group_flip_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
515
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
516
RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5169
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
517
RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5177
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5180
dml_print("DML::%s: k=%0d, DCCEnable = %d\n", __func__, k, DCCEnable[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5181
dml_print("DML::%s: k=%0d, vm_group_bytes = %d\n", __func__, k, vm_group_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5183
__func__, k, dpde0_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5185
__func__, k, dpde0_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5187
__func__, k, meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5189
__func__, k, meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
519
dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5192
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5193
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5194
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5196
(double) (dpde0_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5197
(double) (vm_group_bytes[k]), 1.0) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5198
dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5199
(double) (vm_group_bytes[k]), 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
520
dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5202
(double) (dpde0_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5203
(double) (vm_group_bytes[k]), 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5207
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5209
(double) (meta_pte_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
521
dml_print("DML::%s: k=%0d BytePerPixDETY = %f\n", __func__, k, BytePerPixDETY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5210
(double) (vm_group_bytes[k]), 1.0) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5211
dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5212
(double) (vm_group_bytes[k]), 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5215
(double) (meta_pte_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5216
(double) (vm_group_bytes[k]), 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5219
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
522
dml_print("DML::%s: k=%0d MaximumSwathHeightY = %d\n", __func__, k, MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5221
(double) (dpde0_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5222
(double) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5223
dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5224
(double) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5225
dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5226
(double) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5227
dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5228
(double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
523
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5231
(double) (dpde0_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5232
(double) (vm_group_bytes[k]), 1) + dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5233
(double) (meta_pte_bytes_per_frame_ub_l[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5234
(double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5239
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
524
RoundedUpMaxSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5240
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5241
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5242
dpde0_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5244
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5248
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5249
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
525
dml_print("DML::%s: k=%0d swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5250
meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5252
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5255
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5256
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5257
64 + dpde0_bytes_per_frame_ub_c[k] / 64 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5258
meta_pte_bytes_per_frame_ub_l[k] / 64 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5259
meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
526
dml_print("DML::%s: k=%0d BytePerPixDETC = %f\n", __func__, k, BytePerPixDETC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5261
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5262
64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5267
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5268
HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5269
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
527
dml_print("DML::%s: k=%0d MaximumSwathHeightC = %d\n", __func__, k, MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5270
HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5271
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5272
HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5273
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5274
HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5277
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5278
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5279
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
528
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5280
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5284
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5285
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5286
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5287
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
529
RoundedUpMaxSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5291
dml_print("DML::%s: k=%0d, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5292
dml_print("DML::%s: k=%0d, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5293
dml_print("DML::%s: k=%0d, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5294
dml_print("DML::%s: k=%0d, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
532
if (SourcePixelFormat[k] == dm_420_10) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
533
RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
534
RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
538
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
539
TotalActiveDPP = TotalActiveDPP + (ForceSingleDPP ? 1 : DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
540
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
541
SourcePixelFormat[k] == dm_420_12 || SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5689
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5696
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5697
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5698
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5699
if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesY[k] > SwathHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5700
|| (!IsVertical(SourceRotation[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5701
&& BlockHeight256BytesY[k] > SwathHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5702
|| DCCYMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5708
+ ReadBandwidthSurfaceLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5709
/ dml_min(NetDCCRateLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5713
__func__, k, ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5715
__func__, k, NetDCCRateLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5717
__func__, k, MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5720
+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5722
+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5725
if (ReadBandwidthSurfaceChroma[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5726
if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesC[k] > SwathHeightC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5727
|| (!IsVertical(SourceRotation[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5728
&& BlockHeight256BytesC[k] > SwathHeightC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5729
|| DCCCMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5736
+ ReadBandwidthSurfaceChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5737
/ dml_min(NetDCCRateChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5741
__func__, k, ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5743
__func__, k, NetDCCRateChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5745
__func__, k, MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5748
+ ReadBandwidthSurfaceChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5749
* DCCFractionOfZeroSizeRequestsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5751
+ ReadBandwidthSurfaceChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5752
* DCCFractionOfZeroSizeRequestsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5757
+ ReadBandwidthSurfaceLuma[k] + ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5760
+ DPPPerSurface[k] * (meta_row_bw[k] + dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5835
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5836
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5837
LinesInDETY = ((double) DETBufferSizeY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5839
* ReadBandwidthSurfaceLuma[k] / TotalDataReadBandwidth)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5840
/ BytePerPixelDETY[k] / SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5841
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5842
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((double) HTotal[k] / PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5843
/ VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5845
dml_print("DML::%s: k=%0d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5846
dml_print("DML::%s: k=%0d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5847
dml_print("DML::%s: k=%0d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5849
__func__, k, ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5850
dml_print("DML::%s: k=%0d, TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5851
dml_print("DML::%s: k=%0d, LinesInDETY = %f\n", __func__, k, LinesInDETY);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5853
__func__, k, LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5854
dml_print("DML::%s: k=%0d, HTotal = %d\n", __func__, k, HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5855
dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5856
dml_print("DML::%s: k=%0d, VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5857
dml_print("DML::%s: k=%0d, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5858
dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5862
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5868
dml_floor((double) VTotal[k] / 2.0, 1.0) : VTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5869
* (double) HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5872
dml_floor((double) VActive[k] / 2.0, 1.0) : VActive[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5873
* (double) HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5874
BytePerPixelYCriticalSurface = BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5875
SwathWidthYCriticalSurface = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5876
SwathHeightYCriticalSurface = SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5877
BlockWidth256BytesYCriticalSurface = BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5878
LinesToFinishSwathTransferStutterCriticalSurface = SwathHeightY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5880
DETBufferSizeYCriticalSurface = DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5881
MinTTUVBlankCriticalSurface = MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5882
doublePlaneCriticalSurface = (ReadBandwidthSurfaceChroma[k] == 0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5883
doublePipeCriticalSurface = (DPPPerSurface[k] == 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5887
__func__, k, FoundCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5889
__func__, k, *StutterPeriod);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5891
__func__, k, MinTTUVBlankCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5893
__func__, k, FrameTimeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5895
__func__, k, VActiveTimeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5897
__func__, k, BytePerPixelYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5899
__func__, k, SwathWidthYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5901
__func__, k, SwathHeightYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5903
__func__, k, BlockWidth256BytesYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5905
__func__, k, doublePlaneCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5907
__func__, k, doublePipeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5909
__func__, k, LinesToFinishSwathTransferStutterCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5958
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5959
if (WritebackEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
596
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
598
DETBufferSizeInKByteForSwathCalculation = (UseMALLForPStateChange[k] ==
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
599
dm_use_mall_pstate_change_phantom_pipe ? 1024 : DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5996
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5997
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5998
if (BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6000
doublePixelClock = PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6001
doubleHTotal = HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6002
doubleVTotal = VTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6003
} else if (doublePixelClock != PixelClock[k] || doubleHTotal != HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6004
|| doubleVTotal != VTotal[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
601
dml_print("DML::%s: k=%0d DETBufferSizeInKByteForSwathCalculation = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
605
if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
607
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
608
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
609
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
610
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
611
} else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
612
RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6122
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6127
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6128
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6133
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6134
VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
614
SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
615
SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
616
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
617
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6176
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
618
} else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6182
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6183
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6189
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
619
RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <=
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6190
ActiveBandwidthPerSurface = ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6194
TotalPrefetchBandwidth = TotalPrefetchBandwidth + PrefetchBW[k] * VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6196
*MaxPrefetchBandwidth = *MaxPrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6198
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
621
SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
622
SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6225
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6228
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6229
CalculateBandwidthAvailableForImmediateFlip_val = CalculateBandwidthAvailableForImmediateFlip_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
623
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6230
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
624
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
626
SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6262
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6264
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6265
if (ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6266
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6267
NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6268
NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
627
SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6270
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6271
NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6272
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
628
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
629
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6298
int k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6312
for (k = 0; k < NumberOfActiveSurfaces; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6313
SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6315
if (SwathHeightC[k] != 0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6316
SwathSizePerSurfaceC[k] = SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6318
SwathSizePerSurfaceC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
632
if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 >
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6320
SwathSizeAllSurfaces += SwathSizePerSurfaceY[k] + SwathSizePerSurfaceC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6326
for (k = 0; k < NumberOfActiveSurfaces; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6327
double LineTime = HTotal[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6330
if (UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6331
DETSwathLatencyHidingYUs = (dml_floor(DETBufferSizeY[k] / BytePerPixelInDETY[k] / SwathWidthY[k], 1.0) - SwathHeightY[k]) / VRatioY[k] * LineTime;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6333
if (SwathHeightC[k] != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6334
DETSwathLatencyHidingCUs = (dml_floor(DETBufferSizeC[k] / BytePerPixelInDETC[k] / SwathWidthC[k], 1.0) - SwathHeightC[k]) / VRatioC[k] * LineTime;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
634
|| SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
635
SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
637
ViewportSizeSupportPerSurface[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
639
ViewportSizeSupportPerSurface[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
642
if (SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
644
dml_print("DML::%s: k=%0d All DET for plane0\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
646
DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
647
DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
650
dml_print("DML::%s: k=%0d Half DET for plane0, half for plane1\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
652
DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
653
DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
656
dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
658
DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
659
DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
663
dml_print("DML::%s: k=%0d SwathHeightY = %d\n", __func__, k, SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
664
dml_print("DML::%s: k=%0d SwathHeightC = %d\n", __func__, k, SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
666
k, RoundedUpMaxSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
668
k, RoundedUpMaxSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
669
dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesY = %d\n", __func__, k, RoundedUpSwathSizeBytesY);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
670
dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesC = %d\n", __func__, k, RoundedUpSwathSizeBytesC);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
671
dml_print("DML::%s: k=%0d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
672
dml_print("DML::%s: k=%0d DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
673
dml_print("DML::%s: k=%0d DETBufferSizeC = %d\n", __func__, k, DETBufferSizeC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
674
dml_print("DML::%s: k=%0d ViewportSizeSupportPerSurface = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
675
ViewportSizeSupportPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
719
unsigned int k, j;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
732
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
733
if (!IsVertical(SourceRotation[k]))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
734
SwathWidthdoubleDPPY[k] = ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
736
SwathWidthdoubleDPPY[k] = ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
739
dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
740
dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
743
MainSurfaceODMMode = ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
745
if (BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
750
SwathWidthY[k] = SwathWidthdoubleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
753
SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
754
dml_round(HActive[k] / 4.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
756
SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
757
dml_round(HActive[k] / 2.0 * HRatio[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
758
} else if (DPPPerSurface[k] == 2) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
759
SwathWidthY[k] = SwathWidthdoubleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
761
SwathWidthY[k] = SwathWidthdoubleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
766
dml_print("DML::%s: k=%d HActive=%d\n", __func__, k, HActive[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
767
dml_print("DML::%s: k=%d HRatio=%f\n", __func__, k, HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
768
dml_print("DML::%s: k=%d MainSurfaceODMMode=%d\n", __func__, k, MainSurfaceODMMode);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
769
dml_print("DML::%s: k=%d SwathWidthdoubleDPPY=%d\n", __func__, k, SwathWidthdoubleDPPY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
770
dml_print("DML::%s: k=%d SwathWidthY=%d\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
773
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
774
SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
775
SwathWidthC[k] = SwathWidthY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
776
SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
778
SwathWidthC[k] = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
779
SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
783
SwathWidthY[k] = SwathWidthdoubleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
784
SwathWidthC[k] = SwathWidthdoubleDPPC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
787
surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
788
surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
790
if (!IsVertical(SourceRotation[k])) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
791
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
792
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
793
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
794
swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
795
dml_floor(ViewportXStart[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
796
SwathWidthY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
797
Read256BytesBlockWidthY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
798
Read256BytesBlockWidthY[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
799
dml_floor(ViewportXStart[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
800
Read256BytesBlockWidthY[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
802
swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
803
dml_ceil(SwathWidthY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
804
Read256BytesBlockWidthY[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
805
Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
807
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
808
surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
809
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
810
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
811
dml_floor(ViewportXStartC[k] + SwathWidthC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
812
Read256BytesBlockWidthC[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
813
Read256BytesBlockWidthC[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
814
dml_floor(ViewportXStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
815
Read256BytesBlockWidthC[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
817
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
818
dml_ceil(SwathWidthC[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
819
Read256BytesBlockWidthC[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
820
Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
823
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
826
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
827
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
829
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
830
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
831
SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
832
Read256BytesBlockHeightY[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
833
dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
835
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
836
Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
838
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
839
surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
840
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
841
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
842
dml_floor(ViewportYStartC[k] + SwathWidthC[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
843
Read256BytesBlockHeightC[k] - 1,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
844
Read256BytesBlockHeightC[k]) -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
845
dml_floor(ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
846
Read256BytesBlockHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
848
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
849
dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
850
Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
853
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
858
dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
859
dml_print("DML::%s: k=%d surface_height_ub_l=%0d\n", __func__, k, surface_height_ub_l);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
860
dml_print("DML::%s: k=%d surface_width_ub_c=%0d\n", __func__, k, surface_width_ub_c);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
861
dml_print("DML::%s: k=%d surface_height_ub_c=%0d\n", __func__, k, surface_height_ub_c);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
862
dml_print("DML::%s: k=%d Read256BytesBlockWidthY=%0d\n", __func__, k, Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
863
dml_print("DML::%s: k=%d Read256BytesBlockHeightY=%0d\n", __func__, k, Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
864
dml_print("DML::%s: k=%d Read256BytesBlockWidthC=%0d\n", __func__, k, Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
865
dml_print("DML::%s: k=%d Read256BytesBlockHeightC=%0d\n", __func__, k, Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
866
dml_print("DML::%s: k=%d ViewportStationary=%0d\n", __func__, k, ViewportStationary[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
867
dml_print("DML::%s: k=%d DPPPerSurface=%0d\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
868
dml_print("DML::%s: k=%d swath_width_luma_ub=%0d\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
869
dml_print("DML::%s: k=%d swath_width_chroma_ub=%0d\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
870
dml_print("DML::%s: k=%d MaximumSwathHeightY=%0d\n", __func__, k, MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
871
dml_print("DML::%s: k=%d MaximumSwathHeightC=%0d\n", __func__, k, MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
938
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
964
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
965
DETBufferSizeInKByte[k] = nomDETInKByte;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
966
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
967
SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
977
if (2.0 * ((double) RoundedUpMaxSwathSizeBytesY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
978
(double) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
984
dml_print("DML::%s: k=%0d minDET = %d\n", __func__, k, minDET);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
985
dml_print("DML::%s: k=%0d max_minDET = %d\n", __func__, k, max_minDET);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
986
dml_print("DML::%s: k=%0d minDET_pipe = %d\n", __func__, k, minDET_pipe);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
987
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
988
RoundedUpMaxSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
989
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
990
RoundedUpMaxSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
994
minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
995
(double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
998
__func__, k, minDET_pipe);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
723
unsigned int k,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
304
unsigned int i, j, k;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
306
for (k = 0; k < num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
307
visited[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
308
pipe_index_in_combine[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
280
for (int k = start_index; k < end_index; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
281
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
282
swap_table_entries(&table[k], &table[k+1]);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1050
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1053
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1054
mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1055
if (mode_lib->vba.Interlace[k] == 1
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1057
mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1079
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1101
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1102
pipe_idx = get_pipe_idx(mode_lib, k);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1107
total_pipes += mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1110
mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
1112
mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
221
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
224
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
225
immediate_flip_bw += mode_lib->vba.ImmediateFlipBW[k];
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
234
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
238
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
239
total_prefetch_bw += mode_lib->vba.PrefetchBandwidth[k];
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
248
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
251
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
252
size += mode_lib->vba.SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
521
unsigned int j, k;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
526
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k)
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
527
visited[k] = false;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
742
for (k = 0; k < DC__NUM_CURSOR__MAX; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
743
switch (k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
783
for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
784
display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
785
display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
787
if (src_k->is_hsplit && !visited[k]
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
789
mode_lib->vba.pipe_plane[k] =
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
809
visited[k] = true;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
843
for (k = j + 1; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
844
if (!PlaneVisited[k] && OTGInstPlane[j] == OTGInstPlane[k]) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
848
mode_lib->vba.BlendingAndTiming[k] = j;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
849
PlaneVisited[k] = true;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
865
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
866
if (pipes[k].pipe.src.unbounded_req_mode == 0)
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
872
for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
873
ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
881
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
882
mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable || !!pipes[k].pipe.src.gpuvm || !!pipes[k].pipe.src.vm;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
884
(pipes[k].pipe.src.gpuvm_levels_force_en
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
886
< pipes[k].pipe.src.gpuvm_levels_force) ?
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
887
pipes[k].pipe.src.gpuvm_levels_force :
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
890
mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable || !!pipes[k].pipe.src.hostvm || !!pipes[k].pipe.src.vm;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
892
(pipes[k].pipe.src.hostvm_levels_force_en
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
894
< pipes[k].pipe.src.hostvm_levels_force) ?
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
895
pipes[k].pipe.src.hostvm_levels_force :
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
908
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
909
mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
910
mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
912
if (mode_lib->vba.PteBufferMode[k] == 0 && mode_lib->vba.GPUVMEnable) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
913
if (mode_lib->vba.ForceOneRowForFrame[k] ||
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
914
(mode_lib->vba.GPUVMMinPageSizeKBytes[k] > 64*1024) ||
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
915
(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_disable) ||
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
916
(mode_lib->vba.UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable)) {
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
919
__func__, mode_lib->vba.PteBufferMode[k], k);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
921
__func__, mode_lib->vba.ForceOneRowForFrame[k]);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
923
__func__, mode_lib->vba.GPUVMMinPageSizeKBytes[k]);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
925
__func__, (int) mode_lib->vba.UsesMALLForPStateChange[k]);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
927
__func__, (int) mode_lib->vba.UseMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
949
int k = 0;
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
951
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
952
mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
10141
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
10142
clk_cfg.dppclk_option[k] = dml_use_required_freq;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2698
for (dml_uint_t k = 0; k < num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2699
display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2700
if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2701
display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2853
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2854
if (p->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2890
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2891
s->TotalPixelBW = s->TotalPixelBW + p->DPPPerSurface[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2892
* (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * p->VRatio[k] + p->SwathWidthC[k] * p->BytePerPixelDETC[k] * p->VRatioChroma[k]) / (p->HTotal[k] / p->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2895
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2897
s->LBLatencyHidingSourceLinesY[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthY[k] / dml_max(p->HRatio[k], 1.0)), 1)) - (p->VTaps[k] - 1));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2898
s->LBLatencyHidingSourceLinesC[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthC[k] / dml_max(p->HRatioChroma[k], 1.0)), 1)) - (p->VTapsChroma[k] - 1));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2902
dml_print("DML::%s: k=%u, MaxLineBufferLines = %u\n", __func__, k, p->MaxLineBufferLines);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2903
dml_print("DML::%s: k=%u, LineBufferSize = %u\n", __func__, k, p->LineBufferSize);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2904
dml_print("DML::%s: k=%u, LBBitPerPixel = %u\n", __func__, k, p->LBBitPerPixel[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2905
dml_print("DML::%s: k=%u, HRatio = %f\n", __func__, k, p->HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2906
dml_print("DML::%s: k=%u, VTaps = %u\n", __func__, k, p->VTaps[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2909
s->EffectiveLBLatencyHidingY = s->LBLatencyHidingSourceLinesY[k] / p->VRatio[k] * (p->HTotal[k] / p->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2910
s->EffectiveLBLatencyHidingC = s->LBLatencyHidingSourceLinesC[k] / p->VRatioChroma[k] * (p->HTotal[k] / p->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2912
s->EffectiveDETBufferSizeY = p->DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2914
s->EffectiveDETBufferSizeY = s->EffectiveDETBufferSizeY + p->CompressedBufferSizeInkByte * 1024 * (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * p->VRatio[k]) / (p->HTotal[k] / p->PixelClock[k]) / s->TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2917
s->LinesInDETY[k] = (dml_float_t)s->EffectiveDETBufferSizeY / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2918
s->LinesInDETYRoundedDownToSwath[k] = (dml_uint_t)(dml_floor(s->LinesInDETY[k], p->SwathHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2919
s->FullDETBufferingTimeY = s->LinesInDETYRoundedDownToSwath[k] * (p->HTotal[k] / p->PixelClock[k]) / p->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2921
s->ActiveClockChangeLatencyHidingY = s->EffectiveLBLatencyHidingY + s->FullDETBufferingTimeY - ((dml_float_t)p->DSTXAfterScaler[k] / (dml_float_t)p->HTotal[k] + (dml_float_t)p->DSTYAfterScaler[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2924
s->ActiveClockChangeLatencyHidingY = s->ActiveClockChangeLatencyHidingY - (1.0 - 1.0 / (dml_float_t)p->NumberOfActiveSurfaces) * (dml_float_t)p->SwathHeightY[k] * (dml_float_t)p->HTotal[k] / p->PixelClock[k] / p->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2927
if (p->BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2928
s->LinesInDETC[k] = p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2929
s->LinesInDETCRoundedDownToSwath[k] = (dml_uint_t)(dml_floor(s->LinesInDETC[k], p->SwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2930
s->FullDETBufferingTimeC = s->LinesInDETCRoundedDownToSwath[k] * (p->HTotal[k] / p->PixelClock[k]) / p->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2931
s->ActiveClockChangeLatencyHidingC = s->EffectiveLBLatencyHidingC + s->FullDETBufferingTimeC - ((dml_float_t)p->DSTXAfterScaler[k] / (dml_float_t)p->HTotal[k] + (dml_float_t)p->DSTYAfterScaler[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2933
s->ActiveClockChangeLatencyHidingC = s->ActiveClockChangeLatencyHidingC - (1.0 - 1.0 / (dml_float_t)p->NumberOfActiveSurfaces) * (dml_float_t)p->SwathHeightC[k] * (dml_float_t)p->HTotal[k] / p->PixelClock[k] / p->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2940
s->ActiveDRAMClockChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->UrgentWatermark - p->Watermark->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2941
s->ActiveFCLKChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->UrgentWatermark - p->Watermark->FCLKChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2942
s->USRRetrainingLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->USRRetrainingWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2944
if (p->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2945
s->WritebackLatencyHiding = (dml_float_t)p->WritebackInterfaceBufferSize * 1024.0 / ((dml_float_t)p->WritebackDestinationWidth[k] * (dml_float_t)p->WritebackDestinationHeight[k] / ((dml_float_t)p->WritebackSourceHeight[k] * (dml_float_t)p->HTotal[k] / p->PixelClock[k]) * 4.0);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2946
if (p->WritebackPixelFormat[k] == dml_444_64) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2953
s->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(s->ActiveDRAMClockChangeLatencyMargin[k], s->WritebackFCLKChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2954
s->ActiveFCLKChangeLatencyMargin[k] = dml_min(s->ActiveFCLKChangeLatencyMargin[k], s->WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2956
p->MaxActiveDRAMClockChangeLatencySupported[k] = (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) ? 0 : (s->ActiveDRAMClockChangeLatencyMargin[k] + p->mmSOCParameters.DRAMClockChangeLatency);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2957
p->ActiveDRAMClockChangeLatencyMargin[k] = s->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2961
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2962
if ((p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) && (s->USRRetrainingLatencyMargin[k] < 0)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2968
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2969
if ((p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) && ((!s->FoundCriticalSurface)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2970
|| ((s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency) < *p->MaxActiveFCLKChangeLatencySupported))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2972
*p->MaxActiveFCLKChangeLatencySupported = s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2992
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2993
if ((p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) && (s->ActiveFCLKChangeLatencyMargin[k] < 0)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2994
if (!(p->PrefetchMode[k] <= 1)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2997
s->FCLKChangeSupportNumber = ((p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2998
s->LastSurfaceWithoutMargin = k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
2999
} else if (((s->FCLKChangeSupportNumber == 1) && (p->DRRDisplay[k] || (!s->SynchronizedSurfaces[s->LastSurfaceWithoutMargin][k]))) || (s->FCLKChangeSupportNumber == 2))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3013
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3014
if (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3016
else if (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3021
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3022
if (((s->DRAMClockChangeMethod == 0) && (s->ActiveDRAMClockChangeLatencyMargin[k] < 0)) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3023
((s->DRAMClockChangeMethod == 1) && (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_full_frame)) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3024
((s->DRAMClockChangeMethod == 2) && (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_sub_viewport) && (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3025
if (p->PrefetchMode[k] != 0) { // Don't need to support DRAM clock change, PrefetchMode 0 means needs DRAM clock change support
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3028
s->DRAMClockChangeSupportNumber = (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3029
s->LastSurfaceWithoutMargin = k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3030
} else if (((s->DRAMClockChangeSupportNumber == 1) && (p->DRRDisplay[k] || !s->SynchronizedSurfaces[s->LastSurfaceWithoutMargin][k])) || (s->DRAMClockChangeSupportNumber == 2)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3068
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3069
s->dst_y_pstate = (dml_uint_t)(dml_ceil((p->mmSOCParameters.DRAMClockChangeLatency + p->mmSOCParameters.UrgentLatency) / (p->HTotal[k] / p->PixelClock[k]), 1));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3070
s->src_y_pstate_l = (dml_uint_t)(dml_ceil(s->dst_y_pstate * p->VRatio[k], p->SwathHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3071
s->src_y_ahead_l = (dml_uint_t)(dml_floor(p->DETBufferSizeY[k] / p->BytePerPixelDETY[k] / p->SwathWidthY[k], p->SwathHeightY[k]) + s->LBLatencyHidingSourceLinesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3072
s->sub_vp_lines_l = s->src_y_pstate_l + s->src_y_ahead_l + p->meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3075
dml_print("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3076
dml_print("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3077
dml_print("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3078
dml_print("DML::%s: k=%u, SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3079
dml_print("DML::%s: k=%u, LBLatencyHidingSourceLinesY = %u\n", __func__, k, s->LBLatencyHidingSourceLinesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3080
dml_print("DML::%s: k=%u, dst_y_pstate = %u\n", __func__, k, s->dst_y_pstate);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3081
dml_print("DML::%s: k=%u, src_y_pstate_l = %u\n", __func__, k, s->src_y_pstate_l);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3082
dml_print("DML::%s: k=%u, src_y_ahead_l = %u\n", __func__, k, s->src_y_ahead_l);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3083
dml_print("DML::%s: k=%u, meta_row_height = %u\n", __func__, k, p->meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3084
dml_print("DML::%s: k=%u, sub_vp_lines_l = %u\n", __func__, k, s->sub_vp_lines_l);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3086
p->SubViewportLinesNeededInMALL[k] = s->sub_vp_lines_l;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3088
if (p->BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3089
s->src_y_pstate_c = (dml_uint_t)(dml_ceil(s->dst_y_pstate * p->VRatioChroma[k], p->SwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3090
s->src_y_ahead_c = (dml_uint_t)(dml_floor(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3091
s->sub_vp_lines_c = s->src_y_pstate_c + s->src_y_ahead_c + p->meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3092
p->SubViewportLinesNeededInMALL[k] = (dml_uint_t)(dml_max(s->sub_vp_lines_l, s->sub_vp_lines_c));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3095
dml_print("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s->src_y_pstate_c);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3096
dml_print("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s->src_y_ahead_c);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3097
dml_print("DML::%s: k=%u, meta_row_height_chroma = %u\n", __func__, k, p->meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3098
dml_print("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s->sub_vp_lines_c);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3138
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3140
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3141
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3143
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3145
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3148
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3149
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3151
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3155
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3156
DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3157
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3159
DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3161
DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3164
dml_print("DML::%s: k=%u, PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3165
dml_print("DML::%s: k=%u, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3169
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3170
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3182
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3183
*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3305
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3308
dml_print("DML::%s: k=%u : HRatio = %f\n", __func__, k, HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3309
dml_print("DML::%s: k=%u : VRatio = %f\n", __func__, k, VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3310
dml_print("DML::%s: k=%u : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3311
dml_print("DML::%s: k=%u : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3312
dml_print("DML::%s: k=%u : swath_width_luma_ub = %u\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3313
dml_print("DML::%s: k=%u : swath_width_chroma_ub = %u\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3314
dml_print("DML::%s: k=%u : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3315
dml_print("DML::%s: k=%u : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3316
dml_print("DML::%s: k=%u : DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3317
dml_print("DML::%s: k=%u : PixelClock = %f\n", __func__, k, PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3318
dml_print("DML::%s: k=%u : Dppclk = %f\n", __func__, k, Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3321
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3322
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3324
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3327
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3328
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3330
if (VRatioChroma[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3331
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3333
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3337
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3338
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3340
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3343
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3344
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3346
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3347
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3349
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3353
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3354
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3355
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3356
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3360
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3361
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3362
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3364
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3367
dml_print("DML::%s: k=%u : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3370
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3371
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3372
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3373
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3374
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3376
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3377
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3379
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3382
dml_print("DML::%s: k=%u : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3384
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3385
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3388
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3389
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3390
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3391
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3395
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3397
cursor_req_per_width = (dml_uint_t)(dml_ceil((dml_float_t) CursorWidth[k] * (dml_float_t) CursorBPP[k] / 256.0 / 8.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3398
if (NumberOfCursors[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3399
if (VRatio[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3400
CursorRequestDeliveryTime[k] = (dml_float_t) CursorWidth[k] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3402
CursorRequestDeliveryTime[k] = (dml_float_t) CursorWidth[k] / PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3404
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3405
CursorRequestDeliveryTimePrefetch[k] = (dml_float_t) CursorWidth[k] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3407
CursorRequestDeliveryTimePrefetch[k] = (dml_float_t) CursorWidth[k] / PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3410
CursorRequestDeliveryTime[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3411
CursorRequestDeliveryTimePrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3414
dml_print("DML::%s: k=%u : NumberOfCursors = %u\n", __func__, k, NumberOfCursors[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3415
dml_print("DML::%s: k=%u : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3416
dml_print("DML::%s: k=%u : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3492
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3493
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3494
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3495
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3497
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3499
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3500
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3501
DST_Y_PER_META_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3503
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3507
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3508
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3509
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3510
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3511
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3512
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3513
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3514
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3516
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3523
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3524
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3525
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3526
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3527
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3528
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3529
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3531
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3532
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3533
meta_chunk_per_row_int_chroma = (dml_uint_t)((dml_float_t) meta_row_width_chroma[k] / meta_chunk_width_chroma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3534
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3535
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3536
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3538
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3545
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3546
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3547
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3550
TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3551
TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3552
TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3553
TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3554
TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3555
TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3559
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3561
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3562
dpte_group_width_luma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeY[k] * PixelPTEReqWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3564
dpte_group_width_luma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeY[k] * PixelPTEReqHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3567
if (use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3568
dpte_groups_per_row_luma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_luma_ub[k] / (dml_float_t) dpte_group_width_luma / 2.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3570
dpte_groups_per_row_luma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_luma_ub[k] / (dml_float_t) dpte_group_width_luma, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3573
dml_print("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, use_one_row_for_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3574
dml_print("DML::%s: k=%u, dpte_group_bytes = %u\n", __func__, k, dpte_group_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3575
dml_print("DML::%s: k=%u, PTERequestSizeY = %u\n", __func__, k, PTERequestSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3576
dml_print("DML::%s: k=%u, PixelPTEReqWidthY = %u\n", __func__, k, PixelPTEReqWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3577
dml_print("DML::%s: k=%u, PixelPTEReqHeightY = %u\n", __func__, k, PixelPTEReqHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3578
dml_print("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, dpte_row_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3579
dml_print("DML::%s: k=%u, dpte_group_width_luma = %u\n", __func__, k, dpte_group_width_luma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3580
dml_print("DML::%s: k=%u, dpte_groups_per_row_luma_ub = %u\n", __func__, k, dpte_groups_per_row_luma_ub);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3582
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3583
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3584
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3585
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3586
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3587
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3588
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3590
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3591
dpte_group_width_chroma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeC[k] * PixelPTEReqWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3593
dpte_group_width_chroma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeC[k] * PixelPTEReqHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3596
if (use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3597
dpte_groups_per_row_chroma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_chroma_ub[k] / (dml_float_t) dpte_group_width_chroma / 2.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3599
dpte_groups_per_row_chroma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_chroma_ub[k] / (dml_float_t) dpte_group_width_chroma, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3601
dml_print("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, dpte_row_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3602
dml_print("DML::%s: k=%u, dpte_group_width_chroma = %u\n", __func__, k, dpte_group_width_chroma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3603
dml_print("DML::%s: k=%u, dpte_groups_per_row_chroma_ub = %u\n", __func__, k, dpte_groups_per_row_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3605
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3606
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3607
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3610
time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3611
time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3612
time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3613
time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3614
time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3615
time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3618
dml_print("DML::%s: k=%u, DestinationLinesToRequestRowInVBlank = %f\n", __func__, k, DestinationLinesToRequestRowInVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3619
dml_print("DML::%s: k=%u, DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, k, DestinationLinesToRequestRowInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3621
dml_print("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_L = %f\n", __func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3622
dml_print("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_C = %f\n", __func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3623
dml_print("DML::%s: k=%u, DST_Y_PER_META_ROW_NOM_L = %f\n", __func__, k, DST_Y_PER_META_ROW_NOM_L[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3624
dml_print("DML::%s: k=%u, DST_Y_PER_META_ROW_NOM_C = %f\n", __func__, k, DST_Y_PER_META_ROW_NOM_C[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3625
dml_print("DML::%s: k=%u, TimePerMetaChunkNominal = %f\n", __func__, k, TimePerMetaChunkNominal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3626
dml_print("DML::%s: k=%u, TimePerMetaChunkVBlank = %f\n", __func__, k, TimePerMetaChunkVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3627
dml_print("DML::%s: k=%u, TimePerMetaChunkFlip = %f\n", __func__, k, TimePerMetaChunkFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3628
dml_print("DML::%s: k=%u, TimePerChromaMetaChunkNominal = %f\n", __func__, k, TimePerChromaMetaChunkNominal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3629
dml_print("DML::%s: k=%u, TimePerChromaMetaChunkVBlank = %f\n", __func__, k, TimePerChromaMetaChunkVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3630
dml_print("DML::%s: k=%u, TimePerChromaMetaChunkFlip = %f\n", __func__, k, TimePerChromaMetaChunkFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3631
dml_print("DML::%s: k=%u, time_per_pte_group_nom_luma = %f\n", __func__, k, time_per_pte_group_nom_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3632
dml_print("DML::%s: k=%u, time_per_pte_group_vblank_luma = %f\n", __func__, k, time_per_pte_group_vblank_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3633
dml_print("DML::%s: k=%u, time_per_pte_group_flip_luma = %f\n", __func__, k, time_per_pte_group_flip_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3634
dml_print("DML::%s: k=%u, time_per_pte_group_nom_chroma = %f\n", __func__, k, time_per_pte_group_nom_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3635
dml_print("DML::%s: k=%u, time_per_pte_group_vblank_chroma = %f\n", __func__, k, time_per_pte_group_vblank_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3636
dml_print("DML::%s: k=%u, time_per_pte_group_flip_chroma = %f\n", __func__, k, time_per_pte_group_flip_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3672
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3675
dml_print("DML::%s: k=%u, DCCEnable = %u\n", __func__, k, DCCEnable[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3676
dml_print("DML::%s: k=%u, vm_group_bytes = %u\n", __func__, k, vm_group_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3677
dml_print("DML::%s: k=%u, dpde0_bytes_per_frame_ub_l = %u\n", __func__, k, dpde0_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3678
dml_print("DML::%s: k=%u, dpde0_bytes_per_frame_ub_c = %u\n", __func__, k, dpde0_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3679
dml_print("DML::%s: k=%u, meta_pte_bytes_per_frame_ub_l = %u\n", __func__, k, meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3680
dml_print("DML::%s: k=%u, meta_pte_bytes_per_frame_ub_c = %u\n", __func__, k, meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3683
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3684
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3685
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3686
num_group_per_lower_vm_stage = (dml_uint_t) (dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_l[k] / (dml_float_t) vm_group_bytes[k], 1.0) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3687
dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_c[k] / (dml_float_t) vm_group_bytes[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3689
num_group_per_lower_vm_stage = (dml_uint_t) (dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_l[k] / (dml_float_t) vm_group_bytes[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3693
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3694
num_group_per_lower_vm_stage = (dml_uint_t)(dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3695
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_c[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3697
num_group_per_lower_vm_stage = (dml_uint_t)(dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3700
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3701
num_group_per_lower_vm_stage = (dml_uint_t)(2.0 + dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3702
dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_c[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3703
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3704
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_c[k]) / (dml_float_t) (vm_group_bytes[k]), 1));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3706
num_group_per_lower_vm_stage = (dml_uint_t)(1.0 + dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3707
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3712
if (DCCEnable[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3713
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3714
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3716
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3720
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3721
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3723
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3726
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3727
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3729
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3734
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3735
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3736
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3737
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3740
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3741
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3742
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3743
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3747
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3748
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3749
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3750
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3754
dml_print("DML::%s: k=%u, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3755
dml_print("DML::%s: k=%u, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3756
dml_print("DML::%s: k=%u, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3757
dml_print("DML::%s: k=%u, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3813
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3814
if (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3815
if (p->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3816
if ((dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockWidth256BytesY[k] > p->SwathHeightY[k]) || (!dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockHeight256BytesY[k] > p->SwathHeightY[k]) || p->DCCYMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3821
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] / dml_min(p->NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3823
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3824
dml_print("DML::%s: k=%u, NetDCCRateLuma = %f\n", __func__, k, p->NetDCCRateLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3825
dml_print("DML::%s: k=%u, MaximumEffectiveCompressionLuma = %f\n", __func__, k, MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3827
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->DCCFractionOfZeroSizeRequestsLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3828
TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3830
if (p->ReadBandwidthSurfaceChroma[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3831
if ((dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockWidth256BytesC[k] > p->SwathHeightC[k]) || (!dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockHeight256BytesC[k] > p->SwathHeightC[k]) || p->DCCCMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3836
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] / dml_min(p->NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3838
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, p->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3839
dml_print("DML::%s: k=%u, NetDCCRateChroma = %f\n", __func__, k, p->NetDCCRateChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3840
dml_print("DML::%s: k=%u, MaximumEffectiveCompressionChroma = %f\n", __func__, k, MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3842
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->DCCFractionOfZeroSizeRequestsChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3843
TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3846
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] + p->ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3848
TotalRowReadBandwidth = TotalRowReadBandwidth + p->DPPPerSurface[k] * (p->meta_row_bw[k] + p->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3903
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3904
if (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3905
LinesInDETY = ((dml_float_t)p->DETBufferSizeY[k] + (p->UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * p->ReadBandwidthSurfaceLuma[k] / p->TotalDataReadBandwidth) / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3906
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, p->SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3907
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((dml_float_t)p->HTotal[k] / p->PixelClock[k]) / p->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3909
dml_print("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3910
dml_print("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3911
dml_print("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3912
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3913
dml_print("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, p->TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3914
dml_print("DML::%s: k=%u, LinesInDETY = %f\n", __func__, k, LinesInDETY);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3915
dml_print("DML::%s: k=%u, LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3916
dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, p->HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3917
dml_print("DML::%s: k=%u, PixelClock = %f\n", __func__, k, p->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3918
dml_print("DML::%s: k=%u, VRatio = %f\n", __func__, k, p->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3919
dml_print("DML::%s: k=%u, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3920
dml_print("DML::%s: k=%u,PixelClock = %f\n", __func__, k, p->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3924
dml_bool_t isInterlaceTiming = p->Interlace[k] && !p->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3928
FrameTimeCriticalSurface = (isInterlaceTiming ? dml_floor((dml_float_t)p->VTotal[k]/2.0, 1.0) : p->VTotal[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3929
VActiveTimeCriticalSurface = (isInterlaceTiming ? dml_floor((dml_float_t)p->VActive[k]/2.0, 1.0) : p->VActive[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3930
BytePerPixelYCriticalSurface = p->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3931
SwathWidthYCriticalSurface = p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3932
SwathHeightYCriticalSurface = p->SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3933
BlockWidth256BytesYCriticalSurface = p->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3934
LinesToFinishSwathTransferStutterCriticalSurface = p->SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3935
DETBufferSizeYCriticalSurface = p->DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3936
MinTTUVBlankCriticalSurface = p->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3937
SinglePlaneCriticalSurface = (p->ReadBandwidthSurfaceChroma[k] == 0);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3938
SinglePipeCriticalSurface = (p->DPPPerSurface[k] == 1);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3941
dml_print("DML::%s: k=%u, FoundCriticalSurface = %u\n", __func__, k, FoundCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3942
dml_print("DML::%s: k=%u, StutterPeriod = %f\n", __func__, k, *p->StutterPeriod);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3943
dml_print("DML::%s: k=%u, MinTTUVBlankCriticalSurface = %f\n", __func__, k, MinTTUVBlankCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3944
dml_print("DML::%s: k=%u, FrameTimeCriticalSurface = %f\n", __func__, k, FrameTimeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3945
dml_print("DML::%s: k=%u, VActiveTimeCriticalSurface = %f\n", __func__, k, VActiveTimeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3946
dml_print("DML::%s: k=%u, BytePerPixelYCriticalSurface = %u\n", __func__, k, BytePerPixelYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3947
dml_print("DML::%s: k=%u, SwathWidthYCriticalSurface = %f\n", __func__, k, SwathWidthYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3948
dml_print("DML::%s: k=%u, SwathHeightYCriticalSurface = %f\n", __func__, k, SwathHeightYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3949
dml_print("DML::%s: k=%u, BlockWidth256BytesYCriticalSurface = %u\n", __func__, k, BlockWidth256BytesYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3950
dml_print("DML::%s: k=%u, SinglePlaneCriticalSurface = %u\n", __func__, k, SinglePlaneCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3951
dml_print("DML::%s: k=%u, SinglePipeCriticalSurface = %u\n", __func__, k, SinglePipeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3952
dml_print("DML::%s: k=%u, LinesToFinishSwathTransferStutterCriticalSurface = %f\n", __func__, k, LinesToFinishSwathTransferStutterCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3985
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
3986
if (p->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4016
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4017
if (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4018
if (p->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4020
SinglePixelClock = p->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4021
SingleHTotal = p->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4022
SingleVTotal = p->VTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4023
} else if (SinglePixelClock != p->PixelClock[k] || SingleHTotal != p->HTotal[k] || SingleVTotal != p->VTotal[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4108
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4109
dml_print("DML::%s: DPPPerSurface[%u] = %u\n", __func__, k, p->DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4149
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4150
RoundedUpMaxSwathSizeBytesY[k] = (dml_uint_t)(p->swath_width_luma_ub[k] * p->BytePerPixDETY[k] * MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4151
RoundedUpMaxSwathSizeBytesC[k] = (dml_uint_t)(p->swath_width_chroma_ub[k] * p->BytePerPixDETC[k] * MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4153
dml_print("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, p->DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4154
dml_print("DML::%s: k=%u swath_width_luma_ub = %u\n", __func__, k, p->swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4155
dml_print("DML::%s: k=%u BytePerPixDETY = %f\n", __func__, k, p->BytePerPixDETY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4156
dml_print("DML::%s: k=%u MaximumSwathHeightY = %u\n", __func__, k, MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4157
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesY = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4158
dml_print("DML::%s: k=%u swath_width_chroma_ub = %u\n", __func__, k, p->swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4159
dml_print("DML::%s: k=%u BytePerPixDETC = %f\n", __func__, k, p->BytePerPixDETC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4160
dml_print("DML::%s: k=%u MaximumSwathHeightC = %u\n", __func__, k, MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4161
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesC = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4163
if (p->SourcePixelFormat[k] == dml_420_10) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4164
RoundedUpMaxSwathSizeBytesY[k] = (dml_uint_t)(dml_ceil((dml_float_t) RoundedUpMaxSwathSizeBytesY[k], 256));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4165
RoundedUpMaxSwathSizeBytesC[k] = (dml_uint_t)(dml_ceil((dml_float_t) RoundedUpMaxSwathSizeBytesC[k], 256));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4169
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4170
TotalActiveDPP = TotalActiveDPP + (p->ForceSingleDPP ? 1 : p->DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4171
if (p->DPPPerSurface[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4172
SurfaceDoingUnboundedRequest = k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4173
if (p->SourcePixelFormat[k] == dml_420_8 || p->SourcePixelFormat[k] == dml_420_10 ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4174
p->SourcePixelFormat[k] == dml_420_12 || p->SourcePixelFormat[k] == dml_rgbe_alpha
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4175
|| p->SurfaceTiling[k] == dml_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4215
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4217
DETBufferSizeInKByteForSwathCalculation = (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe ? 1024 : p->DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4219
dml_print("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation = %u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4222
if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4223
p->SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4224
p->SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4225
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4226
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4227
} else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] && RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4228
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4229
p->SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4230
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4231
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4232
} else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] && RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4233
p->SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4234
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4235
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4236
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4238
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4239
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4240
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4241
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4244
if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 > DETBufferSizeInKByteForSwathCalculation * 1024 / 2) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4245
p->SwathWidth[k] > p->MaximumSwathWidthLuma[k] || (p->SwathHeightC[k] > 0 && p->SwathWidthChroma[k] > p->MaximumSwathWidthChroma[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4247
p->ViewportSizeSupportPerSurface[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4249
p->ViewportSizeSupportPerSurface[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4252
if (p->SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4254
dml_print("DML::%s: k=%u All DET for plane0\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4256
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4257
p->DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4258
} else if (RoundedUpSwathSizeBytesY[k] <= 1.5 * RoundedUpSwathSizeBytesC[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4260
dml_print("DML::%s: k=%u Half DET for plane0, half for plane1\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4262
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4263
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4266
dml_print("DML::%s: k=%u 2/3 DET for plane0, 1/3 for plane1\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4268
p->DETBufferSizeY[k] = (dml_uint_t)(dml_floor(p->DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4269
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 - p->DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4273
dml_print("DML::%s: k=%u SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4274
dml_print("DML::%s: k=%u SwathHeightC = %u\n", __func__, k, p->SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4275
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesY = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4276
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesC = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4277
dml_print("DML::%s: k=%u RoundedUpSwathSizeBytesY = %u\n", __func__, k, RoundedUpSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4278
dml_print("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4279
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, p->DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4280
dml_print("DML::%s: k=%u DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4281
dml_print("DML::%s: k=%u DETBufferSizeC = %u\n", __func__, k, p->DETBufferSizeC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4282
dml_print("DML::%s: k=%u ViewportSizeSupportPerSurface = %u\n", __func__, k, p->ViewportSizeSupportPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4345
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4346
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4347
SwathWidthSingleDPPY[k] = ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4349
SwathWidthSingleDPPY[k] = ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4353
dml_print("DML::%s: k=%u ViewportWidth=%u\n", __func__, k, ViewportWidth[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4354
dml_print("DML::%s: k=%u ViewportHeight=%u\n", __func__, k, ViewportHeight[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4355
dml_print("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4358
MainSurfaceODMMode = ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4360
if (BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4366
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4369
SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k], true)));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4371
SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k], true)));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4372
} else if (DPPPerSurface[k] == 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4373
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4375
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4380
dml_print("DML::%s: k=%u HActive=%u\n", __func__, k, HActive[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4381
dml_print("DML::%s: k=%u HRatio=%f\n", __func__, k, HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4382
dml_print("DML::%s: k=%u MainSurfaceODMMode=%u\n", __func__, k, MainSurfaceODMMode);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4383
dml_print("DML::%s: k=%u SwathWidthSingleDPPY=%u\n", __func__, k, SwathWidthSingleDPPY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4384
dml_print("DML::%s: k=%u SwathWidthY=%u\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4387
if (SourcePixelFormat[k] == dml_420_8 || SourcePixelFormat[k] == dml_420_10 || SourcePixelFormat[k] == dml_420_12) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4388
SwathWidthC[k] = SwathWidthY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4389
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4391
SwathWidthC[k] = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4392
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4396
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4397
SwathWidthC[k] = SwathWidthSingleDPPC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4400
surface_width_ub_l = (dml_uint_t)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4401
surface_height_ub_l = (dml_uint_t)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4403
if (!dml_is_vertical_rotation(SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4404
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4405
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4406
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4407
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_floor(ViewportXStart[k] + SwathWidthY[k] + Read256BytesBlockWidthY[k] - 1, Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStart[k], Read256BytesBlockWidthY[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4409
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4411
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4412
surface_width_ub_c = (dml_uint_t)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4413
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4414
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_floor(ViewportXStartC[k] + SwathWidthC[k] + Read256BytesBlockWidthC[k] - 1, Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], Read256BytesBlockWidthC[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4416
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4419
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4422
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4423
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4425
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4426
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4428
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4430
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4431
surface_height_ub_c = (dml_uint_t)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4432
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4433
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_floor(ViewportYStartC[k] + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], Read256BytesBlockHeightC[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4435
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4438
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4443
dml_print("DML::%s: k=%u surface_width_ub_l=%u\n", __func__, k, surface_width_ub_l);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4444
dml_print("DML::%s: k=%u surface_height_ub_l=%u\n", __func__, k, surface_height_ub_l);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4445
dml_print("DML::%s: k=%u surface_width_ub_c=%u\n", __func__, k, surface_width_ub_c);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4446
dml_print("DML::%s: k=%u surface_height_ub_c=%u\n", __func__, k, surface_height_ub_c);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4447
dml_print("DML::%s: k=%u Read256BytesBlockWidthY=%u\n", __func__, k, Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4448
dml_print("DML::%s: k=%u Read256BytesBlockHeightY=%u\n", __func__, k, Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4449
dml_print("DML::%s: k=%u Read256BytesBlockWidthC=%u\n", __func__, k, Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4450
dml_print("DML::%s: k=%u Read256BytesBlockHeightC=%u\n", __func__, k, Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4451
dml_print("DML::%s: k=%u ViewportStationary=%u\n", __func__, k, ViewportStationary[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4452
dml_print("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4453
dml_print("DML::%s: k=%u swath_width_luma_ub=%u\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4454
dml_print("DML::%s: k=%u swath_width_chroma_ub=%u\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4455
dml_print("DML::%s: k=%u MaximumSwathHeightY=%u\n", __func__, k, MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4456
dml_print("DML::%s: k=%u MaximumSwathHeightC=%u\n", __func__, k, MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4550
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4551
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4607
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4608
s->TotalMaxPrefetchFlipDPTERowBandwidth[j] = s->TotalMaxPrefetchFlipDPTERowBandwidth[j] + p->NoOfDPP[j][k] * p->DPTEBytesPerRow[j][k] / (15.75 * p->HTotal[k] / p->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4611
for (dml_uint_t k = 0; k <= p->NumberOfActiveSurfaces - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4612
s->NoOfDPPState[k] = p->NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4623
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4627
s->PixelDCFCLKCyclesRequiredInPrefetch[k] = (p->PrefetchLinesY[j][k] * p->swath_width_luma_ub_all_states[j][k] * p->BytePerPixelY[k] + p->PrefetchLinesC[j][k] * p->swath_width_chroma_ub_all_states[j][k] * p->BytePerPixelC[k]) / s->NormalEfficiency / p->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4628
DCFCLKCyclesRequiredInPrefetch = 2 * s->ExtraLatencyCycles / s->NoOfDPPState[k] + p->PDEAndMetaPTEBytesPerFrame[j][k] / s->NormalEfficiency / s->NormalEfficiency / p->ReturnBusWidth * (p->GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * p->DPTEBytesPerRow[j][k] / s->NormalEfficiency / s->NormalEfficiency / p->ReturnBusWidth + 2 * p->MetaRowBytes[j][k] / s->NormalEfficiency / p->ReturnBusWidth + s->PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4629
s->PrefetchPixelLinesTime[k] = dml_max(p->PrefetchLinesY[j][k], p->PrefetchLinesC[j][k]) * p->HTotal[k] / p->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4630
s->DynamicMetadataVMExtraLatency[k] = (p->GPUVMEnable == true && p->DynamicMetadataEnable[k] == true && p->DynamicMetadataVMEnabled == true) ? p->UrgLatency * p->GPUVMMaxPageTableLevels * (p->HostVMEnable == true ? p->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4633
p->UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4635
p->DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4641
PrefetchTime = (p->MaximumVStartup[j][k] - 1) * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - p->UrgLatency * ((p->GPUVMMaxPageTableLevels <= 2 ? p->GPUVMMaxPageTableLevels : p->GPUVMMaxPageTableLevels - 2) * (p->HostVMEnable == true ? p->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - s->DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4645
ExpectedVRatioPrefetch = s->PrefetchPixelLinesTime[k] / (PrefetchTime * s->PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4646
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = s->NoOfDPPState[k] * s->PixelDCFCLKCyclesRequiredInPrefetch[k] / s->PrefetchPixelLinesTime[k] * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4648
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = s->DCFCLKRequiredForPeakBandwidthPerSurface[k] + s->NoOfDPPState[k] * s->DPTEBandwidth / s->NormalEfficiency / s->NormalEfficiency / p->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4651
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = p->DCFCLKPerState;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4653
if (p->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4662
p->RequiredDPPCLKPerSurface[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4665
p->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4666
p->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4667
p->VTotal[k] - p->VActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4668
p->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4669
p->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4670
p->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4682
AllowedTimeForUrgentExtraLatency = p->MaximumVStartup[j][k] * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe - TdmsksPipe - s->DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4684
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = dml_max(s->DCFCLKRequiredForPeakBandwidthPerSurface[k], s->ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4686
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = p->DCFCLKPerState;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4691
for (dml_uint_t k = 0; k <= p->NumberOfActiveSurfaces - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4692
s->DCFCLKRequiredForPeakBandwidth = s->DCFCLKRequiredForPeakBandwidth + s->DCFCLKRequiredForPeakBandwidthPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4695
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4697
MaximumTvmPlus2Tr0PlusTsw = (p->MaximumVStartup[j][k] - 2) * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - s->DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4698
if (MaximumTvmPlus2Tr0PlusTsw <= s->MinimumTvmPlus2Tr0 + s->PrefetchPixelLinesTime[k] / 4) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4702
2 * s->ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - s->MinimumTvmPlus2Tr0 - s->PrefetchPixelLinesTime[k] / 4),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4703
(2 * s->ExtraLatencyCycles + s->PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - s->MinimumTvmPlus2Tr0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4761
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4762
if (ViewportStationary[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4763
SurfaceSizeInMALL[k] = (dml_uint_t)(dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], ReadBlockWidthY[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4764
dml_min(dml_ceil(SurfaceHeightY[k], ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) - dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4765
BytesPerPixelY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4767
if (ReadBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4768
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4769
dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) - dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4770
dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]), dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) - dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) * BytesPerPixelC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4772
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4773
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4774
dml_min(dml_ceil(SurfaceWidthY[k], 8 * Read256BytesBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4775
dml_min(dml_ceil(SurfaceHeightY[k], 8 * Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 * Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 * Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4776
if (Read256BytesBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4777
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4778
dml_min(dml_ceil(SurfaceWidthC[k], 8 * Read256BytesBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1, 8 * Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], 8 * Read256BytesBlockWidthC[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4779
dml_min(dml_ceil(SurfaceHeightC[k], 8 * Read256BytesBlockHeightC[k]), dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1, 8 * Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], 8 * Read256BytesBlockHeightC[k])) * BytesPerPixelC[k] / 256);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4783
SurfaceSizeInMALL[k] = (dml_uint_t)(dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4784
if (ReadBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4785
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4786
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4787
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4789
if (DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4790
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4791
dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1), 8 * Read256BytesBlockWidthY[k]) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4792
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1), 8 * Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4794
if (Read256BytesBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4795
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4796
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1), 8 * Read256BytesBlockWidthC[k]) *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4797
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1), 8 * Read256BytesBlockHeightC[k]) * BytesPerPixelC[k] / 256);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4803
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4804
if (UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4805
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4864
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4865
DETBufferSizeInKByte[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4866
if (SourcePixelFormat[k] == dml_420_8 || SourcePixelFormat[k] == dml_420_10 || SourcePixelFormat[k] == dml_420_12) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4876
if (2.0 * ((dml_float_t) RoundedUpMaxSwathSizeBytesY[k] + (dml_float_t) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4882
dml_print("DML::%s: k=%u minDET = %u\n", __func__, k, minDET);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4883
dml_print("DML::%s: k=%u max_minDET = %u\n", __func__, k, max_minDET);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4884
dml_print("DML::%s: k=%u minDET_pipe = %u\n", __func__, k, minDET_pipe);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4885
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesY = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4886
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesC = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4890
minDET_pipe = (dml_uint_t)(dml_max(128, dml_ceil(((dml_float_t)RoundedUpMaxSwathSizeBytesY[k] + (dml_float_t)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4892
dml_print("DML::%s: k=%u minDET_pipe = %u (assume each plane take half DET)\n", __func__, k, minDET_pipe);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4896
if (UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4897
DETBufferSizeInKByte[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4898
} else if (DETSizeOverride[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4899
DETBufferSizeInKByte[k] = DETSizeOverride[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4900
DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4901
} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4902
DETBufferSizeInKByte[k] = minDET_pipe;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4903
DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4907
dml_print("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4908
dml_print("DML::%s: k=%u DETSizeOverride = %u\n", __func__, k, DETSizeOverride[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4909
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4915
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4916
if (UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4917
TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4921
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4922
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4928
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4930
if (UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4931
DETPieceAssignedToThisSurfaceAlready[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4932
} else if (DETSizeOverride[k] > 0 || (((dml_float_t) (ForceSingleDPP ? 1 : DPPPerSurface[k]) * (dml_float_t) DETBufferSizeInKByte[k] / (dml_float_t) MaxTotalDETInKByte) >= ((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4933
DETPieceAssignedToThisSurfaceAlready[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4934
BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece - ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4936
DETPieceAssignedToThisSurfaceAlready[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4939
dml_print("DML::%s: k=%u DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, k, DETPieceAssignedToThisSurfaceAlready[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4940
dml_print("DML::%s: k=%u BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k, BandwidthOfSurfacesNotAssignedDETPiece);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4948
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4950
dml_print("DML::%s: j=%u k=%u, ReadBandwidthLuma[k] = %f\n", __func__, j, k, ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4951
dml_print("DML::%s: j=%u k=%u, ReadBandwidthChroma[k] = %f\n", __func__, j, k, ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4952
dml_print("DML::%s: j=%u k=%u, ReadBandwidthLuma[Next] = %f\n", __func__, j, k, ReadBandwidthLuma[NextSurfaceToAssignDETPiece]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4953
dml_print("DML::%s: j=%u k=%u, ReadBandwidthChroma[Next] = %f\n", __func__, j, k, ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4954
dml_print("DML::%s: j=%u k=%u, NextSurfaceToAssignDETPiece = %u\n", __func__, j, k, NextSurfaceToAssignDETPiece);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4956
if (!DETPieceAssignedToThisSurfaceAlready[k] && (!NextPotentialSurfaceToAssignDETPieceFound ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4957
ReadBandwidthLuma[k] + ReadBandwidthChroma[k] < ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[NextSurfaceToAssignDETPiece])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4958
NextSurfaceToAssignDETPiece = k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4962
dml_print("DML::%s: j=%u k=%u, DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
4963
dml_print("DML::%s: j=%u k=%u, NextPotentialSurfaceToAssignDETPieceFound = %u\n", __func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5011
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5012
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u (TotalReadBandWidth=%f)\n", __func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5059
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5061
p->vm_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5062
p->dpte_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5064
p->vm_group_bytes[k] = 2048;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5065
if (p->GPUVMMinPageSizeKBytes[k] >= 64 && dml_is_vertical_rotation(p->myPipe[k].SourceScan)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5066
p->dpte_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5068
p->dpte_group_bytes[k] = 2048;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5071
p->vm_group_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5072
p->dpte_group_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5075
if (p->myPipe[k].SourcePixelFormat == dml_420_8 || p->myPipe[k].SourcePixelFormat == dml_420_10 ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5076
p->myPipe[k].SourcePixelFormat == dml_420_12 || p->myPipe[k].SourcePixelFormat == dml_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5077
if ((p->myPipe[k].SourcePixelFormat == dml_420_10 || p->myPipe[k].SourcePixelFormat == dml_420_12) && !dml_is_vertical_rotation(p->myPipe[k].SourceScan)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5078
s->PTEBufferSizeInRequestsForLuma[k] = (p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma) / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5079
s->PTEBufferSizeInRequestsForChroma[k] = s->PTEBufferSizeInRequestsForLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5081
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5082
s->PTEBufferSizeInRequestsForChroma[k] = p->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5086
p->myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5087
p->myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5088
p->myPipe[k].DPPPerSurface,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5089
p->myPipe[k].BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5090
p->myPipe[k].BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5091
p->myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5092
p->myPipe[k].SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5093
p->myPipe[k].BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5094
p->myPipe[k].SourceScan,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5095
p->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5096
p->myPipe[k].ViewportHeightChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5097
p->myPipe[k].ViewportXStartC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5098
p->myPipe[k].ViewportYStartC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5101
p->GPUVMMinPageSizeKBytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5102
s->PTEBufferSizeInRequestsForChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5103
p->myPipe[k].PitchC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5104
p->myPipe[k].DCCMetaPitchC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5105
p->myPipe[k].BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5106
p->myPipe[k].BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5109
&s->MetaRowByteC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5110
&s->PixelPTEBytesPerRowC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5111
&s->PixelPTEBytesPerRowStorageC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5112
&p->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5113
&p->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5114
&p->dpte_row_height_linear_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5115
&s->PixelPTEBytesPerRowC_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5116
&s->dpte_row_width_chroma_ub_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5117
&s->dpte_row_height_chroma_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5118
&p->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5119
&p->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5120
&p->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5121
&p->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5122
&p->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5123
&p->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5124
&p->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5125
&p->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5126
&p->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5128
p->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines (
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5129
p->myPipe[k].VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5130
p->myPipe[k].VTapsChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5131
p->myPipe[k].InterlaceEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5132
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5133
p->myPipe[k].SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5134
p->myPipe[k].SourceScan,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5135
p->myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5136
p->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5137
p->myPipe[k].ViewportHeightChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5138
p->myPipe[k].ViewportXStartC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5139
p->myPipe[k].ViewportYStartC,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5142
&p->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5143
&p->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5145
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5146
s->PTEBufferSizeInRequestsForChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5147
s->PixelPTEBytesPerRowC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5148
s->PixelPTEBytesPerRowStorageC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5150
s->MetaRowByteC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5151
p->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5152
p->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5153
s->dpte_row_height_chroma_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5154
s->dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5155
s->PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5159
p->myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5160
p->myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5161
p->myPipe[k].DPPPerSurface,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5162
p->myPipe[k].BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5163
p->myPipe[k].BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5164
p->myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5165
p->myPipe[k].SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5166
p->myPipe[k].BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5167
p->myPipe[k].SourceScan,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5168
p->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5169
p->myPipe[k].ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5170
p->myPipe[k].ViewportXStart,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5171
p->myPipe[k].ViewportYStart,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5174
p->GPUVMMinPageSizeKBytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5175
s->PTEBufferSizeInRequestsForLuma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5176
p->myPipe[k].PitchY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5177
p->myPipe[k].DCCMetaPitchY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5178
p->myPipe[k].BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5179
p->myPipe[k].BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5182
&s->MetaRowByteY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5183
&s->PixelPTEBytesPerRowY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5184
&s->PixelPTEBytesPerRowStorageY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5185
&p->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5186
&p->dpte_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5187
&p->dpte_row_height_linear_luma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5188
&s->PixelPTEBytesPerRowY_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5189
&s->dpte_row_width_luma_ub_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5190
&s->dpte_row_height_luma_one_row_per_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5191
&p->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5192
&p->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5193
&p->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5194
&p->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5195
&p->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5196
&p->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5197
&p->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5198
&p->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5199
&p->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5201
p->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5202
p->myPipe[k].VRatio,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5203
p->myPipe[k].VTaps,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5204
p->myPipe[k].InterlaceEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5205
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5206
p->myPipe[k].SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5207
p->myPipe[k].SourceScan,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5208
p->myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5209
p->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5210
p->myPipe[k].ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5211
p->myPipe[k].ViewportXStart,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5212
p->myPipe[k].ViewportYStart,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5215
&p->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5216
&p->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5218
p->PDEAndMetaPTEBytesFrame[k] = (s->PDEAndMetaPTEBytesFrameY + s->PDEAndMetaPTEBytesFrameC) * (1 + 8 * s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5219
p->MetaRowByte[k] = s->MetaRowByteY[k] + s->MetaRowByteC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5221
if (s->PixelPTEBytesPerRowStorageY[k] <= 64 * s->PTEBufferSizeInRequestsForLuma[k] && s->PixelPTEBytesPerRowStorageC[k] <= 64 * s->PTEBufferSizeInRequestsForChroma[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5222
p->PTEBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5224
p->PTEBufferSizeNotExceeded[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5226
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowY = %u\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5227
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowC = %u\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5228
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowStorageY = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5229
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowStorageC = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5230
dml_print("DML::%s: k=%u, PTEBufferSizeInRequestsForLuma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5231
dml_print("DML::%s: k=%u, PTEBufferSizeInRequestsForChroma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5232
dml_print("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5235
s->one_row_per_frame_fits_in_buffer[k] = (s->PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForLuma[k] &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5236
s->PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5239
dml_print("DML::%s: k=%u, PDEAndMetaPTEBytesFrame = %u\n", __func__, k, p->PDEAndMetaPTEBytesFrame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5240
dml_print("DML::%s: k=%u, PDEAndMetaPTEBytesFrameY = %u\n", __func__, k, s->PDEAndMetaPTEBytesFrameY);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5241
dml_print("DML::%s: k=%u, PDEAndMetaPTEBytesFrameC = %u\n", __func__, k, s->PDEAndMetaPTEBytesFrameC);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5242
dml_print("DML::%s: k=%u, HostVMDynamicLevels = %u\n", __func__, k, s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5243
dml_print("DML::%s: k=%u, one_row_per_frame_fits_in_buffer = %u\n", __func__, k, s->one_row_per_frame_fits_in_buffer[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5244
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowY_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowY_one_row_per_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5245
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowC_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowC_one_row_per_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5258
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5259
if (p->PTEBufferModeOverrideEn[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5260
p->PTE_BUFFER_MODE[k] = p->PTEBufferModeOverrideVal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5262
p->PTE_BUFFER_MODE[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->UsesMALLForStaticScreen[k] || (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5263
(p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) || (p->GPUVMMinPageSizeKBytes[k] > 64);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5264
p->BIGK_FRAGMENT_SIZE[k] = (dml_uint_t)(dml_log2(p->GPUVMMinPageSizeKBytes[k] * 1024) - 12);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5267
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5269
dml_print("DML::%s: k=%u, SurfaceSizeInMALL = %u\n", __func__, k, p->SurfaceSizeInMALL[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5270
dml_print("DML::%s: k=%u, UsesMALLForStaticScreen = %u\n", __func__, k, p->UsesMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5272
p->use_one_row_for_frame[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->UsesMALLForStaticScreen[k] || (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5273
(p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) || (p->GPUVMMinPageSizeKBytes[k] > 64 && dml_is_vertical_rotation(p->myPipe[k].SourceScan));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5275
p->use_one_row_for_frame_flip[k] = p->use_one_row_for_frame[k] && !(p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5277
if (p->use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5278
p->dpte_row_height_luma[k] = s->dpte_row_height_luma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5279
p->dpte_row_width_luma_ub[k] = s->dpte_row_width_luma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5280
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5281
p->dpte_row_height_chroma[k] = s->dpte_row_height_chroma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5282
p->dpte_row_width_chroma_ub[k] = s->dpte_row_width_chroma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5283
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5284
p->PTEBufferSizeNotExceeded[k] = s->one_row_per_frame_fits_in_buffer[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5287
if (p->MetaRowByte[k] <= p->DCCMetaBufferSizeBytes) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5288
p->DCCMetaBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5290
p->DCCMetaBufferSizeNotExceeded[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5293
dml_print("DML::%s: k=%u, MetaRowByte = %u\n", __func__, k, p->MetaRowByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5294
dml_print("DML::%s: k=%u, DCCMetaBufferSizeBytes = %u\n", __func__, k, p->DCCMetaBufferSizeBytes);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5295
dml_print("DML::%s: k=%u, DCCMetaBufferSizeNotExceeded = %u\n", __func__, k, p->DCCMetaBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5298
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY[k] * (1 + 8 * s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5299
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC[k] * (1 + 8 * s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5300
p->PixelPTEBytesPerRow[k] = s->PixelPTEBytesPerRowY[k] + s->PixelPTEBytesPerRowC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5301
if (p->use_one_row_for_frame[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5302
p->PixelPTEBytesPerRow[k] = p->PixelPTEBytesPerRow[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5306
p->myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5307
p->myPipe[k].VRatio,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5308
p->myPipe[k].VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5309
p->myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5310
p->myPipe[k].HTotal / p->myPipe[k].PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5311
s->MetaRowByteY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5312
s->MetaRowByteC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5313
p->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5314
p->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5315
s->PixelPTEBytesPerRowY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5316
s->PixelPTEBytesPerRowC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5317
p->dpte_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5318
p->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5321
&p->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5322
&p->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5324
dml_print("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p->use_one_row_for_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5325
dml_print("DML::%s: k=%u, use_one_row_for_frame_flip = %u\n", __func__, k, p->use_one_row_for_frame_flip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5326
dml_print("DML::%s: k=%u, UseMALLForPStateChange = %u\n", __func__, k, p->UseMALLForPStateChange[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5327
dml_print("DML::%s: k=%u, dpte_row_height_luma = %u\n", __func__, k, p->dpte_row_height_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5328
dml_print("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p->dpte_row_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5329
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowY = %u\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5330
dml_print("DML::%s: k=%u, dpte_row_height_chroma = %u\n", __func__, k, p->dpte_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5331
dml_print("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p->dpte_row_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5332
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowC = %u\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5333
dml_print("DML::%s: k=%u, PixelPTEBytesPerRow = %u\n", __func__, k, p->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5334
dml_print("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5335
dml_print("DML::%s: k=%u, PTE_BUFFER_MODE = %u\n", __func__, k, p->PTE_BUFFER_MODE[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5336
dml_print("DML::%s: k=%u, BIGK_FRAGMENT_SIZE = %u\n", __func__, k, p->BIGK_FRAGMENT_SIZE[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5702
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5703
Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5704
*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5709
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5710
Dppclk[k] = *GlobalDPPCLK / 255.0 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5711
dml_print("DML::%s: Dppclk[%0d] = %f\n", __func__, k, Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5731
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5732
UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5733
if (UsesMALLForStaticScreen[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5734
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5736
dml_print("DML::%s: k=%u, UsesMALLForStaticScreen = %u\n", __func__, k, UsesMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5737
dml_print("DML::%s: k=%u, TotalSurfaceSizeInMALL = %u\n", __func__, k, TotalSurfaceSizeInMALL);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5745
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5746
if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5747
!UsesMALLForStaticScreen[k] && UseMALLForStaticScreen[k] != dml_use_mall_static_screen_disable && one_row_per_frame_fits_in_buffer[k] &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5748
(!CanAddAnotherSurfaceToMALL || SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5750
SurfaceToAddToMALL = k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5751
dml_print("DML::%s: k=%u, UseMALLForStaticScreen = %u (dis, en, optimize)\n", __func__, k, UseMALLForStaticScreen[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5936
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5937
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5942
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5943
VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5986
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5987
if (NotUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5993
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5994
*PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5995
ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
5996
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6000
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6001
if (UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6003
+ dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6004
ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6005
+ cursor_bw[k] * UrgentBurstFactorCursor[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6006
+ NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6007
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6008
+ PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6009
+ cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6042
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6043
ret_val = ret_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6044
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) +
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6045
cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6047
dml_print("DML::%s: k=%u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6048
dml_print("DML::%s: NumberOfDPP = %u\n", __func__, NumberOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6049
dml_print("DML::%s: ReadBandwidthLuma = %f\n", __func__, ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6050
dml_print("DML::%s: UrgentBurstFactorLuma = %f\n", __func__, UrgentBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6051
dml_print("DML::%s: ReadBandwidthChroma = %f\n", __func__, ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6052
dml_print("DML::%s: UrgentBurstFactorChroma = %f\n", __func__, UrgentBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6053
dml_print("DML::%s: cursor_bw = %f\n", __func__, cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6054
dml_print("DML::%s: UrgentBurstFactorCursor = %f\n", __func__, UrgentBurstFactorCursor[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6056
dml_print("DML::%s: PrefetchBandwidthLuma = %f\n", __func__, PrefetchBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6057
dml_print("DML::%s: UrgentBurstFactorLumaPre = %f\n", __func__, UrgentBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6058
dml_print("DML::%s: PrefetchBandwidthChroma = %f\n", __func__, PrefetchBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6059
dml_print("DML::%s: UrgentBurstFactorChromaPre = %f\n", __func__, UrgentBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6060
dml_print("DML::%s: cursor_bw_pre = %f\n", __func__, cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6061
dml_print("DML::%s: UrgentBurstFactorCursorPre = %f\n", __func__, UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6099
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6100
if (ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6104
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6105
NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6106
NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6108
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6109
NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6110
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6113
dml_print("DML::%s: k = %u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6114
dml_print("DML::%s: ImmediateFlipRequirement = %u\n", __func__, ImmediateFlipRequirement[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6116
dml_print("DML::%s: NumberOfDPP = %u\n", __func__, NumberOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6117
dml_print("DML::%s: prefetch_vmrow_bw = %f\n", __func__, prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6118
dml_print("DML::%s: final_flip_bw = %f\n", __func__, final_flip_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6119
dml_print("DML::%s: ReadBandwidthLuma = %f\n", __func__, ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6120
dml_print("DML::%s: UrgentBurstFactorLuma = %f\n", __func__, UrgentBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6121
dml_print("DML::%s: ReadBandwidthChroma = %f\n", __func__, ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6122
dml_print("DML::%s: UrgentBurstFactorChroma = %f\n", __func__, UrgentBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6123
dml_print("DML::%s: cursor_bw = %f\n", __func__, cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6124
dml_print("DML::%s: UrgentBurstFactorCursor = %f\n", __func__, UrgentBurstFactorCursor[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6125
dml_print("DML::%s: PrefetchBandwidthLuma = %f\n", __func__, PrefetchBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6126
dml_print("DML::%s: UrgentBurstFactorLumaPre = %f\n", __func__, UrgentBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6127
dml_print("DML::%s: PrefetchBandwidthChroma = %f\n", __func__, PrefetchBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6128
dml_print("DML::%s: UrgentBurstFactorChromaPre = %f\n", __func__, UrgentBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6129
dml_print("DML::%s: cursor_bw_pre = %f\n", __func__, cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6130
dml_print("DML::%s: UrgentBurstFactorCursorPre = %f\n", __func__, UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6131
dml_print("DML::%s: meta_row_bandwidth = %f\n", __func__, meta_row_bandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6132
dml_print("DML::%s: dpte_row_bandwidth = %f\n", __func__, dpte_row_bandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6137
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6138
if (UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6139
if (ImmediateFlipRequirement[k] != dml_immediate_flip_not_required)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6140
*TotalBandwidthNotIncludingMALLPrefetch = *TotalBandwidthNotIncludingMALLPrefetch + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6141
NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6142
NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6143
+ cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6145
*TotalBandwidthNotIncludingMALLPrefetch = *TotalBandwidthNotIncludingMALLPrefetch + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6146
NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6147
+ ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6148
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6149
+ cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6221
dml_uint_t k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6223
CalculatePrefetchSchedule_params->DSCDelay = mode_lib->ms.DSCDelayPerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6230
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(mode_lib->ms.SwathWidthYThisState[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6231
CalculatePrefetchSchedule_params->OutputFormat = mode_lib->ms.cache_display_cfg.output.OutputFormat[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6238
CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6240
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6241
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6245
CalculatePrefetchSchedule_params->PDEAndMetaPTEBytesFrame = mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6246
CalculatePrefetchSchedule_params->MetaRowByte = mode_lib->ms.MetaRowBytes[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6247
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = mode_lib->ms.DPTEBytesPerRow[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6248
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = mode_lib->ms.PrefetchLinesY[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6249
CalculatePrefetchSchedule_params->VInitPreFillY = mode_lib->ms.PrefillY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6250
CalculatePrefetchSchedule_params->MaxNumSwathY = mode_lib->ms.MaxNumSwY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6251
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = mode_lib->ms.PrefetchLinesC[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6252
CalculatePrefetchSchedule_params->VInitPreFillC = mode_lib->ms.PrefillC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6253
CalculatePrefetchSchedule_params->MaxNumSwathC = mode_lib->ms.MaxNumSwC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6254
CalculatePrefetchSchedule_params->swath_width_luma_ub = mode_lib->ms.swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6255
CalculatePrefetchSchedule_params->swath_width_chroma_ub = mode_lib->ms.swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6256
CalculatePrefetchSchedule_params->SwathHeightY = mode_lib->ms.SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6257
CalculatePrefetchSchedule_params->SwathHeightC = mode_lib->ms.SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6259
CalculatePrefetchSchedule_params->DestinationLinesForPrefetch = &mode_lib->ms.LineTimesForPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6260
CalculatePrefetchSchedule_params->DestinationLinesToRequestVMInVBlank = &mode_lib->ms.LinesForMetaPTE[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6261
CalculatePrefetchSchedule_params->DestinationLinesToRequestRowInVBlank = &mode_lib->ms.LinesForMetaAndDPTERow[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6262
CalculatePrefetchSchedule_params->VRatioPrefetchY = &mode_lib->ms.VRatioPreY[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6263
CalculatePrefetchSchedule_params->VRatioPrefetchC = &mode_lib->ms.VRatioPreC[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6264
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWLuma = &mode_lib->ms.RequiredPrefetchPixelDataBWLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6265
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWChroma = &mode_lib->ms.RequiredPrefetchPixelDataBWChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6266
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->ms.support.NoTimeForDynamicMetadata[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6267
CalculatePrefetchSchedule_params->Tno_bw = &mode_lib->ms.Tno_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6276
dml_uint_t j, k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6281
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6282
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6283
mode_lib->ms.swath_width_luma_ub_this_state[k] = mode_lib->ms.swath_width_luma_ub_all_states[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6284
mode_lib->ms.swath_width_chroma_ub_this_state[k] = mode_lib->ms.swath_width_chroma_ub_all_states[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6285
mode_lib->ms.SwathWidthYThisState[k] = mode_lib->ms.SwathWidthYAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6286
mode_lib->ms.SwathWidthCThisState[k] = mode_lib->ms.SwathWidthCAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6287
mode_lib->ms.SwathHeightYThisState[k] = mode_lib->ms.SwathHeightYAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6288
mode_lib->ms.SwathHeightCThisState[k] = mode_lib->ms.SwathHeightCAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6291
mode_lib->ms.DETBufferSizeInKByteThisState[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6292
mode_lib->ms.DETBufferSizeYThisState[k] = mode_lib->ms.DETBufferSizeYAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6293
mode_lib->ms.DETBufferSizeCThisState[k] = mode_lib->ms.DETBufferSizeCAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6343
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6344
CalculatePrefetchMode(mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k], &s->MinPrefetchMode[k], &s->MaxPrefetchMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6345
s->NextPrefetchMode[k] = s->MinPrefetchMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6352
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6353
mode_lib->ms.PrefetchMode[k] = s->NextPrefetchMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6355
mode_lib->ms.PrefetchMode[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6356
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6358
mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6365
myPipe->Dppclk = mode_lib->ms.RequiredDPPCLKPerSurface[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6367
myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6369
myPipe->DPPPerSurface = mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6370
myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6371
myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6372
myPipe->BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6373
myPipe->BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6374
myPipe->BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6375
myPipe->BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6376
myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6377
myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6378
myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6379
myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6380
myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6381
myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6382
myPipe->ODMMode = mode_lib->ms.ODMModePerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6383
myPipe->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6384
myPipe->BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6385
myPipe->BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6389
dml_print("DML::%s: Calling CalculatePrefetchSchedule for j=%u, k=%u\n", __func__, j, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6390
dml_print("DML::%s: MaximumVStartup = %u\n", __func__, s->MaximumVStartup[j][k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6392
dml_print("DML::%s: NextPrefetchMode = %u\n", __func__, s->NextPrefetchMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6393
dml_print("DML::%s: AllowForPStateChangeOrStutterInVBlank = %u\n", __func__, mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6394
dml_print("DML::%s: PrefetchMode = %u\n", __func__, mode_lib->ms.PrefetchMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6399
CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->MaxVStartup, s->MaximumVStartup[j][k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6400
CalculatePrefetchSchedule_params->MaxVStartup = s->MaximumVStartup[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6401
CalculatePrefetchSchedule_params->DSTXAfterScaler = &s->DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6402
CalculatePrefetchSchedule_params->DSTYAfterScaler = &s->DSTYAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6403
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &mode_lib->ms.prefetch_vmrow_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6411
set_calculate_prefetch_schedule_params(mode_lib, CalculatePrefetchSchedule_params, j, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6413
mode_lib->ms.support.NoTimeForPrefetch[j][k] =
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6418
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6420
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6421
mode_lib->ms.swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6422
mode_lib->ms.swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6423
mode_lib->ms.SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6424
mode_lib->ms.SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6425
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6428
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6429
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6430
mode_lib->ms.VRatioPreY[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6431
mode_lib->ms.VRatioPreC[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6432
mode_lib->ms.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6433
mode_lib->ms.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6434
mode_lib->ms.DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6435
mode_lib->ms.DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6437
&mode_lib->ms.UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6438
&mode_lib->ms.UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6439
&mode_lib->ms.UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6440
&mode_lib->ms.NotUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6442
mode_lib->ms.cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] *
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6443
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6444
mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.VRatioPreY[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6477
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6478
if (mode_lib->ms.LineTimesForPrefetch[k] < 2.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6479
|| mode_lib->ms.LinesForMetaPTE[k] >= 32.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6480
|| mode_lib->ms.LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6481
|| mode_lib->ms.support.NoTimeForPrefetch[j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6487
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6488
if (mode_lib->ms.support.NoTimeForDynamicMetadata[j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6494
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6495
if (mode_lib->ms.support.NoTimeForPrefetch[j][k] == true ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6496
mode_lib->ms.VRatioPreY[j][k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6497
mode_lib->ms.VRatioPreC[j][k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6498
((s->MaxVStartup < s->MaximumVStartup[j][k] || mode_lib->ms.policy.EnhancedPrefetchScheduleAccelerationFinal == 0) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6499
(mode_lib->ms.VRatioPreY[j][k] > __DML_MAX_VRATIO_PRE__ || mode_lib->ms.VRatioPreC[j][k] > __DML_MAX_VRATIO_PRE__))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6505
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6506
if (mode_lib->ms.LinesForMetaAndDPTERow[k] >= 16 || mode_lib->ms.LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6530
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6531
if (!(mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6532
mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * (mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k] + mode_lib->ms.MetaRowBytes[j][k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6533
if (mode_lib->ms.use_one_row_for_frame_flip[j][k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6534
mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * (2 * mode_lib->ms.DPTEBytesPerRow[j][k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6536
mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * mode_lib->ms.DPTEBytesPerRow[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6541
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6551
mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6552
mode_lib->ms.MetaRowBytes[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6553
mode_lib->ms.DPTEBytesPerRow[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6556
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6557
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6558
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6559
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6560
mode_lib->ms.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6561
mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6562
mode_lib->ms.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6563
mode_lib->ms.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6564
mode_lib->ms.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6565
mode_lib->ms.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6566
mode_lib->ms.use_one_row_for_frame_flip[j][k], // 24
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6569
&mode_lib->ms.DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6570
&mode_lib->ms.DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6571
&mode_lib->ms.final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6572
&mode_lib->ms.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6605
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6606
if (!(mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required) && (mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6616
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6617
s->NextPrefetchMode[k] = s->NextPrefetchMode[k] + 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6619
if (s->NextPrefetchMode[k] <= s->MaxPrefetchMode[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6632
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6633
mode_lib->ms.use_one_row_for_frame_this_state[k] = mode_lib->ms.use_one_row_for_frame[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6792
dml_uint_t j, k, m;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6817
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6818
if (mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6819
&& ((mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6820
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6821
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6822
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6823
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6824
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6825
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6826
|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6827
|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6828
|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6829
|| mode_lib->ms.cache_display_cfg.plane.VTaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6831
} else if (mode_lib->ms.cache_display_cfg.plane.VTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.VTaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6832
|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6833
|| (mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 1.0 && (mode_lib->ms.cache_display_cfg.plane.HTaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6834
|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.ip.max_hscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6835
|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.ip.max_vscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6836
|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.cache_display_cfg.plane.HTaps[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6837
|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.cache_display_cfg.plane.VTaps[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6838
|| (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6839
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6840
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6841
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6842
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6843
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6844
&& (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] > 8 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 8 ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6845
(mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 1 && mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] % 2 == 1) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6846
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.ip.max_hscl_ratio ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6847
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.ip.max_vscl_ratio ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6848
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6849
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6856
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6857
if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear && (!(!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) || mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6862
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6864
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6865
mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6868
&mode_lib->ms.BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6869
&mode_lib->ms.BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6870
&mode_lib->ms.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6871
&mode_lib->ms.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6872
&mode_lib->ms.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6873
&mode_lib->ms.Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6874
&mode_lib->ms.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6875
&mode_lib->ms.Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6876
&mode_lib->ms.MacroTileHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6877
&mode_lib->ms.MacroTileHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6878
&mode_lib->ms.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6879
&mode_lib->ms.MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6883
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6884
if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6885
mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6886
mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6888
mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6889
mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6892
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6893
mode_lib->ms.ReadBandwidthLuma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * dml_ceil(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6894
mode_lib->ms.ReadBandwidthChroma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * dml_ceil(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6896
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6897
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6898
&& mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_64) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6899
mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6900
* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6901
/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6902
* mode_lib->ms.cache_display_cfg.timing.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6903
/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6904
} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6905
mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6906
* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6907
/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6908
* mode_lib->ms.cache_display_cfg.timing.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6909
/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6911
mode_lib->ms.WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6917
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6918
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6919
(mode_lib->ms.WriteBandwidth[k] > mode_lib->ms.ip.writeback_interface_buffer_size_kbytes * 1024 / mode_lib->ms.state.writeback_latency_us)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6926
for (k = 0; k <= (dml_uint_t) mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6927
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6939
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6940
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6941
if (mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > mode_lib->ms.ip.writeback_max_hscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6942
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > mode_lib->ms.ip.writeback_max_vscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6943
|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] < mode_lib->ms.ip.writeback_min_hscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6944
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] < mode_lib->ms.ip.writeback_min_vscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6945
|| mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_hscl_taps
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6946
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_vscl_taps
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6947
|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6948
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6949
|| (mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > 2.0 && ((mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6952
if (2.0 * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * (mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] - 1) * 57 > mode_lib->ms.ip.writeback_line_buffer_buffer_size) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6958
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6960
mode_lib->ms.cache_display_cfg.plane.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6961
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6962
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6963
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6966
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6967
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6968
mode_lib->ms.cache_display_cfg.plane.HTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6969
mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6970
mode_lib->ms.cache_display_cfg.plane.VTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6971
mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6973
&mode_lib->ms.PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6974
&mode_lib->ms.PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6975
&mode_lib->ms.MinDPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6978
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6979
if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6981
} else if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6983
} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6985
} else if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6987
} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelY[k] == 8 && mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6993
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_8 || mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_10 || mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_12) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6998
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = mode_lib->ms.ip.line_buffer_size_bits * dml_max(mode_lib->ms.cache_display_cfg.plane.HRatio[k], 1.0) / mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
6999
(mode_lib->ms.cache_display_cfg.plane.VTaps[k] + dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7000
if (mode_lib->ms.BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7005
* dml_max(mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7006
/ mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7007
/ (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7008
+ dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7010
mode_lib->ms.MaximumSwathWidthLuma[k] = dml_min(s->MaximumSwathWidthSupportLuma, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7011
mode_lib->ms.MaximumSwathWidthChroma[k] = dml_min(s->MaximumSwathWidthSupportChroma, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7015
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7016
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7017
mode_lib->ms.cache_display_cfg.output.DSCEnable[k] != dml_dsc_disable) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7018
mode_lib->ms.support.NumberOfDSCSlices[k] = mode_lib->ms.cache_display_cfg.output.DSCSlices[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7020
if (mode_lib->ms.support.NumberOfDSCSlices[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7021
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 4800) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7022
mode_lib->ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7023
} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 2400) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7024
mode_lib->ms.support.NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7025
} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 1200) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7026
mode_lib->ms.support.NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7027
} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7028
mode_lib->ms.support.NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7030
mode_lib->ms.support.NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7034
mode_lib->ms.support.NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7105
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7106
if (mode_lib->ms.policy.MPCCombineUse[k] == dml_mpc_as_needed_for_pstate_and_voltage)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7108
if (mode_lib->ms.policy.MPCCombineUse[k] == dml_mpc_as_possible)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7117
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7120
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7121
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7122
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7123
mode_lib->ms.policy.ODMUse[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7129
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7133
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7143
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7144
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7145
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7146
mode_lib->ms.policy.ODMUse[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7152
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7156
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7169
(mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7170
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7171
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7172
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7173
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7174
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7175
mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7176
mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7177
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7178
mode_lib->ms.cache_display_cfg.output.AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7179
mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7182
mode_lib->ms.cache_display_cfg.output.DSCEnable[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7183
mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7184
mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7187
&mode_lib->ms.RequiresDSC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7188
&mode_lib->ms.RequiresFEC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7189
&mode_lib->ms.OutputBppPerState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7190
&mode_lib->ms.OutputTypePerState[k], // VBA_DELTA, VBA uses a string to represent type and rate, but DML uses enum, don't want to rely on strng
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7191
&mode_lib->ms.OutputRatePerState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7192
&mode_lib->ms.RequiredSlots[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7194
if (mode_lib->ms.RequiresDSC[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7195
mode_lib->ms.ODMModePerState[k] = s->ODMModeNoDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7196
mode_lib->ms.RequiredDISPCLKPerSurface[j][k] = s->RequiredDISPCLKPerSurfaceNoDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7201
mode_lib->ms.ODMModePerState[k] = s->ODMModeDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7202
mode_lib->ms.RequiredDISPCLKPerSurface[j][k] = s->RequiredDISPCLKPerSurfaceDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7209
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7210
if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7211
mode_lib->ms.MPCCombine[j][k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7212
mode_lib->ms.NoOfDPP[j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7213
} else if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7214
mode_lib->ms.MPCCombine[j][k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7215
mode_lib->ms.NoOfDPP[j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7216
} else if (mode_lib->ms.policy.MPCCombineUse[k] == dml_mpc_disabled) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7217
mode_lib->ms.MPCCombine[j][k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7218
mode_lib->ms.NoOfDPP[j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7219
} else if (RoundToDFSGranularity(mode_lib->ms.MinDPPCLKUsingSingleDPP[k] * (1 + mode_lib->ms.soc.dcn_downspread_percent / 100),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7221
mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7222
mode_lib->ms.MPCCombine[j][k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7223
mode_lib->ms.NoOfDPP[j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7225
mode_lib->ms.MPCCombine[j][k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7226
mode_lib->ms.NoOfDPP[j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7229
mode_lib->ms.MPCCombine[j][k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7230
mode_lib->ms.NoOfDPP[j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7237
for (k = 0; k < (dml_uint_t) mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7238
if (mode_lib->ms.NoOfDPP[j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7240
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_8
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7241
|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_10
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7242
|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_12
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7243
|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_rgbe_alpha
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7244
|| mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7255
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7256
if (mode_lib->ms.policy.MPCCombineUse[k] != dml_mpc_disabled && mode_lib->ms.policy.MPCCombineUse[k] != dml_mpc_as_needed_for_voltage &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7257
mode_lib->ms.ReadBandwidthLuma[k] + mode_lib->ms.ReadBandwidthChroma[k] > s->BWOfNonCombinedSurfaceOfMaximumBandwidth &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7258
(mode_lib->ms.ODMModePerState[k] != dml_odm_mode_combine_2to1 && mode_lib->ms.ODMModePerState[k] != dml_odm_mode_combine_4to1) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7259
mode_lib->ms.MPCCombine[j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7260
s->BWOfNonCombinedSurfaceOfMaximumBandwidth = mode_lib->ms.ReadBandwidthLuma[k] + mode_lib->ms.ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7261
s->NumberOfNonCombinedSurfaceOfMaximumBandwidth = k;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7273
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7274
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7276
CalculateWriteBackDISPCLK(mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7277
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7278
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7279
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7280
mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7281
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7282
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7283
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7284
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7291
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7292
mode_lib->ms.RequiredDISPCLK[j] = dml_max(mode_lib->ms.RequiredDISPCLK[j], mode_lib->ms.RequiredDISPCLKPerSurface[j][k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7295
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7296
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7308
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7309
mode_lib->ms.RequiredDPPCLKPerSurface[j][k] = mode_lib->ms.RequiredDPPCLKThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7325
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7326
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7328
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7330
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7332
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k || mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7345
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7346
if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7347
!(mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7348
|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7349
|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 8.0
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7350
|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] > (dml_uint_t) mode_lib->ms.ip.maximum_dsc_bits_per_component
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7357
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7358
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7359
s->TotalSlots = mode_lib->ms.RequiredSlots[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7361
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[j] == k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7364
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp && s->TotalSlots > 63)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7366
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 && s->TotalSlots > 64)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7371
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7372
if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7373
mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7374
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) && mode_lib->ms.OutputBppPerState[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7389
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7390
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7391
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7392
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_lib->ms.ip.ptoi_supported == true)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7395
if (mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] != 0)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7397
if ((mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable || mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary) && mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 && !mode_lib->ms.ip.dsc422_native_support)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7400
if (((mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr2 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr3) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7401
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_edp) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7402
((mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr10 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr13p5 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr20) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7403
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp2p0))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7406
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7407
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_na)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7409
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] == 0)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7412
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == j && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] == 0)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7417
if ((mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7418
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1 && mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7421
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1 && mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == j)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7425
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && (mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_split_1to2 ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7426
mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to2 || mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to4))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7429
if ((mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to2 && mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k] < 2) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7430
(mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to4 && mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k] < 4))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7436
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7437
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7438
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7440
mode_lib->ms.RequiresDSC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7441
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7442
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7443
mode_lib->ms.OutputBppPerState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7444
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7445
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7446
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7447
mode_lib->ms.cache_display_cfg.output.AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7448
mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k]) > mode_lib->ms.state.dtbclk_mhz) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7455
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7456
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1 && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7459
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1 && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7460
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7466
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7467
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7468
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7469
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7470
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7471
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7472
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7474
} else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_444) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7476
} else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7482
dml_print("DML::%s: k=%u, RequiresDSC = %u\n", __func__, k, mode_lib->ms.RequiresDSC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7484
if (mode_lib->ms.RequiresDSC[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7485
if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7486
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7488
dml_print("DML::%s: k=%u, PixelClockBackEnd = %f\n", __func__, k, mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7489
dml_print("DML::%s: k=%u, DSCCLKPerState = %f\n", __func__, k, mode_lib->ms.state.dscclk_mhz);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7490
dml_print("DML::%s: k=%u, DSCFormatFactor = %u\n", __func__, k, s->DSCFormatFactor);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7494
} else if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7495
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7499
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7516
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7517
if (mode_lib->ms.RequiresDSC[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7518
if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7519
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 4 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7522
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 16)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7524
} else if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7525
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 2 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7528
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 8)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7531
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7534
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 4)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7544
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7545
mode_lib->ms.DSCDelayPerState[k] = DSCDelayRequirement(mode_lib->ms.RequiresDSC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7546
mode_lib->ms.ODMModePerState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7547
mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7548
mode_lib->ms.OutputBppPerState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7549
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7550
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7551
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7552
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7553
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7554
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7555
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7558
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7561
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m && mode_lib->ms.RequiresDSC[m] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7562
mode_lib->ms.DSCDelayPerState[k] = mode_lib->ms.DSCDelayPerState[m];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7571
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7572
mode_lib->ms.RequiredDPPCLKThisState[k] = mode_lib->ms.RequiredDPPCLKPerSurface[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7573
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7574
mode_lib->ms.ODMModeThisState[k] = mode_lib->ms.ODMModePerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7642
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7643
mode_lib->ms.swath_width_luma_ub_all_states[j][k] = mode_lib->ms.swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7644
mode_lib->ms.swath_width_chroma_ub_all_states[j][k] = mode_lib->ms.swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7645
mode_lib->ms.SwathWidthYAllStates[j][k] = mode_lib->ms.SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7646
mode_lib->ms.SwathWidthCAllStates[j][k] = mode_lib->ms.SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7647
mode_lib->ms.SwathHeightYAllStates[j][k] = mode_lib->ms.SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7648
mode_lib->ms.SwathHeightCAllStates[j][k] = mode_lib->ms.SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7651
mode_lib->ms.DETBufferSizeInKByteAllStates[j][k] = mode_lib->ms.DETBufferSizeInKByteThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7652
mode_lib->ms.DETBufferSizeYAllStates[j][k] = mode_lib->ms.DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7653
mode_lib->ms.DETBufferSizeCAllStates[j][k] = mode_lib->ms.DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7657
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7658
mode_lib->ms.cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7695
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7696
mode_lib->ms.swath_width_luma_ub_this_state[k] = mode_lib->ms.swath_width_luma_ub_all_states[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7697
mode_lib->ms.swath_width_chroma_ub_this_state[k] = mode_lib->ms.swath_width_chroma_ub_all_states[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7698
mode_lib->ms.SwathWidthYThisState[k] = mode_lib->ms.SwathWidthYAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7699
mode_lib->ms.SwathWidthCThisState[k] = mode_lib->ms.SwathWidthCAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7700
mode_lib->ms.SwathHeightYThisState[k] = mode_lib->ms.SwathHeightYAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7701
mode_lib->ms.SwathHeightCThisState[k] = mode_lib->ms.SwathHeightCAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7702
mode_lib->ms.DETBufferSizeInKByteThisState[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7703
mode_lib->ms.DETBufferSizeYThisState[k] = mode_lib->ms.DETBufferSizeYAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7704
mode_lib->ms.DETBufferSizeCThisState[k] = mode_lib->ms.DETBufferSizeCAllStates[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7705
mode_lib->ms.RequiredDPPCLKThisState[k] = mode_lib->ms.RequiredDPPCLKPerSurface[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7706
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7710
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7711
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7712
mode_lib->ms.TotalNumberOfDCCActiveDPP[j] = mode_lib->ms.TotalNumberOfDCCActiveDPP[j] + mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7716
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7717
s->SurfParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7718
s->SurfParameters[k].DPPPerSurface = mode_lib->ms.NoOfDPP[j][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7719
s->SurfParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7720
s->SurfParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7721
s->SurfParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7722
s->SurfParameters[k].BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7723
s->SurfParameters[k].BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7724
s->SurfParameters[k].BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7725
s->SurfParameters[k].BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7726
s->SurfParameters[k].BlockWidthY = mode_lib->ms.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7727
s->SurfParameters[k].BlockHeightY = mode_lib->ms.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7728
s->SurfParameters[k].BlockWidthC = mode_lib->ms.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7729
s->SurfParameters[k].BlockHeightC = mode_lib->ms.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7730
s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7731
s->SurfParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7732
s->SurfParameters[k].DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7733
s->SurfParameters[k].SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7734
s->SurfParameters[k].SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7735
s->SurfParameters[k].BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7736
s->SurfParameters[k].BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7737
s->SurfParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ms.ip.ptoi_supported;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7738
s->SurfParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7739
s->SurfParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7740
s->SurfParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7741
s->SurfParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7742
s->SurfParameters[k].PitchY = mode_lib->ms.cache_display_cfg.surface.PitchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7743
s->SurfParameters[k].DCCMetaPitchY = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7744
s->SurfParameters[k].PitchC = mode_lib->ms.cache_display_cfg.surface.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7745
s->SurfParameters[k].DCCMetaPitchC = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7746
s->SurfParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7747
s->SurfParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7748
s->SurfParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7749
s->SurfParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7750
s->SurfParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7751
s->SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7752
s->SurfParameters[k].SwathHeightY = mode_lib->ms.SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7753
s->SurfParameters[k].SwathHeightC = mode_lib->ms.SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7761
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7762
mode_lib->ms.PrefetchLinesY[j][k] = mode_lib->ms.PrefetchLinesYThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7763
mode_lib->ms.PrefetchLinesC[j][k] = mode_lib->ms.PrefetchLinesCThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7764
mode_lib->ms.meta_row_bandwidth[j][k] = mode_lib->ms.meta_row_bandwidth_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7765
mode_lib->ms.dpte_row_bandwidth[j][k] = mode_lib->ms.dpte_row_bandwidth_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7766
mode_lib->ms.DPTEBytesPerRow[j][k] = mode_lib->ms.DPTEBytesPerRowThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7767
mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k] = mode_lib->ms.PDEAndMetaPTEBytesPerFrameThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7768
mode_lib->ms.MetaRowBytes[j][k] = mode_lib->ms.MetaRowBytesThisState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7769
mode_lib->ms.use_one_row_for_frame[j][k] = mode_lib->ms.use_one_row_for_frame_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7770
mode_lib->ms.use_one_row_for_frame_flip[j][k] = mode_lib->ms.use_one_row_for_frame_flip_this_state[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7775
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7776
if (mode_lib->ms.PTEBufferSizeNotExceededPerState[k] == false)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7779
dml_print("DML::%s: j=%u k=%u, PTEBufferSizeNotExceededPerState[%u] = %u\n", __func__, j, k, k, mode_lib->ms.PTEBufferSizeNotExceededPerState[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7787
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7788
if (mode_lib->ms.DCCMetaBufferSizeNotExceededPerState[k] == false)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7803
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7805
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7806
mode_lib->ms.swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7807
mode_lib->ms.swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7808
mode_lib->ms.SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7809
mode_lib->ms.SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7810
(dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7813
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7814
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7815
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7816
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7817
mode_lib->ms.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7818
mode_lib->ms.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7819
mode_lib->ms.DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7820
mode_lib->ms.DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7822
&mode_lib->ms.UrgentBurstFactorCursor[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7823
&mode_lib->ms.UrgentBurstFactorLuma[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7824
&mode_lib->ms.UrgentBurstFactorChroma[j][k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7825
&mode_lib->ms.NotUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7853
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7854
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7855
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7856
mode_lib->ms.WritebackDelayTime[k] = mode_lib->ms.state.writeback_latency_us + CalculateWriteBackDelay(
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7857
mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7858
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7859
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7860
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7861
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7862
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7863
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7864
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / mode_lib->ms.RequiredDISPCLK[j];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7866
mode_lib->ms.WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7869
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[m] == k && mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7870
mode_lib->ms.WritebackDelayTime[k] = dml_max(mode_lib->ms.WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7884
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7886
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7887
mode_lib->ms.WritebackDelayTime[k] = mode_lib->ms.WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7893
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7894
s->MaximumVStartup[j][k] = CalculateMaxVStartup(k,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7898
mode_lib->ms.WritebackDelayTime[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7900
s->MaxVStartupAllPlanes[j] = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes[j], s->MaximumVStartup[j][k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7902
dml_print("DML::%s: k=%u, MaxVStartupAllPlanes[%u] = %u\n", __func__, k, j, s->MaxVStartupAllPlanes[j]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7903
dml_print("DML::%s: k=%u, MaximumVStartup[%u][%u] = %u\n", __func__, k, j, k, s->MaximumVStartup[j][k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7918
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7919
s->ImmediateFlipRequiredFinal = s->ImmediateFlipRequiredFinal || (mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7923
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7925
((mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_required) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7926
(mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7931
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7933
mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == true || mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7934
(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame || mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7938
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7940
((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)) ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7941
((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_disable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7948
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7949
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7951
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7953
if (mode_lib->ms.cache_display_cfg.timing.RefreshRate[k] > 120)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
7956
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8045
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8046
s->MaxTotalVActiveRDBandwidth = s->MaxTotalVActiveRDBandwidth + mode_lib->ms.ReadBandwidthLuma[k] + mode_lib->ms.ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8071
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8072
if (mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8073
if (mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] == 64 && mode_lib->ms.ip.cursor_64bpp_support == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8081
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8082
mode_lib->ms.support.AlignedYPitch[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8083
dml_max(mode_lib->ms.cache_display_cfg.surface.PitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8084
mode_lib->ms.MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8085
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8086
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8088
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8090
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8091
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8092
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8093
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8094
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8095
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8096
mode_lib->ms.support.AlignedCPitch[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.PitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), mode_lib->ms.MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8097
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8098
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8100
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8103
mode_lib->ms.support.AlignedCPitch[k] = mode_lib->ms.cache_display_cfg.surface.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8104
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8106
if (mode_lib->ms.support.AlignedYPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchY[k] || mode_lib->ms.support.AlignedCPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchC[k] ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8107
mode_lib->ms.support.AlignedDCCMetaPitchY[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k] || mode_lib->ms.support.AlignedDCCMetaPitchC[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8113
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8114
if (mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8116
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32 &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8117
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_8 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8118
if (mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8235
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8236
mode_lib->ms.support.MPCCombineEnable[k] = mode_lib->ms.MPCCombine[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8237
mode_lib->ms.support.DPPPerSurface[k] = mode_lib->ms.NoOfDPP[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8238
mode_lib->ms.SwathHeightY[k] = mode_lib->ms.SwathHeightYAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8239
mode_lib->ms.SwathHeightC[k] = mode_lib->ms.SwathHeightCAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8240
mode_lib->ms.DETBufferSizeInKByte[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8241
mode_lib->ms.DETBufferSizeY[k] = mode_lib->ms.DETBufferSizeYAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8242
mode_lib->ms.DETBufferSizeC[k] = mode_lib->ms.DETBufferSizeCAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8252
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8253
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8254
mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMModePerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8256
mode_lib->ms.support.ODMMode[k] = dml_odm_mode_bypass;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8259
mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8260
mode_lib->ms.support.FECEnabled[k] = mode_lib->ms.RequiresFEC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8261
mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBppPerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8262
mode_lib->ms.support.OutputType[k] = mode_lib->ms.OutputTypePerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8263
mode_lib->ms.support.OutputRate[k] = mode_lib->ms.OutputRatePerState[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8264
mode_lib->ms.support.SubViewportLinesNeededInMALL[k] = mode_lib->ms.SubViewportLinesNeededInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8310
dml_uint_t j = 0, k = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8348
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8349
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8354
mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8355
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8356
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8357
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8358
mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8359
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8360
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8361
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8362
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8370
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8371
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8373
mode_lib->ms.cache_display_cfg.hw.ODMMode[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8374
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8391
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8393
mode_lib->ms.cache_display_cfg.plane.HRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8394
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8395
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8396
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8399
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8400
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8401
mode_lib->ms.cache_display_cfg.plane.HTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8402
mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8403
mode_lib->ms.cache_display_cfg.plane.VTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8404
mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8407
&locals->PSCL_THROUGHPUT[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8408
&locals->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8409
&locals->DPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8421
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8422
if (clk_cfg->dppclk_option[k] == dml_use_required_freq)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8423
locals->Dppclk[k] = locals->Dppclk_calculated[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8424
else if (clk_cfg->dppclk_option[k] == dml_use_override_freq)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8425
locals->Dppclk[k] = clk_cfg->dppclk_mhz[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8427
locals->Dppclk[k] = mode_lib->ms.state.dppclk_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8429
dml_print("DML::%s: Using Dppclk[%0d] = %f\n", __func__, k, locals->Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8433
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8435
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8436
mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8439
&locals->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8440
&locals->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8441
&locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8442
&locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8443
&locals->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8444
&locals->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8445
&locals->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8446
&locals->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8447
&locals->BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8448
&locals->BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8449
&locals->BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8450
&locals->BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8493
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8494
locals->ReadBandwidthSurfaceLuma[k] = locals->SwathWidthSingleDPPY[k] * locals->BytePerPixelY[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8495
locals->ReadBandwidthSurfaceChroma[k] = locals->SwathWidthSingleDPPC[k] * locals->BytePerPixelC[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8496
dml_print("DML::%s: ReadBandwidthSurfaceLuma[%i] = %fBps\n", __func__, k, locals->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8497
dml_print("DML::%s: ReadBandwidthSurfaceChroma[%i] = %fBps\n", __func__, k, locals->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8591
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8592
if ((mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] != k) || !mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8593
locals->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8595
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8597
else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_444)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8599
else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8603
if (mode_lib->ms.cache_display_cfg.hw.ODMMode[k] == dml_odm_mode_combine_4to1)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8604
locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8605
else if (mode_lib->ms.cache_display_cfg.hw.ODMMode[k] == dml_odm_mode_combine_2to1)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8606
locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8608
locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8613
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8614
locals->DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8615
mode_lib->ms.cache_display_cfg.hw.ODMMode[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8616
mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8617
mode_lib->ms.cache_display_cfg.output.OutputBpp[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8618
mode_lib->ms.cache_display_cfg.timing.HActive[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8619
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8620
mode_lib->ms.cache_display_cfg.hw.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8621
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8622
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8623
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8624
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8627
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8629
if (j != k && mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j && mode_lib->ms.cache_display_cfg.hw.DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8630
locals->DSCDelay[k] = locals->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8666
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8667
s->SurfaceParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8668
s->SurfaceParameters[k].DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8669
s->SurfaceParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8670
s->SurfaceParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8671
s->SurfaceParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8672
s->SurfaceParameters[k].BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8673
s->SurfaceParameters[k].BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8674
s->SurfaceParameters[k].BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8675
s->SurfaceParameters[k].BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8676
s->SurfaceParameters[k].BlockWidthY = locals->BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8677
s->SurfaceParameters[k].BlockHeightY = locals->BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8678
s->SurfaceParameters[k].BlockWidthC = locals->BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8679
s->SurfaceParameters[k].BlockHeightC = locals->BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8680
s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8681
s->SurfaceParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8682
s->SurfaceParameters[k].DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8683
s->SurfaceParameters[k].SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8684
s->SurfaceParameters[k].SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8685
s->SurfaceParameters[k].BytePerPixelY = locals->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8686
s->SurfaceParameters[k].BytePerPixelC = locals->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8687
s->SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ms.ip.ptoi_supported;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8688
s->SurfaceParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8689
s->SurfaceParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8690
s->SurfaceParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8691
s->SurfaceParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8692
s->SurfaceParameters[k].PitchY = mode_lib->ms.cache_display_cfg.surface.PitchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8693
s->SurfaceParameters[k].DCCMetaPitchY = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8694
s->SurfaceParameters[k].PitchC = mode_lib->ms.cache_display_cfg.surface.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8695
s->SurfaceParameters[k].DCCMetaPitchC = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8696
s->SurfaceParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8697
s->SurfaceParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8698
s->SurfaceParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8699
s->SurfaceParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8700
s->SurfaceParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8701
s->SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8702
s->SurfaceParameters[k].SwathHeightY = locals->SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8703
s->SurfaceParameters[k].SwathHeightC = locals->SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8807
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8808
s->TotalActiveDPP = s->TotalActiveDPP + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8809
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8810
s->TotalDCCActiveDPP = s->TotalDCCActiveDPP + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8833
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8834
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8835
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8836
locals->WritebackDelay[k] =
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8839
mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8840
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8841
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8842
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8843
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8844
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8845
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8846
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8848
locals->WritebackDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8850
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[j] == k
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8852
locals->WritebackDelay[k] =
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8854
locals->WritebackDelay[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8864
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8870
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8872
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8873
locals->WritebackDelay[k] = locals->WritebackDelay[j];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8883
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8884
CalculateUrgentBurstFactor(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8885
locals->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8886
locals->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8887
locals->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8888
locals->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8889
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8892
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8893
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8894
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8895
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8896
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8897
locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8898
locals->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8899
locals->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8902
&locals->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8903
&locals->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8904
&locals->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8905
&locals->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8907
locals->cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8908
((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8914
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8915
s->MaxVStartupLines[k] = CalculateMaxVStartup(k,
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8919
locals->WritebackDelay[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8922
dml_print("DML::%s: k=%u MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8923
dml_print("DML::%s: k=%u WritebackDelay = %f\n", __func__, k, locals->WritebackDelay[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8927
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8928
s->MaxVStartupAllPlanes = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes, s->MaxVStartupLines[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8931
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8932
s->ImmediateFlipRequirementFinal = s->ImmediateFlipRequirementFinal || (mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8944
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8945
CalculatePrefetchMode(mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k], &s->MinPrefetchMode[k], &s->MaxPrefetchMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8946
s->NextPrefetchMode[k] = s->MinPrefetchMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8958
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8959
locals->PrefetchMode[k] = s->NextPrefetchMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8961
locals->PrefetchMode[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8962
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8964
mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8971
myPipe->Dppclk = locals->Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8973
myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8975
myPipe->DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8976
myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8977
myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8978
myPipe->BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8979
myPipe->BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8980
myPipe->BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8981
myPipe->BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8982
myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8983
myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8984
myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8985
myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8986
myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8987
myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8988
myPipe->ODMMode = mode_lib->ms.cache_display_cfg.hw.ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8989
myPipe->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8990
myPipe->BytePerPixelY = locals->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8991
myPipe->BytePerPixelC = locals->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8995
dml_print("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8996
dml_print("DML::%s: AllowForPStateChangeOrStutterInVBlank = %u\n", __func__, mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
8997
dml_print("DML::%s: PrefetchMode[k] = %u (Min=%u Max=%u)\n", __func__, locals->PrefetchMode[k], s->MinPrefetchMode[k], s->MaxPrefetchMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9003
CalculatePrefetchSchedule_params->DSCDelay = locals->DSCDelay[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9009
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(locals->SwathWidthY[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9010
CalculatePrefetchSchedule_params->OutputFormat = mode_lib->ms.cache_display_cfg.output.OutputFormat[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9012
CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9013
CalculatePrefetchSchedule_params->MaxVStartup = s->MaxVStartupLines[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9019
CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9021
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9022
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9026
CalculatePrefetchSchedule_params->PDEAndMetaPTEBytesFrame = locals->PDEAndMetaPTEBytesFrame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9027
CalculatePrefetchSchedule_params->MetaRowByte = locals->MetaRowByte[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9028
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = locals->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9029
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = locals->PrefetchSourceLinesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9030
CalculatePrefetchSchedule_params->VInitPreFillY = locals->VInitPreFillY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9031
CalculatePrefetchSchedule_params->MaxNumSwathY = locals->MaxNumSwathY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9032
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = locals->PrefetchSourceLinesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9033
CalculatePrefetchSchedule_params->VInitPreFillC = locals->VInitPreFillC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9034
CalculatePrefetchSchedule_params->MaxNumSwathC = locals->MaxNumSwathC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9035
CalculatePrefetchSchedule_params->swath_width_luma_ub = locals->swath_width_luma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9036
CalculatePrefetchSchedule_params->swath_width_chroma_ub = locals->swath_width_chroma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9037
CalculatePrefetchSchedule_params->SwathHeightY = locals->SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9038
CalculatePrefetchSchedule_params->SwathHeightC = locals->SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9040
CalculatePrefetchSchedule_params->DSTXAfterScaler = &locals->DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9041
CalculatePrefetchSchedule_params->DSTYAfterScaler = &locals->DSTYAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9042
CalculatePrefetchSchedule_params->DestinationLinesForPrefetch = &locals->DestinationLinesForPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9043
CalculatePrefetchSchedule_params->DestinationLinesToRequestVMInVBlank = &locals->DestinationLinesToRequestVMInVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9044
CalculatePrefetchSchedule_params->DestinationLinesToRequestRowInVBlank = &locals->DestinationLinesToRequestRowInVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9045
CalculatePrefetchSchedule_params->VRatioPrefetchY = &locals->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9046
CalculatePrefetchSchedule_params->VRatioPrefetchC = &locals->VRatioPrefetchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9047
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWLuma = &locals->RequiredPrefetchPixDataBWLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9048
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWChroma = &locals->RequiredPrefetchPixDataBWChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9049
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &locals->NotEnoughTimeForDynamicMetadata[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9050
CalculatePrefetchSchedule_params->Tno_bw = &locals->Tno_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9051
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &locals->prefetch_vmrow_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9052
CalculatePrefetchSchedule_params->Tdmdl_vm = &locals->Tdmdl_vm[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9053
CalculatePrefetchSchedule_params->Tdmdl = &locals->Tdmdl[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9054
CalculatePrefetchSchedule_params->TSetup = &locals->TSetup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9055
CalculatePrefetchSchedule_params->VUpdateOffsetPix = &locals->VUpdateOffsetPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9056
CalculatePrefetchSchedule_params->VUpdateWidthPix = &locals->VUpdateWidthPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9057
CalculatePrefetchSchedule_params->VReadyOffsetPix = &locals->VReadyOffsetPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9059
locals->NoTimeToPrefetch[k] =
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9064
dml_print("DML::%s: k=%0u NoTimeToPrefetch=%0d\n", __func__, k, locals->NoTimeToPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9066
locals->VStartup[k] = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9067
locals->VStartupMin[k] = locals->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9070
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9072
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9073
locals->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9074
locals->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9075
locals->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9076
locals->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9077
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9080
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9081
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9082
locals->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9083
locals->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9084
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9085
locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9086
locals->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9087
locals->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9089
&locals->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9090
&locals->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9091
&locals->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9092
&locals->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9094
locals->cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * locals->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9097
dml_print("DML::%s: k=%0u DPPPerSurface=%u\n", __func__, k, mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9098
dml_print("DML::%s: k=%0u UrgBurstFactorLuma=%f\n", __func__, k, locals->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9099
dml_print("DML::%s: k=%0u UrgBurstFactorChroma=%f\n", __func__, k, locals->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9100
dml_print("DML::%s: k=%0u UrgBurstFactorLumaPre=%f\n", __func__, k, locals->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9101
dml_print("DML::%s: k=%0u UrgBurstFactorChromaPre=%f\n", __func__, k, locals->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9103
dml_print("DML::%s: k=%0u VRatioPrefetchY=%f\n", __func__, k, locals->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9104
dml_print("DML::%s: k=%0u VRatioY=%f\n", __func__, k, mode_lib->ms.cache_display_cfg.plane.VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9106
dml_print("DML::%s: k=%0u prefetch_vmrow_bw=%f\n", __func__, k, locals->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9107
dml_print("DML::%s: k=%0u ReadBandwidthSurfaceLuma=%f\n", __func__, k, locals->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9108
dml_print("DML::%s: k=%0u ReadBandwidthSurfaceChroma=%f\n", __func__, k, locals->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9109
dml_print("DML::%s: k=%0u cursor_bw=%f\n", __func__, k, locals->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9110
dml_print("DML::%s: k=%0u meta_row_bw=%f\n", __func__, k, locals->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9111
dml_print("DML::%s: k=%0u dpte_row_bw=%f\n", __func__, k, locals->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9112
dml_print("DML::%s: k=%0u RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, locals->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9113
dml_print("DML::%s: k=%0u RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, locals->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9114
dml_print("DML::%s: k=%0u cursor_bw_pre=%f\n", __func__, k, locals->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9115
dml_print("DML::%s: k=%0u MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, s->MaxTotalRDBandwidthNoUrgentBurst);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9117
if (locals->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9120
if (locals->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9121
locals->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9122
((s->VStartupLines < s->MaxVStartupLines[k] || mode_lib->ms.policy.EnhancedPrefetchScheduleAccelerationFinal == 0) &&
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9123
(locals->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE__ || locals->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE__)))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9173
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9174
s->dummy_unit_vector[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9211
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9212
if (locals->NoTimeToPrefetch[k] == true || locals->NotEnoughTimeForDynamicMetadata[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9213
dml_print("DML::%s: k=%u, NoTimeToPrefetch = %0d\n", __func__, k, locals->NoTimeToPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9214
dml_print("DML::%s: k=%u, NotEnoughTimeForDynamicMetadata=%u\n", __func__, k, locals->NotEnoughTimeForDynamicMetadata[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9239
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9240
if (mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9241
locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * (locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9242
if (locals->use_one_row_for_frame_flip[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9243
locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * (2 * locals->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9245
locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * locals->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9248
dml_print("DML::%s: k = %u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9249
dml_print("DML::%s: DPPPerSurface = %u\n", __func__, mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9250
dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %u\n", __func__, locals->PDEAndMetaPTEBytesFrame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9251
dml_print("DML::%s: MetaRowByte = %u\n", __func__, locals->MetaRowByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9252
dml_print("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, locals->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9257
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9267
locals->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9268
locals->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9269
locals->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9272
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9273
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9274
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9275
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9276
locals->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9277
mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9278
locals->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9279
locals->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9280
locals->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9281
locals->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9282
locals->use_one_row_for_frame_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9285
&locals->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9286
&locals->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9287
&locals->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9288
&locals->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9347
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9348
if (mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required && locals->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9351
dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9370
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9371
dml_print("DML::%s: ImmediateFlipRequirement[%u] = %u\n", __func__, k, mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9384
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9385
s->NextPrefetchMode[k] = s->NextPrefetchMode[k] + 1;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9387
if (s->NextPrefetchMode[k] <= s->MaxPrefetchMode[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9491
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9492
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9493
locals->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9494
mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9495
locals->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9496
mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackFCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9498
locals->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9499
locals->WritebackAllowFCLKChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9621
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9622
if (locals->PrefetchMode[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9623
locals->MinTTUVBlank[k] = dml_max4(
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9628
} else if (locals->PrefetchMode[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9629
locals->MinTTUVBlank[k] = dml_max3(
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9633
} else if (locals->PrefetchMode[k] == 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9634
locals->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9638
locals->MinTTUVBlank[k] = locals->Watermark.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9640
if (!mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9641
locals->MinTTUVBlank[k] = locals->TCalc + locals->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9645
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9647
dml_print("DML::%s: Calculate DCC configuration for surface k=%u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9650
mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9652
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9653
mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9654
mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9655
mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9656
mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9658
locals->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9659
locals->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9660
mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9661
locals->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9662
locals->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9663
locals->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9664
locals->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9665
mode_lib->ms.cache_display_cfg.plane.SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9667
&locals->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9668
&locals->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9669
&locals->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9670
&locals->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9671
&locals->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9672
&locals->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9676
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9677
s->Tvstartup_margin = (s->MaxVStartupLines[k] - locals->VStartupMin[k]) * mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9679
dml_print("DML::%s: k=%u, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k, locals->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9682
locals->MinTTUVBlank[k] = locals->MinTTUVBlank[k] + s->Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9685
dml_print("DML::%s: k=%u, Tvstartup_margin = %f\n", __func__, k, s->Tvstartup_margin);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9686
dml_print("DML::%s: k=%u, MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9687
dml_print("DML::%s: k=%u, MinTTUVBlank = %f\n", __func__, k, locals->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9690
locals->Tdmdl[k] = locals->Tdmdl[k] + s->Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9691
if (mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k] && mode_lib->ms.ip.dynamic_metadata_vm_enabled) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9692
locals->Tdmdl_vm[k] = locals->Tdmdl_vm[k] + s->Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9695
isInterlaceTiming = (mode_lib->ms.cache_display_cfg.timing.Interlace[k] && !mode_lib->ms.ip.ptoi_supported);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9698
locals->VStartup[k] = (isInterlaceTiming ? (2 * s->MaxVStartupLines[k]) : s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9700
s->dlg_vblank_start = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9701
mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9702
s->LSetup = dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9703
s->blank_lines_remaining = (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k]) - locals->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9710
locals->MIN_DST_Y_NEXT_START[k] = s->dlg_vblank_start + s->blank_lines_remaining + s->LSetup;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9713
s->old_MIN_DST_Y_NEXT_START = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9714
mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k])
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9715
+ dml_max(1.0, dml_ceil((dml_float_t) locals->WritebackDelay[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0))
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9716
+ dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9718
if (((locals->VUpdateOffsetPix[k] + locals->VUpdateWidthPix[k] + locals->VReadyOffsetPix[k]) / (double) mode_lib->ms.cache_display_cfg.timing.HTotal[k]) <=
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9720
dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9721
(int) (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9722
locals->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9724
locals->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9727
dml_print("DML::%s: k=%u, VStartup = %u (max)\n", __func__, k, locals->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9728
dml_print("DML::%s: k=%u, VStartupMin = %u (max)\n", __func__, k, locals->VStartupMin[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9729
dml_print("DML::%s: k=%u, VUpdateOffsetPix = %u\n", __func__, k, locals->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9730
dml_print("DML::%s: k=%u, VUpdateWidthPix = %u\n", __func__, k, locals->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9731
dml_print("DML::%s: k=%u, VReadyOffsetPix = %u\n", __func__, k, locals->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9732
dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9733
dml_print("DML::%s: k=%u, VTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9734
dml_print("DML::%s: k=%u, VActive = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VActive[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9735
dml_print("DML::%s: k=%u, VFrontPorch = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9736
dml_print("DML::%s: k=%u, TSetup = %f\n", __func__, k, locals->TSetup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9737
dml_print("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f\n", __func__, k, locals->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9738
dml_print("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f (old)\n", __func__, k, s->old_MIN_DST_Y_NEXT_START);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9739
dml_print("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, locals->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9746
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9747
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true && mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_32) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9748
s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9749
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9750
} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9751
s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9752
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9758
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9759
locals->TotalDataReadBandwidth = locals->TotalDataReadBandwidth + locals->ReadBandwidthSurfaceLuma[k] + locals->ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9762
dml_print("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, locals->TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9763
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, locals->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9764
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, locals->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9769
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9770
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
9772
+ locals->ReadBandwidthSurfaceLuma[k] + locals->ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
732
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
733
if (display_cfg->plane.ViewportWidth[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
786
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
787
pipe_plane[k] = __DML_PIPE_NO_PLANE__;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
381
int i, j, k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
441
for (k = 0; k < dc->res_pool->pipe_count; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
442
if (context->res_ctx.pipe_ctx[k].stream &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
443
context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
444
context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
445
static_base_state->stream_v1.base.pipe_mask |= (1 << k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
446
static_base_state->stream_v1.base.plane_pipe_masks[j] |= (1 << k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
478
for (k = 0; k < dc->res_pool->pipe_count; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
479
if (context->res_ctx.pipe_ctx[k].stream &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
480
context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
481
context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
485
static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
486
static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 << k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10003
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10004
num_group_per_lower_vm_stage += (unsigned int)(2.0 /*for each mpde0 group*/ + math_ceil2((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) +
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10005
math_ceil2((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10007
num_group_per_lower_vm_stage += (unsigned int)(1.0 + math_ceil2((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10014
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut && display_cfg->gpuvm_enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10015
num_group_per_lower_vm_stage_pref += (unsigned int) math_ceil2(tdlut_pte_bytes_per_frame[k] / vm_group_bytes[k], 1);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10021
num_req_per_lower_vm_stage += dpde0_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10022
if (BytePerPixelC[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10023
num_req_per_lower_vm_stage += dpde0_bytes_per_frame_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10027
num_req_per_lower_vm_stage += meta_pte_bytes_per_frame_ub_l[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10028
if (BytePerPixelC[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10029
num_req_per_lower_vm_stage += meta_pte_bytes_per_frame_ub_c[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10035
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut && display_cfg->gpuvm_enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10036
num_req_per_lower_vm_stage_pref += tdlut_pte_bytes_per_frame[k] / 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10039
line_time = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10042
TimePerVMGroupVBlank[k] = dst_y_per_vm_vblank[k] * line_time / num_group_per_lower_vm_stage_pref;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10044
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10047
TimePerVMGroupFlip[k] = dst_y_per_vm_flip[k] * line_time / num_group_per_lower_vm_stage_flip;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10049
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10052
TimePerVMRequestVBlank[k] = dst_y_per_vm_vblank[k] * line_time / num_req_per_lower_vm_stage_pref;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10054
TimePerVMRequestVBlank[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10056
TimePerVMRequestFlip[k] = dst_y_per_vm_flip[k] * line_time / num_req_per_lower_vm_stage_flip;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10058
TimePerVMRequestFlip[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10060
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_vm_vblank = %f\n", __func__, k, dst_y_per_vm_vblank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10061
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_vm_flip = %f\n", __func__, k, dst_y_per_vm_flip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10062
DML_LOG_VERBOSE("DML::%s: k=%u, line_time = %f\n", __func__, k, line_time);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10063
DML_LOG_VERBOSE("DML::%s: k=%u, num_group_per_lower_vm_stage_pref = %d\n", __func__, k, num_group_per_lower_vm_stage_pref);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10064
DML_LOG_VERBOSE("DML::%s: k=%u, num_group_per_lower_vm_stage_flip = %d\n", __func__, k, num_group_per_lower_vm_stage_flip);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10065
DML_LOG_VERBOSE("DML::%s: k=%u, num_req_per_lower_vm_stage_pref = %d\n", __func__, k, num_req_per_lower_vm_stage_pref);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10066
DML_LOG_VERBOSE("DML::%s: k=%u, num_req_per_lower_vm_stage_flip = %d\n", __func__, k, num_req_per_lower_vm_stage_flip);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10069
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10070
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10071
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10072
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10076
TimePerVMGroupVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10077
TimePerVMGroupFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10078
TimePerVMRequestVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10079
TimePerVMRequestFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10083
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10084
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10085
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10086
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10105
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10106
if (!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10107
if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10108
if ((dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockWidth256BytesY[k] > p->SwathHeightY[k]) || (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockHeight256BytesY[k] > p->SwathHeightY[k]) || p->DCCYMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10113
l->TotalCompressedReadBandwidth = l->TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] / math_min2(p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane0, l->MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10115
DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10116
DML_LOG_VERBOSE("DML::%s: k=%u, NetDCCRateLuma = %f\n", __func__, k, p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10117
DML_LOG_VERBOSE("DML::%s: k=%u, MaximumEffectiveCompressionLuma = %f\n", __func__, k, l->MaximumEffectiveCompressionLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10119
l->TotalZeroSizeRequestReadBandwidth = l->TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10120
l->TotalZeroSizeCompressedReadBandwidth = l->TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane0 / l->MaximumEffectiveCompressionLuma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10122
if (p->ReadBandwidthSurfaceChroma[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10123
if ((dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockWidth256BytesC[k] > p->SwathHeightC[k]) || (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockHeight256BytesC[k] > p->SwathHeightC[k]) || p->DCCCMaxUncompressedBlock[k] < 256) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10128
l->TotalCompressedReadBandwidth = l->TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] / math_min2(p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane1, l->MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10130
DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, p->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10131
DML_LOG_VERBOSE("DML::%s: k=%u, NetDCCRateChroma = %f\n", __func__, k, p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane1);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10132
DML_LOG_VERBOSE("DML::%s: k=%u, MaximumEffectiveCompressionChroma = %f\n", __func__, k, l->MaximumEffectiveCompressionChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10134
l->TotalZeroSizeRequestReadBandwidth = l->TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10135
l->TotalZeroSizeCompressedReadBandwidth = l->TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane1 / l->MaximumEffectiveCompressionChroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10138
l->TotalCompressedReadBandwidth = l->TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] + p->ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10140
l->TotalRowReadBandwidth = l->TotalRowReadBandwidth + p->DPPPerSurface[k] * (p->meta_row_bw[k] + p->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10202
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10203
if (!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10204
l->LinesInDETY = ((double)p->DETBufferSizeY[k] + (p->UnboundedRequestEnabled == true ? l->EffectiveCompressedBufferSize : 0) * p->ReadBandwidthSurfaceLuma[k] / p->TotalDataReadBandwidth) / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10205
l->LinesInDETYRoundedDownToSwath = math_floor2(l->LinesInDETY, p->SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10206
l->DETBufferingTimeY = l->LinesInDETYRoundedDownToSwath * ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10208
DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferSizeY = %u (%u kbytes)\n", __func__, k, p->DETBufferSizeY[k], p->DETBufferSizeY[k] / 1024);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10209
DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10210
DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10211
DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10212
DML_LOG_VERBOSE("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, p->TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10213
DML_LOG_VERBOSE("DML::%s: k=%u, LinesInDETY = %f\n", __func__, k, l->LinesInDETY);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10214
DML_LOG_VERBOSE("DML::%s: k=%u, LinesInDETYRoundedDownToSwath = %f\n", __func__, k, l->LinesInDETYRoundedDownToSwath);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10215
DML_LOG_VERBOSE("DML::%s: k=%u, VRatio = %f\n", __func__, k, p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10216
DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferingTimeY = %f\n", __func__, k, l->DETBufferingTimeY);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10220
bool isInterlaceTiming = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !p->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10224
l->FrameTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10225
l->VActiveTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10226
l->BytePerPixelYCriticalSurface = p->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10227
l->SwathWidthYCriticalSurface = p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10228
l->SwathHeightYCriticalSurface = p->SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10229
l->BlockWidth256BytesYCriticalSurface = p->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10230
l->DETBufferSizeYCriticalSurface = p->DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10231
l->MinTTUVBlankCriticalSurface = p->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10232
l->SinglePlaneCriticalSurface = (p->ReadBandwidthSurfaceChroma[k] == 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10233
l->SinglePipeCriticalSurface = (p->DPPPerSurface[k] == 1);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10236
DML_LOG_VERBOSE("DML::%s: k=%u, FoundCriticalSurface = %u\n", __func__, k, FoundCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10237
DML_LOG_VERBOSE("DML::%s: k=%u, StutterPeriod = %f\n", __func__, k, *p->StutterPeriod);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10238
DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlankCriticalSurface = %f\n", __func__, k, l->MinTTUVBlankCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10239
DML_LOG_VERBOSE("DML::%s: k=%u, FrameTimeCriticalSurface= %f\n", __func__, k, l->FrameTimeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10240
DML_LOG_VERBOSE("DML::%s: k=%u, VActiveTimeCriticalSurface = %f\n", __func__, k, l->VActiveTimeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10241
DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelYCriticalSurface = %u\n", __func__, k, l->BytePerPixelYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10242
DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthYCriticalSurface = %f\n", __func__, k, l->SwathWidthYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10243
DML_LOG_VERBOSE("DML::%s: k=%u, SwathHeightYCriticalSurface = %f\n", __func__, k, l->SwathHeightYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10244
DML_LOG_VERBOSE("DML::%s: k=%u, BlockWidth256BytesYCriticalSurface = %u\n", __func__, k, l->BlockWidth256BytesYCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10245
DML_LOG_VERBOSE("DML::%s: k=%u, SinglePlaneCriticalSurface = %u\n", __func__, k, l->SinglePlaneCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10246
DML_LOG_VERBOSE("DML::%s: k=%u, SinglePipeCriticalSurface = %u\n", __func__, k, l->SinglePipeCriticalSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10288
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10289
if (!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10290
if (!l->stream_visited[p->display_cfg->plane_descriptors[k].stream_index]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10292
if (p->display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10296
SinglePixelClock = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10297
SingleHTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10298
SingleVTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10299
} else if (SinglePixelClock != ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10300
SingleHTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10301
SingleVTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10305
l->stream_visited[p->display_cfg->plane_descriptors[k].stream_index] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10401
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10430
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10431
unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10442
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_4to1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10445
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_3to1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10448
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_2to1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10452
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10454
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10456
mode_lib->mp.ODMMode[k] = dml2_odm_mode_bypass;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10461
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10462
mode_lib->mp.NoOfDPP[k] = cfg_support_info->plane_support_info[k].dpps_used;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10463
mode_lib->mp.Dppclk[k] = programming->plane_programming[k].min_clocks.dcn4x.dppclk_khz / 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10464
DML_ASSERT(mode_lib->mp.Dppclk[k] > 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10467
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10468
unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10469
mode_lib->mp.DSCCLK[k] = programming->stream_programming[stream_index].min_clocks.dcn4x.dscclk_khz / 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10470
DML_LOG_VERBOSE("DML::%s: k=%d stream_index=%d, mode_lib->mp.DSCCLK = %f\n", __func__, k, stream_index, mode_lib->mp.DSCCLK[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10493
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10494
DML_LOG_VERBOSE("DML::%s: Dppclk[%0d] = %f\n", __func__, k, mode_lib->mp.Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10505
for (k = 0; k < mode_lib->mp.num_active_pipes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10506
DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10507
DML_LOG_VERBOSE("DML::%s: Per-plane DPPPerSurface[%0d] = %d\n", __func__, k, mode_lib->mp.NoOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10510
for (k = 0; k < s->num_active_planes; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10511
DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1052
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1053
DETBufferSizeInKByte[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10531
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10533
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10534
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10535
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10536
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10539
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1054
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10540
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10541
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10542
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10543
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10544
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10547
&mode_lib->mp.PSCL_THROUGHPUT[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10548
&mode_lib->mp.PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10549
&mode_lib->mp.DPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10552
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10554
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10555
display_cfg->plane_descriptors[k].surface.tiling,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10556
display_cfg->plane_descriptors[k].surface.plane0.pitch,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10557
display_cfg->plane_descriptors[k].surface.plane1.pitch,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10560
&mode_lib->mp.BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10561
&mode_lib->mp.BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10562
&mode_lib->mp.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10563
&mode_lib->mp.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10564
&mode_lib->mp.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10565
&mode_lib->mp.Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10566
&mode_lib->mp.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10567
&mode_lib->mp.Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10568
&mode_lib->mp.MacroTileHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10569
&mode_lib->mp.MacroTileHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10570
&mode_lib->mp.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10571
&mode_lib->mp.MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10572
&mode_lib->mp.surf_linear128_l[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10573
&mode_lib->mp.surf_linear128_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10603
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10604
mode_lib->mp.cursor_bw[k] = display_cfg->plane_descriptors[k].cursor.num_cursors * display_cfg->plane_descriptors[k].cursor.cursor_width * display_cfg->plane_descriptors[k].cursor.cursor_bpp / 8.0 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10605
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10606
mode_lib->mp.vactive_sw_bw_l[k] = mode_lib->mp.SwathWidthSingleDPPY[k] * mode_lib->mp.BytePerPixelY[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10607
mode_lib->mp.vactive_sw_bw_c[k] = mode_lib->mp.SwathWidthSingleDPPC[k] * mode_lib->mp.BytePerPixelC[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10608
DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_l[%i] = %fBps\n", __func__, k, mode_lib->mp.vactive_sw_bw_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10609
DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_c[%i] = %fBps\n", __func__, k, mode_lib->mp.vactive_sw_bw_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1064
if (2.0 * ((double)full_swath_bytes_l[k] + (double)full_swath_bytes_c[k]) / 1024.0 <= l->minDET)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10670
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10671
mode_lib->mp.DSCDelay[k] = DSCDelayRequirement(cfg_support_info->stream_support_info[display_cfg->plane_descriptors[k].stream_index].dsc_enable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10672
mode_lib->mp.ODMMode[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10674
s->OutputBpp[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10675
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10676
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10677
cfg_support_info->stream_support_info[display_cfg->plane_descriptors[k].stream_index].num_dsc_slices,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10678
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10679
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10680
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10681
s->PixelClockBackEnd[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10686
for (k = 0; k < s->num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10687
mode_lib->mp.SurfaceSizeInTheMALL[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1069
DML_LOG_VERBOSE("DML::%s: k=%u minDET = %u\n", __func__, k, l->minDET);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1070
DML_LOG_VERBOSE("DML::%s: k=%u max_minDET = %u\n", __func__, k, l->max_minDET);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10709
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1071
DML_LOG_VERBOSE("DML::%s: k=%u minDET_pipe = %u\n", __func__, k, l->minDET_pipe);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10710
s->SurfaceParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10711
s->SurfaceParameters[k].DPPPerSurface = mode_lib->mp.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10712
s->SurfaceParameters[k].RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10713
s->SurfaceParameters[k].ViewportHeight = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10714
s->SurfaceParameters[k].ViewportHeightC = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10715
s->SurfaceParameters[k].BlockWidth256BytesY = mode_lib->mp.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10716
s->SurfaceParameters[k].BlockHeight256BytesY = mode_lib->mp.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10717
s->SurfaceParameters[k].BlockWidth256BytesC = mode_lib->mp.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10718
s->SurfaceParameters[k].BlockHeight256BytesC = mode_lib->mp.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10719
s->SurfaceParameters[k].BlockWidthY = mode_lib->mp.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1072
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, full_swath_bytes_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10720
s->SurfaceParameters[k].BlockHeightY = mode_lib->mp.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10721
s->SurfaceParameters[k].BlockWidthC = mode_lib->mp.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10722
s->SurfaceParameters[k].BlockHeightC = mode_lib->mp.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10723
s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10724
s->SurfaceParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10725
s->SurfaceParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10726
s->SurfaceParameters[k].SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10727
s->SurfaceParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10728
s->SurfaceParameters[k].BytePerPixelY = mode_lib->mp.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10729
s->SurfaceParameters[k].BytePerPixelC = mode_lib->mp.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1073
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, full_swath_bytes_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10730
s->SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ip.ptoi_supported;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10731
s->SurfaceParameters[k].VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10732
s->SurfaceParameters[k].VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10733
s->SurfaceParameters[k].VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10734
s->SurfaceParameters[k].VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10735
s->SurfaceParameters[k].PitchY = display_cfg->plane_descriptors[k].surface.plane0.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10736
s->SurfaceParameters[k].PitchC = display_cfg->plane_descriptors[k].surface.plane1.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10737
s->SurfaceParameters[k].ViewportStationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10738
s->SurfaceParameters[k].ViewportXStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10739
s->SurfaceParameters[k].ViewportYStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10740
s->SurfaceParameters[k].ViewportXStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10741
s->SurfaceParameters[k].ViewportYStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10742
s->SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = display_cfg->plane_descriptors[k].overrides.hw.force_one_row_for_frame;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10743
s->SurfaceParameters[k].SwathHeightY = mode_lib->mp.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10744
s->SurfaceParameters[k].SwathHeightC = mode_lib->mp.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10745
s->SurfaceParameters[k].DCCMetaPitchY = display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10746
s->SurfaceParameters[k].DCCMetaPitchC = display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1076
l->minDET_pipe = (unsigned int)(math_max2(128, math_ceil2(((double)full_swath_bytes_l[k] + (double)full_swath_bytes_c[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1077
DML_LOG_VERBOSE("DML::%s: k=%u minDET_pipe = %u (assume each plane take half DET)\n", __func__, k, l->minDET_pipe);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1080
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1081
DETBufferSizeInKByte[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1082
} else if (display_cfg->plane_descriptors[k].overrides.det_size_override_kb > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10820
for (k = 0; k < s->num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10821
mode_lib->mp.mall_prefetch_sdp_overhead_factor[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10822
mode_lib->mp.mall_prefetch_dram_overhead_factor[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10823
mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p0[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10824
mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p0[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10825
mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p1[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10826
mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p1[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10829
for (k = 0; k < s->num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1083
DETBufferSizeInKByte[k] = display_cfg->plane_descriptors[k].overrides.det_size_override_kb;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10830
calculate_mcache_setting_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10836
calculate_mcache_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10838
calculate_mcache_setting_params->source_format = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10839
calculate_mcache_setting_params->surf_vert = dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1084
l->DETBufferSizePoolInKByte = l->DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * display_cfg->plane_descriptors[k].overrides.det_size_override_kb;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10840
calculate_mcache_setting_params->vp_stationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10841
calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10842
calculate_mcache_setting_params->imall_enable = mode_lib->ip.imall_supported && display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10844
calculate_mcache_setting_params->vp_start_x_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10845
calculate_mcache_setting_params->vp_start_y_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10846
calculate_mcache_setting_params->full_vp_width_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10847
calculate_mcache_setting_params->full_vp_height_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10848
calculate_mcache_setting_params->blk_width_l = mode_lib->mp.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10849
calculate_mcache_setting_params->blk_height_l = mode_lib->mp.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1085
} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * l->minDET_pipe <= l->DETBufferSizePoolInKByte) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10850
calculate_mcache_setting_params->vmpg_width_l = s->vmpg_width_y[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10851
calculate_mcache_setting_params->vmpg_height_l = s->vmpg_height_y[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10852
calculate_mcache_setting_params->full_swath_bytes_l = s->full_swath_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10853
calculate_mcache_setting_params->bytes_per_pixel_l = mode_lib->mp.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10855
calculate_mcache_setting_params->vp_start_x_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10856
calculate_mcache_setting_params->vp_start_y_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10857
calculate_mcache_setting_params->full_vp_width_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10858
calculate_mcache_setting_params->full_vp_height_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10859
calculate_mcache_setting_params->blk_width_c = mode_lib->mp.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1086
DETBufferSizeInKByte[k] = l->minDET_pipe;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10860
calculate_mcache_setting_params->blk_height_c = mode_lib->mp.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10861
calculate_mcache_setting_params->vmpg_width_c = s->vmpg_width_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10862
calculate_mcache_setting_params->vmpg_height_c = s->vmpg_height_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10863
calculate_mcache_setting_params->full_swath_bytes_c = s->full_swath_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10864
calculate_mcache_setting_params->bytes_per_pixel_c = mode_lib->mp.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10867
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_l = &mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p0[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10868
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_l = &mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p0[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10869
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_c = &mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p1[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1087
l->DETBufferSizePoolInKByte = l->DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * l->minDET_pipe;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10870
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_c = &mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p1[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10872
calculate_mcache_setting_params->num_mcaches_l = &mode_lib->mp.num_mcaches_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10873
calculate_mcache_setting_params->mcache_row_bytes_l = &mode_lib->mp.mcache_row_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10874
calculate_mcache_setting_params->mcache_row_bytes_per_channel_l = &mode_lib->mp.mcache_row_bytes_per_channel_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10875
calculate_mcache_setting_params->mcache_offsets_l = mode_lib->mp.mcache_offsets_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10876
calculate_mcache_setting_params->mcache_shift_granularity_l = &mode_lib->mp.mcache_shift_granularity_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10878
calculate_mcache_setting_params->num_mcaches_c = &mode_lib->mp.num_mcaches_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10879
calculate_mcache_setting_params->mcache_row_bytes_c = &mode_lib->mp.mcache_row_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10880
calculate_mcache_setting_params->mcache_row_bytes_per_channel_c = &mode_lib->mp.mcache_row_bytes_per_channel_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10881
calculate_mcache_setting_params->mcache_offsets_c = mode_lib->mp.mcache_offsets_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10882
calculate_mcache_setting_params->mcache_shift_granularity_c = &mode_lib->mp.mcache_shift_granularity_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10884
calculate_mcache_setting_params->mall_comb_mcache_l = &mode_lib->mp.mall_comb_mcache_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10885
calculate_mcache_setting_params->mall_comb_mcache_c = &mode_lib->mp.mall_comb_mcache_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10886
calculate_mcache_setting_params->lc_comb_mcache = &mode_lib->mp.lc_comb_mcache[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1090
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1091
DML_LOG_VERBOSE("DML::%s: k=%u DETSizeOverride = %u\n", __func__, k, display_cfg->plane_descriptors[k].overrides.det_size_override_kb);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1092
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10928
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10929
s->TotalActiveDPP = s->TotalActiveDPP + mode_lib->mp.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10930
if (display_cfg->plane_descriptors[k].surface.dcc.enable)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10931
s->TotalDCCActiveDPP = s->TotalDCCActiveDPP + mode_lib->mp.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10934
for (k = 0; k <= s->num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10936
calculate_tdlut_setting_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10937
calculate_tdlut_setting_params->tdlut_width_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_width_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10938
calculate_tdlut_setting_params->tdlut_addressing_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_addressing_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10941
calculate_tdlut_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10944
calculate_tdlut_setting_params->tdlut_pte_bytes_per_frame = &s->tdlut_pte_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10945
calculate_tdlut_setting_params->tdlut_bytes_per_frame = &s->tdlut_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10946
calculate_tdlut_setting_params->tdlut_groups_per_2row_ub = &s->tdlut_groups_per_2row_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10947
calculate_tdlut_setting_params->tdlut_opt_time = &s->tdlut_opt_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10948
calculate_tdlut_setting_params->tdlut_drain_time = &s->tdlut_drain_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10949
calculate_tdlut_setting_params->tdlut_bytes_to_deliver = &s->tdlut_bytes_to_deliver[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10950
calculate_tdlut_setting_params->tdlut_bytes_per_group = &s->tdlut_bytes_per_group[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10992
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10993
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10994
mode_lib->mp.WritebackDelay[k] =
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10997
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10998
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10999
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11000
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11001
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11002
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11003
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11004
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->mp.Dispclk;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11006
mode_lib->mp.WritebackDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1104
for (unsigned int k = 0; k < display_cfg->num_streams; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1105
l->TotalPixelRate += display_cfg->stream_descriptors[k].timing.pixel_clock_khz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11087
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11089
s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1109
for (unsigned int k = 0; k < display_cfg->num_streams; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11090
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11092
s->pixel_format[k] = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11094
s->lb_source_lines_l[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11095
mode_lib->mp.NoOfDPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11096
display_cfg->plane_descriptors[k].composition.viewport.plane0.width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11097
display_cfg->plane_descriptors[k].composition.viewport.plane0.height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11098
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11099
display_cfg->plane_descriptors[k].composition.rotation_angle);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1110
l->DETBudgetPerStream[k] = (unsigned int)((double) display_cfg->stream_descriptors[k].timing.pixel_clock_khz * MaxTotalDETInKByte / l->TotalPixelRate);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11101
s->lb_source_lines_c[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11102
mode_lib->mp.NoOfDPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11103
display_cfg->plane_descriptors[k].composition.viewport.plane1.width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11104
display_cfg->plane_descriptors[k].composition.viewport.plane1.height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11105
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11106
display_cfg->plane_descriptors[k].composition.rotation_angle);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11108
if (display_cfg->plane_descriptors[k].cursor.num_cursors > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1111
l->RemainingDETBudgetPerStream[k] = l->DETBudgetPerStream[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11110
display_cfg->plane_descriptors[k].cursor.cursor_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11111
display_cfg->plane_descriptors[k].cursor.cursor_bpp,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11114
&s->cursor_lines_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11115
&s->cursor_bytes_per_line[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11116
&s->cursor_bytes_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11117
&s->cursor_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11121
display_cfg->plane_descriptors[k].cursor.cursor_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11122
s->cursor_bytes_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11123
s->cursor_lines_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11124
s->line_times[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11128
&mode_lib->mp.UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11131
mode_lib->mp.UrgentBurstFactorCursorPre[k] = mode_lib->mp.UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11134
&display_cfg->plane_descriptors[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11135
mode_lib->mp.swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11136
mode_lib->mp.swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11137
mode_lib->mp.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11138
mode_lib->mp.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11139
s->line_times[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11141
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11142
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11143
mode_lib->mp.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11144
mode_lib->mp.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11145
mode_lib->mp.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11146
mode_lib->mp.DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11149
&mode_lib->mp.UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1115
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11150
&mode_lib->mp.UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11151
&mode_lib->mp.NotEnoughUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11153
mode_lib->mp.NotEnoughUrgentLatencyHiding[k] = mode_lib->mp.NotEnoughUrgentLatencyHiding[k] || cursor_not_enough_urgent_latency_hiding;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11156
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11157
s->MaxVStartupLines[k] = CalculateMaxVStartup(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1116
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11160
&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11161
mode_lib->mp.WritebackDelay[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11164
DML_LOG_VERBOSE("DML::%s: k=%u MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11165
DML_LOG_VERBOSE("DML::%s: k=%u WritebackDelay = %f\n", __func__, k, mode_lib->mp.WritebackDelay[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1117
l->TotalBandwidthPerStream[display_cfg->plane_descriptors[k].stream_index] += (unsigned int)(ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11170
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11171
s->immediate_flip_required = s->immediate_flip_required || display_cfg->plane_descriptors[k].immediate_flip;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1120
if (l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index] >= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1121
l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index] -= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11212
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11215
DML_LOG_VERBOSE("DML::%s: k=%d MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11216
mode_lib->mp.TWait[k] = CalculateTWait(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11217
display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11220
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11223
myPipe->Dppclk = mode_lib->mp.Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11225
myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11227
myPipe->DPPPerSurface = mode_lib->mp.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11228
myPipe->ScalerEnabled = display_cfg->plane_descriptors[k].composition.scaler_info.enabled;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11229
myPipe->VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11230
myPipe->VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11231
myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11232
myPipe->VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11233
myPipe->RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11234
myPipe->mirrored = display_cfg->plane_descriptors[k].composition.mirrored;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11235
myPipe->BlockWidth256BytesY = mode_lib->mp.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11236
myPipe->BlockHeight256BytesY = mode_lib->mp.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11237
myPipe->BlockWidth256BytesC = mode_lib->mp.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11238
myPipe->BlockHeight256BytesC = mode_lib->mp.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11239
myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11240
myPipe->NumberOfCursors = display_cfg->plane_descriptors[k].cursor.num_cursors;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11241
myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11242
myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11243
myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11244
myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11245
myPipe->ODMMode = mode_lib->mp.ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11246
myPipe->SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11247
myPipe->BytePerPixelY = mode_lib->mp.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11248
myPipe->BytePerPixelC = mode_lib->mp.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11252
DML_LOG_VERBOSE("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11257
CalculatePrefetchSchedule_params->DSCDelay = mode_lib->mp.DSCDelay[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11263
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (unsigned int)(mode_lib->mp.SwathWidthY[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11264
CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11266
CalculatePrefetchSchedule_params->VStartup = s->MaxVStartupLines[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11268
CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11270
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = display_cfg->plane_descriptors[k].dynamic_meta_data.lines_before_active_required;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11271
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = display_cfg->plane_descriptors[k].dynamic_meta_data.transmitted_bytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11275
CalculatePrefetchSchedule_params->vm_bytes = mode_lib->mp.vm_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11276
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = mode_lib->mp.PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11277
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = mode_lib->mp.PrefetchSourceLinesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11278
CalculatePrefetchSchedule_params->VInitPreFillY = mode_lib->mp.VInitPreFillY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11279
CalculatePrefetchSchedule_params->MaxNumSwathY = mode_lib->mp.MaxNumSwathY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11280
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = mode_lib->mp.PrefetchSourceLinesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11281
CalculatePrefetchSchedule_params->VInitPreFillC = mode_lib->mp.VInitPreFillC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11282
CalculatePrefetchSchedule_params->MaxNumSwathC = mode_lib->mp.MaxNumSwathC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11283
CalculatePrefetchSchedule_params->swath_width_luma_ub = mode_lib->mp.swath_width_luma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11284
CalculatePrefetchSchedule_params->swath_width_chroma_ub = mode_lib->mp.swath_width_chroma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11285
CalculatePrefetchSchedule_params->SwathHeightY = mode_lib->mp.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11286
CalculatePrefetchSchedule_params->SwathHeightC = mode_lib->mp.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11287
CalculatePrefetchSchedule_params->TWait = mode_lib->mp.TWait[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11290
CalculatePrefetchSchedule_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11291
CalculatePrefetchSchedule_params->tdlut_pte_bytes_per_frame = s->tdlut_pte_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11292
CalculatePrefetchSchedule_params->tdlut_bytes_per_frame = s->tdlut_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11293
CalculatePrefetchSchedule_params->tdlut_opt_time = s->tdlut_opt_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11294
CalculatePrefetchSchedule_params->tdlut_drain_time = s->tdlut_drain_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11295
CalculatePrefetchSchedule_params->num_cursors = (display_cfg->plane_descriptors[k].cursor.cursor_width > 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11296
CalculatePrefetchSchedule_params->cursor_bytes_per_chunk = s->cursor_bytes_per_chunk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11297
CalculatePrefetchSchedule_params->cursor_bytes_per_line = s->cursor_bytes_per_line[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11298
CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11300
CalculatePrefetchSchedule_params->meta_row_bytes = mode_lib->mp.meta_row_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11301
CalculatePrefetchSchedule_params->mall_prefetch_sdp_overhead_factor = mode_lib->mp.mall_prefetch_sdp_overhead_factor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11302
CalculatePrefetchSchedule_params->impacted_dst_y_pre = s->impacted_dst_y_pre[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11303
CalculatePrefetchSchedule_params->vactive_sw_bw_l = mode_lib->mp.vactive_sw_bw_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11304
CalculatePrefetchSchedule_params->vactive_sw_bw_c = mode_lib->mp.vactive_sw_bw_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11307
CalculatePrefetchSchedule_params->DSTXAfterScaler = &mode_lib->mp.DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11308
CalculatePrefetchSchedule_params->DSTYAfterScaler = &mode_lib->mp.DSTYAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11309
CalculatePrefetchSchedule_params->dst_y_prefetch = &mode_lib->mp.dst_y_prefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11310
CalculatePrefetchSchedule_params->dst_y_per_vm_vblank = &mode_lib->mp.dst_y_per_vm_vblank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11311
CalculatePrefetchSchedule_params->dst_y_per_row_vblank = &mode_lib->mp.dst_y_per_row_vblank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11312
CalculatePrefetchSchedule_params->VRatioPrefetchY = &mode_lib->mp.VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11313
CalculatePrefetchSchedule_params->VRatioPrefetchC = &mode_lib->mp.VRatioPrefetchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11314
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWLuma = &mode_lib->mp.RequiredPrefetchPixelDataBWLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11315
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWChroma = &mode_lib->mp.RequiredPrefetchPixelDataBWChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11316
CalculatePrefetchSchedule_params->RequiredPrefetchBWMax = &s->dummy_single_array[0][k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11317
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->mp.NotEnoughTimeForDynamicMetadata[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11318
CalculatePrefetchSchedule_params->Tno_bw = &mode_lib->mp.Tno_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11319
CalculatePrefetchSchedule_params->Tno_bw_flip = &mode_lib->mp.Tno_bw_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11320
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &mode_lib->mp.prefetch_vmrow_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11321
CalculatePrefetchSchedule_params->Tdmdl_vm = &mode_lib->mp.Tdmdl_vm[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11322
CalculatePrefetchSchedule_params->Tdmdl = &mode_lib->mp.Tdmdl[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11323
CalculatePrefetchSchedule_params->TSetup = &mode_lib->mp.TSetup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11324
CalculatePrefetchSchedule_params->Tvm_trips = &s->Tvm_trips[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11325
CalculatePrefetchSchedule_params->Tr0_trips = &s->Tr0_trips[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11326
CalculatePrefetchSchedule_params->Tvm_trips_flip = &s->Tvm_trips_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11327
CalculatePrefetchSchedule_params->Tr0_trips_flip = &s->Tr0_trips_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11328
CalculatePrefetchSchedule_params->Tvm_trips_flip_rounded = &s->Tvm_trips_flip_rounded[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11329
CalculatePrefetchSchedule_params->Tr0_trips_flip_rounded = &s->Tr0_trips_flip_rounded[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11330
CalculatePrefetchSchedule_params->VUpdateOffsetPix = &mode_lib->mp.VUpdateOffsetPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11331
CalculatePrefetchSchedule_params->VUpdateWidthPix = &mode_lib->mp.VUpdateWidthPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11332
CalculatePrefetchSchedule_params->VReadyOffsetPix = &mode_lib->mp.VReadyOffsetPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11333
CalculatePrefetchSchedule_params->prefetch_cursor_bw = &mode_lib->mp.prefetch_cursor_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11334
CalculatePrefetchSchedule_params->prefetch_sw_bytes = &s->prefetch_sw_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11335
CalculatePrefetchSchedule_params->Tpre_rounded = &s->Tpre_rounded[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11336
CalculatePrefetchSchedule_params->Tpre_oto = &s->Tpre_oto[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11339
mode_lib->mp.NoTimeToPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1134
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11341
if (s->impacted_dst_y_pre[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11342
mode_lib->mp.impacted_prefetch_margin_us[k] = (mode_lib->mp.dst_y_prefetch[k] - s->impacted_dst_y_pre[k]) * s->line_times[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11344
mode_lib->mp.impacted_prefetch_margin_us[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11347
DML_LOG_VERBOSE("DML::%s: k=%0u NoTimeToPrefetch=%0d\n", __func__, k, mode_lib->mp.NoTimeToPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11349
mode_lib->mp.VStartupMin[k] = s->MaxVStartupLines[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1135
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11353
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11354
if (mode_lib->mp.NoTimeToPrefetch[k] == true ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11355
mode_lib->mp.NotEnoughTimeForDynamicMetadata[k] ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11356
mode_lib->mp.DSTYAfterScaler[k] > 8) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11357
DML_LOG_VERBOSE("DML::%s: k=%u, NoTimeToPrefetch = %0d\n", __func__, k, mode_lib->mp.NoTimeToPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11358
DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughTimeForDynamicMetadata=%u\n", __func__, k, mode_lib->mp.NotEnoughTimeForDynamicMetadata[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11359
DML_LOG_VERBOSE("DML::%s: k=%u, DSTYAfterScaler=%u (should be <= 0)\n", __func__, k, mode_lib->mp.DSTYAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1136
l->IdealDETBudget = (unsigned int)(((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / l->TotalBandwidthPerStream[display_cfg->plane_descriptors[k].stream_index])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11362
if (mode_lib->mp.dst_y_prefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11365
if (mode_lib->mp.VRatioPrefetchY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11366
mode_lib->mp.VRatioPrefetchC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11368
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPrefetchY=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchY[k], __DML2_CALCS_MAX_VRATIO_PRE__);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11369
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPrefetchC=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchC[k], __DML2_CALCS_MAX_VRATIO_PRE__);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1137
* l->DETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11373
if (mode_lib->mp.NotEnoughUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11374
DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughUrgentLatencyHiding = %u\n", __func__, k, mode_lib->mp.NotEnoughUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1139
if (l->IdealDETBudget > DETBufferSizeInKByte[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11390
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11391
double line_time_us = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11392
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11394
&display_cfg->plane_descriptors[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11395
mode_lib->mp.swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11396
mode_lib->mp.swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11397
mode_lib->mp.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11398
mode_lib->mp.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1140
l->DeltaDETBudget = l->IdealDETBudget - DETBufferSizeInKByte[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11401
mode_lib->mp.VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11402
mode_lib->mp.VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11403
mode_lib->mp.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11404
mode_lib->mp.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11405
mode_lib->mp.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11406
mode_lib->mp.DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11408
&mode_lib->mp.UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11409
&mode_lib->mp.UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1141
if (l->DeltaDETBudget > l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11410
&mode_lib->mp.NotEnoughUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11413
DML_LOG_VERBOSE("DML::%s: k=%0u DPPPerSurface=%u\n", __func__, k, mode_lib->mp.NoOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11414
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorLuma=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11415
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorChroma=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11416
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorLumaPre=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11417
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorChromaPre=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11419
DML_LOG_VERBOSE("DML::%s: k=%0u VRatioPrefetchY=%f\n", __func__, k, mode_lib->mp.VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1142
l->DeltaDETBudget = l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11420
DML_LOG_VERBOSE("DML::%s: k=%0u VRatioY=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11422
DML_LOG_VERBOSE("DML::%s: k=%0u prefetch_vmrow_bw=%f\n", __func__, k, mode_lib->mp.prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11423
DML_LOG_VERBOSE("DML::%s: k=%0u vactive_sw_bw_l=%f\n", __func__, k, mode_lib->mp.vactive_sw_bw_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11424
DML_LOG_VERBOSE("DML::%s: k=%0u vactive_sw_bw_c=%f\n", __func__, k, mode_lib->mp.vactive_sw_bw_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11425
DML_LOG_VERBOSE("DML::%s: k=%0u cursor_bw=%f\n", __func__, k, mode_lib->mp.cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11426
DML_LOG_VERBOSE("DML::%s: k=%0u dpte_row_bw=%f\n", __func__, k, mode_lib->mp.dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11427
DML_LOG_VERBOSE("DML::%s: k=%0u meta_row_bw=%f\n", __func__, k, mode_lib->mp.meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11428
DML_LOG_VERBOSE("DML::%s: k=%0u RequiredPrefetchPixelDataBWLuma=%f\n", __func__, k, mode_lib->mp.RequiredPrefetchPixelDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11429
DML_LOG_VERBOSE("DML::%s: k=%0u RequiredPrefetchPixelDataBWChroma=%f\n", __func__, k, mode_lib->mp.RequiredPrefetchPixelDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11430
DML_LOG_VERBOSE("DML::%s: k=%0u prefetch_cursor_bw=%f\n", __func__, k, mode_lib->mp.prefetch_cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11434
for (k = 0; k <= s->num_active_planes - 1; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11435
mode_lib->mp.final_flip_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1145
DETBufferSizeInKByte[k] += (unsigned int)((double)l->DeltaDETBudget / (ForceSingleDPP ? 1 : DPPPerSurface[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1146
l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index] -= l->DeltaDETBudget;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11496
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11497
if (mode_lib->mp.NotEnoughUrgentLatencyHidingPre[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11498
DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughUrgentLatencyHidingPre = %u\n", __func__, k, mode_lib->mp.NotEnoughUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1150
DETBufferSizeInKByte[k] = (DETBufferSizeInKByte[k] / ConfigReturnBufferSegmentSizeInkByte) * ConfigReturnBufferSegmentSizeInkByte;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11513
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11514
if (display_cfg->plane_descriptors[k].immediate_flip) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11515
s->per_pipe_flip_bytes[k] = get_pipe_flip_bytes(s->HostVMInefficiencyFactor,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11516
mode_lib->mp.vm_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11517
mode_lib->mp.PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11518
mode_lib->mp.meta_row_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1152
l->ResidualDETAfterRounding -= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11520
s->per_pipe_flip_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11522
mode_lib->mp.TotImmediateFlipBytes += s->per_pipe_flip_bytes[k] * mode_lib->mp.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11524
DML_LOG_VERBOSE("DML::%s: k = %u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11525
DML_LOG_VERBOSE("DML::%s: DPPPerSurface = %u\n", __func__, mode_lib->mp.NoOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11526
DML_LOG_VERBOSE("DML::%s: vm_bytes = %u\n", __func__, mode_lib->mp.vm_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11527
DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, mode_lib->mp.PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11528
DML_LOG_VERBOSE("DML::%s: meta_row_bytes = %u\n", __func__, mode_lib->mp.meta_row_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11532
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11535
display_cfg->plane_descriptors[k].immediate_flip,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11538
s->Tvm_trips_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11539
s->Tr0_trips_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11540
s->Tvm_trips_flip_rounded[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11541
s->Tr0_trips_flip_rounded[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11543
mode_lib->mp.vm_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11544
mode_lib->mp.PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11547
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11548
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11549
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11550
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11551
mode_lib->mp.Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11552
mode_lib->mp.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11553
mode_lib->mp.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11554
mode_lib->mp.use_one_row_for_frame_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11557
s->per_pipe_flip_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11558
mode_lib->mp.meta_row_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11559
mode_lib->mp.meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11560
mode_lib->mp.meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11561
mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11564
&mode_lib->mp.dst_y_per_vm_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11565
&mode_lib->mp.dst_y_per_row_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11566
&mode_lib->mp.final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11567
&mode_lib->mp.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1160
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1161
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1162
l->TotalBandwidth = l->TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11624
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11625
if (display_cfg->plane_descriptors[k].immediate_flip && mode_lib->mp.ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11628
DML_LOG_VERBOSE("DML::%s: Pipe %0d not supporting iflip!\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11642
for (k = 0; k < s->num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11643
DML_LOG_VERBOSE("DML::%s: immediate_flip_required[%u] = %u\n", __func__, k, display_cfg->plane_descriptors[k].immediate_flip);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11648
DML_LOG_VERBOSE("DML::%s: Done one iteration: k=%d, MaxVStartupLines=%u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11651
for (k = 0; k < s->num_active_planes; ++k)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11652
DML_LOG_VERBOSE("DML::%s: k=%d MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1166
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11660
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11662
DML_LOG_VERBOSE("DML::%s: Calculate DCC configuration for surface k=%u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11665
display_cfg->plane_descriptors[k].surface.dcc.enable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11667
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11668
display_cfg->plane_descriptors[k].surface.plane0.width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11669
display_cfg->plane_descriptors[k].surface.plane1.width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1167
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11670
display_cfg->plane_descriptors[k].surface.plane0.height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11671
display_cfg->plane_descriptors[k].surface.plane1.height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11673
mode_lib->mp.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11674
mode_lib->mp.Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11675
display_cfg->plane_descriptors[k].surface.tiling,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11676
mode_lib->mp.BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11677
mode_lib->mp.BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11678
mode_lib->mp.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11679
mode_lib->mp.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11680
display_cfg->plane_descriptors[k].composition.rotation_angle,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11683
&mode_lib->mp.RequestLuma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11684
&mode_lib->mp.RequestChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11685
&mode_lib->mp.DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11686
&mode_lib->mp.DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11687
&mode_lib->mp.DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11688
&mode_lib->mp.DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11689
&mode_lib->mp.DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11690
&mode_lib->mp.DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1172
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1174
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1175
DETPieceAssignedToThisSurfaceAlready[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11757
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11758
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11759
mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1176
} else if (display_cfg->plane_descriptors[k].overrides.det_size_override_kb > 0 || (((double)(ForceSingleDPP ? 1 : DPPPerSurface[k]) * (double)DETBufferSizeInKByte[k] / (double)MaxTotalDETInKByte) >= ((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / l->TotalBandwidth))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11760
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11761
mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11762
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackFCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11764
mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11765
mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1177
DETPieceAssignedToThisSurfaceAlready[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1178
l->BandwidthOfSurfacesNotAssignedDETPiece = l->BandwidthOfSurfacesNotAssignedDETPiece - ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1180
DETPieceAssignedToThisSurfaceAlready[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1182
DML_LOG_VERBOSE("DML::%s: k=%u DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, k, DETPieceAssignedToThisSurfaceAlready[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1183
DML_LOG_VERBOSE("DML::%s: k=%u BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k, l->BandwidthOfSurfacesNotAssignedDETPiece);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11876
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11879
mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.TWait[k] + mode_lib->mp.ExtraLatency;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11880
if (!display_cfg->plane_descriptors[k].dynamic_meta_data.enable)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11881
mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.TCalc + mode_lib->mp.MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11884
DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k, mode_lib->mp.MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11886
s->Tvstartup_margin = (s->MaxVStartupLines[k] - mode_lib->mp.VStartupMin[k]) * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11887
mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.MinTTUVBlank[k] + s->Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11890
DML_LOG_VERBOSE("DML::%s: k=%u, Tvstartup_margin = %f\n", __func__, k, s->Tvstartup_margin);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11891
DML_LOG_VERBOSE("DML::%s: k=%u, MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11892
DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlank = %f\n", __func__, k, mode_lib->mp.MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11895
mode_lib->mp.Tdmdl[k] = mode_lib->mp.Tdmdl[k] + s->Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11896
if (display_cfg->plane_descriptors[k].dynamic_meta_data.enable && mode_lib->ip.dynamic_metadata_vm_enabled) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11897
mode_lib->mp.Tdmdl_vm[k] = mode_lib->mp.Tdmdl_vm[k] + s->Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1190
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11900
isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11903
mode_lib->mp.VStartup[k] = (isInterlaceTiming ? (2 * s->MaxVStartupLines[k]) : s->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11905
s->dlg_vblank_start = ((isInterlaceTiming ? math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11906
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total) - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11907
s->LSetup = math_floor2(4.0 * mode_lib->mp.TSetup[k] / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11908
s->blank_lines_remaining = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active) - mode_lib->mp.VStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1191
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthLuma[k] = %f\n", __func__, j, k, ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11915
mode_lib->mp.MIN_DST_Y_NEXT_START[k] = s->dlg_vblank_start + s->blank_lines_remaining + s->LSetup;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11918
if (((mode_lib->mp.VUpdateOffsetPix[k] + mode_lib->mp.VUpdateWidthPix[k] + mode_lib->mp.VReadyOffsetPix[k]) / (double) display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) <=
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1192
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthChroma[k] = %f\n", __func__, j, k, ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11920
math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11921
(int)(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11922
mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11924
mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11927
DML_LOG_VERBOSE("DML::%s: k=%u, VStartup = %u (max)\n", __func__, k, mode_lib->mp.VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11928
DML_LOG_VERBOSE("DML::%s: k=%u, VStartupMin = %u (max)\n", __func__, k, mode_lib->mp.VStartupMin[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11929
DML_LOG_VERBOSE("DML::%s: k=%u, VUpdateOffsetPix = %u\n", __func__, k, mode_lib->mp.VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1193
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthLuma[Next] = %f\n", __func__, j, k, ReadBandwidthLuma[l->NextSurfaceToAssignDETPiece]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11930
DML_LOG_VERBOSE("DML::%s: k=%u, VUpdateWidthPix = %u\n", __func__, k, mode_lib->mp.VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11931
DML_LOG_VERBOSE("DML::%s: k=%u, VReadyOffsetPix = %u\n", __func__, k, mode_lib->mp.VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11932
DML_LOG_VERBOSE("DML::%s: k=%u, HTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11933
DML_LOG_VERBOSE("DML::%s: k=%u, VTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11934
DML_LOG_VERBOSE("DML::%s: k=%u, VActive = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11935
DML_LOG_VERBOSE("DML::%s: k=%u, VFrontPorch = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11936
DML_LOG_VERBOSE("DML::%s: k=%u, TSetup = %f\n", __func__, k, mode_lib->mp.TSetup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11937
DML_LOG_VERBOSE("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f\n", __func__, k, mode_lib->mp.MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11938
DML_LOG_VERBOSE("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1194
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthChroma[Next] = %f\n", __func__, j, k, ReadBandwidthChroma[l->NextSurfaceToAssignDETPiece]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11944
for (k = 0; k < display_cfg->num_streams; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11946
if (display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11947
s->WRBandwidth = display_cfg->stream_descriptors[k].writeback.writeback_stream[0].output_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11948
* display_cfg->stream_descriptors[k].writeback.writeback_stream[0].output_width /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11949
(display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0].input_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1195
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, NextSurfaceToAssignDETPiece = %u\n", __func__, j, k, l->NextSurfaceToAssignDETPiece);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11950
/ ((double)display_cfg->stream_descriptors[k].timing.pixel_clock_khz / 1000))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11951
* (display_cfg->stream_descriptors[k].writeback.writeback_stream[0].pixel_format == dml2_444_32 ? 4.0 : 8.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11957
for (k = 0; k < s->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11958
mode_lib->mp.TotalDataReadBandwidth = mode_lib->mp.TotalDataReadBandwidth + mode_lib->mp.vactive_sw_bw_l[k] + mode_lib->mp.vactive_sw_bw_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1196
if (!DETPieceAssignedToThisSurfaceAlready[k] && (!NextPotentialSurfaceToAssignDETPieceFound ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11960
DML_LOG_VERBOSE("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, mode_lib->mp.TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11961
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_l = %f\n", __func__, k, mode_lib->mp.vactive_sw_bw_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11962
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_c = %f\n", __func__, k, mode_lib->mp.vactive_sw_bw_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1197
ReadBandwidthLuma[k] + ReadBandwidthChroma[k] < ReadBandwidthLuma[l->NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[l->NextSurfaceToAssignDETPiece])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1198
l->NextSurfaceToAssignDETPiece = k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1201
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1202
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, NextPotentialSurfaceToAssignDETPieceFound = %u\n", __func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1235
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1236
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u (TotalReadBandWidth=%f)\n", __func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13016
unsigned int k, n;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13076
for (k = 0; k < out->display_config.num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13078
out->informative.mode_support_info.FCLKChangeSupport[k] = mode_lib->ms.support.FCLKChangeSupport[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13079
out->informative.mode_support_info.MPCCombineEnable[k] = mode_lib->ms.support.MPCCombineEnable[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13080
out->informative.mode_support_info.ODMMode[k] = mode_lib->ms.support.ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13081
out->informative.mode_support_info.DPPPerSurface[k] = mode_lib->ms.support.DPPPerSurface[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13082
out->informative.mode_support_info.DSCEnabled[k] = mode_lib->ms.support.DSCEnabled[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13083
out->informative.mode_support_info.FECEnabled[k] = mode_lib->ms.support.FECEnabled[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13084
out->informative.mode_support_info.NumberOfDSCSlices[k] = mode_lib->ms.support.NumberOfDSCSlices[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13085
out->informative.mode_support_info.OutputBpp[k] = mode_lib->ms.support.OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13087
if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_unknown)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13088
out->informative.mode_support_info.OutputType[k] = dml2_output_type_unknown;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13089
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_dp)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13090
out->informative.mode_support_info.OutputType[k] = dml2_output_type_dp;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13091
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_edp)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13092
out->informative.mode_support_info.OutputType[k] = dml2_output_type_edp;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13093
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_dp2p0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13094
out->informative.mode_support_info.OutputType[k] = dml2_output_type_dp2p0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13095
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_hdmi)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13096
out->informative.mode_support_info.OutputType[k] = dml2_output_type_hdmi;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13097
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_hdmifrl)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13098
out->informative.mode_support_info.OutputType[k] = dml2_output_type_hdmifrl;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13100
if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_unknown)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13101
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_unknown;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13102
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13103
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13104
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr2)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13105
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13106
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr3)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13107
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13108
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr10)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13109
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr10;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13110
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr13p5)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13111
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr13p5;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13112
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr20)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13113
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr20;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13114
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_3x3)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13115
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_3x3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13116
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x3)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13117
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_6x3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13118
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x4)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13119
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_6x4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13120
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_8x4)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13121
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_8x4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13122
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_10x4)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13123
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_10x4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13124
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_12x4)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13125
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_12x4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13126
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_16x4)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13127
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_16x4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13128
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_20x4)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13129
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_20x4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13131
out->informative.mode_support_info.AlignedYPitch[k] = mode_lib->ms.support.AlignedYPitch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13132
out->informative.mode_support_info.AlignedCPitch[k] = mode_lib->ms.support.AlignedCPitch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13151
for (k = 0; k < out->display_config.num_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13152
out->informative.mall.total_surface_size_in_mall_bytes += mode_lib->mp.SurfaceSizeInTheMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13153
out->informative.dpp.total_num_dpps_required += mode_lib->mp.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13235
for (k = 0; k < out->display_config.num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13240
out->informative.misc.PrefetchMode[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13243
out->informative.misc.PrefetchMode[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13245
out->informative.misc.PrefetchMode[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13247
out->informative.misc.PrefetchMode[k] = 3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13249
out->informative.misc.min_ttu_vblank_us[k] = mode_lib->mp.MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13250
out->informative.mall.subviewport_lines_needed_in_mall[k] = mode_lib->mp.SubViewportLinesNeededInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13251
out->informative.crb.det_size_in_kbytes[k] = mode_lib->mp.DETBufferSizeInKByte[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13252
out->informative.crb.DETBufferSizeY[k] = mode_lib->mp.DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13253
out->informative.misc.ImmediateFlipSupportedForPipe[k] = mode_lib->mp.ImmediateFlipSupportedForPipe[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13254
out->informative.misc.UsesMALLForStaticScreen[k] = mode_lib->mp.is_using_mall_for_ss[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13255
out->informative.plane_info[k].dpte_row_height_plane0 = mode_lib->mp.dpte_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13256
out->informative.plane_info[k].dpte_row_height_plane1 = mode_lib->mp.dpte_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13257
out->informative.plane_info[k].meta_row_height_plane0 = mode_lib->mp.meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13258
out->informative.plane_info[k].meta_row_height_plane1 = mode_lib->mp.meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13259
out->informative.dcc_control[k].max_uncompressed_block_plane0 = mode_lib->mp.DCCYMaxUncompressedBlock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13260
out->informative.dcc_control[k].max_compressed_block_plane0 = mode_lib->mp.DCCYMaxCompressedBlock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13261
out->informative.dcc_control[k].independent_block_plane0 = mode_lib->mp.DCCYIndependentBlock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13262
out->informative.dcc_control[k].max_uncompressed_block_plane1 = mode_lib->mp.DCCCMaxUncompressedBlock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13263
out->informative.dcc_control[k].max_compressed_block_plane1 = mode_lib->mp.DCCCMaxCompressedBlock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13264
out->informative.dcc_control[k].independent_block_plane1 = mode_lib->mp.DCCCIndependentBlock[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13265
out->informative.misc.dst_x_after_scaler[k] = mode_lib->mp.DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13266
out->informative.misc.dst_y_after_scaler[k] = mode_lib->mp.DSTYAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13267
out->informative.misc.prefetch_source_lines_plane0[k] = mode_lib->mp.PrefetchSourceLinesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13268
out->informative.misc.prefetch_source_lines_plane1[k] = mode_lib->mp.PrefetchSourceLinesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13269
out->informative.misc.vready_at_or_after_vsync[k] = mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13270
out->informative.misc.min_dst_y_next_start[k] = mode_lib->mp.MIN_DST_Y_NEXT_START[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13271
out->informative.plane_info[k].swath_width_plane0 = mode_lib->mp.SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13272
out->informative.plane_info[k].swath_height_plane0 = mode_lib->mp.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13273
out->informative.plane_info[k].swath_height_plane1 = mode_lib->mp.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13274
out->informative.misc.CursorDstXOffset[k] = mode_lib->mp.CursorDstXOffset[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13275
out->informative.misc.CursorDstYOffset[k] = mode_lib->mp.CursorDstYOffset[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13276
out->informative.misc.CursorChunkHDLAdjust[k] = mode_lib->mp.CursorChunkHDLAdjust[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13277
out->informative.misc.dpte_group_bytes[k] = mode_lib->mp.dpte_group_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13278
out->informative.misc.vm_group_bytes[k] = mode_lib->mp.vm_group_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13279
out->informative.misc.DisplayPipeRequestDeliveryTimeLuma[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13280
out->informative.misc.DisplayPipeRequestDeliveryTimeChroma[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13281
out->informative.misc.DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeLumaPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13282
out->informative.misc.DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeChromaPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13283
out->informative.misc.TimePerVMGroupVBlank[k] = mode_lib->mp.TimePerVMGroupVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13284
out->informative.misc.TimePerVMGroupFlip[k] = mode_lib->mp.TimePerVMGroupFlip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13285
out->informative.misc.TimePerVMRequestVBlank[k] = mode_lib->mp.TimePerVMRequestVBlank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13286
out->informative.misc.TimePerVMRequestFlip[k] = mode_lib->mp.TimePerVMRequestFlip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13287
out->informative.misc.Tdmdl_vm[k] = mode_lib->mp.Tdmdl_vm[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13288
out->informative.misc.Tdmdl[k] = mode_lib->mp.Tdmdl[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13289
out->informative.misc.VStartup[k] = mode_lib->mp.VStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13290
out->informative.misc.VUpdateOffsetPix[k] = mode_lib->mp.VUpdateOffsetPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13291
out->informative.misc.VUpdateWidthPix[k] = mode_lib->mp.VUpdateWidthPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13292
out->informative.misc.VReadyOffsetPix[k] = mode_lib->mp.VReadyOffsetPix[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13294
out->informative.misc.DST_Y_PER_PTE_ROW_NOM_L[k] = mode_lib->mp.DST_Y_PER_PTE_ROW_NOM_L[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13295
out->informative.misc.DST_Y_PER_PTE_ROW_NOM_C[k] = mode_lib->mp.DST_Y_PER_PTE_ROW_NOM_C[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13296
out->informative.misc.time_per_pte_group_nom_luma[k] = mode_lib->mp.time_per_pte_group_nom_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13297
out->informative.misc.time_per_pte_group_nom_chroma[k] = mode_lib->mp.time_per_pte_group_nom_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13298
out->informative.misc.time_per_pte_group_vblank_luma[k] = mode_lib->mp.time_per_pte_group_vblank_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13299
out->informative.misc.time_per_pte_group_vblank_chroma[k] = mode_lib->mp.time_per_pte_group_vblank_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13300
out->informative.misc.time_per_pte_group_flip_luma[k] = mode_lib->mp.time_per_pte_group_flip_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13301
out->informative.misc.time_per_pte_group_flip_chroma[k] = mode_lib->mp.time_per_pte_group_flip_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13302
out->informative.misc.VRatioPrefetchY[k] = mode_lib->mp.VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13303
out->informative.misc.VRatioPrefetchC[k] = mode_lib->mp.VRatioPrefetchC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13304
out->informative.misc.DestinationLinesForPrefetch[k] = mode_lib->mp.dst_y_prefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13305
out->informative.misc.DestinationLinesToRequestVMInVBlank[k] = mode_lib->mp.dst_y_per_vm_vblank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13306
out->informative.misc.DestinationLinesToRequestRowInVBlank[k] = mode_lib->mp.dst_y_per_row_vblank[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13307
out->informative.misc.DestinationLinesToRequestVMInImmediateFlip[k] = mode_lib->mp.dst_y_per_vm_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13308
out->informative.misc.DestinationLinesToRequestRowInImmediateFlip[k] = mode_lib->mp.dst_y_per_row_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13309
out->informative.misc.DisplayPipeLineDeliveryTimeLuma[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13310
out->informative.misc.DisplayPipeLineDeliveryTimeChroma[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13311
out->informative.misc.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeLumaPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13312
out->informative.misc.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeChromaPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13315
out->informative.misc.WritebackAllowDRAMClockChangeEndPosition[k] = mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13316
out->informative.misc.WritebackAllowFCLKChangeEndPosition[k] = mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13317
out->informative.misc.DSCCLK_calculated[k] = mode_lib->mp.DSCCLK[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13318
out->informative.misc.BIGK_FRAGMENT_SIZE[k] = mode_lib->mp.BIGK_FRAGMENT_SIZE[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13319
out->informative.misc.PTE_BUFFER_MODE[k] = mode_lib->mp.PTE_BUFFER_MODE[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13320
out->informative.misc.DSCDelay[k] = mode_lib->mp.DSCDelay[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13321
out->informative.misc.MaxActiveDRAMClockChangeLatencySupported[k] = mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13323
if (mode_lib->mp.impacted_prefetch_margin_us[k] < out->informative.misc.LowestPrefetchMargin)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13324
out->informative.misc.LowestPrefetchMargin = mode_lib->mp.impacted_prefetch_margin_us[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13330
for (k = 0; k < out->display_config.num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13331
out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane0 = dml_get_plane_num_mcaches_plane0(mode_lib, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13332
out->informative.non_optimized_mcache_allocation[k].informative.meta_row_bytes_plane0 = dml_get_plane_mcache_row_bytes_plane0(mode_lib, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13334
for (n = 0; n < out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane0; n++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13335
out->informative.non_optimized_mcache_allocation[k].mcache_x_offsets_plane0[n] = dml_get_plane_array_mcache_offsets_plane0(mode_lib, k, n);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13336
out->informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane0[n] = k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13339
out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane1 = dml_get_plane_num_mcaches_plane1(mode_lib, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13340
out->informative.non_optimized_mcache_allocation[k].informative.meta_row_bytes_plane1 = dml_get_plane_mcache_row_bytes_plane1(mode_lib, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13342
for (n = 0; n < out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane1; n++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13343
out->informative.non_optimized_mcache_allocation[k].mcache_x_offsets_plane1[n] = dml_get_plane_array_mcache_offsets_plane1(mode_lib, k, n);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13344
out->informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane1[n] = k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
159
for (unsigned int k = 0; k < display_cfg->num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
160
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
161
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
162
switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
164
out_bpp[k] = bpc * 3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
167
out_bpp[k] = bpc * 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
170
out_bpp[k] = bpc * 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
174
out_bpp[k] = bpc * 1.5;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
177
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
178
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
180
out_bpp[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
182
DML_LOG_VERBOSE("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
183
DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
184
DML_LOG_VERBOSE("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1960
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1961
is_using_mall_for_ss[k] = (display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1962
if (is_using_mall_for_ss[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1963
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1965
DML_LOG_VERBOSE("DML::%s: k=%u, is_using_mall_for_ss = %u\n", __func__, k, is_using_mall_for_ss[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1966
DML_LOG_VERBOSE("DML::%s: k=%u, TotalSurfaceSizeInMALL = %u\n", __func__, k, TotalSurfaceSizeInMALL);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1974
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1975
if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCN * 1024 * 1024 &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1976
!is_using_mall_for_ss[k] && display_cfg->plane_descriptors[k].overrides.refresh_from_mall != dml2_refresh_from_mall_mode_override_force_disable && one_row_per_frame_fits_in_buffer[k] &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1977
(!CanAddAnotherSurfaceToMALL || SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1979
SurfaceToAddToMALL = k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1980
DML_LOG_VERBOSE("DML::%s: k=%u, UseMALLForStaticScreen = %u (dis, en, optimize)\n", __func__, k, display_cfg->plane_descriptors[k].overrides.refresh_from_mall);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
209
for (unsigned int k = 0; k < num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
210
num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
221
for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
222
pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2637
for (unsigned int k = 0; k < num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2638
mall_prefetch_sdp_overhead_factor[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2639
mall_prefetch_dram_overhead_factor[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2642
if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall) // always no data return
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2643
mall_prefetch_sdp_overhead_factor[k] = 1.25;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2644
else if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2645
mall_prefetch_sdp_overhead_factor[k] = 0.25;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2648
if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2649
mall_prefetch_dram_overhead_factor[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2652
DML_LOG_VERBOSE("DML::%s: k=%u, mall_prefetch_sdp_overhead_factor = %f\n", __func__, k, mall_prefetch_sdp_overhead_factor[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2653
DML_LOG_VERBOSE("DML::%s: k=%u, mall_prefetch_dram_overhead_factor = %f\n", __func__, k, mall_prefetch_dram_overhead_factor[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2820
unsigned int n, m, k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2833
for (k = 0; k < num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2835
DML_LOG_VERBOSE("DML::%s: plane %0d\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2836
DML_LOG_VERBOSE("DML::%s: ReadBandwidthLuma=%f\n", __func__, ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2837
DML_LOG_VERBOSE("DML::%s: ReadBandwidthChroma=%f\n", __func__, ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2838
DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor_p0=%f\n", __func__, dcc_dram_bw_nom_overhead_factor_p0[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2839
DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor_p1=%f\n", __func__, dcc_dram_bw_nom_overhead_factor_p1[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2840
DML_LOG_VERBOSE("DML::%s: mall_prefetch_dram_overhead_factor=%f\n", __func__, mall_prefetch_dram_overhead_factor[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2841
DML_LOG_VERBOSE("DML::%s: mall_prefetch_sdp_overhead_factor=%f\n", __func__, mall_prefetch_sdp_overhead_factor[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2844
sdp_overhead_factor = mall_prefetch_sdp_overhead_factor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2845
dram_overhead_factor_p0 = dcc_dram_bw_nom_overhead_factor_p0[k] * mall_prefetch_dram_overhead_factor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2846
dram_overhead_factor_p1 = dcc_dram_bw_nom_overhead_factor_p1[k] * mall_prefetch_dram_overhead_factor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2850
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2851
avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] += sdp_overhead_factor * (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) + cursor_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2852
avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] += dram_overhead_factor_p0 * ReadBandwidthLuma[k] + dram_overhead_factor_p1 * ReadBandwidthChroma[k] + cursor_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2854
avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] += sdp_overhead_factor * (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) + cursor_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2855
avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] += dram_overhead_factor_p0 * ReadBandwidthLuma[k] + dram_overhead_factor_p1 * ReadBandwidthChroma[k] + cursor_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2873
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2875
p->vm_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2876
p->dpte_group_bytes[k] = 512;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2878
p->vm_group_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2879
p->dpte_group_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2882
if (dml_is_420(p->myPipe[k].SourcePixelFormat) || p->myPipe[k].SourcePixelFormat == dml2_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2883
if ((p->myPipe[k].SourcePixelFormat == dml2_420_10 || p->myPipe[k].SourcePixelFormat == dml2_420_12) && !dml_is_vertical_rotation(p->myPipe[k].RotationAngle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2884
s->PTEBufferSizeInRequestsForLuma[k] = (p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma) / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2885
s->PTEBufferSizeInRequestsForChroma[k] = s->PTEBufferSizeInRequestsForLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2887
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2888
s->PTEBufferSizeInRequestsForChroma[k] = p->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2891
scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2892
scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2893
scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2894
scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2895
scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2896
scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2897
scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2898
scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2899
scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2900
scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2901
scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeightC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2902
scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStartC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2903
scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStartC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2906
scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2907
scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2908
scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2909
scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2910
scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2911
scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2912
scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2915
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2916
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2917
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_chroma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2918
scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2919
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2920
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowC_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2921
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_chroma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2922
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_chroma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2923
scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2924
scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2925
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2926
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2927
scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2928
scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2930
scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2931
scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2932
scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2933
scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2934
scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2935
scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2939
p->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2940
p->myPipe[k].VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2941
p->myPipe[k].VTapsChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2942
p->myPipe[k].InterlaceEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2943
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2944
p->myPipe[k].SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2945
p->myPipe[k].RotationAngle,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2946
p->myPipe[k].mirrored,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2947
p->myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2948
p->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2949
p->myPipe[k].ViewportHeightC,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2950
p->myPipe[k].ViewportXStartC,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2951
p->myPipe[k].ViewportYStartC,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2954
&p->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2955
&p->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2957
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2958
s->PTEBufferSizeInRequestsForChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2959
s->PixelPTEBytesPerRowC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2960
s->PixelPTEBytesPerRowStorageC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2962
p->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2963
p->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2964
s->dpte_row_height_chroma_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2965
s->dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2966
s->PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2969
scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2970
scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2971
scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2972
scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2973
scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2974
scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2975
scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2976
scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2977
scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2978
scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2979
scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeight;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2980
scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStart;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2981
scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStart;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2984
scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2985
scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForLuma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2986
scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2987
scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2988
scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2989
scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2990
scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchY;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2993
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2994
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2995
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_luma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2996
scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2997
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2998
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowY_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2999
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_luma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3000
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_luma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3001
scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_y[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3002
scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_y[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3003
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3004
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3005
scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3006
scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3008
scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3009
scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3010
scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3011
scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3012
scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3013
scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3017
p->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3018
p->myPipe[k].VRatio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3019
p->myPipe[k].VTaps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3020
p->myPipe[k].InterlaceEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3021
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3022
p->myPipe[k].SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3023
p->myPipe[k].RotationAngle,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3024
p->myPipe[k].mirrored,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3025
p->myPipe[k].ViewportStationary,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3026
p->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3027
p->myPipe[k].ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3028
p->myPipe[k].ViewportXStart,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3029
p->myPipe[k].ViewportYStart,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3032
&p->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3033
&p->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3036
DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes_l = %u (before hvm level)\n", __func__, k, s->vm_bytes_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3037
DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes_c = %u (before hvm level)\n", __func__, k, s->vm_bytes_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3038
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes_per_row_ub_l = %u\n", __func__, k, s->meta_row_bytes_per_row_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3039
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes_per_row_ub_c = %u\n", __func__, k, s->meta_row_bytes_per_row_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3041
p->vm_bytes[k] = (s->vm_bytes_l + s->vm_bytes_c) * (1 + 8 * s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3042
p->meta_row_bytes[k] = s->meta_row_bytes_per_row_ub_l[k] + s->meta_row_bytes_per_row_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3043
p->meta_row_bytes_per_row_ub_l[k] = s->meta_row_bytes_per_row_ub_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3044
p->meta_row_bytes_per_row_ub_c[k] = s->meta_row_bytes_per_row_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3047
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes = %u\n", __func__, k, p->meta_row_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3048
DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes = %u (after hvm level)\n", __func__, k, p->vm_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3050
if (s->PixelPTEBytesPerRowStorageY[k] <= 64 * s->PTEBufferSizeInRequestsForLuma[k] && s->PixelPTEBytesPerRowStorageC[k] <= 64 * s->PTEBufferSizeInRequestsForChroma[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3051
p->PTEBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3053
p->PTEBufferSizeNotExceeded[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3056
s->one_row_per_frame_fits_in_buffer[k] = (s->PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForLuma[k] &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3057
s->PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3059
if (p->PTEBufferSizeNotExceeded[k] == 0 || s->one_row_per_frame_fits_in_buffer[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3060
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY = %u (before hvm level)\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3061
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC = %u (before hvm level)\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3062
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowStorageY = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3063
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowStorageC = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3064
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeInRequestsForLuma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3065
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeInRequestsForChroma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3066
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded (not one_row_per_frame) = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3068
DML_LOG_VERBOSE("DML::%s: k=%u, HostVMDynamicLevels = %u\n", __func__, k, s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3069
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowY_one_row_per_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3070
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowC_one_row_per_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3071
DML_LOG_VERBOSE("DML::%s: k=%u, one_row_per_frame_fits_in_buffer = %u\n", __func__, k, s->one_row_per_frame_fits_in_buffer[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3085
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3087
if (p->display_cfg->plane_descriptors[k].overrides.hw.force_pte_buffer_mode.enable == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3088
p->PTE_BUFFER_MODE[k] = p->display_cfg->plane_descriptors[k].overrides.hw.force_pte_buffer_mode.value;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3090
p->PTE_BUFFER_MODE[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->is_using_mall_for_ss[k] || (p->display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3091
dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) || (p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes > 64);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3092
p->BIGK_FRAGMENT_SIZE[k] = (unsigned int)(math_log((float)p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes * 1024, 2) - 12);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3094
p->PTE_BUFFER_MODE[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3095
p->BIGK_FRAGMENT_SIZE[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3099
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3100
p->DCCMetaBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3102
DML_LOG_VERBOSE("DML::%s: k=%u, SurfaceSizeInMALL = %u\n", __func__, k, p->SurfaceSizeInMALL[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3103
DML_LOG_VERBOSE("DML::%s: k=%u, is_using_mall_for_ss = %u\n", __func__, k, p->is_using_mall_for_ss[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3105
p->use_one_row_for_frame[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->is_using_mall_for_ss[k] || (p->display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3106
(dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) || (p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes > 64 && dml_is_vertical_rotation(p->myPipe[k].RotationAngle));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3108
p->use_one_row_for_frame_flip[k] = p->use_one_row_for_frame[k] && !(p->display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3110
if (p->use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3111
p->dpte_row_height_luma[k] = s->dpte_row_height_luma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3112
p->dpte_row_width_luma_ub[k] = s->dpte_row_width_luma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3113
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3114
p->dpte_row_height_chroma[k] = s->dpte_row_height_chroma_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3115
p->dpte_row_width_chroma_ub[k] = s->dpte_row_width_chroma_ub_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3116
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC_one_row_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3117
p->PTEBufferSizeNotExceeded[k] = s->one_row_per_frame_fits_in_buffer[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3120
if (p->meta_row_bytes[k] <= p->DCCMetaBufferSizeBytes) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3121
p->DCCMetaBufferSizeNotExceeded[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3123
p->DCCMetaBufferSizeNotExceeded[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3126
DML_LOG_VERBOSE("DML::%s: k=%d, meta_row_bytes = %d\n", __func__, k, p->meta_row_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3127
DML_LOG_VERBOSE("DML::%s: k=%d, DCCMetaBufferSizeBytes = %d\n", __func__, k, p->DCCMetaBufferSizeBytes);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3128
DML_LOG_VERBOSE("DML::%s: k=%d, DCCMetaBufferSizeNotExceeded = %d\n", __func__, k, p->DCCMetaBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3132
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY[k] * (1 + 8 * s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3133
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC[k] * (1 + 8 * s->HostVMDynamicLevels);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3134
p->PixelPTEBytesPerRow[k] = s->PixelPTEBytesPerRowY[k] + s->PixelPTEBytesPerRowC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3135
p->dpte_row_bytes_per_row_l[k] = s->PixelPTEBytesPerRowY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3136
p->dpte_row_bytes_per_row_c[k] = s->PixelPTEBytesPerRowC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3139
if (p->use_one_row_for_frame[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3140
p->PixelPTEBytesPerRow[k] = p->PixelPTEBytesPerRow[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3144
p->use_one_row_for_frame[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3145
p->myPipe[k].SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3146
p->myPipe[k].VRatio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3147
p->myPipe[k].VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3148
p->myPipe[k].DCCEnable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3149
p->myPipe[k].HTotal / p->myPipe[k].PixelClock,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3150
s->PixelPTEBytesPerRowY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3151
s->PixelPTEBytesPerRowC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3152
p->dpte_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3153
p->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3156
p->meta_row_bytes_per_row_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3157
p->meta_row_bytes_per_row_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3158
p->meta_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3159
p->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3162
&p->dpte_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3163
&p->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3165
DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p->use_one_row_for_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3166
DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame_flip = %u\n", __func__, k, p->use_one_row_for_frame_flip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3167
DML_LOG_VERBOSE("DML::%s: k=%u, UseMALLForPStateChange = %u\n", __func__, k, p->display_cfg->plane_descriptors[k].overrides.legacy_svp_config);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3168
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_height_luma = %u\n", __func__, k, p->dpte_row_height_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3169
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p->dpte_row_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3170
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY = %u (after hvm level)\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3171
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_height_chroma = %u\n", __func__, k, p->dpte_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3172
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p->dpte_row_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3173
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC = %u (after hvm level)\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3174
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRow = %u\n", __func__, k, p->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3175
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3176
DML_LOG_VERBOSE("DML::%s: k=%u, gpuvm_enable = %u\n", __func__, k, p->display_cfg->gpuvm_enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3177
DML_LOG_VERBOSE("DML::%s: k=%u, PTE_BUFFER_MODE = %u\n", __func__, k, p->PTE_BUFFER_MODE[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3178
DML_LOG_VERBOSE("DML::%s: k=%u, BIGK_FRAGMENT_SIZE = %u\n", __func__, k, p->BIGK_FRAGMENT_SIZE[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3521
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3522
double pixel_rate_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3524
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3525
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_rate_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3527
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3529
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3532
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3533
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerSurface[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_rate_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3535
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3539
if (BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3540
DCFClkDeepSleepPerSurface[k] = math_max2(__DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3541
__DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3543
DCFClkDeepSleepPerSurface[k] = __DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3545
DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], pixel_rate_mhz / 16);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3548
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut && tdlut_bytes_to_deliver[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3549
double tdlut_required_deepsleep_dcfclk = (double) tdlut_bytes_to_deliver[k] / 64.0 / prefetch_swath_time_us[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3551
DML_LOG_VERBOSE("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3552
DML_LOG_VERBOSE("DML::%s: k=%d, tdlut_bytes_to_deliver = %d\n", __func__, k, tdlut_bytes_to_deliver[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3553
DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_swath_time_us = %f\n", __func__, k, prefetch_swath_time_us[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3554
DML_LOG_VERBOSE("DML::%s: k=%d, tdlut_required_deepsleep_dcfclk = %f\n", __func__, k, tdlut_required_deepsleep_dcfclk);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3557
if (tdlut_required_deepsleep_dcfclk > DCFClkDeepSleepPerSurface[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3558
DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], tdlut_required_deepsleep_dcfclk);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3559
DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], dispclk / 4.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3564
DML_LOG_VERBOSE("DML::%s: k=%u, PixelClock = %f\n", __func__, k, pixel_rate_mhz);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3565
DML_LOG_VERBOSE("DML::%s: k=%u, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3569
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3570
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3582
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3583
*DCFClkDeepSleep = math_max2(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3713
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3714
DML_LOG_VERBOSE("DML::%s: DPPPerSurface[%u] = %u\n", __func__, k, p->DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3744
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3745
p->full_swath_bytes_l[k] = (unsigned int)(p->swath_width_luma_ub[k] * p->BytePerPixDETY[k] * MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3746
p->full_swath_bytes_c[k] = (unsigned int)(p->swath_width_chroma_ub[k] * p->BytePerPixDETC[k] * MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3748
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, p->DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3749
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_luma_ub = %u\n", __func__, k, p->swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3750
DML_LOG_VERBOSE("DML::%s: k=%u BytePerPixDETY = %f\n", __func__, k, p->BytePerPixDETY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3751
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightY = %u\n", __func__, k, MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3752
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, p->full_swath_bytes_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3753
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_chroma_ub = %u\n", __func__, k, p->swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3754
DML_LOG_VERBOSE("DML::%s: k=%u BytePerPixDETC = %f\n", __func__, k, p->BytePerPixDETC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3755
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightC = %u\n", __func__, k, MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3756
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, p->full_swath_bytes_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3758
if (p->display_cfg->plane_descriptors[k].pixel_format == dml2_420_10) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3759
p->full_swath_bytes_l[k] = (unsigned int)(math_ceil2((double)p->full_swath_bytes_l[k], 256));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3760
p->full_swath_bytes_c[k] = (unsigned int)(math_ceil2((double)p->full_swath_bytes_c[k], 256));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3764
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3765
TotalActiveDPP = TotalActiveDPP + (p->ForceSingleDPP ? 1 : p->DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3766
if (p->DPPPerSurface[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3767
SurfaceDoingUnboundedRequest = k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3768
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format) || p->display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3769
|| p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3807
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3809
DETBufferSizeInKByteForSwathCalculation = (dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) ? 1024 : p->DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3811
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation = %u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3813
if (p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3814
p->SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3815
p->SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3816
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3817
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3819
if (p->surf_linear128_l[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3820
p->request_size_bytes_luma[k] = 128;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3822
p->request_size_bytes_luma[k] = 256;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3824
if (p->surf_linear128_c[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3825
p->request_size_bytes_chroma[k] = 128;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3827
p->request_size_bytes_chroma[k] = 256;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3829
} else if (p->full_swath_bytes_l[k] + p->full_swath_bytes_c[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3830
p->SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3831
p->SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3832
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3833
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3834
p->request_size_bytes_luma[k] = 256;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3835
p->request_size_bytes_chroma[k] = 256;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3837
} else if (p->full_swath_bytes_l[k] >= 1.5 * p->full_swath_bytes_c[k] && p->full_swath_bytes_l[k] / 2 + p->full_swath_bytes_c[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3838
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3839
p->SwathHeightC[k] = MaximumSwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3840
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3841
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3842
p->request_size_bytes_luma[k] = ((p->BytePerPixY[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3843
p->request_size_bytes_chroma[k] = 256;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3845
} else if (p->full_swath_bytes_l[k] < 1.5 * p->full_swath_bytes_c[k] && p->full_swath_bytes_l[k] + p->full_swath_bytes_c[k] / 2 <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3846
p->SwathHeightY[k] = MaximumSwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3847
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3848
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3849
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3850
p->request_size_bytes_luma[k] = 256;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3851
p->request_size_bytes_chroma[k] = ((p->BytePerPixC[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3854
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3855
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3856
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3857
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3858
p->request_size_bytes_luma[k] = ((p->BytePerPixY[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3859
p->request_size_bytes_chroma[k] = ((p->BytePerPixC[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3862
if (p->SwathHeightC[k] == 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3863
p->request_size_bytes_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3865
if ((p->full_swath_bytes_l[k] / 2 + p->full_swath_bytes_c[k] / 2 > DETBufferSizeInKByteForSwathCalculation * 1024 / 2) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3866
p->SwathWidth[k] > p->MaximumSwathWidthLuma[k] || (p->SwathHeightC[k] > 0 && p->SwathWidthChroma[k] > p->MaximumSwathWidthChroma[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3868
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l=%u\n", __func__, k, p->full_swath_bytes_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3869
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c=%u\n", __func__, k, p->full_swath_bytes_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3870
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation=%u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3871
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidth=%u\n", __func__, k, p->SwathWidth[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3872
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthLuma=%f\n", __func__, k, p->MaximumSwathWidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3873
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthChroma=%d\n", __func__, k, p->SwathWidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3874
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthChroma=%f\n", __func__, k, p->MaximumSwathWidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3875
p->ViewportSizeSupportPerSurface[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3877
p->ViewportSizeSupportPerSurface[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3880
if (p->SwathHeightC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3882
DML_LOG_VERBOSE("DML::%s: k=%u, All DET will be used for plane0\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3884
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3885
p->DETBufferSizeC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3886
} else if (RoundedUpSwathSizeBytesY[k] <= 1.5 * RoundedUpSwathSizeBytesC[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3888
DML_LOG_VERBOSE("DML::%s: k=%u, Half DET will be used for plane0, and half for plane1\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3890
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3891
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3894
DML_LOG_VERBOSE("DML::%s: k=%u, 2/3 DET will be used for plane0, and 1/3 for plane1\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3896
p->DETBufferSizeY[k] = (unsigned int)(math_floor2(p->DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3897
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 - p->DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3901
DML_LOG_VERBOSE("DML::%s: k=%u SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3902
DML_LOG_VERBOSE("DML::%s: k=%u SwathHeightC = %u\n", __func__, k, p->SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3903
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, p->full_swath_bytes_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3904
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, p->full_swath_bytes_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3905
DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesY = %u\n", __func__, k, RoundedUpSwathSizeBytesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3906
DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3907
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, p->DETBufferSizeInKByte[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3908
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3909
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeC = %u\n", __func__, k, p->DETBufferSizeC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3910
DML_LOG_VERBOSE("DML::%s: k=%u ViewportSizeSupportPerSurface = %u\n", __func__, k, p->ViewportSizeSupportPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3933
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3935
&& p->display_cfg->plane_descriptors[k].surface.dcc.enable
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3937
+ *p->CompressedBufferSizeInkByte * MAXIMUMCOMPRESSION * 1024) > TTUFIFODEPTH * (RoundedUpSwathSizeBytesY[k] + RoundedUpSwathSizeBytesC[k])))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3940
DML_LOG_VERBOSE("DML::%s: k=%u UnboundedRequestEnabled = %u\n", __func__, k, *p->UnboundedRequestEnabled);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3941
DML_LOG_VERBOSE("DML::%s: k=%u MAXIMUMCOMPRESSION = %lu\n", __func__, k, MAXIMUMCOMPRESSION);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3942
DML_LOG_VERBOSE("DML::%s: k=%u TTUFIFODEPTH = %lu\n", __func__, k, TTUFIFODEPTH);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3943
DML_LOG_VERBOSE("DML::%s: k=%u CompressedBufferSizeInkByte = %u\n", __func__, k, *p->CompressedBufferSizeInkByte);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3944
DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3945
DML_LOG_VERBOSE("DML::%s: k=%u hw_debug5 = %u\n", __func__, k, *p->hw_debug5);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
434
for (unsigned int k = 0; k < display_cfg->num_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
435
PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
436
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && ptoi_supported == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4568
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4569
const struct dml2_composition_cfg *composition = &display_cfg->plane_descriptors[k].composition;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4570
const struct dml2_surface_cfg *surface = &display_cfg->plane_descriptors[k].surface;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4573
SurfaceSizeInMALL[k] = (unsigned int)(math_min2(math_ceil2((double)surface->plane0.width, ReadBlockWidthY[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4574
math_floor2(composition->viewport.plane0.x_start + composition->viewport.plane0.width + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) -
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4575
math_floor2((double)composition->viewport.plane0.x_start, ReadBlockWidthY[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4576
math_min2(math_ceil2((double)surface->plane0.height, ReadBlockHeightY[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4577
math_floor2((double)composition->viewport.plane0.y_start + composition->viewport.plane0.height + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4578
math_floor2((double)composition->viewport.plane0.y_start, ReadBlockHeightY[k])) * BytesPerPixelY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4580
if (ReadBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4581
SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4582
math_min2(math_ceil2((double)surface->plane1.width, ReadBlockWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4583
math_floor2((double)composition->viewport.plane1.y_start + composition->viewport.plane1.width + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4584
math_floor2((double)composition->viewport.plane1.y_start, ReadBlockWidthC[k])) *
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4585
math_min2(math_ceil2((double)surface->plane1.height, ReadBlockHeightC[k]),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4586
math_floor2((double)composition->viewport.plane1.y_start + composition->viewport.plane1.height + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4587
math_floor2(composition->viewport.plane1.y_start, ReadBlockHeightC[k])) * BytesPerPixelC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4590
SurfaceSizeInMALL[k] = (unsigned int)(math_ceil2(math_min2(surface->plane0.width, composition->viewport.plane0.width + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4591
math_ceil2(math_min2(surface->plane0.height, composition->viewport.plane0.height + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4592
if (ReadBlockWidthC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4593
SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4594
math_ceil2(math_min2(surface->plane1.width, composition->viewport.plane1.width + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4595
math_ceil2(math_min2(surface->plane1.height, composition->viewport.plane1.height + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4600
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4602
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4603
TotalSurfaceSizeInMALLForSubVP += SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4604
else if (display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4605
TotalSurfaceSizeInMALLForSS += SurfaceSizeInMALL[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4759
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4760
extra_bytes = extra_bytes + (NumberOfDPP[k] * PixelChunkSizeInKByte * 1024);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4762
if (display_cfg->plane_descriptors[k].surface.dcc.enable)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4765
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4766
extra_bytes = extra_bytes + tdlut_bytes_per_group[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4771
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4773
extra_bytes = extra_bytes + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4774
extra_bytes_prefetch = extra_bytes_prefetch + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactorPrefetch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4907
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4908
l->mall_svp_prefetch_factor = (state_type == dml2_core_internal_soc_state_svp_prefetch) ? (bw_type == dml2_core_internal_bw_dram ? mall_prefetch_dram_overhead_factor[k] : mall_prefetch_sdp_overhead_factor[k]) : 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4909
l->tmp_nom_adj_factor_p0 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p0[k] : 1.0) * l->mall_svp_prefetch_factor;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4910
l->tmp_nom_adj_factor_p1 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p1[k] : 1.0) * l->mall_svp_prefetch_factor;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4911
l->tmp_pref_adj_factor_p0 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_pref_overhead_factor_p0[k] : 1.0) * l->mall_svp_prefetch_factor;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4912
l->tmp_pref_adj_factor_p1 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_pref_overhead_factor_p1[k] : 1.0) * l->mall_svp_prefetch_factor;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4914
l->adj_factor_p0 = UrgentBurstFactorLuma[k] * l->tmp_nom_adj_factor_p0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4915
l->adj_factor_p1 = UrgentBurstFactorChroma[k] * l->tmp_nom_adj_factor_p1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4916
l->adj_factor_cur = UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4917
l->adj_factor_p0_pre = UrgentBurstFactorLumaPre[k] * l->tmp_pref_adj_factor_p0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4918
l->adj_factor_p1_pre = UrgentBurstFactorChromaPre[k] * l->tmp_pref_adj_factor_p1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4919
l->adj_factor_cur_pre = UrgentBurstFactorCursorPre[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4921
bool is_phantom = dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4932
l->per_plane_flip_bw[k] = 0; // qual_row_bw
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4933
else if (!display_cfg->plane_descriptors[k].immediate_flip)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4934
l->per_plane_flip_bw[k] = NumberOfDPP[k] * (dpte_row_bw[k] + meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4937
if ((!display_cfg->plane_descriptors[k].immediate_flip && !display_cfg->hostvm_enable) || !inc_flip_bw)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4938
l->per_plane_flip_bw[k] = NumberOfDPP[k] * (dpte_row_bw[k] + meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4940
l->per_plane_flip_bw[k] = NumberOfDPP[k] * flip_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4944
l->vm_row_bw = NumberOfDPP[k] * prefetch_vmrow_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4945
l->flip_and_active_bw = l->per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l->adj_factor_p0 + ReadBandwidthChroma[k] * l->adj_factor_p1 + cursor_bw[k] * l->adj_factor_cur;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4946
l->flip_and_prefetch_bw = l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4947
l->flip_and_prefetch_bw_max = l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthMax[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4948
l->active_and_excess_bw = (ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l->tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l->tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4949
surface_required_bw[k] = math_max5(l->vm_row_bw, l->flip_and_active_bw, l->flip_and_prefetch_bw, l->active_and_excess_bw, l->flip_and_prefetch_bw_max);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4952
surface_peak_required_bw[k] = math_max2(surface_required_bw[k], surface_peak_required_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4955
DML_LOG_VERBOSE("DML::%s: k=%d, max1: vm_row_bw=%f\n", __func__, k, l->vm_row_bw);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4956
DML_LOG_VERBOSE("DML::%s: k=%d, max2: flip_and_active_bw=%f\n", __func__, k, l->flip_and_active_bw);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4957
DML_LOG_VERBOSE("DML::%s: k=%d, max3: flip_and_prefetch_bw=%f\n", __func__, k, l->flip_and_prefetch_bw);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4958
DML_LOG_VERBOSE("DML::%s: k=%d, max4: active_and_excess_bw=%f\n", __func__, k, l->active_and_excess_bw);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4959
DML_LOG_VERBOSE("DML::%s: k=%d, surface_required_bw=%f\n", __func__, k, surface_required_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4960
DML_LOG_VERBOSE("DML::%s: k=%d, surface_peak_required_bw=%f\n", __func__, k, surface_peak_required_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4963
surface_required_bw[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4966
l->required_bandwidth_mbps += surface_required_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4969
DML_LOG_VERBOSE("DML::%s: k=%d, NumberOfDPP=%d\n", __func__, k, NumberOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4970
DML_LOG_VERBOSE("DML::%s: k=%d, use_qual_row_bw=%d\n", __func__, k, use_qual_row_bw);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4971
DML_LOG_VERBOSE("DML::%s: k=%d, immediate_flip=%d\n", __func__, k, display_cfg->plane_descriptors[k].immediate_flip);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4972
DML_LOG_VERBOSE("DML::%s: k=%d, mall_svp_prefetch_factor=%f\n", __func__, k, l->mall_svp_prefetch_factor);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4973
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p0=%f\n", __func__, k, l->adj_factor_p0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4974
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p1=%f\n", __func__, k, l->adj_factor_p1);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4975
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_cur=%f\n", __func__, k, l->adj_factor_cur);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4977
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p0_pre=%f\n", __func__, k, l->adj_factor_p0_pre);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4978
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p1_pre=%f\n", __func__, k, l->adj_factor_p1_pre);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4979
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_cur_pre=%f\n", __func__, k, l->adj_factor_cur_pre);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4981
DML_LOG_VERBOSE("DML::%s: k=%d, per_plane_flip_bw=%f\n", __func__, k, l->per_plane_flip_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4982
DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_vmrow_bw=%f\n", __func__, k, prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4983
DML_LOG_VERBOSE("DML::%s: k=%d, ReadBandwidthLuma=%f\n", __func__, k, ReadBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4984
DML_LOG_VERBOSE("DML::%s: k=%d, ReadBandwidthChroma=%f\n", __func__, k, ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4985
DML_LOG_VERBOSE("DML::%s: k=%d, excess_vactive_fill_bw_l=%f\n", __func__, k, excess_vactive_fill_bw_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4986
DML_LOG_VERBOSE("DML::%s: k=%d, excess_vactive_fill_bw_c=%f\n", __func__, k, excess_vactive_fill_bw_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4987
DML_LOG_VERBOSE("DML::%s: k=%d, cursor_bw=%f\n", __func__, k, cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4989
DML_LOG_VERBOSE("DML::%s: k=%d, meta_row_bw=%f\n", __func__, k, meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4990
DML_LOG_VERBOSE("DML::%s: k=%d, dpte_row_bw=%f\n", __func__, k, dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4991
DML_LOG_VERBOSE("DML::%s: k=%d, PrefetchBandwidthLuma=%f\n", __func__, k, PrefetchBandwidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4992
DML_LOG_VERBOSE("DML::%s: k=%d, PrefetchBandwidthChroma=%f\n", __func__, k, PrefetchBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4993
DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_cursor_bw=%f\n", __func__, k, prefetch_cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4994
DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l->required_bandwidth_mbps, inc_flip_bw, is_phantom, exclude_this_plane);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4995
DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), soc_state=%s, inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l->required_bandwidth_mbps, dml2_core_internal_soc_state_type_str(state_type), inc_flip_bw, is_phantom, exclude_this_plane);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4996
DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l->required_bandwidth_mbps, inc_flip_bw, is_phantom, exclude_this_plane);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5058
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5059
if (request_size_bytes_luma[k] > max_request_size_bytes)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5060
max_request_size_bytes = request_size_bytes_luma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5061
if (request_size_bytes_chroma[k] > max_request_size_bytes)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5062
max_request_size_bytes = request_size_bytes_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5991
unsigned int i, k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6065
k = find_max_impact_plane(i, p->num_active_planes, s->accumulated_return_path_dcfclk_cycles); // plane k causes most impact to plane i
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6067
p->impacted_dst_y_pre[i] = s->accumulated_return_path_dcfclk_cycles[k]/p->estimated_dcfclk_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6068
p->impacted_dst_y_pre[i] += calculate_impacted_Tsw(k, p->num_active_planes, p->prefetch_sw_bytes, p->estimated_urg_bandwidth_required_mbps);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6072
DML_LOG_VERBOSE("DML::%s: i=%u impacted_Tpre=%f (k=%u)\n", __func__, i, p->impacted_dst_y_pre[i], k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6117
for (unsigned int k = 0; k < p->num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6118
l->unity_array[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6119
l->zero_array[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6734
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6735
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6771
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6772
double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6773
double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6774
double v_ratio = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6775
double v_ratio_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6776
s->TotalPixelBW = s->TotalPixelBW + p->DPPPerSurface[k]
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6777
* (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * v_ratio + p->SwathWidthC[k] * p->BytePerPixelDETC[k] * v_ratio_c) / (h_total / pixel_clock_mhz);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6783
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6784
double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6785
double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6786
double v_ratio = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6787
double v_ratio_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6788
double v_taps = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6789
double v_taps_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6790
double h_ratio = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6791
double h_ratio_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6794
s->LBLatencyHidingSourceLinesY[k] = (unsigned int)(math_min2((double)p->MaxLineBufferLines, math_floor2((double)p->LineBufferSize / LBBitPerPixel / ((double)p->SwathWidthY[k] / math_max2(h_ratio, 1.0)), 1)) - (v_taps - 1));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6795
s->LBLatencyHidingSourceLinesC[k] = (unsigned int)(math_min2((double)p->MaxLineBufferLines, math_floor2((double)p->LineBufferSize / LBBitPerPixel / ((double)p->SwathWidthC[k] / math_max2(h_ratio_c, 1.0)), 1)) - (v_taps_c - 1));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6798
DML_LOG_VERBOSE("DML::%s: k=%u, MaxLineBufferLines = %u\n", __func__, k, p->MaxLineBufferLines);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6799
DML_LOG_VERBOSE("DML::%s: k=%u, LineBufferSize = %u\n", __func__, k, p->LineBufferSize);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6800
DML_LOG_VERBOSE("DML::%s: k=%u, LBBitPerPixel = %f\n", __func__, k, LBBitPerPixel);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6801
DML_LOG_VERBOSE("DML::%s: k=%u, HRatio = %f\n", __func__, k, h_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6802
DML_LOG_VERBOSE("DML::%s: k=%u, VTaps = %f\n", __func__, k, v_taps);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6805
s->EffectiveLBLatencyHidingY = s->LBLatencyHidingSourceLinesY[k] / v_ratio * (h_total / pixel_clock_mhz);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6806
s->EffectiveLBLatencyHidingC = s->LBLatencyHidingSourceLinesC[k] / v_ratio_c * (h_total / pixel_clock_mhz);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6808
s->EffectiveDETBufferSizeY = p->DETBufferSizeY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6810
s->EffectiveDETBufferSizeY = s->EffectiveDETBufferSizeY + p->CompressedBufferSizeInkByte * 1024 * (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * v_ratio) / (h_total / pixel_clock_mhz) / s->TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6813
s->LinesInDETY[k] = (double)s->EffectiveDETBufferSizeY / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6814
s->LinesInDETYRoundedDownToSwath[k] = (unsigned int)(math_floor2(s->LinesInDETY[k], p->SwathHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6815
s->FullDETBufferingTimeY = s->LinesInDETYRoundedDownToSwath[k] * (h_total / pixel_clock_mhz) / v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6817
s->ActiveClockChangeLatencyHidingY = s->EffectiveLBLatencyHidingY + s->FullDETBufferingTimeY - ((double)p->DSTXAfterScaler[k] / h_total + (double)p->DSTYAfterScaler[k]) * h_total / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6820
s->ActiveClockChangeLatencyHidingY = s->ActiveClockChangeLatencyHidingY - (1.0 - 1.0 / (double)p->NumberOfActiveSurfaces) * (double)p->SwathHeightY[k] * (double)h_total / pixel_clock_mhz / v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6823
if (p->BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6824
s->LinesInDETC[k] = p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6825
s->LinesInDETCRoundedDownToSwath[k] = (unsigned int)(math_floor2(s->LinesInDETC[k], p->SwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6826
s->FullDETBufferingTimeC = s->LinesInDETCRoundedDownToSwath[k] * (h_total / pixel_clock_mhz) / v_ratio_c;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6827
s->ActiveClockChangeLatencyHidingC = s->EffectiveLBLatencyHidingC + s->FullDETBufferingTimeC - ((double)p->DSTXAfterScaler[k] / (double)h_total + (double)p->DSTYAfterScaler[k]) * (double)h_total / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6829
s->ActiveClockChangeLatencyHidingC = s->ActiveClockChangeLatencyHidingC - (1.0 - 1.0 / (double)p->NumberOfActiveSurfaces) * (double)p->SwathHeightC[k] * (double)h_total / pixel_clock_mhz / v_ratio_c;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6836
s->ActiveDRAMClockChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6837
s->ActiveFCLKChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->FCLKChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6838
s->USRRetrainingLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->USRRetrainingWatermark;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6839
s->g6_temp_read_latency_margin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->temp_read_or_ppt_watermark_us;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6842
p->VActiveLatencyHidingMargin[k] = s->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6845
p->VActiveLatencyHidingUs[k] = s->ActiveClockChangeLatencyHiding;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6847
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6849
/ ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6850
* (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6851
/ ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height * (double)h_total / pixel_clock_mhz) * 4.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6852
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6859
s->ActiveDRAMClockChangeLatencyMargin[k] = math_min2(s->ActiveDRAMClockChangeLatencyMargin[k], s->WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6860
s->ActiveFCLKChangeLatencyMargin[k] = math_min2(s->ActiveFCLKChangeLatencyMargin[k], s->WritebackFCLKChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6862
p->MaxActiveDRAMClockChangeLatencySupported[k] = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) ? 0 : (s->ActiveDRAMClockChangeLatencyMargin[k] + p->mmSOCParameters.DRAMClockChangeLatency);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6864
uclk_pstate_change_strategy = p->display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6865
reserved_vblank_time_us = (double)p->display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns / 1000;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6867
p->FCLKChangeSupport[k] = dml2_pstate_change_unsupported;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6868
if (s->ActiveFCLKChangeLatencyMargin[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6869
p->FCLKChangeSupport[k] = dml2_pstate_change_vactive;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6871
p->FCLKChangeSupport[k] = dml2_pstate_change_vblank;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6873
if (p->FCLKChangeSupport[k] == dml2_pstate_change_unsupported)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6876
p->DRAMClockChangeSupport[k] = dml2_pstate_change_unsupported;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6879
(s->ActiveDRAMClockChangeLatencyMargin[k] > 0 && reserved_vblank_time_us >= p->mmSOCParameters.DRAMClockChangeLatency))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6880
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank_and_vactive;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6881
else if (s->ActiveDRAMClockChangeLatencyMargin[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6882
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vactive;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6884
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6885
} else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_vactive && s->ActiveDRAMClockChangeLatencyMargin[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6886
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vactive;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6888
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6890
p->DRAMClockChangeSupport[k] = dml2_pstate_change_drr;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6892
p->DRAMClockChangeSupport[k] = dml2_pstate_change_mall_svp;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6894
p->DRAMClockChangeSupport[k] = dml2_pstate_change_mall_full_frame;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6896
if (p->DRAMClockChangeSupport[k] == dml2_pstate_change_unsupported)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6900
s->src_y_pstate_l = (unsigned int)(math_ceil2(s->dst_y_pstate * v_ratio, p->SwathHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6901
s->src_y_ahead_l = (unsigned int)(math_floor2(p->DETBufferSizeY[k] / p->BytePerPixelDETY[k] / p->SwathWidthY[k], p->SwathHeightY[k]) + s->LBLatencyHidingSourceLinesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6902
s->sub_vp_lines_l = s->src_y_pstate_l + s->src_y_ahead_l + p->meta_row_height_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6905
DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6906
DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6907
DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6908
DML_LOG_VERBOSE("DML::%s: k=%u, SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6909
DML_LOG_VERBOSE("DML::%s: k=%u, LBLatencyHidingSourceLinesY = %u\n", __func__, k, s->LBLatencyHidingSourceLinesY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6910
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_pstate = %u\n", __func__, k, s->dst_y_pstate);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6911
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_pstate_l = %u\n", __func__, k, s->src_y_pstate_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6912
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_ahead_l = %u\n", __func__, k, s->src_y_ahead_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6913
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_height_l = %u\n", __func__, k, p->meta_row_height_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6914
DML_LOG_VERBOSE("DML::%s: k=%u, sub_vp_lines_l = %u\n", __func__, k, s->sub_vp_lines_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6916
p->SubViewportLinesNeededInMALL[k] = s->sub_vp_lines_l;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6918
if (p->BytePerPixelDETC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6919
s->src_y_pstate_c = (unsigned int)(math_ceil2(s->dst_y_pstate * v_ratio_c, p->SwathHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6920
s->src_y_ahead_c = (unsigned int)(math_floor2(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6921
s->sub_vp_lines_c = s->src_y_pstate_c + s->src_y_ahead_c + p->meta_row_height_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6923
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6924
p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, 2 * s->sub_vp_lines_c));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6926
p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, s->sub_vp_lines_c));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6929
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, k, p->meta_row_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6930
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s->src_y_pstate_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6931
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s->src_y_ahead_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6932
DML_LOG_VERBOSE("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s->sub_vp_lines_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6938
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6939
if ((!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6940
(s->g6_temp_read_latency_margin[k] < 0)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6945
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6946
if ((!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) && ((!FoundCriticalSurface)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6947
|| ((s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency) < *p->MaxActiveFCLKChangeLatencySupported))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6949
*p->MaxActiveFCLKChangeLatencySupported = s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7319
unsigned int k;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7335
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7336
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7341
calculate_tdlut_setting_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7342
calculate_tdlut_setting_params->tdlut_width_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_width_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7343
calculate_tdlut_setting_params->tdlut_addressing_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_addressing_mode;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7346
calculate_tdlut_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7347
calculate_tdlut_setting_params->tdlut_mpc_width_flag = display_cfg->plane_descriptors[k].tdlut.tdlut_mpc_width_flag;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7348
calculate_tdlut_setting_params->is_gfx11 = dml_get_gfx_version(display_cfg->plane_descriptors[k].surface.tiling);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7351
calculate_tdlut_setting_params->tdlut_pte_bytes_per_frame = &s->tdlut_pte_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7352
calculate_tdlut_setting_params->tdlut_bytes_per_frame = &s->tdlut_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7353
calculate_tdlut_setting_params->tdlut_groups_per_2row_ub = &s->tdlut_groups_per_2row_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7354
calculate_tdlut_setting_params->tdlut_opt_time = &s->tdlut_opt_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7355
calculate_tdlut_setting_params->tdlut_drain_time = &s->tdlut_drain_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7356
calculate_tdlut_setting_params->tdlut_bytes_to_deliver = &s->tdlut_bytes_to_deliver[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7357
calculate_tdlut_setting_params->tdlut_bytes_per_group = &s->tdlut_bytes_per_group[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7400
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7401
s->impacted_dst_y_pre[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7408
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7409
s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7410
s->pixel_format[k] = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7412
s->lb_source_lines_l[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7413
mode_lib->ms.NoOfDPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7414
display_cfg->plane_descriptors[k].composition.viewport.plane0.width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7415
display_cfg->plane_descriptors[k].composition.viewport.plane0.height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7416
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7417
display_cfg->plane_descriptors[k].composition.rotation_angle);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7419
s->lb_source_lines_c[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7420
mode_lib->ms.NoOfDPP[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7421
display_cfg->plane_descriptors[k].composition.viewport.plane1.width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7422
display_cfg->plane_descriptors[k].composition.viewport.plane1.height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7423
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7424
display_cfg->plane_descriptors[k].composition.rotation_angle);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7428
mode_lib->ms.TWait[k] = CalculateTWait(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7429
display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7432
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7435
myPipe->Dppclk = mode_lib->ms.RequiredDPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7437
myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7439
myPipe->DPPPerSurface = mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7440
myPipe->ScalerEnabled = display_cfg->plane_descriptors[k].composition.scaler_info.enabled;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7441
myPipe->VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7442
myPipe->VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7443
myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7444
myPipe->VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7445
myPipe->RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7446
myPipe->mirrored = display_cfg->plane_descriptors[k].composition.mirrored;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7447
myPipe->BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7448
myPipe->BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7449
myPipe->BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7450
myPipe->BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7451
myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7452
myPipe->NumberOfCursors = display_cfg->plane_descriptors[k].cursor.num_cursors;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7453
myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7454
myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7455
myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7456
myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7457
myPipe->ODMMode = mode_lib->ms.ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7458
myPipe->SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7459
myPipe->BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7460
myPipe->BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7464
DML_LOG_VERBOSE("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7465
DML_LOG_VERBOSE("DML::%s: MaximumVStartup = %u\n", __func__, s->MaximumVStartup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7470
CalculatePrefetchSchedule_params->DSCDelay = mode_lib->ms.DSCDelay[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7476
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (unsigned int)(mode_lib->ms.SwathWidthY[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7477
CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7479
CalculatePrefetchSchedule_params->VStartup = s->MaximumVStartup[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7481
CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7483
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = display_cfg->plane_descriptors[k].dynamic_meta_data.lines_before_active_required;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7484
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = display_cfg->plane_descriptors[k].dynamic_meta_data.transmitted_bytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7488
CalculatePrefetchSchedule_params->vm_bytes = mode_lib->ms.vm_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7489
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = mode_lib->ms.DPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7490
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = mode_lib->ms.PrefetchLinesY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7491
CalculatePrefetchSchedule_params->VInitPreFillY = mode_lib->ms.PrefillY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7492
CalculatePrefetchSchedule_params->MaxNumSwathY = mode_lib->ms.MaxNumSwathY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7493
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = mode_lib->ms.PrefetchLinesC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7494
CalculatePrefetchSchedule_params->VInitPreFillC = mode_lib->ms.PrefillC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7495
CalculatePrefetchSchedule_params->MaxNumSwathC = mode_lib->ms.MaxNumSwathC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7496
CalculatePrefetchSchedule_params->swath_width_luma_ub = mode_lib->ms.swath_width_luma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7497
CalculatePrefetchSchedule_params->swath_width_chroma_ub = mode_lib->ms.swath_width_chroma_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7498
CalculatePrefetchSchedule_params->SwathHeightY = mode_lib->ms.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7499
CalculatePrefetchSchedule_params->SwathHeightC = mode_lib->ms.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7500
CalculatePrefetchSchedule_params->TWait = mode_lib->ms.TWait[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7503
CalculatePrefetchSchedule_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7504
CalculatePrefetchSchedule_params->tdlut_pte_bytes_per_frame = s->tdlut_pte_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7505
CalculatePrefetchSchedule_params->tdlut_bytes_per_frame = s->tdlut_bytes_per_frame[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7506
CalculatePrefetchSchedule_params->tdlut_opt_time = s->tdlut_opt_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7507
CalculatePrefetchSchedule_params->tdlut_drain_time = s->tdlut_drain_time[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7508
CalculatePrefetchSchedule_params->num_cursors = (display_cfg->plane_descriptors[k].cursor.cursor_width > 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7509
CalculatePrefetchSchedule_params->cursor_bytes_per_chunk = s->cursor_bytes_per_chunk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7510
CalculatePrefetchSchedule_params->cursor_bytes_per_line = s->cursor_bytes_per_line[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7511
CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7513
CalculatePrefetchSchedule_params->meta_row_bytes = mode_lib->ms.meta_row_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7514
CalculatePrefetchSchedule_params->mall_prefetch_sdp_overhead_factor = mode_lib->ms.mall_prefetch_sdp_overhead_factor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7515
CalculatePrefetchSchedule_params->impacted_dst_y_pre = s->impacted_dst_y_pre[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7516
CalculatePrefetchSchedule_params->vactive_sw_bw_l = mode_lib->ms.vactive_sw_bw_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7517
CalculatePrefetchSchedule_params->vactive_sw_bw_c = mode_lib->ms.vactive_sw_bw_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7520
CalculatePrefetchSchedule_params->DSTXAfterScaler = &s->DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7521
CalculatePrefetchSchedule_params->DSTYAfterScaler = &s->DSTYAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7522
CalculatePrefetchSchedule_params->dst_y_prefetch = &mode_lib->ms.dst_y_prefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7523
CalculatePrefetchSchedule_params->dst_y_per_vm_vblank = &mode_lib->ms.LinesForVM[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7524
CalculatePrefetchSchedule_params->dst_y_per_row_vblank = &mode_lib->ms.LinesForDPTERow[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7525
CalculatePrefetchSchedule_params->VRatioPrefetchY = &mode_lib->ms.VRatioPreY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7526
CalculatePrefetchSchedule_params->VRatioPrefetchC = &mode_lib->ms.VRatioPreC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7527
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWLuma = &mode_lib->ms.RequiredPrefetchPixelDataBWLuma[k]; // prefetch_sw_bw_l
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7528
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWChroma = &mode_lib->ms.RequiredPrefetchPixelDataBWChroma[k]; // prefetch_sw_bw_c
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7529
CalculatePrefetchSchedule_params->RequiredPrefetchBWMax = &mode_lib->ms.RequiredPrefetchBWMax[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7530
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->ms.NoTimeForDynamicMetadata[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7531
CalculatePrefetchSchedule_params->Tno_bw = &mode_lib->ms.Tno_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7532
CalculatePrefetchSchedule_params->Tno_bw_flip = &mode_lib->ms.Tno_bw_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7533
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &mode_lib->ms.prefetch_vmrow_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7537
CalculatePrefetchSchedule_params->Tvm_trips = &s->Tvm_trips[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7538
CalculatePrefetchSchedule_params->Tr0_trips = &s->Tr0_trips[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7539
CalculatePrefetchSchedule_params->Tvm_trips_flip = &s->Tvm_trips_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7540
CalculatePrefetchSchedule_params->Tr0_trips_flip = &s->Tr0_trips_flip[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7541
CalculatePrefetchSchedule_params->Tvm_trips_flip_rounded = &s->Tvm_trips_flip_rounded[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7542
CalculatePrefetchSchedule_params->Tr0_trips_flip_rounded = &s->Tr0_trips_flip_rounded[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7546
CalculatePrefetchSchedule_params->prefetch_cursor_bw = &mode_lib->ms.prefetch_cursor_bw[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7547
CalculatePrefetchSchedule_params->prefetch_sw_bytes = &s->prefetch_sw_bytes[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7548
CalculatePrefetchSchedule_params->Tpre_rounded = &s->Tpre_rounded[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7549
CalculatePrefetchSchedule_params->Tpre_oto = &s->Tpre_oto[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7550
CalculatePrefetchSchedule_params->prefetch_swath_time_us = &s->prefetch_swath_time_us[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7552
mode_lib->ms.NoTimeForPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7554
mode_lib->ms.support.PrefetchSupported &= !mode_lib->ms.NoTimeForPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7555
DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_per_vm_vblank = %f\n", __func__, k, *CalculatePrefetchSchedule_params->dst_y_per_vm_vblank);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7556
DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_per_row_vblank = %f\n", __func__, k, *CalculatePrefetchSchedule_params->dst_y_per_row_vblank);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7580
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7581
if (mode_lib->ms.dst_y_prefetch[k] < 2.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7582
|| mode_lib->ms.LinesForVM[k] >= 32.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7583
|| mode_lib->ms.LinesForDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7584
|| mode_lib->ms.NoTimeForPrefetch[k] == true
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7585
|| s->DSTYAfterScaler[k] > 8) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7587
DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_prefetch=%f (should not be < 2)\n", __func__, k, mode_lib->ms.dst_y_prefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7588
DML_LOG_VERBOSE("DML::%s: k=%d, LinesForVM=%f (should not be >= 32)\n", __func__, k, mode_lib->ms.LinesForVM[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7589
DML_LOG_VERBOSE("DML::%s: k=%d, LinesForDPTERow=%f (should not be >= 16)\n", __func__, k, mode_lib->ms.LinesForDPTERow[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7590
DML_LOG_VERBOSE("DML::%s: k=%d, DSTYAfterScaler=%d (should be <= 8)\n", __func__, k, s->DSTYAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7591
DML_LOG_VERBOSE("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib->ms.NoTimeForPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7596
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7597
if (mode_lib->ms.NoTimeForDynamicMetadata[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7603
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7604
if (mode_lib->ms.VRatioPreY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7605
mode_lib->ms.VRatioPreC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7607
DML_LOG_VERBOSE("DML::%s: k=%d VRatioPreY = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreY[k], __DML2_CALCS_MAX_VRATIO_PRE__);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7608
DML_LOG_VERBOSE("DML::%s: k=%d VRatioPreC = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreC[k], __DML2_CALCS_MAX_VRATIO_PRE__);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7620
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7623
DML_LOG_VERBOSE("DML::%s: k=%d, Calling CalculateUrgentBurstFactor (for prefetch)\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7624
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPreY=%f\n", __func__, k, mode_lib->ms.VRatioPreY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7625
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPreC=%f\n", __func__, k, mode_lib->ms.VRatioPreC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7628
&display_cfg->plane_descriptors[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7629
mode_lib->ms.swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7630
mode_lib->ms.swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7631
mode_lib->ms.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7632
mode_lib->ms.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7633
s->line_times[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7635
mode_lib->ms.VRatioPreY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7636
mode_lib->ms.VRatioPreC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7637
mode_lib->ms.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7638
mode_lib->ms.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7639
mode_lib->ms.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7640
mode_lib->ms.DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7642
&mode_lib->ms.UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7643
&mode_lib->ms.UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7644
&mode_lib->ms.NotEnoughUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7649
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7650
mode_lib->ms.final_flip_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7711
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7712
if (mode_lib->ms.NotEnoughUrgentLatencyHidingPre[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7714
DML_LOG_VERBOSE("DML::%s: k=%d, NotEnoughUrgentLatencyHidingPre=%d\n", __func__, k, mode_lib->ms.NotEnoughUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7767
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7768
if (display_cfg->plane_descriptors[k].immediate_flip) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7769
s->per_pipe_flip_bytes[k] = get_pipe_flip_bytes(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7771
mode_lib->ms.vm_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7772
mode_lib->ms.DPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7773
mode_lib->ms.meta_row_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7775
s->per_pipe_flip_bytes[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7777
mode_lib->ms.TotImmediateFlipBytes += s->per_pipe_flip_bytes[k] * mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7781
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7784
display_cfg->plane_descriptors[k].immediate_flip,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7787
s->Tvm_trips_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7788
s->Tr0_trips_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7789
s->Tvm_trips_flip_rounded[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7790
s->Tr0_trips_flip_rounded[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7792
mode_lib->ms.vm_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7793
mode_lib->ms.DPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7796
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7797
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7798
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7799
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7800
mode_lib->ms.Tno_bw_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7801
mode_lib->ms.dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7802
mode_lib->ms.dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7803
mode_lib->ms.use_one_row_for_frame_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7806
s->per_pipe_flip_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7807
mode_lib->ms.meta_row_bytes[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7808
s->meta_row_height_luma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7809
s->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7810
mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7813
&mode_lib->ms.dst_y_per_vm_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7814
&mode_lib->ms.dst_y_per_row_flip[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7815
&mode_lib->ms.final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7816
&mode_lib->ms.ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7870
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7871
if (display_cfg->plane_descriptors[k].immediate_flip == true && mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7961
unsigned int k, m, n;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8004
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8005
DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8029
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8030
if (display_cfg->plane_descriptors[k].composition.scaler_info.enabled == false
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8031
&& (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8032
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio != 1.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8033
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8034
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio != 1.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8035
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8037
} else if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps < 1.0 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps > 8.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8038
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps < 1.0 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps > 8.0
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8039
|| (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps > 1.0 && (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8040
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio > mode_lib->ip.max_hscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8041
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio > mode_lib->ip.max_vscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8042
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8043
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8044
|| (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8045
&& (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps < 1 || display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps > 8 ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8046
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps < 1 || display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps > 8 ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8047
(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps > 1 && display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps % 2 == 1) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8048
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio > mode_lib->ip.max_hscl_ratio ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8049
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio > mode_lib->ip.max_vscl_ratio ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8050
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8051
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8058
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8059
if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear && dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8064
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8066
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8067
display_cfg->plane_descriptors[k].surface.tiling,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8068
display_cfg->plane_descriptors[k].surface.plane0.pitch,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8069
display_cfg->plane_descriptors[k].surface.plane1.pitch,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8072
&mode_lib->ms.BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8073
&mode_lib->ms.BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8074
&mode_lib->ms.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8075
&mode_lib->ms.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8076
&mode_lib->ms.Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8077
&mode_lib->ms.Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8078
&mode_lib->ms.Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8079
&mode_lib->ms.Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8080
&mode_lib->ms.MacroTileHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8081
&mode_lib->ms.MacroTileHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8082
&mode_lib->ms.MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8083
&mode_lib->ms.MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8084
&mode_lib->ms.surf_linear128_l[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8085
&mode_lib->ms.surf_linear128_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8089
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8090
if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8091
mode_lib->ms.SwathWidthYSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8092
mode_lib->ms.SwathWidthCSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane1.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8094
mode_lib->ms.SwathWidthYSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8095
mode_lib->ms.SwathWidthCSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8099
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8100
mode_lib->ms.vactive_sw_bw_l[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8101
mode_lib->ms.vactive_sw_bw_c[k] = mode_lib->ms.SwathWidthCSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8103
mode_lib->ms.cursor_bw[k] = display_cfg->plane_descriptors[k].cursor.num_cursors * display_cfg->plane_descriptors[k].cursor.cursor_width *
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8104
display_cfg->plane_descriptors[k].cursor.cursor_bpp / 8.0 / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8107
DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthLuma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8108
DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthChroma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * math_ceil2(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio / 2.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8109
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_l = %f\n", __func__, k, mode_lib->ms.vactive_sw_bw_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8110
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_c = %f\n", __func__, k, mode_lib->ms.vactive_sw_bw_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8115
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8116
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8117
mode_lib->ms.WriteBandwidth[k][0] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8118
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8119
/ (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8120
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8121
/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 8.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8122
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8123
mode_lib->ms.WriteBandwidth[k][0] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8124
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8125
/ (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8126
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8127
/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 4.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8129
mode_lib->ms.WriteBandwidth[k][0] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8135
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8136
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8137
(mode_lib->ms.WriteBandwidth[k][0] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / ((double)mode_lib->soc.qos_parameters.writeback.base_latency_us))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8145
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8146
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8147
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio > mode_lib->ip.writeback_max_hscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8148
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio > mode_lib->ip.writeback_max_vscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8149
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio < mode_lib->ip.writeback_min_hscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8150
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio < mode_lib->ip.writeback_min_vscl_ratio
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8151
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > (unsigned int) mode_lib->ip.writeback_max_hscl_taps
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8152
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps > (unsigned int) mode_lib->ip.writeback_max_vscl_taps
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8153
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio > (unsigned int)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8154
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio > (unsigned int)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8155
|| (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8158
if (2.0 * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height * (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps - 1) * 57 > mode_lib->ip.writeback_line_buffer_buffer_size) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8164
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8166
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8167
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8168
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8169
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8172
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8173
display_cfg->plane_descriptors[k].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8174
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8175
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8176
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8177
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8179
&mode_lib->ms.PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8180
&mode_lib->ms.PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8181
&mode_lib->ms.MinDPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8185
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8186
if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8188
} else if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelC[k] > 0 && display_cfg->plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // horz video
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8190
} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelC[k] > 0 && display_cfg->plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // vert video
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8192
} else if (display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) { // rgbe + alpha
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8194
} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelY[k] == 8 && display_cfg->plane_descriptors[k].surface.dcc.enable == true) { // vert 64bpp
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8200
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8218
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8219
(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio, 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8220
if (mode_lib->ms.BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8223
mode_lib->ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8224
(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio, 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8227
mode_lib->ms.MaximumSwathWidthLuma[k] = math_min2(s->MaximumSwathWidthSupportLuma, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8228
mode_lib->ms.MaximumSwathWidthChroma[k] = math_min2(s->MaximumSwathWidthSupportChroma, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8230
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthLuma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8231
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthSupportLuma=%u\n", __func__, k, s->MaximumSwathWidthSupportLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8232
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthInLineBufferLuma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8234
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthChroma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8235
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthSupportChroma=%u\n", __func__, k, s->MaximumSwathWidthSupportChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8236
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthInLineBufferChroma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8241
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8242
if (display_cfg->plane_descriptors[k].cursor.num_cursors > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8243
if (display_cfg->plane_descriptors[k].cursor.cursor_bpp == 64 && mode_lib->ip.cursor_64bpp_support == false)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8250
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8253
unsigned int alignment_l = mode_lib->ms.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8255
if (mode_lib->ms.surf_linear128_l[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8258
mode_lib->ms.support.AlignedYPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.plane0.pitch, display_cfg->plane_descriptors[k].surface.plane0.width), alignment_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8259
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8260
unsigned int alignment_c = mode_lib->ms.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8262
if (mode_lib->ms.surf_linear128_c[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8264
mode_lib->ms.support.AlignedCPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.plane1.pitch, display_cfg->plane_descriptors[k].surface.plane1.width), alignment_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8266
mode_lib->ms.support.AlignedCPitch[k] = display_cfg->plane_descriptors[k].surface.plane1.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8269
if (mode_lib->ms.support.AlignedYPitch[k] > display_cfg->plane_descriptors[k].surface.plane0.pitch ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8270
mode_lib->ms.support.AlignedCPitch[k] > display_cfg->plane_descriptors[k].surface.plane1.pitch) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8273
DML_LOG_VERBOSE("DML::%s: k=%u AlignedYPitch = %d\n", __func__, k, mode_lib->ms.support.AlignedYPitch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8274
DML_LOG_VERBOSE("DML::%s: k=%u PitchY = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.pitch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8275
DML_LOG_VERBOSE("DML::%s: k=%u AlignedCPitch = %d\n", __func__, k, mode_lib->ms.support.AlignedCPitch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8276
DML_LOG_VERBOSE("DML::%s: k=%u PitchC = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane1.pitch);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8277
DML_LOG_VERBOSE("DML::%s: k=%u PitchSupport = %d\n", __func__, k, mode_lib->ms.support.PitchSupport);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8282
if (mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8283
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8284
display_cfg->plane_descriptors[k].surface.plane0.width), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8286
if (mode_lib->ms.support.AlignedDCCMetaPitchY[k] > display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8289
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8290
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8291
display_cfg->plane_descriptors[k].surface.plane1.width), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8293
if (mode_lib->ms.support.AlignedDCCMetaPitchC[k] > display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8297
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8298
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8304
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8305
if (display_cfg->plane_descriptors[k].composition.viewport.plane0.width > display_cfg->plane_descriptors[k].surface.plane0.width ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8306
display_cfg->plane_descriptors[k].composition.viewport.plane0.height > display_cfg->plane_descriptors[k].surface.plane0.height) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8309
DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth = %ld\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.width);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8310
DML_LOG_VERBOSE("DML::%s: k=%u SurfaceWidthY = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.width);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8311
DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight = %ld\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.height);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8312
DML_LOG_VERBOSE("DML::%s: k=%u SurfaceHeightY = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.height);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8313
DML_LOG_VERBOSE("DML::%s: k=%u ViewportExceedsSurface = %d\n", __func__, k, mode_lib->ms.support.ViewportExceedsSurface);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8316
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8317
if (display_cfg->plane_descriptors[k].composition.viewport.plane1.width > display_cfg->plane_descriptors[k].surface.plane1.width ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8318
display_cfg->plane_descriptors[k].composition.viewport.plane1.height > display_cfg->plane_descriptors[k].surface.plane1.height) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8386
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8388
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8389
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8391
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8392
mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8394
if (s->PixelClockBackEnd[k] > 4800) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8395
mode_lib->ms.support.NumberOfDSCSlices[k] = (unsigned int)(math_ceil2(s->PixelClockBackEnd[k] / 600, 4));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8396
} else if (s->PixelClockBackEnd[k] > 2400) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8397
mode_lib->ms.support.NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8398
} else if (s->PixelClockBackEnd[k] > 1200) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8399
mode_lib->ms.support.NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8400
} else if (s->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8401
mode_lib->ms.support.NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8403
mode_lib->ms.support.NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8407
mode_lib->ms.support.NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8412
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8413
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8414
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8415
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8422
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8423
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8433
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8434
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8435
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8436
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8443
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8444
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8458
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8459
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8460
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8461
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8462
s->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8463
s->OutputBpp[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8465
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8466
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_rate,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8467
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_layout,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8470
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8471
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_lane_count,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8472
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8475
&mode_lib->ms.RequiresDSC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8476
&mode_lib->ms.RequiresFEC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8477
&mode_lib->ms.OutputBpp[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8478
&mode_lib->ms.OutputType[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8479
&mode_lib->ms.OutputRate[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8480
&mode_lib->ms.RequiredSlots[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8482
if (s->OutputBpp[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8483
s->OutputBpp[k] = mode_lib->ms.OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8486
if (mode_lib->ms.RequiresDSC[k] == false) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8487
mode_lib->ms.ODMMode[k] = s->ODMModeNoDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8488
mode_lib->ms.RequiredDISPCLKPerSurface[k] = s->RequiredDISPCLKPerSurfaceNoDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8493
mode_lib->ms.ODMMode[k] = s->ODMModeDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8494
mode_lib->ms.RequiredDISPCLKPerSurface[k] = s->RequiredDISPCLKPerSurfaceDSC;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8500
DML_LOG_VERBOSE("DML::%s: k=%d RequiresDSC = %d\n", __func__, k, mode_lib->ms.RequiresDSC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8501
DML_LOG_VERBOSE("DML::%s: k=%d ODMMode = %d\n", __func__, k, mode_lib->ms.ODMMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8506
if (mode_lib->ms.RequiresDSC[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8508
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8509
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8510
mode_lib->ms.support.DSCSlicesODMModeSupported = ((mode_lib->ms.support.NumberOfDSCSlices[k] % 2) == 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8511
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8512
mode_lib->ms.support.DSCSlicesODMModeSupported = (mode_lib->ms.support.NumberOfDSCSlices[k] == 12);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8513
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8514
mode_lib->ms.support.DSCSlicesODMModeSupported = ((mode_lib->ms.support.NumberOfDSCSlices[k] % 4) == 0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8517
DML_LOG_VERBOSE("DML::%s: k=%d Invalid dsc num_slices and ODM mode setting\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8518
DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8519
DML_LOG_VERBOSE("DML::%s: k=%d ODMMode = %d\n", __func__, k, mode_lib->ms.ODMMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8524
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8525
mode_lib->ms.support.NumberOfDSCSlices[k] = 2 * (unsigned int)math_ceil2(mode_lib->ms.support.NumberOfDSCSlices[k] / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8526
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8527
mode_lib->ms.support.NumberOfDSCSlices[k] = 12;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8528
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8529
mode_lib->ms.support.NumberOfDSCSlices[k] = 4 * (unsigned int)math_ceil2(mode_lib->ms.support.NumberOfDSCSlices[k] / 4.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8533
mode_lib->ms.support.NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8538
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8539
if (mode_lib->ip.imall_supported && display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8543
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8544
mode_lib->ms.MPCCombine[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8545
mode_lib->ms.NoOfDPP[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8546
mode_lib->ms.NoOfOPP[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8548
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8549
mode_lib->ms.MPCCombine[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
855
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8550
mode_lib->ms.NoOfDPP[k] = 4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8551
mode_lib->ms.NoOfOPP[k] = 4;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8552
} else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8553
mode_lib->ms.MPCCombine[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8554
mode_lib->ms.NoOfDPP[k] = 3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8555
mode_lib->ms.NoOfOPP[k] = 3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8556
} else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8557
mode_lib->ms.MPCCombine[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8558
mode_lib->ms.NoOfDPP[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8559
mode_lib->ms.NoOfOPP[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
856
if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8560
} else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8561
mode_lib->ms.MPCCombine[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8562
mode_lib->ms.NoOfDPP[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8563
} else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8564
mode_lib->ms.MPCCombine[k] = false;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8565
mode_lib->ms.NoOfDPP[k] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8566
if (!mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
857
SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8570
if ((mode_lib->ms.MinDPPCLKUsingSingleDPP[k] > mode_lib->ms.max_dppclk_freq_mhz) || !mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8571
mode_lib->ms.MPCCombine[k] = true;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8572
mode_lib->ms.NoOfDPP[k] = 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8576
DML_LOG_VERBOSE("DML::%s: k=%d, NoOfDPP = %d\n", __func__, k, mode_lib->ms.NoOfDPP[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8582
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8583
mode_lib->ms.TotalNumberOfActiveDPP += mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8584
mode_lib->ms.TotalNumberOfActiveOPP += mode_lib->ms.NoOfOPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
859
SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8593
for (k = 0; k < (unsigned int)mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8594
if (mode_lib->ms.NoOfDPP[k] == 1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8600
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8601
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8603
CalculateWriteBackDISPCLK(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8604
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8605
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8606
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8607
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8608
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8609
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8610
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8611
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8617
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8618
mode_lib->ms.RequiredDISPCLK = math_max2(mode_lib->ms.RequiredDISPCLK, mode_lib->ms.RequiredDISPCLKPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
862
DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth=%lu\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.width);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8622
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8623
mode_lib->ms.RequiredDPPCLK[k] = mode_lib->ms.MinDPPCLKUsingSingleDPP[k] / mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8624
mode_lib->ms.GlobalDPPCLK = math_max2(mode_lib->ms.GlobalDPPCLK, mode_lib->ms.RequiredDPPCLK[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
863
DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight=%lu\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.height);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8637
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8638
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8639
if (!s->stream_visited[display_cfg->plane_descriptors[k].stream_index]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
864
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8640
s->stream_visited[display_cfg->plane_descriptors[k].stream_index] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8642
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8646
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8648
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
866
MainSurfaceODMMode = ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8671
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8672
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_disabled == false &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8673
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8674
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) && mode_lib->ms.OutputBpp[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8689
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
869
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8690
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8691
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8692
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8695
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8698
if (((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr2 ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8699
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr3) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8700
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_dp && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_edp) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8701
((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr10 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr13p5 ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8702
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr20) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8703
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_dp2p0))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8718
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8719
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8720
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8729
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_dp && (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_split_1to2 ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8730
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to2 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to4))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8733
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to2 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_lane_count < 2) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8734
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to4 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_lane_count < 4))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8740
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8741
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8742
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8743
mode_lib->ms.RequiredDTBCLK[k] = RequiredDTBCLK(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8744
mode_lib->ms.RequiresDSC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8745
s->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8746
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8747
mode_lib->ms.OutputBpp[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8748
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8749
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8750
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8751
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_rate,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8752
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_layout);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8754
if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_ss_clocks_khz.dtbclk / 1000)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8763
mode_lib->ms.RequiredDTBCLK[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8768
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8769
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8770
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8771
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8772
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8773
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8775
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_444) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8777
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8783
DML_LOG_VERBOSE("DML::%s: k=%u, RequiresDSC = %u\n", __func__, k, mode_lib->ms.RequiresDSC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8785
if (mode_lib->ms.RequiresDSC[k] == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8788
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
879
SwathWidthY[k] = (unsigned int)(math_min2((double)SwathWidthSingleDPPY[k], math_round((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active / odm_hactive_factor * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio)));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8790
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8792
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8795
mode_lib->ms.required_dscclk_freq_mhz[k] = s->PixelClockBackEnd[k] / s->PixelClockBackEndFactor / (double)s->DSCFormatFactor;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8796
if (mode_lib->ms.required_dscclk_freq_mhz[k] > mode_lib->ms.max_dscclk_freq_mhz) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
880
} else if (DPPPerSurface[k] == 2) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8801
DML_LOG_VERBOSE("DML::%s: k=%u, PixelClockBackEnd = %f\n", __func__, k, s->PixelClockBackEnd[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8802
DML_LOG_VERBOSE("DML::%s: k=%u, required_dscclk_freq_mhz = %f\n", __func__, k, mode_lib->ms.required_dscclk_freq_mhz[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8803
DML_LOG_VERBOSE("DML::%s: k=%u, DSCFormatFactor = %u\n", __func__, k, s->DSCFormatFactor);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8804
DML_LOG_VERBOSE("DML::%s: k=%u, DSCCLKRequiredMoreThanSupported = %u\n", __func__, k, mode_lib->ms.support.DSCCLKRequiredMoreThanSupported);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
881
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8816
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8817
if (mode_lib->ms.RequiresDSC[k] == true && !s->stream_visited[display_cfg->plane_descriptors[k].stream_index]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8820
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8822
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8824
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8827
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active > s->NumDSCUnitRequired * (unsigned int)mode_lib->ip.maximum_pixels_per_line_per_dsc_unit)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
883
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8831
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 4 * s->NumDSCUnitRequired)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8834
s->stream_visited[display_cfg->plane_descriptors[k].stream_index] = 1;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8843
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8844
mode_lib->ms.DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.RequiresDSC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8845
mode_lib->ms.ODMMode[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8847
s->OutputBpp[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8848
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8849
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8850
mode_lib->ms.support.NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8851
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8852
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8853
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8854
s->PixelClockBackEnd[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
887
DML_LOG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
888
DML_LOG_VERBOSE("DML::%s: k=%u HRatio=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8886
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8887
mode_lib->ms.SurfaceSizeInMALL[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
889
DML_LOG_VERBOSE("DML::%s: k=%u MainSurfaceODMMode=%u\n", __func__, k, MainSurfaceODMMode);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
890
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthSingleDPPY=%u\n", __func__, k, SwathWidthSingleDPPY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
891
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthY=%u\n", __func__, k, SwathWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8912
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8913
if (display_cfg->plane_descriptors[k].surface.dcc.enable == true) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8914
mode_lib->ms.TotalNumberOfDCCActiveDPP = mode_lib->ms.TotalNumberOfDCCActiveDPP + mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8918
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8919
s->SurfParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8920
s->SurfParameters[k].DPPPerSurface = mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8921
s->SurfParameters[k].RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8922
s->SurfParameters[k].ViewportHeight = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8923
s->SurfParameters[k].ViewportHeightC = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8924
s->SurfParameters[k].BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8925
s->SurfParameters[k].BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8926
s->SurfParameters[k].BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8927
s->SurfParameters[k].BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8928
s->SurfParameters[k].BlockWidthY = mode_lib->ms.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8929
s->SurfParameters[k].BlockHeightY = mode_lib->ms.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
893
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8930
s->SurfParameters[k].BlockWidthC = mode_lib->ms.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8931
s->SurfParameters[k].BlockHeightC = mode_lib->ms.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8932
s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8933
s->SurfParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8934
s->SurfParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8935
s->SurfParameters[k].SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8936
s->SurfParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8937
s->SurfParameters[k].BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8938
s->SurfParameters[k].BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8939
s->SurfParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ip.ptoi_supported;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
894
SwathWidthC[k] = SwathWidthY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8940
s->SurfParameters[k].VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8941
s->SurfParameters[k].VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8942
s->SurfParameters[k].VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8943
s->SurfParameters[k].VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8944
s->SurfParameters[k].PitchY = display_cfg->plane_descriptors[k].surface.plane0.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8945
s->SurfParameters[k].PitchC = display_cfg->plane_descriptors[k].surface.plane1.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8946
s->SurfParameters[k].ViewportStationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8947
s->SurfParameters[k].ViewportXStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8948
s->SurfParameters[k].ViewportYStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8949
s->SurfParameters[k].ViewportXStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
895
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8950
s->SurfParameters[k].ViewportYStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8951
s->SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = display_cfg->plane_descriptors[k].overrides.hw.force_one_row_for_frame;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8952
s->SurfParameters[k].SwathHeightY = mode_lib->ms.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8953
s->SurfParameters[k].SwathHeightC = mode_lib->ms.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8955
s->SurfParameters[k].DCCMetaPitchY = display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8956
s->SurfParameters[k].DCCMetaPitchC = display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
897
SwathWidthC[k] = SwathWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
898
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
902
SwathWidthY[k] = SwathWidthSingleDPPY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
903
SwathWidthC[k] = SwathWidthSingleDPPC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9031
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9032
if (mode_lib->ms.PTEBufferSizeNotExceeded[k] == false)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9035
if (mode_lib->ms.DCCMetaBufferSizeNotExceeded[k] == false)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9039
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, mode_lib->ms.PTEBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9040
DML_LOG_VERBOSE("DML::%s: k=%u, DCCMetaBufferSizeNotExceeded = %u\n", __func__, k, mode_lib->ms.DCCMetaBufferSizeNotExceeded[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
906
req_width_horz_y = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
907
req_width_horz_c = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
909
if (surf_linear128_l[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9116
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9117
double line_time_us = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
912
if (surf_linear128_c[k])
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9120
if (display_cfg->plane_descriptors[k].cursor.num_cursors > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9122
display_cfg->plane_descriptors[k].cursor.cursor_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9123
display_cfg->plane_descriptors[k].cursor.cursor_bpp,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9126
&s->cursor_lines_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9127
&s->cursor_bytes_per_line[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9128
&s->cursor_bytes_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9129
&s->cursor_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9133
display_cfg->plane_descriptors[k].cursor.cursor_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9134
s->cursor_bytes_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9135
s->cursor_lines_per_chunk[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9140
&mode_lib->ms.UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9144
mode_lib->ms.UrgentBurstFactorCursorPre[k] = mode_lib->ms.UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9147
DML_LOG_VERBOSE("DML::%s: k=%d, Calling CalculateUrgentBurstFactor\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9148
DML_LOG_VERBOSE("DML::%s: k=%d, VRatio=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9149
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioChroma=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
915
surface_width_ub_l = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane0.width, req_width_horz_y);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9153
&display_cfg->plane_descriptors[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9154
mode_lib->ms.swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9155
mode_lib->ms.swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9156
mode_lib->ms.SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9157
mode_lib->ms.SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
916
surface_height_ub_l = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane0.height, Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9160
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9161
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9162
mode_lib->ms.BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9163
mode_lib->ms.BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9164
mode_lib->ms.DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9165
mode_lib->ms.DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9168
&mode_lib->ms.UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9169
&mode_lib->ms.UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
917
surface_width_ub_c = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane1.width, req_width_horz_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9170
&mode_lib->ms.NotEnoughUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9172
mode_lib->ms.NotEnoughUrgentLatencyHiding[k] = mode_lib->ms.NotEnoughUrgentLatencyHiding[k] || cursor_not_enough_urgent_latency_hiding;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
918
surface_height_ub_c = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane1.height, Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9193
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9194
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9195
mode_lib->ms.WritebackDelayTime[k] = mode_lib->soc.qos_parameters.writeback.base_latency_us + CalculateWriteBackDelay(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9196
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9197
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9198
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9199
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
920
DML_LOG_VERBOSE("DML::%s: k=%u surface_width_ub_l=%u\n", __func__, k, surface_width_ub_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9200
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9201
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9202
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9203
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->ms.RequiredDISPCLK;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9205
mode_lib->ms.WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
921
DML_LOG_VERBOSE("DML::%s: k=%u surface_height_ub_l=%u\n", __func__, k, surface_height_ub_l);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9210
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9211
bool isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9212
s->MaximumVStartup[k] = CalculateMaxVStartup(
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9215
&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9216
mode_lib->ms.WritebackDelayTime[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9217
mode_lib->ms.MaxVStartupLines[k] = (isInterlaceTiming ? (2 * s->MaximumVStartup[k]) : s->MaximumVStartup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
922
DML_LOG_VERBOSE("DML::%s: k=%u surface_width_ub_c=%u\n", __func__, k, surface_width_ub_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9221
DML_LOG_VERBOSE("DML::%s: k=%u, MaximumVStartup = %u\n", __func__, k, s->MaximumVStartup[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9226
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9227
s->ImmediateFlipRequired = s->ImmediateFlipRequired || display_cfg->plane_descriptors[k].immediate_flip;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
923
DML_LOG_VERBOSE("DML::%s: k=%u surface_height_ub_c=%u\n", __func__, k, surface_height_ub_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9231
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9234
((display_cfg->hostvm_enable == true || display_cfg->plane_descriptors[k].immediate_flip == true) &&
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9235
(display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame || dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9239
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
924
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_y=%u\n", __func__, k, req_width_horz_y);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9241
((display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable || display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_auto) && (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))) ||
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9242
((display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_disable || display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_auto) && (display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9249
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
925
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_c=%u\n", __func__, k, req_width_horz_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9250
if (display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9252
if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9256
unsigned long long refresh_rate = (unsigned long long) ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz * 1000 /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9257
(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9258
(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
926
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockWidthY=%u\n", __func__, k, Read256BytesBlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9263
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
927
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockHeightY=%u\n", __func__, k, Read256BytesBlockHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
928
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockWidthC=%u\n", __func__, k, Read256BytesBlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
929
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockHeightC=%u\n", __func__, k, Read256BytesBlockHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
930
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_y=%u\n", __func__, k, req_width_horz_y);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9303
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9306
outstanding_latency_us = (mode_lib->soc.max_outstanding_reqs * mode_lib->ms.support.request_size_bytes_luma[k]
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
931
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_c=%u\n", __func__, k, req_width_horz_c);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
932
DML_LOG_VERBOSE("DML::%s: k=%u ViewportStationary=%u\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.stationary);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9320
DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_luma = %d\n", __func__, k, mode_lib->ms.support.request_size_bytes_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9321
DML_LOG_VERBOSE("DML::%s: k=%d, outstanding_latency_us = %f (luma)\n", __func__, k, outstanding_latency_us);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9325
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x && mode_lib->ms.BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9326
outstanding_latency_us = (mode_lib->soc.max_outstanding_reqs * mode_lib->ms.support.request_size_bytes_chroma[k]
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
933
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9337
DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_chroma = %d\n", __func__, k, mode_lib->ms.support.request_size_bytes_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9338
DML_LOG_VERBOSE("DML::%s: k=%d, outstanding_latency_us = %f (chroma)\n", __func__, k, outstanding_latency_us);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9345
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9346
mode_lib->ms.mall_prefetch_sdp_overhead_factor[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9347
mode_lib->ms.mall_prefetch_dram_overhead_factor[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9348
mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9349
mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p0[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
935
req_per_swath_ub_l[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9350
mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9351
mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p1[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9354
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9355
calculate_mcache_setting_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
936
req_per_swath_ub_c[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9361
calculate_mcache_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9363
calculate_mcache_setting_params->source_format = display_cfg->plane_descriptors[k].pixel_format;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9364
calculate_mcache_setting_params->surf_vert = dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9365
calculate_mcache_setting_params->vp_stationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9366
calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9367
calculate_mcache_setting_params->imall_enable = mode_lib->ip.imall_supported && display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9369
calculate_mcache_setting_params->vp_start_x_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
937
if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9370
calculate_mcache_setting_params->vp_start_y_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9371
calculate_mcache_setting_params->full_vp_width_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9372
calculate_mcache_setting_params->full_vp_height_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9373
calculate_mcache_setting_params->blk_width_l = mode_lib->ms.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9374
calculate_mcache_setting_params->blk_height_l = mode_lib->ms.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9375
calculate_mcache_setting_params->vmpg_width_l = s->vmpg_width_y[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9376
calculate_mcache_setting_params->vmpg_height_l = s->vmpg_height_y[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9377
calculate_mcache_setting_params->full_swath_bytes_l = s->full_swath_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9378
calculate_mcache_setting_params->bytes_per_pixel_l = mode_lib->ms.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
938
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9380
calculate_mcache_setting_params->vp_start_x_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.x_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9381
calculate_mcache_setting_params->vp_start_y_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9382
calculate_mcache_setting_params->full_vp_width_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9383
calculate_mcache_setting_params->full_vp_height_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9384
calculate_mcache_setting_params->blk_width_c = mode_lib->ms.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9385
calculate_mcache_setting_params->blk_height_c = mode_lib->ms.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9386
calculate_mcache_setting_params->vmpg_width_c = s->vmpg_width_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9387
calculate_mcache_setting_params->vmpg_height_c = s->vmpg_height_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9388
calculate_mcache_setting_params->full_swath_bytes_c = s->full_swath_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9389
calculate_mcache_setting_params->bytes_per_pixel_c = mode_lib->ms.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
939
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9392
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_l = &mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9393
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_l = &mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p0[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9394
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_c = &mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9395
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_c = &mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p1[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9397
calculate_mcache_setting_params->num_mcaches_l = &mode_lib->ms.num_mcaches_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9398
calculate_mcache_setting_params->mcache_row_bytes_l = &mode_lib->ms.mcache_row_bytes_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9399
calculate_mcache_setting_params->mcache_row_bytes_per_channel_l = &mode_lib->ms.mcache_row_bytes_per_channel_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
940
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9400
calculate_mcache_setting_params->mcache_offsets_l = mode_lib->ms.mcache_offsets_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9401
calculate_mcache_setting_params->mcache_shift_granularity_l = &mode_lib->ms.mcache_shift_granularity_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9403
calculate_mcache_setting_params->num_mcaches_c = &mode_lib->ms.num_mcaches_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9404
calculate_mcache_setting_params->mcache_row_bytes_c = &mode_lib->ms.mcache_row_bytes_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9405
calculate_mcache_setting_params->mcache_row_bytes_per_channel_c = &mode_lib->ms.mcache_row_bytes_per_channel_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9406
calculate_mcache_setting_params->mcache_offsets_c = mode_lib->ms.mcache_offsets_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9407
calculate_mcache_setting_params->mcache_shift_granularity_c = &mode_lib->ms.mcache_shift_granularity_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9409
calculate_mcache_setting_params->mall_comb_mcache_l = &mode_lib->ms.mall_comb_mcache_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
941
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_width_ub_l, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start + SwathWidthY[k] + req_width_horz_y - 1, req_width_horz_y) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start, req_width_horz_y)));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9410
calculate_mcache_setting_params->mall_comb_mcache_c = &mode_lib->ms.mall_comb_mcache_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9411
calculate_mcache_setting_params->lc_comb_mcache = &mode_lib->ms.lc_comb_mcache[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
943
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_width_ub_l, math_ceil2((double)SwathWidthY[k] - 1, req_width_horz_y) + req_width_horz_y));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
945
req_per_swath_ub_l[k] = swath_width_luma_ub[k] / req_width_horz_y;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
947
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
948
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9481
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9482
if (mode_lib->ms.NotEnoughUrgentLatencyHiding[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9484
DML_LOG_VERBOSE("DML::%s: k=%u NotEnoughUrgentLatencyHiding set\n", __func__, k);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
949
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_width_ub_c, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start + SwathWidthC[k] + req_width_horz_c - 1, req_width_horz_c) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start, req_width_horz_c)));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
951
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_width_ub_c, math_ceil2((double)SwathWidthC[k] - 1, req_width_horz_c) + req_width_horz_c));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
953
req_per_swath_ub_c[k] = swath_width_chroma_ub[k] / req_width_horz_c;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
955
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
958
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
959
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9598
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9599
mode_lib->ms.support.MPCCombineEnable[k] = mode_lib->ms.MPCCombine[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9600
mode_lib->ms.support.DPPPerSurface[k] = mode_lib->ms.NoOfDPP[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9603
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9604
mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMMode[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9605
mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9606
mode_lib->ms.support.FECEnabled[k] = mode_lib->ms.RequiresFEC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9607
mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9608
mode_lib->ms.support.OutputType[k] = mode_lib->ms.OutputType[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9609
mode_lib->ms.support.OutputRate[k] = mode_lib->ms.OutputRate[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
961
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9612
DML_LOG_VERBOSE("DML::%s: k=%d, ODMMode = %u\n", __func__, k, mode_lib->ms.support.ODMMode[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9613
DML_LOG_VERBOSE("DML::%s: k=%d, DSCEnabled = %u\n", __func__, k, mode_lib->ms.support.DSCEnabled[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
962
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_height_ub_l, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start, Read256BytesBlockHeightY[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9639
for (unsigned int k = 0; k < in_out_params->in_display_cfg->num_planes; k++)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
964
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_height_ub_l, math_ceil2((double)SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9640
DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, in_out_params->in_display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
966
req_per_swath_ub_l[k] = swath_width_luma_ub[k] / Read256BytesBlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
967
if (BytePerPixC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9672
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9673
double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9676
DML_LOG_VERBOSE("DML::%s: k=%u : HRatio = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9677
DML_LOG_VERBOSE("DML::%s: k=%u : VRatio = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9678
DML_LOG_VERBOSE("DML::%s: k=%u : HRatioChroma = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9679
DML_LOG_VERBOSE("DML::%s: k=%u : VRatioChroma = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
968
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9680
DML_LOG_VERBOSE("DML::%s: k=%u : VRatioPrefetchY = %f\n", __func__, k, VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9681
DML_LOG_VERBOSE("DML::%s: k=%u : VRatioPrefetchC = %f\n", __func__, k, VRatioPrefetchC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9682
DML_LOG_VERBOSE("DML::%s: k=%u : swath_width_luma_ub = %u\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9683
DML_LOG_VERBOSE("DML::%s: k=%u : swath_width_chroma_ub = %u\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9684
DML_LOG_VERBOSE("DML::%s: k=%u : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9685
DML_LOG_VERBOSE("DML::%s: k=%u : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9686
DML_LOG_VERBOSE("DML::%s: k=%u : DPPPerSurface = %u\n", __func__, k, cfg_support_info->plane_support_info[k].dpps_used);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9687
DML_LOG_VERBOSE("DML::%s: k=%u : pixel_clock_mhz = %f\n", __func__, k, pixel_clock_mhz);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9688
DML_LOG_VERBOSE("DML::%s: k=%u : Dppclk = %f\n", __func__, k, Dppclk[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
969
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_height_ub_c, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start, Read256BytesBlockHeightC[k])));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9690
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9691
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9693
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9696
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9697
DisplayPipeLineDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9699
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9700
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9702
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9706
if (VRatioPrefetchY[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9707
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9709
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
971
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_height_ub_c, math_ceil2((double)SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9712
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9713
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9715
if (VRatioPrefetchC[k] <= 1) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9716
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_clock_mhz;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9718
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9722
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9723
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9724
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9725
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9729
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
973
req_per_swath_ub_c[k] = swath_width_chroma_ub[k] / Read256BytesBlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9731
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9732
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub_l[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9733
if (BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9734
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9735
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9737
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9738
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub_c[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9741
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9742
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9743
DML_LOG_VERBOSE("DML::%s: k=%u : req_per_swath_ub_l = %d\n", __func__, k, req_per_swath_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9744
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9745
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9746
DML_LOG_VERBOSE("DML::%s: k=%u : req_per_swath_ub_c = %d\n", __func__, k, req_per_swath_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
975
swath_width_chroma_ub[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9771
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9772
p->DST_Y_PER_PTE_ROW_NOM_L[k] = p->dpte_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9773
if (p->BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9774
p->DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9776
p->DST_Y_PER_PTE_ROW_NOM_C[k] = p->dpte_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9778
p->DST_Y_PER_META_ROW_NOM_L[k] = p->meta_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9779
if (p->BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9780
p->DST_Y_PER_META_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9782
p->DST_Y_PER_META_ROW_NOM_C[k] = p->meta_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9786
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9787
if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true && p->mrq_present) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9788
meta_chunk_width = p->MetaChunkSize * 1024 * 256 / p->BytePerPixelY[k] / p->meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9789
min_meta_chunk_width = p->MinMetaChunkSizeBytes * 256 / p->BytePerPixelY[k] / p->meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
979
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_luma_ub=%u\n", __func__, k, swath_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9790
meta_chunk_per_row_int = p->meta_row_width[k] / meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9791
meta_row_remainder = p->meta_row_width[k] % meta_chunk_width;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9792
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9793
meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_width[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9795
meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_height[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
980
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_chroma_ub=%u\n", __func__, k, swath_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9802
p->TimePerMetaChunkNominal[k] = p->meta_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio *
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9803
p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9804
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9805
p->TimePerMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9806
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9807
p->TimePerMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9808
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9809
if (p->BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
981
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightY=%u\n", __func__, k, MaximumSwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9810
p->TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9811
p->TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9812
p->TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9814
meta_chunk_width_chroma = p->MetaChunkSize * 1024 * 256 / p->BytePerPixelC[k] / p->meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9815
min_meta_chunk_width_chroma = p->MinMetaChunkSizeBytes * 256 / p->BytePerPixelC[k] / p->meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9816
meta_chunk_per_row_int_chroma = (unsigned int)((double)p->meta_row_width_chroma[k] / meta_chunk_width_chroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9817
meta_row_remainder_chroma = p->meta_row_width_chroma[k] % meta_chunk_width_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9818
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9819
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - p->meta_req_width_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
982
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightC=%u\n", __func__, k, MaximumSwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9821
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - p->meta_req_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9828
p->TimePerChromaMetaChunkNominal[k] = p->meta_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9829
p->TimePerChromaMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
983
DML_LOG_VERBOSE("DML::%s: k=%u req_per_swath_ub_l=%u\n", __func__, k, req_per_swath_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9830
p->TimePerChromaMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9833
p->TimePerMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9834
p->TimePerMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9835
p->TimePerMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9836
p->TimePerChromaMetaChunkNominal[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9837
p->TimePerChromaMetaChunkVBlank[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9838
p->TimePerChromaMetaChunkFlip[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
984
DML_LOG_VERBOSE("DML::%s: k=%u req_per_swath_ub_c=%u\n", __func__, k, req_per_swath_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9842
DML_LOG_VERBOSE("DML::%s: k=%d, DST_Y_PER_META_ROW_NOM_L = %f\n", __func__, k, p->DST_Y_PER_META_ROW_NOM_L[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9843
DML_LOG_VERBOSE("DML::%s: k=%d, DST_Y_PER_META_ROW_NOM_C = %f\n", __func__, k, p->DST_Y_PER_META_ROW_NOM_C[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9844
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkNominal = %f\n", __func__, k, p->TimePerMetaChunkNominal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9845
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkVBlank = %f\n", __func__, k, p->TimePerMetaChunkVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9846
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkFlip = %f\n", __func__, k, p->TimePerMetaChunkFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9847
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkNominal = %f\n", __func__, k, p->TimePerChromaMetaChunkNominal[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9848
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkVBlank = %f\n", __func__, k, p->TimePerChromaMetaChunkVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9849
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkFlip = %f\n", __func__, k, p->TimePerChromaMetaChunkFlip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9853
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9854
p->DST_Y_PER_PTE_ROW_NOM_L[k] = p->dpte_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9855
if (p->BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9856
p->DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9858
p->DST_Y_PER_PTE_ROW_NOM_C[k] = p->dpte_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9862
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9863
pixel_clock_mhz = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9865
if (p->display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9866
p->time_per_tdlut_group[k] = 2 * p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / p->tdlut_groups_per_2row_ub[k];
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9868
p->time_per_tdlut_group[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9870
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_tdlut_group = %f\n", __func__, k, p->time_per_tdlut_group[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9873
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9874
dpte_group_width_luma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeY[k] * p->PixelPTEReqWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9876
dpte_group_width_luma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeY[k] * p->PixelPTEReqHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9878
if (p->use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9879
dpte_groups_per_row_luma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_luma_ub[k] / (double)dpte_group_width_luma / 2.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9881
dpte_groups_per_row_luma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_luma_ub[k] / (double)dpte_group_width_luma, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9886
DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p->use_one_row_for_frame[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9887
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_bytes = %u\n", __func__, k, p->dpte_group_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9888
DML_LOG_VERBOSE("DML::%s: k=%u, PTERequestSizeY = %u\n", __func__, k, p->PTERequestSizeY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9889
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEReqWidthY = %u\n", __func__, k, p->PixelPTEReqWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9890
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEReqHeightY = %u\n", __func__, k, p->PixelPTEReqHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9891
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p->dpte_row_width_luma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9892
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_width_luma = %u\n", __func__, k, dpte_group_width_luma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9893
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_groups_per_row_luma_ub = %u\n", __func__, k, dpte_groups_per_row_luma_ub);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9895
p->time_per_pte_group_nom_luma[k] = p->DST_Y_PER_PTE_ROW_NOM_L[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9896
p->time_per_pte_group_vblank_luma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9897
p->time_per_pte_group_flip_luma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9898
if (p->BytePerPixelC[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9899
p->time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9900
p->time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9901
p->time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9903
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9904
dpte_group_width_chroma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeC[k] * p->PixelPTEReqWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9906
dpte_group_width_chroma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeC[k] * p->PixelPTEReqHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9909
if (p->use_one_row_for_frame[k]) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9910
dpte_groups_per_row_chroma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_chroma_ub[k] / (double)dpte_group_width_chroma / 2.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9912
dpte_groups_per_row_chroma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_chroma_ub[k] / (double)dpte_group_width_chroma, 1.0));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9917
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p->dpte_row_width_chroma_ub[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9918
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_width_chroma = %u\n", __func__, k, dpte_group_width_chroma);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9919
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_groups_per_row_chroma_ub = %u\n", __func__, k, dpte_groups_per_row_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9921
p->time_per_pte_group_nom_chroma[k] = p->DST_Y_PER_PTE_ROW_NOM_C[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9922
p->time_per_pte_group_vblank_chroma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9923
p->time_per_pte_group_flip_chroma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9926
p->time_per_pte_group_nom_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9927
p->time_per_pte_group_vblank_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9928
p->time_per_pte_group_flip_luma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9929
p->time_per_pte_group_nom_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9930
p->time_per_pte_group_vblank_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9931
p->time_per_pte_group_flip_chroma[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9934
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_row_vblank = %f\n", __func__, k, p->dst_y_per_row_vblank[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9935
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_row_flip = %f\n", __func__, k, p->dst_y_per_row_flip[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9937
DML_LOG_VERBOSE("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_L = %f\n", __func__, k, p->DST_Y_PER_PTE_ROW_NOM_L[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9938
DML_LOG_VERBOSE("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_C = %f\n", __func__, k, p->DST_Y_PER_PTE_ROW_NOM_C[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9939
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_nom_luma = %f\n", __func__, k, p->time_per_pte_group_nom_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9940
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_vblank_luma = %f\n", __func__, k, p->time_per_pte_group_vblank_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9941
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_flip_luma = %f\n", __func__, k, p->time_per_pte_group_flip_luma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9942
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_nom_chroma = %f\n", __func__, k, p->time_per_pte_group_nom_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9943
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_vblank_chroma = %f\n", __func__, k, p->time_per_pte_group_vblank_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9944
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_flip_chroma = %f\n", __func__, k, p->time_per_pte_group_flip_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9982
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9983
double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9984
bool dcc_mrq_enable = display_cfg->plane_descriptors[k].surface.dcc.enable && mrq_present;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9986
DML_LOG_VERBOSE("DML::%s: k=%u, dcc_mrq_enable = %u\n", __func__, k, dcc_mrq_enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9987
DML_LOG_VERBOSE("DML::%s: k=%u, vm_group_bytes = %u\n", __func__, k, vm_group_bytes[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9988
DML_LOG_VERBOSE("DML::%s: k=%u, dpde0_bytes_per_frame_ub_l = %u\n", __func__, k, dpde0_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9989
DML_LOG_VERBOSE("DML::%s: k=%u, dpde0_bytes_per_frame_ub_c = %u\n", __func__, k, dpde0_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9990
DML_LOG_VERBOSE("DML::%s: k=%d, meta_pte_bytes_per_frame_ub_l = %d\n", __func__, k, meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9991
DML_LOG_VERBOSE("DML::%s: k=%d, meta_pte_bytes_per_frame_ub_c = %d\n", __func__, k, meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9996
num_group_per_lower_vm_stage += (unsigned int) math_ceil2((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9998
if (BytePerPixelC[k] > 0)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9999
num_group_per_lower_vm_stage += (unsigned int) math_ceil2((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
339
for (unsigned int k = 0; k < display_cfg->num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
340
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
341
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
342
switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
344
out_bpp[k] = bpc * 3;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
347
out_bpp[k] = bpc * 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
350
out_bpp[k] = bpc * 2;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
354
out_bpp[k] = bpc * 1.5;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
357
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
358
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
360
out_bpp[k] = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
363
DML_LOG_VERBOSE("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
364
DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
365
DML_LOG_VERBOSE("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
391
for (unsigned int k = 0; k < num_planes; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
392
num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
405
for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
406
pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1295
int i = 0, j = 0, k = 0;
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1320
for (k = 0; k < MAX_PIPES; k++) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1323
if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
1324
current_pipe_context = &context->res_ctx.pipe_ctx[k];
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
449
uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
498
for (k = 0; k < 16; k++) {
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
499
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
500
hw_points += (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
504
for (k = 0; k < (region_end - region_start); k++) {
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
505
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
506
start_index = (region_start + k + MAX_LOW_POINT) *
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
566
k = 0;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
568
if (seg_distr[k] != -1) {
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
569
regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
571
regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
573
k++;
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
576
if (seg_distr[k] != -1)
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
577
regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
315
uint32_t i, j, k;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
349
for (k = 0; k < dc->res_pool->pipe_count; k++) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
350
if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
351
context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
353
pipe_counted[k] = 1;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
358
for (k = 0; k < dc->res_pool->pipe_count; k++) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
359
if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
360
context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
361
pipe_segments[k] = plane_segments / pipe_plane_count;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2698
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2742
k = 0;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2748
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2754
&adev->pm.dpm.ps[i], k,
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2756
k++;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1945
u32 k = dte_data->k;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1954
for (i = 0; i < k; i++) {
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
2586
if (dte_data->k <= 0)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
2595
table_size = dte_data->k;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3371
u32 k, a, ah, al;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3377
k = (100 * fh) / fl;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3378
t1 = (t * (k - 100));
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5883
u8 i, j, k;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5894
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5895
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5897
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5905
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5906
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5908
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5910
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5919
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5920
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5921
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5929
for(k = 0; k < table->num_entries; k++)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5930
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5932
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7317
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7364
k = 0;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7370
if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7376
&adev->pm.dpm.ps[i], k,
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7378
k++;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h
342
u32 k;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5364
uint32_t i, j, k;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5374
for (k = 0; k < watermarks->num_wm_sets; k++) {
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5375
if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 &&
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5376
dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 &&
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5377
dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 &&
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5378
dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) {
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5380
table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5386
table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id);
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2586
uint8_t i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2600
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2601
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2603
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2612
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2613
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2615
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2618
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2627
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2628
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2629
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2640
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2641
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2643
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
724
int i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
752
for (k = 0; k < SMU7_DTE_SINKS; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
753
dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
754
dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1858
int i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1895
for (k = 0; k < SMU71_DTE_SINKS; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1896
dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1897
dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2513
uint8_t i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2527
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2528
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2530
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2539
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2540
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2542
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2545
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2555
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2556
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2557
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2568
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2569
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2571
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
438
int i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
463
for (k = 0; k < SMU74_DTE_SINKS; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
464
table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
465
table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1835
int i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1859
for (k = 0; k < SMU72_DTE_SINKS; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1860
dpm_table->BAPMTI_R[i][j][k] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1862
dpm_table->BAPMTI_RC[i][j][k] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2977
uint8_t i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2992
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2993
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2995
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3004
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3005
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3007
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3010
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3019
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3020
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3021
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3031
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3032
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3034
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1449
int i, j, k;
drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1474
for (k = 0; k < SMU75_DTE_SINKS; k++) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1475
table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1476
table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
780
int inst, j, k, idx;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
787
for_each_inst(k, inst_mask) {
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
789
inst = GET_INST(VCN, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
812
for_each_inst(k, inst_mask) {
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
813
inst = GET_INST(GC, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2572
int ret, inst, i, j, k, idx;
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2612
for_each_inst(k, inst_mask) {
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2614
inst = GET_INST(VCN, k);
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2641
for_each_inst(k, inst_mask) {
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2642
inst = GET_INST(GC, k);
drivers/gpu/drm/drm_edid.c
3238
BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
drivers/gpu/drm/drm_edid.c
3240
return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
drivers/gpu/drm/exynos/exynos_drm_gsc.c
798
int i, j, k, sc_ratio;
drivers/gpu/drm/exynos/exynos_drm_gsc.c
817
for (k = 0; k < GSC_COEF_DEPTH; k++)
drivers/gpu/drm/exynos/exynos_drm_gsc.c
819
GSC_HCOEF(i, j, k));
drivers/gpu/drm/exynos/exynos_drm_gsc.c
824
int i, j, k, sc_ratio;
drivers/gpu/drm/exynos/exynos_drm_gsc.c
843
for (k = 0; k < GSC_COEF_DEPTH; k++)
drivers/gpu/drm/exynos/exynos_drm_gsc.c
845
GSC_VCOEF(i, j, k));
drivers/gpu/drm/i915/display/intel_dp.c
668
int i = 0, j = 0, k = 0;
drivers/gpu/drm/i915/display/intel_dp.c
672
if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
drivers/gpu/drm/i915/display/intel_dp.c
673
return k;
drivers/gpu/drm/i915/display/intel_dp.c
674
common_rates[k] = source_rates[i];
drivers/gpu/drm/i915/display/intel_dp.c
675
++k;
drivers/gpu/drm/i915/display/intel_dp.c
684
return k;
drivers/gpu/drm/i915/display/intel_hdcp.c
121
int k;
drivers/gpu/drm/i915/display/intel_hdcp.c
126
data->k = 0;
drivers/gpu/drm/i915/display/intel_hdcp.c
143
data->streams[data->k].stream_id =
drivers/gpu/drm/i915/display/intel_hdcp.c
145
data->k++;
drivers/gpu/drm/i915/display/intel_hdcp.c
153
if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0))
drivers/gpu/drm/i915/display/intel_hdcp.c
160
for (k = 0; k < data->k; k++)
drivers/gpu/drm/i915/display/intel_hdcp.c
161
data->streams[k].stream_type =
drivers/gpu/drm/i915/display/intel_hdcp.c
1714
msgs.stream_manage.k = cpu_to_be16(data->k);
drivers/gpu/drm/i915/display/intel_hdcp.c
1716
for (i = 0; i < data->k; i++) {
drivers/gpu/drm/i915/display/intel_hdcp.c
1721
streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
drivers/gpu/drm/i915/display/intel_hdcp.c
177
data->k = 1;
drivers/gpu/drm/i915/display/intel_hdcp.c
1908
data->k = 0;
drivers/gpu/drm/i915/display/intel_hdcp.c
2139
data->k = 0;
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
478
cmd_size = struct_size(verify_mprime_in, streams, data->k);
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
499
array_size(data->k, sizeof(*data->streams)));
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
501
verify_mprime_in->k = cpu_to_be16(data->k);
drivers/gpu/drm/i915/display/intel_lt_phy.c
1820
int i, j, k;
drivers/gpu/drm/i915/display/intel_lt_phy.c
1837
for (j = 3, k = 0; j >= 0; j--, k++)
drivers/gpu/drm/i915/display/intel_lt_phy.c
1840
crtc_state->dpll_hw_state.ltpll.data[i][k],
drivers/gpu/drm/i915/display/intel_lt_phy.c
2236
int i, j, k;
drivers/gpu/drm/i915/display/intel_lt_phy.c
2251
for (j = 3, k = 0; j >= 0; j--, k++)
drivers/gpu/drm/i915/display/intel_lt_phy.c
2252
pll_state->data[i][k] =
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
250
#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
34
#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1066
int i, j, k, tmp, maxregcount = 0;
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1070
for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) {
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1071
if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0)
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1074
tmp = guc_cap_list_num_regs(guc->capture, i, j, k);
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1609
int i, j, k;
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1614
for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) {
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
1615
cache = &gc->ads_cache[i][j][k];
drivers/gpu/drm/i915/selftests/intel_memory_region.c
1317
int i, j, k;
drivers/gpu/drm/i915/selftests/intel_memory_region.c
1324
for (k = 0; k < ARRAY_SIZE(types); ++k) {
drivers/gpu/drm/i915/selftests/intel_memory_region.c
1329
types[k]);
drivers/gpu/drm/imagination/pvr_cccb.c
199
struct rogue_fwif_kccb_cmd_kick_data *k)
drivers/gpu/drm/imagination/pvr_cccb.c
201
k->context_fw_addr = ctx_fw_addr;
drivers/gpu/drm/imagination/pvr_cccb.c
202
k->client_woff_update = cccb->write_offset;
drivers/gpu/drm/imagination/pvr_cccb.c
203
k->client_wrap_mask_update = cccb->wrap_mask;
drivers/gpu/drm/imagination/pvr_cccb.c
209
&k->cleanup_ctl_fw_addr[k->num_cleanup_ctl++]);
drivers/gpu/drm/imagination/pvr_rogue_fwif.h
1971
#define ROGUE_FWIF_GET_DELTA_OSTIME_NS(delta_cr, k) \
drivers/gpu/drm/imagination/pvr_rogue_fwif.h
1972
(((delta_cr) * (k)) >> ROGUE_FWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT)
drivers/gpu/drm/lima/lima_vm.c
256
int i, j, k;
drivers/gpu/drm/lima/lima_vm.c
273
for (k = 0; k < LIMA_PAGE_ENT_NUM; k++) {
drivers/gpu/drm/lima/lima_vm.c
277
printk(KERN_INFO " pt %03x:%08x\n", k, pte);
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
1735
int k;
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
1740
for (k = 0; k < indent; k++)
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
1852
int k;
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
1854
for (k = 0; k < count; index++, offset++, k++) {
drivers/gpu/drm/msm/adreno/adreno_device.c
59
for (int k = 0; info->chip_ids[k]; k++)
drivers/gpu/drm/msm/adreno/adreno_device.c
60
if (info->chip_ids[k] == chip_id)
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
169
u32 i, j, k;
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
191
for (k = 0; k < ARRAY_SIZE(freq_list); k++) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
197
core_clk = div_u64(freq_list[k],
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
198
ratio_list[k / sz_band] * clks_pll_div *
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
213
if (freq_list[k] >= min_freq &&
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
214
freq_list[k] <= max_freq) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
217
if (freq_list[k] <= freq_optimal) {
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
218
freq_optimal = freq_list[k];
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
219
optimal_index = k;
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
321
int i, j, k;
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
330
for (k = 0; k < 2; k++) {
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
331
rs[k] = max((int64_t)rs[k], id2);
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
334
struct filter_params *p = &fparams[k][j];
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
340
p->ki3r*i*i*i) * rs[k]
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
344
p->ki3rf*i*i*i) * flicker * rs[k];
drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
346
(*filters[k])[j][i] = (c + id5/2) >> 39
drivers/gpu/drm/nouveau/nouveau_dp.c
115
for (int k = outp->dp.rate_nr; k > j; k--)
drivers/gpu/drm/nouveau/nouveau_dp.c
116
outp->dp.rate[k] = outp->dp.rate[k - 1];
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
41
int i, j, k;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
62
for (k = 0; k < 4; k++)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
66
calc_bias(struct nvkm_fb *fb, int k, int i, int j)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
70
nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >>
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
78
calc_ref(struct nvkm_fb *fb, int l, int k, int i)
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
83
int m = (l >> (8 * i) & 0xff) + calc_bias(fb, k, i, j);
drivers/gpu/drm/panel/panel-himax-hx8279.c
898
int i, j, k, x;
drivers/gpu/drm/panel/panel-himax-hx8279.c
918
k = HX8279_PG_DGAMMA_NUM_LO_BYTES + i;
drivers/gpu/drm/panel/panel-himax-hx8279.c
922
gamma_high_bits[0] = FIELD_GET(HX8279_DGAMMA_DGMA1_HI, component[k]);
drivers/gpu/drm/panel/panel-himax-hx8279.c
923
gamma_high_bits[1] = FIELD_GET(HX8279_DGAMMA_DGMA2_HI, component[k]);
drivers/gpu/drm/panel/panel-himax-hx8279.c
924
gamma_high_bits[2] = FIELD_GET(HX8279_DGAMMA_DGMA3_HI, component[k]);
drivers/gpu/drm/panel/panel-himax-hx8279.c
925
gamma_high_bits[3] = FIELD_GET(HX8279_DGAMMA_DGMA4_HI, component[k]);
drivers/gpu/drm/radeon/btc_dpm.c
1890
u8 i, j, k;
drivers/gpu/drm/radeon/btc_dpm.c
1899
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/btc_dpm.c
1900
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/btc_dpm.c
1902
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/radeon/btc_dpm.c
1912
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/btc_dpm.c
1913
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/btc_dpm.c
1915
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/btc_dpm.c
1917
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/radeon/btc_dpm.c
1928
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/btc_dpm.c
1929
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/btc_dpm.c
1931
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/ci_dpm.c
409
int i, j, k;
drivers/gpu/drm/radeon/ci_dpm.c
4290
u8 i, j, k;
drivers/gpu/drm/radeon/ci_dpm.c
4301
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4302
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ci_dpm.c
4303
((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/radeon/ci_dpm.c
4312
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4313
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ci_dpm.c
4314
(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/ci_dpm.c
4316
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/radeon/ci_dpm.c
4325
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4326
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ci_dpm.c
4327
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
drivers/gpu/drm/radeon/ci_dpm.c
4338
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4339
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ci_dpm.c
4340
(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/ci_dpm.c
437
for (k = 0; k < SMU7_DTE_SINKS; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
438
dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
drivers/gpu/drm/radeon/ci_dpm.c
439
dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
drivers/gpu/drm/radeon/ci_dpm.c
4487
u8 i, k;
drivers/gpu/drm/radeon/ci_dpm.c
4502
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4503
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
drivers/gpu/drm/radeon/ci_dpm.c
4504
(table->mc_reg_table_entry[k].mclk_max == 137500))
drivers/gpu/drm/radeon/ci_dpm.c
4505
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4506
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
drivers/gpu/drm/radeon/ci_dpm.c
4511
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4512
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
drivers/gpu/drm/radeon/ci_dpm.c
4513
(table->mc_reg_table_entry[k].mclk_max == 137500))
drivers/gpu/drm/radeon/ci_dpm.c
4514
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4515
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
drivers/gpu/drm/radeon/ci_dpm.c
4520
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4521
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
drivers/gpu/drm/radeon/ci_dpm.c
4522
(table->mc_reg_table_entry[k].mclk_max == 137500))
drivers/gpu/drm/radeon/ci_dpm.c
4523
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4524
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
drivers/gpu/drm/radeon/ci_dpm.c
4529
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4530
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
drivers/gpu/drm/radeon/ci_dpm.c
4531
(table->mc_reg_table_entry[k].mclk_max == 137500))
drivers/gpu/drm/radeon/ci_dpm.c
4532
table->mc_reg_table_entry[k].mc_data[i] = 0;
drivers/gpu/drm/radeon/ci_dpm.c
4536
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4537
if (table->mc_reg_table_entry[k].mclk_max == 125000)
drivers/gpu/drm/radeon/ci_dpm.c
4538
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4539
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
drivers/gpu/drm/radeon/ci_dpm.c
4541
else if (table->mc_reg_table_entry[k].mclk_max == 137500)
drivers/gpu/drm/radeon/ci_dpm.c
4542
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4543
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
drivers/gpu/drm/radeon/ci_dpm.c
4548
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ci_dpm.c
4549
if (table->mc_reg_table_entry[k].mclk_max == 125000)
drivers/gpu/drm/radeon/ci_dpm.c
4550
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4551
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
drivers/gpu/drm/radeon/ci_dpm.c
4553
else if (table->mc_reg_table_entry[k].mclk_max == 137500)
drivers/gpu/drm/radeon/ci_dpm.c
4554
table->mc_reg_table_entry[k].mc_data[i] =
drivers/gpu/drm/radeon/ci_dpm.c
4555
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
drivers/gpu/drm/radeon/ci_dpm.c
5492
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/radeon/ci_dpm.c
5545
k = 0;
drivers/gpu/drm/radeon/ci_dpm.c
5551
if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/radeon/ci_dpm.c
5557
&rdev->pm.dpm.ps[i], k,
drivers/gpu/drm/radeon/ci_dpm.c
5559
k++;
drivers/gpu/drm/radeon/cik.c
5783
u32 i, j, k;
drivers/gpu/drm/radeon/cik.c
5789
for (k = 0; k < rdev->usec_timeout; k++) {
drivers/gpu/drm/radeon/cik.c
5799
for (k = 0; k < rdev->usec_timeout; k++) {
drivers/gpu/drm/radeon/cik.c
6549
u32 i, j, k, active_cu_number = 0;
drivers/gpu/drm/radeon/cik.c
6558
for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
drivers/gpu/drm/radeon/evergreen.c
4162
u32 dws, data, i, j, k, reg_num;
drivers/gpu/drm/radeon/evergreen.c
4317
for (k = 0; k < reg_num; k++) {
drivers/gpu/drm/radeon/evergreen.c
4318
data = cs_data[i].section[j].extent[k];
drivers/gpu/drm/radeon/evergreen.c
4319
dst_ptr[reg_list_blk_index + k] = cpu_to_le32(data);
drivers/gpu/drm/radeon/kv_dpm.c
2433
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/radeon/kv_dpm.c
2479
k = 0;
drivers/gpu/drm/radeon/kv_dpm.c
2485
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/radeon/kv_dpm.c
2491
&rdev->pm.dpm.ps[i], k,
drivers/gpu/drm/radeon/kv_dpm.c
2493
k++;
drivers/gpu/drm/radeon/ni_dpm.c
2718
u8 i, j, k;
drivers/gpu/drm/radeon/ni_dpm.c
2729
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/radeon/ni_dpm.c
2730
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ni_dpm.c
2732
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/radeon/ni_dpm.c
2740
for(k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/ni_dpm.c
2741
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ni_dpm.c
2743
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/ni_dpm.c
2745
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/radeon/ni_dpm.c
2755
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/radeon/ni_dpm.c
2756
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/ni_dpm.c
2758
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/r600_dpm.c
221
u32 k, a, ah, al;
drivers/gpu/drm/radeon/r600_dpm.c
227
k = (100 * fh) / fl;
drivers/gpu/drm/radeon/r600_dpm.c
228
t1 = (t * (k - 100));
drivers/gpu/drm/radeon/radeon_atombios.c
530
int i, j, k, path_size, device_support;
drivers/gpu/drm/radeon/radeon_atombios.c
648
for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
drivers/gpu/drm/radeon/radeon_atombios.c
649
u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
drivers/gpu/drm/radeon/radeon_atombios.c
653
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
drivers/gpu/drm/radeon/radeon_atombios.c
679
for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
drivers/gpu/drm/radeon/radeon_atombios.c
680
u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
drivers/gpu/drm/radeon/radeon_atombios.c
684
le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
drivers/gpu/drm/radeon/radeon_atombios.c
692
le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
drivers/gpu/drm/radeon/radeon_i2c.c
328
int i, j, k, ret = num;
drivers/gpu/drm/radeon/radeon_i2c.c
472
for (k = 0; k < 32; k++) {
drivers/gpu/drm/radeon/radeon_i2c.c
504
for (k = 0; k < 32; k++) {
drivers/gpu/drm/radeon/radeon_i2c.c
532
for (k = 0; k < 32; k++) {
drivers/gpu/drm/radeon/radeon_test.c
528
int i, j, k;
drivers/gpu/drm/radeon/radeon_test.c
549
for (k = 0; k < j; ++k) {
drivers/gpu/drm/radeon/radeon_test.c
550
struct radeon_ring *ringC = &rdev->ring[k];
drivers/gpu/drm/radeon/radeon_test.c
560
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
drivers/gpu/drm/radeon/radeon_test.c
563
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
drivers/gpu/drm/radeon/radeon_test.c
566
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
drivers/gpu/drm/radeon/radeon_test.c
569
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
drivers/gpu/drm/radeon/radeon_test.c
572
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
drivers/gpu/drm/radeon/radeon_test.c
575
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
drivers/gpu/drm/radeon/si.c
2976
int i, j, k;
drivers/gpu/drm/radeon/si.c
2986
for (k = 0; k < 16; k++) {
drivers/gpu/drm/radeon/si.c
2987
mask <<= k;
drivers/gpu/drm/radeon/si.c
5304
u32 i, j, k, active_cu_number = 0;
drivers/gpu/drm/radeon/si.c
5313
for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
drivers/gpu/drm/radeon/si_dpm.c
1777
u32 k = dte_data->k;
drivers/gpu/drm/radeon/si_dpm.c
1786
for (i = 0; i < k; i++) {
drivers/gpu/drm/radeon/si_dpm.c
2419
if (dte_data->k <= 0)
drivers/gpu/drm/radeon/si_dpm.c
2428
table_size = dte_data->k;
drivers/gpu/drm/radeon/si_dpm.c
5303
u8 i, j, k;
drivers/gpu/drm/radeon/si_dpm.c
5314
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/radeon/si_dpm.c
5315
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/si_dpm.c
5317
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
drivers/gpu/drm/radeon/si_dpm.c
5325
for (k = 0; k < table->num_entries; k++) {
drivers/gpu/drm/radeon/si_dpm.c
5326
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/si_dpm.c
5328
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/si_dpm.c
5330
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
drivers/gpu/drm/radeon/si_dpm.c
5339
for (k = 0; k < table->num_entries; k++)
drivers/gpu/drm/radeon/si_dpm.c
5340
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/si_dpm.c
5341
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
drivers/gpu/drm/radeon/si_dpm.c
5351
for(k = 0; k < table->num_entries; k++)
drivers/gpu/drm/radeon/si_dpm.c
5352
table->mc_reg_table_entry[k].mc_data[j] =
drivers/gpu/drm/radeon/si_dpm.c
5354
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
drivers/gpu/drm/radeon/si_dpm.c
6756
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/radeon/si_dpm.c
6805
k = 0;
drivers/gpu/drm/radeon/si_dpm.c
6811
if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/radeon/si_dpm.c
6817
&rdev->pm.dpm.ps[i], k,
drivers/gpu/drm/radeon/si_dpm.c
6819
k++;
drivers/gpu/drm/radeon/si_dpm.h
70
u32 k;
drivers/gpu/drm/radeon/sumo_dpm.c
1455
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/radeon/sumo_dpm.c
1503
k = 0;
drivers/gpu/drm/radeon/sumo_dpm.c
1507
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/radeon/sumo_dpm.c
1514
&rdev->pm.dpm.ps[i], k,
drivers/gpu/drm/radeon/sumo_dpm.c
1516
k++;
drivers/gpu/drm/radeon/trinity_dpm.c
1686
int i, j, k, non_clock_array_index, clock_array_index;
drivers/gpu/drm/radeon/trinity_dpm.c
1734
k = 0;
drivers/gpu/drm/radeon/trinity_dpm.c
1740
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
drivers/gpu/drm/radeon/trinity_dpm.c
1746
&rdev->pm.dpm.ps[i], k,
drivers/gpu/drm/radeon/trinity_dpm.c
1748
k++;
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
104
.k = { .min = -32768, .max = 32767 },
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
696
FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k));
drivers/gpu/drm/solomon/ssd130x.c
744
int ret, i, j, k;
drivers/gpu/drm/solomon/ssd130x.c
798
for (k = 0; k < m; k++) {
drivers/gpu/drm/solomon/ssd130x.c
799
u32 idx = (page_height * i + k) * line_length + j / 8;
drivers/gpu/drm/solomon/ssd130x.c
803
data |= bit << k;
drivers/gpu/drm/tegra/dc.c
520
unsigned int i, k;
drivers/gpu/drm/tegra/dc.c
526
for (i = 0, k = 128; i < 16; i++, k -= 8)
drivers/gpu/drm/tegra/dc.c
527
tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
drivers/gpu/drm/tegra/dsi.c
1211
unsigned int i, j, k;
drivers/gpu/drm/tegra/dsi.c
1263
for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
drivers/gpu/drm/tegra/dsi.c
1264
rx[j + k] = (value >> (k << 3)) & 0xff;
drivers/gpu/drm/tiny/pixpaper.c
733
int k;
drivers/gpu/drm/tiny/pixpaper.c
735
for (k = 0; k < 4; k++) {
drivers/gpu/drm/tiny/pixpaper.c
736
int current_pixel_x = j * 4 + k;
drivers/gpu/drm/tiny/pixpaper.c
770
packed_byte |= two_bit_val << ((3 - k) * 2);
drivers/gpu/drm/vc4/vc4_gem.c
162
unsigned int i, j, k, unref_list_count;
drivers/gpu/drm/vc4/vc4_gem.c
198
k = 0;
drivers/gpu/drm/vc4/vc4_gem.c
213
kernel_state->bo[k++] = exec[i]->bo[j];
drivers/gpu/drm/vc4/vc4_gem.c
221
kernel_state->bo[k++] = &bo->base.base;
drivers/gpu/drm/vc4/vc4_gem.c
225
WARN_ON_ONCE(k != state->bo_count);
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
1517
u32 i, k;
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
1534
for (k = 0; k < num_units; k++) {
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
1535
struct vmw_display_unit *unit = units[k];
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
474
int i, k;
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
481
for (i = 0, k = 0; i < VMW_MAX_NUM_STREAMS; i++)
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
483
k++;
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
487
return k;
drivers/gpu/drm/xe/tests/xe_args_test.c
138
count = COUNT_ARGS(a, b, c, d, e, f, g, h, i, j, k, l);
drivers/gpu/drm/xe/xe_guc_capture.c
1513
int i, j, k, tmp, maxregcount = 0;
drivers/gpu/drm/xe/xe_guc_capture.c
1517
for (k = 0; k < GUC_CAPTURE_LIST_CLASS_MAX; ++k) {
drivers/gpu/drm/xe/xe_guc_capture.c
1520
if (j == GUC_STATE_CAPTURE_TYPE_GLOBAL && k > 0)
drivers/gpu/drm/xe/xe_guc_capture.c
1524
match = guc_capture_get_one_list(guc->capture->reglists, i, j, k);
drivers/gpu/drm/xe/xe_guc_capture.c
1528
match = guc_capture_get_one_list(guc->capture->extlists, i, j, k);
drivers/hid/hid-debug.c
3057
unsigned i,k;
drivers/hid/hid-debug.c
3071
for (k = 0; k < report->maxfield; k++) {
drivers/hid/hid-debug.c
3073
seq_printf(f, "Field(%d)\n", k);
drivers/hid/hid-debug.c
3074
hid_dump_field(report->field[k], 6, f);
drivers/hid/hid-debug.c
3634
int i, j, k;
drivers/hid/hid-debug.c
3638
for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) {
drivers/hid/hid-debug.c
3639
list_for_each_entry(report, &hid->report_enum[k].report_list, list) {
drivers/hid/hid-input.c
136
unsigned int i, j, k, cur_idx = 0;
drivers/hid/hid-input.c
140
for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) {
drivers/hid/hid-input.c
141
list_for_each_entry(report, &hid->report_enum[k].report_list, list) {
drivers/hid/hid-input.c
2171
int i, k;
drivers/hid/hid-input.c
2177
for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) {
drivers/hid/hid-input.c
2178
if (k == HID_OUTPUT_REPORT &&
drivers/hid/hid-input.c
2182
list_for_each_entry(report, &hid->report_enum[k].report_list,
drivers/hid/hid-input.c
2234
int i, j, k;
drivers/hid/hid-input.c
2279
for (k = first_field_index; k <= i; k++)
drivers/hid/hid-input.c
2280
report->field[k]->slot_idx = slot_idx;
drivers/hid/hid-input.c
2305
int i, k;
drivers/hid/hid-input.c
2327
for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) {
drivers/hid/hid-input.c
2328
if (k == HID_OUTPUT_REPORT &&
drivers/hid/hid-input.c
2332
list_for_each_entry(report, &hid->report_enum[k].report_list, list) {
drivers/hid/hid-picolcd_core.c
75
int i, j, k;
drivers/hid/hid-picolcd_core.c
92
for (i = k = 0; i < report->maxfield; i++)
drivers/hid/hid-picolcd_core.c
94
hid_set_field(report->field[i], j, k < size ? raw_data[k] : 0);
drivers/hid/hid-picolcd_core.c
95
k++;
drivers/hid/wacom_sys.c
2638
int error, k;
drivers/hid/wacom_sys.c
2643
for (k = 0; k < WACOM_MAX_REMOTES; k++) {
drivers/hid/wacom_sys.c
2644
if (remote->remotes[k].serial == serial)
drivers/hid/wacom_sys.c
2648
if (k < WACOM_MAX_REMOTES) {
drivers/hwmon/i5k_amb.c
245
int i, j, k, d = 0;
drivers/hwmon/i5k_amb.c
269
k = amb_num_from_reg(i, j);
drivers/hwmon/i5k_amb.c
281
iattr->s_attr.index = k;
drivers/hwmon/i5k_amb.c
296
iattr->s_attr.index = k;
drivers/hwmon/i5k_amb.c
312
iattr->s_attr.index = k;
drivers/hwmon/i5k_amb.c
328
iattr->s_attr.index = k;
drivers/hwmon/i5k_amb.c
344
iattr->s_attr.index = k;
drivers/hwmon/i5k_amb.c
359
iattr->s_attr.index = k;
drivers/hwmon/mr75203.c
635
int ret, i, j, k;
drivers/hwmon/mr75203.c
673
k = 0;
drivers/hwmon/mr75203.c
676
pvt->vd[k].vm_map = vm_idx[i];
drivers/hwmon/mr75203.c
677
pvt->vd[k].ch_map = j;
drivers/hwmon/mr75203.c
678
k++;
drivers/i2c/busses/i2c-bcm-kona.c
394
int k;
drivers/i2c/busses/i2c-bcm-kona.c
409
for (k = 0; k < len; k++)
drivers/i2c/busses/i2c-bcm-kona.c
410
writel(buf[k], (dev->base + DAT_OFFSET));
drivers/i2c/busses/i2c-mpc.c
124
int k;
drivers/i2c/busses/i2c-mpc.c
127
for (k = 9; k; k--) {
drivers/i2c/busses/i2c-mpc.c
136
if (k != 1)
drivers/i2c/busses/i2c-sh_mobile.c
829
int k = 0, ret;
drivers/i2c/busses/i2c-sh_mobile.c
834
while ((irq = platform_get_irq_optional(dev, k)) != -ENXIO) {
drivers/i2c/busses/i2c-sh_mobile.c
843
k++;
drivers/i2c/busses/i2c-sh_mobile.c
849
while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
drivers/i2c/busses/i2c-sh_mobile.c
858
k++;
drivers/i2c/busses/i2c-sh_mobile.c
862
return k > 0 ? 0 : -ENOENT;
drivers/iio/adc/ad7173.c
1395
int i, j, k, ret;
drivers/iio/adc/ad7173.c
1465
for (k = 0; k < st->num_channels; k++)
drivers/iio/adc/ad7173.c
1466
st->channels[k].cfg.live = false;
drivers/iio/adc/palmas_gpadc.c
343
int k;
drivers/iio/adc/palmas_gpadc.c
368
k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
drivers/iio/adc/palmas_gpadc.c
373
adc->adc_info[adc_chan].gain_error = k;
drivers/iio/adc/palmas_gpadc.c
376
adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
drivers/iio/adc/ti-ads1015.c
912
unsigned int k;
drivers/iio/adc/ti-ads1015.c
921
for (k = 0; k < ADS1015_CHANNELS; ++k) {
drivers/iio/adc/ti-ads1015.c
922
data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
drivers/iio/adc/ti-ads1015.c
923
data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
drivers/iio/adc/ti_am335x_adc.c
195
int i, k, fifo1count, read;
drivers/iio/adc/ti_am335x_adc.c
199
for (k = 0; k < fifo1count; k = k + i) {
drivers/iio/adc/twl6030-gpadc.c
576
int b, k, gain, x1, x2, i;
drivers/iio/adc/twl6030-gpadc.c
589
k = 1000 + (((d2 - d1) * 1000) / (x2 - x1));
drivers/iio/adc/twl6030-gpadc.c
592
b = (d1 * 1000) - (k - 1000) * x1;
drivers/iio/adc/twl6030-gpadc.c
595
gpadc->twl6030_cal_tbl[i].gain_error = k;
drivers/iio/adc/twl6030-gpadc.c
603
dev_dbg(gpadc->dev, "GPADC k for Chn: %d = %d\n", channel, k);
drivers/iio/magnetometer/yamaha-yas530.c
1110
c->k = FIELD_GET(GENMASK(14, 8), val4);
drivers/iio/magnetometer/yamaha-yas530.c
1140
dev_dbg(yas5xx->dev, "k = %d\n", c->k);
drivers/iio/magnetometer/yamaha-yas530.c
1160
dev_dbg(yas5xx->dev, "k = %d\n", c->k);
drivers/iio/magnetometer/yamaha-yas530.c
161
u8 k;
drivers/iio/magnetometer/yamaha-yas530.c
411
h[0] = (c->k * (128 * s[0] + c->a2 * s[1] + c->a3 * s[2])) / half_range;
drivers/iio/magnetometer/yamaha-yas530.c
412
h[1] = (c->k * (c->a4 * s[0] + c->a5 * s[1] + c->a6 * s[2])) / half_range;
drivers/iio/magnetometer/yamaha-yas530.c
413
h[2] = (c->k * (c->a7 * s[0] + c->a8 * s[1] + c->a9 * s[2])) / half_range;
drivers/iio/magnetometer/yamaha-yas530.c
569
*xo = c->k * ((100 * sx + c->a2 * sy + c->a3 * sz) / 10);
drivers/iio/magnetometer/yamaha-yas530.c
570
*yo = c->k * ((c->a4 * sx + c->a5 * sy + c->a6 * sz) / 10);
drivers/iio/magnetometer/yamaha-yas530.c
571
*zo = c->k * ((c->a7 * sx + c->a8 * sy + c->a9 * sz) / 10);
drivers/iio/magnetometer/yamaha-yas530.c
813
c->k = FIELD_GET(GENMASK_ULL(14, 10), val) + 10;
drivers/infiniband/hw/bnxt_re/qplib_res.c
407
int i, j, k;
drivers/infiniband/hw/bnxt_re/qplib_res.c
423
for (k = 0; k < pg_count; k++) {
drivers/infiniband/hw/bnxt_re/qplib_res.c
424
ptr = &pbl_ptr[PTR_PG(j + k)][PTR_IDX(j + k)];
drivers/infiniband/hw/bnxt_re/qplib_res.c
425
dma_ptr = &tbl->pbl[PBL_LVL_1].pg_map_arr[k];
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
4395
int i, j, k;
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
4409
k = mhop.l2_idx;
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
4415
k;
drivers/infiniband/hw/mlx4/alias_GUID.c
583
int j, k, entry;
drivers/infiniband/hw/mlx4/alias_GUID.c
588
for (k = 0; k < NUM_ALIAS_GUID_IN_REC; k++) {
drivers/infiniband/hw/mlx4/alias_GUID.c
589
entry = j * NUM_ALIAS_GUID_IN_REC + k;
drivers/infiniband/hw/mlx4/alias_GUID.c
597
[GUID_REC_SIZE * k] = guid;
drivers/infiniband/hw/mlx4/main.c
1430
int i, j, k;
drivers/infiniband/hw/mlx4/main.c
1444
for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
drivers/infiniband/hw/mlx4/main.c
1445
j < flow_attr->num_of_specs; k++) {
drivers/infiniband/hw/mlx4/main.c
1451
(pdefault_rules->mandatory_fields[k] &
drivers/infiniband/hw/mlx4/main.c
1454
pdefault_rules->mandatory_fields[k]))
drivers/infiniband/hw/mlx4/main.c
1459
pdefault_rules->mandatory_fields[k]) {
drivers/infiniband/hw/mlx4/main.c
1469
for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
drivers/infiniband/hw/mlx4/main.c
1472
pdefault_rules->mandatory_not_fields[k])
drivers/input/input-mt.c
389
int i, k, sum;
drivers/input/input-mt.c
391
for (k = 0; k < nrc; k++) {
drivers/input/input.c
831
u8 *k = (u8 *)dev->keycode;
drivers/input/input.c
832
*old_keycode = k[index];
drivers/input/input.c
833
k[index] = ke->keycode;
drivers/input/input.c
837
u16 *k = (u16 *)dev->keycode;
drivers/input/input.c
838
*old_keycode = k[index];
drivers/input/input.c
839
k[index] = ke->keycode;
drivers/input/input.c
843
u32 *k = (u32 *)dev->keycode;
drivers/input/input.c
844
*old_keycode = k[index];
drivers/input/input.c
845
k[index] = ke->keycode;
drivers/input/joystick/sidewinder.c
572
int i, j, k, l;
drivers/input/joystick/sidewinder.c
635
k = SW_FAIL; /* Try SW_FAIL times */
drivers/input/joystick/sidewinder.c
639
k--;
drivers/input/joystick/sidewinder.c
642
dbg("Init 3: Mode %d. Length %d. Last %d. Tries %d.", m, i, l, k);
drivers/input/joystick/sidewinder.c
699
} while (k && sw->type == -1);
drivers/input/joystick/sidewinder.c
718
k = i;
drivers/input/joystick/sidewinder.c
767
dbg("%s%s [%d-bit id %d data %d]\n", sw->name, comment, m, l, k);
drivers/input/joystick/tmdc.c
131
int i[2], j[2], t[2], p, k;
drivers/input/joystick/tmdc.c
135
for (k = 0; k < 2; k++) {
drivers/input/joystick/tmdc.c
136
t[k] = gameport_time(gameport, TMDC_MAX_START);
drivers/input/joystick/tmdc.c
137
i[k] = j[k] = 0;
drivers/input/joystick/tmdc.c
149
for (k = 0, v = w, u = x; k < 2; k++, v >>= 2, u >>= 2) {
drivers/input/joystick/tmdc.c
151
if (t[k] <= 0 || i[k] >= TMDC_MAX_LENGTH) continue;
drivers/input/joystick/tmdc.c
152
t[k] = p;
drivers/input/joystick/tmdc.c
153
if (j[k] == 0) { /* Start bit */
drivers/input/joystick/tmdc.c
154
if (~v & 1) t[k] = 0;
drivers/input/joystick/tmdc.c
155
data[k][i[k]] = 0; j[k]++; continue;
drivers/input/joystick/tmdc.c
157
if (j[k] == 9) { /* Stop bit */
drivers/input/joystick/tmdc.c
158
if (v & 1) t[k] = 0;
drivers/input/joystick/tmdc.c
159
j[k] = 0; i[k]++; continue;
drivers/input/joystick/tmdc.c
161
data[k][i[k]] |= (~v & 1) << (j[k]++ - 1); /* Data bit */
drivers/input/joystick/tmdc.c
163
t[k]--;
drivers/input/joystick/tmdc.c
174
int i, k, l;
drivers/input/joystick/tmdc.c
204
for (k = l = 0; k < 4; k++) {
drivers/input/joystick/tmdc.c
205
for (i = 0; i < port->btnc[k]; i++)
drivers/input/joystick/tmdc.c
207
((data[tmdc_byte_d[k]] >> (i + port->btno[k])) & 1));
drivers/input/joystick/tmdc.c
208
l += port->btnc[k];
drivers/input/keyboard/sh_keysc.c
114
for (k = 0; k < keyin_nr; k++) {
drivers/input/keyboard/sh_keysc.c
115
if (tmp & (1 << k))
drivers/input/keyboard/sh_keysc.c
116
__set_bit(n + k, keys);
drivers/input/keyboard/sh_keysc.c
138
k = pdata->keycodes[i];
drivers/input/keyboard/sh_keysc.c
139
if (!k)
drivers/input/keyboard/sh_keysc.c
146
input_event(priv->input, EV_KEY, k, 1);
drivers/input/keyboard/sh_keysc.c
151
input_event(priv->input, EV_KEY, k, 0);
drivers/input/keyboard/sh_keysc.c
75
int k;
drivers/input/keyboard/sh_keysc.c
77
for (k = 0; k < BITS_TO_LONGS(SH_KEYSC_MAXKEYS); k++)
drivers/input/keyboard/sh_keysc.c
78
dev_dbg(dev, "%s[%d] 0x%lx\n", str, k, map[k]);
drivers/input/keyboard/sh_keysc.c
92
int i, k, n;
drivers/input/misc/cm109.c
791
unsigned short k = keymap(i);
drivers/input/misc/cm109.c
792
dev->keymap[i] = k;
drivers/input/misc/cm109.c
793
__set_bit(k, input_dev->keybit);
drivers/input/misc/iqs7222.c
1842
int error, i, j, k;
drivers/input/misc/iqs7222.c
1901
for (k = 0; k < num_col; k++)
drivers/input/misc/iqs7222.c
1902
val[k] = le16_to_cpu(val_buf[k]);
drivers/input/misc/iqs7222.c
1906
for (k = 0; k < num_col; k++)
drivers/input/misc/iqs7222.c
1907
val_buf[k] = cpu_to_le16(val[k]);
drivers/input/misc/iqs7222.c
2949
int k = 2 + j * (num_chan > 16 ? 2 : 1);
drivers/input/misc/iqs7222.c
2950
u16 state = le16_to_cpu(status[k + i / 16]);
drivers/input/misc/yealink.c
60
#define _LOC(k,l) { .a = (k), .m = (l) }
drivers/input/misc/yealink.c
920
int k = map_p1k_to_key(i);
drivers/input/misc/yealink.c
921
if (k >= 0) {
drivers/input/misc/yealink.c
922
set_bit(k & 0xff, input_dev->keybit);
drivers/input/misc/yealink.c
923
if (k >> 8)
drivers/input/misc/yealink.c
924
set_bit(k >> 8, input_dev->keybit);
drivers/input/sparse-keymap.c
24
const struct key_entry *k)
drivers/input/sparse-keymap.c
31
if (key == k)
drivers/input/touchscreen/iqs7211.c
1755
int error, count, i, j, k, cycle_start;
drivers/input/touchscreen/iqs7211.c
1781
for (k = cycle_start; k < num_cycles; k++) {
drivers/input/touchscreen/iqs7211.c
1782
if (cycle_alloc[k][slot] < U8_MAX)
drivers/input/touchscreen/iqs7211.c
1785
cycle_alloc[k][slot] = chan;
drivers/input/touchscreen/iqs7211.c
1789
if (k < num_cycles) {
drivers/input/touchscreen/iqs7211.c
1790
cycle_stop = max(k, cycle_stop);
drivers/iommu/io-pgtable-arm-selftests.c
166
int i, j, k, pass = 0, fail = 0;
drivers/iommu/io-pgtable-arm-selftests.c
184
for (k = 0; k <= j; ++k) {
drivers/iommu/io-pgtable-arm-selftests.c
186
cfg.ias = address_size[k];
drivers/irqchip/irq-renesas-intc-irqpin.c
304
int k;
drivers/irqchip/irq-renesas-intc-irqpin.c
306
for (k = 0; k < 8; k++) {
drivers/irqchip/irq-renesas-intc-irqpin.c
307
if (reg_source & BIT(7 - k)) {
drivers/irqchip/irq-renesas-intc-irqpin.c
308
if (BIT(k) & p->shared_irq_mask)
drivers/irqchip/irq-renesas-intc-irqpin.c
311
status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
drivers/irqchip/irq-renesas-intc-irqpin.c
385
int k;
drivers/irqchip/irq-renesas-intc-irqpin.c
408
for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
drivers/irqchip/irq-renesas-intc-irqpin.c
409
io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
drivers/irqchip/irq-renesas-intc-irqpin.c
410
if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
drivers/irqchip/irq-renesas-intc-irqpin.c
418
for (k = 0; k < INTC_IRQPIN_MAX; k++) {
drivers/irqchip/irq-renesas-intc-irqpin.c
419
ret = platform_get_irq_optional(pdev, k);
drivers/irqchip/irq-renesas-intc-irqpin.c
425
p->irq[k].p = p;
drivers/irqchip/irq-renesas-intc-irqpin.c
426
p->irq[k].requested_irq = ret;
drivers/irqchip/irq-renesas-intc-irqpin.c
429
nirqs = k;
drivers/irqchip/irq-renesas-intc-irqpin.c
437
for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
drivers/irqchip/irq-renesas-intc-irqpin.c
438
i = &p->iomem[k];
drivers/irqchip/irq-renesas-intc-irqpin.c
441
if (!io[k])
drivers/irqchip/irq-renesas-intc-irqpin.c
444
switch (resource_size(io[k])) {
drivers/irqchip/irq-renesas-intc-irqpin.c
461
i->iomem = devm_ioremap(dev, io[k]->start,
drivers/irqchip/irq-renesas-intc-irqpin.c
462
resource_size(io[k]));
drivers/irqchip/irq-renesas-intc-irqpin.c
480
for (k = 0; k < nirqs; k++)
drivers/irqchip/irq-renesas-intc-irqpin.c
481
intc_irqpin_mask_unmask_prio(p, k, 1);
drivers/irqchip/irq-renesas-intc-irqpin.c
489
for (k = 1; k < nirqs; k++) {
drivers/irqchip/irq-renesas-intc-irqpin.c
490
if (ref_irq != p->irq[k].requested_irq) {
drivers/irqchip/irq-renesas-intc-irqpin.c
537
for (k = 0; k < nirqs; k++) {
drivers/irqchip/irq-renesas-intc-irqpin.c
538
if (devm_request_irq(dev, p->irq[k].requested_irq,
drivers/irqchip/irq-renesas-intc-irqpin.c
540
&p->irq[k])) {
drivers/irqchip/irq-renesas-intc-irqpin.c
549
for (k = 0; k < nirqs; k++)
drivers/irqchip/irq-renesas-intc-irqpin.c
550
intc_irqpin_mask_unmask_prio(p, k, 0);
drivers/irqchip/irq-renesas-irqc.c
130
int k;
drivers/irqchip/irq-renesas-irqc.c
143
for (k = 0; k < IRQC_IRQ_MAX; k++) {
drivers/irqchip/irq-renesas-irqc.c
144
ret = platform_get_irq_optional(pdev, k);
drivers/irqchip/irq-renesas-irqc.c
150
p->irq[k].p = p;
drivers/irqchip/irq-renesas-irqc.c
151
p->irq[k].hw_irq = k;
drivers/irqchip/irq-renesas-irqc.c
152
p->irq[k].requested_irq = ret;
drivers/irqchip/irq-renesas-irqc.c
155
p->number_of_irqs = k;
drivers/irqchip/irq-renesas-irqc.c
200
for (k = 0; k < p->number_of_irqs; k++) {
drivers/irqchip/irq-renesas-irqc.c
201
if (devm_request_irq(dev, p->irq[k].requested_irq,
drivers/irqchip/irq-renesas-irqc.c
202
irqc_irq_handler, 0, name, &p->irq[k])) {
drivers/irqchip/irq-renesas-rzv2h.c
200
u32 tint_nr, tssel_n, k, tssr;
drivers/irqchip/irq-renesas-rzv2h.c
208
k = tint_nr / nr_tint;
drivers/irqchip/irq-renesas-rzv2h.c
212
tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
drivers/irqchip/irq-renesas-rzv2h.c
217
writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
drivers/irqchip/irq-renesas-rzv2h.c
326
int k = tint_nr / 16;
drivers/irqchip/irq-renesas-rzv2h.c
329
titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));
drivers/irqchip/irq-renesas-rzv2h.c
41
#define ICU_TITSR(k) (0x28 + (k) * 4)
drivers/irqchip/irq-renesas-rzv2h.c
42
#define ICU_TSSR(k) (0x30 + (k) * 4)
drivers/irqchip/irq-renesas-rzv2h.c
43
#define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4)
drivers/irqchip/irq-renesas-rzv2h.c
44
#define ICU_DMACKSELk(k) (0x500 + (k) * 4)
drivers/isdn/hardware/mISDN/hfcsusb.c
1007
for (k = 0; k < num_isoc_packets; ++k) {
drivers/isdn/hardware/mISDN/hfcsusb.c
1008
len = urb->iso_frame_desc[k].actual_length;
drivers/isdn/hardware/mISDN/hfcsusb.c
1009
offset = urb->iso_frame_desc[k].offset;
drivers/isdn/hardware/mISDN/hfcsusb.c
1011
iso_status = urb->iso_frame_desc[k].status;
drivers/isdn/hardware/mISDN/hfcsusb.c
1016
hw->name, __func__, k, iso_status);
drivers/isdn/hardware/mISDN/hfcsusb.c
1025
k, num_isoc_packets - 1,
drivers/isdn/hardware/mISDN/hfcsusb.c
1164
int k, tx_offset, num_isoc_packets, sink, remain, current_len,
drivers/isdn/hardware/mISDN/hfcsusb.c
1234
for (k = 0; k < num_isoc_packets; ++k) {
drivers/isdn/hardware/mISDN/hfcsusb.c
1237
errcode = urb->iso_frame_desc[k].status;
drivers/isdn/hardware/mISDN/hfcsusb.c
1241
hw->name, __func__, k, errcode);
drivers/isdn/hardware/mISDN/hfcsusb.c
1289
urb->iso_frame_desc[k].offset = tx_offset;
drivers/isdn/hardware/mISDN/hfcsusb.c
1290
urb->iso_frame_desc[k].length = current_len + 1;
drivers/isdn/hardware/mISDN/hfcsusb.c
1298
k, num_isoc_packets - 1,
drivers/isdn/hardware/mISDN/hfcsusb.c
1299
urb->iso_frame_desc[k].offset,
drivers/isdn/hardware/mISDN/hfcsusb.c
1300
urb->iso_frame_desc[k].length);
drivers/isdn/hardware/mISDN/hfcsusb.c
1302
for (i = urb->iso_frame_desc[k].offset;
drivers/isdn/hardware/mISDN/hfcsusb.c
1303
i < (urb->iso_frame_desc[k].offset
drivers/isdn/hardware/mISDN/hfcsusb.c
1304
+ urb->iso_frame_desc[k].length);
drivers/isdn/hardware/mISDN/hfcsusb.c
1315
urb->iso_frame_desc[k].offset = tx_offset++;
drivers/isdn/hardware/mISDN/hfcsusb.c
1316
urb->iso_frame_desc[k].length = 1;
drivers/isdn/hardware/mISDN/hfcsusb.c
1385
int i, k, errcode;
drivers/isdn/hardware/mISDN/hfcsusb.c
1419
for (k = 0; k < num_packets_per_urb; k++) {
drivers/isdn/hardware/mISDN/hfcsusb.c
1421
iso_frame_desc[k].offset =
drivers/isdn/hardware/mISDN/hfcsusb.c
1422
k * packet_size;
drivers/isdn/hardware/mISDN/hfcsusb.c
1424
iso_frame_desc[k].length =
drivers/isdn/hardware/mISDN/hfcsusb.c
945
int k;
drivers/isdn/hardware/mISDN/hfcsusb.c
955
for (k = 0; k < num_packets; k++) {
drivers/isdn/hardware/mISDN/hfcsusb.c
956
urb->iso_frame_desc[k].offset = packet_size * k;
drivers/isdn/hardware/mISDN/hfcsusb.c
957
urb->iso_frame_desc[k].length = packet_size;
drivers/isdn/hardware/mISDN/hfcsusb.c
958
urb->iso_frame_desc[k].actual_length = 0;
drivers/isdn/hardware/mISDN/hfcsusb.c
969
int k, len, errcode, offset, num_isoc_packets, fifon, maxlen,
drivers/isdn/mISDN/dsp_audio.c
193
int i, j, k;
drivers/isdn/mISDN/dsp_audio.c
200
for (k = 0; k < 256; k++) {
drivers/isdn/mISDN/dsp_audio.c
201
if (dsp_audio_alaw_to_s32[k]
drivers/isdn/mISDN/dsp_blowfish.c
457
u8 k = dsp->bf_decrypt_out_pos;
drivers/isdn/mISDN/dsp_blowfish.c
474
*data++ = bf_data_out[k++];
drivers/isdn/mISDN/dsp_blowfish.c
476
if (k == 9)
drivers/isdn/mISDN/dsp_blowfish.c
477
k = 0; /* repeat if no sync has been found */
drivers/isdn/mISDN/dsp_blowfish.c
546
k = 0; /* start with new decoded frame */
drivers/isdn/mISDN/dsp_blowfish.c
551
dsp->bf_decrypt_out_pos = k;
drivers/isdn/mISDN/dsp_core.c
741
int k;
drivers/isdn/mISDN/dsp_core.c
747
k = *digits | DTMF_TONE_VAL;
drivers/isdn/mISDN/dsp_core.c
749
MISDN_ID_ANY, sizeof(int), &k,
drivers/isdn/mISDN/dsp_core.c
787
int k;
drivers/isdn/mISDN/dsp_core.c
793
k = *digits | DTMF_TONE_VAL;
drivers/isdn/mISDN/dsp_core.c
795
MISDN_ID_ANY, sizeof(int), &k,
drivers/isdn/mISDN/dsp_dtmf.c
124
int k, n, i;
drivers/isdn/mISDN/dsp_dtmf.c
158
for (k = 0; k < NCOEFF; k++) {
drivers/isdn/mISDN/dsp_dtmf.c
166
result[k] =
drivers/isdn/mISDN/dsp_dtmf.c
168
(((cos2pik[k] * sk) >> 15) * sk2) +
drivers/isdn/mISDN/dsp_dtmf.c
184
for (k = 0; k < NCOEFF; k++) {
drivers/isdn/mISDN/dsp_dtmf.c
189
cos2pik_ = cos2pik[k];
drivers/isdn/mISDN/dsp_dtmf.c
200
result[k] =
drivers/isdn/mISDN/dsp_dtmf.c
202
(((cos2pik[k] * sk) >> 15) * sk2) +
drivers/mailbox/arm_mhuv2.c
878
int protocol, windows = 0, next_window = 0, i, j, k;
drivers/mailbox/arm_mhuv2.c
905
for (k = 0; k < MHUV2_STAT_BITS; k++) {
drivers/mailbox/arm_mhuv2.c
912
priv->doorbell = k;
drivers/mailbox/arm_mhuv3.c
606
int k;
drivers/mailbox/arm_mhuv3.c
608
for (k = 0; k < MHUV3_FLAG_BITS; k++) {
drivers/mailbox/arm_mhuv3.c
615
priv->doorbell = k;
drivers/md/bcache/alloc.c
468
void bch_bucket_free(struct cache_set *c, struct bkey *k)
drivers/md/bcache/alloc.c
472
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/alloc.c
473
__bch_bucket_free(c->cache, PTR_BUCKET(c, k, i));
drivers/md/bcache/alloc.c
477
struct bkey *k, bool wait)
drivers/md/bcache/alloc.c
488
bkey_init(k);
drivers/md/bcache/alloc.c
495
k->ptr[0] = MAKE_PTR(ca->buckets[b].gen,
drivers/md/bcache/alloc.c
499
SET_KEY_PTRS(k, 1);
drivers/md/bcache/alloc.c
505
struct bkey *k, bool wait)
drivers/md/bcache/alloc.c
510
ret = __bch_bucket_alloc_set(c, reserve, k, wait);
drivers/md/bcache/alloc.c
591
struct bkey *k,
drivers/md/bcache/alloc.c
611
while (!(b = pick_data_bucket(c, k, write_point, &alloc.key))) {
drivers/md/bcache/alloc.c
638
k->ptr[i] = b->key.ptr[i];
drivers/md/bcache/alloc.c
642
SET_KEY_OFFSET(k, KEY_OFFSET(k) + sectors);
drivers/md/bcache/alloc.c
643
SET_KEY_SIZE(k, sectors);
drivers/md/bcache/alloc.c
644
SET_KEY_PTRS(k, KEY_PTRS(&b->key));
drivers/md/bcache/alloc.c
651
bkey_copy_key(&b->key, k);
drivers/md/bcache/alloc.c
713
struct task_struct *k = kthread_run(bch_allocator_thread,
drivers/md/bcache/alloc.c
715
if (IS_ERR(k))
drivers/md/bcache/alloc.c
716
return PTR_ERR(k);
drivers/md/bcache/alloc.c
718
ca->alloc_thread = k;
drivers/md/bcache/bcache.h
1000
struct bkey *k, bool wait);
drivers/md/bcache/bcache.h
1001
bool bch_alloc_sectors(struct cache_set *c, struct bkey *k,
drivers/md/bcache/bcache.h
821
const struct bkey *k,
drivers/md/bcache/bcache.h
824
return sector_to_bucket(c, PTR_OFFSET(k, ptr));
drivers/md/bcache/bcache.h
828
const struct bkey *k,
drivers/md/bcache/bcache.h
831
return c->cache->buckets + PTR_BUCKET_NR(c, k, ptr);
drivers/md/bcache/bcache.h
841
static inline uint8_t ptr_stale(struct cache_set *c, const struct bkey *k,
drivers/md/bcache/bcache.h
844
return gen_after(PTR_BUCKET(c, k, i)->gen, PTR_GEN(k, i));
drivers/md/bcache/bcache.h
847
static inline bool ptr_available(struct cache_set *c, const struct bkey *k,
drivers/md/bcache/bcache.h
850
return (PTR_DEV(k, i) < MAX_CACHES_PER_SET) && c->cache;
drivers/md/bcache/bcache.h
985
struct bkey *k, unsigned int ptr);
drivers/md/bcache/bcache.h
994
void bch_bucket_free(struct cache_set *c, struct bkey *k);
drivers/md/bcache/bcache.h
998
struct bkey *k, bool wait);
drivers/md/bcache/bcache_ondisk.h
101
return (sizeof(struct bkey) / sizeof(__u64)) + KEY_PTRS(k);
drivers/md/bcache/bcache_ondisk.h
104
static inline unsigned long bkey_bytes(const struct bkey *k)
drivers/md/bcache/bcache_ondisk.h
106
return bkey_u64s(k) * sizeof(__u64);
drivers/md/bcache/bcache_ondisk.h
118
static inline struct bkey *bkey_next(const struct bkey *k)
drivers/md/bcache/bcache_ondisk.h
12
static inline __u64 name(const type *k) \
drivers/md/bcache/bcache_ondisk.h
120
__u64 *d = (void *) k;
drivers/md/bcache/bcache_ondisk.h
122
return (struct bkey *) (d + bkey_u64s(k));
drivers/md/bcache/bcache_ondisk.h
125
static inline struct bkey *bkey_idx(const struct bkey *k, unsigned int nr_keys)
drivers/md/bcache/bcache_ondisk.h
127
__u64 *d = (void *) k;
drivers/md/bcache/bcache_ondisk.h
13
{ return (k->field >> offset) & ~(~0ULL << size); } \
drivers/md/bcache/bcache_ondisk.h
15
static inline void SET_##name(type *k, __u64 v) \
drivers/md/bcache/bcache_ondisk.h
17
k->field &= ~(~(~0ULL << size) << offset); \
drivers/md/bcache/bcache_ondisk.h
18
k->field |= (v & ~(~0ULL << size)) << offset; \
drivers/md/bcache/bcache_ondisk.h
33
static inline __u64 name(const struct bkey *k, unsigned int i) \
drivers/md/bcache/bcache_ondisk.h
34
{ return (k->ptr[i] >> offset) & ~(~0ULL << size); } \
drivers/md/bcache/bcache_ondisk.h
36
static inline void SET_##name(struct bkey *k, unsigned int i, __u64 v) \
drivers/md/bcache/bcache_ondisk.h
38
k->ptr[i] &= ~(~(~0ULL << size) << offset); \
drivers/md/bcache/bcache_ondisk.h
39
k->ptr[i] |= (v & ~(~0ULL << size)) << offset; \
drivers/md/bcache/bcache_ondisk.h
56
static inline __u64 KEY_OFFSET(const struct bkey *k)
drivers/md/bcache/bcache_ondisk.h
58
return k->low;
drivers/md/bcache/bcache_ondisk.h
61
static inline void SET_KEY_OFFSET(struct bkey *k, __u64 v)
drivers/md/bcache/bcache_ondisk.h
63
k->low = v;
drivers/md/bcache/bcache_ondisk.h
83
#define KEY_START(k) (KEY_OFFSET(k) - KEY_SIZE(k))
drivers/md/bcache/bcache_ondisk.h
84
#define START_KEY(k) KEY(KEY_INODE(k), KEY_START(k), 0)
drivers/md/bcache/bcache_ondisk.h
99
static inline unsigned long bkey_u64s(const struct bkey *k)
drivers/md/bcache/bset.c
1086
return bkey_cmp(l.k, r.k) > 0;
drivers/md/bcache/bset.c
1094
void bch_btree_iter_push(struct btree_iter *iter, struct bkey *k,
drivers/md/bcache/bset.c
1097
if (k != end)
drivers/md/bcache/bset.c
1099
((struct btree_iter_set) { k, end }),
drivers/md/bcache/bset.c
113
struct bkey *k = iter->data->k, *next = bkey_next(k);
drivers/md/bcache/bset.c
1141
ret = iter->data->k;
drivers/md/bcache/bset.c
1142
iter->data->k = bkey_next(iter->data->k);
drivers/md/bcache/bset.c
1144
if (iter->data->k > iter->data->end) {
drivers/md/bcache/bset.c
1146
iter->data->k = iter->data->end;
drivers/md/bcache/bset.c
1149
if (iter->data->k == iter->data->end)
drivers/md/bcache/bset.c
116
bkey_cmp(k, iter->b->ops->is_extents ?
drivers/md/bcache/bset.c
1199
struct bkey *k, *last = NULL;
drivers/md/bcache/bset.c
1200
BKEY_PADDED(k) tmp;
drivers/md/bcache/bset.c
1211
k = b->ops->sort_fixup(iter, &tmp.k);
drivers/md/bcache/bset.c
1213
k = NULL;
drivers/md/bcache/bset.c
1215
if (!k)
drivers/md/bcache/bset.c
1216
k = __bch_btree_iter_next(iter, b->ops->sort_cmp);
drivers/md/bcache/bset.c
1218
if (bad(b, k))
drivers/md/bcache/bset.c
1223
bkey_copy(last, k);
drivers/md/bcache/bset.c
1224
} else if (!bch_bkey_try_merge(b, last, k)) {
drivers/md/bcache/bset.c
1226
bkey_copy(last, k);
drivers/md/bcache/bset.c
161
struct bkey *k = l->keys;
drivers/md/bcache/bset.c
163
if (k == l->top)
drivers/md/bcache/bset.c
166
while (bkey_next(k) != l->top)
drivers/md/bcache/bset.c
167
k = bkey_next(k);
drivers/md/bcache/bset.c
169
return l->top = k;
drivers/md/bcache/bset.c
197
bool __bch_cut_front(const struct bkey *where, struct bkey *k)
drivers/md/bcache/bset.c
201
if (bkey_cmp(where, &START_KEY(k)) <= 0)
drivers/md/bcache/bset.c
204
if (bkey_cmp(where, k) < 0)
drivers/md/bcache/bset.c
205
len = KEY_OFFSET(k) - KEY_OFFSET(where);
drivers/md/bcache/bset.c
207
bkey_copy_key(k, where);
drivers/md/bcache/bset.c
209
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/bset.c
210
SET_PTR_OFFSET(k, i, PTR_OFFSET(k, i) + KEY_SIZE(k) - len);
drivers/md/bcache/bset.c
212
BUG_ON(len > KEY_SIZE(k));
drivers/md/bcache/bset.c
213
SET_KEY_SIZE(k, len);
drivers/md/bcache/bset.c
217
bool __bch_cut_back(const struct bkey *where, struct bkey *k)
drivers/md/bcache/bset.c
221
if (bkey_cmp(where, k) >= 0)
drivers/md/bcache/bset.c
224
BUG_ON(KEY_INODE(where) != KEY_INODE(k));
drivers/md/bcache/bset.c
226
if (bkey_cmp(where, &START_KEY(k)) > 0)
drivers/md/bcache/bset.c
227
len = KEY_OFFSET(where) - KEY_START(k);
drivers/md/bcache/bset.c
229
bkey_copy_key(k, where);
drivers/md/bcache/bset.c
23
struct bkey *k, *next;
drivers/md/bcache/bset.c
231
BUG_ON(len > KEY_SIZE(k));
drivers/md/bcache/bset.c
232
SET_KEY_SIZE(k, len);
drivers/md/bcache/bset.c
25
for (k = i->start; k < bset_bkey_last(i); k = next) {
drivers/md/bcache/bset.c
26
next = bkey_next(k);
drivers/md/bcache/bset.c
29
(unsigned int) ((u64 *) k - i->d), i->keys);
drivers/md/bcache/bset.c
32
b->ops->key_dump(b, k);
drivers/md/bcache/bset.c
34
pr_cont("%llu:%llu\n", KEY_INODE(k), KEY_OFFSET(k));
drivers/md/bcache/bset.c
37
bkey_cmp(k, b->ops->is_extents ?
drivers/md/bcache/bset.c
532
static unsigned int bkey_to_cacheline(struct bset_tree *t, struct bkey *k)
drivers/md/bcache/bset.c
534
return ((void *) k - (void *) t->data) / BSET_CACHELINE;
drivers/md/bcache/bset.c
539
struct bkey *k)
drivers/md/bcache/bset.c
541
return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0);
drivers/md/bcache/bset.c
58
struct bkey *k;
drivers/md/bcache/bset.c
584
static inline unsigned int bfloat_mantissa(const struct bkey *k,
drivers/md/bcache/bset.c
587
const uint64_t *p = &k->low - (f->exponent >> 6);
drivers/md/bcache/bset.c
61
for_each_key(b, k, &iter)
drivers/md/bcache/bset.c
62
ret += KEY_SIZE(k);
drivers/md/bcache/bset.c
69
struct bkey *k, *p = NULL;
drivers/md/bcache/bset.c
693
struct bkey *prev = NULL, *k = t->data->start;
drivers/md/bcache/bset.c
715
while (bkey_to_cacheline(t, k) < cacheline) {
drivers/md/bcache/bset.c
716
prev = k;
drivers/md/bcache/bset.c
717
k = bkey_next(k);
drivers/md/bcache/bset.c
721
t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k);
drivers/md/bcache/bset.c
724
while (bkey_next(k) != bset_bkey_last(t->data))
drivers/md/bcache/bset.c
725
k = bkey_next(k);
drivers/md/bcache/bset.c
727
t->end = *k;
drivers/md/bcache/bset.c
73
for_each_key(b, k, &iter) {
drivers/md/bcache/bset.c
738
void bch_bset_fix_invalidated_key(struct btree_keys *b, struct bkey *k)
drivers/md/bcache/bset.c
744
if (k < bset_bkey_last(t->data))
drivers/md/bcache/bset.c
752
inorder = bkey_to_cacheline(t, k);
drivers/md/bcache/bset.c
754
if (k == t->data->start)
drivers/md/bcache/bset.c
757
if (bkey_next(k) == bset_bkey_last(t->data)) {
drivers/md/bcache/bset.c
758
t->end = *k;
drivers/md/bcache/bset.c
76
if (p && bkey_cmp(&START_KEY(p), &START_KEY(k)) > 0)
drivers/md/bcache/bset.c
766
k == tree_to_bkey(t, j))
drivers/md/bcache/bset.c
776
k == tree_to_prev_bkey(t, j))
drivers/md/bcache/bset.c
785
struct bkey *k)
drivers/md/bcache/bset.c
787
unsigned int shift = bkey_u64s(k);
drivers/md/bcache/bset.c
788
unsigned int j = bkey_to_cacheline(t, k);
drivers/md/bcache/bset.c
79
if (bch_ptr_invalid(b, k))
drivers/md/bcache/bset.c
800
table_to_bkey(t, j) <= k)
drivers/md/bcache/bset.c
811
k = table_to_bkey(t, j - 1);
drivers/md/bcache/bset.c
813
while (k < cacheline_to_bkey(t, j, 0))
drivers/md/bcache/bset.c
814
k = bkey_next(k);
drivers/md/bcache/bset.c
816
t->prev[j] = bkey_to_cacheline_offset(t, j, k);
drivers/md/bcache/bset.c
825
for (k = table_to_bkey(t, t->size - 1);
drivers/md/bcache/bset.c
826
k != bset_bkey_last(t->data);
drivers/md/bcache/bset.c
827
k = bkey_next(k))
drivers/md/bcache/bset.c
828
if (t->size == bkey_to_cacheline(t, k)) {
drivers/md/bcache/bset.c
83
if (p && bkey_cmp(p, &START_KEY(k)) > 0)
drivers/md/bcache/bset.c
830
bkey_to_cacheline_offset(t, t->size, k);
drivers/md/bcache/bset.c
86
if (bch_ptr_bad(b, k))
drivers/md/bcache/bset.c
876
unsigned int bch_btree_insert_key(struct btree_keys *b, struct bkey *k,
drivers/md/bcache/bset.c
886
BUG_ON(b->ops->is_extents && !KEY_SIZE(k));
drivers/md/bcache/bset.c
894
preceding_key(&START_KEY(k), &preceding_key_p);
drivers/md/bcache/bset.c
896
preceding_key(k, &preceding_key_p);
drivers/md/bcache/bset.c
90
if (p && !bkey_cmp(p, k))
drivers/md/bcache/bset.c
900
if (b->ops->insert_fixup(b, k, &iter.iter, replace_key))
drivers/md/bcache/bset.c
906
bkey_cmp(k, b->ops->is_extents ? &START_KEY(m) : m) > 0) {
drivers/md/bcache/bset.c
914
bch_bkey_try_merge(b, prev, k))
drivers/md/bcache/bset.c
919
KEY_PTRS(m) == KEY_PTRS(k) && !KEY_SIZE(m))
drivers/md/bcache/bset.c
924
bch_bkey_try_merge(b, k, m))
drivers/md/bcache/bset.c
927
bch_bset_insert(b, m, k);
drivers/md/bcache/bset.c
928
copy: bkey_copy(m, k);
drivers/md/bcache/bset.c
93
p = k;
drivers/md/bcache/bset.h
199
const struct bkey *k);
drivers/md/bcache/bset.h
201
const struct bkey *k);
drivers/md/bcache/bset.h
206
const struct bkey *k);
drivers/md/bcache/bset.h
208
const struct bkey *k);
drivers/md/bcache/bset.h
244
static inline bool bkey_written(struct btree_keys *b, struct bkey *k)
drivers/md/bcache/bset.h
246
return !b->last_set_unwritten || k < b->set[b->nsets].data->start;
drivers/md/bcache/bset.h
261
#define __set_bytes(i, k) (sizeof(*(i)) + (k) * sizeof(uint64_t))
drivers/md/bcache/bset.h
264
#define __set_blocks(i, k, block_bytes) \
drivers/md/bcache/bset.h
265
DIV_ROUND_UP(__set_bytes(i, k), block_bytes)
drivers/md/bcache/bset.h
300
void bch_bset_fix_invalidated_key(struct btree_keys *b, struct bkey *k);
drivers/md/bcache/bset.h
304
unsigned int bch_btree_insert_key(struct btree_keys *b, struct bkey *k,
drivers/md/bcache/bset.h
323
struct bkey *k, *end;
drivers/md/bcache/bset.h
338
typedef bool (*ptr_filter_fn)(struct btree_keys *b, const struct bkey *k);
drivers/md/bcache/bset.h
345
void bch_btree_iter_push(struct btree_iter *iter, struct bkey *k,
drivers/md/bcache/bset.h
364
#define for_each_key_filter(b, k, stack_iter, filter) \
drivers/md/bcache/bset.h
366
((k) = bch_btree_iter_next_filter(&((stack_iter)->iter), (b), \
drivers/md/bcache/bset.h
369
#define for_each_key(b, k, stack_iter) \
drivers/md/bcache/bset.h
371
((k) = bch_btree_iter_next(&((stack_iter)->iter)));)
drivers/md/bcache/bset.h
420
static inline void bkey_init(struct bkey *k)
drivers/md/bcache/bset.h
422
*k = ZERO_KEY;
drivers/md/bcache/bset.h
435
bool __bch_cut_front(const struct bkey *where, struct bkey *k);
drivers/md/bcache/bset.h
436
bool __bch_cut_back(const struct bkey *where, struct bkey *k);
drivers/md/bcache/bset.h
438
static inline bool bch_cut_front(const struct bkey *where, struct bkey *k)
drivers/md/bcache/bset.h
440
BUG_ON(bkey_cmp(where, k) > 0);
drivers/md/bcache/bset.h
441
return __bch_cut_front(where, k);
drivers/md/bcache/bset.h
444
static inline bool bch_cut_back(const struct bkey *where, struct bkey *k)
drivers/md/bcache/bset.h
446
BUG_ON(bkey_cmp(where, &START_KEY(k)) < 0);
drivers/md/bcache/bset.h
447
return __bch_cut_back(where, k);
drivers/md/bcache/bset.h
459
static inline void preceding_key(struct bkey *k, struct bkey **preceding_key_p)
drivers/md/bcache/bset.h
461
if (KEY_INODE(k) || KEY_OFFSET(k)) {
drivers/md/bcache/bset.h
462
(**preceding_key_p) = KEY(KEY_INODE(k), KEY_OFFSET(k), 0);
drivers/md/bcache/bset.h
471
static inline bool bch_ptr_invalid(struct btree_keys *b, const struct bkey *k)
drivers/md/bcache/bset.h
473
return b->ops->key_invalid(b, k);
drivers/md/bcache/bset.h
476
static inline bool bch_ptr_bad(struct btree_keys *b, const struct bkey *k)
drivers/md/bcache/bset.h
478
return b->ops->key_bad(b, k);
drivers/md/bcache/bset.h
482
size_t size, const struct bkey *k)
drivers/md/bcache/bset.h
484
return b->ops->key_to_text(buf, size, k);
drivers/md/bcache/bset.h
517
static inline void bch_keylist_init_single(struct keylist *l, struct bkey *k)
drivers/md/bcache/bset.h
519
l->keys = k;
drivers/md/bcache/bset.h
520
l->top = bkey_next(k);
drivers/md/bcache/bset.h
528
static inline void bch_keylist_add(struct keylist *l, struct bkey *k)
drivers/md/bcache/bset.h
530
bkey_copy(l->top, k);
drivers/md/bcache/btree.c
100
(((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
drivers/md/bcache/btree.c
1006
struct bkey *k, int level, bool write,
drivers/md/bcache/btree.c
1014
b = mca_find(c, k);
drivers/md/bcache/btree.c
1021
b = mca_alloc(c, op, k, level);
drivers/md/bcache/btree.c
1035
if (PTR_HASH(c, &b->key) != PTR_HASH(c, k)) {
drivers/md/bcache/btree.c
1062
static void btree_node_prefetch(struct btree *parent, struct bkey *k)
drivers/md/bcache/btree.c
1067
b = mca_alloc(parent->c, NULL, k, parent->level - 1);
drivers/md/bcache/btree.c
1123
BKEY_PADDED(key) k;
drivers/md/bcache/btree.c
1130
if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, wait))
drivers/md/bcache/btree.c
1133
bkey_put(c, &k.key);
drivers/md/bcache/btree.c
1134
SET_KEY_SIZE(&k.key, c->btree_pages * PAGE_SECTORS);
drivers/md/bcache/btree.c
1136
b = mca_alloc(c, op, &k.key, level);
drivers/md/bcache/btree.c
1154
bch_bucket_free(c, &k.key);
drivers/md/bcache/btree.c
1184
static void make_btree_freeing_key(struct btree *b, struct bkey *k)
drivers/md/bcache/btree.c
1192
bkey_copy(k, &b->key);
drivers/md/bcache/btree.c
1193
bkey_copy_key(k, &ZERO_KEY);
drivers/md/bcache/btree.c
1195
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/btree.c
1196
SET_PTR_GEN(k, i,
drivers/md/bcache/btree.c
1227
struct bkey *k)
drivers/md/bcache/btree.c
1238
if (!bkey_cmp(k, &ZERO_KEY))
drivers/md/bcache/btree.c
1241
for (i = 0; i < KEY_PTRS(k); i++) {
drivers/md/bcache/btree.c
1242
if (!ptr_available(c, k, i))
drivers/md/bcache/btree.c
1245
g = PTR_BUCKET(c, k, i);
drivers/md/bcache/btree.c
1247
if (gen_after(g->last_gc, PTR_GEN(k, i)))
drivers/md/bcache/btree.c
1248
g->last_gc = PTR_GEN(k, i);
drivers/md/bcache/btree.c
1250
if (ptr_stale(c, k, i)) {
drivers/md/bcache/btree.c
1251
stale = max(stale, ptr_stale(c, k, i));
drivers/md/bcache/btree.c
1262
else if (KEY_DIRTY(k))
drivers/md/bcache/btree.c
1269
GC_SECTORS_USED(g) + KEY_SIZE(k),
drivers/md/bcache/btree.c
1278
#define btree_mark_key(b, k) __bch_btree_mark_key(b->c, b->level, k)
drivers/md/bcache/btree.c
128
void bkey_put(struct cache_set *c, struct bkey *k)
drivers/md/bcache/btree.c
1280
void bch_initial_mark_key(struct cache_set *c, int level, struct bkey *k)
drivers/md/bcache/btree.c
1284
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/btree.c
1285
if (ptr_available(c, k, i) &&
drivers/md/bcache/btree.c
1286
!ptr_stale(c, k, i)) {
drivers/md/bcache/btree.c
1287
struct bucket *b = PTR_BUCKET(c, k, i);
drivers/md/bcache/btree.c
1289
b->gen = PTR_GEN(k, i);
drivers/md/bcache/btree.c
1291
if (level && bkey_cmp(k, &ZERO_KEY))
drivers/md/bcache/btree.c
1297
__bch_btree_mark_key(c, level, k);
drivers/md/bcache/btree.c
1309
struct bkey *k;
drivers/md/bcache/btree.c
1315
for_each_key_filter(&b->keys, k, &iter, bch_ptr_invalid) {
drivers/md/bcache/btree.c
1316
stale = max(stale, btree_mark_key(b, k));
drivers/md/bcache/btree.c
1319
if (bch_ptr_bad(&b->keys, k))
drivers/md/bcache/btree.c
132
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/btree.c
1322
gc->key_bytes += bkey_u64s(k);
drivers/md/bcache/btree.c
1326
gc->data += KEY_SIZE(k);
drivers/md/bcache/btree.c
133
if (ptr_available(c, k, i))
drivers/md/bcache/btree.c
134
atomic_dec_bug(&PTR_BUCKET(c, k, i)->pin);
drivers/md/bcache/btree.c
1366
struct bkey *k;
drivers/md/bcache/btree.c
1407
struct bkey *k, *last = NULL;
drivers/md/bcache/btree.c
1412
for (k = n2->start;
drivers/md/bcache/btree.c
1413
k < bset_bkey_last(n2);
drivers/md/bcache/btree.c
1414
k = bkey_next(k)) {
drivers/md/bcache/btree.c
1416
bkey_u64s(k),
drivers/md/bcache/btree.c
1420
last = k;
drivers/md/bcache/btree.c
1421
keys += bkey_u64s(k);
drivers/md/bcache/btree.c
1517
while ((k = bch_keylist_pop(&keylist)))
drivers/md/bcache/btree.c
1518
if (!bkey_cmp(k, &ZERO_KEY))
drivers/md/bcache/btree.c
1570
struct bkey *k;
drivers/md/bcache/btree.c
1574
for_each_key_filter(&b->keys, k, &iter, bch_ptr_bad)
drivers/md/bcache/btree.c
1575
ret += bkey_u64s(k);
drivers/md/bcache/btree.c
1611
struct bkey *k;
drivers/md/bcache/btree.c
1622
k = bch_btree_iter_next_filter(&iter.iter, &b->keys,
drivers/md/bcache/btree.c
1624
if (k) {
drivers/md/bcache/btree.c
1625
r->b = bch_btree_node_get(b->c, op, k, b->level - 1,
drivers/md/bcache/btree.c
1763
uint64_t *k;
drivers/md/bcache/btree.c
1801
for (k = ca->sb.d; k < ca->sb.d + ca->sb.keys; k++)
drivers/md/bcache/btree.c
1802
SET_GC_MARK(ca->buckets + *k, GC_MARK_METADATA);
drivers/md/bcache/btree.c
1804
for (k = ca->prio_buckets;
drivers/md/bcache/btree.c
1805
k < ca->prio_buckets + prio_buckets(ca) * 2; k++)
drivers/md/bcache/btree.c
1806
SET_GC_MARK(ca->buckets + *k, GC_MARK_METADATA);
drivers/md/bcache/btree.c
1916
struct bkey *k, *p = NULL;
drivers/md/bcache/btree.c
1919
for_each_key_filter(&b->keys, k, &iter, bch_ptr_invalid)
drivers/md/bcache/btree.c
1920
bch_initial_mark_key(b->c, b->level, k);
drivers/md/bcache/btree.c
1928
k = bch_btree_iter_next_filter(&iter.iter, &b->keys,
drivers/md/bcache/btree.c
1930
if (k) {
drivers/md/bcache/btree.c
1931
btree_node_prefetch(b, k);
drivers/md/bcache/btree.c
1942
p = k;
drivers/md/bcache/btree.c
1957
struct bkey *k, *p;
drivers/md/bcache/btree.c
1960
k = p = NULL;
drivers/md/bcache/btree.c
1966
k = bch_btree_iter_next_filter(&iter.iter, &c->root->keys, bch_ptr_bad);
drivers/md/bcache/btree.c
1967
BUG_ON(!k);
drivers/md/bcache/btree.c
1969
p = k;
drivers/md/bcache/btree.c
1970
while (k) {
drivers/md/bcache/btree.c
1984
k = bch_btree_iter_next_filter(&iter.iter,
drivers/md/bcache/btree.c
1987
if (k)
drivers/md/bcache/btree.c
1988
p = k;
drivers/md/bcache/btree.c
2056
struct bkey *k = NULL;
drivers/md/bcache/btree.c
2061
for_each_key_filter(&c->root->keys, k, &iter, bch_ptr_invalid)
drivers/md/bcache/btree.c
2062
bch_initial_mark_key(c, c->root->level, k);
drivers/md/bcache/btree.c
2163
static bool btree_insert_key(struct btree *b, struct bkey *k,
drivers/md/bcache/btree.c
2168
BUG_ON(bkey_cmp(k, &b->key) > 0);
drivers/md/bcache/btree.c
2170
status = bch_btree_insert_key(&b->keys, k, replace_key);
drivers/md/bcache/btree.c
2175
trace_bcache_btree_insert_key(b, k, replace_key != NULL,
drivers/md/bcache/btree.c
2203
struct bkey *k = insert_keys->keys;
drivers/md/bcache/btree.c
2205
if (bkey_u64s(k) > insert_u64s_remaining(b))
drivers/md/bcache/btree.c
2208
if (bkey_cmp(k, &b->key) <= 0) {
drivers/md/bcache/btree.c
2210
bkey_put(b->c, k);
drivers/md/bcache/btree.c
2212
ret |= btree_insert_key(b, k, replace_key);
drivers/md/bcache/btree.c
2214
} else if (bkey_cmp(&START_KEY(k), &b->key) < 0) {
drivers/md/bcache/btree.c
2507
struct bkey *k;
drivers/md/bcache/btree.c
2511
while ((k = bch_keylist_pop(keys)))
drivers/md/bcache/btree.c
2512
bkey_put(c, k);
drivers/md/bcache/btree.c
2552
struct bkey *k;
drivers/md/bcache/btree.c
2557
while ((k = bch_btree_iter_next_filter(&iter.iter, &b->keys,
drivers/md/bcache/btree.c
2559
ret = bcache_btree(map_nodes_recurse, k, b,
drivers/md/bcache/btree.c
2585
struct bkey *k;
drivers/md/bcache/btree.c
2590
while ((k = bch_btree_iter_next_filter(&iter.iter, &b->keys,
drivers/md/bcache/btree.c
2593
? fn(op, b, k)
drivers/md/bcache/btree.c
2594
: bcache_btree(map_keys_recurse, k,
drivers/md/bcache/btree.c
2642
struct bkey *k)
drivers/md/bcache/btree.c
2648
if (bkey_cmp(k, refill->end) > 0) {
drivers/md/bcache/btree.c
2653
if (!KEY_SIZE(k)) /* end key */
drivers/md/bcache/btree.c
2656
if (refill->pred(buf, k)) {
drivers/md/bcache/btree.c
2668
bkey_copy(&w->key, k);
drivers/md/bcache/btree.c
2681
buf->last_scanned = *k;
drivers/md/bcache/btree.c
342
BKEY_PADDED(key) k;
drivers/md/bcache/btree.c
371
bkey_copy(&k.key, &b->key);
drivers/md/bcache/btree.c
372
SET_PTR_OFFSET(&k.key, 0, PTR_OFFSET(&k.key, 0) +
drivers/md/bcache/btree.c
385
bch_submit_bbio(b->bio, b->c, &k.key, 0);
drivers/md/bcache/btree.c
396
bch_submit_bbio(b->bio, b->c, &k.key, 0);
drivers/md/bcache/btree.c
543
static unsigned int btree_order(struct bkey *k)
drivers/md/bcache/btree.c
545
return ilog2(KEY_SIZE(k) / PAGE_SECTORS ?: 1);
drivers/md/bcache/btree.c
548
static void mca_data_alloc(struct btree *b, struct bkey *k, gfp_t gfp)
drivers/md/bcache/btree.c
553
btree_order(k)),
drivers/md/bcache/btree.c
582
struct bkey *k, gfp_t gfp)
drivers/md/bcache/btree.c
602
mca_data_alloc(b, k, gfp);
drivers/md/bcache/btree.c
848
static struct hlist_head *mca_hash(struct cache_set *c, struct bkey *k)
drivers/md/bcache/btree.c
850
return &c->bucket_hash[hash_32(PTR_HASH(c, k), BUCKET_HASH_BITS)];
drivers/md/bcache/btree.c
853
static struct btree *mca_find(struct cache_set *c, struct bkey *k)
drivers/md/bcache/btree.c
858
hlist_for_each_entry_rcu(b, mca_hash(c, k), hash)
drivers/md/bcache/btree.c
859
if (PTR_HASH(c, &b->key) == PTR_HASH(c, k))
drivers/md/bcache/btree.c
885
struct bkey *k)
drivers/md/bcache/btree.c
895
if (!mca_reap(b, btree_order(k), false))
drivers/md/bcache/btree.c
899
if (!mca_reap(b, btree_order(k), true))
drivers/md/bcache/btree.c
923
struct bkey *k, int level)
drivers/md/bcache/btree.c
931
if (mca_find(c, k))
drivers/md/bcache/btree.c
938
if (!mca_reap(b, btree_order(k), false))
drivers/md/bcache/btree.c
946
mca_data_alloc(b, k, __GFP_NOWARN|GFP_NOIO);
drivers/md/bcache/btree.c
953
b = mca_bucket_alloc(c, k, __GFP_NOWARN|GFP_NOIO);
drivers/md/bcache/btree.c
963
bkey_copy(&b->key, k);
drivers/md/bcache/btree.c
966
hlist_add_head_rcu(&b->hash, mca_hash(c, k));
drivers/md/bcache/btree.c
986
b = mca_cannibalize(c, op, k);
drivers/md/bcache/btree.c
99
#define PTR_HASH(c, k) \
drivers/md/bcache/btree.h
200
void bkey_put(struct cache_set *c, struct bkey *k);
drivers/md/bcache/btree.h
272
struct bkey *k, int level, bool write,
drivers/md/bcache/btree.h
284
void bch_initial_mark_key(struct cache_set *c, int level, struct bkey *k);
drivers/md/bcache/btree.h
396
struct bkey *k);
drivers/md/bcache/btree.h
403
typedef bool (keybuf_pred_fn)(struct keybuf *buf, struct bkey *k);
drivers/md/bcache/debug.c
166
static bool dump_pred(struct keybuf *buf, struct bkey *k)
drivers/md/bcache/extents.c
104
p("%llu:%llu len %llu -> [", KEY_INODE(k), KEY_START(k), KEY_SIZE(k));
drivers/md/bcache/extents.c
106
for (i = 0; i < KEY_PTRS(k); i++) {
drivers/md/bcache/extents.c
110
if (PTR_DEV(k, i) == PTR_CHECK_DEV)
drivers/md/bcache/extents.c
113
p("%llu:%llu gen %llu", PTR_DEV(k, i),
drivers/md/bcache/extents.c
114
PTR_OFFSET(k, i), PTR_GEN(k, i));
drivers/md/bcache/extents.c
119
if (KEY_DIRTY(k))
drivers/md/bcache/extents.c
121
if (KEY_CSUM(k))
drivers/md/bcache/extents.c
122
p(" cs%llu %llx", KEY_CSUM(k), k->ptr[1]);
drivers/md/bcache/extents.c
126
static void bch_bkey_dump(struct btree_keys *keys, const struct bkey *k)
drivers/md/bcache/extents.c
132
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/extents.c
135
for (j = 0; j < KEY_PTRS(k); j++) {
drivers/md/bcache/extents.c
136
size_t n = PTR_BUCKET_NR(b->c, k, j);
drivers/md/bcache/extents.c
141
PTR_BUCKET(b->c, k, j)->prio);
drivers/md/bcache/extents.c
144
pr_cont(" %s\n", bch_ptr_status(b->c, k));
drivers/md/bcache/extents.c
149
bool __bch_btree_ptr_invalid(struct cache_set *c, const struct bkey *k)
drivers/md/bcache/extents.c
153
if (!KEY_PTRS(k) || !KEY_SIZE(k) || KEY_DIRTY(k))
drivers/md/bcache/extents.c
156
if (__ptr_invalid(c, k))
drivers/md/bcache/extents.c
161
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/extents.c
162
cache_bug(c, "spotted btree ptr %s: %s", buf, bch_ptr_status(c, k));
drivers/md/bcache/extents.c
166
static bool bch_btree_ptr_invalid(struct btree_keys *bk, const struct bkey *k)
drivers/md/bcache/extents.c
170
return __bch_btree_ptr_invalid(b->c, k);
drivers/md/bcache/extents.c
173
static bool btree_ptr_bad_expensive(struct btree *b, const struct bkey *k)
drivers/md/bcache/extents.c
180
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/extents.c
181
if (ptr_available(b->c, k, i)) {
drivers/md/bcache/extents.c
182
g = PTR_BUCKET(b->c, k, i);
drivers/md/bcache/extents.c
184
if (KEY_DIRTY(k) ||
drivers/md/bcache/extents.c
197
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/extents.c
200
buf, PTR_BUCKET_NR(b->c, k, i), atomic_read(&g->pin),
drivers/md/bcache/extents.c
205
static bool bch_btree_ptr_bad(struct btree_keys *bk, const struct bkey *k)
drivers/md/bcache/extents.c
210
if (!bkey_cmp(k, &ZERO_KEY) ||
drivers/md/bcache/extents.c
211
!KEY_PTRS(k) ||
drivers/md/bcache/extents.c
212
bch_ptr_invalid(bk, k))
drivers/md/bcache/extents.c
215
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/extents.c
216
if (!ptr_available(b->c, k, i) ||
drivers/md/bcache/extents.c
217
ptr_stale(b->c, k, i))
drivers/md/bcache/extents.c
221
btree_ptr_bad_expensive(b, k))
drivers/md/bcache/extents.c
261
int64_t c = bkey_cmp(&START_KEY(l.k), &START_KEY(r.k));
drivers/md/bcache/extents.c
263
return c ? c > 0 : l.k < r.k;
drivers/md/bcache/extents.c
276
if (bkey_cmp(top->k, &START_KEY(i->k)) <= 0)
drivers/md/bcache/extents.c
279
if (!KEY_SIZE(i->k)) {
drivers/md/bcache/extents.c
285
if (top->k > i->k) {
drivers/md/bcache/extents.c
286
if (bkey_cmp(top->k, i->k) >= 0)
drivers/md/bcache/extents.c
289
bch_cut_front(top->k, i->k);
drivers/md/bcache/extents.c
294
BUG_ON(!bkey_cmp(&START_KEY(top->k), &START_KEY(i->k)));
drivers/md/bcache/extents.c
296
if (bkey_cmp(i->k, top->k) < 0) {
drivers/md/bcache/extents.c
297
bkey_copy(tmp, top->k);
drivers/md/bcache/extents.c
299
bch_cut_back(&START_KEY(i->k), tmp);
drivers/md/bcache/extents.c
300
bch_cut_front(i->k, top->k);
drivers/md/bcache/extents.c
305
bch_cut_back(&START_KEY(i->k), top->k);
drivers/md/bcache/extents.c
313
static void bch_subtract_dirty(struct bkey *k,
drivers/md/bcache/extents.c
318
if (KEY_DIRTY(k))
drivers/md/bcache/extents.c
319
bcache_dev_sectors_dirty_add(c, KEY_INODE(k),
drivers/md/bcache/extents.c
33
i->k = bkey_next(i->k);
drivers/md/bcache/extents.c
337
struct bkey *k = bch_btree_iter_next(iter);
drivers/md/bcache/extents.c
339
if (!k)
drivers/md/bcache/extents.c
342
if (bkey_cmp(&START_KEY(k), insert) >= 0) {
drivers/md/bcache/extents.c
343
if (KEY_SIZE(k))
drivers/md/bcache/extents.c
349
if (bkey_cmp(k, &START_KEY(insert)) <= 0)
drivers/md/bcache/extents.c
35
if (i->k == i->end)
drivers/md/bcache/extents.c
352
old_offset = KEY_START(k);
drivers/md/bcache/extents.c
353
old_size = KEY_SIZE(k);
drivers/md/bcache/extents.c
363
if (replace_key && KEY_SIZE(k)) {
drivers/md/bcache/extents.c
369
uint64_t offset = KEY_START(k) -
drivers/md/bcache/extents.c
373
if (KEY_START(k) < KEY_START(replace_key) ||
drivers/md/bcache/extents.c
374
KEY_OFFSET(k) > KEY_OFFSET(replace_key))
drivers/md/bcache/extents.c
378
if (KEY_START(k) > KEY_START(insert) + sectors_found)
drivers/md/bcache/extents.c
381
if (!bch_bkey_equal_header(k, replace_key))
drivers/md/bcache/extents.c
390
if (k->ptr[i] != replace_key->ptr[i] + offset)
drivers/md/bcache/extents.c
393
sectors_found = KEY_OFFSET(k) - KEY_START(insert);
drivers/md/bcache/extents.c
396
if (bkey_cmp(insert, k) < 0 &&
drivers/md/bcache/extents.c
397
bkey_cmp(&START_KEY(insert), &START_KEY(k)) > 0) {
drivers/md/bcache/extents.c
407
bch_subtract_dirty(k, c, KEY_START(insert),
drivers/md/bcache/extents.c
410
if (bkey_written(b, k)) {
drivers/md/bcache/extents.c
42
int64_t c = bkey_cmp(l.k, r.k);
drivers/md/bcache/extents.c
425
bch_bset_insert(b, top, k);
drivers/md/bcache/extents.c
428
bkey_copy(&temp.key, k);
drivers/md/bcache/extents.c
429
bch_bset_insert(b, k, &temp.key);
drivers/md/bcache/extents.c
430
top = bkey_next(k);
drivers/md/bcache/extents.c
434
bch_cut_back(&START_KEY(insert), k);
drivers/md/bcache/extents.c
435
bch_bset_fix_invalidated_key(b, k);
drivers/md/bcache/extents.c
439
if (bkey_cmp(insert, k) < 0) {
drivers/md/bcache/extents.c
44
return c ? c > 0 : l.k < r.k;
drivers/md/bcache/extents.c
440
bch_cut_front(insert, k);
drivers/md/bcache/extents.c
442
if (bkey_cmp(&START_KEY(insert), &START_KEY(k)) > 0)
drivers/md/bcache/extents.c
445
if (bkey_written(b, k) &&
drivers/md/bcache/extents.c
446
bkey_cmp(&START_KEY(insert), &START_KEY(k)) <= 0) {
drivers/md/bcache/extents.c
451
bch_cut_front(k, k);
drivers/md/bcache/extents.c
453
__bch_cut_back(&START_KEY(insert), k);
drivers/md/bcache/extents.c
454
bch_bset_fix_invalidated_key(b, k);
drivers/md/bcache/extents.c
458
bch_subtract_dirty(k, c, old_offset, old_size - KEY_SIZE(k));
drivers/md/bcache/extents.c
47
static bool __ptr_invalid(struct cache_set *c, const struct bkey *k)
drivers/md/bcache/extents.c
480
bool __bch_extent_invalid(struct cache_set *c, const struct bkey *k)
drivers/md/bcache/extents.c
484
if (!KEY_SIZE(k))
drivers/md/bcache/extents.c
487
if (KEY_SIZE(k) > KEY_OFFSET(k))
drivers/md/bcache/extents.c
490
if (__ptr_invalid(c, k))
drivers/md/bcache/extents.c
495
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/extents.c
496
cache_bug(c, "spotted extent %s: %s", buf, bch_ptr_status(c, k));
drivers/md/bcache/extents.c
500
static bool bch_extent_invalid(struct btree_keys *bk, const struct bkey *k)
drivers/md/bcache/extents.c
504
return __bch_extent_invalid(b->c, k);
drivers/md/bcache/extents.c
507
static bool bch_extent_bad_expensive(struct btree *b, const struct bkey *k,
drivers/md/bcache/extents.c
51
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/extents.c
510
struct bucket *g = PTR_BUCKET(b->c, k, ptr);
drivers/md/bcache/extents.c
517
(GC_MARK(g) != GC_MARK_DIRTY && KEY_DIRTY(k))))
drivers/md/bcache/extents.c
52
if (ptr_available(c, k, i)) {
drivers/md/bcache/extents.c
529
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/extents.c
532
buf, PTR_BUCKET_NR(b->c, k, ptr), atomic_read(&g->pin),
drivers/md/bcache/extents.c
537
static bool bch_extent_bad(struct btree_keys *bk, const struct bkey *k)
drivers/md/bcache/extents.c
54
size_t bucket = PTR_BUCKET_NR(c, k, i);
drivers/md/bcache/extents.c
543
if (!KEY_PTRS(k) ||
drivers/md/bcache/extents.c
544
bch_extent_invalid(bk, k))
drivers/md/bcache/extents.c
547
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/extents.c
548
if (!ptr_available(b->c, k, i))
drivers/md/bcache/extents.c
55
size_t r = bucket_remainder(c, PTR_OFFSET(k, i));
drivers/md/bcache/extents.c
551
for (i = 0; i < KEY_PTRS(k); i++) {
drivers/md/bcache/extents.c
552
stale = ptr_stale(b->c, k, i);
drivers/md/bcache/extents.c
554
if (stale && KEY_DIRTY(k)) {
drivers/md/bcache/extents.c
555
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/extents.c
568
bch_extent_bad_expensive(b, k, i))
drivers/md/bcache/extents.c
57
if (KEY_SIZE(k) + r > c->cache->sb.bucket_size ||
drivers/md/bcache/extents.c
68
static const char *bch_ptr_status(struct cache_set *c, const struct bkey *k)
drivers/md/bcache/extents.c
72
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/extents.c
73
if (ptr_available(c, k, i)) {
drivers/md/bcache/extents.c
75
size_t bucket = PTR_BUCKET_NR(c, k, i);
drivers/md/bcache/extents.c
76
size_t r = bucket_remainder(c, PTR_OFFSET(k, i));
drivers/md/bcache/extents.c
78
if (KEY_SIZE(k) + r > c->cache->sb.bucket_size)
drivers/md/bcache/extents.c
84
if (ptr_stale(c, k, i))
drivers/md/bcache/extents.c
88
if (!bkey_cmp(k, &ZERO_KEY))
drivers/md/bcache/extents.c
90
if (!KEY_PTRS(k))
drivers/md/bcache/extents.c
92
if (!KEY_SIZE(k))
drivers/md/bcache/extents.c
97
void bch_extent_to_text(char *buf, size_t size, const struct bkey *k)
drivers/md/bcache/extents.h
11
void bch_extent_to_text(char *buf, size_t size, const struct bkey *k);
drivers/md/bcache/extents.h
12
bool __bch_btree_ptr_invalid(struct cache_set *c, const struct bkey *k);
drivers/md/bcache/extents.h
13
bool __bch_extent_invalid(struct cache_set *c, const struct bkey *k);
drivers/md/bcache/io.c
46
struct bkey *k, unsigned int ptr)
drivers/md/bcache/io.c
50
bch_bkey_copy_single_ptr(&b->key, k, ptr);
drivers/md/bcache/journal.c
295
struct bkey *k;
drivers/md/bcache/journal.c
323
for (k = i->j.start;
drivers/md/bcache/journal.c
324
k < bset_bkey_last(&i->j);
drivers/md/bcache/journal.c
325
k = bkey_next(k))
drivers/md/bcache/journal.c
326
if (!__bch_extent_invalid(c, k)) {
drivers/md/bcache/journal.c
329
for (j = 0; j < KEY_PTRS(k); j++)
drivers/md/bcache/journal.c
330
if (ptr_available(c, k, j))
drivers/md/bcache/journal.c
331
atomic_inc(&PTR_BUCKET(c, k, j)->pin);
drivers/md/bcache/journal.c
333
bch_initial_mark_key(c, 0, k);
drivers/md/bcache/journal.c
341
struct bkey *k;
drivers/md/bcache/journal.c
358
for (k = i->j.start;
drivers/md/bcache/journal.c
359
k < bset_bkey_last(&i->j);
drivers/md/bcache/journal.c
360
k = bkey_next(k)) {
drivers/md/bcache/journal.c
361
trace_bcache_journal_replay_key(k);
drivers/md/bcache/journal.c
363
bch_keylist_init_single(&keylist, k);
drivers/md/bcache/journal.c
576
struct bkey *k = &c->journal.key;
drivers/md/bcache/journal.c
603
k->ptr[0] = MAKE_PTR(0,
drivers/md/bcache/journal.c
608
bkey_init(k);
drivers/md/bcache/journal.c
609
SET_KEY_PTRS(k, 1);
drivers/md/bcache/journal.c
677
struct bkey *k = &c->journal.key;
drivers/md/bcache/journal.c
711
for (i = 0; i < KEY_PTRS(k); i++) {
drivers/md/bcache/journal.c
719
bio->bi_iter.bi_sector = PTR_OFFSET(k, i);
drivers/md/bcache/journal.c
729
SET_PTR_OFFSET(k, i, PTR_OFFSET(k, i) + sectors);
drivers/md/bcache/movinggc.c
22
static bool moving_pred(struct keybuf *buf, struct bkey *k)
drivers/md/bcache/movinggc.c
28
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/movinggc.c
29
if (ptr_available(c, k, i) &&
drivers/md/bcache/movinggc.c
30
GC_MOVE(PTR_BUCKET(c, k, i)))
drivers/md/bcache/request.c
206
struct bkey *k;
drivers/md/bcache/request.c
217
k = op->insert_keys.top;
drivers/md/bcache/request.c
218
bkey_init(k);
drivers/md/bcache/request.c
219
SET_KEY_INODE(k, op->inode);
drivers/md/bcache/request.c
220
SET_KEY_OFFSET(k, bio->bi_iter.bi_sector);
drivers/md/bcache/request.c
222
if (!bch_alloc_sectors(op->c, k, bio_sectors(bio),
drivers/md/bcache/request.c
227
n = bio_next_split(bio, KEY_SIZE(k), GFP_NOIO, split);
drivers/md/bcache/request.c
233
SET_KEY_DIRTY(k, true);
drivers/md/bcache/request.c
235
for (i = 0; i < KEY_PTRS(k); i++)
drivers/md/bcache/request.c
236
SET_GC_MARK(PTR_BUCKET(op->c, k, i),
drivers/md/bcache/request.c
240
SET_KEY_CSUM(k, op->csum);
drivers/md/bcache/request.c
241
if (KEY_CSUM(k))
drivers/md/bcache/request.c
242
bio_csum(n, k);
drivers/md/bcache/request.c
244
trace_bcache_cache_insert(k);
drivers/md/bcache/request.c
248
bch_submit_bbio(n, op->c, k, 0);
drivers/md/bcache/request.c
358
static struct hlist_head *iohash(struct cached_dev *dc, uint64_t k)
drivers/md/bcache/request.c
360
return &dc->io_hash[hash_64(k, RECENT_IO_BITS)];
drivers/md/bcache/request.c
40
static void bio_csum(struct bio *bio, struct bkey *k)
drivers/md/bcache/request.c
527
static int cache_lookup_fn(struct btree_op *op, struct btree *b, struct bkey *k)
drivers/md/bcache/request.c
53
k->ptr[KEY_PTRS(k)] = csum & (~0ULL >> 1);
drivers/md/bcache/request.c
534
if (bkey_cmp(k, &KEY(s->iop.inode, bio->bi_iter.bi_sector, 0)) <= 0)
drivers/md/bcache/request.c
537
if (KEY_INODE(k) != s->iop.inode ||
drivers/md/bcache/request.c
538
KEY_START(k) > bio->bi_iter.bi_sector) {
drivers/md/bcache/request.c
540
unsigned int sectors = KEY_INODE(k) == s->iop.inode
drivers/md/bcache/request.c
542
KEY_START(k) - bio->bi_iter.bi_sector)
drivers/md/bcache/request.c
553
if (!KEY_SIZE(k))
drivers/md/bcache/request.c
559
PTR_BUCKET(b->c, k, ptr)->prio = INITIAL_PRIO;
drivers/md/bcache/request.c
561
if (KEY_DIRTY(k))
drivers/md/bcache/request.c
565
KEY_OFFSET(k) - bio->bi_iter.bi_sector),
drivers/md/bcache/request.c
569
bch_bkey_copy_single_ptr(bio_key, k, ptr);
drivers/md/bcache/stats.c
77
static void bch_stats_release(struct kobject *k)
drivers/md/bcache/super.c
1993
struct bkey *k;
drivers/md/bcache/super.c
2018
k = &j->btree_root;
drivers/md/bcache/super.c
2021
if (__bch_btree_ptr_invalid(c, k))
drivers/md/bcache/super.c
2025
c->root = bch_btree_node_get(c, NULL, k,
drivers/md/bcache/super.c
2437
static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
drivers/md/bcache/super.c
2439
static ssize_t bch_pending_bdevs_cleanup(struct kobject *k,
drivers/md/bcache/super.c
2549
static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
drivers/md/bcache/super.c
2699
static ssize_t bch_pending_bdevs_cleanup(struct kobject *k,
drivers/md/bcache/super.c
416
static void uuid_io(struct cache_set *c, blk_opf_t opf, struct bkey *k,
drivers/md/bcache/super.c
428
for (i = 0; i < KEY_PTRS(k); i++) {
drivers/md/bcache/super.c
432
bio->bi_iter.bi_size = KEY_SIZE(k) << 9;
drivers/md/bcache/super.c
438
bch_submit_bbio(bio, c, k, i);
drivers/md/bcache/super.c
444
bch_extent_to_text(buf, sizeof(buf), k);
drivers/md/bcache/super.c
459
struct bkey *k = &j->uuid_bucket;
drivers/md/bcache/super.c
461
if (__bch_btree_ptr_invalid(c, k))
drivers/md/bcache/super.c
464
bkey_copy(&c->uuid_bucket, k);
drivers/md/bcache/super.c
465
uuid_io(c, REQ_OP_READ, k, cl);
drivers/md/bcache/super.c
500
BKEY_PADDED(key) k;
drivers/md/bcache/super.c
508
if (bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, true))
drivers/md/bcache/super.c
512
SET_KEY_SIZE(&k.key, size);
drivers/md/bcache/super.c
513
uuid_io(c, REQ_OP_WRITE, &k.key, &cl);
drivers/md/bcache/super.c
519
bkey_copy(&c->uuid_bucket, &k.key);
drivers/md/bcache/super.c
520
bkey_put(c, &k.key);
drivers/md/bcache/sysfs.c
660
struct bkey *k;
drivers/md/bcache/sysfs.c
673
for_each_key_filter(&b->keys, k, &iter, bch_ptr_bad)
drivers/md/bcache/sysfs.c
674
bytes += bkey_bytes(k);
drivers/md/bcache/sysfs.c
950
static void bch_cache_set_internal_release(struct kobject *k)
drivers/md/bcache/writeback.c
1001
k, &iter, bch_ptr_invalid) {
drivers/md/bcache/writeback.c
1002
if (KEY_INODE(k) != op.inode)
drivers/md/bcache/writeback.c
1004
sectors_dirty_init_fn(&op.op, c->root, k);
drivers/md/bcache/writeback.c
641
static bool dirty_pred(struct keybuf *buf, struct bkey *k)
drivers/md/bcache/writeback.c
647
BUG_ON(KEY_INODE(k) != dc->disk.id);
drivers/md/bcache/writeback.c
649
return KEY_DIRTY(k);
drivers/md/bcache/writeback.c
853
struct bkey *k)
drivers/md/bcache/writeback.c
857
if (KEY_INODE(k) > op->inode)
drivers/md/bcache/writeback.c
860
if (KEY_DIRTY(k))
drivers/md/bcache/writeback.c
861
bcache_dev_sectors_dirty_add(b->c, KEY_INODE(k),
drivers/md/bcache/writeback.c
862
KEY_START(k), KEY_SIZE(k));
drivers/md/bcache/writeback.c
873
struct bkey *k)
drivers/md/bcache/writeback.c
883
k,
drivers/md/bcache/writeback.c
911
struct bkey *k, *p;
drivers/md/bcache/writeback.c
914
k = p = NULL;
drivers/md/bcache/writeback.c
918
k = bch_btree_iter_next_filter(&iter.iter, &c->root->keys, bch_ptr_bad);
drivers/md/bcache/writeback.c
919
BUG_ON(!k);
drivers/md/bcache/writeback.c
921
p = k;
drivers/md/bcache/writeback.c
923
while (k) {
drivers/md/bcache/writeback.c
932
k = bch_btree_iter_next_filter(&iter.iter,
drivers/md/bcache/writeback.c
935
if (k)
drivers/md/bcache/writeback.c
936
p = k;
drivers/md/bcache/writeback.c
980
struct bkey *k = NULL;
drivers/md/dm-cache-target.c
106
struct continuation *k;
drivers/md/dm-cache-target.c
1079
init_continuation(&mg->k, continuation);
drivers/md/dm-cache-target.c
1080
dm_cell_quiesce_v2(mg->cache->prison, mg->cell, &mg->k.ws);
drivers/md/dm-cache-target.c
1085
struct continuation *k = container_of(ws, struct continuation, ws);
drivers/md/dm-cache-target.c
1087
return container_of(k, struct dm_cache_migration, k);
drivers/md/dm-cache-target.c
1092
struct dm_cache_migration *mg = container_of(context, struct dm_cache_migration, k);
drivers/md/dm-cache-target.c
1095
mg->k.input = BLK_STS_IOERR;
drivers/md/dm-cache-target.c
1097
queue_continuation(mg->cache->wq, &mg->k);
drivers/md/dm-cache-target.c
1114
dm_kcopyd_copy(cache->copier, &o_region, 1, &c_region, 0, copy_complete, &mg->k);
drivers/md/dm-cache-target.c
1116
dm_kcopyd_copy(cache->copier, &c_region, 1, &o_region, 0, copy_complete, &mg->k);
drivers/md/dm-cache-target.c
1137
mg->k.input = bio->bi_status;
drivers/md/dm-cache-target.c
1139
queue_continuation(cache->wq, &mg->k);
drivers/md/dm-cache-target.c
1159
init_continuation(&mg->k, continuation);
drivers/md/dm-cache-target.c
1192
else if (mg->k.input)
drivers/md/dm-cache-target.c
1193
mg->overwrite_bio->bi_status = mg->k.input;
drivers/md/dm-cache-target.c
1239
mg_complete(mg, mg->k.input == 0);
drivers/md/dm-cache-target.c
126
k = container_of(ws, struct continuation, ws);
drivers/md/dm-cache-target.c
127
k->input = r;
drivers/md/dm-cache-target.c
1293
init_continuation(&mg->k, mg_success);
drivers/md/dm-cache-target.c
1294
continue_after_commit(&cache->committer, &mg->k);
drivers/md/dm-cache-target.c
1311
if (mg->k.input)
drivers/md/dm-cache-target.c
1325
if (mg->k.input)
drivers/md/dm-cache-target.c
1358
init_continuation(&mg->k, mg_upgrade_lock);
drivers/md/dm-cache-target.c
1426
mg_copy(&mg->k.ws);
drivers/md/dm-cache-target.c
1481
invalidate_complete(mg, !mg->k.input);
drivers/md/dm-cache-target.c
1521
init_continuation(&mg->k, invalidate_completed);
drivers/md/dm-cache-target.c
1522
continue_after_commit(&cache->committer, &mg->k);
drivers/md/dm-cache-target.c
1557
init_continuation(&mg->k, invalidate_remove);
drivers/md/dm-cache-target.c
1558
queue_work(cache->wq, &mg->k.ws);
drivers/md/dm-cache-target.c
166
static void continue_after_commit(struct batcher *b, struct continuation *k)
drivers/md/dm-cache-target.c
172
list_add_tail(&k->ws.entry, &b->work_items);
drivers/md/dm-cache-target.c
426
struct continuation k;
drivers/md/dm-cache-target.c
54
static inline void init_continuation(struct continuation *k,
drivers/md/dm-cache-target.c
57
INIT_WORK(&k->ws, fn);
drivers/md/dm-cache-target.c
58
k->input = 0;
drivers/md/dm-cache-target.c
62
struct continuation *k)
drivers/md/dm-cache-target.c
64
queue_work(wq, &k->ws);
drivers/md/dm-integrity.c
2943
unsigned int k, l, next_loop;
drivers/md/dm-integrity.c
2964
for (k = j + 1; k < ic->journal_section_entries; k++) {
drivers/md/dm-integrity.c
2965
struct journal_entry *je2 = access_journal_entry(ic, i, k);
drivers/md/dm-integrity.c
2975
if (area2 != area || offset2 != offset + ((k - j) << ic->sb->log2_sectors_per_block))
drivers/md/dm-integrity.c
2977
restore_last_bytes(ic, access_journal_data(ic, i, k), je2);
drivers/md/dm-integrity.c
2979
next_loop = k - 1;
drivers/md/dm-integrity.c
2984
io->range.n_sectors = (k - j) << ic->sb->log2_sectors_per_block;
drivers/md/dm-integrity.c
2993
while (j < k && find_newer_committed_node(ic, &section_node[j])) {
drivers/md/dm-integrity.c
3002
while (j < k && find_newer_committed_node(ic, &section_node[k - 1])) {
drivers/md/dm-integrity.c
3003
struct journal_entry *je2 = access_journal_entry(ic, i, k - 1);
drivers/md/dm-integrity.c
3006
remove_journal_node(ic, &section_node[k - 1]);
drivers/md/dm-integrity.c
3007
k--;
drivers/md/dm-integrity.c
3009
if (j == k) {
drivers/md/dm-integrity.c
3015
for (l = j; l < k; l++)
drivers/md/dm-integrity.c
3021
for (l = j; l < k; l++) {
drivers/md/dm-integrity.c
3052
(k - j) << ic->sb->log2_sectors_per_block,
drivers/md/dm-integrity.c
3539
unsigned char k;
drivers/md/dm-integrity.c
3541
for (k = 0; k < N_COMMIT_IDS; k++) {
drivers/md/dm-integrity.c
3542
if (dm_integrity_commit_id(ic, i, j, k) == id)
drivers/md/dm-integrity.c
3543
return k;
drivers/md/dm-integrity.c
3593
int k;
drivers/md/dm-integrity.c
3596
k = find_commit_seq(ic, i, j, js->commit_id);
drivers/md/dm-integrity.c
3597
if (k < 0)
drivers/md/dm-integrity.c
3599
used_commit_ids[k] = true;
drivers/md/dm-integrity.c
3600
max_commit_id_sections[k] = i;
drivers/md/dm-integrity.c
4332
char *k;
drivers/md/dm-integrity.c
4340
k = strchr(a->alg_string, ':');
drivers/md/dm-integrity.c
4341
if (k) {
drivers/md/dm-integrity.c
4342
*k = 0;
drivers/md/dm-integrity.c
4343
a->key_string = k + 1;
drivers/md/dm-table.c
1567
unsigned int l, n = 0, k = 0;
drivers/md/dm-table.c
1574
n = get_child(n, k);
drivers/md/dm-table.c
1577
for (k = 0; k < KEYS_PER_NODE; k++)
drivers/md/dm-table.c
1578
if (node[k] >= sector)
drivers/md/dm-table.c
1582
return &t->targets[(KEYS_PER_NODE * n) + k];
drivers/md/dm-table.c
52
static inline unsigned int get_child(unsigned int n, unsigned int k)
drivers/md/dm-table.c
54
return (n * CHILDREN_PER_NODE) + k;
drivers/md/dm-table.c
87
unsigned int n, k;
drivers/md/dm-table.c
93
for (k = 0U; k < KEYS_PER_NODE; k++)
drivers/md/dm-table.c
94
node[k] = high(t, l + 1, get_child(n, k));
drivers/md/dm-vdo/murmurhash3.c
22
static __always_inline u64 fmix64(u64 k)
drivers/md/dm-vdo/murmurhash3.c
24
k ^= k >> 33;
drivers/md/dm-vdo/murmurhash3.c
25
k *= 0xff51afd7ed558ccdLLU;
drivers/md/dm-vdo/murmurhash3.c
26
k ^= k >> 33;
drivers/md/dm-vdo/murmurhash3.c
27
k *= 0xc4ceb9fe1a85ec53LLU;
drivers/md/dm-vdo/murmurhash3.c
28
k ^= k >> 33;
drivers/md/dm-vdo/murmurhash3.c
30
return k;
drivers/md/dm-verity-fec.c
204
unsigned int n, k;
drivers/md/dm-verity-fec.c
280
k = fec_buffer_rs_index(n, j) + block_offset;
drivers/md/dm-verity-fec.c
282
if (k >= 1 << v->data_dev_block_bits)
drivers/md/dm-verity-fec.c
286
rs_block[i] = bbuf[k];
drivers/md/md-bitmap.c
2006
unsigned long k, pages;
drivers/md/md-bitmap.c
2033
for (k = 0; k < pages; k++)
drivers/md/md-bitmap.c
2034
if (bp[k].map && !bp[k].hijacked)
drivers/md/md-bitmap.c
2035
kfree(bp[k].map);
drivers/md/md-bitmap.c
2478
unsigned long k;
drivers/md/md-bitmap.c
2481
for (k = 0; k < page; k++) {
drivers/md/md-bitmap.c
2482
kfree(new_bp[k].map);
drivers/md/md-bitmap.c
2535
unsigned long k;
drivers/md/md-bitmap.c
2536
for (k = 0; k < old_counts.pages; k++)
drivers/md/md-bitmap.c
2537
if (!old_counts.bp[k].hijacked)
drivers/md/md-bitmap.c
2538
kfree(old_counts.bp[k].map);
drivers/md/persistent-data/dm-btree-remove.c
701
uint64_t k;
drivers/md/persistent-data/dm-btree-remove.c
730
k = le64_to_cpu(n->keys[index]);
drivers/md/persistent-data/dm-btree-remove.c
731
if (k >= keys[last_level] && k < end_key) {
drivers/md/persistent-data/dm-btree-remove.c
737
keys[last_level] = k + 1ull;
drivers/md/raid0.c
39
int j, k;
drivers/md/raid0.c
51
for (k = 0; k < conf->strip_zone[j].nb_dev; k++)
drivers/md/raid0.c
52
len += scnprintf(line+len, 200-len, "%s%pg", k?"/":"",
drivers/md/raid0.c
53
conf->devlist[j * raid_disks + k]->bdev);
drivers/md/raid1.c
1479
int i, disks, k;
drivers/md/raid1.c
1679
for (k = 0; k < i; k++) {
drivers/md/raid1.c
1680
if (r1_bio->bios[k]) {
drivers/md/raid1.c
1681
rdev_dec_pending(conf->mirrors[k].rdev, mddev);
drivers/md/raid1.c
1682
r1_bio->bios[k] = NULL;
drivers/md/raid10.c
1348
int i, k;
drivers/md/raid10.c
1511
for (k = 0; k < i; k++) {
drivers/md/raid10.c
1512
int d = r10_bio->devs[k].devnum;
drivers/md/raid10.c
1516
if (r10_bio->devs[k].bio) {
drivers/md/raid10.c
1518
r10_bio->devs[k].bio = NULL;
drivers/md/raid10.c
1520
if (r10_bio->devs[k].repl_bio) {
drivers/md/raid10.c
1522
r10_bio->devs[k].repl_bio = NULL;
drivers/md/raid10.c
3356
int k;
drivers/md/raid10.c
3395
for (k=0; k<conf->copies; k++)
drivers/md/raid10.c
3396
if (r10_bio->devs[k].devnum == i)
drivers/md/raid10.c
3398
BUG_ON(k == conf->copies);
drivers/md/raid10.c
3399
to_addr = r10_bio->devs[k].addr;
drivers/md/raid10.c
3445
int k;
drivers/md/raid10.c
3446
for (k = 0; k < conf->copies; k++)
drivers/md/raid10.c
3447
if (r10_bio->devs[k].devnum == i)
drivers/md/raid10.c
3453
r10_bio->devs[k].addr,
drivers/md/raid10.c
3458
r10_bio->devs[k].addr,
drivers/md/raid10.c
3461
mdname(mddev), r10_bio->devs[k].addr, max_sync);
drivers/md/raid5.c
7258
int i, j, k;
drivers/md/raid5.c
7292
for (k = 0; k < NR_STRIPE_HASH_LOCKS; k++)
drivers/md/raid5.c
7293
INIT_LIST_HEAD(worker->temp_inactive_list + k);
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1000
tpg->colors[k][1] = s;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1001
tpg->colors[k][2] = v;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1046
tpg->colors[k][0] = y;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1047
tpg->colors[k][1] = cb;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1048
tpg->colors[k][2] = cr;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1053
tpg->colors[k][0] = r >> 4;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1116
tpg->colors[k][0] = r;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1117
tpg->colors[k][1] = g;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1118
tpg->colors[k][2] = b;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1126
int k;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1128
for (k = 0; k < TPG_COLOR_MAX; k++)
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1129
precalculate_color(tpg, k);
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
883
static void precalculate_color(struct tpg_data *tpg, int k)
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
885
int col = k;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
892
if (k == TPG_COLOR_TEXTBG) {
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
898
} else if (k == TPG_COLOR_TEXTFG) {
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
906
} else if (k == TPG_COLOR_RANDOM) {
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
908
} else if (k >= TPG_COLOR_RAMP) {
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
909
r = g = b = k - TPG_COLOR_RAMP;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
999
tpg->colors[k][0] = h;
drivers/media/dvb-frontends/dib3000mc.c
859
int k;
drivers/media/dvb-frontends/dib3000mc.c
870
for (k = no_of_demods-1; k >= 0; k--) {
drivers/media/dvb-frontends/dib3000mc.c
871
dmcst->cfg = &cfg[k];
drivers/media/dvb-frontends/dib3000mc.c
874
new_addr = DIB3000MC_I2C_ADDRESS[k];
drivers/media/dvb-frontends/dib3000mc.c
879
dprintk("-E- DiB3000P/MC #%d: not identified\n", k);
drivers/media/dvb-frontends/dib3000mc.c
892
for (k = 0; k < no_of_demods; k++) {
drivers/media/dvb-frontends/dib3000mc.c
893
dmcst->cfg = &cfg[k];
drivers/media/dvb-frontends/dib3000mc.c
894
dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k];
drivers/media/dvb-frontends/dib7000m.c
1357
int k = 0;
drivers/media/dvb-frontends/dib7000m.c
1360
for (k = no_of_demods-1; k >= 0; k--) {
drivers/media/dvb-frontends/dib7000m.c
1361
st.cfg = cfg[k];
drivers/media/dvb-frontends/dib7000m.c
1364
new_addr = (0x40 + k) << 1;
drivers/media/dvb-frontends/dib7000m.c
1369
dprintk("DiB7000M #%d: not identified\n", k);
drivers/media/dvb-frontends/dib7000m.c
1382
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
drivers/media/dvb-frontends/dib7000m.c
1385
for (k = 0; k < no_of_demods; k++) {
drivers/media/dvb-frontends/dib7000m.c
1386
st.cfg = cfg[k];
drivers/media/dvb-frontends/dib7000m.c
1387
st.i2c_addr = (0x40 + k) << 1;
drivers/media/dvb-frontends/dib7000p.c
1208
int k;
drivers/media/dvb-frontends/dib7000p.c
1222
for (k = 0; k < 8; k++) {
drivers/media/dvb-frontends/dib7000p.c
1223
pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
drivers/media/dvb-frontends/dib7000p.c
1226
coef_re[k] = 256;
drivers/media/dvb-frontends/dib7000p.c
1227
coef_im[k] = 0;
drivers/media/dvb-frontends/dib7000p.c
1229
coef_re[k] = sine[256 - (pha & 0xff)];
drivers/media/dvb-frontends/dib7000p.c
1230
coef_im[k] = sine[pha & 0xff];
drivers/media/dvb-frontends/dib7000p.c
1232
coef_re[k] = 0;
drivers/media/dvb-frontends/dib7000p.c
1233
coef_im[k] = 256;
drivers/media/dvb-frontends/dib7000p.c
1235
coef_re[k] = -sine[pha & 0xff];
drivers/media/dvb-frontends/dib7000p.c
1236
coef_im[k] = sine[256 - (pha & 0xff)];
drivers/media/dvb-frontends/dib7000p.c
1238
coef_re[k] = -256;
drivers/media/dvb-frontends/dib7000p.c
1239
coef_im[k] = 0;
drivers/media/dvb-frontends/dib7000p.c
1241
coef_re[k] = -sine[256 - (pha & 0xff)];
drivers/media/dvb-frontends/dib7000p.c
1242
coef_im[k] = -sine[pha & 0xff];
drivers/media/dvb-frontends/dib7000p.c
1244
coef_re[k] = 0;
drivers/media/dvb-frontends/dib7000p.c
1245
coef_im[k] = -256;
drivers/media/dvb-frontends/dib7000p.c
1247
coef_re[k] = sine[pha & 0xff];
drivers/media/dvb-frontends/dib7000p.c
1248
coef_im[k] = -sine[256 - (pha & 0xff)];
drivers/media/dvb-frontends/dib7000p.c
1251
coef_re[k] *= notch[k];
drivers/media/dvb-frontends/dib7000p.c
1252
coef_re[k] += (1 << 14);
drivers/media/dvb-frontends/dib7000p.c
1253
if (coef_re[k] >= (1 << 24))
drivers/media/dvb-frontends/dib7000p.c
1254
coef_re[k] = (1 << 24) - 1;
drivers/media/dvb-frontends/dib7000p.c
1255
coef_re[k] /= (1 << 15);
drivers/media/dvb-frontends/dib7000p.c
1257
coef_im[k] *= notch[k];
drivers/media/dvb-frontends/dib7000p.c
1258
coef_im[k] += (1 << 14);
drivers/media/dvb-frontends/dib7000p.c
1259
if (coef_im[k] >= (1 << 24))
drivers/media/dvb-frontends/dib7000p.c
1260
coef_im[k] = (1 << 24) - 1;
drivers/media/dvb-frontends/dib7000p.c
1261
coef_im[k] /= (1 << 15);
drivers/media/dvb-frontends/dib7000p.c
1263
dprintk("PALF COEF: %d re: %d im: %d\n", k, coef_re[k], coef_im[k]);
drivers/media/dvb-frontends/dib7000p.c
1265
dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
drivers/media/dvb-frontends/dib7000p.c
1266
dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
drivers/media/dvb-frontends/dib7000p.c
1267
dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
drivers/media/dvb-frontends/dib7000p.c
2081
int k = 0;
drivers/media/dvb-frontends/dib7000p.c
2091
for (k = no_of_demods - 1; k >= 0; k--) {
drivers/media/dvb-frontends/dib7000p.c
2092
dpst->cfg = cfg[k];
drivers/media/dvb-frontends/dib7000p.c
2095
if (cfg[k].default_i2c_addr != 0)
drivers/media/dvb-frontends/dib7000p.c
2096
new_addr = cfg[k].default_i2c_addr + (k << 1);
drivers/media/dvb-frontends/dib7000p.c
2098
new_addr = (0x40 + k) << 1;
drivers/media/dvb-frontends/dib7000p.c
2105
dprintk("DiB7000P #%d: not identified\n", k);
drivers/media/dvb-frontends/dib7000p.c
2117
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
drivers/media/dvb-frontends/dib7000p.c
2120
for (k = 0; k < no_of_demods; k++) {
drivers/media/dvb-frontends/dib7000p.c
2121
dpst->cfg = cfg[k];
drivers/media/dvb-frontends/dib7000p.c
2122
if (cfg[k].default_i2c_addr != 0)
drivers/media/dvb-frontends/dib7000p.c
2123
dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
drivers/media/dvb-frontends/dib7000p.c
2125
dpst->i2c_addr = (0x40 + k) << 1;
drivers/media/dvb-frontends/dib8000.c
4295
int k = 0, ret = 0;
drivers/media/dvb-frontends/dib8000.c
4318
for (k = no_of_demods - 1; k >= 0; k--) {
drivers/media/dvb-frontends/dib8000.c
4320
new_addr = first_addr + (k << 1);
drivers/media/dvb-frontends/dib8000.c
4331
dprintk("#%d: not identified\n", k);
drivers/media/dvb-frontends/dib8000.c
4345
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
drivers/media/dvb-frontends/dib8000.c
4348
for (k = 0; k < no_of_demods; k++) {
drivers/media/dvb-frontends/dib8000.c
4349
new_addr = first_addr | (k << 1);
drivers/media/dvb-frontends/dib9000.c
2377
int k = 0, ret = 0;
drivers/media/dvb-frontends/dib9000.c
2396
for (k = no_of_demods - 1; k >= 0; k--) {
drivers/media/dvb-frontends/dib9000.c
2398
new_addr = first_addr + (k << 1);
drivers/media/dvb-frontends/dib9000.c
2415
dprintk("DiB9000 #%d: not identified\n", k);
drivers/media/dvb-frontends/dib9000.c
2424
dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
drivers/media/dvb-frontends/dib9000.c
2427
for (k = 0; k < no_of_demods; k++) {
drivers/media/dvb-frontends/dib9000.c
2428
new_addr = first_addr | (k << 1);
drivers/media/dvb-frontends/drx39xyj/drxj.c
1147
u32 k = 0;
drivers/media/dvb-frontends/drx39xyj/drxj.c
1156
for (k = scale; k > 0; k--) {
drivers/media/dvb-frontends/drx39xyj/drxj.c
1162
for (k = scale; k < 31; k++) {
drivers/media/dvb-frontends/drx39xyj/drxj.c
1173
y = k * ((((u32) 1) << scale) * 200);
drivers/media/dvb-frontends/stv0367.c
469
int i, j, k, freq;
drivers/media/dvb-frontends/stv0367.c
476
k = 1; /* equivalent to Xtal 25M on 362*/
drivers/media/dvb-frontends/stv0367.c
478
k = 0; /* equivalent to Xtal 27M on 362*/
drivers/media/dvb-frontends/stv0367.c
480
k = 2; /* equivalent to Xtal 30M on 362*/
drivers/media/dvb-frontends/stv0367.c
490
MSB(CellsCoeffs[k][i-1][j-1]));
drivers/media/dvb-frontends/stv0367.c
493
LSB(CellsCoeffs[k][i-1][j-1]));
drivers/media/firewire/firedtv-avc.c
628
int ret, pos, k;
drivers/media/firewire/firedtv-avc.c
648
for (k = 0; k < pidc; k++) {
drivers/media/firewire/firedtv-avc.c
651
c->operand[pos++] = (pid[k] >> 8) & 0x1f;
drivers/media/firewire/firedtv-avc.c
652
c->operand[pos++] = pid[k] & 0xff;
drivers/media/firewire/firedtv-avc.c
836
int pos, j, k, ret;
drivers/media/firewire/firedtv-avc.c
855
for (k = 0; k < diseqcmd[j].msg_len; k++)
drivers/media/firewire/firedtv-avc.c
856
c->operand[pos++] = diseqcmd[j].msg[k];
drivers/media/i2c/cx25840/cx25840-ir.c
496
unsigned int i, j, k;
drivers/media/i2c/cx25840/cx25840-ir.c
579
k = kfifo_in_locked(&ir_state->rx_kfifo,
drivers/media/i2c/cx25840/cx25840-ir.c
582
if (k != j)
drivers/media/pci/cx23885/cx23888-ir.c
512
unsigned int i, j, k;
drivers/media/pci/cx23885/cx23888-ir.c
579
k = kfifo_in_locked(&state->rx_kfifo,
drivers/media/pci/cx23885/cx23888-ir.c
582
if (k != j)
drivers/media/pci/dm1105/dm1105.c
478
int addr, rc, i, j, k, len, byte, data;
drivers/media/pci/dm1105/dm1105.c
512
k = 1;
drivers/media/pci/dm1105/dm1105.c
517
data = msgs[i].buf[k + byte];
drivers/media/pci/dm1105/dm1105.c
531
k += 48;
drivers/media/pci/tw68/tw68-video.c
776
int i, j, k;
drivers/media/pci/tw68/tw68-video.c
800
for (k = 0; k < 4; k++) {
drivers/media/platform/chips-media/coda/coda-common.c
324
int k;
drivers/media/platform/chips-media/coda/coda-common.c
331
for (k = 0; k < num_codecs; k++) {
drivers/media/platform/chips-media/coda/coda-common.c
332
if (codecs[k].src_fourcc == src_fourcc &&
drivers/media/platform/chips-media/coda/coda-common.c
333
codecs[k].dst_fourcc == dst_fourcc)
drivers/media/platform/chips-media/coda/coda-common.c
337
if (k == num_codecs)
drivers/media/platform/chips-media/coda/coda-common.c
340
return &codecs[k];
drivers/media/platform/chips-media/coda/coda-common.c
350
int k;
drivers/media/platform/chips-media/coda/coda-common.c
356
for (k = 0, w = 0, h = 0; k < num_codecs; k++) {
drivers/media/platform/chips-media/coda/coda-common.c
357
w = max(w, codecs[k].max_w);
drivers/media/platform/chips-media/coda/coda-common.c
358
h = max(h, codecs[k].max_h);
drivers/media/platform/chips-media/coda/coda-jpeg.c
585
int i, j, k, lastk, si, code, maxsymbol;
drivers/media/platform/chips-media/coda/coda-jpeg.c
606
k = 0;
drivers/media/platform/chips-media/coda/coda-jpeg.c
609
if (k + j > maxsymbol)
drivers/media/platform/chips-media/coda/coda-jpeg.c
612
huff->size[k++] = i;
drivers/media/platform/chips-media/coda/coda-jpeg.c
614
lastk = k;
drivers/media/platform/chips-media/coda/coda-jpeg.c
617
k = 0;
drivers/media/platform/chips-media/coda/coda-jpeg.c
620
while (k < lastk) {
drivers/media/platform/chips-media/coda/coda-jpeg.c
621
while (huff->size[k] == si) {
drivers/media/platform/chips-media/coda/coda-jpeg.c
622
huff->code[k++] = code;
drivers/media/platform/chips-media/coda/coda-jpeg.c
632
for (k = 0; k < lastk; k++) {
drivers/media/platform/chips-media/coda/coda-jpeg.c
633
i = huffval[k];
drivers/media/platform/chips-media/coda/coda-jpeg.c
636
ehufco[i] = huff->code[k];
drivers/media/platform/chips-media/coda/coda-jpeg.c
637
ehufsi[i] = huff->size[k];
drivers/media/platform/m2m-deinterlace.c
106
unsigned int k;
drivers/media/platform/m2m-deinterlace.c
108
for (k = 0; k < NUM_FORMATS; k++) {
drivers/media/platform/m2m-deinterlace.c
109
fmt = &formats[k];
drivers/media/platform/m2m-deinterlace.c
115
if (k == NUM_FORMATS)
drivers/media/platform/m2m-deinterlace.c
118
return &formats[k];
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
246
unsigned int k;
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
249
for (k = 0; k < num_formats; k++) {
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
250
fmt = &mtk_jpeg_formats[k];
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c
25
unsigned int k;
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c
27
for (k = 0; k < *dec_pdata->num_formats; k++) {
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c
28
fmt = &dec_pdata->vdec_formats[k];
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
216
unsigned int k;
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
219
for (k = 0; k < num_supported_formats; k++) {
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
220
fmt = &mtk_video_formats[k];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1193
void vdec_vp9_slice_map_counts_eob_coef(unsigned int i, unsigned int j, unsigned int k,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1207
counts_helper->coeff[i][j][k][l][m] =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1208
(u32 (*)[3]) & counts->coef_probs[i][j][k].band_0[m];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1209
counts_helper->eob[i][j][k][l][m][0] =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1210
&counts->eob_branch[i][j][k].band_0[m];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1211
counts_helper->eob[i][j][k][l][m][1] =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1212
&counts->coef_probs[i][j][k].band_0[m][3];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1217
counts_helper->coeff[i][j][k][l][m] =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1218
(u32 (*)[3]) & counts->coef_probs[i][j][k].band_1_5[l - 1][m];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1219
counts_helper->eob[i][j][k][l][m][0] =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1220
&counts->eob_branch[i][j][k].band_1_5[l - 1][m];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1221
counts_helper->eob[i][j][k][l][m][1] =
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1222
&counts->coef_probs[i][j][k].band_1_5[l - 1][m][3];
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1231
int i, j, k;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1305
for (k = 0; k < 2; k++)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1306
vdec_vp9_slice_map_counts_eob_coef(i, j, k, counts, counts_helper);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1309
static void vdec_vp9_slice_map_to_coef(unsigned int i, unsigned int j, unsigned int k,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1317
memcpy(frame_ctx_helper->coef[i][j][k][l][m],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1318
frame_ctx->coef_probs[i][j][k][l].probs[m],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1319
sizeof(frame_ctx_helper->coef[i][j][k][l][0]));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1324
static void vdec_vp9_slice_map_from_coef(unsigned int i, unsigned int j, unsigned int k,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1332
memcpy(frame_ctx->coef_probs[i][j][k][l].probs[m],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1333
frame_ctx_helper->coef[i][j][k][l][m],
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1334
sizeof(frame_ctx_helper->coef[i][j][k][l][0]));
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1346
u32 i, j, k;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1350
for (k = 0; k < ARRAY_SIZE(frame_ctx_helper->coef[0][0]); k++)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1351
vdec_vp9_slice_map_to_coef(i, j, k, pre_frame_ctx,
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1442
u32 i, j, k;
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1458
for (k = 0; k < ARRAY_SIZE(frame_ctx_helper->coef[0][0]); k++)
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
1459
vdec_vp9_slice_map_from_coef(i, j, k, frame_ctx,
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
141
unsigned int k;
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
143
for (k = 0; k < pdata->num_capture_formats; k++) {
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
144
fmt = &pdata->capture_formats[k];
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
149
for (k = 0; k < pdata->num_output_formats; k++) {
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
150
fmt = &pdata->output_formats[k];
drivers/media/platform/nuvoton/npcm-video.c
181
unsigned int k;
drivers/media/platform/nuvoton/npcm-video.c
183
for (k = 0; k < NUM_FORMATS; k++) {
drivers/media/platform/nuvoton/npcm-video.c
184
fmt = &npcm_fmt_list[k];
drivers/media/platform/nuvoton/npcm-video.c
189
if (k == NUM_FORMATS)
drivers/media/platform/nuvoton/npcm-video.c
192
return &npcm_fmt_list[k];
drivers/media/platform/nuvoton/npcm-video.c
699
unsigned int k;
drivers/media/platform/nuvoton/npcm-video.c
701
for (k = 0; k < NUM_FORMATS; k++) {
drivers/media/platform/nuvoton/npcm-video.c
702
fmt = &npcm_fmt_list[k];
drivers/media/platform/nvidia/tegra-vde/h264.c
204
unsigned int i, k;
drivers/media/platform/nvidia/tegra-vde/h264.c
239
for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) {
drivers/media/platform/nvidia/tegra-vde/h264.c
240
frame = &dpb_frames[k + 1];
drivers/media/platform/nvidia/tegra-vde/h264.c
244
value = (k + 1) << 26;
drivers/media/platform/nvidia/tegra-vde/h264.c
252
for (k = 0; i < ref_frames_nb; i++, k++) {
drivers/media/platform/nvidia/tegra-vde/h264.c
253
frame = &dpb_frames[k + 1];
drivers/media/platform/nvidia/tegra-vde/h264.c
257
value = (k + 1) << 26;
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
681
unsigned int k;
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
683
for (k = 0; k < MXC_JPEG_NUM_FORMATS; k++) {
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
684
const struct mxc_jpeg_fmt *fmt = &mxc_formats[k];
drivers/media/platform/nxp/imx-pxp.c
189
unsigned int k;
drivers/media/platform/nxp/imx-pxp.c
191
for (k = 0; k < NUM_FORMATS; k++) {
drivers/media/platform/nxp/imx-pxp.c
192
fmt = &formats[k];
drivers/media/platform/nxp/imx-pxp.c
197
if (k == NUM_FORMATS)
drivers/media/platform/nxp/imx-pxp.c
200
return &formats[k];
drivers/media/platform/nxp/mx2_emmaprp.c
182
unsigned int k;
drivers/media/platform/nxp/mx2_emmaprp.c
184
for (k = 0; k < NUM_FORMATS; k++) {
drivers/media/platform/nxp/mx2_emmaprp.c
185
fmt = &formats[k];
drivers/media/platform/nxp/mx2_emmaprp.c
190
if (k == NUM_FORMATS)
drivers/media/platform/nxp/mx2_emmaprp.c
193
return &formats[k];
drivers/media/platform/qcom/camss/camss-video.c
361
int i, j, k;
drivers/media/platform/qcom/camss/camss-video.c
382
k = -1;
drivers/media/platform/qcom/camss/camss-video.c
396
k++;
drivers/media/platform/qcom/camss/camss-video.c
398
if (k == f->index)
drivers/media/platform/qcom/camss/camss-video.c
402
if (k == -1 || k < f->index)
drivers/media/platform/qcom/camss/camss.c
4572
int i, j, k;
drivers/media/platform/qcom/camss/camss.c
4611
for (k = 0; k < camss->res->vfe_num; k++)
drivers/media/platform/qcom/camss/camss.c
4612
for (j = 0; j < camss->vfe[k].res->line_num; j++) {
drivers/media/platform/qcom/camss/camss.c
4614
struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
drivers/media/platform/qcom/camss/camss.c
4630
for (k = 0; k < camss->res->vfe_num; k++)
drivers/media/platform/qcom/camss/camss.c
4631
for (j = 0; j < camss->vfe[k].res->line_num; j++) {
drivers/media/platform/qcom/camss/camss.c
4633
struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
drivers/media/platform/qcom/venus/vdec.c
151
unsigned int i, k = 0;
drivers/media/platform/qcom/venus/vdec.c
172
if (k == index && valid)
drivers/media/platform/qcom/venus/vdec.c
175
k++;
drivers/media/platform/qcom/venus/venc.c
106
if (k == index && valid)
drivers/media/platform/qcom/venus/venc.c
109
k++;
drivers/media/platform/qcom/venus/venc.c
94
unsigned int i, k = 0;
drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
505
unsigned int i, j, k = 0;
drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
510
RKISP1_CIF_ISP_CT_COEFF_0 + 4 * k++,
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
172
int k, m, n;
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
175
for (k = 0; k < 6; k++) {
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
178
p = coef[k][m][n];
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
197
unsigned int i, j, k;
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
219
for (k = 0; k < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob[0][0]);
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
220
k++) {
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
221
u8 val = v4l2_vp9_kf_y_mode_prob[i][j][k];
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
247
unsigned int i, j, k;
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
274
for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++)
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
275
write_coeff_plane(probs->coef[i][j][k],
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
276
rkprobs->coef[k][i][j]);
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
902
int i, j, k, l, m;
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
943
vp9_ctx->inter_cnts.coeff[i][j][k][l][m] = \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
944
&inter_cnts->ref_cnt[k][i][j][l][m].coeff; \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
945
vp9_ctx->inter_cnts.eob[i][j][k][l][m][0] = \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
946
&inter_cnts->ref_cnt[k][i][j][l][m].eob[0]; \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
947
vp9_ctx->inter_cnts.eob[i][j][k][l][m][1] = \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
948
&inter_cnts->ref_cnt[k][i][j][l][m].eob[1]; \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
950
vp9_ctx->intra_cnts.coeff[i][j][k][l][m] = \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
951
&intra_cnts->ref_cnt[k][i][j][l][m].coeff; \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
952
vp9_ctx->intra_cnts.eob[i][j][k][l][m][0] = \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
953
&intra_cnts->ref_cnt[k][i][j][l][m].eob[0]; \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
954
vp9_ctx->intra_cnts.eob[i][j][k][l][m][1] = \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
955
&intra_cnts->ref_cnt[k][i][j][l][m].eob[1]; \
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
961
for (k = 0; k < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0]); ++k)
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
1365
unsigned int k, fmt_flag;
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
1376
for (k = 0; k < ARRAY_SIZE(sjpeg_formats); k++) {
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
1377
struct s5p_jpeg_fmt *fmt = &sjpeg_formats[k];
drivers/media/platform/ti/am437x/am437x-vpfe.c
115
unsigned int k;
drivers/media/platform/ti/am437x/am437x-vpfe.c
117
for (k = 0; k < vpfe->num_active_fmt; k++) {
drivers/media/platform/ti/am437x/am437x-vpfe.c
118
fmt = vpfe->active_fmt[k];
drivers/media/platform/ti/am437x/am437x-vpfe.c
130
unsigned int k;
drivers/media/platform/ti/am437x/am437x-vpfe.c
132
for (k = 0; k < vpfe->num_active_fmt; k++) {
drivers/media/platform/ti/am437x/am437x-vpfe.c
133
fmt = vpfe->active_fmt[k];
drivers/media/platform/ti/am437x/am437x-vpfe.c
2150
int i, j, k;
drivers/media/platform/ti/am437x/am437x-vpfe.c
2186
for (k = 0; k < ARRAY_SIZE(formats); k++) {
drivers/media/platform/ti/am437x/am437x-vpfe.c
2187
fmt = &formats[k];
drivers/media/platform/ti/cal/cal-video.c
61
unsigned int k;
drivers/media/platform/ti/cal/cal-video.c
63
for (k = 0; k < ctx->num_active_fmt; k++) {
drivers/media/platform/ti/cal/cal-video.c
64
fmtinfo = ctx->active_fmt[k];
drivers/media/platform/ti/cal/cal-video.c
76
unsigned int k;
drivers/media/platform/ti/cal/cal-video.c
78
for (k = 0; k < ctx->num_active_fmt; k++) {
drivers/media/platform/ti/cal/cal-video.c
79
fmtinfo = ctx->active_fmt[k];
drivers/media/platform/ti/cal/cal-video.c
846
unsigned int i, j, k;
drivers/media/platform/ti/cal/cal-video.c
878
for (k = 0; k < cal_num_formats; k++) {
drivers/media/platform/ti/cal/cal-video.c
879
fmtinfo = &cal_formats[k];
drivers/media/platform/ti/davinci/vpif_capture.c
1400
int j, err, k;
drivers/media/platform/ti/davinci/vpif_capture.c
1463
for (k = 0; k < j; k++) {
drivers/media/platform/ti/davinci/vpif_capture.c
1465
ch = vpif_obj.dev[k];
drivers/media/platform/ti/davinci/vpif_display.c
1123
int j, err, k;
drivers/media/platform/ti/davinci/vpif_display.c
1128
for (k = 0; k < VPIF_NUMOBJECTS; k++) {
drivers/media/platform/ti/davinci/vpif_display.c
1129
common = &ch->common[k];
drivers/media/platform/ti/davinci/vpif_display.c
1206
for (k = 0; k < j; k++) {
drivers/media/platform/ti/davinci/vpif_display.c
1207
ch = vpif_obj.dev[k];
drivers/media/platform/ti/omap/omap_vout.c
1442
int ret = 0, k;
drivers/media/platform/ti/omap/omap_vout.c
1453
for (k = 0; k < pdev->num_resources; k++) {
drivers/media/platform/ti/omap/omap_vout.c
1461
vout->vid = k;
drivers/media/platform/ti/omap/omap_vout.c
1462
vid_dev->vouts[k] = vout;
drivers/media/platform/ti/omap/omap_vout.c
1466
vout->vid_info.overlays[0] = vid_dev->overlays[k + 2];
drivers/media/platform/ti/omap/omap_vout.c
1469
vout->vid_info.overlays[0] = vid_dev->overlays[k + 1];
drivers/media/platform/ti/omap/omap_vout.c
1471
vout->vid_info.id = k + 1;
drivers/media/platform/ti/omap/omap_vout.c
1496
if (omap_vout_setup_video_bufs(pdev, k) != 0) {
drivers/media/platform/ti/omap/omap_vout.c
1516
if (k == (pdev->num_resources - 1))
drivers/media/platform/ti/omap/omap_vout.c
1573
int k;
drivers/media/platform/ti/omap/omap_vout.c
1579
for (k = 0; k < pdev->num_resources; k++)
drivers/media/platform/ti/omap/omap_vout.c
1580
omap_vout_cleanup_device(vid_dev->vouts[k]);
drivers/media/platform/ti/omap/omap_vout.c
1582
for (k = 0; k < vid_dev->num_displays; k++) {
drivers/media/platform/ti/omap/omap_vout.c
1583
if (vid_dev->displays[k]->state != OMAP_DSS_DISPLAY_DISABLED)
drivers/media/platform/ti/omap/omap_vout.c
1584
vid_dev->displays[k]->driver->disable(vid_dev->displays[k]);
drivers/media/platform/ti/omap/omap_vout.c
1586
omap_dss_put_device(vid_dev->displays[k]);
drivers/media/platform/ti/vpe/vip.c
3163
unsigned int k, i, j;
drivers/media/platform/ti/vpe/vip.c
3168
for (k = 0, i = 0; (ret != -EINVAL); k++) {
drivers/media/platform/ti/vpe/vip.c
3170
mbus_code.index = k;
drivers/media/platform/ti/vpe/vip.c
3179
subdev->name, mbus_code.code, k);
drivers/media/platform/ti/vpe/vpe.c
352
unsigned int k;
drivers/media/platform/ti/vpe/vpe.c
354
for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
drivers/media/platform/ti/vpe/vpe.c
355
fmt = &vpe_formats[k];
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
549
unsigned int i, j, k;
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
570
for (k = 0; k < 4; k++)
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
571
*p++ = sc->scaling_list_4x4[i][4 * k + j];
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
575
for (k = 0; k < 8; k++)
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
576
*p++ = sc->scaling_list_8x8[i][8 * k + j];
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
580
for (k = 0; k < 8; k++)
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
581
*p++ = sc->scaling_list_16x16[i][8 * k + j];
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
585
for (k = 0; k < 8; k++)
drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
586
*p++ = sc->scaling_list_32x32[i][8 * k + j];
drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
624
memcpy(adaptive->coef[i][j][k][l][m], \
drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
625
probs->coef[i][j][k][l][m], \
drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
626
sizeof(probs->coef[i][j][k][l][m])); \
drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
628
adaptive->coef[i][j][k][l][m][3] = 0; \
drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
641
int i, j, k, l, m;
drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
733
for (k = 0; k < ARRAY_SIZE(adaptive->coef[0][0]); ++k)
drivers/media/platform/verisilicon/hantro_vp8.c
115
for (k = 0; k < 3; ++k) {
drivers/media/platform/verisilicon/hantro_vp8.c
116
dst[0] = entropy->coeff_probs[i][j][k][0];
drivers/media/platform/verisilicon/hantro_vp8.c
117
dst[1] = entropy->coeff_probs[i][j][k][1];
drivers/media/platform/verisilicon/hantro_vp8.c
118
dst[2] = entropy->coeff_probs[i][j][k][2];
drivers/media/platform/verisilicon/hantro_vp8.c
119
dst[3] = entropy->coeff_probs[i][j][k][3];
drivers/media/platform/verisilicon/hantro_vp8.c
130
for (k = 0; k < 3; ++k) {
drivers/media/platform/verisilicon/hantro_vp8.c
131
dst[0] = entropy->coeff_probs[i][j][k][4];
drivers/media/platform/verisilicon/hantro_vp8.c
132
dst[1] = entropy->coeff_probs[i][j][k][5];
drivers/media/platform/verisilicon/hantro_vp8.c
133
dst[2] = entropy->coeff_probs[i][j][k][6];
drivers/media/platform/verisilicon/hantro_vp8.c
134
dst[3] = entropy->coeff_probs[i][j][k][7];
drivers/media/platform/verisilicon/hantro_vp8.c
135
dst[4] = entropy->coeff_probs[i][j][k][8];
drivers/media/platform/verisilicon/hantro_vp8.c
136
dst[5] = entropy->coeff_probs[i][j][k][9];
drivers/media/platform/verisilicon/hantro_vp8.c
137
dst[6] = entropy->coeff_probs[i][j][k][10];
drivers/media/platform/verisilicon/hantro_vp8.c
53
u32 i, j, k;
drivers/media/platform/verisilicon/hantro_vp9.c
100
return &cnts->count_coeffs32x32[j][k][l][m][3];
drivers/media/platform/verisilicon/hantro_vp9.c
108
vp9_ctx->cnts.coeff[i][j][k][l][m] = \
drivers/media/platform/verisilicon/hantro_vp9.c
109
get_coeffs_arr(cnts, i, j, k, l, m); \
drivers/media/platform/verisilicon/hantro_vp9.c
110
vp9_ctx->cnts.eob[i][j][k][l][m][0] = \
drivers/media/platform/verisilicon/hantro_vp9.c
111
&cnts->count_eobs[i][j][k][l][m]; \
drivers/media/platform/verisilicon/hantro_vp9.c
112
vp9_ctx->cnts.eob[i][j][k][l][m][1] = \
drivers/media/platform/verisilicon/hantro_vp9.c
113
get_eobs1(cnts, i, j, k, l, m); \
drivers/media/platform/verisilicon/hantro_vp9.c
121
int i, j, k, l, m;
drivers/media/platform/verisilicon/hantro_vp9.c
153
for (k = 0; k < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0]); ++k)
drivers/media/platform/verisilicon/hantro_vp9.c
71
static void *get_coeffs_arr(struct symbol_counts *cnts, int i, int j, int k, int l, int m)
drivers/media/platform/verisilicon/hantro_vp9.c
74
return &cnts->count_coeffs[j][k][l][m];
drivers/media/platform/verisilicon/hantro_vp9.c
77
return &cnts->count_coeffs8x8[j][k][l][m];
drivers/media/platform/verisilicon/hantro_vp9.c
80
return &cnts->count_coeffs16x16[j][k][l][m];
drivers/media/platform/verisilicon/hantro_vp9.c
83
return &cnts->count_coeffs32x32[j][k][l][m];
drivers/media/platform/verisilicon/hantro_vp9.c
88
static void *get_eobs1(struct symbol_counts *cnts, int i, int j, int k, int l, int m)
drivers/media/platform/verisilicon/hantro_vp9.c
91
return &cnts->count_coeffs[j][k][l][m][3];
drivers/media/platform/verisilicon/hantro_vp9.c
94
return &cnts->count_coeffs8x8[j][k][l][m][3];
drivers/media/platform/verisilicon/hantro_vp9.c
97
return &cnts->count_coeffs16x16[j][k][l][m][3];
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
563
int k;
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
569
for (k = 0; (1 << k) < target; k++);
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
571
return k;
drivers/media/test-drivers/vicodec/codec-fwht.c
622
unsigned int k, l;
drivers/media/test-drivers/vicodec/codec-fwht.c
630
for (k = 0; k < 8; k++) {
drivers/media/test-drivers/vicodec/codec-fwht.c
664
int k, l;
drivers/media/test-drivers/vicodec/codec-fwht.c
666
for (k = 0; k < 8; k++) {
drivers/media/test-drivers/vim2m.c
159
unsigned int k;
drivers/media/test-drivers/vim2m.c
161
for (k = 0; k < NUM_FORMATS; k++) {
drivers/media/test-drivers/vim2m.c
162
fmt = &formats[k];
drivers/media/test-drivers/vim2m.c
167
if (k == NUM_FORMATS)
drivers/media/test-drivers/vim2m.c
170
return &formats[k];
drivers/media/test-drivers/vivid/vivid-core.c
1917
for (int j = 0, k = 0; j < dev->num_inputs; ++j)
drivers/media/test-drivers/vivid/vivid-core.c
1919
dev->hdmi_index_to_input_index[k++] = j;
drivers/media/test-drivers/vivid/vivid-core.c
1920
for (int j = 0, k = 0; j < dev->num_outputs; ++j)
drivers/media/test-drivers/vivid/vivid-core.c
1922
dev->output_to_iface_index[j] = k;
drivers/media/test-drivers/vivid/vivid-core.c
1923
dev->hdmi_index_to_output_index[k++] = j;
drivers/media/test-drivers/vivid/vivid-core.c
1925
for (int j = 0, k = 0; j < dev->num_inputs; ++j)
drivers/media/test-drivers/vivid/vivid-core.c
1927
dev->svid_index_to_input_index[k++] = j;
drivers/media/test-drivers/vivid/vivid-core.c
1928
for (int j = 0, k = 0; j < dev->num_outputs; ++j)
drivers/media/test-drivers/vivid/vivid-core.c
1930
dev->output_to_iface_index[j] = k++;
drivers/media/test-drivers/vivid/vivid-core.c
2263
for (u8 j = 0, k = 0; j < n_outputs && hdmi_count < MAX_MENU_ITEMS &&
drivers/media/test-drivers/vivid/vivid-core.c
2264
k < MAX_HDMI_OUTPUTS; ++j) {
drivers/media/test-drivers/vivid/vivid-core.c
2272
i & 0xff, k);
drivers/media/test-drivers/vivid/vivid-core.c
2273
k++;
drivers/media/test-drivers/vivid/vivid-core.c
2277
for (u8 j = 0, k = 0; j < n_outputs && svid_count < MAX_MENU_ITEMS; ++j) {
drivers/media/test-drivers/vivid/vivid-core.c
2285
i & 0xff, k);
drivers/media/test-drivers/vivid/vivid-core.c
2286
k++;
drivers/media/test-drivers/vivid/vivid-vid-common.c
760
unsigned k;
drivers/media/test-drivers/vivid/vivid-vid-common.c
762
for (k = 0; k < ARRAY_SIZE(vivid_formats); k++) {
drivers/media/test-drivers/vivid/vivid-vid-common.c
763
fmt = &vivid_formats[k];
drivers/media/tuners/e4000.c
101
unsigned int div_n, k, k_cw, div_out;
drivers/media/tuners/e4000.c
143
div_n = div_u64_rem(f_vco, F_REF, &k);
drivers/media/tuners/e4000.c
144
k_cw = div_u64((u64) k * 0x10000, F_REF);
drivers/media/tuners/e4000.c
148
dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k,
drivers/media/tuners/fc2580.c
32
unsigned int uitmp, div_ref, div_ref_val, div_n, k, k_cw, div_out;
drivers/media/tuners/fc2580.c
91
div_n = div_u64_rem(f_vco, uitmp, &k);
drivers/media/tuners/fc2580.c
92
k_cw = div_u64((u64) k * 0x100000, uitmp);
drivers/media/tuners/fc2580.c
97
div_n, k, div_out, k_cw);
drivers/media/tuners/msi001.c
211
div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k);
drivers/media/tuners/msi001.c
213
k_frac = div_u64((u64) k * k_thresh, (DIV_PRE_N * F_REF));
drivers/media/tuners/msi001.c
87
unsigned int uitmp, div_n, k, k_thresh, k_frac, div_lo, f_if1;
drivers/media/tuners/mxl5005s.c
3505
u16 i, k ;
drivers/media/tuners/mxl5005s.c
3512
for (k = 0; k < state->Init_Ctrl[i].size; k++)
drivers/media/tuners/mxl5005s.c
3513
ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
drivers/media/tuners/mxl5005s.c
3524
for (k = 0; k < state->CH_Ctrl[i].size; k++)
drivers/media/tuners/mxl5005s.c
3525
ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
drivers/media/tuners/mxl5005s.c
3538
for (k = 0; k < state->MXL_Ctrl[i].size; k++)
drivers/media/tuners/mxl5005s.c
3539
ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
drivers/media/usb/au0828/au0828-video.c
203
int j, k;
drivers/media/usb/au0828/au0828-video.c
259
k = 0;
drivers/media/usb/au0828/au0828-video.c
261
urb->iso_frame_desc[j].offset = k;
drivers/media/usb/au0828/au0828-video.c
264
k += dev->isoc_ctl.max_pkt_size;
drivers/media/usb/cx231xx/cx231xx-audio.c
273
int j, k;
drivers/media/usb/cx231xx/cx231xx-audio.c
300
for (j = k = 0; j < CX231XX_ISO_NUM_AUDIO_PACKETS;
drivers/media/usb/cx231xx/cx231xx-audio.c
301
j++, k += dev->adev.max_pkt_size) {
drivers/media/usb/cx231xx/cx231xx-audio.c
302
urb->iso_frame_desc[j].offset = k;
drivers/media/usb/cx231xx/cx231xx-core.c
1082
k = 0;
drivers/media/usb/cx231xx/cx231xx-core.c
1084
urb->iso_frame_desc[j].offset = k;
drivers/media/usb/cx231xx/cx231xx-core.c
1087
k += dev->video_mode.isoc_ctl.max_pkt_size;
drivers/media/usb/cx231xx/cx231xx-core.c
990
int j, k;
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
430
int i, k, ret = 0;
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
540
for (k = 0; k < 26; k++)
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
541
buf[k] = USB_END_I2C_CMD;
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
665
for (k = 0;
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
666
k < 8-(i+1);
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
667
k++) {
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
669
msg->buf[(index*8)+(k+i+1)] =
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
670
readbuff[k];
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
672
msg->buf[(index*8)+(k+i)],
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
673
(index*8)+(k+i));
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
675
msg->buf[(index*8)+(k+i+1)],
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
676
readbuff[k]);
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
698
for (k = 0; k < 26; k++)
drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c
699
buf[k] = USB_END_I2C_CMD;
drivers/media/usb/em28xx/em28xx-audio.c
763
int j, k;
drivers/media/usb/em28xx/em28xx-audio.c
793
for (j = k = 0; j < npackets; j++, k += ep_size) {
drivers/media/usb/em28xx/em28xx-audio.c
794
urb->iso_frame_desc[j].offset = k;
drivers/media/usb/em28xx/em28xx-core.c
609
u8 k = 0;
drivers/media/usb/em28xx/em28xx-core.c
611
while (dev->board.leds[k].role >= 0 &&
drivers/media/usb/em28xx/em28xx-core.c
612
dev->board.leds[k].role < EM28XX_NUM_LED_ROLES) {
drivers/media/usb/em28xx/em28xx-core.c
613
if (dev->board.leds[k].role == role)
drivers/media/usb/em28xx/em28xx-core.c
614
return &dev->board.leds[k];
drivers/media/usb/em28xx/em28xx-core.c
615
k++;
drivers/media/usb/em28xx/em28xx-core.c
885
int j, k;
drivers/media/usb/em28xx/em28xx-core.c
976
k = 0;
drivers/media/usb/em28xx/em28xx-core.c
978
urb->iso_frame_desc[j].offset = k;
drivers/media/usb/em28xx/em28xx-core.c
981
k += usb_bufs->max_pkt_size;
drivers/media/usb/gspca/cpia1.c
564
u8 i, u8 j, u8 k, u8 l)
drivers/media/usb/gspca/cpia1.c
582
gspca_dev->usb_buf[6] = k;
drivers/media/usb/gspca/pac7302.c
428
const unsigned int k = 1000; /* precision factor */
drivers/media/usb/gspca/pac7302.c
432
norm = k * (rgb_ctrl_val - PAC7302_RGB_BALANCE_MIN)
drivers/media/usb/gspca/pac7302.c
435
return 64 * norm * norm / (k*k) + 32 * norm / k + 32;
drivers/media/usb/msi2500/msi2500.c
673
unsigned int f_vco, f_sr, div_n, k, k_cw, div_out;
drivers/media/usb/msi2500/msi2500.c
781
div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k);
drivers/media/usb/msi2500/msi2500.c
782
k_cw = div_u64((u64) k * 0x200000, DIV_PRE_N * F_REF);
drivers/media/usb/msi2500/msi2500.c
791
f_sr, f_vco, div_n, k, div_out, reg3, reg4);
drivers/media/usb/pwc/pwc-dec23.c
104
for (k = 0; k < 16; k++) {
drivers/media/usb/pwc/pwc-dec23.c
105
if (k == 0)
drivers/media/usb/pwc/pwc-dec23.c
107
else if (k >= 1 && k < 3)
drivers/media/usb/pwc/pwc-dec23.c
109
else if (k >= 3 && k < 6)
drivers/media/usb/pwc/pwc-dec23.c
111
else if (k >= 6 && k < 10)
drivers/media/usb/pwc/pwc-dec23.c
113
else if (k >= 10 && k < 13)
drivers/media/usb/pwc/pwc-dec23.c
115
else if (k >= 13 && k < 15)
drivers/media/usb/pwc/pwc-dec23.c
119
if (k == 0)
drivers/media/usb/pwc/pwc-dec23.c
126
p0[k + 0x00] = (1 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
127
p0[k + 0x10] = (2 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
128
p0[k + 0x20] = (3 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
129
p0[k + 0x30] = (4 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
130
p0[k + 0x40] = (-1 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
131
p0[k + 0x50] = (-2 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
132
p0[k + 0x60] = (-3 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
133
p0[k + 0x70] = (-4 * pw) + 0x80;
drivers/media/usb/pwc/pwc-dec23.c
92
int compression_mode, j, k, bit, pw;
drivers/media/usb/stk1160/stk1160-video.c
434
int i, j, k, sb_size, max_packets, num_bufs;
drivers/media/usb/stk1160/stk1160-video.c
488
k = 0;
drivers/media/usb/stk1160/stk1160-video.c
490
urb->iso_frame_desc[j].offset = k;
drivers/media/usb/stk1160/stk1160-video.c
493
k += dev->isoc_ctl.max_pkt_size;
drivers/media/v4l2-core/v4l2-h264.c
263
u8 lt, i = 0, j = 0, k = 0;
drivers/media/v4l2-core/v4l2-h264.c
271
reflist[k++] = tmplist[i++];
drivers/media/v4l2-core/v4l2-h264.c
278
reflist[k++] = tmplist[j++];
drivers/media/v4l2-core/v4l2-vp9.c
1227
int i, j, k;
drivers/media/v4l2-core/v4l2-vp9.c
1231
for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++)
drivers/media/v4l2-core/v4l2-vp9.c
1232
update_coeff(deltas->coef[i][j][k], probs->coef[i][j][k]);
drivers/media/v4l2-core/v4l2-vp9.c
1672
static void _adapt_coeff(unsigned int i, unsigned int j, unsigned int k,
drivers/media/v4l2-core/v4l2-vp9.c
1681
u8 *p = probs->coef[i][j][k][l][m];
drivers/media/v4l2-core/v4l2-vp9.c
1683
*counts->eob[i][j][k][l][m][1],
drivers/media/v4l2-core/v4l2-vp9.c
1684
*counts->eob[i][j][k][l][m][0] - *counts->eob[i][j][k][l][m][1],
drivers/media/v4l2-core/v4l2-vp9.c
1687
adapt_probs_variant_a_coef(p, *counts->coeff[i][j][k][l][m], uf);
drivers/media/v4l2-core/v4l2-vp9.c
1697
unsigned int i, j, k;
drivers/media/v4l2-core/v4l2-vp9.c
1701
for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++)
drivers/media/v4l2-core/v4l2-vp9.c
1702
_adapt_coeff(i, j, k, probs, counts, uf);
drivers/mfd/sm501.c
394
unsigned int m, n, k;
drivers/mfd/sm501.c
453
unsigned int m, n, k;
drivers/mfd/sm501.c
462
for (k = 0; k <= 1; k++) {
drivers/mfd/sm501.c
463
mclk = (24000000UL * m / n) >> k;
drivers/mfd/sm501.c
469
clock->k = k;
drivers/mfd/sm501.c
542
pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
drivers/misc/altera-stapl/altera-jtag.c
403
u32 i, j, k;
drivers/misc/altera-stapl/altera-jtag.c
414
k = preamble_count + target_count;
drivers/misc/altera-stapl/altera-jtag.c
415
for (; i < k; ++i, ++j) {
drivers/misc/altera-stapl/altera-jtag.c
424
k = preamble_count + target_count + postamble_count;
drivers/misc/altera-stapl/altera-jtag.c
425
for (; i < k; ++i, ++j) {
drivers/misc/altera-stapl/altera-jtag.c
570
u32 k;
drivers/misc/altera-stapl/altera-jtag.c
573
k = start_index + target_count;
drivers/misc/altera-stapl/altera-jtag.c
574
for (i = start_index; i < k; ++i, ++j) {
drivers/misc/altera-stapl/altera.c
142
u32 size, line, lines, linebits, value, j, k;
drivers/misc/altera-stapl/altera.c
1622
s32 k = long_idx;
drivers/misc/altera-stapl/altera.c
1632
if (charptr_tmp[k >> 3] &
drivers/misc/altera-stapl/altera.c
1633
(1 << (k & 7)))
drivers/misc/altera-stapl/altera.c
1640
++k;
drivers/misc/altera-stapl/altera.c
165
for (k = 0; k < linebits; ++k) {
drivers/misc/altera-stapl/altera.c
166
i = k + offset;
drivers/misc/altera-stapl/altera.c
175
if ((k & 3) > 0)
drivers/misc/mei/hdcp/mei_hdcp.c
562
cmd_size = struct_size(verify_mprime_in, streams, data->k);
drivers/misc/mei/hdcp/mei_hdcp.c
583
array_size(data->k, sizeof(*data->streams)));
drivers/misc/mei/hdcp/mei_hdcp.c
585
verify_mprime_in->k = cpu_to_be16(data->k);
drivers/misc/sgi-gru/grufault.c
145
unsigned long i, k;
drivers/misc/sgi-gru/grufault.c
151
k = tfm->fault_bits[i];
drivers/misc/sgi-gru/grufault.c
152
if (k)
drivers/misc/sgi-gru/grufault.c
153
k = xchg(&tfm->fault_bits[i], 0UL);
drivers/misc/sgi-gru/grufault.c
154
imap->fault_bits[i] = k;
drivers/misc/sgi-gru/grufault.c
155
k = tfm->done_bits[i];
drivers/misc/sgi-gru/grufault.c
156
if (k)
drivers/misc/sgi-gru/grufault.c
157
k = xchg(&tfm->done_bits[i], 0UL);
drivers/misc/sgi-gru/grufault.c
158
dmap->fault_bits[i] = k;
drivers/misc/sgi-gru/grukservices.c
1050
int i, k, istatus, bytes;
drivers/misc/sgi-gru/grukservices.c
1069
k = numcb;
drivers/misc/sgi-gru/grukservices.c
1089
k--;
drivers/misc/sgi-gru/grukservices.c
1092
} while (k);
drivers/misc/sgi-gru/grutables.h
528
#define for_each_cbr_in_allocation_map(i, map, k) \
drivers/misc/sgi-gru/grutables.h
529
for_each_set_bit((k), (map), GRU_CBR_AU) \
drivers/misc/sgi-gru/grutables.h
530
for ((i) = (k)*GRU_CBR_AU_SIZE; \
drivers/misc/sgi-gru/grutables.h
531
(i) < ((k) + 1) * GRU_CBR_AU_SIZE; (i)++)
drivers/misc/xilinx_sdfec.c
459
static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize,
drivers/misc/xilinx_sdfec.c
465
(n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) {
drivers/misc/xilinx_sdfec.c
471
if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX ||
drivers/misc/xilinx_sdfec.c
472
(k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) {
drivers/misc/xilinx_sdfec.c
476
k = k << XSDFEC_REG0_K_LSB;
drivers/misc/xilinx_sdfec.c
477
wdata = k | n;
drivers/misc/xilinx_sdfec.c
681
ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize,
drivers/mmc/host/wbsd.c
1273
int i, j, k;
drivers/mmc/host/wbsd.c
1298
for (k = 0; k < ARRAY_SIZE(valid_ids); k++) {
drivers/mmc/host/wbsd.c
1299
if (id == valid_ids[k]) {
drivers/mtd/nand/raw/atmel/pmecc.c
197
const unsigned int k = BIT(deg(poly));
drivers/mtd/nand/raw/atmel/pmecc.c
201
if (k != (1u << mm))
drivers/mtd/nand/raw/atmel/pmecc.c
211
if (x & k)
drivers/mtd/nand/raw/atmel/pmecc.c
493
int i, j, k;
drivers/mtd/nand/raw/atmel/pmecc.c
586
for (k = 0; k < num; k++)
drivers/mtd/nand/raw/atmel/pmecc.c
587
smu[(i + 1) * num + k] = 0;
drivers/mtd/nand/raw/atmel/pmecc.c
590
for (k = 0; k <= lmu[ro] >> 1; k++) {
drivers/mtd/nand/raw/atmel/pmecc.c
593
if (!(smu[ro * num + k] && dmu[i]))
drivers/mtd/nand/raw/atmel/pmecc.c
598
c = index_of[smu[ro * num + k]];
drivers/mtd/nand/raw/atmel/pmecc.c
601
smu[(i + 1) * num + (k + diff)] = a;
drivers/mtd/nand/raw/atmel/pmecc.c
604
for (k = 0; k <= lmu[i] >> 1; k++)
drivers/mtd/nand/raw/atmel/pmecc.c
605
smu[(i + 1) * num + k] ^= smu[i * num + k];
drivers/mtd/nand/raw/atmel/pmecc.c
616
for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
drivers/mtd/nand/raw/atmel/pmecc.c
618
if (k == 0) {
drivers/mtd/nand/raw/atmel/pmecc.c
620
} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
drivers/mtd/nand/raw/atmel/pmecc.c
623
a = index_of[smu[(i + 1) * num + k]];
drivers/mtd/nand/raw/atmel/pmecc.c
624
b = si[2 * (i - 1) + 3 - k];
drivers/mtd/nand/raw/brcmnand/brcmnand.c
1580
int j, k = 0;
drivers/mtd/nand/raw/brcmnand/brcmnand.c
1602
plast[k++] = oob[j++];
drivers/mtd/nand/raw/fsmc_nand.c
467
int k, written_bits = 0;
drivers/mtd/nand/raw/fsmc_nand.c
469
for (k = 0; k < size; k++) {
drivers/mtd/nand/raw/fsmc_nand.c
470
written_bits += hweight8(~buff[k]);
drivers/mtd/nand/raw/nand_onfi.c
118
int i, j, k;
drivers/mtd/nand/raw/nand_onfi.c
126
for (k = 0; k < nsrcbufs; k++) {
drivers/mtd/nand/raw/nand_onfi.c
127
const u8 *srcbuf = srcbufs[k];
drivers/mtd/ssfdc.c
104
int ret, k, cis_sector;
drivers/mtd/ssfdc.c
120
for (k = 0, offset = 0; k < 4; k++, offset += mtd->erasesize) {
drivers/mtd/ssfdc.c
184
int k;
drivers/mtd/ssfdc.c
188
for (k = 0; k < size; k++) {
drivers/mtd/ssfdc.c
189
parity += (number >> k);
drivers/mtd/ssfdc.c
76
int k;
drivers/mtd/ssfdc.c
79
k = 0;
drivers/mtd/ssfdc.c
80
while (chs_table[k].size > 0 && size > chs_table[k].size)
drivers/mtd/ssfdc.c
81
k++;
drivers/mtd/ssfdc.c
83
if (chs_table[k].size > 0) {
drivers/mtd/ssfdc.c
85
*cyl = chs_table[k].cyl;
drivers/mtd/ssfdc.c
87
*head = chs_table[k].head;
drivers/mtd/ssfdc.c
89
*sec = chs_table[k].sec;
drivers/mtd/tests/oobtest.c
210
int k;
drivers/mtd/tests/oobtest.c
239
k = use_offset + use_len;
drivers/mtd/tests/oobtest.c
240
bitflips += memffshow(addr, k, readbuf + k,
drivers/mtd/tests/oobtest.c
241
mtd->oobavail - k);
drivers/mtd/tests/speedtest.c
163
uint64_t k, us;
drivers/mtd/tests/speedtest.c
168
k = (uint64_t)goodebcnt * (mtd->erasesize / 1024) * 1000000;
drivers/mtd/tests/speedtest.c
169
do_div(k, us);
drivers/mtd/tests/speedtest.c
170
return k;
drivers/mtd/tests/speedtest.c
175
int err, i, blocks, j, k;
drivers/mtd/tests/speedtest.c
370
for (k = 1; k < 7; k++) {
drivers/mtd/tests/speedtest.c
371
blocks = 1 << k;
drivers/mtd/tests/subpagetest.c
100
addr += subpgsize * k;
drivers/mtd/tests/subpagetest.c
181
int err = 0, k;
drivers/mtd/tests/subpagetest.c
184
for (k = 1; k < 33; ++k) {
drivers/mtd/tests/subpagetest.c
185
if (addr + (subpgsize * k) > (loff_t)(ebnum + 1) * mtd->erasesize)
drivers/mtd/tests/subpagetest.c
187
prandom_bytes_state(&rnd_state, writebuf, subpgsize * k);
drivers/mtd/tests/subpagetest.c
188
clear_data(readbuf, subpgsize * k);
drivers/mtd/tests/subpagetest.c
189
err = mtd_read(mtd, addr, subpgsize * k, &read, readbuf);
drivers/mtd/tests/subpagetest.c
190
if (unlikely(err || read != subpgsize * k)) {
drivers/mtd/tests/subpagetest.c
191
if (mtd_is_bitflip(err) && read == subpgsize * k) {
drivers/mtd/tests/subpagetest.c
201
if (unlikely(memcmp(readbuf, writebuf, subpgsize * k))) {
drivers/mtd/tests/subpagetest.c
206
addr += subpgsize * k;
drivers/mtd/tests/subpagetest.c
81
int err = 0, k;
drivers/mtd/tests/subpagetest.c
84
for (k = 1; k < 33; ++k) {
drivers/mtd/tests/subpagetest.c
85
if (addr + (subpgsize * k) > (loff_t)(ebnum + 1) * mtd->erasesize)
drivers/mtd/tests/subpagetest.c
87
prandom_bytes_state(&rnd_state, writebuf, subpgsize * k);
drivers/mtd/tests/subpagetest.c
88
err = mtd_write(mtd, addr, subpgsize * k, &written, writebuf);
drivers/mtd/tests/subpagetest.c
89
if (unlikely(err || written != subpgsize * k)) {
drivers/mtd/tests/subpagetest.c
92
if (written != subpgsize * k) {
drivers/mtd/tests/subpagetest.c
94
subpgsize * k);
drivers/mtd/ubi/build.c
1268
int err, i, k;
drivers/mtd/ubi/build.c
1320
for (k = 0; k < i; k++)
drivers/mtd/ubi/build.c
1321
if (ubi_devices[k]) {
drivers/mtd/ubi/build.c
1323
ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1);
drivers/net/dsa/sja1105/sja1105_ethtool.c
565
int rc, k = 0;
drivers/net/dsa/sja1105/sja1105_ethtool.c
577
rc = sja1105_port_counter_read(priv, port, i, &data[k++]);
drivers/net/dsa/sja1105/sja1105_tas.c
175
int i, k = 0;
drivers/net/dsa/sja1105/sja1105_tas.c
282
schedule_start_idx = k;
drivers/net/dsa/sja1105/sja1105_tas.c
283
schedule_end_idx = k + offload->num_entries - 1;
drivers/net/dsa/sja1105/sja1105_tas.c
310
for (i = 0; i < offload->num_entries; i++, k++) {
drivers/net/dsa/sja1105/sja1105_tas.c
313
schedule[k].delta = ns_to_sja1105_delta(delta_ns);
drivers/net/dsa/sja1105/sja1105_tas.c
314
schedule[k].destports = BIT(port);
drivers/net/dsa/sja1105/sja1105_tas.c
315
schedule[k].resmedia_en = true;
drivers/net/dsa/sja1105/sja1105_tas.c
316
schedule[k].resmedia = SJA1105_GATE_MASK &
drivers/net/dsa/sja1105/sja1105_tas.c
328
schedule_start_idx = k;
drivers/net/dsa/sja1105/sja1105_tas.c
329
schedule_end_idx = k + gating_cfg->num_entries - 1;
drivers/net/dsa/sja1105/sja1105_tas.c
344
schedule[k].delta = ns_to_sja1105_delta(e->interval);
drivers/net/dsa/sja1105/sja1105_tas.c
345
schedule[k].destports = e->rule->vl.destports;
drivers/net/dsa/sja1105/sja1105_tas.c
346
schedule[k].setvalid = true;
drivers/net/dsa/sja1105/sja1105_tas.c
347
schedule[k].txen = true;
drivers/net/dsa/sja1105/sja1105_tas.c
348
schedule[k].vlindex = e->rule->vl.sharindx;
drivers/net/dsa/sja1105/sja1105_tas.c
349
schedule[k].winstindex = e->rule->vl.sharindx;
drivers/net/dsa/sja1105/sja1105_tas.c
351
schedule[k].winst = true;
drivers/net/dsa/sja1105/sja1105_tas.c
353
schedule[k].winend = true;
drivers/net/dsa/sja1105/sja1105_tas.c
354
k++;
drivers/net/dsa/sja1105/sja1105_vl.c
323
int i, j, k;
drivers/net/dsa/sja1105/sja1105_vl.c
394
k = 0;
drivers/net/dsa/sja1105/sja1105_vl.c
403
vl_lookup[k].format = SJA1105_VL_FORMAT_PSFP;
drivers/net/dsa/sja1105/sja1105_vl.c
404
vl_lookup[k].port = port;
drivers/net/dsa/sja1105/sja1105_vl.c
405
vl_lookup[k].macaddr = rule->key.vl.dmac;
drivers/net/dsa/sja1105/sja1105_vl.c
407
vl_lookup[k].vlanid = rule->key.vl.vid;
drivers/net/dsa/sja1105/sja1105_vl.c
408
vl_lookup[k].vlanprior = rule->key.vl.pcp;
drivers/net/dsa/sja1105/sja1105_vl.c
414
vl_lookup[k].vlanid = vid;
drivers/net/dsa/sja1105/sja1105_vl.c
415
vl_lookup[k].vlanprior = 0;
drivers/net/dsa/sja1105/sja1105_vl.c
422
vl_lookup[k].destports = rule->vl.destports;
drivers/net/dsa/sja1105/sja1105_vl.c
424
vl_lookup[k].iscritical = true;
drivers/net/dsa/sja1105/sja1105_vl.c
425
vl_lookup[k].flow_cookie = rule->cookie;
drivers/net/dsa/sja1105/sja1105_vl.c
426
k++;
drivers/net/ethernet/3com/3c59x.c
2768
int k;
drivers/net/ethernet/3com/3c59x.c
2770
for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
drivers/net/ethernet/3com/3c59x.c
2772
le32_to_cpu(vp->tx_ring[i].frag[k].addr),
drivers/net/ethernet/3com/3c59x.c
2773
le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
drivers/net/ethernet/agere/et131x.c
1951
u32 k = (i * FBR_CHUNKS) + j;
drivers/net/ethernet/agere/et131x.c
1956
fbr->virt[k] = (u8 *)fbr->mem_virtaddrs[i] +
drivers/net/ethernet/agere/et131x.c
1962
fbr->bus_high[k] = upper_32_bits(fbr_physaddr);
drivers/net/ethernet/agere/et131x.c
1963
fbr->bus_low[k] = lower_32_bits(fbr_physaddr);
drivers/net/ethernet/amazon/ena/ena_netdev.c
1657
int rc = 0, i, k, irq_idx;
drivers/net/ethernet/amazon/ena/ena_netdev.c
1698
for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
drivers/net/ethernet/amazon/ena/ena_netdev.c
1699
irq = &adapter->irq_tbl[k];
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
124
for (k = 0; k < 1000; k++) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
133
if (k == 1000) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
154
for (k = 0; k < 1000; k++) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
161
if (k == 1000) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
174
int k;
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
203
for (k = 0; k < 1000; k++) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
223
for (k = 0; k < 1000; k++) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
230
if (k == 1000) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
245
int k;
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
247
for (k = 0; k < 1000; ++k) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
256
if (k == 1000) {
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
98
int k = 0;
drivers/net/ethernet/broadcom/b44.c
1494
int k, j, len = offset;
drivers/net/ethernet/broadcom/b44.c
1510
for (k = 0; k< ethaddr_bytes; k++) {
drivers/net/ethernet/broadcom/b44.c
1512
(j * ETH_ALEN) + k] = macaddr[k];
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
1390
int k;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
1409
for (k = 0; k < 8; k++) {
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
1411
bn->toeplitz_prefix |= key[k];
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
266
int cp_count = 0, k;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
298
for (k = 0; k < cp_count; k++) {
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
299
cpr = &nqr->cp_ring_arr[k];
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
305
cpr->cp_idx = k;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
306
if (!k && rx) {
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
310
int n, tc = k - rx;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
440
int k, last;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
457
for (k = 0; k < last; k++, j++) {
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
459
skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
932
int k;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
936
k = j + BNGE_RING_TO_TC_OFF(bd, i);
drivers/net/ethernet/broadcom/bnge/bnge_netdev.c
938
bnapi2 = bn->bnapi[k];
drivers/net/ethernet/broadcom/bnx2.c
5427
int k, last;
drivers/net/ethernet/broadcom/bnx2.c
5443
for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) {
drivers/net/ethernet/broadcom/bnx2.c
5447
skb_frag_size(&skb_shinfo(skb)->frags[k]),
drivers/net/ethernet/broadcom/bnx2.c
8252
u8 num, k, skip0;
drivers/net/ethernet/broadcom/bnx2.c
8260
for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
drivers/net/ethernet/broadcom/bnx2.c
8261
if (num >= k || !skip0 || k == 1) {
drivers/net/ethernet/broadcom/bnx2.c
8262
bp->fw_version[j++] = (num / k) + '0';
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3233
int i, j, k = 0;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3241
buf[k + j] = 0;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3248
buf[k + j] = (u64) *offset;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3252
buf[k + j] = HILO_U64(*offset, *(offset + 1));
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3254
k += BNX2X_NUM_Q_STATS;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3264
buf[k + j] = 0;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3271
buf[k + j] = (u64) *offset;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
3276
buf[k + j] = HILO_U64(*offset, *(offset + 1));
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
853
u32 i, j, k, n;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
873
for (k = 0; k < read_num; k++) {
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
874
if (IS_REG_IN_PRESET(read_addr[k].presets,
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
876
size = read_addr[k].size;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
878
addr = read_addr[k].addr + n*4;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4202
int cp_count = 0, k;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4239
for (k = 0; k < cp_count; k++) {
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4240
cpr2 = &cpr->cp_ring_arr[k];
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4246
cpr2->cp_idx = k;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4247
if (!k && rx) {
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4251
int n, tc = k - rx;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4694
int k;
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4713
for (k = 0; k < 8; k++) {
drivers/net/ethernet/broadcom/bnxt/bnxt.c
4715
bp->toeplitz_prefix |= key[k];
drivers/net/ethernet/broadcom/bnxt/bnxt.c
5560
int k = j + BNXT_RING_TO_TC_OFF(bp, i);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
5562
bnapi2 = bp->bnapi[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
614
int k;
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
617
for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
618
buf[j] = sw_stats[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
621
k = NUM_RING_RX_HW_STATS;
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
622
for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
623
j++, k++)
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
624
buf[j] = sw_stats[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
629
k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
630
for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
631
tpa_stats; j++, k++)
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
632
buf[j] = sw_stats[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
637
for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
638
buf[j] = sw[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
642
for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
643
buf[j] = sw[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
460
u32 nr_pages, size, i, j, k = 0;
drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
482
for (j = 0; j < BNXT_HWRM_REQS_PER_PAGE && k < num_vfs; j++) {
drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
483
struct bnxt_vf_info *vf = &bp->pf.vf[k];
drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
490
k++;
drivers/net/ethernet/broadcom/cnic.c
914
int i, k, arr_size;
drivers/net/ethernet/broadcom/cnic.c
924
k = 0;
drivers/net/ethernet/broadcom/cnic.c
936
for (j = lo; j < hi; j += cp->cids_per_blk, k++)
drivers/net/ethernet/broadcom/cnic.c
937
cp->ctx_arr[k].cid = j;
drivers/net/ethernet/broadcom/cnic.c
940
cp->ctx_blks = k;
drivers/net/ethernet/broadcom/tg3.c
12978
int i, j, k, err = 0, size;
drivers/net/ethernet/broadcom/tg3.c
13068
for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
drivers/net/ethernet/broadcom/tg3.c
13074
parity[k++] = buf8[i] & msk;
drivers/net/ethernet/broadcom/tg3.c
13081
parity[k++] = buf8[i] & msk;
drivers/net/ethernet/broadcom/tg3.c
13085
parity[k++] = buf8[i] & msk;
drivers/net/ethernet/brocade/bna/bna_enet.c
203
int k;
drivers/net/ethernet/brocade/bna/bna_enet.c
206
for (k = 0; k < count; k++) {
drivers/net/ethernet/brocade/bna/bna_enet.c
207
stats_dst[k] = be64_to_cpu(*stats_src);
drivers/net/ethernet/brocade/bna/bna_enet.c
218
int k;
drivers/net/ethernet/brocade/bna/bna_enet.c
221
for (k = 0; k < count; k++) {
drivers/net/ethernet/brocade/bna/bna_enet.c
222
stats_dst[k] = be64_to_cpu(*stats_src);
drivers/net/ethernet/chelsio/cxgb3/sge.c
1011
unsigned int i, j = 0, k = 0, nfrags;
drivers/net/ethernet/chelsio/cxgb3/sge.c
1015
sgp->addr[j++] = cpu_to_be64(addr[k++]);
drivers/net/ethernet/chelsio/cxgb3/sge.c
1023
sgp->addr[j] = cpu_to_be64(addr[k++]);
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
2401
u8 i, k;
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
2477
for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
2478
dst_off[k] = cpu_to_be64(src_off[k]);
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
3239
int i, k, rc;
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
3251
for (k = 0; k < mbox_cmds; k++) {
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
3252
entry_idx = log->cursor + k;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4025
unsigned int i, j, k;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4111
for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4149
cpu_to_be64(adapter->hma.phy_addr[j + k]);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3436
int k, int c)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3445
if (k > c) {
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3457
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3458
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3519
uint32_t d, c, k;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3523
k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3534
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
3535
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
drivers/net/ethernet/cisco/enic/enic_clsf.c
157
struct flow_keys *k)
drivers/net/ethernet/cisco/enic/enic_clsf.c
162
if (tpos->keys.addrs.v4addrs.src == k->addrs.v4addrs.src &&
drivers/net/ethernet/cisco/enic/enic_clsf.c
163
tpos->keys.addrs.v4addrs.dst == k->addrs.v4addrs.dst &&
drivers/net/ethernet/cisco/enic/enic_clsf.c
164
tpos->keys.ports.ports == k->ports.ports &&
drivers/net/ethernet/cisco/enic/enic_clsf.c
165
tpos->keys.basic.ip_proto == k->basic.ip_proto &&
drivers/net/ethernet/cisco/enic/enic_clsf.c
166
tpos->keys.basic.n_proto == k->basic.n_proto)
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
1903
int k, i;
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
1905
for_each_possible_cpu(k) {
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
1906
sgt_cache = per_cpu_ptr(priv->sgt_cache, k);
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
266
int j, k, err, num_cnt, i = 0;
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
286
for (k = 0; k < num_cnt; k++)
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
287
*(data + i++) = dpni_stats.raw.counter[k];
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
291
for_each_online_cpu(k) {
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
292
extras = per_cpu_ptr(priv->percpu_extras, k);
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
299
for (k = 0; k < priv->num_channels; k++) {
drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c
300
ch_stats = &priv->channel[k]->stats;
drivers/net/ethernet/freescale/enetc/enetc.c
1682
int i, k, frm_len = tmp_tx_swbd->len;
drivers/net/ethernet/freescale/enetc/enetc.c
1694
for (k = 0; k < num_tx_swbd; k++) {
drivers/net/ethernet/freescale/enetc/enetc.c
1695
struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k];
drivers/net/ethernet/freescale/enetc/enetc.c
1787
int xdp_tx_bd_cnt, i, k;
drivers/net/ethernet/freescale/enetc/enetc.c
1800
for (k = 0; k < num_frames; k++) {
drivers/net/ethernet/freescale/enetc/enetc.c
1803
frames[k]);
drivers/net/ethernet/freescale/enetc/enetc.c
1819
if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt))
drivers/net/ethernet/freescale/fman/fman_sp.c
15
int i = 0, j = 0, k = 0;
drivers/net/ethernet/freescale/fman/fman_sp.c
41
for (k = i; k > j; k--)
drivers/net/ethernet/freescale/fman/fman_sp.c
42
ordered_array[k] =
drivers/net/ethernet/freescale/fman/fman_sp.c
43
ordered_array[k - 1];
drivers/net/ethernet/freescale/fman/fman_sp.c
48
ordered_array[k] =
drivers/net/ethernet/freescale/gianfar_ethtool.c
688
int i = 0x0, k = 0x0;
drivers/net/ethernet/freescale/gianfar_ethtool.c
768
for (k = j+1; k < MAX_FILER_IDX; k++) {
drivers/net/ethernet/freescale/gianfar_ethtool.c
769
priv->ftp_rqfpr[priv->cur_filer_idx] = local_rqfpr[k];
drivers/net/ethernet/freescale/gianfar_ethtool.c
770
priv->ftp_rqfcr[priv->cur_filer_idx] = local_rqfcr[k];
drivers/net/ethernet/freescale/gianfar_ethtool.c
772
local_rqfcr[k], local_rqfpr[k]);
drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
334
int k;
drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
341
for (k = 0; k < handle->q_num; k++) {
drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
343
hns_rcb_int_clr_hw(handle->qs[k],
drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
346
hns_rcbv2_int_clr_hw(handle->qs[k],
drivers/net/ethernet/hisilicon/hns/hns_enet.c
294
int k;
drivers/net/ethernet/hisilicon/hns/hns_enet.c
301
for (k = 0; k < frag_buf_num; k++)
drivers/net/ethernet/hisilicon/hns/hns_enet.c
302
fill_v2_desc_hw(ring, priv, k == 0 ? size : 0,
drivers/net/ethernet/hisilicon/hns/hns_enet.c
303
(k == frag_buf_num - 1) ?
drivers/net/ethernet/hisilicon/hns/hns_enet.c
305
dma + BD_MAX_SEND_SIZE * k,
drivers/net/ethernet/hisilicon/hns/hns_enet.c
306
frag_end && (k == frag_buf_num - 1) ? 1 : 0,
drivers/net/ethernet/hisilicon/hns/hns_enet.c
308
(type == DESC_TYPE_SKB && !k) ?
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
1705
unsigned int frag_buf_num, k;
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
1724
for (k = 0; k < frag_buf_num; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
1726
desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
1727
desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
861
#define calc_x(x, k, v) ((x) = ~(k) & (v))
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
862
#define calc_y(y, k, v) ((y) = (k) & (v))
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c
184
int i, k, n;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c
214
for (k = 0; k < n; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c
238
int i, k, n;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c
268
for (k = 0; k < n; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1001
u16 i, k;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1005
for (k = 0; k < hdev->num_alloc_vport; k++)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1008
vport[k].qs_offset + i,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1009
k, true);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1189
u32 i, k;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1200
for (k = 0; k < hdev->num_alloc_vport; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1201
struct hnae3_knic_private_info *kinfo = &vport[k].nic.kinfo;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1206
dwrr = i < kinfo->tc_info.num_tc ? vport[k].dwrr : 0;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1208
hdev, vport[k].qs_offset + i,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1534
int k, ret;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1536
for (k = 0; k < hdev->num_alloc_vport; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1537
struct hclge_vport *vport = &hdev->vport[k];
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1639
u32 i, k;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1644
for (k = 0; k < hdev->num_alloc_vport; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
1645
kinfo = &vport[k].nic.kinfo;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
793
int k;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
807
for (k = 0; k < hdev->tm_info.num_tc; k++)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
808
hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
809
for (; k < HNAE3_MAX_TC; k++)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
810
hdev->tm_info.pg_info[i].tc_dwrr[k] = DEFAULT_BW_WEIGHT;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
976
u16 i, k;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
980
for (k = 0; k < hdev->num_alloc_vport; k++) {
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
981
struct hnae3_knic_private_info *kinfo = &vport[k].nic.kinfo;
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
988
vport[k].qs_offset + i,
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
226
int i, k, tmp;
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
237
for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++)
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
238
tmp += port->port_res[k].p_stats.poll_receive_errors;
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
241
for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++)
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
242
tmp += port->port_res[k].p_stats.err_tcp_cksum;
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
245
for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++)
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
246
tmp += port->port_res[k].p_stats.err_ip_cksum;
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
249
for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++)
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
250
tmp += port->port_res[k].p_stats.err_frame_crc;
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
253
for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++)
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
254
tmp += port->port_res[k].p_stats.queue_stopped;
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
257
for (k = 0; k < 16; k++)
drivers/net/ethernet/ibm/ehea/ehea_ethtool.c
258
data[i++] = atomic_read(&port->port_res[k].swqe_avail);
drivers/net/ethernet/ibm/ehea/ehea_main.c
152
int num_fw_handles, k, l;
drivers/net/ethernet/ibm/ehea/ehea_main.c
160
for (k = 0; k < EHEA_MAX_PORTS; k++) {
drivers/net/ethernet/ibm/ehea/ehea_main.c
161
struct ehea_port *port = adapter->port[k];
drivers/net/ethernet/ibm/ehea/ehea_main.c
186
for (k = 0; k < EHEA_MAX_PORTS; k++) {
drivers/net/ethernet/ibm/ehea/ehea_main.c
187
struct ehea_port *port = adapter->port[k];
drivers/net/ethernet/ibm/ehea/ehea_main.c
240
int k;
drivers/net/ethernet/ibm/ehea/ehea_main.c
246
for (k = 0; k < EHEA_MAX_PORTS; k++) {
drivers/net/ethernet/ibm/ehea/ehea_main.c
247
struct ehea_port *port = adapter->port[k];
drivers/net/ethernet/ibm/ehea/ehea_main.c
266
for (k = 0; k < EHEA_MAX_PORTS; k++) {
drivers/net/ethernet/ibm/ehea/ehea_main.c
267
struct ehea_port *port = adapter->port[k];
drivers/net/ethernet/ibm/ehea/ehea_qmr.c
44
int i, k;
drivers/net/ethernet/ibm/ehea/ehea_qmr.c
68
for (k = 0; k < pages_per_kpage && i < nr_of_pages; k++) {
drivers/net/ethernet/ibm/ehea/ehea_qmr.c
796
unsigned long k = 0;
drivers/net/ethernet/ibm/ehea/ehea_qmr.c
804
pg = sectbase + ((k++) * EHEA_PAGESIZE);
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1382
int i, j, k, l, lc, good_cnt, ret_val = 0;
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1397
k = l = 0;
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1403
txdr->buffer_info[k].dma,
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1404
txdr->buffer_info[k].length,
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1406
if (unlikely(++k == txdr->count))
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1407
k = 0;
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
1409
ew32(TDT, k);
drivers/net/ethernet/intel/e1000e/ethtool.c
1635
int i, j, k, l;
drivers/net/ethernet/intel/e1000e/ethtool.c
1653
k = 0;
drivers/net/ethernet/intel/e1000e/ethtool.c
1659
buffer_info = &tx_ring->buffer_info[k];
drivers/net/ethernet/intel/e1000e/ethtool.c
1666
k++;
drivers/net/ethernet/intel/e1000e/ethtool.c
1667
if (k == tx_ring->count)
drivers/net/ethernet/intel/e1000e/ethtool.c
1668
k = 0;
drivers/net/ethernet/intel/e1000e/ethtool.c
1670
ew32(TDT(0), k);
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2788
u8 i, j, k;
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2836
for (k = 0; k < ice_fd_pairs[index].count; k++) {
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2837
es[first_free - k].prot_id =
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2839
es[first_free - k].off =
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2840
ice_fd_pairs[index].off + (k * 2);
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2842
if (k > first_free)
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2846
mask_sel |= BIT(first_free - k);
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2878
for (k = 0; k < indexes_used; k++) {
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2879
used[si - k] = (pair_start[idx] - k) |
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2896
for (k = 0; k < 4; k++) {
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2899
idx = (j * 4) + k;
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2901
raw_swap |= used[idx] << (k * BITS_PER_BYTE);
drivers/net/ethernet/intel/ice/ice_flex_pipe.c
2903
raw_in |= ICE_INSET_DFLT << (k * BITS_PER_BYTE);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1444
int k = 0;
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1454
for (unsigned int j = 0; j < tx_grp->num_txq; j++, k++) {
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1455
vport->txqs[k] = tx_grp->txqs[j];
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1456
vport->txqs[k]->idx = k;
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1461
vport->txqs[k]->cached_tstamp_caps = caps;
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1462
vport->txqs[k]->tstamp_task = tstamp_task;
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1870
for (unsigned int k = 0; k < bufq_set->num_refillqs; k++) {
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1872
&bufq_set->refillqs[k];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1415
int i, j, k = 0;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1422
for (j = 0; j < tx_qgrp->num_txq && k < num_regs; j++, k++)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1424
idpf_get_reg_addr(adapter, reg_vals[k]);
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1432
for (j = 0; j < num_rxq && k < num_regs; j++, k++) {
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1437
reg_vals[k]);
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1446
for (j = 0; j < num_bufqs && k < num_regs; j++, k++) {
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1451
reg_vals[k]);
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1459
return k;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1879
u32 k = 0;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1890
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_TX;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1891
qs->qs[k++].txq = tx_qgrp->txqs[j];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1895
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1896
qs->qs[k++].complq = tx_qgrp->complq;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
1901
if (k != totqs)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2068
u32 k = 0;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2085
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2086
qs->qs[k++].bufq = &rx_qgrp->splitq.bufq_sets[j].bufq;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2093
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_RX;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2096
qs->qs[k++].rxq =
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2099
qs->qs[k++].rxq = rx_qgrp->singleq.rxqs[j];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2104
if (k != totqs)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2213
u32 num_txq, num_q, k = 0;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2229
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_TX;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2230
qs->qs[k++].txq = tx_qgrp->txqs[j];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2236
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2237
qs->qs[k++].complq = tx_qgrp->complq;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2240
if (k != num_txq)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2255
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_RX;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2258
qs->qs[k++].rxq =
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2261
qs->qs[k++].rxq = rx_qgrp->singleq.rxqs[j];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2268
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2269
qs->qs[k++].bufq = &rx_qgrp->splitq.bufq_sets[j].bufq;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2273
if (k != num_q)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2409
u32 k = 0;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2419
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_TX;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2420
qs->qs[k++].txq = tx_qgrp->txqs[j];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2424
if (k != rsrc->num_txq)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2437
qs->qs[k].type = VIRTCHNL2_QUEUE_TYPE_RX;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2440
qs->qs[k++].rxq =
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2443
qs->qs[k++].rxq = rx_qgrp->singleq.rxqs[j];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
2447
if (k != num_q)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3915
int i, j, k = 0;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3922
for (j = 0; j < tx_qgrp->num_txq && k < num_qids; j++, k++)
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3923
tx_qgrp->txqs[j]->q_id = qids[k];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3936
for (j = 0; j < num_rxq && k < num_qids; j++, k++) {
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3943
q->q_id = qids[k];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3948
for (i = 0; i < rsrc->num_txq_grp && k < num_qids; i++, k++) {
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3951
tx_qgrp->complq->q_id = qids[k];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3959
for (j = 0; j < num_bufqs && k < num_qids; j++, k++) {
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3963
q->q_id = qids[k];
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
3971
return k;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
4304
int i = 0, k;
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
4365
for (i = 0, k = 0; i < num_msgs; i++) {
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
4384
memcpy(ma_list->mac_addr_list, &mac_addr[k], entries_size);
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
4392
k += num_entries;
drivers/net/ethernet/intel/igb/e1000_i210.c
231
u32 i, k, eewr = 0;
drivers/net/ethernet/intel/igb/e1000_i210.c
252
for (k = 0; k < attempts; k++) {
drivers/net/ethernet/intel/igc/igc_i225.c
232
u32 i, k, eewr = 0;
drivers/net/ethernet/intel/igc/igc_i225.c
251
for (k = 0; k < attempts; k++) {
drivers/net/ethernet/marvell/prestera/prestera_router_hw.c
214
const struct prestera_rif_entry_key *k)
drivers/net/ethernet/marvell/prestera/prestera_router_hw.c
219
if (__prestera_rif_entry_key_copy(k, &lk))
drivers/net/ethernet/marvell/prestera/prestera_router_hw.c
224
if (!memcmp(k, &rif_entry->key, sizeof(*k)))
drivers/net/ethernet/marvell/prestera/prestera_router_hw.c
248
struct prestera_rif_entry_key *k,
drivers/net/ethernet/marvell/prestera/prestera_router_hw.c
259
if (__prestera_rif_entry_key_copy(k, &e->key))
drivers/net/ethernet/marvell/prestera/prestera_router_hw.h
124
const struct prestera_rif_entry_key *k);
drivers/net/ethernet/marvell/prestera/prestera_router_hw.h
129
struct prestera_rif_entry_key *k,
drivers/net/ethernet/mediatek/mtk_eth_soc.c
1582
int k = 0;
drivers/net/ethernet/mediatek/mtk_eth_soc.c
1603
k++);
drivers/net/ethernet/mediatek/mtk_eth_soc.c
1652
txd_info.size, k++);
drivers/net/ethernet/mediatek/mtk_eth_soc.c
1664
if (k & 0x1)
drivers/net/ethernet/mediatek/mtk_ppe.c
957
int i, k;
drivers/net/ethernet/mediatek/mtk_ppe.c
967
for (k = 0; k < ARRAY_SIZE(skip); k++) {
drivers/net/ethernet/mediatek/mtk_ppe.c
970
hwe = mtk_foe_get_entry(ppe, i + skip[k]);
drivers/net/ethernet/mellanox/mlx4/qp.c
559
int k;
drivers/net/ethernet/mellanox/mlx4/qp.c
620
for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]);
drivers/net/ethernet/mellanox/mlx4/qp.c
621
k++) {
drivers/net/ethernet/mellanox/mlx4/qp.c
694
err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size),
drivers/net/ethernet/mellanox/mlx4/qp.c
701
err = mlx4_bitmap_init(*bitmap + k, 1,
drivers/net/ethernet/mellanox/mlx4/qp.c
705
mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0);
drivers/net/ethernet/mellanox/mlx4/qp.c
713
err = mlx4_zone_add_one(qp_table->zones, *bitmap + k,
drivers/net/ethernet/mellanox/mlx4/qp.c
717
offset, qp_table->zones_uids + k);
drivers/net/ethernet/mellanox/mlx4/qp.c
731
for (k = 0; k < bitmap_initialized; k++)
drivers/net/ethernet/mellanox/mlx4/qp.c
732
mlx4_bitmap_cleanup(*bitmap + k);
drivers/net/ethernet/mellanox/mlx4/qp.c
772
int k;
drivers/net/ethernet/mellanox/mlx4/qp.c
790
for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++)
drivers/net/ethernet/mellanox/mlx4/qp.c
791
fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k];
drivers/net/ethernet/mellanox/mlx4/qp.c
863
for (k = 0; k < dev->caps.num_ports; k++) {
drivers/net/ethernet/mellanox/mlx4/qp.c
864
dev->caps.spec_qps[k].qp0_proxy = dev->phys_caps.base_proxy_sqpn +
drivers/net/ethernet/mellanox/mlx4/qp.c
865
8 * mlx4_master_func_num(dev) + k;
drivers/net/ethernet/mellanox/mlx4/qp.c
866
dev->caps.spec_qps[k].qp0_tunnel = dev->caps.spec_qps[k].qp0_proxy + 8 * MLX4_MFUNC_MAX;
drivers/net/ethernet/mellanox/mlx4/qp.c
867
dev->caps.spec_qps[k].qp1_proxy = dev->phys_caps.base_proxy_sqpn +
drivers/net/ethernet/mellanox/mlx4/qp.c
868
8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
drivers/net/ethernet/mellanox/mlx4/qp.c
869
dev->caps.spec_qps[k].qp1_tunnel = dev->caps.spec_qps[k].qp1_proxy + 8 * MLX4_MFUNC_MAX;
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
2369
int k;
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
2372
for (k = 0; k < dev->profile.num_cmd_caches; k++) {
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
2373
ch = &cmd->cache[k];
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
2376
ch->num_ent = cmd_cache_num_ent[k];
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
2377
ch->max_inbox_size = cmd_cache_ent_size[k];
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
491
for (int k = 0; k < rq->wqe.info.num_frags; k++, frag++)
drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
48
int err, i, j, k, idx;
drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
94
mlx5_ldev_for_each_reverse(k, i, 0, ldev) {
drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
96
idx = k * ldev->buckets + j;
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_rule.c
725
int i, k;
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_rule.c
733
for (i = num_of_builders, k = 0; i < new_hw_ste_arr_sz; i++, k++) {
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_rule.c
752
ste_info_arr[k] = mlx5dr_send_info_alloc(dmn,
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_rule.c
754
if (!ste_info_arr[k])
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_rule.c
766
ste_info_arr[k],
drivers/net/ethernet/microchip/enc28j60.c
1254
int test_len, k;
drivers/net/ethernet/microchip/enc28j60.c
1265
for (k = 0; k < test_len; k++) {
drivers/net/ethernet/microchip/enc28j60.c
1266
if (priv->tx_skb->data[k] != test_buf[k]) {
drivers/net/ethernet/microchip/enc28j60.c
1269
k, priv->tx_skb->data[k], test_buf[k]);
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
618
int k = j % 8;
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
620
if (i == 0 || k == 0)
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
623
if (v & (1 << k))
drivers/net/ethernet/netronome/nfp/abm/cls.c
24
struct tc_u32_key *k;
drivers/net/ethernet/netronome/nfp/abm/cls.c
79
k = &knode->sel->keys[0];
drivers/net/ethernet/netronome/nfp/abm/cls.c
80
if (k->offmask) {
drivers/net/ethernet/netronome/nfp/abm/cls.c
84
if (k->off) {
drivers/net/ethernet/netronome/nfp/abm/cls.c
88
if (k->val & ~k->mask) {
drivers/net/ethernet/netronome/nfp/abm/cls.c
92
if (be32_to_cpu(k->mask) >> tos_off & ~abm->dscp_mask) {
drivers/net/ethernet/netronome/nfp/abm/cls.c
96
be32_to_cpu(k->mask) >> tos_off, abm->dscp_mask);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c
771
int k;
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c
779
k = nfp_cpp_area_write(area, offset + i, &tmp, sizeof(tmp));
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c
780
if (k < 0)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c
781
return k;
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1483
int j, k;
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1492
k = i;
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1495
tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1497
if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1502
unused, j, i, k, tx_ring->next_to_use,
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
1504
i = k; /*found one to clean, usu gbec_status==2000.*/
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2149
int loop_cnt, i, k, timeout_flag = 0;
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2188
for (k = 0; k < read_cnt; k++) {
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2205
int i, k, loop_cnt;
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2223
for (k = 0; k < read_cnt; k++) {
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2283
int loop_cnt, k;
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2294
for (k = 0; k < read_cnt; k++) {
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2501
int i, k, data_size = 0;
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2507
for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) {
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2509
data_size += hdr->capture_size_array[k];
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2028
int i, k;
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2082
k = i % 4;
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2084
if ((k == 0) && (i > 0)) {
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2094
hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length);
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2095
switch (k) {
drivers/net/ethernet/qlogic/qed/qed_cxt.c
1013
for (k = 0; k < p_mngr->vf_count; k++) {
drivers/net/ethernet/qlogic/qed/qed_cxt.c
1015
u32 lines = clients[i].vf_total_lines * k;
drivers/net/ethernet/qlogic/qed/qed_cxt.c
992
u32 size, i, j, k;
drivers/net/ethernet/qlogic/qed/qed_int.c
1022
u8 i, j, k, bit_idx;
drivers/net/ethernet/qlogic/qed/qed_int.c
1061
for (k = 0; k < MAX_ATTN_GRPS; k++) {
drivers/net/ethernet/qlogic/qed/qed_int.c
1065
if (!(deasserted_bits & (1 << k)))
drivers/net/ethernet/qlogic/qed/qed_int.c
1073
k * sizeof(u32) * NUM_ATTN_REGS;
drivers/net/ethernet/qlogic/qed/qed_int.c
1373
int i, j, k;
drivers/net/ethernet/qlogic/qed/qed_int.c
1385
for (j = 0, k = 0; k < 32 && j < 32; j++) {
drivers/net/ethernet/qlogic/qed/qed_int.c
1390
sb_info->parity_mask[i] |= 1 << k;
drivers/net/ethernet/qlogic/qed/qed_int.c
1392
k += ATTENTION_LENGTH(p_aeu->flags);
drivers/net/ethernet/qlogic/qed/qed_sriov.c
4494
int k;
drivers/net/ethernet/qlogic/qed/qed_sriov.c
4500
for (k = 0; k < 100; k++) {
drivers/net/ethernet/qlogic/qed/qed_sriov.c
4507
if (k < 100)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3478
int err, k, total_regs;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3492
for (k = 2; k < 28; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3493
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3496
for (k += 6; k < 60; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3497
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3500
for (k += 6; k < 80; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3501
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3503
for (; k < total_regs; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3504
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3507
for (k = 2; k < 8; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3508
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3510
for (k += 2; k < 24; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3511
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3513
for (k += 2; k < total_regs; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3514
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3517
for (k = 2; k < 10; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3518
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3520
for (k += 2; k < total_regs; k += 2)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3521
data = qlcnic_83xx_copy_stats(cmd, data, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
1069
u8 i, j, k, map;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
1082
for (k = 0; k < QLC_DCB_MAX_TC; k++) {
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
569
int err, i, j, k, max_app, size;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
593
k = 2;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
599
each->hdr_prio_pfc_map[0] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
600
each->hdr_prio_pfc_map[1] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
601
each->prio_pg_map[0] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
602
each->prio_pg_map[1] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
603
each->pg_bw_map[0] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
604
each->pg_bw_map[1] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
605
each->pg_tsa_map[0] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
606
each->pg_tsa_map[1] = cmd.rsp.arg[k++];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
611
each->app[i] = cmd.rsp.arg[i + k];
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
617
k = 18;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c
619
k = 34;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
657
int i, k, frag_count, delta = 0;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
720
k = i % 4;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
722
if ((k == 0) && (i > 0)) {
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
731
hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
732
switch (k) {
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
1290
int i, k, ops_cnt, ops_index, dump_size = 0;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
1320
for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
1322
dump_size += qlcnic_get_cap_size(adapter, tmpl_hdr, k);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
407
int i, k, timeout = 0;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
415
k = 0;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
416
for (k = 0; k < 8; k++) {
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
417
if (!(ctr->opcode & (1 << k)))
drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c
419
switch (1 << k) {
drivers/net/ethernet/sfc/siena/siena_sriov.c
947
unsigned int pos, count, k, buftbl, abs_evq;
drivers/net/ethernet/sfc/siena/siena_sriov.c
970
for (k = 0; k < count; k++) {
drivers/net/ethernet/sfc/siena/siena_sriov.c
971
copy_req[k].from_buf = NULL;
drivers/net/ethernet/sfc/siena/siena_sriov.c
972
copy_req[k].from_rid = efx->pci_dev->devfn;
drivers/net/ethernet/sfc/siena/siena_sriov.c
973
copy_req[k].from_addr = buffer->dma_addr;
drivers/net/ethernet/sfc/siena/siena_sriov.c
974
copy_req[k].to_rid = vf->pci_rid;
drivers/net/ethernet/sfc/siena/siena_sriov.c
975
copy_req[k].to_addr = vf->evq0_addrs[pos + k];
drivers/net/ethernet/sfc/siena/siena_sriov.c
976
copy_req[k].length = EFX_PAGE_SIZE;
drivers/net/ethernet/smsc/smc91c92_cs.c
404
int k;
drivers/net/ethernet/smsc/smc91c92_cs.c
413
for (k = 0; k < 0x400; k += 0x10) {
drivers/net/ethernet/smsc/smc91c92_cs.c
414
if (k & 0x80)
drivers/net/ethernet/smsc/smc91c92_cs.c
416
p_dev->resource[0]->start = k ^ 0x300;
drivers/net/ethernet/sun/niu.c
6450
int i, j, k, err;
drivers/net/ethernet/sun/niu.c
6456
for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
drivers/net/ethernet/sun/niu.c
6464
rp->rbr[k++] = cpu_to_le32(base);
drivers/net/ethernet/sun/niu.c
6468
for (; k < MAX_RBR_RING_SIZE; k++) {
drivers/net/ethernet/sun/niu.c
6469
err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
130
int i, j, k;
drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
142
for (k = 0; k < WX_FDIR_STATS_LEN; k++) {
drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
143
p = (char *)wx + wx_gstrings_fdir_stats[k].stat_offset;
drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
149
for (k = 0; k < WX_RSC_STATS_LEN; k++) {
drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
150
p = (char *)wx + wx_gstrings_rsc_stats[k].stat_offset;
drivers/net/fddi/skfp/fplustm.c
51
#define CHECK_NPP() { unsigned int k = 10000 ;\
drivers/net/fddi/skfp/fplustm.c
52
while ((inpw(FM_A(FM_STMCHN)) & FM_SNPPND) && k) k--;\
drivers/net/fddi/skfp/fplustm.c
53
if (!k) { \
drivers/net/fddi/skfp/fplustm.c
58
#define CHECK_CAM() { unsigned int k = 10 ;\
drivers/net/fddi/skfp/fplustm.c
59
while (!(inpw(FM_A(FM_AFSTAT)) & FM_DONE) && k) k--;\
drivers/net/fddi/skfp/fplustm.c
60
if (!k) { \
drivers/net/hamradio/scc.c
1094
int k;
drivers/net/hamradio/scc.c
1100
for (k = 0; k < (Nchips * 2); k++)
drivers/net/hamradio/scc.c
1102
scc2 = &SCC_Info[k];
drivers/net/hamradio/scc.c
1465
int chip, k;
drivers/net/hamradio/scc.c
1473
for (k = 0; k < nr_irqs; k++)
drivers/net/hamradio/scc.c
1474
if (Ivec[k].used)
drivers/net/hamradio/scc.c
1476
printk("%s%d", flag, k);
drivers/net/hamradio/scc.c
1981
int k;
drivers/net/hamradio/scc.c
1983
for (k = 0; k < Nchips*2; ++k) {
drivers/net/hamradio/scc.c
1984
if (!SCC_Info[k].init)
drivers/net/hamradio/scc.c
1987
return &SCC_Info[k];
drivers/net/hamradio/scc.c
2000
unsigned k;
drivers/net/hamradio/scc.c
2004
for (k = (v == SEQ_START_TOKEN) ? 0 : (scc - SCC_Info)+1;
drivers/net/hamradio/scc.c
2005
k < Nchips*2; ++k) {
drivers/net/hamradio/scc.c
2006
if (SCC_Info[k].init)
drivers/net/hamradio/scc.c
2007
return &SCC_Info[k];
drivers/net/hamradio/scc.c
2123
int k;
drivers/net/hamradio/scc.c
2136
for (k = 0; k < Nchips; k++)
drivers/net/hamradio/scc.c
2137
if ( (ctrl = SCC_ctrl[k].chan_A) )
drivers/net/hamradio/scc.c
2145
for (k = 0; k < nr_irqs ; k++)
drivers/net/hamradio/scc.c
2146
if (Ivec[k].used) free_irq(k, NULL);
drivers/net/hamradio/scc.c
2151
for (k = 0; k < Nchips*2; k++)
drivers/net/hamradio/scc.c
2153
scc = &SCC_Info[k];
drivers/net/hamradio/scc.c
345
int k;
drivers/net/hamradio/scc.c
347
for (k=0; k<3; k++)
drivers/net/hamradio/scc.c
638
int k;
drivers/net/hamradio/scc.c
642
for(k=0; k < SCC_IRQTIMEOUT; k++)
drivers/net/hamradio/scc.c
658
if (k == SCC_IRQTIMEOUT)
drivers/net/hamradio/scc.c
678
for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++)
drivers/net/hamradio/scc.c
689
if (k == SCC_IRQTIMEOUT)
drivers/net/hamradio/yam.c
316
int k;
drivers/net/hamradio/yam.c
319
for (k = 0; k < 8; k++) {
drivers/net/macsec.c
3161
int k;
drivers/net/macsec.c
3202
for (i = 0, k = 1; i < MACSEC_NUM_AN; i++) {
drivers/net/macsec.c
3211
rxsa_nest = nla_nest_start_noflag(skb, k++);
drivers/net/phy/mediatek/mtk-ge-soc.c
849
int i, k;
drivers/net/phy/mediatek/mtk-ge-soc.c
855
for (k = 0, i = 1; i < 12; i++) {
drivers/net/phy/mediatek/mtk-ge-soc.c
858
phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
drivers/net/phy/smsc.c
380
size_t i, j, k;
drivers/net/phy/smsc.c
393
k = 0;
drivers/net/phy/smsc.c
405
data[k++] = pattern[i];
drivers/net/phy/smsc.c
410
*datalen = k;
drivers/net/wireguard/selftest/allowedips.c
256
unsigned int i, j, k, mutate_amount, cidr;
drivers/net/wireguard/selftest/allowedips.c
304
for (k = 0; k < mutate_amount / 8; ++k)
drivers/net/wireguard/selftest/allowedips.c
305
mutate_mask[k] = 0xff;
drivers/net/wireguard/selftest/allowedips.c
306
mutate_mask[k] = 0xff
drivers/net/wireguard/selftest/allowedips.c
308
for (; k < 4; ++k)
drivers/net/wireguard/selftest/allowedips.c
309
mutate_mask[k] = 0;
drivers/net/wireguard/selftest/allowedips.c
310
for (k = 0; k < 4; ++k)
drivers/net/wireguard/selftest/allowedips.c
311
mutated[k] = (mutated[k] & mutate_mask[k]) |
drivers/net/wireguard/selftest/allowedips.c
312
(~mutate_mask[k] &
drivers/net/wireguard/selftest/allowedips.c
348
for (k = 0; k < mutate_amount / 8; ++k)
drivers/net/wireguard/selftest/allowedips.c
349
mutate_mask[k] = 0xff;
drivers/net/wireguard/selftest/allowedips.c
350
mutate_mask[k] = 0xff
drivers/net/wireguard/selftest/allowedips.c
352
for (; k < 4; ++k)
drivers/net/wireguard/selftest/allowedips.c
353
mutate_mask[k] = 0;
drivers/net/wireguard/selftest/allowedips.c
354
for (k = 0; k < 4; ++k)
drivers/net/wireguard/selftest/allowedips.c
355
mutated[k] = (mutated[k] & mutate_mask[k]) |
drivers/net/wireguard/selftest/allowedips.c
356
(~mutate_mask[k] &
drivers/net/wireless/ath/ath10k/debugfs_sta.c
545
int k = 0; \
drivers/net/wireless/ath/ath10k/debugfs_sta.c
551
k++; \
drivers/net/wireless/ath/ath10k/debugfs_sta.c
552
if (k % 8 == 0) { \
drivers/net/wireless/ath/ath10k/debugfs_sta.c
658
int len = 0, i, j, k, retval = 0;
drivers/net/wireless/ath/ath10k/debugfs_sta.c
676
for (k = 0; k < ATH10K_STATS_TYPE_MAX; k++) {
drivers/net/wireless/ath/ath10k/debugfs_sta.c
678
stats = &arsta->tx_stats->stats[k];
drivers/net/wireless/ath/ath10k/debugfs_sta.c
680
str_name[k],
drivers/net/wireless/ath/ath11k/debugfs_sta.c
146
int len = 0, i, j, k, retval = 0;
drivers/net/wireless/ath/ath11k/debugfs_sta.c
160
for (k = 0; k < ATH11K_STATS_TYPE_MAX; k++) {
drivers/net/wireless/ath/ath11k/debugfs_sta.c
162
stats = &arsta->tx_stats->stats[k];
drivers/net/wireless/ath/ath11k/debugfs_sta.c
164
str_name[k],
drivers/net/wireless/ath/ath11k/reg.c
434
u8 i, j, k;
drivers/net/wireless/ath/ath11k/reg.c
470
for (i = 0, k = 0; i < num_old_regd_rules; i++) {
drivers/net/wireless/ath/ath11k/reg.c
477
(new_rule + k++));
drivers/net/wireless/ath/ath11k/reg.c
639
u8 i = 0, j = 0, k = 0;
drivers/net/wireless/ath/ath11k/reg.c
725
k < reg_6ghz_number) {
drivers/net/wireless/ath/ath11k/reg.c
726
reg_rule = reg_rule_6ghz + k++;
drivers/net/wireless/ath/ath12k/reg.c
651
u8 i = 0, j = 0, k = 0;
drivers/net/wireless/ath/ath12k/reg.c
748
(k < reg_6ghz_number)) {
drivers/net/wireless/ath/ath12k/reg.c
749
reg_rule = reg_rule_6ghz + k++;
drivers/net/wireless/ath/ath9k/calib.c
440
int i, j, k = 0;
drivers/net/wireless/ath/ath9k/calib.c
447
h[i].privNF = ath9k_hw_get_default_nf(ah, chan, k);
drivers/net/wireless/ath/ath9k/calib.c
451
if (++k >= AR5416_MAX_CHAINS)
drivers/net/wireless/ath/ath9k/calib.c
452
k = 0;
drivers/net/wireless/ath/ath9k/eeprom.c
244
u16 i, k;
drivers/net/wireless/ath/ath9k/eeprom.c
257
k = pVpdList[idxL];
drivers/net/wireless/ath/ath9k/eeprom.c
259
k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
drivers/net/wireless/ath/ath9k/eeprom.c
262
pRetVpdList[i] = (u8) k;
drivers/net/wireless/ath/ath9k/eeprom.c
460
int i, j, k;
drivers/net/wireless/ath/ath9k/eeprom.c
583
k = 0;
drivers/net/wireless/ath/ath9k/eeprom.c
611
while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
drivers/net/wireless/ath/ath9k/eeprom.c
613
pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
drivers/net/wireless/ath/ath9k/eeprom.c
623
while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
drivers/net/wireless/ath/ath9k/eeprom.c
624
pPDADCValues[k++] = vpdTableI[i][ss++];
drivers/net/wireless/ath/ath9k/eeprom.c
633
(k < (AR5416_NUM_PDADC_VALUES - 1))) {
drivers/net/wireless/ath/ath9k/eeprom.c
636
pPDADCValues[k++] = (u8)((tmpVal > 255) ?
drivers/net/wireless/ath/ath9k/eeprom.c
653
while (k < AR5416_NUM_PDADC_VALUES) {
drivers/net/wireless/ath/ath9k/eeprom.c
654
pPDADCValues[k] = pPDADCValues[k - 1];
drivers/net/wireless/ath/ath9k/eeprom.c
655
k++;
drivers/net/wireless/ath/ath9k/eeprom_def.c
699
u16 k;
drivers/net/wireless/ath/ath9k/eeprom_def.c
717
for (k = 0; k < numXpdGain; k++)
drivers/net/wireless/ath/ath9k/eeprom_def.c
718
gb[k] = (u16)(gb[k] - *diff);
drivers/net/wireless/ath/ath9k/eeprom_def.c
725
for (k = 0; k < numXpdGain; k++)
drivers/net/wireless/ath/ath9k/eeprom_def.c
726
gb[k] = (u16)min(gb_limit, gb[k]);
drivers/net/wireless/ath/ath9k/eeprom_def.c
738
u16 k;
drivers/net/wireless/ath/ath9k/eeprom_def.c
748
for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
drivers/net/wireless/ath/ath9k/eeprom_def.c
749
pdadcValues[k] = pdadcValues[k + diff];
drivers/net/wireless/ath/ath9k/eeprom_def.c
753
for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
drivers/net/wireless/ath/ath9k/eeprom_def.c
754
pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
drivers/net/wireless/ath/carl9170/phy.c
1395
int k = i;
drivers/net/wireless/ath/carl9170/phy.c
1398
while (k-- > 0) {
drivers/net/wireless/ath/carl9170/phy.c
1399
if (modes[k].max_power !=
drivers/net/wireless/ath/carl9170/phy.c
1401
modes[i].max_power = modes[k].max_power;
drivers/net/wireless/ath/key.c
130
const struct ath_keyval *k,
drivers/net/wireless/ath/key.c
143
switch (k->kv_type) {
drivers/net/wireless/ath/key.c
164
if (k->kv_len < WLAN_KEY_LEN_WEP40) {
drivers/net/wireless/ath/key.c
166
k->kv_len);
drivers/net/wireless/ath/key.c
169
if (k->kv_len <= WLAN_KEY_LEN_WEP40)
drivers/net/wireless/ath/key.c
171
else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
drivers/net/wireless/ath/key.c
180
ath_err(common, "cipher %u not supported\n", k->kv_type);
drivers/net/wireless/ath/key.c
184
key0 = get_unaligned_le32(k->kv_val + 0);
drivers/net/wireless/ath/key.c
185
key1 = get_unaligned_le16(k->kv_val + 4);
drivers/net/wireless/ath/key.c
186
key2 = get_unaligned_le32(k->kv_val + 6);
drivers/net/wireless/ath/key.c
187
key3 = get_unaligned_le16(k->kv_val + 10);
drivers/net/wireless/ath/key.c
188
key4 = get_unaligned_le32(k->kv_val + 12);
drivers/net/wireless/ath/key.c
189
if (k->kv_len <= WLAN_KEY_LEN_WEP104)
drivers/net/wireless/ath/key.c
237
mic0 = get_unaligned_le32(k->kv_mic + 0);
drivers/net/wireless/ath/key.c
238
mic2 = get_unaligned_le32(k->kv_mic + 4);
drivers/net/wireless/ath/key.c
239
mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
drivers/net/wireless/ath/key.c
240
mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
drivers/net/wireless/ath/key.c
241
mic4 = get_unaligned_le32(k->kv_txmic + 4);
drivers/net/wireless/ath/key.c
279
mic0 = get_unaligned_le32(k->kv_mic + 0);
drivers/net/wireless/ath/key.c
280
mic2 = get_unaligned_le32(k->kv_mic + 4);
drivers/net/wireless/ath/wil6210/fw_inc.c
489
int n, i, k;
drivers/net/wireless/ath/wil6210/fw_inc.c
512
for (k = 0; k < ARRAY_SIZE(block->value); k++)
drivers/net/wireless/ath/wil6210/fw_inc.c
513
if (!wil_fw_addr_check(wil, &gwa_val[k],
drivers/net/wireless/ath/wil6210/fw_inc.c
514
d->gateway_value_addr[k],
drivers/net/wireless/ath/wil6210/fw_inc.c
536
for (k = 0; k < ARRAY_SIZE(block->value); k++)
drivers/net/wireless/ath/wil6210/fw_inc.c
537
v[k] = le32_to_cpu(block[i].value[k]);
drivers/net/wireless/ath/wil6210/fw_inc.c
543
for (k = 0; k < ARRAY_SIZE(block->value); k++)
drivers/net/wireless/ath/wil6210/fw_inc.c
544
writel(v[k], gwa_val[k]);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6181
int k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6243
for (k = 0; k < hw->max_rates; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6244
is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6246
if ((txrate[k]->idx >= 0)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6247
&& (txrate[k]->idx <
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6249
rspec[k] =
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6251
bitrates[txrate[k]->idx].hw_value;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6253
rspec[k] = BRCM_RATE_1M;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6256
rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6257
NRATE_MCS_INUSE | txrate[k]->idx);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6266
txrate[k]->
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6269
txrate[k]->
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6278
if (!rspec_active(rspec[k])) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6279
rspec[k] = BRCM_RATE_1M;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6292
for (k = 0; k < hw->max_rates; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6297
if (((is_mcs_rate(rspec[k]) &&
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6298
is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6299
is_ofdm_rate(rspec[k]))
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6300
&& ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6301
|| !(rspec[k] & RSPEC_OVERRIDE))) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6302
rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6305
if (is_mcs_rate(rspec[k])
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6311
rspec[k] |= (PHY_TXC1_MODE_STBC <<
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6315
rspec[k] |=
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6330
if (is_mcs_rate(rspec[k])) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6332
if ((rspec[k] & RSPEC_RATE_MASK)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6342
} else if (is_ofdm_rate(rspec[k])) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6354
if ((rspec[k] & RSPEC_RATE_MASK) == 32)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6356
rspec[k] = RSPEC_MIMORATE;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6362
rspec[k] &= ~RSPEC_BW_MASK;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6363
if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6364
rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6366
rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6369
rspec[k] &= ~RSPEC_SHORT_GI;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6372
if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6375
if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6376
&& (!is_mcs_rate(rspec[k]))) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6382
if (is_mcs_rate(rspec[k])) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6383
preamble_type[k] = mimo_preamble_type;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6389
if ((rspec[k] & RSPEC_SHORT_GI)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6390
&& is_single_stream(rspec[k] &
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6392
preamble_type[k] = BRCMS_MM_PREAMBLE;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6399
preamble_type[k] = BRCMS_SHORT_PREAMBLE;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6402
for (k = 0; k < hw->max_rates; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6404
rspec[k] &= ~RSPEC_BW_MASK;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6405
rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6408
if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6409
rspec[k] &= ~RSPEC_STF_MASK;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6410
rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6534
for (k = 0; k < 2; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
6535
rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1417
int rate_start_index = 0, rate1, rate2, k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1429
for (k = 0; k < 4; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1430
switch (k) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1475
for (k = 0; k < 4; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1476
switch (k) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1520
for (k = 0; k < 2; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1521
switch (k) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1539
for (k = 0; k < 2; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c
1540
switch (k) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3337
u16 num_samps, t, k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3359
k = 1;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3361
bw = phy_bw * 1000 * k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3363
k++;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3432
int k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3442
k = wlc_lcnphy_calc_floor(coeff_x, 0);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3443
y = 8 + k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3444
k = wlc_lcnphy_calc_floor(coeff_x, 1);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3445
x = 8 - k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3448
k = wlc_lcnphy_calc_floor(coeff_y, 0);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3449
y = 8 + k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3450
k = wlc_lcnphy_calc_floor(coeff_y, 1);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3451
x = 8 - k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3456
k = wlc_lcnphy_calc_floor(coeff_x, 0);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3457
y = 8 + k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3458
k = wlc_lcnphy_calc_floor(coeff_x, 1);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3459
x = 8 - k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3462
k = wlc_lcnphy_calc_floor(coeff_y, 0);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3463
y = 8 + k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3464
k = wlc_lcnphy_calc_floor(coeff_y, 1);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3465
x = 8 - k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3595
int phy_c4, phy_c5, k, l, j, phy_c6;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3716
for (k = -phy_c7; k <= phy_c7; k += phy_c7) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
3718
phy_c11 = phy_c15 + k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
977
int k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
978
k = 0;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
981
k = (coeff_x - 1) / 2;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
983
k = coeff_x / 2;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
988
k = (coeff_x) / 2;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
990
k = (coeff_x + 1) / 2;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c
992
return k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23381
u8 k;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23414
for (k = 0; k < NPHY_IQCAL_NUMGAINS; k++) {
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23415
if (tbl_iqcal_gainparams_nphy[band_idx][k][0] ==
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23420
if (WARN_ON(k == NPHY_IQCAL_NUMGAINS))
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23423
params->txgm = tbl_iqcal_gainparams_nphy[band_idx][k][1];
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23424
params->pga = tbl_iqcal_gainparams_nphy[band_idx][k][2];
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23425
params->pad = tbl_iqcal_gainparams_nphy[band_idx][k][3];
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23428
params->ncorr[0] = tbl_iqcal_gainparams_nphy[band_idx][k][4];
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23429
params->ncorr[1] = tbl_iqcal_gainparams_nphy[band_idx][k][5];
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23430
params->ncorr[2] = tbl_iqcal_gainparams_nphy[band_idx][k][6];
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c
23431
params->ncorr[3] = tbl_iqcal_gainparams_nphy[band_idx][k][7];
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
754
int i, j, k, ret, tbl_rev;
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
879
for (k = 0; k < BIOS_GEO_NUM_CHAINS; k++) {
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
882
fwrt->geo_profiles[i].bands[j].chains[k] =
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
883
fwrt->geo_profiles[i].bands[1].chains[k];
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
893
fwrt->geo_profiles[i].bands[j].chains[k] =
drivers/net/wireless/intel/iwlwifi/mld/d3.c
1172
for (int k = 0; k < SCAN_OFFLOAD_MATCHING_CHANNELS_LEN; k++)
drivers/net/wireless/intel/iwlwifi/mld/d3.c
1174
hweight8(matches[i].matching_channels[k]);
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1000
!pp->direct_scan[k].len)
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1004
if (pp->direct_scan[k].len)
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1007
s_ssid_bitmap |= BIT(k);
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1017
for (k = 0; k < pp->bssid_num; k++) {
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1018
if (memcmp(&pp->bssid_array[k],
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1023
if (bssid_bitmap & BIT(k))
drivers/net/wireless/intel/iwlwifi/mld/scan.c
1027
bssid_bitmap |= BIT(k);
drivers/net/wireless/intel/iwlwifi/mld/scan.c
693
int k;
drivers/net/wireless/intel/iwlwifi/mld/scan.c
697
for (k = 0; k < idex_s; k++) {
drivers/net/wireless/intel/iwlwifi/mld/scan.c
698
if (pp->short_ssid[k] ==
drivers/net/wireless/intel/iwlwifi/mld/scan.c
703
if (k == idex_s && idex_s < SCAN_SHORT_SSID_MAX_SIZE) {
drivers/net/wireless/intel/iwlwifi/mld/scan.c
710
for (k = 0; k < idex_b; k++) {
drivers/net/wireless/intel/iwlwifi/mld/scan.c
711
if (!memcmp(&pp->bssid_array[k],
drivers/net/wireless/intel/iwlwifi/mld/scan.c
716
if (k == idex_b && idex_b < SCAN_BSSID_MAX_SIZE &&
drivers/net/wireless/intel/iwlwifi/mld/scan.c
882
u8 k, n_s_ssids = 0, n_bssids = 0;
drivers/net/wireless/intel/iwlwifi/mld/scan.c
980
for (k = 0;
drivers/net/wireless/intel/iwlwifi/mld/scan.c
981
k < pp->short_ssid_num && n_s_ssids < max_s_ssids;
drivers/net/wireless/intel/iwlwifi/mld/scan.c
982
k++) {
drivers/net/wireless/intel/iwlwifi/mld/scan.c
984
le32_to_cpu(pp->short_ssid[k]) ==
drivers/net/wireless/intel/iwlwifi/mld/scan.c
987
if (s_ssid_bitmap & BIT(k)) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1720
int k;
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1724
for (k = 0; k < idex_s; k++) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1725
if (pp->short_ssid[k] ==
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1730
if (k == idex_s && idex_s < SCAN_SHORT_SSID_MAX_SIZE) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1737
for (k = 0; k < idex_b; k++) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1738
if (!memcmp(&pp->bssid_array[k],
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1743
if (k == idex_b && idex_b < SCAN_BSSID_MAX_SIZE &&
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1776
u8 k, n_s_ssids = 0, n_bssids = 0;
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1881
for (k = 0;
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1882
k < pp->short_ssid_num && n_s_ssids < max_s_ssids;
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1883
k++) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1885
le32_to_cpu(pp->short_ssid[k]) ==
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1888
if (s_ssid_bitmap & BIT(k)) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1902
!pp->direct_scan[k].len)
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1906
if (pp->direct_scan[k].len)
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1909
s_ssid_bitmap |= BIT(k);
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1919
for (k = 0; k < pp->bssid_num; k++) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1920
if (!memcmp(&pp->bssid_array[k],
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1923
if (!(bssid_bitmap & BIT(k))) {
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
1925
bssid_bitmap |= BIT(k);
drivers/net/wireless/intersil/p54/eeprom.c
323
unsigned int i, j, k, max_channel_num;
drivers/net/wireless/intersil/p54/eeprom.c
393
k = 0;
drivers/net/wireless/intersil/p54/eeprom.c
395
if (p54_generate_band(dev, list, &k, i) == 0)
drivers/net/wireless/marvell/mwifiex/cfg80211.c
3275
int j, k, valid_byte_cnt = 0;
drivers/net/wireless/marvell/mwifiex/cfg80211.c
3279
for (k = 0; k < 8; k++) {
drivers/net/wireless/marvell/mwifiex/cfg80211.c
3280
if (pat->mask[j] & 1 << k) {
drivers/net/wireless/marvell/mwifiex/cfg80211.c
3282
&pat->pattern[j * 8 + k], 1);
drivers/net/wireless/marvell/mwifiex/cfp.c
415
u32 k = 0;
drivers/net/wireless/marvell/mwifiex/cfp.c
425
k = mwifiex_copy_rates(rates, k, supported_rates_b,
drivers/net/wireless/marvell/mwifiex/cfp.c
433
k = mwifiex_copy_rates(rates, k, supported_rates_g,
drivers/net/wireless/marvell/mwifiex/cfp.c
445
k = mwifiex_copy_rates(rates, k, supported_rates_bg,
drivers/net/wireless/marvell/mwifiex/cfp.c
453
k = mwifiex_copy_rates(rates, k, supported_rates_a,
drivers/net/wireless/marvell/mwifiex/cfp.c
464
k = mwifiex_copy_rates(rates, k, supported_rates_a,
drivers/net/wireless/marvell/mwifiex/cfp.c
471
k = mwifiex_copy_rates(rates, k, supported_rates_n,
drivers/net/wireless/marvell/mwifiex/cfp.c
480
k = mwifiex_copy_rates(rates, k, adhoc_rates_b,
drivers/net/wireless/marvell/mwifiex/cfp.c
486
k = mwifiex_copy_rates(rates, k, adhoc_rates_g,
drivers/net/wireless/marvell/mwifiex/cfp.c
492
k = mwifiex_copy_rates(rates, k, adhoc_rates_bg,
drivers/net/wireless/marvell/mwifiex/cfp.c
498
k = mwifiex_copy_rates(rates, k, adhoc_rates_a,
drivers/net/wireless/marvell/mwifiex/cfp.c
504
return k;
drivers/net/wireless/mediatek/mt76/mt7603/mac.c
741
int i, k;
drivers/net/wireless/mediatek/mt76/mt7603/mac.c
772
for (k = 0; k < i; k++) {
drivers/net/wireless/mediatek/mt76/mt7603/mac.c
773
if (rates[i].idx != rates[k].idx)
drivers/net/wireless/mediatek/mt76/mt7603/mac.c
775
if ((rates[i].flags ^ rates[k].flags) &
drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
1705
int k = 0;
drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
1708
for (k = 0; k < bssid_index; k++) {
drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
1709
if (!memcmp(&mdev->rnr.bssid[k],
drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
1715
if (k == bssid_index &&
drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
1719
mdev->rnr.channel[k] = scan_list[ch_idx]->hw_value;
drivers/net/wireless/mediatek/mt76/mt76x0/init.c
173
int ret, i, k;
drivers/net/wireless/mediatek/mt76/mt76x0/init.c
199
for (k = 0; k < 4; k++)
drivers/net/wireless/mediatek/mt76/mt76x0/init.c
200
mt76x02_mac_shared_key_setup(dev, i, k, NULL);
drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
130
for (k = 0; k < 4; k++)
drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
131
mt76x02_mac_shared_key_setup(dev, i, k, NULL);
drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
74
int i, k;
drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c
128
int i, k, err;
drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c
171
for (k = 0; k < 4; k++)
drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c
172
mt76x02_mac_shared_key_setup(dev, i, k, NULL);
drivers/net/wireless/mediatek/mt7601u/mac.c
318
int i, j, k;
drivers/net/wireless/mediatek/mt7601u/mac.c
326
k = 0;
drivers/net/wireless/mediatek/mt7601u/mac.c
342
sum += (val & 0xffff) * (1 + k * 2) +
drivers/net/wireless/mediatek/mt7601u/mac.c
343
(val >> 16) * (2 + k * 2);
drivers/net/wireless/mediatek/mt7601u/mac.c
344
k++;
drivers/net/wireless/microchip/wilc1000/wlan.c
824
u8 k, ac;
drivers/net/wireless/microchip/wilc1000/wlan.c
873
for (k = 0; (k < num_pkts_to_add[ac]) &&
drivers/net/wireless/microchip/wilc1000/wlan.c
874
(!max_size_over) && tqe_q[ac]; k++) {
drivers/net/wireless/realtek/rtlwifi/efuse.c
102
k++;
drivers/net/wireless/realtek/rtlwifi/efuse.c
103
if (k == 1000)
drivers/net/wireless/realtek/rtlwifi/efuse.c
119
u32 k = 0;
drivers/net/wireless/realtek/rtlwifi/efuse.c
152
k++;
drivers/net/wireless/realtek/rtlwifi/efuse.c
153
if (k == 100) {
drivers/net/wireless/realtek/rtlwifi/efuse.c
154
k = 0;
drivers/net/wireless/realtek/rtlwifi/efuse.c
76
u32 k = 0;
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
1431
u8 i, j, k, l, m;
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
1438
for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
1442
[i][j][k][m][l]
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
1447
for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
1451
[i][j][k][m][l]
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3718
int i, k, vdf_y[3], vdf_x[3],
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3828
for (k = 0; k <= 2; k++) {
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3829
switch (k) {
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3882
vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3884
vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3903
if (k == 3) {
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3904
tx_x0[cal] = vdf_x[k-1];
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3905
tx_y0[cal] = vdf_y[k-1];
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3964
for (k = 0; k <= 2; k++) {
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
3983
switch (k) {
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
4104
if (k == 2)
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
4132
vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
4134
vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
4155
if (k == 3) {
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
4156
rx_x0[cal] = vdf_x[k-1];
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c
4157
rx_y0[cal] = vdf_y[k-1];
drivers/net/wireless/realtek/rtw88/rtw8821a.c
143
int k;
drivers/net/wireless/realtek/rtw88/rtw8821a.c
145
for (k = 0; k < 3; k++) {
drivers/net/wireless/realtek/rtw88/rtw8821a.c
146
switch (k) {
drivers/net/wireless/realtek/rtw88/rtw8821a.c
229
vdf_x[k] = rtw_read32_mask(rtwdev,
drivers/net/wireless/realtek/rtw88/rtw8821a.c
232
vdf_x[k] <<= 21;
drivers/net/wireless/realtek/rtw88/rtw8821a.c
236
vdf_y[k] = rtw_read32_mask(rtwdev,
drivers/net/wireless/realtek/rtw88/rtw8821a.c
239
vdf_y[k] <<= 21;
drivers/net/wireless/realtek/rtw88/rtw8821a.c
255
if (k == 3) {
drivers/net/wireless/realtek/rtw88/rtw8821a.c
256
tx_x0[cal] = vdf_x[k - 1];
drivers/net/wireless/realtek/rtw88/rtw8821a.c
257
tx_y0[cal] = vdf_y[k - 1];
drivers/net/wireless/realtek/rtw88/sar.c
100
for (k = 0; k < RTW_RATE_SECTION_NUM; k++) {
drivers/net/wireless/realtek/rtw88/sar.c
104
.rs = k,
drivers/net/wireless/realtek/rtw88/sar.c
108
new.cfg[j][k].common[idx] = val;
drivers/net/wireless/realtek/rtw88/sar.c
78
u32 idx, i, j, k;
drivers/net/wireless/realtek/rtw89/coex.c
6606
u8 j, k, dbcc_2g_cid, dbcc_2g_cid2, dbcc_2g_phy, pta_req_band;
drivers/net/wireless/realtek/rtw89/coex.c
6640
for (k = 0; k < link_cnt; k++) {
drivers/net/wireless/realtek/rtw89/coex.c
6641
if (k == dbcc_2g_cid)
drivers/net/wireless/realtek/rtw89/coex.c
6644
if (phy[k] == dbcc_2g_phy) {
drivers/net/wireless/realtek/rtw89/coex.c
6646
dbcc_2g_cid2 = k;
drivers/net/wireless/realtek/rtw89/debug.c
1021
u32 i, j, k, page;
drivers/net/wireless/realtek/rtw89/debug.c
1079
for (k = 0; k < 4; k++) {
drivers/net/wireless/realtek/rtw89/debug.c
1080
val = rtw89_read32(rtwdev, j + (k << 2));
drivers/net/wireless/realtek/rtw89/debug.c
269
u32 addr, addr_end, data, k;
drivers/net/wireless/realtek/rtw89/debug.c
303
for (k = 0; k < 16; k += 4) {
drivers/net/wireless/realtek/rtw89/debug.c
304
data = rtw89_read32(rtwdev, addr + k);
drivers/net/wireless/realtek/rtw89/phy.c
3467
int i, j, k;
drivers/net/wireless/realtek/rtw89/phy.c
3665
for (k = 0; k < 4; k++) {
drivers/net/wireless/realtek/rtw89/phy.c
3668
i, j, k, tssi->alignment_power_cw_h[i][j][k]);
drivers/net/wireless/realtek/rtw89/phy.c
3671
i, j, k, tssi->alignment_power_cw_l[i][j][k]);
drivers/net/wireless/realtek/rtw89/phy.c
3674
i, j, k, tssi->alignment_power[i][j][k]);
drivers/net/wireless/realtek/rtw89/phy.c
3677
i, j, k,
drivers/net/wireless/realtek/rtw89/phy.c
3678
(tssi->alignment_power_cw_h[i][j][k] << 8) +
drivers/net/wireless/realtek/rtw89/phy.c
3679
tssi->alignment_power_cw_l[i][j][k]);
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
3491
int j, k;
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
3517
for (k = 0; k < retry; k++) {
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
3531
k, tx_counter_tmp, path);
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
3534
if (k >= retry) {
drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
3537
k, path);
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c
3561
int j, k;
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c
3588
for (k = 0; k < retry; k++) {
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c
3602
k, tx_counter_tmp, path);
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c
3605
if (k >= retry) {
drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c
3608
k, path);
drivers/net/wireless/realtek/rtw89/sar.c
462
unsigned int i, j, k;
drivers/net/wireless/realtek/rtw89/sar.c
485
for (k = 0; k < NUM_OF_RTW89_ACPI_SAR_SUBBAND; k++)
drivers/net/wireless/realtek/rtw89/sar.c
487
"On subband %u, { %d, %d }\n", k,
drivers/net/wireless/realtek/rtw89/sar.c
488
ent->v[k][RF_PATH_A], ent->v[k][RF_PATH_B]);
drivers/net/wireless/silabs/wfx/key.c
154
struct wfx_hif_req_add_key k = { };
drivers/net/wireless/silabs/wfx/key.c
165
k.int_id = wvif->id;
drivers/net/wireless/silabs/wfx/key.c
166
k.entry_index = idx;
drivers/net/wireless/silabs/wfx/key.c
170
k.type = fill_wep_pair(&k.key.wep_pairwise_key, key, sta->addr);
drivers/net/wireless/silabs/wfx/key.c
172
k.type = fill_wep_group(&k.key.wep_group_key, key);
drivers/net/wireless/silabs/wfx/key.c
175
k.type = fill_tkip_pair(&k.key.tkip_pairwise_key, key, sta->addr);
drivers/net/wireless/silabs/wfx/key.c
177
k.type = fill_tkip_group(&k.key.tkip_group_key, key, &seq,
drivers/net/wireless/silabs/wfx/key.c
181
k.type = fill_ccmp_pair(&k.key.aes_pairwise_key, key, sta->addr);
drivers/net/wireless/silabs/wfx/key.c
183
k.type = fill_ccmp_group(&k.key.aes_group_key, key, &seq);
drivers/net/wireless/silabs/wfx/key.c
186
k.type = fill_sms4_pair(&k.key.wapi_pairwise_key, key, sta->addr);
drivers/net/wireless/silabs/wfx/key.c
188
k.type = fill_sms4_group(&k.key.wapi_group_key, key);
drivers/net/wireless/silabs/wfx/key.c
190
k.type = fill_aes_cmac_group(&k.key.igtk_group_key, key, &seq);
drivers/net/wireless/silabs/wfx/key.c
197
ret = wfx_hif_add_key(wdev, &k);
drivers/net/wireless/zydas/zd1211rw/zd_usb.c
630
unsigned int l, k, n;
drivers/net/wireless/zydas/zd1211rw/zd_usb.c
632
k = get_unaligned_le16(&length_info->length[i]);
drivers/net/wireless/zydas/zd1211rw/zd_usb.c
633
if (k == 0)
drivers/net/wireless/zydas/zd1211rw/zd_usb.c
635
n = l+k;
drivers/net/wireless/zydas/zd1211rw/zd_usb.c
638
zd_mac_rx(zd_usb_to_hw(usb), buffer+l, k);
drivers/nfc/fdp/i2c.c
132
u8 tmp[FDP_NCI_I2C_MAX_PAYLOAD], lrc, k;
drivers/nfc/fdp/i2c.c
139
for (k = 0; k < 2; k++) {
drivers/of/overlay.c
211
int k;
drivers/of/overlay.c
231
for (k = 0; k < ovcs->count; k++) {
drivers/of/overlay.c
232
fragment = &ovcs->fragments[k];
drivers/of/overlay.c
236
if (k >= ovcs->count)
drivers/pci/pci.c
6699
char *k = strchr(str, ',');
drivers/pci/pci.c
6700
if (k)
drivers/pci/pci.c
6701
*k++ = 0;
drivers/pci/pci.c
6760
str = k;
drivers/pcmcia/i82365.c
755
int i, j, sock, k, ns, id;
drivers/pcmcia/i82365.c
816
for (k = 0; k <= sockets; k++)
drivers/pcmcia/i82365.c
817
i365_set(k, I365_MEM(0)+I365_W_OFF, k);
drivers/pcmcia/i82365.c
818
for (k = 0; k <= sockets; k++)
drivers/pcmcia/i82365.c
819
if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k)
drivers/pcmcia/i82365.c
821
if (k <= sockets) break;
drivers/perf/amlogic/meson_ddr_pmu_core.c
415
int i, j, k;
drivers/perf/amlogic/meson_ddr_pmu_core.c
419
k = 0;
drivers/perf/amlogic/meson_ddr_pmu_core.c
422
dst[j++] = &event_attrs[k].attr.attr;
drivers/perf/amlogic/meson_ddr_pmu_core.c
423
dst[j++] = &event_unit_attrs[k].attr;
drivers/perf/amlogic/meson_ddr_pmu_core.c
424
dst[j++] = &event_scale_attrs[k].attr;
drivers/perf/amlogic/meson_ddr_pmu_core.c
426
k++;
drivers/perf/amlogic/meson_ddr_pmu_core.c
429
for (i = 0; i < pmu->info.hw_info->chann_nr; i++, k++) {
drivers/perf/amlogic/meson_ddr_pmu_core.c
430
dst[j++] = &event_attrs[k].attr.attr;
drivers/perf/amlogic/meson_ddr_pmu_core.c
431
dst[j++] = &event_unit_attrs[k].attr;
drivers/perf/amlogic/meson_ddr_pmu_core.c
432
dst[j++] = &event_scale_attrs[k].attr;
drivers/perf/riscv_pmu_sbi.c
309
int i, j, k, result = 0, count = 0;
drivers/perf/riscv_pmu_sbi.c
321
for (k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++)
drivers/perf/riscv_pmu_sbi.c
323
pmu_cache_event_map[i][j][k].event_idx;
drivers/perf/riscv_pmu_sbi.c
348
for (k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) {
drivers/perf/riscv_pmu_sbi.c
351
pmu_cache_event_map[i][j][k].event_idx = -ENOENT;
drivers/perf/riscv_pmu_sbi.c
394
for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++)
drivers/perf/riscv_pmu_sbi.c
395
pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]);
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
1048
unsigned long k = 0, lc, k_sub, lc_sub;
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
1080
&k, &lc);
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
1102
cfg->sdm_en = k > 0 ? 1 : 0;
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
1106
cfg->sdm_num = k;
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
1055
int i = 0, j = 0, k = 0, bank;
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
1095
k = info->banks[bank].pin_base;
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
1103
for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) {
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
1104
pdesc->number = k;
drivers/pinctrl/mvebu/pinctrl-mvebu.c
583
unsigned gid, n, k;
drivers/pinctrl/mvebu/pinctrl-mvebu.c
617
for (k = 0; k < ctrl->npins; k++)
drivers/pinctrl/mvebu/pinctrl-mvebu.c
618
ctrl->pins[k] = ctrl->pid + k;
drivers/pinctrl/mvebu/pinctrl-mvebu.c
680
for (k = 1; k < ctrl->npins; k++) {
drivers/pinctrl/mvebu/pinctrl-mvebu.c
686
pctl->groups[gid].pins = &ctrl->pins[k];
drivers/pinctrl/mvebu/pinctrl-mvebu.c
688
sprintf(noname_buf, "mpp%d", ctrl->pid+k);
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
873
#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
877
.flag = k }
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
1272
#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
1278
.fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \
drivers/pinctrl/pinctrl-at91.c
1364
int ret, i, j, k;
drivers/pinctrl/pinctrl-at91.c
1381
for (i = 0, k = 0; i < gpio_banks; i++) {
drivers/pinctrl/pinctrl-at91.c
1388
for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
drivers/pinctrl/pinctrl-at91.c
1393
pdesc->number = k;
drivers/pinctrl/pinctrl-rockchip.c
3970
int k;
drivers/pinctrl/pinctrl-rockchip.c
3986
for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
drivers/pinctrl/pinctrl-rockchip.c
3993
for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
drivers/pinctrl/pinctrl-rockchip.c
3994
pdesc->number = k;
drivers/pinctrl/pinctrl-rp1.c
1726
int k;
drivers/pinctrl/pinctrl-rp1.c
1728
for (k = 0; k < array_size; k++) {
drivers/pinctrl/pinctrl-rp1.c
1729
regfield = array[k];
drivers/pinctrl/pinctrl-rp1.c
1735
out[k] = devm_regmap_field_alloc(dev, regmap, regfield);
drivers/pinctrl/pinctrl-rp1.c
1737
if (IS_ERR(out[k]))
drivers/pinctrl/pinctrl-rp1.c
1738
return PTR_ERR(out[k]);
drivers/pinctrl/pinctrl-st.c
1590
int i = 0, j = 0, k = 0, bank;
drivers/pinctrl/pinctrl-st.c
1646
k = info->banks[bank].range.pin_base;
drivers/pinctrl/pinctrl-st.c
1653
for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
drivers/pinctrl/pinctrl-st.c
1654
pdesc->number = k;
drivers/pinctrl/renesas/core.c
1042
unsigned int i, j, k;
drivers/pinctrl/renesas/core.c
1155
for (k = 0; k < info->nr_groups; k++) {
drivers/pinctrl/renesas/core.c
1157
info->groups[k].name)) {
drivers/pinctrl/renesas/core.c
1158
refcnts[k]++;
drivers/pinctrl/renesas/core.c
1163
if (k == info->nr_groups)
drivers/pinctrl/renesas/core.c
205
unsigned int k;
drivers/pinctrl/renesas/core.c
215
for (k = 0; k <= in_pos; k++)
drivers/pinctrl/renesas/core.c
216
*posp -= abs(crp->var_field_width[k]);
drivers/pinctrl/renesas/core.c
249
unsigned int k = 0;
drivers/pinctrl/renesas/core.c
253
pfc->info->cfg_regs + k;
drivers/pinctrl/renesas/core.c
287
k++;
drivers/pinctrl/renesas/core.c
297
unsigned int k;
drivers/pinctrl/renesas/core.c
304
for (k = 0; k < pfc->info->pinmux_data_size; k++) {
drivers/pinctrl/renesas/core.c
305
if (data[k] == mark) {
drivers/pinctrl/renesas/core.c
306
*enum_idp = data[k + 1];
drivers/pinctrl/renesas/core.c
307
return k + 1;
drivers/pinctrl/renesas/gpio.c
202
unsigned int i, k;
drivers/pinctrl/renesas/gpio.c
207
for (k = 0; gpios[k] >= 0; k++) {
drivers/pinctrl/renesas/gpio.c
208
if (gpios[k] == offset)
drivers/pinctrl/stm32/pinctrl-stm32.c
708
int i, k;
drivers/pinctrl/stm32/pinctrl-stm32.c
720
for (k = 0; k < STM32_CONFIG_NUM; k++) {
drivers/pinctrl/sunplus/sppctl.c
1027
for (k = 0; k < sppctl_list_funcs[i].gnum; k++) {
drivers/pinctrl/sunplus/sppctl.c
1028
sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name;
drivers/pinctrl/sunplus/sppctl.c
1030
sppctl->g2fp_maps[j].g_idx = k;
drivers/pinctrl/sunplus/sppctl.c
996
int i, k, j;
drivers/pinctrl/tegra/pinctrl-tegra.c
773
unsigned int i, k;
drivers/pinctrl/tegra/pinctrl-tegra.c
778
for (k = 0; k < bank_size; k++)
drivers/pinctrl/tegra/pinctrl-tegra.c
791
unsigned int i, k;
drivers/pinctrl/tegra/pinctrl-tegra.c
796
for (k = 0; k < bank_size; k++)
drivers/platform/mellanox/mlxreg-hotplug.c
259
int num_attrs = 0, id = 0, i, j, k, count, ret;
drivers/platform/mellanox/mlxreg-hotplug.c
284
k = 0;
drivers/platform/mellanox/mlxreg-hotplug.c
319
PRIV_DEV_ATTR(id).index = k;
drivers/platform/mellanox/mlxreg-hotplug.c
323
k++;
drivers/platform/mellanox/mlxreg-hotplug.c
325
num_attrs += k;
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1474
is_adjacent_block(u32 *addrs, dma_addr_t addr, unsigned int k)
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1478
if (!k)
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1481
tmp = (addrs[k - 1] & PAGE_MASK) +
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1482
(((addrs[k - 1] & ~PAGE_MASK) + 1) << PAGE_SHIFT);
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1502
unsigned int num_pages, offset, i, k;
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1640
k = 0;
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1652
if (is_adjacent_block(addrs, addr, k))
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1653
addrs[k - 1] += ((len + PAGE_SIZE - 1) >> PAGE_SHIFT);
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
1655
addrs[k++] = (addr & PAGE_MASK) |
drivers/platform/x86/amd/hfi/hfi.c
190
for (unsigned int k = 0; k < info->nr_class; k++) {
drivers/platform/x86/amd/hfi/hfi.c
195
info->amd_hfi_classes[k].eff = table[apic_index + 2 * k];
drivers/platform/x86/amd/hfi/hfi.c
196
info->amd_hfi_classes[k].perf = table[apic_index + 2 * k + 1];
drivers/platform/x86/uv_sysfs.c
368
int j = 0, k = 0, ret, sz;
drivers/platform/x86/uv_sysfs.c
399
for (k = 0; k < hub_buf[j].ports; k++) {
drivers/platform/x86/uv_sysfs.c
400
uv_hubs[j]->ports[k] = kzalloc_obj(*uv_hubs[j]->ports[k]);
drivers/platform/x86/uv_sysfs.c
401
if (!uv_hubs[j]->ports[k]) {
drivers/platform/x86/uv_sysfs.c
403
k--;
drivers/platform/x86/uv_sysfs.c
406
uv_hubs[j]->ports[k]->port_info = &port_buf[j][k];
drivers/platform/x86/uv_sysfs.c
407
ret = kobject_init_and_add(&uv_hubs[j]->ports[k]->kobj, &uv_port_attr_type,
drivers/platform/x86/uv_sysfs.c
408
&uv_hubs[j]->kobj, "port_%d", port_buf[j][k].port);
drivers/platform/x86/uv_sysfs.c
411
kobject_uevent(&uv_hubs[j]->ports[k]->kobj, KOBJ_ADD);
drivers/platform/x86/uv_sysfs.c
418
for (; k >= 0; k--)
drivers/platform/x86/uv_sysfs.c
419
kobject_put(&uv_hubs[j]->ports[k]->kobj);
drivers/platform/x86/uv_sysfs.c
421
k = hub_buf[j-1].ports - 1;
drivers/platform/x86/uv_sysfs.c
437
int j, k;
drivers/platform/x86/uv_sysfs.c
440
for (k = hub_buf[j].ports - 1; k >= 0; k--)
drivers/platform/x86/uv_sysfs.c
441
kobject_put(&uv_hubs[j]->ports[k]->kobj);
drivers/platform/x86/uv_sysfs.c
654
int l = 0, k = 0;
drivers/platform/x86/uv_sysfs.c
684
uv_pci_objs[k] = kzalloc_obj(*uv_pci_objs[k]);
drivers/platform/x86/uv_sysfs.c
685
if (!uv_pci_objs[k]) {
drivers/platform/x86/uv_sysfs.c
689
ret = init_pci_top_obj(uv_pci_objs[k], found);
drivers/platform/x86/uv_sysfs.c
692
k++;
drivers/platform/x86/uv_sysfs.c
693
if (k == num_pci_lines)
drivers/platform/x86/uv_sysfs.c
704
k--;
drivers/platform/x86/uv_sysfs.c
705
for (; k >= 0; k--)
drivers/platform/x86/uv_sysfs.c
706
kobject_put(&uv_pci_objs[k]->kobj);
drivers/platform/x86/uv_sysfs.c
716
int k;
drivers/platform/x86/uv_sysfs.c
718
for (k = 0; k < num_pci_lines; k++)
drivers/platform/x86/uv_sysfs.c
719
kobject_put(&uv_pci_objs[k]->kobj);
drivers/platform/x86/winmate-fm07-keys.c
31
uint8_t k;
drivers/platform/x86/winmate-fm07-keys.c
60
k = inb(PORT_DATA);
drivers/platform/x86/winmate-fm07-keys.c
64
input_report_key(input, BASE_KEY + i, (~k) & 1);
drivers/platform/x86/winmate-fm07-keys.c
65
k >>= 1;
drivers/pmdomain/renesas/rcar-gen4-sysc.c
117
int k;
drivers/pmdomain/renesas/rcar-gen4-sysc.c
140
for (k = 0; k < PDRESR_RETRIES; k++) {
drivers/pmdomain/renesas/rcar-gen4-sysc.c
152
if (k == PDRESR_RETRIES) {
drivers/pmdomain/renesas/rcar-sysc.c
107
unsigned int status, k;
drivers/pmdomain/renesas/rcar-sysc.c
133
for (k = 0; k < PWRER_RETRIES; k++) {
drivers/pmdomain/renesas/rcar-sysc.c
145
if (k == PWRER_RETRIES) {
drivers/ps3/ps3av.c
796
int i, j, k, res;
drivers/ps3/ps3av.c
817
for (k = 0; k < hw_conf->num_of_spdif; k++)
drivers/ps3/ps3av.c
818
ps3av->av_port[i + j + k] = PS3AV_CMD_AVPORT_SPDIF_0 + k;
drivers/regulator/core.c
5862
int i, k;
drivers/regulator/core.c
5878
for (k = 1; k < __n_coupled; k++) {
drivers/regulator/core.c
5879
__c_rdev = __c_desc->coupled_rdevs[k];
drivers/regulator/core.c
5882
__c_desc->coupled_rdevs[k] = NULL;
drivers/rtc/rtc-r9701.c
55
int k, ret;
drivers/rtc/rtc-r9701.c
59
for (k = 0; ret == 0 && k < no_regs; k++) {
drivers/rtc/rtc-r9701.c
60
txbuf[0] = 0x80 | regs[k];
drivers/rtc/rtc-r9701.c
62
regs[k] = rxbuf[0];
drivers/s390/block/dcssblk.c
962
int rc, i, j, k;
drivers/s390/block/dcssblk.c
978
for (k = 0; (buf[k] != ':') && (buf[k] != '\0'); k++)
drivers/s390/block/dcssblk.c
979
buf[k] = toupper(buf[k]);
drivers/s390/block/dcssblk.c
980
buf[k] = '\0';
drivers/s390/char/con3270.c
1332
int k;
drivers/s390/char/con3270.c
1339
k = min_t(int, line->len - tp->cx, tp->view.cols - tp->cx - n);
drivers/s390/char/con3270.c
1340
while (k--)
drivers/s390/char/con3270.c
1341
line->cells[tp->cx + n + k] = line->cells[tp->cx + k];
drivers/s390/char/keyboard.c
158
int i, j, k;
drivers/s390/char/keyboard.c
166
k = ((i & 1) << 7) + j;
drivers/s390/char/keyboard.c
170
ascebc[KVAL(keysym)] = k;
drivers/s390/char/keyboard.c
172
ascebc[ret_diacr[KVAL(keysym)]] = k;
drivers/s390/char/keyboard.c
185
int i, j, k;
drivers/s390/char/keyboard.c
194
k = ((i & 1) << 7) + j;
drivers/s390/char/keyboard.c
197
ebcasc[k] = KVAL(keysym);
drivers/s390/char/keyboard.c
199
ebcasc[k] = ret_diacr[KVAL(keysym)];
drivers/scsi/FlashPoint.c
5431
unsigned char i, k, ScamFlg;
drivers/scsi/FlashPoint.c
5562
k = FPT_scxferc(p_port, 0x00);
drivers/scsi/FlashPoint.c
5564
if (FPT_scvalq(k)) {
drivers/scsi/FlashPoint.c
5570
(k &
drivers/scsi/FlashPoint.c
5732
unsigned char i, k, scam_id;
drivers/scsi/FlashPoint.c
5743
for (k = 0; k < ID_STRING_LENGTH; k++) {
drivers/scsi/FlashPoint.c
5744
temp_id_string[k] = (unsigned char)0x00;
drivers/scsi/FlashPoint.c
5758
for (k = 4; k < ID_STRING_LENGTH; k++)
drivers/scsi/FlashPoint.c
5759
temp_id_string[k] = (unsigned char)0x00;
drivers/scsi/FlashPoint.c
5777
for (k = 1; k < 0x08; k <<= 1)
drivers/scsi/FlashPoint.c
5778
if (!(k & i))
drivers/scsi/FlashPoint.c
6175
unsigned char i, k, max_id;
drivers/scsi/FlashPoint.c
6190
for (k = 0; k < 4; k++)
drivers/scsi/FlashPoint.c
6191
FPT_scamInfo[i].id_string[k] =
drivers/scsi/FlashPoint.c
6192
pCurrNvRam->niScamTbl[i][k];
drivers/scsi/FlashPoint.c
6193
for (k = 4; k < ID_STRING_LENGTH; k++)
drivers/scsi/FlashPoint.c
6194
FPT_scamInfo[i].id_string[k] =
drivers/scsi/FlashPoint.c
6205
for (k = 0; k < ID_STRING_LENGTH; k += 2) {
drivers/scsi/FlashPoint.c
6211
((unsigned short)ID_STRING_LENGTH / 2)) + (unsigned short)(k / 2)));
drivers/scsi/FlashPoint.c
6212
FPT_scamInfo[i].id_string[k] =
drivers/scsi/FlashPoint.c
6215
FPT_scamInfo[i].id_string[k + 1] =
drivers/scsi/FlashPoint.c
6229
for (k = 0; k < ID_STRING_LENGTH; k++)
drivers/scsi/FlashPoint.c
6230
FPT_scamInfo[p_our_id].id_string[k] = FPT_scamHAString[k];
drivers/scsi/FlashPoint.c
6247
unsigned char i, k, match;
drivers/scsi/FlashPoint.c
6253
for (k = 0; k < ID_STRING_LENGTH; k++) {
drivers/scsi/FlashPoint.c
6254
if (p_id_string[k] != FPT_scamInfo[i].id_string[k])
drivers/scsi/FlashPoint.c
6280
for (k = 0; k < ID_STRING_LENGTH; k++) {
drivers/scsi/FlashPoint.c
6281
FPT_scamInfo[match].id_string[k] =
drivers/scsi/FlashPoint.c
6282
p_id_string[k];
drivers/scsi/FlashPoint.c
6324
for (k = 0; k < ID_STRING_LENGTH; k++) {
drivers/scsi/FlashPoint.c
6325
FPT_scamInfo[match].id_string[k] =
drivers/scsi/FlashPoint.c
6326
p_id_string[k];
drivers/scsi/FlashPoint.c
6361
unsigned char i, k, max_id;
drivers/scsi/FlashPoint.c
6380
for (k = 0; k < ID_STRING_LENGTH; k += 2) {
drivers/scsi/FlashPoint.c
6381
ee_data = FPT_scamInfo[i].id_string[k + 1];
drivers/scsi/FlashPoint.c
6383
ee_data |= FPT_scamInfo[i].id_string[k];
drivers/scsi/FlashPoint.c
6388
((unsigned short)ID_STRING_LENGTH / 2)) + (unsigned short)(k / 2)));
drivers/scsi/advansys.c
2434
int k;
drivers/scsi/advansys.c
2442
if ((k = (l - i) / 4) >= 8) {
drivers/scsi/advansys.c
2443
k = 8;
drivers/scsi/advansys.c
2449
for (j = 0; j < k; j++) {
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
153
u_int k = 0;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
161
for (k = start_addr; k < count + start_addr; k++) {
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
171
if ((k & (1 << i)) != 0)
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
177
if ((k & (1 << i)) != 0)
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
198
buf[k - start_addr] = v;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
205
for (k = 0; k < count; k = k + 1) {
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
206
if (((k % 8) == 0) && (k != 0)) {
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
209
printk(KERN_CONT " 0x%x", buf[k]);
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
227
int i, k;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
247
for (k = start_addr; k < count + start_addr; k++) {
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
253
if ((k & (1 << i)) != 0)
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
259
if ((k & (1 << i)) != 0)
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
264
v = buf[k - start_addr];
drivers/scsi/aic94xx/aic94xx_hwi.c
1334
int num = 0, k;
drivers/scsi/aic94xx/aic94xx_hwi.c
1348
k = num;
drivers/scsi/aic94xx/aic94xx_hwi.c
1349
ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL);
drivers/scsi/aic94xx/aic94xx_hwi.c
1354
num -= k;
drivers/scsi/aic94xx/aic94xx_hwi.c
1362
k = asd_post_ascb_list(asd_ha, ascb_list, num);
drivers/scsi/aic94xx/aic94xx_hwi.c
1363
if (k)
drivers/scsi/aic94xx/aic94xx_hwi.c
1366
return k;
drivers/scsi/aic94xx/aic94xx_hwi.c
338
int i, k, z = 0;
drivers/scsi/aic94xx/aic94xx_hwi.c
348
for (k = 0; k < ASD_EDBS_PER_SCB; k++) {
drivers/scsi/aic94xx/aic94xx_hwi.c
349
struct sg_el *eb = &escb->eb[k];
drivers/scsi/aic94xx/aic94xx_scb.c
115
int i, k = 0;
drivers/scsi/aic94xx/aic94xx_scb.c
119
return k;
drivers/scsi/aic94xx/aic94xx_scb.c
120
k++;
drivers/scsi/atp870u.c
1017
unsigned char i, j, k;
drivers/scsi/atp870u.c
1067
k = (i & 0x07) | 0x40;
drivers/scsi/atp870u.c
1069
k = i;
drivers/scsi/atp870u.c
1071
atp_writeb_io(dev, 0, 0x15, k);
drivers/scsi/atp870u.c
1081
k = atp_readb_io(dev, 0, 0x17);
drivers/scsi/atp870u.c
1082
if ((k == 0x85) || (k == 0x42))
drivers/scsi/atp870u.c
1084
if (k != 0x16)
drivers/scsi/atp870u.c
1086
} while (k != 0x16);
drivers/scsi/atp870u.c
1087
if ((k == 0x85) || (k == 0x42))
drivers/scsi/atp870u.c
1166
k = fun_scam(dev, &val);
drivers/scsi/atp870u.c
1167
if ((k & 0x03) == 0)
drivers/scsi/atp870u.c
1171
if ((k & 0x02) != 0)
drivers/scsi/atp870u.c
1189
k = mbuf[1];
drivers/scsi/atp870u.c
1192
m <<= k;
drivers/scsi/atp870u.c
1195
if (k > 0)
drivers/scsi/atp870u.c
1196
k--;
drivers/scsi/atp870u.c
1202
k = i; /* max acceptable ID# */
drivers/scsi/atp870u.c
1205
m <<= k;
drivers/scsi/atp870u.c
1208
if (k > 0)
drivers/scsi/atp870u.c
1209
k--;
drivers/scsi/atp870u.c
1216
if (k < 8) {
drivers/scsi/atp870u.c
1221
k &= 0x07;
drivers/scsi/atp870u.c
1222
quintet[1] = g2q_tab[k];
drivers/scsi/atp870u.c
1239
int j, k;
drivers/scsi/atp870u.c
1241
for (k = 0; k < 16; k++) {
drivers/scsi/atp870u.c
1242
if (!atp_dev->id[j][k].prd_table)
drivers/scsi/atp870u.c
1245
atp_dev->id[j][k].prd_table,
drivers/scsi/atp870u.c
1246
atp_dev->id[j][k].prd_bus);
drivers/scsi/atp870u.c
1247
atp_dev->id[j][k].prd_table = NULL;
drivers/scsi/atp870u.c
1255
int c,k;
drivers/scsi/atp870u.c
1257
for(k=0;k<16;k++) {
drivers/scsi/atp870u.c
1258
atp_dev->id[c][k].prd_table =
drivers/scsi/atp870u.c
126
unsigned long adrcnt, k;
drivers/scsi/atp870u.c
1260
&(atp_dev->id[c][k].prd_bus),
drivers/scsi/atp870u.c
1262
if (!atp_dev->id[c][k].prd_table) {
drivers/scsi/atp870u.c
1267
atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
drivers/scsi/atp870u.c
1268
atp_dev->id[c][k].devsp=0x20;
drivers/scsi/atp870u.c
1269
atp_dev->id[c][k].devtype = 0x7f;
drivers/scsi/atp870u.c
1270
atp_dev->id[c][k].curr_req = NULL;
drivers/scsi/atp870u.c
1282
for (k = 0; k < qcnt; k++) {
drivers/scsi/atp870u.c
1283
atp_dev->quereq[c][k] = NULL;
drivers/scsi/atp870u.c
1285
for (k = 0; k < 16; k++) {
drivers/scsi/atp870u.c
1286
atp_dev->id[c][k].curr_req = NULL;
drivers/scsi/atp870u.c
1287
atp_dev->sp[c][k] = 0x04;
drivers/scsi/atp870u.c
1309
unsigned char k, host_id;
drivers/scsi/atp870u.c
1340
k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10;
drivers/scsi/atp870u.c
1341
atp_writeb_base(atpdev, 0x3a, k);
drivers/scsi/atp870u.c
1342
atp_writeb_base(atpdev, 0x3a, k & 0xdf);
drivers/scsi/atp870u.c
1344
atp_writeb_base(atpdev, 0x3a, k);
drivers/scsi/atp870u.c
1361
unsigned char k, m, host_id;
drivers/scsi/atp870u.c
1414
for (k = 0; k < 16; k++) {
drivers/scsi/atp870u.c
1415
n = 1 << k;
drivers/scsi/atp870u.c
1416
if (atpdev->sp[0][k] > 1)
drivers/scsi/atp870u.c
1419
if (atpdev->sp[0][k] == 0)
drivers/scsi/atp870u.c
1425
k = atp_readb_base(atpdev, 0x38) & 0x80;
drivers/scsi/atp870u.c
1426
atp_writeb_base(atpdev, 0x38, k);
drivers/scsi/atp870u.c
1447
unsigned char k, m, c;
drivers/scsi/atp870u.c
1470
for (k = 0; k < 4; k++) {
drivers/scsi/atp870u.c
1472
((u32 *)&setupdata[m][0])[k] =
drivers/scsi/atp870u.c
1475
for (k = 0; k < 4; k++) {
drivers/scsi/atp870u.c
1477
((u32 *)&atpdev->sp[m][0])[k] =
drivers/scsi/atp870u.c
1488
for (k = 0; k < 16; k++) {
drivers/scsi/atp870u.c
1489
n = 1 << k;
drivers/scsi/atp870u.c
1490
if (atpdev->sp[c][k] > 1)
drivers/scsi/atp870u.c
1493
if (atpdev->sp[c][k] == 0)
drivers/scsi/atp870u.c
1499
k = setupdata[c][1];
drivers/scsi/atp870u.c
1500
if ((k & 0x40) != 0)
drivers/scsi/atp870u.c
1502
k &= 0x07;
drivers/scsi/atp870u.c
1503
atpdev->global_map[c] |= k;
drivers/scsi/atp870u.c
1510
k = atp_readb_base(atpdev, 0x28) & 0x8f;
drivers/scsi/atp870u.c
1511
k |= 0x10;
drivers/scsi/atp870u.c
1512
atp_writeb_base(atpdev, 0x28, k);
drivers/scsi/atp870u.c
1524
k = atpdev->host_id[0];
drivers/scsi/atp870u.c
1525
if (k > 7)
drivers/scsi/atp870u.c
1526
k = (k & 0x07) | 0x40;
drivers/scsi/atp870u.c
1527
atp_set_host_id(atpdev, 0, k);
drivers/scsi/atp870u.c
1529
k = atpdev->host_id[1];
drivers/scsi/atp870u.c
1530
if (k > 7)
drivers/scsi/atp870u.c
1531
k = (k & 0x07) | 0x40;
drivers/scsi/atp870u.c
1532
atp_set_host_id(atpdev, 1, k);
drivers/scsi/atp870u.c
154
for (k=0; k < 1000; k++) {
drivers/scsi/atp870u.c
1541
k = atp_readb_base(atpdev, 0x28) & 0xcf;
drivers/scsi/atp870u.c
1542
k |= 0xc0;
drivers/scsi/atp870u.c
1543
atp_writeb_base(atpdev, 0x28, k);
drivers/scsi/atp870u.c
1544
k = atp_readb_base(atpdev, 0x1f) | 0x80;
drivers/scsi/atp870u.c
1545
atp_writeb_base(atpdev, 0x1f, k);
drivers/scsi/atp870u.c
1546
k = atp_readb_base(atpdev, 0x29) | 0x01;
drivers/scsi/atp870u.c
1547
atp_writeb_base(atpdev, 0x29, k);
drivers/scsi/atp870u.c
1645
unsigned char j, k, c;
drivers/scsi/atp870u.c
1667
for (k=0; k < workrequ->cmd_len; k++) {
drivers/scsi/atp870u.c
1668
printk(" %2x ",workrequ->cmnd[k]);
drivers/scsi/atp870u.c
1774
unsigned char i, j, k, rmb, n;
drivers/scsi/atp870u.c
1877
k = atp_readb_io(dev, c, 0x1f);
drivers/scsi/atp870u.c
1878
if ((k & 0x01) != 0) {
drivers/scsi/atp870u.c
1882
if ((k & 0x80) == 0) {
drivers/scsi/atp870u.c
1996
k = 0;
drivers/scsi/atp870u.c
2000
mbuf[k++] = atp_readb_io(dev, c, 0x19);
drivers/scsi/atp870u.c
204
k = dev->id[c][target_id].last_len;
drivers/scsi/atp870u.c
205
k -= adrcnt;
drivers/scsi/atp870u.c
206
dev->id[c][target_id].tran_len = k;
drivers/scsi/atp870u.c
2122
k = 0;
drivers/scsi/atp870u.c
2126
mbuf[k++] = atp_readb_io(dev, c, 0x19);
drivers/scsi/atp870u.c
2290
k = 0;
drivers/scsi/atp870u.c
2294
mbuf[k++] = atp_readb_io(dev, c, 0x19);
drivers/scsi/atp870u.c
265
k = dev->id[c][target_id].last_len;
drivers/scsi/atp870u.c
266
k -= adrcnt;
drivers/scsi/atp870u.c
267
dev->id[c][target_id].tran_len = k;
drivers/scsi/atp870u.c
305
k = dev->id[c][target_id].last_len;
drivers/scsi/atp870u.c
306
k -= adrcnt;
drivers/scsi/atp870u.c
307
dev->id[c][target_id].tran_len = k;
drivers/scsi/atp870u.c
357
k = dev->id[c][target_id].last_len;
drivers/scsi/atp870u.c
359
atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]);
drivers/scsi/atp870u.c
360
atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]);
drivers/scsi/atp870u.c
361
atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]);
drivers/scsi/atp870u.c
363
printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k,
drivers/scsi/atp870u.c
437
k = 0x10000;
drivers/scsi/atp870u.c
439
k = id;
drivers/scsi/atp870u.c
441
if (k > adrcnt) {
drivers/scsi/atp870u.c
443
(unsigned short int)(k - adrcnt);
drivers/scsi/atp870u.c
448
adrcnt -= k;
drivers/scsi/atp870u.c
562
k = dev->id[c][target_id].last_len;
drivers/scsi/atp870u.c
564
((unsigned char *) (&k))[2]);
drivers/scsi/atp870u.c
566
((unsigned char *) (&k))[1]);
drivers/scsi/atp870u.c
568
((unsigned char *) (&k))[0]);
drivers/scsi/atp870u.c
584
k = dev->id[c][target_id].last_len;
drivers/scsi/atp870u.c
586
((unsigned char *) (&k))[2]);
drivers/scsi/atp870u.c
588
((unsigned char *) (&k))[1]);
drivers/scsi/atp870u.c
590
((unsigned char *) (&k))[0]);
drivers/scsi/atp870u.c
983
unsigned short int i, k;
drivers/scsi/atp870u.c
988
k = atp_readw_io(dev, 0, 0x1c);
drivers/scsi/atp870u.c
989
j = (unsigned char) (k >> 8);
drivers/scsi/atp870u.c
990
if ((k & 0x8000) != 0) /* DB7 all release? */
drivers/scsi/bfa/bfa_fcpim.h
313
uint16_t k = (__ioim)->iotag >> BFA_IOIM_RETRY_TAG_OFFSET; \
drivers/scsi/bfa/bfa_fcpim.h
314
k++; (__ioim)->iotag &= BFA_IOIM_IOTAG_MASK; \
drivers/scsi/bfa/bfa_fcpim.h
315
(__ioim)->iotag |= k << BFA_IOIM_RETRY_TAG_OFFSET; \
drivers/scsi/bfa/bfa_fcpim.h
321
uint16_t k = ioim->iotag >> BFA_IOIM_RETRY_TAG_OFFSET;
drivers/scsi/bfa/bfa_fcpim.h
322
if (k < BFA_IOIM_RETRY_MAX)
drivers/scsi/bfa/bfa_fcs_lport.c
1258
u8 k = 0;
drivers/scsi/bfa/bfa_fcs_lport.c
1270
port->port_topo.ploop.alpa_pos_map[k] =
drivers/scsi/bfa/bfa_fcs_lport.c
1272
k++;
drivers/scsi/bfa/bfa_fcs_lport.c
1273
bfa_trc(port->fcs->bfa, k);
drivers/scsi/bfa/bfa_fcs_lport.c
1275
port->port_topo.ploop.alpa_pos_map[k]);
drivers/scsi/bfa/bfa_fcs_lport.c
1279
port->port_topo.ploop.num_alpa = k;
drivers/scsi/constants.c
265
int arr_sz, k;
drivers/scsi/constants.c
284
for (k = 0; k < arr_sz; ++k, ++arr) {
drivers/scsi/constants.c
288
if (k < arr_sz)
drivers/scsi/constants.c
436
int k;
drivers/scsi/constants.c
438
for (k = 0; k < ARRAY_SIZE(scsi_mlreturn_arr); ++k, ++arr) {
drivers/scsi/csiostor/csio_hw.c
2246
int k, int c)
drivers/scsi/csiostor/csio_hw.c
2255
if (k > c) {
drivers/scsi/csiostor/csio_hw.c
2267
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
drivers/scsi/csiostor/csio_hw.c
2268
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
drivers/scsi/csiostor/csio_hw.c
2370
uint32_t d, c, k;
drivers/scsi/csiostor/csio_hw.c
2374
k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
drivers/scsi/csiostor/csio_hw.c
2385
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
drivers/scsi/csiostor/csio_hw.c
2386
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
drivers/scsi/csiostor/csio_init.c
335
int i, j, idx, k = 0;
drivers/scsi/csiostor/csio_init.c
407
k = j % info->max_cpus;
drivers/scsi/csiostor/csio_init.c
408
orig = &hw->sqset[i][k];
drivers/scsi/csiostor/csio_isr.c
356
int k = CSIO_EXTRA_VECS;
drivers/scsi/csiostor/csio_isr.c
358
int cnt = hw->num_sqsets + k;
drivers/scsi/csiostor/csio_isr.c
372
for (i = k; i < cnt; i++, entryp++) {
drivers/scsi/csiostor/csio_isr.c
383
int rv, i, j, k = 0;
drivers/scsi/csiostor/csio_isr.c
403
rv = request_irq(pci_irq_vector(pdev, k), csio_nondata_isr, 0,
drivers/scsi/csiostor/csio_isr.c
404
entryp[k].desc, hw);
drivers/scsi/csiostor/csio_isr.c
407
pci_irq_vector(pdev, k), rv);
drivers/scsi/csiostor/csio_isr.c
411
entryp[k++].dev_id = hw;
drivers/scsi/csiostor/csio_isr.c
413
rv = request_irq(pci_irq_vector(pdev, k), csio_fwevt_isr, 0,
drivers/scsi/csiostor/csio_isr.c
414
entryp[k].desc, hw);
drivers/scsi/csiostor/csio_isr.c
417
pci_irq_vector(pdev, k), rv);
drivers/scsi/csiostor/csio_isr.c
421
entryp[k++].dev_id = (void *)hw;
drivers/scsi/csiostor/csio_isr.c
426
for (j = 0; j < info->max_cpus; j++, k++) {
drivers/scsi/csiostor/csio_isr.c
430
rv = request_irq(pci_irq_vector(pdev, k), csio_scsi_isr, 0,
drivers/scsi/csiostor/csio_isr.c
431
entryp[k].desc, q);
drivers/scsi/csiostor/csio_isr.c
435
pci_irq_vector(pdev, k), rv);
drivers/scsi/csiostor/csio_isr.c
439
entryp[k].dev_id = q;
drivers/scsi/csiostor/csio_isr.c
449
for (i = 0; i < k; i++)
drivers/scsi/csiostor/csio_isr.c
499
int i, j, k, n, min, cnt;
drivers/scsi/csiostor/csio_isr.c
531
k = 0;
drivers/scsi/csiostor/csio_isr.c
532
csio_set_nondata_intr_idx(hw, k);
drivers/scsi/csiostor/csio_isr.c
533
csio_set_mb_intr_idx(csio_hw_to_mbm(hw), k++);
drivers/scsi/csiostor/csio_isr.c
534
csio_set_fwevt_intr_idx(hw, k++);
drivers/scsi/csiostor/csio_isr.c
540
n = (j % info->max_cpus) + k;
drivers/scsi/csiostor/csio_isr.c
544
k += info->max_cpus;
drivers/scsi/device_handler/scsi_dh_alua.c
539
int len, k, off, bufflen = ALUA_RTPG_SIZE;
drivers/scsi/device_handler/scsi_dh_alua.c
681
for (k = tpg_desc_tbl_off, desc = buff + tpg_desc_tbl_off;
drivers/scsi/device_handler/scsi_dh_alua.c
682
k < len;
drivers/scsi/device_handler/scsi_dh_alua.c
683
k += off, desc += off) {
drivers/scsi/esas2r/esas2r_ioctl.c
1313
int i = 0, k = 0;
drivers/scsi/esas2r/esas2r_ioctl.c
1320
ioctl->data.chanlist.channel[k] = i;
drivers/scsi/esas2r/esas2r_ioctl.c
1321
k++;
drivers/scsi/imm.c
1023
int loop, old_mode, status, k, ppb = dev->base;
drivers/scsi/imm.c
1064
k = 1000000; /* 1 Second */
drivers/scsi/imm.c
1067
k--;
drivers/scsi/imm.c
1069
} while (!(l & 0x80) && (k));
drivers/scsi/imm.c
180
int k;
drivers/scsi/imm.c
186
k = IMM_SPIN_TMO;
drivers/scsi/imm.c
189
k--;
drivers/scsi/imm.c
192
while (!(r & 0x80) && (k));
drivers/scsi/imm.c
214
if (k)
drivers/scsi/imm.c
542
int k;
drivers/scsi/imm.c
551
k = IMM_SELECT_TMO;
drivers/scsi/imm.c
553
k--;
drivers/scsi/imm.c
554
} while ((r_str(ppb) & 0x08) && (k));
drivers/scsi/imm.c
556
if (!k)
drivers/scsi/imm.c
576
k = IMM_SELECT_TMO;
drivers/scsi/imm.c
578
k--;
drivers/scsi/imm.c
580
while (!(r_str(ppb) & 0x08) && (k));
drivers/scsi/imm.c
586
return (k) ? 1 : 0;
drivers/scsi/imm.c
618
int k;
drivers/scsi/imm.c
621
for (k = 0; k < cmd->cmd_len; k += 2)
drivers/scsi/imm.c
622
if (!imm_out(dev, &cmd->cmnd[k], 2))
drivers/scsi/lpfc/lpfc_attr.c
302
int len = 0, i, j, k, cpu;
drivers/scsi/lpfc/lpfc_attr.c
374
for (j = 0, k = 0; j < strlen(vmp->host_vmid); j++, k += 3)
drivers/scsi/lpfc/lpfc_attr.c
375
sprintf((char *)(hxstr + k), "%2x ", vmp->host_vmid[j]);
drivers/scsi/lpfc/lpfc_hbadisc.c
3561
int numalpa, j, k;
drivers/scsi/lpfc/lpfc_hbadisc.c
3575
for (k = 1; j < numalpa; k++) {
drivers/scsi/lpfc/lpfc_hbadisc.c
3576
un.pamap[k - 1] =
drivers/scsi/lpfc/lpfc_hbadisc.c
3579
if (k == 16)
drivers/scsi/lpfc/lpfc_sli.c
6423
uint16_t rsrc_id, rsrc_start, j, k;
drivers/scsi/lpfc/lpfc_sli.c
6601
for (i = 0, j = 0, k = 0; i < rsrc_cnt; i++) {
drivers/scsi/lpfc/lpfc_sli.c
6604
&id_array[k]);
drivers/scsi/lpfc/lpfc_sli.c
6607
&id_array[k]);
drivers/scsi/lpfc/lpfc_sli.c
6632
k++;
drivers/scsi/megaraid/megaraid_sas_fusion.c
787
int i, j, k, msix_count;
drivers/scsi/megaraid/megaraid_sas_fusion.c
886
for (k = 0; k < dma_alloc_count; k++) {
drivers/scsi/megaraid/megaraid_sas_fusion.c
888
abs_index = (k * RDPQ_MAX_INDEX_IN_ONE_CHUNK) + i;
drivers/scsi/megaraid/megaraid_sas_fusion.c
894
cpu_to_le64(rdpq_chunk_phys[k] + offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
896
rdpq_chunk_phys[k] + offset;
drivers/scsi/megaraid/megaraid_sas_fusion.c
898
(union MPI2_REPLY_DESCRIPTORS_UNION *)((u8 *)rdpq_chunk_virt[k] + offset);
drivers/scsi/ppa.c
191
int k;
drivers/scsi/ppa.c
195
k = PPA_SPIN_TMO;
drivers/scsi/ppa.c
197
for (r = r_str(ppb); ((r & 0xc0) != 0xc0) && (k); k--) {
drivers/scsi/ppa.c
209
if (k)
drivers/scsi/ppa.c
425
int k;
drivers/scsi/ppa.c
432
k = PPA_SELECT_TMO;
drivers/scsi/ppa.c
434
k--;
drivers/scsi/ppa.c
436
} while ((r_str(ppb) & 0x40) && (k));
drivers/scsi/ppa.c
437
if (!k)
drivers/scsi/ppa.c
446
k = PPA_SELECT_TMO;
drivers/scsi/ppa.c
448
k--;
drivers/scsi/ppa.c
451
while (!(r_str(ppb) & 0x40) && (k));
drivers/scsi/ppa.c
452
if (!k)
drivers/scsi/ppa.c
521
int k;
drivers/scsi/ppa.c
525
for (k = 0; k < cmd->cmd_len; k++)
drivers/scsi/ppa.c
526
if (!ppa_out(dev, &cmd->cmnd[k], 1))
drivers/scsi/ppa.c
591
unsigned long k = dev->recon_tmo;
drivers/scsi/ppa.c
592
for (; k && ((r = (r_str(ppb) & 0xf0)) & 0xc0) != 0xc0;
drivers/scsi/ppa.c
593
k--)
drivers/scsi/ppa.c
596
if (!k)
drivers/scsi/ppa.c
912
int loop, old_mode, status, k, ppb = dev->base;
drivers/scsi/ppa.c
954
k = 1000000; /* 1 Second */
drivers/scsi/ppa.c
957
k--;
drivers/scsi/ppa.c
959
} while (!(l & 0x80) && (k));
drivers/scsi/qla2xxx/qla_gs.c
3158
int k;
drivers/scsi/qla2xxx/qla_gs.c
3168
for (k = i + 1; k < vha->hw->max_fibre_devices; k++) {
drivers/scsi/qla2xxx/qla_gs.c
3169
trp = &vha->scan.l[k];
drivers/scsi/qla2xxx/qla_gs.c
3339
int i, j, k;
drivers/scsi/qla2xxx/qla_gs.c
3370
for (k = 0; k < num_fibre_dev; k++) {
drivers/scsi/qla2xxx/qla_gs.c
3371
rp = &vha->scan.l[k];
drivers/scsi/qla2xxx/qla_gs.c
3382
for (k = 0; k < num_fibre_dev; k++) {
drivers/scsi/qla2xxx/qla_gs.c
3383
rp = &vha->scan.l[k];
drivers/scsi/qla2xxx/qla_gs.c
3396
for (k = 0; k < num_fibre_dev; k++) {
drivers/scsi/qla2xxx/qla_gs.c
3397
rp = &vha->scan.l[k];
drivers/scsi/qla2xxx/qla_gs.c
3410
for (k = 0; k < num_fibre_dev; k++) {
drivers/scsi/qla2xxx/qla_gs.c
3411
rp = &vha->scan.l[k];
drivers/scsi/qla2xxx/qla_isr.c
3099
uint32_t i, j = 0, k = 0, num_ent;
drivers/scsi/qla2xxx/qla_isr.c
3107
if (k + num_ent < blocks_done) {
drivers/scsi/qla2xxx/qla_isr.c
3108
k += num_ent;
drivers/scsi/qla2xxx/qla_isr.c
3111
j = blocks_done - k - 1;
drivers/scsi/qla2xxx/qla_isr.c
3112
k = blocks_done;
drivers/scsi/qla2xxx/qla_isr.c
3116
if (k != blocks_done) {
drivers/scsi/qla2xxx/qla_nx.c
1419
int i, j = 0, k, start, end, loop, sz[2], off0[2];
drivers/scsi/qla2xxx/qla_nx.c
1470
for (k = start; k <= end; k++) {
drivers/scsi/qla2xxx/qla_nx.c
1472
mem_crb + MIU_TEST_AGT_RDDATA(k));
drivers/scsi/qla2xxx/qla_nx.c
1473
word[i] |= ((uint64_t)temp << (32 * (k & 1)));
drivers/scsi/qla2xxx/qla_nx.c
3815
uint32_t i, k, loop_count, t_value, r_cnt, r_value;
drivers/scsi/qla2xxx/qla_nx.c
3857
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla2xxx/qla_nx.c
3874
uint32_t i, k, loop_count, t_value, r_cnt, r_value;
drivers/scsi/qla2xxx/qla_nx.c
3893
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla2xxx/qla_nx.c
3910
uint32_t i, k, loop_cnt;
drivers/scsi/qla2xxx/qla_nx.c
3923
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla2xxx/qla_nx.c
4267
int i, k;
drivers/scsi/qla2xxx/qla_nx.c
4279
for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
drivers/scsi/qla2xxx/qla_nx.c
4281
ha->md_dump_size += tmplt_hdr->capture_size_array[k];
drivers/scsi/qla2xxx/qla_nx2.c
2464
uint32_t i, k, loop_count, t_value, r_cnt, r_value;
drivers/scsi/qla2xxx/qla_nx2.c
2505
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla2xxx/qla_nx2.c
2521
uint32_t i, k, loop_count, t_value, r_cnt, r_value;
drivers/scsi/qla2xxx/qla_nx2.c
2540
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla2xxx/qla_nx2.c
2616
uint32_t i, k, loop_cnt;
drivers/scsi/qla2xxx/qla_nx2.c
2630
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla4xxx/ql4_init.c
308
int hdr_entry_bit, k;
drivers/scsi/qla4xxx/ql4_init.c
375
for (hdr_entry_bit = 0x2, k = 1; (hdr_entry_bit & 0xFF);
drivers/scsi/qla4xxx/ql4_init.c
376
hdr_entry_bit <<= 1, k++) {
drivers/scsi/qla4xxx/ql4_init.c
378
ha->fw_dump_size += md_hdr->capture_size_array[k];
drivers/scsi/qla4xxx/ql4_nx.c
1350
int i, j = 0, k, start, end, loop, sz[2], off0[2];
drivers/scsi/qla4xxx/ql4_nx.c
1403
for (k = start; k <= end; k++) {
drivers/scsi/qla4xxx/ql4_nx.c
1405
mem_crb + MIU_TEST_AGT_RDDATA(k));
drivers/scsi/qla4xxx/ql4_nx.c
1406
word[i] |= ((uint64_t)temp << (32 * (k & 1)));
drivers/scsi/qla4xxx/ql4_nx.c
2132
uint32_t i, k, loop_count, t_value, r_cnt, r_value;
drivers/scsi/qla4xxx/ql4_nx.c
2174
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla4xxx/ql4_nx.c
2362
uint32_t i, k, loop_count, t_value, r_cnt, r_value;
drivers/scsi/qla4xxx/ql4_nx.c
2381
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qla4xxx/ql4_nx.c
2397
uint32_t i, k, loop_cnt;
drivers/scsi/qla4xxx/ql4_nx.c
2411
for (k = 0; k < r_cnt; k++) {
drivers/scsi/qlogicfas408.c
188
int k;
drivers/scsi/qlogicfas408.c
192
k = 0;
drivers/scsi/qlogicfas408.c
195
!((k = inb(qbase + 4)) & 0xe0)) {
drivers/scsi/qlogicfas408.c
203
if (k & 0x60)
drivers/scsi/qlogicfas408.c
205
if (k & 0x20)
drivers/scsi/qlogicfas408.c
207
if (k & 0x40)
drivers/scsi/qlogicfas408.c
267
unsigned long k;
drivers/scsi/qlogicfas408.c
338
if ((k = ql_wai(priv))) {
drivers/scsi/qlogicfas408.c
339
set_host_byte(cmd, k);
drivers/scsi/qlogicfas408.c
342
k = inb(qbase + 5); /* should be 0x10, bus service */
drivers/scsi/qlogicfas408.c
349
k = jiffies + WATCHDOG;
drivers/scsi/qlogicfas408.c
351
while (time_before(jiffies, k) && !priv->qabort &&
drivers/scsi/qlogicfas408.c
355
if (time_after_eq(jiffies, k)) {
drivers/scsi/qlogicfas408.c
372
if ((k = ql_wai(priv))) {
drivers/scsi/qlogicfas408.c
373
set_host_byte(cmd, k);
drivers/scsi/qlogicfas408.c
391
if ((k = ql_wai(priv))) {
drivers/scsi/qlogicfas408.c
392
set_host_byte(cmd, k);
drivers/scsi/scsi_common.c
251
int add_sen_len, add_len, desc_len, k;
drivers/scsi/scsi_common.c
261
for (desc_len = 0, k = 0; k < add_sen_len; k += desc_len) {
drivers/scsi/scsi_common.c
263
add_len = (k < (add_sen_len - 1)) ? descp[1]: -1;
drivers/scsi/scsi_debug.c
1533
int k;
drivers/scsi/scsi_debug.c
1535
k = find_first_bit(devip->uas_bm, SDEBUG_NUM_UAS);
drivers/scsi/scsi_debug.c
1536
if (k != SDEBUG_NUM_UAS) {
drivers/scsi/scsi_debug.c
1539
switch (k) {
drivers/scsi/scsi_debug.c
1608
pr_warn("unexpected unit attention code=%d\n", k);
drivers/scsi/scsi_debug.c
1613
clear_bit(k, devip->uas_bm);
drivers/scsi/scsi_debug.c
2492
int k, offset, len, errsts, bump, na;
drivers/scsi/scsi_debug.c
2539
for (k = 0, oip = oip->arrp; k < na; ++k, ++oip) {
drivers/scsi/scsi_debug.c
2590
for (k = 0, oip = oip->arrp; k < na;
drivers/scsi/scsi_debug.c
2591
++k, ++oip) {
drivers/scsi/scsi_debug.c
2596
supp = (k >= na) ? 1 : 3;
drivers/scsi/scsi_debug.c
2599
for (k = 0, oip = oip->arrp; k < na;
drivers/scsi/scsi_debug.c
2600
++k, ++oip) {
drivers/scsi/scsi_debug.c
2605
supp = (k >= na) ? 1 : 3;
drivers/scsi/scsi_debug.c
2612
for (k = 1; k < u; ++k)
drivers/scsi/scsi_debug.c
2613
arr[4 + k] = (k < 16) ?
drivers/scsi/scsi_debug.c
2614
oip->len_mask[k] : 0xff;
drivers/scsi/scsi_debug.c
5088
u16 lbdof, num_lrd, k;
drivers/scsi/scsi_debug.c
5160
for (k = 0, up = lrdp + lrd_size; k < num_lrd; ++k, up += lrd_size) {
drivers/scsi/scsi_debug.c
5166
my_name, k, lba, num, sg_off);
drivers/scsi/scsi_debug.c
5734
int k, j, n, res;
drivers/scsi/scsi_debug.c
5782
for (k = 0, j = 0, res = 0; true; ++k, j = 0) {
drivers/scsi/scsi_debug.c
5785
if (k == 0) {
drivers/scsi/scsi_debug.c
5791
if ((k * RL_BUCKET_ELEMS) + j > lun_cnt)
drivers/scsi/scsi_debug.c
6992
int k = 0;
drivers/scsi/scsi_debug.c
7003
++k;
drivers/scsi/scsi_debug.c
7009
"%d device(s) found in target\n", k);
drivers/scsi/scsi_debug.c
7025
int k = 0;
drivers/scsi/scsi_debug.c
7036
++k;
drivers/scsi/scsi_debug.c
7041
"%d device(s) found in host\n", k);
drivers/scsi/scsi_debug.c
7049
int k = 0;
drivers/scsi/scsi_debug.c
7061
++k;
drivers/scsi/scsi_debug.c
7068
"%d device(s) found\n", k);
drivers/scsi/scsi_debug.c
7076
int sectors_per_part, num_sectors, k;
drivers/scsi/scsi_debug.c
7092
for (k = 1; k < sdebug_num_parts; ++k) {
drivers/scsi/scsi_debug.c
7093
starts[k] = ((k * sectors_per_part) / heads_by_sects)
drivers/scsi/scsi_debug.c
7095
if (starts[k] - starts[k - 1] < max_part_secs)
drivers/scsi/scsi_debug.c
7096
max_part_secs = starts[k] - starts[k - 1];
drivers/scsi/scsi_debug.c
7104
for (k = 0; starts[k + 1]; ++k, ++pp) {
drivers/scsi/scsi_debug.c
7105
start_sec = starts[k];
drivers/scsi/scsi_debug.c
7106
end_sec = starts[k] + max_part_secs - 1;
drivers/scsi/scsi_debug.c
7502
int k;
drivers/scsi/scsi_debug.c
7504
k = scnprintf(sdebug_info, SDEBUG_INFO_LEN, "%s: version %s [%s]\n",
drivers/scsi/scsi_debug.c
7506
if (k >= (SDEBUG_INFO_LEN - 1))
drivers/scsi/scsi_debug.c
7508
scnprintf(sdebug_info + k, SDEBUG_INFO_LEN - k,
drivers/scsi/scsi_debug.c
8487
int k, ret, hosts_to_add;
drivers/scsi/scsi_debug.c
8591
k = sdeb_zbc_model_str(sdeb_zbc_model_s);
drivers/scsi/scsi_debug.c
8592
if (k < 0)
drivers/scsi/scsi_debug.c
8593
return k;
drivers/scsi/scsi_debug.c
8594
sdeb_zbc_model = k;
drivers/scsi/scsi_debug.c
8687
for (k = 0; k < hosts_to_add; k++) {
drivers/scsi/scsi_debug.c
8688
if (want_store && k == 0) {
drivers/scsi/scsi_debug.c
8692
k, -ret);
drivers/scsi/scsi_debug.c
8699
pr_err("add_host k=%d error=%d\n", k, -ret);
drivers/scsi/scsi_debug.c
8720
int k = sdebug_num_hosts;
drivers/scsi/scsi_debug.c
8722
for (; k; k--)
drivers/scsi/scsi_debug.c
8864
int k, devs_per_host, idx;
drivers/scsi/scsi_debug.c
8880
for (k = 0; k < devs_per_host; k++) {
drivers/scsi/scsi_debug.c
9316
int k, na;
drivers/scsi/scsi_debug.c
9345
for (k = 0, n = 0; k < len && n < sb; ++k)
drivers/scsi/scsi_debug.c
9347
(u32)cmd[k]);
drivers/scsi/scsi_debug.c
9401
for (k = 0; k <= na; oip = r_oip->arrp + k++) {
drivers/scsi/scsi_debug.c
9407
for (k = 0; k <= na; oip = r_oip->arrp + k++) {
drivers/scsi/scsi_debug.c
9413
if (k > na) {
drivers/scsi/scsi_debug.c
9439
for (k = 1; k < oip->len_mask[0] && k < 16; ++k) {
drivers/scsi/scsi_debug.c
9440
rem = ~oip->len_mask[k] & cmd[k];
drivers/scsi/scsi_debug.c
9446
mk_sense_invalid_fld(scp, SDEB_IN_CDB, k, j);
drivers/scsi/scsi_logging.c
160
int len, k;
drivers/scsi/scsi_logging.c
170
for (k = 0; k < len; ++k) {
drivers/scsi/scsi_logging.c
174
" %02x", cdb[k]);
drivers/scsi/scsi_logging.c
182
int k;
drivers/scsi/scsi_logging.c
208
for (k = 0; k < cmd->cmd_len; k += 16) {
drivers/scsi/scsi_logging.c
209
size_t linelen = min(cmd->cmd_len - k, 16);
drivers/scsi/scsi_logging.c
216
"CDB[%02x]: ", k);
drivers/scsi/scsi_logging.c
217
hex_dump_to_buffer(&cmd->cmnd[k], linelen,
drivers/scsi/scsi_transport_spi.c
631
int j, k, r, result;
drivers/scsi/scsi_transport_spi.c
649
k = j;
drivers/scsi/scsi_transport_spi.c
652
for ( ; j < min(len, k + 32); j += 2) {
drivers/scsi/scsi_transport_spi.c
657
k = j;
drivers/scsi/scsi_transport_spi.c
660
for ( ; j < min(len, k + 32); j += 2) {
drivers/scsi/scsi_transport_spi.c
665
k = j;
drivers/scsi/scsi_transport_spi.c
667
for ( ; j < min(len, k + 32); j += 4) {
drivers/scsi/sg.c
1223
int k, length;
drivers/scsi/sg.c
1236
for (k = 0; k < rsv_schp->k_use_sg && sa < vma->vm_end; k++) {
drivers/scsi/sg.c
1240
struct page *page = rsv_schp->pages[k] + (offset >> PAGE_SHIFT);
drivers/scsi/sg.c
1262
int k, length;
drivers/scsi/sg.c
1282
for (k = 0; k < rsv_schp->k_use_sg && sa < vma->vm_end; k++) {
drivers/scsi/sg.c
1437
u32 k;
drivers/scsi/sg.c
1463
k = error;
drivers/scsi/sg.c
1466
"sg_alloc: dev=%d \n", k));
drivers/scsi/sg.c
1467
sprintf(sdp->name, "sg%d", k);
drivers/scsi/sg.c
1475
sdp->index = k;
drivers/scsi/sg.c
1867
int ret_sz = 0, i, k, rem_sz, num, mx_sc_elems;
drivers/scsi/sg.c
1900
for (k = 0, rem_sz = blk_size; rem_sz > 0 && k < mx_sc_elems;
drivers/scsi/sg.c
1901
k++, rem_sz -= ret_sz) {
drivers/scsi/sg.c
1906
schp->pages[k] = alloc_pages(gfp_mask, order);
drivers/scsi/sg.c
1907
if (!schp->pages[k])
drivers/scsi/sg.c
1919
k, num, ret_sz));
drivers/scsi/sg.c
1923
schp->k_use_sg = k;
drivers/scsi/sg.c
1926
k, rem_sz));
drivers/scsi/sg.c
1933
for (i = 0; i < k; i++)
drivers/scsi/sg.c
1949
int k;
drivers/scsi/sg.c
1951
for (k = 0; k < schp->k_use_sg && schp->pages[k]; k++) {
drivers/scsi/sg.c
1955
k, schp->pages[k]));
drivers/scsi/sg.c
1956
__free_pages(schp->pages[k], schp->page_order);
drivers/scsi/sg.c
1969
int k, num;
drivers/scsi/sg.c
1978
for (k = 0; k < schp->k_use_sg && schp->pages[k]; k++) {
drivers/scsi/sg.c
1980
if (copy_to_user(outp, page_address(schp->pages[k]),
drivers/scsi/sg.c
1985
if (copy_to_user(outp, page_address(schp->pages[k]),
drivers/scsi/sg.c
2021
int k, num, rem;
drivers/scsi/sg.c
2029
for (k = 0; k < rsv_schp->k_use_sg; k++) {
drivers/scsi/sg.c
2031
req_schp->k_use_sg = k + 1;
drivers/scsi/sg.c
2042
if (k >= rsv_schp->k_use_sg)
drivers/scsi/sg.c
2098
int k;
drivers/scsi/sg.c
2107
for (k = 0; k < SG_MAX_QUEUE; ++k, ++rp) {
drivers/scsi/sg.c
2111
if (k >= SG_MAX_QUEUE)
drivers/scsi/sg.c
2264
int *k = data;
drivers/scsi/sg.c
2266
if (*k < id)
drivers/scsi/sg.c
2267
*k = id;
drivers/scsi/sg.c
2275
int k = -1;
drivers/scsi/sg.c
2279
idr_for_each(&sg_index_idr, sg_idr_max_id, &k);
drivers/scsi/sg.c
2281
return k + 1; /* origin 1 */
drivers/scsi/sg.c
2424
unsigned long k = ULONG_MAX;
drivers/scsi/sg.c
2429
err = kstrtoul_from_user(buffer, count, 0, &k);
drivers/scsi/sg.c
2432
if (k <= 1048576) { /* limit "big buff" to 1 MB */
drivers/scsi/sg.c
2433
sg_big_buff = k;
drivers/scsi/sg.c
2533
int k, new_interface, blen, usg;
drivers/scsi/sg.c
2541
k = 0;
drivers/scsi/sg.c
2543
k++;
drivers/scsi/sg.c
2546
"(res)sgat=%d low_dma=%d\n", k,
drivers/scsi/sg.c
598
int mxsize, cmd_size, k;
drivers/scsi/sg.c
704
k = sg_common_write(sfp, srp, cmnd, sfp->timeout, blocking);
drivers/scsi/sg.c
705
return (k < 0) ? k : count;
drivers/scsi/sg.c
713
int k;
drivers/scsi/sg.c
769
k = sg_common_write(sfp, srp, cmnd, timeout, blocking);
drivers/scsi/sg.c
770
if (k < 0)
drivers/scsi/sg.c
771
return k;
drivers/scsi/sg.c
781
int k, at_head;
drivers/scsi/sg.c
802
k = sg_start_req(srp, cmnd);
drivers/scsi/sg.c
803
if (k) {
drivers/scsi/sg.c
805
"sg_common_write: start_req err=%d\n", k));
drivers/scsi/sg.c
808
return k; /* probably out of space --> ENOMEM */
drivers/scsi/sym53c8xx_2/sym_hipd.c
3276
int i, k;
drivers/scsi/sym53c8xx_2/sym_hipd.c
3297
for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
drivers/scsi/sym53c8xx_2/sym_hipd.c
3298
if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
drivers/scsi/sym53c8xx_2/sym_hipd.c
3433
for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
drivers/scsi/sym53c8xx_2/sym_hipd.c
3434
if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
drivers/scsi/sym53c8xx_2/sym_hipd.c
3435
lun = k;
drivers/sh/clk/cpg.c
237
int k;
drivers/sh/clk/cpg.c
246
for (k = 0; !ret && (k < nr); k++) {
drivers/sh/clk/cpg.c
247
clkp = clks + k;
drivers/sh/clk/cpg.c
252
clkp->freq_table = freq_table + (k * freq_table_size);
drivers/sh/clk/cpg.c
86
int k;
drivers/sh/clk/cpg.c
88
for (k = 0; !ret && (k < nr); k++) {
drivers/sh/clk/cpg.c
89
clkp = clks + k;
drivers/sh/intc/access.c
17
int k;
drivers/sh/intc/access.c
20
for (k = 0; k < d->nr_windows; k++) {
drivers/sh/intc/access.c
21
window = d->window + k;
drivers/sh/intc/access.c
41
unsigned int k;
drivers/sh/intc/access.c
45
for (k = 0; k < d->nr_reg; k++) {
drivers/sh/intc/access.c
46
if (d->reg[k] == address)
drivers/sh/intc/access.c
47
return k;
drivers/sh/intc/core.c
199
unsigned int i, k, smp;
drivers/sh/intc/core.c
224
for (k = 0; k < d->nr_windows; k++) {
drivers/sh/intc/core.c
225
res = desc->resource + k;
drivers/sh/intc/core.c
227
d->window[k].phys = res->start;
drivers/sh/intc/core.c
228
d->window[k].size = resource_size(res);
drivers/sh/intc/core.c
229
d->window[k].virt = ioremap(res->start,
drivers/sh/intc/core.c
231
if (!d->window[k].virt)
drivers/sh/intc/core.c
255
k = 0;
drivers/sh/intc/core.c
260
k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
drivers/sh/intc/core.c
261
k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
drivers/sh/intc/core.c
263
k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
drivers/sh/intc/core.c
275
k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
drivers/sh/intc/core.c
276
k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
drivers/sh/intc/core.c
289
k += save_reg(d, k, hw->sense_regs[i].reg, 0);
drivers/sh/intc/core.c
298
k+= save_reg(d, k, hw->subgroups[i].reg, 0);
drivers/sh/intc/core.c
305
k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
drivers/sh/intc/core.c
317
BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
drivers/sh/intc/core.c
335
for (k = i + 1; k < hw->nr_vectors; k++) {
drivers/sh/intc/core.c
336
struct intc_vect *vect2 = hw->vectors + k;
drivers/sh/intc/core.c
381
for (k = 0; k < d->nr_windows; k++)
drivers/sh/intc/core.c
382
if (d->window[k].virt)
drivers/sh/intc/core.c
383
iounmap(d->window[k].virt);
drivers/sh/maple/maple.c
494
int retval, k, devcheck;
drivers/sh/maple/maple.c
499
for (k = 0; k < 5; k++) {
drivers/sh/maple/maple.c
500
ds.unit = k + 1;
drivers/sh/maple/maple.c
510
mdev_add = maple_alloc_dev(mdev->port, k + 1);
drivers/soc/fsl/qbman/qman_ccsr.c
395
static void qm_set_pfdr_threshold(u32 th, u8 k)
drivers/soc/fsl/qbman/qman_ccsr.c
398
qm_ccsr_out(REG_PFDR_CFG, k);
drivers/soc/fsl/qbman/qman_test_stash.c
111
struct task_struct *k = kthread_run_on_cpu(bstrap_fn, &bstrap,
drivers/soc/fsl/qbman/qman_test_stash.c
115
if (IS_ERR(k))
drivers/soc/fsl/qbman/qman_test_stash.c
125
ret = kthread_stop(k);
drivers/soc/hisilicon/kunpeng_hccs.c
1280
u8 i, j, k;
drivers/soc/hisilicon/kunpeng_hccs.c
1288
for (k = 0; k < die->port_num; k++) {
drivers/soc/hisilicon/kunpeng_hccs.c
1289
port = &die->ports[k];
drivers/soc/hisilicon/kunpeng_hccs.c
1319
u8 i, j, k;
drivers/soc/hisilicon/kunpeng_hccs.c
1327
for (k = 0; k < die->port_num; k++) {
drivers/soc/hisilicon/kunpeng_hccs.c
1328
port = &die->ports[k];
drivers/soc/hisilicon/kunpeng_hccs.c
1705
u8 id, k;
drivers/soc/hisilicon/kunpeng_hccs.c
1725
for (k = 0; k < id; k++)
drivers/soc/hisilicon/kunpeng_hccs.c
1726
hccs_remove_chip_dir(&hdev->chips[k]);
drivers/soc/hisilicon/kunpeng_hccs.c
52
static struct hccs_port_info *kobj_to_port_info(struct kobject *k)
drivers/soc/hisilicon/kunpeng_hccs.c
54
return container_of(k, struct hccs_port_info, kobj);
drivers/soc/hisilicon/kunpeng_hccs.c
57
static struct hccs_die_info *kobj_to_die_info(struct kobject *k)
drivers/soc/hisilicon/kunpeng_hccs.c
59
return container_of(k, struct hccs_die_info, kobj);
drivers/soc/hisilicon/kunpeng_hccs.c
62
static struct hccs_chip_info *kobj_to_chip_info(struct kobject *k)
drivers/soc/hisilicon/kunpeng_hccs.c
64
return container_of(k, struct hccs_chip_info, kobj);
drivers/soc/hisilicon/kunpeng_hccs.c
67
static struct hccs_dev *device_kobj_to_hccs_dev(struct kobject *k)
drivers/soc/hisilicon/kunpeng_hccs.c
69
struct device *dev = container_of(k, struct device, kobj);
drivers/soc/hisilicon/kunpeng_hccs.c
714
u16 i, j, k;
drivers/soc/hisilicon/kunpeng_hccs.c
720
for (k = 0; k < die->port_num; k++) {
drivers/soc/hisilicon/kunpeng_hccs.c
721
port = &die->ports[k];
drivers/soc/hisilicon/kunpeng_hccs.c
898
static ssize_t hccs_show(struct kobject *k, struct attribute *attr, char *buf)
drivers/soc/hisilicon/kunpeng_hccs.c
904
return kobj_attr->show(k, kobj_attr, buf);
drivers/soc/qcom/rpmh-rsc.c
549
int j, k;
drivers/soc/qcom/rpmh-rsc.c
557
for (k = 0; k < msg->num_cmds; k++) {
drivers/soc/qcom/rpmh-rsc.c
558
if (cmd_db_match_resource_addr(msg->cmds[k].addr, addr))
drivers/spi/spi-aspeed-smc.c
1476
int k = j;
drivers/spi/spi-aspeed-smc.c
1478
while (k < cols && buf[i][k])
drivers/spi/spi-aspeed-smc.c
1479
k++;
drivers/spi/spi-aspeed-smc.c
1481
if (k - j > max) {
drivers/spi/spi-aspeed-smc.c
1482
max = k - j;
drivers/spi/spi-aspeed-smc.c
1484
c = j + (k - j) / 2;
drivers/spi/spi-aspeed-smc.c
1487
j = k + 1;
drivers/spi/spi-cadence-xspi.c
966
int k;
drivers/spi/spi-cadence-xspi.c
968
for (k = 0; k < 8; k++) {
drivers/spi/spi-cadence-xspi.c
969
u8 val = bitrev8((ptr[k]));
drivers/spi/spi-cadence-xspi.c
983
int k;
drivers/spi/spi-cadence-xspi.c
985
for (k = 0; k < data_count % MRVL_XFER_QWORD_BYTECOUNT; k++) {
drivers/spi/spi-cadence-xspi.c
986
u8 val = bitrev8((ptr[k]));
drivers/spi/spi-sh-msiof.c
302
unsigned int k;
drivers/spi/spi-sh-msiof.c
304
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
305
sh_msiof_write(p, SITFDR, buf_8[k] << fs);
drivers/spi/spi-sh-msiof.c
313
unsigned int k;
drivers/spi/spi-sh-msiof.c
315
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
316
sh_msiof_write(p, SITFDR, buf_16[k] << fs);
drivers/spi/spi-sh-msiof.c
324
unsigned int k;
drivers/spi/spi-sh-msiof.c
326
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
327
sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
drivers/spi/spi-sh-msiof.c
335
unsigned int k;
drivers/spi/spi-sh-msiof.c
337
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
338
sh_msiof_write(p, SITFDR, buf_32[k] << fs);
drivers/spi/spi-sh-msiof.c
346
unsigned int k;
drivers/spi/spi-sh-msiof.c
348
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
349
sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
drivers/spi/spi-sh-msiof.c
357
unsigned int k;
drivers/spi/spi-sh-msiof.c
359
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
360
sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
drivers/spi/spi-sh-msiof.c
368
unsigned int k;
drivers/spi/spi-sh-msiof.c
370
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
371
sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
drivers/spi/spi-sh-msiof.c
379
unsigned int k;
drivers/spi/spi-sh-msiof.c
381
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
382
buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
drivers/spi/spi-sh-msiof.c
390
unsigned int k;
drivers/spi/spi-sh-msiof.c
392
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
393
buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
drivers/spi/spi-sh-msiof.c
401
unsigned int k;
drivers/spi/spi-sh-msiof.c
403
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
404
put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
drivers/spi/spi-sh-msiof.c
412
unsigned int k;
drivers/spi/spi-sh-msiof.c
414
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
415
buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
drivers/spi/spi-sh-msiof.c
423
unsigned int k;
drivers/spi/spi-sh-msiof.c
425
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
426
put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
drivers/spi/spi-sh-msiof.c
434
unsigned int k;
drivers/spi/spi-sh-msiof.c
436
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
437
buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
drivers/spi/spi-sh-msiof.c
445
unsigned int k;
drivers/spi/spi-sh-msiof.c
447
for (k = 0; k < words; k++)
drivers/spi/spi-sh-msiof.c
448
put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
drivers/spi/spi-zynq-qspi.c
414
int count, len, k;
drivers/spi/spi-zynq-qspi.c
437
for (k = 0; k < count; k++)
drivers/spi/spi-zynq-qspi.c
452
int count, len, k;
drivers/spi/spi-zynq-qspi.c
463
for (k = 0; k < count; k++)
drivers/staging/greybus/audio_topology.c
494
struct snd_kcontrol *k, int event)
drivers/staging/greybus/audio_topology.c
502
struct snd_kcontrol *k, int event)
drivers/staging/greybus/audio_topology.c
510
struct snd_kcontrol *k, int event)
drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c
37
unsigned int i, j, k, idx;
drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c
44
for (k = 0; k < 4; k++)
drivers/staging/media/atomisp/pci/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c
46
idx = idx_map[i] + (k * IA_CSS_MACC_NUM_AXES);
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
325
int out_width, out_height, chunk, rest, kmax, y, x, k, elm_start, elm, ofs;
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
351
for (k = 0; k < kmax; k++, elm++) {
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
352
output[ofs + k].ae_y = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
354
output[ofs + k].awb_cnt = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
356
output[ofs + k].awb_gr = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
358
output[ofs + k].awb_r = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
360
output[ofs + k].awb_b = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
362
output[ofs + k].awb_gb = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
364
output[ofs + k].af_hpf1 = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c
366
output[ofs + k].af_hpf2 = merge_hi_lo_14(
drivers/staging/media/atomisp/pci/sh_css_params.c
1409
unsigned int i, j, k, step, width, height;
drivers/staging/media/atomisp/pci/sh_css_params.c
1436
for (k = 0; k < width;
drivers/staging/media/atomisp/pci/sh_css_params.c
1437
k++, x_ptr++, y_ptr++, val_x += (short)step) {
drivers/staging/media/atomisp/pci/sh_css_params.c
1438
if (k == 0)
drivers/staging/media/atomisp/pci/sh_css_params.c
1440
else if (k == width - 1)
drivers/staging/media/atomisp/pci/sh_css_params.c
933
unsigned int height, width, y, x, k, data;
drivers/staging/media/atomisp/pci/sh_css_params.c
971
for (k = 0; k < ISP_VEC_NELEMS; k += 2) {
drivers/staging/media/atomisp/pci/sh_css_params.c
973
params->fpn_config.data[ofs + 2 * k] =
drivers/staging/media/atomisp/pci/sh_css_params.c
975
params->fpn_config.data[ofs + 2 * k + 2] =
drivers/staging/media/atomisp/pci/sh_css_params.c
979
for (k = 0; k < ISP_VEC_NELEMS; k += 2) {
drivers/staging/media/atomisp/pci/sh_css_params.c
981
params->fpn_config.data[ofs + 2 * k + 1] =
drivers/staging/media/atomisp/pci/sh_css_params.c
983
params->fpn_config.data[ofs + 2 * k + 3] =
drivers/staging/media/av7110/av7110_hw.c
123
int k;
drivers/staging/media/av7110/av7110_hw.c
127
for (k = 0; k < 100; k++) {
drivers/staging/media/ipu3/ipu3.c
111
unsigned int i, k, node;
drivers/staging/media/ipu3/ipu3.c
144
for (k = 0; k < IMGU_MAX_QUEUE_DEPTH; k++)
drivers/staging/media/ipu3/ipu3.c
145
imgu_css_buf_init(&imgu_pipe->queues[i].dummybufs[k], i,
drivers/staging/media/sunxi/cedrus/cedrus_h264.c
286
int i, j, k;
drivers/staging/media/sunxi/cedrus/cedrus_h264.c
308
for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) {
drivers/staging/media/sunxi/cedrus/cedrus_h264.c
311
val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) |
drivers/staging/media/sunxi/cedrus/cedrus_h264.c
312
(factors->chroma_weight[j][k] & 0x1ff);
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
275
u32 i, j, k, val;
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
295
for (k = 0; k < 8; k += 4) {
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
296
val = ((u32)scaling->scaling_list_8x8[i][j + (k + 3) * 8] << 24) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
297
((u32)scaling->scaling_list_8x8[i][j + (k + 2) * 8] << 16) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
298
((u32)scaling->scaling_list_8x8[i][j + (k + 1) * 8] << 8) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
299
scaling->scaling_list_8x8[i][j + k * 8];
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
305
for (k = 0; k < 8; k += 4) {
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
306
val = ((u32)scaling->scaling_list_32x32[i][j + (k + 3) * 8] << 24) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
307
((u32)scaling->scaling_list_32x32[i][j + (k + 2) * 8] << 16) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
308
((u32)scaling->scaling_list_32x32[i][j + (k + 1) * 8] << 8) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
309
scaling->scaling_list_32x32[i][j + k * 8];
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
315
for (k = 0; k < 8; k += 4) {
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
316
val = ((u32)scaling->scaling_list_16x16[i][j + (k + 3) * 8] << 24) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
317
((u32)scaling->scaling_list_16x16[i][j + (k + 2) * 8] << 16) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
318
((u32)scaling->scaling_list_16x16[i][j + (k + 1) * 8] << 8) |
drivers/staging/media/sunxi/cedrus/cedrus_h265.c
319
scaling->scaling_list_16x16[i][j + k * 8];
drivers/staging/media/sunxi/cedrus/cedrus_vp8.c
597
int i, j, k;
drivers/staging/media/sunxi/cedrus/cedrus_vp8.c
619
for (k = 0; k < 3; ++k)
drivers/staging/media/sunxi/cedrus/cedrus_vp8.c
620
memcpy(&prob_table[i * 512 + j * 64 + k * 16],
drivers/staging/media/sunxi/cedrus/cedrus_vp8.c
621
slice->entropy.coeff_probs[i][j][k], 11);
drivers/staging/rtl8723bs/core/rtw_efuse.c
69
u32 k = 0;
drivers/staging/rtl8723bs/core/rtw_efuse.c
92
k++;
drivers/staging/rtl8723bs/core/rtw_efuse.c
93
if (k == 1000)
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3666
int j, k = 0;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3671
InfoContent[k] = i;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3673
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3679
if (k < 16) {
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3680
InfoContent[k] = j; /* channel number */
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3682
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
3686
pframe = rtw_set_ie(pframe, WLAN_EID_BSS_INTOLERANT_CHL_REPORT, k, InfoContent, &(pattrib->pktlen));
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4240
u8 j, k;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4278
i = j = k = 0;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4290
chplan_new[k].ChannelNum = chplan_ap.Channel[j];
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4291
chplan_new[k].ScanType = SCAN_ACTIVE;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4294
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4296
chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4297
chplan_new[k].ScanType = SCAN_PASSIVE;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4299
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4301
chplan_new[k].ChannelNum = chplan_ap.Channel[j];
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4302
chplan_new[k].ScanType = SCAN_ACTIVE;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4304
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4313
chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4314
chplan_new[k].ScanType = SCAN_PASSIVE;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4316
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4321
chplan_new[k].ChannelNum = chplan_ap.Channel[j];
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4322
chplan_new[k].ScanType = SCAN_ACTIVE;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4324
k++;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4331
chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4332
chplan_new[k].ScanType = chplan_sta[i].ScanType;
drivers/staging/rtl8723bs/core/rtw_mlme_ext.c
4334
k++;
drivers/staging/rtl8723bs/hal/hal_com_phycfg.c
792
u8 i, j, k, l, m;
drivers/staging/rtl8723bs/hal/hal_com_phycfg.c
796
for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
drivers/staging/rtl8723bs/hal/hal_com_phycfg.c
799
pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
169
u32 k = 0;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
236
(k >= (rtw_hal_sdio_max_txoqt_free_space(padapter) - 1))
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
244
pframe->agg_num = k;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
245
pxmitbuf->agg_num = k;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
267
k = 0;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
282
if (k == 0) {
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
298
k++;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
299
if (k != 1)
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
310
if (k != 1)
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
328
pframe->agg_num = k;
drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c
329
pxmitbuf->agg_num = k;
drivers/target/iscsi/iscsi_target_seq_pdu_list.c
107
for (k = 0; k < i + 1; k++) {
drivers/target/iscsi/iscsi_target_seq_pdu_list.c
109
if ((array[k] & 0x80000000) && (array[k] == j))
drivers/target/iscsi/iscsi_target_seq_pdu_list.c
96
int i, j, k;
drivers/target/target_core_user.c
3313
int ret, i, k, len = 0;
drivers/target/target_core_user.c
3353
for (k = 0; passthrough_pr_attrib_attrs[k] != NULL; k++)
drivers/target/target_core_user.c
3354
tcmu_attrs[i++] = passthrough_pr_attrib_attrs[k];
drivers/target/target_core_user.c
3355
for (k = 0; tcmu_attrib_attrs[k] != NULL; k++)
drivers/target/target_core_user.c
3356
tcmu_attrs[i++] = tcmu_attrib_attrs[k];
drivers/tty/n_gsm.c
1574
unsigned int ftype, i, adaption, prio, n1, k;
drivers/tty/n_gsm.c
1580
k = FIELD_GET(PN_K_FIELD_K, params->k_bits);
drivers/tty/n_gsm.c
1636
if (ftype != UI && ftype != UIH && k > dlci->k) {
drivers/tty/n_gsm.c
1638
pr_info("%s invalid k %d in PN\n", __func__, k);
drivers/tty/n_gsm.c
1641
dlci->k = k;
drivers/tty/n_gsm.c
1662
dlci->k = k;
drivers/tty/n_gsm.c
179
u8 k; /* Window size */
drivers/tty/n_gsm.c
2522
dc->k = (u32)dlci->k;
drivers/tty/n_gsm.c
2559
if (dc->k > 7)
drivers/tty/n_gsm.c
2617
if (dc->k)
drivers/tty/n_gsm.c
2618
dlci->k = (u8)dc->k;
drivers/tty/n_gsm.c
2620
dlci->k = gsm->k;
drivers/tty/n_gsm.c
2671
dlci->k = gsm->k;
drivers/tty/n_gsm.c
3309
gsm->k = K;
drivers/tty/n_gsm.c
3360
c->k = gsm->k;
drivers/tty/n_gsm.c
337
u8 k; /* Window size */
drivers/tty/n_gsm.c
3384
if (c->k > MAX_WINDOW_SIZE)
drivers/tty/n_gsm.c
3435
if (c->k)
drivers/tty/n_gsm.c
3436
gsm->k = c->k;
drivers/tty/n_gsm.c
631
params->k_bits = FIELD_PREP(PN_K_FIELD_K, dlci->k);
drivers/tty/serial/8250/8250_fintek.c
374
int i, j, k, min, max;
drivers/tty/serial/8250/8250_fintek.c
389
for (k = min; k < max; k++) {
drivers/tty/serial/8250/8250_fintek.c
392
sio_write_reg(pdata, LDN, k);
drivers/tty/serial/8250/8250_fintek.c
398
pdata->index = k;
drivers/tty/tty_ioctl.c
395
__weak int user_termios_to_kernel_termios(struct ktermios *k,
drivers/tty/tty_ioctl.c
398
return copy_from_user(k, u, sizeof(struct termios2));
drivers/tty/tty_ioctl.c
401
struct ktermios *k)
drivers/tty/tty_ioctl.c
403
return copy_to_user(u, k, sizeof(struct termios2));
drivers/tty/tty_ioctl.c
405
__weak int user_termios_to_kernel_termios_1(struct ktermios *k,
drivers/tty/tty_ioctl.c
408
return copy_from_user(k, u, sizeof(struct termios));
drivers/tty/tty_ioctl.c
411
struct ktermios *k)
drivers/tty/tty_ioctl.c
413
return copy_to_user(u, k, sizeof(struct termios));
drivers/tty/tty_ioctl.c
418
__weak int user_termios_to_kernel_termios(struct ktermios *k,
drivers/tty/tty_ioctl.c
421
return copy_from_user(k, u, sizeof(struct termios));
drivers/tty/tty_ioctl.c
424
struct ktermios *k)
drivers/tty/tty_ioctl.c
426
return copy_to_user(u, k, sizeof(struct termios));
drivers/tty/vt/keyboard.c
405
unsigned int k, sym, val;
drivers/tty/vt/keyboard.c
410
for_each_set_bit(k, key_down, min(NR_KEYS, KEY_CNT)) {
drivers/tty/vt/keyboard.c
411
sym = U(key_maps[0][k]);
drivers/tty/vt/vt.c
3743
int j, k ;
drivers/tty/vt/vt.c
3748
for (j=k=0; j<16; j++) {
drivers/tty/vt/vt.c
3749
vc->vc_palette[k++] = default_red[j] ;
drivers/tty/vt/vt.c
3750
vc->vc_palette[k++] = default_grn[j] ;
drivers/tty/vt/vt.c
3751
vc->vc_palette[k++] = default_blu[j] ;
drivers/tty/vt/vt.c
3921
int i, j = -1, k = -1, retval = -ENODEV;
drivers/tty/vt/vt.c
3973
k = i;
drivers/tty/vt/vt.c
4002
if (k >= 0) {
drivers/tty/vt/vt.c
4003
vc = vc_cons[k].d;
drivers/tty/vt/vt.c
4763
int i, j, k;
drivers/tty/vt/vt.c
4770
for (i = k = 0; i < 16; i++) {
drivers/tty/vt/vt.c
4771
default_red[i] = colormap[k++];
drivers/tty/vt/vt.c
4772
default_grn[i] = colormap[k++];
drivers/tty/vt/vt.c
4773
default_blu[i] = colormap[k++];
drivers/tty/vt/vt.c
4778
for (j = k = 0; j < 16; j++) {
drivers/tty/vt/vt.c
4779
vc_cons[i].d->vc_palette[k++] = default_red[j];
drivers/tty/vt/vt.c
4780
vc_cons[i].d->vc_palette[k++] = default_grn[j];
drivers/tty/vt/vt.c
4781
vc_cons[i].d->vc_palette[k++] = default_blu[j];
drivers/tty/vt/vt.c
4791
int i, k;
drivers/tty/vt/vt.c
4795
for (i = k = 0; i < 16; i++) {
drivers/tty/vt/vt.c
4796
colormap[k++] = default_red[i];
drivers/tty/vt/vt.c
4797
colormap[k++] = default_grn[i];
drivers/tty/vt/vt.c
4798
colormap[k++] = default_blu[i];
drivers/tty/vt/vt.c
4809
int j, k;
drivers/tty/vt/vt.c
4810
for (j=k=0; j<16; j++) {
drivers/tty/vt/vt.c
4811
vc->vc_palette[k++] = default_red[j];
drivers/tty/vt/vt.c
4812
vc->vc_palette[k++] = default_grn[j];
drivers/tty/vt/vt.c
4813
vc->vc_palette[k++] = default_blu[j];
drivers/usb/chipidea/udc.c
2035
int k = i + j * ci->hw_ep_max/2;
drivers/usb/chipidea/udc.c
2036
struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
drivers/usb/core/config.c
262
int i, j, k;
drivers/usb/core/config.c
274
for (k = 0; k < alt->desc.bNumEndpoints; ++k) {
drivers/usb/core/config.c
275
epd = &alt->endpoint[k].desc;
drivers/usb/gadget/function/f_uac2.c
650
#define DECLARE_UAC2_CNTRL_RANGES_LAY3(k, n) \
drivers/usb/gadget/function/f_uac2.c
651
struct cntrl_ranges_lay3_##k { \
drivers/usb/host/isp116x.h
565
int k;
drivers/usb/host/isp116x.h
569
for (k = 0; k < PTD_GET_LEN(ptd); ++k)
drivers/usb/host/isp116x.h
570
printk("%02x ", ((u8 *) buf)[k]);
drivers/usb/host/isp116x.h
577
int k;
drivers/usb/host/isp116x.h
581
for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
drivers/usb/host/isp116x.h
582
printk("%02x ", ((u8 *) buf)[k]);
drivers/usb/host/xhci-mtk-sch.c
425
int i, j, k;
drivers/usb/host/xhci-mtk-sch.c
431
k = XHCI_MTK_BW_INDEX(base + j);
drivers/usb/host/xhci-mtk-sch.c
432
bw = sch_bw->bus_bw[k] + sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
461
int i, j, k;
drivers/usb/host/xhci-mtk-sch.c
466
k = XHCI_MTK_BW_INDEX(base + j);
drivers/usb/host/xhci-mtk-sch.c
468
sch_bw->bus_bw[k] += sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
470
sch_bw->bus_bw[k] -= sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
500
int i, k;
drivers/usb/host/xhci-mtk-sch.c
510
k = XHCI_MTK_BW_INDEX(offset + i);
drivers/usb/host/xhci-mtk-sch.c
512
tmp = tt->fs_bus_bw_out[k] + sch_ep->bw_budget_table[i];
drivers/usb/host/xhci-mtk-sch.c
514
tmp = tt->fs_bus_bw_in[k];
drivers/usb/host/xhci-mtk-sch.c
527
int i, j, k;
drivers/usb/host/xhci-mtk-sch.c
531
k = XHCI_MTK_BW_INDEX(offset + sch_ep->num_budget_microframes - 1) / UFRAMES_PER_FRAME;
drivers/usb/host/xhci-mtk-sch.c
533
if (j != k) {
drivers/usb/host/xhci-mtk-sch.c
535
tail = tt->fs_frame_bw[k];
drivers/usb/host/xhci-mtk-sch.c
638
int i, j, k;
drivers/usb/host/xhci-mtk-sch.c
648
k = XHCI_MTK_BW_INDEX(base + j);
drivers/usb/host/xhci-mtk-sch.c
649
if (tt->in_ss_cnt[k])
drivers/usb/host/xhci-mtk-sch.c
653
k = XHCI_MTK_BW_INDEX(base);
drivers/usb/host/xhci-mtk-sch.c
655
if (tt->fs_bus_bw_out[k])
drivers/usb/host/xhci-mtk-sch.c
739
int i, j, k, f;
drivers/usb/host/xhci-mtk-sch.c
750
k = XHCI_MTK_BW_INDEX(base + j);
drivers/usb/host/xhci-mtk-sch.c
751
f = k / UFRAMES_PER_FRAME;
drivers/usb/host/xhci-mtk-sch.c
754
tt->ls_bus_bw[k] += (u8)sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
756
fs_bus_bw[k] += (u16)sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
760
tt->ls_bus_bw[k] -= (u8)sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
762
fs_bus_bw[k] -= (u16)sch_ep->bw_budget_table[j];
drivers/usb/host/xhci-mtk-sch.c
768
k = XHCI_MTK_BW_INDEX(base);
drivers/usb/host/xhci-mtk-sch.c
770
tt->in_ss_cnt[k]++;
drivers/usb/host/xhci-mtk-sch.c
772
tt->in_ss_cnt[k]--;
drivers/usb/host/xhci-tegra.c
1591
unsigned int i, j, k;
drivers/usb/host/xhci-tegra.c
1777
for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
drivers/usb/host/xhci-tegra.c
1793
tegra->phys[k++] = phy;
drivers/usb/host/xhci-tegra.c
2118
unsigned int i, j, k;
drivers/usb/host/xhci-tegra.c
2122
for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
drivers/usb/host/xhci-tegra.c
2134
phy = tegra->phys[k++];
drivers/usb/serial/garmin_gps.c
594
int k;
drivers/usb/serial/garmin_gps.c
599
k = garmin_data_p->outsize;
drivers/usb/serial/garmin_gps.c
600
if ((k+count) > GPS_OUT_BUFSIZ) {
drivers/usb/serial/garmin_gps.c
606
memcpy(garmin_data_p->outbuffer+k, buf, count);
drivers/usb/serial/garmin_gps.c
607
k += count;
drivers/usb/serial/garmin_gps.c
608
garmin_data_p->outsize = k;
drivers/usb/serial/garmin_gps.c
610
if (k >= GARMIN_PKTHDR_LENGTH) {
drivers/usb/serial/garmin_gps.c
614
if (k < i)
drivers/usb/serial/garmin_gps.c
620
dev_dbg(dev, "%s - %d bytes in buffer, %d bytes in pkt.\n", __func__, k, i);
drivers/usb/serial/garmin_gps.c
624
usb_serial_debug_data(&garmin_data_p->port->dev, __func__, k,
drivers/usb/serial/garmin_gps.c
647
k = 0;
drivers/usb/serial/garmin_gps.c
651
k++;
drivers/usb/serial/garmin_gps.c
655
if (k > (GARMIN_PKTHDR_LENGTH-2)) {
drivers/usb/typec/ucsi/ucsi.c
512
int k = 0;
drivers/usb/typec/ucsi/ucsi.c
540
orig[k].mid = alt.mid;
drivers/usb/typec/ucsi/ucsi.c
541
orig[k].svid = alt.svid;
drivers/usb/typec/ucsi/ucsi.c
542
k++;
drivers/usb/typec/ucsi/ucsi_ccg.c
404
int i, j, k = 0;
drivers/usb/typec/ucsi/ucsi_ccg.c
436
new_alt[k].svid = alt[i].svid;
drivers/usb/typec/ucsi/ucsi_ccg.c
437
new_alt[k].mid |= alt[i].mid;
drivers/usb/typec/ucsi/ucsi_ccg.c
438
new_alt[k].linked_idx = i;
drivers/usb/typec/ucsi/ucsi_ccg.c
439
alt[i].linked_idx = k;
drivers/usb/typec/ucsi/ucsi_ccg.c
440
updated[k].svid = new_alt[k].svid;
drivers/usb/typec/ucsi/ucsi_ccg.c
441
updated[k].mid = new_alt[k].mid;
drivers/usb/typec/ucsi/ucsi_ccg.c
442
k++;
drivers/usb/typec/ucsi/ucsi_ccg.c
452
new_alt[k].svid = alt[i].svid;
drivers/usb/typec/ucsi/ucsi_ccg.c
453
new_alt[k].mid |= alt[i].mid | alt[j].mid;
drivers/usb/typec/ucsi/ucsi_ccg.c
454
new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX;
drivers/usb/typec/ucsi/ucsi_ccg.c
455
alt[i].linked_idx = k;
drivers/usb/typec/ucsi/ucsi_ccg.c
456
alt[j].linked_idx = k;
drivers/usb/typec/ucsi/ucsi_ccg.c
465
new_alt[k].svid = alt[i].svid;
drivers/usb/typec/ucsi/ucsi_ccg.c
466
new_alt[k].mid |= alt[i].mid;
drivers/usb/typec/ucsi/ucsi_ccg.c
467
new_alt[k].linked_idx = i;
drivers/usb/typec/ucsi/ucsi_ccg.c
468
alt[i].linked_idx = k;
drivers/usb/typec/ucsi/ucsi_ccg.c
470
updated[k].svid = new_alt[k].svid;
drivers/usb/typec/ucsi/ucsi_ccg.c
471
updated[k].mid = new_alt[k].mid;
drivers/usb/typec/ucsi/ucsi_ccg.c
472
k++;
drivers/usb/typec/ucsi/ucsi_ccg.c
485
int i, j, k = 0xff;
drivers/usb/typec/ucsi/ucsi_ccg.c
519
if (k == 0xff || (k != 0xff && pin >
drivers/usb/typec/ucsi/ucsi_ccg.c
520
DP_CONF_GET_PIN_ASSIGN(port[k].mid))
drivers/usb/typec/ucsi/ucsi_ccg.c
522
k = j;
drivers/usb/typec/ucsi/ucsi_ccg.c
526
cam = k;
drivers/video/fbdev/aty/mach64_gx.c
620
u16 m, n, k = 0, save_m, save_n, twoToKth;
drivers/video/fbdev/aty/mach64_gx.c
643
k++;
drivers/video/fbdev/aty/mach64_gx.c
646
twoToKth = 1 << k;
drivers/video/fbdev/aty/mach64_gx.c
671
program_bits = (k << 6) + (save_m) + (save_n << 8);
drivers/video/fbdev/controlfb.c
384
unsigned long p0, p1, p2, k, l, m, n, min;
drivers/video/fbdev/controlfb.c
393
for (k = 1, min = l; k < 32; k++) {
drivers/video/fbdev/controlfb.c
396
m = CONTROL_PIXCLOCK_BASE * k;
drivers/video/fbdev/controlfb.c
400
p0 = k;
drivers/video/fbdev/core/fb_logo.c
101
int i, j, k;
drivers/video/fbdev/core/fb_logo.c
138
for (k = 7; k >= 0 && j < logo->width; k--) {
drivers/video/fbdev/core/fb_logo.c
139
*dst++ = ((d >> k) & 1) ? fg : 0;
drivers/video/fbdev/core/fbcon.c
2590
int i, j, k, depth;
drivers/video/fbdev/core/fbcon.c
2602
k = table[i];
drivers/video/fbdev/core/fbcon.c
2604
palette_red[k] = (val << 8) | val;
drivers/video/fbdev/core/fbcon.c
2606
palette_green[k] = (val << 8) | val;
drivers/video/fbdev/core/fbcon.c
2608
palette_blue[k] = (val << 8) | val;
drivers/video/fbdev/maxinefb.c
78
register unsigned int j, k;
drivers/video/fbdev/maxinefb.c
82
k = *((volatile unsigned short *) regs);
drivers/video/fbdev/maxinefb.c
84
return (j & 0xffff) | ((k & 0xff00) << 8);
drivers/video/fbdev/mb862xx/mb862xxfb_accel.c
103
int k = 0;
drivers/video/fbdev/mb862xx/mb862xxfb_accel.c
104
for (k = 0; k < step; k++)
drivers/video/fbdev/mb862xx/mb862xxfb_accel.c
105
cmd[9 + i * step + k] =
drivers/video/fbdev/mb862xx/mb862xxfb_accel.c
106
cpu_to_be32(cmd[9 + i * step + k]);
drivers/video/fbdev/nvidia/nv_accel.c
358
int j, k = 0;
drivers/video/fbdev/nvidia/nv_accel.c
386
tmp = data[k++];
drivers/video/fbdev/nvidia/nv_accel.c
398
tmp = data[k++];
drivers/video/fbdev/nvidia/nvidia.c
116
int i, j, k = 0;
drivers/video/fbdev/nvidia/nvidia.c
138
NV_WR32(&par->CURSOR[k++], 0, tmp);
drivers/video/fbdev/nvidia/nvidia.c
140
k += (MAX_CURS - w) / 2;
drivers/video/fbdev/omap/sossi.c
562
u32 l, k;
drivers/video/fbdev/omap/sossi.c
618
k = sossi_read_reg(SOSSI_ID_REG);
drivers/video/fbdev/omap/sossi.c
620
if (l != 0x55555555 || k != 0xaaaaaaaa) {
drivers/video/fbdev/omap/sossi.c
622
"invalid SoSSI sync pattern: %08x, %08x\n", l, k);
drivers/video/fbdev/pm2fb.c
1331
int k = 8 - j;
drivers/video/fbdev/pm2fb.c
1351
for (; k > 0; k--) {
drivers/video/fbdev/pm2fb.c
1440
int k = 8 - j;
drivers/video/fbdev/pm2fb.c
1453
for (; k > 0; k--)
drivers/video/fbdev/pm2fb.c
1466
int k = 8 - j;
drivers/video/fbdev/pm2fb.c
1474
for (; k > 0; k--)
drivers/video/fbdev/pm3fb.c
687
int k = 8 - j;
drivers/video/fbdev/pm3fb.c
705
for (; k > 0; k--) {
drivers/video/fbdev/riva/fbdev.c
481
int i, j, k = 0;
drivers/video/fbdev/riva/fbdev.c
506
writel(tmp, &par->riva.CURSOR[k++]);
drivers/video/fbdev/riva/fbdev.c
508
k += (MAX_CURS - w)/2;
drivers/video/fbdev/sh_mobile_lcdcfb.c
1001
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
1014
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
1015
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
1025
for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
1026
struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
1036
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
1037
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
1063
int k;
drivers/video/fbdev/sh_mobile_lcdcfb.c
1066
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
1067
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
1099
for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
drivers/video/fbdev/sh_mobile_lcdcfb.c
1100
if (priv->ch[k].enabled)
drivers/video/fbdev/sh_mobile_lcdcfb.c
638
int k;
drivers/video/fbdev/sh_mobile_lcdcfb.c
648
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
649
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
696
int k;
drivers/video/fbdev/sh_mobile_lcdcfb.c
705
for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
drivers/video/fbdev/sh_mobile_lcdcfb.c
706
if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
drivers/video/fbdev/sh_mobile_lcdcfb.c
708
tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
drivers/video/fbdev/sh_mobile_lcdcfb.c
874
int k, m;
drivers/video/fbdev/sh_mobile_lcdcfb.c
887
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
888
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
915
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
916
ch = &priv->ch[k];
drivers/video/fbdev/sh_mobile_lcdcfb.c
986
int k;
drivers/video/fbdev/sh_mobile_lcdcfb.c
989
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sh_mobile_lcdcfb.c
990
if (priv->ch[k].enabled)
drivers/video/fbdev/sh_mobile_lcdcfb.c
998
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
drivers/video/fbdev/sis/init.c
2874
unsigned short data, data2, time, i, j, k, m, n, o;
drivers/video/fbdev/sis/init.c
2909
for(k = 0; k < 3; k++) {
drivers/video/fbdev/sis/init.c
2921
for(k = 0; k < 3; k++) SiS_SetRegByte(DACData, data);
drivers/video/fbdev/sis/sis_main.c
4229
unsigned int k, RankCapacity, PageCapacity, BankNumHigh, BankNumMid;
drivers/video/fbdev/sis/sis_main.c
4232
for (k = 0; k < ARRAY_SIZE(SiS_DRAMType); k++) {
drivers/video/fbdev/sis/sis_main.c
4233
RankCapacity = buswidth * SiS_DRAMType[k][3];
drivers/video/fbdev/sis/sis_main.c
4238
if ((SiS_DRAMType[k][2] + SiS_DRAMType[k][0]) > PseudoAdrPinCount)
drivers/video/fbdev/sis/sis_main.c
4248
PageCapacity = (1 << SiS_DRAMType[k][1]) * buswidth * 4;
drivers/video/fbdev/sis/sis_main.c
4251
PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh;
drivers/video/fbdev/sis/sis_main.c
4255
sr14 = (SiS_DRAMType[k][3] * buswidth) - 1;
drivers/video/fbdev/sis/sis_main.c
4262
SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]);
drivers/video/fbdev/sis/sis_main.c
4604
int i, j, k, l, status;
drivers/video/fbdev/sis/sis_main.c
4807
k = (ivideo->chip == XGI_20) ? 12 : 4;
drivers/video/fbdev/sis/sis_main.c
4810
for(i = 0; i < k; i++) {
drivers/video/fbdev/sis/sis_main.c
5081
int i, j, k, index;
drivers/video/fbdev/sis/sis_main.c
5431
for(k = 0; k < 16; k++) {
drivers/video/fbdev/sm501fb.c
1540
int k;
drivers/video/fbdev/sm501fb.c
1631
for (k = 0; k < (256 * 3); k++)
drivers/video/fbdev/sm501fb.c
1632
smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
drivers/video/fbdev/ssd1307fb.c
221
int ret, i, j, k;
drivers/video/fbdev/ssd1307fb.c
273
for (k = 0; k < m; k++) {
drivers/video/fbdev/ssd1307fb.c
274
u8 byte = vmem[(8 * i + k) * line_length +
drivers/video/fbdev/ssd1307fb.c
277
data |= bit << k;
drivers/video/fbdev/tdfxfb.c
290
int m, n, k, best_m, best_n, best_k, best_error;
drivers/video/fbdev/tdfxfb.c
296
for (k = 3; k >= 0; k--) {
drivers/video/fbdev/tdfxfb.c
302
int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
drivers/video/fbdev/tdfxfb.c
312
int f = (fref * (n + 2) / (m + 2)) >> k;
drivers/video/fbdev/tdfxfb.c
323
best_k = k;
drivers/video/fbdev/tdfxfb.c
331
k = best_k;
drivers/video/fbdev/tdfxfb.c
332
*freq_out = (fref * (n + 2) / (m + 2)) >> k;
drivers/video/fbdev/tdfxfb.c
334
return (n << 8) | (m << 2) | k;
drivers/video/fbdev/tridentfb.c
838
int m, n, k;
drivers/video/fbdev/tridentfb.c
845
for (k = shift; k >= 0; k--)
drivers/video/fbdev/tridentfb.c
849
fi = ((14318l * (n + 8)) / (m + 2)) >> k;
drivers/video/fbdev/tridentfb.c
851
if (di < d || (di == d && k == best_k)) {
drivers/video/fbdev/tridentfb.c
855
best_k = k;
drivers/video/fbdev/tridentfb.c
912
unsigned int k;
drivers/video/fbdev/tridentfb.c
916
k = memsize * Kb;
drivers/video/fbdev/tridentfb.c
920
k = 2560 * Kb;
drivers/video/fbdev/tridentfb.c
927
k = 512 * Kb;
drivers/video/fbdev/tridentfb.c
930
k = 6 * Mb; /* XP */
drivers/video/fbdev/tridentfb.c
933
k = 1 * Mb;
drivers/video/fbdev/tridentfb.c
936
k = 8 * Mb;
drivers/video/fbdev/tridentfb.c
939
k = 10 * Mb; /* XP */
drivers/video/fbdev/tridentfb.c
942
k = 2 * Mb;
drivers/video/fbdev/tridentfb.c
945
k = 12 * Mb; /* XP */
drivers/video/fbdev/tridentfb.c
948
k = 14 * Mb; /* XP */
drivers/video/fbdev/tridentfb.c
951
k = 16 * Mb; /* XP */
drivers/video/fbdev/tridentfb.c
958
k = 20 * Mb;
drivers/video/fbdev/tridentfb.c
961
k = 24 * Mb;
drivers/video/fbdev/tridentfb.c
964
k = 28 * Mb;
drivers/video/fbdev/tridentfb.c
967
k = 32 * Mb;
drivers/video/fbdev/tridentfb.c
970
k = 1 * Mb;
drivers/video/fbdev/tridentfb.c
976
k = 4 * Mb;
drivers/video/fbdev/tridentfb.c
979
k = 1 * Mb;
drivers/video/fbdev/tridentfb.c
984
k -= memdiff * Kb;
drivers/video/fbdev/tridentfb.c
985
output("framebuffer size = %d Kb\n", k / Kb);
drivers/video/fbdev/tridentfb.c
986
return k;
drivers/video/fbdev/udlfb.c
373
int j, k;
drivers/video/fbdev/udlfb.c
388
for (k = width - 1; k > j; k--) {
drivers/video/fbdev/udlfb.c
389
if (back[k] != front[k]) {
drivers/video/fbdev/udlfb.c
390
end = k+1;
drivers/video/logo/pnmtologo.c
307
unsigned int i, j, k;
drivers/video/logo/pnmtologo.c
313
for (k = 0; k < 16; k++)
drivers/video/logo/pnmtologo.c
314
if (is_equal(logo_data[i][j], clut_vga16[k]))
drivers/video/logo/pnmtologo.c
316
if (k == 16)
drivers/video/logo/pnmtologo.c
328
for (k = 0; k < 16; k++)
drivers/video/logo/pnmtologo.c
329
if (is_equal(logo_data[i][j], clut_vga16[k]))
drivers/video/logo/pnmtologo.c
331
val = k<<4;
drivers/video/logo/pnmtologo.c
333
for (k = 0; k < 16; k++)
drivers/video/logo/pnmtologo.c
334
if (is_equal(logo_data[i][j], clut_vga16[k]))
drivers/video/logo/pnmtologo.c
336
val |= k;
drivers/video/logo/pnmtologo.c
347
unsigned int i, j, k;
drivers/video/logo/pnmtologo.c
352
for (k = 0; k < logo_clutsize; k++)
drivers/video/logo/pnmtologo.c
353
if (is_equal(logo_data[i][j], logo_clut[k]))
drivers/video/logo/pnmtologo.c
355
if (k == logo_clutsize) {
drivers/video/logo/pnmtologo.c
370
for (k = 0; k < logo_clutsize; k++)
drivers/video/logo/pnmtologo.c
371
if (is_equal(logo_data[i][j], logo_clut[k]))
drivers/video/logo/pnmtologo.c
373
write_hex(k+32);
fs/binfmt_elf.c
1046
unsigned long k, vaddr;
fs/binfmt_elf.c
1216
k = elf_ppnt->p_vaddr;
fs/binfmt_elf.c
1217
if ((elf_ppnt->p_flags & PF_X) && k < start_code)
fs/binfmt_elf.c
1218
start_code = k;
fs/binfmt_elf.c
1219
if (start_data < k)
fs/binfmt_elf.c
1220
start_data = k;
fs/binfmt_elf.c
1227
if (BAD_ADDR(k) || elf_ppnt->p_filesz > elf_ppnt->p_memsz ||
fs/binfmt_elf.c
1229
TASK_SIZE - elf_ppnt->p_memsz < k) {
fs/binfmt_elf.c
1235
k = elf_ppnt->p_vaddr + elf_ppnt->p_filesz;
fs/binfmt_elf.c
1237
if ((elf_ppnt->p_flags & PF_X) && end_code < k)
fs/binfmt_elf.c
1238
end_code = k;
fs/binfmt_elf.c
1239
if (end_data < k)
fs/binfmt_elf.c
1240
end_data = k;
fs/binfmt_elf.c
1241
k = elf_ppnt->p_vaddr + elf_ppnt->p_memsz;
fs/binfmt_elf.c
1242
if (k > elf_brk)
fs/binfmt_elf.c
1243
elf_brk = k;
fs/binfmt_elf.c
682
unsigned long k, map_addr;
fs/binfmt_elf.c
708
k = load_addr + eppnt->p_vaddr;
fs/binfmt_elf.c
709
if (BAD_ADDR(k) ||
fs/binfmt_elf.c
712
TASK_SIZE - eppnt->p_memsz < k) {
fs/btrfs/disk-io.c
697
static int global_root_key_cmp(const void *k, const struct rb_node *node)
fs/btrfs/disk-io.c
699
const struct btrfs_key *key = k;
fs/btrfs/send.c
4098
static int rbtree_check_dir_ref_comp(const void *k, const struct rb_node *node)
fs/btrfs/send.c
4100
const struct recorded_ref *data = k;
fs/btrfs/send.c
4615
static int rbtree_ref_comp(const void *k, const struct rb_node *node)
fs/btrfs/send.c
4617
const struct recorded_ref *data = k;
fs/ext2/inode.c
1044
int k, err;
fs/ext2/inode.c
1047
for (k = depth; k > 1 && !offsets[k-1]; k--)
fs/ext2/inode.c
1049
partial = ext2_get_branch(inode, k, offsets, chain, &err);
fs/ext2/inode.c
1051
partial = chain + k-1;
fs/ext2/inode.c
1069
if (p == chain + k - 1 && p > chain) {
fs/ext2/inode.c
361
ext2_blks_to_allocate(Indirect * branch, int k, unsigned long blks,
fs/ext2/inode.c
370
if (k > 0) {
fs/ext4/extents.c
1062
int i = at, k, m, a;
fs/ext4/extents.c
1192
k = depth - at - 1;
fs/ext4/extents.c
1193
if (unlikely(k < 0)) {
fs/ext4/extents.c
1194
EXT4_ERROR_INODE(inode, "k %d < 0!", k);
fs/ext4/extents.c
1198
if (k)
fs/ext4/extents.c
1199
ext_debug(inode, "create %d intermediate indices\n", k);
fs/ext4/extents.c
1203
while (k--) {
fs/ext4/extents.c
1710
int k, err = 0;
fs/ext4/extents.c
1734
k = depth - 1;
fs/ext4/extents.c
1736
err = ext4_ext_get_access(handle, inode, path + k);
fs/ext4/extents.c
1739
if (unlikely(path[k].p_idx > EXT_LAST_INDEX(path[k].p_hdr))) {
fs/ext4/extents.c
1742
k, path[k].p_idx,
fs/ext4/extents.c
1743
EXT_LAST_INDEX(path[k].p_hdr));
fs/ext4/extents.c
1746
path[k].p_idx->ei_block = border;
fs/ext4/extents.c
1747
err = ext4_ext_dirty(handle, inode, path + k);
fs/ext4/extents.c
1751
while (k--) {
fs/ext4/extents.c
1753
if (path[k+1].p_idx != EXT_FIRST_INDEX(path[k+1].p_hdr))
fs/ext4/extents.c
1755
err = ext4_ext_get_access(handle, inode, path + k);
fs/ext4/extents.c
1758
if (unlikely(path[k].p_idx > EXT_LAST_INDEX(path[k].p_hdr))) {
fs/ext4/extents.c
1761
k, path[k].p_idx,
fs/ext4/extents.c
1762
EXT_LAST_INDEX(path[k].p_hdr));
fs/ext4/extents.c
1766
path[k].p_idx->ei_block = border;
fs/ext4/extents.c
1767
err = ext4_ext_dirty(handle, inode, path + k);
fs/ext4/extents.c
1780
while (++k < depth)
fs/ext4/extents.c
1781
clear_buffer_verified(path[k].p_bh);
fs/ext4/extents.c
2318
int k = depth - 1;
fs/ext4/extents.c
2321
leaf = ext4_idx_pblock(path[k].p_idx);
fs/ext4/extents.c
2322
if (unlikely(path[k].p_hdr->eh_entries == 0)) {
fs/ext4/extents.c
2323
EXT4_ERROR_INODE(inode, "path[%d].p_hdr->eh_entries == 0", k);
fs/ext4/extents.c
2326
err = ext4_ext_get_access(handle, inode, path + k);
fs/ext4/extents.c
2330
if (path[k].p_idx != EXT_LAST_INDEX(path[k].p_hdr)) {
fs/ext4/extents.c
2331
int len = EXT_LAST_INDEX(path[k].p_hdr) - path[k].p_idx;
fs/ext4/extents.c
2333
memmove(path[k].p_idx, path[k].p_idx + 1, len);
fs/ext4/extents.c
2336
le16_add_cpu(&path[k].p_hdr->eh_entries, -1);
fs/ext4/extents.c
2337
err = ext4_ext_dirty(handle, inode, path + k);
fs/ext4/extents.c
2346
while (--k >= 0) {
fs/ext4/extents.c
2347
if (path[k + 1].p_idx != EXT_FIRST_INDEX(path[k + 1].p_hdr))
fs/ext4/extents.c
2349
err = ext4_ext_get_access(handle, inode, path + k);
fs/ext4/extents.c
2352
path[k].p_idx->ei_block = path[k + 1].p_idx->ei_block;
fs/ext4/extents.c
2353
err = ext4_ext_dirty(handle, inode, path + k);
fs/ext4/extents.c
2366
while (++k < depth)
fs/ext4/extents.c
2367
clear_buffer_verified(path[k].p_bh);
fs/ext4/extents.c
2958
int k = i = depth;
fs/ext4/extents.c
2959
while (--k > 0)
fs/ext4/extents.c
2960
path[k].p_block =
fs/ext4/extents.c
2961
le16_to_cpu(path[k].p_hdr->eh_entries)+1;
fs/ext4/extents.c
668
int k, l = path->p_depth;
fs/ext4/extents.c
671
for (k = 0; k <= l; k++, path++) {
fs/ext4/extents.c
784
int k;
fs/ext4/extents.c
787
for (k = 0; k < le16_to_cpu(eh->eh_entries); k++, ix++) {
fs/ext4/extents.c
788
if (k != 0 && le32_to_cpu(ix->ei_block) <=
fs/ext4/extents.c
791
"first=0x%p\n", k,
fs/ext4/extents.c
797
BUG_ON(k && le32_to_cpu(ix->ei_block)
fs/ext4/extents.c
856
int k;
fs/ext4/extents.c
859
for (k = 0; k < le16_to_cpu(eh->eh_entries); k++, ex++) {
fs/ext4/extents.c
860
BUG_ON(k && le32_to_cpu(ex->ee_block)
fs/ext4/indirect.c
277
static int ext4_blks_to_allocate(Indirect *branch, int k, unsigned int blks,
fs/ext4/indirect.c
286
if (k > 0) {
fs/ext4/indirect.c
802
int k, err;
fs/ext4/indirect.c
806
for (k = depth; k > 1 && !offsets[k-1]; k--)
fs/ext4/indirect.c
808
partial = ext4_get_branch(inode, k, offsets, chain, &err);
fs/ext4/indirect.c
811
partial = chain + k-1;
fs/ext4/indirect.c
827
if (p == chain + k - 1 && p > chain) {
fs/ext4/mballoc.c
2510
int k;
fs/ext4/mballoc.c
2523
k = mb_find_next_zero_bit(buddy, max, 0);
fs/ext4/mballoc.c
2524
if (k >= max) {
fs/ext4/mballoc.c
2537
ac->ac_b_ex.fe_start = k << i;
fs/ext4/mballoc.c
712
int k;
fs/ext4/mballoc.c
768
k = i >> j;
fs/ext4/mballoc.c
769
MB_CHECK_ASSERT(k < max2);
fs/ext4/mballoc.c
770
if (!mb_test_bit(k, buddy2))
fs/ext4/mballoc.c
788
ext4_get_group_no_and_offset(sb, pa->pa_pstart, &groupnr, &k);
fs/ext4/mballoc.c
791
MB_CHECK_ASSERT(mb_test_bit(k + i, buddy));
fs/fat/dir.c
375
int chi, chl, i, j, k;
fs/fat/dir.c
428
for (k = 8; k < MSDOS_NAME;) {
fs/fat/dir.c
429
c = work[k];
fs/fat/dir.c
432
chl = fat_shortname2uni(nls_disk, &work[k], MSDOS_NAME - k,
fs/fat/dir.c
436
k++;
fs/fat/dir.c
447
int offset = min(chl, MSDOS_NAME-k);
fs/fat/dir.c
448
k += offset;
fs/fat/dir.c
451
for (chi = 0; chi < chl && k < MSDOS_NAME;
fs/fat/dir.c
452
chi++, i++, k++) {
fs/fat/dir.c
453
ptname[i] = work[k];
fs/fuse/file.c
419
u32 *k = fc->scramble_key;
fs/fuse/file.c
427
v0 += ((v1 << 4 ^ v1 >> 5) + v1) ^ (sum + k[sum & 3]);
fs/fuse/file.c
429
v1 += ((v0 << 4 ^ v0 >> 5) + v0) ^ (sum + k[sum>>11 & 3]);
fs/hpfs/alloc.c
161
unsigned k = le32_to_cpu(bmp[i-1]);
fs/hpfs/alloc.c
162
while (k & 0x80000000) {
fs/hpfs/alloc.c
163
q--; k <<= 1;
fs/hpfs/alloc.c
368
unsigned k;
fs/hpfs/alloc.c
370
for (k = le32_to_cpu(bmp[j]); k; k >>= 1) if (k & 1) if (!--n) {
fs/hpfs/alloc.c
389
u32 k;
fs/hpfs/alloc.c
391
for (k = 0xf; k; k <<= 4)
fs/hpfs/alloc.c
392
if ((le32_to_cpu(bmp[j]) & k) == k) {
fs/jfs/jfs_dmap.c
1316
int rc, ti, i, k, m, n, agperlev;
fs/jfs/jfs_dmap.c
1414
for (k = bmp->db_agheight; k > 0; k--) {
fs/jfs/jfs_dmap.c
2866
int lp, pp, k;
fs/jfs/jfs_dmap.c
2890
for (k = 0; k < le32_to_cpu(tp->dmt_height); k++) {
fs/jfs/jfs_dmap.c
2949
int ti, n = 0, k, x = 0;
fs/jfs/jfs_dmap.c
2965
for (k = le32_to_cpu(tp->dmt_height), ti = 1;
fs/jfs/jfs_dmap.c
2966
k > 0; k--, ti = ((ti + n) << 2) + 1) {
fs/jfs/jfs_dmap.c
3371
int i, i0 = true, j, j0 = true, k, n;
fs/jfs/jfs_dmap.c
3420
k = 1 << (l2agsize - oldl2agsize);
fs/jfs/jfs_dmap.c
3426
for (j = 0; j < k && i < agno; j++, i++) {
fs/jfs/jfs_dmap.c
3440
bmp->db_maxag = bmp->db_maxag / k;
fs/jfs/jfs_dmap.c
3459
k = blkno >> L2MAXL1SIZE;
fs/jfs/jfs_dmap.c
3460
l2leaf = l2dcp->stree + CTLLEAFIND + k;
fs/jfs/jfs_dmap.c
3466
for (; k < LPERCTL; k++, p += nbperpage) {
fs/jfs/jfs_dmap.c
3607
if (k > 0)
fs/jfs/jfs_extent.c
386
u64 m, k;
fs/jfs/jfs_extent.c
394
k = (u64) 1 << i;
fs/jfs/jfs_extent.c
395
k = ((k - 1) & nb) ? k : k >> 1;
fs/jfs/jfs_extent.c
397
return (k);
fs/jfs/jfs_txnmgr.c
1140
int k, n;
fs/jfs/jfs_txnmgr.c
1196
for (k = 0; k < cd.nip; k++) {
fs/jfs/jfs_txnmgr.c
1197
top = (cd.iplist[k])->i_ino;
fs/jfs/jfs_txnmgr.c
1198
for (n = k + 1; n < cd.nip; n++) {
fs/jfs/jfs_txnmgr.c
1202
cd.iplist[n] = cd.iplist[k];
fs/jfs/jfs_txnmgr.c
1203
cd.iplist[k] = ip;
fs/jfs/jfs_txnmgr.c
1207
ip = cd.iplist[k];
fs/jfs/jfs_txnmgr.c
1342
for (k = 0; k < cd.nip; k++) {
fs/jfs/jfs_txnmgr.c
1343
ip = cd.iplist[k];
fs/jfs/jfs_txnmgr.c
2255
int k, nlock;
fs/jfs/jfs_txnmgr.c
227
int k, size;
fs/jfs/jfs_txnmgr.c
2302
for (k = 0; k < nlock; k++, maplock++) {
fs/jfs/jfs_txnmgr.c
275
for (k = 0; k < nTxBlock; k++) {
fs/jfs/jfs_txnmgr.c
276
init_waitqueue_head(&TxBlock[k].gcwait);
fs/jfs/jfs_txnmgr.c
277
init_waitqueue_head(&TxBlock[k].waitor);
fs/jfs/jfs_txnmgr.c
280
for (k = 1; k < nTxBlock - 1; k++) {
fs/jfs/jfs_txnmgr.c
281
TxBlock[k].next = k + 1;
fs/jfs/jfs_txnmgr.c
283
TxBlock[k].next = 0;
fs/jfs/jfs_txnmgr.c
304
for (k = 1; k < nTxLock - 1; k++)
fs/jfs/jfs_txnmgr.c
305
TxLock[k].next = k + 1;
fs/jfs/jfs_txnmgr.c
306
TxLock[k].next = 0;
fs/jfs/jfs_txnmgr.c
905
lid_t lid, next, llid, k;
fs/jfs/jfs_txnmgr.c
959
k = linelock->next;
fs/jfs/jfs_txnmgr.c
961
llid = k;
fs/minix/bitmap.c
188
int k = sb->s_blocksize_bits + 3;
fs/minix/bitmap.c
196
bit = ino & ((1<<k) - 1);
fs/minix/bitmap.c
197
ino >>= k;
fs/minix/bitmap.c
47
int k = sb->s_blocksize_bits + 3;
fs/minix/bitmap.c
55
bit = zone & ((1<<k) - 1);
fs/minix/bitmap.c
56
zone >>= k;
fs/minix/itree_common.c
230
int k, err;
fs/minix/itree_common.c
233
for (k = depth; k > 1 && !offsets[k-1]; k--)
fs/minix/itree_common.c
235
partial = get_branch(inode, k, offsets, chain, &err);
fs/minix/itree_common.c
239
partial = chain + k-1;
fs/minix/itree_common.c
246
if (p == chain + k - 1 && p > chain) {
fs/minix/itree_common.c
359
int k = sb->s_blocksize_bits - 10;
fs/minix/itree_common.c
361
blocks = (size + sb->s_blocksize - 1) >> (BLOCK_SIZE_BITS + k);
fs/netfs/fscache_cookie.c
37
const u8 *k;
fs/netfs/fscache_cookie.c
51
k = (cookie->key_len <= sizeof(cookie->inline_key)) ?
fs/netfs/fscache_cookie.c
53
pr_err("%c-key=[%u] '%*phN'\n", prefix, cookie->key_len, cookie->key_len, k);
fs/nfsd/nfs4state.c
2399
static void __free_client(struct kref *k)
fs/nfsd/nfs4state.c
2401
struct nfsdfs_client *c = container_of(k, struct nfsdfs_client, cl_ref);
fs/nilfs2/alloc.c
833
int i, j, k, ret;
fs/nilfs2/alloc.c
904
for (k = 0; k < nempties; k++) {
fs/nilfs2/alloc.c
906
last_nrs[k]);
fs/nilfs2/alloc.c
910
ret, (unsigned long long)last_nrs[k],
fs/ntfs3/bitmap.c
148
struct rb_node_key *k;
fs/ntfs3/bitmap.c
150
k = rb_entry(*p, struct rb_node_key, node);
fs/ntfs3/bitmap.c
151
if (v < k->key) {
fs/ntfs3/bitmap.c
153
} else if (v > k->key) {
fs/ntfs3/bitmap.c
154
r = &k->node;
fs/ntfs3/bitmap.c
1552
unsigned int k, lim = bits / BITS_PER_LONG;
fs/ntfs3/bitmap.c
1555
for (k = 0; k < lim; k++)
fs/ntfs3/bitmap.c
1556
w += hweight_long(bmp[k]);
fs/ntfs3/bitmap.c
1559
w += hweight_long(ul_to_cpu(((bitmap_ulong *)bitmap)[k]) &
fs/ntfs3/bitmap.c
157
return &k->node;
fs/ntfs3/bitmap.c
175
struct e_node *k =
fs/ntfs3/bitmap.c
178
if (e_ckey > k->count.key) {
fs/ntfs3/bitmap.c
180
} else if (e_ckey < k->count.key) {
fs/ntfs3/bitmap.c
182
} else if (e_skey < k->start.key) {
fs/ntfs3/bitmap.c
184
} else if (e_skey > k->start.key) {
fs/ntfs3/bitmap.c
207
struct e_node *k;
fs/ntfs3/bitmap.c
211
k = rb_entry(parent, struct e_node, start.node);
fs/ntfs3/bitmap.c
212
if (e_skey < k->start.key) {
fs/ntfs3/bitmap.c
214
} else if (e_skey > k->start.key) {
fs/ntfs3/index.c
2570
size_t k = le64_to_cpu(ib->vbn) >>
fs/ntfs3/index.c
2573
indx_mark_free(indx, ni, k);
fs/ntfs3/index.c
2574
if (k < trim_bit)
fs/ntfs3/index.c
2575
trim_bit = k;
fs/proc/array.c
251
struct k_sigaction *k;
fs/proc/array.c
254
k = p->sighand->action;
fs/proc/array.c
255
for (i = 1; i <= _NSIG; ++i, ++k) {
fs/proc/array.c
256
if (k->sa.sa_handler == SIG_IGN)
fs/proc/array.c
258
else if (k->sa.sa_handler != SIG_DFL)
fs/proc/page.c
150
unsigned long k;
fs/proc/page.c
165
k = folio->flags.f;
fs/proc/page.c
185
u |= kpf_copy_bit(k, KPF_COMPOUND_HEAD, PG_head);
fs/proc/page.c
212
u |= kpf_copy_bit(k, KPF_IDLE, PG_idle);
fs/proc/page.c
218
u |= kpf_copy_bit(k, KPF_LOCKED, PG_locked);
fs/proc/page.c
219
u |= kpf_copy_bit(k, KPF_DIRTY, PG_dirty);
fs/proc/page.c
220
u |= kpf_copy_bit(k, KPF_UPTODATE, PG_uptodate);
fs/proc/page.c
221
u |= kpf_copy_bit(k, KPF_WRITEBACK, PG_writeback);
fs/proc/page.c
223
u |= kpf_copy_bit(k, KPF_LRU, PG_lru);
fs/proc/page.c
224
u |= kpf_copy_bit(k, KPF_REFERENCED, PG_referenced);
fs/proc/page.c
225
u |= kpf_copy_bit(k, KPF_ACTIVE, PG_active);
fs/proc/page.c
226
u |= kpf_copy_bit(k, KPF_RECLAIM, PG_reclaim);
fs/proc/page.c
229
if ((k & SWAPCACHE) == SWAPCACHE)
fs/proc/page.c
231
u |= kpf_copy_bit(k, KPF_SWAPBACKED, PG_swapbacked);
fs/proc/page.c
233
u |= kpf_copy_bit(k, KPF_UNEVICTABLE, PG_unevictable);
fs/proc/page.c
234
u |= kpf_copy_bit(k, KPF_MLOCKED, PG_mlocked);
fs/proc/page.c
238
u |= kpf_copy_bit(k, KPF_HWPOISON, PG_hwpoison);
fs/proc/page.c
243
u |= kpf_copy_bit(k, KPF_RESERVED, PG_reserved);
fs/proc/page.c
244
u |= kpf_copy_bit(k, KPF_OWNER_2, PG_owner_2);
fs/proc/page.c
245
u |= kpf_copy_bit(k, KPF_PRIVATE, PG_private);
fs/proc/page.c
246
u |= kpf_copy_bit(k, KPF_PRIVATE_2, PG_private_2);
fs/proc/page.c
247
u |= kpf_copy_bit(k, KPF_OWNER_PRIVATE, PG_owner_priv_1);
fs/proc/page.c
248
u |= kpf_copy_bit(k, KPF_ARCH, PG_arch_1);
fs/proc/page.c
250
u |= kpf_copy_bit(k, KPF_ARCH_2, PG_arch_2);
fs/proc/page.c
253
u |= kpf_copy_bit(k, KPF_ARCH_3, PG_arch_3);
fs/smb/common/cifs_md4.c
51
#define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s))
fs/smb/common/cifs_md4.c
52
#define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (u32)0x5A827999,s))
fs/smb/common/cifs_md4.c
53
#define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (u32)0x6ED9EBA1,s))
fs/ubifs/key.h
103
static inline void ino_key_init_flash(const struct ubifs_info *c, void *k,
fs/ubifs/key.h
106
union ubifs_key *key = k;
fs/ubifs/key.h
110
memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8);
fs/ubifs/key.h
181
static inline void dent_key_init_flash(const struct ubifs_info *c, void *k,
fs/ubifs/key.h
185
union ubifs_key *key = k;
fs/ubifs/key.h
192
memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8);
fs/ubifs/key.h
233
static inline void xent_key_init_flash(const struct ubifs_info *c, void *k,
fs/ubifs/key.h
236
union ubifs_key *key = k;
fs/ubifs/key.h
243
memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8);
fs/ubifs/key.h
333
static inline int key_type_flash(const struct ubifs_info *c, const void *k)
fs/ubifs/key.h
335
const union ubifs_key *key = k;
fs/ubifs/key.h
345
static inline ino_t key_inum(const struct ubifs_info *c, const void *k)
fs/ubifs/key.h
347
const union ubifs_key *key = k;
fs/ubifs/key.h
357
static inline ino_t key_inum_flash(const struct ubifs_info *c, const void *k)
fs/ubifs/key.h
359
const union ubifs_key *key = k;
fs/ubifs/key.h
380
static inline uint32_t key_hash_flash(const struct ubifs_info *c, const void *k)
fs/ubifs/key.h
382
const union ubifs_key *key = k;
fs/ubifs/key.h
404
const void *k)
fs/ubifs/key.h
406
const union ubifs_key *key = k;
fs/ubifs/lpt.c
275
const int k = 32 - nrbits;
fs/ubifs/lpt.c
324
val <<= k;
fs/ubifs/lpt.c
325
val >>= k;
fs/ubifs/tnc.c
2823
int i, n, k, err = 0;
fs/ubifs/tnc.c
2861
for (i = n + 1, k = 0; i < znode->child_cnt; i++, k++) {
fs/ubifs/tnc.c
2874
if (k) {
fs/ubifs/tnc.c
2875
for (i = n + 1 + k; i < znode->child_cnt; i++)
fs/ubifs/tnc.c
2876
znode->zbranch[i - k] = znode->zbranch[i];
fs/ubifs/tnc.c
2877
znode->child_cnt -= k;
fs/udf/partition.c
153
int i, j, k, l;
fs/udf/partition.c
182
for (k = 0; k < reallocationTableLen; k++) {
fs/udf/partition.c
183
struct sparingEntry *entry = &st->mapEntry[k];
fs/udf/partition.c
223
for (l = k; l < reallocationTableLen; l++) {
fs/udf/partition.c
239
memmove(&st->mapEntry[k + 1],
fs/udf/partition.c
240
&st->mapEntry[k],
fs/udf/partition.c
241
(l - k) *
fs/udf/partition.c
243
st->mapEntry[k] = mapEntry;
fs/udf/partition.c
252
st->mapEntry[k].mappedLocation) +
fs/ufs/balloc.c
572
for (k = count; k < uspi->s_fpb; k++) \
fs/ufs/balloc.c
573
if (fs32_to_cpu(sb, ucg->cg_frsum[k])) \
fs/ufs/balloc.c
583
unsigned oldcg, i, j, k, allocsize;
fs/xfs/libxfs/xfs_alloc.c
441
xfs_extlen_t k;
fs/xfs/libxfs/xfs_alloc.c
451
k = rlen % args->prod;
fs/xfs/libxfs/xfs_alloc.c
452
if (k == args->mod)
fs/xfs/libxfs/xfs_alloc.c
454
if (k > args->mod)
fs/xfs/libxfs/xfs_alloc.c
455
rlen = rlen - (k - args->mod);
fs/xfs/libxfs/xfs_alloc.c
457
rlen = rlen - args->prod + (args->mod - k);
fs/xfs/libxfs/xfs_format.h
1270
#define XFS_INO_MASK(k) (uint32_t)((1ULL << (k)) - 1)
fs/xfs/libxfs/xfs_format.h
1891
static inline xfs_fsblock_t nullstartblock(int k)
fs/xfs/libxfs/xfs_format.h
1893
ASSERT(k < (1 << STARTBLOCKVALBITS));
fs/xfs/libxfs/xfs_format.h
1894
return STARTBLOCKMASK | (k);
fs/xfs/xfs_log_priv.h
739
unsigned k = i % XLOG_CYCLE_DATA_SIZE;
fs/xfs/xfs_log_priv.h
741
return &rhead->h_ext[j - 1].xh_cycle_data[k];
include/asm-generic/uaccess.h
140
#define __put_user_fn(sz, u, k) __put_user_fn(sz, u, k)
include/asm-generic/uaccess.h
201
#define __get_user_fn(sz, u, k) __get_user_fn(sz, u, k)
include/asm-generic/uaccess.h
40
#define __get_user_fn(sz, u, k) __get_user_fn(sz, u, k)
include/asm-generic/uaccess.h
65
#define __put_user_fn(sz, u, k) __put_user_fn(sz, u, k)
include/crypto/aes.h
101
union aes_enckey_arch k;
include/crypto/twofish.h
18
u32 s[4][256], w[8], k[32];
include/drm/display/drm_hdcp.h
216
__be16 k;
include/drm/drm_edid.h
132
u8 k;
include/drm/intel/i915_hdcp_interface.h
538
__be16 k;
include/drm/intel/i915_hdcp_interface.h
97
u16 k;
include/kvm/arm_vgic.h
415
#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
include/kvm/arm_vgic.h
416
#define vgic_initialized(k) ((k)->arch.vgic.initialized)
include/kvm/arm_vgic.h
417
#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
include/kvm/arm_vgic.h
418
((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
include/linux/clk/renesas.h
109
} k;
include/linux/clk/renesas.h
129
s16 k;
include/linux/clk/renesas.h
164
.k = { .min = -32768, .max = 32767 }, \
include/linux/filter.h
1470
if (first->k == SKF_AD_OFF + SKF_AD_ALU_XOR_X)
include/linux/filter.h
1489
switch (ftest->k) {
include/linux/filter.h
1514
int k, unsigned int size);
include/linux/input/matrix_keypad.h
17
#define KEY_ROW(k) (((k) >> 24) & 0xff)
include/linux/input/matrix_keypad.h
18
#define KEY_COL(k) (((k) >> 16) & 0xff)
include/linux/input/matrix_keypad.h
19
#define KEY_VAL(k) ((k) & 0xffff)
include/linux/jhash.h
100
case 1: a += k[0];
include/linux/jhash.h
117
static inline u32 jhash2(const u32 *k, u32 length, u32 initval)
include/linux/jhash.h
126
a += k[0];
include/linux/jhash.h
127
b += k[1];
include/linux/jhash.h
128
c += k[2];
include/linux/jhash.h
131
k += 3;
include/linux/jhash.h
136
case 3: c += k[2]; fallthrough;
include/linux/jhash.h
137
case 2: b += k[1]; fallthrough;
include/linux/jhash.h
138
case 1: a += k[0];
include/linux/jhash.h
73
const u8 *k = key;
include/linux/jhash.h
80
a += get_unaligned((u32 *)k);
include/linux/jhash.h
81
b += get_unaligned((u32 *)(k + 4));
include/linux/jhash.h
82
c += get_unaligned((u32 *)(k + 8));
include/linux/jhash.h
85
k += 12;
include/linux/jhash.h
89
case 12: c += (u32)k[11]<<24; fallthrough;
include/linux/jhash.h
90
case 11: c += (u32)k[10]<<16; fallthrough;
include/linux/jhash.h
91
case 10: c += (u32)k[9]<<8; fallthrough;
include/linux/jhash.h
92
case 9: c += k[8]; fallthrough;
include/linux/jhash.h
93
case 8: b += (u32)k[7]<<24; fallthrough;
include/linux/jhash.h
94
case 7: b += (u32)k[6]<<16; fallthrough;
include/linux/jhash.h
95
case 6: b += (u32)k[5]<<8; fallthrough;
include/linux/jhash.h
96
case 5: b += k[4]; fallthrough;
include/linux/jhash.h
97
case 4: a += (u32)k[3]<<24; fallthrough;
include/linux/jhash.h
98
case 3: a += (u32)k[2]<<16; fallthrough;
include/linux/jhash.h
99
case 2: a += (u32)k[1]<<8; fallthrough;
include/linux/jump_label.h
343
#define static_key_enable_cpuslocked(k) static_key_enable((k))
include/linux/jump_label.h
344
#define static_key_disable_cpuslocked(k) static_key_disable((k))
include/linux/key.h
501
#define key_validate(k) 0
include/linux/key.h
502
#define key_serial(k) 0
include/linux/key.h
503
#define key_get(k) ({ NULL; })
include/linux/key.h
504
#define key_revoke(k) do { } while(0)
include/linux/key.h
505
#define key_invalidate(k) do { } while(0)
include/linux/key.h
506
#define key_put(k) do { } while(0)
include/linux/key.h
507
#define key_ref_put(k) do { } while(0)
include/linux/key.h
508
#define make_key_ref(k, p) NULL
include/linux/key.h
509
#define key_ref_to_ptr(k) NULL
include/linux/key.h
510
#define is_key_possessed(k) 0
include/linux/key.h
516
#define key_lookup(k) NULL
include/linux/klist.h
34
extern void klist_init(struct klist *k, void (*get)(struct klist_node *),
include/linux/klist.h
43
extern void klist_add_tail(struct klist_node *n, struct klist *k);
include/linux/klist.h
44
extern void klist_add_head(struct klist_node *n, struct klist *k);
include/linux/klist.h
60
extern void klist_iter_init(struct klist *k, struct klist_iter *i);
include/linux/klist.h
61
extern void klist_iter_init_node(struct klist *k, struct klist_iter *i,
include/linux/kobject.h
186
static inline struct kset *kset_get(struct kset *k)
include/linux/kobject.h
188
return k ? to_kset(kobject_get(&k->kobj)) : NULL;
include/linux/kobject.h
191
static inline void kset_put(struct kset *k)
include/linux/kobject.h
193
kobject_put(&k->kobj);
include/linux/kthread.h
103
void free_kthread_struct(struct task_struct *k);
include/linux/kthread.h
104
void kthread_bind(struct task_struct *k, unsigned int cpu);
include/linux/kthread.h
105
void kthread_bind_mask(struct task_struct *k, const struct cpumask *mask);
include/linux/kthread.h
107
int kthread_stop(struct task_struct *k);
include/linux/kthread.h
108
int kthread_stop_put(struct task_struct *k);
include/linux/kthread.h
113
void *kthread_func(struct task_struct *k);
include/linux/kthread.h
114
void *kthread_data(struct task_struct *k);
include/linux/kthread.h
115
void *kthread_probe_data(struct task_struct *k);
include/linux/kthread.h
116
int kthread_park(struct task_struct *k);
include/linux/kthread.h
117
void kthread_unpark(struct task_struct *k);
include/linux/kthread.h
57
void kthread_set_per_cpu(struct task_struct *k, int cpu);
include/linux/kthread.h
58
bool kthread_is_per_cpu(struct task_struct *k);
include/linux/mempolicy.h
153
static inline void check_highest_zone(enum zone_type k)
include/linux/mempolicy.h
155
if (k > policy_zone && k != ZONE_MOVABLE)
include/linux/mempolicy.h
156
policy_zone = k;
include/linux/mempolicy.h
279
static inline void check_highest_zone(int k)
include/linux/mtio.h
31
static inline int put_user_mtget(void __user *u, struct mtget *k)
include/linux/mtio.h
34
.mt_type = k->mt_type,
include/linux/mtio.h
35
.mt_resid = k->mt_resid,
include/linux/mtio.h
36
.mt_dsreg = k->mt_dsreg,
include/linux/mtio.h
37
.mt_gstat = k->mt_gstat,
include/linux/mtio.h
38
.mt_erreg = k->mt_erreg,
include/linux/mtio.h
39
.mt_fileno = k->mt_fileno,
include/linux/mtio.h
40
.mt_blkno = k->mt_blkno,
include/linux/mtio.h
47
ret = copy_to_user(u, k, sizeof(*k));
include/linux/mtio.h
52
static inline int put_user_mtpos(void __user *u, struct mtpos *k)
include/linux/mtio.h
55
return put_user(k->mt_blkno, (u32 __user *)u);
include/linux/mtio.h
57
return put_user(k->mt_blkno, (long __user *)u);
include/linux/platform_data/sh_mmcif.h
126
int k;
include/linux/platform_data/sh_mmcif.h
139
for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
include/linux/platform_data/sh_mmcif.h
140
buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
include/linux/platform_data/sh_mmcif.h
150
unsigned long k;
include/linux/platform_data/sh_mmcif.h
167
for (k = 0; !ret && k < nr_blocks; k++)
include/linux/platform_data/sh_mmcif.h
168
ret = sh_mmcif_boot_do_read_single(base, first_block + k,
include/linux/platform_data/sh_mmcif.h
169
buf + (k * SH_MMCIF_BBS));
include/linux/sysfs.h
613
static inline int sysfs_rename_link_ns(struct kobject *k, struct kobject *t,
include/linux/sysfs.h
620
static inline void sysfs_delete_link(struct kobject *k, struct kobject *t,
include/linux/workqueue.h
232
#define __WORK_INIT_LOCKDEP_MAP(n, k) \
include/linux/workqueue.h
233
.lockdep_map = STATIC_LOCKDEP_MAP_INIT(n, k),
include/linux/workqueue.h
235
#define __WORK_INIT_LOCKDEP_MAP(n, k)
include/linux/ww_mutex.h
31
#define ww_mutex_base_init(l,n,k) __mutex_init(l,n,k)
include/linux/ww_mutex.h
35
#define ww_mutex_base_init(l,n,k) __rt_mutex_init(l,n,k)
include/linux/zutil.h
84
int k;
include/linux/zutil.h
89
k = len < NMAX ? len : NMAX;
include/linux/zutil.h
90
len -= k;
include/linux/zutil.h
91
while (k >= 16) {
include/linux/zutil.h
94
k -= 16;
include/linux/zutil.h
96
if (k != 0) do {
include/linux/zutil.h
99
} while (--k);
include/net/llc_conn.h
55
u8 k; /* tx window size; max = 127 */
include/net/xfrm.h
1894
const struct xfrm_kmaddress *k,
include/net/xfrm.h
1906
struct xfrm_kmaddress *k, struct net *net,
include/net/xfrm.h
717
const struct xfrm_kmaddress *k,
include/sound/soc-topology.h
101
struct snd_kcontrol *k, int event);
include/trace/events/bcache.h
188
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
189
TP_ARGS(k)
include/trace/events/bcache.h
210
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
211
TP_ARGS(k)
include/trace/events/bcache.h
323
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
324
TP_ARGS(k)
include/trace/events/bcache.h
328
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
329
TP_ARGS(k)
include/trace/events/bcache.h
333
TP_PROTO(struct btree *b, struct bkey *k, unsigned op, unsigned status),
include/trace/events/bcache.h
334
TP_ARGS(b, k, op, status),
include/trace/events/bcache.h
350
__entry->inode = KEY_INODE(k);
include/trace/events/bcache.h
351
__entry->offset = KEY_OFFSET(k);
include/trace/events/bcache.h
352
__entry->size = KEY_SIZE(k);
include/trace/events/bcache.h
353
__entry->dirty = KEY_DIRTY(k);
include/trace/events/bcache.h
42
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
43
TP_ARGS(k),
include/trace/events/bcache.h
493
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
494
TP_ARGS(k)
include/trace/events/bcache.h
498
TP_PROTO(struct bkey *k),
include/trace/events/bcache.h
499
TP_ARGS(k)
include/trace/events/bcache.h
53
__entry->inode = KEY_INODE(k);
include/trace/events/bcache.h
54
__entry->offset = KEY_OFFSET(k);
include/trace/events/bcache.h
55
__entry->size = KEY_SIZE(k);
include/trace/events/bcache.h
56
__entry->dirty = KEY_DIRTY(k);
include/uapi/drm/drm_fourcc.h
1012
#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
include/uapi/drm/drm_fourcc.h
1015
(((k) & 0xff) << 12) | \
include/uapi/linux/filter.h
28
__u32 k; /* Generic multiuse field */
include/uapi/linux/filter.h
49
#define BPF_STMT(code, k) { (unsigned short)(code), 0, 0, k }
include/uapi/linux/filter.h
52
#define BPF_JUMP(code, k, jt, jf) { (unsigned short)(code), jt, jf, k }
include/uapi/linux/gsmmux.h
140
__u32 k;
include/uapi/linux/gsmmux.h
56
unsigned int k;
include/uapi/linux/map_to_14segment.h
107
#define _SEG14(sym, a, b, c, d, e, f, g1, g2, h, j, k, l, m, n) \
include/uapi/linux/map_to_14segment.h
113
k << BIT_SEG14_J | l << BIT_SEG14_K | \
include/uapi/misc/xilinx_sdfec.h
172
__u32 k;
io_uring/bpf_filter.c
182
u32 k = ftest->k;
io_uring/bpf_filter.c
188
if (k >= sizeof(struct io_uring_bpf_ctx) || k & 3)
io_uring/bpf_filter.c
193
ftest->k = sizeof(struct io_uring_bpf_ctx);
io_uring/bpf_filter.c
197
ftest->k = sizeof(struct io_uring_bpf_ctx);
kernel/audit.h
315
#define audit_to_watch(k, p, l, o) (-EINVAL)
kernel/audit.h
316
#define audit_add_watch(k, l) (-EINVAL)
kernel/audit.h
317
#define audit_remove_watch_rule(k) BUG()
kernel/audit.h
321
#define audit_alloc_mark(k, p, l) (ERR_PTR(-EINVAL))
kernel/audit.h
324
#define audit_remove_mark_rule(k) do { } while (0)
kernel/bpf/core.c
78
void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb, int k, unsigned int size)
kernel/bpf/core.c
82
if (k >= SKF_NET_OFF) {
kernel/bpf/core.c
83
ptr = skb_network_header(skb) + k - SKF_NET_OFF;
kernel/bpf/core.c
84
} else if (k >= SKF_LL_OFF) {
kernel/bpf/core.c
87
ptr = skb_mac_header(skb) + k - SKF_LL_OFF;
kernel/bpf/devmap.c
848
u32 k = *(u32 *)key;
kernel/bpf/devmap.c
850
if (k >= map->max_entries)
kernel/bpf/devmap.c
853
old_dev = unrcu_pointer(xchg(&dtab->netdev_map[k], NULL));
kernel/bpf/devmap.c
865
u32 k = *(u32 *)key;
kernel/bpf/devmap.c
871
old_dev = __dev_map_hash_lookup_elem(map, k);
kernel/bpf/tnum.c
290
u8 k;
kernel/bpf/tnum.c
307
k = fls64(p); /* k is the most-significant 0-to-1 flip */
kernel/bpf/tnum.c
308
q = U64_MAX << k;
kernel/bpf/tnum.c
315
k = fls64(p); /* k is the most-significant 1-to-0 flip */
kernel/bpf/tnum.c
316
q = U64_MAX << k;
kernel/bpf/tnum.c
321
u = v + (1ULL << k);
kernel/compat.c
113
unsigned long *k;
kernel/compat.c
120
k = cpumask_bits(new_mask);
kernel/compat.c
121
return compat_get_bitmap(k, user_mask_ptr, len * 8);
kernel/kexec_file.c
899
int i, k;
kernel/kexec_file.c
918
for (k = 0; k < sechdrs[i].sh_size/sizeof(Elf_Sym); k++) {
kernel/kexec_file.c
919
if (ELF_ST_BIND(syms[k].st_info) != STB_GLOBAL)
kernel/kexec_file.c
922
if (strcmp(strtab + syms[k].st_name, name) != 0)
kernel/kexec_file.c
925
if (syms[k].st_shndx == SHN_UNDEF ||
kernel/kexec_file.c
926
syms[k].st_shndx >= ehdr->e_shnum) {
kernel/kexec_file.c
928
name, syms[k].st_shndx);
kernel/kexec_file.c
933
return &syms[k];
kernel/kthread.c
122
void free_kthread_struct(struct task_struct *k)
kernel/kthread.c
129
kthread = to_kthread(k);
kernel/kthread.c
136
k->worker_private = NULL;
kernel/kthread.c
154
static bool __kthread_should_park(struct task_struct *k)
kernel/kthread.c
156
return test_bit(KTHREAD_SHOULD_PARK, &to_kthread(k)->flags);
kernel/kthread.c
636
void kthread_set_per_cpu(struct task_struct *k, int cpu)
kernel/kthread.c
638
struct kthread *kthread = to_kthread(k);
kernel/kthread.c
642
WARN_ON_ONCE(!(k->flags & PF_NO_SETAFFINITY));
kernel/kthread.c
670
void kthread_unpark(struct task_struct *k)
kernel/kthread.c
672
struct kthread *kthread = to_kthread(k);
kernel/kthread.c
681
__kthread_bind(k, kthread->cpu, TASK_PARKED);
kernel/kthread.c
687
wake_up_state(k, TASK_PARKED);
kernel/kthread.c
703
int kthread_park(struct task_struct *k)
kernel/kthread.c
705
struct kthread *kthread = to_kthread(k);
kernel/kthread.c
707
if (WARN_ON(k->flags & PF_EXITING))
kernel/kthread.c
714
if (k != current) {
kernel/kthread.c
715
wake_up_process(k);
kernel/kthread.c
725
WARN_ON_ONCE(!wait_task_inactive(k, TASK_PARKED));
kernel/kthread.c
747
int kthread_stop(struct task_struct *k)
kernel/kthread.c
752
trace_sched_kthread_stop(k);
kernel/kthread.c
754
get_task_struct(k);
kernel/kthread.c
755
kthread = to_kthread(k);
kernel/kthread.c
757
kthread_unpark(k);
kernel/kthread.c
758
set_tsk_thread_flag(k, TIF_NOTIFY_SIGNAL);
kernel/kthread.c
759
wake_up_process(k);
kernel/kthread.c
762
put_task_struct(k);
kernel/kthread.c
777
int kthread_stop_put(struct task_struct *k)
kernel/kthread.c
781
ret = kthread_stop(k);
kernel/kthread.c
782
put_task_struct(k);
kernel/kthread.c
82
static inline struct kthread *to_kthread(struct task_struct *k)
kernel/kthread.c
84
WARN_ON(!(k->flags & PF_KTHREAD));
kernel/kthread.c
85
return k->worker_private;
kernel/kthread.c
881
struct kthread *k;
kernel/kthread.c
894
list_for_each_entry(k, &kthread_affinity_list, affinity_node) {
kernel/kthread.c
895
if (WARN_ON_ONCE((k->task->flags & PF_NO_SETAFFINITY) ||
kernel/kthread.c
896
kthread_is_per_cpu(k->task))) {
kernel/kthread.c
913
if (force || k->preferred_affinity || k->node != NUMA_NO_NODE) {
kernel/kthread.c
914
kthread_fetch_affinity(k, affinity);
kernel/kthread.c
915
set_cpus_allowed_ptr(k->task, affinity);
kernel/locking/lockdep.c
1224
struct lock_class_key *k;
kernel/locking/lockdep.c
1234
hlist_for_each_entry_rcu(k, hash_head, hash_entry) {
kernel/locking/lockdep.c
1235
if (WARN_ON_ONCE(k == key))
kernel/locking/lockdep.c
1251
struct lock_class_key *k;
kernel/locking/lockdep.c
1268
hlist_for_each_entry_rcu(k, hash_head, hash_entry) {
kernel/locking/lockdep.c
1269
if (k == key) {
kernel/locking/lockdep.c
6585
struct lock_class_key *k;
kernel/locking/lockdep.c
6599
hlist_for_each_entry_rcu(k, hash_head, hash_entry) {
kernel/locking/lockdep.c
6600
if (k == key) {
kernel/locking/lockdep.c
6601
hlist_del_rcu(&k->hash_entry);
kernel/power/hibernate.c
295
unsigned int k;
kernel/power/hibernate.c
303
k = nr_pages * (PAGE_SIZE / 1024);
kernel/power/hibernate.c
304
kps = (k * 100) / centisecs;
kernel/power/hibernate.c
306
msg, k, centisecs / 100, centisecs % 100, kps / 1000,
kernel/power/swap.c
1044
handle->k = 0;
kernel/power/swap.c
1058
offset = handle->cur->entries[handle->k];
kernel/power/swap.c
1067
if (++handle->k >= MAP_PAGE_ENTRIES) {
kernel/power/swap.c
1068
handle->k = 0;
kernel/power/swap.c
1349
handle->cur->entries[handle->k]) {
kernel/power/swap.c
414
handle->k = 0;
kernel/power/swap.c
437
handle->cur->entries[handle->k++] = offset;
kernel/power/swap.c
438
if (handle->k >= MAP_PAGE_ENTRIES) {
kernel/power/swap.c
448
handle->k = 0;
kernel/power/swap.c
98
unsigned int k;
kernel/printk/printk.c
1317
unsigned long long k;
kernel/printk/printk.c
1325
k = (unsigned long long)loops_per_msec * boot_delay;
kernel/printk/printk.c
1328
while (k) {
kernel/printk/printk.c
1329
k--;
kernel/range.c
128
int i, j, k = az - 1, nr_range = az;
kernel/range.c
130
for (i = 0; i < k; i++) {
kernel/range.c
133
for (j = k; j > i; j--) {
kernel/range.c
135
k = j;
kernel/range.c
141
range[i].start = range[k].start;
kernel/range.c
142
range[i].end = range[k].end;
kernel/range.c
143
range[k].start = 0;
kernel/range.c
144
range[k].end = 0;
kernel/range.c
145
k--;
kernel/sched/topology.c
2078
int k;
kernel/sched/topology.c
2085
for_each_cpu_node_but(k, offline_node) {
kernel/sched/topology.c
2087
(arch_sched_node_distance(j, k) !=
kernel/sched/topology.c
2088
arch_sched_node_distance(k, j)))
kernel/sched/topology.c
2091
if (arch_sched_node_distance(j, k) >
kernel/sched/topology.c
2095
cpumask_or(mask, mask, cpumask_of_node(k));
kernel/sched/topology.c
2268
struct __cmp_key *k = (struct __cmp_key *)a;
kernel/sched/topology.c
2270
if (cpumask_weight_and(k->cpus, cur_hop[k->node]) <= k->cpu)
kernel/sched/topology.c
2273
if (b == k->masks) {
kernel/sched/topology.c
2274
k->w = 0;
kernel/sched/topology.c
2279
k->w = cpumask_weight_and(k->cpus, prev_hop[k->node]);
kernel/sched/topology.c
2280
if (k->w <= k->cpu)
kernel/sched/topology.c
2298
struct __cmp_key k = { .cpus = cpus, .cpu = cpu };
kernel/sched/topology.c
2309
k.node = node;
kernel/sched/topology.c
2311
k.masks = rcu_dereference(sched_domains_numa_masks);
kernel/sched/topology.c
2312
if (!k.masks)
kernel/sched/topology.c
2315
hop_masks = bsearch(&k, k.masks, sched_domains_numa_levels, sizeof(k.masks[0]), hop_cmp);
kernel/sched/topology.c
2318
hop = hop_masks - k.masks;
kernel/sched/topology.c
2321
cpumask_nth_and_andnot(cpu - k.w, cpus, k.masks[hop][node], k.masks[hop-1][node]) :
kernel/sched/topology.c
2322
cpumask_nth_and(cpu, cpus, k.masks[0][node]);
kernel/seccomp.c
284
u32 k = ftest->k;
kernel/seccomp.c
290
if (k >= sizeof(struct seccomp_data) || k & 3)
kernel/seccomp.c
295
ftest->k = sizeof(struct seccomp_data);
kernel/seccomp.c
299
ftest->k = sizeof(struct seccomp_data);
kernel/seccomp.c
787
u32 k = insn->k;
kernel/seccomp.c
791
switch (k) {
kernel/seccomp.c
805
return k == SECCOMP_RET_ALLOW;
kernel/seccomp.c
807
pc += insn->k;
kernel/seccomp.c
815
op_res = reg_value == k;
kernel/seccomp.c
818
op_res = reg_value >= k;
kernel/seccomp.c
821
op_res = reg_value > k;
kernel/seccomp.c
824
op_res = !!(reg_value & k);
kernel/seccomp.c
834
reg_value &= k;
kernel/signal.c
4303
struct k_sigaction *k;
kernel/signal.c
4309
k = &p->sighand->action[sig-1];
kernel/signal.c
4312
if (k->sa.sa_flags & SA_IMMUTABLE) {
kernel/signal.c
4317
*oact = *k;
kernel/signal.c
4338
bool was_ignored = k->sa.sa_handler == SIG_IGN;
kernel/signal.c
4342
*k = *act;
kernel/trace/trace_events_hist.c
4740
unsigned int i, j, k;
kernel/trace/trace_events_hist.c
4787
for (j = 1, k = 1; j < hist_data->n_fields; j++) {
kernel/trace/trace_events_hist.c
4794
idx = k++;
kernel/user_namespace.c
251
static int cmp_map_id(const void *k, const void *e)
kernel/user_namespace.c
254
const struct idmap_key *key = k;
lib/bch.c
1079
const unsigned int k = 1 << deg(poly);
lib/bch.c
1082
if (k != (1u << GF_M(bch)))
lib/bch.c
1092
if (x & k)
lib/bch.c
418
int k, pp = -1;
lib/bch.c
431
k = 2*i-pp;
lib/bch.c
438
elp->c[j+k] ^= a_pow(bch, tmp+l);
lib/bch.c
442
tmp = pelp->deg+k;
lib/bch.c
470
int rem, c, r, p, k, param[BCH_MAX_M];
lib/bch.c
472
k = 0;
lib/bch.c
478
p = c-k;
lib/bch.c
497
param[k++] = c;
lib/bch.c
502
if (k > 0) {
lib/bch.c
503
p = k;
lib/bch.c
505
if ((r > m-1-k) && rows[r])
lib/bch.c
514
if (nsol != (1 << k))
lib/bch.c
520
for (c = 0; c < k; c++)
lib/bch.c
542
int i, j, k;
lib/bch.c
547
k = a_log(bch, a);
lib/bch.c
553
(a ? bch->a_pow_tab[mod_s(bch, k)] : 0)^
lib/bch.c
556
k += 2;
lib/bch.c
563
for (k = 0; k < 16; k = (k+j+1) & ~j) {
lib/bch.c
564
t = ((rows[k] >> j)^rows[k+j]) & mask;
lib/bch.c
565
rows[k] ^= (t << j);
lib/bch.c
566
rows[k+j] ^= t;
lib/bch.c
818
static void compute_trace_bk_mod(struct bch_control *bch, int k,
lib/bch.c
828
z->c[1] = bch->a_pow_tab[k];
lib/bch.c
855
dbg("Tr(a^%d.X) mod f = %s\n", k, gf_poly_str(out));
lib/bch.c
861
static void factor_polynomial(struct bch_control *bch, int k, struct gf_poly *f,
lib/bch.c
876
compute_trace_bk_mod(bch, k, f, z, tk);
lib/bch.c
897
static int find_poly_roots(struct bch_control *bch, unsigned int k,
lib/bch.c
920
if (poly->deg && (k <= GF_M(bch))) {
lib/bch.c
921
factor_polynomial(bch, k, poly, &f1, &f2);
lib/bch.c
923
cnt += find_poly_roots(bch, k+1, f1, roots);
lib/bch.c
925
cnt += find_poly_roots(bch, k+1, f2, roots+cnt);
lib/bch.c
942
const unsigned int k = 8*len+bch->ecc_bits;
lib/bch.c
949
for (i = GF_N(bch)-k+1; i <= GF_N(bch); i++) {
lib/bitmap.c
105
if (!rem || off + k + 1 >= lim)
lib/bitmap.c
108
upper = src[off + k + 1];
lib/bitmap.c
109
if (off + k + 1 == lim - 1)
lib/bitmap.c
113
lower = src[off + k];
lib/bitmap.c
114
if (off + k == lim - 1)
lib/bitmap.c
117
dst[k] = lower | upper;
lib/bitmap.c
140
int k;
lib/bitmap.c
143
for (k = lim - off - 1; k >= 0; --k) {
lib/bitmap.c
150
if (rem && k > 0)
lib/bitmap.c
151
lower = src[k - 1] >> (BITS_PER_LONG - rem);
lib/bitmap.c
154
upper = src[k] << rem;
lib/bitmap.c
155
dst[k + off] = lower | upper;
lib/bitmap.c
232
unsigned int k;
lib/bitmap.c
236
for (k = 0; k < lim; k++)
lib/bitmap.c
237
result |= (dst[k] = bitmap1[k] & bitmap2[k]);
lib/bitmap.c
239
result |= (dst[k] = bitmap1[k] & bitmap2[k] &
lib/bitmap.c
248
unsigned int k;
lib/bitmap.c
251
for (k = 0; k < nr; k++)
lib/bitmap.c
252
dst[k] = bitmap1[k] | bitmap2[k];
lib/bitmap.c
259
unsigned int k;
lib/bitmap.c
262
for (k = 0; k < nr; k++)
lib/bitmap.c
263
dst[k] = bitmap1[k] ^ bitmap2[k];
lib/bitmap.c
270
unsigned int k;
lib/bitmap.c
274
for (k = 0; k < lim; k++)
lib/bitmap.c
275
result |= (dst[k] = bitmap1[k] & ~bitmap2[k]);
lib/bitmap.c
277
result |= (dst[k] = bitmap1[k] & ~bitmap2[k] &
lib/bitmap.c
287
unsigned int k;
lib/bitmap.c
290
for (k = 0; k < nr; k++)
lib/bitmap.c
291
dst[k] = (old[k] & ~mask[k]) | (new[k] & mask[k]);
lib/bitmap.c
298
unsigned int k, lim = bits/BITS_PER_LONG;
lib/bitmap.c
299
for (k = 0; k < lim; ++k)
lib/bitmap.c
300
if (bitmap1[k] & bitmap2[k])
lib/bitmap.c
304
if ((bitmap1[k] & bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits))
lib/bitmap.c
313
unsigned int k, lim = bits/BITS_PER_LONG;
lib/bitmap.c
314
for (k = 0; k < lim; ++k)
lib/bitmap.c
315
if (bitmap1[k] & ~bitmap2[k])
lib/bitmap.c
319
if ((bitmap1[k] & ~bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits))
lib/bitmap.c
40
unsigned int k, lim = bits/BITS_PER_LONG;
lib/bitmap.c
41
for (k = 0; k < lim; ++k)
lib/bitmap.c
42
if (bitmap1[k] != bitmap2[k])
lib/bitmap.c
46
if ((bitmap1[k] ^ bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits))
lib/bitmap.c
58
unsigned int k, lim = bits / BITS_PER_LONG;
lib/bitmap.c
61
for (k = 0; k < lim; ++k) {
lib/bitmap.c
62
if ((bitmap1[k] | bitmap2[k]) != bitmap3[k])
lib/bitmap.c
69
tmp = (bitmap1[k] | bitmap2[k]) ^ bitmap3[k];
lib/bitmap.c
75
unsigned int k, lim = BITS_TO_LONGS(bits);
lib/bitmap.c
76
for (k = 0; k < lim; ++k)
lib/bitmap.c
77
dst[k] = ~src[k];
lib/bitmap.c
95
unsigned k, lim = BITS_TO_LONGS(nbits);
lib/bitmap.c
98
for (k = 0; off + k < lim; ++k) {
lib/bootconfig.c
638
struct xbc_node *find_match_node(struct xbc_node *node, char *k)
lib/bootconfig.c
641
if (!strcmp(xbc_node_get_data(node), k))
lib/bootconfig.c
648
static int __init __xbc_add_key(char *k)
lib/bootconfig.c
652
if (!xbc_valid_keyword(k))
lib/bootconfig.c
653
return xbc_parse_error("Invalid keyword", k);
lib/bootconfig.c
659
node = find_match_node(xbc_nodes, k);
lib/bootconfig.c
665
node = find_match_node(child, k);
lib/bootconfig.c
672
node = xbc_add_child(k, XBC_KEY);
lib/bootconfig.c
679
static int __init __xbc_parse_keys(char *k)
lib/bootconfig.c
684
k = strim(k);
lib/bootconfig.c
685
while ((p = strchr(k, '.'))) {
lib/bootconfig.c
687
ret = __xbc_add_key(k);
lib/bootconfig.c
690
k = p;
lib/bootconfig.c
693
return __xbc_add_key(k);
lib/bootconfig.c
696
static int __init xbc_parse_kv(char **k, char *v, int op)
lib/bootconfig.c
703
ret = __xbc_parse_keys(*k);
lib/bootconfig.c
753
*k = next;
lib/bootconfig.c
758
static int __init xbc_parse_key(char **k, char *n)
lib/bootconfig.c
763
*k = strim(*k);
lib/bootconfig.c
764
if (**k != '\0') {
lib/bootconfig.c
765
ret = __xbc_parse_keys(*k);
lib/bootconfig.c
770
*k = n;
lib/bootconfig.c
775
static int __init xbc_open_brace(char **k, char *n)
lib/bootconfig.c
779
ret = __xbc_parse_keys(*k);
lib/bootconfig.c
782
*k = n;
lib/bootconfig.c
787
static int __init xbc_close_brace(char **k, char *n)
lib/bootconfig.c
791
ret = xbc_parse_key(k, n);
lib/crypto/aes.c
452
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/aes.c
456
aes_expandkey_generic(k->rndkeys, inv_k ? inv_k->inv_rndkeys : NULL,
lib/crypto/aes.c
464
aes_encrypt_generic(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/aes.c
483
aes_preparekey_arch(&enc_key->k, inv_k, in_key, key_len,
lib/crypto/arc4.c
16
int i, j = 0, k = 0;
lib/crypto/arc4.c
27
j = (j + in_key[k] + a) & 0xff;
lib/crypto/arc4.c
30
if (++k >= key_len)
lib/crypto/arc4.c
31
k = 0;
lib/crypto/arm/aes.h
16
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/arm/aes.h
20
aes_expandkey_generic(k->rndkeys, inv_k ? inv_k->inv_rndkeys : NULL,
lib/crypto/arm/aes.h
33
__aes_arm_encrypt(key->k.rndkeys, key->nrounds, bounce_buf,
lib/crypto/arm/aes.h
38
__aes_arm_encrypt(key->k.rndkeys, key->nrounds, in, out);
lib/crypto/arm64/aes.h
105
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/arm64/aes.h
109
aes_expandkey_arm64(k->rndkeys, inv_k ? inv_k->inv_rndkeys : NULL,
lib/crypto/arm64/aes.h
136
__aes_ce_encrypt(key->k.rndkeys, out, in, key->nrounds);
lib/crypto/arm64/aes.h
138
__aes_arm64_encrypt(key->k.rndkeys, out, in, key->nrounds);
lib/crypto/chacha20poly1305-selftest.c
8888
size_t i, j, k, total_len;
lib/crypto/chacha20poly1305-selftest.c
9031
k = 0;
lib/crypto/chacha20poly1305-selftest.c
9034
sg_set_buf(&sg_src[k++], input, i);
lib/crypto/chacha20poly1305-selftest.c
9036
sg_set_buf(&sg_src[k++], input + i, j - i);
lib/crypto/chacha20poly1305-selftest.c
9038
sg_set_buf(&sg_src[k++], input + j, total_len - j);
lib/crypto/chacha20poly1305-selftest.c
9039
sg_init_marker(sg_src, k);
lib/crypto/chacha20poly1305-selftest.c
9056
for (k = 0; k < total_len - POLY1305_DIGEST_SIZE; ++k) {
lib/crypto/chacha20poly1305-selftest.c
9057
if (computed_output[k])
lib/crypto/chacha20poly1305-selftest.c
9063
for (k = 0; k < total_len - POLY1305_DIGEST_SIZE; ++k) {
lib/crypto/chacha20poly1305-selftest.c
9064
if (input[k])
lib/crypto/chacha20poly1305.c
103
chacha_init(&chacha_state, k, (u8 *)iv);
lib/crypto/chacha20poly1305.c
108
memzero_explicit(k, sizeof(k));
lib/crypto/chacha20poly1305.c
176
u32 k[CHACHA_KEY_WORDS];
lib/crypto/chacha20poly1305.c
180
chacha_load_key(k, key);
lib/crypto/chacha20poly1305.c
185
chacha_init(&chacha_state, k, (u8 *)iv);
lib/crypto/chacha20poly1305.c
191
memzero_explicit(k, sizeof(k));
lib/crypto/chacha20poly1305.c
21
static void chacha_load_key(u32 *k, const u8 *in)
lib/crypto/chacha20poly1305.c
227
u32 k[CHACHA_KEY_WORDS];
lib/crypto/chacha20poly1305.c
23
k[0] = get_unaligned_le32(in);
lib/crypto/chacha20poly1305.c
24
k[1] = get_unaligned_le32(in + 4);
lib/crypto/chacha20poly1305.c
241
chacha_load_key(b.k, key);
lib/crypto/chacha20poly1305.c
246
chacha_init(&chacha_state, b.k, (u8 *)b.iv);
lib/crypto/chacha20poly1305.c
25
k[2] = get_unaligned_le32(in + 8);
lib/crypto/chacha20poly1305.c
26
k[3] = get_unaligned_le32(in + 12);
lib/crypto/chacha20poly1305.c
27
k[4] = get_unaligned_le32(in + 16);
lib/crypto/chacha20poly1305.c
28
k[5] = get_unaligned_le32(in + 20);
lib/crypto/chacha20poly1305.c
29
k[6] = get_unaligned_le32(in + 24);
lib/crypto/chacha20poly1305.c
30
k[7] = get_unaligned_le32(in + 28);
lib/crypto/chacha20poly1305.c
36
u32 k[CHACHA_KEY_WORDS];
lib/crypto/chacha20poly1305.c
42
chacha_load_key(k, key);
lib/crypto/chacha20poly1305.c
45
chacha_init(chacha_state, k, nonce);
lib/crypto/chacha20poly1305.c
46
hchacha_block(chacha_state, k, 20);
lib/crypto/chacha20poly1305.c
48
chacha_init(chacha_state, k, iv);
lib/crypto/chacha20poly1305.c
50
memzero_explicit(k, sizeof(k));
lib/crypto/chacha20poly1305.c
95
u32 k[CHACHA_KEY_WORDS];
lib/crypto/chacha20poly1305.c
98
chacha_load_key(k, key);
lib/crypto/des.c
622
static unsigned long des_ekey(u32 *pe, const u8 *k)
lib/crypto/des.c
628
d = k[4]; d &= 0x0e; d <<= 4; d |= k[0] & 0x1e; d = pc1[d];
lib/crypto/des.c
629
c = k[5]; c &= 0x0e; c <<= 4; c |= k[1] & 0x1e; c = pc1[c];
lib/crypto/des.c
630
b = k[6]; b &= 0x0e; b <<= 4; b |= k[2] & 0x1e; b = pc1[b];
lib/crypto/des.c
631
a = k[7]; a &= 0x0e; a <<= 4; a |= k[3] & 0x1e; a = pc1[a];
lib/crypto/des.c
656
d = k[0]; d &= 0xe0; d >>= 4; d |= k[4] & 0xf0; d = pc1[d + 1];
lib/crypto/des.c
657
c = k[1]; c &= 0xe0; c >>= 4; c |= k[5] & 0xf0; c = pc1[c + 1];
lib/crypto/des.c
658
b = k[2]; b &= 0xe0; b >>= 4; b |= k[6] & 0xf0; b = pc1[b + 1];
lib/crypto/des.c
659
a = k[3]; a &= 0xe0; a >>= 4; a |= k[7] & 0xf0; a = pc1[a + 1];
lib/crypto/des.c
713
static void dkey(u32 *pe, const u8 *k)
lib/crypto/des.c
719
d = k[4]; d &= 0x0e; d <<= 4; d |= k[0] & 0x1e; d = pc1[d];
lib/crypto/des.c
720
c = k[5]; c &= 0x0e; c <<= 4; c |= k[1] & 0x1e; c = pc1[c];
lib/crypto/des.c
721
b = k[6]; b &= 0x0e; b <<= 4; b |= k[2] & 0x1e; b = pc1[b];
lib/crypto/des.c
722
a = k[7]; a &= 0x0e; a <<= 4; a |= k[3] & 0x1e; a = pc1[a];
lib/crypto/des.c
744
d = k[0]; d &= 0xe0; d >>= 4; d |= k[4] & 0xf0; d = pc1[d + 1];
lib/crypto/des.c
745
c = k[1]; c &= 0xe0; c >>= 4; c |= k[5] & 0xf0; c = pc1[c + 1];
lib/crypto/des.c
746
b = k[2]; b &= 0xe0; b >>= 4; b |= k[6] & 0xf0; b = pc1[b + 1];
lib/crypto/des.c
747
a = k[3]; a &= 0xe0; a >>= 4; a |= k[7] & 0xf0; a = pc1[a + 1];
lib/crypto/gf128mul.c
246
int i, j, k;
lib/crypto/gf128mul.c
267
for (k = 1; k < j; ++k)
lib/crypto/gf128mul.c
268
be128_xor(&t->t[i]->t[j + k],
lib/crypto/gf128mul.c
269
&t->t[i]->t[j], &t->t[i]->t[k]);
lib/crypto/gf128mul.c
327
int j, k;
lib/crypto/gf128mul.c
338
for (k = 1; k < j; ++k)
lib/crypto/gf128mul.c
339
be128_xor(&t->t[j + k], &t->t[j], &t->t[k]);
lib/crypto/mldsa.c
106
.k = 8,
lib/crypto/mldsa.c
360
static bool decode_hint_vector(u8 h[/* k * N */], int k, int omega, const u8 *y)
lib/crypto/mldsa.c
364
memset(h, 0, k * N);
lib/crypto/mldsa.c
365
for (int i = 0; i < k; i++) {
lib/crypto/mldsa.c
506
const struct mldsa_ring_elem *w1, int k)
lib/crypto/mldsa.c
511
if (k == 4) { /* ML-DSA-44? */
lib/crypto/mldsa.c
532
const int k = params->k, l = params->l;
lib/crypto/mldsa.c
553
kmalloc(sizeof(*ws) + (l * sizeof(ws->z[0])) + (k * N),
lib/crypto/mldsa.c
564
if (!decode_hint_vector(h, k, params->omega, sig))
lib/crypto/mldsa.c
590
for (int i = 0; i < k; i++) {
lib/crypto/mldsa.c
630
if (k == 4)
lib/crypto/mldsa.c
636
w1_enc_len = encode_w1(ws->w1_encoded, &ws->tmp, k);
lib/crypto/mldsa.c
73
u8 k; /* num rows in the matrix A */
lib/crypto/mldsa.c
84
.k = 4,
lib/crypto/mldsa.c
95
.k = 6,
lib/crypto/powerpc/aes.h
129
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/powerpc/aes.h
140
ret = aes_p8_set_encrypt_key(in_key, keybits, &k->p8);
lib/crypto/powerpc/aes.h
156
aes_expandkey_generic(k->rndkeys,
lib/crypto/powerpc/aes.h
160
k->p8.nrounds = 0;
lib/crypto/powerpc/aes.h
171
likely(is_vsx_format(&key->k.p8) && may_use_simd())) {
lib/crypto/powerpc/aes.h
175
aes_p8_encrypt(in, out, &key->k.p8);
lib/crypto/powerpc/aes.h
179
} else if (unlikely(is_vsx_format(&key->k.p8))) {
lib/crypto/powerpc/aes.h
189
&key->k.p8.rndkeys[i], false);
lib/crypto/powerpc/aes.h
192
aes_encrypt_generic(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/powerpc/aes.h
45
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/powerpc/aes.h
50
ppc_expand_key_128(k->spe_enc_key, in_key);
lib/crypto/powerpc/aes.h
52
ppc_expand_key_192(k->spe_enc_key, in_key);
lib/crypto/powerpc/aes.h
54
ppc_expand_key_256(k->spe_enc_key, in_key);
lib/crypto/powerpc/aes.h
57
ppc_generate_decrypt_key(inv_k->spe_dec_key, k->spe_enc_key,
lib/crypto/powerpc/aes.h
66
ppc_encrypt_aes(out, in, key->k.spe_enc_key, key->nrounds / 2 - 1);
lib/crypto/riscv/aes.h
18
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/riscv/aes.h
22
aes_expandkey_generic(k->rndkeys, inv_k ? inv_k->inv_rndkeys : NULL,
lib/crypto/riscv/aes.h
32
aes_encrypt_zvkned(key->k.rndkeys, key->len, out, in);
lib/crypto/riscv/aes.h
35
aes_encrypt_generic(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/riscv/aes.h
49
aes_decrypt_zvkned(key->k.rndkeys, key->len, out, in);
lib/crypto/s390/aes.h
20
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/s390/aes.h
26
memcpy(k->raw_key, in_key, AES_KEYSIZE_128);
lib/crypto/s390/aes.h
31
memcpy(k->raw_key, in_key, AES_KEYSIZE_192);
lib/crypto/s390/aes.h
36
memcpy(k->raw_key, in_key, AES_KEYSIZE_256);
lib/crypto/s390/aes.h
40
aes_expandkey_generic(k->rndkeys, inv_k ? inv_k->inv_rndkeys : NULL,
lib/crypto/s390/aes.h
51
(void *)key->k.raw_key, out, in,
lib/crypto/s390/aes.h
58
(void *)key->k.raw_key, out, in,
lib/crypto/s390/aes.h
65
(void *)key->k.raw_key, out, in,
lib/crypto/s390/aes.h
79
aes_encrypt_generic(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/sparc/aes.h
101
aes_encrypt_generic(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/sparc/aes.h
109
aes_sparc64_decrypt_128(key->k.sparc_rndkeys, input, output);
lib/crypto/sparc/aes.h
111
aes_sparc64_decrypt_192(key->k.sparc_rndkeys, input, output);
lib/crypto/sparc/aes.h
113
aes_sparc64_decrypt_256(key->k.sparc_rndkeys, input, output);
lib/crypto/sparc/aes.h
47
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/sparc/aes.h
56
k->sparc_rndkeys, key_len);
lib/crypto/sparc/aes.h
60
k->sparc_rndkeys, key_len);
lib/crypto/sparc/aes.h
69
aes_expandkey_generic(k->rndkeys,
lib/crypto/sparc/aes.h
79
aes_sparc64_encrypt_128(key->k.sparc_rndkeys, input, output);
lib/crypto/sparc/aes.h
81
aes_sparc64_encrypt_192(key->k.sparc_rndkeys, input, output);
lib/crypto/sparc/aes.h
83
aes_sparc64_encrypt_256(key->k.sparc_rndkeys, input, output);
lib/crypto/tests/mldsa_kunit.c
148
const int k = params[tv->alg].k;
lib/crypto/tests/mldsa_kunit.c
151
u8 *hintvec = &sig[tv->sig_len - omega - k];
lib/crypto/tests/mldsa_kunit.c
159
hintvec[omega + k - 1] = omega + 1;
lib/crypto/tests/mldsa_kunit.c
166
KUNIT_ASSERT_GE(test, hintvec[omega + k - 2], 1);
lib/crypto/tests/mldsa_kunit.c
167
hintvec[omega + k - 1] = hintvec[omega + k - 2] - 1;
lib/crypto/tests/mldsa_kunit.c
18
int k;
lib/crypto/tests/mldsa_kunit.c
191
KUNIT_ASSERT_LT(test, hintvec[omega + k - 1], omega);
lib/crypto/tests/mldsa_kunit.c
27
.k = 4,
lib/crypto/tests/mldsa_kunit.c
36
.k = 6,
lib/crypto/tests/mldsa_kunit.c
45
.k = 8,
lib/crypto/x86/aes.h
32
static void aes_preparekey_arch(union aes_enckey_arch *k,
lib/crypto/x86/aes.h
36
u32 *rndkeys = k->rndkeys;
lib/crypto/x86/aes.h
58
aes_encrypt_aesni(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/x86/aes.h
61
aes_encrypt_generic(key->k.rndkeys, key->nrounds, out, in);
lib/crypto/x86/curve25519.h
1533
int i, j, k;
lib/crypto/x86/curve25519.h
1563
k = (64 * i + j - 3);
lib/crypto/x86/curve25519.h
1569
fmul(c, &table_ladder[4 * k], b, ef);
lib/decompress_bunzip2.c
162
i, j, k, t, runPos, symCount, symTotal, nSelectors, *byteCount;
lib/decompress_bunzip2.c
199
k = get_bits(bd, 16);
lib/decompress_bunzip2.c
201
if (k&(1 << (15-j)))
lib/decompress_bunzip2.c
259
k = get_bits(bd, 2);
lib/decompress_bunzip2.c
260
if (k < 2) {
lib/decompress_bunzip2.c
266
t += (((k+1)&2)-1);
lib/decompress_bunzip2.c
490
k = j+byteCount[i];
lib/decompress_bunzip2.c
492
j = k;
lib/inflate.c
1041
register unsigned k; /* number of bits in bit buffer */
lib/inflate.c
1047
k = bk;
lib/inflate.c
1064
bk = k;
lib/inflate.c
1154
int k; /* byte being shifted into crc apparatus */
lib/inflate.c
1169
for (k = i | 256; k != 1; k >>= 1)
lib/inflate.c
1172
if (k & 1)
lib/inflate.c
234
#define NEEDBITS(n) {while(k<(n)){b|=((ulg)NEXTBYTE())<<k;k+=8;}}
lib/inflate.c
235
#define DUMPBITS(n) {b>>=(n);k-=(n);}
lib/inflate.c
343
register int k; /* number of bits in current code */
lib/inflate.c
397
k = j; /* minimum code length */
lib/inflate.c
454
for (; k <= g; k++)
lib/inflate.c
457
a = c[k];
lib/inflate.c
463
while (k > w + l)
lib/inflate.c
471
if ((f = 1 << (j = k - w)) > a + 1) /* try a k-w bit table */
lib/inflate.c
475
xp = c + k;
lib/inflate.c
518
r.b = (uch)(k - w);
lib/inflate.c
535
f = 1 << (k - w);
lib/inflate.c
540
for (j = 1 << (k - 1); i & j; j >>= 1)
lib/inflate.c
604
register unsigned k; /* number of bits in bit buffer */
lib/inflate.c
609
k = bk;
lib/inflate.c
693
bk = k;
lib/inflate.c
710
register unsigned k; /* number of bits in bit buffer */
lib/inflate.c
716
k = bk;
lib/inflate.c
721
n = k & 7;
lib/inflate.c
752
bk = k;
lib/inflate.c
846
register unsigned k; /* number of bits in bit buffer */
lib/inflate.c
862
k = bk;
lib/inflate.c
972
bk = k;
lib/interval_tree_test.c
132
int i, j, k;
lib/interval_tree_test.c
160
for (k = 0; k < nsearches; k++) {
lib/interval_tree_test.c
162
if (!k) {
lib/interval_tree_test.c
242
int i, j, k;
lib/interval_tree_test.c
267
for (k = 0; k < nsearches; k++) {
lib/interval_tree_test.c
269
if (!k) {
lib/iov_iter.c
1029
long k;
lib/iov_iter.c
1034
for (k = 0, skip = i->iov_offset; k < i->nr_segs; k++, skip = 0) {
lib/iov_iter.c
1035
const struct iovec *iov = iter_iov(i) + k;
lib/iov_iter.c
1107
for (int k = 0; k < n; k++) {
lib/iov_iter.c
1108
struct folio *folio = page_folio(page + k);
lib/iov_iter.c
1109
p[k] = page + k;
lib/iov_iter.c
1615
int k = 0;
lib/iov_iter.c
1641
if (k) {
lib/iov_iter.c
1648
(*pages)[k++] = bv.bv_page;
lib/iov_iter.c
1651
if (k >= maxpages)
lib/iov_iter.c
1683
int k;
lib/iov_iter.c
1708
for (k = 0; k < maxpages; k++) {
lib/iov_iter.c
1716
p[k] = page;
lib/iov_iter.c
873
unsigned k;
lib/iov_iter.c
881
for (k = 0; k < i->nr_segs; k++) {
lib/iov_iter.c
882
const struct iovec *iov = iter_iov(i) + k;
lib/klist.c
101
static void add_tail(struct klist *k, struct klist_node *n)
lib/klist.c
103
spin_lock(&k->k_lock);
lib/klist.c
104
list_add_tail(&n->n_node, &k->k_list);
lib/klist.c
105
spin_unlock(&k->k_lock);
lib/klist.c
108
static void klist_node_init(struct klist *k, struct klist_node *n)
lib/klist.c
112
knode_set_klist(n, k);
lib/klist.c
113
if (k->get)
lib/klist.c
114
k->get(n);
lib/klist.c
122
void klist_add_head(struct klist_node *n, struct klist *k)
lib/klist.c
124
klist_node_init(k, n);
lib/klist.c
125
add_head(k, n);
lib/klist.c
134
void klist_add_tail(struct klist_node *n, struct klist *k)
lib/klist.c
136
klist_node_init(k, n);
lib/klist.c
137
add_tail(k, n);
lib/klist.c
148
struct klist *k = knode_klist(pos);
lib/klist.c
150
klist_node_init(k, n);
lib/klist.c
151
spin_lock(&k->k_lock);
lib/klist.c
153
spin_unlock(&k->k_lock);
lib/klist.c
164
struct klist *k = knode_klist(pos);
lib/klist.c
166
klist_node_init(k, n);
lib/klist.c
167
spin_lock(&k->k_lock);
lib/klist.c
169
spin_unlock(&k->k_lock);
lib/klist.c
211
struct klist *k = knode_klist(n);
lib/klist.c
212
void (*put)(struct klist_node *) = k->put;
lib/klist.c
214
spin_lock(&k->k_lock);
lib/klist.c
219
spin_unlock(&k->k_lock);
lib/klist.c
280
void klist_iter_init_node(struct klist *k, struct klist_iter *i,
lib/klist.c
283
i->i_klist = k;
lib/klist.c
297
void klist_iter_init(struct klist *k, struct klist_iter *i)
lib/klist.c
299
klist_iter_init_node(k, i, NULL);
lib/klist.c
84
void klist_init(struct klist *k, void (*get)(struct klist_node *),
lib/klist.c
87
INIT_LIST_HEAD(&k->k_list);
lib/klist.c
88
spin_lock_init(&k->k_lock);
lib/klist.c
89
k->get = get;
lib/klist.c
90
k->put = put;
lib/klist.c
94
static void add_head(struct klist *k, struct klist_node *n)
lib/klist.c
96
spin_lock(&k->k_lock);
lib/klist.c
97
list_add(&n->n_node, &k->k_list);
lib/klist.c
98
spin_unlock(&k->k_lock);
lib/kobject.c
812
void kset_init(struct kset *k)
lib/kobject.c
814
kobject_init_internal(&k->kobj);
lib/kobject.c
815
INIT_LIST_HEAD(&k->list);
lib/kobject.c
816
spin_lock_init(&k->list_lock);
lib/kobject.c
857
int kset_register(struct kset *k)
lib/kobject.c
861
if (!k)
lib/kobject.c
864
if (!k->kobj.ktype) {
lib/kobject.c
869
kset_init(k);
lib/kobject.c
870
err = kobject_add_internal(&k->kobj);
lib/kobject.c
872
kfree_const(k->kobj.name);
lib/kobject.c
874
k->kobj.name = NULL;
lib/kobject.c
877
kobject_uevent(&k->kobj, KOBJ_ADD);
lib/kobject.c
886
void kset_unregister(struct kset *k)
lib/kobject.c
888
if (!k)
lib/kobject.c
890
kobject_del(&k->kobj);
lib/kobject.c
891
kobject_put(&k->kobj);
lib/kobject.c
906
struct kobject *k;
lib/kobject.c
911
list_for_each_entry(k, &kset->list, entry) {
lib/kobject.c
912
if (kobject_name(k) && !strcmp(kobject_name(k), name)) {
lib/kobject.c
913
ret = kobject_get_unless_zero(k);
lib/kunit/executor.c
172
int i, j, k;
lib/kunit/executor.c
221
for (k = 0; k < filter_count; k++) {
lib/kunit/executor.c
223
parsed_filters[k], filter_action, err);
lib/kunit/executor.c
226
if (k > 0 || filter_glob) {
lib/oid_registry.c
31
unsigned i, j, k, hash;
lib/oid_registry.c
47
k = OID__NR;
lib/oid_registry.c
48
while (i < k) {
lib/oid_registry.c
49
j = (i + k) / 2;
lib/oid_registry.c
53
k = j;
lib/oid_registry.c
64
k = j;
lib/oid_registry.c
79
k = j;
lib/raid6/mktables.c
134
for (k = 0; k < 256; k++)
lib/raid6/mktables.c
135
if (exptbl[k] == (i + j)) {
lib/raid6/mktables.c
136
v = k;
lib/raid6/mktables.c
55
int i, j, k;
lib/raid6/mktables.c
72
for (k = 0; k < 8; k++)
lib/raid6/mktables.c
73
printf("0x%02x,%c", gfmul(i, j + k),
lib/raid6/mktables.c
74
(k == 7) ? '\n' : ' ');
lib/raid6/mktables.c
91
for (k = 0; k < 8; k++)
lib/raid6/mktables.c
92
printf("0x%02x,%c", gfmul(i, j + k),
lib/raid6/mktables.c
93
(k == 7) ? '\n' : ' ');
lib/raid6/mktables.c
97
for (k = 0; k < 8; k++)
lib/raid6/mktables.c
98
printf("0x%02x,%c", gfmul(i, (j + k) << 4),
lib/raid6/mktables.c
99
(k == 7) ? '\n' : ' ');
lib/reed_solomon/decode_rs.c
15
int i, j, r, k, pad;
lib/reed_solomon/decode_rs.c
200
for (i = 1, k = iprim - 1; i <= nn; i++, k = rs_modnn(rs, k + iprim)) {
lib/reed_solomon/decode_rs.c
211
if (k < pad) {
lib/reed_solomon/decode_rs.c
218
loc[count] = k;
lib/reed_solomon/decode_rs.c
295
k = (fcr + i) * prim * (nn-loc[j]-1);
lib/reed_solomon/decode_rs.c
296
tmp ^= alpha_to[rs_modnn(rs, index_of[b[j]] + k)];
lib/test_bpf.c
101
for (i = 0; i < len; i++, k--)
lib/test_bpf.c
102
insn[i] = __BPF_STMT(BPF_RET | BPF_K, k);
lib/test_bpf.c
143
__u32 k = prandom_u32_state(&rnd);
lib/test_bpf.c
145
insn[i] = __BPF_STMT(BPF_ALU | BPF_ADD | BPF_K, k);
lib/test_bpf.c
14824
if (fp[len].code != 0 || fp[len].k != 0)
lib/test_bpf.c
626
int imm, k;
lib/test_bpf.c
635
for (k = 0; k < ARRAY_SIZE(regs); k++) {
lib/test_bpf.c
636
s64 reg = regs[k];
lib/test_bpf.c
849
int count, len, k;
lib/test_bpf.c
872
for (k = 0; k < ARRAY_SIZE(sgn); k++) /* Sign combos */
lib/test_bpf.c
879
dst = value(di, db, sgn[k][0]);
lib/test_bpf.c
880
src = value(si, sb, sgn[k][1]);
lib/test_bpf.c
891
for (k = 0; k < ARRAY_SIZE(sgn); k++) /* Sign combos */
lib/test_bpf.c
897
dst = value(bt % dbits, db, sgn[k][0]);
lib/test_bpf.c
898
src = value(bt % sbits, sb, sgn[k][1]);
lib/test_bpf.c
94
__u32 k = ~0;
lib/test_rhashtable.c
274
unsigned int i, j, k;
lib/test_rhashtable.c
295
k = get_random_u32();
lib/test_rhashtable.c
298
rhl_test_objects[i].value.id = k;
lib/test_rhashtable.c
315
.id = k,
lib/test_ubsan.c
80
int i = 4, j = 4, k = -1;
lib/test_ubsan.c
89
OPTIMIZER_HIDE_VAR(k);
lib/test_ubsan.c
95
data.arr[k] = i;
lib/test_xarray.c
1252
unsigned long i, j, k;
lib/test_xarray.c
1267
for (k = 0; k < 100; k++) {
lib/test_xarray.c
1268
unsigned long index = k;
lib/test_xarray.c
1271
if (k <= j)
lib/test_xarray.c
1273
else if (k <= i)
lib/test_xarray.c
1278
index = k;
lib/test_xarray.c
1281
if (k <= j)
lib/test_xarray.c
1283
else if (k <= i)
lib/test_xarray.c
1322
unsigned long i, j, k;
lib/test_xarray.c
1328
for (k = 0; k < 100; k++) {
lib/test_xarray.c
1330
xas_for_each_marked(&xas, entry, k, XA_MARK_0)
lib/test_xarray.c
1332
if (j > k)
lib/test_xarray.c
2146
unsigned long i, j, k;
lib/test_xarray.c
2161
for (k = 0; k < order; k++) {
lib/test_xarray.c
2163
xas_set_order(&xas, j + (1 << k), k);
lib/test_xarray.c
653
unsigned long i, j, k;
lib/test_xarray.c
703
for (k = 0; k < max_order; k++) {
lib/test_xarray.c
704
void *entry = xa_load(xa, (1UL << k) - 1);
lib/test_xarray.c
705
if ((i < k) && (j < k))
lib/tests/string_kunit.c
100
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
22
unsigned i, j, k;
lib/tests/string_kunit.c
32
for (k = 0; k < 512; k++) {
lib/tests/string_kunit.c
33
v = p[k];
lib/tests/string_kunit.c
34
if (k < i) {
lib/tests/string_kunit.c
36
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
37
} else if (k < i + j) {
lib/tests/string_kunit.c
39
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
42
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
51
unsigned i, j, k;
lib/tests/string_kunit.c
61
for (k = 0; k < 512; k++) {
lib/tests/string_kunit.c
62
v = p[k];
lib/tests/string_kunit.c
63
if (k < i) {
lib/tests/string_kunit.c
65
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
66
} else if (k < i + j) {
lib/tests/string_kunit.c
68
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
71
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
80
unsigned i, j, k;
lib/tests/string_kunit.c
90
for (k = 0; k < 512; k++) {
lib/tests/string_kunit.c
91
v = p[k];
lib/tests/string_kunit.c
92
if (k < i) {
lib/tests/string_kunit.c
94
"i:%d j:%d k:%d", i, j, k);
lib/tests/string_kunit.c
95
} else if (k < i + j) {
lib/tests/string_kunit.c
97
"i:%d j:%d k:%d", i, j, k);
lib/tests/test_hash.c
112
int k;
lib/tests/test_hash.c
122
for (k = 1; k <= 32; k++) {
lib/tests/test_hash.c
123
u32 const m = ((u32)2 << (k-1)) - 1; /* Low k bits set */
lib/tests/test_hash.c
126
hash_or[0][k] |= params.h1 = hash_32(params.h0, k);
lib/tests/test_hash.c
129
params.h0, k, params.h1, m);
lib/tests/test_hash.c
132
hash_or[1][k] |= params.h1 = hash_64(h64, k);
lib/tests/test_hash.c
135
h64, k, params.h1, m);
lib/tests/test_hash.c
137
test_int_hash_64(test, &params, &m, &k);
lib/tests/test_hash.c
85
test_int_hash_64(struct kunit *test, struct test_hash_params *params, u32 const *m, int *k)
lib/tests/test_hash.c
87
params->h2 = hash_64_generic(*params->h64, *k);
lib/tests/test_hash.c
91
*params->h64, *k, params->h1, params->h2);
lib/tests/test_hash.c
95
*params->h64, *k, params->h1, *m);
lib/ts_kmp.c
77
unsigned int k, q;
lib/ts_kmp.c
80
for (k = 0, q = 1; q < len; q++) {
lib/ts_kmp.c
81
while (k > 0 && (icase ? toupper(pattern[k]) : pattern[k])
lib/ts_kmp.c
83
k = prefix_tbl[k-1];
lib/ts_kmp.c
84
if ((icase ? toupper(pattern[k]) : pattern[k])
lib/ts_kmp.c
86
k++;
lib/ts_kmp.c
87
prefix_tbl[q] = k;
lib/zlib_deflate/deftree.c
133
static void pqdownheap (deflate_state *s, ct_data *tree, int k);
lib/zlib_deflate/deftree.c
320
int k /* node to move down */
lib/zlib_deflate/deftree.c
323
int v = s->heap[k];
lib/zlib_deflate/deftree.c
324
int j = k << 1; /* left son of k */
lib/zlib_deflate/deftree.c
335
s->heap[k] = s->heap[j]; k = j;
lib/zlib_deflate/deftree.c
340
s->heap[k] = v;
mm/numa_memblks.c
241
int i, j, k;
mm/numa_memblks.c
303
for (k = 0; k < mi->nr_blks; k++) {
mm/numa_memblks.c
304
struct numa_memblk *bk = &mi->blk[k];
mm/numa_memblks.c
311
if (k < mi->nr_blks)
mm/slub.c
9397
static void kmem_cache_release(struct kobject *k)
mm/slub.c
9399
slab_kmem_cache_release(to_slab(k));
net/ax25/af_ax25.c
1954
int k;
net/ax25/af_ax25.c
1969
for (k=0; (ax25->digipeat != NULL) && (k < ax25->digipeat->ndigi); k++) {
net/ax25/af_ax25.c
1971
ax2asc(buf, &ax25->digipeat->calls[k]),
net/ax25/af_ax25.c
1972
ax25->digipeat->repeated[k]? "*":"");
net/ax25/af_ax25.c
370
unsigned int k;
net/ax25/af_ax25.c
387
for (k = 0; k < digi.ndigi; k++)
net/ax25/af_ax25.c
388
digi.calls[k] = ax25_ctl.digi_addr[k];
net/ax25/sysctl_net_ax25.c
149
int k;
net/ax25/sysctl_net_ax25.c
157
for (k = 0; k < AX25_MAX_VALUES; k++)
net/ax25/sysctl_net_ax25.c
158
table[k].data = &ax25_dev->values[k];
net/bluetooth/hci_core.c
1063
struct smp_ltk *k, *tmp;
net/bluetooth/hci_core.c
1065
list_for_each_entry_safe(k, tmp, &hdev->long_term_keys, list) {
net/bluetooth/hci_core.c
1066
list_del_rcu(&k->list);
net/bluetooth/hci_core.c
1067
kfree_rcu(k, rcu);
net/bluetooth/hci_core.c
1073
struct smp_irk *k, *tmp;
net/bluetooth/hci_core.c
1075
list_for_each_entry_safe(k, tmp, &hdev->identity_resolving_keys, list) {
net/bluetooth/hci_core.c
1076
list_del_rcu(&k->list);
net/bluetooth/hci_core.c
1077
kfree_rcu(k, rcu);
net/bluetooth/hci_core.c
1110
struct link_key *k;
net/bluetooth/hci_core.c
1113
list_for_each_entry_rcu(k, &hdev->link_keys, list) {
net/bluetooth/hci_core.c
1114
if (bacmp(bdaddr, &k->bdaddr) == 0) {
net/bluetooth/hci_core.c
1119
k->val)) {
net/bluetooth/hci_core.c
1122
&k->bdaddr);
net/bluetooth/hci_core.c
1126
return k;
net/bluetooth/hci_core.c
1185
struct smp_ltk *k;
net/bluetooth/hci_core.c
1188
list_for_each_entry_rcu(k, &hdev->long_term_keys, list) {
net/bluetooth/hci_core.c
1189
if (addr_type != k->bdaddr_type || bacmp(bdaddr, &k->bdaddr))
net/bluetooth/hci_core.c
1192
if (smp_ltk_is_sc(k) || ltk_role(k->type) == role) {
net/bluetooth/hci_core.c
1196
k->val)) {
net/bluetooth/hci_core.c
1199
&k->bdaddr);
net/bluetooth/hci_core.c
1203
return k;
net/bluetooth/hci_core.c
1393
struct smp_ltk *k, *tmp;
net/bluetooth/hci_core.c
1396
list_for_each_entry_safe(k, tmp, &hdev->long_term_keys, list) {
net/bluetooth/hci_core.c
1397
if (bacmp(bdaddr, &k->bdaddr) || k->bdaddr_type != bdaddr_type)
net/bluetooth/hci_core.c
1402
list_del_rcu(&k->list);
net/bluetooth/hci_core.c
1403
kfree_rcu(k, rcu);
net/bluetooth/hci_core.c
1412
struct smp_irk *k, *tmp;
net/bluetooth/hci_core.c
1414
list_for_each_entry_safe(k, tmp, &hdev->identity_resolving_keys, list) {
net/bluetooth/hci_core.c
1415
if (bacmp(bdaddr, &k->bdaddr) || k->addr_type != addr_type)
net/bluetooth/hci_core.c
1420
list_del_rcu(&k->list);
net/bluetooth/hci_core.c
1421
kfree_rcu(k, rcu);
net/bluetooth/hci_core.c
1427
struct smp_ltk *k;
net/bluetooth/hci_core.c
1450
list_for_each_entry_rcu(k, &hdev->long_term_keys, list) {
net/bluetooth/hci_core.c
1451
if (k->bdaddr_type == addr_type && !bacmp(bdaddr, &k->bdaddr)) {
net/bluetooth/smp.c
169
static int aes_cmac(struct crypto_shash *tfm, const u8 k[16], const u8 *m,
net/bluetooth/smp.c
184
swap_buf(k, tmp, 16);
net/bluetooth/smp.c
188
SMP_DBG("key %16phN", k);
net/bluetooth/smp.c
3515
const u8 k[16] = {
net/bluetooth/smp.c
3533
err = smp_c1(k, r, preq, pres, _iat, &ia, _rat, &ra, res);
net/bluetooth/smp.c
3545
const u8 k[16] = {
net/bluetooth/smp.c
3558
err = smp_s1(k, r1, r2, res);
net/bluetooth/smp.c
375
static int smp_e(const u8 *k, u8 *r)
net/bluetooth/smp.c
381
SMP_DBG("k %16phN r %16phN", k, r);
net/bluetooth/smp.c
384
swap_buf(k, tmp, 16);
net/bluetooth/smp.c
406
static int smp_c1(const u8 k[16],
net/bluetooth/smp.c
413
SMP_DBG("k %16phN r %16phN", k, r);
net/bluetooth/smp.c
431
err = smp_e(k, res);
net/bluetooth/smp.c
448
err = smp_e(k, res);
net/bluetooth/smp.c
455
static int smp_s1(const u8 k[16],
net/bluetooth/smp.c
464
err = smp_e(k, _r);
net/bridge/netfilter/ebtables.c
870
unsigned int i, j, k, udc_cnt;
net/bridge/netfilter/ebtables.c
898
k = 0; /* holds the total nr. of entries, should equal
net/bridge/netfilter/ebtables.c
904
&i, &j, &k, &udc_cnt);
net/bridge/netfilter/ebtables.c
912
if (k != newinfo->nentries)
net/ceph/ceph_hash.c
25
const unsigned char *k = (const unsigned char *)str;
net/ceph/ceph_hash.c
37
a = a + (k[0] + ((__u32)k[1] << 8) + ((__u32)k[2] << 16) +
net/ceph/ceph_hash.c
38
((__u32)k[3] << 24));
net/ceph/ceph_hash.c
39
b = b + (k[4] + ((__u32)k[5] << 8) + ((__u32)k[6] << 16) +
net/ceph/ceph_hash.c
40
((__u32)k[7] << 24));
net/ceph/ceph_hash.c
41
c = c + (k[8] + ((__u32)k[9] << 8) + ((__u32)k[10] << 16) +
net/ceph/ceph_hash.c
42
((__u32)k[11] << 24));
net/ceph/ceph_hash.c
44
k = k + 12;
net/ceph/ceph_hash.c
52
c = c + ((__u32)k[10] << 24);
net/ceph/ceph_hash.c
55
c = c + ((__u32)k[9] << 16);
net/ceph/ceph_hash.c
58
c = c + ((__u32)k[8] << 8);
net/ceph/ceph_hash.c
62
b = b + ((__u32)k[7] << 24);
net/ceph/ceph_hash.c
65
b = b + ((__u32)k[6] << 16);
net/ceph/ceph_hash.c
68
b = b + ((__u32)k[5] << 8);
net/ceph/ceph_hash.c
71
b = b + k[4];
net/ceph/ceph_hash.c
74
a = a + ((__u32)k[3] << 24);
net/ceph/ceph_hash.c
77
a = a + ((__u32)k[2] << 16);
net/ceph/ceph_hash.c
80
a = a + ((__u32)k[1] << 8);
net/ceph/ceph_hash.c
83
a = a + k[0];
net/core/dev.c
745
int k = stack->num_paths++;
net/core/dev.c
747
if (k >= NET_DEVICE_PATH_STACK_MAX)
net/core/dev.c
750
return &stack->path[k];
net/core/filter.c
1099
if (ftest->k == 0)
net/core/filter.c
1104
if (ftest->k >= 32)
net/core/filter.c
1112
if (ftest->k >= BPF_MEMWORDS)
net/core/filter.c
1120
if (ftest->k >= (unsigned int)(flen - pc - 1))
net/core/filter.c
1143
if (anc_found == false && ftest->k >= SKF_AD_OFF)
net/core/filter.c
372
switch (fp->k) {
net/core/filter.c
399
if (fp->k == SKF_AD_OFF + SKF_AD_IFINDEX)
net/core/filter.c
458
switch (fp->k) {
net/core/filter.c
505
int offset = fp->k;
net/core/filter.c
540
if (fp->k)
net/core/filter.c
705
*insn = BPF_RAW_INSN(fp->code, BPF_REG_A, BPF_REG_X, 0, fp->k);
net/core/filter.c
731
target = i + fp->k + 1;
net/core/filter.c
744
if (BPF_SRC(fp->code) == BPF_K && (int) fp->k < 0) {
net/core/filter.c
749
*insn++ = BPF_MOV32_IMM(BPF_REG_TMP, fp->k);
net/core/filter.c
756
insn->imm = fp->k;
net/core/filter.c
805
.k = fp->k,
net/core/filter.c
834
0, fp->k);
net/core/filter.c
841
stack_off = fp->k * 4 + 4;
net/core/filter.c
856
stack_off = fp->k * 4 + 4;
net/core/filter.c
866
BPF_REG_A : BPF_REG_X, fp->k);
net/core/filter.c
890
*insn = BPF_LDX_MEM(BPF_W, BPF_REG_A, BPF_REG_CTX, fp->k);
net/core/filter.c
955
memvalid |= (1 << filter[pc].k);
net/core/filter.c
959
if (!(memvalid & (1 << filter[pc].k))) {
net/core/filter.c
966
masks[pc + 1 + filter[pc].k] &= memvalid;
net/core/skbuff.c
2875
int i, k, eat = (skb->tail + delta) - skb->end;
net/core/skbuff.c
2964
k = 0;
net/core/skbuff.c
2972
skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
net/core/skbuff.c
2982
k++;
net/core/skbuff.c
2985
skb_shinfo(skb)->nr_frags = k;
net/core/skbuff.c
4180
int i, k = 0;
net/core/skbuff.c
4192
skb_shinfo(skb1)->frags[k] = skb_shinfo(skb)->frags[i];
net/core/skbuff.c
4209
k++;
net/core/skbuff.c
4214
skb_shinfo(skb1)->nr_frags = k;
net/core/skbuff.c
6920
int i, k = 0;
net/core/skbuff.c
6945
shinfo->frags[k] = skb_shinfo(skb)->frags[i];
net/core/skbuff.c
6960
k++;
net/core/skbuff.c
6964
shinfo->nr_frags = k;
net/core/skbuff.c
6969
if (k == 0 && pskb_carve_frag_list(shinfo, off - pos, gfp_mask)) {
net/core/sock.c
1087
unsigned int num_tokens, i, j, k, netmem_num = 0;
net/core/sock.c
1124
for (k = 0; k < netmem_num; k++)
net/core/sock.c
1125
WARN_ON_ONCE(!napi_pp_put_page(netmems[k]));
net/core/sock.c
1135
for (k = 0; k < netmem_num; k++)
net/core/sock.c
1136
WARN_ON_ONCE(!napi_pp_put_page(netmems[k]));
net/core/xdp.c
42
const u32 *k = data;
net/core/xdp.c
43
const u32 key = *k;
net/ipv4/arp.c
1422
int k, j;
net/ipv4/arp.c
1434
for (k = 0, j = 0; k < HBUFFERLEN - 3 && j < dev->addr_len; j++) {
net/ipv4/arp.c
1435
hbuffer[k++] = hex_asc_hi(n->ha[j]);
net/ipv4/arp.c
1436
hbuffer[k++] = hex_asc_lo(n->ha[j]);
net/ipv4/arp.c
1437
hbuffer[k++] = ':';
net/ipv4/arp.c
1439
if (k != 0)
net/ipv4/arp.c
1440
--k;
net/ipv4/arp.c
1441
hbuffer[k] = 0;
net/ipv4/fib_trie.c
555
unsigned long j, k;
net/ipv4/fib_trie.c
602
for (k = child_length(inode), j = k / 2; j;) {
net/ipv4/fib_trie.c
603
put_child(node1, --j, get_child(inode, --k));
net/ipv4/fib_trie.c
605
put_child(node1, --j, get_child(inode, --k));
net/ipv4/tcp.c
2505
int err, k;
net/ipv4/tcp.c
2514
for (k = 0; k < max_frags; k++) {
net/ipv4/tcp.c
2515
err = __xa_alloc(&sk->sk_user_frags, &p->tokens[k],
net/ipv4/tcp.c
2523
p->max = k;
net/ipv4/tcp.c
2525
return k ? 0 : err;
net/ipv4/tcp_output.c
1919
int i, k, eat;
net/ipv4/tcp_output.c
1923
k = 0;
net/ipv4/tcp_output.c
1932
shinfo->frags[k] = shinfo->frags[i];
net/ipv4/tcp_output.c
1934
skb_frag_off_add(&shinfo->frags[k], eat);
net/ipv4/tcp_output.c
1935
skb_frag_size_sub(&shinfo->frags[k], eat);
net/ipv4/tcp_output.c
1938
k++;
net/ipv4/tcp_output.c
1941
shinfo->nr_frags = k;
net/ipv6/ioam6_iptunnel.c
182
ilwt->freq.k = freq_k;
net/ipv6/ioam6_iptunnel.c
33
u32 k;
net/ipv6/ioam6_iptunnel.c
353
if (pkt_cnt % ilwt->freq.n >= ilwt->freq.k)
net/ipv6/ioam6_iptunnel.c
474
err = nla_put_u32(skb, IOAM6_IPTUNNEL_FREQ_K, ilwt->freq.k);
net/ipv6/ioam6_iptunnel.c
510
nlsize = nla_total_size(sizeof(ilwt->freq.k)) +
net/ipv6/ioam6_iptunnel.c
532
return (ilwt_a->freq.k != ilwt_b->freq.k ||
net/key/af_key.c
2558
struct xfrm_kmaddress k;
net/key/af_key.c
2578
k.reserved = kma->sadb_x_kmaddress_reserved;
net/key/af_key.c
2581
&k.local, &k.remote, &k.family);
net/key/af_key.c
2633
kma ? &k : NULL, net, NULL, 0, NULL, NULL);
net/key/af_key.c
2920
int i, k, sz = 0;
net/key/af_key.c
2933
for (k = 1; ; k++) {
net/key/af_key.c
2934
const struct xfrm_algo_desc *aalg = xfrm_aalg_get_byidx(k);
net/key/af_key.c
2990
int i, k;
net/key/af_key.c
3009
for (k = 1; ; k++) {
net/key/af_key.c
3011
const struct xfrm_algo_desc *aalg = xfrm_aalg_get_byidx(k);
net/key/af_key.c
3495
static int set_sadb_kmaddress(struct sk_buff *skb, const struct xfrm_kmaddress *k)
net/key/af_key.c
3499
int family = k->family;
net/key/af_key.c
3509
kma->sadb_x_kmaddress_reserved = k->reserved;
net/key/af_key.c
3512
if (!pfkey_sockaddr_fill(&k->local, 0, (struct sockaddr *)sa, family) ||
net/key/af_key.c
3513
!pfkey_sockaddr_fill(&k->remote, 0, (struct sockaddr *)(sa+socklen), family))
net/key/af_key.c
3551
const struct xfrm_kmaddress *k,
net/key/af_key.c
3569
if (k != NULL) {
net/key/af_key.c
3572
pfkey_sockaddr_pair_size(k->family));
net/key/af_key.c
3617
if (k != NULL && (set_sadb_kmaddress(skb, k) < 0))
net/key/af_key.c
3667
const struct xfrm_kmaddress *k,
net/llc/af_llc.c
1139
llc->k = opt;
net/llc/af_llc.c
1202
val = llc->k; break;
net/llc/llc_c_ac.c
1079
if (llc->k - unacked_pdu < 1)
net/llc/llc_c_ac.c
1080
llc->k = 1;
net/llc/llc_c_ac.c
1082
llc->k -= unacked_pdu;
net/llc/llc_c_ac.c
1098
llc->k += 1;
net/llc/llc_c_ac.c
1099
if (llc->k > (u8) ~LLC_2_SEQ_NBR_MODULO)
net/llc/llc_c_ac.c
1100
llc->k = (u8) ~LLC_2_SEQ_NBR_MODULO;
net/llc/llc_c_ev.c
623
return !(skb_queue_len(&llc_sk(sk)->pdu_unack_q) + 1 == llc_sk(sk)->k);
net/llc/llc_c_ev.c
637
return skb_queue_len(&llc_sk(sk)->pdu_unack_q) + 1 == llc_sk(sk)->k;
net/llc/llc_conn.c
912
llc->k = 2; /* tx win size, will adjust dynam */
net/llc/llc_proc.c
192
llc->retry_count, llc->k, llc->rw, llc->p_flag, llc->f_flag,
net/mac80211/trace.h
117
#define KEY_ASSIGN(k) __entry->cipher = (k)->cipher; \
net/mac80211/trace.h
118
__entry->flags = (k)->flags; \
net/mac80211/trace.h
119
__entry->keyidx = (k)->keyidx; \
net/mac80211/trace.h
120
__entry->hw_key_idx = (k)->hw_key_idx;
net/netfilter/ipset/ip_set_hash_gen.h
1043
int i, j, k, r, ret = -IPSET_ERR_EXIST;
net/netfilter/ipset/ip_set_hash_gen.h
1061
for (i = 0, k = 0; i < n->pos; i++) {
net/netfilter/ipset/ip_set_hash_gen.h
1063
k++;
net/netfilter/ipset/ip_set_hash_gen.h
1099
k++;
net/netfilter/ipset/ip_set_hash_gen.h
1101
if (k == n->pos) {
net/netfilter/ipset/ip_set_hash_gen.h
1105
} else if (k >= AHASH_INIT_SIZE) {
net/netfilter/ipset/ip_set_hash_gen.h
1112
for (j = 0, k = 0; j < n->pos; j++) {
net/netfilter/ipset/ip_set_hash_gen.h
1116
memcpy(tmp->value + k * dsize, data, dsize);
net/netfilter/ipset/ip_set_hash_gen.h
1117
set_bit(k, tmp->used);
net/netfilter/ipset/ip_set_hash_gen.h
1118
k++;
net/netfilter/ipset/ip_set_hash_gen.h
1120
tmp->pos = k;
net/netfilter/ipset/ip_set_hash_gen.h
1168
int ret, i, j = 0, k;
net/netfilter/ipset/ip_set_hash_gen.h
1179
for (k = 0; k < NLEN && h->nets[k].cidr[1] && !multi;
net/netfilter/ipset/ip_set_hash_gen.h
1180
k++) {
net/netfilter/ipset/ip_set_hash_gen.h
1181
mtype_data_netmask(d, NCIDR_GET(h->nets[k].cidr[1]),
net/netfilter/ipset/ip_set_hash_gen.h
491
u8 k;
net/netfilter/ipset/ip_set_hash_gen.h
513
for (k = 0; k < IPSET_NET_COUNT; k++)
net/netfilter/ipset/ip_set_hash_gen.h
515
NCIDR_PUT(DCIDR_GET(data->cidr, k)),
net/netfilter/ipset/ip_set_hash_gen.h
516
k);
net/netfilter/ipvs/ip_vs_est.c
902
struct ip_vs_kstats *k = &stats->kstats;
net/netfilter/ipvs/ip_vs_est.c
905
est->last_inbytes = k->inbytes;
net/netfilter/ipvs/ip_vs_est.c
906
est->last_outbytes = k->outbytes;
net/netfilter/ipvs/ip_vs_est.c
907
est->last_conns = k->conns;
net/netfilter/ipvs/ip_vs_est.c
908
est->last_inpkts = k->inpkts;
net/netfilter/ipvs/ip_vs_est.c
909
est->last_outpkts = k->outpkts;
net/netfilter/nf_tables_api.c
1537
const struct nft_object_hash_key *k = data;
net/netfilter/nf_tables_api.c
1539
seed ^= hash_ptr(k->table, 32);
net/netfilter/nf_tables_api.c
1541
return jhash(k->name, strlen(k->name), seed);
net/netfilter/nf_tables_api.c
1554
const struct nft_object_hash_key *k = arg->key;
net/netfilter/nf_tables_api.c
1557
if (obj->key.table != k->table)
net/netfilter/nf_tables_api.c
1560
return strcmp(obj->key.name, k->name);
net/netfilter/nf_tables_api.c
6832
int err, i, k;
net/netfilter/nf_tables_api.c
6850
for (k = i - 1; k >= 0; k--)
net/netfilter/nf_tables_api.c
6851
nft_expr_destroy(ctx, expr_array[k]);
net/netfilter/nf_tables_api.c
8008
struct nft_object_hash_key k = { .table = table };
net/netfilter/nf_tables_api.c
8014
k.name = search;
net/netfilter/nf_tables_api.c
8020
list = rhltable_lookup(&nft_objname_ht, &k, nft_objname_ht_params);
net/netfilter/nft_ct.c
41
enum nft_ct_keys k,
net/netfilter/nft_ct.c
45
return k == NFT_CT_BYTES ? atomic64_read(&c[d].bytes) :
net/netfilter/nft_ct.c
48
return nft_ct_get_eval_counter(c, k, IP_CT_DIR_ORIGINAL) +
net/netfilter/nft_ct.c
49
nft_ct_get_eval_counter(c, k, IP_CT_DIR_REPLY);
net/netfilter/nft_ct.c
827
u32 k = ntohl(nla_get_be32(tb[NFTA_CT_KEY]));
net/netfilter/nft_ct.c
829
switch (k) {
net/netfilter/nft_payload.c
281
unsigned int remainder, delta, k;
net/netfilter/nft_payload.c
295
k = priv_len / sizeof(u32);
net/netfilter/nft_payload.c
298
mask.data[k] = (__force u32)remainder_mask;
net/netfilter/nft_set_bitmap.c
56
u32 k;
net/netfilter/nft_set_bitmap.c
59
k = *(u16 *)key;
net/netfilter/nft_set_bitmap.c
61
k = *(u8 *)key;
net/netfilter/nft_set_bitmap.c
62
k <<= 1;
net/netfilter/nft_set_bitmap.c
64
*idx = k / BITS_PER_BYTE;
net/netfilter/nft_set_bitmap.c
65
*off = k % BITS_PER_BYTE;
net/netfilter/nft_set_pipapo.c
1005
v = k[group / (BITS_PER_BYTE / f->bb)];
net/netfilter/nft_set_pipapo.c
367
unsigned int k;
net/netfilter/nft_set_pipapo.c
370
for (k = 0; k < len; k++) {
net/netfilter/nft_set_pipapo.c
371
bitset = map[k];
net/netfilter/nft_set_pipapo.c
375
int i = k * BITS_PER_LONG + r;
net/netfilter/nft_set_pipapo.c
378
map[k] = 0;
net/netfilter/nft_set_pipapo.c
393
map[k] = 0;
net/netfilter/nft_set_pipapo.c
990
static int pipapo_insert(struct nft_pipapo_field *f, const uint8_t *k,
net/netfilter/nft_xfrm.c
100
switch (k) {
net/netfilter/nft_xfrm.c
98
static bool xfrm_state_addr_ok(enum nft_xfrm_keys k, u8 family, u8 mode)
net/rds/ib_recv.c
812
unsigned int k;
net/rds/ib_recv.c
821
for (k = 0; k < to_copy; k += 8) {
net/rxrpc/conn_service.c
25
struct rxrpc_conn_proto k;
net/rxrpc/conn_service.c
30
k.epoch = sp->hdr.epoch;
net/rxrpc/conn_service.c
31
k.cid = sp->hdr.cid & RXRPC_CIDMASK;
net/rxrpc/conn_service.c
45
if (conn->proto.index_key < k.index_key)
net/rxrpc/conn_service.c
47
else if (conn->proto.index_key > k.index_key)
net/rxrpc/conn_service.c
68
struct rxrpc_conn_proto k = conn->proto;
net/rxrpc/conn_service.c
80
if (cursor->proto.index_key < k.index_key)
net/rxrpc/conn_service.c
82
else if (cursor->proto.index_key > k.index_key)
net/sched/act_pedit.c
46
struct tcf_pedit_key_ex *k;
net/sched/act_pedit.c
54
keys_ex = kzalloc_objs(*k, n);
net/sched/act_pedit.c
561
int k;
net/sched/act_pedit.c
563
for (k = 0; k < tcf_pedit_nkeys(act); k++) {
net/sched/act_pedit.c
564
switch (tcf_pedit_cmd(act, k)) {
net/sched/act_pedit.c
575
entry->mangle.htype = tcf_pedit_htype(act, k);
net/sched/act_pedit.c
576
entry->mangle.mask = tcf_pedit_mask(act, k);
net/sched/act_pedit.c
577
entry->mangle.val = tcf_pedit_val(act, k);
net/sched/act_pedit.c
578
entry->mangle.offset = tcf_pedit_offset(act, k);
net/sched/act_pedit.c
58
k = keys_ex;
net/sched/act_pedit.c
582
*index_inc = k;
net/sched/act_pedit.c
586
int k;
net/sched/act_pedit.c
600
for (k = 1; k < tcf_pedit_nkeys(act); k++) {
net/sched/act_pedit.c
601
if (cmd != tcf_pedit_cmd(act, k)) {
net/sched/act_pedit.c
94
k->htype = nla_get_u16(tb[TCA_PEDIT_KEY_EX_HTYPE]);
net/sched/act_pedit.c
95
k->cmd = nla_get_u16(tb[TCA_PEDIT_KEY_EX_CMD]);
net/sched/act_pedit.c
97
k++;
net/sched/cls_api.c
3873
int i, j, k, index, err = 0;
net/sched/cls_api.c
3898
for (k = 0; k < index ; k++) {
net/sched/cls_api.c
3899
entry[k].hw_stats = tc_act_hw_stats(act->hw_stats);
net/sched/cls_api.c
3900
entry[k].hw_index = act->tcfa_index;
net/sched/cls_api.c
3901
entry[k].cookie = (unsigned long)act;
net/sched/cls_api.c
3902
entry[k].miss_cookie =
net/sched/sch_cake.c
2865
u32 k = j * CAKE_MAX_TINS + i;
net/sched/sch_cake.c
2870
qd->overflow_heap[k].t = i;
net/sched/sch_cake.c
2871
qd->overflow_heap[k].b = j;
net/sched/sch_cake.c
2872
b->overflow_idx[j] = k;
net/sched/sch_cake.c
807
u32 i, k;
net/sched/sch_cake.c
812
for (i = 0, k = inner_hash; i < CAKE_SET_WAYS;
net/sched/sch_cake.c
813
i++, k = (k + 1) % CAKE_SET_WAYS) {
net/sched/sch_cake.c
814
if (q->tags[outer_hash + k] == flow_hash) {
net/sched/sch_cake.c
818
if (!q->flows[outer_hash + k].set) {
net/sched/sch_cake.c
832
i++, k = (k + 1) % CAKE_SET_WAYS) {
net/sched/sch_cake.c
833
if (!q->flows[outer_hash + k].set) {
net/sched/sch_cake.c
848
if (q->flows[outer_hash + k].set == CAKE_SET_BULK) {
net/sched/sch_cake.c
849
cake_dec_srchost_bulk_flow_count(q, &q->flows[outer_hash + k], flow_mode);
net/sched/sch_cake.c
850
cake_dec_dsthost_bulk_flow_count(q, &q->flows[outer_hash + k], flow_mode);
net/sched/sch_cake.c
854
reduced_hash = outer_hash + k;
net/sched/sch_cake.c
861
for (i = 0, k = inner_hash; i < CAKE_SET_WAYS;
net/sched/sch_cake.c
862
i++, k = (k + 1) % CAKE_SET_WAYS) {
net/sched/sch_cake.c
863
if (q->hosts[outer_hash + k].srchost_tag ==
net/sched/sch_cake.c
868
i++, k = (k + 1) % CAKE_SET_WAYS) {
net/sched/sch_cake.c
869
if (!q->hosts[outer_hash + k].srchost_bulk_flow_count)
net/sched/sch_cake.c
872
q->hosts[outer_hash + k].srchost_tag = srchost_hash;
net/sched/sch_cake.c
874
srchost_idx = outer_hash + k;
net/sched/sch_cake.c
885
for (i = 0, k = inner_hash; i < CAKE_SET_WAYS;
net/sched/sch_cake.c
886
i++, k = (k + 1) % CAKE_SET_WAYS) {
net/sched/sch_cake.c
887
if (q->hosts[outer_hash + k].dsthost_tag ==
net/sched/sch_cake.c
892
i++, k = (k + 1) % CAKE_SET_WAYS) {
net/sched/sch_cake.c
893
if (!q->hosts[outer_hash + k].dsthost_bulk_flow_count)
net/sched/sch_cake.c
896
q->hosts[outer_hash + k].dsthost_tag = dsthost_hash;
net/sched/sch_cake.c
898
dsthost_idx = outer_hash + k;
net/smc/smc_llc.c
1247
int i, j, k;
net/smc/smc_llc.c
1268
for (k = 0; k < SMC_LINKS_PER_LGR_MAX; k++) {
net/smc/smc_llc.c
1269
if (!smc_link_usable(&lgr->lnk[k]))
net/smc/smc_llc.c
1271
if (k != i &&
net/smc/smc_llc.c
1272
!memcmp(lgr->lnk[i].peer_gid, lgr->lnk[k].peer_gid,
net/smc/smc_llc.c
1277
if (k != j &&
net/smc/smc_llc.c
1278
!memcmp(lgr->lnk[j].peer_gid, lgr->lnk[k].peer_gid,
net/smc/smc_stats.c
391
int rc_srv = 0, rc_clnt = 0, k;
net/smc/smc_stats.c
397
for (k = 0; k < SMC_MAX_FBACK_RSN_CNT; k++) {
net/smc/smc_stats.c
398
if (k < snum)
net/smc/smc_stats.c
401
rc_srv = smc_nl_get_fback_details(skb, cb, k, is_srv);
net/smc/smc_stats.c
407
rc_clnt = smc_nl_get_fback_details(skb, cb, k, !is_srv);
net/smc/smc_stats.c
417
cb_ctx->pos[0] = k;
net/smc/smc_stats.h
140
#define SMC_STAT_RMB_SIZE_SUB(_smc_stats, _tech, k, _is_add, _len) \
net/smc/smc_stats.h
153
this_cpu_inc((*stats).smc[t].k ## _rmbsize.buf[_pos]); \
net/smc/smc_stats.h
154
this_cpu_add((*stats).smc[t].k ## _rmbuse, _l); \
net/smc/smc_stats.h
156
this_cpu_sub((*stats).smc[t].k ## _rmbuse, _l); \
net/sunrpc/auth_gss/gss_krb5_keys.c
308
__be32 k = cpu_to_be32(outlen * 8);
net/sunrpc/auth_gss/gss_krb5_keys.c
331
ret = crypto_shash_update(desc, (u8 *)&k, sizeof(k));
net/sunrpc/auth_gss/gss_krb5_keys.c
447
__be32 k = cpu_to_be32(outlen * 8);
net/sunrpc/auth_gss/gss_krb5_keys.c
466
ret = crypto_shash_update(desc, (u8 *)&k, sizeof(k));
net/sunrpc/sched.c
321
struct wait_bit_key k = __WAIT_BIT_KEY_INITIALIZER(m, RPC_TASK_ACTIVE);
net/sunrpc/sched.c
331
__wake_up_locked_key(wq, TASK_NORMAL, &k);
net/sunrpc/stats.c
110
for_each_possible_cpu(k)
net/sunrpc/stats.c
111
count += per_cpu(vers->vs_count[j], k);
net/sunrpc/stats.c
86
unsigned int i, j, k;
net/tipc/crypto.c
1214
int k;
net/tipc/crypto.c
1228
k = atomic_xchg(&rx->peer_rx_active, 0);
net/tipc/crypto.c
1229
if (k) {
net/tipc/crypto.c
1230
tipc_aead_users_dec(tx->aead[k], 0);
net/tipc/crypto.c
1238
for (k = KEY_MIN; k <= KEY_MAX; k++)
net/tipc/crypto.c
1239
tipc_crypto_key_detach(c->aead[k], &c->lock);
net/tipc/crypto.c
1327
u8 k, i = 0;
net/tipc/crypto.c
1346
k = (i == 0) ? key.pending :
net/tipc/crypto.c
1348
if (!k)
net/tipc/crypto.c
1350
aead = tipc_aead_rcu_ptr(tx->aead[k], &tx->lock);
net/tipc/crypto.c
1525
u8 k;
net/tipc/crypto.c
1539
for (k = KEY_MIN; k <= KEY_MAX; k++)
net/tipc/crypto.c
1540
tipc_aead_put(rcu_dereference(c->aead[k]));
net/tipc/crypto.c
2084
int k, i = 0;
net/tipc/crypto.c
2087
for (k = KEY_MIN; k <= KEY_MAX; k++) {
net/tipc/crypto.c
2088
if (k == KEY_MASTER) {
net/tipc/crypto.c
2097
if (k == key.passive)
net/tipc/crypto.c
2099
else if (k == key.active)
net/tipc/crypto.c
2101
else if (k == key.pending)
net/tipc/crypto.c
2106
i += scnprintf(buf + i, 200 - i, "\tKey%d: %s", k, s);
net/tipc/crypto.c
2109
aead = rcu_dereference(c->aead[k]);
net/tipc/crypto.c
2132
int k, i = 0;
net/tipc/crypto.c
2138
for (k = KEY_1; k <= KEY_3; k++) {
net/tipc/crypto.c
2139
if (k == key->passive)
net/tipc/crypto.c
2141
else if (k == key->active)
net/tipc/crypto.c
2143
else if (k == key->pending)
net/tipc/crypto.c
2148
(k != KEY_3) ? "%s " : "%s", s);
net/wireless/nl80211.c
1430
struct key_parse *k)
net/wireless/nl80211.c
1439
k->def = !!tb[NL80211_KEY_DEFAULT];
net/wireless/nl80211.c
1440
k->defmgmt = !!tb[NL80211_KEY_DEFAULT_MGMT];
net/wireless/nl80211.c
1441
k->defbeacon = !!tb[NL80211_KEY_DEFAULT_BEACON];
net/wireless/nl80211.c
1443
if (k->def) {
net/wireless/nl80211.c
1444
k->def_uni = true;
net/wireless/nl80211.c
1445
k->def_multi = true;
net/wireless/nl80211.c
1447
if (k->defmgmt || k->defbeacon)
net/wireless/nl80211.c
1448
k->def_multi = true;
net/wireless/nl80211.c
1451
k->idx = nla_get_u8(tb[NL80211_KEY_IDX]);
net/wireless/nl80211.c
1454
k->p.key = nla_data(tb[NL80211_KEY_DATA]);
net/wireless/nl80211.c
1455
k->p.key_len = nla_len(tb[NL80211_KEY_DATA]);
net/wireless/nl80211.c
1459
k->p.seq = nla_data(tb[NL80211_KEY_SEQ]);
net/wireless/nl80211.c
1460
k->p.seq_len = nla_len(tb[NL80211_KEY_SEQ]);
net/wireless/nl80211.c
1464
k->p.cipher = nla_get_u32(tb[NL80211_KEY_CIPHER]);
net/wireless/nl80211.c
1467
k->type = nla_get_u32(tb[NL80211_KEY_TYPE]);
net/wireless/nl80211.c
1480
k->def_uni = kdt[NL80211_KEY_DEFAULT_TYPE_UNICAST];
net/wireless/nl80211.c
1481
k->def_multi = kdt[NL80211_KEY_DEFAULT_TYPE_MULTICAST];
net/wireless/nl80211.c
1485
k->p.mode = nla_get_u8(tb[NL80211_KEY_MODE]);
net/wireless/nl80211.c
1490
static int nl80211_parse_key_old(struct genl_info *info, struct key_parse *k)
net/wireless/nl80211.c
1493
k->p.key = nla_data(info->attrs[NL80211_ATTR_KEY_DATA]);
net/wireless/nl80211.c
1494
k->p.key_len = nla_len(info->attrs[NL80211_ATTR_KEY_DATA]);
net/wireless/nl80211.c
1498
k->p.seq = nla_data(info->attrs[NL80211_ATTR_KEY_SEQ]);
net/wireless/nl80211.c
1499
k->p.seq_len = nla_len(info->attrs[NL80211_ATTR_KEY_SEQ]);
net/wireless/nl80211.c
1503
k->idx = nla_get_u8(info->attrs[NL80211_ATTR_KEY_IDX]);
net/wireless/nl80211.c
1506
k->p.cipher = nla_get_u32(info->attrs[NL80211_ATTR_KEY_CIPHER]);
net/wireless/nl80211.c
1508
k->def = !!info->attrs[NL80211_ATTR_KEY_DEFAULT];
net/wireless/nl80211.c
1509
k->defmgmt = !!info->attrs[NL80211_ATTR_KEY_DEFAULT_MGMT];
net/wireless/nl80211.c
1511
if (k->def) {
net/wireless/nl80211.c
1512
k->def_uni = true;
net/wireless/nl80211.c
1513
k->def_multi = true;
net/wireless/nl80211.c
1515
if (k->defmgmt)
net/wireless/nl80211.c
1516
k->def_multi = true;
net/wireless/nl80211.c
1519
k->type = nla_get_u32(info->attrs[NL80211_ATTR_KEY_TYPE]);
net/wireless/nl80211.c
1531
k->def_uni = kdt[NL80211_KEY_DEFAULT_TYPE_UNICAST];
net/wireless/nl80211.c
1532
k->def_multi = kdt[NL80211_KEY_DEFAULT_TYPE_MULTICAST];
net/wireless/nl80211.c
1538
static int nl80211_parse_key(struct genl_info *info, struct key_parse *k)
net/wireless/nl80211.c
1542
memset(k, 0, sizeof(*k));
net/wireless/nl80211.c
1543
k->idx = -1;
net/wireless/nl80211.c
1544
k->type = -1;
net/wireless/nl80211.c
1547
err = nl80211_parse_key_new(info, info->attrs[NL80211_ATTR_KEY], k);
net/wireless/nl80211.c
1549
err = nl80211_parse_key_old(info, k);
net/wireless/nl80211.c
1554
if ((k->def ? 1 : 0) + (k->defmgmt ? 1 : 0) +
net/wireless/nl80211.c
1555
(k->defbeacon ? 1 : 0) > 1) {
net/wireless/nl80211.c
1561
if (k->defmgmt || k->defbeacon) {
net/wireless/nl80211.c
1562
if (k->def_uni || !k->def_multi) {
net/wireless/nl80211.c
1569
if (k->idx != -1) {
net/wireless/nl80211.c
1570
if (k->defmgmt) {
net/wireless/nl80211.c
1571
if (k->idx < 4 || k->idx > 5) {
net/wireless/nl80211.c
1576
} else if (k->defbeacon) {
net/wireless/nl80211.c
1577
if (k->idx < 6 || k->idx > 7) {
net/wireless/nl80211.c
1582
} else if (k->def) {
net/wireless/nl80211.c
1583
if (k->idx < 0 || k->idx > 3) {
net/wireless/nl80211.c
1588
if (k->idx < 0 || k->idx > 7) {
net/wireless/scan.c
3570
int k;
net/wireless/scan.c
3572
for (k = 0; k < wreq->num_channels; k++) {
net/wireless/scan.c
3574
&wreq->channel_list[k];
net/xdp/xskmap.c
227
u32 k = *(u32 *)key;
net/xdp/xskmap.c
229
if (k >= map->max_entries)
net/xdp/xskmap.c
233
map_entry = &m->xsk_map[k];
net/xfrm/xfrm_policy.c
1161
struct net *net = read_pnet(&b->k.net);
net/xfrm/xfrm_policy.c
128
struct xfrm_pol_inexact_key k;
net/xfrm/xfrm_policy.c
1494
const struct xfrm_pol_inexact_key *k = data;
net/xfrm/xfrm_policy.c
1495
u32 a = k->type << 24 | k->dir << 16 | k->family;
net/xfrm/xfrm_policy.c
1497
return jhash_3words(a, k->if_id, net_hash_mix(read_pnet(&k->net)),
net/xfrm/xfrm_policy.c
1505
return xfrm_pol_bin_key(&b->k, 0, seed);
net/xfrm/xfrm_policy.c
1515
if (!net_eq(read_pnet(&b->k.net), read_pnet(&key->net)))
net/xfrm/xfrm_policy.c
1518
ret = b->k.dir ^ key->dir;
net/xfrm/xfrm_policy.c
1522
ret = b->k.type ^ key->type;
net/xfrm/xfrm_policy.c
1526
ret = b->k.family ^ key->family;
net/xfrm/xfrm_policy.c
1530
return b->k.if_id ^ key->if_id;
net/xfrm/xfrm_policy.c
2039
family = b->k.family;
net/xfrm/xfrm_policy.c
2065
struct xfrm_pol_inexact_key k = {
net/xfrm/xfrm_policy.c
2072
write_pnet(&k.net, net);
net/xfrm/xfrm_policy.c
2074
return rhashtable_lookup(&xfrm_policy_inexact_table, &k,
net/xfrm/xfrm_policy.c
3540
static inline int secpath_has_nontransport(const struct sec_path *sp, int k, int *idxp)
net/xfrm/xfrm_policy.c
3542
for (; k < sp->len; k++) {
net/xfrm/xfrm_policy.c
3543
if (sp->xvec[k]->props.mode != XFRM_MODE_TRANSPORT) {
net/xfrm/xfrm_policy.c
3544
*idxp = k;
net/xfrm/xfrm_policy.c
3804
int i, k = 0;
net/xfrm/xfrm_policy.c
3847
k = xfrm_policy_ok(tpp[i], sp, k, family, if_id);
net/xfrm/xfrm_policy.c
3848
if (k < 0) {
net/xfrm/xfrm_policy.c
3849
if (k < -1)
net/xfrm/xfrm_policy.c
3851
xerr_idx = -(2+k);
net/xfrm/xfrm_policy.c
3857
if (secpath_has_nontransport(sp, k, &xerr_idx)) {
net/xfrm/xfrm_policy.c
3864
sp->verified_cnt = k;
net/xfrm/xfrm_policy.c
4649
struct xfrm_kmaddress *k, struct net *net,
net/xfrm/xfrm_policy.c
4707
km_migrate(sel, dir, type, m, num_migrate, k, encap);
net/xfrm/xfrm_policy.c
752
struct xfrm_pol_inexact_key k = {
net/xfrm/xfrm_policy.c
762
write_pnet(&k.net, net);
net/xfrm/xfrm_policy.c
763
bin = rhashtable_lookup_fast(&xfrm_policy_inexact_table, &k,
net/xfrm/xfrm_policy.c
772
bin->k = k;
net/xfrm/xfrm_policy.c
779
&bin->k, &bin->head,
net/xfrm/xfrm_state.c
2840
const struct xfrm_kmaddress *k,
net/xfrm/xfrm_state.c
2850
ret = km->migrate(sel, dir, type, m, num_migrate, k,
net/xfrm/xfrm_user.c
3068
struct xfrm_kmaddress *k,
net/xfrm/xfrm_user.c
3076
if (k != NULL) {
net/xfrm/xfrm_user.c
3080
memcpy(&k->local, &uk->local, sizeof(k->local));
net/xfrm/xfrm_user.c
3081
memcpy(&k->remote, &uk->remote, sizeof(k->remote));
net/xfrm/xfrm_user.c
3082
k->family = uk->family;
net/xfrm/xfrm_user.c
3083
k->reserved = uk->reserved;
net/xfrm/xfrm_user.c
3196
static int copy_to_user_kmaddress(const struct xfrm_kmaddress *k, struct sk_buff *skb)
net/xfrm/xfrm_user.c
3201
uk.family = k->family;
net/xfrm/xfrm_user.c
3202
uk.reserved = k->reserved;
net/xfrm/xfrm_user.c
3203
memcpy(&uk.local, &k->local, sizeof(uk.local));
net/xfrm/xfrm_user.c
3204
memcpy(&uk.remote, &k->remote, sizeof(uk.remote));
net/xfrm/xfrm_user.c
3220
int num_migrate, const struct xfrm_kmaddress *k,
net/xfrm/xfrm_user.c
3239
if (k != NULL) {
net/xfrm/xfrm_user.c
3240
err = copy_to_user_kmaddress(k, skb);
net/xfrm/xfrm_user.c
3268
const struct xfrm_kmaddress *k,
net/xfrm/xfrm_user.c
3275
skb = nlmsg_new(xfrm_migrate_msgsize(num_migrate, !!k, !!encap),
net/xfrm/xfrm_user.c
3281
err = build_migrate(skb, m, num_migrate, k, sel, encap, dir, type);
net/xfrm/xfrm_user.c
3289
const struct xfrm_kmaddress *k,
rust/helpers/sync.c
10
__rust_helper void rust_helper_lockdep_unregister_key(struct lock_class_key *k)
rust/helpers/sync.c
12
lockdep_unregister_key(k);
rust/helpers/sync.c
5
__rust_helper void rust_helper_lockdep_register_key(struct lock_class_key *k)
rust/helpers/sync.c
7
lockdep_register_key(k);
samples/bpf/hbm.c
329
int k;
samples/bpf/hbm.c
395
for (k = 0; k < RET_VAL_COUNT; k++) {
samples/bpf/hbm.c
396
percent_pkts = (qstats.returnValCount[k] * 100.0) /
samples/bpf/hbm.c
398
fprintf(fout, "%s:%6.2f (%d)\n", returnValNames[k],
samples/bpf/hbm.c
399
percent_pkts, (int)qstats.returnValCount[k]);
samples/bpf/hbm.c
453
int k;
samples/bpf/hbm.c
462
while ((k = getopt_long(argc, argv, optstring, loptions, NULL)) != -1) {
samples/bpf/hbm.c
463
switch (k) {
samples/bpf/tracex3.bpf.c
41
#define S(k) if (n >= (1ull << k)) { i += k; n >>= k; }
samples/seccomp/bpf-helper.c
37
if (labels->labels[instr->k].location == 0xffffffff) {
samples/seccomp/bpf-helper.c
39
labels->labels[instr->k].label);
samples/seccomp/bpf-helper.c
42
instr->k = labels->labels[instr->k].location -
samples/seccomp/bpf-helper.c
48
if (labels->labels[instr->k].location != 0xffffffff) {
samples/seccomp/bpf-helper.c
50
labels->labels[instr->k].label);
samples/seccomp/bpf-helper.c
53
labels->labels[instr->k].location = offset;
samples/seccomp/bpf-helper.c
54
instr->k = 0; /* fall through */
samples/seccomp/bpf-helper.c
95
filter->code, filter->jt, filter->jf, filter->k);
samples/watch_queue/watch_test.c
56
struct key_notification *k = (struct key_notification *)n;
samples/watch_queue/watch_test.c
64
k->key_id, n->subtype, key_subtypes[n->subtype], k->aux);
scripts/gcc-plugins/randomize_layout_plugin.c
125
#define rot(x,k) (((x)<<(k))|((x)>>(64-(k))))
scripts/kallsyms.c
341
unsigned int i, k, off;
scripts/kallsyms.c
390
for (k = 0; k < table[i]->len; k++)
scripts/kallsyms.c
391
printf(", 0x%02x", table[i]->sym[k]);
scripts/mod/sumversion.c
69
#define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s))
scripts/mod/sumversion.c
70
#define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (uint32_t)0x5A827999,s))
scripts/mod/sumversion.c
71
#define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (uint32_t)0x6ED9EBA1,s))
scripts/recordmcount.h
241
unsigned k;
scripts/recordmcount.h
246
for (relhdr = shdr0, k = nhdr; k; --k, ++relhdr) {
scripts/recordmcount.h
617
unsigned k;
scripts/recordmcount.h
654
for (relhdr = shdr0, k = nhdr; k; --k, ++relhdr) {
security/apparmor/label.c
1005
int k;
security/apparmor/label.c
1011
for (k = 0;
security/apparmor/label.c
1012
k < z->size && (p = aa_label_next_in_merge(&i, a, b));
security/apparmor/label.c
1013
k++) {
security/apparmor/label.c
1014
int res = profile_cmp(p, z->vec[k]);
security/apparmor/label.c
1022
else if (k < z->size)
security/apparmor/label.c
1053
int k = 0, invcount = 0;
security/apparmor/label.c
1066
new->vec[k] = aa_get_newest_profile(next);
security/apparmor/label.c
1067
AA_BUG(!new->vec[k]->label.proxy);
security/apparmor/label.c
1068
AA_BUG(!new->vec[k]->label.proxy->label);
security/apparmor/label.c
1069
if (next->label.proxy != new->vec[k]->label.proxy)
security/apparmor/label.c
1071
k++;
security/apparmor/label.c
1074
new->vec[k++] = aa_get_profile(next);
security/apparmor/label.c
1077
new->size = k;
security/apparmor/label.c
1078
new->vec[k] = NULL;
security/apparmor/label.c
1093
if (k == a->size)
security/apparmor/label.c
1095
else if (k == b->size)
security/apparmor/match.c
202
size_t j, k;
security/apparmor/match.c
207
j = k) {
security/apparmor/match.c
211
k = DEFAULT_TABLE(dfa)[j];
security/apparmor/match.c
212
if (j == k)
security/apparmor/match.c
220
j = k) {
security/apparmor/match.c
221
k = DEFAULT_TABLE(dfa)[j];
security/selinux/hooks.c
6903
static int selinux_key_alloc(struct key *k, const struct cred *cred,
security/selinux/hooks.c
6907
struct key_security_struct *ksec = selinux_key(k);
security/selinux/ss/avtab.c
307
int (*insertf)(struct avtab *a, const struct avtab_key *k,
security/selinux/ss/avtab.c
471
static int avtab_insertf(struct avtab *a, const struct avtab_key *k,
security/selinux/ss/avtab.c
474
return avtab_insert(a, k, d);
security/selinux/ss/avtab.h
110
int (*insert)(struct avtab *a, const struct avtab_key *k,
security/selinux/ss/conditional.c
254
static int cond_insertf(struct avtab *a, const struct avtab_key *k,
security/selinux/ss/conditional.c
269
if (k->specified & AVTAB_TYPE) {
security/selinux/ss/conditional.c
270
if (avtab_search_node(&p->te_avtab, k)) {
security/selinux/ss/conditional.c
283
node_ptr = avtab_search_node(&p->te_cond_avtab, k);
security/selinux/ss/conditional.c
286
k->specified)) {
security/selinux/ss/conditional.c
303
if (avtab_search_node(&p->te_cond_avtab, k)) {
security/selinux/ss/conditional.c
310
node_ptr = avtab_insert_nonunique(&p->te_cond_avtab, k, d);
security/selinux/ss/hashtab.c
143
int (*destroy)(void *k, void *d, void *args), void *args)
security/selinux/ss/hashtab.c
88
int hashtab_map(struct hashtab *h, int (*apply)(void *k, void *d, void *args),
security/selinux/ss/hashtab.h
136
int hashtab_map(struct hashtab *h, int (*apply)(void *k, void *d, void *args),
security/selinux/ss/hashtab.h
142
int (*destroy)(void *k, void *d, void *args), void *args);
security/selinux/ss/policydb.c
2358
int k;
security/selinux/ss/policydb.c
2363
for (k = 0; k < 4; k++)
security/selinux/ss/policydb.c
2364
c->u.node6.addr[k] = nodebuf[k];
security/selinux/ss/policydb.c
2365
for (k = 0; k < 4; k++)
security/selinux/ss/policydb.c
2366
c->u.node6.mask[k] = nodebuf[k + 4];
security/selinux/ss/policydb.c
418
static u32 filenametr_hash(const void *k)
security/selinux/ss/policydb.c
420
const struct filename_trans_key *ft = k;
security/selinux/ss/policydb.c
454
static u32 rangetr_hash(const void *k)
security/selinux/ss/policydb.c
456
const struct range_trans *key = k;
security/selinux/ss/policydb.c
491
static u32 role_trans_hash(const void *k)
security/selinux/ss/policydb.c
493
const struct role_trans_key *key = k;
security/selinux/ss/services.c
120
u16 k;
security/selinux/ss/services.c
139
k = 0;
security/selinux/ss/services.c
140
while (p_in->perms[k]) {
security/selinux/ss/services.c
142
if (!*p_in->perms[k]) {
security/selinux/ss/services.c
143
k++;
security/selinux/ss/services.c
146
p_out->perms[k] = string_to_av_perm(pol, p_out->value,
security/selinux/ss/services.c
147
p_in->perms[k]);
security/selinux/ss/services.c
148
if (!p_out->perms[k]) {
security/selinux/ss/services.c
150
p_in->perms[k], p_in->name);
security/selinux/ss/services.c
156
k++;
security/selinux/ss/services.c
158
p_out->num_perms = k;
security/selinux/ss/services.c
3412
static int get_classes_callback(void *k, void *d, void *args)
security/selinux/ss/services.c
3415
char *name = k, **classes = args;
security/selinux/ss/services.c
3453
static int get_permissions_callback(void *k, void *d, void *args)
security/selinux/ss/services.c
3456
char *name = k, **perms = args;
security/selinux/ss/services.c
444
static int dump_masked_av_helper(void *k, void *d, void *args)
security/selinux/ss/services.c
451
permission_names[pdatum->value - 1] = (char *)k;
sound/core/pcm_lib.c
1000
if (num > rats[k].num_max)
sound/core/pcm_lib.c
1001
num = rats[k].num_max;
sound/core/pcm_lib.c
1004
r = (num - rats[k].num_min) % rats[k].num_step;
sound/core/pcm_lib.c
1053
unsigned int k;
sound/core/pcm_lib.c
1063
for (k = 0; k < count; k++) {
sound/core/pcm_lib.c
1064
if (mask && !(mask & (1 << k)))
sound/core/pcm_lib.c
1066
if (!snd_interval_test(i, list[k]))
sound/core/pcm_lib.c
1068
list_range.min = min(list_range.min, list[k]);
sound/core/pcm_lib.c
1069
list_range.max = max(list_range.max, list[k]);
sound/core/pcm_lib.c
1092
unsigned int k;
sound/core/pcm_lib.c
1103
for (k = 0; k < count; k++) {
sound/core/pcm_lib.c
1104
if (mask && !(mask & (1 << k)))
sound/core/pcm_lib.c
1106
snd_interval_copy(&range, &ranges[k]);
sound/core/pcm_lib.c
1172
unsigned int k;
sound/core/pcm_lib.c
1192
k = 0;
sound/core/pcm_lib.c
1194
if (snd_BUG_ON(k >= ARRAY_SIZE(c->deps))) {
sound/core/pcm_lib.c
1198
c->deps[k++] = dep;
sound/core/pcm_lib.c
1578
unsigned int k;
sound/core/pcm_lib.c
1580
for (k = SNDRV_PCM_HW_PARAM_FIRST_MASK; k <= SNDRV_PCM_HW_PARAM_LAST_MASK; k++)
sound/core/pcm_lib.c
1581
_snd_pcm_hw_param_any(params, k);
sound/core/pcm_lib.c
1582
for (k = SNDRV_PCM_HW_PARAM_FIRST_INTERVAL; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++)
sound/core/pcm_lib.c
1583
_snd_pcm_hw_param_any(params, k);
sound/core/pcm_lib.c
762
unsigned int k, struct snd_interval *c)
sound/core/pcm_lib.c
770
c->min = muldiv32(a->min, b->min, k, &r);
sound/core/pcm_lib.c
772
c->max = muldiv32(a->max, b->max, k, &r);
sound/core/pcm_lib.c
792
void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k,
sound/core/pcm_lib.c
801
c->min = muldiv32(a->min, k, b->max, &r);
sound/core/pcm_lib.c
804
c->max = muldiv32(a->max, k, b->min, &r);
sound/core/pcm_lib.c
837
unsigned int k;
sound/core/pcm_lib.c
844
for (k = 0; k < rats_count; ++k) {
sound/core/pcm_lib.c
845
unsigned int num = rats[k].num;
sound/core/pcm_lib.c
852
if (den < rats[k].den_min)
sound/core/pcm_lib.c
854
if (den > rats[k].den_max)
sound/core/pcm_lib.c
855
den = rats[k].den_max;
sound/core/pcm_lib.c
858
r = (den - rats[k].den_min) % rats[k].den_step;
sound/core/pcm_lib.c
883
for (k = 0; k < rats_count; ++k) {
sound/core/pcm_lib.c
884
unsigned int num = rats[k].num;
sound/core/pcm_lib.c
893
if (den > rats[k].den_max)
sound/core/pcm_lib.c
895
if (den < rats[k].den_min)
sound/core/pcm_lib.c
896
den = rats[k].den_min;
sound/core/pcm_lib.c
899
r = (den - rats[k].den_min) % rats[k].den_step;
sound/core/pcm_lib.c
901
den += rats[k].den_step - r;
sound/core/pcm_lib.c
955
unsigned int k;
sound/core/pcm_lib.c
960
for (k = 0; k < rats_count; ++k) {
sound/core/pcm_lib.c
962
unsigned int den = rats[k].den;
sound/core/pcm_lib.c
966
if (num > rats[k].num_max)
sound/core/pcm_lib.c
968
if (num < rats[k].num_min)
sound/core/pcm_lib.c
969
num = rats[k].num_max;
sound/core/pcm_lib.c
972
r = (num - rats[k].num_min) % rats[k].num_step;
sound/core/pcm_lib.c
974
num += rats[k].num_step - r;
sound/core/pcm_lib.c
992
for (k = 0; k < rats_count; ++k) {
sound/core/pcm_lib.c
994
unsigned int den = rats[k].den;
sound/core/pcm_lib.c
998
if (num < rats[k].num_min)
sound/core/pcm_local.h
19
unsigned int k, struct snd_interval *c);
sound/core/pcm_local.h
20
void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k,
sound/core/pcm_native.c
2411
snd_pcm_format_t k;
sound/core/pcm_native.c
2417
pcm_for_each_format(k) {
sound/core/pcm_native.c
2419
if (!snd_mask_test_format(mask, k))
sound/core/pcm_native.c
2421
bits = snd_pcm_format_physical_width(k);
sound/core/pcm_native.c
2425
snd_mask_reset(&m, (__force unsigned)k);
sound/core/pcm_native.c
2434
snd_pcm_format_t k;
sound/core/pcm_native.c
2440
pcm_for_each_format(k) {
sound/core/pcm_native.c
2442
if (!snd_mask_test_format(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), k))
sound/core/pcm_native.c
2444
bits = snd_pcm_format_physical_width(k);
sound/core/pcm_native.c
2535
int k, err;
sound/core/pcm_native.c
2537
for (k = SNDRV_PCM_HW_PARAM_FIRST_MASK; k <= SNDRV_PCM_HW_PARAM_LAST_MASK; k++) {
sound/core/pcm_native.c
2538
snd_mask_any(constrs_mask(constrs, k));
sound/core/pcm_native.c
2541
for (k = SNDRV_PCM_HW_PARAM_FIRST_INTERVAL; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++) {
sound/core/pcm_native.c
2542
snd_interval_any(constrs_interval(constrs, k));
sound/core/pcm_native.c
295
unsigned int k;
sound/core/pcm_native.c
299
for (k = SNDRV_PCM_HW_PARAM_FIRST_MASK; k <= SNDRV_PCM_HW_PARAM_LAST_MASK; k++) {
sound/core/pcm_native.c
300
m = hw_param_mask(params, k);
sound/core/pcm_native.c
305
if (!(params->rmask & PARAM_MASK_BIT(k)))
sound/core/pcm_native.c
311
changed = snd_mask_refine(m, constrs_mask(constrs, k));
sound/core/pcm_native.c
318
trace_hw_mask_param(substream, k, 0, &old_mask, m);
sound/core/pcm_native.c
319
params->cmask |= PARAM_MASK_BIT(k);
sound/core/pcm_native.c
331
unsigned int k;
sound/core/pcm_native.c
335
for (k = SNDRV_PCM_HW_PARAM_FIRST_INTERVAL; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++) {
sound/core/pcm_native.c
336
i = hw_param_interval(params, k);
sound/core/pcm_native.c
341
if (!(params->rmask & PARAM_MASK_BIT(k)))
sound/core/pcm_native.c
347
changed = snd_interval_refine(i, constrs_interval(constrs, k));
sound/core/pcm_native.c
354
trace_hw_interval_param(substream, k, 0, &old_interval, i);
sound/core/pcm_native.c
355
params->cmask |= PARAM_MASK_BIT(k);
sound/core/pcm_native.c
366
unsigned int k;
sound/core/pcm_native.c
396
for (k = 0; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++)
sound/core/pcm_native.c
397
vstamps[k] = (params->rmask & PARAM_MASK_BIT(k)) ? 1 : 0;
sound/core/pcm_native.c
404
for (k = 0; k < constrs->rules_num; k++) {
sound/core/pcm_native.c
405
r = &constrs->rules[k];
sound/core/pcm_native.c
427
if (vstamps[r->deps[d]] > rstamps[k])
sound/core/pcm_native.c
454
k + 1, &old_mask,
sound/core/pcm_native.c
459
k + 1, &old_interval,
sound/core/pcm_native.c
468
rstamps[k] = stamp++;
sound/hda/codecs/side-codecs/tas2781_hda.c
104
for (j = 0, k = 0; j < node_num; j++) {
sound/hda/codecs/side-codecs/tas2781_hda.c
114
if (k >= p->ndev || l > oft * 4) {
sound/hda/codecs/side-codecs/tas2781_hda.c
121
data[l] = k;
sound/hda/codecs/side-codecs/tas2781_hda.c
124
k++;
sound/hda/codecs/side-codecs/tas2781_hda.c
68
int i, j, k, l;
sound/hda/codecs/side-codecs/tas2781_hda_i2c.c
333
int ret, i, j, k;
sound/hda/codecs/side-codecs/tas2781_hda_i2c.c
365
for (k = 0; k < sizeof(var8) && var8[k]; k++)
sound/hda/codecs/side-codecs/tas2781_hda_i2c.c
366
efi_name[k] = var8[k];
sound/isa/sb/emu8000_patch.c
216
int k;
sound/isa/sb/emu8000_patch.c
219
for (k = 1; k <= looplen; k++) {
sound/isa/sb/emu8000_patch.c
220
s = read_word(data, offset - k, sp->v.mode_flags);
sound/pci/ac97/ac97_pcm.c
434
int i, j, k;
sound/pci/ac97/ac97_pcm.c
490
for (k = 0; k < i; k++) {
sound/pci/ac97/ac97_pcm.c
491
if (rpcm->stream == rpcms[k].stream)
sound/pci/ac97/ac97_pcm.c
492
tmp &= ~rpcms[k].r[0].rslots[j];
sound/pci/asihpi/hpidebug.c
51
int k;
sound/pci/asihpi/hpidebug.c
62
for (k = 0; k < cols && i < len; i++, k++)
sound/pci/asihpi/hpidebug.c
63
printk(KERN_CONT "%s%04x", k == 0 ? "" : " ", pdata[i]);
sound/pci/ctxfi/ctmixer.c
1004
enum CT_SUM_CTL k;
sound/pci/ctxfi/ctmixer.c
1009
for (i = AMIXER_MASTER_F, k = SUM_IN_F;
sound/pci/ctxfi/ctmixer.c
1010
i <= AMIXER_MASTER_S; i++, k++) {
sound/pci/ctxfi/ctmixer.c
1012
sum = mixer->sums[k*CHN_NUM];
sound/pci/ctxfi/ctmixer.c
1015
sum = mixer->sums[k*CHN_NUM+1];
sound/pci/ctxfi/ctmixer.c
1039
for (i = AMIXER_PCM_F, k = SUM_IN_F; i <= AMIXER_PCM_S; i++, k++) {
sound/pci/ctxfi/ctmixer.c
1041
sum = mixer->sums[k*CHN_NUM];
sound/pci/ctxfi/ctmixer.c
1044
sum = mixer->sums[k*CHN_NUM+1];
sound/pci/ctxfi/ctresource.c
26
int i, j, k, n;
sound/pci/ctxfi/ctresource.c
31
k = i % 8;
sound/pci/ctxfi/ctresource.c
32
if (rscs[j] & ((u8)1 << k)) {
sound/pci/ctxfi/ctresource.c
48
k = i % 8;
sound/pci/ctxfi/ctresource.c
49
rscs[j] |= ((u8)1 << k);
sound/pci/ctxfi/ctresource.c
60
unsigned int i, j, k, n;
sound/pci/ctxfi/ctresource.c
65
k = i % 8;
sound/pci/ctxfi/ctresource.c
66
rscs[j] &= ~((u8)1 << k);
sound/pci/emu10k1/emufx.c
1577
int j, k, l, d;
sound/pci/emu10k1/emufx.c
1579
k = bass_tmp + (z * 8) + (j * 4);
sound/pci/emu10k1/emufx.c
1584
A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j));
sound/pci/emu10k1/emufx.c
1585
A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j));
sound/pci/emu10k1/emufx.c
1586
A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j));
sound/pci/emu10k1/emufx.c
1587
A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j));
sound/pci/emu10k1/emufx.c
1588
A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
sound/pci/emu10k1/emufx.c
1590
A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j));
sound/pci/emu10k1/emufx.c
1592
A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j));
sound/pci/emu10k1/emufx.c
2178
int j, k, l, d;
sound/pci/emu10k1/emufx.c
2180
k = 0xa0 + (z * 8) + (j * 4);
sound/pci/emu10k1/emufx.c
2185
OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
sound/pci/emu10k1/emufx.c
2186
OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
sound/pci/emu10k1/emufx.c
2187
OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
sound/pci/emu10k1/emufx.c
2188
OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
sound/pci/emu10k1/emufx.c
2189
OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
sound/pci/emu10k1/emufx.c
2191
OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
sound/pci/emu10k1/emufx.c
2193
OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
sound/pci/emu10k1/voice.c
28
int i, j, k, skip;
sound/pci/emu10k1/voice.c
42
for (k = 0; k < number; k++) {
sound/pci/emu10k1/voice.c
43
voice = &emu->voices[i + k];
sound/pci/emu10k1/voice.c
45
skip = k + 1;
sound/pci/emu10k1/voice.c
50
for (k = 0; k < number; k++) {
sound/pci/emu10k1/voice.c
51
voice = &emu->voices[i + k];
sound/pci/ice1712/aureon.c
1346
static int aureon_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
sound/pci/ice1712/phase.c
705
static int phase28_oversampling_info(struct snd_kcontrol *k,
sound/pci/mixart/mixart_hwdep.c
131
u32 k;
sound/pci/mixart/mixart_hwdep.c
163
for(k=0; k < connector->uid_count; k++) {
sound/pci/mixart/mixart_hwdep.c
166
if(k < MIXART_FIRST_DIG_AUDIO_ID) {
sound/pci/mixart/mixart_hwdep.c
167
pipe = &mgr->chip[k/2]->pipe_out_ana;
sound/pci/mixart/mixart_hwdep.c
169
pipe = &mgr->chip[(k-MIXART_FIRST_DIG_AUDIO_ID)/2]->pipe_out_dig;
sound/pci/mixart/mixart_hwdep.c
171
if(k & 1) {
sound/pci/mixart/mixart_hwdep.c
172
pipe->uid_right_connector = connector->uid[k]; /* odd */
sound/pci/mixart/mixart_hwdep.c
174
pipe->uid_left_connector = connector->uid[k]; /* even */
sound/pci/mixart/mixart_hwdep.c
181
request.uid = connector->uid[k];
sound/pci/mixart/mixart_hwdep.c
207
for(k=0; k < connector->uid_count; k++) {
sound/pci/mixart/mixart_hwdep.c
210
if(k < MIXART_FIRST_DIG_AUDIO_ID) {
sound/pci/mixart/mixart_hwdep.c
211
pipe = &mgr->chip[k/2]->pipe_in_ana;
sound/pci/mixart/mixart_hwdep.c
213
pipe = &mgr->chip[(k-MIXART_FIRST_DIG_AUDIO_ID)/2]->pipe_in_dig;
sound/pci/mixart/mixart_hwdep.c
215
if(k & 1) {
sound/pci/mixart/mixart_hwdep.c
216
pipe->uid_right_connector = connector->uid[k]; /* odd */
sound/pci/mixart/mixart_hwdep.c
218
pipe->uid_left_connector = connector->uid[k]; /* even */
sound/pci/mixart/mixart_hwdep.c
225
request.uid = connector->uid[k];
sound/pci/mixart/mixart_hwdep.c
249
u32 k;
sound/pci/mixart/mixart_hwdep.c
294
for(k=0; k<mgr->num_cards; k++) {
sound/pci/mixart/mixart_hwdep.c
295
mgr->chip[k]->uid_in_analog_physio = phys_io.uid[k];
sound/pci/mixart/mixart_hwdep.c
296
mgr->chip[k]->uid_out_analog_physio = phys_io.uid[phys_io.nb_uid/2 + k];
sound/pci/mixart/mixart_hwdep.c
305
u32 k;
sound/pci/mixart/mixart_hwdep.c
324
err = snd_mixart_send_msg(mgr, &request, sizeof(k), &k);
sound/pci/mixart/mixart_hwdep.c
325
if( (err < 0) || (k != 0) ) {
sound/pci/rme9652/rme9652.c
1209
unsigned int k;
sound/pci/rme9652/rme9652.c
1212
for (k = 0; k < rme9652->ss_channels; ++k) {
sound/pci/rme9652/rme9652.c
1213
ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));
sound/pci/rme9652/rme9652.c
1729
unsigned int k;
sound/pci/rme9652/rme9652.c
1757
for (k = 0; k < RME9652_NCHANNELS; ++k)
sound/pci/rme9652/rme9652.c
1758
rme9652_write(rme9652, RME9652_thru_base + k * 4, 0);
sound/soc/amd/acp/acp-mach-common.c
1119
struct snd_kcontrol *k, int event)
sound/soc/amd/vangogh/acp5x-mach.c
62
struct snd_kcontrol *k, int event)
sound/soc/codecs/alc5623.h
119
#define ALC5623_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4)
sound/soc/codecs/alc5632.h
203
#define ALC5632_PLL1_CTRL_K_VAL(k) (((k) & 0x07) << 4)
sound/soc/codecs/aw88081.c
1172
struct snd_kcontrol *k, int event)
sound/soc/codecs/aw88166.c
1633
struct snd_kcontrol *k, int event)
sound/soc/codecs/aw88261.c
975
struct snd_kcontrol *k, int event)
sound/soc/codecs/aw88395/aw88395.c
364
struct snd_kcontrol *k, int event)
sound/soc/codecs/aw88399.c
1973
struct snd_kcontrol *k, int event)
sound/soc/codecs/max98088.c
686
struct snd_kcontrol *k, int event)
sound/soc/codecs/max98088.c
692
struct snd_kcontrol *k, int event)
sound/soc/codecs/max98088.c
698
struct snd_kcontrol *k, int event)
sound/soc/codecs/max98088.c
704
struct snd_kcontrol *k, int event)
sound/soc/codecs/max98095.c
658
struct snd_kcontrol *k, int event)
sound/soc/codecs/max98095.c
664
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8540.c
233
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8540.c
254
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8540.c
276
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8540.c
302
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8821.c
468
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8821.c
597
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8824.c
502
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8824.c
569
struct snd_kcontrol *k, int event)
sound/soc/codecs/nau8825.c
971
struct snd_kcontrol *k, int event)
sound/soc/codecs/pcm6240.c
1839
int j, k;
sound/soc/codecs/pcm6240.c
1860
for (k = 0; k < (int)blk_data[j]->n_subblks; k++) {
sound/soc/codecs/rl6231.c
144
int i, k, n_t;
sound/soc/codecs/rl6231.c
157
k = pll_preset_table[i].k;
sound/soc/codecs/rl6231.c
178
k = min_k;
sound/soc/codecs/rl6231.c
188
k = k_t;
sound/soc/codecs/rl6231.c
197
k = k_t;
sound/soc/codecs/rl6231.c
209
k = k_t;
sound/soc/codecs/rl6231.c
220
if (k == -1) {
sound/soc/codecs/rl6231.c
222
k = 0;
sound/soc/codecs/rl6231.c
229
pll_code->k_code = k;
sound/soc/codecs/rl6231.c
96
int k;
sound/soc/codecs/rt1318.c
795
int i, k, red, n_t, pll_out, in_t, out_t;
sound/soc/codecs/rt1318.c
806
k = pll_preset_table[i].k;
sound/soc/codecs/rt1318.c
815
k = 100000000 / freq_out - 2;
sound/soc/codecs/rt1318.c
816
if (k > RT1318_PLL_K_MAX)
sound/soc/codecs/rt1318.c
817
k = RT1318_PLL_K_MAX;
sound/soc/codecs/rt1318.c
818
if (k < 0) {
sound/soc/codecs/rt1318.c
819
k = 0;
sound/soc/codecs/rt1318.c
823
in_t = freq_in / (k_bypass ? 1 : (k + 2));
sound/soc/codecs/rt1318.c
862
pll_code->k_code = k;
sound/soc/codecs/rt1318.h
327
int k;
sound/soc/codecs/rt5631.h
563
#define RT5631_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4)
sound/soc/codecs/rt5645.c
1932
struct snd_kcontrol *k, int event)
sound/soc/codecs/rt5645.c
1957
struct snd_kcontrol *k, int event)
sound/soc/codecs/rt5682s.c
2384
(a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
sound/soc/codecs/rt5682s.c
2389
a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
sound/soc/codecs/rt5682s.c
2400
(b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
sound/soc/codecs/rt5682s.c
2406
b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
sound/soc/codecs/rt5682s.h
1439
int k;
sound/soc/codecs/tas2781-fmwlib.c
1024
int j, k, chn, chnend;
sound/soc/codecs/tas2781-fmwlib.c
1044
for (k = 0; k < (int)blk_data[j]->n_subblks; k++) {
sound/soc/codecs/tas2781-fmwlib.c
2050
int chn, k;
sound/soc/codecs/tas2781-fmwlib.c
2092
k = chn * (cali_data->cali_dat_sz_per_dev + 1);
sound/soc/codecs/tas2781-fmwlib.c
2098
COPY_CAL_DATA(k);
sound/soc/codecs/tas2781-fmwlib.c
2104
COPY_CAL_DATA(k + 4);
sound/soc/codecs/tas2781-fmwlib.c
2110
COPY_CAL_DATA(k + 8);
sound/soc/codecs/tas2781-fmwlib.c
2116
COPY_CAL_DATA(k + 12);
sound/soc/codecs/tas2781-fmwlib.c
2122
COPY_CAL_DATA(k + 16);
sound/soc/codecs/tas2781-fmwlib.c
2124
calbin_data[k] = chn;
sound/soc/codecs/tas2781-fmwlib.c
2482
int k = i * (cali_data->cali_dat_sz_per_dev + 1);
sound/soc/codecs/tas2781-fmwlib.c
2500
re_cal = data[k + 1] << 8 | data[k + 2];
sound/soc/codecs/tas2781-fmwlib.c
2550
int k = i * (cali_data->cali_dat_sz_per_dev + 1);
sound/soc/codecs/tas2781-fmwlib.c
2556
if (data[k] != i) {
sound/soc/codecs/tas2781-fmwlib.c
2561
k++;
sound/soc/codecs/tas2781-fmwlib.c
2569
rc = tasdevice_dev_bulk_write(priv, i, p->r0_reg, &(data[k]), 4);
sound/soc/codecs/tas2781-fmwlib.c
2574
k += 4;
sound/soc/codecs/tas2781-fmwlib.c
2575
rc = tasdevice_dev_bulk_write(priv, i, p->r0_low_reg, &(data[k]), 4);
sound/soc/codecs/tas2781-fmwlib.c
2580
k += 4;
sound/soc/codecs/tas2781-fmwlib.c
2581
rc = tasdevice_dev_bulk_write(priv, i, p->invr0_reg, &(data[k]), 4);
sound/soc/codecs/tas2781-fmwlib.c
2586
k += 4;
sound/soc/codecs/tas2781-fmwlib.c
2587
rc = tasdevice_dev_bulk_write(priv, i, p->pow_reg, &(data[k]), 4);
sound/soc/codecs/tas2781-fmwlib.c
2592
k += 4;
sound/soc/codecs/tas2781-fmwlib.c
2593
rc = tasdevice_dev_bulk_write(priv, i, p->tlimit_reg, &(data[k]), 4);
sound/soc/codecs/tas2781-i2c.c
254
unsigned int j, k;
sound/soc/codecs/tas2781-i2c.c
285
for (j = 0, k = 0; j < priv->ndev; j++) {
sound/soc/codecs/tas2781-i2c.c
286
if (j == data[k]) {
sound/soc/codecs/tas2781-i2c.c
288
k++;
sound/soc/codecs/tas2781-i2c.c
291
j, data[k]);
sound/soc/codecs/tas2781-i2c.c
292
k += 21;
sound/soc/codecs/tas2781-i2c.c
300
k += 20;
sound/soc/codecs/tas2781-i2c.c
303
rc = memcmp(&dst[i], &data[k], 4);
sound/soc/codecs/tas2781-i2c.c
306
k += 4;
sound/soc/codecs/tas2781-i2c.c
314
k += 16;
sound/soc/codecs/tas2781-i2c.c
317
rc = memcmp(&dst[i], &data[k], 4);
sound/soc/codecs/tas2781-i2c.c
321
k += 4;
sound/soc/codecs/tas2781-i2c.c
328
k += 12;
sound/soc/codecs/tas2781-i2c.c
331
rc = memcmp(&dst[i], &data[k], 4);
sound/soc/codecs/tas2781-i2c.c
335
k += 4;
sound/soc/codecs/tas2781-i2c.c
341
k += 8;
sound/soc/codecs/tas2781-i2c.c
344
rc = memcmp(&dst[i], &data[k], 4);
sound/soc/codecs/tas2781-i2c.c
348
k += 4;
sound/soc/codecs/tas2781-i2c.c
355
rc = memcmp(&dst[i], &data[k], 4);
sound/soc/codecs/tas2781-i2c.c
359
k += 4;
sound/soc/codecs/tas2781-i2c.c
503
int k = i * 9 + j;
sound/soc/codecs/tas2781-i2c.c
505
if (dat[k] != i) {
sound/soc/codecs/tas2781-i2c.c
510
sngl_calib_start(priv, i, reg, dat + k);
sound/soc/codecs/tas2783-sdw.c
813
struct snd_kcontrol *k, s32 event)
sound/soc/codecs/tas2783-sdw.c
835
struct snd_kcontrol *k, s32 event)
sound/soc/codecs/wm8350.c
1014
fll_div->k = K;
sound/soc/codecs/wm8350.c
1016
fll_div->k = 0;
sound/soc/codecs/wm8350.c
1047
freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
sound/soc/codecs/wm8350.c
1058
snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);
sound/soc/codecs/wm8350.c
1062
fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
sound/soc/codecs/wm8350.c
965
int k;
sound/soc/codecs/wm8400.c
845
u16 k;
sound/soc/codecs/wm8400.c
911
factors->k = K / 10;
sound/soc/codecs/wm8400.c
916
factors->n, factors->k, factors->fratio, factors->outdiv);
sound/soc/codecs/wm8400.c
965
snd_soc_component_write(component, WM8400_FLL_CONTROL_2, factors.k);
sound/soc/codecs/wm8510.c
268
unsigned int k;
sound/soc/codecs/wm8510.c
310
pll_div.k = K;
sound/soc/codecs/wm8510.c
333
snd_soc_component_write(component, WM8510_PLLK1, pll_div.k >> 18);
sound/soc/codecs/wm8510.c
334
snd_soc_component_write(component, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8510.c
335
snd_soc_component_write(component, WM8510_PLLK3, pll_div.k & 0x1ff);
sound/soc/codecs/wm8580.c
378
u32 k:24;
sound/soc/codecs/wm8580.c
451
pll_div->k = K;
sound/soc/codecs/wm8580.c
454
pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
sound/soc/codecs/wm8580.c
509
snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
sound/soc/codecs/wm8580.c
510
snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8580.c
512
(pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
sound/soc/codecs/wm8753.c
695
u32 k:24;
sound/soc/codecs/wm8753.c
735
pll_div->k = K;
sound/soc/codecs/wm8753.c
771
value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
sound/soc/codecs/wm8753.c
775
value = (pll_div.k & 0x03fe00) >> 9;
sound/soc/codecs/wm8753.c
779
value = pll_div.k & 0x0001ff;
sound/soc/codecs/wm8804.c
323
u32 k:22;
sound/soc/codecs/wm8804.c
395
pll_div->k = K;
sound/soc/codecs/wm8804.c
436
snd_soc_component_write(component, WM8804_PLL1, pll_div.k & 0xff);
sound/soc/codecs/wm8804.c
437
snd_soc_component_write(component, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
sound/soc/codecs/wm8804.c
438
snd_soc_component_write(component, WM8804_PLL3, pll_div.k >> 16);
sound/soc/codecs/wm8900.c
672
u16 k;
sound/soc/codecs/wm8900.c
736
fll_div->k = K / 10;
sound/soc/codecs/wm8900.c
785
if (fll_div.k) {
sound/soc/codecs/wm8900.c
787
(fll_div.k >> 8) | 0x100);
sound/soc/codecs/wm8900.c
788
snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
sound/soc/codecs/wm8904.c
1626
u16 k;
sound/soc/codecs/wm8904.c
1719
fll_div->k = K / 10;
sound/soc/codecs/wm8904.c
1722
fll_div->n, fll_div->k,
sound/soc/codecs/wm8904.c
1826
if (fll_div.k)
sound/soc/codecs/wm8904.c
1838
snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k);
sound/soc/codecs/wm8940.c
526
unsigned int k;
sound/soc/codecs/wm8940.c
579
pll_div.k = K;
sound/soc/codecs/wm8940.c
604
if (pll_div.k)
sound/soc/codecs/wm8940.c
610
snd_soc_component_write(component, WM8940_PLLK1, pll_div.k >> 18);
sound/soc/codecs/wm8940.c
611
snd_soc_component_write(component, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8940.c
612
snd_soc_component_write(component, WM8940_PLLK3, pll_div.k & 0x1ff);
sound/soc/codecs/wm8955.c
135
int k;
sound/soc/codecs/wm8955.c
185
pll->k = K / 10;
sound/soc/codecs/wm8955.c
187
dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
sound/soc/codecs/wm8955.c
294
pll.k >> 18);
sound/soc/codecs/wm8955.c
297
(pll.k >> 9) & WM8955_K_17_9_MASK);
sound/soc/codecs/wm8955.c
300
pll.k & WM8955_K_8_0_MASK);
sound/soc/codecs/wm8955.c
301
if (pll.k)
sound/soc/codecs/wm8960.c
1136
u32 k:24;
sound/soc/codecs/wm8960.c
1204
pll_div->k = K;
sound/soc/codecs/wm8960.c
1207
pll_div->n, pll_div->k, pll_div->pre_div);
sound/soc/codecs/wm8960.c
1237
if (pll_div.k) {
sound/soc/codecs/wm8960.c
1240
snd_soc_component_write(component, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
sound/soc/codecs/wm8960.c
1241
snd_soc_component_write(component, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
sound/soc/codecs/wm8960.c
1242
snd_soc_component_write(component, WM8960_PLL4, pll_div.k & 0xff);
sound/soc/codecs/wm8960.c
644
int i, j, k;
sound/soc/codecs/wm8960.c
661
for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
sound/soc/codecs/wm8960.c
662
diff = sysclk - bclk * bclk_divs[k] / 10;
sound/soc/codecs/wm8960.c
666
*bclk_idx = k;
sound/soc/codecs/wm8960.c
670
if (k != ARRAY_SIZE(bclk_divs))
sound/soc/codecs/wm8960.c
708
int i, j, k;
sound/soc/codecs/wm8960.c
730
for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
sound/soc/codecs/wm8960.c
734
diff = sysclk - bclk * bclk_divs[k] / 10;
sound/soc/codecs/wm8960.c
738
*bclk_idx = k;
sound/soc/codecs/wm8960.c
744
*bclk_idx = k;
sound/soc/codecs/wm8960.c
759
int i, j, k;
sound/soc/codecs/wm8960.c
799
ret = wm8960_configure_sysclk(wm8960, freq_out, &i, &j, &k);
sound/soc/codecs/wm8960.c
808
freq_out = wm8960_configure_pll(component, freq_in, &i, &j, &k);
sound/soc/codecs/wm8960.c
824
snd_soc_component_update_bits(component, WM8960_CLOCK2, 0xf, k);
sound/soc/codecs/wm8974.c
265
unsigned int k;
sound/soc/codecs/wm8974.c
309
pll_div->k = K;
sound/soc/codecs/wm8974.c
333
snd_soc_component_write(component, WM8974_PLLK1, pll_div.k >> 18);
sound/soc/codecs/wm8974.c
334
snd_soc_component_write(component, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8974.c
335
snd_soc_component_write(component, WM8974_PLLK3, pll_div.k & 0x1ff);
sound/soc/codecs/wm8978.c
401
u32 k;
sound/soc/codecs/wm8978.c
412
unsigned int k, n_div, n_mod;
sound/soc/codecs/wm8978.c
434
k = k_part & 0xFFFFFFFF;
sound/soc/codecs/wm8978.c
436
pll_div->k = k;
sound/soc/codecs/wm8978.c
539
__func__, pll_div.n, pll_div.k, pll_div.div2);
sound/soc/codecs/wm8978.c
545
snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18);
sound/soc/codecs/wm8978.c
546
snd_soc_component_write(component, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8978.c
547
snd_soc_component_write(component, WM8978_PLL_K3, pll_div.k & 0x1ff);
sound/soc/codecs/wm8983.c
746
u32 k:24;
sound/soc/codecs/wm8983.c
780
pll_div->k = K;
sound/soc/codecs/wm8983.c
812
snd_soc_component_write(component, WM8983_PLL_K_3, pll_div.k & 0x1ff);
sound/soc/codecs/wm8983.c
813
snd_soc_component_write(component, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8983.c
814
snd_soc_component_write(component, WM8983_PLL_K_1, (pll_div.k >> 18));
sound/soc/codecs/wm8985.c
843
u32 k:24;
sound/soc/codecs/wm8985.c
877
pll_div->k = K;
sound/soc/codecs/wm8985.c
905
snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff);
sound/soc/codecs/wm8985.c
906
snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
sound/soc/codecs/wm8985.c
907
snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18));
sound/soc/codecs/wm8990.c
799
u32 k;
sound/soc/codecs/wm8990.c
840
pll_div->k = K;
sound/soc/codecs/wm8990.c
863
snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8));
sound/soc/codecs/wm8990.c
864
snd_soc_component_write(component, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
sound/soc/codecs/wm8991.c
870
u32 k;
sound/soc/codecs/wm8991.c
911
pll_div->k = K;
sound/soc/codecs/wm8991.c
936
snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8));
sound/soc/codecs/wm8991.c
937
snd_soc_component_write(component, WM8991_PLL3, (u8)(pll_div.k & 0xFF));
sound/soc/codecs/wm8993.c
362
u16 k;
sound/soc/codecs/wm8993.c
456
fll_div->k = K / 10;
sound/soc/codecs/wm8993.c
459
fll_div->n, fll_div->k,
sound/soc/codecs/wm8993.c
524
if (fll_div.k)
sound/soc/codecs/wm8993.c
533
snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k);
sound/soc/codecs/wm8994.c
2116
u16 k;
sound/soc/codecs/wm8994.c
2188
fll->k = K / 10;
sound/soc/codecs/wm8994.c
2191
pr_debug("N=%x K=%x\n", fll->n, fll->k);
sound/soc/codecs/wm8994.c
2197
fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
sound/soc/codecs/wm8994.c
2327
WM8994_FLL1_K_MASK, fll.k);
sound/soc/codecs/wm8994.c
2396
if (fll.k)
sound/soc/codecs/wm8995.c
1718
u16 k;
sound/soc/codecs/wm8995.c
1787
fll->k = K / 10;
sound/soc/codecs/wm8995.c
1789
pr_debug("N=%x K=%x\n", fll->n, fll->k);
sound/soc/codecs/wm8995.c
1874
snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
sound/soc/codecs/wm9081.c
442
u16 k;
sound/soc/codecs/wm9081.c
535
fll_div->k = K / 10;
sound/soc/codecs/wm9081.c
538
fll_div->n, fll_div->k,
sound/soc/codecs/wm9081.c
597
if (fll_div.k)
sound/soc/codecs/wm9081.c
606
snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k);
sound/soc/codecs/wm9713.c
741
u32 k:24;
sound/soc/codecs/wm9713.c
803
pll_div->k = K;
sound/soc/codecs/wm9713.c
828
if (pll_div.k == 0) {
sound/soc/codecs/wm9713.c
838
reg = reg2 | (0x5 << 4) | (pll_div.k >> 20);
sound/soc/codecs/wm9713.c
842
reg = reg2 | (0x4 << 4) | ((pll_div.k >> 16) & 0xf);
sound/soc/codecs/wm9713.c
846
reg = reg2 | (0x3 << 4) | ((pll_div.k >> 12) & 0xf);
sound/soc/codecs/wm9713.c
850
reg = reg2 | (0x2 << 4) | ((pll_div.k >> 8) & 0xf);
sound/soc/codecs/wm9713.c
854
reg = reg2 | (0x1 << 4) | ((pll_div.k >> 4) & 0xf);
sound/soc/codecs/wm9713.c
857
reg = reg2 | (0x0 << 4) | (pll_div.k & 0xf); /* K [3:0] */
sound/soc/fsl/fsl_asrc_m2m.c
588
snd_pcm_format_t k;
sound/soc/fsl/fsl_asrc_m2m.c
596
pcm_for_each_format(k) {
sound/soc/fsl/fsl_asrc_m2m.c
597
if (pcm_format_to_bits(k) & cap.fmt_in) {
sound/soc/fsl/fsl_asrc_m2m.c
603
codec->descriptor[j].formats = (__force __u32)k;
sound/soc/fsl/fsl_utils.c
172
int i, j, k = 0;
sound/soc/fsl/fsl_utils.c
186
target_rates[k++] = original_constr->list[i];
sound/soc/intel/atom/sst-atom-controls.c
1030
ret = sst_send_pipe_module_params(w, k);
sound/soc/intel/atom/sst-atom-controls.c
1035
struct snd_kcontrol *k, int event)
sound/soc/intel/atom/sst-atom-controls.c
1068
ret = sst_send_pipe_module_params(w, k);
sound/soc/intel/atom/sst-atom-controls.c
533
struct snd_kcontrol *k, int event)
sound/soc/intel/atom/sst-atom-controls.c
536
return sst_send_pipe_module_params(w, k);
sound/soc/intel/atom/sst-atom-controls.c
623
struct snd_kcontrol *k, int event)
sound/soc/intel/atom/sst-atom-controls.c
978
struct snd_kcontrol *k, int event)
sound/soc/intel/atom/sst-atom-controls.c
992
ret = sst_send_pipe_module_params(w, k);
sound/soc/intel/atom/sst-atom-controls.c
998
struct snd_kcontrol *k, int event)
sound/soc/intel/avs/boards/da7219.c
30
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/bdw-rt5677.c
28
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/bytcr_rt5640.c
273
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/bytcr_rt5640.c
314
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/bytcr_rt5651.c
189
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/bytcr_wm5102.c
151
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/cht_bsw_max98090_ti.c
43
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/cht_bsw_rt5645.c
67
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/cht_bsw_rt5672.c
52
struct snd_kcontrol *k, int event)
sound/soc/intel/boards/sof_da7219.c
30
struct snd_kcontrol *k, int event)
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
265
u32 k = iir_coef_tbl_matrix[i][j];
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
267
if (k >= IIR_NO_NEED) {
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
268
} else if (k == IIR_RATIOVER) {
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
269
} else if (k == IIR_INV_COEF) {
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
271
coef = iir_coef_tbl_list[k].coef;
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
272
cnt = iir_coef_tbl_list[k].cnt;
sound/soc/meson/axg-tdm-formatter.c
35
int i, j, k;
sound/soc/meson/axg-tdm-formatter.c
52
for (k = 0; k < 2; k++) {
sound/soc/meson/axg-tdm-formatter.c
53
if ((BIT(i + k) & ts->mask[j]) && ch) {
sound/soc/meson/axg-tdm-formatter.c
54
val[j] |= BIT(i + k);
sound/soc/pxa/spitz.c
202
struct snd_kcontrol *k, int event)
sound/soc/rockchip/rk3288_hdmi_analog.c
32
struct snd_kcontrol *k, int event)
sound/soc/sdca/sdca_regmap.c
250
int i, j, k, l;
sound/soc/sdca/sdca_regmap.c
252
for (i = 0, k = 0; i < function->num_entities; i++) {
sound/soc/sdca/sdca_regmap.c
266
consts[k].reg = SDW_SDCA_CTL(function->desc->adr,
sound/soc/sdca/sdca_regmap.c
270
consts[k].def = control->values[l];
sound/soc/sdca/sdca_regmap.c
272
consts[k].def = control->reset;
sound/soc/sdca/sdca_regmap.c
273
k++;
sound/soc/sdca/sdca_regmap.c
279
return k;
sound/soc/soc-acpi.c
137
int i, j, k;
sound/soc/soc-acpi.c
170
for (k = 0; k < link->num_adr; k++) {
sound/soc/soc-acpi.c
171
u64 adr2 = link->adr_d[k].adr;
sound/soc/soc-topology.c
336
struct snd_kcontrol_new *k, struct snd_kcontrol **kcontrol)
sound/soc/soc-topology.c
341
tplg->dev, k, comp->name_prefix, comp, kcontrol);
sound/soc/soc-topology.c
460
struct snd_kcontrol_new *k,
sound/soc/soc-topology.c
468
&& k->iface & SNDRV_CTL_ELEM_IFACE_MIXER
sound/soc/soc-topology.c
469
&& (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_READ
sound/soc/soc-topology.c
470
|| k->access & SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
sound/soc/soc-topology.c
471
&& k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
sound/soc/soc-topology.c
475
sbe = (struct soc_bytes_ext *)k->private_value;
sound/soc/soc-topology.c
481
k->info = snd_soc_bytes_info_ext;
sound/soc/soc-topology.c
482
k->tlv.c = snd_soc_bytes_tlv_callback;
sound/soc/soc-topology.c
493
k->access |= SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK;
sound/soc/soc-topology.c
506
if ((k->access & SNDRV_CTL_ELEM_ACCESS_TLV_READ) && !sbe->get)
sound/soc/soc-topology.c
508
if ((k->access & SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) && !sbe->put)
sound/soc/soc-topology.c
518
if (k->put == NULL && ops[i].id == le32_to_cpu(hdr->ops.put))
sound/soc/soc-topology.c
519
k->put = ops[i].put;
sound/soc/soc-topology.c
520
if (k->get == NULL && ops[i].id == le32_to_cpu(hdr->ops.get))
sound/soc/soc-topology.c
521
k->get = ops[i].get;
sound/soc/soc-topology.c
522
if (k->info == NULL && ops[i].id == le32_to_cpu(hdr->ops.info))
sound/soc/soc-topology.c
523
k->info = ops[i].info;
sound/soc/soc-topology.c
527
if (k->put && k->get && k->info)
sound/soc/soc-topology.c
535
if (k->put == NULL && ops[i].id == le32_to_cpu(hdr->ops.put))
sound/soc/soc-topology.c
536
k->put = ops[i].put;
sound/soc/soc-topology.c
537
if (k->get == NULL && ops[i].id == le32_to_cpu(hdr->ops.get))
sound/soc/soc-topology.c
538
k->get = ops[i].get;
sound/soc/soc-topology.c
539
if (k->info == NULL && ops[i].id == le32_to_cpu(hdr->ops.info))
sound/soc/soc-topology.c
540
k->info = ops[i].info;
sound/soc/soc-topology.c
544
if (k->put && k->get && k->info)
sound/soc/soc-topology.c
576
struct snd_kcontrol_new *k, struct snd_soc_tplg_ctl_hdr *hdr)
sound/soc/soc-topology.c
581
ret = tplg->ops->control_load(tplg->comp, tplg->index, k, hdr);
sound/soc/sof/ipc3-topology.c
1980
struct snd_kcontrol *k, int event)
sound/soc/sti/sti_uniperif.c
216
int i, j, k;
sound/soc/sti/sti_uniperif.c
227
for (i = 0, j = 0, k = 0; (i < slots_num) && (k < WORD_MAX); i++) {
sound/soc/sti/sti_uniperif.c
238
word_pos[k] = word16_pos[1] |
sound/soc/sti/sti_uniperif.c
243
k++;
sound/soc/sunxi/sun4i-codec.c
1664
struct snd_kcontrol *k, int event)
sound/soc/sunxi/sun8i-codec-analog.c
344
struct snd_kcontrol *k, int event)
sound/soc/tegra/tegra_asoc_machine.c
79
struct snd_kcontrol *k, int event)
sound/soc/ti/ams-delta.c
28
struct snd_kcontrol *k, int event)
sound/soc/ti/ams-delta.c
35
struct snd_kcontrol *k, int event)
sound/soc/ti/n810.c
191
struct snd_kcontrol *k, int event)
sound/soc/ti/n810.c
202
struct snd_kcontrol *k, int event)
sound/soc/ti/omap3pandora.c
65
struct snd_kcontrol *k, int event)
sound/soc/ti/omap3pandora.c
93
struct snd_kcontrol *k, int event)
sound/soc/ti/rx51.c
140
struct snd_kcontrol *k, int event)
sound/usb/6fire/pcm.c
155
int k;
sound/usb/6fire/pcm.c
163
for (k = 0; k < PCM_N_PACKETS_PER_URB; k++) {
sound/usb/6fire/pcm.c
164
packet = &rt->in_urbs[i].packets[k];
sound/usb/6fire/pcm.c
165
packet->offset = k * rt->in_packet_size;
sound/usb/mixer_scarlett2.c
5355
int err, i, j, k, src_idx, dst_idx;
sound/usb/mixer_scarlett2.c
5404
for (k = 0;
sound/usb/mixer_scarlett2.c
5405
k < SCARLETT2_BIQUAD_COEFFS;
sound/usb/mixer_scarlett2.c
5406
k++, src_idx++, dst_idx++)
sound/usb/mixer_scarlett2.c
7048
int err, i, j, k, index;
sound/usb/mixer_scarlett2.c
7083
for (k = 0; k < private->num_mix_in; k++, index++) {
sound/usb/mixer_scarlett2.c
7087
mix_type, 'A' + j, k + 1);
tools/bpf/bpf_dbg.c
1027
&tmp.code, &tmp.jt, &tmp.jf, &tmp.k) != 4) {
tools/bpf/bpf_dbg.c
1035
bpf_image[i].k = tmp.k;
tools/bpf/bpf_dbg.c
219
int val = f.k;
tools/bpf/bpf_dbg.c
302
val = i + 1 + f.k;
tools/bpf/bpf_dbg.c
444
f->code, f->jt, f->jf, f->k);
tools/bpf/bpf_dbg.c
495
f[i].code, f[i].jt, f[i].jf, f[i].k);
tools/bpf/bpf_dbg.c
519
f[i].k > SKF_AD_OFF) {
tools/bpf/bpf_dbg.c
636
uint32_t K = f->k;
tools/bpf/bpf_exp.y
43
static void bpf_set_curr_instr(uint16_t op, uint8_t jt, uint8_t jf, uint32_t k);
tools/bpf/bpf_exp.y
480
uint32_t k)
tools/bpf/bpf_exp.y
486
out[curr_instr].k = k;
tools/bpf/bpf_exp.y
543
out[i].k = (uint32_t) (off - i - 1);
tools/bpf/bpf_exp.y
597
out[i].jt, out[i].jf, out[i].k);
tools/bpf/bpf_exp.y
607
out[i].jt, out[i].jf, out[i].k);
tools/hv/hv_kvp_daemon.c
299
int j, k;
tools/hv/hv_kvp_daemon.c
328
k = j + 1;
tools/hv/hv_kvp_daemon.c
329
for (; k < num_records; k++) {
tools/hv/hv_kvp_daemon.c
330
strcpy(record[j].key, record[k].key);
tools/hv/hv_kvp_daemon.c
331
strcpy(record[j].value, record[k].value);
tools/iio/iio_generic_buffer.c
186
int k;
tools/iio/iio_generic_buffer.c
188
for (k = 0; k < num_channels; k++)
tools/iio/iio_generic_buffer.c
189
switch (channels[k].bytes) {
tools/iio/iio_generic_buffer.c
192
print1byte(*(uint8_t *)(data + channels[k].location),
tools/iio/iio_generic_buffer.c
193
&channels[k]);
tools/iio/iio_generic_buffer.c
196
print2byte(*(uint16_t *)(data + channels[k].location),
tools/iio/iio_generic_buffer.c
197
&channels[k]);
tools/iio/iio_generic_buffer.c
200
print4byte(*(uint32_t *)(data + channels[k].location),
tools/iio/iio_generic_buffer.c
201
&channels[k]);
tools/iio/iio_generic_buffer.c
204
print8byte(*(uint64_t *)(data + channels[k].location),
tools/iio/iio_generic_buffer.c
205
&channels[k]);
tools/include/linux/jhash.h
100
case 2: a += (u32)k[1]<<8;
tools/include/linux/jhash.h
101
case 1: a += k[0];
tools/include/linux/jhash.h
117
static inline u32 jhash2(const u32 *k, u32 length, u32 initval)
tools/include/linux/jhash.h
126
a += k[0];
tools/include/linux/jhash.h
127
b += k[1];
tools/include/linux/jhash.h
128
c += k[2];
tools/include/linux/jhash.h
131
k += 3;
tools/include/linux/jhash.h
136
case 3: c += k[2];
tools/include/linux/jhash.h
137
case 2: b += k[1];
tools/include/linux/jhash.h
138
case 1: a += k[0];
tools/include/linux/jhash.h
73
const u8 *k = key;
tools/include/linux/jhash.h
80
a += __get_unaligned_cpu32(k);
tools/include/linux/jhash.h
81
b += __get_unaligned_cpu32(k + 4);
tools/include/linux/jhash.h
82
c += __get_unaligned_cpu32(k + 8);
tools/include/linux/jhash.h
85
k += 12;
tools/include/linux/jhash.h
90
case 12: c += (u32)k[11]<<24;
tools/include/linux/jhash.h
91
case 11: c += (u32)k[10]<<16;
tools/include/linux/jhash.h
92
case 10: c += (u32)k[9]<<8;
tools/include/linux/jhash.h
93
case 9: c += k[8];
tools/include/linux/jhash.h
94
case 8: b += (u32)k[7]<<24;
tools/include/linux/jhash.h
95
case 7: b += (u32)k[6]<<16;
tools/include/linux/jhash.h
96
case 6: b += (u32)k[5]<<8;
tools/include/linux/jhash.h
97
case 5: b += k[4];
tools/include/linux/jhash.h
98
case 4: a += (u32)k[3]<<24;
tools/include/linux/jhash.h
99
case 3: a += (u32)k[2]<<16;
tools/include/linux/kernel.h
94
#define current_gfp_context(k) 0
tools/include/uapi/linux/filter.h
28
__u32 k; /* Generic multiuse field */
tools/include/uapi/linux/filter.h
49
#define BPF_STMT(code, k) { (unsigned short)(code), 0, 0, k }
tools/include/uapi/linux/filter.h
52
#define BPF_JUMP(code, k, jt, jf) { (unsigned short)(code), jt, jf, k }
tools/lib/bitmap.c
10
unsigned int k, w = 0, lim = bits/BITS_PER_LONG;
tools/lib/bitmap.c
12
for (k = 0; k < lim; k++)
tools/lib/bitmap.c
13
w += hweight_long(bitmap[k]);
tools/lib/bitmap.c
147
unsigned int k;
tools/lib/bitmap.c
151
for (k = 0; k < lim; k++)
tools/lib/bitmap.c
152
result |= (dst[k] = bitmap1[k] & ~bitmap2[k]);
tools/lib/bitmap.c
154
result |= (dst[k] = bitmap1[k] & ~bitmap2[k] &
tools/lib/bitmap.c
16
w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits));
tools/lib/bitmap.c
162
unsigned int k, lim = bits/BITS_PER_LONG;
tools/lib/bitmap.c
163
for (k = 0; k < lim; ++k)
tools/lib/bitmap.c
164
if (bitmap1[k] & ~bitmap2[k])
tools/lib/bitmap.c
168
if ((bitmap1[k] & ~bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits))
tools/lib/bitmap.c
24
int k;
tools/lib/bitmap.c
27
for (k = 0; k < nr; k++)
tools/lib/bitmap.c
28
dst[k] = bitmap1[k] | bitmap2[k];
tools/lib/bitmap.c
63
unsigned int k;
tools/lib/bitmap.c
67
for (k = 0; k < lim; k++)
tools/lib/bitmap.c
68
result |= (dst[k] = bitmap1[k] & bitmap2[k]);
tools/lib/bitmap.c
70
result |= (dst[k] = bitmap1[k] & bitmap2[k] &
tools/lib/bitmap.c
78
unsigned int k, lim = bits/BITS_PER_LONG;
tools/lib/bitmap.c
79
for (k = 0; k < lim; ++k)
tools/lib/bitmap.c
80
if (bitmap1[k] != bitmap2[k])
tools/lib/bitmap.c
84
if ((bitmap1[k] ^ bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits))
tools/lib/bitmap.c
93
unsigned int k, lim = bits/BITS_PER_LONG;
tools/lib/bitmap.c
94
for (k = 0; k < lim; ++k)
tools/lib/bitmap.c
95
if (bitmap1[k] & bitmap2[k])
tools/lib/bitmap.c
99
if ((bitmap1[k] & bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits))
tools/lib/bpf/libbpf.c
1128
int i, j, k, vlen;
tools/lib/bpf/libbpf.c
1147
for (k = 0; k < vlen; ++k) {
tools/lib/bpf/libbpf.c
1148
slot_prog = map->st_ops->progs[k];
tools/lib/perf/cpumap.c
414
int i, j, k;
tools/lib/perf/cpumap.c
431
i = j = k = 0;
tools/lib/perf/cpumap.c
436
tmp_cpus[k++] = __perf_cpu_map__cpu(*orig, i++);
tools/lib/perf/cpumap.c
438
tmp_cpus[k++] = __perf_cpu_map__cpu(other, j++);
tools/lib/perf/cpumap.c
442
tmp_cpus[k++] = __perf_cpu_map__cpu(*orig, i++);
tools/lib/perf/cpumap.c
445
tmp_cpus[k++] = __perf_cpu_map__cpu(other, j++);
tools/lib/perf/cpumap.c
446
assert(k <= tmp_len);
tools/lib/perf/cpumap.c
448
merged = cpu_map__trim_new(k, tmp_cpus);
tools/lib/perf/cpumap.c
458
int i, j, k;
tools/lib/perf/cpumap.c
466
i = j = k = 0;
tools/lib/perf/cpumap.c
475
k++;
tools/lib/perf/cpumap.c
478
if (k == 0) /* Maps are completely disjoint. */
tools/lib/perf/cpumap.c
481
merged = perf_cpu_map__alloc(k);
tools/lib/perf/cpumap.c
485
i = j = k = 0;
tools/lib/perf/cpumap.c
493
RC_CHK_ACCESS(merged)->map[k++] = __perf_cpu_map__cpu(orig, i++);
tools/mm/page-types.c
610
size_t k = HASH_KEY(flags);
tools/mm/page-types.c
620
for (i = 1; i < ARRAY_SIZE(page_flags); i++, k++) {
tools/mm/page-types.c
621
if (!k || k >= ARRAY_SIZE(page_flags))
tools/mm/page-types.c
622
k = 1;
tools/mm/page-types.c
623
if (page_flags[k] == 0) {
tools/mm/page-types.c
624
page_flags[k] = flags;
tools/mm/page-types.c
625
return k;
tools/mm/page-types.c
627
if (page_flags[k] == flags)
tools/mm/page-types.c
628
return k;
tools/perf/bench/inject-buildid.c
352
unsigned int i, k;
tools/perf/bench/inject-buildid.c
374
for (k = 0; k < nr_samples; k++) {
tools/perf/bench/inject-buildid.c
375
if (synthesize_sample(data, dso, timestamp + k * 1000) < 0)
tools/perf/builtin-inject.c
401
u64 i, k;
tools/perf/builtin-inject.c
441
for (k = 0; k < cursor->nr && i < PERF_MAX_STACK_DEPTH; k++) {
tools/perf/builtin-probe.c
346
int i, k;
tools/perf/builtin-probe.c
369
for (i = k = 0; i < npevs; i++)
tools/perf/builtin-probe.c
370
k += pevs[i].ntevs;
tools/perf/builtin-probe.c
372
pr_info("Added new event%s\n", (k > 1) ? "s:" : ":");
tools/perf/builtin-probe.c
376
for (k = 0; k < pev->ntevs; k++) {
tools/perf/builtin-probe.c
377
struct probe_trace_event *tev = &pev->tevs[k];
tools/perf/tests/event_groups.c
105
if (!i && !j && !k)
tools/perf/tests/event_groups.c
106
sibling_fd2 = event_open(types[k], configs_hw[k], group_fd);
tools/perf/tests/event_groups.c
108
sibling_fd2 = event_open(types[k], configs[k], group_fd);
tools/perf/tests/event_groups.c
123
int i, j, k;
tools/perf/tests/event_groups.c
134
for (k = 0; k < 3; k++) {
tools/perf/tests/event_groups.c
135
r = run_test(i, j, k);
tools/perf/tests/event_groups.c
143
if (!i && !j && !k)
tools/perf/tests/event_groups.c
146
types[k], configs_hw[k], r ? "Fail" : "Pass");
tools/perf/tests/event_groups.c
150
types[k], configs[k], r ? "Fail" : "Pass");
tools/perf/tests/event_groups.c
82
static int run_test(int i, int j, int k)
tools/perf/tests/event_groups.c
84
int erroneous = ((((1 << i) | (1 << j) | (1 << k)) & 5) == 5);
tools/perf/tests/hists_common.c
128
size_t k;
tools/perf/tests/hists_common.c
138
for (k = 0; k < fake_symbols[i].nr_syms; k++) {
tools/perf/tests/hists_common.c
140
struct fake_sym *fsym = &fake_symbols[i].syms[k];
tools/perf/tests/hists_link.c
100
map__put(fake_common_samples[k].map);
tools/perf/tests/hists_link.c
101
fake_common_samples[k].map = map__get(al.map);
tools/perf/tests/hists_link.c
102
fake_common_samples[k].sym = al.sym;
tools/perf/tests/hists_link.c
105
for (k = 0; k < ARRAY_SIZE(fake_samples[i]); k++) {
tools/perf/tests/hists_link.c
106
sample.pid = fake_samples[i][k].pid;
tools/perf/tests/hists_link.c
107
sample.tid = fake_samples[i][k].pid;
tools/perf/tests/hists_link.c
108
sample.ip = fake_samples[i][k].ip;
tools/perf/tests/hists_link.c
118
thread__put(fake_samples[i][k].thread);
tools/perf/tests/hists_link.c
119
fake_samples[i][k].thread = thread__get(al.thread);
tools/perf/tests/hists_link.c
120
map__put(fake_samples[i][k].map);
tools/perf/tests/hists_link.c
121
fake_samples[i][k].map = map__get(al.map);
tools/perf/tests/hists_link.c
122
fake_samples[i][k].sym = al.sym;
tools/perf/tests/hists_link.c
72
size_t i = 0, k;
tools/perf/tests/hists_link.c
83
for (k = 0; k < ARRAY_SIZE(fake_common_samples); k++) {
tools/perf/tests/hists_link.c
85
sample.pid = fake_common_samples[k].pid;
tools/perf/tests/hists_link.c
86
sample.tid = fake_common_samples[k].pid;
tools/perf/tests/hists_link.c
87
sample.ip = fake_common_samples[k].ip;
tools/perf/tests/hists_link.c
98
thread__put(fake_common_samples[k].thread);
tools/perf/tests/hists_link.c
99
fake_common_samples[k].thread = thread__get(al.thread);
tools/perf/tests/kmod-path.c
44
#define T(path, an, k, c, n) \
tools/perf/tests/kmod-path.c
45
TEST_ASSERT_VAL("failed", !test(path, an, k, c, n))
tools/perf/tests/pmu-events.c
825
int k;
tools/perf/tests/pmu-events.c
871
k = 1;
tools/perf/tests/pmu-events.c
874
evsel->stats->aggr->counts.val = k;
tools/perf/tests/pmu-events.c
875
k++;
tools/perf/ui/browsers/annotate-data.c
56
int i, k;
tools/perf/ui/browsers/annotate-data.c
63
k = 0;
tools/perf/ui/browsers/annotate-data.c
70
update_hist_entry(&entry->hists[k++], &h->addr[offset]);
tools/perf/util/bpf_skel/lock_contention.bpf.c
901
for (int k = 0; k < MAX_ZONES; k++) {
tools/perf/util/bpf_skel/lock_contention.bpf.c
904
if (k >= nr_zones)
tools/perf/util/bpf_skel/lock_contention.bpf.c
907
zone_addr = (__u64)(void *)pgdat + (sizeof_zone * k) + zone_off;
tools/perf/util/bpf_skel/sample_filter.bpf.c
212
int i, k;
tools/perf/util/bpf_skel/sample_filter.bpf.c
217
k = 0;
tools/perf/util/bpf_skel/sample_filter.bpf.c
239
k = *idx;
tools/perf/util/bpf_skel/sample_filter.bpf.c
244
entry = bpf_map_lookup_elem(&filters, &k);
tools/perf/util/bpf_skel/sample_filter.bpf.c
291
losts = bpf_map_lookup_elem(&dropped, &k);
tools/perf/util/config.c
556
static int perf_env_bool(const char *k, int def)
tools/perf/util/config.c
558
const char *v = getenv(k);
tools/perf/util/config.c
559
return v ? perf_config_bool(k, v) : def;
tools/perf/util/cs-etm.c
2950
int i, k;
tools/perf/util/cs-etm.c
2967
for (k = CS_ETM_COMMON_BLK_MAX_V1 - 1; k < nr_in_params; k++)
tools/perf/util/cs-etm.c
2968
metadata[k + 1] = buff_in[i + k];
tools/perf/util/cs-etm.c
2982
for (k = CS_ETM_MAGIC; k < nr_out_params; k++)
tools/perf/util/cs-etm.c
2983
metadata[k] = buff_in[i + k];
tools/perf/util/demangle-rust-v0.c
318
size_t delta = 0, w = 1, k = 0;
tools/perf/util/demangle-rust-v0.c
320
k += base;
tools/perf/util/demangle-rust-v0.c
321
size_t biased = k < bias ? 0 : k - bias;
tools/perf/util/demangle-rust-v0.c
386
k = 0;
tools/perf/util/demangle-rust-v0.c
389
k += base;
tools/perf/util/demangle-rust-v0.c
391
bias = k + ((base - t_min + 1) * delta) / (delta + skew);
tools/perf/util/hist.c
369
for (int k = 0; k < MEM_STAT_LEN; k++)
tools/perf/util/hist.c
370
dst->mem_stat[i].entries[k] += src->mem_stat[i].entries[k];
tools/perf/util/hist.c
385
for (int k = 0; k < MEM_STAT_LEN; k++)
tools/perf/util/hist.c
386
dst->mem_stat[i].entries[k] = src->mem_stat[i].entries[k];
tools/perf/util/hist.c
397
for (int k = 0; k < MEM_STAT_LEN; k++)
tools/perf/util/hist.c
398
he->mem_stat[i].entries[k] = (he->mem_stat[i].entries[k] * 7) / 8;
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
4143
size_t k;
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
4148
k = len - INTEL_PT_PSB_LEN + 1;
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
4150
p = memrchr(buf, n[0], k);
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
4155
k = p - buf;
tools/perf/util/intel-pt-decoder/intel-pt-decoder.c
4156
if (!k)
tools/perf/util/symbol-elf.c
2096
#define kcore_copy__for_each_phdr(k, p) \
tools/perf/util/symbol-elf.c
2097
list_for_each_entry((p), &(k)->phdrs, node)
tools/perf/util/symbol-elf.c
2288
struct phdr_data *p, *k = NULL;
tools/perf/util/symbol-elf.c
2299
k = p;
tools/perf/util/symbol-elf.c
2304
if (!k)
tools/perf/util/symbol-elf.c
2307
kend = k->offset + k->len;
tools/perf/util/symbol-elf.c
2313
if (p == k)
tools/perf/util/symbol-elf.c
2316
if (p->offset >= k->offset && pend <= kend)
tools/perf/util/symbol-elf.c
2317
p->remaps = k;
tools/perf/util/symbol-elf.c
2337
struct phdr_data *k = p->remaps;
tools/perf/util/symbol-elf.c
2339
if (k)
tools/perf/util/symbol-elf.c
2340
p->rel = p->offset - k->offset + k->rel;
tools/power/x86/intel-speed-select/isst-config.c
560
int i, j, k;
tools/power/x86/intel-speed-select/isst-config.c
593
for (k = 0; k < MAX_PUNIT_PER_DIE && k < MAX_DIE_PER_PACKAGE; k++) {
tools/power/x86/intel-speed-select/isst-config.c
594
id.cpu = cpus[i][k][k];
tools/power/x86/intel-speed-select/isst-config.c
597
id.punit = k;
tools/power/x86/intel-speed-select/isst-config.c
611
for (k = 0; k < MAX_PUNIT_PER_DIE; k++) {
tools/power/x86/intel-speed-select/isst-config.c
612
id.cpu = cpus[i][j][k];
tools/power/x86/intel-speed-select/isst-config.c
618
id.punit = k;
tools/power/x86/intel-speed-select/isst-core-mbox.c
751
int i, k, ret;
tools/power/x86/intel-speed-select/isst-core-mbox.c
773
for (k = 0; k < trl_max_levels; ++k) {
tools/power/x86/intel-speed-select/isst-core-mbox.c
780
(k << 16) | (i << 8) | level, &resp);
tools/power/x86/intel-speed-select/isst-core-mbox.c
786
id->cpu, i, level, k, resp);
tools/power/x86/intel-speed-select/isst-core-mbox.c
789
bucket_info[j + (i * 4)].hp_ratios[k] =
tools/power/x86/intel-speed-select/isst-daemon.c
28
int i, j, k;
tools/power/x86/intel-speed-select/isst-daemon.c
32
for (k = 0; k < MAX_PUNIT_PER_DIE; ++k)
tools/power/x86/intel-speed-select/isst-daemon.c
33
per_package_levels_info[i][j][k] = -1;
tools/power/x86/intel-speed-select/isst-display.c
147
int k = 0;
tools/power/x86/intel-speed-select/isst-display.c
150
k += snprintf(&delimiters[k],
tools/power/x86/intel-speed-select/isst-display.c
151
sizeof(delimiters) - k,
tools/power/x86/intel-speed-select/isst-display.c
371
int j, k;
tools/power/x86/intel-speed-select/isst-display.c
551
for (k = 0; k < trl_max_levels; k++) {
tools/power/x86/intel-speed-select/isst-display.c
552
if (!ctdp_level->trl_ratios[k][0])
tools/power/x86/intel-speed-select/isst-display.c
555
snprintf(header, sizeof(header), "turbo-ratio-limits-%s", isst_get_trl_level_name(k));
tools/power/x86/intel-speed-select/isst-display.c
568
snprintf(value, sizeof(value), "%d", ctdp_level->trl_ratios[k][j] * isst_get_disp_freq_multiplier());
tools/power/x86/turbostat/turbostat.c
7151
int k, l;
tools/power/x86/turbostat/turbostat.c
7166
k = read_sysfs_int(path);
tools/power/x86/turbostat/turbostat.c
7169
fprintf(outf, "Uncore Frequency package%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
tools/power/x86/turbostat/turbostat.c
7172
k = read_sysfs_int(path);
tools/power/x86/turbostat/turbostat.c
7175
fprintf(outf, "(%d - %d MHz)", k / 1000, l / 1000);
tools/power/x86/turbostat/turbostat.c
7178
k = read_sysfs_int(path);
tools/power/x86/turbostat/turbostat.c
7179
fprintf(outf, " %d MHz\n", k / 1000);
tools/power/x86/turbostat/turbostat.c
7204
int k, l;
tools/power/x86/turbostat/turbostat.c
7243
k = read_sysfs_int(path);
tools/power/x86/turbostat/turbostat.c
7246
fprintf(outf, "Uncore Frequency package%d domain%d cluster%d: %d - %d MHz ", unc_pkg_id, domain_id, cluster_id, k / 1000, l / 1000);
tools/power/x86/turbostat/turbostat.c
7249
k = read_sysfs_int(path);
tools/power/x86/turbostat/turbostat.c
7252
fprintf(outf, "(%d - %d MHz)", k / 1000, l / 1000);
tools/power/x86/turbostat/turbostat.c
7255
k = read_sysfs_int(path);
tools/power/x86/turbostat/turbostat.c
7256
fprintf(outf, " %d MHz\n", k / 1000);
tools/testing/radix-tree/multiorder.c
101
for (k = i; index[k] < tag_index[i]; k++)
tools/testing/radix-tree/multiorder.c
103
if (j <= (index[k] | ((1 << order[k]) - 1)))
tools/testing/radix-tree/multiorder.c
110
for (k = i; index[k] < tag_index[i]; k++)
tools/testing/radix-tree/multiorder.c
112
mask = (1UL << order[k]) - 1;
tools/testing/radix-tree/multiorder.c
117
assert(item->order == order[k]);
tools/testing/radix-tree/multiorder.c
126
int mask, k;
tools/testing/radix-tree/multiorder.c
129
for (k = i; index[k] < tag_index[i]; k++)
tools/testing/radix-tree/multiorder.c
131
if (j <= (index[k] | ((1 << order[k]) - 1)))
tools/testing/radix-tree/multiorder.c
137
for (k = i; index[k] < tag_index[i]; k++)
tools/testing/radix-tree/multiorder.c
139
mask = (1 << order[k]) - 1;
tools/testing/radix-tree/multiorder.c
144
assert(item->order == order[k]);
tools/testing/radix-tree/multiorder.c
98
int k;
tools/testing/selftests/arm64/fp/fp-ptrace.c
1573
int i, j, k;
tools/testing/selftests/arm64/fp/fp-ptrace.c
1590
for (k = 0; k < ARRAY_SIZE(svcr_combinations); k++) {
tools/testing/selftests/arm64/fp/fp-ptrace.c
1591
test_config.svcr_in = svcr_combinations[k].svcr_in;
tools/testing/selftests/arm64/fp/fp-ptrace.c
1592
test_config.svcr_expected = svcr_combinations[k].svcr_expected;
tools/testing/selftests/bpf/benchs/bench_lpm_trie_map.c
208
struct trie_key *k = &keys[i];
tools/testing/selftests/bpf/benchs/bench_lpm_trie_map.c
211
k->prefixlen = args.prefixlen;
tools/testing/selftests/bpf/benchs/bench_lpm_trie_map.c
212
k->data = i;
tools/testing/selftests/bpf/prog_tests/hashmap.c
106
long oldk, k = i;
tools/testing/selftests/bpf/prog_tests/hashmap.c
109
err = hashmap__add(map, k, v);
tools/testing/selftests/bpf/prog_tests/hashmap.c
115
err = hashmap__update(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
117
err = hashmap__set(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
121
k, v, err))
tools/testing/selftests/bpf/prog_tests/hashmap.c
123
if (CHECK(!hashmap__find(map, k, &oldv), "elem_find",
tools/testing/selftests/bpf/prog_tests/hashmap.c
124
"failed to find key %ld\n", k))
tools/testing/selftests/bpf/prog_tests/hashmap.c
14
static size_t hash_fn(long k, void *ctx)
tools/testing/selftests/bpf/prog_tests/hashmap.c
141
long k = entry->key;
tools/testing/selftests/bpf/prog_tests/hashmap.c
144
found_msk |= 1ULL << k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
145
if (CHECK(v - k != 256, "elem_check",
tools/testing/selftests/bpf/prog_tests/hashmap.c
146
"invalid updated k/v pair: %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
16
return k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
164
long oldk, k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
167
k = entry->key;
tools/testing/selftests/bpf/prog_tests/hashmap.c
171
found_msk |= 1ULL << k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
173
if (CHECK(!hashmap__delete(map, k, &oldk, &oldv), "elem_del",
tools/testing/selftests/bpf/prog_tests/hashmap.c
174
"failed to delete k/v %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
176
if (CHECK(oldk != k || oldv != v, "check_old",
tools/testing/selftests/bpf/prog_tests/hashmap.c
178
k, v, oldk, oldv))
tools/testing/selftests/bpf/prog_tests/hashmap.c
180
if (CHECK(hashmap__delete(map, k, &oldk, &oldv), "elem_del",
tools/testing/selftests/bpf/prog_tests/hashmap.c
198
long oldk, k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
201
k = entry->key;
tools/testing/selftests/bpf/prog_tests/hashmap.c
205
found_msk |= 1ULL << k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
207
if (CHECK(!hashmap__delete(map, k, &oldk, &oldv), "elem_del",
tools/testing/selftests/bpf/prog_tests/hashmap.c
208
"failed to delete k/v %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
210
if (CHECK(oldk != k || oldv != v, "elem_check",
tools/testing/selftests/bpf/prog_tests/hashmap.c
212
k, v, oldk, oldv))
tools/testing/selftests/bpf/prog_tests/hashmap.c
214
if (CHECK(hashmap__delete(map, k, &oldk, &oldv), "elem_del",
tools/testing/selftests/bpf/prog_tests/hashmap.c
215
"unexpectedly deleted k/v %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
334
static size_t collision_hash_fn(long k, void *ctx)
tools/testing/selftests/bpf/prog_tests/hashmap.c
416
long k = 0;
tools/testing/selftests/bpf/prog_tests/hashmap.c
429
if (CHECK(hashmap__find(map, k, NULL), "elem_find",
tools/testing/selftests/bpf/prog_tests/hashmap.c
432
if (CHECK(hashmap__delete(map, k, NULL, NULL), "elem_del",
tools/testing/selftests/bpf/prog_tests/hashmap.c
440
hashmap__for_each_key_entry(map, entry, k) {
tools/testing/selftests/bpf/prog_tests/hashmap.c
56
long oldk, k = i;
tools/testing/selftests/bpf/prog_tests/hashmap.c
59
err = hashmap__update(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
65
err = hashmap__add(map, k, v);
tools/testing/selftests/bpf/prog_tests/hashmap.c
67
err = hashmap__set(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
73
if (CHECK(err, "elem_add", "failed to add k/v %ld = %ld: %d\n", k, v, err))
tools/testing/selftests/bpf/prog_tests/hashmap.c
76
if (CHECK(!hashmap__find(map, k, &oldv), "elem_find",
tools/testing/selftests/bpf/prog_tests/hashmap.c
77
"failed to find key %ld\n", k))
tools/testing/selftests/bpf/prog_tests/hashmap.c
93
long k = entry->key;
tools/testing/selftests/bpf/prog_tests/hashmap.c
96
found_msk |= 1ULL << k;
tools/testing/selftests/bpf/prog_tests/hashmap.c
97
if (CHECK(v - k != 1024, "check_kv",
tools/testing/selftests/bpf/prog_tests/hashmap.c
98
"invalid k/v pair: %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/test_task_work.c
35
int k, sz;
tools/testing/selftests/bpf/prog_tests/test_task_work.c
38
for (k = 0; k < sz; ++k) {
tools/testing/selftests/bpf/prog_tests/test_task_work.c
39
err = bpf_map__lookup_elem(map, &k, sizeof(int), &value, sizeof(struct elem), 0);
tools/testing/selftests/bpf/prog_tests/timer_lockup.c
17
volatile int k = 0;
tools/testing/selftests/bpf/progs/btf_dump_test_case_syntax.c
143
fn_ptr_arr1_t k;
tools/testing/selftests/bpf/progs/fentry_many_args.c
22
int g, unsigned int h, long i, __u64 j, unsigned long k)
tools/testing/selftests/bpf/progs/fentry_many_args.c
26
i == 24 && j == 25 && k == 26;
tools/testing/selftests/bpf/progs/fentry_many_args.c
33
__u64 g, __u64 h, __u64 i, __u64 j, __u64 k)
tools/testing/selftests/bpf/progs/fentry_many_args.c
37
i == 24 && j == 25 && k == 26;
tools/testing/selftests/bpf/progs/fexit_many_args.c
22
int g, unsigned int h, long i, __u64 j, unsigned long k,
tools/testing/selftests/bpf/progs/fexit_many_args.c
27
i == 24 && j == 25 && k == 26 && ret == 231;
tools/testing/selftests/bpf/progs/fexit_many_args.c
34
__u64 g, __u64 h, __u64 i, __u64 j, __u64 k, __u64 ret)
tools/testing/selftests/bpf/progs/fexit_many_args.c
38
i == 24 && j == 25 && k == 26 && ret == 231;
tools/testing/selftests/bpf/progs/for_each_hash_map_elem.c
33
__u32 k;
tools/testing/selftests/bpf/progs/for_each_hash_map_elem.c
37
k = *key;
tools/testing/selftests/bpf/progs/for_each_hash_map_elem.c
39
if (skb->len == 10000 && k == 10 && v == 10)
tools/testing/selftests/bpf/progs/iters.c
1636
int i, j, k, l, m, n, o;
tools/testing/selftests/bpf/progs/iters.c
1640
bpf_for(k, 0, 10)
tools/testing/selftests/bpf/progs/test_jhash.h
39
const unsigned char *k = key;
tools/testing/selftests/bpf/progs/test_jhash.h
44
a += *(volatile u32 *)(k);
tools/testing/selftests/bpf/progs/test_jhash.h
45
b += *(volatile u32 *)(k + 4);
tools/testing/selftests/bpf/progs/test_jhash.h
46
c += *(volatile u32 *)(k + 8);
tools/testing/selftests/bpf/progs/test_jhash.h
49
k += 12;
tools/testing/selftests/bpf/progs/test_jhash.h
52
case 12: c += (u32)k[11]<<24;
tools/testing/selftests/bpf/progs/test_jhash.h
53
case 11: c += (u32)k[10]<<16;
tools/testing/selftests/bpf/progs/test_jhash.h
54
case 10: c += (u32)k[9]<<8;
tools/testing/selftests/bpf/progs/test_jhash.h
55
case 9: c += k[8];
tools/testing/selftests/bpf/progs/test_jhash.h
56
case 8: b += (u32)k[7]<<24;
tools/testing/selftests/bpf/progs/test_jhash.h
57
case 7: b += (u32)k[6]<<16;
tools/testing/selftests/bpf/progs/test_jhash.h
58
case 6: b += (u32)k[5]<<8;
tools/testing/selftests/bpf/progs/test_jhash.h
59
case 5: b += k[4];
tools/testing/selftests/bpf/progs/test_jhash.h
60
case 4: a += (u32)k[3]<<24;
tools/testing/selftests/bpf/progs/test_jhash.h
61
case 3: a += (u32)k[2]<<16;
tools/testing/selftests/bpf/progs/test_jhash.h
62
case 2: a += (u32)k[1]<<8;
tools/testing/selftests/bpf/progs/test_jhash.h
63
case 1: a += k[0];
tools/testing/selftests/bpf/progs/test_jhash.h
73
static __always_inline u32 jhash2(const u32 *k, u32 length, u32 initval)
tools/testing/selftests/bpf/progs/test_jhash.h
82
a += k[0];
tools/testing/selftests/bpf/progs/test_jhash.h
83
b += k[1];
tools/testing/selftests/bpf/progs/test_jhash.h
84
c += k[2];
tools/testing/selftests/bpf/progs/test_jhash.h
87
k += 3;
tools/testing/selftests/bpf/progs/test_jhash.h
92
case 3: c += k[2];
tools/testing/selftests/bpf/progs/test_jhash.h
93
case 2: b += k[1];
tools/testing/selftests/bpf/progs/test_jhash.h
94
case 1: a += k[0];
tools/testing/selftests/bpf/progs/test_l4lb.c
60
const unsigned char *k = key;
tools/testing/selftests/bpf/progs/test_l4lb.c
65
a += *(u32 *)(k);
tools/testing/selftests/bpf/progs/test_l4lb.c
66
b += *(u32 *)(k + 4);
tools/testing/selftests/bpf/progs/test_l4lb.c
67
c += *(u32 *)(k + 8);
tools/testing/selftests/bpf/progs/test_l4lb.c
70
k += 12;
tools/testing/selftests/bpf/progs/test_l4lb.c
73
case 12: c += (u32)k[11]<<24;
tools/testing/selftests/bpf/progs/test_l4lb.c
74
case 11: c += (u32)k[10]<<16;
tools/testing/selftests/bpf/progs/test_l4lb.c
75
case 10: c += (u32)k[9]<<8;
tools/testing/selftests/bpf/progs/test_l4lb.c
76
case 9: c += k[8];
tools/testing/selftests/bpf/progs/test_l4lb.c
77
case 8: b += (u32)k[7]<<24;
tools/testing/selftests/bpf/progs/test_l4lb.c
78
case 7: b += (u32)k[6]<<16;
tools/testing/selftests/bpf/progs/test_l4lb.c
79
case 6: b += (u32)k[5]<<8;
tools/testing/selftests/bpf/progs/test_l4lb.c
80
case 5: b += k[4];
tools/testing/selftests/bpf/progs/test_l4lb.c
81
case 4: a += (u32)k[3]<<24;
tools/testing/selftests/bpf/progs/test_l4lb.c
82
case 3: a += (u32)k[2]<<16;
tools/testing/selftests/bpf/progs/test_l4lb.c
83
case 2: a += (u32)k[1]<<8;
tools/testing/selftests/bpf/progs/test_l4lb.c
84
case 1: a += k[0];
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
56
const unsigned char *k = key;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
61
a += *(u32 *)(k);
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
62
b += *(u32 *)(k + 4);
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
63
c += *(u32 *)(k + 8);
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
66
k += 12;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
69
case 12: c += (u32)k[11]<<24;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
70
case 11: c += (u32)k[10]<<16;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
71
case 10: c += (u32)k[9]<<8;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
72
case 9: c += k[8];
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
73
case 8: b += (u32)k[7]<<24;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
74
case 7: b += (u32)k[6]<<16;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
75
case 6: b += (u32)k[5]<<8;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
76
case 5: b += k[4];
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
77
case 4: a += (u32)k[3]<<24;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
78
case 3: a += (u32)k[2]<<16;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
79
case 2: a += (u32)k[1]<<8;
tools/testing/selftests/bpf/progs/test_l4lb_noinline.c
80
case 1: a += k[0];
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
58
const unsigned char *k = key;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
63
a += *(u32 *)(k);
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
64
b += *(u32 *)(k + 4);
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
65
c += *(u32 *)(k + 8);
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
68
k += 12;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
71
case 12: c += (u32)k[11]<<24;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
72
case 11: c += (u32)k[10]<<16;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
73
case 10: c += (u32)k[9]<<8;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
74
case 9: c += k[8];
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
75
case 8: b += (u32)k[7]<<24;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
76
case 7: b += (u32)k[6]<<16;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
77
case 6: b += (u32)k[5]<<8;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
78
case 5: b += k[4];
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
79
case 4: a += (u32)k[3]<<24;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
80
case 3: a += (u32)k[2]<<16;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
81
case 2: a += (u32)k[1]<<8;
tools/testing/selftests/bpf/progs/test_l4lb_noinline_dynptr.c
82
case 1: a += k[0];
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
57
const unsigned char *k = key;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
62
a += *(u32 *)(k);
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
63
b += *(u32 *)(k + 4);
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
64
c += *(u32 *)(k + 8);
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
67
k += 12;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
70
case 12: c += (u32)k[11]<<24;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
71
case 11: c += (u32)k[10]<<16;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
72
case 10: c += (u32)k[9]<<8;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
73
case 9: c += k[8];
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
74
case 8: b += (u32)k[7]<<24;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
75
case 7: b += (u32)k[6]<<16;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
76
case 6: b += (u32)k[5]<<8;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
77
case 5: b += k[4];
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
78
case 4: a += (u32)k[3]<<24;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
79
case 3: a += (u32)k[2]<<16;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
80
case 2: a += (u32)k[1]<<8;
tools/testing/selftests/bpf/progs/test_xdp_noinline.c
81
case 1: a += k[0];
tools/testing/selftests/bpf/progs/timer_lockup.c
33
static int timer_cb1(void *map, int *k, struct elem *v)
tools/testing/selftests/bpf/progs/timer_lockup.c
45
static int timer_cb2(void *map, int *k, struct elem *v)
tools/testing/selftests/bpf/sdt.h
204
# define _SDT_ARGTMPL(id) %k[id] /* gcc.gnu.org/PR80115 sourceware.org/PR24541 */
tools/testing/selftests/bpf/sdt.h
65
# define _SDT_DEPAREN_11(a,b,c,d,e,f,g,h,i,j,k) a b c d e f g h i j k
tools/testing/selftests/bpf/sdt.h
66
# define _SDT_DEPAREN_12(a,b,c,d,e,f,g,h,i,j,k,l) a b c d e f g h i j k l
tools/testing/selftests/bpf/test_kmods/bpf_testmod.c
442
unsigned long k)
tools/testing/selftests/bpf/test_kmods/bpf_testmod.c
444
return a + (long)b + c + d + (long)e + f + g + h + i + j + k;
tools/testing/selftests/bpf/test_sockmap.c
1608
int k = ktls;
tools/testing/selftests/bpf/test_sockmap.c
1653
ktls = k;
tools/testing/selftests/bpf/test_sockmap.c
426
unsigned char k = 0;
tools/testing/selftests/bpf/test_sockmap.c
435
for (i = 0; i < cnt; i++, k = 0) {
tools/testing/selftests/bpf/test_sockmap.c
436
for (j = 0; j < iov_length; j++, k++)
tools/testing/selftests/bpf/test_sockmap.c
437
fwrite(&k, sizeof(char), 1, file);
tools/testing/selftests/bpf/test_sockmap.c
485
unsigned char k = 0;
tools/testing/selftests/bpf/test_sockmap.c
507
d[j] = k++;
tools/testing/selftests/bpf/test_sockmap.c
554
unsigned char k = *k_p;
tools/testing/selftests/bpf/test_sockmap.c
591
k += verify_pop_len;
tools/testing/selftests/bpf/test_sockmap.c
594
k = 0;
tools/testing/selftests/bpf/test_sockmap.c
605
if (d[j] != k++) {
tools/testing/selftests/bpf/test_sockmap.c
608
i, j, d[j], k - 1, d[j+1], k);
tools/testing/selftests/bpf/test_sockmap.c
614
k = 0;
tools/testing/selftests/bpf/test_sockmap.c
622
*k_p = k;
tools/testing/selftests/bpf/test_sockmap.c
682
unsigned char k = 0;
tools/testing/selftests/bpf/test_sockmap.c
790
errno = msg_verify_data(&msg, recv, chunk_sz, &k, &bytes_cnt,
tools/testing/selftests/bpf/test_sockmap.c
800
&k,
tools/testing/selftests/bpf/test_verifier.c
193
int i = 0, j, k = 0;
tools/testing/selftests/bpf/test_verifier.c
221
if (++k < 5)
tools/testing/selftests/bpf/test_verifier.c
286
int i = 0, k = 0;
tools/testing/selftests/bpf/test_verifier.c
290
while (k++ < MAX_JMP_SEQ) {
tools/testing/selftests/bpf/test_verifier.c
296
-8 * (k % 64 + 1));
tools/testing/selftests/bpf/test_verifier.c
312
int i = 0, k = 0;
tools/testing/selftests/bpf/test_verifier.c
315
for (k = 0; k < FUNC_NEST; k++) {
tools/testing/selftests/bpf/test_verifier.c
321
k = 0;
tools/testing/selftests/bpf/test_verifier.c
322
while (k++ < MAX_JMP_SEQ) {
tools/testing/selftests/bpf/test_verifier.c
328
-8 * (k % (64 - 4 * FUNC_NEST) + 1));
tools/testing/selftests/bpf/usdt.h
458
#define __usdt_argref(id) %k[id] /* gcc.gnu.org/PR80115 sourceware.org/PR24541 */
tools/testing/selftests/bpf/usdt.h
542
#define __usdt_asm_ops12(a,b,c,d,e,f,g,h,i,j,k,x) __usdt_asm_ops11(a,b,c,d,e,f,g,h,i,j,k), __usdt_asm_op(12, x)
tools/testing/selftests/bpf/veristat.c
2114
int i, j, k, n, cnt, err = 0;
tools/testing/selftests/bpf/veristat.c
2146
for (k = 0; k < npresets; ++k) {
tools/testing/selftests/bpf/veristat.c
2149
if (strcmp(var_name, presets[k].atoms[0].name) != 0)
tools/testing/selftests/bpf/veristat.c
2152
if (presets[k].applied) {
tools/testing/selftests/bpf/veristat.c
2159
&tmp_sinfo, presets + k);
tools/testing/selftests/bpf/veristat.c
2163
err = set_global_var(obj, btf, map, &tmp_sinfo, presets + k);
tools/testing/selftests/bpf/veristat.c
2167
presets[k].applied = true;
tools/testing/selftests/bpf/veristat.c
2785
int i, j, k;
tools/testing/selftests/bpf/veristat.c
2796
for (k = 0; k < len; k++)
tools/testing/selftests/bpf/veristat.c
851
int i, j, k;
tools/testing/selftests/bpf/veristat.c
886
for (k = 0; k < ARRAY_SIZE(var_sfxs); k++) {
tools/testing/selftests/bpf/veristat.c
887
sfx_len = strlen(var_sfxs[k]);
tools/testing/selftests/bpf/veristat.c
891
if (strncmp(name + alias_len, var_sfxs[k], sfx_len) == 0) {
tools/testing/selftests/bpf/veristat.c
892
*var = (enum stat_variant)k;
tools/testing/selftests/dmabuf-heaps/dmabuf-heap.c
211
int i, j, k, ret;
tools/testing/selftests/dmabuf-heaps/dmabuf-heap.c
277
for (k = 0; k < i; k++)
tools/testing/selftests/dmabuf-heaps/dmabuf-heap.c
278
close(dmabuf_fd[k]);
tools/testing/selftests/drivers/dma-buf/udmabuf.c
112
int i = 0, j, k = 0, ret = 0;
tools/testing/selftests/drivers/dma-buf/udmabuf.c
117
for (j = 0; j < NUM_PAGES; j++, k++) {
tools/testing/selftests/drivers/dma-buf/udmabuf.c
119
char2 = *((char *)addr2 + (k * getpagesize()));
tools/testing/selftests/filesystems/binderfs/binderfs_test.c
404
int i, j, k, nthreads;
tools/testing/selftests/filesystems/binderfs/binderfs_test.c
460
for (k = 0; k < ARRAY_SIZE(fds); k++) {
tools/testing/selftests/filesystems/binderfs/binderfs_test.c
462
ret = pthread_create(&threads[i], &attr, binder_version_thread, INT_TO_PTR(fds[k]));
tools/testing/selftests/filesystems/binderfs/binderfs_test.c
481
for (k = 0; k < ARRAY_SIZE(fds); k++)
tools/testing/selftests/filesystems/binderfs/binderfs_test.c
482
close(fds[k]);
tools/testing/selftests/kvm/s390/keyop.c
169
unsigned char k;
tools/testing/selftests/kvm/s390/keyop.c
180
k = do_keyop(vcpu, KVM_S390_KEYOP_RRBE, i, 0xff);
tools/testing/selftests/kvm/s390/keyop.c
181
TEST_ASSERT((expected[i] & KEY_BITS_RC) == k,
tools/testing/selftests/kvm/s390/keyop.c
183
expected[i] & KEY_BITS_RC, k);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
591
uint32_t k;
tools/testing/selftests/kvm/x86/pmu_counters_test.c
664
for (k = 1; k < ARRAY_SIZE(unavailable_masks); k++)
tools/testing/selftests/kvm/x86/pmu_counters_test.c
665
test_arch_events(v, perf_caps[i], j, unavailable_masks[k]);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
676
for (k = 0; k <= (BIT(nr_fixed_counters) - 1); k++)
tools/testing/selftests/kvm/x86/pmu_counters_test.c
677
test_fixed_counters(v, perf_caps[i], j, k);
tools/testing/selftests/mm/mremap_test.c
34
#define SIZE_KB(k) ((size_t)k * 1024)
tools/testing/selftests/net/netfilter/audit_logread.c
110
while ((k = strtok(NULL, "="))) {
tools/testing/selftests/net/netfilter/audit_logread.c
114
if (!strcmp(k, "pid") ||
tools/testing/selftests/net/netfilter/audit_logread.c
115
!strcmp(k, "comm") ||
tools/testing/selftests/net/netfilter/audit_logread.c
116
!strcmp(k, "subj"))
tools/testing/selftests/net/netfilter/audit_logread.c
120
if (!strcmp(k, "table"))
tools/testing/selftests/net/netfilter/audit_logread.c
123
printf("%s%s=%s", sep, k, v);
tools/testing/selftests/net/netfilter/audit_logread.c
99
char *k, *v;
tools/testing/selftests/net/tcp_ao/lib/aolib.h
151
extern bool kernel_config_has(enum test_needs_kconfig k);
tools/testing/selftests/net/tcp_ao/lib/aolib.h
154
enum test_needs_kconfig k)
tools/testing/selftests/net/tcp_ao/lib/aolib.h
156
if (kernel_config_has(k))
tools/testing/selftests/net/tcp_ao/lib/aolib.h
158
test_skip("%s: %s", tst_name, tests_skip_reason[k]);
tools/testing/selftests/net/tcp_ao/lib/kconfig.c
145
bool kernel_config_has(enum test_needs_kconfig k)
tools/testing/selftests/net/tcp_ao/lib/kconfig.c
150
if (kconfig[k]._error == KCONFIG_UNKNOWN) {
tools/testing/selftests/net/tcp_ao/lib/kconfig.c
151
if (kconfig[k].check_kconfig(&kconfig[k]._error))
tools/testing/selftests/net/tcp_ao/lib/kconfig.c
152
test_error("Failed to initialize kconfig %u", k);
tools/testing/selftests/net/tcp_ao/lib/kconfig.c
154
ret = kconfig[k]._error == 0;
tools/testing/selftests/powerpc/nx-gzip/gunz_test.c
372
int k = 0;
tools/testing/selftests/powerpc/nx-gzip/gunz_test.c
376
if (c == EOF || k >= FNAME_MAX)
tools/testing/selftests/powerpc/nx-gzip/gunz_test.c
378
gzfname[k++] = c;
tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c
235
volatile int *k;
tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c
258
k = &readint;
tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c
261
k = &(readintalign[i % (DAWR_LENGTH_MAX/sizeof(int))]);
tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c
263
j = *k;
tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c
264
*k = j;
tools/testing/selftests/powerpc/tm/tm-trap.c
249
uint16_t k = 1;
tools/testing/selftests/powerpc/tm/tm-trap.c
292
le = (int) *(uint8_t *)&k;
tools/testing/selftests/ptrace/vmaccess.c
48
int s, k, pid = fork();
tools/testing/selftests/ptrace/vmaccess.c
59
k = ptrace(PTRACE_ATTACH, pid, 0L, 0L);
tools/testing/selftests/ptrace/vmaccess.c
61
ASSERT_EQ(k, -1);
tools/testing/selftests/ptrace/vmaccess.c
62
k = waitpid(-1, &s, WNOHANG);
tools/testing/selftests/ptrace/vmaccess.c
63
ASSERT_NE(k, -1);
tools/testing/selftests/ptrace/vmaccess.c
64
ASSERT_NE(k, 0);
tools/testing/selftests/ptrace/vmaccess.c
65
ASSERT_NE(k, pid);
tools/testing/selftests/ptrace/vmaccess.c
69
k = ptrace(PTRACE_ATTACH, pid, 0L, 0L);
tools/testing/selftests/ptrace/vmaccess.c
70
ASSERT_EQ(k, 0);
tools/testing/selftests/ptrace/vmaccess.c
71
k = waitpid(-1, &s, 0);
tools/testing/selftests/ptrace/vmaccess.c
72
ASSERT_EQ(k, pid);
tools/testing/selftests/ptrace/vmaccess.c
75
k = ptrace(PTRACE_DETACH, pid, 0L, 0L);
tools/testing/selftests/ptrace/vmaccess.c
76
ASSERT_EQ(k, 0);
tools/testing/selftests/ptrace/vmaccess.c
77
k = waitpid(-1, &s, 0);
tools/testing/selftests/ptrace/vmaccess.c
78
ASSERT_EQ(k, pid);
tools/testing/selftests/ptrace/vmaccess.c
81
k = waitpid(-1, NULL, 0);
tools/testing/selftests/ptrace/vmaccess.c
82
ASSERT_EQ(k, -1);
tools/testing/vma/tests/merge.c
1057
int i, j, k;
tools/testing/vma/tests/merge.c
1062
for (k = 0; k < 2; k++)
tools/testing/vma/tests/merge.c
1063
ASSERT_TRUE(__test_merge_existing(i, j, k));
tools/testing/vma/tests/merge.c
458
int i, j, k, l;
tools/testing/vma/tests/merge.c
463
for (k = 0; k < 2; k++)
tools/testing/vma/tests/merge.c
465
ASSERT_TRUE(__test_merge_new(i, j, k, l));
tools/thermal/tmon/sysfs.c
285
int i, j, n, k = 0;
tools/thermal/tmon/sysfs.c
304
sysfs_get_string(tz_name, "type", ptdata.tzi[k].type);
tools/thermal/tmon/sysfs.c
305
ptdata.tzi[k].instance = i;
tools/thermal/tmon/sysfs.c
308
ptdata.tzi[k].nr_cdev = 0;
tools/thermal/tmon/sysfs.c
309
ptdata.tzi[k].nr_trip_pts = 0;
tools/thermal/tmon/sysfs.c
314
&ptdata.tzi[k], k))
tools/thermal/tmon/sysfs.c
322
&ptdata.tzi[k], i, j))
tools/thermal/tmon/sysfs.c
331
ptdata.tzi[k].nr_cdev);
tools/thermal/tmon/sysfs.c
332
k++;
tools/thermal/tmon/sysfs.c
343
int i, n, k = 0;
tools/thermal/tmon/sysfs.c
366
sysfs_get_string(cdev_name, "type", ptdata.cdi[k].type);
tools/thermal/tmon/sysfs.c
367
ptdata.cdi[k].instance = i;
tools/thermal/tmon/sysfs.c
368
if (strstr(ptdata.cdi[k].type, ctrl_cdev)) {
tools/thermal/tmon/sysfs.c
369
ptdata.cdi[k].flag |= CDEV_FLAG_IN_CONTROL;
tools/thermal/tmon/sysfs.c
377
k++;
tools/thermal/tmon/tui.c
240
int k = 0; /* per zone trip point id that
tools/thermal/tmon/tui.c
251
k++;
tools/thermal/tmon/tui.c
258
k - 1, "*");