bin/csh/char.h

55

#define cmap(c, bits) \

bin/csh/char.h

56

(((c) & QUOTE) ? 0 : (_cmap[(unsigned char)(c)] & (bits)))

bin/mt/mt.c

292

printreg(char *s, u_int v, char *bits)

bin/mt/mt.c

297

if (bits && *bits == 8)

bin/mt/mt.c

301

if (!bits)

bin/mt/mt.c

303

bits++;

bin/mt/mt.c

304

if (v && *bits) {

bin/mt/mt.c

306

while ((i = *bits++)) {

bin/mt/mt.c

311

for (; (c = *bits) > 32; bits++)

bin/mt/mt.c

314

for (; *bits > 32; bits++)

bin/ps/print.c

339

for (i = 0; pledgenames[i].bits != 0; i++) {

bin/ps/print.c

340

if (pledgenames[i].bits & kp->p_pledge) {

games/hack/hack.mkobj.c

158

(objects[otmp->otyp].bits & NODIR) ? 11 : 4);

games/hack/hack.mkobj.c

161

if(objects[otmp->otyp].bits & SPEC) {

games/hack/hack.objnam.c

365

if(obj->known && (objects[obj->otyp].bits & SPEC)) {

games/hack/hack.zap.c

201

if(!(objects[obj->otyp].bits & NODIR) && !getdir(1))

games/hack/hack.zap.c

204

if(objects[obj->otyp].bits & IMMEDIATE) {

include/sndio.h

136

#define SIO_BPS(bits) (((bits) <= 8) ? 1 : (((bits) <= 16) ? 2 : 4))

include/sndio.h

45

unsigned int bits; /* bits per sample */

include/sndio.h

73

unsigned int bits;

lib/libc/gdtoa/gdtoa.c

116

(fpi, be, bits, kindp, mode, ndigits, decpt, rve)

lib/libc/gdtoa/gdtoa.c

117

FPI *fpi; int be; ULong *bits;

lib/libc/gdtoa/gdtoa.c

120

(FPI *fpi, int be, ULong *bits, int *kindp, int mode, int ndigits, int *decpt, char **rve)

lib/libc/gdtoa/gdtoa.c

190

b = bitstob(bits, nbits = fpi->nbits, &bbits);

lib/libc/gdtoa/gdtoa.c

36

bitstob(bits, nbits, bbits) ULong *bits; int nbits; int *bbits;

lib/libc/gdtoa/gdtoa.c

38

bitstob(ULong *bits, int nbits, int *bbits)

lib/libc/gdtoa/gdtoa.c

58

be = bits + ((nbits - 1) >> kshift);

lib/libc/gdtoa/gdtoa.c

61

*x++ = *bits & ALL_ON;

lib/libc/gdtoa/gdtoa.c

63

*x++ = (*bits >> 16) & ALL_ON;

lib/libc/gdtoa/gdtoa.c

65

} while(++bits <= be);

lib/libc/gdtoa/gdtoa.c

675

if (j1 == 0 && !mode && !(bits[0] & 1) && !rdir) {

lib/libc/gdtoa/gdtoa.c

692

&& !(bits[0] & 1)

lib/libc/gdtoa/gdtoa.h

109

extern char* __gdtoa ANSI((FPI *fpi, int be, ULong *bits, int *kindp,

lib/libc/gdtoa/ldtoa.c

64

uint32_t bits[(LDBL_MANT_DIG + 31) / 32];

lib/libc/gdtoa/ldtoa.c

65

void *vbits = bits;

lib/libc/gdtoa/ldtoa.c

76

EXT_TO_ARRAY32(p, bits);

lib/libc/gdtoa/ldtoa.c

82

bits[LDBL_MANT_DIG / 32] |= 1 << ((LDBL_MANT_DIG - 1) % 32);

lib/libc/gdtoa/misc.c

721

(dd, e, bits) double dd; int *e, *bits;

lib/libc/gdtoa/misc.c

723

(double dd, int *e, int *bits)

lib/libc/gdtoa/misc.c

837

*bits = 4*P + 8 - k - hi0bits(word0(&d) & Frac_mask);

lib/libc/gdtoa/misc.c

840

*bits = P - k;

lib/libc/gdtoa/misc.c

847

*bits = 32*i - hi0bits(x[i-1]);

lib/libc/gdtoa/misc.c

849

*bits = (i+2)*16 - hi0bits(x[i]);

lib/libc/gdtoa/strtod.c

168

ULong bits[2];

lib/libc/gdtoa/strtod.c

189

copybits(bits, fpi.nbits, bb);

lib/libc/gdtoa/strtod.c

192

ULtod(((U*)&rv)->L, bits, exp, i);

lib/libc/gdtoa/strtod.c

294

ULong bits[2];

lib/libc/gdtoa/strtod.c

315

&& hexnan(&s, &fpinan, bits)

lib/libc/gdtoa/strtod.c

317

word0(&rv) = 0x7ff00000 | bits[1];

lib/libc/gdtoa/strtod.c

318

word1(&rv) = bits[0];

lib/libc/gdtoa/strtodg.c

1106

b = bits;

lib/libc/gdtoa/strtodg.c

1147

copybits(bits, nbits, rvb);

lib/libc/gdtoa/strtodg.c

178

(d, fpi, exp, bits, exact, rd, irv)

lib/libc/gdtoa/strtodg.c

179

U *d; FPI *fpi; Long *exp; ULong *bits; int exact, rd, *irv;

lib/libc/gdtoa/strtodg.c

181

(U *d, FPI *fpi, Long *exp, ULong *bits, int exact, int rd, int *irv)

lib/libc/gdtoa/strtodg.c

305

copybits(bits, nb, b);

lib/libc/gdtoa/strtodg.c

339

(s00, se, fpi, exp, bits)

lib/libc/gdtoa/strtodg.c

340

CONST char *s00; char **se; FPI *fpi; Long *exp; ULong *bits;

lib/libc/gdtoa/strtodg.c

342

(CONST char *s00, char **se, FPI *fpi, Long *exp, ULong *bits)

lib/libc/gdtoa/strtodg.c

537

irv = hexnan(&s, fpi, bits);

lib/libc/gdtoa/strtodg.c

577

if (rvOK(&rv, fpi, exp, bits, 1, rd, &irv)) {

lib/libc/gdtoa/strtodg.c

590

if (rvOK(&rv, fpi, exp, bits, i, rd, &irv)) {

lib/libc/gdtoa/strtodg.c

623

if (rvOK(&rv, fpi, exp, bits, 0, rd, &irv)) {

lib/libc/gdtoa/strtodg.c

634

if (rvOK(&rv, fpi, exp, bits, 0, rd, &irv)) {

lib/libc/gdtoa/strtof.c

42

ULong bits[1];

lib/libc/gdtoa/strtof.c

52

k = strtodg(s, sp, fpi, &exp, bits);

lib/libc/gdtoa/strtof.c

61

u.L[0] = (bits[0] & 0x7fffff) | ((exp + 0x7f + 23) << 23);

lib/libc/gdtoa/strtof.c

65

u.L[0] = bits[0];

lib/libc/gdtoa/strtorQ.c

107

ULong bits[4];

lib/libc/gdtoa/strtorQ.c

117

k = strtodg(s, sp, fpi, &exp, bits);

lib/libc/gdtoa/strtorQ.c

118

ULtoQ((ULong*)L, bits, exp, k);

lib/libc/gdtoa/strtorQ.c

54

ULtoQ(L, bits, exp, k) ULong *L; ULong *bits; Long exp; int k;

lib/libc/gdtoa/strtorQ.c

56

ULtoQ(ULong *L, ULong *bits, Long exp, int k)

lib/libc/gdtoa/strtorQ.c

67

L[_3] = bits[0];

lib/libc/gdtoa/strtorQ.c

68

L[_2] = bits[1];

lib/libc/gdtoa/strtorQ.c

69

L[_1] = bits[2];

lib/libc/gdtoa/strtorQ.c

70

L[_0] = (bits[3] & ~0x10000) | ((exp + 0x3fff + 112) << 16);

lib/libc/gdtoa/strtorQ.c

74

L[_3] = bits[0];

lib/libc/gdtoa/strtorQ.c

75

L[_2] = bits[1];

lib/libc/gdtoa/strtorQ.c

76

L[_1] = bits[2];

lib/libc/gdtoa/strtorQ.c

77

L[_0] = bits[3];

lib/libc/gdtoa/strtord.c

36

ULtod(L, bits, exp, k) ULong *L; ULong *bits; Long exp; int k;

lib/libc/gdtoa/strtord.c

38

ULtod(ULong *L, ULong *bits, Long exp, int k)

lib/libc/gdtoa/strtord.c

48

L[_1] = bits[0];

lib/libc/gdtoa/strtord.c

49

L[_0] = bits[1];

lib/libc/gdtoa/strtord.c

54

L[_1] = bits[0];

lib/libc/gdtoa/strtord.c

55

L[_0] = (bits[1] & ~0x100000) | ((exp + 0x3ff + 52) << 20);

lib/libc/gdtoa/strtord.c

83

ULong bits[2];

lib/libc/gdtoa/strtord.c

93

k = strtodg(s, sp, fpi, &exp, bits);

lib/libc/gdtoa/strtord.c

94

ULtod((ULong*)d, bits, exp, k);

lib/libc/gdtoa/strtorx.c

110

ULong bits[2];

lib/libc/gdtoa/strtorx.c

120

k = strtodg(s, sp, fpi, &exp, bits);

lib/libc/gdtoa/strtorx.c

121

ULtox((UShort*)L, bits, exp, k);

lib/libc/gdtoa/strtorx.c

56

ULtox(L, bits, exp, k) UShort *L; ULong *bits; Long exp; int k;

lib/libc/gdtoa/strtorx.c

58

ULtox(UShort *L, ULong *bits, Long exp, int k)

lib/libc/gdtoa/strtorx.c

75

L[_4] = (UShort)bits[0];

lib/libc/gdtoa/strtorx.c

76

L[_3] = (UShort)(bits[0] >> 16);

lib/libc/gdtoa/strtorx.c

77

L[_2] = (UShort)bits[1];

lib/libc/gdtoa/strtorx.c

78

L[_1] = (UShort)(bits[1] >> 16);

lib/libc/gen/setmode.c

106

newmode &= ~((clrval<<6) & set->bits);

lib/libc/gen/setmode.c

108

newmode &= ~((clrval<<3) & set->bits);

lib/libc/gen/setmode.c

110

newmode &= ~(clrval & set->bits);

lib/libc/gen/setmode.c

114

newmode |= (value<<6) & set->bits;

lib/libc/gen/setmode.c

116

newmode |= (value<<3) & set->bits;

lib/libc/gen/setmode.c

118

newmode |= value & set->bits;

lib/libc/gen/setmode.c

123

newmode |= set->bits;

lib/libc/gen/setmode.c

127

newmode &= ~set->bits;

lib/libc/gen/setmode.c

132

newmode |= set->bits;

lib/libc/gen/setmode.c

344

set->bits = who ? who : STANDARD_BITS;

lib/libc/gen/setmode.c

353

set->bits = (who ? who : mask) & oparg;

lib/libc/gen/setmode.c

364

set->bits = (mode_t)~0;

lib/libc/gen/setmode.c

367

set->bits = mask;

lib/libc/gen/setmode.c

387

set->cmd, set->bits, set->cmd2 ? " cmd2:" : "",

lib/libc/gen/setmode.c

418

clrbits |= nset->bits;

lib/libc/gen/setmode.c

419

setbits &= ~nset->bits;

lib/libc/gen/setmode.c

420

Xbits &= ~nset->bits;

lib/libc/gen/setmode.c

422

setbits |= nset->bits;

lib/libc/gen/setmode.c

423

clrbits &= ~nset->bits;

lib/libc/gen/setmode.c

424

Xbits &= ~nset->bits;

lib/libc/gen/setmode.c

426

Xbits |= nset->bits & ~setbits;

lib/libc/gen/setmode.c

433

set->bits = clrbits;

lib/libc/gen/setmode.c

439

set->bits = setbits;

lib/libc/gen/setmode.c

445

set->bits = Xbits;

lib/libc/gen/setmode.c

55

mode_t bits;

lib/libc/hash/sha1.c

21

#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))

lib/libc/net/inet_net_ntop.c

112

b = bits % 8;

lib/libc/net/inet_net_ntop.c

128

advance = snprintf(dst, ep - dst, "/%u", bits);

lib/libc/net/inet_net_ntop.c

140

inet_net_ntop_ipv6(const u_char *src, int bits, char *dst, size_t size)

lib/libc/net/inet_net_ntop.c

145

if (bits < 0 || bits > 128) {

lib/libc/net/inet_net_ntop.c

153

ret = snprintf(dst, size, "%s/%d", buf, bits);

lib/libc/net/inet_net_ntop.c

45

inet_net_ntop(int af, const void *src, int bits, char *dst, size_t size)

lib/libc/net/inet_net_ntop.c

49

return (inet_net_ntop_ipv4(src, bits, dst, size));

lib/libc/net/inet_net_ntop.c

51

return (inet_net_ntop_ipv6(src, bits, dst, size));

lib/libc/net/inet_net_ntop.c

72

inet_net_ntop_ipv4(const u_char *src, int bits, char *dst, size_t size)

lib/libc/net/inet_net_ntop.c

84

if (bits < 0 || bits > 32) {

lib/libc/net/inet_net_ntop.c

88

if (bits == 0) {

lib/libc/net/inet_net_ntop.c

96

for (b = bits / 8; b > 0; b--) {

lib/libc/net/inet_net_pton.c

145

bits = -1;

lib/libc/net/inet_net_pton.c

150

bits = 0;

lib/libc/net/inet_net_pton.c

154

bits *= 10;

lib/libc/net/inet_net_pton.c

155

bits += n;

lib/libc/net/inet_net_pton.c

156

if (bits > 32)

lib/libc/net/inet_net_pton.c

172

if (bits == -1) {

lib/libc/net/inet_net_pton.c

174

bits = 32;

lib/libc/net/inet_net_pton.c

176

bits = 4;

lib/libc/net/inet_net_pton.c

178

bits = 24;

lib/libc/net/inet_net_pton.c

180

bits = 16;

lib/libc/net/inet_net_pton.c

182

bits = 8;

lib/libc/net/inet_net_pton.c

184

if (bits < ((dst - odst) * 8))

lib/libc/net/inet_net_pton.c

185

bits = (dst - odst) * 8;

lib/libc/net/inet_net_pton.c

188

while (bits > ((dst - odst) * 8)) {

lib/libc/net/inet_net_pton.c

193

return (bits);

lib/libc/net/inet_net_pton.c

210

int bits;

lib/libc/net/inet_net_pton.c

230

bits = 128;

lib/libc/net/inet_net_pton.c

232

bits = strtonum(sep, 0, 128, &errstr);

lib/libc/net/inet_net_pton.c

239

bytes = (bits + 7) / 8;

lib/libc/net/inet_net_pton.c

245

return (bits);

lib/libc/net/inet_net_pton.c

85

int n, ch, tmp, dirty, bits;

lib/libc/stdlib/malloc.c

1184

lp = &bp->bits[i];

lib/libc/stdlib/malloc.c

1197

lp = &bp->bits[i];

lib/libc/stdlib/malloc.c

1210

bp->bits[bp->offset + k] = size;

lib/libc/stdlib/malloc.c

1263

validate_canary(d, ptr, info->bits[info->offset + chunknum],

lib/libc/stdlib/malloc.c

1283

info->bits[chunknum / MALLOC_BITS] |= 1U << (chunknum % MALLOC_BITS);

lib/libc/stdlib/malloc.c

1609

if (info->bits[info->offset + chunknum] < argsz)

lib/libc/stdlib/malloc.c

1612

info->bits[info->offset + chunknum],

lib/libc/stdlib/malloc.c

1911

info->bits[info->offset + chunknum] = newsz;

lib/libc/stdlib/malloc.c

2041

if (info->bits[info->offset + chunknum] != oldsize)

lib/libc/stdlib/malloc.c

2043

info->bits[info->offset + chunknum],

lib/libc/stdlib/malloc.c

227

u_short bits[CHUNK_INFO_TAIL]; /* which chunks are free */

lib/libc/stdlib/malloc.c

230

#define CHUNK_FREE(i, n) ((i)->bits[(n) / MALLOC_BITS] & \

lib/libc/stdlib/malloc.c

990

memset(p->bits, 0xff, sizeof(p->bits[0]) * (i / MALLOC_BITS));

lib/libc/stdlib/malloc.c

991

p->bits[i / MALLOC_BITS] = (2U << (i % MALLOC_BITS)) - 1;

lib/libcrypto/aes/aes.c

104

AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key)

lib/libcrypto/aes/aes.c

111

if ((key->rounds = aes_rounds_for_key_length(bits)) <= 0)

lib/libcrypto/aes/aes.c

114

return aes_set_decrypt_key_internal(userKey, bits, key);

lib/libcrypto/aes/aes.c

66

int aes_set_encrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes.c

68

int aes_set_decrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes.c

76

aes_rounds_for_key_length(int bits)

lib/libcrypto/aes/aes.c

78

if (bits == 128)

lib/libcrypto/aes/aes.c

80

if (bits == 192)

lib/libcrypto/aes/aes.c

82

if (bits == 256)

lib/libcrypto/aes/aes.c

89

AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key)

lib/libcrypto/aes/aes.c

96

if ((key->rounds = aes_rounds_for_key_length(bits)) <= 0)

lib/libcrypto/aes/aes.c

99

return aes_set_encrypt_key_internal(userKey, bits, key);

lib/libcrypto/aes/aes.h

78

int AES_set_encrypt_key(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes.h

80

int AES_set_decrypt_key(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_amd64.c

23

int aes_set_encrypt_key_generic(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_amd64.c

25

int aes_set_decrypt_key_generic(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_amd64.c

47

int aesni_set_encrypt_key(const unsigned char *userKey, int bits,

lib/libcrypto/aes/aes_amd64.c

49

int aesni_set_decrypt_key(const unsigned char *userKey, int bits,

lib/libcrypto/aes/aes_amd64.c

83

aes_set_encrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_amd64.c

87

return aesni_set_encrypt_key(userKey, bits, key);

lib/libcrypto/aes/aes_amd64.c

89

return aes_set_encrypt_key_generic(userKey, bits, key);

lib/libcrypto/aes/aes_amd64.c

93

aes_set_decrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_amd64.c

97

return aesni_set_decrypt_key(userKey, bits, key);

lib/libcrypto/aes/aes_amd64.c

99

return aes_set_decrypt_key_generic(userKey, bits, key);

lib/libcrypto/aes/aes_core.c

641

aes_set_encrypt_key_generic(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_core.c

654

if (bits == 128) {

lib/libcrypto/aes/aes_core.c

674

if (bits == 192) {

lib/libcrypto/aes/aes_core.c

696

if (bits == 256) {

lib/libcrypto/aes/aes_core.c

730

aes_set_encrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_core.c

733

return aes_set_encrypt_key_generic(userKey, bits, key);

lib/libcrypto/aes/aes_core.c

742

aes_set_decrypt_key_generic(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_core.c

750

if ((ret = aes_set_encrypt_key_generic(userKey, bits, key)) < 0)

lib/libcrypto/aes/aes_core.c

800

aes_set_decrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_core.c

803

return aes_set_decrypt_key_generic(userKey, bits, key);

lib/libcrypto/aes/aes_i386.c

23

int aes_set_encrypt_key_generic(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_i386.c

25

int aes_set_decrypt_key_generic(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_i386.c

47

int aesni_set_encrypt_key(const unsigned char *userKey, int bits,

lib/libcrypto/aes/aes_i386.c

49

int aesni_set_decrypt_key(const unsigned char *userKey, int bits,

lib/libcrypto/aes/aes_i386.c

83

aes_set_encrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_i386.c

87

return aesni_set_encrypt_key(userKey, bits, key);

lib/libcrypto/aes/aes_i386.c

89

return aes_set_encrypt_key_generic(userKey, bits, key);

lib/libcrypto/aes/aes_i386.c

93

aes_set_decrypt_key_internal(const unsigned char *userKey, const int bits,

lib/libcrypto/aes/aes_i386.c

97

return aesni_set_decrypt_key(userKey, bits, key);

lib/libcrypto/aes/aes_i386.c

99

return aes_set_decrypt_key_generic(userKey, bits, key);

lib/libcrypto/asn1/a_bitstr.c

216

int ret, j, bits, len;

lib/libcrypto/asn1/a_bitstr.c

225

bits = (int)a->flags & 0x07;

lib/libcrypto/asn1/a_bitstr.c

236

bits = 0;

lib/libcrypto/asn1/a_bitstr.c

238

bits = 1;

lib/libcrypto/asn1/a_bitstr.c

240

bits = 2;

lib/libcrypto/asn1/a_bitstr.c

242

bits = 3;

lib/libcrypto/asn1/a_bitstr.c

244

bits = 4;

lib/libcrypto/asn1/a_bitstr.c

246

bits = 5;

lib/libcrypto/asn1/a_bitstr.c

248

bits = 6;

lib/libcrypto/asn1/a_bitstr.c

250

bits = 7;

lib/libcrypto/asn1/a_bitstr.c

252

bits = 0;

lib/libcrypto/asn1/a_bitstr.c

255

bits = 0;

lib/libcrypto/asn1/a_bitstr.c

267

*(p++) = (unsigned char)bits;

lib/libcrypto/asn1/a_bitstr.c

272

p[-1] &= 0xff << bits;

lib/libcrypto/bn/bn.h

286

int BN_rand(BIGNUM *rnd, int bits, int top, int bottom);

lib/libcrypto/bn/bn.h

287

int BN_pseudo_rand(BIGNUM *rnd, int bits, int top, int bottom);

lib/libcrypto/bn/bn.h

378

int BN_generate_prime_ex(BIGNUM *ret, int bits, int safe, const BIGNUM *add,

lib/libcrypto/bn/bn_convert.c

691

int bits, bytes;

lib/libcrypto/bn/bn_convert.c

695

bits = BN_num_bits(bn);

lib/libcrypto/bn/bn_convert.c

696

bytes = (bits + 7) / 8;

lib/libcrypto/bn/bn_convert.c

697

extend = (bits != 0) && (bits % 8 == 0);

lib/libcrypto/bn/bn_exp.c

1001

window = BN_window_bits_for_exponent_size(bits);

lib/libcrypto/bn/bn_exp.c

1018

wstart = bits - 1; /* The top bit of the window */

lib/libcrypto/bn/bn_exp.c

1160

int i, j, bits, b, bits1, bits2, ret = 0, wpos1, wpos2, window1, window2, wvalue1, wvalue2;

lib/libcrypto/bn/bn_exp.c

1180

bits = (bits1 > bits2) ? bits1 : bits2;

lib/libcrypto/bn/bn_exp.c

1264

for (b = bits - 1; b >= 0; b--) {

lib/libcrypto/bn/bn_exp.c

182

int i, j, bits, wstart, wend, window, wvalue;

lib/libcrypto/bn/bn_exp.c

200

bits = BN_num_bits(p);

lib/libcrypto/bn/bn_exp.c

201

if (bits == 0) {

lib/libcrypto/bn/bn_exp.c

228

window = BN_window_bits_for_exponent_size(bits);

lib/libcrypto/bn/bn_exp.c

244

wstart = bits - 1; /* The top bit of the window */

lib/libcrypto/bn/bn_exp.c

397

int i, bits, ret = 0, window, wvalue;

lib/libcrypto/bn/bn_exp.c

414

bits = BN_num_bits(p);

lib/libcrypto/bn/bn_exp.c

415

if (bits == 0) {

lib/libcrypto/bn/bn_exp.c

433

window = BN_window_bits_for_ctime_exponent_size(bits);

lib/libcrypto/bn/bn_exp.c

435

if (window == 6 && bits <= 1024)

lib/libcrypto/bn/bn_exp.c

541

bits--;

lib/libcrypto/bn/bn_exp.c

542

for (wvalue = 0, i = bits % 5; i >= 0; i--, bits--)

lib/libcrypto/bn/bn_exp.c

543

wvalue = (wvalue << 1) + BN_is_bit_set(p, bits);

lib/libcrypto/bn/bn_exp.c

549

while (bits >= 0) {

lib/libcrypto/bn/bn_exp.c

550

for (wvalue = 0, i = 0; i < 5; i++, bits--)

lib/libcrypto/bn/bn_exp.c

551

wvalue = (wvalue << 1) + BN_is_bit_set(p, bits);

lib/libcrypto/bn/bn_exp.c

595

bits--;

lib/libcrypto/bn/bn_exp.c

596

for (wvalue = 0, i = bits % window; i >= 0; i--, bits--)

lib/libcrypto/bn/bn_exp.c

597

wvalue = (wvalue << 1) + BN_is_bit_set(p, bits);

lib/libcrypto/bn/bn_exp.c

605

while (bits >= 0) {

lib/libcrypto/bn/bn_exp.c

609

for (i = 0; i < window; i++, bits--) {

lib/libcrypto/bn/bn_exp.c

613

wvalue = (wvalue << 1) + BN_is_bit_set(p, bits);

lib/libcrypto/bn/bn_exp.c

647

int i, j, bits, ret = 0, wstart, wend, window, wvalue;

lib/libcrypto/bn/bn_exp.c

665

bits = BN_num_bits(p);

lib/libcrypto/bn/bn_exp.c

666

if (bits == 0) {

lib/libcrypto/bn/bn_exp.c

700

window = BN_window_bits_for_exponent_size(bits);

lib/libcrypto/bn/bn_exp.c

717

wstart = bits - 1; /* The top bit of the window */

lib/libcrypto/bn/bn_exp.c

811

int b, bits, ret = 0;

lib/libcrypto/bn/bn_exp.c

846

bits = BN_num_bits(p);

lib/libcrypto/bn/bn_exp.c

847

if (bits == 0) {

lib/libcrypto/bn/bn_exp.c

881

for (b = bits - 2; b >= 0; b--) {

lib/libcrypto/bn/bn_exp.c

956

int i, j, bits, wstart, wend, window, wvalue;

lib/libcrypto/bn/bn_exp.c

970

bits = BN_num_bits(p);

lib/libcrypto/bn/bn_exp.c

971

if (bits == 0) {

lib/libcrypto/bn/bn_lib.c

221

bn_expand_bits(BIGNUM *bn, size_t bits)

lib/libcrypto/bn/bn_lib.c

225

if (bits > (INT_MAX - BN_BITS2 + 1))

lib/libcrypto/bn/bn_lib.c

228

words = (bits + BN_BITS2 - 1) / BN_BITS2;

lib/libcrypto/bn/bn_lib.c

635

BN_ULONG bits = 0;

lib/libcrypto/bn/bn_lib.c

639

bits |= bn->d[i];

lib/libcrypto/bn/bn_lib.c

641

return bits == 0;

lib/libcrypto/bn/bn_lib.c

679

int secbits, bits;

lib/libcrypto/bn/bn_lib.c

697

bits = N / 2;

lib/libcrypto/bn/bn_lib.c

698

if (bits < 80)

lib/libcrypto/bn/bn_lib.c

701

return bits >= secbits ? secbits : bits;

lib/libcrypto/bn/bn_local.h

271

int bn_expand_bits(BIGNUM *a, size_t bits);

lib/libcrypto/bn/bn_local.h

281

int BN_bntest_rand(BIGNUM *rnd, int bits, int top, int bottom);

lib/libcrypto/bn/bn_prime.c

125

static int probable_prime(BIGNUM *rnd, int bits);

lib/libcrypto/bn/bn_prime.c

126

static int probable_prime_dh(BIGNUM *rnd, int bits,

lib/libcrypto/bn/bn_prime.c

128

static int probable_prime_dh_safe(BIGNUM *rnd, int bits,

lib/libcrypto/bn/bn_prime.c

156

BN_generate_prime_ex(BIGNUM *ret, int bits, int safe, const BIGNUM *add,

lib/libcrypto/bn/bn_prime.c

165

if (bits < 2 || (bits == 2 && safe)) {

lib/libcrypto/bn/bn_prime.c

183

if (!probable_prime(ret, bits))

lib/libcrypto/bn/bn_prime.c

187

if (!probable_prime_dh_safe(ret, bits, add, rem, ctx))

lib/libcrypto/bn/bn_prime.c

190

if (!probable_prime_dh(ret, bits, add, rem, ctx))

lib/libcrypto/bn/bn_prime.c

275

probable_prime(BIGNUM *rnd, int bits)

lib/libcrypto/bn/bn_prime.c

282

if (!BN_rand(rnd, bits, 1, 1))

lib/libcrypto/bn/bn_prime.c

310

probable_prime_dh(BIGNUM *rnd, int bits, const BIGNUM *add, const BIGNUM *rem,

lib/libcrypto/bn/bn_prime.c

320

if (!BN_rand(rnd, bits, 0, 1))

lib/libcrypto/bn/bn_prime.c

359

probable_prime_dh_safe(BIGNUM *p, int bits, const BIGNUM *padd,

lib/libcrypto/bn/bn_prime.c

365

bits--;

lib/libcrypto/bn/bn_prime.c

377

if (!BN_rand(q, bits, 0, 1))

lib/libcrypto/bn/bn_primitives.c

29

BN_ULONG bits, mask, shift;

lib/libcrypto/bn/bn_primitives.c

31

bits = shift = BN_BITS2;

lib/libcrypto/bn/bn_primitives.c

35

bits += (shift & mask) - (shift & ~mask);

lib/libcrypto/bn/bn_primitives.c

36

mask = bn_ct_ne_zero_mask(w >> bits);

lib/libcrypto/bn/bn_primitives.c

38

bits += 1 & mask;

lib/libcrypto/bn/bn_primitives.c

40

bits -= bn_ct_eq_zero(w);

lib/libcrypto/bn/bn_primitives.c

42

return BN_BITS2 - bits;

lib/libcrypto/bn/bn_rand.c

122

bnrand(int pseudorand, BIGNUM *rnd, int bits, int top, int bottom)

lib/libcrypto/bn/bn_rand.c

132

if (bits < 0 || (bits == 1 && top > 0)) {

lib/libcrypto/bn/bn_rand.c

136

if (bits > INT_MAX - 7) {

lib/libcrypto/bn/bn_rand.c

141

if (bits == 0) {

lib/libcrypto/bn/bn_rand.c

146

bytes = (bits + 7) / 8;

lib/libcrypto/bn/bn_rand.c

147

bit = (bits - 1) % 8;

lib/libcrypto/bn/bn_rand.c

201

BN_rand(BIGNUM *rnd, int bits, int top, int bottom)

lib/libcrypto/bn/bn_rand.c

203

return bnrand(0, rnd, bits, top, bottom);

lib/libcrypto/bn/bn_rand.c

208

BN_pseudo_rand(BIGNUM *rnd, int bits, int top, int bottom)

lib/libcrypto/bn/bn_rand.c

210

return bnrand(1, rnd, bits, top, bottom);

lib/libcrypto/bn/bn_rand.c

216

BN_bntest_rand(BIGNUM *rnd, int bits, int top, int bottom)

lib/libcrypto/bn/bn_rand.c

218

return bnrand(2, rnd, bits, top, bottom);

lib/libcrypto/camellia/camellia.c

584

Camellia_set_key(const unsigned char *userKey, const int bits,

lib/libcrypto/camellia/camellia.c

589

if (bits != 128 && bits != 192 && bits != 256)

lib/libcrypto/camellia/camellia.c

591

key->grand_rounds = Camellia_Ekeygen(bits, userKey, key->u.rd_key);

lib/libcrypto/camellia/camellia.h

86

int Camellia_set_key(const unsigned char *userKey, const int bits,

lib/libcrypto/dsa/dsa.h

163

int DSA_generate_parameters_ex(DSA *dsa, int bits,

lib/libcrypto/dsa/dsa_gen.c

103

dsa_builtin_paramgen(DSA *ret, size_t bits, size_t qbits, const EVP_MD *evpmd,

lib/libcrypto/dsa/dsa_gen.c

129

if (bits < 512)

lib/libcrypto/dsa/dsa_gen.c

130

bits = 512;

lib/libcrypto/dsa/dsa_gen.c

132

bits = (bits + 63) / 64 * 64;

lib/libcrypto/dsa/dsa_gen.c

171

if (!BN_lshift(test, BN_value_one(), bits - 1))

lib/libcrypto/dsa/dsa_gen.c

235

n = (bits - 1) / 160;

lib/libcrypto/dsa/dsa_gen.c

266

if (!BN_mask_bits(W, bits - 1))

lib/libcrypto/dsa/dsa_gen.c

83

DSA_generate_parameters_ex(DSA *ret, int bits, const unsigned char *seed_in,

lib/libcrypto/dsa/dsa_gen.c

89

if (bits >= 2048) {

lib/libcrypto/dsa/dsa_gen.c

97

return dsa_builtin_paramgen(ret, bits, qbits, evpmd, seed_in, seed_len,

lib/libcrypto/dsa/dsa_local.h

100

int dsa_builtin_paramgen(DSA *ret, size_t bits, size_t qbits,

lib/libcrypto/ec/ec_mult.c

40

int bits = BN_num_bits(bn);

lib/libcrypto/ec/ec_mult.c

42

if (bits >= 2000)

lib/libcrypto/ec/ec_mult.c

44

if (bits >= 800)

lib/libcrypto/ec/ec_mult.c

46

if (bits >= 300)

lib/libcrypto/ec/ec_mult.c

48

if (bits >= 70)

lib/libcrypto/ec/ec_mult.c

50

if (bits >= 20)

lib/libcrypto/mlkem/mlkem_internal.c

562

scalar_encode(uint8_t *out, const scalar *s, int bits)

lib/libcrypto/mlkem/mlkem_internal.c

567

assert(bits <= (int)sizeof(*s->c) * 8 && bits != 1);

lib/libcrypto/mlkem/mlkem_internal.c

572

while (element_bits_done < bits) {

lib/libcrypto/mlkem/mlkem_internal.c

573

int chunk_bits = bits - element_bits_done;

lib/libcrypto/mlkem/mlkem_internal.c

623

vector_encode(uint8_t *out, const scalar *a, int bits, size_t rank)

lib/libcrypto/mlkem/mlkem_internal.c

628

scalar_encode(out + i * bits * DEGREE / 8, &a[i], bits);

lib/libcrypto/mlkem/mlkem_internal.c

634

vector_encode_cbb(CBB *cbb, const scalar *a, int bits, size_t rank)

lib/libcrypto/mlkem/mlkem_internal.c

640

vector_encode(encoded_vector, a, bits, rank);

lib/libcrypto/mlkem/mlkem_internal.c

651

scalar_decode(scalar *out, const uint8_t *in, int bits)

lib/libcrypto/mlkem/mlkem_internal.c

656

assert(bits <= (int)sizeof(*out->c) * 8 && bits != 1);

lib/libcrypto/mlkem/mlkem_internal.c

662

while (element_bits_done < bits) {

lib/libcrypto/mlkem/mlkem_internal.c

663

int chunk_bits = bits - element_bits_done;

lib/libcrypto/mlkem/mlkem_internal.c

714

vector_decode(scalar *out, const uint8_t *in, int bits, size_t rank)

lib/libcrypto/mlkem/mlkem_internal.c

719

if (!scalar_decode(&out[i], in + i * bits * DEGREE / 8,

lib/libcrypto/mlkem/mlkem_internal.c

720

bits)) {

lib/libcrypto/mlkem/mlkem_internal.c

736

compress(uint16_t x, int bits)

lib/libcrypto/mlkem/mlkem_internal.c

738

uint32_t shifted = (uint32_t)x << bits;

lib/libcrypto/mlkem/mlkem_internal.c

752

return quotient & ((1 << bits) - 1);

lib/libcrypto/mlkem/mlkem_internal.c

761

decompress(uint16_t x, int bits)

lib/libcrypto/mlkem/mlkem_internal.c

764

uint32_t power = 1 << bits;

lib/libcrypto/mlkem/mlkem_internal.c

768

uint32_t lower = product >> bits;

lib/libcrypto/mlkem/mlkem_internal.c

776

return lower + (remainder >> (bits - 1));

lib/libcrypto/mlkem/mlkem_internal.c

780

scalar_compress(scalar *s, int bits)

lib/libcrypto/mlkem/mlkem_internal.c

785

s->c[i] = compress(s->c[i], bits);

lib/libcrypto/mlkem/mlkem_internal.c

790

scalar_decompress(scalar *s, int bits)

lib/libcrypto/mlkem/mlkem_internal.c

795

s->c[i] = decompress(s->c[i], bits);

lib/libcrypto/mlkem/mlkem_internal.c

800

vector_compress(scalar *v, int bits, size_t rank)

lib/libcrypto/mlkem/mlkem_internal.c

805

scalar_compress(&v[i], bits);

lib/libcrypto/mlkem/mlkem_internal.c

810

vector_decompress(scalar *v, int bits, size_t rank)

lib/libcrypto/mlkem/mlkem_internal.c

815

scalar_decompress(&v[i], bits);

lib/libcrypto/modes/cfb128.c

215

size_t bits, const void *key,

lib/libcrypto/modes/cfb128.c

222

for (n = 0; n < bits; ++n)

lib/libcrypto/modes/modes.h

62

size_t bits, const void *key,

lib/libcrypto/rc2/rc2.c

107

if (bits <= 0)

lib/libcrypto/rc2/rc2.c

108

bits = 1024;

lib/libcrypto/rc2/rc2.c

109

if (bits > 1024)

lib/libcrypto/rc2/rc2.c

110

bits = 1024;

lib/libcrypto/rc2/rc2.c

126

j = (bits + 7) >> 3;

lib/libcrypto/rc2/rc2.c

128

c = (0xff >> (-bits & 0x07));

lib/libcrypto/rc2/rc2.c

95

RC2_set_key(RC2_KEY *key, int len, const unsigned char *data, int bits)

lib/libcrypto/rc2/rc2.h

83

void RC2_set_key(RC2_KEY *key, int len, const unsigned char *data, int bits);

lib/libcrypto/rsa/rsa.h

163

#define EVP_PKEY_CTX_set_rsa_keygen_bits(ctx, bits) \

lib/libcrypto/rsa/rsa.h

165

EVP_PKEY_CTRL_RSA_KEYGEN_BITS, bits, NULL)

lib/libcrypto/rsa/rsa.h

243

RSA *RSA_generate_key(int bits, unsigned long e,

lib/libcrypto/rsa/rsa.h

247

int RSA_generate_key_ex(RSA *rsa, int bits, BIGNUM *e, BN_GENCB *cb);

lib/libcrypto/rsa/rsa.h

429

int RSA_meth_set_keygen(RSA_METHOD *meth, int (*keygen)(RSA *rsa, int bits,

lib/libcrypto/rsa/rsa.h

448

int (*RSA_meth_get_keygen(const RSA_METHOD *meth))(RSA *rsa, int bits, BIGNUM *e,

lib/libcrypto/rsa/rsa_gen.c

106

bitsp = (bits + 1) / 2;

lib/libcrypto/rsa/rsa_gen.c

107

bitsq = bits - bitsp;

lib/libcrypto/rsa/rsa_gen.c

114

if (bits < 200)

lib/libcrypto/rsa/rsa_gen.c

116

if (!BN_set_bit(mindiff, bits/2 - 100))

lib/libcrypto/rsa/rsa_gen.c

242

RSA_generate_key(int bits, unsigned long e_value,

lib/libcrypto/rsa/rsa_gen.c

263

if (RSA_generate_key_ex(rsa, bits, e, &cb)) {

lib/libcrypto/rsa/rsa_gen.c

69

static int rsa_builtin_keygen(RSA *rsa, int bits, BIGNUM *e_value, BN_GENCB *cb);

lib/libcrypto/rsa/rsa_gen.c

72

RSA_generate_key_ex(RSA *rsa, int bits, BIGNUM *e_value, BN_GENCB *cb)

lib/libcrypto/rsa/rsa_gen.c

75

return rsa->meth->rsa_keygen(rsa, bits, e_value, cb);

lib/libcrypto/rsa/rsa_gen.c

76

return rsa_builtin_keygen(rsa, bits, e_value, cb);

lib/libcrypto/rsa/rsa_gen.c

81

rsa_builtin_keygen(RSA *rsa, int bits, BIGNUM *e_value, BN_GENCB *cb)

lib/libcrypto/rsa/rsa_local.h

98

int (*rsa_keygen)(RSA *rsa, int bits, BIGNUM *e, BN_GENCB *cb);

lib/libcrypto/rsa/rsa_meth.c

162

RSA_meth_set_keygen(RSA_METHOD *meth, int (*keygen)(RSA *rsa, int bits,

lib/libcrypto/rsa/rsa_meth.c

250

(*RSA_meth_get_keygen(const RSA_METHOD *meth))(RSA *rsa, int bits, BIGNUM *e,

lib/libcrypto/x509/x509_bitst.c

177

i2v_ASN1_BIT_STRING(X509V3_EXT_METHOD *method, ASN1_BIT_STRING *bits,

lib/libcrypto/x509/x509_bitst.c

189

if (!ASN1_BIT_STRING_get_bit(bits, bnam->bitnum))

lib/libcrypto/x509/x509_vfy.c

2504

enough_bits_for_security_level(int bits, int level)

lib/libcrypto/x509/x509_vfy.c

2519

return bits >= 80;

lib/libcrypto/x509/x509_vfy.c

2521

return bits >= 112;

lib/libcrypto/x509/x509_vfy.c

2523

return bits >= 128;

lib/libcrypto/x509/x509_vfy.c

2525

return bits >= 192;

lib/libcrypto/x509/x509_vfy.c

2527

return bits >= 256;

lib/libcrypto/x509/x509_vfy.c

2542

int bits;

lib/libcrypto/x509/x509_vfy.c

2548

if ((bits = EVP_PKEY_security_bits(pkey)) <= 0)

lib/libcrypto/x509/x509_vfy.c

2551

return enough_bits_for_security_level(bits, ctx->param->security_level);

lib/libcrypto/x509/x509_vfy.c

2563

int bits;

lib/libcrypto/x509/x509_vfy.c

2565

if (!X509_get_signature_info(cert, NULL, NULL, &bits, NULL))

lib/libcrypto/x509/x509_vfy.c

2568

return enough_bits_for_security_level(bits, ctx->param->security_level);

lib/libcrypto/x509/x509v3.h

468

ASN1_BIT_STRING *bits,

lib/libcurses/base/lib_color.c

271

result->bits.red = UChar(n);

lib/libcurses/base/lib_color.c

272

result->bits.green = UChar(n);

lib/libcurses/base/lib_color.c

273

result->bits.blue = UChar(width - (2 * n));

lib/libcurses/base/lib_color.c

275

result->bits.red = UChar(n);

lib/libcurses/base/lib_color.c

276

result->bits.green = UChar(n);

lib/libcurses/base/lib_color.c

277

result->bits.blue = UChar(n);

lib/libcurses/base/lib_color.c

297

result->bits.red = UChar(red);

lib/libcurses/base/lib_color.c

298

result->bits.green = UChar(green);

lib/libcurses/base/lib_color.c

299

result->bits.blue = UChar(blue);

lib/libcurses/base/lib_color.c

851

#define max_direct_color(name) ((1 << work->bits.name) - 1)

lib/libcurses/base/lib_color.c

861

bitoff += work->bits.blue;

lib/libcurses/base/lib_color.c

864

bitoff += work->bits.green;

lib/libcurses/curses.priv.h

402

} bits; /* bits per color-value in RGB */

lib/libcurses/tinfo/read_entry.c

739

int bits[4];

lib/libcurses/tinfo/read_entry.c

740

int ch = lookup_b64(bits, &source);

lib/libcurses/tinfo/read_entry.c

746

*target++ = (char) ((bits[0] << 2) | (bits[1] >> 4));

lib/libcurses/tinfo/read_entry.c

747

if (bits[2] < 64) {

lib/libcurses/tinfo/read_entry.c

748

*target++ = (char) ((bits[1] << 4) | (bits[2] >> 2));

lib/libcurses/tinfo/read_entry.c

749

if (bits[3] < 64) {

lib/libcurses/tinfo/read_entry.c

750

*target++ = (char) ((bits[2] << 6) | bits[3]);

lib/libm/arch/hppa/fenv.c

145

u.bits[0] &= ~(excepts << _MASK_SHIFT);

lib/libm/arch/hppa/fenv.c

146

u.bits[0] |= (*flagp & excepts) << _MASK_SHIFT;

lib/libm/arch/hppa/fenv.c

171

return ((u.bits[0] >> _MASK_SHIFT) & excepts);

lib/libm/arch/hppa/fenv.c

187

return (u.bits[0] & _ROUND_MASK);

lib/libm/arch/hppa/fenv.c

210

u.bits[0] &= ~_ROUND_MASK;

lib/libm/arch/hppa/fenv.c

211

u.bits[0] |= round;

lib/libm/arch/hppa/fenv.c

23

unsigned int bits[2];

lib/libm/arch/hppa/fenv.c

233

*envp = u.bits[0];

lib/libm/arch/hppa/fenv.c

254

*envp = u.bits[0];

lib/libm/arch/hppa/fenv.c

257

u.bits[0] &= ~(FE_ALL_EXCEPT << _MASK_SHIFT);

lib/libm/arch/hppa/fenv.c

260

u.bits[0] &= ~FE_ALL_EXCEPT;

lib/libm/arch/hppa/fenv.c

285

u.bits[0] &= ~(FE_ALL_EXCEPT | _ROUND_MASK |

lib/libm/arch/hppa/fenv.c

287

u.bits[0] |= *envp & (FE_ALL_EXCEPT | _ROUND_MASK |

lib/libm/arch/hppa/fenv.c

318

feraiseexcept(u.bits[0] >> _MASK_SHIFT);

lib/libm/arch/hppa/fenv.c

339

omask = u.bits[0] & FE_ALL_EXCEPT;

lib/libm/arch/hppa/fenv.c

340

u.bits[0] |= mask;

lib/libm/arch/hppa/fenv.c

361

omask = u.bits[0] & FE_ALL_EXCEPT;

lib/libm/arch/hppa/fenv.c

362

u.bits[0] &= ~mask;

lib/libm/arch/hppa/fenv.c

379

return (u.bits[0] & FE_ALL_EXCEPT);

lib/libm/arch/hppa/fenv.c

53

u.bits[0] &= ~(excepts << _MASK_SHIFT);

lib/libm/arch/hppa/fenv.c

79

*flagp = (u.bits[0] >> _MASK_SHIFT) & excepts;

lib/libm/arch/powerpc/fenv.c

114

u.bits[1] &= ~excepts;

lib/libm/arch/powerpc/fenv.c

115

u.bits[1] |= *flagp & excepts;

lib/libm/arch/powerpc/fenv.c

118

u.bits[1] |= _FE_INVALID_SOFT;

lib/libm/arch/powerpc/fenv.c

120

u.bits[1] &= ~_FE_INVALID_ALL;

lib/libm/arch/powerpc/fenv.c

145

return (u.bits[1] & excepts);

lib/libm/arch/powerpc/fenv.c

160

return (u.bits[1] & _ROUND_MASK);

lib/libm/arch/powerpc/fenv.c

182

u.bits[1] &= ~_ROUND_MASK;

lib/libm/arch/powerpc/fenv.c

183

u.bits[1] |= round;

lib/libm/arch/powerpc/fenv.c

204

*envp = u.bits[1];

lib/libm/arch/powerpc/fenv.c

224

*envp = u.bits[1];

lib/libm/arch/powerpc/fenv.c

227

u.bits[1] &= ~(FE_ALL_EXCEPT | _FE_INVALID_ALL);

lib/libm/arch/powerpc/fenv.c

23

unsigned int bits[2];

lib/libm/arch/powerpc/fenv.c

230

u.bits[1] &= ~(FE_ALL_EXCEPT >> _MASK_SHIFT);

lib/libm/arch/powerpc/fenv.c

250

u.bits[0] = 0;

lib/libm/arch/powerpc/fenv.c

251

u.bits[1] = *envp;

lib/libm/arch/powerpc/fenv.c

280

feraiseexcept(u.bits[1]);

lib/libm/arch/powerpc/fenv.c

300

omask = (u.bits[1] << _MASK_SHIFT) & FE_ALL_EXCEPT;

lib/libm/arch/powerpc/fenv.c

301

u.bits[1] |= mask >> _MASK_SHIFT;

lib/libm/arch/powerpc/fenv.c

321

omask = (u.bits[1] << _MASK_SHIFT) & FE_ALL_EXCEPT;

lib/libm/arch/powerpc/fenv.c

322

u.bits[1] &= ~(mask >> _MASK_SHIFT);

lib/libm/arch/powerpc/fenv.c

338

return ((u.bits[1] << _MASK_SHIFT) & FE_ALL_EXCEPT);

lib/libm/arch/powerpc/fenv.c

51

u.bits[1] &= ~excepts;

lib/libm/arch/powerpc/fenv.c

53

u.bits[1] &= ~_FE_INVALID_ALL;

lib/libm/arch/powerpc/fenv.c

78

*flagp = u.bits[1] & excepts;

lib/libm/arch/powerpc64/fenv.c

114

u.bits[1] &= ~excepts;

lib/libm/arch/powerpc64/fenv.c

115

u.bits[1] |= *flagp & excepts;

lib/libm/arch/powerpc64/fenv.c

118

u.bits[1] |= _FE_INVALID_SOFT;

lib/libm/arch/powerpc64/fenv.c

120

u.bits[1] &= ~_FE_INVALID_ALL;

lib/libm/arch/powerpc64/fenv.c

145

return (u.bits[1] & excepts);

lib/libm/arch/powerpc64/fenv.c

160

return (u.bits[1] & _ROUND_MASK);

lib/libm/arch/powerpc64/fenv.c

182

u.bits[1] &= ~_ROUND_MASK;

lib/libm/arch/powerpc64/fenv.c

183

u.bits[1] |= round;

lib/libm/arch/powerpc64/fenv.c

204

*envp = u.bits[1];

lib/libm/arch/powerpc64/fenv.c

224

*envp = u.bits[1];

lib/libm/arch/powerpc64/fenv.c

227

u.bits[1] &= ~(FE_ALL_EXCEPT | _FE_INVALID_ALL);

lib/libm/arch/powerpc64/fenv.c

23

unsigned int bits[2];

lib/libm/arch/powerpc64/fenv.c

230

u.bits[1] &= ~(FE_ALL_EXCEPT >> _MASK_SHIFT);

lib/libm/arch/powerpc64/fenv.c

250

u.bits[0] = 0;

lib/libm/arch/powerpc64/fenv.c

251

u.bits[1] = *envp;

lib/libm/arch/powerpc64/fenv.c

280

feraiseexcept(u.bits[1]);

lib/libm/arch/powerpc64/fenv.c

300

omask = (u.bits[1] << _MASK_SHIFT) & FE_ALL_EXCEPT;

lib/libm/arch/powerpc64/fenv.c

301

u.bits[1] |= mask >> _MASK_SHIFT;

lib/libm/arch/powerpc64/fenv.c

321

omask = (u.bits[1] << _MASK_SHIFT) & FE_ALL_EXCEPT;

lib/libm/arch/powerpc64/fenv.c

322

u.bits[1] &= ~(mask >> _MASK_SHIFT);

lib/libm/arch/powerpc64/fenv.c

338

return ((u.bits[1] << _MASK_SHIFT) & FE_ALL_EXCEPT);

lib/libm/arch/powerpc64/fenv.c

51

u.bits[1] &= ~excepts;

lib/libm/arch/powerpc64/fenv.c

53

u.bits[1] &= ~_FE_INVALID_ALL;

lib/libm/arch/powerpc64/fenv.c

78

*flagp = u.bits[1] & excepts;

lib/libm/src/e_acosl.c

52

struct ieee_ext bits;

lib/libm/src/e_acosl.c

57

expsign = (u.bits.ext_sign << 15) | u.bits.ext_exp;

lib/libm/src/e_acosl.c

60

if(expt==BIAS && ((u.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_acosl.c

62

| u.bits.ext_frachm

lib/libm/src/e_acosl.c

65

| u.bits.ext_fraclm

lib/libm/src/e_acosl.c

67

| u.bits.ext_fracl)==0) {

lib/libm/src/e_acosl.c

92

u.bits.ext_fracl = 0;

lib/libm/src/e_acosl.c

94

u.bits.ext_fraclm = 0;

lib/libm/src/e_asinl.c

42

struct ieee_ext bits;

lib/libm/src/e_asinl.c

47

expsign = (u.bits.ext_sign << 15) | u.bits.ext_exp;

lib/libm/src/e_asinl.c

50

if(expt==BIAS && ((u.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_asinl.c

52

| u.bits.ext_frachm

lib/libm/src/e_asinl.c

55

| u.bits.ext_fraclm

lib/libm/src/e_asinl.c

57

| u.bits.ext_fracl)==0)

lib/libm/src/e_asinl.c

78

if((((uint64_t)u.bits.ext_frach << EXT_FRACHMBITS)

lib/libm/src/e_asinl.c

79

| u.bits.ext_frachm) >= THRESH) {

lib/libm/src/e_asinl.c

82

if(u.bits.ext_frach>=THRESH) { /* if |x| is close to 1 */

lib/libm/src/e_asinl.c

88

u.bits.ext_fracl = 0;

lib/libm/src/e_asinl.c

90

u.bits.ext_fraclm = 0;

lib/libm/src/e_atan2l.c

100

if(expty==0 && ((uy.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_atan2l.c

102

| uy.bits.ext_frachm

lib/libm/src/e_atan2l.c

105

| uy.bits.ext_fraclm

lib/libm/src/e_atan2l.c

107

| uy.bits.ext_fracl)==0) {

lib/libm/src/e_atan2l.c

116

if(exptx==0 && ((ux.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_atan2l.c

118

| ux.bits.ext_frachm

lib/libm/src/e_atan2l.c

121

| ux.bits.ext_fraclm

lib/libm/src/e_atan2l.c

123

| ux.bits.ext_fracl)==0)

lib/libm/src/e_atan2l.c

56

struct ieee_ext bits;

lib/libm/src/e_atan2l.c

63

expsigny = (uy.bits.ext_sign << 15) | uy.bits.ext_exp;

lib/libm/src/e_atan2l.c

66

expsignx = (ux.bits.ext_sign << 15) | ux.bits.ext_exp;

lib/libm/src/e_atan2l.c

70

((ux.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_atan2l.c

72

| ux.bits.ext_frachm

lib/libm/src/e_atan2l.c

75

| ux.bits.ext_fraclm

lib/libm/src/e_atan2l.c

77

| ux.bits.ext_fracl)!=0) || /* x is NaN */

lib/libm/src/e_atan2l.c

79

((uy.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_atan2l.c

81

| uy.bits.ext_frachm

lib/libm/src/e_atan2l.c

84

| uy.bits.ext_fraclm

lib/libm/src/e_atan2l.c

86

| uy.bits.ext_fracl)!=0)) /* y is NaN */

lib/libm/src/e_atan2l.c

88

if (expsignx==BIAS && ((ux.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/e_atan2l.c

90

| ux.bits.ext_frachm

lib/libm/src/e_atan2l.c

93

| ux.bits.ext_fraclm

lib/libm/src/e_atan2l.c

95

| ux.bits.ext_fracl)==0)

lib/libm/src/e_sqrtl.c

142

struct ieee_ext bits;

lib/libm/src/e_sqrtl.c

152

if (u.bits.ext_exp == LDBL_MAX_EXP * 2 - 1)

lib/libm/src/e_sqrtl.c

156

if ((u.bits.ext_frach

lib/libm/src/e_sqrtl.c

158

| u.bits.ext_frachm

lib/libm/src/e_sqrtl.c

161

| u.bits.ext_fraclm

lib/libm/src/e_sqrtl.c

163

| u.bits.ext_fracl | u.bits.ext_exp) == 0)

lib/libm/src/e_sqrtl.c

167

if (u.bits.ext_sign)

lib/libm/src/e_sqrtl.c

170

if (u.bits.ext_exp == 0) {

lib/libm/src/e_sqrtl.c

181

if ((u.bits.ext_exp - 0x3ffe) & 1) { /* n is odd. */

lib/libm/src/e_sqrtl.c

182

k += u.bits.ext_exp - 0x3fff; /* 2k = n - 1. */

lib/libm/src/e_sqrtl.c

183

u.bits.ext_exp = 0x3fff; /* u.e in [1,2). */

lib/libm/src/e_sqrtl.c

185

k += u.bits.ext_exp - 0x4000; /* 2k = n - 2. */

lib/libm/src/e_sqrtl.c

186

u.bits.ext_exp = 0x4000; /* u.e in [2,4). */

lib/libm/src/e_sqrtl.c

198

u.bits.ext_fracl = 0; /* Zero out lower bits. */

lib/libm/src/e_sqrtl.c

200

u.bits.ext_fraclm = 0;

lib/libm/src/e_sqrtl.c

205

u.bits.ext_exp += (k >> 1) - 1;

lib/libm/src/e_sqrtl.c

229

u.bits.ext_exp--;

lib/libm/src/ld128/s_exp2l.c

359

struct ieee_ext bits;

lib/libm/src/ld128/s_exp2l.c

368

hx = (u.bits.ext_sign << 15) | u.bits.ext_exp;

lib/libm/src/ld128/s_exp2l.c

372

if (u.bits.ext_frach != 0

lib/libm/src/ld128/s_exp2l.c

373

|| u.bits.ext_frachm != 0

lib/libm/src/ld128/s_exp2l.c

374

|| u.bits.ext_fraclm != 0

lib/libm/src/ld128/s_exp2l.c

375

|| u.bits.ext_fracl != 0

lib/libm/src/ld128/s_exp2l.c

404

i0 = ((((uint64_t)u.bits.ext_fraclm << EXT_FRACLBITS)

lib/libm/src/ld128/s_exp2l.c

405

| u.bits.ext_fracl) & 0xffffffff) + TBLSIZE / 2;

lib/libm/src/ld128/s_exp2l.c

410

v.bits.ext_frach = 0;

lib/libm/src/ld128/s_exp2l.c

411

v.bits.ext_frachm = 0;

lib/libm/src/ld128/s_exp2l.c

412

v.bits.ext_fraclm = 0;

lib/libm/src/ld128/s_exp2l.c

413

v.bits.ext_fracl = 0;

lib/libm/src/ld128/s_exp2l.c

416

v.bits.ext_exp = es & 0x7fffffff;

lib/libm/src/ld128/s_exp2l.c

417

v.bits.ext_sign = u.bits.ext_sign >> 15;

lib/libm/src/ld128/s_exp2l.c

421

v.bits.ext_exp = es & 0x7fffffff;

lib/libm/src/ld128/s_exp2l.c

422

v.bits.ext_sign = u.bits.ext_sign >> 15;

lib/libm/src/ld128/s_nanl.c

42

uint32_t bits[4];

lib/libm/src/ld128/s_nanl.c

45

_scan_nan(u.bits, 4, s);

lib/libm/src/ld80/e_fmodl.c

101

iy = uy.bits.ext_exp - BIAS;

lib/libm/src/ld80/e_fmodl.c

105

hx = SET_NBIT(ux.bits.ext_frach);

lib/libm/src/ld80/e_fmodl.c

106

hy = SET_NBIT(uy.bits.ext_frach);

lib/libm/src/ld80/e_fmodl.c

107

lx = ux.bits.ext_fracl;

lib/libm/src/ld80/e_fmodl.c

108

ly = uy.bits.ext_fracl;

lib/libm/src/ld80/e_fmodl.c

132

ux.bits.ext_frach = hx; /* The mantissa is truncated here if needed. */

lib/libm/src/ld80/e_fmodl.c

133

ux.bits.ext_fracl = lx;

lib/libm/src/ld80/e_fmodl.c

135

ux.bits.ext_exp = iy + (BIAS + 512);

lib/libm/src/ld80/e_fmodl.c

138

ux.bits.ext_exp = iy + BIAS;

lib/libm/src/ld80/e_fmodl.c

58

struct ieee_ext bits;

lib/libm/src/ld80/e_fmodl.c

67

sx = ux.bits.ext_sign;

lib/libm/src/ld80/e_fmodl.c

70

if((uy.bits.ext_exp|uy.bits.ext_frach|uy.bits.ext_fracl)==0 || /* y=0 */

lib/libm/src/ld80/e_fmodl.c

71

(ux.bits.ext_exp == BIAS + LDBL_MAX_EXP) || /* or x not finite */

lib/libm/src/ld80/e_fmodl.c

72

(uy.bits.ext_exp == BIAS + LDBL_MAX_EXP &&

lib/libm/src/ld80/e_fmodl.c

73

((uy.bits.ext_frach&~LDBL_NBIT)|uy.bits.ext_fracl)!=0)) /* or y is NaN */

lib/libm/src/ld80/e_fmodl.c

75

if(ux.bits.ext_exp<=uy.bits.ext_exp) {

lib/libm/src/ld80/e_fmodl.c

76

if((ux.bits.ext_exp<uy.bits.ext_exp) ||

lib/libm/src/ld80/e_fmodl.c

77

(ux.bits.ext_frach<=uy.bits.ext_frach &&

lib/libm/src/ld80/e_fmodl.c

78

(ux.bits.ext_frach<uy.bits.ext_frach ||

lib/libm/src/ld80/e_fmodl.c

79

ux.bits.ext_fracl<uy.bits.ext_fracl))) {

lib/libm/src/ld80/e_fmodl.c

82

if(ux.bits.ext_frach==uy.bits.ext_frach &&

lib/libm/src/ld80/e_fmodl.c

83

ux.bits.ext_fracl==uy.bits.ext_fracl) {

lib/libm/src/ld80/e_fmodl.c

89

if(ux.bits.ext_exp == 0) { /* subnormal x */

lib/libm/src/ld80/e_fmodl.c

91

ix = ux.bits.ext_exp - (BIAS + 512);

lib/libm/src/ld80/e_fmodl.c

93

ix = ux.bits.ext_exp - BIAS;

lib/libm/src/ld80/e_fmodl.c

97

if(uy.bits.ext_exp == 0) { /* subnormal y */

lib/libm/src/ld80/e_fmodl.c

99

iy = uy.bits.ext_exp - (BIAS + 512);

lib/libm/src/ld80/s_exp2l.c

213

struct ieee_ext bits;

lib/libm/src/ld80/s_exp2l.c

221

hx = (u.bits.ext_sign << 15) | u.bits.ext_exp;

lib/libm/src/ld80/s_exp2l.c

225

if ((u.bits.ext_frach != 1U << 31 &&

lib/libm/src/ld80/s_exp2l.c

226

u.bits.ext_fracl != 0) || (hx & 0x8000) == 0)

lib/libm/src/ld80/s_exp2l.c

254

i0 = u.bits.ext_fracl + TBLSIZE / 2;

lib/libm/src/ld80/s_exp2l.c

260

v.bits.ext_frach = 1U << 31;

lib/libm/src/ld80/s_exp2l.c

261

v.bits.ext_fracl = 0;

lib/libm/src/ld80/s_exp2l.c

265

v.bits.ext_exp = es & 0x7fffffff;

lib/libm/src/ld80/s_exp2l.c

266

v.bits.ext_sign = u.bits.ext_sign >> 15;

lib/libm/src/ld80/s_exp2l.c

270

v.bits.ext_exp = es & 0x7fffffff;

lib/libm/src/ld80/s_exp2l.c

271

v.bits.ext_sign = u.bits.ext_sign >> 15;

lib/libm/src/ld80/s_nanl.c

42

uint32_t bits[3];

lib/libm/src/ld80/s_nanl.c

45

_scan_nan(u.bits, 3, s);

lib/libm/src/s_atanl.c

42

struct ieee_ext bits;

lib/libm/src/s_atanl.c

50

expsign = (u.bits.ext_sign << 15) | u.bits.ext_exp;

lib/libm/src/s_atanl.c

54

((u.bits.ext_frach&~LDBL_NBIT)

lib/libm/src/s_atanl.c

56

| u.bits.ext_frachm

lib/libm/src/s_atanl.c

59

| u.bits.ext_fraclm

lib/libm/src/s_atanl.c

61

| u.bits.ext_fracl)!=0)

lib/libm/src/s_atanl.c

69

((u.bits.ext_frach >> (EXT_FRACHBITS - 9)) & 0xff);

lib/libm/src/s_cosl.c

58

struct ieee_ext bits;

lib/libm/src/s_cosl.c

65

z.bits.ext_sign = 0;

lib/libm/src/s_cosl.c

68

if (z.bits.ext_exp == 0)

lib/libm/src/s_cosl.c

72

if (z.bits.ext_exp == 32767)

lib/libm/src/s_logbl.c

25

struct ieee_ext bits;

lib/libm/src/s_logbl.c

31

if (u.bits.ext_exp == 0) {

lib/libm/src/s_logbl.c

32

if ((u.bits.ext_fracl

lib/libm/src/s_logbl.c

34

| u.bits.ext_fraclm

lib/libm/src/s_logbl.c

37

| u.bits.ext_frachm

lib/libm/src/s_logbl.c

39

| u.bits.ext_frach) == 0) { /* x == 0 */

lib/libm/src/s_logbl.c

40

u.bits.ext_sign = 1;

lib/libm/src/s_logbl.c

44

if (u.bits.ext_frach == 0

lib/libm/src/s_logbl.c

46

&& u.bits.ext_frachm == 0

lib/libm/src/s_logbl.c

50

for (b = EXT_FRACHBITS; !(u.bits.ext_fracl & m); m >>= 1)

lib/libm/src/s_logbl.c

54

for (b += EXT_FRACHMBITS; !(u.bits.ext_fraclm & m);

lib/libm/src/s_logbl.c

60

for (b = 0; !(u.bits.ext_frach & m); m >>= 1)

lib/libm/src/s_logbl.c

64

for (; !(u.bits.ext_frachm & m); m >>= 1)

lib/libm/src/s_logbl.c

73

if (u.bits.ext_exp < (LDBL_MAX_EXP << 1) - 1) /* normal */

lib/libm/src/s_logbl.c

74

return ((long double)(u.bits.ext_exp - LDBL_MAX_EXP + 1));

lib/libm/src/s_nan.c

100

uint32_t bits[2];

lib/libm/src/s_nan.c

103

_scan_nan(u.bits, 2, s);

lib/libm/src/s_nan.c

105

u.bits[1] |= 0x7ff80000;

lib/libm/src/s_nan.c

107

u.bits[0] |= 0x7ff80000;

lib/libm/src/s_nan.c

119

uint32_t bits[1];

lib/libm/src/s_nan.c

122

_scan_nan(u.bits, 1, s);

lib/libm/src/s_nan.c

123

u.bits[0] |= 0x7fc00000;

lib/libm/src/s_rintl.c

57

struct ieee_ext bits;

lib/libm/src/s_rintl.c

63

expsign = (u.bits.ext_sign << 15) | u.bits.ext_exp;

lib/libm/src/s_scalbnl.c

45

struct ieee_ext bits;

lib/libm/src/s_scalbnl.c

49

k = u.bits.ext_exp; /* extract exponent */

lib/libm/src/s_scalbnl.c

51

if ((u.bits.ext_frach

lib/libm/src/s_scalbnl.c

53

| u.bits.ext_frachm

lib/libm/src/s_scalbnl.c

56

| u.bits.ext_fraclm

lib/libm/src/s_scalbnl.c

58

| u.bits.ext_fracl)==0) return x; /* +-0 */

lib/libm/src/s_scalbnl.c

60

k = u.bits.ext_exp - 128;

lib/libm/src/s_scalbnl.c

67

{u.bits.ext_exp = k; return u.e;}

lib/libm/src/s_scalbnl.c

74

u.bits.ext_exp = k;

lib/libm/src/s_sincosl.c

55

struct ieee_ext bits;

lib/libm/src/s_sincosl.c

62

z.bits.ext_sign = 0;

lib/libm/src/s_sincosl.c

70

if (z.bits.ext_exp == 0) {

lib/libm/src/s_sincosl.c

79

if (z.bits.ext_exp == 32767) {

lib/libm/src/s_sinl.c

56

struct ieee_ext bits;

lib/libm/src/s_sinl.c

63

s = z.bits.ext_sign;

lib/libm/src/s_sinl.c

64

z.bits.ext_sign = 0;

lib/libm/src/s_sinl.c

67

if (z.bits.ext_exp == 0)

lib/libm/src/s_sinl.c

71

if (z.bits.ext_exp == 32767)

lib/libm/src/s_tanl.c

59

struct ieee_ext bits;

lib/libm/src/s_tanl.c

66

s = z.bits.ext_sign;

lib/libm/src/s_tanl.c

67

z.bits.ext_sign = 0;

lib/libm/src/s_tanl.c

70

if (z.bits.ext_exp == 0)

lib/libm/src/s_tanl.c

74

if (z.bits.ext_exp == 32767)

lib/libsndio/amsg.h

79

uint8_t bits; /* actually used bits */

lib/libsndio/sio_aucat.c

286

hdl->aucat.wmsg.u.par.bits = par->bits;

lib/libsndio/sio_aucat.c

322

par->bits = hdl->aucat.rmsg.u.par.bits;

lib/libsndio/sio_aucat.c

352

cap->enc[i].bits = bps == 4 ? 24 : bps * 8;

lib/libsndio/sio_sun.c

108

ap.bits = enc->bits;

lib/libsndio/sio_sun.c

112

if (ap.bps * 8 > ap.bits)

lib/libsndio/sio_sun.c

132

if (ap.bits != enc->bits)

lib/libsndio/sio_sun.c

138

if (ap.bits < ap.bps * 8 && ap.msb != enc->msb)

lib/libsndio/sio_sun.c

177

ap.bits = encs[i];

lib/libsndio/sio_sun.c

178

ap.sig = (ap.bits > 8) ? 1 : 0;

lib/libsndio/sio_sun.c

181

if (ap.bits == encs[i]) {

lib/libsndio/sio_sun.c

183

cap->enc[i].bits = ap.bits;

lib/libsndio/sio_sun.c

420

ap.bits = par->bits;

lib/libsndio/sio_sun.c

459

par->bits = ap.bits;

lib/libssl/s3_cbc.c

400

unsigned int bits; /* at most 18 bits */

lib/libssl/s3_cbc.c

524

bits = 8*mac_end_offset;

lib/libssl/s3_cbc.c

526

bits += 8*md_block_size;

lib/libssl/s3_cbc.c

537

length_bytes[md_length_size - 4] = (unsigned char)(bits >> 24);

lib/libssl/s3_cbc.c

538

length_bytes[md_length_size - 3] = (unsigned char)(bits >> 16);

lib/libssl/s3_cbc.c

539

length_bytes[md_length_size - 2] = (unsigned char)(bits >> 8);

lib/libssl/s3_cbc.c

540

length_bytes[md_length_size - 1] = (unsigned char)bits;

lib/libssl/s3_cbc.c

543

length_bytes[md_length_size - 5] = (unsigned char)(bits >> 24);

lib/libssl/s3_cbc.c

544

length_bytes[md_length_size - 6] = (unsigned char)(bits >> 16);

lib/libssl/s3_cbc.c

545

length_bytes[md_length_size - 7] = (unsigned char)(bits >> 8);

lib/libssl/s3_cbc.c

546

length_bytes[md_length_size - 8] = (unsigned char)bits;

lib/libssl/ssl_local.h

1223

int bits, int nid, void *other, void *ex_data);

lib/libssl/ssl_local.h

320

int (*security_cb)(const SSL *s, const SSL_CTX *ctx, int op, int bits,

lib/libssl/ssl_seclevel.c

108

if (bits < minimum_bits)

lib/libssl/ssl_seclevel.c

176

ssl_security_secop_tmp_dh(const SSL_CTX *ctx, const SSL *ssl, int bits)

lib/libssl/ssl_seclevel.c

185

if (security_level <= 0 && bits < 80)

lib/libssl/ssl_seclevel.c

188

return bits >= minimum_bits;

lib/libssl/ssl_seclevel.c

192

ssl_security_secop_default(const SSL_CTX *ctx, const SSL *ssl, int bits)

lib/libssl/ssl_seclevel.c

199

return bits >= minimum_bits;

lib/libssl/ssl_seclevel.c

203

ssl_security_default_cb(const SSL *ssl, const SSL_CTX *ctx, int secop, int bits,

lib/libssl/ssl_seclevel.c

210

return ssl_security_secop_cipher(ctx, ssl, bits, cipher);

lib/libssl/ssl_seclevel.c

218

return ssl_security_secop_tmp_dh(ctx, ssl, bits);

lib/libssl/ssl_seclevel.c

220

return ssl_security_secop_default(ctx, ssl, bits);

lib/libssl/ssl_seclevel.c

225

ssl_ctx_security(const SSL_CTX *ctx, int secop, int bits, int nid, void *other)

lib/libssl/ssl_seclevel.c

227

return ctx->cert->security_cb(NULL, ctx, secop, bits, nid,

lib/libssl/ssl_seclevel.c

232

ssl_security(const SSL *ssl, int secop, int bits, int nid, void *other)

lib/libssl/ssl_seclevel.c

234

return ssl->cert->security_cb(ssl, NULL, secop, bits, nid, other,

lib/libssl/ssl_seclevel.c

241

int bits;

lib/libssl/ssl_seclevel.c

243

bits = EVP_PKEY_security_bits(pkey);

lib/libssl/ssl_seclevel.c

245

return ssl_security(ssl, SSL_SECOP_SIGALG_CHECK, bits, 0, NULL);

lib/libssl/ssl_seclevel.c

287

int bits;

lib/libssl/ssl_seclevel.c

289

bits = DH_security_bits(dh);

lib/libssl/ssl_seclevel.c

291

return ssl_ctx_security(ctx, SSL_SECOP_TMP_DH, bits, 0, dh);

lib/libssl/ssl_seclevel.c

297

int bits;

lib/libssl/ssl_seclevel.c

299

bits = DH_security_bits(dh);

lib/libssl/ssl_seclevel.c

301

return ssl_security(ssl, SSL_SECOP_TMP_DH, bits, 0, dh);

lib/libssl/ssl_seclevel.c

444

int bits, nid;

lib/libssl/ssl_seclevel.c

449

if (!tls1_ec_group_id2bits(group_id, &bits))

lib/libssl/ssl_seclevel.c

461

return ssl_security(ssl, secop, bits, nid, group);

lib/libssl/ssl_seclevel.c

95

ssl_security_secop_cipher(const SSL_CTX *ctx, const SSL *ssl, int bits,

lib/libssl/t1_lib.c

156

int bits;

lib/libssl/t1_lib.c

167

.bits = 80,

lib/libssl/t1_lib.c

172

.bits = 80,

lib/libssl/t1_lib.c

177

.bits = 80,

lib/libssl/t1_lib.c

182

.bits = 80,

lib/libssl/t1_lib.c

187

.bits = 80,

lib/libssl/t1_lib.c

192

.bits = 112,

lib/libssl/t1_lib.c

197

.bits = 112,

lib/libssl/t1_lib.c

202

.bits = 112,

lib/libssl/t1_lib.c

207

.bits = 128,

lib/libssl/t1_lib.c

212

.bits = 128,

lib/libssl/t1_lib.c

217

.bits = 192,

lib/libssl/t1_lib.c

222

.bits = 192,

lib/libssl/t1_lib.c

227

.bits = 256,

lib/libssl/t1_lib.c

232

.bits = 256,

lib/libssl/t1_lib.c

237

.bits = 80,

lib/libssl/t1_lib.c

242

.bits = 80,

lib/libssl/t1_lib.c

247

.bits = 80,

lib/libssl/t1_lib.c

252

.bits = 80,

lib/libssl/t1_lib.c

257

.bits = 80,

lib/libssl/t1_lib.c

262

.bits = 112,

lib/libssl/t1_lib.c

267

.bits = 112,

lib/libssl/t1_lib.c

272

.bits = 128,

lib/libssl/t1_lib.c

277

.bits = 128,

lib/libssl/t1_lib.c

282

.bits = 192,

lib/libssl/t1_lib.c

287

.bits = 256,

lib/libssl/t1_lib.c

292

.bits = 128,

lib/libssl/t1_lib.c

297

.bits = 192,

lib/libssl/t1_lib.c

302

.bits = 256,

lib/libssl/t1_lib.c

307

.bits = 128,

lib/libssl/t1_lib.c

312

.bits = 128,

lib/libssl/t1_lib.c

405

*out_bits = sg->bits;

lib/libz/deflate.c

718

int ZEXPORT deflatePending(z_streamp strm, unsigned *pending, int *bits) {

lib/libz/deflate.c

720

if (bits != Z_NULL)

lib/libz/deflate.c

721

*bits = strm->state->bi_valid;

lib/libz/deflate.c

733

int ZEXPORT deflateUsed(z_streamp strm, int *bits) {

lib/libz/deflate.c

735

if (bits != Z_NULL)

lib/libz/deflate.c

736

*bits = strm->state->bi_used;

lib/libz/deflate.c

741

int ZEXPORT deflatePrime(z_streamp strm, int bits, int value) {

lib/libz/deflate.c

748

if (bits < 0 || bits > 16 ||

lib/libz/deflate.c

752

if (bits < 0 || bits > 16 ||

lib/libz/deflate.c

758

if (put > bits)

lib/libz/deflate.c

759

put = bits;

lib/libz/deflate.c

764

bits -= put;

lib/libz/deflate.c

765

} while (bits);

lib/libz/infback.c

117

hold += (unsigned long)(*next++) << bits; \

lib/libz/infback.c

118

bits += 8; \

lib/libz/infback.c

126

while (bits < (unsigned)(n)) \

lib/libz/infback.c

138

bits -= (unsigned)(n); \

lib/libz/infback.c

144

hold >>= bits & 7; \

lib/libz/infback.c

145

bits -= bits & 7; \

lib/libz/infback.c

198

unsigned bits; /* bits in bit buffer */

lib/libz/infback.c

221

bits = 0;

lib/libz/infback.c

355

if ((unsigned)(here.bits) <= bits) break;

lib/libz/infback.c

359

DROPBITS(here.bits);

lib/libz/infback.c

364

NEEDBITS(here.bits + 2);

lib/libz/infback.c

365

DROPBITS(here.bits);

lib/libz/infback.c

381

NEEDBITS(here.bits + 3);

lib/libz/infback.c

382

DROPBITS(here.bits);

lib/libz/infback.c

388

NEEDBITS(here.bits + 7);

lib/libz/infback.c

389

DROPBITS(here.bits);

lib/libz/infback.c

474

if ((unsigned)(here.bits) <= bits) break;

lib/libz/infback.c

481

(BITS(last.bits + last.op) >> last.bits)];

lib/libz/infback.c

482

if ((unsigned)(last.bits + here.bits) <= bits) break;

lib/libz/infback.c

485

DROPBITS(last.bits);

lib/libz/infback.c

487

DROPBITS(here.bits);

lib/libz/infback.c

532

if ((unsigned)(here.bits) <= bits) break;

lib/libz/infback.c

539

(BITS(last.bits + last.op) >> last.bits)];

lib/libz/infback.c

540

if ((unsigned)(last.bits + here.bits) <= bits) break;

lib/libz/infback.c

543

DROPBITS(last.bits);

lib/libz/infback.c

545

DROPBITS(here.bits);

lib/libz/infback.c

76

bits = state->bits; \

lib/libz/infback.c

87

state->bits = bits; \

lib/libz/infback.c

94

bits = 0; \

lib/libz/inffast.c

101

if (bits < 15) {

lib/libz/inffast.c

102

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

103

bits += 8;

lib/libz/inffast.c

104

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

105

bits += 8;

lib/libz/inffast.c

109

op = (unsigned)(here->bits);

lib/libz/inffast.c

111

bits -= op;

lib/libz/inffast.c

123

if (bits < op) {

lib/libz/inffast.c

124

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

125

bits += 8;

lib/libz/inffast.c

129

bits -= op;

lib/libz/inffast.c

132

if (bits < 15) {

lib/libz/inffast.c

133

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

134

bits += 8;

lib/libz/inffast.c

135

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

136

bits += 8;

lib/libz/inffast.c

140

op = (unsigned)(here->bits);

lib/libz/inffast.c

142

bits -= op;

lib/libz/inffast.c

147

if (bits < op) {

lib/libz/inffast.c

148

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

149

bits += 8;

lib/libz/inffast.c

150

if (bits < op) {

lib/libz/inffast.c

151

hold += (unsigned long)(*in++) << bits;

lib/libz/inffast.c

152

bits += 8;

lib/libz/inffast.c

165

bits -= op;

lib/libz/inffast.c

303

len = bits >> 3;

lib/libz/inffast.c

305

bits -= len << 3;

lib/libz/inffast.c

306

hold &= (1U << bits) - 1;

lib/libz/inffast.c

315

state->bits = bits;

lib/libz/inffast.c

65

unsigned bits; /* local strm->bits */

lib/libz/inffast.c

92

bits = state->bits;

lib/libz/inflate.c

1000

state->back += last.bits;

lib/libz/inflate.c

1002

DROPBITS(here.bits);

lib/libz/inflate.c

1003

state->back += here.bits;

lib/libz/inflate.c

1044

if ((unsigned)(here.bits) <= bits) break;

lib/libz/inflate.c

1051

(BITS(last.bits + last.op) >> last.bits)];

lib/libz/inflate.c

1052

if ((unsigned)(last.bits + here.bits) <= bits) break;

lib/libz/inflate.c

1055

DROPBITS(last.bits);

lib/libz/inflate.c

1056

state->back += last.bits;

lib/libz/inflate.c

1058

DROPBITS(here.bits);

lib/libz/inflate.c

1059

state->back += here.bits;

lib/libz/inflate.c

117

state->bits = 0;

lib/libz/inflate.c

1233

strm->data_type = (int)state->bits + (state->last ? 64 : 0) +

lib/libz/inflate.c

1360

if (strm->avail_in == 0 && state->bits < 8) return Z_BUF_ERROR;

lib/libz/inflate.c

1365

state->hold >>= state->bits & 7;

lib/libz/inflate.c

1366

state->bits -= state->bits & 7;

lib/libz/inflate.c

1368

while (state->bits >= 8) {

lib/libz/inflate.c

1371

state->bits -= 8;

lib/libz/inflate.c

1411

return state->mode == STORED && state->bits == 0;

lib/libz/inflate.c

219

int ZEXPORT inflatePrime(z_streamp strm, int bits, int value) {

lib/libz/inflate.c

223

if (bits == 0)

lib/libz/inflate.c

226

if (bits < 0) {

lib/libz/inflate.c

228

state->bits = 0;

lib/libz/inflate.c

231

if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR;

lib/libz/inflate.c

232

value &= (1L << bits) - 1;

lib/libz/inflate.c

233

state->hold += (unsigned long)value << state->bits;

lib/libz/inflate.c

234

state->bits += (uInt)bits;

lib/libz/inflate.c

335

bits = state->bits; \

lib/libz/inflate.c

346

state->bits = bits; \

lib/libz/inflate.c

353

bits = 0; \

lib/libz/inflate.c

362

hold += (unsigned long)(*next++) << bits; \

lib/libz/inflate.c

363

bits += 8; \

lib/libz/inflate.c

370

while (bits < (unsigned)(n)) \

lib/libz/inflate.c

382

bits -= (unsigned)(n); \

lib/libz/inflate.c

388

hold >>= bits & 7; \

lib/libz/inflate.c

389

bits -= bits & 7; \

lib/libz/inflate.c

480

unsigned bits; /* bits in bit buffer */

lib/libz/inflate.c

868

if ((unsigned)(here.bits) <= bits) break;

lib/libz/inflate.c

872

DROPBITS(here.bits);

lib/libz/inflate.c

877

NEEDBITS(here.bits + 2);

lib/libz/inflate.c

878

DROPBITS(here.bits);

lib/libz/inflate.c

894

NEEDBITS(here.bits + 3);

lib/libz/inflate.c

895

DROPBITS(here.bits);

lib/libz/inflate.c

901

NEEDBITS(here.bits + 7);

lib/libz/inflate.c

902

DROPBITS(here.bits);

lib/libz/inflate.c

988

if ((unsigned)(here.bits) <= bits) break;

lib/libz/inflate.c

995

(BITS(last.bits + last.op) >> last.bits)];

lib/libz/inflate.c

996

if ((unsigned)(last.bits + here.bits) <= bits) break;

lib/libz/inflate.c

999

DROPBITS(last.bits);

lib/libz/inflate.h

103

unsigned bits; /* number of bits in hold */

lib/libz/inftrees.c

120

root = *bits;

lib/libz/inftrees.c

126

here.bits = (unsigned char)1;

lib/libz/inftrees.c

130

*bits = 1;

lib/libz/inftrees.c

221

here.bits = (unsigned char)(len - drop);

lib/libz/inftrees.c

290

(*table)[low].bits = (unsigned char)root;

lib/libz/inftrees.c

300

here.bits = (unsigned char)(len - drop);

lib/libz/inftrees.c

307

*bits = root;

lib/libz/inftrees.c

326

unsigned sym, bits;

lib/libz/inftrees.c

338

bits = 9;

lib/libz/inftrees.c

339

inflate_table(LENS, lens, 288, &(next), &(bits), work);

lib/libz/inftrees.c

345

bits = 5;

lib/libz/inftrees.c

346

inflate_table(DISTS, lens, 32, &(next), &(bits), work);

lib/libz/inftrees.c

404

state.lencode[low].bits, state.lencode[low].val);

lib/libz/inftrees.c

414

printf("{%u,%u,%d}", state.distcode[low].op, state.distcode[low].bits,

lib/libz/inftrees.c

46

unsigned FAR *bits, unsigned short FAR *work) {

lib/libz/inftrees.h

26

unsigned char bits; /* bits in this part of the code */

lib/libz/inftrees.h

62

unsigned FAR *bits, unsigned short FAR *work);

lib/libz/trees.c

204

int bits; /* bit index */

lib/libz/trees.c

210

for (bits = 1; bits <= MAX_BITS; bits++) {

lib/libz/trees.c

211

code = (code + bl_count[bits - 1]) << 1;

lib/libz/trees.c

212

next_code[bits] = (ush)code;

lib/libz/trees.c

297

int bits; /* bit counter */

lib/libz/trees.c

349

for (bits = 0; bits <= MAX_BITS; bits++) bl_count[bits] = 0;

lib/libz/trees.c

547

int bits; /* bit length */

lib/libz/trees.c

552

for (bits = 0; bits <= MAX_BITS; bits++) s->bl_count[bits] = 0;

lib/libz/trees.c

561

bits = tree[tree[n].Dad].Len + 1;

lib/libz/trees.c

562

if (bits > max_length) bits = max_length, overflow++;

lib/libz/trees.c

563

tree[n].Len = (ush)bits;

lib/libz/trees.c

568

s->bl_count[bits]++;

lib/libz/trees.c

572

s->opt_len += (ulg)f * (unsigned)(bits + xbits);

lib/libz/trees.c

582

bits = max_length - 1;

lib/libz/trees.c

583

while (s->bl_count[bits] == 0) bits--;

lib/libz/trees.c

584

s->bl_count[bits]--; /* move one leaf down the tree */

lib/libz/trees.c

585

s->bl_count[bits + 1] += 2; /* move one overflow item as its brother */

lib/libz/trees.c

598

for (bits = max_length; bits != 0; bits--) {

lib/libz/trees.c

599

n = s->bl_count[bits];

lib/libz/trees.c

603

if ((unsigned) tree[m].Len != (unsigned) bits) {

lib/libz/trees.c

604

Tracev((stderr,"code %d bits %d->%d\n", m, tree[m].Len, bits));

lib/libz/trees.c

605

s->opt_len += ((ulg)bits - tree[m].Len) * tree[m].Freq;

lib/libz/trees.c

606

tree[m].Len = (ush)bits;

lib/libz/zlib.h

1012

int bits,

lib/libz/zlib.h

788

int *bits);

lib/libz/zlib.h

805

int *bits);

lib/libz/zlib.h

817

int bits,

libexec/ld.so/loader.c

1057

Elf_Addr bits = *reloc >> 1;

libexec/ld.so/loader.c

1060

while (bits != 0) {

libexec/ld.so/loader.c

1061

if (bits & 1) {

libexec/ld.so/loader.c

1064

bits >>= 1;

libexec/ld.so/malloc.c

124

u_short bits[1];

libexec/ld.so/malloc.c

499

init_chunk_info(struct dir_info *d, struct chunk_info *p, int bits)

libexec/ld.so/malloc.c

503

if (bits == 0) {

libexec/ld.so/malloc.c

509

p->shift = bits;

libexec/ld.so/malloc.c

511

p->size = 1U << bits;

libexec/ld.so/malloc.c

518

_dl_memset(p->bits, 0xff, sizeof(p->bits[0]) * (i / MALLOC_BITS));

libexec/ld.so/malloc.c

519

p->bits[i / MALLOC_BITS] = (2U << (i % MALLOC_BITS)) - 1;

libexec/ld.so/malloc.c

523

alloc_chunk_info(struct dir_info *d, int bits)

libexec/ld.so/malloc.c

527

if (LIST_EMPTY(&d->chunk_info_list[bits])) {

libexec/ld.so/malloc.c

531

if (bits == 0)

libexec/ld.so/malloc.c

534

count = MALLOC_PAGESIZE >> bits;

libexec/ld.so/malloc.c

549

LIST_INSERT_HEAD(&d->chunk_info_list[bits],

libexec/ld.so/malloc.c

552

p = LIST_FIRST(&d->chunk_info_list[bits]);

libexec/ld.so/malloc.c

555

init_chunk_info(d, p, bits);

libexec/ld.so/malloc.c

563

omalloc_make_chunks(struct dir_info *d, int bits, int listnum)

libexec/ld.so/malloc.c

573

bp = alloc_chunk_info(d, bits);

libexec/ld.so/malloc.c

577

if (bits == 0 && _dl_mprotect(pp, MALLOC_PAGESIZE, PROT_NONE) < 0)

libexec/ld.so/malloc.c

582

if (insert(d, (void *)((uintptr_t)pp | (bits + 1)), (uintptr_t)bp))

libexec/ld.so/malloc.c

584

LIST_INSERT_HEAD(&d->chunk_dir[bits][listnum], bp, entries);

libexec/ld.so/malloc.c

655

lp = &bp->bits[i / MALLOC_BITS];

libexec/ld.so/malloc.c

669

lp = &bp->bits[i];

libexec/ld.so/malloc.c

683

k += (lp - bp->bits) * MALLOC_BITS;

libexec/ld.so/malloc.c

686

bp->bits[bp->offset + k] = size;

libexec/ld.so/malloc.c

729

validate_canary(ptr, info->bits[info->offset + chunknum],

libexec/ld.so/malloc.c

737

if (info->bits[chunknum / MALLOC_BITS] &

libexec/ld.so/malloc.c

757

info->bits[chunknum / MALLOC_BITS] |= 1U << (chunknum % MALLOC_BITS);

libexec/spamd-setup/spamd-setup.c

107

maxblock(u_int32_t addr, u_int8_t bits)

libexec/spamd-setup/spamd-setup.c

111

while (bits > 0) {

libexec/spamd-setup/spamd-setup.c

112

m = imask(bits - 1);

libexec/spamd-setup/spamd-setup.c

115

return (bits);

libexec/spamd-setup/spamd-setup.c

116

bits--;

libexec/spamd-setup/spamd-setup.c

118

return (bits);

libexec/spamd-setup/spamd-setup.c

124

u_int8_t bits = 0;

libexec/spamd-setup/spamd-setup.c

128

while (bits < 32) {

libexec/spamd-setup/spamd-setup.c

129

m = imask(bits);

libexec/spamd-setup/spamd-setup.c

132

return (bits);

libexec/spamd-setup/spamd-setup.c

133

bits++;

libexec/spamd-setup/spamd-setup.c

135

return (bits);

libexec/spamd-setup/spamd-setup.c

159

list[*cli].bits = maxsize;

libexec/spamd-setup/spamd-setup.c

170

*end = cidr.addr + (1 << (32 - cidr.bits)) - 1;

libexec/spamd-setup/spamd-setup.c

206

c.bits = maskbits;

libexec/spamd-setup/spamd-setup.c

50

u_int8_t bits;

libexec/spamd-setup/spamd-setup.c

636

blacklists->bits);

libexec/spamd-setup/spamd-setup.c

684

blacklists->bits);

regress/lib/libc/cephes/ieee.c

576

register unsigned short bits;

regress/lib/libc/cephes/ieee.c

581

bits = 0;

regress/lib/libc/cephes/ieee.c

585

bits |= 1;

regress/lib/libc/cephes/ieee.c

587

if( bits & 2 )

regress/lib/libc/cephes/ieee.c

589

bits <<= 1;

regress/lib/libc/cephes/ieee.c

603

register unsigned short bits;

regress/lib/libc/cephes/ieee.c

607

bits = 0;

regress/lib/libc/cephes/ieee.c

612

bits |= 1;

regress/lib/libc/cephes/ieee.c

614

if( bits & 2 )

regress/lib/libc/cephes/ieee.c

616

bits <<= 1;

regress/lib/libcrypto/bn/bn_general.c

100

.bits = 16384,

regress/lib/libcrypto/bn/bn_general.c

129

bm->setup(dst, src, bm->bits);

regress/lib/libcrypto/bn/bn_general.c

50

int bits;

regress/lib/libcrypto/bn/bn_general.c

58

.bits = 32,

regress/lib/libcrypto/bn/bn_general.c

64

.bits = 256,

regress/lib/libcrypto/bn/bn_general.c

70

.bits = 320,

regress/lib/libcrypto/bn/bn_general.c

76

.bits = 512,

regress/lib/libcrypto/bn/bn_general.c

82

.bits = 1024,

regress/lib/libcrypto/bn/bn_general.c

88

.bits = 2048,

regress/lib/libcrypto/bn/bn_general.c

94

.bits = 4096,

regress/lib/libcrypto/bn/bn_mod_exp.c

227

int bits;

regress/lib/libcrypto/bn/bn_mod_exp.c

235

bits = avg_bits + arc4random_uniform(deviate) - deviate;

regress/lib/libcrypto/bn/bn_mod_exp.c

237

return BN_rand(bn, bits, 0, force_odd);

regress/lib/libcrypto/bn/bn_test.c

822

int bits = (200 * (i + 1)) / num2;

regress/lib/libcrypto/bn/bn_test.c

824

if (bits == 0)

regress/lib/libcrypto/bn/bn_test.c

826

CHECK_GOTO(BN_bntest_rand(n, bits, 0, 1));

regress/lib/libcrypto/des/destest.c

299

static int cfb_test(int bits, unsigned char *cfb_cipher);

regress/lib/libcrypto/des/destest.c

775

static int cfb_test(int bits, unsigned char *cfb_cipher)

regress/lib/libcrypto/des/destest.c

782

DES_cfb_encrypt(plain,cfb_buf1,bits,sizeof(plain),&ks,&cfb_tmp,

regress/lib/libcrypto/des/destest.c

792

DES_cfb_encrypt(cfb_buf1,cfb_buf2,bits,sizeof(plain),&ks,&cfb_tmp,

regress/lib/libcrypto/rsa/rsa_method_test.c

118

generate_rsa_keypair(int bits, int exponent, RSA **out_priv, RSA **out_pub)

regress/lib/libcrypto/rsa/rsa_method_test.c

133

if (!RSA_generate_key_ex(rsa, bits, e, NULL))

regress/lib/libsndio/cap/cap.c

17

fprintf(stderr, "%s%d", enc->sig ? "s" : "u", enc->bits);

regress/lib/libsndio/cap/cap.c

20

if (enc->bps != SIO_BPS(enc->bits))

regress/lib/libsndio/fd/fd.c

207

par.bits = 16;

regress/lib/libsndio/play/play.c

52

par.bits = 16;

regress/lib/libsndio/rec/rec.c

49

par.bits = 16;

regress/lib/libsndio/tools.c

111

if (bps * 8 < bits)

regress/lib/libsndio/tools.c

134

par->bits = bits;

regress/lib/libsndio/tools.c

30

if (par->bits > 9)

regress/lib/libsndio/tools.c

31

*p++ = '0' + par->bits / 10;

regress/lib/libsndio/tools.c

32

*p++ = '0' + par->bits % 10;

regress/lib/libsndio/tools.c

36

if (par->bps != SIO_BPS(par->bits) ||

regress/lib/libsndio/tools.c

37

par->bits < par->bps * 8) {

regress/lib/libsndio/tools.c

39

if (par->bits < par->bps * 8) {

regress/lib/libsndio/tools.c

58

int i, sig, bits, le, bps, msb;

regress/lib/libsndio/tools.c

79

bits = 0;

regress/lib/libsndio/tools.c

83

bits = (bits * 10) + *p - '0';

regress/lib/libsndio/tools.c

86

if (bits < 1 || bits > 32)

regress/lib/libsndio/tools.c

88

bps = SIO_BPS(bits);

regress/lib/libsndio/vol/vol.c

48

par.bits = 16;

regress/lib/libz/infcover.c

620

unsigned bits;

regress/lib/libz/infcover.c

626

for (bits = 0; bits < 15; bits++)

regress/lib/libz/infcover.c

627

lens[bits] = (unsigned short)(bits + 1);

regress/lib/libz/infcover.c

630

bits = 15;

regress/lib/libz/infcover.c

631

ret = inflate_table(DISTS, lens, 16, &next, &bits, work);

regress/lib/libz/infcover.c

634

bits = 1;

regress/lib/libz/infcover.c

635

ret = inflate_table(DISTS, lens, 16, &next, &bits, work);

regress/sbin/ifconfig/ifaddr.c

1608

int bits, l;

regress/sbin/ifconfig/ifaddr.c

1617

(bits = inet_net_pton(AF_INET, s, &tsin.sin_addr,

regress/sbin/ifconfig/ifaddr.c

1619

l = snprintf(p, sizeof(p), "%d", bits);

regress/sbin/ifconfig/ifaddr.c

1621

errx(1, "%d: bad prefixlen", bits);

regress/sbin/ifconfig/ifaddr.c

1663

printb(char *s, unsigned int v, unsigned char *bits)

regress/sbin/ifconfig/ifaddr.c

1668

if (bits && *bits == 8)

regress/sbin/ifconfig/ifaddr.c

1673

if (bits) {

regress/sbin/ifconfig/ifaddr.c

1674

bits++;

regress/sbin/ifconfig/ifaddr.c

1676

while ((i = *bits++)) {

regress/sbin/ifconfig/ifaddr.c

1681

for (; (c = *bits) > 32; bits++)

regress/sbin/ifconfig/ifaddr.c

1684

for (; *bits > 32; bits++)

regress/sbin/ifconfig/ifaddr.c

1695

printb_status(unsigned short v, unsigned char *bits)

regress/sbin/ifconfig/ifaddr.c

1700

if (bits) {

regress/sbin/ifconfig/ifaddr.c

1701

bits++;

regress/sbin/ifconfig/ifaddr.c

1702

while ((i = *bits++)) {

regress/sbin/ifconfig/ifaddr.c

1707

for (; (c = *bits) > 32; bits++)

regress/sbin/ifconfig/ifaddr.c

1710

for (; *bits > 32; bits++)

regress/sbin/iked/dh/dhtest.c

75

group->spec->bits, ibuf_length(buf) * 8);

regress/sbin/isakmpd/dh/dhtest.c

61

group->spec->bits);

regress/usr.bin/ssh/unittests/kex/test_kex.c

77

struct sshkey *key, int keytype, int bits)

regress/usr.bin/ssh/unittests/kex/test_kex.c

91

ASSERT_INT_EQ(sshkey_generate(keytype, bits, &private), 0);

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

127

signature_bench(const char *name, int ktype, int bits, const char *sig_alg,

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

137

ASSERT_INT_EQ(sshkey_generate(ktype, bits, &k), 0);

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

151

verify_bench(const char *name, int ktype, int bits, const char *sig_alg,

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

161

ASSERT_INT_EQ(sshkey_generate(ktype, bits, &k), 0);

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

208

signature_benchmark(const char *name, int ktype, int bits,

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

215

verify_bench(name, ktype, bits, sig_alg, buf, sizeof(buf));

regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c

217

signature_bench(name, ktype, bits, sig_alg, buf, sizeof(buf));

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

44

int bits;

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

55

if ((bits = inet_net_pton(AF_INET, s, &h->v4, sizeof(h->v4))) == -1)

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

57

*len = bits;

sbin/atactl/atactl.c

460

print_bitinfo(const char *f, u_int bits, struct bitinfo *binfo)

sbin/atactl/atactl.c

464

if (bits & binfo->bitmask)

sbin/ifconfig/ifconfig.c

6477

int bits, l;

sbin/ifconfig/ifconfig.c

6486

(bits = inet_net_pton(AF_INET, s, &tsin.sin_addr,

sbin/ifconfig/ifconfig.c

6488

l = snprintf(p, sizeof(p), "%d", bits);

sbin/ifconfig/ifconfig.c

6490

errx(1, "%d: bad prefixlen", bits);

sbin/ifconfig/ifconfig.c

6534

printb(char *s, unsigned int v, unsigned char *bits)

sbin/ifconfig/ifconfig.c

6539

if (bits && *bits == 8)

sbin/ifconfig/ifconfig.c

6544

if (bits) {

sbin/ifconfig/ifconfig.c

6545

bits++;

sbin/ifconfig/ifconfig.c

6547

while ((i = *bits++)) {

sbin/ifconfig/ifconfig.c

6552

for (; (c = *bits) > 32; bits++)

sbin/ifconfig/ifconfig.c

6555

for (; *bits > 32; bits++)

sbin/ifconfig/ifconfig.c

6566

printb_status(unsigned short v, unsigned char *bits)

sbin/ifconfig/ifconfig.c

6571

if (bits) {

sbin/ifconfig/ifconfig.c

6572

bits++;

sbin/ifconfig/ifconfig.c

6573

while ((i = *bits++)) {

sbin/ifconfig/ifconfig.c

6578

for (; (c = *bits) > 32; bits++)

sbin/ifconfig/ifconfig.c

6581

for (; *bits > 32; bits++)

sbin/iked/dh.c

455

return (roundup(group->spec->bits, 8) / 8);

sbin/iked/dh.c

526

return ((roundup(group->spec->bits, 8) * 2) / 8);

sbin/iked/dh.h

32

int bits;

sbin/iked/util.c

509

print_bits(unsigned short v, unsigned char *bits)

sbin/iked/util.c

516

if (!bits)

sbin/iked/util.c

524

bits++;

sbin/iked/util.c

525

while ((i = *bits++)) {

sbin/iked/util.c

533

for (; (c = *bits) > 32; bits++) {

sbin/iked/util.c

539

for (; *bits > 32; bits++)

sbin/ipsecctl/ipsecctl.c

391

int bits;

sbin/ipsecctl/ipsecctl.c

403

bits = unmask(&ipa->mask);

sbin/ipsecctl/ipsecctl.c

404

if (bits != (ipa->af == AF_INET ? 32 : 128))

sbin/ipsecctl/ipsecctl.c

405

printf("/%d", bits);

sbin/ipsecctl/parse.y

1745

int bits = 32;

sbin/ipsecctl/parse.y

1749

if ((bits = inet_net_pton(AF_INET, s, &ina, sizeof(ina))) == -1)

sbin/ipsecctl/parse.y

1768

set_ipmask(ipa, bits);

sbin/isakmpd/dh.c

368

return (roundup(group->spec->bits, 8) / 8);

sbin/isakmpd/dh.c

437

return ((roundup(group->spec->bits, 8) * 2) / 8);

sbin/isakmpd/dh.h

31

int bits;

sbin/ldattach/ldattach.c

119

int bits = 0, parity = 0, stop = 0, flowcl = 0, hupcl = 1;

sbin/ldattach/ldattach.c

134

bits = 7;

sbin/ldattach/ldattach.c

230

if (bits == 7) {

sbin/ldattach/ldattach.c

233

} else if (bits == 8) {

sbin/pfctl/parse.y

4667

int bits;

sbin/pfctl/parse.y

4673

bits = unmask(&h->addr.v.a.mask);

sbin/pfctl/parse.y

4674

if ((af == AF_INET && bits < 32) ||

sbin/pfctl/parse.y

4675

(af == AF_INET6 && bits < 128))

sbin/pfctl/parse.y

4677

"%s/%d", a, bits);

sbin/pfctl/pf_print_state.c

114

int bits = unmask(&addr->v.a.mask);

sbin/pfctl/pf_print_state.c

116

if (bits < (af == AF_INET ? 32 : 128))

sbin/pfctl/pf_print_state.c

117

printf("/%d", bits);

sbin/pfctl/pfctl_parser.c

1949

int bits;

sbin/pfctl/pfctl_parser.c

1970

bits = 32;

sbin/pfctl/pfctl_parser.c

1975

bits = 128;

sbin/pfctl/pfctl_parser.c

1981

if ((test && (not || addr.pfra_net != bits)) ||

sbin/pfctl/pfctl_parser.c

1982

addr.pfra_net > bits) {

sbin/route/route.c

1037

bits = inet_net_pton(AF_INET, s, &su->sin.sin_addr,

sbin/route/route.c

1039

if (bits == 32)

sbin/route/route.c

1041

if (bits >= 0) {

sbin/route/route.c

1044

&su->sin, bits);

sbin/route/route.c

2252

int bits, bytes, error, first = 1;

sbin/route/route.c

2276

bits = *src;

sbin/route/route.c

2279

bytes = (bits + 7) / 8;

sbin/route/route.c

2292

printf("%s%s/%u %s ", first ? "" : ", ", ntoabuf, bits,

sbin/route/route.c

884

inet_makenetandmask(u_int32_t net, struct sockaddr_in *sin, int bits)

sbin/route/route.c

889

if (bits == 0 && net == 0)

sbin/route/route.c

892

if (bits == 0)

sbin/route/route.c

893

bits = 32;

sbin/route/route.c

894

mask = 0xffffffff << (32 - bits);

sbin/route/route.c

913

int aflength, afamily, bits;

sbin/route/show.c

461

const struct bits *p = bits;

sbin/route/show.c

72

static const struct bits bits[] = {

sbin/savecore/savecore.c

55

extern FILE *zopen(const char *fname, const char *mode, int bits);

sbin/savecore/zopen.c

371

int bits;

sbin/savecore/zopen.c

380

bits = zs->zs_n_bits;

sbin/savecore/zopen.c

388

bits -= (8 - r_off);

sbin/savecore/zopen.c

391

if (bits >= 8) {

sbin/savecore/zopen.c

394

bits -= 8;

sbin/savecore/zopen.c

397

if (bits)

sbin/savecore/zopen.c

434

bits = zs->zs_bp - zs->zs_buf;

sbin/savecore/zopen.c

435

if (write(zs->zs_fd, zs->zs_buf, bits) != bits)

sbin/savecore/zopen.c

437

zs->zs_bytes_out += bits;

sbin/savecore/zopen.c

447

bits = zs->zs_bp - zs->zs_buf;

sbin/savecore/zopen.c

448

if (write(zs->zs_fd, zs->zs_buf, bits) != bits)

sbin/savecore/zopen.c

450

zs->zs_bytes_out += bits;

sbin/savecore/zopen.c

523

zopen(const char *name, const char *mode, int bits)

sbin/savecore/zopen.c

531

if ((cookie = z_open(fd, mode, NULL, bits, 0, 0)) == NULL) {

sbin/savecore/zopen.c

545

z_open(int fd, const char *mode, char *name, int bits,

sbin/savecore/zopen.c

551

bits < 0 || bits > BITS) {

sbin/savecore/zopen.c

560

zs->zs_maxbits = bits ? bits : BITS;

sbin/scsi/libscsi.c

168

u_char bits = 0; /* For bit fields */

sbin/scsi/libscsi.c

219

bits = *databuf++;

sbin/scsi/libscsi.c

222

value = (bits >> (shift - width)) & mask[width];

sbin/scsi/libscsi.c

226

shift, bits, value, width, mask[width]);

sbin/unwind/frontend.c

1004

pq->edns.bits & EDNS_DO, MINIMIZE_ANSWER) == 0)

sbin/unwind/frontend.c

908

pq->edns.bits & EDNS_DO, MINIMIZE_ANSWER) == 0)

sbin/unwind/libunbound/daemon/remote.h

361

void fast_reload_service_cb(int fd, short bits, void* arg);

sbin/unwind/libunbound/libunbound/libworker.c

591

edns->bits = EDNS_DO;

sbin/unwind/libunbound/libunbound/unbound-event.h

98

int fd, short bits, void (*cb)(int, short, void*), void* arg);

sbin/unwind/libunbound/services/authzone.c

3525

edns->bits &= EDNS_DO;

sbin/unwind/libunbound/services/authzone.c

3533

(int)(edns->bits&EDNS_DO), 0)) {

sbin/unwind/libunbound/services/authzone.c

3549

edns->bits &= EDNS_DO;

sbin/unwind/libunbound/services/authzone.c

5452

edns.bits = EDNS_DO;

sbin/unwind/libunbound/services/authzone.c

6647

edns.bits = EDNS_DO;

sbin/unwind/libunbound/services/authzone.c

8469

edns.bits = EDNS_DO;

sbin/unwind/libunbound/services/localzone.c

1331

edns->bits &= EDNS_DO;

sbin/unwind/libunbound/services/localzone.c

1335

buf, 0, 0, temp, udpsize, edns, (int)(edns->bits&EDNS_DO), 0)) {

sbin/unwind/libunbound/services/localzone.c

1353

edns->bits &= EDNS_DO;

sbin/unwind/libunbound/services/mesh.c

1345

r->edns.bits &= EDNS_DO;

sbin/unwind/libunbound/services/mesh.c

1346

if(m->s.env->cfg->disable_edns_do && (r->edns.bits&EDNS_DO))

sbin/unwind/libunbound/services/mesh.c

1354

(int)(r->edns.bits & EDNS_DO), secure))

sbin/unwind/libunbound/services/mesh.c

1479

prev->edns.bits == r->edns.bits &&

sbin/unwind/libunbound/services/mesh.c

1522

r->edns.bits &= EDNS_DO;

sbin/unwind/libunbound/services/mesh.c

1523

if(m->s.env->cfg->disable_edns_do && (r->edns.bits&EDNS_DO))

sbin/unwind/libunbound/services/mesh.c

1541

udp_size, &r->edns, (int)(r->edns.bits & EDNS_DO),

sbin/unwind/libunbound/services/outside_network.c

2817

int bits = 0;

sbin/unwind/libunbound/services/outside_network.c

2826

if(bits == 0) {

sbin/unwind/libunbound/services/outside_network.c

2828

bits = 30;

sbin/unwind/libunbound/services/outside_network.c

2836

bits--;

sbin/unwind/libunbound/services/outside_network.c

2892

edns.bits = 0;

sbin/unwind/libunbound/services/outside_network.c

2894

edns.bits = EDNS_DO;

sbin/unwind/libunbound/services/rpz.c

1805

edns->bits &= EDNS_DO;

sbin/unwind/libunbound/services/rpz.c

1810

buf, 0, 0, temp, udpsize, edns, (int)(edns->bits&EDNS_DO), 0)) {

sbin/unwind/libunbound/util/data/msgencode.c

1123

es.bits &= EDNS_DO;

sbin/unwind/libunbound/util/data/msgencode.c

936

sldns_buffer_write_u16(pkt, edns->bits);

sbin/unwind/libunbound/util/data/msgparse.c

1207

edns->bits = sldns_read_uint16(&found->rr_last->ttl_data[2]);

sbin/unwind/libunbound/util/data/msgparse.c

1303

edns->bits = sldns_buffer_read_u16(pkt);

sbin/unwind/libunbound/util/data/msgparse.c

137

uint8_t win, blen, bits;

sbin/unwind/libunbound/util/data/msgparse.c

145

bits = sldns_buffer_read_u8(pkt);

sbin/unwind/libunbound/util/data/msgparse.c

148

if(win == 0 && blen >= 1 && (bits & 0x02)) {

sbin/unwind/libunbound/util/data/msgparse.h

231

uint16_t bits;

sbin/unwind/libunbound/util/mini_event.c

204

short bits = 0;

sbin/unwind/libunbound/util/mini_event.c

209

bits |= EV_READ;

sbin/unwind/libunbound/util/mini_event.c

213

bits |= EV_WRITE;

sbin/unwind/libunbound/util/mini_event.c

216

bits &= base->fds[i]->ev_events;

sbin/unwind/libunbound/util/mini_event.c

217

if(bits) {

sbin/unwind/libunbound/util/mini_event.c

221

bits, base->fds[i]->ev_arg);

sbin/unwind/libunbound/util/mini_event.c

271

void event_set(struct event* ev, int fd, short bits,

sbin/unwind/libunbound/util/mini_event.c

276

ev->ev_events = bits;

sbin/unwind/libunbound/util/ub_event.h

100

void ub_event_del_bits(struct ub_event*, short bits);

sbin/unwind/libunbound/util/ub_event.h

123

void ub_winsock_tcp_wouldblock(struct ub_event*, int bits);

sbin/unwind/libunbound/util/ub_event.h

89

int fd, short bits, void (*cb)(int, short, void*), void* arg);

sbin/unwind/libunbound/util/ub_event.h

98

void ub_event_add_bits(struct ub_event*, short bits);

sbin/unwind/libunbound/util/ub_event_pluggable.c

156

my_event_add_bits(struct ub_event* ev, short bits)

sbin/unwind/libunbound/util/ub_event_pluggable.c

158

AS_MY_EVENT(ev)->ev.ev_events |= NATIVE_BITS(bits);

sbin/unwind/libunbound/util/ub_event_pluggable.c

162

my_event_del_bits(struct ub_event* ev, short bits)

sbin/unwind/libunbound/util/ub_event_pluggable.c

164

AS_MY_EVENT(ev)->ev.ev_events &= ~NATIVE_BITS(bits);

sbin/unwind/libunbound/util/ub_event_pluggable.c

276

my_event_new(struct ub_event_base* base, int fd, short bits,

sbin/unwind/libunbound/util/ub_event_pluggable.c

285

event_set(&my_ev->ev, fd, NATIVE_BITS(bits), NATIVE_BITS_CB(cb), arg);

sbin/unwind/libunbound/util/ub_event_pluggable.c

508

ub_event_new(struct ub_event_base* base, int fd, short bits,

sbin/unwind/libunbound/util/ub_event_pluggable.c

514

return (*base->vmt->new_event)(base, fd, bits, cb, arg);

sbin/unwind/libunbound/util/ub_event_pluggable.c

545

ub_event_add_bits(struct ub_event* ev, short bits)

sbin/unwind/libunbound/util/ub_event_pluggable.c

550

(*ev->vmt->add_bits)(ev, bits);

sbin/unwind/libunbound/util/ub_event_pluggable.c

555

ub_event_del_bits(struct ub_event* ev, short bits)

sbin/unwind/libunbound/util/ub_event_pluggable.c

560

(*ev->vmt->del_bits)(ev, bits);

sbin/unwind/libunbound/util/ub_event_pluggable.c

89

# define UB_EV_BITS_CB(C) void my_ ## C (int fd, short bits, void *arg) \

sbin/unwind/libunbound/util/ub_event_pluggable.c

90

{ (C)(fd, UB_EV_BITS(bits), arg); }

sbin/unwind/libunbound/util/winsock_event.c

321

short bits = 0;

sbin/unwind/libunbound/util/winsock_event.c

345

bits |= EV_READ;

sbin/unwind/libunbound/util/winsock_event.c

351

bits |= EV_WRITE;

sbin/unwind/libunbound/util/winsock_event.c

357

bits |= EV_READ;

sbin/unwind/libunbound/util/winsock_event.c

358

bits |= EV_WRITE;

sbin/unwind/libunbound/util/winsock_event.c

364

bits |= EV_READ;

sbin/unwind/libunbound/util/winsock_event.c

370

bits |= EV_READ;

sbin/unwind/libunbound/util/winsock_event.c

371

bits |= EV_WRITE;

sbin/unwind/libunbound/util/winsock_event.c

378

bits |= eventlist[i]->old_events;

sbin/unwind/libunbound/util/winsock_event.c

380

if(eventlist[i]->is_tcp && bits) {

sbin/unwind/libunbound/util/winsock_event.c

381

eventlist[i]->old_events = bits;

sbin/unwind/libunbound/util/winsock_event.c

383

if((eventlist[i]->ev_events & bits)) {

sbin/unwind/libunbound/util/winsock_event.c

391

if((bits & eventlist[i]->ev_events)) {

sbin/unwind/libunbound/util/winsock_event.c

402

(bits&EV_READ)?" EV_READ":"",

sbin/unwind/libunbound/util/winsock_event.c

403

(bits&EV_WRITE)?" EV_WRITE":"",

sbin/unwind/libunbound/util/winsock_event.c

404

(bits&EV_TIMEOUT)?" EV_TIMEOUT":"");

sbin/unwind/libunbound/util/winsock_event.c

409

bits & eventlist[i]->ev_events,

sbin/unwind/libunbound/util/winsock_event.c

412

if(eventlist[i]->is_tcp && bits)

sbin/unwind/libunbound/util/winsock_event.c

469

void event_set(struct event *ev, int fd, short bits,

sbin/unwind/libunbound/util/winsock_event.c

474

ev->ev_events = bits;

sbin/unwind/libunbound/validator/autotrust.c

2400

edns.bits = EDNS_DO;

sbin/unwind/libunbound/validator/val_kentry.c

418

size_t bits = 0;

sbin/unwind/libunbound/validator/val_kentry.c

425

if(i==0 || dnskey_get_keysize(d, i) < bits)

sbin/unwind/libunbound/validator/val_kentry.c

426

bits = dnskey_get_keysize(d, i);

sbin/unwind/libunbound/validator/val_kentry.c

428

return bits;

sbin/unwind/libunbound/validator/val_nsec3.c

466

get_max_iter(struct val_env* ve, size_t bits)

sbin/unwind/libunbound/validator/val_nsec3.c

472

if(bits <= ve->nsec3_keysize[i])

sbin/unwind/libunbound/validator/val_nsec3.c

494

size_t bits = key_entry_keysize(kkey);

sbin/unwind/libunbound/validator/val_nsec3.c

495

size_t max_iter = get_max_iter(ve, bits);

sbin/unwind/libunbound/validator/val_nsec3.c

497

(int)bits, (int)max_iter);

sys/arch/alpha/alpha/db_disasm.c

1072

db_printf("? 0x%x ?", i.bits);

sys/arch/alpha/alpha/db_disasm.c

72

unsigned int bits;

sys/arch/alpha/alpha/db_disasm.c

822

inst.bits = db_get_value(loc, 4, 0);

sys/arch/alpha/alpha/db_disasm.c

980

p.bits = i.bits;

sys/arch/alpha/alpha/db_disasm.c

988

p.bits = i.bits;

sys/arch/alpha/alpha/db_instruction.h

91

unsigned int bits;

sys/arch/alpha/alpha/db_instruction.h

98

unsigned bits:26,

sys/arch/alpha/alpha/db_interface.c

285

insn.bits = ins;

sys/arch/alpha/alpha/db_interface.c

296

insn.bits = ins;

sys/arch/alpha/alpha/db_interface.c

306

insn.bits = ins;

sys/arch/alpha/alpha/db_interface.c

316

insn.bits = ins;

sys/arch/alpha/alpha/db_interface.c

345

insn.bits = ins;

sys/arch/alpha/alpha/db_interface.c

368

insn.bits = ins;

sys/arch/alpha/alpha/db_interface.c

400

insn.bits = ins;

sys/arch/alpha/alpha/fp_complete.c

143

this_cannot_happen(int what_cannot_happen, int64_t bits)

sys/arch/alpha/alpha/fp_complete.c

149

inst.bits = bits;

sys/arch/alpha/alpha/fp_complete.c

151

if (bits != -1)

sys/arch/alpha/alpha/fp_complete.c

159

if (bits)

sys/arch/alpha/alpha/fp_complete.c

160

printf("FP instruction %x\n", (unsigned int)bits);

sys/arch/alpha/alpha/fp_complete.c

239

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

276

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

290

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

293

this_cannot_happen(3, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

301

this_cannot_happen(4, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

327

inst.bits = inst_bits;

sys/arch/alpha/alpha/fp_complete.c

500

alpha_fp_interpret(struct proc *p, u_int64_t bits)

sys/arch/alpha/alpha/fp_complete.c

506

inst.bits = bits;

sys/arch/alpha/alpha/fp_complete.c

510

this_cannot_happen(2, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

521

this_cannot_happen(3, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

534

this_cannot_happen(1, inst.bits);

sys/arch/alpha/alpha/fp_complete.c

547

inst.bits, p);

sys/arch/alpha/alpha/fp_complete.c

596

alpha_fp_interpret(p, inst.bits);

sys/arch/alpha/alpha/pmap.c

1389

pt_entry_t *l1pte, *l2pte, *l3pte, bits;

sys/arch/alpha/alpha/pmap.c

1409

bits = pte_prot(pmap, prot);

sys/arch/alpha/alpha/pmap.c

1430

if (pmap_pte_prot_chg(l3pte, bits)) {

sys/arch/alpha/alpha/pmap.c

1432

pmap_pte_set_prot(l3pte, bits);

sys/arch/alpha/alpha/process_machdep.c

284

error = ptrace_read_int(p, pc, &ins.bits);

sys/arch/alpha/alpha/prom.c

114

ret.bits = prom_putstr(alpha_console, to, 1);

sys/arch/alpha/alpha/prom.c

132

ret.bits = prom_getc(alpha_console);

sys/arch/alpha/alpha/prom.c

146

ret.bits = prom_getenv_disp(id, to, len);

sys/arch/alpha/alpha/prom.c

154

return (ret.bits);

sys/arch/alpha/include/prom.h

47

u_int64_t bits;

sys/arch/alpha/pci/tsciic.c

180

tsciicbb_set_bits(void *cookie, uint32_t bits)

sys/arch/alpha/pci/tsciic.c

184

val = (bits & MPD_BIT_SDA ? MPD_DS : 0) |

sys/arch/alpha/pci/tsciic.c

185

(bits & MPD_BIT_SCL ? MPD_CKS : 0);

sys/arch/alpha/pci/tsciic.c

201

uint32_t bits;

sys/arch/alpha/pci/tsciic.c

204

bits = (val & MPD_DR ? MPD_BIT_SDA : 0) |

sys/arch/alpha/pci/tsciic.c

206

return bits;

sys/arch/alpha/stand/boot/disk.c

109

ret.bits = prom_getenv(PROM_E_BOOTED_DEV, devname, sizeof(devname));

sys/arch/alpha/stand/boot/disk.c

112

ret.bits = prom_open((u_int64_t)devname, devlen);

sys/arch/alpha/stand/boot/disk.c

82

ret.bits = prom_read(sc->sc_fd, reqcnt, addr, bn + pp->p_offset);

sys/arch/alpha/stand/boot/disk.c

84

ret.bits = prom_write(sc->sc_fd, reqcnt, addr, bn + pp->p_offset);

sys/arch/alpha/stand/bootxx.c

118

ret.bits = prom_read(fd, bbinfop->bsize, cp,

sys/arch/alpha/stand/bootxx.c

60

ret.bits = prom_getenv(PROM_E_BOOTED_DEV, devname, sizeof(devname));

sys/arch/alpha/stand/bootxx.c

63

ret.bits = prom_open((u_int64_t)devname, devlen);

sys/arch/alpha/stand/nboot/disk.c

104

ret.bits = prom_getenv(PROM_E_BOOTED_DEV, devname, sizeof(devname));

sys/arch/alpha/stand/nboot/disk.c

107

ret.bits = prom_open((u_int64_t)devname, devlen);

sys/arch/alpha/stand/nboot/disk.c

80

ret.bits = prom_read(sc->sc_fd, reqcnt, addr, bn);

sys/arch/alpha/stand/nboot/disk.c

82

ret.bits = prom_write(sc->sc_fd, reqcnt, addr, bn);

sys/arch/alpha/stand/nboot/prom.c

64

ret.bits = prom_dispatch(PROM_R_GETENV, id, (u_int64_t)abuf, 128, 0);

sys/arch/alpha/stand/nboot/promcons.c

73

ret.bits = prom_dispatch(PROM_R_GETC, unit, 0, 0, 0);

sys/arch/alpha/stand/nboot/promcons.c

93

ret.bits = prom_dispatch(PROM_R_PUTS, unit,

sys/arch/alpha/stand/netboot/if_prom.c

124

ret.bits = prom_read(netfd, 0, hate, 0);

sys/arch/alpha/stand/netboot/if_prom.c

126

ret.bits = prom_read(netfd, sizeof hate, hate, 0);

sys/arch/alpha/stand/netboot/if_prom.c

171

ret.bits = prom_getenv(PROM_E_BOOTED_DEV, devname, sizeof(devname));

sys/arch/alpha/stand/netboot/if_prom.c

214

ret.bits = prom_open((u_int64_t)devname, devlen + 1);

sys/arch/alpha/stand/prom.c

106

ret.bits = prom_dispatch(PROM_R_GETENV, id, (u_int64_t)abuf, 128, 0);

sys/arch/alpha/stand/prom.c

64

ret.bits = prom_dispatch(PROM_R_GETC, console, 0, 0, 0);

sys/arch/alpha/stand/prom.c

80

ret.bits = prom_dispatch(PROM_R_PUTS, console,

sys/arch/alpha/stand/prom.c

87

ret.bits = prom_dispatch(PROM_R_PUTS, console,

sys/arch/alpha/tc/ioasic.c

300

#define CHECKINTR(slot, bits, clear) \

sys/arch/alpha/tc/ioasic.c

301

if (sir & (bits)) { \

sys/arch/alpha/tc/ioasic.c

307

sir &= ~(bits); \

sys/arch/alpha/tc/tc_3000_300.c

250

#define PRINTINTR(msg, bits) \

sys/arch/alpha/tc/tc_3000_300.c

251

if (tcir & bits) \

sys/arch/alpha/tc/tc_3000_500.c

235

#define PRINTINTR(msg, bits) \

sys/arch/alpha/tc/tc_3000_500.c

236

if (ir & bits) \

sys/arch/amd64/amd64/identcpu.c

357

pmsr032(uint32_t msr, uint32_t value, const char *bits)

sys/arch/amd64/amd64/identcpu.c

360

printf("\ncpu0: msr %x=%b", msr, value, bits);

sys/arch/amd64/amd64/identcpu.c

364

pbitdiff(uint32_t value, uint32_t base_value, const char *bits)

sys/arch/amd64/amd64/identcpu.c

372

printf("-%b", minus, bits);

sys/arch/amd64/amd64/identcpu.c

374

printf("+%b", value, bits);

sys/arch/amd64/amd64/identcpu.c

379

uint32_t prev_val, const char *bits)

sys/arch/amd64/amd64/identcpu.c

382

pcpu0id3(id, reg, val, bits, 0, 0, NULL, 0, 0, NULL);

sys/arch/amd64/amd64/identcpu.c

385

pbitdiff(val, prev_val, bits);

sys/arch/amd64/amd64/identcpu.c

438

const char *bits)

sys/arch/amd64/amd64/identcpu.c

441

pmsr032(msr, value, bits);

sys/arch/amd64/amd64/identcpu.c

444

pbitdiff(value, prev_value, bits);

sys/arch/amd64/include/atomic.h

290

x86_atomic_setbits_u32(volatile u_int32_t *ptr, u_int32_t bits)

sys/arch/amd64/include/atomic.h

292

__asm volatile(_LOCK " orl %1,%0" : "=m" (*ptr) : "ir" (bits));

sys/arch/amd64/include/atomic.h

296

x86_atomic_clearbits_u32(volatile u_int32_t *ptr, u_int32_t bits)

sys/arch/amd64/include/atomic.h

298

__asm volatile(_LOCK " andl %1,%0" : "=m" (*ptr) : "ir" (~bits));

sys/arch/amd64/include/atomic.h

302

x86_atomic_setbits_u64(volatile u_int64_t *ptr, u_int64_t bits)

sys/arch/amd64/include/atomic.h

304

__asm volatile(_LOCK " orq %1,%0" : "=m" (*ptr) : "er" (bits));

sys/arch/amd64/include/atomic.h

308

x86_atomic_clearbits_u64(volatile u_int64_t *ptr, u_int64_t bits)

sys/arch/amd64/include/atomic.h

310

__asm volatile(_LOCK " andq %1,%0" : "=m" (*ptr) : "er" (~bits));

sys/arch/arm64/arm64/cryptox.c

69

extern int aes_v8_set_encrypt_key(const uint8_t *user_key, const int bits,

sys/arch/arm64/arm64/cryptox.c

71

extern int aes_v8_set_decrypt_key(const uint8_t *user_key, const int bits,

sys/arch/arm64/arm64/pmap.c

229

uint32_t bits;

sys/arch/arm64/arm64/pmap.c

238

bits = pmap_asid[asid / 32];

sys/arch/arm64/arm64/pmap.c

239

if ((bits & (3U << bit)) == 0)

sys/arch/arm64/arm64/pmap.c

246

bits = pmap_asid[asid / 32];

sys/arch/arm64/arm64/pmap.c

247

if ((bits & (3U << bit)) == 0)

sys/arch/arm64/arm64/pmap.c

253

bits = pmap_asid[asid / 32];

sys/arch/arm64/arm64/pmap.c

254

if (bits == ~0)

sys/arch/arm64/arm64/pmap.c

257

if ((bits & (3U << bit)) == 0)

sys/arch/arm64/dev/agintc.c

316

uint32_t ctrl, bits;

sys/arch/arm64/dev/agintc.c

591

bits = GICD_CTLR_ARE_NS | GICD_CTLR_EnableGrp1A | GICD_CTLR_EnableGrp1;

sys/arch/arm64/dev/agintc.c

593

bits &= ~GICD_CTLR_EnableGrp1A;

sys/arch/arm64/dev/agintc.c

594

bits <<= 1;

sys/arch/arm64/dev/agintc.c

596

bus_space_write_4(sc->sc_iot, sc->sc_d_ioh, GICD_CTLR, ctrl | bits);

sys/arch/arm64/dev/apldc.c

68

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/apldc.c

69

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/apldc.c

70

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/apldc.c

71

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/apliic.c

60

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/apliic.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/apliic.c

62

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/apliic.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplintc.c

87

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/aplintc.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplintc.c

89

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/aplintc.c

90

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplmca.c

100

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/aplmca.c

101

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplmca.c

102

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/aplmca.c

103

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplnco.c

46

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/aplnco.c

47

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplnco.c

48

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/aplnco.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpcie.c

105

#define LSET4(sc, port, reg, bits) \

sys/arch/arm64/dev/aplpcie.c

106

LWRITE4((sc), (port), (reg), LREAD4((sc), (port), (reg)) | (bits))

sys/arch/arm64/dev/aplpcie.c

107

#define LCLR4(sc, port, reg, bits) \

sys/arch/arm64/dev/aplpcie.c

108

LWRITE4((sc), (port), (reg), LREAD4((sc), (port), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpcie.c

114

#define PSET4(sc, port, reg, bits) \

sys/arch/arm64/dev/aplpcie.c

115

PWRITE4((sc), (port), (reg), PREAD4((sc), (port), (reg)) | (bits))

sys/arch/arm64/dev/aplpcie.c

116

#define PCLR4(sc, port, reg, bits) \

sys/arch/arm64/dev/aplpcie.c

117

PWRITE4((sc), (port), (reg), PREAD4((sc), (port), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpcie.c

96

#define RSET4(sc, reg, bits) \

sys/arch/arm64/dev/aplpcie.c

97

RWRITE4((sc), (reg), RREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplpcie.c

98

#define RCLR4(sc, reg, bits) \

sys/arch/arm64/dev/aplpcie.c

99

RWRITE4((sc), (reg), RREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpinctrl.c

58

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/aplpinctrl.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplpinctrl.c

60

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/aplpinctrl.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplspi.c

100

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplspi.c

101

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/aplspi.c

102

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplspi.c

99

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/bcm2712_mip.c

49

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/bcm2712_mip.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/bcm2712_mip.c

51

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/bcm2712_mip.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/rpiclock.c

59

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/rpiclock.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/rpiclock.c

61

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/rpiclock.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/rpipwm.c

36

#define HSET4(sc, reg, bits) \

sys/arch/arm64/dev/rpipwm.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/rpipwm.c

38

#define HCLR4(sc, reg, bits) \

sys/arch/arm64/dev/rpipwm.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exclock.c

60

#define HSET4(sc, reg, bits) \

sys/arch/armv7/exynos/exclock.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/exclock.c

62

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/exynos/exclock.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exiic.c

100

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exiic.c

97

#define HSET4(sc, reg, bits) \

sys/arch/armv7/exynos/exiic.c

98

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/exiic.c

99

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/exynos/expower.c

35

#define HSET4(sc, reg, bits) \

sys/arch/armv7/exynos/expower.c

36

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/expower.c

37

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/exynos/expower.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/imx/imxtemp.c

65

#define HSET4(sc, reg, bits) \

sys/arch/armv7/imx/imxtemp.c

66

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/imx/imxtemp.c

67

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/imx/imxtemp.c

68

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvacc.c

38

#define HSET4(sc, reg, bits) \

sys/arch/armv7/marvell/mvacc.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvacc.c

40

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/marvell/mvacc.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvagc.c

32

#define HSET4(sc, reg, bits) \

sys/arch/armv7/marvell/mvagc.c

33

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvagc.c

34

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/marvell/mvagc.c

35

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvodog.c

37

#define HSET4(sc, ioh, reg, bits) \

sys/arch/armv7/marvell/mvodog.c

38

HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) | (bits))

sys/arch/armv7/marvell/mvodog.c

39

#define HCLR4(sc, ioh, reg, bits) \

sys/arch/armv7/marvell/mvodog.c

40

HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvpcie.c

81

#define HSET4(po, reg, bits) \

sys/arch/armv7/marvell/mvpcie.c

82

HWRITE4((po), (reg), HREAD4((po), (reg)) | (bits))

sys/arch/armv7/marvell/mvpcie.c

83

#define HCLR4(po, reg, bits) \

sys/arch/armv7/marvell/mvpcie.c

84

HWRITE4((po), (reg), HREAD4((po), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvsysctrl.c

37

#define HSET4(sc, reg, bits) \

sys/arch/armv7/marvell/mvsysctrl.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvsysctrl.c

39

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/marvell/mvsysctrl.c

40

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/amdisplay.c

58

#define HSET4(sc, reg, bits) \

sys/arch/armv7/omap/amdisplay.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/amdisplay.c

60

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/omap/amdisplay.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/nxphdmi.c

499

nxphdmi_set(struct nxphdmi_softc *sc, uint16_t reg, uint8_t bits)

sys/arch/armv7/omap/nxphdmi.c

505

buf |= bits;

sys/arch/armv7/omap/nxphdmi.c

512

nxphdmi_clear(struct nxphdmi_softc *sc, uint16_t reg, uint8_t bits)

sys/arch/armv7/omap/nxphdmi.c

518

buf &= ~bits;

sys/arch/armv7/omap/omclock.c

42

#define HSET4(sc, reg, bits) \

sys/arch/armv7/omap/omclock.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/omclock.c

44

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/omap/omclock.c

45

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/ommmc.c

225

#define HSET4(sc, reg, bits) \

sys/arch/armv7/omap/ommmc.c

226

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/ommmc.c

227

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/omap/ommmc.c

228

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/omrng.c

59

#define HSET4(sc, reg, bits) \

sys/arch/armv7/omap/omrng.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/omrng.c

61

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/omap/omrng.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/vexpress/pciecam.c

53

#define HSET4(sc, reg, bits) \

sys/arch/armv7/vexpress/pciecam.c

54

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/vexpress/pciecam.c

55

#define HCLR4(sc, reg, bits) \

sys/arch/armv7/vexpress/pciecam.c

56

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/hppa/gsc/harmony.c

1048

return (harmony_speeds[selected].bits);

sys/arch/hppa/gsc/harmony.c

1054

u_int32_t bits, mask, val, old;

sys/arch/hppa/gsc/harmony.c

1057

bits = GAINCTL_LE | GAINCTL_HE | GAINCTL_SE | GAINCTL_IS_MASK;

sys/arch/hppa/gsc/harmony.c

1060

bits |= ((sc->sc_input_lvl.left >> (8 - GAINCTL_INPUT_BITS)) <<

sys/arch/hppa/gsc/harmony.c

1062

bits |= ((sc->sc_input_lvl.right >> (8 - GAINCTL_INPUT_BITS)) <<

sys/arch/hppa/gsc/harmony.c

1068

bits |= (val << GAINCTL_OUTPUT_LEFT_S) & GAINCTL_OUTPUT_LEFT_M;

sys/arch/hppa/gsc/harmony.c

1070

bits |= (val << GAINCTL_OUTPUT_RIGHT_S) & GAINCTL_OUTPUT_RIGHT_M;

sys/arch/hppa/gsc/harmony.c

1075

bits |= (val << GAINCTL_MONITOR_S) & GAINCTL_MONITOR_M;

sys/arch/hppa/gsc/harmony.c

1078

bits &= ~GAINCTL_IS_MASK;

sys/arch/hppa/gsc/harmony.c

1080

bits |= GAINCTL_IS_LINE;

sys/arch/hppa/gsc/harmony.c

1082

bits |= GAINCTL_IS_MICROPHONE;

sys/arch/hppa/gsc/harmony.c

1085

bits &= ~(GAINCTL_LE | GAINCTL_HE | GAINCTL_SE);

sys/arch/hppa/gsc/harmony.c

1087

bits |= GAINCTL_LE;

sys/arch/hppa/gsc/harmony.c

1089

bits |= GAINCTL_SE;

sys/arch/hppa/gsc/harmony.c

1091

bits |= GAINCTL_HE;

sys/arch/hppa/gsc/harmony.c

1095

bus_space_write_4(sc->sc_bt, sc->sc_bh, HARMONY_GAINCTL, bits);

sys/arch/hppa/gsc/harmony.c

1096

if ((old & mask) != (bits & mask))

sys/arch/hppa/gsc/harmony.c

379

u_int32_t bits;

sys/arch/hppa/gsc/harmony.c

383

bits = CNTL_FORMAT_ULAW;

sys/arch/hppa/gsc/harmony.c

387

bits = CNTL_FORMAT_ALAW;

sys/arch/hppa/gsc/harmony.c

392

bits = CNTL_FORMAT_SLINEAR16BE;

sys/arch/hppa/gsc/harmony.c

399

bits = CNTL_FORMAT_ULINEAR8;

sys/arch/hppa/gsc/harmony.c

408

bits |= CNTL_OLB;

sys/arch/hppa/gsc/harmony.c

411

bits |= CNTL_CHANS_MONO;

sys/arch/hppa/gsc/harmony.c

413

bits |= CNTL_CHANS_STEREO;

sys/arch/hppa/gsc/harmony.c

424

bits |= harmony_speed_bits(sc, &p->sample_rate);

sys/arch/hppa/gsc/harmony.c

425

sc->sc_cntlbits = bits;

sys/arch/hppa/gsc/harmony.c

998

u_int32_t bits;

sys/arch/hppa/include/pdc.h

667

#define PZL_ENCODE(bits, parity, speed) \

sys/arch/hppa/include/pdc.h

668

(((bits) - 5) & 0x03) | (((parity) & 0x3) << 3) | \

sys/arch/hppa/stand/libsa/cmd_hppa.c

168

int port, mode, speed, parity, bits;

sys/arch/hppa/stand/libsa/cmd_hppa.c

237

bits = PZL_BITS(sstor.ss_console.dp_layers[0]);

sys/arch/hppa/stand/libsa/cmd_hppa.c

238

printf(".%d", bits);

sys/arch/hppa/stand/libsa/cmd_hppa.c

318

int speed, parity, bits;

sys/arch/hppa/stand/libsa/cmd_hppa.c

356

bits = 8;

sys/arch/hppa/stand/libsa/cmd_hppa.c

359

bits = *arg - '0';

sys/arch/hppa/stand/libsa/cmd_hppa.c

361

bits = 0;

sys/arch/hppa/stand/libsa/cmd_hppa.c

363

if (bits < 5 || bits > 8) {

sys/arch/hppa/stand/libsa/cmd_hppa.c

391

console->dp_layers[0] = PZL_ENCODE(bits, parity, speed);

sys/arch/i386/i386/db_memrw.c

107

if (bits & PG_PS)

sys/arch/i386/i386/db_memrw.c

130

pmap_pte_setbits(addr, bits, PG_RW);

sys/arch/i386/i386/db_memrw.c

71

uint32_t bits;

sys/arch/i386/i386/db_memrw.c

83

bits = pmap_pte_bits(addr);

sys/arch/i386/i386/db_memrw.c

85

if ((bits & PG_V) == 0) {

sys/arch/i386/i386/db_memrw.c

93

if (bits & PG_PS) {

sys/arch/i386/i386/pmap.c

664

pmap_pte_set_86(vaddr_t va, paddr_t pa, u_int32_t bits)

sys/arch/i386/i386/pmap.c

670

pte = i386_atomic_testset_ul(ptep, pa | bits); /* zap! */

sys/arch/i386/i386/pmap.c

833

uint32_t bits;

sys/arch/i386/i386/pmap.c

845

bits = pmap_pte_set(va, pa, ((prot & PROT_WRITE) ? PG_RW : PG_RO) |

sys/arch/i386/i386/pmap.c

850

if (pmap_valid_entry(bits)) {

sys/arch/i386/i386/pmap.c

851

if (pa & PMAP_NOCACHE && (bits & PG_N) == 0)

sys/arch/i386/i386/pmap.c

871

uint32_t bits;

sys/arch/i386/i386/pmap.c

877

bits = pmap_pte_set(va, 0, 0);

sys/arch/i386/i386/pmap.c

879

if (bits & PG_PVLIST)

sys/arch/i386/i386/pmapae.c

566

pmap_pte_set_pae(vaddr_t va, paddr_t pa, u_int32_t bits)

sys/arch/i386/i386/pmapae.c

573

if (bits & PG_X)

sys/arch/i386/i386/pmapae.c

578

pte = i386_atomic_testset_uq(ptep, pa | bits | nx); /* zap! */

sys/arch/i386/i386/pmapae.c

650

u_int32_t bits, *pd = NULL;

sys/arch/i386/i386/pmapae.c

699

bits = pmap_pte_bits_86(va) | pmap_pg_g;

sys/arch/i386/i386/pmapae.c

712

bits |= PG_X;

sys/arch/i386/i386/pmapae.c

714

bits &= ~PG_X;

sys/arch/i386/i386/pmapae.c

716

if (pmap_valid_entry(bits))

sys/arch/i386/i386/pmapae.c

717

pmap_pte_set_pae(va, pmap_pte_paddr_86(va), bits);

sys/arch/i386/i386/pmapae.c

752

bits = ptp[l1idx] & (PG_PROT|PG_N|PG_WT);

sys/arch/i386/i386/pmapae.c

761

pmap_enter_special_pae(va, npa, 0, bits);

sys/arch/i386/include/atomic.h

296

i386_atomic_setbits_l(volatile u_int32_t *ptr, unsigned long bits)

sys/arch/i386/include/atomic.h

298

__asm volatile(_LOCK " orl %1,%0" : "=m" (*ptr) : "ir" (bits));

sys/arch/i386/include/atomic.h

302

i386_atomic_clearbits_l(volatile u_int32_t *ptr, unsigned long bits)

sys/arch/i386/include/atomic.h

304

bits = ~bits;

sys/arch/i386/include/atomic.h

305

__asm volatile(_LOCK " andl %1,%0" : "=m" (*ptr) : "ir" (bits));

sys/arch/loongson/dev/gdiumiic.c

300

gdiumiic_bb_set_bits(void *cookie, u_int32_t bits)

sys/arch/loongson/dev/gdiumiic.c

305

bits & GPIOIIC_SDA ? GPIO_PIN_HIGH : GPIO_PIN_LOW);

sys/arch/loongson/dev/gdiumiic.c

307

bits & GPIOIIC_SCL ? GPIO_PIN_HIGH : GPIO_PIN_LOW);

sys/arch/loongson/dev/gdiumiic.c

311

gdiumiic_bb_set_dir(void *cookie, u_int32_t bits)

sys/arch/loongson/dev/gdiumiic.c

317

sda |= (bits & GPIOIIC_SDA ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT);

sys/arch/loongson/dev/gdiumiic.c

319

if ((sda & GPIO_PIN_PUSHPULL) && !(bits & GPIOIIC_SDA))

sys/arch/loongson/dev/gdiumiic.c

333

u_int32_t bits = 0;

sys/arch/loongson/dev/gdiumiic.c

337

bits |= GPIOIIC_SDA;

sys/arch/loongson/dev/gdiumiic.c

340

bits |= GPIOIIC_SCL;

sys/arch/loongson/dev/gdiumiic.c

342

return bits;

sys/arch/luna88k/cbus/nec86hw.c

863

nec86hw_set_rate_real(struct nec86hw_softc *sc, u_int8_t bits)

sys/arch/luna88k/cbus/nec86hw.c

871

data |= bits & NEC86_FIFOCTL_MASK_RATE;

sys/arch/m88k/include/ieeefp.h

66

#define float_raise(bits) curproc->p_md.md_tf->tf_fpsr |= bits

sys/arch/macppc/dev/awacs.c

1090

sc->sc_soundctl |= awacs_speeds[selected].bits;

sys/arch/macppc/dev/awacs.c

209

u_int32_t bits;

sys/arch/macppc/dev/uni_n.c

216

memc_enable(struct memc_softc *sc, int offset, uint32_t bits)

sys/arch/macppc/dev/uni_n.c

218

bits |= memc_read(sc, offset);

sys/arch/macppc/dev/uni_n.c

219

memc_write(sc, offset, bits);

sys/arch/macppc/dev/uni_n.c

223

memc_disable(struct memc_softc *sc, int offset, uint32_t bits)

sys/arch/macppc/dev/uni_n.c

225

bits = memc_read(sc, offset) & ~bits;

sys/arch/macppc/dev/uni_n.c

226

memc_write(sc, offset, bits);

sys/arch/macppc/pci/macobio.c

240

macobio_enable(int offset, u_int32_t bits)

sys/arch/macppc/pci/macobio.c

246

bits |= in32rb(sc->obiomem + offset);

sys/arch/macppc/pci/macobio.c

247

out32rb(sc->obiomem + offset, bits);

sys/arch/macppc/pci/macobio.c

250

macobio_disable(int offset, u_int32_t bits)

sys/arch/macppc/pci/macobio.c

256

bits = in32rb(sc->obiomem + offset) & ~bits;

sys/arch/macppc/pci/macobio.c

257

out32rb(sc->obiomem + offset, bits);

sys/arch/macppc/pci/macobio.c

271

macobio_write(int offset, uint8_t bits)

sys/arch/macppc/pci/macobio.c

277

out8rb(sc->obiomem + offset, bits);

sys/arch/mips64/include/ieeefp.h

36

#define float_raise(bits) \

sys/arch/mips64/include/ieeefp.h

37

do { curproc->p_md.md_regs->fsr |= (bits) << FPCSR_C_SHIFT; } while (0)

sys/arch/octeon/dev/octdwctwo.c

296

u_int64_t bits)

sys/arch/octeon/dev/octdwctwo.c

300

value |= bits;

sys/arch/octeon/dev/octdwctwo.c

308

u_int64_t bits)

sys/arch/octeon/dev/octdwctwo.c

312

value &= ~bits;

sys/arch/octeon/include/octeonvar.h

55

#define __BITS64_GET(name, bits) \

sys/arch/octeon/include/octeonvar.h

56

(((uint64_t)(bits) & name) >> name##_SHIFT)

sys/arch/powerpc/include/pio.h

161

__flash_led(bits, count)

sys/arch/powerpc/include/pio.h

162

int bits;

sys/arch/powerpc/include/pio.h

166

if(bits == 0) {

sys/arch/powerpc/include/pio.h

167

v = 1; bits = 3;

sys/arch/powerpc/include/pio.h

169

bits &= 3;

sys/arch/powerpc/include/pio.h

173

v ^= bits;

sys/arch/powerpc/powerpc/pmap.c

1007

bits = pg->pg_flags & flagbit;

sys/arch/powerpc/powerpc/pmap.c

1018

bits |= pmap_pte2flags(ptp64->pte_lo & ptebit);

sys/arch/powerpc/powerpc/pmap.c

1029

bits |= pmap_pte2flags(ptp32->pte_lo & ptebit);

sys/arch/powerpc/powerpc/pmap.c

1047

bits |= pg->pg_flags & flagbit;

sys/arch/powerpc/powerpc/pmap.c

1050

return bits;

sys/arch/powerpc/powerpc/pmap.c

1096

u_int bits;

sys/arch/powerpc/powerpc/pmap.c

1117

bits = usedsr[tblidx];

sys/arch/powerpc/powerpc/pmap.c

1118

if ((bits & (1U << tbloff)) == 0) {

sys/arch/powerpc/powerpc/pmap.c

1119

if (atomic_cas_uint(&usedsr[tblidx], bits,

sys/arch/powerpc/powerpc/pmap.c

1120

bits | (1U << tbloff)) != bits) {

sys/arch/powerpc/powerpc/pmap.c

126

void pmap_attr_save(paddr_t pa, u_int32_t bits);

sys/arch/powerpc/powerpc/pmap.c

522

pmap_attr_save(paddr_t pa, u_int32_t bits)

sys/arch/powerpc/powerpc/pmap.c

530

atomic_setbits_int(&pg->pg_flags, pmap_pte2flags(bits));

sys/arch/powerpc/powerpc/pmap.c

958

u_int bits;

sys/arch/powerpc/powerpc/pmap.c

966

bits = pg->pg_flags & flagbit;

sys/arch/powerpc/powerpc/pmap.c

967

if (bits == flagbit)

sys/arch/powerpc/powerpc/pmap.c

968

return bits;

sys/arch/powerpc/powerpc/pmap.c

978

bits |= pmap_pte2flags(ptp64->pte_lo & ptebit);

sys/arch/powerpc/powerpc/pmap.c

981

bits |= pmap_pte2flags(ptp32->pte_lo & ptebit);

sys/arch/powerpc/powerpc/pmap.c

986

if (bits == flagbit)

sys/arch/powerpc/powerpc/pmap.c

991

atomic_setbits_int(&pg->pg_flags, bits);

sys/arch/powerpc/powerpc/pmap.c

993

return bits;

sys/arch/powerpc/powerpc/pmap.c

999

u_int bits;

sys/arch/powerpc64/powerpc64/pmap.c

387

uint32_t bits;

sys/arch/powerpc64/powerpc64/pmap.c

394

bits = pmap_vsid[vsid / 32];

sys/arch/powerpc64/powerpc64/pmap.c

395

} while (bits & (1U << bit));

sys/arch/powerpc64/powerpc64/pmap.c

397

if (atomic_cas_uint(&pmap_vsid[vsid / 32], bits,

sys/arch/powerpc64/powerpc64/pmap.c

398

bits | (1U << bit)) == bits)

sys/arch/powerpc64/powerpc64/pmap.c

406

uint32_t bits;

sys/arch/powerpc64/powerpc64/pmap.c

413

bits = pmap_vsid[vsid / 32];

sys/arch/powerpc64/powerpc64/pmap.c

414

if (atomic_cas_uint(&pmap_vsid[vsid / 32], bits,

sys/arch/powerpc64/powerpc64/pmap.c

415

bits & ~(1U << bit)) == bits)

sys/arch/riscv64/dev/sfgpio.c

57

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/sfgpio.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/sfgpio.c

59

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/sfgpio.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/sfuart.c

62

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/sfuart.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/sfuart.c

64

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/sfuart.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtclock.c

138

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/smtclock.c

139

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtclock.c

140

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/smtclock.c

141

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtgpio.c

40

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/smtgpio.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtgpio.c

42

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/smtgpio.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtiic.c

80

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/smtiic.c

81

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtiic.c

82

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/smtiic.c

83

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfclock.c

1123

uint32_t bits, offset;

sys/arch/riscv64/dev/stfclock.c

1126

bits = 1U << (idx % 32);

sys/arch/riscv64/dev/stfclock.c

1129

HSET4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

1131

HCLR4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

183

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/stfclock.c

184

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/stfclock.c

185

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/stfclock.c

186

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfclock.c

632

uint32_t bits, offset;

sys/arch/riscv64/dev/stfclock.c

635

bits = 1U << (idx % 32);

sys/arch/riscv64/dev/stfclock.c

638

HSET4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

640

HCLR4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

847

uint32_t bits, offset;

sys/arch/riscv64/dev/stfclock.c

850

bits = 1U << (idx % 32);

sys/arch/riscv64/dev/stfclock.c

853

HSET4(sc, offset, bits);

sys/arch/riscv64/dev/stfclock.c

855

HCLR4(sc, offset, bits);

sys/arch/riscv64/dev/stfpciephy.c

38

#define HSET4(sc, reg, bits) \

sys/arch/riscv64/dev/stfpciephy.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/stfpciephy.c

40

#define HCLR4(sc, reg, bits) \

sys/arch/riscv64/dev/stfpciephy.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/sh/sh/cache_sh3.c

136

cache_sh3_op_line_16_nway(int n, vaddr_t va, uint32_t bits)

sys/arch/sh/sh/cache_sh3.c

147

_reg_bclr_4(cca, bits);

sys/arch/sh/sh/cache_sh3.c

158

cache_sh3_op_8lines_16_nway(int n, vaddr_t va, uint32_t bits)

sys/arch/sh/sh/cache_sh3.c

170

cca[ 0] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

171

cca[ 4] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

172

cca[ 8] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

173

cca[12] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

174

cca[16] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

175

cca[20] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

176

cca[24] &= ~bits;

sys/arch/sh/sh/cache_sh3.c

177

cca[28] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

184

cache_sh4_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)

sys/arch/sh/sh/cache_sh4.c

189

_reg_bclr_4(cca, bits);

sys/arch/sh/sh/cache_sh4.c

198

cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)

sys/arch/sh/sh/cache_sh4.c

203

cca[ 0] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

204

cca[ 8] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

205

cca[16] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

206

cca[24] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

207

cca[32] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

208

cca[40] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

209

cca[48] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

210

cca[56] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

351

uint32_t bits, uint32_t way_shift)

sys/arch/sh/sh/cache_sh4.c

360

_reg_bclr_4(cca, bits);

sys/arch/sh/sh/cache_sh4.c

363

_reg_bclr_4(cca, bits);

sys/arch/sh/sh/cache_sh4.c

373

uint32_t bits, uint32_t way_shift)

sys/arch/sh/sh/cache_sh4.c

382

cca[ 0] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

383

cca[ 8] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

384

cca[16] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

385

cca[24] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

386

cca[32] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

387

cca[40] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

388

cca[48] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

389

cca[56] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

392

cca[ 0] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

393

cca[ 8] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

394

cca[16] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

395

cca[24] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

396

cca[32] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

397

cca[40] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

398

cca[48] &= ~bits;

sys/arch/sh/sh/cache_sh4.c

399

cca[56] &= ~bits;

sys/arch/sparc64/dev/auxio.c

187

auxio_fd_control(u_int32_t bits)

sys/arch/sparc64/dev/auxio.c

200

auxio_flip(sc, AUXIO_LED_FLOPPY_MASK, bits);

sys/arch/sparc64/dev/ce4231.c

328

u_char bits;

sys/arch/sparc64/dev/ce4231.c

377

sc->sc_speed_bits = speed_table[selected].bits;

sys/arch/sparc64/dev/ce4231.c

440

int err, bits, enc = p->encoding;

sys/arch/sparc64/dev/ce4231.c

447

bits = FMT_ULAW >> 5;

sys/arch/sparc64/dev/ce4231.c

451

bits = FMT_ALAW >> 5;

sys/arch/sparc64/dev/ce4231.c

455

bits = FMT_TWOS_COMP >> 5;

sys/arch/sparc64/dev/ce4231.c

459

bits = FMT_TWOS_COMP_BE >> 5;

sys/arch/sparc64/dev/ce4231.c

464

bits = FMT_PCM8 >> 5;

sys/arch/sparc64/dev/ce4231.c

481

sc->sc_format_bits = bits;

sys/arch/sparc64/dev/psycho.c

797

u_int64_t afsr, afar, bits;

sys/arch/sparc64/dev/psycho.c

802

bits = afsr & (PSY_PCIAFSR_PMA | PSY_PCIAFSR_PTA | PSY_PCIAFSR_PTRY |

sys/arch/sparc64/dev/psycho.c

806

if (bits == 0)

sys/arch/sparc64/dev/psycho.c

817

psycho_psychoreg_write(sc, psy_pcictl[bus].pci_afsr, bits);

sys/arch/sparc64/dev/sab.c

897

sabtty_mdmctrl(struct sabtty_softc *sc, int bits, int how)

sys/arch/sparc64/dev/sab.c

905

bits = 0;

sys/arch/sparc64/dev/sab.c

907

bits |= TIOCM_CTS;

sys/arch/sparc64/dev/sab.c

909

bits |= TIOCM_CD;

sys/arch/sparc64/dev/sab.c

913

bits |= TIOCM_DTR;

sys/arch/sparc64/dev/sab.c

915

bits |= TIOCM_DSR;

sys/arch/sparc64/dev/sab.c

919

bits |= TIOCM_RTS;

sys/arch/sparc64/dev/sab.c

923

if (bits & TIOCM_RTS) {

sys/arch/sparc64/dev/sab.c

931

if (bits & TIOCM_DTR)

sys/arch/sparc64/dev/sab.c

938

if (bits & TIOCM_RTS) {

sys/arch/sparc64/dev/sab.c

944

if (bits & TIOCM_DTR) {

sys/arch/sparc64/dev/sab.c

951

if (bits & TIOCM_RTS) {

sys/arch/sparc64/dev/sab.c

956

if (bits & TIOCM_DTR) {

sys/arch/sparc64/dev/sab.c

964

return (bits);

sys/crypto/rijndael.c

1125

rijndael_set_key_enc_only(rijndael_ctx *ctx, const u_char *key, int bits)

sys/crypto/rijndael.c

1129

rounds = rijndaelKeySetupEnc(ctx->ek, key, bits);

sys/crypto/rijndael.c

1141

rijndael_set_key(rijndael_ctx *ctx, const u_char *key, int bits)

sys/crypto/rijndael.c

1145

rounds = rijndaelKeySetupEnc(ctx->ek, key, bits);

sys/crypto/rijndael.c

1148

if (rijndaelKeySetupDec(ctx->dk, key, bits) != rounds)

sys/crypto/sha1.c

27

#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))

sys/dev/acpi/dwgpio.c

47

#define HSET4(sc, reg, bits) \

sys/dev/acpi/dwgpio.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/acpi/dwgpio.c

49

#define HCLR4(sc, reg, bits) \

sys/dev/acpi/dwgpio.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/acpi/qcgpio.c

63

#define HSET4(sc, reg, bits) \

sys/dev/acpi/qcgpio.c

64

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/acpi/qcgpio.c

65

#define HCLR4(sc, reg, bits) \

sys/dev/acpi/qcgpio.c

66

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/acpi/qciic.c

188

qciic_wait(struct qciic_softc *sc, uint32_t bits)

sys/dev/acpi/qciic.c

195

if (stat & bits)

sys/dev/audio.c

1003

if (sc->bits == 8) {

sys/dev/audio.c

1006

} else if (sc->bits == 24) {

sys/dev/audio.c

1016

DEVNAME(sc), sc->hw_enc, sc->bits);

sys/dev/audio.c

1046

DEVNAME(sc), sc->sw_enc, sc->bits, sc->bps, sc->msb,

sys/dev/audio.c

1091

p->bits = sc->bits;

sys/dev/audio.c

1115

if (p->sig != ~0U || p->le != ~0U || p->bits != ~0U) {

sys/dev/audio.c

1118

sc->bits = 16;

sys/dev/audio.c

1125

if (p->bits != ~0U) {

sys/dev/audio.c

1126

sc->bits = p->bits;

sys/dev/audio.c

1127

sc->bps = sc->bits <= 8 ?

sys/dev/audio.c

1128

1 : (sc->bits <= 16 ? 2 : 4);

sys/dev/audio.c

1257

sc->bits = 16;

sys/dev/audio.c

128

unsigned int bits; /* bits per sample */

sys/dev/audio.c

443

s >>= 32 - sc->bits;

sys/dev/audio.c

647

p.precision = sc->bits;

sys/dev/audio.c

670

p.precision = sc->bits;

sys/dev/audio.c

888

DEVNAME(sc), sc->sw_enc, sc->bits, sc->bps, sc->msb,

sys/dev/audio.c

917

if (sc->bits < 8)

sys/dev/audio.c

918

sc->bits = 8;

sys/dev/audio.c

919

else if (sc->bits > 32)

sys/dev/audio.c

920

sc->bits = 32;

sys/dev/audio.c

934

p.precision = r.precision = sc->bits;

sys/dev/audio.c

960

sc->bits = p.precision;

sys/dev/audio.c

968

sc->bits = r.precision;

sys/dev/audio.c

974

if (sc->rate == 0 || sc->bps == 0 || sc->bits == 0) {

sys/dev/audio_if.h

43

#define AUDIO_BPS(bits) (bits) <= 8 ? 1 : ((bits) <= 16 ? 2 : 4)

sys/dev/fdt/amlclock.c

110

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlclock.c

111

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlclock.c

112

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlclock.c

113

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amldwusb.c

109

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amldwusb.c

110

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amldwusb.c

111

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amldwusb.c

112

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amliic.c

62

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amliic.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amliic.c

64

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amliic.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlmmc.c

112

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlmmc.c

113

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlmmc.c

114

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlmmc.c

115

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpciephy.c

49

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlpciephy.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpciephy.c

51

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlpciephy.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpwm.c

54

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlpwm.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpwm.c

56

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlpwm.c

57

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpwrc.c

51

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlpwrc.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpwrc.c

53

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlpwrc.c

54

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlreset.c

39

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlreset.c

40

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlreset.c

41

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlreset.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amltemp.c

52

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amltemp.c

53

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amltemp.c

54

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amltemp.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amluart.c

58

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amluart.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amluart.c

60

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amluart.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlusbphy.c

87

#define HSET4(sc, reg, bits) \

sys/dev/fdt/amlusbphy.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlusbphy.c

89

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/amlusbphy.c

90

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2711_pcie.c

160

#define HSET4(sc, reg, bits) \

sys/dev/fdt/bcm2711_pcie.c

161

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcm2711_pcie.c

162

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/bcm2711_pcie.c

163

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2835_dog.c

48

#define HSET4(sc, reg, bits) \

sys/dev/fdt/bcm2835_dog.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcm2835_dog.c

50

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/bcm2835_dog.c

51

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbgpio.c

45

#define HSET4(sc, reg, bits) \

sys/dev/fdt/bcmstbgpio.c

46

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbgpio.c

47

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/bcmstbgpio.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbintc.c

41

#define HSET4(sc, reg, bits) \

sys/dev/fdt/bcmstbintc.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbintc.c

43

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/bcmstbintc.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbrescal.c

41

#define HSET4(sc, reg, bits) \

sys/dev/fdt/bcmstbrescal.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbrescal.c

43

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/bcmstbrescal.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwdog.c

45

#define HSET4(sc, reg, bits) \

sys/dev/fdt/dwdog.c

46

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwdog.c

47

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/dwdog.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwmmc.c

160

#define HSET4(sc, reg, bits) \

sys/dev/fdt/dwmmc.c

161

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwmmc.c

162

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/dwmmc.c

163

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwpcie.c

194

#define HSET4(sc, reg, bits) \

sys/dev/fdt/dwpcie.c

195

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwpcie.c

196

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/dwpcie.c

197

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/if_fec.c

142

#define HSET4(sc, reg, bits) \

sys/dev/fdt/if_fec.c

143

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/if_fec.c

144

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/if_fec.c

145

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/if_mvpp.c

3529

mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t enable)

sys/dev/fdt/if_mvpp.c

3537

if (bits & BIT(i))

sys/dev/fdt/if_mvpp.c

3588

mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t mask)

sys/dev/fdt/if_mvpp.c

3596

if (bits & BIT(i))

sys/dev/fdt/if_mvpp.c

3614

mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t mask)

sys/dev/fdt/if_mvpp.c

3622

if (bits & BIT(i))

sys/dev/fdt/if_mvpp.c

3636

uint8_t bits;

sys/dev/fdt/if_mvpp.c

3641

bits = (pe->sram.byte[ai_off] >> ai_shift) |

sys/dev/fdt/if_mvpp.c

3644

return bits;

sys/dev/fdt/if_mvpp.c

3770

uint8_t bits;

sys/dev/fdt/if_mvpp.c

3779

bits = mvpp2_prs_sram_ai_get(&pe);

sys/dev/fdt/if_mvpp.c

3781

if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)

sys/dev/fdt/imxanatop.c

95

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxanatop.c

96

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxanatop.c

97

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxanatop.c

98

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxccm.c

180

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxccm.c

181

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxccm.c

182

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxccm.c

183

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxesdhc.c

224

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxesdhc.c

225

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxesdhc.c

226

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxesdhc.c

227

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxpwm.c

57

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxpwm.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxpwm.c

59

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxpwm.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxspi.c

125

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxspi.c

126

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxspi.c

127

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxspi.c

128

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxsrc.c

96

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxsrc.c

97

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxsrc.c

98

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxsrc.c

99

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxtmu.c

58

#define HSET4(sc, reg, bits) \

sys/dev/fdt/imxtmu.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxtmu.c

60

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/imxtmu.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvclock.c

35

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvclock.c

36

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvclock.c

37

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvclock.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvdog.c

40

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvdog.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvdog.c

42

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvdog.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvgpio.c

41

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvgpio.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvgpio.c

43

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvgpio.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mviic.c

88

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mviic.c

89

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mviic.c

90

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mviic.c

91

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvkpcie.c

131

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvkpcie.c

132

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvkpcie.c

133

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvkpcie.c

134

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvpinctrl.c

44

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvpinctrl.c

45

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvpinctrl.c

46

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvpinctrl.c

47

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvrng.c

52

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvrng.c

53

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvrng.c

54

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvrng.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvspi.c

85

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvspi.c

86

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvspi.c

87

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvspi.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvuart.c

64

#define HSET4(sc, reg, bits) \

sys/dev/fdt/mvuart.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvuart.c

66

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/mvuart.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/ociic.c

85

ociic_set(struct ociic_softc *sc, bus_size_t reg, uint8_t bits)

sys/dev/fdt/ociic.c

87

ociic_write(sc, reg, ociic_read(sc, reg) | bits);

sys/dev/fdt/ociic.c

91

ociic_clr(struct ociic_softc *sc, bus_size_t reg, uint8_t bits)

sys/dev/fdt/ociic.c

93

ociic_write(sc, reg, ociic_read(sc, reg) & ~bits);

sys/dev/fdt/pciecam.c

59

#define HSET4(sc, reg, bits) \

sys/dev/fdt/pciecam.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/pciecam.c

61

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/pciecam.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/plgpio.c

38

#define HSET1(sc, reg, bits) \

sys/dev/fdt/plgpio.c

39

HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))

sys/dev/fdt/plgpio.c

40

#define HCLR1(sc, reg, bits) \

sys/dev/fdt/plgpio.c

41

HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))

sys/dev/fdt/qcgpio_fdt.c

56

#define HSET4(sc, reg, bits) \

sys/dev/fdt/qcgpio_fdt.c

57

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcgpio_fdt.c

58

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/qcgpio_fdt.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qciic_fdt.c

143

qciic_fdt_wait(struct qciic_fdt_softc *sc, uint32_t bits)

sys/dev/fdt/qciic_fdt.c

150

if (stat & bits)

sys/dev/fdt/qcpdc.c

41

#define HSET4(sc, reg, bits) \

sys/dev/fdt/qcpdc.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcpdc.c

43

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/qcpdc.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qcspmi.c

105

#define HSET4(sc, obj, reg, bits) \

sys/dev/fdt/qcspmi.c

106

HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcspmi.c

107

#define HCLR4(sc, obj, reg, bits) \

sys/dev/fdt/qcspmi.c

108

HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkclock.c

261

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkclock.c

262

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkclock.c

263

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkclock.c

264

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkcomphy.c

107

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkcomphy.c

108

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkcomphy.c

109

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkcomphy.c

110

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkgpio.c

75

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkgpio.c

76

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkgpio.c

77

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkgpio.c

78

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiic.c

73

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkiic.c

74

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkiic.c

75

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkiic.c

76

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiis.c

135

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkiis.c

136

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkiis.c

137

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkiis.c

138

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkpinctrl.c

1184

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

1221

bits = (mux << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1222

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1228

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1229

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1236

bits = ((1 << (strength + 1)) - 1) << ((idx % 2) * 8);

sys/dev/fdt/rkpinctrl.c

1237

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1244

bits = schmitt << ((idx % 8) * 2);

sys/dev/fdt/rkpinctrl.c

1245

regmap_write_4(rm, ie_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1294

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

1355

bits = (mux << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1356

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1362

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1363

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1370

bits = (strength << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1371

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1378

bits = (schmitt << (idx % 8));

sys/dev/fdt/rkpinctrl.c

1379

regmap_write_4(rm, smt_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1503

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

1551

bits = (mux << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1552

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1557

bits = (mux << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1558

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1565

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

1566

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1573

bits = (strength << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

1574

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

1581

bits = (schmitt << (idx % 8));

sys/dev/fdt/rkpinctrl.c

1582

regmap_write_4(rm, smt_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

285

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

316

bits = (mux << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

319

bits = (mux << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

327

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

333

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

334

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

341

bits = (strength << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

342

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

428

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

451

bits = (mux << 12);

sys/dev/fdt/rkpinctrl.c

455

bits = mux;

sys/dev/fdt/rkpinctrl.c

458

bits = (mux << ((idx - 16) * 2));

sys/dev/fdt/rkpinctrl.c

461

bits = (mux << (((idx - 18) * 4) + 4));

sys/dev/fdt/rkpinctrl.c

465

bits = (mux << ((idx - 21) * 4));

sys/dev/fdt/rkpinctrl.c

468

bits = (mux << (((idx - 12) * 4) + 8));

sys/dev/fdt/rkpinctrl.c

471

bits = (mux << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

473

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

479

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

480

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

487

bits = (strength << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

488

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

574

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

597

bits = mux;

sys/dev/fdt/rkpinctrl.c

600

bits = (mux << ((idx - 16) * 3));

sys/dev/fdt/rkpinctrl.c

603

bits = (mux << ((idx - 21) * 3));

sys/dev/fdt/rkpinctrl.c

606

bits = (mux << (idx * 3));

sys/dev/fdt/rkpinctrl.c

609

bits = (mux << ((idx - 5) * 3));

sys/dev/fdt/rkpinctrl.c

612

bits = (mux << ((idx - 8) * 3));

sys/dev/fdt/rkpinctrl.c

615

bits = (mux << ((idx - 13) * 3));

sys/dev/fdt/rkpinctrl.c

618

bits = (mux << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

628

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

634

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

635

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

642

bits = (strength << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

643

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

764

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

792

bits = (mux << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

793

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

799

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

800

regmap_write_4(rm, base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

809

bits = (strength << ((idx % 8) * shift));

sys/dev/fdt/rkpinctrl.c

812

mask << 16 | (bits & 0x0000ffff));

sys/dev/fdt/rkpinctrl.c

816

(mask & 0xffff0000) | bits >> 16);

sys/dev/fdt/rkpinctrl.c

909

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

961

bits = (mux << ((idx % 4) * 4));

sys/dev/fdt/rkpinctrl.c

962

regmap_write_4(rm, iomux_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

968

bits = (pull << ((idx % 8) * 2));

sys/dev/fdt/rkpinctrl.c

969

regmap_write_4(rm, p_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

976

bits = ((1 << (strength + 1)) - 1) << ((idx % 2) * 8);

sys/dev/fdt/rkpinctrl.c

977

regmap_write_4(rm, ds_base + off, mask << 16 | bits);

sys/dev/fdt/rkpinctrl.c

984

bits = schmitt << (idx % 8);

sys/dev/fdt/rkpinctrl.c

985

regmap_write_4(rm, st_base + off, mask << 16 | bits);

sys/dev/fdt/rkpwm.c

48

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkpwm.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkpwm.c

50

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkpwm.c

51

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkspi.c

122

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkspi.c

123

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkspi.c

124

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkspi.c

125

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rktcphy.c

108

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rktcphy.c

109

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rktcphy.c

110

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rktcphy.c

111

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkusbdpphy.c

55

#define HSET4(sc, reg, bits) \

sys/dev/fdt/rkusbdpphy.c

56

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkusbdpphy.c

57

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/rkusbdpphy.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sunxireg.h

22

#define SXISET1(sc, reg, bits) \

sys/dev/fdt/sunxireg.h

23

SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) | (bits))

sys/dev/fdt/sunxireg.h

24

#define SXICLR1(sc, reg, bits) \

sys/dev/fdt/sunxireg.h

25

SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) & ~(bits))

sys/dev/fdt/sunxireg.h

26

#define SXICMS1(sc, reg, mask, bits) \

sys/dev/fdt/sunxireg.h

27

SXIWRITE1((sc), (reg), (SXIREAD1((sc), (reg)) & ~(mask)) | (bits))

sys/dev/fdt/sunxireg.h

33

#define SXISET4(sc, reg, bits) \

sys/dev/fdt/sunxireg.h

34

SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sunxireg.h

35

#define SXICLR4(sc, reg, bits) \

sys/dev/fdt/sunxireg.h

36

SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sunxireg.h

37

#define SXICMS4(sc, reg, mask, bits) \

sys/dev/fdt/sunxireg.h

38

SXIWRITE4((sc), (reg), (SXIREAD4((sc), (reg)) & ~(mask)) | (bits))

sys/dev/fdt/sxirintc.c

36

#define HSET4(sc, reg, bits) \

sys/dev/fdt/sxirintc.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sxirintc.c

38

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/sxirintc.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sxirsb.c

64

#define HSET4(sc, reg, bits) \

sys/dev/fdt/sxirsb.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sxirsb.c

66

#define HCLR4(sc, reg, bits) \

sys/dev/fdt/sxirsb.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/gpio/gpioiic.c

267

gpioiic_bb_set_bits(void *cookie, u_int32_t bits)

sys/dev/gpio/gpioiic.c

272

bits & GPIOIIC_SDA ? GPIO_PIN_HIGH : GPIO_PIN_LOW);

sys/dev/gpio/gpioiic.c

274

bits & GPIOIIC_SCL ? GPIO_PIN_HIGH : GPIO_PIN_LOW);

sys/dev/gpio/gpioiic.c

278

gpioiic_bb_set_dir(void *cookie, u_int32_t bits)

sys/dev/gpio/gpioiic.c

284

sda |= (bits & GPIOIIC_SDA ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT);

sys/dev/gpio/gpioiic.c

285

if ((sda & GPIO_PIN_PUSHPULL) && !(bits & GPIOIIC_SDA))

sys/dev/gpio/gpioiic.c

298

u_int32_t bits = 0;

sys/dev/gpio/gpioiic.c

302

bits |= GPIOIIC_SDA;

sys/dev/gpio/gpioiic.c

305

bits |= GPIOIIC_SCL;

sys/dev/gpio/gpioiic.c

307

return bits;

sys/dev/ic/ac97.c

1026

dip->un.v.delta = 1 << (8 - si->bits);

sys/dev/ic/ac97.c

1060

mask = (1 << si->bits) - 1;

sys/dev/ic/ac97.c

1110

l >>= 8 - si->bits;

sys/dev/ic/ac97.c

1111

r >>= 8 - si->bits;

sys/dev/ic/ac97.c

132

u_int8_t bits:3;

sys/dev/ic/ac97.c

1335

mask = (1 << si->bits) - 1;

sys/dev/ic/ac97.c

1364

l <<= 8 - si->bits;

sys/dev/ic/ac97.c

1365

r <<= 8 - si->bits;

sys/dev/ic/ac97.c

703

si->bits = 1;

sys/dev/ic/ar5210.c

1913

u_int32_t bits;

sys/dev/ic/ar5210.c

1916

bits = AR5K_AR5210_DIAG_SW_DIS_ENC | AR5K_AR5210_DIAG_SW_DIS_DEC;

sys/dev/ic/ar5210.c

1919

AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, bits);

sys/dev/ic/ar5210.c

1922

AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, bits);

sys/dev/ic/ar5211.c

2024

u_int32_t bits;

sys/dev/ic/ar5211.c

2027

bits = AR5K_AR5211_DIAG_SW_DIS_ENC | AR5K_AR5211_DIAG_SW_DIS_DEC;

sys/dev/ic/ar5211.c

2030

AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, bits);

sys/dev/ic/ar5211.c

2033

AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, bits);

sys/dev/ic/ar5212.c

2387

u_int32_t bits;

sys/dev/ic/ar5212.c

2390

bits = AR5K_AR5212_DIAG_SW_DIS_ENC | AR5K_AR5212_DIAG_SW_DIS_DEC;

sys/dev/ic/ar5212.c

2393

AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, bits);

sys/dev/ic/ar5212.c

2396

AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, bits);

sys/dev/ic/ar5xxx.c

1271

ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits,

sys/dev/ic/ar5xxx.c

1283

if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {

sys/dev/ic/ar5xxx.c

1292

data = ar5k_bitswap(reg, bits);

sys/dev/ic/ar5xxx.c

1294

for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {

sys/dev/ic/ar5xxx.c

1312

data = set == AH_TRUE ? 1 : ar5k_bitswap(data, bits);

sys/dev/ic/ar5xxx.c

603

ar5k_bitswap(u_int32_t val, u_int bits)

sys/dev/ic/ar5xxx.c

605

if (bits == 8) {

sys/dev/ic/ar5xxx.c

614

for (i = 0; i < bits; i++) {

sys/dev/ic/atw.c

1916

uint32_t bits, mask, reg;

sys/dev/ic/atw.c

1924

bits = val | (addr << 18);

sys/dev/ic/atw.c

1931

bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |

sys/dev/ic/atw.c

1943

if ((bits & mask) != 0)

sys/dev/ic/atw.c

2923

atw_idle(struct atw_softc *sc, u_int32_t bits)

sys/dev/ic/atw.c

2930

opmode = sc->sc_opmode & ~bits;

sys/dev/ic/atw.c

2932

if (bits & ATW_NAR_SR)

sys/dev/ic/atw.c

2935

if (bits & ATW_NAR_ST) {

sys/dev/ic/atw.c

2958

if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 &&

sys/dev/ic/atw.c

2964

sc->sc_dev.dv_xname, bits, test0, stsr));

sys/dev/ic/atw.c

2967

if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 &&

sys/dev/ic/atw.c

2973

sc->sc_dev.dv_xname, bits, test0, stsr));

sys/dev/ic/atw.c

2976

if ((bits & ATW_NAR_ST) != 0)

sys/dev/ic/bwi.c

1922

uint32_t filt, bits;

sys/dev/ic/bwi.c

1931

bits = 0xf;

sys/dev/ic/bwi.c

1934

bits |= 0x60;

sys/dev/ic/bwi.c

1939

bits |= 0x200;

sys/dev/ic/bwi.c

1947

CSR_FILT_SETBITS_4(sc, BWI_GPIO_CTRL, filt, bits);

sys/dev/ic/bwivar.h

642

#define MOBJ_SETBITS_4(mac, objid, ofs, bits) \

sys/dev/ic/bwivar.h

644

MOBJ_READ_4((mac), (objid), (ofs)) | (bits))

sys/dev/ic/bwivar.h

645

#define MOBJ_CLRBITS_4(mac, objid, ofs, bits) \

sys/dev/ic/bwivar.h

647

MOBJ_READ_4((mac), (objid), (ofs)) & ~(bits))

sys/dev/ic/bwivar.h

649

#define MOBJ_FILT_SETBITS_2(mac, objid, ofs, filt, bits) \

sys/dev/ic/bwivar.h

651

(MOBJ_READ_2((mac), (objid), (ofs)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

657

#define HFLAGS_CLRBITS(mac, bits) \

sys/dev/ic/bwivar.h

658

HFLAGS_WRITE((mac), HFLAGS_READ((mac)) | (bits))

sys/dev/ic/bwivar.h

659

#define HFLAGS_SETBITS(mac, bits) \

sys/dev/ic/bwivar.h

660

HFLAGS_WRITE((mac), HFLAGS_READ((mac)) & ~(bits))

sys/dev/ic/bwivar.h

679

#define PHY_SETBITS(mac, ctrl, bits) \

sys/dev/ic/bwivar.h

680

PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) | (bits))

sys/dev/ic/bwivar.h

681

#define PHY_CLRBITS(mac, ctrl, bits) \

sys/dev/ic/bwivar.h

682

PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) & ~(bits))

sys/dev/ic/bwivar.h

683

#define PHY_FILT_SETBITS(mac, ctrl, filt, bits) \

sys/dev/ic/bwivar.h

684

PHY_WRITE((mac), (ctrl), (PHY_READ((mac), (ctrl)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

734

#define RF_SETBITS(mac, ofs, bits) \

sys/dev/ic/bwivar.h

735

RF_WRITE((mac), (ofs), RF_READ((mac), (ofs)) | (bits))

sys/dev/ic/bwivar.h

736

#define RF_CLRBITS(mac, ofs, bits) \

sys/dev/ic/bwivar.h

737

RF_WRITE((mac), (ofs), RF_READ((mac), (ofs)) & ~(bits))

sys/dev/ic/bwivar.h

738

#define RF_FILT_SETBITS(mac, ofs, filt, bits) \

sys/dev/ic/bwivar.h

739

RF_WRITE((mac), (ofs), (RF_READ((mac), (ofs)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

84

#define CSR_SETBITS_4(sc, reg, bits) \

sys/dev/ic/bwivar.h

85

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))

sys/dev/ic/bwivar.h

86

#define CSR_SETBITS_2(sc, reg, bits) \

sys/dev/ic/bwivar.h

87

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

sys/dev/ic/bwivar.h

89

#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \

sys/dev/ic/bwivar.h

90

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

91

#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \

sys/dev/ic/bwivar.h

92

CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

94

#define CSR_CLRBITS_4(sc, reg, bits) \

sys/dev/ic/bwivar.h

95

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

sys/dev/ic/bwivar.h

96

#define CSR_CLRBITS_2(sc, reg, bits) \

sys/dev/ic/bwivar.h

97

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

sys/dev/ic/cissreg.h

232

u_int8_t bits;

sys/dev/ic/com.c

712

int bits = 0;

sys/dev/ic/com.c

716

SET(bits, TIOCM_DTR);

sys/dev/ic/com.c

718

SET(bits, TIOCM_RTS);

sys/dev/ic/com.c

721

SET(bits, TIOCM_CD);

sys/dev/ic/com.c

723

SET(bits, TIOCM_CTS);

sys/dev/ic/com.c

725

SET(bits, TIOCM_DSR);

sys/dev/ic/com.c

727

SET(bits, TIOCM_RI);

sys/dev/ic/com.c

729

SET(bits, TIOCM_LE);

sys/dev/ic/com.c

730

*(int *)data = bits;

sys/dev/ic/cy.c

785

cy_modem_control(struct cy_port *cy, int bits, int howto)

sys/dev/ic/cy.c

797

bits = 0;

sys/dev/ic/cy.c

799

bits |= TIOCM_LE;

sys/dev/ic/cy.c

803

bits |= TIOCM_DTR;

sys/dev/ic/cy.c

805

bits |= TIOCM_RTS;

sys/dev/ic/cy.c

808

bits |= TIOCM_RTS;

sys/dev/ic/cy.c

810

bits |= TIOCM_DTR;

sys/dev/ic/cy.c

813

bits |= TIOCM_CTS;

sys/dev/ic/cy.c

815

bits |= TIOCM_CD;

sys/dev/ic/cy.c

818

bits |= TIOCM_DSR;

sys/dev/ic/cy.c

821

bits |= TIOCM_RI;

sys/dev/ic/cy.c

823

return (bits);

sys/dev/ic/cy.c

829

((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0));

sys/dev/ic/cy.c

831

((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0));

sys/dev/ic/cy.c

835

((bits & TIOCM_RTS) ? CD1400_MSVR1_RTS : 0));

sys/dev/ic/cy.c

837

((bits & TIOCM_DTR) ? CD1400_MSVR2_DTR : 0));

sys/dev/ic/cy.c

844

(bits & TIOCM_RTS) != 0)

sys/dev/ic/cy.c

846

if (bits & TIOCM_DTR)

sys/dev/ic/cy.c

850

(bits & TIOCM_RTS) != 0)

sys/dev/ic/cy.c

852

if (bits & TIOCM_DTR)

sys/dev/ic/cy.c

860

(bits & TIOCM_RTS))

sys/dev/ic/cy.c

862

if (bits & TIOCM_DTR)

sys/dev/ic/cy.c

866

(bits & TIOCM_RTS))

sys/dev/ic/cy.c

868

if (bits & TIOCM_DTR)

sys/dev/ic/dc.c

1494

dc_read_srom(struct dc_softc *sc, int bits)

sys/dev/ic/dc.c

1496

sc->dc_sromsize = 2 << bits;

sys/dev/ic/dc.c

511

dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)

sys/dev/ic/dc.c

516

dc_mii_writebit(sc, bits & i);

sys/dev/ic/imxiic.c

66

#define HSET1(sc, reg, bits) \

sys/dev/ic/imxiic.c

67

HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))

sys/dev/ic/imxiic.c

68

#define HCLR1(sc, reg, bits) \

sys/dev/ic/imxiic.c

69

HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))

sys/dev/ic/iosf.c

149

uint32_t offset, uint32_t bits, uint32_t mask)

sys/dev/ic/iosf.c

160

SET(mdr, bits & mask);

sys/dev/ic/iosf.c

205

uint32_t bits, uint32_t mask)

sys/dev/ic/iosf.c

215

iosf_mbi_mdr_modify(mbi, port, opcode, offset, bits, mask);

sys/dev/ic/lsi64854.c

377

char bits[64];

sys/dev/ic/lsi64854.c

388

snprintf(bits, sizeof(bits), "%b", csr, DDMACSR_BITS);

sys/dev/ic/lsi64854.c

389

printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits);

sys/dev/ic/lsi64854.c

501

char bits[64];

sys/dev/ic/lsi64854.c

512

snprintf(bits, sizeof(bits), "%b", csr, EDMACSR_BITS);

sys/dev/ic/lsi64854.c

513

printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits);

sys/dev/ic/qcuart.c

66

#define HSET4(sc, reg, bits) \

sys/dev/ic/qcuart.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/ic/qcuart.c

68

#define HCLR4(sc, reg, bits) \

sys/dev/ic/qcuart.c

69

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/ic/rtl81x9.c

282

rl_mii_send(struct rl_softc *sc, u_int32_t bits, int cnt)

sys/dev/ic/rtl81x9.c

289

if (bits & i)

sys/dev/ic/rtsx.c

87

#define RTSX_CLR(sc, reg, bits) \

sys/dev/ic/rtsx.c

89

int err = rtsx_write((sc), (reg), (bits), 0); \

sys/dev/ic/rtsx.c

94

#define RTSX_SET(sc, reg, bits) \

sys/dev/ic/rtsx.c

96

int err = rtsx_write((sc), (reg), (bits), 0xff);\

sys/dev/ic/rtw.c

4732

rtw_rf_hostbangbits(struct rtw_regs *regs, u_int32_t bits, int lo_to_hi,

sys/dev/ic/rtw.c

4741

("%s: %u bits, %#08x, %s\n", __func__, nbits, bits,

sys/dev/ic/rtw.c

4756

__func__, bits, mask, bits & mask));

sys/dev/ic/rtw.c

4758

if ((bits & mask) != 0)

sys/dev/ic/rtw.c

4787

rtw_rf_rtl8225_hostbangbits(struct rtw_regs *regs, u_int32_t bits, int lo_to_hi,

sys/dev/ic/rtw.c

4821

__func__, bits, mask, bits & mask));

sys/dev/ic/rtw.c

4823

if ((bits & mask) != 0)

sys/dev/ic/rtw.c

4914

u_int32_t bits;

sys/dev/ic/rtw.c

4925

bits = LSHIFT(val, MAX2820_TWI_DATA_MASK) |

sys/dev/ic/rtw.c

4931

bits = LSHIFT(val, SA2400_TWI_DATA_MASK) |

sys/dev/ic/rtw.c

4939

bits = rtw_grf5101_host_crypt(addr, val);

sys/dev/ic/rtw.c

4946

bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |

sys/dev/ic/rtw.c

4955

bits = LSHIFT(val, RTL8225_TWI_DATA_MASK) |

sys/dev/ic/rtw.c

4967

(*rf_bangbits)(&sc->sc_regs, bits, lo_to_hi, nbits);

sys/dev/ic/smc93cx6.c

118

if (seeprom_read.bits[i] != 0)

sys/dev/ic/smc93cx6.c

124

if (seeprom_read.bits[i] != 0)

sys/dev/ic/smc93cx6.c

72

unsigned char bits[3];

sys/dev/ic/wdc.c

1088

wdc_wait_for_status(struct channel_softc *chp, int mask, int bits, int timeout)

sys/dev/ic/wdc.c

1111

if ((status & WDCS_BSY) == 0 && (status & mask) == bits)

sys/dev/ic/xl.c

274

xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)

sys/dev/ic/xl.c

282

if (bits & i) {

sys/dev/ipmi.c

1107

ipmi_sensor_name(char *name, int len, u_int8_t typelen, u_int8_t *bits,

sys/dev/ipmi.c

1126

*(name++) = bcdplus[bits[i] >> 4];

sys/dev/ipmi.c

1127

*(name++) = bcdplus[bits[i] & 0xF];

sys/dev/ipmi.c

1140

*(name++) = getbits(bits, i, 6) + ' ';

sys/dev/ipmi.c

1151

*(name++) = *(bits++);

sys/dev/ipmi.c

1178

signextend(unsigned long val, int bits)

sys/dev/ipmi.c

1180

long msk = (1L << (bits-1))-1;

sys/dev/isa/ad1848.c

1215

u_char bits;

sys/dev/isa/ad1848.c

1267

sc->speed_bits = speed_table[selected].bits;

sys/dev/isa/ad1848.c

914

int error, bits, enc;

sys/dev/isa/ad1848.c

941

bits = FMT_ULAW;

sys/dev/isa/ad1848.c

945

bits = FMT_ALAW;

sys/dev/isa/ad1848.c

949

bits = FMT_TWOS_COMP;

sys/dev/isa/ad1848.c

955

bits = FMT_TWOS_COMP_BE;

sys/dev/isa/ad1848.c

961

bits = FMT_PCM8;

sys/dev/isa/ad1848.c

981

sc->format_bits = bits;

sys/dev/isa/ad1848.c

986

DPRINTF(("ad1848_set_params succeeded, bits=%x\n", bits));

sys/dev/isa/ast.c

181

int bits;

sys/dev/isa/ast.c

183

bits = ~bus_space_read_1(iot, sc->sc_slaveioh[3], 7) & alive;

sys/dev/isa/ast.c

184

if (bits == 0)

sys/dev/isa/ast.c

189

if (bits & (1 << (n))) \

sys/dev/isa/ast.c

196

bits = ~bus_space_read_1(iot, sc->sc_slaveioh[3], 7) & alive;

sys/dev/isa/ast.c

197

if (bits == 0)

sys/dev/isa/boca.c

178

int bits;

sys/dev/isa/boca.c

180

bits = bus_space_read_1(iot, sc->sc_slaveioh[0], 7) & alive;

sys/dev/isa/boca.c

181

if (bits == 0)

sys/dev/isa/boca.c

186

if (bits & (1 << (n))) \

sys/dev/isa/boca.c

197

bits = bus_space_read_1(iot, sc->sc_slaveioh[0], 7) & alive;

sys/dev/isa/boca.c

198

if (bits == 0)

sys/dev/isa/gscsio.c

257

gscsio_acb_wait(struct gscsio_acb *acb, int bits, int flags)

sys/dev/isa/gscsio.c

279

if ((st & bits) == bits)

sys/dev/isa/gscsio.c

283

if ((st & bits) != bits) {

sys/dev/isa/hsq.c

225

int bits;

sys/dev/isa/hsq.c

227

bits = bus_space_read_1(iot, sc->sc_slaveioh[0], com_uir) & UART_MASK;

sys/dev/isa/hsq.c

228

if ( !bits )

sys/dev/isa/hsq.c

233

if ( sc->sc_slaves[n] && bits & (1 << (n)) ) \

sys/dev/isa/hsq.c

242

bits = bus_space_read_1(iot, sc->sc_slaveioh[0],

sys/dev/isa/hsq.c

244

if ( !bits )

sys/dev/isa/isapnp.c

234

if (i->bits == 0) {

sys/dev/isa/isapnp.c

239

if (isa_intr_alloc(ic, i->bits, i->type, &irq) == 0) {

sys/dev/isa/isapnp.c

256

if (i->bits == 0) {

sys/dev/isa/isapnp.c

262

if ((i->bits & (1 << b)) && isa_drq_isfree(isa, b)) {

sys/dev/isa/isapnpdebug.c

104

if (irq->bits & (1 << i))

sys/dev/isa/isapnpdebug.c

129

if (drq->bits & (1 << i))

sys/dev/isa/isapnpres.c

315

p->bits = buf[0] | (buf[1] << 8);

sys/dev/isa/isapnpres.c

327

p->bits = buf[0];

sys/dev/isa/isavar.h

210

u_int16_t bits;

sys/dev/isa/sbdsp.c

1493

int mask, bits;

sys/dev/isa/sbdsp.c

1616

bits = sbdsp_mix_read(sc, SB16P_OSWITCH);

sys/dev/isa/sbdsp.c

1619

bits = bits & ~mask;

sys/dev/isa/sbdsp.c

1621

bits = bits | mask;

sys/dev/isa/sbdsp.c

1622

sbdsp_mix_write(sc, SB16P_OSWITCH, bits);

sys/dev/ofw/ofw_misc.c

573

uint32_t reg[2], bits[2] = {};

sys/dev/ofw/ofw_misc.c

582

OF_getpropintarray(node, "bits", bits, sizeof(bits));

sys/dev/ofw/ofw_misc.c

589

nc->nc_offset = bits[0];

sys/dev/ofw/ofw_misc.c

590

nc->nc_bitlen = bits[1];

sys/dev/pci/azalia.c

3364

int length, nconn, bits, conn, last;

sys/dev/pci/azalia.c

3375

bits = 8;

sys/dev/pci/azalia.c

3377

bits = 16;

sys/dev/pci/azalia.c

3395

for (k = 0; i < length && (k < 32 / bits); k++) {

sys/dev/pci/azalia.c

3396

conn = (result >> (k * bits)) & ((1 << bits) - 1);

sys/dev/pci/azalia.c

3400

if ((nconn > 0) && (conn & (1 << (bits - 1))))

sys/dev/pci/azalia.c

3401

nconn += (conn & ~(1 << (bits - 1))) - last;

sys/dev/pci/azalia.c

3419

for (k = 0; i < nconn && (k < 32 / bits); k++) {

sys/dev/pci/azalia.c

3420

conn = (result >> (k * bits)) & ((1 << bits) - 1);

sys/dev/pci/azalia.c

3424

if ((i > 0) && (conn & (1 << (bits - 1)))) {

sys/dev/pci/azalia_codec.c

1148

bits = (1 << CORB_PWC_VREF_GND);

sys/dev/pci/azalia_codec.c

1153

bits = (1 << CORB_PWC_VREF_50);

sys/dev/pci/azalia_codec.c

1158

bits = (1 << CORB_PWC_VREF_80);

sys/dev/pci/azalia_codec.c

1163

bits = (1 << CORB_PWC_VREF_100);

sys/dev/pci/azalia_codec.c

1169

bits) == bits) {

sys/dev/pci/azalia_codec.c

2589

int bits, offset;

sys/dev/pci/azalia_codec.c

2593

bits = CORB_CD_DEVICE_BITS;

sys/dev/pci/azalia_codec.c

2597

bits = CORB_CD_PORT_BITS;

sys/dev/pci/azalia_codec.c

2603

val &= bits;

sys/dev/pci/azalia_codec.c

848

int err, i, j, k, bits;

sys/dev/pci/cmpci.c

1233

int bits, mask;

sys/dev/pci/cmpci.c

1311

bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX);

sys/dev/pci/cmpci.c

1313

bits = bits & ~mask;

sys/dev/pci/cmpci.c

1315

bits = bits | mask;

sys/dev/pci/cmpci.c

1316

cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits);

sys/dev/pci/com_pci.c

36

#define HSET4(sc, reg, bits) \

sys/dev/pci/com_pci.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/pci/com_pci.c

38

#define HCLR4(sc, reg, bits) \

sys/dev/pci/com_pci.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/pci/cs4281reg.h

273

Logical Size: 256 x 32 bits (1 kbytes stereo double words)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

181

amdgpu_bb_set_bits(void *cookie, uint32_t bits)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

183

amdgpu_i2c_set_clock(cookie, bits & AMDGPU_BB_SCL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

184

amdgpu_i2c_set_data(cookie, bits & AMDGPU_BB_SDA);

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

188

amdgpu_bb_set_dir(void *cookie, uint32_t bits)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

195

uint32_t bits = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

198

bits |= AMDGPU_BB_SCL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

200

bits |= AMDGPU_BB_SDA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

202

return bits;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

63

int amdgpu_pasid_alloc(unsigned int bits)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

67

if (bits == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

75

1U << bits, GFP_ATOMIC);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

73

int amdgpu_pasid_alloc(unsigned int bits);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1207

if (adev->virt.ras_en_caps.bits.block_umc)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1209

if (adev->virt.ras_en_caps.bits.block_sdma)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1211

if (adev->virt.ras_en_caps.bits.block_gfx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1213

if (adev->virt.ras_en_caps.bits.block_mmhub)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1215

if (adev->virt.ras_en_caps.bits.block_athub)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1217

if (adev->virt.ras_en_caps.bits.block_pcie_bif)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1219

if (adev->virt.ras_en_caps.bits.block_hdp)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1221

if (adev->virt.ras_en_caps.bits.block_xgmi_wafl)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1223

if (adev->virt.ras_en_caps.bits.block_df)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1225

if (adev->virt.ras_en_caps.bits.block_smn)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1227

if (adev->virt.ras_en_caps.bits.block_sem)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1229

if (adev->virt.ras_en_caps.bits.block_mp0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1231

if (adev->virt.ras_en_caps.bits.block_mp1)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1233

if (adev->virt.ras_en_caps.bits.block_fuse)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1235

if (adev->virt.ras_en_caps.bits.block_mca)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1237

if (adev->virt.ras_en_caps.bits.block_vcn)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1239

if (adev->virt.ras_en_caps.bits.block_jpeg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1241

if (adev->virt.ras_en_caps.bits.block_ih)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1243

if (adev->virt.ras_en_caps.bits.block_mpio)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1246

if (adev->virt.ras_en_caps.bits.poison_propogation_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2387

unsigned bits = ilog2(vm_size) + 18;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2392

return (bits - 9);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2394

return ((bits + 3) / 2);

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

145

} bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1038

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1048

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1051

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1056

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

1059

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1223

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1234

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1238

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1244

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1248

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1393

u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1405

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1409

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1415

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1419

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

417

u32 bits, i, tmp, reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

425

bits = 0x7f;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

432

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

438

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

446

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

452

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

469

u32 tmp, reg, bits, i, j;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

471

bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

499

tmp &= ~bits;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

527

tmp |= bits;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

654

misc_pkt.change_config.option.bits.limit_single_process =

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

693

misc_pkt.change_config.option.bits.limit_single_process =

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

834

reg_gfx_index.bits.sh_broadcast_writes = 1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

835

reg_gfx_index.bits.se_broadcast_writes = 1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

836

reg_gfx_index.bits.instance_broadcast_writes = 1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

837

reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

838

reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

839

reg_sq_cmd.bits.vm_id = vmid;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

60

} bitfields, bits;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

75

} bitfields, bits;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

158

struct kfd_process *p, uint32_t id, uint32_t bits)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

168

if (bits > 31 || (1U << bits) >= KFD_SIGNAL_EVENT_LIMIT) {

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

178

for (ev = NULL; id < KFD_SIGNAL_EVENT_LIMIT && !ev; id += 1U << bits) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11910

dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1371

hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1596

if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1597

offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1606

if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1616

test_response.bits.ACK = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1788

reg.bits.status = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1789

reg.bits.command_code = command_code;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1790

reg.bits.param = param;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1798

reg.bits.status = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1976

init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1978

init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2059

adev->dm.dc->debug.fams2_config.bits.enable = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3691

if (caps->ext_caps->bits.oled == 1

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4131

if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4137

if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4138

hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4219

if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7338

stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9623

attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

736

lut->state.bits.initialized = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

743

lut->state.bits.initialized = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1068

if (!test_request.bits.EDID_READ)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1071

test_response.bits.EDID_CHECKSUM_WRITE = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1202

new_downspread.bits.IGNORE_MSA_TIMING_PARAM =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1244

switch (dpcd_test_pattern.bits.PATTERN) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1252

test_pattern = (dpcd_test_params.bits.DYN_RANGE ==

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1262

if (dpcd_test_params.bits.CLR_FORMAT == 0)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1265

test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1269

switch (dpcd_test_params.bits.BPC) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1286

switch (dpcd_test_params.bits.CLR_FORMAT) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1396

if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1819

dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1851

*cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

246

link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1391

attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

46

if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

47

!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

50

if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

58

if (!dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

62

if (!as_caps->dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

106

} bits;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

504

msg_data.bits.hr_id = hr_id;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

505

msg_data.bits.bw_mbps = bw_kbps / 1000;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1968

if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1973

if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2203

uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2206

context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2533

if (dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2657

update_flags->bits.color_space_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2662

update_flags->bits.horizontal_mirror_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2667

update_flags->bits.rotation_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2672

update_flags->bits.pixel_format_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2677

update_flags->bits.stereo_format_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2682

update_flags->bits.per_pixel_alpha_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2687

update_flags->bits.global_alpha_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2699

update_flags->bits.dcc_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2708

update_flags->bits.bpp_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2714

update_flags->bits.plane_size_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2721

update_flags->bits.swizzle_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2731

update_flags->bits.bandwidth_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2757

update_flags->bits.scaling_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2762

update_flags->bits.clock_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2769

update_flags->bits.bandwidth_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2775

update_flags->bits.bandwidth_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2784

update_flags->bits.position_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2787

if (update_flags->bits.clock_change

sys/dev/pci/drm/amd/display/dc/core/dc.c

2788

|| update_flags->bits.bandwidth_change

sys/dev/pci/drm/amd/display/dc/core/dc.c

2789

|| update_flags->bits.scaling_change)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2792

if (update_flags->bits.position_change)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2820

update_flags->bits.addr_update = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2822

update_flags->bits.tmz_changed = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2827

update_flags->bits.in_transfer_func_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2830

update_flags->bits.input_csc_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2833

update_flags->bits.coeff_reduction_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2836

update_flags->bits.gamut_remap_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2839

update_flags->bits.gamma_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2850

update_flags->bits.gamma_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2854

update_flags->bits.lut_3d = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2858

update_flags->bits.hdr_mult = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2864

update_flags->bits.sdr_white_level_nits = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2873

update_flags->bits.mcm_transfer_function_enable_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2876

update_flags->bits.mcm_transfer_function_enable_change = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2878

if (update_flags->bits.in_transfer_func_change) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2883

if (update_flags->bits.lut_3d &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2888

if (update_flags->bits.mcm_transfer_function_enable_change) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2894

(update_flags->bits.gamma_change ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2895

update_flags->bits.gamut_remap_change ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2896

update_flags->bits.input_csc_change ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2897

update_flags->bits.coeff_reduction_change)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2922

updates[i].surface->update_flags.bits.addr_update = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2958

su_flags->bits.scaling = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2961

su_flags->bits.out_tf = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2964

su_flags->bits.abm_level = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2967

su_flags->bits.dpms_off = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2970

su_flags->bits.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2973

su_flags->bits.wb_update = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2976

su_flags->bits.dsc_changed = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2979

su_flags->bits.mst_bw = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2984

su_flags->bits.fams_changed = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2987

su_flags->bits.scaler_sharpener = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2990

su_flags->bits.sharpening_required = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2993

su_flags->bits.out_csc = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2999

su_flags->bits.out_csc = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3005

su_flags->bits.out_tf = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3041

uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3043

stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3553

if (surface->update_flags.bits.position_change) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3866

addr_only_update_flags.bits.addr_update = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3868

return update_flags.bits.addr_update &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

3928

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3958

if (dc->debug.fams2_config.bits.enable &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

3959

dc->debug.fams2_config.bits.enable_offload_flip &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4149

if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4156

hw_locks.bits.lock_dig = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4397

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4409

if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4426

hw_locks.bits.lock_dig = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4488

!pipe_ctx->plane_state->update_flags.bits.addr_update ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

5820

!dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5826

if (!dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

711

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

799

if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

815

if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

823

if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

828

if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

833

if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

839

if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

854

if (current_mpc_pipe->stream->update_flags.bits.out_csc) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

912

current_mpc_pipe->plane_state->update_flags.bits.addr_update &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4427

hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4430

hdmi_info.bits.header.version = 2;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4431

hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4457

hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4460

hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4463

hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4465

hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4470

hdmi_info.bits.S0_S1 = scan_type;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4476

hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4480

hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4485

hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4486

hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4489

hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4490

hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4494

hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4500

hdmi_info.bits.EC0_EC2 = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4501

hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4510

hdmi_info.bits.M0_M1 = aspect;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4517

hdmi_info.bits.M0_M1 = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4521

hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4525

hdmi_info.bits.CN0_CN1 = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4526

hdmi_info.bits.ITC = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4529

hdmi_info.bits.CN0_CN1 = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4530

hdmi_info.bits.ITC = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4533

hdmi_info.bits.CN0_CN1 = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4534

hdmi_info.bits.ITC = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4537

hdmi_info.bits.CN0_CN1 = 2;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4538

hdmi_info.bits.ITC = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4541

hdmi_info.bits.CN0_CN1 = 3;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4542

hdmi_info.bits.ITC = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4549

hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4552

hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4554

hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4556

hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4560

hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4587

hdmi_info.bits.VIC0_VIC7 = vic;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4589

hdmi_info.bits.header.version = 3;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4593

if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4594

hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4595

hdmi_info.bits.header.version = 4;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4596

hdmi_info.bits.header.length = 14;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4600

hdmi_info.bits.header.version = 4;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4601

hdmi_info.bits.header.length = 15;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4603

hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4604

hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4605

hdmi_info.bits.RID0_RID5 = rid;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4611

hdmi_info.bits.PR0_PR3 = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4618

hdmi_info.bits.bar_top = stream->timing.v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4619

hdmi_info.bits.bar_bottom = (stream->timing.v_total

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4621

hdmi_info.bits.bar_left = stream->timing.h_border_left;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4622

hdmi_info.bits.bar_right = (stream->timing.h_total

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4630

hdmi_info.bits.ACE0_ACE3 = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4635

*check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4637

for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

980

is_fams2_in_use |= state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

983

is_fams2_in_use |= dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

140

if (pipe_ctx->plane_state && flags.bits.address)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

155

if (flags.bits.address)

sys/dev/pci/drm/amd/display/dc/dc.h

1322

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

1411

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

476

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

771

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

788

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

809

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

854

} bits;

sys/dev/pci/drm/amd/display/dc/dc.h

870

} bits;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

148

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1046

payload->enable = hubp->pos.cur_ctl.bits.cur_enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1257

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1258

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1264

new_signals.bits.allow_idle = 1; /* always set */

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1268

new_signals.bits.allow_pg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1269

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1270

new_signals.bits.allow_ips2 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1271

new_signals.bits.allow_z10 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1273

new_signals.bits.allow_ips1z8 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1275

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1278

new_signals.bits.allow_pg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1279

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1282

new_signals.bits.allow_pg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1283

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1284

new_signals.bits.allow_ips2 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1289

new_signals.bits.allow_pg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1290

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1291

new_signals.bits.allow_ips2 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1292

new_signals.bits.allow_z10 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1294

new_signals.bits.allow_ips1z8 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1297

new_signals.bits.allow_pg = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1298

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1299

new_signals.bits.allow_ips2 = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1300

new_signals.bits.allow_z10 = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1303

new_signals.bits.allow_pg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1304

new_signals.bits.allow_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1305

new_signals.bits.allow_ips2 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1306

new_signals.bits.allow_z10 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1310

new_signals.bits.allow_ips0_rcg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1311

new_signals.bits.allow_ips1_rcg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1313

new_signals.bits.allow_ips1_rcg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1315

new_signals.bits.allow_ips0_rcg = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1319

new_signals.bits.allow_dynamic_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1321

new_signals.bits.allow_dynamic_ips1 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1322

new_signals.bits.allow_dynamic_ips1_z8 = 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1332

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1333

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1375

ips_driver->signals.bits.allow_ips1,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1376

ips_driver->signals.bits.allow_ips2,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1377

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1378

ips_fw->signals.bits.ips2_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1379

ips_fw->signals.bits.ips1z8_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1390

if (!dc->caps.ips_v2_support && ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1392

ips_fw->signals.bits.ips2_commit || !ips_fw->signals.bits.in_idle))) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1395

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1396

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1398

if (!dc->debug.optimize_ips_handshake || !ips_fw->signals.bits.ips2_commit)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1403

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1404

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1409

if (ips_fw->signals.bits.ips2_commit) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1413

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1414

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1421

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1422

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1428

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1429

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1431

while (ips_fw->signals.bits.ips2_commit)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1436

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1437

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1444

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1445

ips_fw->signals.bits.ips2_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1452

if (prev_driver_signals.bits.allow_ips1 || prev_driver_signals.all == 0) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1455

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1456

ips_fw->signals.bits.ips2_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1457

ips_fw->signals.bits.ips1z8_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1459

while (ips_fw->signals.bits.ips1_commit)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1464

ips_fw->signals.bits.ips1_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1465

ips_fw->signals.bits.ips2_commit,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1466

ips_fw->signals.bits.ips1z8_commit);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1531

dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1533

return ips_fw->signals.bits.detection_required;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1712

global_cmd->config.global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1713

global_cmd->config.global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1714

global_cmd->config.global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1744

global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1745

global_cmd->config.global.features.bits.enable = enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1747

if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1774

if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1776

config->global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1777

config->global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1778

config->global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1798

config->global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1799

config->global.features.bits.enable = enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1881

cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

330

return boot_status.bits.optimized_init_done;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

362

return boot_status.bits.restore_required;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1007

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1017

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1026

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1036

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1051

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1059

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1067

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1077

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1117

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1128

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1140

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1302

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1324

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1334

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1345

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1356

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1364

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1374

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1382

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

212

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

220

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

230

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

240

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

248

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

258

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

272

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

286

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

295

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

309

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

322

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

331

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

364

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

378

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

399

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

420

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

432

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

446

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

455

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

467

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

495

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

505

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

540

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

561

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

571

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

650

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

664

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

672

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

686

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

696

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

705

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

714

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

723

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

737

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

745

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

753

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

786

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

925

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

943

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

952

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

961

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

970

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

989

} bits;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

997

} bits;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

592

} bits;

sys/dev/pci/drm/amd/display/dc/dc_plane.h

34

} bits;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

149

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1006

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1101

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1119

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

649

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

835

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

845

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

857

} bits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

868

} bits;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

123

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

133

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

185

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

194

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

203

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

212

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

238

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

247

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

256

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

265

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

334

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

358

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

402

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

457

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

464

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

474

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

481

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

491

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

498

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

508

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

515

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

525

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

532

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

678

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

685

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

299

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

303

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

308

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1188

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

141

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1460

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1466

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1472

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1478

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1499

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1505

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1511

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1517

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1539

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1704

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1715

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1726

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1737

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

174

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1766

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1779

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1859

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1867

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1875

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1883

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1902

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1908

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1914

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1920

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1926

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1936

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1943

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1950

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1957

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1964

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

213

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

240

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

277

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

326

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

371

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

397

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

430

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

467

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

282

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

289

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

299

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

306

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

316

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

323

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

333

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

340

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

391

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

400

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

409

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

418

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

444

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

453

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

462

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

471

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

489

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

498

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

507

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

516

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

528

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

542

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

550

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

558

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

566

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

708

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

715

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

722

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

810

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

817

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

824

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

831

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

239

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

240

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

241

masterCmdData1.bits.rfb_update_auto_en =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

243

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

244

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

245

masterCmdData1.bits.phy_type = psr_context->phyType;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

246

masterCmdData1.bits.frame_cap_ind =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

248

masterCmdData1.bits.aux_chan = psr_context->channel;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

249

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

254

masterCmdData2.bits.dig_fe = psr_context->engineId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

255

masterCmdData2.bits.dig_be = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

256

masterCmdData2.bits.skip_wait_for_pll_lock =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

258

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

259

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

260

masterCmdData2.bits.num_of_controllers =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

266

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

313

masterCmdData1.bits.wait_loop = wait_loop_number;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

399

if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) {

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

677

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

678

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

679

masterCmdData1.bits.rfb_update_auto_en =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

681

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

682

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

683

masterCmdData1.bits.phy_type = psr_context->phyType;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

684

masterCmdData1.bits.frame_cap_ind =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

686

masterCmdData1.bits.aux_chan = psr_context->channel;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

687

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

688

masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

693

masterCmdData2.bits.dig_fe = psr_context->engineId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

694

masterCmdData2.bits.dig_be = psr_context->transmitterId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

695

masterCmdData2.bits.skip_wait_for_pll_lock =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

697

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

698

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

699

masterCmdData2.bits.num_of_controllers =

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

705

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

739

masterCmdData1.bits.wait_loop = wait_loop_number;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

265

} bits;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

281

} bits;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

293

} bits;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

301

} bits;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

327

if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

436

if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

98

CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

99

CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1346

training_lane_set.bits.VOLTAGE_SWING_SET =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1348

training_lane_set.bits.PRE_EMPHASIS_SET =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1356

training_lane_set.bits.POST_CURSOR2_SET =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1673

if (enc->features.flags.bits.IS_HBR2_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1676

if (enc->features.flags.bits.IS_HBR3_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1795

enc110->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1802

enc110->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1804

enc110->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1806

enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1813

enc110->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

787

if ((!enc110->base.features.flags.bits.HDMI_6GB_EN ||

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

893

enc110->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

900

enc110->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

902

enc110->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

904

enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

911

enc110->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

396

if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

180

if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

149

if (compressor->options.bits.CLK_GATING_DISABLED == 1) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

191

if (compressor->options.bits.FBC_SUPPORT &&

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

243

if (compressor->options.bits.FBC_SUPPORT) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

427

compressor->base.options.bits.FBC_SUPPORT = true;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

431

compressor->base.options.bits.DUMMY_BACKEND = false;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

439

compressor->base.options.bits.CLK_GATING_DISABLED = false;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

109

if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

326

if (compressor->options.bits.CLK_GATING_DISABLED == 1) {

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

369

if (compressor->options.bits.FBC_SUPPORT &&

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

370

(compressor->options.bits.DUMMY_BACKEND == 0) &&

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

383

if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

418

if (compressor->options.bits.FBC_SUPPORT &&

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

432

if (compressor->options.bits.LPT_SUPPORT)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

497

if (compressor->options.bits.LPT_SUPPORT) {

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

664

if (!compressor->options.bits.LPT_SUPPORT)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

794

compressor->base.options.bits.FBC_SUPPORT = true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

795

compressor->base.options.bits.LPT_SUPPORT = true;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

798

compressor->base.options.bits.DUMMY_BACKEND = false;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

803

compressor->base.options.bits.LPT_SUPPORT = false;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

805

compressor->base.options.bits.CLK_GATING_DISABLED = false;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

186

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

193

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

195

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

197

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

198

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

206

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

210

if (enc->features.flags.bits.DP_IS_USB_C) {

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

244

if (enc->features.flags.bits.DP_IS_USB_C) {

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

421

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

428

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

430

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

432

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

433

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

441

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

61

if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

71

if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

56

if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

70

if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false &&

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1124

training_lane_set.bits.VOLTAGE_SWING_SET =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1126

training_lane_set.bits.PRE_EMPHASIS_SET =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1134

training_lane_set.bits.POST_CURSOR2_SET =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1458

if (enc->features.flags.bits.IS_HBR2_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1461

if (enc->features.flags.bits.IS_HBR3_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1464

if (enc->features.flags.bits.IS_UHBR10_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1467

if (enc->features.flags.bits.IS_UHBR13_5_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1470

if (enc->features.flags.bits.IS_UHBR20_CAPABLE)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

645

if ((!enc10->base.features.flags.bits.HDMI_6GB_EN ||

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

757

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

764

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

766

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

768

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

769

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

777

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

291

if (enc->features.flags.bits.DP_IS_USB_C) {

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

480

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

487

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

489

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

491

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

492

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

500

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

180

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

187

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

189

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

191

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

192

enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

193

enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

194

enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

195

enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

196

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

204

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

169

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

176

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

178

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

180

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

181

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c

189

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

369

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

376

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

378

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

380

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

381

enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

382

enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

383

enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

384

enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

385

enc10->base.features.flags.bits.DP_IS_USB_C =

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

393

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

599

if (!enc->features.flags.bits.DP_IS_USB_C)

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

645

if (!enc->features.flags.bits.DP_IS_USB_C)

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

312

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

320

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

322

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

324

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

325

enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

326

enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

327

enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

328

enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

335

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

117

enc10->base.features.flags.bits.DP_IS_USB_C = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

166

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

174

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

176

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

178

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

179

enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

180

enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

181

enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

182

enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c

189

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

123

dcn35_link_encoder_set_fgcg(enc, enc->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dio);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

194

enc10->base.features.flags.bits.DP_IS_USB_C = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

244

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

252

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

254

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

256

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

257

enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

258

enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

259

enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

260

enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

268

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

247

enc10->base.features.flags.bits.DP_IS_USB_C = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

297

enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

305

enc10->base.features.flags.bits.IS_HBR2_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

307

enc10->base.features.flags.bits.IS_HBR3_CAPABLE =

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

309

enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

310

enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

311

enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

312

enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

313

enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

320

enc10->base.features.flags.bits.HDMI_6GB_EN = 0;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1237

pipe->plane_state->update_flags.bits.full_update = 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

17

bool disable_fams2 = !in_dc->debug.fams2_config.bits.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

510

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12735

fams2_global_config->features.bits.enable = display_cfg->stage3.fams2_required;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12737

if (fams2_global_config->features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12738

fams2_global_config->features.bits.enable_stall_recovery = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12739

fams2_global_config->features.bits.allow_delay_check_mode = FAMS2_ALLOW_DELAY_CHECK_FROM_START;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12779

base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12794

base_programming->config.bits.min_ttu_vblank_usable = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12799

base_programming->config.bits.min_ttu_vblank_usable = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12815

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12825

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12839

base_programming->config.bits.clamp_vtotal_min = display_cfg->display_config.num_streams == 1;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12857

sub_programming->subvp.config.bits.is_multi_planar =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12859

sub_programming->subvp.config.bits.is_yuv420 =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12868

base_programming->config.bits.clamp_vtotal_min = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

486

if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

489

dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

529

dpp_base->pos.cur0_ctl.bits.cur0_enable = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

168

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

170

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

630

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

659

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

349

if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1207

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1401

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

394

if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

412

dpp_base->att.cur0_ctl.bits.expansion_mode = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

413

dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

414

dpp_base->att.cur0_ctl.bits.mode = color_format;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

525

if (dpp_base->deferred_reg_writes.bits.disable_dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

527

dpp_base->deferred_reg_writes.bits.disable_dscl = false;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

530

if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

536

dpp_base->deferred_reg_writes.bits.disable_gamcor = false;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

539

if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

545

dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

548

if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

554

dpp_base->deferred_reg_writes.bits.disable_3dlut = false;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

557

if (dpp_base->deferred_reg_writes.bits.disable_shaper) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

563

dpp_base->deferred_reg_writes.bits.disable_shaper = false;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

573

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

579

dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

590

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

596

dpp_base->deferred_reg_writes.bits.disable_3dlut = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

607

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

613

dpp_base->deferred_reg_writes.bits.disable_shaper = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

132

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

138

dpp_base->deferred_reg_writes.bits.disable_gamcor = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

227

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

101

if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

119

dpp_base->att.cur0_ctl.bits.expansion_mode = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

120

dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

121

dpp_base->att.cur0_ctl.bits.mode = color_format;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

134

if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

137

dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1104

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1133

if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

160

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

162

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1093

is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.RGB;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1098

is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_444;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1103

is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1107

is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1113

is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_420;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1131

is_dsc_possible = (bool)dsc_common_caps.color_depth.bits.COLOR_DEPTH_8_BPC;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1134

is_dsc_possible = (bool)dsc_common_caps.color_depth.bits.COLOR_DEPTH_10_BPC;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1137

is_dsc_possible = (bool)dsc_common_caps.color_depth.bits.COLOR_DEPTH_12_BPC;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1216

if (dsc_common_caps.slice_caps.bits.NUM_SLICES_12)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

551

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

554

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

557

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

560

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

566

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

572

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

575

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

578

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_3;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

581

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

685

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

706

dsc_common_caps->slice_caps.bits.NUM_SLICES_1 =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

707

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_1 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

708

dsc_common_caps->slice_caps.bits.NUM_SLICES_2 =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

709

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_2 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

710

dsc_common_caps->slice_caps.bits.NUM_SLICES_4 =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

711

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

712

dsc_common_caps->slice_caps.bits.NUM_SLICES_8 =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

713

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

714

dsc_common_caps->slice_caps.bits.NUM_SLICES_12 =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

715

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_12 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_12;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

716

dsc_common_caps->slice_caps.bits.NUM_SLICES_16 =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

717

dsc_sink_caps->slice_caps2.bits.NUM_SLICES_16 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_16;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

738

if (dsc_common_caps->slice_caps.bits.NUM_SLICES_1)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

741

if (dsc_common_caps->slice_caps.bits.NUM_SLICES_2)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

744

if (dsc_common_caps->slice_caps.bits.NUM_SLICES_4)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

894

if (slice_caps.bits.NUM_SLICES_1)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

897

if (slice_caps.bits.NUM_SLICES_2)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

900

if (slice_caps.bits.NUM_SLICES_4)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

903

if (slice_caps.bits.NUM_SLICES_8)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

906

if (slice_caps.bits.NUM_SLICES_12)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

909

if (slice_caps.bits.NUM_SLICES_16)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

100

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

101

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

102

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

103

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

105

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

106

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

107

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

120

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

121

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

129

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

130

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

91

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

92

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

93

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

94

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

99

dsc_enc_caps->color_formats.bits.RGB = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

69

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

70

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

71

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

72

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

77

dsc_enc_caps->color_formats.bits.RGB = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

78

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

79

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

80

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

81

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

83

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

84

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

85

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

81

} bits;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

531

.bits.dchubbub);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1061

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1081

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1082

hubp->pos.position.bits.x_pos = pos->x;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1083

hubp->pos.position.bits.y_pos = pos->y;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1084

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1085

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1086

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

627

CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

639

hubp->att.size.bits.width = attr->width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

640

hubp->att.size.bits.height = attr->height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

641

hubp->att.cur_ctl.bits.mode = attr->color_format;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

646

hubp->att.cur_ctl.bits.pitch = hw_pitch;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

647

hubp->att.cur_ctl.bits.line_per_chunk = lpc;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

648

hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

649

hubp->att.settings.bits.dst_y_offset = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

650

hubp->att.settings.bits.chunk_hdl_adjust = 3;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

135

CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

52

hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

770

(1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

782

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

802

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

803

hubp->pos.position.bits.x_pos = pos->x;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

804

hubp->pos.position.bits.y_pos = pos->y;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

805

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

806

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

807

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1043

if (enable && link->dpcd_sink_ext_caps.bits.oled &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1050

if (link->dpcd_sink_ext_caps.bits.oled ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1051

link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1052

link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2980

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2981

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2982

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2985

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

956

unsigned int pre_T11_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

957

unsigned int post_T7_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

965

if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

966

link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

967

link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

335

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

336

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

337

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

340

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2252

hw_locks.bits.lock_cursor = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2934

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2994

if (plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3049

if (plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3066

if (plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3067

plane_state->update_flags.bits.bpp_change)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3070

if (plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3071

plane_state->update_flags.bits.per_pixel_alpha_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3072

plane_state->update_flags.bits.global_alpha_change)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3075

if (plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3076

plane_state->update_flags.bits.per_pixel_alpha_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3077

plane_state->update_flags.bits.global_alpha_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3078

plane_state->update_flags.bits.scaling_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3079

plane_state->update_flags.bits.position_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3083

if (plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3084

plane_state->update_flags.bits.scaling_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3085

plane_state->update_flags.bits.position_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3100

if (plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3111

if (plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3112

plane_state->update_flags.bits.pixel_format_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3113

plane_state->update_flags.bits.horizontal_mirror_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3114

plane_state->update_flags.bits.rotation_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3115

plane_state->update_flags.bits.swizzle_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3116

plane_state->update_flags.bits.dcc_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3117

plane_state->update_flags.bits.bpp_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3118

plane_state->update_flags.bits.scaling_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3119

plane_state->update_flags.bits.plane_size_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3228

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3235

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3236

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3237

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3246

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3302

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3306

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1106

if (plane_state->lut3d_func.state.bits.initialized == 1)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1464

hw_locks.bits.lock_pipe = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1468

hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1510

new_pipe->update_flags.bits.disable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1517

new_pipe->update_flags.bits.odm = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1524

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1525

new_pipe->update_flags.bits.mpcc = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1526

new_pipe->update_flags.bits.dppclk = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1527

new_pipe->update_flags.bits.hubp_interdependent = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1528

new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1529

new_pipe->update_flags.bits.unbounded_req = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1530

new_pipe->update_flags.bits.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1531

new_pipe->update_flags.bits.scaler = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1532

new_pipe->update_flags.bits.viewport = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1533

new_pipe->update_flags.bits.det_size = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1537

new_pipe->update_flags.bits.test_pattern_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1539

new_pipe->update_flags.bits.odm = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1540

new_pipe->update_flags.bits.global_sync = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1551

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1558

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1561

new_pipe->update_flags.bits.disable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1567

new_pipe->update_flags.bits.plane_changed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1577

new_pipe->update_flags.bits.global_sync = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1581

new_pipe->update_flags.bits.det_size = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1591

new_pipe->update_flags.bits.opp_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1593

new_pipe->update_flags.bits.tg_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1602

new_pipe->update_flags.bits.mpcc = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1606

new_pipe->update_flags.bits.dppclk = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1610

new_pipe->update_flags.bits.scaler = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1615

new_pipe->update_flags.bits.viewport = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1661

new_pipe->update_flags.bits.hubp_interdependent = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1667

new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1671

new_pipe->update_flags.bits.unbounded_req = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1675

new_pipe->update_flags.bits.test_pattern_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1692

if (pipe_ctx->update_flags.bits.dppclk)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1695

if (pipe_ctx->update_flags.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1703

if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1722

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1725

if (pipe_ctx->update_flags.bits.hubp_interdependent) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1738

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1739

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1740

plane_state->update_flags.bits.bpp_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1741

plane_state->update_flags.bits.input_csc_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1742

plane_state->update_flags.bits.color_space_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1743

plane_state->update_flags.bits.coeff_reduction_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1765

if (pipe_ctx->update_flags.bits.mpcc

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1766

|| pipe_ctx->update_flags.bits.plane_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1767

|| plane_state->update_flags.bits.global_alpha_change

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1768

|| plane_state->update_flags.bits.per_pixel_alpha_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1773

if (pipe_ctx->update_flags.bits.scaler ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1774

plane_state->update_flags.bits.scaling_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1775

plane_state->update_flags.bits.position_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1776

plane_state->update_flags.bits.per_pixel_alpha_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1777

pipe_ctx->stream->update_flags.bits.scaling) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1785

if (pipe_ctx->update_flags.bits.viewport ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1786

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1787

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1788

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1801

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1802

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1813

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1814

|| pipe_ctx->update_flags.bits.plane_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1815

|| pipe_ctx->stream->update_flags.bits.gamut_remap

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1816

|| plane_state->update_flags.bits.gamut_remap_change

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1817

|| pipe_ctx->stream->update_flags.bits.out_csc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1829

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1830

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1831

pipe_ctx->update_flags.bits.opp_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1832

plane_state->update_flags.bits.pixel_format_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1833

plane_state->update_flags.bits.horizontal_mirror_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1834

plane_state->update_flags.bits.rotation_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1835

plane_state->update_flags.bits.swizzle_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1836

plane_state->update_flags.bits.dcc_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1837

plane_state->update_flags.bits.bpp_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1838

plane_state->update_flags.bits.scaling_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1839

plane_state->update_flags.bits.plane_size_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1855

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1856

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1857

plane_state->update_flags.bits.addr_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1870

if (pipe_ctx->update_flags.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1936

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1937

pipe_ctx->update_flags.bits.odm ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1938

pipe_ctx->stream->update_flags.bits.abm_level)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1945

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1949

if (pipe_ctx->update_flags.bits.odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1952

if (pipe_ctx->update_flags.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1962

if (pipe_ctx->update_flags.bits.det_size) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1977

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1978

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1982

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1983

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1984

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1985

pipe_ctx->update_flags.bits.enable))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1992

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1993

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1994

pipe_ctx->stream->update_flags.bits.out_tf)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2002

if (pipe_ctx->update_flags.bits.enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2003

|| pipe_ctx->update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2026

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2099

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2113

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2121

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2122

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2131

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2152

pipe->update_flags.bits.odm &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2261

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2273

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2985

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2986

!pipe_ctx->update_flags.bits.mpcc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

485

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

277

stream->lut3d_func->state.bits.initialized == 1 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

278

stream->lut3d_func->state.bits.rmu_idx_valid == 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

279

if (stream->lut3d_func->state.bits.rmu_mux_num == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

280

mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

281

else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

282

mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

283

else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

284

mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

291

stream->lut3d_func->state.bits.rmu_mux_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

292

if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

296

stream->lut3d_func->state.bits.rmu_mux_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

301

stream->lut3d_func->state.bits.rmu_mux_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

661

if (dc->debug.enable_mem_low_power.bits.dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

669

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

674

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

243

if (dc->debug.enable_mem_low_power.bits.i2c)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

293

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

336

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

75

if (dc->debug.enable_mem_low_power.bits.dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

83

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

88

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

93

if (dc->debug.enable_mem_low_power.bits.mpc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

98

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

236

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

287

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

457

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1002

dc->debug.fams2_config.bits.enable = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1440

if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1448

phantom_pipe->plane_state->update_flags.bits.position_change = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1465

phantom_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1466

phantom_pipe->update_flags.bits.mpcc = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1467

phantom_pipe->update_flags.bits.dppclk = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1468

phantom_pipe->update_flags.bits.hubp_interdependent = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1469

phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1470

phantom_pipe->update_flags.bits.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1471

phantom_pipe->update_flags.bits.scaler = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1472

phantom_pipe->update_flags.bits.viewport = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1473

phantom_pipe->update_flags.bits.det_size = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1475

phantom_pipe->update_flags.bits.odm = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1476

phantom_pipe->update_flags.bits.global_sync = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

413

hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

414

hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

415

hw_lock_cmd.bits.lock = lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

416

hw_lock_cmd.bits.should_release = !lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

431

hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

432

hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

433

hw_lock_cmd.bits.lock = lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

434

hw_lock_cmd.bits.should_release = !lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

462

stream->lut3d_func->state.bits.initialized == 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

514

if (plane_state->lut3d_func.state.bits.initialized == 1)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

802

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

807

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

dc->debug.fams2_config.bits.enable &= true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

103

if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

278

if (dc->debug.enable_mem_low_power.bits.i2c)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

482

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

493

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpstream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

504

if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

81

if (dc->debug.enable_mem_low_power.bits.dmcu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

89

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

94

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

99

if (dc->debug.enable_mem_low_power.bits.mpc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1171

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1192

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1356

pipe_ctx->plane_state->update_flags.bits.addr_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1415

if (dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1436

if (dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1485

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1488

hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1489

hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1490

hw_lock_cmd.bits.lock = lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1491

hw_lock_cmd.bits.should_release = !lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1503

hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1504

hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1505

hw_lock_cmd.bits.lock = lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1506

hw_lock_cmd.bits.should_release = !lock;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1515

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1518

fams2_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1637

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1645

dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1659

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

166

if (dc->debug.enable_mem_low_power.bits.optc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

171

if (dc->debug.enable_mem_low_power.bits.vga) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1991

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1992

pipe_ctx->update_flags.bits.odm ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1993

pipe_ctx->stream->update_flags.bits.abm_level)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2000

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2004

if (pipe_ctx->update_flags.bits.odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2007

if (pipe_ctx->update_flags.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2017

if (pipe_ctx->update_flags.bits.det_size) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2031

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2032

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2036

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2037

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2038

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2039

pipe_ctx->update_flags.bits.enable))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2046

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2047

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2048

pipe_ctx->stream->update_flags.bits.out_tf)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2056

if (pipe_ctx->update_flags.bits.enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2057

|| pipe_ctx->update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2080

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2155

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2169

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2178

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2179

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2188

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2209

pipe->update_flags.bits.odm &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2283

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2295

if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2480

new_pipe->update_flags.bits.disable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2487

new_pipe->update_flags.bits.odm = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2494

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2495

new_pipe->update_flags.bits.mpcc = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2496

new_pipe->update_flags.bits.dppclk = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2497

new_pipe->update_flags.bits.hubp_interdependent = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2498

new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2499

new_pipe->update_flags.bits.unbounded_req = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2500

new_pipe->update_flags.bits.gamut_remap = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2501

new_pipe->update_flags.bits.scaler = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2502

new_pipe->update_flags.bits.viewport = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2503

new_pipe->update_flags.bits.det_size = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2507

new_pipe->update_flags.bits.test_pattern_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2509

new_pipe->update_flags.bits.odm = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2510

new_pipe->update_flags.bits.global_sync = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2521

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2528

new_pipe->update_flags.bits.enable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2531

new_pipe->update_flags.bits.disable = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2537

new_pipe->update_flags.bits.plane_changed = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2546

new_pipe->update_flags.bits.global_sync = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2550

new_pipe->update_flags.bits.det_size = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2560

new_pipe->update_flags.bits.opp_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2562

new_pipe->update_flags.bits.tg_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2571

new_pipe->update_flags.bits.mpcc = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2575

new_pipe->update_flags.bits.dppclk = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2579

new_pipe->update_flags.bits.scaler = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2584

new_pipe->update_flags.bits.viewport = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2631

new_pipe->update_flags.bits.hubp_interdependent = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2637

new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2641

new_pipe->update_flags.bits.unbounded_req = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2645

new_pipe->update_flags.bits.test_pattern_changed = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

360

dc->debug.fams2_config.bits.enable &=

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

476

if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

655

if (plane_state->lut3d_func.state.bits.initialized == 1)

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

133

} bits;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

95

} bits;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

420

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

86

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

19

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

28

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

35

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

42

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

55

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

63

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

83

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

65

} bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

67

} bits;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

215

channel_count = min(dpcd_test_mode.bits.channel_count + 1, AUDIO_CHANNELS_COUNT);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

234

switch (dpcd_test_mode.bits.sampling_rate) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

269

link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

334

switch (dpcd_test_pattern.bits.PATTERN) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

445

(dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

448

(dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

593

if (test_request.bits.LINK_TRAINING) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

595

test_response.bits.ACK = 1;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

603

test_response.bits.ACK = 0;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

605

if (test_request.bits.LINK_TEST_PATTRN) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

623

test_response.bits.ACK = dm_helpers_dp_handle_test_pattern_request(link->ctx, link,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

627

if (test_request.bits.AUDIO_TEST_PATTERN) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

628

dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

629

test_response.bits.ACK = 1;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

632

if (test_request.bits.PHY_TEST_PATTERN) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

634

test_response.bits.ACK = 1;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

638

if (test_response.bits.ACK)

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

884

hw_locks.bits.lock_dig = 1;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

932

hw_locks.bits.lock_dig = 1;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

130

link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

83

if (!link->dpcd_caps.lttpr_caps.main_link_channel_coding.bits.DP_128b_132b_SUPPORTED)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

129

if (!link->dpcd_caps.lttpr_caps.main_link_channel_coding.bits.DP_128b_132b_SUPPORTED)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1014

if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1015

&& link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1016

&& link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1018

link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1031

if (link->dpcd_caps.sink_count.bits.SINK_COUNT)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1033

link->dpcd_caps.sink_count.bits.SINK_COUNT;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1333

ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1357

ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

544

lane_count_set.bits.LANE_COUNT_SET;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

582

max_down_spread.bits.MAX_DOWN_SPREAD ?

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

607

link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

700

!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

708

!link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

899

(link->dpcd_sink_ext_caps.bits.oled == 1)) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

979

link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

995

link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1064

new_downspread.bits.IGNORE_MSA_TIMING_PARAM =

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1233

if (update_status.bits.ACT_HANDLED == 1) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1584

update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1621

if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2143

if (link->dpcd_sink_ext_caps.bits.oled == 1 ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2144

link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2145

link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2148

if (link->dpcd_sink_ext_caps.bits.oled == 1)

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

632

DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);

sys/dev/pci/drm/amd/display/dc/link/link_factory.c

633

DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

148

if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

285

!link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

306

bool is_max_uncompressed_pixel_rate_exceeded = link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

307

timing->pix_clk_100hz > link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1106

autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1120

(!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1121

!hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1175

switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1205

hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1207

if (port_caps->bits.DWN_STRM_PORTX_TYPE

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1210

hdmi_caps.bits.YCrCr422_PASS_THROUGH;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1212

hdmi_caps.bits.YCrCr420_PASS_THROUGH;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1214

hdmi_caps.bits.YCrCr422_CONVERSION;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1216

hdmi_caps.bits.YCrCr420_CONVERSION;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1221

hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1227

hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1358

down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1367

link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1371

link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1377

edp_config_cap.bits.ALT_SCRAMBLER_RESET;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1379

edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1469

if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1487

link->link_enc->features.flags.bits.DP_IS_USB_C == 0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1538

if (st == DC_OK && cap.bits.MST_CAP == 1)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1561

if (link->is_dds && !link->dpcd_sink_ext_caps.bits.oled) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1770

aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1772

if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1857

down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1866

link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1870

link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1876

edp_config_cap.bits.ALT_SCRAMBLER_RESET;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1878

edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1964

is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1996

link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2000

(link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2016

if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2024

if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2026

else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2028

else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2042

if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2044

if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2046

if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2050

link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2058

if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2156

if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2184

if (link->dpcd_sink_ext_caps.bits.emission_output)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2272

if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2297

if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2298

link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2316

if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2416

if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

243

out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

244

b->bits.UHBR10_20_CAPABILITY);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

245

out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

246

b->bits.UHBR13_5_CAPABILITY);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

247

out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2540

if (link->dpcd_caps.alpm_caps.bits.AUX_LESS_ALPM_CAP) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2542

if (link->dpcd_caps.lttpr_caps.alpm.bits.AUX_LESS_ALPM_SUPPORTED)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2548

if (link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

264

if (hdmi_encoded_link_bw.bits.BW_48Gbps)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

266

else if (hdmi_encoded_link_bw.bits.BW_40Gbps)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

268

else if (hdmi_encoded_link_bw.bits.BW_32Gbps)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

270

else if (hdmi_encoded_link_bw.bits.BW_24Gbps)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

272

else if (hdmi_encoded_link_bw.bits.BW_18Gbps)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

274

else if (hdmi_encoded_link_bw.bits.BW_9Gbps)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

276

else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

353

link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

441

if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

443

else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

445

else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

455

if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

457

} else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

459

} else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

461

if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

562

return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

616

link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

158

link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

160

if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

161

&& link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

164

dp_tunnel_setting->group_id = link->dpcd_caps.usb4_dp_tun_info.dpia_tunnel_info.bits.group_id;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

68

if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling == false)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

76

if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

94

link->dpcd_caps.usb4_dp_tun_info.dpia_info.bits.dpia_num,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

95

link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

96

link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

228

if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

250

if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

302

if (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

335

!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

51

return (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

52

&& link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

53

&& link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

136

if (psr_configuration.bits.ENABLE) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

153

if (psr_error_status.bits.LINK_CRC_ERROR ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

154

psr_error_status.bits.RFB_STORAGE_ERROR ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

155

psr_error_status.bits.VSC_SDP_ERROR) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

175

} else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

225

if (replay_error_status.bits.LINK_CRC_ERROR ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

226

replay_configuration.bits.DESYNC_ERROR_STATUS ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

227

replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

233

if (replay_configuration.bits.DESYNC_ERROR_STATUS)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

327

irq_data->bytes.lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

328

dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

329

irq_data->bytes.lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

330

dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

355

if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

447

if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

453

device_service_clear.bits.AUTOMATED_TEST = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

483

if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

490

if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

524

if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

525

if (hpd_irq_dpcd_data.bytes.link_service_irq_esi0.bits.DP_LINK_TUNNELING_IRQ)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

530

hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

74

if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

75

!lane_status.bits.CR_DONE_0 ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

76

!lane_status.bits.SYMBOL_LOCKED_0) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

89

(!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

90

!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b)) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

92

} else if (!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1106

lane_count_set.bits.LANE_COUNT_SET =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1109

lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1110

lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1115

lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1116

link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1207

link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1208

link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1209

link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1210

link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1216

link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1217

link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1218

link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1219

link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1300

lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1301

lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1302

lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1303

lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1316

lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1317

lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1318

lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1319

lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1454

if (dpcd_lane_status_updated.bits.

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1469

dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET !=

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1470

dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1471

lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET !=

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1472

dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1524

if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1541

lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1542

lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1543

lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

364

dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

366

dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

368

dpcd_lane_settings[lane].bits.MAX_SWING_REACHED =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

371

dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

446

if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

448

else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

450

else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

452

else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

469

if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

484

if (!dpcd_lane_status[lane].bits.CR_DONE_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

497

if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

508

if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

515

return align_status.bits.INTERLANE_ALIGN_DONE == 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

577

if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

578

!lane_status.bits.CR_DONE_0 ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

579

!lane_status.bits.SYMBOL_LOCKED_0 ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

784

if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

820

if (enc_caps->flags.bits.IS_TPS4_CAPABLE &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

821

rx_caps->max_down_spread.bits.TPS4_SUPPORTED)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

823

else if (enc_caps->flags.bits.IS_TPS3_CAPABLE &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

824

rx_caps->max_ln_count.bits.TPS3_SUPPORTED)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

865

(enum dc_voltage_swing)(ln_adjust[lane].bits.

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

868

(enum dc_pre_emphasis)(ln_adjust[lane].bits.

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

124

} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

137

} else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

142

} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

182

dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

185

} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

64

interval_unit = dpcd_interval.bits.UNIT ? 1 : 2; /* 0b = 2 ms, 1b = 1 ms */

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

68

*interval_in_us = (dpcd_interval.bits.VALUE + 1) * interval_unit * 1000;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

101

switch (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

174

if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

313

lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

314

dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

404

return dpcd_lane_status[0].bits.CR_DONE_0 ?

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

70

if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

71

wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

419

if ((lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

420

dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

421

&& (lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

422

dpcd_lane_adjust[0].bits.PRE_EMPHASIS_LANE))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

523

if ((lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

524

dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

525

&& (lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

526

dpcd_lane_adjust[0].bits.PRE_EMPHASIS_LANE))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

925

if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

253

lane_count_set.bits.LANE_COUNT_SET =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

256

lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

257

lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

261

lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

262

link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

379

lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

381

lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

427

if (lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

428

dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

485

lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

487

lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

66

dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

67

dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

84

dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

86

dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1054

replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1055

replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1057

replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1063

alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1066

alpm_config.bits.ALPM_MODE_SEL = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1067

alpm_config.bits.ACDS_PERIOD_DURATION = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

211

if (link->dpcd_sink_ext_caps.bits.oled == 1)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

316

if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

389

lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

523

alpm_config.bits.ENABLE = (enable ? true : false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

742

psr_configuration.bits.ENABLE = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

743

psr_configuration.bits.CRC_VERIFICATION = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

744

psr_configuration.bits.FRAME_CAPTURE_INDICATION =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

754

psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

758

psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

762

psr_configuration.bits.ENABLE_PSR2 = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

766

psr_configuration.bits.EARLY_TRANSPORT_ENABLE = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

789

vtotal_control.bits.ENABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

79

edp_config_set.bits.PANEL_MODE_EDP

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

82

edp_config_set.bits.PANEL_MODE_EDP =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

855

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

858

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

874

psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

877

psr_context->psr_level.bits.DISABLE_ALPM = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

878

psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1297

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1458

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

385

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

834

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

845

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

878

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

272

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

52

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

695

if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

76

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

986

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

146

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

217

if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

531

optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

323

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

388

if (dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver && dc->debug.fams2_config.bits.enable) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

615

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

616

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

659

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

660

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

618

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

619

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

620

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

621

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

702

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

703

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

704

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

705

.flags.bits.IS_TPS4_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

709

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

710

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

715

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

716

.flags.bits.IS_TPS3_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

728

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

729

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

730

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

731

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

908

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

909

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

910

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

911

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

785

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

786

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

787

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

788

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1196

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1197

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1198

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1199

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1449

state->bits.rmu_idx_valid = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1450

state->bits.rmu_mux_num = i;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1451

if (state->bits.rmu_mux_num == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1452

state->bits.mpc_rmu0_mux = mpcc_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1453

else if (state->bits.rmu_mux_num == 1)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1454

state->bits.mpc_rmu1_mux = mpcc_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1455

else if (state->bits.rmu_mux_num == 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1456

state->bits.mpc_rmu2_mux = mpcc_id;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

916

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

917

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

918

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

919

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

872

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

873

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

874

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

875

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

836

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

837

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

838

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

839

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

791

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

792

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

793

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

794

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1082

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1083

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1084

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1085

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2186

!dc->debug.dpia_debug.bits.disable_dpia) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

878

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1140

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1141

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1142

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1143

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

898

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

912

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1080

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1081

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1082

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1083

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

878

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1074

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1075

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1076

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1077

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

873

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1030

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1031

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1032

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1033

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

708

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1024

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1025

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1026

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1027

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

704

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1063

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1064

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1065

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1066

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1595

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1634

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1688

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2155

if (dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

738

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

751

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

828

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

858

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1043

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1044

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1045

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1046

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1575

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1614

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1668

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2127

if (dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

718

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

731

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

808

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

838

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1044

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1045

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1046

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1047

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1576

dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1615

ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1669

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2128

if (dc->debug.dpia_debug.bits.disable_dpia)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

719

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

732

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

809

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

839

dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1022

.flags.bits.IS_HBR2_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1023

.flags.bits.IS_HBR3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1024

.flags.bits.IS_TPS3_CAPABLE = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1025

.flags.bits.IS_TPS4_CAPABLE = true

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1587

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

699

.bits = {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

731

.bits = {

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1081

} bits; /**< GPINT bit access */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1347

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1375

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1973

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2203

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2236

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2288

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2320

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2358

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3044

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3693

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3702

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3709

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3716

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3729

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3753

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3761

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4602

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

654

} bits; /**< status bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

743

} bits; /**< status bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

768

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

850

} bits; /**< boot bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

896

} bits;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

916

} bits;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

103

cmd.bits.status = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

104

cmd.bits.command_code = DMUB_GPINT__STOP_FW;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

105

cmd.bits.param = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

378

reg.bits.status = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

408

boot_options.bits.skip_phy_init_panel_sequence = skip;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

299

return is_enable != 0 && status.bits.dal_fw;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

327

reg.bits.status = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

373

boot_options.bits.z10_disable = params->disable_z10;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

374

boot_options.bits.dpia_supported = params->dpia_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

375

boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

376

boot_options.bits.usb4_cm_version = params->usb4_cm_version;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

377

boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

378

boot_options.bits.power_optimization = params->power_optimization;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

379

boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

380

boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

382

boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

391

boot_options.bits.skip_phy_init_panel_sequence = skip;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

92

cmd.bits.status = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

93

cmd.bits.command_code = DMUB_GPINT__STOP_FW;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

94

cmd.bits.param = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

100

cmd.bits.command_code = DMUB_GPINT__STOP_FW;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

101

cmd.bits.param = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

329

return is_hw_init != 0 && status.bits.dal_fw;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

352

reg.bits.status = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

390

boot_options.bits.z10_disable = params->disable_z10;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

399

boot_options.bits.skip_phy_init_panel_sequence = skip;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

99

cmd.bits.status = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

100

cmd.bits.param = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

335

return is_enable != 0 && status.bits.dal_fw;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

358

reg.bits.status = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

405

dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

408

boot_options.bits.z10_disable = params->disable_z10;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

409

boot_options.bits.dpia_supported = params->dpia_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

410

boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

411

boot_options.bits.usb4_cm_version = params->usb4_cm_version;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

412

boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

413

boot_options.bits.power_optimization = params->power_optimization;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

414

boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

415

boot_options.bits.disable_clk_gate = params->disable_clock_gate;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

416

boot_options.bits.ips_disable = params->disable_ips;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

417

boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

418

boot_options.bits.disable_sldo_opt = params->disable_sldo_opt;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

419

boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

420

boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

429

boot_options.bits.skip_phy_init_panel_sequence = skip;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

569

return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) ||

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

570

(!status.bits.dal_fw && status.bits.mailbox_rdy);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

98

cmd.bits.status = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

99

cmd.bits.command_code = DMUB_GPINT__STOP_FW;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

315

return is_hw_init != 0 && status.bits.dal_fw;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

338

reg.bits.status = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

376

boot_options.bits.z10_disable = params->disable_z10;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

378

boot_options.bits.skip_phy_access = params->disallow_phy_access;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

387

boot_options.bits.skip_phy_init_panel_sequence = skip;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

77

cmd.bits.status = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

78

cmd.bits.command_code = DMUB_GPINT__STOP_FW;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

79

cmd.bits.param = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1033

reg.bits.status = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1034

reg.bits.command_code = command_code;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1035

reg.bits.param = param;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

924

if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on)

sys/dev/pci/drm/amd/display/include/audio_types.h

97

} bits;

sys/dev/pci/drm/amd/display/include/link_service_types.h

233

} bits;

sys/dev/pci/drm/amd/display/include/set_mode_types.h

95

} bits;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.h

56

} bits;

sys/dev/pci/drm/amd/display/modules/inc/mod_shared.h

69

} bits;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

911

(6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

927

psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

930

!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;

sys/dev/pci/drm/amd/include/discovery.h

412

} bits;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

652

} bits;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

710

} bits;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

777

} bits;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

115

} bits;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

138

} bits;

sys/dev/pci/drm/drm_format_helper.c

1274

unsigned int i, bits = min(pixels, 4U);

sys/dev/pci/drm/drm_format_helper.c

1277

for (i = 0; i < bits; i++, pixels--) {

sys/dev/pci/drm/drm_format_helper.c

1292

unsigned int i, bits = min(pixels, 8U);

sys/dev/pci/drm/drm_format_helper.c

1295

for (i = 0; i < bits; i++, pixels--) {

sys/dev/pci/drm/drm_print.c

319

const char * const bits[], unsigned int nbits)

sys/dev/pci/drm/drm_print.c

328

if (WARN_ON_ONCE(!bits[i]))

sys/dev/pci/drm/drm_print.c

331

bits[i]);

sys/dev/pci/drm/drm_print.c

77

.bits = &__drm_debug,

sys/dev/pci/drm/i915/display/intel_display.c

1955

bitmap_zero(mask->bits, POWER_DOMAIN_NUM);

sys/dev/pci/drm/i915/display/intel_display.c

1960

set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1961

set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1964

set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1970

set_bit(intel_encoder->power_domain, mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1974

set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1977

set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1980

set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);

sys/dev/pci/drm/i915/display/intel_display.c

1993

bitmap_andnot(new_domains.bits,

sys/dev/pci/drm/i915/display/intel_display.c

1994

domains.bits,

sys/dev/pci/drm/i915/display/intel_display.c

1995

crtc->enabled_power_domains.mask.bits,

sys/dev/pci/drm/i915/display/intel_display.c

1997

bitmap_andnot(old_domains->bits,

sys/dev/pci/drm/i915/display/intel_display.c

1998

crtc->enabled_power_domains.mask.bits,

sys/dev/pci/drm/i915/display/intel_display.c

1999

domains.bits,

sys/dev/pci/drm/i915/display/intel_display_irq.c

155

void ilk_enable_display_irq(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

157

ilk_update_display_irq(display, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

160

void ilk_disable_display_irq(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

162

ilk_update_display_irq(display, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

230

enum pipe pipe, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

232

bdw_update_pipe_irq(display, pipe, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

236

enum pipe pipe, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

238

bdw_update_pipe_irq(display, pipe, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.c

268

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

270

ibx_display_interrupt_update(display, bits, bits);

sys/dev/pci/drm/i915/display/intel_display_irq.c

273

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits)

sys/dev/pci/drm/i915/display/intel_display_irq.c

275

ibx_display_interrupt_update(display, bits, 0);

sys/dev/pci/drm/i915/display/intel_display_irq.h

24

void ilk_enable_display_irq(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

25

void ilk_disable_display_irq(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

28

void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

29

void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

33

void ibx_enable_display_interrupt(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_irq.h

34

void ibx_disable_display_interrupt(struct intel_display *display, u32 bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

363

bitmap_or(mask->bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

364

power_domains->async_put_domains[0].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

365

power_domains->async_put_domains[1].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

379

bitmap_intersects(power_domains->async_put_domains[0].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

380

power_domains->async_put_domains[1].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

39

for_each_if(test_bit((__domain), (__power_well)->domains.bits))

sys/dev/pci/drm/i915/display/intel_display_power.c

398

!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));

sys/dev/pci/drm/i915/display/intel_display_power.c

415

drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));

sys/dev/pci/drm/i915/display/intel_display_power.c

43

for_each_if(test_bit((__domain), (__power_well)->domains.bits))

sys/dev/pci/drm/i915/display/intel_display_power.c

474

clear_bit(domain, power_domains->async_put_domains[0].bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

475

clear_bit(domain, power_domains->async_put_domains[1].bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

498

if (!test_bit(domain, async_put_mask.bits))

sys/dev/pci/drm/i915/display/intel_display_power.c

506

if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))

sys/dev/pci/drm/i915/display/intel_display_power.c

618

test_bit(domain, async_put_mask.bits),

sys/dev/pci/drm/i915/display/intel_display_power.c

704

if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {

sys/dev/pci/drm/i915/display/intel_display_power.c

705

bitmap_copy(power_domains->async_put_domains[0].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

706

power_domains->async_put_domains[1].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

708

bitmap_zero(power_domains->async_put_domains[1].bits,

sys/dev/pci/drm/i915/display/intel_display_power.c

764

set_bit(domain, power_domains->async_put_domains[1].bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

768

set_bit(domain, power_domains->async_put_domains[0].bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

889

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

sys/dev/pci/drm/i915/display/intel_display_power.c

895

set_bit(domain, power_domain_set->mask.bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

905

drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));

sys/dev/pci/drm/i915/display/intel_display_power.c

914

set_bit(domain, power_domain_set->mask.bits);

sys/dev/pci/drm/i915/display/intel_display_power.c

928

!bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));

sys/dev/pci/drm/i915/display/intel_display_power.c

938

clear_bit(domain, power_domain_set->mask.bits);

sys/dev/pci/drm/i915/display/intel_display_power.h

129

DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);

sys/dev/pci/drm/i915/display/intel_display_power.h

168

for_each_if(test_bit((__domain), (__mask)->bits))

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1782

bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1788

set_bit(inst->domain_list->list[j], power_well->domains.bits);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1352

#define BITS_SET(val, bits) (((val) & (bits)) == (bits))

sys/dev/pci/drm/i915/display/intel_fb.c

2167

if (!atomic_read(&front->bits))

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

264

drm_WARN_ON(display->drm, atomic_read(&front->bits));

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

296

atomic_set(&front->bits, 0);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

351

!(atomic_read(&old->bits) & frontbuffer_bits));

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

352

atomic_andnot(frontbuffer_bits, &old->bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

359

atomic_read(&new->bits) & frontbuffer_bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.c

360

atomic_or(frontbuffer_bits, &new->bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

106

frontbuffer_bits = atomic_read(&front->bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

134

frontbuffer_bits = atomic_read(&front->bits);

sys/dev/pci/drm/i915/display/intel_frontbuffer.h

46

atomic_t bits;

sys/dev/pci/drm/i915/display/intel_gmbus.c

397

intel_bb_set_bits(void *cookie, uint32_t bits)

sys/dev/pci/drm/i915/display/intel_gmbus.c

399

set_clock(cookie, bits & INTEL_BB_SCL);

sys/dev/pci/drm/i915/display/intel_gmbus.c

400

set_data(cookie, bits & INTEL_BB_SDA);

sys/dev/pci/drm/i915/display/intel_gmbus.c

404

intel_bb_set_dir(void *cookie, uint32_t bits)

sys/dev/pci/drm/i915/display/intel_gmbus.c

411

uint32_t bits = 0;

sys/dev/pci/drm/i915/display/intel_gmbus.c

414

bits |= INTEL_BB_SCL;

sys/dev/pci/drm/i915/display/intel_gmbus.c

416

bits |= INTEL_BB_SDA;

sys/dev/pci/drm/i915/display/intel_gmbus.c

418

return bits;

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

187

u32 mask, u32 bits)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

190

drm_WARN_ON(display->drm, bits & ~mask);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

192

intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

209

u32 bits)

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

212

i915_hotplug_interrupt_update_locked(display, mask, bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

26

u32 mask, u32 bits);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.h

28

u32 mask, u32 bits);

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

998

if (drm_WARN_ON(display->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))

sys/dev/pci/drm/i915/display/intel_pfit.c

372

u32 bits;

sys/dev/pci/drm/i915/display/intel_pfit.c

385

bits = panel_fitter_scaling(pipe_src_h,

sys/dev/pci/drm/i915/display/intel_pfit.c

388

*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |

sys/dev/pci/drm/i915/display/intel_pfit.c

389

PFIT_VERT_SCALE(bits));

sys/dev/pci/drm/i915/display/intel_pfit.c

400

bits = panel_fitter_scaling(pipe_src_w,

sys/dev/pci/drm/i915/display/intel_pfit.c

403

*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |

sys/dev/pci/drm/i915/display/intel_pfit.c

404

PFIT_VERT_SCALE(bits));

sys/dev/pci/drm/i915/display/intel_plane_initial.c

384

atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);

sys/dev/pci/drm/i915/gt/intel_gtt.h

110

#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \

sys/dev/pci/drm/i915/gt/intel_gtt.h

111

(((bits) & 0x8) << (11 - 3)))

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

185

u32 bits[SLPC_OVERRIDE_BITFIELD_SIZE];

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

95

data->override_params.bits[id >> 5] |= (1 << (id % 32));

sys/dev/pci/drm/i915/i915_cmd_parser.c

1314

if (desc->bits[i].mask == 0)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1317

if (desc->bits[i].condition_mask != 0) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1319

desc->bits[i].condition_offset;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1321

desc->bits[i].condition_mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1327

if (desc->bits[i].offset >= length) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1333

dword = cmd[desc->bits[i].offset] &

sys/dev/pci/drm/i915/i915_cmd_parser.c

1334

desc->bits[i].mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1336

if (dword != desc->bits[i].expected) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1339

desc->bits[i].mask,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1340

desc->bits[i].expected,

sys/dev/pci/drm/i915/i915_cmd_parser.c

177

} bits[MAX_CMD_DESC_BITMASKS];

sys/dev/pci/drm/i915/i915_cmd_parser.c

232

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

239

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

262

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

269

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

275

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

281

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

289

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

298

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

340

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

347

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

367

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

384

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

391

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

411

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

421

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

428

.bits = {{

sys/dev/pci/drm/i915/i915_cmd_parser.c

503

.bits = {{

sys/dev/pci/drm/i915/i915_ptr_util.h

16

#define ptr_unpack_bits(ptr, bits, n) ({ \

sys/dev/pci/drm/i915/i915_ptr_util.h

18

*(bits) = __v & (BIT(n) - 1); \

sys/dev/pci/drm/i915/i915_ptr_util.h

22

#define ptr_pack_bits(ptr, bits, n) ({ \

sys/dev/pci/drm/i915/i915_ptr_util.h

23

unsigned long __bits = (bits); \

sys/dev/pci/drm/i915/i915_ptr_util.h

40

#define page_pack_bits(ptr, bits) ptr_pack_bits(ptr, bits, PAGE_SHIFT)

sys/dev/pci/drm/i915/i915_ptr_util.h

41

#define page_unpack_bits(ptr, bits) ptr_unpack_bits(ptr, bits, PAGE_SHIFT)

sys/dev/pci/drm/include/drm/drm_print.h

202

const char * const bits[], unsigned int nbits);

sys/dev/pci/drm/include/linux/atomic.h

62

#define atomic_andnot(bits, p) atomic_clearbits_int(p,bits)

sys/dev/pci/drm/include/linux/hash.h

12

hash_32(uint32_t val, unsigned int bits)

sys/dev/pci/drm/include/linux/hash.h

14

return (val * GOLDEN_RATIO_32) >> (32 - bits);

sys/dev/pci/drm/include/linux/hash.h

21

hash_64(uint64_t val, unsigned int bits)

sys/dev/pci/drm/include/linux/hash.h

23

return (val * GOLDEN_RATIO_64) >> (64 - bits);

sys/dev/pci/drm/include/linux/hash.h

27

#define hash_long(val, bits) hash_64(val, bits)

sys/dev/pci/drm/include/linux/hash.h

29

#define hash_long(val, bits) hash_32(val, bits)

sys/dev/pci/drm/include/linux/hashtable.h

24

#define DECLARE_HASHTABLE(name, bits) struct hlist_head name[1 << (bits)]

sys/dev/pci/drm/radeon/cik_reg.h

235

} bitfields, bits;

sys/dev/pci/drm/radeon/radeon_device.c

1195

unsigned bits = ilog2(radeon_vm_size) + 18;

sys/dev/pci/drm/radeon/radeon_device.c

1200

radeon_vm_block_size = bits - 9;

sys/dev/pci/drm/radeon/radeon_device.c

1202

radeon_vm_block_size = (bits + 3) / 2;

sys/dev/pci/drm/radeon/radeon_i2c.c

257

radeon_bb_set_bits(void *cookie, uint32_t bits)

sys/dev/pci/drm/radeon/radeon_i2c.c

259

set_clock(cookie, bits & RADEON_BB_SCL);

sys/dev/pci/drm/radeon/radeon_i2c.c

260

set_data(cookie, bits & RADEON_BB_SDA);

sys/dev/pci/drm/radeon/radeon_i2c.c

264

radeon_bb_set_dir(void *cookie, uint32_t bits)

sys/dev/pci/drm/radeon/radeon_i2c.c

271

uint32_t bits = 0;

sys/dev/pci/drm/radeon/radeon_i2c.c

274

bits |= RADEON_BB_SCL;

sys/dev/pci/drm/radeon/radeon_i2c.c

276

bits |= RADEON_BB_SDA;

sys/dev/pci/drm/radeon/radeon_i2c.c

278

return bits;

sys/dev/pci/envy.c

371

int bits, i, reg;

sys/dev/pci/envy.c

395

bits = 0xa000 | (addr << 8) | data;

sys/dev/pci/envy.c

398

reg |= (bits & 0x8000) ? dout : 0;

sys/dev/pci/envy.c

405

bits <<= 1;

sys/dev/pci/envy.c

457

int bits, i, reg;

sys/dev/pci/envy.c

465

bits = 0xa000 | (addr << 8) | data;

sys/dev/pci/envy.c

468

reg |= (bits & 0x8000) ? AP192K_GPIO_DOUT : 0;

sys/dev/pci/envy.c

475

bits <<= 1;

sys/dev/pci/envy.c

513

int bits, i, reg;

sys/dev/pci/envy.c

520

bits = 0xa000 | (addr << 8) | data;

sys/dev/pci/envy.c

523

reg |= (bits & 0x8000) ? EWX_GPIO_DOUT : 0;

sys/dev/pci/envy.c

530

bits <<= 1;

sys/dev/pci/envy.c

590

int attn, bits, mask, reg;

sys/dev/pci/envy.c

601

bits = 0xa000 | (addr << 8) | data;

sys/dev/pci/envy.c

604

reg |= (bits & mask) ? REVO51_GPIO_DOUT : 0;

sys/dev/pci/glxpcib.c

794

glxpcib_smb_wait(struct glxpcib_softc *sc, int bits, int flags)

sys/dev/pci/glxpcib.c

804

sc->sc_dev.dv_xname, bits, st);

sys/dev/pci/glxpcib.c

808

if ((bits & AMD5536_SMB_STS_MASTER) == 0 &&

sys/dev/pci/glxpcib.c

816

if ((st & bits) == bits)

sys/dev/pci/glxpcib.c

820

if ((st & bits) != bits) {

sys/dev/pci/if_aq_pci.c

2554

uint32_t bits;

sys/dev/pci/if_aq_pci.c

2561

bits = 0x11111111;

sys/dev/pci/if_aq_pci.c

2564

bits = 0x22222222;

sys/dev/pci/if_aq_pci.c

2567

bits = 0x33333333;

sys/dev/pci/if_aq_pci.c

2572

RX_FLR_RSS_CONTROL1_EN | bits);

sys/dev/pci/if_aq_pci.c

2846

int bits, queue;

sys/dev/pci/if_aq_pci.c

2887

bits = 0;

sys/dev/pci/if_aq_pci.c

2891

while (bits < 16) {

sys/dev/pci/if_aq_pci.c

2892

redir |= (queue << bits);

sys/dev/pci/if_aq_pci.c

2893

bits += 3;

sys/dev/pci/if_aq_pci.c

2911

bits -= 16;

sys/dev/pci/if_de.c

172

void tulip_mii_writebits(tulip_softc_t * const sc, unsigned data, unsigned bits);

sys/dev/pci/if_de.c

1775

unsigned lastbit, data, bits, bit, csr;

sys/dev/pci/if_de.c

1782

for (bits = idx|cmdmask, bit = bitwidth + 3; bit > 0; bit--, bits <<= 1) {

sys/dev/pci/if_de.c

1783

const unsigned thisbit = bits & msb;

sys/dev/pci/if_de.c

1795

for (data = 0, bits = 0; bits < 16; bits++) {

sys/dev/pci/if_de.c

1810

tulip_mii_writebits(tulip_softc_t * const sc, unsigned data, unsigned bits)

sys/dev/pci/if_de.c

1812

unsigned msb = 1 << (bits - 1);

sys/dev/pci/if_de.c

1818

for (; bits > 0; bits--, data <<= 1) {

sys/dev/pci/if_iwm.c

1127

iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwm.c

1131

if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/pci/if_iwm.c

1188

iwm_set_bits_mask_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits,

sys/dev/pci/if_iwm.c

1195

val |= bits;

sys/dev/pci/if_iwm.c

1204

iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwm.c

1206

return iwm_set_bits_mask_prph(sc, reg, bits, ~0);

sys/dev/pci/if_iwm.c

1210

iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwm.c

1212

return iwm_set_bits_mask_prph(sc, reg, 0, ~bits);

sys/dev/pci/if_iwx.c

1766

iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwx.c

1770

if ((IWX_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/pci/if_iwx.c

1841

iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits,

sys/dev/pci/if_iwx.c

1848

val |= bits;

sys/dev/pci/if_iwx.c

1857

iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwx.c

1859

return iwx_set_bits_mask_prph(sc, reg, bits, ~0);

sys/dev/pci/if_iwx.c

1863

iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwx.c

1865

return iwx_set_bits_mask_prph(sc, reg, 0, ~bits);

sys/dev/pci/if_mwx.c

490

mwx_set(struct mwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_mwx.c

492

return mwx_rmw(sc, reg, bits, 0);

sys/dev/pci/if_mwx.c

496

mwx_clear(struct mwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_mwx.c

498

return mwx_rmw(sc, reg, 0, bits);

sys/dev/pci/if_nge.c

338

nge_mii_send(struct nge_softc *sc, u_int32_t bits, int cnt)

sys/dev/pci/if_nge.c

345

if (bits & i) {

sys/dev/pci/if_sis.c

391

sis_mii_send(struct sis_softc *sc, u_int32_t bits, int cnt)

sys/dev/pci/if_sis.c

398

if (bits & i)

sys/dev/pci/if_ste.c

170

ste_mii_send(struct ste_softc *sc, u_int32_t bits, int cnt)

sys/dev/pci/if_ste.c

177

if (bits & i) {

sys/dev/pci/if_tl.c

518

tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt)

sys/dev/pci/if_tl.c

524

if (bits & i)

sys/dev/pci/if_wb.c

291

wb_mii_send(struct wb_softc *sc, u_int32_t bits, int cnt)

sys/dev/pci/if_wb.c

298

if (bits & i) {

sys/dev/pci/ixgbe.c

3230

uint32_t bits;

sys/dev/pci/ixgbe.c

3251

bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));

sys/dev/pci/ixgbe.c

3252

if (bits == vlan)

sys/dev/pci/ixgbe.c

3254

if (!first_empty_slot && !bits)

sys/dev/pci/ixgbe.c

3348

uint32_t bits;

sys/dev/pci/ixgbe.c

3370

bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));

sys/dev/pci/ixgbe.c

3373

bits |= 1 << (vind % 32);

sys/dev/pci/ixgbe.c

3378

bits ^= 1 << (vind % 32);

sys/dev/pci/ixgbe.c

3380

if (!bits &&

sys/dev/pci/ixgbe.c

3414

IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);

sys/dev/pci/ixgbe_82598.c

1015

uint32_t bits;

sys/dev/pci/ixgbe_82598.c

1031

bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));

sys/dev/pci/ixgbe_82598.c

1032

bits &= (~(0x0F << bitindex));

sys/dev/pci/ixgbe_82598.c

1033

bits |= (vind << bitindex);

sys/dev/pci/ixgbe_82598.c

1034

IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);

sys/dev/pci/ixgbe_82598.c

1039

bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));

sys/dev/pci/ixgbe_82598.c

1042

bits |= (1 << bitindex);

sys/dev/pci/ixgbe_82598.c

1045

bits &= ~(1 << bitindex);

sys/dev/pci/ixgbe_82598.c

1046

IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);

sys/dev/sbus/cs4231.c

277

u_char bits;

sys/dev/sbus/cs4231.c

326

sc->sc_speed_bits = speed_table[selected].bits;

sys/dev/sbus/cs4231.c

469

int err, bits, enc = p->encoding;

sys/dev/sbus/cs4231.c

475

bits = FMT_ULAW >> 5;

sys/dev/sbus/cs4231.c

480

bits = FMT_ALAW >> 5;

sys/dev/sbus/cs4231.c

484

bits = FMT_TWOS_COMP >> 5;

sys/dev/sbus/cs4231.c

490

bits = FMT_TWOS_COMP_BE >> 5;

sys/dev/sbus/cs4231.c

497

bits = FMT_PCM8 >> 5;

sys/dev/sbus/cs4231.c

516

sc->sc_format_bits = bits;

sys/dev/sbus/magma.c

1144

mtty_modem_control(struct mtty_port *mp, int bits, int howto)

sys/dev/sbus/magma.c

1156

bits = 0;

sys/dev/sbus/magma.c

1158

bits |= TIOCM_LE;

sys/dev/sbus/magma.c

1162

bits |= TIOCM_DTR;

sys/dev/sbus/magma.c

1166

bits |= TIOCM_RTS;

sys/dev/sbus/magma.c

1168

bits |= TIOCM_CTS;

sys/dev/sbus/magma.c

1170

bits |= TIOCM_RI;

sys/dev/sbus/magma.c

1172

bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR);

sys/dev/sbus/magma.c

1174

bits |= (cd->cd_parmode ? 0 : TIOCM_CD);

sys/dev/sbus/magma.c

1181

((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0));

sys/dev/sbus/magma.c

1184

((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0));

sys/dev/sbus/magma.c

1189

if ((bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS))

sys/dev/sbus/magma.c

1192

if (bits & TIOCM_DTR)

sys/dev/sbus/magma.c

1198

if ((bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS))

sys/dev/sbus/magma.c

1201

if (bits & TIOCM_DTR)

sys/dev/sbus/magma.c

1208

return (bits);

sys/dev/sbus/spif.c

502

stty_modem_control(struct stty_port *sp, int bits, int how)

sys/dev/sbus/spif.c

513

bits = TIOCM_LE;

sys/dev/sbus/spif.c

515

bits |= TIOCM_DTR;

sys/dev/sbus/spif.c

518

bits |= TIOCM_DSR;

sys/dev/sbus/spif.c

520

bits |= TIOCM_CD;

sys/dev/sbus/spif.c

522

bits |= TIOCM_CTS;

sys/dev/sbus/spif.c

524

bits |= TIOCM_RTS;

sys/dev/sbus/spif.c

527

DTR_WRITE(csc, sp->sp_channel, ISSET(bits, TIOCM_DTR) ? 1 : 0);

sys/dev/sbus/spif.c

528

if (ISSET(bits, TIOCM_RTS))

sys/dev/sbus/spif.c

536

if (ISSET(bits, TIOCM_DTR))

sys/dev/sbus/spif.c

538

if (ISSET(bits, TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS))

sys/dev/sbus/spif.c

543

if (ISSET(bits, TIOCM_DTR))

sys/dev/sbus/spif.c

545

if (ISSET(bits, TIOCM_RTS))

sys/dev/sbus/spif.c

552

return (bits);

sys/dev/sdmmc/sdhc.c

85

#define HCLR1(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

86

HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))

sys/dev/sdmmc/sdhc.c

87

#define HCLR2(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

88

HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))

sys/dev/sdmmc/sdhc.c

89

#define HSET1(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

90

HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))

sys/dev/sdmmc/sdhc.c

91

#define HSET2(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

92

HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))

sys/dev/spdmem.c

473

int dimm_size, cycle_time, d_clk, p_clk, bits;

sys/dev/spdmem.c

517

bits = s->sm_data[SPDMEM_DDR_DATAWIDTH] |

sys/dev/spdmem.c

520

bits -= 8;

sys/dev/spdmem.c

523

p_clk = d_clk * bits / 8;

sys/dev/spdmem.c

544

int dimm_size, cycle_time, d_clk, p_clk, bits;

sys/dev/spdmem.c

584

bits = s->sm_data[SPDMEM_DDR2_DATAWIDTH];

sys/dev/spdmem.c

586

bits -= 8;

sys/dev/spdmem.c

589

p_clk = d_clk * bits / 8;

sys/dev/spdmem.c

619

int dimm_size, cycle_time, d_clk, p_clk, bits;

sys/dev/spdmem.c

651

bits = 1 << ((s->sm_data[SPDMEM_FBDIMM_RANKS] &

sys/dev/spdmem.c

654

p_clk = (d_clk * bits) / 8 / cycle_time;

sys/dev/spdmem.c

664

int dimm_size, cycle_time, d_clk, p_clk, bits;

sys/dev/spdmem.c

711

bits = 1 << ((s->sm_data[SPDMEM_DDR3_DATAWIDTH] &

sys/dev/spdmem.c

719

p_clk = (d_clk * bits) / 8 / cycle_time;

sys/dev/spdmem.c

749

int dimm_size, cycle_time, d_clk, p_clk, bits;

sys/dev/spdmem.c

816

bits = 1 << ((s->sm_data[SPDMEM_DDR4_DATAWIDTH] &

sys/dev/spdmem.c

819

p_clk = (d_clk * bits) / 8 / cycle_time;

sys/dev/tc/tcds.c

482

#define PRINTINTR(msg, bits) \

sys/dev/tc/tcds.c

483

if (ir & bits) \

sys/dev/usb/if_smsc.c

264

smsc_wait_for_bits(struct smsc_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/usb/if_smsc.c

272

if (!(val & bits))

sys/dev/usb/uaudio.c

1915

a->nch, a->bits, a->bps);

sys/dev/usb/uaudio.c

1931

p->palt ? p->palt->bits : 0,

sys/dev/usb/uaudio.c

1934

p->ralt ? p->ralt->bits : 0,

sys/dev/usb/uaudio.c

2531

unsigned int type, bps, bits, nch, nrates, rate_min, rate_max, rates;

sys/dev/usb/uaudio.c

2548

if (!uaudio_getnum(p, 1, &bits))

sys/dev/usb/uaudio.c

2594

if (!uaudio_getnum(p, 1, &bits))

sys/dev/usb/uaudio.c

2604

a->bits = bits;

sys/dev/usb/uaudio.c

2709

if (a->bits > anext->bits)

sys/dev/usb/uaudio.c

2746

if (ar->bps != ap->bps || ar->bits != ap->bits)

sys/dev/usb/uaudio.c

297

int bps, bits, nch; /* audio encoding */

sys/dev/usb/uaudio.c

4123

if (p->palt->bits != ap->precision)

sys/dev/usb/uaudio.c

4127

if (p->ralt->bits != ar->precision)

sys/dev/usb/uaudio.c

4161

ap->precision = p->palt->bits;

sys/dev/usb/uaudio.c

4169

ar->precision = p->ralt->bits;

sys/dev/usb/uaudio.c

748

unsigned int bits, n;

sys/dev/usb/uaudio.c

754

bits = (ctl >> i) & 1;

sys/dev/usb/uaudio.c

755

if (bits)

sys/dev/usb/uaudio.c

756

bits |= 2;

sys/dev/usb/uaudio.c

757

n |= bits << (2 * i);

sys/kern/kern_descrip.c

104

if (want > bits)

sys/kern/kern_descrip.c

116

maxoff = NDLOSLOTS(bits);

sys/kern/kern_descrip.c

99

find_next_zero(u_int *bitmap, int want, u_int bits)

sys/kern/kern_pledge.c

557

for (i = 0; code && pledgenames[i].bits != 0; i++)

sys/kern/kern_pledge.c

558

if (pledgenames[i].bits & code) {

sys/kern/sys_generic.c

603

fd_mask bits[6];

sys/kern/sys_generic.c

616

if (ni > sizeof(bits[0])) {

sys/kern/sys_generic.c

627

memset(bits, 0, sizeof(bits));

sys/kern/sys_generic.c

628

pibits[0] = (fd_set *)&bits[0];

sys/kern/sys_generic.c

629

pibits[1] = (fd_set *)&bits[1];

sys/kern/sys_generic.c

630

pibits[2] = (fd_set *)&bits[2];

sys/kern/sys_generic.c

631

pobits[0] = (fd_set *)&bits[3];

sys/kern/sys_generic.c

632

pobits[1] = (fd_set *)&bits[4];

sys/kern/sys_generic.c

633

pobits[2] = (fd_set *)&bits[5];

sys/kern/sys_generic.c

731

if (pibits[0] != (fd_set *)&bits[0])

sys/kern/sys_generic.c

751

fd_mask bits;

sys/kern/sys_generic.c

755

bits = pibits[msk]->fds_bits[i / NFDBITS];

sys/kern/sys_generic.c

756

while ((j = ffs(bits)) && (fd = i + --j) < nfd) {

sys/kern/sys_generic.c

757

bits &= ~(1 << j);

sys/lib/libsa/rijndael.c

1223

rijndael_set_key_enc_only(rijndael_ctx *ctx, const u_char *key, int bits)

sys/lib/libsa/rijndael.c

1227

rounds = rijndaelKeySetupEnc(ctx->ek, key, bits);

sys/lib/libsa/rijndael.c

1239

rijndael_set_key(rijndael_ctx *ctx, const u_char *key, int bits)

sys/lib/libsa/rijndael.c

1243

rounds = rijndaelKeySetupEnc(ctx->ek, key, bits);

sys/lib/libsa/rijndael.c

1246

if (rijndaelKeySetupDec(ctx->dk, key, bits) != rounds)

sys/lib/libsa/sha1.c

26

#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))

sys/lib/libz/deflate.c

718

int ZEXPORT deflatePending(z_streamp strm, unsigned *pending, int *bits) {

sys/lib/libz/deflate.c

720

if (bits != Z_NULL)

sys/lib/libz/deflate.c

721

*bits = strm->state->bi_valid;

sys/lib/libz/deflate.c

733

int ZEXPORT deflateUsed(z_streamp strm, int *bits) {

sys/lib/libz/deflate.c

735

if (bits != Z_NULL)

sys/lib/libz/deflate.c

736

*bits = strm->state->bi_used;

sys/lib/libz/deflate.c

741

int ZEXPORT deflatePrime(z_streamp strm, int bits, int value) {

sys/lib/libz/deflate.c

748

if (bits < 0 || bits > 16 ||

sys/lib/libz/deflate.c

752

if (bits < 0 || bits > 16 ||

sys/lib/libz/deflate.c

758

if (put > bits)

sys/lib/libz/deflate.c

759

put = bits;

sys/lib/libz/deflate.c

764

bits -= put;

sys/lib/libz/deflate.c

765

} while (bits);

sys/lib/libz/infback.c

117

hold += (unsigned long)(*next++) << bits; \

sys/lib/libz/infback.c

118

bits += 8; \

sys/lib/libz/infback.c

126

while (bits < (unsigned)(n)) \

sys/lib/libz/infback.c

138

bits -= (unsigned)(n); \

sys/lib/libz/infback.c

144

hold >>= bits & 7; \

sys/lib/libz/infback.c

145

bits -= bits & 7; \

sys/lib/libz/infback.c

198

unsigned bits; /* bits in bit buffer */

sys/lib/libz/infback.c

221

bits = 0;

sys/lib/libz/infback.c

355

if ((unsigned)(here.bits) <= bits) break;

sys/lib/libz/infback.c

359

DROPBITS(here.bits);

sys/lib/libz/infback.c

364

NEEDBITS(here.bits + 2);

sys/lib/libz/infback.c

365

DROPBITS(here.bits);

sys/lib/libz/infback.c

381

NEEDBITS(here.bits + 3);

sys/lib/libz/infback.c

382

DROPBITS(here.bits);

sys/lib/libz/infback.c

388

NEEDBITS(here.bits + 7);

sys/lib/libz/infback.c

389

DROPBITS(here.bits);

sys/lib/libz/infback.c

474

if ((unsigned)(here.bits) <= bits) break;

sys/lib/libz/infback.c

481

(BITS(last.bits + last.op) >> last.bits)];

sys/lib/libz/infback.c

482

if ((unsigned)(last.bits + here.bits) <= bits) break;

sys/lib/libz/infback.c

485

DROPBITS(last.bits);

sys/lib/libz/infback.c

487

DROPBITS(here.bits);

sys/lib/libz/infback.c

532

if ((unsigned)(here.bits) <= bits) break;

sys/lib/libz/infback.c

539

(BITS(last.bits + last.op) >> last.bits)];

sys/lib/libz/infback.c

540

if ((unsigned)(last.bits + here.bits) <= bits) break;

sys/lib/libz/infback.c

543

DROPBITS(last.bits);

sys/lib/libz/infback.c

545

DROPBITS(here.bits);

sys/lib/libz/infback.c

76

bits = state->bits; \

sys/lib/libz/infback.c

87

state->bits = bits; \

sys/lib/libz/infback.c

94

bits = 0; \

sys/lib/libz/inffast.c

101

if (bits < 15) {

sys/lib/libz/inffast.c

102

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

103

bits += 8;

sys/lib/libz/inffast.c

104

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

105

bits += 8;

sys/lib/libz/inffast.c

109

op = (unsigned)(here->bits);

sys/lib/libz/inffast.c

111

bits -= op;

sys/lib/libz/inffast.c

123

if (bits < op) {

sys/lib/libz/inffast.c

124

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

125

bits += 8;

sys/lib/libz/inffast.c

129

bits -= op;

sys/lib/libz/inffast.c

132

if (bits < 15) {

sys/lib/libz/inffast.c

133

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

134

bits += 8;

sys/lib/libz/inffast.c

135

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

136

bits += 8;

sys/lib/libz/inffast.c

140

op = (unsigned)(here->bits);

sys/lib/libz/inffast.c

142

bits -= op;

sys/lib/libz/inffast.c

147

if (bits < op) {

sys/lib/libz/inffast.c

148

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

149

bits += 8;

sys/lib/libz/inffast.c

150

if (bits < op) {

sys/lib/libz/inffast.c

151

hold += (unsigned long)(*in++) << bits;

sys/lib/libz/inffast.c

152

bits += 8;

sys/lib/libz/inffast.c

165

bits -= op;

sys/lib/libz/inffast.c

303

len = bits >> 3;

sys/lib/libz/inffast.c

305

bits -= len << 3;

sys/lib/libz/inffast.c

306

hold &= (1U << bits) - 1;

sys/lib/libz/inffast.c

315

state->bits = bits;

sys/lib/libz/inffast.c

65

unsigned bits; /* local strm->bits */

sys/lib/libz/inffast.c

92

bits = state->bits;

sys/lib/libz/inflate.c

1000

state->back += last.bits;

sys/lib/libz/inflate.c

1002

DROPBITS(here.bits);

sys/lib/libz/inflate.c

1003

state->back += here.bits;

sys/lib/libz/inflate.c

1044

if ((unsigned)(here.bits) <= bits) break;

sys/lib/libz/inflate.c

1051

(BITS(last.bits + last.op) >> last.bits)];

sys/lib/libz/inflate.c

1052

if ((unsigned)(last.bits + here.bits) <= bits) break;

sys/lib/libz/inflate.c

1055

DROPBITS(last.bits);

sys/lib/libz/inflate.c

1056

state->back += last.bits;

sys/lib/libz/inflate.c

1058

DROPBITS(here.bits);

sys/lib/libz/inflate.c

1059

state->back += here.bits;

sys/lib/libz/inflate.c

117

state->bits = 0;

sys/lib/libz/inflate.c

1233

strm->data_type = (int)state->bits + (state->last ? 64 : 0) +

sys/lib/libz/inflate.c

1360

if (strm->avail_in == 0 && state->bits < 8) return Z_BUF_ERROR;

sys/lib/libz/inflate.c

1365

state->hold >>= state->bits & 7;

sys/lib/libz/inflate.c

1366

state->bits -= state->bits & 7;

sys/lib/libz/inflate.c

1368

while (state->bits >= 8) {

sys/lib/libz/inflate.c

1371

state->bits -= 8;

sys/lib/libz/inflate.c

1411

return state->mode == STORED && state->bits == 0;

sys/lib/libz/inflate.c

219

int ZEXPORT inflatePrime(z_streamp strm, int bits, int value) {

sys/lib/libz/inflate.c

223

if (bits == 0)

sys/lib/libz/inflate.c

226

if (bits < 0) {

sys/lib/libz/inflate.c

228

state->bits = 0;

sys/lib/libz/inflate.c

231

if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR;

sys/lib/libz/inflate.c

232

value &= (1L << bits) - 1;

sys/lib/libz/inflate.c

233

state->hold += (unsigned long)value << state->bits;

sys/lib/libz/inflate.c

234

state->bits += (uInt)bits;

sys/lib/libz/inflate.c

335

bits = state->bits; \

sys/lib/libz/inflate.c

346

state->bits = bits; \

sys/lib/libz/inflate.c

353

bits = 0; \

sys/lib/libz/inflate.c

362

hold += (unsigned long)(*next++) << bits; \

sys/lib/libz/inflate.c

363

bits += 8; \

sys/lib/libz/inflate.c

370

while (bits < (unsigned)(n)) \

sys/lib/libz/inflate.c

382

bits -= (unsigned)(n); \

sys/lib/libz/inflate.c

388

hold >>= bits & 7; \

sys/lib/libz/inflate.c

389

bits -= bits & 7; \

sys/lib/libz/inflate.c

480

unsigned bits; /* bits in bit buffer */

sys/lib/libz/inflate.c

868

if ((unsigned)(here.bits) <= bits) break;

sys/lib/libz/inflate.c

872

DROPBITS(here.bits);

sys/lib/libz/inflate.c

877

NEEDBITS(here.bits + 2);

sys/lib/libz/inflate.c

878

DROPBITS(here.bits);

sys/lib/libz/inflate.c

894

NEEDBITS(here.bits + 3);

sys/lib/libz/inflate.c

895

DROPBITS(here.bits);

sys/lib/libz/inflate.c

901

NEEDBITS(here.bits + 7);

sys/lib/libz/inflate.c

902

DROPBITS(here.bits);

sys/lib/libz/inflate.c

988

if ((unsigned)(here.bits) <= bits) break;

sys/lib/libz/inflate.c

995

(BITS(last.bits + last.op) >> last.bits)];

sys/lib/libz/inflate.c

996

if ((unsigned)(last.bits + here.bits) <= bits) break;

sys/lib/libz/inflate.c

999

DROPBITS(last.bits);

sys/lib/libz/inflate.h

103

unsigned bits; /* number of bits in hold */

sys/lib/libz/inftrees.c

120

root = *bits;

sys/lib/libz/inftrees.c

126

here.bits = (unsigned char)1;

sys/lib/libz/inftrees.c

130

*bits = 1;

sys/lib/libz/inftrees.c

221

here.bits = (unsigned char)(len - drop);

sys/lib/libz/inftrees.c

290

(*table)[low].bits = (unsigned char)root;

sys/lib/libz/inftrees.c

300

here.bits = (unsigned char)(len - drop);

sys/lib/libz/inftrees.c

307

*bits = root;

sys/lib/libz/inftrees.c

326

unsigned sym, bits;

sys/lib/libz/inftrees.c

338

bits = 9;

sys/lib/libz/inftrees.c

339

inflate_table(LENS, lens, 288, &(next), &(bits), work);

sys/lib/libz/inftrees.c

345

bits = 5;

sys/lib/libz/inftrees.c

346

inflate_table(DISTS, lens, 32, &(next), &(bits), work);

sys/lib/libz/inftrees.c

404

state.lencode[low].bits, state.lencode[low].val);

sys/lib/libz/inftrees.c

414

printf("{%u,%u,%d}", state.distcode[low].op, state.distcode[low].bits,

sys/lib/libz/inftrees.c

46

unsigned FAR *bits, unsigned short FAR *work) {

sys/lib/libz/inftrees.h

26

unsigned char bits; /* bits in this part of the code */

sys/lib/libz/inftrees.h

62

unsigned FAR *bits, unsigned short FAR *work);

sys/lib/libz/trees.c

204

int bits; /* bit index */

sys/lib/libz/trees.c

210

for (bits = 1; bits <= MAX_BITS; bits++) {

sys/lib/libz/trees.c

211

code = (code + bl_count[bits - 1]) << 1;

sys/lib/libz/trees.c

212

next_code[bits] = (ush)code;

sys/lib/libz/trees.c

297

int bits; /* bit counter */

sys/lib/libz/trees.c

349

for (bits = 0; bits <= MAX_BITS; bits++) bl_count[bits] = 0;

sys/lib/libz/trees.c

547

int bits; /* bit length */

sys/lib/libz/trees.c

552

for (bits = 0; bits <= MAX_BITS; bits++) s->bl_count[bits] = 0;

sys/lib/libz/trees.c

561

bits = tree[tree[n].Dad].Len + 1;

sys/lib/libz/trees.c

562

if (bits > max_length) bits = max_length, overflow++;

sys/lib/libz/trees.c

563

tree[n].Len = (ush)bits;

sys/lib/libz/trees.c

568

s->bl_count[bits]++;

sys/lib/libz/trees.c

572

s->opt_len += (ulg)f * (unsigned)(bits + xbits);

sys/lib/libz/trees.c

582

bits = max_length - 1;

sys/lib/libz/trees.c

583

while (s->bl_count[bits] == 0) bits--;

sys/lib/libz/trees.c

584

s->bl_count[bits]--; /* move one leaf down the tree */

sys/lib/libz/trees.c

585

s->bl_count[bits + 1] += 2; /* move one overflow item as its brother */

sys/lib/libz/trees.c

598

for (bits = max_length; bits != 0; bits--) {

sys/lib/libz/trees.c

599

n = s->bl_count[bits];

sys/lib/libz/trees.c

603

if ((unsigned) tree[m].Len != (unsigned) bits) {

sys/lib/libz/trees.c

604

Tracev((stderr,"code %d bits %d->%d\n", m, tree[m].Len, bits));

sys/lib/libz/trees.c

605

s->opt_len += ((ulg)bits - tree[m].Len) * tree[m].Freq;

sys/lib/libz/trees.c

606

tree[m].Len = (ush)bits;

sys/lib/libz/zlib.h

1012

int bits,

sys/lib/libz/zlib.h

788

int *bits);

sys/lib/libz/zlib.h

805

int *bits);

sys/lib/libz/zlib.h

817

int bits,

sys/net/art.c

151

unsigned int bits = 0;

sys/net/art.c

174

bits += levels[i];

sys/net/art.c

176

if (alen != bits)

sys/net/art.c

177

panic("sum of levels %u != address len %u", bits, alen);

sys/net/art.c

213

art_bindex(unsigned int offset, unsigned int bits,

sys/net/art.c

220

KASSERT(plen <= (offset + bits));

sys/net/art.c

236

bend = (bits + boff);

sys/net/art.c

253

k = (addr[0] >> (8 - bend)) & ((1 << bits) - 1);

sys/net/art.c

259

return ((k >> (bits - plen)) + (1 << plen));

sys/net/art.c

287

unsigned int bits = art->art_levels[level];

sys/net/art.c

288

unsigned int p = offset + bits;

sys/net/art.c

299

j = art_bindex(offset, bits, addr, p);

sys/net/art.c

368

unsigned int bits, p;

sys/net/art.c

395

bits = art->art_levels[level];

sys/net/art.c

396

p = offset + bits;

sys/net/art.c

401

j = art_bindex(offset, bits, addr, p);

sys/net/art.c

415

i = art_bindex(offset, bits, addr, plen);

sys/net/art.c

860

unsigned int bits;

sys/net/art.c

872

bits = art->art_levels[level];

sys/net/art.c

873

switch (bits) {

sys/net/art.c

881

panic("incorrect stride length %u", bits);

sys/net/art.c

893

at->at_minfringe = (1 << bits);

sys/net/art.c

895

at->at_bits = bits;

sys/net/art.h

81

#define AT_HEAPSIZE(bits) ((1 << ((bits) + 1)) * sizeof(art_heap_entry))

sys/net/bsd-comp.c

298

int bits;

sys/net/bsd-comp.c

306

bits = BSD_NBITS(options[2]);

sys/net/bsd-comp.c

307

switch (bits) {

sys/net/bsd-comp.c

335

maxmaxcode = MAXCODE(bits);

sys/net/bsd-comp.c

356

db->maxbits = bits;

sys/net/if_aggr.c

1848

uint8_t bits = LACP_STATE_ACTIVITY | LACP_STATE_TIMEOUT |

sys/net/if_aggr.c

1875

if (ISSET(pi->lacp_state, bits) != ISSET(state, bits))

sys/sys/audioio.h

53

unsigned int bits; /* bits per sample */

sys/sys/ctf.h

135

#define _CTF_DATA(encoding, offset, bits) \

sys/sys/ctf.h

136

(((encoding) << 24) | ((offset) << 16) | (bits))

sys/sys/pledge.h

72

uint64_t bits;

sys/sys/videoio.h

2954

u_int8_t bits[2][10];

sys/sys/videoio.h

3233

u_int8_t bits;

usr.bin/aucat/afile.c

259

if (f->par.bits < BITS_MIN || f->par.bits > BITS_MAX) {

usr.bin/aucat/afile.c

260

logx(1, "%s: %u: unsupported bits per sample", f->path, f->par.bits);

usr.bin/aucat/afile.c

263

if (f->par.bits > f->par.bps * 8) {

usr.bin/aucat/afile.c

267

if (f->fmt == AFILE_FMT_FLOAT && f->par.bits != 32) {

usr.bin/aucat/afile.c

291

f->par.bits = le16_get(&fmt.bits);

usr.bin/aucat/afile.c

301

f->par.bps = (f->par.bits + 7) / 8;

usr.bin/aucat/afile.c

302

f->par.bits = le16_get(&fmt.valbits);

usr.bin/aucat/afile.c

305

f->par.bps = (f->par.bits + 7) / 8;

usr.bin/aucat/afile.c

313

f->par.sig = (f->par.bits <= 8) ? 0 : 1;

usr.bin/aucat/afile.c

317

f->par.bits = 8;

usr.bin/aucat/afile.c

322

f->par.bits = 8;

usr.bin/aucat/afile.c

412

le16_set(&hdr.fmt.bits, f->par.bits);

usr.bin/aucat/afile.c

415

le16_set(&hdr.fmt.valbits, f->par.bits);

usr.bin/aucat/afile.c

452

f->par.bits = be16_get(&comm.base.bits);

usr.bin/aucat/afile.c

455

f->par.bits = 32;

usr.bin/aucat/afile.c

458

f->par.bits = 8;

usr.bin/aucat/afile.c

461

f->par.bits = 8;

usr.bin/aucat/afile.c

468

f->par.bits = be16_get(&comm.base.bits);

usr.bin/aucat/afile.c

473

f->par.bps = (f->par.bits + 7) / 8;

usr.bin/aucat/afile.c

598

be16_set(&hdr.comm.bits, f->par.bits);

usr.bin/aucat/afile.c

61

le16_t bits;

usr.bin/aucat/afile.c

629

f->par.bits = 8;

usr.bin/aucat/afile.c

633

f->par.bits = 16;

usr.bin/aucat/afile.c

637

f->par.bits = 24;

usr.bin/aucat/afile.c

641

f->par.bits = 32;

usr.bin/aucat/afile.c

645

f->par.bits = 8;

usr.bin/aucat/afile.c

649

f->par.bits = 8;

usr.bin/aucat/afile.c

653

f->par.bits = 32;

usr.bin/aucat/afile.c

661

f->par.bps = f->par.bits / 8;

usr.bin/aucat/afile.c

685

switch (f->par.bits) {

usr.bin/aucat/afile.c

700

logx(1, "%s: %u: wrong precision", f->path, f->par.bits);

usr.bin/aucat/afile.c

874

f->par.bps = (f->par.bits + 7) >> 3;

usr.bin/aucat/afile.c

875

if (f->par.bits > 8) {

usr.bin/aucat/afile.c

880

if (f->par.bits & 7)

usr.bin/aucat/afile.c

887

f->par.bps = (f->par.bits + 7) >> 3;

usr.bin/aucat/afile.c

891

if (f->par.bits & 7)

usr.bin/aucat/afile.c

899

f->par.bits = (f->par.bits + 7) & ~7;

usr.bin/aucat/afile.c

900

f->par.bps = f->par.bits / 8;

usr.bin/aucat/afile.c

93

be16_t bits;

usr.bin/aucat/aucat.c

1340

par.bits = ADATA_BITS;

usr.bin/aucat/aucat.c

1341

par.bps = APARAMS_BPS(par.bits);

usr.bin/aucat/aucat.c

630

par.bits = ADATA_BITS;

usr.bin/aucat/aucat.c

644

dev_par.bits = par.bits;

usr.bin/aucat/dsp.c

205

if (par->bits > 9)

usr.bin/aucat/dsp.c

206

*p++ = '0' + par->bits / 10;

usr.bin/aucat/dsp.c

207

*p++ = '0' + par->bits % 10;

usr.bin/aucat/dsp.c

211

if (par->bps != APARAMS_BPS(par->bits) ||

usr.bin/aucat/dsp.c

212

par->bits < par->bps * 8) {

usr.bin/aucat/dsp.c

214

if (par->bits < par->bps * 8) {

usr.bin/aucat/dsp.c

234

int i, sig, bits, le, bps, msb;

usr.bin/aucat/dsp.c

255

bits = 0;

usr.bin/aucat/dsp.c

259

bits = (bits * 10) + *p - '0';

usr.bin/aucat/dsp.c

262

if (bits < BITS_MIN || bits > BITS_MAX)

usr.bin/aucat/dsp.c

264

bps = APARAMS_BPS(bits);

usr.bin/aucat/dsp.c

287

if (bps < (bits + 7) / 8 ||

usr.bin/aucat/dsp.c

311

par->bits = bits;

usr.bin/aucat/dsp.c

325

par->bits = ADATA_BITS;

usr.bin/aucat/dsp.c

339

par->bits == ADATA_BITS &&

usr.bin/aucat/dsp.c

341

(par->bits == par->bps * 8 || !par->msb);

usr.bin/aucat/dsp.c

657

p->shift = 32 - par->bits;

usr.bin/aucat/dsp.c

840

p->shift = 32 - par->bits;

usr.bin/aucat/dsp.h

72

#define APARAMS_BPS(bits) (((bits) <= 8) ? 1 : (((bits) <= 16) ? 2 : 4))

usr.bin/aucat/dsp.h

76

unsigned int bits; /* actually used bits */

usr.bin/audioctl/audioctl.c

119

if (ap->bps < ((ap->bits + 7) >> 3) || ap->bps > 4)

usr.bin/audioctl/audioctl.c

164

printf("%s%u", ap->sig ? "s" : "u", ap->bits);

usr.bin/audioctl/audioctl.c

168

if (ap->bps != BPS(ap->bits) || ap->bits < ap->bps * 8) {

usr.bin/audioctl/audioctl.c

170

if (ap->bits < ap->bps * 8)

usr.bin/audioctl/audioctl.c

31

#define BPS(bits) (((bits) <= 8) ? 1 : (((bits) <= 16) ? 2 : 4))

usr.bin/audioctl/audioctl.c

88

ap->bits = 0;

usr.bin/audioctl/audioctl.c

90

ap->bits = (ap->bits * 10) + *p++ - '0';

usr.bin/audioctl/audioctl.c

91

if (ap->bits > 32)

usr.bin/audioctl/audioctl.c

94

if (ap->bits < 8)

usr.bin/audioctl/audioctl.c

98

ap->bps = BPS(ap->bits);

usr.bin/cdio/rip.c

478

info->par.bits = 16;

usr.bin/cdio/rip.c

495

info->par.bits != 16 ||

usr.bin/compress/gzopen.c

348

put_header(gz_stream *s, char *name, u_int32_t mtime, int bits)

usr.bin/compress/gzopen.c

361

buf[8] = bits == 1 ? 4 : bits == 9 ? 2 : 0; /* xflags */

usr.bin/compress/gzopen.c

378

gz_wopen(int fd, char *name, int bits, u_int32_t mtime)

usr.bin/compress/gzopen.c

385

if (bits < 0 || bits > Z_BEST_COMPRESSION) {

usr.bin/compress/gzopen.c

408

if (deflateInit2(&(s->z_stream), bits, Z_DEFLATED,

usr.bin/compress/gzopen.c

420

if (put_header(s, name, mtime, bits) != 0) {

usr.bin/compress/main.c

178

int bits, ch, error, rc, cflag, oflag;

usr.bin/compress/main.c

183

bits = cflag = oflag = 0;

usr.bin/compress/main.c

188

bits = 6;

usr.bin/compress/main.c

259

bits = ch - '0';

usr.bin/compress/main.c

265

bits = strtol(optarg, &p, 10);

usr.bin/compress/main.c

286

bits = 6;

usr.bin/compress/main.c

468

error = docompress(infile, outfile, method, bits, entry->fts_statp);

usr.bin/compress/main.c

556

int bits, struct stat *sb)

usr.bin/compress/main.c

592

if ((cookie = method->wopen(ofd, name, bits, mtime)) == NULL) {

usr.bin/compress/nullopen.c

69

null_wopen(int fd, char *name, int bits, u_int32_t mtime)

usr.bin/compress/zopen.c

369

int bits;

usr.bin/compress/zopen.c

378

bits = zs->zs_n_bits;

usr.bin/compress/zopen.c

386

bits -= (8 - r_off);

usr.bin/compress/zopen.c

389

if (bits >= 8) {

usr.bin/compress/zopen.c

392

bits -= 8;

usr.bin/compress/zopen.c

395

if (bits)

usr.bin/compress/zopen.c

432

bits = zs->zs_bp - zs->zs_buf;

usr.bin/compress/zopen.c

433

if (write(zs->zs_fd, zs->zs_buf, bits) != bits)

usr.bin/compress/zopen.c

435

zs->zs_bytes_out += bits;

usr.bin/compress/zopen.c

445

bits = zs->zs_bp - zs->zs_buf;

usr.bin/compress/zopen.c

446

if (write(zs->zs_fd, zs->zs_buf, bits) != bits)

usr.bin/compress/zopen.c

448

zs->zs_bytes_out += bits;

usr.bin/compress/zopen.c

597

int r_off, bits;

usr.bin/compress/zopen.c

626

if ((bits = read(zs->zs_fd, bp, ZBUFSIZ -

usr.bin/compress/zopen.c

629

zs->zs_in_count += bits;

usr.bin/compress/zopen.c

631

zs->zs_ebp = bp + bits;

usr.bin/compress/zopen.c

643

bits = zs->zs_n_bits;

usr.bin/compress/zopen.c

651

bits -= (8 - r_off);

usr.bin/compress/zopen.c

655

if (bits >= 8) {

usr.bin/compress/zopen.c

658

bits -= 8;

usr.bin/compress/zopen.c

662

gcode |= (*bp & rmask[bits]) << r_off;

usr.bin/compress/zopen.c

733

z_wopen(int fd, char *name, int bits, u_int32_t mtime)

usr.bin/compress/zopen.c

737

if (bits < 0 || bits > BITS) {

usr.bin/compress/zopen.c

746

zs->zs_maxbits = bits ? bits : BITS;

usr.bin/ctfconv/parse.c

1063

size_t off = 0, ref = 0, bits = 0;

usr.bin/ctfconv/parse.c

1110

bits = dav2val(dav, psz);

usr.bin/ctfconv/parse.c

1111

assert(bits < USHRT_MAX);

usr.bin/ctfconv/parse.c

751

uint16_t encoding, enc = 0, bits = 0;

usr.bin/ctfconv/parse.c

760

bits = 8 * dav2val(dav, psz);

usr.bin/ctfconv/parse.c

791

if (bits < psz)

usr.bin/ctfconv/parse.c

793

else if (bits == psz)

usr.bin/ctfconv/parse.c

800

if (bits < psz)

usr.bin/ctfconv/parse.c

802

else if (bits == psz)

usr.bin/ctfconv/parse.c

809

if (bits < psz)

usr.bin/ctfconv/parse.c

811

else if (bits == psz)

usr.bin/ctfconv/parse.c

822

it = it_new(++tidx, die->die_offset, enc2name(enc), bits,

usr.bin/dc/bcode.c

697

int bits;

usr.bin/dc/bcode.c

706

bits = BN_num_bits(int_part);

usr.bin/dc/bcode.c

708

if (bits == 0)

usr.bin/dc/bcode.c

715

d = (c * bits) >> 32;

usr.bin/dc/bcode.c

718

if (d != (c * (bits - 1)) >> 32) {

usr.bin/dig/lib/dns/dst_api.c

317

unsigned int bits)

usr.bin/dig/lib/dns/dst_api.c

336

key->key_size = bits;

usr.bin/dig/lib/dns/dst_api.c

62

unsigned int bits);

usr.bin/dig/lib/dns/include/dst/dst.h

327

dst_key_setbits(dst_key_t *key, uint16_t bits);

usr.bin/dig/lib/dns/key.c

65

dst_key_setbits(dst_key_t *key, uint16_t bits) {

usr.bin/dig/lib/dns/key.c

67

if (bits != 0) {

usr.bin/dig/lib/dns/key.c

70

REQUIRE(bits <= maxbits);

usr.bin/dig/lib/dns/key.c

72

key->key_bits = bits;

usr.bin/dig/lib/dns/rdata/generic/opt_41.c

145

uint8_t bits = ~0U << (8 - (addrlen % 8));

usr.bin/dig/lib/dns/rdata/generic/opt_41.c

146

bits &= sregion.base[addrbytes - 1];

usr.bin/dig/lib/dns/rdata/generic/opt_41.c

147

if (bits != sregion.base[addrbytes - 1])

usr.bin/kdump/kdump.c

1483

for (i = 0; pledge->code && pledgenames[i].bits != 0; i++) {

usr.bin/kdump/kdump.c

1484

if (pledgenames[i].bits & pledge->code) {

usr.bin/mandoc/dbm.c

289

res.bits = iteration == ITER_NAME ? cp[-1] : 0;

usr.bin/mandoc/dbm.h

36

int32_t bits;

usr.bin/mandoc/main.c

712

page->bits = NAME_FILE & NAME_MASK;

usr.bin/mandoc/mansearch.c

172

rp->bits <= (int32_t)(NAME_SYN & NAME_MASK)))

usr.bin/mandoc/mansearch.c

199

mpage->bits = search->firstmatch ? rp->bits : 0;

usr.bin/mandoc/mansearch.c

262

if ((e->bits & ib) == 0)

usr.bin/mandoc/mansearch.c

296

rp->bits |= res.bits;

usr.bin/mandoc/mansearch.c

411

if ((diff = mp2->bits - mp1->bits) ||

usr.bin/mandoc/mansearch.c

45

uint64_t bits; /* Type mask. */

usr.bin/mandoc/mansearch.c

743

e->bits = 0;

usr.bin/mandoc/mansearch.c

748

e->bits = TYPE_Nm;

usr.bin/mandoc/mansearch.c

760

e->bits = TYPE_Nm;

usr.bin/mandoc/mansearch.c

765

e->bits = TYPE_Nm | TYPE_Nd;

usr.bin/mandoc/mansearch.c

771

e->bits = TYPE_Nm | TYPE_Nd;

usr.bin/mandoc/mansearch.c

802

if (e->bits) {

usr.bin/mandoc/mansearch.c

817

e->bits |= iterbit;

usr.bin/mandoc/mansearch.c

825

e->bits |= ~0ULL;

usr.bin/mandoc/mansearch.h

95

uint64_t bits; /* name type mask */

usr.bin/netstat/show.c

404

const struct bits *p = bits;

usr.bin/netstat/show.c

72

static const struct bits bits[] = {

usr.bin/openssl/prime.c

149

if (cfg.bits == 0) {

usr.bin/openssl/prime.c

158

if (!BN_generate_prime_ex(bn, cfg.bits,

usr.bin/openssl/prime.c

60

int bits;

usr.bin/openssl/prime.c

73

.opt.value = &cfg.bits,

usr.bin/openssl/speed.c

157

int bits, int sec);

usr.bin/openssl/speed.c

2403

int bits = p->bits;

usr.bin/openssl/speed.c

2414

pkey_print_message("keygen", "mlkem", bits, MLKEM_SECONDS);

usr.bin/openssl/speed.c

2438

: "%ld %d-bit ML-KEM keygen in %.2fs\n", count, bits, d);

usr.bin/openssl/speed.c

245

int bits;

usr.bin/openssl/speed.c

2452

pkey_print_message("encap", "mlkem", bits, MLKEM_SECONDS);

usr.bin/openssl/speed.c

2467

: "%ld %d-bit ML-KEM encap in %.2fs\n", count, bits, d);

usr.bin/openssl/speed.c

2476

pkey_print_message("decap", "mlkem", bits, MLKEM_SECONDS);

usr.bin/openssl/speed.c

2488

: "%ld %d-bit ML-KEM decap in %.2fs\n", count, bits, d);

usr.bin/openssl/speed.c

2636

mlkem_params[k].bits,

usr.bin/openssl/speed.c

2643

mlkem_params[k].bits,

usr.bin/openssl/speed.c

2687

int bits, int tm)

usr.bin/openssl/speed.c

2690

: "Doing %d bit %s %s for %ds: ", bits, str, str2, tm);

usr.bin/openssl/ts.c

737

create_nonce(int bits)

usr.bin/openssl/ts.c

744

if (!BN_rand(bn, bits, BN_RAND_TOP_ANY, BN_RAND_BOTTOM_ANY))

usr.bin/openssl/ts.c

92

static ASN1_INTEGER *create_nonce(int bits);

usr.bin/sndiod/dsp.c

136

if (par->bits > 9)

usr.bin/sndiod/dsp.c

137

*p++ = '0' + par->bits / 10;

usr.bin/sndiod/dsp.c

138

*p++ = '0' + par->bits % 10;

usr.bin/sndiod/dsp.c

142

if (par->bps != APARAMS_BPS(par->bits) ||

usr.bin/sndiod/dsp.c

143

par->bits < par->bps * 8) {

usr.bin/sndiod/dsp.c

145

if (par->bits < par->bps * 8) {

usr.bin/sndiod/dsp.c

165

int i, sig, bits, le, bps, msb;

usr.bin/sndiod/dsp.c

186

bits = 0;

usr.bin/sndiod/dsp.c

190

bits = (bits * 10) + *p - '0';

usr.bin/sndiod/dsp.c

193

if (bits < BITS_MIN || bits > BITS_MAX)

usr.bin/sndiod/dsp.c

195

bps = APARAMS_BPS(bits);

usr.bin/sndiod/dsp.c

218

if (bps < (bits + 7) / 8 ||

usr.bin/sndiod/dsp.c

242

par->bits = bits;

usr.bin/sndiod/dsp.c

256

par->bits = ADATA_BITS;

usr.bin/sndiod/dsp.c

270

par->bits == ADATA_BITS &&

usr.bin/sndiod/dsp.c

272

(par->bits == par->bps * 8 || !par->msb);

usr.bin/sndiod/dsp.c

588

p->shift = 32 - par->bits;

usr.bin/sndiod/dsp.c

676

p->shift = 32 - par->bits;

usr.bin/sndiod/dsp.h

72

#define APARAMS_BPS(bits) (((bits) <= 8) ? 1 : (((bits) <= 16) ? 2 : 4))

usr.bin/sndiod/dsp.h

76

unsigned int bits; /* actually used bits */

usr.bin/sndiod/siofile.c

133

par.bits = d->par.bits;

usr.bin/sndiod/siofile.c

158

par.bits = d->par.bits;

usr.bin/sndiod/siofile.c

185

if (par.bits > BITS_MAX) {

usr.bin/sndiod/siofile.c

186

logx(0, "%s: %u: unsupported number of bits", d->path, par.bits);

usr.bin/sndiod/siofile.c

215

d->par.bits = par.bits;

usr.bin/sndiod/sndiod.c

544

par.bits = DEFAULT_BITS;

usr.bin/sndiod/sndiod.c

545

par.bps = APARAMS_BPS(par.bits);

usr.bin/sndiod/sock.c

600

if (AMSG_ISSET(p->bits)) {

usr.bin/sndiod/sock.c

601

if (p->bits < BITS_MIN || p->bits > BITS_MAX) {

usr.bin/sndiod/sock.c

603

logx(1, "sock %d: %d: bits out of bounds", f->fd, p->bits);

usr.bin/sndiod/sock.c

608

if (p->bps < ((p->bits + 7) / 8) || p->bps > 4) {

usr.bin/sndiod/sock.c

616

p->bps = APARAMS_BPS(p->bits);

usr.bin/sndiod/sock.c

617

s->par.bits = p->bits;

usr.bin/sndiod/sock.c

991

m->u.par.bits = s->par.bits;

usr.bin/ssh/bitmap.c

141

size_t bits;

usr.bin/ssh/bitmap.c

151

bits = (b->top + 1) * BITMAP_BITS;

usr.bin/ssh/bitmap.c

154

bits--;

usr.bin/ssh/bitmap.c

156

return bits;

usr.bin/ssh/dh.c

488

dh_estimate(int bits)

usr.bin/ssh/dh.c

490

if (bits <= 112)

usr.bin/ssh/dh.c

492

if (bits <= 128)

usr.bin/ssh/dh.c

494

if (bits <= 192)

usr.bin/ssh/kexgexc.c

103

if ((bits = BN_num_bits(p)) < 0 ||

usr.bin/ssh/kexgexc.c

104

(u_int)bits < kex->min || (u_int)bits > kex->max) {

usr.bin/ssh/kexgexc.c

94

int r, bits;

usr.bin/ssh/srclimit.c

131

int i, bits, first_unused, count = 0;

usr.bin/ssh/srclimit.c

140

bits = xa.af == AF_INET ? ipv4_masklen : ipv6_masklen;

usr.bin/ssh/srclimit.c

141

if (srclimit_mask_addr(&xa, bits, &xb) != 0)

usr.bin/ssh/srclimit.c

159

__func__, xas, bits, count, max_persource);

usr.bin/ssh/srclimit.c

262

int bits, max_sources, overflow_mode;

usr.bin/ssh/srclimit.c

292

bits = addr.af == AF_INET ? ipv4_masklen : ipv6_masklen;

usr.bin/ssh/srclimit.c

294

if (srclimit_mask_addr(&addr, bits, &find.addr) != 0)

usr.bin/ssh/srclimit.c

314

int bits;

usr.bin/ssh/srclimit.c

321

bits = p->addr.af == AF_INET ? ipv4_masklen : ipv6_masklen;

usr.bin/ssh/srclimit.c

322

addr_masklen_ntop(&p->addr, bits, s, sizeof(s));

usr.bin/ssh/srclimit.c

349

int bits, max_sources = 0, overflow_mode;

usr.bin/ssh/srclimit.c

402

bits = addr->af == AF_INET ? ipv4_masklen : ipv6_masklen;

usr.bin/ssh/srclimit.c

403

if (srclimit_mask_addr(addr, bits, &masked) != 0)

usr.bin/ssh/srclimit.c

405

addr_masklen_ntop(addr, bits, addrnetmask, sizeof(addrnetmask));

usr.bin/ssh/srclimit.c

475

int bits;

usr.bin/ssh/srclimit.c

482

bits = p->addr.af == AF_INET ? ipv4_masklen : ipv6_masklen;

usr.bin/ssh/srclimit.c

483

addr_masklen_ntop(&p->addr, bits, s, sizeof(s));

usr.bin/ssh/srclimit.c

69

srclimit_mask_addr(const struct xaddr *addr, int bits, struct xaddr *masked)

usr.bin/ssh/srclimit.c

74

if (addr_netmask(addr->af, bits, &xmask) != 0 ||

usr.bin/ssh/srclimit.c

76

debug3_f("%s: invalid mask %d bits", __func__, bits);

usr.bin/ssh/ssh-ecdsa.c

157

ssh_ecdsa_generate(struct sshkey *k, int bits)

usr.bin/ssh/ssh-ecdsa.c

163

if ((k->ecdsa_nid = sshkey_ecdsa_bits_to_nid(bits)) == -1)

usr.bin/ssh/ssh-ed25519.c

79

ssh_ed25519_generate(struct sshkey *k, int bits)

usr.bin/ssh/ssh-keygen.c

1001

uint32_t bits = 0;

usr.bin/ssh/ssh-keygen.c

1049

bits = 0;

usr.bin/ssh/ssh-keygen.c

1050

type_bits_valid(type, NULL, &bits);

usr.bin/ssh/ssh-keygen.c

1051

if ((r = sshkey_generate(type, bits, &private)) != 0) {

usr.bin/ssh/ssh-keygen.c

3288

uint32_t bits = 0;

usr.bin/ssh/ssh-keygen.c

3323

bits = (uint32_t)strtonum(optarg, 1, UINT32_MAX,

usr.bin/ssh/ssh-keygen.c

3748

type_bits_valid(type, key_type_name, &bits);

usr.bin/ssh/ssh-keygen.c

3833

if ((r = sshkey_generate(type, bits, &private)) != 0)

usr.bin/ssh/ssh-pkcs11.c

1631

char *label, CK_ULONG bits, CK_BYTE keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.c

1659

FILL_ATTR(tpub, npub, CKA_MODULUS_BITS, &bits, sizeof(bits));

usr.bin/ssh/ssh-pkcs11.c

1749

char *label, CK_ULONG bits, CK_BYTE keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.c

1770

if (ec_curve_infos[i].size == bits)

usr.bin/ssh/ssh-pkcs11.c

1774

error_f("invalid key size %lu", bits);

usr.bin/ssh/ssh-pkcs11.c

2079

unsigned int type, unsigned int bits, unsigned char keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.c

2114

bits, keyid, err)) == NULL) {

usr.bin/ssh/ssh-pkcs11.c

2121

bits, keyid, err)) == NULL) {

usr.bin/ssh/ssh-rsa.c

114

ssh_rsa_generate(struct sshkey *k, int bits)

usr.bin/ssh/ssh-rsa.c

121

if (bits < SSH_RSA_MINIMUM_MODULUS_SIZE ||

usr.bin/ssh/ssh-rsa.c

122

bits > SSHBUF_MAX_BIGNUM * 8)

usr.bin/ssh/ssh-rsa.c

133

if (EVP_PKEY_CTX_set_rsa_keygen_bits(ctx, bits) <= 0) {

usr.bin/ssh/sshkey.c

1451

sshkey_generate(int type, u_int bits, struct sshkey **keyp)

usr.bin/ssh/sshkey.c

1467

if ((ret = impl->funcs->generate(k, bits)) != 0) {

usr.bin/ssh/sshkey.c

575

sshkey_ecdsa_bits_to_nid(int bits)

usr.bin/ssh/sshkey.c

577

switch (bits) {

usr.bin/ssh/sshkey.h

195

int sshkey_generate(int type, u_int bits, struct sshkey **keyp);

usr.bin/tic/dump_entry.c

890

int bits = sizeof(unsigned long) * 8;

usr.bin/tic/dump_entry.c

893

for (nn = 8; nn < bits; ++nn) {

usr.sbin/bgpd/config.c

561

int bits;

usr.sbin/bgpd/config.c

572

if ((bits = inet_net_pton(AF_INET, s, &h->v4,

usr.sbin/bgpd/config.c

575

*len = bits;

usr.sbin/bgpd/flowspec.c

517

fmt_flags(uint64_t val, const char *bits, char *buf, size_t blen)

usr.sbin/bgpd/flowspec.c

523

if (bits[i] == '\0' || bits[i] == ' ')

usr.sbin/bgpd/flowspec.c

525

buf[bi++] = bits[i];

usr.sbin/bgpd/flowspec.c

539

const char *bits)

usr.sbin/bgpd/flowspec.c

578

fmt_flags(val, bits, bit, sizeof(bit)),

usr.sbin/bgpd/flowspec.c

579

fmt_flags(val2, bits, mask, sizeof(mask)));

usr.sbin/bgpd/flowspec.c

584

fmt_flags(val, bits, bit, sizeof(bit)));

usr.sbin/bgpd/flowspec.c

588

fmt_flags(val, bits, mask, sizeof(mask)));

usr.sbin/bgpd/flowspec.c

592

fmt_flags(val, bits, bit, sizeof(bit)),

usr.sbin/bgpd/flowspec.c

593

fmt_flags(val, bits, mask, sizeof(mask)));

usr.sbin/cron/entry.c

430

get_list(bitstr_t *bits, int low, int high, const char *names[],

usr.sbin/cron/entry.c

446

bit_nclear(bits, 0, high - low);

usr.sbin/cron/entry.c

452

if ((ch = get_range(bits, low, high, names, ch, file)) == EOF)

usr.sbin/cron/entry.c

470

get_range(bitstr_t *bits, int low, int high, const char *names[],

usr.sbin/cron/entry.c

555

if (set_element(bits, low, high, num1) == EOF) {

usr.sbin/cron/entry.c

600

if (set_range(bits, low, high, num1, num2, num3) == EOF) {

usr.sbin/cron/entry.c

664

set_element(bitstr_t *bits, int low, int high, int number)

usr.sbin/cron/entry.c

671

bit_set(bits, number);

usr.sbin/cron/entry.c

676

set_range(bitstr_t *bits, int low, int high, int start, int stop, int step)

usr.sbin/cron/entry.c

686

bit_nset(bits, start, stop);

usr.sbin/cron/entry.c

691

bit_set(bits, i);

usr.sbin/dvmrpctl/parser.c

278

int bits = 32;

usr.sbin/dvmrpctl/parser.c

287

if ((bits = inet_net_pton(AF_INET, word,

usr.sbin/dvmrpctl/parser.c

290

addr->s_addr = ina.s_addr & htonl(0xffffffff << (32 - bits));

usr.sbin/dvmrpctl/parser.c

291

*prefixlen = bits;

usr.sbin/httpd/httpd.c

1221

printb_flags(const uint32_t v, const char *bits)

usr.sbin/httpd/httpd.c

1231

if (bits) {

usr.sbin/httpd/httpd.c

1232

bits++;

usr.sbin/httpd/httpd.c

1233

while ((i = *bits++)) {

usr.sbin/httpd/httpd.c

1240

for (; (c = *bits) > 32; bits++) {

usr.sbin/httpd/httpd.c

1248

for (; *bits > 32; bits++)

usr.sbin/mrouted/inet.c

124

int bits;

usr.sbin/mrouted/inet.c

132

bits = 33 - ffs(ntohl(mask));

usr.sbin/mrouted/inet.c

135

snprintf(s, SNAMLEN, "%u.%u.%u.%u/%d", a[0], a[1], a[2], a[3], bits);

usr.sbin/mrouted/inet.c

137

snprintf(s, SNAMLEN, "%u.%u.%u/%d", a[0], a[1], a[2], bits);

usr.sbin/mrouted/inet.c

139

snprintf(s, SNAMLEN, "%u.%u/%d", a[0], a[1], bits);

usr.sbin/mrouted/inet.c

141

snprintf(s, SNAMLEN, "%u/%d", a[0], bits);

usr.sbin/npppd/npppd/mppe.c

536

mppe_bits_to_string(uint32_t bits)

usr.sbin/npppd/npppd/mppe.c

541

, ((CCP_MPPC_ALONE & bits) != 0)? ",mppc" : ""

usr.sbin/npppd/npppd/mppe.c

542

, ((CCP_MPPE_LM_40bit& bits) != 0)? ",40bit(LM)" : ""

usr.sbin/npppd/npppd/mppe.c

543

, ((CCP_MPPE_NT_40bit& bits) != 0)? ",40bit" : ""

usr.sbin/npppd/npppd/mppe.c

544

, ((CCP_MPPE_NT_128bit& bits) != 0)? ",128bit" : ""

usr.sbin/npppd/npppd/mppe.c

545

, ((CCP_MPPE_NT_56bit& bits) != 0)? ",56bit" : ""

usr.sbin/npppd/npppd/mppe.c

546

, ((CCP_MPPE_STATELESS& bits) != 0)? ",stateless" : ",stateful");

usr.sbin/npppd/pptp/pptp_subr.c

49

pptp_framing_string(uint32_t bits)

usr.sbin/npppd/pptp/pptp_subr.c

54

(bits & PPTP_CTRL_FRAMING_ASYNC)? ",async" : "",

usr.sbin/npppd/pptp/pptp_subr.c

55

(bits & PPTP_CTRL_FRAMING_SYNC)? ",sync" : "");

usr.sbin/npppd/pptp/pptp_subr.c

66

pptp_bearer_string(uint32_t bits)

usr.sbin/npppd/pptp/pptp_subr.c

71

(bits &PPTP_CTRL_BEARER_ANALOG)? ",analog" : "",

usr.sbin/npppd/pptp/pptp_subr.c

72

(bits &PPTP_CTRL_BEARER_DIGITAL)? ",digital" : "");

usr.sbin/nsd/bitset.c

104

bits |= (srcset2->bits[i] & mask);

usr.sbin/nsd/bitset.c

107

destset->bits[i] = bits;

usr.sbin/nsd/bitset.c

16

size_t nsd_bitset_size(size_t bits)

usr.sbin/nsd/bitset.c

18

if(bits == 0)

usr.sbin/nsd/bitset.c

19

bits++;

usr.sbin/nsd/bitset.c

21

return (bits / CHAR_BIT) + ((bits % CHAR_BIT) != 0) + sizeof(size_t);

usr.sbin/nsd/bitset.c

32

memset(bset->bits, 0, sz);

usr.sbin/nsd/bitset.c

35

void nsd_bitset_init(struct nsd_bitset *bset, size_t bits)

usr.sbin/nsd/bitset.c

38

if (bits == 0)

usr.sbin/nsd/bitset.c

39

bits++;

usr.sbin/nsd/bitset.c

41

bset->size = bits;

usr.sbin/nsd/bitset.c

51

return (bset->bits[ (bit / CHAR_BIT) ] & (1 << (bit % CHAR_BIT))) != 0;

usr.sbin/nsd/bitset.c

58

bset->bits[ (bit / CHAR_BIT) ] |= (1 << (bit % CHAR_BIT));

usr.sbin/nsd/bitset.c

65

bset->bits[ (bit / CHAR_BIT) ] &= ~(1 << (bit % CHAR_BIT));

usr.sbin/nsd/bitset.c

74

unsigned char bits;

usr.sbin/nsd/bitset.c

85

bits = 0;

usr.sbin/nsd/bitset.c

89

bits |= srcset1->bits[i];

usr.sbin/nsd/bitset.c

94

bits |= (srcset1->bits[i] & mask);

usr.sbin/nsd/bitset.c

99

bits |= srcset2->bits[i];

usr.sbin/nsd/bitset.h

20

unsigned char bits[];

usr.sbin/nsd/bitset.h

23

size_t nsd_bitset_size(size_t bits);

usr.sbin/nsd/bitset.h

27

void nsd_bitset_init(struct nsd_bitset *bset, size_t bits);

usr.sbin/nsd/mini_event.c

225

short bits = 0;

usr.sbin/nsd/mini_event.c

230

bits |= EV_READ;

usr.sbin/nsd/mini_event.c

234

bits |= EV_WRITE;

usr.sbin/nsd/mini_event.c

237

bits &= base->fds[i]->ev_flags;

usr.sbin/nsd/mini_event.c

238

if(bits) {

usr.sbin/nsd/mini_event.c

240

bits, base->fds[i]->ev_arg);

usr.sbin/nsd/mini_event.c

323

event_set(struct event* ev, int fd, short bits,

usr.sbin/nsd/mini_event.c

328

ev->ev_flags = bits;

usr.sbin/nsd/rdata.c

1553

int bits;

usr.sbin/nsd/rdata.c

1570

bits = (rr->rdlength - 5) * 8;

usr.sbin/nsd/rdata.c

1572

for (int service = 0; service < bits; service++) {

usr.sbin/nsd/simdzone/src/generic/endian.h

176

# define htobe(bits, x) bswap ## bits((x))

usr.sbin/nsd/simdzone/src/generic/endian.h

177

# define htole(bits, x) (x)

usr.sbin/nsd/simdzone/src/generic/endian.h

178

# define betoh(bits, x) bswap ## bits((x))

usr.sbin/nsd/simdzone/src/generic/endian.h

179

# define letoh(bits, x) (x)

usr.sbin/nsd/simdzone/src/generic/endian.h

181

# define htobe(bits, x) (x)

usr.sbin/nsd/simdzone/src/generic/endian.h

182

# define htole(bits, x) bswap ## bits((x))

usr.sbin/nsd/simdzone/src/generic/endian.h

183

# define betoh(bits, x) (x)

usr.sbin/nsd/simdzone/src/generic/endian.h

184

# define letoh(bits, x) bswap ## bits((x))

usr.sbin/nsd/simdzone/src/haswell/bits.h

25

static inline uint64_t count_ones(uint64_t bits) {

usr.sbin/nsd/simdzone/src/haswell/bits.h

26

return (uint64_t)_mm_popcnt_u64(bits);

usr.sbin/nsd/simdzone/src/haswell/bits.h

30

static inline uint64_t trailing_zeroes(uint64_t bits) {

usr.sbin/nsd/simdzone/src/haswell/bits.h

31

return (uint64_t)_tzcnt_u64(bits);

usr.sbin/nsd/simdzone/src/haswell/bits.h

35

static inline uint64_t clear_lowest_bit(uint64_t bits) {

usr.sbin/nsd/simdzone/src/haswell/bits.h

36

return bits & (bits - 1);

usr.sbin/nsd/simdzone/src/haswell/bits.h

39

static inline uint64_t leading_zeroes(uint64_t bits) {

usr.sbin/nsd/simdzone/src/haswell/bits.h

40

return (uint64_t)_lzcnt_u64(bits);

usr.sbin/nsd/util.c

256

set_bit(uint8_t bits[], size_t index)

usr.sbin/nsd/util.c

262

bits[index / 8] |= (1 << (7 - index % 8));

usr.sbin/nsd/util.c

266

clear_bit(uint8_t bits[], size_t index)

usr.sbin/nsd/util.c

272

bits[index / 8] &= ~(1 << (7 - index % 8));

usr.sbin/nsd/util.c

276

get_bit(const uint8_t bits[], size_t index)

usr.sbin/nsd/util.c

282

return bits[index / 8] & (1 << (7 - index % 8));

usr.sbin/nsd/util.h

124

void set_bit(uint8_t bits[], size_t index);

usr.sbin/nsd/util.h

129

void clear_bit(uint8_t bits[], size_t index);

usr.sbin/nsd/util.h

134

int get_bit(const uint8_t bits[], size_t index);

usr.sbin/ospf6d/database.c

100

bits &= ~OSPF_DBD_MS;

usr.sbin/ospf6d/database.c

101

bits &= ~OSPF_DBD_M;

usr.sbin/ospf6d/database.c

102

bits &= ~OSPF_DBD_I;

usr.sbin/ospf6d/database.c

134

dd_hdr.bits = bits;

usr.sbin/ospf6d/database.c

182

nbr->last_rx_bits == dd_hdr.bits &&

usr.sbin/ospf6d/database.c

213

if (dd_hdr.bits == (OSPF_DBD_I | OSPF_DBD_M | OSPF_DBD_MS)) {

usr.sbin/ospf6d/database.c

224

} else if (!(dd_hdr.bits & (OSPF_DBD_I | OSPF_DBD_MS))) {

usr.sbin/ospf6d/database.c

256

if (dd_hdr.bits & OSPF_DBD_I ||

usr.sbin/ospf6d/database.c

257

!(dd_hdr.bits & OSPF_DBD_MS) == !nbr->dd_master) {

usr.sbin/ospf6d/database.c

327

if (!(dd_hdr.bits & OSPF_DBD_M) &&

usr.sbin/ospf6d/database.c

337

nbr->last_rx_bits = dd_hdr.bits;

usr.sbin/ospf6d/database.c

44

u_int8_t bits = 0;

usr.sbin/ospf6d/database.c

68

bits |= OSPF_DBD_MS | OSPF_DBD_M | OSPF_DBD_I;

usr.sbin/ospf6d/database.c

73

bits |= OSPF_DBD_MS;

usr.sbin/ospf6d/database.c

75

bits &= ~OSPF_DBD_MS;

usr.sbin/ospf6d/database.c

78

bits &= ~OSPF_DBD_M;

usr.sbin/ospf6d/database.c

81

bits |= OSPF_DBD_M;

usr.sbin/ospf6d/database.c

85

bits &= ~OSPF_DBD_I;

usr.sbin/ospf6d/database.c

98

bits |= OSPF_DBD_MS;

usr.sbin/ospf6d/ospf6.h

138

u_int8_t bits;

usr.sbin/ospfctl/parser.c

350

int bits = 32;

usr.sbin/ospfctl/parser.c

359

if ((bits = inet_net_pton(AF_INET, word,

usr.sbin/ospfctl/parser.c

362

addr->s_addr = ina.s_addr & htonl(prefixlen2mask(bits));

usr.sbin/ospfctl/parser.c

363

*prefixlen = bits;

usr.sbin/ospfd/database.c

101

bits |= OSPF_DBD_MS;

usr.sbin/ospfd/database.c

103

bits &= ~OSPF_DBD_MS;

usr.sbin/ospfd/database.c

104

bits &= ~OSPF_DBD_M;

usr.sbin/ospfd/database.c

105

bits &= ~OSPF_DBD_I;

usr.sbin/ospfd/database.c

140

dd_hdr.bits = bits;

usr.sbin/ospfd/database.c

188

nbr->last_rx_bits == dd_hdr.bits &&

usr.sbin/ospfd/database.c

226

if (dd_hdr.bits == (OSPF_DBD_I | OSPF_DBD_M | OSPF_DBD_MS)) {

usr.sbin/ospfd/database.c

237

} else if (!(dd_hdr.bits & (OSPF_DBD_I | OSPF_DBD_MS))) {

usr.sbin/ospfd/database.c

269

if (dd_hdr.bits & OSPF_DBD_I ||

usr.sbin/ospfd/database.c

270

!(dd_hdr.bits & OSPF_DBD_MS) == !nbr->dd_master) {

usr.sbin/ospfd/database.c

340

if (!(dd_hdr.bits & OSPF_DBD_M) &&

usr.sbin/ospfd/database.c

350

nbr->last_rx_bits = dd_hdr.bits;

usr.sbin/ospfd/database.c

46

u_int8_t bits = 0;

usr.sbin/ospfd/database.c

70

bits |= OSPF_DBD_MS | OSPF_DBD_M | OSPF_DBD_I;

usr.sbin/ospfd/database.c

75

bits |= OSPF_DBD_MS;

usr.sbin/ospfd/database.c

77

bits &= ~OSPF_DBD_MS;

usr.sbin/ospfd/database.c

80

bits &= ~OSPF_DBD_M;

usr.sbin/ospfd/database.c

83

bits |= OSPF_DBD_M;

usr.sbin/ospfd/database.c

87

bits &= ~OSPF_DBD_I;

usr.sbin/ospfd/ospf.h

162

u_int8_t bits;

usr.sbin/ospfd/parse.y

1495

int bits = 32;

usr.sbin/ospfd/parse.y

1499

if ((bits = inet_net_pton(AF_INET, s, &ina, sizeof(ina))) == -1)

usr.sbin/ospfd/parse.y

1507

mask->s_addr = prefixlen2mask(bits);

usr.sbin/relayd/util.c

245

printb_flags(const u_int32_t v, const char *bits)

usr.sbin/relayd/util.c

255

if (bits) {

usr.sbin/relayd/util.c

256

bits++;

usr.sbin/relayd/util.c

257

while ((i = *bits++)) {

usr.sbin/relayd/util.c

264

for (; (c = *bits) > 32; bits++) {

usr.sbin/relayd/util.c

271

for (; *bits > 32; bits++)

usr.sbin/ripctl/parser.c

285

int bits = 32;

usr.sbin/ripctl/parser.c

294

if ((bits = inet_net_pton(AF_INET, word,

usr.sbin/ripctl/parser.c

297

addr->s_addr = ina.s_addr & htonl(prefixlen2mask(bits));

usr.sbin/ripctl/parser.c

298

*prefixlen = bits;

usr.sbin/ripd/parse.y

927

int bits = 32;

usr.sbin/ripd/parse.y

931

if ((bits = inet_net_pton(AF_INET, s, &ina, sizeof(ina))) == -1)

usr.sbin/ripd/parse.y

939

mask->s_addr = prefixlen2mask(bits);

usr.sbin/sasyncd/conf.y

223

int bits;

usr.sbin/sasyncd/conf.y

225

bits = cfgstate.sharedkey_len;

usr.sbin/sasyncd/conf.y

226

if (bits != 128 && bits != 192 && bits != 256) {

usr.sbin/sasyncd/conf.y

228

"should be 128, 192 or 256 bits\n", bits);

usr.sbin/smtpd/smtpd.h

117

int bits;

usr.sbin/smtpd/table.c

448

for (i = 0; i < ssmask->bits; ++i)

usr.sbin/smtpd/table.c

469

for (i = 0; i < ssmask->bits / 8; i++)

usr.sbin/smtpd/table.c

471

i = ssmask->bits % 8;

usr.sbin/smtpd/table.c

473

mask.s6_addr[ssmask->bits / 8] = 0xff00 >> i;

usr.sbin/smtpd/to.c

224

int bits;

usr.sbin/smtpd/to.c

234

bits = inet_net_pton(AF_INET, s, &ssin.sin_addr,

usr.sbin/smtpd/to.c

236

if (bits != -1) {

usr.sbin/smtpd/to.c

255

bits = inet_net_pton(AF_INET6, buf, &ssin6.sin6_addr,

usr.sbin/smtpd/to.c

257

if (bits == -1)

usr.sbin/smtpd/to.c

265

netaddr->bits = bits;

usr.sbin/snmpd/mib.y

655

| bits

usr.sbin/snmpd/mib.y

899

bits : BITS '{' namedbits '}'

usr.sbin/tcpdump/pf_print_state.c

107

int bits = unmask(&addr->v.a.mask);

usr.sbin/tcpdump/pf_print_state.c

109

if (bits != (af == AF_INET ? 32 : 128))

usr.sbin/tcpdump/pf_print_state.c

110

printf("/%d", bits);

usr.sbin/tcpdump/print-ospf.c

102

ospf_print_bits(const struct bits *bp, u_char options)

usr.sbin/tcpdump/print-ospf.c

47

static const struct bits ospf_option_bits[] = {

usr.sbin/tcpdump/print-ospf.c

54

static const struct bits ospf_rla_flag_bits[] = {

usr.sbin/tcpdump/print-ospf.c

76

static inline void ospf_print_bits(const struct bits *, u_char);

usr.sbin/tcpdump/print-ospf6.c

106

ospf6_print_bits(const struct bits *bp, u_char options)

usr.sbin/tcpdump/print-ospf6.c

48

static const struct bits ospf6_option_bits[] = {

usr.sbin/tcpdump/print-ospf6.c

58

static const struct bits ospf6_rla_flag_bits[] = {

usr.sbin/tcpdump/print-ospf6.c

80

static inline void ospf6_print_bits(const struct bits *, u_char);

usr.sbin/tcpdump/util.c

318

printb(char *s, unsigned short v, char *bits)

usr.sbin/tcpdump/util.c

323

if (bits && *bits == 8)

usr.sbin/tcpdump/util.c

328

if (bits) {

usr.sbin/tcpdump/util.c

329

bits++;

usr.sbin/tcpdump/util.c

331

while ((i = *bits++)) {

usr.sbin/tcpdump/util.c

336

for (; (c = *bits) > 32; bits++)

usr.sbin/tcpdump/util.c

339

for (; *bits > 32; bits++)

usr.sbin/unbound/cachedb/cachedb.c

388

edns.bits = EDNS_DO;

usr.sbin/unbound/daemon/remote.c

7824

void fast_reload_service_cb(int ATTR_UNUSED(fd), short ATTR_UNUSED(bits),

usr.sbin/unbound/daemon/remote.h

361

void fast_reload_service_cb(int fd, short bits, void* arg);

usr.sbin/unbound/daemon/stats.c

581

if( (edns->bits & EDNS_DO) )

usr.sbin/unbound/daemon/worker.c

1194

edns->bits &= EDNS_DO;

usr.sbin/unbound/daemon/worker.c

596

edns->bits &= EDNS_DO;

usr.sbin/unbound/daemon/worker.c

634

edns->bits &= EDNS_DO;

usr.sbin/unbound/daemon/worker.c

635

if(worker->env.cfg->disable_edns_do && (edns->bits & EDNS_DO))

usr.sbin/unbound/daemon/worker.c

654

udpsize, edns, (int)(edns->bits & EDNS_DO), secure)) {

usr.sbin/unbound/daemon/worker.c

798

edns->bits &= EDNS_DO;

usr.sbin/unbound/daemon/worker.c

799

if(worker->env.cfg->disable_edns_do && (edns->bits & EDNS_DO))

usr.sbin/unbound/daemon/worker.c

840

edns->bits &= EDNS_DO;

usr.sbin/unbound/daemon/worker.c

841

if(worker->env.cfg->disable_edns_do && (edns->bits & EDNS_DO))

usr.sbin/unbound/daemon/worker.c

893

udpsize, edns, (int)(edns->bits & EDNS_DO),

usr.sbin/unbound/daemon/worker.c

974

edns->bits &= EDNS_DO;

usr.sbin/unbound/dnstap/dtstream.c

1485

void dtio_output_cb(int ATTR_UNUSED(fd), short bits, void* arg)

usr.sbin/unbound/dnstap/dtstream.c

1512

if((bits&UB_EV_READ) || dtio->ssl_brief_write) {

usr.sbin/unbound/dnstap/dtstream.c

1579

void dtio_cmd_cb(int fd, short ATTR_UNUSED(bits), void* arg)

usr.sbin/unbound/dnstap/dtstream.c

1723

void dtio_stop_timer_cb(int ATTR_UNUSED(fd), short ATTR_UNUSED(bits),

usr.sbin/unbound/dnstap/dtstream.c

1734

void dtio_stop_ev_cb(int ATTR_UNUSED(fd), short bits, void* arg)

usr.sbin/unbound/dnstap/dtstream.c

1764

if((bits&UB_EV_READ)) {

usr.sbin/unbound/dnstap/dtstream.c

564

short ATTR_UNUSED(bits), void* arg)

usr.sbin/unbound/dnstap/dtstream.h

334

void dtio_reconnect_timeout_cb(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/dtstream.h

337

void dtio_output_cb(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/dtstream.h

340

void dtio_cmd_cb(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/dtstream.h

343

void dtio_stop_timer_cb(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/dtstream.h

346

void dtio_stop_ev_cb(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/dtstream.h

349

void dtio_tap_callback(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/dtstream.h

352

void dtio_mainfdcallback(int fd, short bits, void* arg);

usr.sbin/unbound/dnstap/unbound-dnstap-socket.c

1047

void dtio_tap_callback(int ATTR_UNUSED(fd), short ATTR_UNUSED(bits), void* arg)

usr.sbin/unbound/dnstap/unbound-dnstap-socket.c

1146

void dtio_mainfdcallback(int fd, short ATTR_UNUSED(bits), void* arg)

usr.sbin/unbound/libunbound/libworker.c

591

edns->bits = EDNS_DO;

usr.sbin/unbound/libunbound/unbound-event.h

98

int fd, short bits, void (*cb)(int, short, void*), void* arg);

usr.sbin/unbound/services/authzone.c

3525

edns->bits &= EDNS_DO;

usr.sbin/unbound/services/authzone.c

3533

(int)(edns->bits&EDNS_DO), 0)) {

usr.sbin/unbound/services/authzone.c

3549

edns->bits &= EDNS_DO;

usr.sbin/unbound/services/authzone.c

5452

edns.bits = EDNS_DO;

usr.sbin/unbound/services/authzone.c

6647

edns.bits = EDNS_DO;

usr.sbin/unbound/services/authzone.c

8469

edns.bits = EDNS_DO;

usr.sbin/unbound/services/localzone.c

1331

edns->bits &= EDNS_DO;

usr.sbin/unbound/services/localzone.c

1335

buf, 0, 0, temp, udpsize, edns, (int)(edns->bits&EDNS_DO), 0)) {

usr.sbin/unbound/services/localzone.c

1353

edns->bits &= EDNS_DO;

usr.sbin/unbound/services/mesh.c

1345

r->edns.bits &= EDNS_DO;

usr.sbin/unbound/services/mesh.c

1346

if(m->s.env->cfg->disable_edns_do && (r->edns.bits&EDNS_DO))

usr.sbin/unbound/services/mesh.c

1354

(int)(r->edns.bits & EDNS_DO), secure))

usr.sbin/unbound/services/mesh.c

1479

prev->edns.bits == r->edns.bits &&

usr.sbin/unbound/services/mesh.c

1522

r->edns.bits &= EDNS_DO;

usr.sbin/unbound/services/mesh.c

1523

if(m->s.env->cfg->disable_edns_do && (r->edns.bits&EDNS_DO))

usr.sbin/unbound/services/mesh.c

1541

udp_size, &r->edns, (int)(r->edns.bits & EDNS_DO),

usr.sbin/unbound/services/outside_network.c

2817

int bits = 0;

usr.sbin/unbound/services/outside_network.c

2826

if(bits == 0) {

usr.sbin/unbound/services/outside_network.c

2828

bits = 30;

usr.sbin/unbound/services/outside_network.c

2836

bits--;

usr.sbin/unbound/services/outside_network.c

2892

edns.bits = 0;

usr.sbin/unbound/services/outside_network.c

2894

edns.bits = EDNS_DO;

usr.sbin/unbound/services/rpz.c

1805

edns->bits &= EDNS_DO;

usr.sbin/unbound/services/rpz.c

1810

buf, 0, 0, temp, udpsize, edns, (int)(edns->bits&EDNS_DO), 0)) {

usr.sbin/unbound/testcode/dohclient.c

247

edns.bits = EDNS_DO;

usr.sbin/unbound/testcode/doqclient.c

1618

short ATTR_UNUSED(bits), void* arg)

usr.sbin/unbound/testcode/doqclient.c

2051

doq_client_event_cb(int ATTR_UNUSED(fd), short bits, void* arg)

usr.sbin/unbound/testcode/doqclient.c

2055

((bits&UB_EV_READ)!=0?"EV_READ":""),

usr.sbin/unbound/testcode/doqclient.c

2056

((bits&(UB_EV_READ|UB_EV_WRITE))==(UB_EV_READ|UB_EV_WRITE)?

usr.sbin/unbound/testcode/doqclient.c

2058

((bits&UB_EV_WRITE)!=0?"EV_WRITE":""));

usr.sbin/unbound/testcode/doqclient.c

2059

if((bits&UB_EV_READ)) {

usr.sbin/unbound/testcode/doqclient.c

347

edns.bits = EDNS_DO;

usr.sbin/unbound/testcode/fake_event.c

1344

edns.bits = 0;

usr.sbin/unbound/testcode/fake_event.c

1346

edns.bits = EDNS_DO;

usr.sbin/unbound/testcode/perf.c

491

ed.bits = EDNS_DO;

usr.sbin/unbound/testcode/streamtcp.c

215

edns.bits = EDNS_DO;

usr.sbin/unbound/testcode/unitecs.c

141

int bits = rand() % maxlen;

usr.sbin/unbound/testcode/unitecs.c

142

int bytes = bits/8 + (bits%8>0); /*ceil*/

usr.sbin/unbound/testcode/unitecs.c

147

return (addrlen_t)bits;

usr.sbin/unbound/testcode/unitmain.c

984

edns->bits &= EDNS_DO;

usr.sbin/unbound/testcode/unitmsgparse.c

182

r2, 65535, (int)(edns->bits & EDNS_DO), 0);

usr.sbin/unbound/testcode/unitmsgparse.c

345

region, 65535, (int)(edns.bits & EDNS_DO), 0);

usr.sbin/unbound/testcode/unitmsgparse.c

360

(int)(edns.bits & EDNS_DO), 0);

usr.sbin/unbound/util/data/msgencode.c

1123

es.bits &= EDNS_DO;

usr.sbin/unbound/util/data/msgencode.c

936

sldns_buffer_write_u16(pkt, edns->bits);

usr.sbin/unbound/util/data/msgparse.c

1207

edns->bits = sldns_read_uint16(&found->rr_last->ttl_data[2]);

usr.sbin/unbound/util/data/msgparse.c

1303

edns->bits = sldns_buffer_read_u16(pkt);

usr.sbin/unbound/util/data/msgparse.c

137

uint8_t win, blen, bits;

usr.sbin/unbound/util/data/msgparse.c

145

bits = sldns_buffer_read_u8(pkt);

usr.sbin/unbound/util/data/msgparse.c

148

if(win == 0 && blen >= 1 && (bits & 0x02)) {

usr.sbin/unbound/util/data/msgparse.h

231

uint16_t bits;

usr.sbin/unbound/util/mini_event.c

204

short bits = 0;

usr.sbin/unbound/util/mini_event.c

209

bits |= EV_READ;

usr.sbin/unbound/util/mini_event.c

213

bits |= EV_WRITE;

usr.sbin/unbound/util/mini_event.c

216

bits &= base->fds[i]->ev_events;

usr.sbin/unbound/util/mini_event.c

217

if(bits) {

usr.sbin/unbound/util/mini_event.c

221

bits, base->fds[i]->ev_arg);

usr.sbin/unbound/util/mini_event.c

271

void event_set(struct event* ev, int fd, short bits,

usr.sbin/unbound/util/mini_event.c

276

ev->ev_events = bits;

usr.sbin/unbound/util/ub_event.c

349

ub_event_new(struct ub_event_base* base, int fd, short bits,

usr.sbin/unbound/util/ub_event.c

358

event_set(ev, fd, NATIVE_BITS(bits), NATIVE_BITS_CB(cb), arg);

usr.sbin/unbound/util/ub_event.c

364

if (event_assign(ev, AS_EVENT_BASE(base), fd, bits, cb, arg) != 0) {

usr.sbin/unbound/util/ub_event.c

421

ub_event_add_bits(struct ub_event* ev, short bits)

usr.sbin/unbound/util/ub_event.c

423

AS_EVENT(ev)->ev_events |= NATIVE_BITS(bits);

usr.sbin/unbound/util/ub_event.c

427

ub_event_del_bits(struct ub_event* ev, short bits)

usr.sbin/unbound/util/ub_event.c

429

AS_EVENT(ev)->ev_events &= ~NATIVE_BITS(bits);

usr.sbin/unbound/util/ub_event.c

94

# define UB_EV_BITS_CB(C) void my_ ## C (int fd, short bits, void *arg) \

usr.sbin/unbound/util/ub_event.c

95

{ (C)(fd, UB_EV_BITS(bits), arg); }

usr.sbin/unbound/util/ub_event.h

100

void ub_event_del_bits(struct ub_event*, short bits);

usr.sbin/unbound/util/ub_event.h

123

void ub_winsock_tcp_wouldblock(struct ub_event*, int bits);

usr.sbin/unbound/util/ub_event.h

89

int fd, short bits, void (*cb)(int, short, void*), void* arg);

usr.sbin/unbound/util/ub_event.h

98

void ub_event_add_bits(struct ub_event*, short bits);

usr.sbin/unbound/util/ub_event_pluggable.c

156

my_event_add_bits(struct ub_event* ev, short bits)

usr.sbin/unbound/util/ub_event_pluggable.c

158

AS_MY_EVENT(ev)->ev.ev_events |= NATIVE_BITS(bits);

usr.sbin/unbound/util/ub_event_pluggable.c

162

my_event_del_bits(struct ub_event* ev, short bits)

usr.sbin/unbound/util/ub_event_pluggable.c

164

AS_MY_EVENT(ev)->ev.ev_events &= ~NATIVE_BITS(bits);

usr.sbin/unbound/util/ub_event_pluggable.c

276

my_event_new(struct ub_event_base* base, int fd, short bits,

usr.sbin/unbound/util/ub_event_pluggable.c

285

event_set(&my_ev->ev, fd, NATIVE_BITS(bits), NATIVE_BITS_CB(cb), arg);

usr.sbin/unbound/util/ub_event_pluggable.c

508

ub_event_new(struct ub_event_base* base, int fd, short bits,

usr.sbin/unbound/util/ub_event_pluggable.c

514

return (*base->vmt->new_event)(base, fd, bits, cb, arg);

usr.sbin/unbound/util/ub_event_pluggable.c

545

ub_event_add_bits(struct ub_event* ev, short bits)

usr.sbin/unbound/util/ub_event_pluggable.c

550

(*ev->vmt->add_bits)(ev, bits);

usr.sbin/unbound/util/ub_event_pluggable.c

555

ub_event_del_bits(struct ub_event* ev, short bits)

usr.sbin/unbound/util/ub_event_pluggable.c

560

(*ev->vmt->del_bits)(ev, bits);

usr.sbin/unbound/util/ub_event_pluggable.c

89

# define UB_EV_BITS_CB(C) void my_ ## C (int fd, short bits, void *arg) \

usr.sbin/unbound/util/ub_event_pluggable.c

90

{ (C)(fd, UB_EV_BITS(bits), arg); }

usr.sbin/unbound/util/winsock_event.c

321

short bits = 0;

usr.sbin/unbound/util/winsock_event.c

345

bits |= EV_READ;

usr.sbin/unbound/util/winsock_event.c

351

bits |= EV_WRITE;

usr.sbin/unbound/util/winsock_event.c

357

bits |= EV_READ;

usr.sbin/unbound/util/winsock_event.c

358

bits |= EV_WRITE;

usr.sbin/unbound/util/winsock_event.c

364

bits |= EV_READ;

usr.sbin/unbound/util/winsock_event.c

370

bits |= EV_READ;

usr.sbin/unbound/util/winsock_event.c

371

bits |= EV_WRITE;

usr.sbin/unbound/util/winsock_event.c

378

bits |= eventlist[i]->old_events;

usr.sbin/unbound/util/winsock_event.c

380

if(eventlist[i]->is_tcp && bits) {

usr.sbin/unbound/util/winsock_event.c

381

eventlist[i]->old_events = bits;

usr.sbin/unbound/util/winsock_event.c

383

if((eventlist[i]->ev_events & bits)) {

usr.sbin/unbound/util/winsock_event.c

391

if((bits & eventlist[i]->ev_events)) {

usr.sbin/unbound/util/winsock_event.c

402

(bits&EV_READ)?" EV_READ":"",

usr.sbin/unbound/util/winsock_event.c

403

(bits&EV_WRITE)?" EV_WRITE":"",

usr.sbin/unbound/util/winsock_event.c

404

(bits&EV_TIMEOUT)?" EV_TIMEOUT":"");

usr.sbin/unbound/util/winsock_event.c

409

bits & eventlist[i]->ev_events,

usr.sbin/unbound/util/winsock_event.c

412

if(eventlist[i]->is_tcp && bits)

usr.sbin/unbound/util/winsock_event.c

469

void event_set(struct event *ev, int fd, short bits,

usr.sbin/unbound/util/winsock_event.c

474

ev->ev_events = bits;

usr.sbin/unbound/validator/autotrust.c

2396

edns.bits = EDNS_DO;

usr.sbin/unbound/validator/val_kentry.c

418

size_t bits = 0;

usr.sbin/unbound/validator/val_kentry.c

425

if(i==0 || dnskey_get_keysize(d, i) < bits)

usr.sbin/unbound/validator/val_kentry.c

426

bits = dnskey_get_keysize(d, i);

usr.sbin/unbound/validator/val_kentry.c

428

return bits;

usr.sbin/unbound/validator/val_nsec3.c

466

get_max_iter(struct val_env* ve, size_t bits)

usr.sbin/unbound/validator/val_nsec3.c

472

if(bits <= ve->nsec3_keysize[i])

usr.sbin/unbound/validator/val_nsec3.c

494

size_t bits = key_entry_keysize(kkey);

usr.sbin/unbound/validator/val_nsec3.c

495

size_t max_iter = get_max_iter(ve, bits);

usr.sbin/unbound/validator/val_nsec3.c

497

(int)bits, (int)max_iter);