sys/arm/allwinner/a10_codec.c

178

#define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg))

sys/arm/allwinner/a10_codec.c

181

#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/a10_dmac.c

86

#define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg))

sys/arm/allwinner/a31_dmac.c

160

#define DMA_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/a33_codec.c

154

#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/a64/sun50i_a64_acodec.c

133

#define A64CODEC_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_cir.c

49

#define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))

sys/arm/allwinner/aw_gpio.c

433

bus_read_4((_sc)->sc_res[AW_GPIO_MEMRES], _off)

sys/arm/allwinner/aw_i2s.c

237

#define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/aw_mmc.c

218

bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)

sys/arm/allwinner/aw_nmi.c

61

#define SC_NMI_READ(_sc, _reg) bus_read_4(_sc->res[0], _reg)

sys/arm/allwinner/aw_reset.c

66

#define RESET_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_rsb.c

152

#define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_rtc.c

92

#define RTC_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_sid.c

286

#define RD4(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_thermal.c

374

#define RD4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/aw_timer.c

105

bus_read_4(sc->res[AW_TIMER_MEMRES], reg)

sys/arm/allwinner/aw_ts.c

44

#define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))

sys/arm/allwinner/aw_usb3phy.c

106

#define RD4(res, o) bus_read_4(res, (o))

sys/arm/allwinner/aw_usbphy.c

180

#define RD4(res, o) bus_read_4(res, (o))

sys/arm/allwinner/aw_usbphy.c

309

val = bus_read_4(sc->phy_ctrl, PHY_CSR);

sys/arm/allwinner/aw_usbphy.c

447

val = bus_read_4(sc->phy_ctrl, PHY_CSR);

sys/arm/allwinner/aw_wdog.c

49

#define READ(_sc, _r) bus_read_4((_sc)->res, (_r))

sys/arm/allwinner/if_awg.c

1391

return (bus_read_4(sc->res[_RES_SYSCON], 0));

sys/arm/allwinner/if_awg.c

71

#define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))

sys/arm/annapurna/alpine/alpine_nb_service.c

106

val = bus_read_4(sc->res, AL_NB_ACF_MISC_OFFSET);

sys/arm/arm/gic.c

1353

typer = bus_read_4(sc->sc_mem, GICV2M_MSI_TYPER);

sys/arm/arm/gic.c

153

bus_read_4((_sc)->gic_res[GIC_RES_CPU], (_reg))

sys/arm/arm/gic.c

160

bus_read_4((_sc)->gic_res[GIC_RES_DIST], (_reg))

sys/arm/arm/mpcore_timer.c

114

#define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)

sys/arm/arm/mpcore_timer.c

116

#define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)

sys/arm/broadcom/bcm2835/bcm2835_dma.c

183

cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));

sys/arm/broadcom/bcm2835/bcm2835_dma.c

191

cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));

sys/arm/broadcom/bcm2835/bcm2835_dma.c

240

reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

243

reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

545

reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

631

cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));

sys/arm/broadcom/bcm2835/bcm2835_dma.c

647

debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));

sys/arm/broadcom/bcm2835/bcm2835_rng.c

176

return bus_read_4(sc->sc_mem_res, off);

sys/arm/broadcom/bcm2835/bcm2838_pci.c

176

return (le32toh(bus_read_4(sc->base.base.res, reg)));

sys/arm/broadcom/bcm2835/bcm2838_pci.c

335

data = le32toh(bus_read_4(sc->base.base.res, offset));

sys/arm/freescale/fsl_ocotp.c

101

return (bus_read_4(sc->mem_res, off));

sys/arm/freescale/imx/imx6_anatop.c

149

return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));

sys/arm/freescale/imx/imx6_ccm.c

69

return (bus_read_4(sc->mem_res, off));

sys/arm/freescale/imx/imx6_ipu.c

83

#define IPU_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, (reg))

sys/arm/freescale/imx/imx6_src.c

60

return (bus_read_4(sc->mem_res, off));

sys/arm/freescale/imx/imx_epit.c

136

return (bus_read_4(sc->memres, offset));

sys/arm/freescale/imx/imx_iomux.c

108

return (bus_read_4(sc->mem_res, off));

sys/arm/freescale/imx/imx_spi.c

156

return (bus_read_4(sc->memres, offset));

sys/arm/include/pl310.h

171

return bus_read_4(sc->sc_mem_res, off);

sys/arm/mv/armada/thermal.c

247

tsen_stat = bus_read_4(sc->stat_res, 0);

sys/arm/mv/armada/thermal.c

268

reg = bus_read_4(sc->stat_res, 0);

sys/arm/mv/armada/thermal.c

291

tsen_ctrl = bus_read_4(sc->ctrl_res, 0);

sys/arm/mv/armada/wdt.c

190

return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL));

sys/arm/mv/armada38x/armada38x_rtc.c

316

return (bus_read_4(sc->res[RTC_RES], off));

sys/arm/mv/armada38x/armada38x_rtc.c

339

val = bus_read_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL);

sys/arm/mv/armada38x/armada38x_rtc.c

351

val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0);

sys/arm/mv/armada38x/armada38x_rtc.c

357

val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0);

sys/arm/mv/clk/a37x0_periph_clk_driver.c

185

*val = bus_read_4(sc->res, addr);

sys/arm/mv/clk/a37x0_tbg.c

122

*val = bus_read_4(sc->res, offset);

sys/arm/mv/clk/armada38x_coreclk.c

94

*val = bus_read_4(sc->res, addr);

sys/arm/mv/clk/armada38x_gateclk.c

53

#define RD4(_sc, addr) bus_read_4(_sc->res, addr)

sys/arm/mv/mv_ap806_gicp.c

78

#define RD4(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/mv/mv_ap806_sei.c

102

#define RD4(sc, reg) bus_read_4((sc)->mem_res, (reg))

sys/arm/mv/mv_cp110_icu.c

99

#define RD4(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/mv/rtc.c

183

return (bus_read_4(sc->res[0], off));

sys/arm/nvidia/drm2/tegra_dc.c

56

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, 4 * (_r))

sys/arm/nvidia/drm2/tegra_hdmi.c

59

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, 4 * (_r))

sys/arm/nvidia/drm2/tegra_host1x.c

58

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra124/tegra124_car.c

467

*val = bus_read_4(sc->mem_res, addr);

sys/arm/nvidia/tegra124/tegra124_car.c

489

reg = bus_read_4(sc->mem_res, addr);

sys/arm/nvidia/tegra124/tegra124_pmc.c

136

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

171

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra_abpmisc.c

59

#define ABP_RD4(_sc, _r) bus_read_4((_sc)->abp_misc_res, (_r))

sys/arm/nvidia/tegra_abpmisc.c

60

#define STR_RD4(_sc, _r) bus_read_4((_sc)->strap_opt_res, (_r))

sys/arm/nvidia/tegra_ahci.c

208

#define AHCI_RD4(_sc, _r) bus_read_4((_sc)->ctlr.r_mem, (_r))

sys/arm/nvidia/tegra_ahci.c

210

#define SATA_RD4(_sc, _r) bus_read_4((_sc)->sata_mem, (_r))

sys/arm/nvidia/tegra_ahci.c

578

val = bus_read_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1);

sys/arm/nvidia/tegra_efuse.c

50

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (FUSES_START + (_r)))

sys/arm/nvidia/tegra_gpio.c

167

val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));

sys/arm/nvidia/tegra_gpio.c

361

tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));

sys/arm/nvidia/tegra_gpio.c

408

val = bus_read_4(sc->mem_res, GPIO_INT_STA +

sys/arm/nvidia/tegra_gpio.c

410

val &= bus_read_4(sc->mem_res, GPIO_INT_ENB +

sys/arm/nvidia/tegra_gpio.c

63

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra_i2c.c

192

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra_lic.c

66

#define RD4(_sc, _b, _r) bus_read_4((_sc)->mem_res[_b], (_r))

sys/arm/nvidia/tegra_mc.c

98

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra_pcie.c

233

#define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r))

sys/arm/nvidia/tegra_pcie.c

235

#define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r))

sys/arm/nvidia/tegra_pcie.c

520

code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;

sys/arm/nvidia/tegra_pcie.c

521

signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE);

sys/arm/nvidia/tegra_pinmux.c

488

reg = bus_read_4(sc->mux_mem_res, mux->reg);

sys/arm/nvidia/tegra_pinmux.c

552

reg = bus_read_4(sc->pad_mem_res, grp->reg);

sys/arm/nvidia/tegra_pinmux.c

613

reg = bus_read_4(sc->mipi_mem_res, 0); /* register 0x820 */

sys/arm/nvidia/tegra_rtc.c

76

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra_sdhci.c

122

return (bus_read_4(sc->mem_res, off));

sys/arm/nvidia/tegra_sdhci.c

150

val32 = bus_read_4(sc->mem_res, off);

sys/arm/nvidia/tegra_soctherm.c

132

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm/nvidia/tegra_usbphy.c

307

bus_read_4(sc->mem_res, offs)

sys/arm/nvidia/tegra_usbphy.c

413

val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);

sys/arm/nvidia/tegra_usbphy.c

543

val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);

sys/arm/nvidia/tegra_xhci.c

212

#define IPFS_RD4(_sc, _r) bus_read_4((_sc)->mem_res_ipfs, (_r))

sys/arm/nvidia/tegra_xhci.c

214

#define FPCI_RD4(_sc, _r) bus_read_4((_sc)->mem_res_fpci, (_r))

sys/arm/ti/am335x/am335x_dmtimer.c

88

#define DMTIMER_READ4(sc, reg) bus_read_4((sc)->tmr_mem_res, (reg))

sys/arm/ti/am335x/am335x_dmtpps.c

145

#define DMTIMER_READ4(sc, reg) bus_read_4((sc)->mem_res, (reg))

sys/arm/ti/am335x/am335x_ecap.c

60

#define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);

sys/arm/ti/am335x/am335x_lcd.c

182

#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);

sys/arm/ti/am335x/am335x_musb.c

102

#define USB_READ4(sc, idx, reg) bus_read_4((sc)->sc_mem_res[idx], (reg))

sys/arm/ti/am335x/am335x_rtc.c

52

bus_read_4((_sc)->sc_mem_res, reg)

sys/arm/ti/cpsw/if_cpsw.c

367

#define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg))

sys/arm/ti/ti_adcvar.h

32

#define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg)

sys/arm/ti/ti_edma3.c

123

#define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg)

sys/arm/ti/ti_gpio.c

157

return (bus_read_4(sc->sc_mem_res, off));

sys/arm/ti/ti_sdhci.c

136

return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));

sys/arm/ti/ti_sdhci.c

150

return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));

sys/arm/ti/ti_sdma.c

160

return bus_read_4(sc->sc_mem_res, off);

sys/arm/xilinx/zy7_devcfg.c

96

#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))

sys/arm/xilinx/zy7_gpio.c

182

#define RD4(sc, off) bus_read_4((sc)->mem_res, (off))

sys/arm/xilinx/zy7_qspi.c

105

#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))

sys/arm/xilinx/zy7_slcr.c

73

#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))

sys/arm/xilinx/zy7_spi.c

92

#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))

sys/arm64/apple/apple_aic.c

203

info = bus_read_4(sc->sc_mem, AIC_INFO);

sys/arm64/apple/apple_aic.c

223

sc->sc_cpuids[cpu] = bus_read_4(sc->sc_mem, AIC_WHOAMI);

sys/arm64/apple/apple_aic.c

567

event = bus_read_4(sc->sc_mem, AIC_EVENT);

sys/arm64/apple/apple_aic.c

742

sc->sc_cpuids[cpu] = bus_read_4(sc->sc_mem, AIC_WHOAMI);

sys/arm64/apple/apple_pinctrl.c

64

bus_read_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg)

sys/arm64/arm64/cmn600.c

51

#define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r))

sys/arm64/arm64/gic_v3.c

1245

while ((bus_read_4(res, offset + GICD_CTLR) & GICD_CTLR_RWP) != 0) {

sys/arm64/arm64/gic_v3.c

1406

pidr2 = bus_read_4(r_res, GICR_PIDR2);

sys/arm64/arm64/gic_v3.c

228

return (bus_read_4(rdist, offset));

sys/arm64/arm64/gicv3_its.c

337

bus_read_4((sc)->sc_its_res, (reg))

sys/arm64/arm64/pl031_rtc.c

120

ts->tv_sec = bus_read_4(sc->reg, RTCDR);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

173

val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

203

bus_read_4(sc->reg_base, MDIO_STAT_OFFSET);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

208

param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

225

ret = bus_read_4(sc->reg_base, MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK;

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

237

val = bus_read_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET);

sys/arm64/broadcom/genet/if_genet.c

80

#define RD4(sc, reg) bus_read_4((sc)->res[_RES_MAC], (reg))

sys/arm64/coresight/coresight_cpu_debug.c

89

reg = bus_read_4(sc->res, EDPRCR);

sys/arm64/coresight/coresight_cpu_debug.c

98

reg = bus_read_4(sc->res, EDPRSR);

sys/arm64/coresight/coresight_etm4x.c

141

reg = bus_read_4(sc->res, TRCVIIECTLR);

sys/arm64/coresight/coresight_etm4x.c

183

reg = bus_read_4(sc->res, TRCIDR(1));

sys/arm64/coresight/coresight_etm4x.c

207

reg = bus_read_4(sc->res, TRCSTATR);

sys/arm64/coresight/coresight_etm4x.c

210

if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0)

sys/arm64/coresight/coresight_etm4x.c

230

reg = bus_read_4(sc->res, TRCSTATR);

sys/arm64/coresight/coresight_funnel.c

106

reg = bus_read_4(sc->res, FUNNEL_FUNCTL);

sys/arm64/coresight/coresight_funnel.c

70

dprintf("Device ID: %x\n", bus_read_4(sc->res, FUNNEL_DEVICEID));

sys/arm64/coresight/coresight_funnel.c

86

reg = bus_read_4(sc->res, FUNNEL_FUNCTL);

sys/arm64/coresight/coresight_tmc.c

112

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

122

bus_read_4(sc->res, TMC_STS),

sys/arm64/coresight/coresight_tmc.c

123

bus_read_4(sc->res, TMC_CTL),

sys/arm64/coresight/coresight_tmc.c

124

bus_read_4(sc->res, TMC_RSZ),

sys/arm64/coresight/coresight_tmc.c

125

bus_read_4(sc->res, TMC_RRP),

sys/arm64/coresight/coresight_tmc.c

126

bus_read_4(sc->res, TMC_RWP),

sys/arm64/coresight/coresight_tmc.c

127

bus_read_4(sc->res, TMC_CBUFLEVEL),

sys/arm64/coresight/coresight_tmc.c

128

bus_read_4(sc->res, TMC_LBUFLEVEL));

sys/arm64/coresight/coresight_tmc.c

145

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

175

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

198

reg = bus_read_4(sc->res, TMC_DEVID);

sys/arm64/coresight/coresight_tmc.c

299

if (bus_read_4(sc->res, TMC_STS) & STS_FULL) {

sys/arm64/coresight/coresight_tmc.c

305

cur_ptr = bus_read_4(sc->res, TMC_RWP);

sys/arm64/coresight/coresight_tmc.c

66

if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN)

sys/arm64/coresight/coresight_tmc.c

71

if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)

sys/arm64/coresight/coresight_tmc.c

75

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

78

if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0)

sys/arm64/coresight/coresight_tmc.c

92

reg = bus_read_4(sc->res, TMC_CTL);

sys/arm64/coresight/coresight_tmc.c

97

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/freescale/imx/imx_ccm.c

64

return (bus_read_4(sc->mem_res, off));

sys/arm64/iommu/smmu.c

1064

reg = bus_read_4(sc->res[0], SMMU_CR0);

sys/arm64/iommu/smmu.c

1217

reg = bus_read_4(sc->res[0], SMMU_CR0);

sys/arm64/iommu/smmu.c

1325

reg = bus_read_4(sc->res[0], SMMU_IDR0);

sys/arm64/iommu/smmu.c

1432

reg = bus_read_4(sc->res[0], SMMU_IDR1);

sys/arm64/iommu/smmu.c

1469

reg = bus_read_4(sc->res[0], SMMU_IDR3);

sys/arm64/iommu/smmu.c

1474

reg = bus_read_4(sc->res[0], SMMU_IDR5);

sys/arm64/iommu/smmu.c

299

v = bus_read_4(sc->res[0], reg_ack);

sys/arm64/iommu/smmu.c

543

cmdq->lc.cons = bus_read_4(sc->res[0], cmdq->cons_off);

sys/arm64/nvidia/tegra210/tegra210_car.c

465

*val = bus_read_4(sc->mem_res, addr);

sys/arm64/nvidia/tegra210/tegra210_car.c

487

reg = bus_read_4(sc->mem_res, addr);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

459

reg = bus_read_4(sc->mux_mem_res, mux->reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

523

reg = bus_read_4(sc->pad_mem_res, grp->reg);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

215

return(bus_read_4(sc->mem_res, r));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

325

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm64/qoriq/clk/lx2160a_clkgen.c

188

printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x00080, bus_read_4(sc->res, 0x00080));

sys/arm64/qoriq/clk/lx2160a_clkgen.c

189

printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x000A0, bus_read_4(sc->res, 0x000A0));

sys/arm64/qoriq/clk/lx2160a_clkgen.c

190

printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x10080, bus_read_4(sc->res, 0x10080));

sys/arm64/qoriq/clk/lx2160a_clkgen.c

191

printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x100A0, bus_read_4(sc->res, 0x100A0));

sys/arm64/qoriq/clk/lx2160a_clkgen.c

192

printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x60080, bus_read_4(sc->res, 0x60080));

sys/arm64/qoriq/clk/lx2160a_clkgen.c

193

printf(" %s: offset: 0x%08X, val: 0x%08X\n", __func__, 0x600A0, bus_read_4(sc->res, 0x600A0));

sys/arm64/qoriq/clk/qoriq_clkgen.c

111

*val = le32toh(bus_read_4(sc->res, addr));

sys/arm64/qoriq/clk/qoriq_clkgen.c

113

*val = be32toh(bus_read_4(sc->res, addr));

sys/arm64/qoriq/clk/qoriq_clkgen.c

127

reg = le32toh(bus_read_4(sc->res, addr));

sys/arm64/qoriq/clk/qoriq_clkgen.c

129

reg = be32toh(bus_read_4(sc->res, addr));

sys/arm64/qoriq/qoriq_gpio_pic.c

67

#define RD4(sc, off) bus_read_4((sc)->base.sc_mem, (off))

sys/arm64/qoriq/qoriq_therm.c

208

val = bus_read_4(sc->mem_res, addr);

sys/arm64/rockchip/rk3328_codec.c

159

#define RKCODEC_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm64/rockchip/rk3568_combphy.c

184

bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);

sys/arm64/rockchip/rk3568_combphy.c

208

(bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |

sys/arm64/rockchip/rk3568_combphy.c

227

(bus_read_4(sc->mem, PHYREG32) & PHYREG32_SSC_MASK) |

sys/arm64/rockchip/rk3568_combphy.c

232

bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN);

sys/arm64/rockchip/rk3568_combphy.c

236

(bus_read_4(sc->mem, PHYREG33) & PHYREG33_PLL_KVCO_MASK) |

sys/arm64/rockchip/rk3568_combphy.c

244

(bus_read_4(sc->mem, PHYREG6) & PHYREG6_PLL_DIV_MASK) |

sys/arm64/rockchip/rk3568_combphy.c

279

(bus_read_4(sc->mem, PHYREG15) &

sys/arm64/rockchip/rk3568_combphy.c

299

(bus_read_4(sc->mem, PHYREG33) &

sys/arm64/rockchip/rk3568_combphy.c

308

(bus_read_4(sc->mem, PHYREG6) &

sys/arm64/rockchip/rk3568_combphy.c

320

(bus_read_4(sc->mem, PHYREG32) & ~0x000000f0) |

sys/arm64/rockchip/rk3568_combphy.c

336

bus_read_4(sc->mem, PHYREG8) | PHYREG8_SSC_EN);

sys/arm64/rockchip/rk3568_pcie.c

125

val = bus_read_4(sc->apb_res, PCIE_CLIENT_LTSSM_STATUS);

sys/arm64/rockchip/rk_i2s.c

163

#define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm64/rockchip/rk_otp.c

146

*buffer++ = bus_read_4(sc->mem, OTPC_USER_Q);

sys/arm64/rockchip/rk_otp.c

89

while (!(bus_read_4(sc->mem, OTPC_SBPI_INT_STATUS) & status)) {

sys/arm64/rockchip/rk_pcie.c

180

#define APB_RD4(_sc, _r) bus_read_4((_sc)->apb_mem_res, (_r))

sys/arm64/rockchip/rk_pcie.c

258

val = bus_read_4(sc->apb_mem_res, base + reg);

sys/arm64/rockchip/rk_pcie.c

289

val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3));

sys/arm64/rockchip/rk_pcie.c

295

val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3));

sys/arm64/rockchip/rk_tsadc.c

101

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/arm64/rockchip/rk_typec_phy.c

134

#define RK_TYPEC_PHY_READ(sc, reg) bus_read_4(sc->res, (reg))

sys/arm64/rockchip/rk_usbphy.c

68

#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))

sys/dev/acpica/acpi_apei.c

135

return (bus_read_4(res, offset) |

sys/dev/acpica/acpi_apei.c

136

((uint64_t)bus_read_4(res, offset + 4)) << 32);

sys/dev/acpica/acpi_hpet.c

143

return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));

sys/dev/acpica/acpi_hpet.c

185

val = bus_read_4(sc->mem_res, HPET_CONFIG);

sys/dev/acpica/acpi_hpet.c

199

val = bus_read_4(sc->mem_res, HPET_CONFIG);

sys/dev/acpica/acpi_hpet.c

227

now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

245

now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

292

t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +

sys/dev/acpica/acpi_hpet.c

302

now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

322

val = bus_read_4(sc->mem_res, HPET_ISR);

sys/dev/acpica/acpi_hpet.c

507

val = bus_read_4(sc->mem_res, HPET_PERIOD);

sys/dev/acpica/acpi_hpet.c

516

sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);

sys/dev/acpica/acpi_hpet.c

559

t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));

sys/dev/acpica/acpi_hpet.c

560

t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);

sys/dev/acpica/acpi_hpet.c

576

val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

578

val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

906

t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

915

bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));

sys/dev/acpica/acpi_hpet.c

941

u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

943

u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/acpica/acpi_hpet.c

945

u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);

sys/dev/adlink/adlink.c

136

u = bus_read_4(sc->res[0], 0x38);

sys/dev/adlink/adlink.c

145

u = bus_read_4(sc->res[1], 0x18);

sys/dev/adlink/adlink.c

310

u = bus_read_4(sc->res[0], 0x3c);

sys/dev/ae/if_ae.c

189

bus_read_4((sc)->mem[0], (reg))

sys/dev/age/if_agevar.h

243

bus_read_4((_sc)->age_res[0], (reg))

sys/dev/agp/agp_i810.c

1098

pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);

sys/dev/agp/agp_i810.c

1135

pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2);

sys/dev/agp/agp_i810.c

1140

pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);

sys/dev/agp/agp_i810.c

1214

pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);

sys/dev/agp/agp_i810.c

1340

pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);

sys/dev/agp/agp_i810.c

1621

pte = bus_read_4(sc->sc_res[0], AGP_I810_GTT + index * 4);

sys/dev/agp/agp_i810.c

1632

pte = bus_read_4(sc->sc_res[1], index * 4);

sys/dev/agp/agp_i810.c

1643

pte = bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024));

sys/dev/agp/agp_i810.c

1654

pte = bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024));

sys/dev/agp/agp_i810.c

2008

hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);

sys/dev/agp/agp_i810.c

2011

hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);

sys/dev/agp/agp_i810.c

796

bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));

sys/dev/agp/agp_i810.c

807

bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));

sys/dev/agp/agp_i810.c

818

bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));

sys/dev/agp/agp_i810.c

829

bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));

sys/dev/agp/agp_i810.c

842

bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2));

sys/dev/agp/agp_i810.c

913

switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &

sys/dev/ahci/ahci.h

558

bus_read_4((res), (offset))

sys/dev/ahci/ahci.h

592

bus_read_4((res), (offset))

sys/dev/alc/if_alcvar.h

268

bus_read_4((_sc)->alc_res[0], (reg))

sys/dev/ale/if_alevar.h

237

bus_read_4((_sc)->ale_res[0], (reg))

sys/dev/amdgpio/amdgpio.c

69

return (bus_read_4(sc->sc_res[0], off));

sys/dev/amdsbwd/amdsbwd.c

149

return (bus_read_4(sc->res_ctrl, 0));

sys/dev/amdsbwd/amdsbwd.c

161

return (bus_read_4(sc->res_count, 0));

sys/dev/ata/ata-all.h

510

bus_read_4((res), (offset))

sys/dev/axgbe/xgbe-common.h

1505

bus_read_4((_pdata)->xgmac_res, _reg)

sys/dev/axgbe/xgbe-common.h

1529

bus_read_4((_pdata)->xgmac_res, \

sys/dev/axgbe/xgbe-common.h

1592

bus_read_4((_pdata)->xpcs_res, (_off))

sys/dev/axgbe/xgbe-common.h

1690

bus_read_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET)

sys/dev/axgbe/xgbe-common.h

1724

bus_read_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET)

sys/dev/bfe/if_bfereg.h

444

#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)

sys/dev/bge/if_bgereg.h

2807

bus_read_4(sc->bge_res, reg)

sys/dev/bge/if_bgereg.h

2819

bus_read_4(sc->bge_res2, reg)

sys/dev/bhnd/bhnd.h

1651

bus_read_4((r)->res, (o)) : \

sys/dev/bhnd/bhndb/bhndb_pci.c

1649

return (bus_read_4(r, res_offset));

sys/dev/bhnd/bhndb/bhndb_pci.c

761

return (bus_read_4(r, r_offset));

sys/dev/bhnd/cores/chipc/chipc_slicer.c

160

val = bus_read_4(res, ofs);

sys/dev/bhnd/cores/chipc/chipc_slicer.c

172

fs_ofs = bus_read_4(res, ofs + 24);

sys/dev/bhnd/cores/chipc/chipc_slicer.c

188

fw_len = bus_read_4(res, ofs + 4);

sys/dev/bhnd/cores/chipc/chipc_spi.h

85

#define SPI_READ(sc, reg) bus_read_4(sc->sc_res, (reg))

sys/dev/bwn/if_bwnvar.h

71

(bus_read_4((mac)->mac_sc->sc_mem_res, (o)))

sys/dev/cadence/if_cgem.c

220

#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))

sys/dev/cesa/cesa.h

92

bus_read_4((sc)->sc_res[RES_CESA_REGS], (reg))

sys/dev/cesa/cesa.h

97

bus_read_4((sc)->sc_res[RES_TDMA_REGS], (reg))

sys/dev/clk/allwinner/aw_ccung.c

73

#define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/clk/rockchip/rk_cru.c

67

#define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/clk/starfive/jh7110_clk.c

46

bus_read_4(_sc->mem_res, _off)

sys/dev/cxgbe/adapter.h

1277

return bus_read_4(sc->regs_res, reg);

sys/dev/cxgbe/adapter.h

1296

return (uint64_t)bus_read_4(sc->regs_res, reg) +

sys/dev/cxgbe/adapter.h

1297

((uint64_t)bus_read_4(sc->regs_res, reg + 4) << 32);

sys/dev/cxgbe/t4_iov.c

148

return bus_read_4(sc->regs_res, reg);

sys/dev/dpaa2/dpaa2_console.c

133

#define DPAA2_MC_READ_4(_sc, _r) bus_read_4((_sc)->res, (_r))

sys/dev/dpaa2/dpaa2_mc.c

73

#define mcreg_read_4(_sc, _r) bus_read_4(&(_sc)->map[1], (_r))

sys/dev/dpaa2/dpaa2_swp.c

1139

verb = (uint32_t) (bus_read_4(map, offset) & 0xFFu);

sys/dev/dpaa2/dpaa2_swp.c

1146

ret = bus_read_4(map, offset);

sys/dev/dpaa2/dpaa2_swp.c

358

return (bus_read_4(swp->cinh_map, o));

sys/dev/dpaa2/dpaa2_swp.c

685

verb = bus_read_4(map, offset);

sys/dev/dpaa2/memac_mdio_common.c

150

v = bus_read_4(sc->mem_res, reg);

sys/dev/dwc/if_dwcvar.h

119

bus_read_4((_sc)->res[0], _reg)

sys/dev/dwwdt/dwwdt.c

61

#define DWWDT_READ4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/enetc/enetc.h

104

bus_read_4((sc)->regs, reg)

sys/dev/enetc/enetc.h

111

bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg))

sys/dev/enetc/enetc_mdio.c

42

bus_read_4((regs), (base) + (off))

sys/dev/eqos/if_eqos.c

97

#define RD4(sc, o) bus_read_4(sc->res[EQOS_RES_MEM], (o))

sys/dev/et/if_etvar.h

71

bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/etherswitch/ar40xx/ar40xx_var.h

41

#define AR40XX_REG_READ(sc, reg) bus_read_4(sc->sc_ess_mem_res, (reg))

sys/dev/etherswitch/felix/felix_var.h

48

#define FELIX_RD4(sc, reg) bus_read_4((sc)->regs, reg)

sys/dev/etherswitch/mtkswitch/mtkswitchvar.h

129

bus_read_4((_sc)->sc_res, (_reg))

sys/dev/fdt/simple_mfd.c

115

val = bus_read_4(sc->mem_res, offset);

sys/dev/fdt/simple_mfd.c

90

val = bus_read_4(sc->mem_res, offset);

sys/dev/ffec/if_ffec.c

228

return (bus_read_4(sc->mem_res, off));

sys/dev/flash/cqspi.c

80

#define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg)

sys/dev/flash/cqspi.c

86

#define READ_DATA_4(_sc, _reg) bus_read_4((_sc)->res[1], _reg)

sys/dev/flash/flexspi/flex_spi.c

136

return ((bus_read_4(sc->mem_res, offset)));

sys/dev/flash/flexspi/flex_spi.c

522

*(uint32_t*)data = bus_read_4(sc->ahb_mem_res, offset);

sys/dev/fxp/if_fxpvar.h

246

#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)

sys/dev/glxsb/glxsb.c

451

status = bus_read_4(sc->sc_sr, SB_RANDOM_NUM_STATUS);

sys/dev/glxsb/glxsb.c

453

value = bus_read_4(sc->sc_sr, SB_RANDOM_NUM);

sys/dev/glxsb/glxsb.c

612

status = bus_read_4(sc->sc_sr, SB_CTL_A);

sys/dev/goldfish/goldfish_rtc.c

132

low = bus_read_4(sc->res, GOLDFISH_RTC_TIME_LOW);

sys/dev/goldfish/goldfish_rtc.c

133

high = bus_read_4(sc->res, GOLDFISH_RTC_TIME_HIGH);

sys/dev/gpio/bytgpio.c

297

return (bus_read_4(sc->sc_mem_res, off));

sys/dev/gpio/chvgpio.c

120

return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin));

sys/dev/gpio/chvgpio.c

132

return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin) + 4);

sys/dev/gpio/chvgpio.c

465

reg = bus_read_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS);

sys/dev/gpio/dwgpio/dwgpio_bus.c

141

val = bus_read_4(sc->res[0], offset);

sys/dev/gpio/qoriq_gpio.c

114

reg = bus_read_4(sc->sc_mem, GPIO_GPDIR);

sys/dev/gpio/qoriq_gpio.c

119

reg = bus_read_4(sc->sc_mem, GPIO_GPDIR);

sys/dev/gpio/qoriq_gpio.c

122

reg = bus_read_4(sc->sc_mem, GPIO_GPODR);

sys/dev/gpio/qoriq_gpio.c

185

outvals = bus_read_4(sc->sc_mem, GPIO_GPDAT);

sys/dev/gpio/qoriq_gpio.c

204

*value = (bus_read_4(sc->sc_mem, GPIO_GPDAT) >> (31 - pin)) & 1;

sys/dev/gpio/qoriq_gpio.c

221

val = bus_read_4(sc->sc_mem, GPIO_GPDAT);

sys/dev/gpio/qoriq_gpio.c

262

hwstate = bus_read_4(sc->sc_mem, GPIO_GPDAT);

sys/dev/gpio/qoriq_gpio.c

312

reg = (bus_read_4(sc->sc_mem, GPIO_GPDIR) & ~mask) | dir;

sys/dev/gpio/qoriq_gpio.c

315

reg = (bus_read_4(sc->sc_mem, GPIO_GPODR) & ~mask) | odr;

sys/dev/gve/gve_utils.c

37

return (be32toh(bus_read_4(priv->reg_bar, offset)));

sys/dev/hwpmc/pmu_dmc620.c

69

#define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r))

sys/dev/ichiic/ig4_iic.c

172

value = bus_read_4(sc->regs_res, reg);

sys/dev/ichwd/ichwd.c

309

bus_read_4((sc)->tco_res, (off))

sys/dev/ichwd/ichwd.c

311

bus_read_4((sc)->smi_res, (off))

sys/dev/ichwd/ichwd.c

313

bus_read_4((sc)->gcs_res, (off))

sys/dev/ichwd/ichwd.c

316

bus_read_4((sc)->gcs_res, (off))

sys/dev/ichwd/ichwd.c

318

bus_read_4((sc)->gc_res, (off))

sys/dev/ida/idavar.h

41

bus_read_4((ida)->regs, port)

sys/dev/iicbus/controller/qcom/geni_iic.c

125

#define RD(sc, reg) bus_read_4((sc)->regs_res, reg)

sys/dev/iicbus/controller/rockchip/rk_i2c.c

162

#define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/dev/iicbus/controller/twsi/twsi.c

100

val = bus_read_4(sc->res[0], off);

sys/dev/intel/pchtherm.c

127

temp = bus_read_4(sc->tbar, PCHTHERM_REG_TL);

sys/dev/intel/pchtherm.c

214

val = bus_read_4(sc->tbar, PCHTHERM_REG_TL);

sys/dev/intel/spi.c

75

bus_read_4((_sc)->sc_mem_res, (_off))

sys/dev/ips/ips.h

61

#define ips_read_4(sc,offset) bus_read_4(sc->iores, offset)

sys/dev/ismt/ismt.c

182

val = bus_read_4(sc->mmio_res, ISMT_MSTR_MSTS);

sys/dev/ismt/ismt.c

261

val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL);

sys/dev/ismt/ismt.c

267

val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL);

sys/dev/ismt/ismt.c

652

val = bus_read_4(sc->mmio_res, ISMT_MSTR_MDS);

sys/dev/isp/isp_pci.c

716

#define BXR4(isp, off) bus_read_4((isp)->isp_regs, (off))

sys/dev/isp/isp_pci.c

718

#define B2R4(isp, off) bus_read_4((isp)->isp_regs2, (off))

sys/dev/jme/if_jmevar.h

232

bus_read_4((_sc)->jme_res[0], (reg))

sys/dev/mailbox/arm/arm_doorbell.c

106

reg = bus_read_4(sc->res[0], MHU_CHAN_RX_HP + MHU_INTR_STAT);

sys/dev/mailbox/arm/arm_doorbell.c

313

reg = bus_read_4(sc->res[0], offset + MHU_INTR_STAT);

sys/dev/mailbox/arm/arm_doorbell.c

84

reg = bus_read_4(sc->res[0], MHU_CHAN_RX_LP + MHU_INTR_STAT);

sys/dev/mgb/if_mgb.h

231

bus_read_4((sc)->regs, reg)

sys/dev/mge/if_mgevar.h

119

#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg))

sys/dev/mlx/mlxreg.h

121

#define MLX_V4_GET_IDBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_IDBR)

sys/dev/mlx/mlxreg.h

123

#define MLX_V4_GET_ODBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_ODBR)

sys/dev/mmc/host/dwmmc.c

89

bus_read_4((_sc)->res[0], _reg)

sys/dev/msk/if_mskreg.h

2132

bus_read_4((sc)->msk_res[0], (reg))

sys/dev/msk/if_mskreg.h

2146

bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))

sys/dev/mvs/mvs.h

638

bus_read_4((res), (offset))

sys/dev/neta/if_mvnetavar.h

61

bus_read_4((sc)->res[0], (reg))

sys/dev/neta/if_mvnetavar.h

71

bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg))

sys/dev/netmap/if_ptnet.c

1090

return bus_read_4(sc->iomem, PTNET_IO_PTCTL);

sys/dev/netmap/if_ptnet.c

1098

info->num_tx_rings = bus_read_4(sc->iomem, PTNET_IO_NUM_TX_RINGS);

sys/dev/netmap/if_ptnet.c

1099

info->num_rx_rings = bus_read_4(sc->iomem, PTNET_IO_NUM_RX_RINGS);

sys/dev/netmap/if_ptnet.c

1100

info->num_tx_descs = bus_read_4(sc->iomem, PTNET_IO_NUM_TX_SLOTS);

sys/dev/netmap/if_ptnet.c

1101

info->num_rx_descs = bus_read_4(sc->iomem, PTNET_IO_NUM_RX_SLOTS);

sys/dev/netmap/if_ptnet.c

1151

sc->vnet_hdr_len = bus_read_4(sc->iomem, PTNET_IO_VNET_HDR_LEN);

sys/dev/netmap/if_ptnet.c

312

ptfeatures = bus_read_4(sc->iomem, PTNET_IO_PTFEAT); /* acked */

sys/dev/netmap/if_ptnet.c

315

num_tx_rings = bus_read_4(sc->iomem, PTNET_IO_NUM_TX_RINGS);

sys/dev/netmap/if_ptnet.c

316

num_rx_rings = bus_read_4(sc->iomem, PTNET_IO_NUM_RX_RINGS);

sys/dev/netmap/if_ptnet.c

415

macreg = bus_read_4(sc->iomem, PTNET_IO_MAC_HI);

sys/dev/netmap/if_ptnet.c

418

macreg = bus_read_4(sc->iomem, PTNET_IO_MAC_LO);

sys/dev/netmap/if_ptnet.c

452

nifp_offset = bus_read_4(sc->iomem, PTNET_IO_NIFP_OFS);

sys/dev/netmap/if_ptnet.c

455

na_arg.num_tx_desc = bus_read_4(sc->iomem, PTNET_IO_NUM_TX_SLOTS);

sys/dev/netmap/if_ptnet.c

456

na_arg.num_rx_desc = bus_read_4(sc->iomem, PTNET_IO_NUM_RX_SLOTS);

sys/dev/netmap/if_ptnet.c

469

bus_read_4(sc->iomem, PTNET_IO_HOSTMEMID));

sys/dev/netmap/netmap_freebsd.c

816

*mem_size = bus_read_4(ptn_dev->pci_io, PTNET_MDEV_IO_MEMSIZE_HI);

sys/dev/netmap/netmap_freebsd.c

817

*mem_size = bus_read_4(ptn_dev->pci_io, PTNET_MDEV_IO_MEMSIZE_LO) |

sys/dev/netmap/netmap_freebsd.c

843

return bus_read_4(ptn_dev->pci_io, reg);

sys/dev/netmap/netmap_freebsd.c

895

mem_id = bus_read_4(ptn_dev->pci_io, PTNET_MDEV_IO_MEMID);

sys/dev/nfe/if_nfereg.h

289

bus_read_4((sc)->nfe_res[0], (reg))

sys/dev/nge/if_ngereg.h

680

bus_read_4((sc)->nge_res, reg)

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1655

laddr = bus_read_4(msix->msix_table_res, offset +

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1664

data = bus_read_4(msix->msix_table_res, offset +

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

121

bus_read_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

127

bus_read_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

133

bus_read_4((sc)->mw_info[(sc)->b2b_mw].mw_res, \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

349

val = bus_read_4(sc->conf_res, 0x360);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

444

if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678)

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

457

if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678)

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

566

val = bus_read_4(sc->conf_res, reg);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

588

val = bus_read_4(sc->conf_res, reg);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

605

val = bus_read_4(sc->conf_res, reg);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

900

if (bus_read_4(sc->conf_res, off) == val)

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

934

*val = bus_read_4(sc->conf_res, off);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

972

*val = bus_read_4(sc->mw_info[sc->b2b_mw].mw_res, off);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

974

*val = bus_read_4(sc->conf_res, off);

sys/dev/nvme/nvme_private.h

329

bus_read_4((sc)->resource, nvme_mmio_offsetof(reg))

sys/dev/p2sb/p2sb.c

89

return (bus_read_4(sc->res, P2SB_PORT_ADDRESS(port) + reg));

sys/dev/pci/pci.c

1745

val = bus_read_4(msix->msix_table_res, offset);

sys/dev/pci/pci.c

1764

val = bus_read_4(msix->msix_table_res, offset);

sys/dev/pci/pci.c

1784

return (bus_read_4(msix->msix_pba_res, offset) & bit);

sys/dev/pci/pci.c

3649

ctl = bus_read_4(res, OHCI_CONTROL);

sys/dev/pci/pci.c

3657

ctl = bus_read_4(res, OHCI_CONTROL);

sys/dev/pci/pci.c

3714

cparams = bus_read_4(res, EHCI_HCCPARAMS);

sys/dev/pci/pci.c

3746

offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));

sys/dev/pci/pci.c

3770

cparams = bus_read_4(res, XHCI_HCCPARAMS1);

sys/dev/pci/pci.c

3777

eec = bus_read_4(res, eecp);

sys/dev/pci/pci.c

3809

bus_read_4(res, offs + XHCI_USBSTS);

sys/dev/pci/pci_dw.c

556

data = bus_read_4(res, reg);

sys/dev/pci/pci_dw.c

74

bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg))

sys/dev/pci/pci_dw.c

98

return (bus_read_4(sc->dbi_res, reg));

sys/dev/pci/pci_host_generic.c

323

data = le32toh(bus_read_4(sc->res, offset));

sys/dev/pci/pci_user.c

1071

pbi->pbi_value = bus_read_4(res, offset);

sys/dev/proto/proto_core.c

365

pci_read_config(dev, ofs, 4) : bus_read_4(r->r_d.res, ofs);

sys/dev/pwm/controller/allwinner/aw_pwm.c

109

#define AW_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/pwm/controller/rockchip/rk_pwm.c

123

#define RK_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/qat/include/common/adf_accel_devices.h

496

#define ADF_CSR_RD(csr_base, csr_offset) bus_read_4(csr_base, csr_offset)

sys/dev/qat/include/common/adf_accel_devices.h

505

return (((uint64_t)bus_read_4(csr_base, offset)) |

sys/dev/qat/include/common/adf_accel_devices.h

506

(((uint64_t)bus_read_4(csr_base, offset + 4)) << 32));

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

50

#define EDMA_REG_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))

sys/dev/qcom_gcc/qcom_gcc_clock.c

54

*val = bus_read_4(sc->reg, addr);

sys/dev/qcom_gcc/qcom_gcc_clock.c

76

reg = bus_read_4(sc->reg, addr);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

146

reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

170

reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

43

#define MDIO_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))

sys/dev/qcom_qup/qcom_spi_var.h

116

#define QCOM_SPI_READ_4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/qcom_rnd/qcom_rnd.c

142

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_CONFIG);

sys/dev/qcom_rnd/qcom_rnd.c

149

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_LFSR_CFG);

sys/dev/qcom_rnd/qcom_rnd.c

155

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_CONFIG);

sys/dev/qcom_rnd/qcom_rnd.c

200

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_STATUS);

sys/dev/qcom_rnd/qcom_rnd.c

203

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_DATA_OUT);

sys/dev/qcom_tcsr/qcom_tcsr_var.h

31

#define QCOM_TCSR_READ_4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/qcom_tlmm/qcom_tlmm_var.h

44

#define GPIO_READ(sc, reg) bus_read_4(sc->gpio_mem_res, (reg))

sys/dev/qlnx/qlnxe/qlnx_os.c

5150

data32 = bus_read_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \

sys/dev/qlnx/qlnxe/qlnx_os.c

5215

data32 = bus_read_4(((qlnx_host_t *)cdev)->pci_reg, offset);

sys/dev/qlxgb/qla_reg.h

228

#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)

sys/dev/qlxgb/qla_reg.h

234

bus_read_4((ha->pci_reg), reg);\

sys/dev/qlxgb/qla_reg.h

246

bus_read_4((ha->pci_reg), off);\

sys/dev/qlxgbe/ql_hw.h

203

#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)

sys/dev/qlxgbe/ql_hw.h

208

bus_read_4((ha->pci_reg), reg);\

sys/dev/qlxge/qls_hw.h

898

#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)

sys/dev/qlxge/qls_hw.h

922

#define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

936

#define Q81_RD_CQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

950

#define Q81_RD_LBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\

sys/dev/qlxge/qls_hw.h

956

#define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\

sys/dev/safexcel/safexcel_var.h

423

#define SAFEXCEL_READ(sc, off) bus_read_4((sc)->sc_res, (off))

sys/dev/sdhci/fsl_sdhci.c

193

return (bus_read_4(sc->mem_res, off));

sys/dev/sdhci/sdhci_acpi.c

160

return bus_read_4(sc->mem_res, off);

sys/dev/sdhci/sdhci_fdt.c

292

val32 = bus_read_4(sc->mem_res[slot->num], off);

sys/dev/sdhci/sdhci_fdt_cvitek.c

118

reg = bus_read_4(res, CVI_CV181X_SDHCI_EMMC_CTRL);

sys/dev/sdhci/sdhci_fdt_rockchip.c

197

val = bus_read_4(sc->mem_res[slot->num],

sys/dev/sdhci/sdhci_fsl_fdt.c

261

return (be32toh(bus_read_4(sc->mem_res, off)));

sys/dev/sdhci/sdhci_fsl_fdt.c

275

return (bus_read_4(sc->mem_res, off));

sys/dev/sdhci/sdhci_fsl_fdt.c

441

return (bus_read_4(sc->mem_res, off));

sys/dev/sdhci/sdhci_pci.c

222

return bus_read_4(sc->mem_res[slot->num], off);

sys/dev/sdhci/sdhci_xenon.c

107

return bus_read_4(sc->mem_res, off);

sys/dev/sdhci/sdhci_xenon.c

198

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

215

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

223

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

244

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

252

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);

sys/dev/sdhci/sdhci_xenon.c

261

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

270

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);

sys/dev/sdhci/sdhci_xenon.c

276

reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

280

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

300

reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

309

reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);

sys/dev/sdhci/sdhci_xenon.c

314

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);

sys/dev/sdhci/sdhci_xenon.c

368

reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

547

reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

556

reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

565

reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

570

reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);

sys/dev/sge/if_sge.c

184

#define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg)

sys/dev/siis/siis.h

434

bus_read_4((res), (offset))

sys/dev/sis/if_sis.c

120

#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)

sys/dev/sk/if_skreg.h

1282

bus_read_4((sc)->sk_res[0], (reg))

sys/dev/sound/macio/davbus.c

181

bus_read_4(d->reg, DAVBUS_CODEC_STATUS)));

sys/dev/sound/macio/davbus.c

219

while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) &

sys/dev/sound/macio/davbus.c

348

bus_read_4(d->reg, DAVBUS_CODEC_STATUS)));

sys/dev/sound/macio/davbus.c

381

while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY)

sys/dev/sound/macio/davbus.c

389

while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY)

sys/dev/sound/macio/davbus.c

582

reg = bus_read_4(d->reg, DAVBUS_SOUND_CTRL);

sys/dev/sound/macio/davbus.c

585

status = bus_read_4(d->reg, DAVBUS_CODEC_STATUS);

sys/dev/sound/macio/i2s.c

533

x = bus_read_4(sc->reg, I2S_WORDSIZE);

sys/dev/sound/macio/i2s.c

537

x = bus_read_4(sc->reg, I2S_FORMAT);

sys/dev/spibus/controller/allwinner/aw_spi.c

161

#define AW_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/dev/spibus/controller/rockchip/rk_spi.c

123

#define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/dev/ste/if_stereg.h

489

bus_read_4((sc)->ste_res, reg)

sys/dev/stge/if_stgereg.h

97

bus_read_4((_sc)->sc_res[0], (reg))

sys/dev/sym/sym_hipd.c

846

#define INL_OFF(o) bus_read_4(np->io_res, (o))

sys/dev/sym/sym_hipd.c

856

#define INL_OFF(o) bus_read_4(np->mmio_res, (o))

sys/dev/syscon/syscon_generic.c

121

val = bus_read_4(sc->mem_res, offset);

sys/dev/syscon/syscon_generic.c

97

val = bus_read_4(sc->mem_res, offset);

sys/dev/tpm/tpm_bus.c

47

return (bus_read_4(sc->mem_res, off));

sys/dev/usb/controller/ehci_imx.c

160

reg = bus_read_4(sc->mmio, index * sizeof(uint32_t));

sys/dev/usb/controller/ehci_imx.c

172

reg = bus_read_4(sc->mmio, index * sizeof(uint32_t));

sys/dev/vge/if_vgevar.h

224

bus_read_4(sc->vge_res, reg)

sys/dev/viawd/viawd.c

45

#define viawd_read_4(sc, off) bus_read_4((sc)->wd_res, (off))

sys/dev/virtio/mmio/virtio_mmio.c

116

bus_read_4((sc)->res[0], (o))

sys/dev/virtio/pci/virtio_pci_legacy.c

127

le32toh(bus_read_4((sc)->vtpci_res, (o)))

sys/dev/virtio/pci/virtio_pci_legacy.c

136

bus_read_4((sc)->vtpci_res, (o))

sys/dev/virtio/pci/virtio_pci_modern.c

1323

bus_read_4(&sc->vtpci_common_res_map.vtrm_map, off));

sys/dev/virtio/pci/virtio_pci_modern.c

1390

return (bus_read_4(&sc->vtpci_device_res_map.vtrm_map, off));

sys/dev/vmd/vmd.c

187

return (bus_read_4(sc->vmd_regs_res[0], offset));

sys/dev/vmware/pvscsi/pvscsi.c

256

return (bus_read_4(sc->mm_res, offset));

sys/dev/xdma/controller/pl330.c

76

bus_read_4(_sc->res[0], _reg)

sys/dev/xilinx/if_xae.c

72

#define XAE_RD4(_sc, _reg) bus_read_4((_sc)->res[0], _reg)

sys/dev/xilinx/if_xae.c

77

#define AXIDMA_RD4(_sc, _reg) bus_read_4((_sc)->dma_res, _reg)

sys/dev/xilinx/xlnx_pcib.c

119

reg = bus_read_4(sc->res, XLNX_PCIE_RPERRFRR);

sys/dev/xilinx/xlnx_pcib.c

140

val = bus_read_4(sc->res, XLNX_PCIE_IDR);

sys/dev/xilinx/xlnx_pcib.c

141

mask = bus_read_4(sc->res, XLNX_PCIE_IMR);

sys/dev/xilinx/xlnx_pcib.c

221

reg = bus_read_4(sc->res, msireg);

sys/dev/xilinx/xlnx_pcib.c

299

reg = bus_read_4(sc->res[0], XLNX_PCIE_IDR);

sys/dev/xilinx/xlnx_pcib.c

310

reg = bus_read_4(sc->res[0], XLNX_PCIE_RPSCR);

sys/dev/xilinx/xlnx_pcib.c

699

reg = bus_read_4(sc->res, msireg);

sys/powerpc/amigaone/cpld_a1222.c

349

*word = bus_read_4(sc->sc_mem, CPLD_MEM_DATA);

sys/powerpc/amigaone/cpld_x5000.c

287

*word = bus_read_4(sc->sc_mem, CPLD_MEM_DATA);

sys/powerpc/mpc85xx/fsl_diu.c

205

reg = bus_read_4(sc->res[0], DIU_INT_STATUS);

sys/powerpc/mpc85xx/fsl_diu.c

246

reg = bus_read_4(sc->res[0], DIU_DIU_MODE);

sys/powerpc/mpc85xx/fsl_diu.c

322

reg = bus_read_4(sc->res[0], DIU_DIU_MODE);

sys/powerpc/mpc85xx/fsl_espi.c

106

#define FSL_ESPI_READ(sc,off) bus_read_4(sc->sc_mem_res, off)

sys/powerpc/mpc85xx/fsl_sata.c

307

bus_read_4((res), (offset))

sys/powerpc/mpc85xx/mpc85xx_cache.c

124

bus_read_4(sc->sc_mem, L2_CTL);

sys/powerpc/mpc85xx/mpc85xx_gpio.c

129

outvals = bus_read_4(sc->out_res, 0);

sys/powerpc/mpc85xx/mpc85xx_gpio.c

148

*value = (bus_read_4(sc->in_res, 0) >> (31 - pin)) & 1;

sys/powerpc/mpc85xx/mpc85xx_gpio.c

165

val = bus_read_4(sc->out_res, 0);

sys/powerpc/mpc85xx/pci_mpc85xx.c

332

ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);

sys/powerpc/mpc85xx/platform_mpc85xx.c

662

devdisr = bus_read_4(sc->sc_mem, GUTS_DEVDISR);

sys/powerpc/powermac/ata_kauai.c

298

bus_read_4(sc->sc_memr, PIO_CONFIG_REG) & 0x0f000fff;

sys/powerpc/powermac/ata_macio.c

231

timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG);

sys/powerpc/powermac/atibl.c

170

(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);

sys/powerpc/powermac/atibl.c

171

(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);

sys/powerpc/powermac/atibl.c

173

data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);

sys/powerpc/powermac/atibl.c

176

save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);

sys/powerpc/powermac/atibl.c

179

tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);

sys/powerpc/powermac/atibl.c

192

(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);

sys/powerpc/powermac/atibl.c

193

(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);

sys/powerpc/powermac/atibl.c

199

save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);

sys/powerpc/powermac/atibl.c

202

tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);

sys/powerpc/powermac/atibl.c

220

lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);

sys/powerpc/powermac/atibl.c

224

disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);

sys/powerpc/powermac/atibl.c

227

lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);

sys/powerpc/powermac/atibl.c

267

lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);

sys/powerpc/powermac/dbdma.c

374

return (bus_read_4(chan->sc_regs, chan->sc_off + offset));

sys/powerpc/powermac/kiic.c

258

return bus_read_4(sc->sc_reg, sc->sc_regstep * reg) & 0xff;

sys/powerpc/powermac/macgpio.c

368

sc->sc_saved_gpio_levels[0] = bus_read_4(sc->sc_gpios, GPIO_LEVELS_0);

sys/powerpc/powermac/macgpio.c

369

sc->sc_saved_gpio_levels[1] = bus_read_4(sc->sc_gpios, GPIO_LEVELS_1);

sys/powerpc/powermac/macio.c

415

fcr = bus_read_4(sc->sc_memr, HEATHROW_FCR);

sys/powerpc/powermac/macio.c

438

fcr1 = bus_read_4(sc->sc_memr, KEYLARGO_FCR1);

sys/powerpc/powermac/macio.c

739

x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);

sys/powerpc/powermac/macio.c

748

x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);

sys/powerpc/powermac/macio.c

763

x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);

sys/powerpc/powermac/macio.c

767

x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);

sys/powerpc/powernv/xive.c

678

val = bus_read_4(sc->sc_mem, XIVE_TM_QW2_HV_POOL + TM_WORD2);

sys/powerpc/powerpc/openpic.c

404

sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);

sys/powerpc/powerpc/openpic.c

406

sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));

sys/powerpc/powerpc/openpic.c

410

sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));

sys/powerpc/powerpc/openpic.c

414

sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));

sys/powerpc/powerpc/openpic.c

415

sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));

sys/powerpc/powerpc/openpic.c

416

sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));

sys/powerpc/powerpc/openpic.c

417

sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));

sys/powerpc/powerpc/openpic.c

422

bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;

sys/powerpc/powerpc/openpic.c

435

sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);

sys/powerpc/pseries/xics.c

383

xirr = bus_read_4(regs, 4);

sys/riscv/riscv/aplic.c

159

#define aplic_read(sc, reg) bus_read_4(sc->mem_res, (reg))

sys/riscv/riscv/plic.c

113

bus_read_4(sc->mem_res, (reg))

sys/riscv/sifive/fe310_aon.c

107

#define FEAON_READ_4(sc, reg) bus_read_4(sc->reg_res, reg)

sys/riscv/sifive/fu740_pci_dw.c

101

#define FUDW_MGMT_READ(_sc, _o) bus_read_4((_sc)->mgmt_res, (_o))

sys/riscv/sifive/sifive_gpio.c

81

bus_read_4((_sc)->mem_res, (_off))

sys/riscv/starfive/jh7110_gpio.c

77

#define JH7110_GPIO_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/riscv/starfive/jh7110_pcie.c

161

#define RD4(sc, reg) bus_read_4((sc)->reg_mem_res, (reg))

sys/riscv/starfive/jh7110_pcie.c

186

data = le32toh(bus_read_4(sc->cfg_mem_res, offset));

sys/riscv/starfive/jh7110_pcie.c

465

reg = bus_read_4(sc->cfg_mem_res, sc->msi_mask_offset);

sys/x86/iommu/amd_iommu.h

147

return (bus_read_4(unit->mmio_res, reg));

sys/x86/iommu/amd_iommu.h

156

low = bus_read_4(unit->mmio_res, reg);

sys/x86/iommu/amd_iommu.h

157

high = bus_read_4(unit->mmio_res, reg + 4);

sys/x86/iommu/intel_dmar.h

275

return (bus_read_4(unit->regs, reg));

sys/x86/iommu/intel_dmar.h

284

low = bus_read_4(unit->regs, reg);

sys/x86/iommu/intel_dmar.h

285

high = bus_read_4(unit->regs, reg + 4);

tools/bus_space/C/libbus.h

33

int64_t bus_read_4(int rid, long ofs);

tools/bus_space/Python/lang.c

422

{ "read_4", bus_read_4, METH_VARARGS, "Read a 4-byte data item." },