clk_enable
error = clk_enable(esc->sc_clk_biu);
error = clk_enable(esc->sc_clk_ciu);
if (clk_enable(clk_gmac) != 0) {
if (clk_enable(clk) != 0) {
error = clk_enable(clkp_parent);
if (clk_enable(clk_gmac) != 0) {
if (sc->sc_clk == NULL || clk_enable(sc->sc_clk) != 0) {
if (clk != NULL && clk_enable(clk) != 0) {
if (clk_core == NULL || clk_enable(clk_core) != 0) {
if (clk_clkin == NULL || clk_enable(clk_clkin) != 0) {
if (clk_core == NULL || clk_enable(clk_core) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(sc->sc_clk_core) != 0) {
if (clk_enable(sc->sc_clk_clkin[0]) != 0 ||
clk_enable(sc->sc_clk_clkin[1]) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(sc->sc_clk_phy) != 0) {
if (clk_enable(sc->sc_clk_peripheral) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk);
if (clk_enable(clk) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(sc->sc_clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk);
error = clk_enable(clk);
if (clk == NULL || clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk_sata);
error = clk_enable(sc->sc_clk_sata_oob);
error = clk_enable(sc->sc_clk_cml1);
error = clk_enable(clk);
error = clk_enable(sc->sc_clk);
error = clk_enable(sc->sc_clk_host1x);
error = clk_enable(sc->sc_clk_dc[index]);
error = clk_enable(sc->sc_clk_hdmi_parent);
error = clk_enable(sc->sc_clk_hdmi);
clk_enable(fuse_softc->sc_clk);
error = clk_enable(sc->sc_clk_hda);
error = clk_enable(sc->sc_clk_hda2hdmi);
error = clk_enable(sc->sc_clk_hda2codec_2x);
error = clk_enable(sc->sc_clk);
error = clk_enable(sc->sc_clk_pwr);
error = clk_enable(sc->sc_clk_gpu);
if (clk == NULL || clk_enable(clk) != 0)
error = clk_enable(sc->sc_clk);
error = clk_enable(sc->sc_clk_tsensor);
error = clk_enable(sc->sc_clk_soctherm);
error = clk_enable(sc->sc_clk_reg);
error = clk_enable(clk); /* XXX set frequency */
error = clk_enable(clk); /* XXX set frequency */
error = clk_enable(clk);
error = clk_enable(clk); /* XXX set frequency */
error = clk_enable(clk); /* XXX set frequency */
error = clk_enable(psc->sc_clk_ss_src);
error = clk_enable(clk); /* XXX set frequency */
error = clk_enable(clk);
error = clk_enable(clk);
error = clk_enable(sc->sc_clk_ipg);
error = clk_enable(sc->sc_clk_enet);
error = clk_enable(sc->sc_clk_enet_ref);
error = clk_enable(sc->sc_clk);
error = clk_enable(ifsc->sc_clk);
error = clk_enable(sc->sc_clk);
error = clk_enable(sc->sc_clk);
error = clk_enable(sc->sc_clk_sata);
error = clk_enable(sc->sc_clk_sata_ref);
error = clk_enable(sc->sc_clk_ahb);
error = clk_enable(clkp_parent);
return clk_enable(extclk);
if (per != NULL && clk_enable(per) != 0) {
error = clk_enable(imxsc->sc_clk);
error = clk_enable(sc->sc_clk_per);
error = clk_enable(sc->sc_clk_pcie);
error = clk_enable(sc->sc_clk_pcie_ext);
error = clk_enable(sc->sc_clk_pcie_bus);
error = clk_enable(sc->sc_clk_pcie_phy);
if (clk_enable(clk) != 0)
if (clk_enable(clk) != 0)
error = clk_enable(clkp_parent);
if (sc->sc_clk_vpll != NULL && clk_enable(sc->sc_clk_vpll) != 0) {
if (clk_enable(clk) != 0) {
error = clk_enable(clk);
if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || clk_enable(clk) != 0) {
if (sc->sc_sclk == NULL || clk_enable(sc->sc_sclk) != 0) {
if (sc->sc_pclk == NULL || clk_enable(sc->sc_pclk) != 0) {
error = clk_enable(sc->sc_clk);
|| clk_enable(sclk) != 0) {
|| clk_enable(pclk) != 0) {
clk_enable(sc->sc_core_clk);
clk_enable(sc->sc_phy_ref_clk);
error = clk_enable(sc->sc_clock);
error = clk_enable(sc->sc_clockapb);
if (clk && clk_enable(clk) != 0) {
if (sc->sc_dclk == NULL || clk_enable(sc->sc_dclk) != 0) {
error = clk_enable(esc->sc_clk_biu);
error = clk_enable(esc->sc_clk_ciu);
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk_uart == NULL || clk_enable(clk_uart) != 0) {
if (clk_uart_baud0 == NULL || clk_enable(clk_uart_baud0) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
|| clk_enable(clk) != 0) {
|| clk_enable(modclk) != 0) {
clk_enable(clk) != 0) {
|| clk_enable(clk) != 0) {
|| clk_enable(modclk) != 0) {
if (clk_enable(sc->sc_clk_gate) != 0) {
if (clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk_phy);
error = clk_enable(sc->sc_clk_hsic);
if (clk_enable(clk) != 0) {
error = clk_enable(clkp_parent);
error = clk_enable(clkp);
error = clk_enable(clk);
error = clk_enable(clk);
if (clk_bus == NULL || clk_enable(clk_bus) != 0) {
if (clk_mod == NULL || clk_enable(clk_mod) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0 ||
clk_enable(sc->sc_clk_mod) != 0) {
if (clk_enable(sc->sc_clk_ram) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0 ||
clk_enable(sc->sc_clk_mod) != 0) {
if (clk_iahb == NULL || clk_enable(clk_iahb) != 0) {
if (clk_isfr == NULL || clk_enable(clk_isfr) != 0) {
if (clk_tmds == NULL || clk_enable(clk_tmds) != 0) {
error = clk_enable(sc->clk_ahb);
error = clk_enable(sc->clk_ephy);
if (clk_enable(clk_gmac_tx) != 0 || clk_enable(clk_gmac) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0) {
error = clk_enable(sc->sc_clk_mod);
clk_enable(sc->sc_clk_bus);
clk_enable(sc->sc_clk_mod);
clk_enable(sc->sc_clk_pll0);
|| clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk);
error = clk_enable(clk);
error = clk_enable(sc->sc_clk_ch[0]);
error = clk_enable(sc->sc_clk_ch[1]);
if (clk == NULL || clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_bus == NULL || clk_enable(clk_bus) != 0) {
clk_enable(clk_mod) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0 ||
clk_enable(sc->sc_clk_mmc) != 0) {
if (clk_enable(clk) != 0) {
if ((error = clk_enable(sc->sc_clk_ahb)) != 0)
if ((error = clk_enable(sc->sc_clk_mod)) != 0)
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0) {
if (clk_enable(sc->sc_clk_ahb) != 0) {
error = clk_enable(sc->sc_clk_ch0);
if ((error = clk_enable(sc->sc_clk_ch0)) != 0) {
if ((error = clk_enable(sc->sc_clk_ch1)) != 0) {
error = clk_enable(sc->sc_clk_ch1);
error = clk_enable(clk);
error = clk_enable(clk);
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk);
error = clk_enable(phy->phy_clk48);
error = clk_enable(sc->sc_phy_logic_clk);
if (clk_enable(sc->sc_ref_clk)) {
return clk_enable(clk_gate);
return clk_enable(clk_parent);
if (clk_enable(clk) != 0) {
return clk_enable(clk_parent);
if (sc->sc_clk == NULL || clk_enable(sc->sc_clk) != 0) {
if (hwmod == NULL || clk_enable(hwmod) != 0) {
error = clk_enable(clkp_parent);
return clk_enable(clk);
if (clk == NULL || clk_enable(clk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
int error = clk_enable(clk_parent);
if (clk_enable(clk) != 0) {
int clk_enable(struct clk *);
if (clk_enable(clk) != 0) {
if (clk_enable(sc->sc_clk_xin) != 0 || clk_enable(sc->sc_clk_ahb) != 0) {
if (sc->sc_pclk == NULL || clk_enable(sc->sc_pclk) != 0) {
if (clk_enable(ssc->ssc_clk) != 0) {
if (ssc->ssc_pclk != NULL && clk_enable(ssc->ssc_pclk) != 0) {
if (clk == NULL || clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
error = clk_enable(esc->sc_clk_biu);
error = clk_enable(esc->sc_clk_ciu);
if (clk == NULL || clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
if (clk_enable(clk) != 0) {
return clk_enable(clk);
return clk_enable(clk);
error = clk_enable(sc->sc_clk);
if (clk_enable(clk) != 0) {
error = clk_enable(sc->sc_clk);
if (sc->sc_clk == NULL || clk_enable(sc->sc_clk) != 0) {