common/lib/libc/misc/ubsan.c

1381

zWidth = __BIT(__SHIFTOUT(pType->mTypeInfo, ~NUMBER_SIGNED_BIT));

lib/libc/arch/aarch64/gen/flt_rounds.c

67

return (__SHIFTOUT(reg_fpcr_read(), FPCR_RMODE) + 1) & 3;

lib/libc/arch/aarch64/gen/fpgetmask.c

48

return __SHIFTOUT(reg_fpcr_read(), FPCR_ESUM);

lib/libc/arch/aarch64/gen/fpgetround.c

48

return __SHIFTOUT(reg_fpcr_read(), FPCR_RMODE);

lib/libc/arch/aarch64/gen/fpgetsticky.c

48

return __SHIFTOUT(reg_fpsr_read(), FPSR_CSUM);

lib/libc/arch/aarch64/gen/fpsetmask.c

52

return __SHIFTOUT(old_fpcr, FPCR_ESUM);

lib/libc/arch/aarch64/gen/fpsetround.c

52

return __SHIFTOUT(old_fpcr, FPCR_RMODE);

lib/libc/arch/aarch64/gen/fpsetsticky.c

52

return __SHIFTOUT(old_fpsr, FPSR_CSUM);

lib/libc/arch/arm/hardfloat/fpgetround.c

59

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RN, VFP_FPSCR_RMODE) == FP_RN);

lib/libc/arch/arm/hardfloat/fpgetround.c

60

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RP, VFP_FPSCR_RMODE) == FP_RP);

lib/libc/arch/arm/hardfloat/fpgetround.c

61

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RM, VFP_FPSCR_RMODE) == FP_RM);

lib/libc/arch/arm/hardfloat/fpgetround.c

62

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RZ, VFP_FPSCR_RMODE) == FP_RZ);

lib/libc/arch/arm/hardfloat/fpgetround.c

65

return __SHIFTOUT(fpscr, VFP_FPSCR_RMODE);

lib/libc/arch/arm/hardfloat/fpsetround.c

59

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RN, VFP_FPSCR_RMODE) == FP_RN);

lib/libc/arch/arm/hardfloat/fpsetround.c

60

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RP, VFP_FPSCR_RMODE) == FP_RP);

lib/libc/arch/arm/hardfloat/fpsetround.c

61

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RM, VFP_FPSCR_RMODE) == FP_RM);

lib/libc/arch/arm/hardfloat/fpsetround.c

62

__CTASSERT(__SHIFTOUT(VFP_FPSCR_RZ, VFP_FPSCR_RMODE) == FP_RZ);

lib/libc/arch/arm/hardfloat/fpsetround.c

65

fp_rnd old_rnd = __SHIFTOUT(fpscr, VFP_FPSCR_RMODE);

lib/libc/arch/m68k/hardfloat/flt_rounds.c

44

return __SHIFTOUT(fpcr, FPCR_ROUND) ^ 1;

lib/libc/arch/m68k/hardfloat/fpgetmask.c

46

return __SHIFTOUT(fpcr, FPCR_EXCP2);

lib/libc/arch/m68k/hardfloat/fpgetround.c

46

return __SHIFTOUT(fpcr, FPCR_ROUND);

lib/libc/arch/m68k/hardfloat/fpgetsticky.c

46

return __SHIFTOUT(fpsr, FPSR_AEX);

lib/libc/arch/m68k/hardfloat/fpsetmask.c

50

return __SHIFTOUT(old_fpcr, FPCR_EXCP2);

lib/libc/arch/m68k/hardfloat/fpsetround.c

50

return __SHIFTOUT(old_fpcr, FPCR_ROUND);

lib/libc/arch/m68k/hardfloat/fpsetsticky.c

50

return __SHIFTOUT(old_fpsr, FPSR_AEX);

lib/libc/arch/or1k/gen/fpgetround.c

56

return __SHIFTOUT(fpcsr, FPCSR_RND);

lib/libc/arch/riscv/gen/fpgetmask.c

53

return __SHIFTOUT(fcsr_read(), FCSR_FMASK);

lib/libc/arch/riscv/gen/fpsetmask.c

53

return __SHIFTOUT(fcsr_fmask_write(__SHIFTIN(mask, FCSR_MASK)), FCSR_FMASK);

lib/libc/locale/c16rtomb.c

180

c32 = __SHIFTIN(__SHIFTOUT(w1, __BITS(9,0)), __BITS(19,10)) |

lib/libc/locale/c16rtomb.c

181

__SHIFTIN(__SHIFTOUT(w2, __BITS(9,0)), __BITS(9,0));

lib/libc/locale/c8rtomb.c

196

state = __SHIFTOUT(S->state_c32, __BITS(31,24));

lib/libc/locale/c8rtomb.c

197

c32 = __SHIFTOUT(S->state_c32, __BITS(23,0));

lib/libc/locale/mbrtoc16.c

199

const char16_t w1 = 0xd800 | __SHIFTOUT(c32, __BITS(19,10));

lib/libc/locale/mbrtoc16.c

200

const char16_t w2 = 0xdc00 | __SHIFTOUT(c32, __BITS(9,0));

lib/libc/locale/mbrtoc8.c

198

*pc8 = 0xc0 | __SHIFTOUT(c32, __BITS(10,6));

lib/libc/locale/mbrtoc8.c

199

S->buf[2] = 0x80 | __SHIFTOUT(c32, __BITS(5,0));

lib/libc/locale/mbrtoc8.c

204

*pc8 = 0xe0 | __SHIFTOUT(c32, __BITS(15,12));

lib/libc/locale/mbrtoc8.c

205

S->buf[1] = 0x80 | __SHIFTOUT(c32, __BITS(11,6));

lib/libc/locale/mbrtoc8.c

206

S->buf[2] = 0x80 | __SHIFTOUT(c32, __BITS(5,0));

lib/libc/locale/mbrtoc8.c

211

*pc8 = 0xf0 | __SHIFTOUT(c32, __BITS(20,18));

lib/libc/locale/mbrtoc8.c

212

S->buf[0] = 0x80 | __SHIFTOUT(c32, __BITS(17,12));

lib/libc/locale/mbrtoc8.c

213

S->buf[1] = 0x80 | __SHIFTOUT(c32, __BITS(11,6));

lib/libc/locale/mbrtoc8.c

214

S->buf[2] = 0x80 | __SHIFTOUT(c32, __BITS(5,0));

lib/libkvm/kvm_aarch64.c

133

pte_addr += 8 * __SHIFTOUT(va, idx_mask);

lib/libkvm/kvm_aarch64.c

88

const u_int t1siz = __SHIFTOUT(cpu_kh->kh_tcr1, TCR_T1SZ);

lib/libkvm/kvm_m68k_gen.c

144

if (__SHIFTOUT(gen->srp[0], DT51_TYPE) != DT51_SHORT) {

lib/libkvm/kvm_m68k_gen.c

156

type = __SHIFTOUT(entry, DT51_TYPE);

lib/libkvm/kvm_m68k_gen.c

204

vmst->pgshift = __SHIFTOUT(gen->tcr, TCR51_PS);

lib/libkvm/kvm_m68k_gen.c

213

unsigned int is = __SHIFTOUT(gen->tcr, TCR51_IS);

lib/libkvm/kvm_m68k_gen.c

214

ti[0] = __SHIFTOUT(gen->tcr, TCR51_TIA);

lib/libkvm/kvm_m68k_gen.c

215

ti[1] = __SHIFTOUT(gen->tcr, TCR51_TIB);

lib/libkvm/kvm_m68k_gen.c

216

ti[2] = __SHIFTOUT(gen->tcr, TCR51_TIC);

lib/libkvm/kvm_m68k_gen.c

217

ti[3] = __SHIFTOUT(gen->tcr, TCR51_TID);

lib/libm/arch/aarch64/fenv.c

147

return __SHIFTOUT(reg_fpsr_read(), FPSR_CSUM) & excepts;

lib/libm/arch/aarch64/fenv.c

156

return __SHIFTOUT(reg_fpcr_read(), FPCR_RMODE);

lib/libm/arch/aarch64/fenv.c

168

_DIAGASSERT(!(round & ~__SHIFTOUT(FPCR_RMODE, FPCR_RMODE)));

lib/libm/arch/aarch64/fenv.c

241

return __SHIFTOUT(__fpcr, FPCR_ESUM);

lib/libm/arch/aarch64/fenv.c

249

return __SHIFTOUT(__fpcr, FPCR_ESUM);

lib/libm/arch/aarch64/fenv.c

256

return __SHIFTOUT(__fpcr, FPCR_ESUM);

lib/libm/arch/aarch64/fenv.c

94

*flagp = __SHIFTOUT(reg_fpsr_read(), FPSR_CSUM) & excepts;

lib/libm/arch/arm/fenv.c

145

return __SHIFTOUT(fpscr, VFP_FPSCR_ESUM) & FE_ALL_EXCEPT;

lib/libm/arch/arm/fenv.c

156

return __SHIFTOUT(fpscr, VFP_FPSCR_ESUM) & FE_ALL_EXCEPT;

lib/libm/arch/arm/fenv.c

168

return __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_CSUM) & excepts;

lib/libm/arch/arm/fenv.c

174

return __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_ESUM);

lib/libm/arch/arm/fenv.c

183

return __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_RMODE);

lib/libm/arch/arm/fenv.c

195

_DIAGASSERT(!(round & ~__SHIFTOUT(VFP_FPSCR_RMODE, VFP_FPSCR_RMODE)));

lib/libm/arch/arm/fenv.c

94

*flagp = __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_CSUM) & excepts;

lib/libm/arch/riscv/fenv.c

243

|| __SHIFTOUT(env, FCSR_FRM) > FCSR_FRM_RMM)) {

lib/libnvmm/libnvmm_x86.c

3344

val = __SHIFTOUT(val, instr->src.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3365

val = __SHIFTOUT(val, instr->dst.u.reg->mask);

sbin/efi/devpath2.c

67

text[0] = (char)__SHIFTOUT(u.b[0], __BITS(4,0));

sbin/efi/devpath2.c

68

text[1] = (char)__SHIFTOUT(u.b[0], __BITS(7,5));

sbin/efi/devpath2.c

69

text[1] |= (char)__SHIFTOUT(u.b[1], __BITS(1,0)) << 3;

sbin/efi/devpath2.c

70

text[2] = (char)__SHIFTOUT(u.b[1], __BITS(7,2));

sbin/efi/devpath3.c

1040

switch (__SHIFTOUT(LoginOptions, __BITS(1,0))) {

sbin/efi/devpath3.c

1051

switch (__SHIFTOUT(LoginOptions, __BITS(3,2))) {

sbin/efi/devpath3.c

1062

switch (__SHIFTOUT(LoginOptions, __BITS(12,10))) {

sbin/efi/devpath3.c

422

#define SASINFO_BYTES(b) __SHIFTOUT((b), SASINFO_BYTES_MASK)

sbin/nvmectl/firmware.c

262

if (slot > __SHIFTOUT(cdata.frmw, NVME_ID_CTRLR_FRMW_NSLOT))

sbin/nvmectl/firmware.c

266

(uint8_t)__SHIFTOUT(cdata.frmw, NVME_ID_CTRLR_FRMW_NSLOT));

sbin/nvmectl/identify.c

118

1 << __SHIFTOUT(cdata->sqes, NVME_ID_CTRLR_SQES_MAX));

sbin/nvmectl/identify.c

120

1 << __SHIFTOUT(cdata->sqes, NVME_ID_CTRLR_SQES_MIN));

sbin/nvmectl/identify.c

123

1 << __SHIFTOUT(cdata->cqes, NVME_ID_CTRLR_CQES_MAX));

sbin/nvmectl/identify.c

125

1 << __SHIFTOUT(cdata->cqes, NVME_ID_CTRLR_CQES_MIN));

sbin/nvmectl/identify.c

99

(uint8_t)__SHIFTOUT(cdata->frmw, NVME_ID_CTRLR_FRMW_NSLOT));

sbin/nvmectl/logpage.c

128

(uint8_t)__SHIFTOUT(pt.cpl.flags, NVME_CQE_SCT_MASK),

sbin/nvmectl/logpage.c

129

(uint8_t)__SHIFTOUT(pt.cpl.flags, NVME_CQE_SC_MASK));

sbin/nvmectl/logpage.c

178

(uint16_t)__SHIFTOUT(entry->status, NVME_CQE_PHASE));

sbin/nvmectl/logpage.c

180

(uint16_t)__SHIFTOUT(entry->status, NVME_CQE_SC_MASK));

sbin/nvmectl/logpage.c

182

(uint16_t)__SHIFTOUT(entry->status, NVME_CQE_SCT_MASK));

sbin/nvmectl/logpage.c

184

(uint16_t)__SHIFTOUT(entry->status, NVME_CQE_M));

sbin/nvmectl/logpage.c

186

(uint16_t)__SHIFTOUT(entry->status, NVME_CQE_DNR));

sbin/nvmectl/logpage.c

243

(uint8_t)__SHIFTOUT(health->critical_warning,

sbin/nvmectl/logpage.c

246

(uint8_t)__SHIFTOUT(health->critical_warning,

sbin/nvmectl/logpage.c

249

(uint8_t)__SHIFTOUT(health->critical_warning,

sbin/nvmectl/logpage.c

252

(uint8_t)__SHIFTOUT(health->critical_warning,

sbin/nvmectl/logpage.c

255

(uint8_t)__SHIFTOUT(health->critical_warning,

sbin/nvmectl/logpage.c

318

slots = MIN(__SHIFTOUT(cdata->frmw, NVME_ID_CTRLR_FRMW_NSLOT),

sbin/nvmectl/logpage.c

323

if (__SHIFTOUT(fw->afi, NVME_FW_PAGE_AFI_SLOT) == i + 1)

sbin/nvmectl/power.c

68

if (__SHIFTOUT(psd->ips, NVME_PSD_IPS_MASK) == 1)

sbin/nvmectl/power.c

71

if (__SHIFTOUT(psd->ap, NVME_PSD_APS_MASK) == 1)

sbin/nvmectl/power.c

83

(uint16_t)__SHIFTOUT(psd->ap, NVME_PSD_APW_MASK));

sbin/scsictl/scsictl.c

681

__SHIFTOUT(SINQ_DEVICE_ID_CODESET_BINARY, SINQ_DEVICE_ID_CODESET);

sbin/scsictl/scsictl.c

684

assoc = __SHIFTOUT(did->flags, SINQ_DEVICE_ID_ASSOCIATION);

sbin/scsictl/scsictl.c

685

proto = __SHIFTOUT(did->pc, SINQ_DEVICE_ID_PROTOCOL);

sbin/scsictl/scsictl.c

686

code = __SHIFTOUT(did->pc, SINQ_DEVICE_ID_CODESET);

sbin/scsictl/scsictl.c

687

type = __SHIFTOUT(did->flags, SINQ_DEVICE_ID_TYPE);

sys/arch/aarch64/aarch64/aarch64_tlb.c

50

KERNEL_PID :__SHIFTOUT(reg_ttbr0_el1_read(), TTBR_ASID);

sys/arch/aarch64/aarch64/cpu.c

260

variant = __SHIFTOUT(cpuid, CPU_ID_VARIANT_MASK);

sys/arch/aarch64/aarch64/cpu.c

261

revision = __SHIFTOUT(cpuid, CPU_ID_REVISION_MASK);

sys/arch/aarch64/aarch64/cpu.c

344

__SHIFTOUT(ctr, CTR_EL0_CWG_LINE) * 4,

sys/arch/aarch64/aarch64/cpu.c

345

__SHIFTOUT(ctr, CTR_EL0_ERG_LINE) * 4);

sys/arch/aarch64/aarch64/cpu.c

349

sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE),

sys/arch/aarch64/aarch64/cpu.c

350

sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_IMIN_LINE),

sys/arch/aarch64/aarch64/cpu.c

351

__SHIFTOUT(ctr, CTR_EL0_DIC),

sys/arch/aarch64/aarch64/cpu.c

352

__SHIFTOUT(ctr, CTR_EL0_IDC),

sys/arch/aarch64/aarch64/cpu.c

353

__SHIFTOUT(clidr, CLIDR_LOUU),

sys/arch/aarch64/aarch64/cpu.c

354

__SHIFTOUT(clidr, CLIDR_LOC),

sys/arch/aarch64/aarch64/cpu.c

355

__SHIFTOUT(clidr, CLIDR_LOUIS));

sys/arch/aarch64/aarch64/cpu.c

372

switch (__SHIFTOUT(id->ac_aa64dfr0, ID_AA64DFR0_EL1_PMUVER)) {

sys/arch/aarch64/aarch64/cpu.c

394

switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN4)) {

sys/arch/aarch64/aarch64/cpu.c

399

switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN16)) {

sys/arch/aarch64/aarch64/cpu.c

404

switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN64)) {

sys/arch/aarch64/aarch64/cpu.c

410

switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_ASIDBITS)) {

sys/arch/aarch64/aarch64/cpu.c

423

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV3)) {

sys/arch/aarch64/aarch64/cpu.c

428

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV2)) {

sys/arch/aarch64/aarch64/cpu.c

433

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_GIC)) {

sys/arch/aarch64/aarch64/cpu.c

438

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_FP)) {

sys/arch/aarch64/aarch64/cpu.c

447

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_CRC32)) {

sys/arch/aarch64/aarch64/cpu.c

452

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_SHA1)) {

sys/arch/aarch64/aarch64/cpu.c

457

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_SHA2)) {

sys/arch/aarch64/aarch64/cpu.c

462

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_AES)) {

sys/arch/aarch64/aarch64/cpu.c

470

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_RNDR)) {

sys/arch/aarch64/aarch64/cpu.c

477

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_DIT)) {

sys/arch/aarch64/aarch64/cpu.c

484

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {

sys/arch/aarch64/aarch64/cpu.c

493

switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_FPROUND)) {

sys/arch/aarch64/aarch64/cpu.c

498

switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_FPTRAP)) {

sys/arch/aarch64/aarch64/cpu.c

503

switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_FPDNAN)) {

sys/arch/aarch64/aarch64/cpu.c

508

switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_FPFTZ)) {

sys/arch/aarch64/aarch64/cpu.c

513

switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_SIMDREG)) {

sys/arch/aarch64/aarch64/cpu.c

521

switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_SIMDFMAC)) {

sys/arch/aarch64/aarch64/cpu.c

538

const u_int pmuver = __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_PMUVER);

sys/arch/aarch64/aarch64/cpu.c

677

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_RNDR)) {

sys/arch/aarch64/aarch64/cpu.c

708

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_AES)) {

sys/arch/aarch64/aarch64/cpu.c

718

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {

sys/arch/aarch64/aarch64/cpu.c

736

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {

sys/arch/aarch64/aarch64/cpufunc.c

110

switch (__SHIFTOUT(ctr, CTR_EL0_L1IP_MASK)) {

sys/arch/aarch64/aarch64/cpufunc.c

186

if (arm_dcache_maxline < __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE)) {

sys/arch/aarch64/aarch64/cpufunc.c

187

arm_dcache_maxline = __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE);

sys/arch/aarch64/aarch64/cpufunc.c

454

if (__SHIFTOUT(ctr, CTR_EL0_DIC) == 1) {

sys/arch/aarch64/aarch64/cpufunc.c

458

} else if (__SHIFTOUT(ctr, CTR_EL0_IDC) == 1 ||

sys/arch/aarch64/aarch64/cpufunc.c

459

__SHIFTOUT(clidr, CLIDR_LOC) == 0 ||

sys/arch/aarch64/aarch64/cpufunc.c

460

(__SHIFTOUT(clidr, CLIDR_LOUIS) == 0 && __SHIFTOUT(clidr, CLIDR_LOUU) == 0)) {

sys/arch/aarch64/aarch64/cpufunc.c

488

hafdbs = __SHIFTOUT(reg_id_aa64mmfr1_el1_read(),

sys/arch/aarch64/aarch64/cpufunc.c

555

if (__SHIFTOUT(reg, ID_AA64MMFR1_EL1_PAN) !=

sys/arch/aarch64/aarch64/cpufunc.c

590

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_APA) !=

sys/arch/aarch64/aarch64/cpufunc.c

593

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_API) !=

sys/arch/aarch64/aarch64/cpufunc.c

596

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_GPA) !=

sys/arch/aarch64/aarch64/cpufunc.c

599

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_GPI) !=

sys/arch/aarch64/aarch64/cpufunc.c

78

switch (__SHIFTOUT(mmfr2, ID_AA64MMFR2_EL1_CCIDX)) {

sys/arch/aarch64/aarch64/cpufunc.c

81

1 << (__SHIFTOUT(ccsidr, CCSIDR_LINESIZE) + 4);

sys/arch/aarch64/aarch64/cpufunc.c

82

cunit->cache_ways = __SHIFTOUT(ccsidr, CCSIDR_ASSOC) + 1;

sys/arch/aarch64/aarch64/cpufunc.c

83

cunit->cache_sets = __SHIFTOUT(ccsidr, CCSIDR_NUMSET) + 1;

sys/arch/aarch64/aarch64/cpufunc.c

87

1 << (__SHIFTOUT(ccsidr, CCSIDR64_LINESIZE) + 4);

sys/arch/aarch64/aarch64/cpufunc.c

88

cunit->cache_ways = __SHIFTOUT(ccsidr, CCSIDR64_ASSOC) + 1;

sys/arch/aarch64/aarch64/cpufunc.c

89

cunit->cache_sets = __SHIFTOUT(ccsidr, CCSIDR64_NUMSET) + 1;

sys/arch/aarch64/aarch64/db_interface.c

446

pr(", ATTR(%lu)", __SHIFTOUT(pte, LX_BLKPAG_ATTR_INDX));

sys/arch/aarch64/aarch64/db_machdep.c

1157

if (__SHIFTOUT(tf->tf_esr, ESR_ISS) == 0xffff)

sys/arch/aarch64/aarch64/db_machdep.c

459

paddr_t pa = (__SHIFTOUT(par, PAR_PA) << PAR_PA_SHIFT) +

sys/arch/aarch64/aarch64/db_machdep.c

462

if (__SHIFTOUT(par, PAR_F) == 0) {

sys/arch/aarch64/aarch64/db_machdep.c

470

__SHIFTOUT(par, PAR_ATTR),

sys/arch/aarch64/aarch64/db_machdep.c

471

__SHIFTOUT(par, PAR_NS),

sys/arch/aarch64/aarch64/db_machdep.c

472

__SHIFTOUT(par, PAR_SH),

sys/arch/aarch64/aarch64/db_machdep.c

481

__SHIFTOUT(par, PAR_S),

sys/arch/aarch64/aarch64/db_machdep.c

482

__SHIFTOUT(par, PAR_PTW),

sys/arch/aarch64/aarch64/db_machdep.c

483

__SHIFTOUT(par, PAR_FST));

sys/arch/aarch64/aarch64/db_machdep.c

843

cpu_max_breakpoint = __SHIFTOUT(dfr, ID_AA64DFR0_EL1_BRPS);

sys/arch/aarch64/aarch64/db_machdep.c

844

cpu_max_watchpoint = __SHIFTOUT(dfr, ID_AA64DFR0_EL1_WRPS);

sys/arch/aarch64/aarch64/db_machdep.c

867

const u_int cpu_max_breakpoint = __SHIFTOUT(dfr, ID_AA64DFR0_EL1_BRPS);

sys/arch/aarch64/aarch64/db_machdep.c

868

const u_int cpu_max_watchpoint = __SHIFTOUT(dfr, ID_AA64DFR0_EL1_WRPS);

sys/arch/aarch64/aarch64/db_trace.c

89

eclass_trapname(__SHIFTOUT(tf_buf.tf_esr, ESR_EC)),

sys/arch/aarch64/aarch64/exec_machdep.c

91

if (__SHIFTOUT(l->l_cpu->ci_id.ac_aa64pfr0, ID_AA64PFR0_EL1_EL0) !=

sys/arch/aarch64/aarch64/fault.c

108

fsc = __SHIFTOUT(esr, ESR_ISS_DATAABORT_DFSC);

sys/arch/aarch64/aarch64/fault.c

158

rw = __SHIFTOUT(esr, ESR_ISS_DATAABORT_WnR); /* 0 if IFSC */

sys/arch/aarch64/aarch64/fault.c

182

else if (__SHIFTOUT(esr, ESR_ISS_DATAABORT_CM))

sys/arch/aarch64/aarch64/fault.c

244

fsc = __SHIFTOUT(esr, ESR_ISS_DATAABORT_DFSC); /* also IFSC */

sys/arch/aarch64/aarch64/fault.c

336

if (__SHIFTOUT(esr, ESR_EC) == ESR_EC_DATA_ABT_EL1 ||

sys/arch/aarch64/aarch64/fault.c

337

__SHIFTOUT(esr, ESR_EC) == ESR_EC_DATA_ABT_EL0)

sys/arch/aarch64/aarch64/fault.c

344

if (__SHIFTOUT(esr, ESR_ISS_DATAABORT_EA) != 0)

sys/arch/aarch64/aarch64/fault.c

348

if (__SHIFTOUT(esr, ESR_ISS_DATAABORT_S1PTW) != 0)

sys/arch/aarch64/aarch64/fpu.c

104

switch (__SHIFTOUT(mvfr1, MVFR1_FPDNAN)) {

sys/arch/aarch64/aarch64/fpu.c

120

switch (__SHIFTOUT(mvfr1, MVFR1_FPFTZ)) {

sys/arch/aarch64/aarch64/fpu.c

94

switch (__SHIFTOUT(mvfr1, MVFR1_FPHP)) {

sys/arch/aarch64/aarch64/netbsd32_machdep.c

406

if (__SHIFTOUT(spsr, SPSR_M) != SPSR_M_USR32)

sys/arch/aarch64/aarch64/pmap.c

746

pa = (__SHIFTOUT(par, PAR_PA) << PAR_PA_SHIFT) +

sys/arch/aarch64/aarch64/pmap_machdep.c

468

pm->pm_l0_pa = __SHIFTOUT(reg_ttbr1_el1_read(), TTBR_BADDR);

sys/arch/aarch64/aarch64/pmapboot.c

486

Ln_ENTRIES - __SHIFTOUT(va, L3_ADDR_BITS));

sys/arch/aarch64/aarch64/pmapboot.c

499

Ln_ENTRIES - __SHIFTOUT(va, L2_ADDR_BITS));

sys/arch/aarch64/aarch64/procfs_machdep.c

201

__SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_IMPLEMENTOR_MASK));

sys/arch/aarch64/aarch64/procfs_machdep.c

204

__SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_VARIANT_MASK));

sys/arch/aarch64/aarch64/procfs_machdep.c

206

__SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_PARTNO_MASK));

sys/arch/aarch64/aarch64/procfs_machdep.c

208

__SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_REVISION_MASK));

sys/arch/aarch64/aarch64/procfs_machdep.c

79

#define SO_EQ(reg, mask, val) (__SHIFTOUT((reg), (mask)) == (val))

sys/arch/aarch64/aarch64/trap.c

1001

const uint32_t eclass = __SHIFTOUT(ksi->ksi_trap, ESR_EC);

sys/arch/aarch64/aarch64/trap.c

201

const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */

sys/arch/aarch64/aarch64/trap.c

222

if (__SHIFTOUT(esr, ESR_ISS) == 0x40d &&

sys/arch/aarch64/aarch64/trap.c

288

if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DMIN_LINE) >

sys/arch/aarch64/aarch64/trap.c

289

__SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) ||

sys/arch/aarch64/aarch64/trap.c

290

(__SHIFTOUT(ctr_el0_raw, CTR_EL0_IMIN_LINE) >

sys/arch/aarch64/aarch64/trap.c

291

__SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE)))

sys/arch/aarch64/aarch64/trap.c

294

if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DIC) == 1 &&

sys/arch/aarch64/aarch64/trap.c

295

__SHIFTOUT(ctr_el0_usr, CTR_EL0_DIC) == 0) ||

sys/arch/aarch64/aarch64/trap.c

296

(__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 1 &&

sys/arch/aarch64/aarch64/trap.c

297

__SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 0))

sys/arch/aarch64/aarch64/trap.c

305

if (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 0 &&

sys/arch/aarch64/aarch64/trap.c

306

__SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 1)

sys/arch/aarch64/aarch64/trap.c

334

if (__SHIFTOUT(clidr, CLIDR_LOC) == 0 ||

sys/arch/aarch64/aarch64/trap.c

335

(__SHIFTOUT(clidr, CLIDR_LOUIS) == 0 &&

sys/arch/aarch64/aarch64/trap.c

336

__SHIFTOUT(clidr, CLIDR_LOUU) == 0)) {

sys/arch/aarch64/aarch64/trap.c

346

if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1)

sys/arch/aarch64/aarch64/trap.c

351

__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1)

sys/arch/aarch64/aarch64/trap.c

362

if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DMIN_LINE) <

sys/arch/aarch64/aarch64/trap.c

363

__SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) {

sys/arch/aarch64/aarch64/trap.c

368

(__SHIFTOUT(ctr_el0_cpu, CTR_EL0_IMIN_LINE) <

sys/arch/aarch64/aarch64/trap.c

369

__SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) {

sys/arch/aarch64/aarch64/trap.c

414

const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */

sys/arch/aarch64/aarch64/trap.c

685

Rn = __SHIFTOUT(insn, 0x000f0000);

sys/arch/aarch64/aarch64/trap.c

686

Rd = __SHIFTOUT(insn, 0x0000f000);

sys/arch/aarch64/aarch64/trap.c

687

Rm = __SHIFTOUT(insn, 0x0000000f);

sys/arch/aarch64/aarch64/trap.c

826

const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */

sys/arch/aarch64/include/cpufunc.h

136

return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1);

sys/arch/aarch64/include/locore.h

44

msr daifclr, #__SHIFTOUT(DAIF_I | DAIF_F, DAIF_MASK)

sys/arch/aarch64/include/locore.h

46

msr daifset, #__SHIFTOUT(DAIF_I | DAIF_F, DAIF_MASK)

sys/arch/aarch64/include/locore.h

62

reg_daifclr_write(__SHIFTOUT(DAIF_I | DAIF_F, DAIF_MASK))

sys/arch/aarch64/include/locore.h

64

reg_daifset_write(__SHIFTOUT(DAIF_I | DAIF_F, DAIF_MASK))

sys/arch/aarch64/include/locore.h

74

reg_daifclr_write(__SHIFTOUT(psw, DAIF_MASK));

sys/arch/aarch64/include/locore.h

86

reg_daifset_write(__SHIFTOUT(psw, DAIF_MASK));

sys/arch/aarch64/include/pmap.h

69

switch (__SHIFTOUT(reg_id_aa64mmfr0_el1_read(), ID_AA64MMFR0_EL1_ASIDBITS)) {

sys/arch/alpha/alpha/fp_complete.c

661

rm != __SHIFTOUT(fpcr, FPCR_DYN_RM))) {

sys/arch/alpha/pci/lca.c

137

lca_bcache_sizes[__SHIFTOUT(car, MEMC_CAR_BCS)];

sys/arch/alpha/pci/lca.c

97

static const u_int lca_bcache_sizes[__SHIFTOUT(MEMC_CAR_BCS, MEMC_CAR_BCS)] = {

sys/arch/alpha/pci/pci_machdep.c

478

return __SHIFTOUT(ihp->value, ALPHA_PCI_INTR_HANDLE_IRQ);

sys/arch/alpha/pci/pci_machdep.c

492

return __SHIFTOUT(ihp->value, ALPHA_PCI_INTR_HANDLE_FLAGS);

sys/arch/alpha/pci/pci_machdep.c

540

*busp = __SHIFTOUT(tag, PCI_CONF_TYPE1_BUS);

sys/arch/alpha/pci/pci_machdep.c

542

*devp = __SHIFTOUT(tag, PCI_CONF_TYPE1_DEVICE);

sys/arch/alpha/pci/pci_machdep.c

544

*funcp = __SHIFTOUT(tag, PCI_CONF_TYPE1_FUNCTION);

sys/arch/alpha/pci/sio_pic.c

569

const int irq = __SHIFTOUT(pirqreg, PIRQ_RTCTRL_IRQ);

sys/arch/amd64/include/msan.h

209

*type = __SHIFTOUT(orig, __MD_ORIG_TYPE);

sys/arch/arm/acpi/acpi_pci_machdep.c

447

const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/acpi/acpi_pci_machdep.c

448

const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC);

sys/arch/arm/acpi/acpi_pci_machdep.c

549

const int irq = (int)__SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/acpi/gic_acpi.c

81

return __SHIFTOUT(reg_id_aa64pfr0_el1_read(), ID_AA64PFR0_EL1_GIC) == 0;

sys/arch/arm/acpi/gic_v2m_acpi.c

110

frame->frame_base = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE);

sys/arch/arm/acpi/gic_v2m_acpi.c

111

frame->frame_count = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER);

sys/arch/arm/acpi/gicv3_acpi.c

94

return __SHIFTOUT(reg_id_aa64pfr0_el1_read(), ID_AA64PFR0_EL1_GIC) != 0;

sys/arch/arm/altera/cycv_clkmgr.c

385

numer = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1;

sys/arch/arm/altera/cycv_clkmgr.c

386

denom = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1;

sys/arch/arm/altera/cycv_clkmgr.c

498

numer = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1;

sys/arch/arm/altera/cycv_clkmgr.c

499

divisor = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1;

sys/arch/arm/altera/cycv_clkmgr.c

587

parent_index = __SHIFTOUT(tmp, mux->mask);

sys/arch/arm/altera/cycv_clkmgr.c

621

(__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1) /

sys/arch/arm/altera/cycv_clkmgr.c

622

(__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1);

sys/arch/arm/altera/cycv_clkmgr.c

625

return vco / 2 / (__SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MPUCLK_CNT) + 1);

sys/arch/arm/altera/cycv_clkmgr.c

640

if (__SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_L4SRC_L4SP) == 0) {

sys/arch/arm/altera/cycv_clkmgr.c

643

(__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1) /

sys/arch/arm/altera/cycv_clkmgr.c

644

(__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1);

sys/arch/arm/altera/cycv_clkmgr.c

646

tmp = __SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MAINCLK_CNT);

sys/arch/arm/altera/cycv_clkmgr.c

652

(__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1) /

sys/arch/arm/altera/cycv_clkmgr.c

653

(__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1);

sys/arch/arm/altera/cycv_clkmgr.c

656

tmp = __SHIFTOUT(tmp, CYCV_CLKMGR_PERI_PLL_PERBASECLK_CNT);

sys/arch/arm/altera/cycv_clkmgr.c

662

tmp = __SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MAINDIV_L4SP);

sys/arch/arm/amlogic/meson8b_clkc.c

141

if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_PLLSEL) != 1) {

sys/arch/arm/amlogic/meson8b_clkc.c

145

if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_SOUTSEL) != 0) {

sys/arch/arm/amlogic/meson_clk_div.c

64

ratio = __SHIFTOUT(val, div->div);

sys/arch/arm/amlogic/meson_clk_mpll.c

64

sdm = __SHIFTOUT(val, mpll->sdm.mask);

sys/arch/arm/amlogic/meson_clk_mpll.c

67

n2 = __SHIFTOUT(val, mpll->n2.mask);

sys/arch/arm/amlogic/meson_clk_mux.c

52

sel = __SHIFTOUT(val, mux->sel);

sys/arch/arm/amlogic/meson_clk_pll.c

132

m_max = __SHIFTOUT(pll->m.mask, pll->m.mask);

sys/arch/arm/amlogic/meson_clk_pll.c

133

frac_max = __SHIFTOUT(pll->frac.mask, pll->frac.mask);

sys/arch/arm/amlogic/meson_clk_pll.c

63

n = __SHIFTOUT(val, pll->n.mask);

sys/arch/arm/amlogic/meson_clk_pll.c

66

m = __SHIFTOUT(val, pll->m.mask);

sys/arch/arm/amlogic/meson_clk_pll.c

70

frac = __SHIFTOUT(val, pll->frac.mask);

sys/arch/arm/amlogic/meson_pinctrl.c

245

val = __SHIFTOUT(data, gpio_reg->mask);

sys/arch/arm/amlogic/meson_platform.c

353

const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/amlogic/meson_pwm.c

135

clk_div = __SHIFTOUT(val, MESON_PWM_MISC_AB_A_CLK_DIV);

sys/arch/arm/amlogic/meson_pwm.c

137

hi = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_HIGH);

sys/arch/arm/amlogic/meson_pwm.c

138

lo = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_LOW);

sys/arch/arm/amlogic/meson_pwm.c

142

clk_div = __SHIFTOUT(val, MESON_PWM_MISC_AB_B_CLK_DIV);

sys/arch/arm/amlogic/meson_pwm.c

144

hi = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_HIGH);

sys/arch/arm/amlogic/meson_pwm.c

145

lo = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_LOW);

sys/arch/arm/amlogic/meson_pwm.c

221

old_div = __SHIFTOUT(val, MESON_PWM_MISC_AB_A_CLK_DIV);

sys/arch/arm/amlogic/meson_pwm.c

230

old_hi = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_HIGH);

sys/arch/arm/amlogic/meson_pwm.c

231

old_lo = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_LOW);

sys/arch/arm/amlogic/meson_pwm.c

241

old_div = __SHIFTOUT(val, MESON_PWM_MISC_AB_B_CLK_DIV);

sys/arch/arm/amlogic/meson_pwm.c

250

old_hi = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_HIGH);

sys/arch/arm/amlogic/meson_pwm.c

251

old_lo = __SHIFTOUT(val, MESON_PWM_DUTYCYCLE_LOW);

sys/arch/arm/amlogic/meson_rtc.c

207

data |= __SHIFTOUT(RTC_READ(sc, AO_RTC_REG1), AO_RTC_REG1_SDO);

sys/arch/arm/amlogic/meson_sdhc.c

365

const u_int clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV);

sys/arch/arm/amlogic/meson_sdhc.c

926

clk_div = __SHIFTOUT(clkc, SD_CLKC_CLK_DIV);

sys/arch/arm/amlogic/mesong12_clkc.c

1302

m = __SHIFTOUT(val, __BITS(7,0));

sys/arch/arm/amlogic/mesong12_clkc.c

1303

n = __SHIFTOUT(val, __BITS(14,10));

sys/arch/arm/amlogic/mesong12_clkc.c

1304

div_shift = __SHIFTOUT(val, __BITS(18,16));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

177

return __SHIFTOUT(val, USB3PCIEPHY_R5_PHY_CR_DATA_OUT);

sys/arch/arm/apple/apple_dart.c

247

int32_t code = __SHIFTOUT(status, DART_ERR_CODE_MASK);

sys/arch/arm/apple/apple_dart.c

665

KASSERTMSG(__SHIFTOUT(pa, __BITS(DART_TTBR_SHIFT - 1, 0)) == 0,

sys/arch/arm/apple/apple_dart.c

98

#define DART_L2_SUBPAGE(addr) __SHIFTOUT((addr), __BITS(13, 2))

sys/arch/arm/apple/apple_intc.c

314

evtype = __SHIFTOUT(ev, AIC_EVENT_TYPE);

sys/arch/arm/apple/apple_intc.c

315

evdata = __SHIFTOUT(ev, AIC_EVENT_DATA);

sys/arch/arm/apple/apple_pcie.c

158

u_int portno = __SHIFTOUT(be32toh(reg[0]), __BITS(13,11));

sys/arch/arm/apple/apple_pcie.c

198

__SHIFTOUT(sc->sc_msi_addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

491

__SHIFTOUT(addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

493

__SHIFTOUT(addr, __BITS(63, 32)));

sys/arch/arm/apple/apple_pcie.c

497

__SHIFTOUT(addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

543

__SHIFTOUT(addr, __BITS(31, 0)));

sys/arch/arm/apple/apple_pcie.c

545

__SHIFTOUT(addr, __BITS(63, 32)));

sys/arch/arm/apple/apple_pcie.c

686

const int msino = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/apple/apple_pcie.c

704

const int msino = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ);

sys/arch/arm/apple/apple_pinctrl.c

176

int val = __SHIFTOUT(reg, GPIO_PIN_DATA);

sys/arch/arm/apple/apple_pinctrl.c

61

#define APPLE_PIN(pinmux) __SHIFTOUT((pinmux), __BITS(15, 0))

sys/arch/arm/apple/apple_pinctrl.c

62

#define APPLE_FUNC(pinmux) __SHIFTOUT((pinmux), __BITS(31, 16))

sys/arch/arm/apple/apple_platform.c

221

const u_int aff2 = __SHIFTOUT(cpuid, MPIDR_AFF2);

sys/arch/arm/apple/apple_pmgr.c

93

if (__SHIFTOUT(val, PMGR_PS_ACTUAL_MASK) == pstate)

sys/arch/arm/apple/apple_rtkit.c

38

#define RTKIT_MGMT_TYPE(x) __SHIFTOUT((x), RTKIT_MGMT_TYPE_MASK)

sys/arch/arm/apple/apple_rtkit.c

41

#define RTKIT_MGMT_PWR_STATE(x) __SHIFTOUT((x), RTKIT_MGMT_PWR_STATE_MASK)

sys/arch/arm/apple/apple_rtkit.c

52

#define RTKIT_MGMT_HELLO_MINVER(x) __SHIFTOUT((x), RTKIT_MGMT_HELLO_MINVER_MASK)

sys/arch/arm/apple/apple_rtkit.c

54

#define RTKIT_MGMT_HELLO_MAXVER(x) __SHIFTOUT((x), RTKIT_MGMT_HELLO_MAXVER_MASK)

sys/arch/arm/apple/apple_rtkit.c

62

#define RTKIT_MGMT_EPMAP_BASE(x) __SHIFTOUT((x), RTKIT_MGMT_EPMAP_BASE_MASK)

sys/arch/arm/apple/apple_rtkit.c

64

#define RTKIT_MGMT_EPMAP_BITMAP(x) __SHIFTOUT((x), RTKIT_MGMT_EPMAP_BITMAP_MASK)

sys/arch/arm/apple/apple_rtkit.c

69

#define RTKIT_BUFFER_ADDR(x) __SHIFTOUT((x), RTKIT_BUFFER_ADDR_MASK)

sys/arch/arm/apple/apple_rtkit.c

71

#define RTKIT_BUFFER_SIZE(x) __SHIFTOUT((x), RTKIT_BUFFER_SIZE_MASK)

sys/arch/arm/apple/apple_smc.c

283

key |= __SHIFTIN(digits[__SHIFTOUT(pn, __BITS(3, 0))], __BITS(7, 0));

sys/arch/arm/apple/apple_smc.c

284

key |= __SHIFTIN(digits[__SHIFTOUT(pn, __BITS(7, 4))], __BITS(15, 8));

sys/arch/arm/apple/apple_smc.c

81

#define SMC_ERROR(d) __SHIFTOUT((d), SMC_ERROR_MASK)

sys/arch/arm/arm/arm_cpu_topology.c

59

pkgid = __SHIFTOUT(mpidr, MPIDR_AFF2);

sys/arch/arm/arm/arm_cpu_topology.c

60

coreid = __SHIFTOUT(mpidr, MPIDR_AFF1);

sys/arch/arm/arm/arm_cpu_topology.c

61

smtid = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/arm/arm_cpu_topology.c

63

pkgid = __SHIFTOUT(mpidr, MPIDR_AFF1);

sys/arch/arm/arm/arm_cpu_topology.c

64

coreid = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/arm/cpufunc.c

3015

__SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_VARIANT_MASK), __BITS(7,4)) |

sys/arch/arm/arm/cpufunc.c

3016

__SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_REVISION_MASK), __BITS(3,0)) |

sys/arch/arm/arm/cpufunc.c

3576

return __SHIFTOUT(armreg_mpidr_read(), MPIDR_AFF1);

sys/arch/arm/arm/disassem.c

910

if (__SHIFTOUT(insn, __BIT(21)))

sys/arch/arm/arm/syscall.c

201

const uint32_t swi = __SHIFTOUT(insn, __BITS(23,0));

sys/arch/arm/arm32/arm32_tlb.c

166

const tlb_asid_t asid = __SHIFTOUT(d,

sys/arch/arm/arm32/arm32_tlb.c

199

const tlb_asid_t asid = __SHIFTOUT(d01,

sys/arch/arm/arm32/cpu.c

890

if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) {

sys/arch/arm/arm32/db_machdep.c

271

const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE);

sys/arch/arm/arm32/db_machdep.c

272

return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1)

sys/arch/arm/arm32/db_machdep.c

285

const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA);

sys/arch/arm/arm32/db_machdep.c

290

const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE);

sys/arch/arm/arm32/db_machdep.c

291

const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM);

sys/arch/arm/arm32/db_machdep.c

292

const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP);

sys/arch/arm/arm32/db_machdep.c

298

const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID);

sys/arch/arm/arm32/db_machdep.c

302

const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX);

sys/arch/arm/arm32/db_machdep.c

332

const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE);

sys/arch/arm/arm32/db_machdep.c

337

return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1)

sys/arch/arm/arm32/db_machdep.c

348

const paddr_t pfn = __SHIFTOUT(d12, ARM_A7_TLBDATA12_PA);

sys/arch/arm/arm32/db_machdep.c

353

const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE);

sys/arch/arm/arm32/db_machdep.c

354

const u_int domain = __SHIFTOUT(d2, ARM_A7_TLBDATA2_DOM);

sys/arch/arm/arm32/db_machdep.c

355

const u_int ap = __SHIFTOUT(d1, ARM_A7_TLBDATA1_AP);

sys/arch/arm/arm32/db_machdep.c

361

const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID);

sys/arch/arm/arm32/db_machdep.c

365

const u_int is = __SHIFTOUT(d2, ARM_A7_TLBDATA2_IS);

sys/arch/arm/arm32/db_machdep.c

367

u_int mt = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SDO_MT);

sys/arch/arm/arm32/db_machdep.c

380

const u_int os = __SHIFTOUT(d2, ARM_A7_TLBDATA2_OS);

sys/arch/arm/arm32/db_machdep.c

381

const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH);

sys/arch/arm/arm32/pmap.c

7810

if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) {

sys/arch/arm/arm32/pmap.c

7833

if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) {

sys/arch/arm/arm32/pmap.c

7835

} else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) {

sys/arch/arm/broadcom/bcm2835_intr.c

704

uint32_t mask = __SHIFTOUT(irq_mask, BCM2836MP_TIMER_IRQS);

sys/arch/arm/broadcom/bcm2835_intr.c

717

uint32_t mask = __SHIFTOUT(irq_mask, BCM2836MP_MAILBOX_IRQS);

sys/arch/arm/broadcom/bcm2835_intr.c

751

uint32_t mask = __SHIFTOUT(irq_mask, BCM2836MP_TIMER_IRQS);

sys/arch/arm/broadcom/bcm2835_intr.c

760

uint32_t mask = __SHIFTOUT(irq_mask, BCM2836MP_MAILBOX_IRQS);

sys/arch/arm/broadcom/bcm2835_pwm.c

266

w = __SHIFTIN(__SHIFTOUT(w, pwm->stamask), PWM_STA_STA)

sys/arch/arm/broadcom/bcm2835_pwm.c

267

| __SHIFTIN(__SHIFTOUT(w, pwm->gapomask), PWM_STA_GAPO)

sys/arch/arm/broadcom/bcm2835_rng.c

137

cnt = __SHIFTOUT(status, RNG_STATUS_CNT);

sys/arch/arm/broadcom/bcm2838_pcie.c

341

switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) {

sys/arch/arm/broadcom/bcm2838_pcie.c

365

__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) {

sys/arch/arm/broadcom/bcm2838_pcie.c

373

__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64 ? 64 : 32,

sys/arch/arm/broadcom/bcm2838_pcie.c

463

(u_int)__SHIFTOUT(w, PCIE_MISC_REVISION_MAJMIN));

sys/arch/arm/broadcom/bcm2838_pcie.c

783

const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/broadcom/bcm2838_pcie.c

784

const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC);

sys/arch/arm/broadcom/bcm283x_platform.c

868

const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/broadcom/bcm283x_platform.c

885

const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/broadcom/bcm53xx_board.c

161

const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW)

sys/arch/arm/broadcom/bcm53xx_board.c

162

- __SHIFTOUT(v82, CTL_82_ROW_DIFF);

sys/arch/arm/broadcom/bcm53xx_board.c

163

const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL)

sys/arch/arm/broadcom/bcm53xx_board.c

164

- __SHIFTOUT(v82, CTL_82_COL_DIFF);

sys/arch/arm/broadcom/bcm53xx_board.c

165

const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF);

sys/arch/arm/broadcom/bcm53xx_board.c

170

const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL);

sys/arch/arm/broadcom/bcm53xx_board.c

171

u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP);

sys/arch/arm/broadcom/bcm53xx_board.c

214

return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1;

sys/arch/arm/broadcom/bcm53xx_board.c

225

const uint32_t ndiv_frac = __SHIFTOUT(control5,

sys/arch/arm/broadcom/bcm53xx_board.c

253

const uint32_t ndiv_frac = __SHIFTOUT(control1,

sys/arch/arm/broadcom/bcm53xx_board.c

325

u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV);

sys/arch/arm/broadcom/bcm53xx_board.c

326

u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV);

sys/arch/arm/broadcom/bcm53xx_board.c

327

u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV);

sys/arch/arm/broadcom/bcm53xx_board.c

331

clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ);

sys/arch/arm/broadcom/bcm53xx_board.c

342

policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2);

sys/arch/arm/broadcom/bcm53xx_board.c

358

const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC);

sys/arch/arm/broadcom/bcm53xx_board.c

436

cpu->cpu_chipid = __SHIFTOUT(chipid, CHIPID_ID);

sys/arch/arm/broadcom/bcm53xx_cca.c

168

(u_int)__SHIFTOUT(chipid, CHIPID_ID),

sys/arch/arm/broadcom/bcm53xx_cca.c

169

(u_int)('A' + (__SHIFTOUT(chipid, CHIPID_REV) >> 2)),

sys/arch/arm/broadcom/bcm53xx_cca.c

170

(u_int)(__SHIFTOUT(chipid, CHIPID_REV) & 3));

sys/arch/arm/broadcom/bcm53xx_eth.c

1048

uint32_t currdscr = __SHIFTOUT(rcvsts0, RCV_CURRDSCR);

sys/arch/arm/broadcom/bcm53xx_eth.c

1077

? __SHIFTOUT(rxsts, RXSTS_DESC_COUNT) + 1 : 1;

sys/arch/arm/broadcom/bcm53xx_eth.c

1079

size_t desc_count = __SHIFTOUT(rxsts, RXSTS_DESC_COUNT) + 1;

sys/arch/arm/broadcom/bcm53xx_eth.c

1129

uint32_t framelen = __SHIFTOUT(rxsts, RXSTS_FRAMELEN);

sys/arch/arm/broadcom/bcm53xx_eth.c

1619

if (consumer == txq->txq_first + __SHIFTOUT(s0, XMT_CURRDSCR)) {

sys/arch/arm/broadcom/bcm53xx_eth.c

1795

uint32_t descs = __SHIFTOUT(rcvsts0, RCV_CURRDSCR);

sys/arch/arm/broadcom/bcm53xx_eth.c

1810

const uint32_t framecount = __SHIFTOUT(sc->sc_rcvlazy,

sys/arch/arm/broadcom/bcm53xx_eth.c

486

KASSERT(sc->sc_rcvoffset <= __SHIFTOUT(RCVCTL_RCVOFFSET, RCVCTL_RCVOFFSET));

sys/arch/arm/broadcom/bcm53xx_eth.c

629

if (__SHIFTOUT(tx0, XMTSTATE) == XMTSTATE_DIS

sys/arch/arm/broadcom/bcm53xx_eth.c

630

&& __SHIFTOUT(rx0, RCVSTATE) == RCVSTATE_DIS)

sys/arch/arm/broadcom/bcm53xx_mdio.c

146

int val = __SHIFTOUT(bcmmdio_read_4(sc, MIICMD), MIICMD_DATA);

sys/arch/arm/broadcom/bcm53xx_mdio.c

95

uint32_t div = __SHIFTOUT(miimgt, MIIMGT_MDCDIV);

sys/arch/arm/broadcom/bcm53xx_pax.c

304

sc->sc_linkup = __SHIFTOUT(lcsr, PCIE_LCSR_NLW) != 0

sys/arch/arm/broadcom/bcm53xx_pax.c

309

lcsr, __SHIFTOUT(lcsr, PCIE_LCSR_NLW),

sys/arch/arm/broadcom/bcm53xx_pax.c

393

*busp = __SHIFTOUT(tag, CFG_ADDR_BUS);

sys/arch/arm/broadcom/bcm53xx_pax.c

395

*devp = __SHIFTOUT(tag, CFG_ADDR_DEV);

sys/arch/arm/broadcom/bcm53xx_pax.c

397

*funcp = __SHIFTOUT(tag, CFG_ADDR_FUNC);

sys/arch/arm/broadcom/bcm53xx_pax.c

413

uint32_t reg = __SHIFTOUT(tag, CFG_ADDR_REG);

sys/arch/arm/broadcom/bcm53xx_pax.c

414

uint32_t func = __SHIFTOUT(tag, CFG_ADDR_FUNC);

sys/arch/arm/broadcom/bcm53xx_rng.c

167

size_t nwords = __SHIFTOUT(bcmrng_read_4(sc, RNG_STATUS), RNG_VAL);

sys/arch/arm/cortex/a9wdt.c

207

__SHIFTOUT(sc->sc_wdog_ctl, TMR_CTL_PRESCALER) + 1;

sys/arch/arm/cortex/gic.c

348

uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ);

sys/arch/arm/cortex/gic.c

353

irq = __SHIFTOUT(iar, GICC_IAR_IRQ);

sys/arch/arm/cortex/gic.c

632

const int iidr_prod = __SHIFTOUT(iidr, GICC_IIDR_ProductID);

sys/arch/arm/cortex/gic.c

633

const int iidr_arch = __SHIFTOUT(iidr, GICC_IIDR_ArchVersion);

sys/arch/arm/cortex/gic.c

634

const int iidr_rev = __SHIFTOUT(iidr, GICC_IIDR_Revision);

sys/arch/arm/cortex/gic.c

635

const int iidr_imp = __SHIFTOUT(iidr, GICC_IIDR_Implementer);

sys/arch/arm/cortex/gic_reg.h

161

#define GICD_TYPER_LINES(n) MIN(32*(__SHIFTOUT((n), GICD_TYPER_ITLinesNumber) + 1), 1020)

sys/arch/arm/cortex/gic_v2m.c

336

const int spi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/cortex/gic_v2m.c

351

const int spi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ);

sys/arch/arm/cortex/gicv3.c

344

aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/cortex/gicv3.c

345

aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1);

sys/arch/arm/cortex/gicv3.c

346

aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2);

sys/arch/arm/cortex/gicv3.c

347

aff3 = __SHIFTOUT(mpidr, MPIDR_AFF3);

sys/arch/arm/cortex/gicv3.c

369

const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);

sys/arch/arm/cortex/gicv3.c

370

const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);

sys/arch/arm/cortex/gicv3.c

371

const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2);

sys/arch/arm/cortex/gicv3.c

372

const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3);

sys/arch/arm/cortex/gicv3.c

383

const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);

sys/arch/arm/cortex/gicv3.c

384

const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);

sys/arch/arm/cortex/gicv3.c

385

const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2);

sys/arch/arm/cortex/gicv3.c

386

const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3);

sys/arch/arm/cortex/gicv3.c

593

sc->sc_processor_id[cpu_index(ci)] = __SHIFTOUT(typer, GICR_TYPER_Processor_Number);

sys/arch/arm/cortex/gicv3.c

608

if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) != GICR_Shareability_IS) {

sys/arch/arm/cortex/gicv3.c

609

if (__SHIFTOUT(propbase, GICR_PROPBASER_Shareability) == GICR_Shareability_NS) {

sys/arch/arm/cortex/gicv3.c

625

if (__SHIFTOUT(pendbase, GICR_PENDBASER_Shareability) == GICR_Shareability_NS) {

sys/arch/arm/cortex/gicv3.c

748

const uint32_t irq = __SHIFTOUT(iar, ICC_IAR_INTID);

sys/arch/arm/cortex/gicv3.c

924

const u_int aff0 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff0);

sys/arch/arm/cortex/gicv3.c

925

const u_int aff1 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff1);

sys/arch/arm/cortex/gicv3.c

926

const u_int aff2 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff2);

sys/arch/arm/cortex/gicv3.c

927

const u_int aff3 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff3);

sys/arch/arm/cortex/gicv3_its.c

1037

if (__SHIFTOUT(baser, GITS_BASER_Shareability) == GITS_Shareability_NS) {

sys/arch/arm/cortex/gicv3_its.c

1047

gits_cache_type[__SHIFTOUT(baser, GITS_BASER_InnerCache)],

sys/arch/arm/cortex/gicv3_its.c

1048

gits_share_type[__SHIFTOUT(baser, GITS_BASER_Shareability)],

sys/arch/arm/cortex/gicv3_its.c

1051

if (__SHIFTOUT(baser, GITS_BASER_Type) == GITS_Type_Devices) {

sys/arch/arm/cortex/gicv3_its.c

1054

__SHIFTOUT(baser, GITS_BASER_Shareability) != GITS_Shareability_NS;

sys/arch/arm/cortex/gicv3_its.c

474

const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1;

sys/arch/arm/cortex/gicv3_its.c

484

__SHIFTOUT(typer, GITS_TYPER_ID_bits));

sys/arch/arm/cortex/gicv3_its.c

660

const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;

sys/arch/arm/cortex/gicv3_its.c

730

const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;

sys/arch/arm/cortex/gicv3_its.c

799

const int lpi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/cortex/gicv3_its.c

800

const uint32_t eventid = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC);

sys/arch/arm/cortex/gicv3_its.c

824

const int lpi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ);

sys/arch/arm/cortex/gicv3_its.c

825

const uint32_t eventid = __SHIFTOUT(pih[n], ARM_PCI_INTR_MSI_VEC);

sys/arch/arm/cortex/gicv3_its.c

870

if (__SHIFTOUT(tmp, GITS_CBASER_Shareability) != GITS_Shareability_IS) {

sys/arch/arm/cortex/gicv3_its.c

871

if (__SHIFTOUT(tmp, GITS_CBASER_InnerCache) == GITS_Shareability_NS) {

sys/arch/arm/cortex/gicv3_its.c

883

gits_cache_type[__SHIFTOUT(cbaser, GITS_BASER_InnerCache)],

sys/arch/arm/cortex/gicv3_its.c

884

gits_share_type[__SHIFTOUT(cbaser, GITS_BASER_Shareability)]);

sys/arch/arm/cortex/gicv3_its.c

898

*devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;

sys/arch/arm/cortex/gicv3_its.c

946

l1_entry_size = __SHIFTOUT(baser, GITS_BASER_Entry_Size) + 1;

sys/arch/arm/cortex/gicv3_its.c

950

switch (__SHIFTOUT(baser, GITS_BASER_Page_Size)) {

sys/arch/arm/cortex/gicv3_its.c

963

switch (__SHIFTOUT(baser, GITS_BASER_Type)) {

sys/arch/arm/cortex/gicv3_its.h

52

CTASSERT(__SHIFTOUT(ARM_PCI_INTR_MSI_VEC, ARM_PCI_INTR_MSI_VEC) >= ITS_MAX_EVENTS - 1);

sys/arch/arm/cortex/pl310.c

166

u_int rev = __SHIFTOUT(id, CACHE_ID_REV);

sys/arch/arm/cortex/pl310.c

282

info->cache_type = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE);

sys/arch/arm/cortex/pl310.c

283

info->cache_unified = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) == 0;

sys/arch/arm/cortex/pl310.c

284

u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE);

sys/arch/arm/cortex/pl310.c

286

u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE);

sys/arch/arm/cortex/pl310.c

287

info->dcache_ways = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC);

sys/arch/arm/cortex/pl310.c

288

info->dcache_line_size = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE);

sys/arch/arm/cortex/pl310.c

298

u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE);

sys/arch/arm/cortex/pl310.c

299

u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE);

sys/arch/arm/cortex/pl310.c

300

info->icache_ways = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC);

sys/arch/arm/cortex/pl310.c

301

info->icache_line_size = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE);

sys/arch/arm/fdt/gic_fdt.c

223

base_spi = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE);

sys/arch/arm/fdt/gic_fdt.c

225

num_spis = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER);

sys/arch/arm/fdt/pcihost_fdt.c

297

const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) ==

sys/arch/arm/fdt/pcihost_fdt.c

299

switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) {

sys/arch/arm/fdt/pcihost_fdt.c

338

__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) {

sys/arch/arm/fdt/pcihost_fdt.c

568

const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);

sys/arch/arm/fdt/pcihost_fdt.c

569

const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC);

sys/arch/arm/fdt/psci_fdt.c

97

const u_int ver_maj = __SHIFTOUT(ver, PSCI_VERSION_MAJOR);

sys/arch/arm/fdt/psci_fdt.c

98

const u_int ver_min = __SHIFTOUT(ver, PSCI_VERSION_MINOR);

sys/arch/arm/imx/if_enet.c

744

hashidx = __SHIFTOUT(crc, __BITS(30,26));

sys/arch/arm/imx/if_enet.c

745

gaddr[__SHIFTOUT(crc, __BIT(31))] |= __BIT(hashidx);

sys/arch/arm/imx/imx23_digfilt.c

227

__SHIFTOUT(v, HW_AUDIOOUT_VERSION_MAJOR),

sys/arch/arm/imx/imx23_digfilt.c

228

__SHIFTOUT(v, HW_AUDIOOUT_VERSION_MINOR),

sys/arch/arm/imx/imx23_digfilt.c

229

__SHIFTOUT(v, HW_AUDIOOUT_VERSION_STEP));

sys/arch/arm/imx/imx23_digfilt.c

486

nvol = __SHIFTOUT(val, HW_AUDIOOUT_DACVOLUME_VOLUME_LEFT);

sys/arch/arm/imx/imx23_digfilt.c

489

nvol = __SHIFTOUT(val, HW_AUDIOOUT_DACVOLUME_VOLUME_RIGHT);

sys/arch/arm/imx/imx23_digfilt.c

497

nvol = __SHIFTOUT(val, HW_AUDIOOUT_HPVOL_VOL_LEFT);

sys/arch/arm/imx/imx23_digfilt.c

500

nvol = __SHIFTOUT(val, HW_AUDIOOUT_HPVOL_VOL_RIGHT);

sys/arch/arm/imx/imx23_icoll.c

163

irq = __SHIFTOUT(ICOLL_READ(icoll_sc, HW_ICOLL_STAT),

sys/arch/arm/imx/imx23_icoll.c

70

__SHIFTOUT(ICOLL_READ(sc, HW_ICOLL_INTERRUPT0 + \

sys/arch/arm/imx/imx23_mmc.c

231

__SHIFTOUT(imx23_mmc_vers, HW_SSP_VERSION_MAJOR),

sys/arch/arm/imx/imx23_mmc.c

232

__SHIFTOUT(imx23_mmc_vers, HW_SSP_VERSION_MINOR));

sys/arch/arm/imx/imx23_usbphy.c

106

__SHIFTOUT(phy_version, HW_USBPHY_VERSION_MAJOR),

sys/arch/arm/imx/imx23_usbphy.c

107

__SHIFTOUT(phy_version, HW_USBPHY_VERSION_MINOR));

sys/arch/arm/imx/imx51_ccm.c

177

switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL)) {

sys/arch/arm/imx/imx51_ccm.c

184

(1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF));

sys/arch/arm/imx/imx51_ccm.c

187

(1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF));

sys/arch/arm/imx/imx51_ccm.c

215

switch (__SHIFTOUT(cbcdr, CBCDR_PERIPH_CLK_SEL)) {

sys/arch/arm/imx/imx51_ccm.c

234

switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL)) {

sys/arch/arm/imx/imx51_ccm.c

255

return freq / (1 + __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF));

sys/arch/arm/imx/imx51_ccm.c

261

return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF));

sys/arch/arm/imx/imx51_ccm.c

265

return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF));

sys/arch/arm/imx/imx51_ccm.c

286

freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1);

sys/arch/arm/imx/imx51_ccm.c

287

freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2);

sys/arch/arm/imx/imx51_ccm.c

288

freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PODF);

sys/arch/arm/imx/imx51_ccm.c

298

sel = __SHIFTOUT(cscmr1, CSCMR1_UART_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

311

return freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PRED)) /

sys/arch/arm/imx/imx51_ccm.c

312

(1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF));

sys/arch/arm/imx/imx51_ccm.c

315

switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL)) {

sys/arch/arm/imx/imx51_ccm.c

338

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

340

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

356

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

358

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

384

freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) /

sys/arch/arm/imx/imx51_ccm.c

385

(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF));

sys/arch/arm/imx/imx51_ccm.c

387

freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PRED)) /

sys/arch/arm/imx/imx51_ccm.c

388

(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PODF));

sys/arch/arm/imx/imx51_ccm.c

397

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

399

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

415

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

417

sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

431

freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) /

sys/arch/arm/imx/imx51_ccm.c

432

(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF));

sys/arch/arm/imx/imx51_ccm.c

434

freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC2_CLK_PRED)) /

sys/arch/arm/imx/imx51_ccm.c

435

(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC2_CLK_PODF));

sys/arch/arm/imx/imx51_ccm.c

442

sel = __SHIFTOUT(cscmr1, CSCMR1_CSPI_CLK_SEL);

sys/arch/arm/imx/imx51_ccm.c

454

freq = freq / (1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PRED)) /

sys/arch/arm/imx/imx51_ccm.c

455

(1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PODF));

sys/arch/arm/imx/imx51_ccm.c

517

mfi = uimax(5, __SHIFTOUT(dp_op, DP_OP_MFI));

sys/arch/arm/imx/imxgpio.c

153

int gtype = __SHIFTOUT(v, mask);

sys/arch/arm/imx/imxgpio.c

234

val = __SHIFTOUT(GPIO_READ(gpio, GPIO_DR), __BIT(pin));

sys/arch/arm/imx/imxpwm.c

94

const int div = __SHIFTOUT(cr, PWM_CR_PRESCALER) + 1;

sys/arch/arm/imx/imxpwm.c

95

const int polarity = __SHIFTOUT(cr, PWM_CR_POUTC);

sys/arch/arm/imx/imxpwm.c

97

const u_int cycles = __SHIFTOUT(pr, PWM_PR_PERIOD) + 2;

sys/arch/arm/imx/imxpwm.c

98

const u_int act_cycles = __SHIFTOUT(sar, PWM_SAR_SAMPLE);

sys/arch/arm/imx/imxsnvs.c

91

__SHIFTOUT(v1, SNVS_HPVIDR1_IP_ID),

sys/arch/arm/imx/imxsnvs.c

92

__SHIFTOUT(v1, SNVS_HPVIDR1_MAJOR_REV),

sys/arch/arm/imx/imxsnvs.c

93

__SHIFTOUT(v1, SNVS_HPVIDR1_MINOR_REV),

sys/arch/arm/imx/imxsnvs.c

94

__SHIFTOUT(v2, SNVS_HPVIDR2_IP_ERA),

sys/arch/arm/imx/imxsnvs.c

95

__SHIFTOUT(v2, SNVS_HPVIDR2_INTG_OPT),

sys/arch/arm/imx/imxsnvs.c

96

__SHIFTOUT(v2, SNVS_HPVIDR2_ECO_REV),

sys/arch/arm/imx/imxsnvs.c

97

__SHIFTOUT(v2, SNVS_HPVIDR2_CONFIG_OPT));

sys/arch/arm/imx/imxusb.c

131

(int)__SHIFTOUT(id, IMXUSB_ID_ID),

sys/arch/arm/imx/imxusb.c

132

(int)__SHIFTOUT(id, IMXUSB_ID_REVISION),

sys/arch/arm/imx/imxusb.c

142

int n_ports = 1 + __SHIFTOUT(hwhost, HWHOST_NPORT);

sys/arch/arm/imx/imxusb.c

149

int n_endpoints = __SHIFTOUT(hwdevice, HWDEVICE_DEVEP);

sys/arch/arm/imx/imxusb.c

314

return __SHIFTOUT(reg, ULPI_DATRD);

sys/arch/arm/imx/imxwdog.c

147

sc->sc_wdog_armed = __SHIFTOUT(wdog_read(sc, IMX_WDOG_WCR), WCR_WDE);

sys/arch/arm/include/armreg.h

692

const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK);

sys/arch/arm/include/db_machdep.h

110

(__SHIFTOUT((ins), INSN_COND_MASK) == INSN_COND_AL \

sys/arch/arm/include/fenv.h

45

#define __FENV_GET_FLAGS(__envp) __SHIFTOUT(*(__envp), VFP_FPSCR_CSUM)

sys/arch/arm/include/fenv.h

46

#define __FENV_GET_MASK(__envp) __SHIFTOUT(*(__envp), VFP_FPSCR_ESUM)

sys/arch/arm/include/fenv.h

47

#define __FENV_GET_ROUND(__envp) __SHIFTOUT(*(__envp), VFP_FPSCR_RMODE)

sys/arch/arm/nvidia/soc_tegra124.c

66

arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);

sys/arch/arm/nvidia/tegra124_car.c

1037

divm = __SHIFTOUT(base, tpll->divm_mask);

sys/arch/arm/nvidia/tegra124_car.c

1038

divn = __SHIFTOUT(base, tpll->divn_mask);

sys/arch/arm/nvidia/tegra124_car.c

1040

divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;

sys/arch/arm/nvidia/tegra124_car.c

1042

divp = __SHIFTOUT(base, tpll->divp_mask);

sys/arch/arm/nvidia/tegra124_car.c

1195

const u_int src = __SHIFTOUT(v, tmux->bits);

sys/arch/arm/nvidia/tegra124_car.c

1247

const u_int raw_div = __SHIFTOUT(v, tdiv->bits);

sys/arch/arm/nvidia/tegra124_car.c

1298

raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits);

sys/arch/arm/nvidia/tegra210_car.c

1159

divm = __SHIFTOUT(base, tpll->divm_mask);

sys/arch/arm/nvidia/tegra210_car.c

1160

divn = __SHIFTOUT(base, tpll->divn_mask);

sys/arch/arm/nvidia/tegra210_car.c

1162

divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;

sys/arch/arm/nvidia/tegra210_car.c

1168

divm *= __SHIFTOUT(base, tpll->divp_mask);

sys/arch/arm/nvidia/tegra210_car.c

1170

divp = __SHIFTOUT(base, tpll->divp_mask);

sys/arch/arm/nvidia/tegra210_car.c

1301

const u_int src = __SHIFTOUT(v, tmux->bits);

sys/arch/arm/nvidia/tegra210_car.c

1343

u_int raw_div = __SHIFTOUT(v, tdiv->bits);

sys/arch/arm/nvidia/tegra210_car.c

1366

switch (__SHIFTOUT(v, CAR_CLKSRC_SDMMC_SRC)) {

sys/arch/arm/nvidia/tegra210_car.c

1402

raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits);

sys/arch/arm/nvidia/tegra210_xusbpad.c

379

const u_int hs_curr_level = __SHIFTOUT(skucalib, FUSE_SKUCALIB_HS_CURR_LEVEL((u_int)index));

sys/arch/arm/nvidia/tegra210_xusbpad.c

380

const u_int hs_term_range_adj = __SHIFTOUT(skucalib, FUSE_SKUCALIB_HS_TERM_RANGE_ADJ);

sys/arch/arm/nvidia/tegra210_xusbpad.c

383

const u_int ext_rpd_ctrl = __SHIFTOUT(usbcalib, FUSE_USBCALIB_EXT_RPD_CTRL);

sys/arch/arm/nvidia/tegra_cec.c

218

__SHIFTOUT(val, CEC_RX_REGISTER_DATA);

sys/arch/arm/nvidia/tegra_cec.c

352

__SHIFTOUT(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS);

sys/arch/arm/nvidia/tegra_ehci.c

161

const u_int cm = __SHIFTOUT(usbmode, TEGRA_EHCI_USBMODE_CM);

sys/arch/arm/nvidia/tegra_ehci.c

195

switch (__SHIFTOUT(val, TEGRA_EHCI_HOSTPC1_DEVLC_PSPD)) {

sys/arch/arm/nvidia/tegra_i2c.c

386

__SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT);

sys/arch/arm/nvidia/tegra_i2c.c

442

__SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT);

sys/arch/arm/nvidia/tegra_pcie.c

332

switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) {

sys/arch/arm/nvidia/tegra_platform.c

119

arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);

sys/arch/arm/nvidia/tegra_soctherm.c

281

sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE);

sys/arch/arm/nvidia/tegra_soctherm.c

282

sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE);

sys/arch/arm/nvidia/tegra_soctherm.c

379

const u_int temp = __SHIFTOUT(status,

sys/arch/arm/nvidia/tegra_soctherm.c

396

const uint32_t v = __SHIFTOUT(val, bitmask);

sys/arch/arm/nvidia/tegra_xusb.c

543

const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA);

sys/arch/arm/nvidia/tegra_xusb.c

544

const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE);

sys/arch/arm/nvidia/tegra_xusb.c

923

const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE);

sys/arch/arm/nvidia/tegra_xusb.c

924

const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET);

sys/arch/arm/nvidia/tegra_xusb.c

936

const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE);

sys/arch/arm/nvidia/tegra_xusb.c

937

const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET);

sys/arch/arm/nvidia/tegra_xusb.c

954

const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE);

sys/arch/arm/nxp/imx6_ccm.c

168

uint32_t div = __SHIFTOUT(v, pll->mask);

sys/arch/arm/nxp/imx6_ccm.c

183

uint32_t div = __SHIFTOUT(v, pll->mask);

sys/arch/arm/nxp/imx6_ccm.c

201

uint32_t div = __SHIFTOUT(v, pll->mask);

sys/arch/arm/nxp/imx6_ccm.c

288

uint32_t n = __SHIFTOUT(v, div->mask);

sys/arch/arm/nxp/imx6_ccm.c

317

uint32_t n = __SHIFTOUT(v, __BITS(5, 0) << (pfd->index * 8));

sys/arch/arm/nxp/imx6_ccm.c

393

u_int sel = __SHIFTOUT(v, mux->mask);

sys/arch/arm/nxp/imx6_ccm.c

548

if (__SHIFTOUT(v, pll->powerdown) != enable)

sys/arch/arm/nxp/imx6_iomux.c

94

if (__SHIFTOUT(input_val, __BITS(31, 24)) == 0xff) {

sys/arch/arm/nxp/imx6_iomux.c

95

uint8_t sel = __SHIFTOUT(input_val, __BITS(7, 0));

sys/arch/arm/nxp/imx6_iomux.c

96

uint8_t width = __SHIFTOUT(input_val, __BITS(15, 8));

sys/arch/arm/nxp/imx6_iomux.c

97

uint8_t shift = __SHIFTOUT(input_val, __BITS(23, 16));

sys/arch/arm/nxp/imx_ccm_composite.c

115

const u_int mux = __SHIFTOUT(val, TARGET_ROOT_MUX);

sys/arch/arm/nxp/imx_ccm_composite.c

173

const u_int mux = __SHIFTOUT(val, TARGET_ROOT_MUX);

sys/arch/arm/nxp/imx_ccm_composite.c

85

const u_int pre_div = __SHIFTOUT(val, TARGET_ROOT_PRE_PODF) + 1;

sys/arch/arm/nxp/imx_ccm_composite.c

86

const u_int post_div = __SHIFTOUT(val, TARGET_ROOT_POST_PODF) + 1;

sys/arch/arm/nxp/imx_ccm_div.c

60

const u_int n = __SHIFTOUT(val, div->mask);

sys/arch/arm/nxp/imx_ccm_mux.c

50

const u_int sel = __SHIFTOUT(val, mux->sel);

sys/arch/arm/nxp/imx_ccm_pll.c

92

const u_int div = __SHIFTOUT(val, pll->div_mask);

sys/arch/arm/nxp/imxpcie.c

233

v = __SHIFTOUT(PCIE_READ(sc, PCIE_PL_PHY_STATUS),

sys/arch/arm/nxp/imxpcie.c

380

uint32_t ltssm = __SHIFTOUT(PCIE_READ(sc, PCIE_PL_DEBUG0),

sys/arch/arm/nxp/imxpcie.c

471

(int)__SHIFTOUT(v, PCIE_RC_LCSR_LINK_SPEED));

sys/arch/arm/nxp/imxwdog.c

192

sc->sc_wdog_armed = __SHIFTOUT(wdog_read(sc, IMX_WDOG_WCR), WCR_WDE);

sys/arch/arm/pci/pci_msi_machdep.c

53

const int id = __SHIFTOUT(ih, ARM_PCI_INTR_FRAME);

sys/arch/arm/pci/pci_smccc.c

116

*bus_start = __SHIFTOUT(res1, GET_SEG_INFO_BUS_START);

sys/arch/arm/pci/pci_smccc.c

117

*bus_end = __SHIFTOUT(res1, GET_SEG_INFO_BUS_END);

sys/arch/arm/rockchip/rk3066_smp.c

148

const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/rockchip/rk3399_cru.c

256

const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);

sys/arch/arm/rockchip/rk3399_cru.c

257

const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2);

sys/arch/arm/rockchip/rk3399_cru.c

258

const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1);

sys/arch/arm/rockchip/rk3399_cru.c

259

const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV);

sys/arch/arm/rockchip/rk3399_cru.c

260

const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV);

sys/arch/arm/rockchip/rk3399_cru.c

261

const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD);

sys/arch/arm/rockchip/rk3399_pcie.c

43

#define GETREG(m, v) (__SHIFTOUT((v), (m)))

sys/arch/arm/rockchip/rk3399_pcie.c

64

#define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20))

sys/arch/arm/rockchip/rk3399_pmucru.c

184

const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);

sys/arch/arm/rockchip/rk3399_pmucru.c

185

const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2);

sys/arch/arm/rockchip/rk3399_pmucru.c

186

const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1);

sys/arch/arm/rockchip/rk3399_pmucru.c

187

const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV);

sys/arch/arm/rockchip/rk3399_pmucru.c

188

const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV);

sys/arch/arm/rockchip/rk3399_pmucru.c

189

const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD);

sys/arch/arm/rockchip/rk_cru_arm.c

207

const u_int mux = __SHIFTOUT(val, arm->mux_mask);

sys/arch/arm/rockchip/rk_cru_arm.c

58

const u_int div = __SHIFTOUT(val, arm->divs[0].mask) + 1;

sys/arch/arm/rockchip/rk_cru_composite.c

228

mux = __SHIFTOUT(val, composite->mux_mask);

sys/arch/arm/rockchip/rk_cru_composite.c

89

div = 1U << __SHIFTOUT(val, composite->div_mask);

sys/arch/arm/rockchip/rk_cru_composite.c

91

div = __SHIFTOUT(val, composite->div_mask) * 2 + 3;

sys/arch/arm/rockchip/rk_cru_composite.c

95

? __SHIFTOUT(val, composite->div_mask) + 1 : 1;

sys/arch/arm/rockchip/rk_cru_mux.c

58

const u_int index = __SHIFTOUT(val, mux->mask);

sys/arch/arm/rockchip/rk_cru_pll.c

115

const u_int nr = __SHIFTOUT(con0, RK3288_CLKR) + 1;

sys/arch/arm/rockchip/rk_cru_pll.c

116

const u_int no = __SHIFTOUT(con0, RK3288_CLKOD) + 1;

sys/arch/arm/rockchip/rk_cru_pll.c

117

const u_int nf = __SHIFTOUT(con1, RK3288_CLKF) + 1;

sys/arch/arm/rockchip/rk_cru_pll.c

123

const uint64_t m = __SHIFTOUT(con0, RK3588_PLLCON0_M);

sys/arch/arm/rockchip/rk_cru_pll.c

124

const uint64_t p = __SHIFTOUT(con1, RK3588_PLLCON1_P);

sys/arch/arm/rockchip/rk_cru_pll.c

125

const uint64_t s = __SHIFTOUT(con1, RK3588_PLLCON1_S);

sys/arch/arm/rockchip/rk_cru_pll.c

126

const uint64_t k = __SHIFTOUT(con2, RK3588_PLLCON2_K);

sys/arch/arm/rockchip/rk_cru_pll.c

136

const u_int postdiv1 = __SHIFTOUT(con0, PLL_POSTDIV1);

sys/arch/arm/rockchip/rk_cru_pll.c

137

const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);

sys/arch/arm/rockchip/rk_cru_pll.c

138

const u_int dsmpd = __SHIFTOUT(con1, PLL_DSMPD);

sys/arch/arm/rockchip/rk_cru_pll.c

139

const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV);

sys/arch/arm/rockchip/rk_cru_pll.c

140

const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2);

sys/arch/arm/rockchip/rk_cru_pll.c

141

const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV);

sys/arch/arm/rockchip/rk_cru_pll.c

185

if (__SHIFTOUT(CRU_READ(sc, pll->mode_reg), pll->mode_mask) ==

sys/arch/arm/rockchip/rk_gpio.c

213

val = __SHIFTOUT(data, data_mask);

sys/arch/arm/rockchip/rk_gpio.c

269

val = __SHIFTOUT(data, data_mask);

sys/arch/arm/rockchip/rk_i2s.c

383

fifolr = __SHIFTOUT(val, RXFIFOLR_RFL(0));

sys/arch/arm/rockchip/rk_i2s.c

397

fifolr = __SHIFTOUT(val, TXFIFOLR_TFL(0));

sys/arch/arm/rockchip/rk_i2s.c

440

const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);

sys/arch/arm/rockchip/rk_i2s.c

441

const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);

sys/arch/arm/rockchip/rk_i2s.c

442

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/arch/arm/rockchip/rk_pwm.c

147

div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2;

sys/arch/arm/rockchip/rk_pwm.c

153

div /= (1 << __SHIFTOUT(ctrl, CTRL_PRESCALE));

sys/arch/arm/rockchip/rk_spi.c

389

avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR);

sys/arch/arm/rockchip/rk_spi.c

396

avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR);

sys/arch/arm/samsung/exynos5410_clock.c

770

const u_int sel = __SHIFTOUT(v, emux->bits);

sys/arch/arm/samsung/exynos5410_clock.c

790

const u_int div = __SHIFTOUT(v, ediv->bits);

sys/arch/arm/samsung/exynos5422_clock.c

817

const u_int sel = __SHIFTOUT(v, emux->bits);

sys/arch/arm/samsung/exynos5422_clock.c

837

const u_int div = __SHIFTOUT(v, ediv->bits);

sys/arch/arm/samsung/exynos_combiner.c

218

const uint32_t istatus = __SHIFTOUT(istr, COMBINER_GROUP_MASK(group_no));

sys/arch/arm/samsung/exynos_gpio.c

275

return __SHIFTOUT(val, __BIT(pin));

sys/arch/arm/samsung/exynos_platform.c

150

const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);

sys/arch/arm/samsung/exynos_platform.c

151

const u_int aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/samsung/exynos_platform.c

173

if (cluster == 1 && __SHIFTOUT(bp_mpidr, MPIDR_AFF1) == 1) {

sys/arch/arm/samsung/exynos_platform.c

296

arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);

sys/arch/arm/samsung/exynos_platform.c

357

if (mpidr != cpu_mpidr_aff_read() && __SHIFTOUT(mpidr, MPIDR_AFF1) == 1)

sys/arch/arm/samsung/exynos_reg.h

137

__SHIFTOUT((v), PLL35XX_CON0_M),\

sys/arch/arm/samsung/exynos_reg.h

138

__SHIFTOUT((v), PLL35XX_CON0_P),\

sys/arch/arm/samsung/exynos_reg.h

139

__SHIFTOUT((v), PLL35XX_CON0_S))

sys/arch/arm/samsung/exynos_reg.h

146

__SHIFTOUT((v0), PLL2650X_CON0_M),\

sys/arch/arm/samsung/exynos_reg.h

147

__SHIFTOUT((v1), PLL2650X_CON1_K),\

sys/arch/arm/samsung/exynos_reg.h

148

__SHIFTOUT((v0), PLL2650X_CON0_P),\

sys/arch/arm/samsung/exynos_reg.h

149

__SHIFTOUT((v0), PLL2650X_CON0_S))

sys/arch/arm/samsung/exynos_uart.c

311

if (__SHIFTOUT(ufstat, sc->sc_conf->rxcount) == 0) {

sys/arch/arm/samsung/exynos_uart.c

615

if (__SHIFTOUT(ufstat, sc->sc_conf->rxcount) == 0) {

sys/arch/arm/samsung/exynos_var.h

47

#define EXYNOS_PRODUCT_FAMILY(soc) __SHIFTOUT((soc), __BITS(24,31))

sys/arch/arm/samsung/exynos_var.h

50

#define EXYNOS_PRODUCT_ID(soc) __SHIFTOUT((soc), __BITS(12,31))

sys/arch/arm/samsung/exynos_var.h

51

#define EXYNOS_PRODUCT_PACKAGE(soc) __SHIFTOUT((soc), __BITS(8,11))

sys/arch/arm/samsung/exynos_var.h

52

#define EXYNOS_PRODUCT_REV(soc) __SHIFTOUT((soc), __BITS(4,7))

sys/arch/arm/samsung/exynos_var.h

53

#define EXYNOS_PRODUCT_SUBREV(soc) __SHIFTOUT((soc), __BITS(0,3))

sys/arch/arm/samsung/exynos_wdt.c

214

__SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER);

sys/arch/arm/samsung/exynos_wdt.c

216

__SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT);

sys/arch/arm/sunxi/sun4i_a10_codec.c

185

nvol = __SHIFTOUT(val, mix->mask) << shift;

sys/arch/arm/sunxi/sun4i_emac.c

568

uint32_t rxlen = __SHIFTOUT(rxhdr, EMAC_RXHDR_LEN);

sys/arch/arm/sunxi/sun4i_emac.c

569

uint32_t rxsts = __SHIFTOUT(rxhdr, EMAC_RXHDR_STS);

sys/arch/arm/sunxi/sun4i_spi.c

209

? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1)))

sys/arch/arm/sunxi/sun4i_spi.c

210

: (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1))

sys/arch/arm/sunxi/sun4i_spi.c

298

rxavail = __SHIFTOUT(fsr, SPI_FIFO_STA_RF_CNT);

sys/arch/arm/sunxi/sun4i_spi.c

299

txavail = 64 - __SHIFTOUT(fsr, SPI_FIFO_STA_TF_CNT);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

180

return __SHIFTOUT(RD4(sc, A64_PR_CFG), A64_ACDA_PR_RDAT);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

387

nvol = __SHIFTOUT(val, mix->mask) << shift;

sys/arch/arm/sunxi/sun6i_a31_codec.c

246

nvol = __SHIFTOUT(val, mix->mask) << shift;

sys/arch/arm/sunxi/sun6i_spi.c

243

? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1)))

sys/arch/arm/sunxi/sun6i_spi.c

244

: (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1))

sys/arch/arm/sunxi/sun6i_spi.c

329

if (__SHIFTOUT(fsr, SPI_FSR_TF_CNT) >= 64) {

sys/arch/arm/sunxi/sun6i_spi.c

354

if (__SHIFTOUT(fsr, SPI_FSR_RF_CNT) == 0) {

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

175

const u_int div = __SHIFTOUT(val, APB0_DIV);

sys/arch/arm/sunxi/sun8i_codec.c

214

const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);

sys/arch/arm/sunxi/sun8i_codec.c

215

const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);

sys/arch/arm/sunxi/sun8i_codec.c

216

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/arch/arm/sunxi/sun8i_crypto.c

1108

*donep = __SHIFTOUT(isr, SUN8I_CRYPTO_ISR_DONE);

sys/arch/arm/sunxi/sun8i_crypto.c

1150

esr_chan = __SHIFTOUT(esr, SUN8I_CRYPTO_ESR_CHAN(i));

sys/arch/arm/sunxi/sun8i_h3_codec.c

169

return __SHIFTOUT(RD4(csc, H3_PR_CFG), H3_ACDA_PR_RDAT);

sys/arch/arm/sunxi/sun8i_h3_codec.c

331

nvol = __SHIFTOUT(val, mix->mask) << shift;

sys/arch/arm/sunxi/sun8i_v3s_codec.c

156

return __SHIFTOUT(RD4(csc, V3S_PR_CFG), V3S_ADDA_PR_RDAT);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

310

nvol = __SHIFTOUT(val, mix->mask) << shift;

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

177

const u_int sel = __SHIFTOUT(val, CPUS_CLK_SRC_SEL);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

178

const u_int post_div = __SHIFTOUT(val, CPUS_POST_DIV);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

179

const u_int clk_ratio = __SHIFTOUT(val, CPUS_CLK_RATIO);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

194

const u_int sel = __SHIFTOUT(val, CPUS_CLK_SRC_SEL);

sys/arch/arm/sunxi/sunxi_ccu_div.c

226

index = __SHIFTOUT(val, div->sel);

sys/arch/arm/sunxi/sunxi_ccu_div.c

83

ratio = __SHIFTOUT(val, div->div);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

133

parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

210

parent_rate = parent_rate / (__SHIFTOUT(val, fractional->prediv) + 1);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

84

rate = rate / (__SHIFTOUT(val, fractional->prediv) + 1);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

93

int sel = __SHIFTOUT(val, fractional->frac_sel);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

96

m = __SHIFTOUT(val, fractional->m);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

79

index = __SHIFTOUT(val, mux->sel);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

103

m = __SHIFTOUT(val, nkmp->m);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

107

p = __SHIFTOUT(val, nkmp->p);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

158

if (nkmp->p && __SHIFTOUT(val, nkmp->p) < tab->p) {

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

164

if (nkmp->m && __SHIFTOUT(val, nkmp->m) < tab->m) {

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

180

if (nkmp->m && __SHIFTOUT(val, nkmp->m) > tab->m) {

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

186

if (nkmp->p && __SHIFTOUT(val, nkmp->p) > tab->p) {

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

95

n = __SHIFTOUT(val, nkmp->n);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

99

k = __SHIFTOUT(val, nkmp->k);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

112

const u_int n_max = __SHIFTOUT(nm->n, nm->n);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

113

const u_int m_max = __SHIFTOUT(nm->m, nm->m);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

229

index = __SHIFTOUT(val, nm->sel);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

82

n = __SHIFTOUT(val, nm->n);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

83

m = __SHIFTOUT(val, nm->m);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

78

delay = __SHIFTOUT(val, phase->mask);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

136

index = __SHIFTOUT(val, prediv->sel);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

61

pre = __SHIFTOUT(val, prediv->prediv);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

65

div = __SHIFTOUT(val, prediv->div);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

68

sel = __SHIFTOUT(val, prediv->sel);

sys/arch/arm/sunxi/sunxi_gmacclk.c

213

sel = __SHIFTOUT(val, GMAC_CLK_PIT);

sys/arch/arm/sunxi/sunxi_gpio.c

393

val = __SHIFTOUT(data, data_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

400

__SHIFTOUT(val, data_mask), val);

sys/arch/arm/sunxi/sunxi_gpio.c

902

val = __SHIFTOUT(data, data_mask);

sys/arch/arm/sunxi/sunxi_hdmi.c

205

const int vmaj = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_H);

sys/arch/arm/sunxi/sunxi_hdmi.c

206

const int vmin = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_L);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

262

sc->sc_rcalib = __SHIFTOUT(val, ANA_STS_RESDO2D);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

343

b_out = __SHIFTOUT(val, ANA_STS_B_OUT);

sys/arch/arm/sunxi/sunxi_i2s.c

698

const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);

sys/arch/arm/sunxi/sunxi_i2s.c

699

const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);

sys/arch/arm/sunxi/sunxi_i2s.c

700

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/arch/arm/sunxi/sunxi_mc_smp.c

208

const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);

sys/arch/arm/sunxi/sunxi_mc_smp.c

209

const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/sunxi/sunxi_mc_smp.c

242

const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);

sys/arch/arm/sunxi/sunxi_mc_smp.c

243

const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0);

sys/arch/arm/sunxi/sunxi_nand.c

162

return __SHIFTOUT(status, NDFC_ST_RB_STATE(chip->chip_rb));

sys/arch/arm/sunxi/sunxi_pwm.c

136

const u_int cycles = __SHIFTOUT(ch_period, PWM_CH0_ENTIRE_CYS) + 1;

sys/arch/arm/sunxi/sunxi_pwm.c

137

const u_int act_cycles = __SHIFTOUT(ch_period, PWM_CH0_ENTIRE_ACT_CYS);

sys/arch/arm/sunxi/sunxi_rsb.c

272

"\n", __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID));

sys/arch/arm/sunxi/sunxi_rtc.c

449

dt->dt_year = __SHIFTOUT(yymmdd, conf->year) + conf->base_year;

sys/arch/arm/sunxi/sunxi_rtc.c

450

dt->dt_mon = __SHIFTOUT(yymmdd, conf->month);

sys/arch/arm/sunxi/sunxi_rtc.c

451

dt->dt_day = __SHIFTOUT(yymmdd, conf->day);

sys/arch/arm/sunxi/sunxi_rtc.c

452

dt->dt_wday = __SHIFTOUT(hhmmss, conf->wk_no);

sys/arch/arm/sunxi/sunxi_rtc.c

453

dt->dt_hour = __SHIFTOUT(hhmmss, conf->hour);

sys/arch/arm/sunxi/sunxi_rtc.c

454

dt->dt_min = __SHIFTOUT(hhmmss, conf->minute);

sys/arch/arm/sunxi/sunxi_rtc.c

455

dt->dt_sec = __SHIFTOUT(hhmmss, conf->second);

sys/arch/arm/sunxi/sunxi_rtc.c

475

maxyear = __SHIFTOUT(0xffffffff, conf->year) + conf->base_year;

sys/arch/arm/sunxi/sunxi_rtc.c

536

__SHIFTOUT(RTC_READ(sc, SUN6I_INTOSC_CLK_PRESCAL_REG),

sys/arch/arm/ti/if_cpsw.c

1202

off = __SHIFTOUT(dw[2], (uint32_t)__BITS(26, 16));

sys/arch/arm/ti/if_cpsw.c

1203

len = __SHIFTOUT(dw[3], (uint32_t)__BITS(10, 0));

sys/arch/arm/ti/omap3_platform.c

275

clksel = __SHIFTOUT(sys_clksel, OMAP4_SYS_CLKSEL_CLKIN);

sys/arch/arm/ti/omap3_platform.c

279

m = __SHIFTOUT(dpll1, OMAP4_DPLL_MULT);

sys/arch/arm/ti/omap3_platform.c

280

n = __SHIFTOUT(dpll1, OMAP4_DPLL_DIV);

sys/arch/arm/ti/omap3_platform.c

281

m2 = __SHIFTOUT(dpll2, OMAP4_DPLL_CLKOUT_DIV);

sys/arch/arm/ti/ti_cpufreq.c

69

rev = __BIT(__SHIFTOUT(syscon_read_4(ti_opp_syscon, AM33XX_REV_OFFSET), AM33XX_REV_MASK));

sys/arch/arm/ti/ti_cpufreq.c

70

efuse = __SHIFTOUT(syscon_read_4(ti_opp_syscon, AM33XX_EFUSE_OFFSET), AM33XX_EFUSE_MASK);

sys/arch/arm/ti/ti_div_clock.c

198

div = __SHIFTOUT(val, mask) + (start_index ? 0 : 1);

sys/arch/arm/ti/ti_dpll_clock.c

259

const u_int mult = __SHIFTOUT(val, DPLL_MULT);

sys/arch/arm/ti/ti_dpll_clock.c

260

const u_int div = __SHIFTOUT(val, DPLL_DIV) + 1;

sys/arch/arm/ti/ti_dpll_clock.c

369

const u_int mult = __SHIFTOUT(val, OMAP3_CORE_DPLL_MULT);

sys/arch/arm/ti/ti_dpll_clock.c

370

const u_int div = __SHIFTOUT(val, OMAP3_CORE_DPLL_DIV) + 1;

sys/arch/arm/ti/ti_dpll_clock.c

371

const u_int postdiv = __SHIFTOUT(val, OMAP3_CORE_DPLL_CLKOUT_DIV);

sys/arch/arm/ti/ti_dpll_clock.c

390

const u_int mult = __SHIFTOUT(val, DPLL_MULT);

sys/arch/arm/ti/ti_dpll_clock.c

391

const u_int div = __SHIFTOUT(val, DPLL_DIV) + 1;

sys/arch/arm/ti/ti_dpll_clock.c

392

const u_int postdiv = __SHIFTOUT(val, DPLL_CLKOUT_DIV);

sys/arch/arm/ti/ti_gpio.c

232

val = __SHIFTOUT(data, data_mask);

sys/arch/arm/ti/ti_gpio.c

404

val = __SHIFTOUT(data, data_mask);

sys/arch/arm/ti/ti_mux_clock.c

191

sel = __SHIFTOUT(val, sc->sc_mask);

sys/arch/arm/vexpress/vexpress_platform.c

185

arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);

sys/arch/arm/vfp/vfp_init.c

279

bool vfp_p = __SHIFTOUT(cpacr, cpacr_vfp2) == CPACR_ALL

sys/arch/arm/vfp/vfp_init.c

280

&& __SHIFTOUT(cpacr, cpacr_vfp) == CPACR_ALL;

sys/arch/arm/xilinx/zynq7000_clkc.c

178

return sc->sc_ps_clk_frequency * __SHIFTOUT(val, PLL_FDIV);

sys/arch/arm/xilinx/zynq7000_clkc.c

192

sel = __SHIFTOUT(val, CLK_CTRL_SRCSEL);

sys/arch/arm/xilinx/zynq7000_clkc.c

204

return prate / __SHIFTOUT(val, CLK_CTRL_DIVISOR);

sys/arch/arm/xilinx/zynq7000_clkc.c

244

return prate / __SHIFTOUT(val, ARM_CLK_CTRL_DIVISOR) / 6;

sys/arch/arm/xilinx/zynq_gpio.c

207

val = __SHIFTOUT(data, DATA_RO_BIT(pin));

sys/arch/arm/xilinx/zynq_uart.c

1507

if (ISSET(__SHIFTOUT(data, ERROR_BITS), ERRBITS)) {

sys/arch/arm/xilinx/zynq_uart.c

1511

if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_ROVR))

sys/arch/arm/xilinx/zynq_uart.c

1513

if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_FRAME)) {

sys/arch/arm/xilinx/zynq_uart.c

1517

if (ISSET(__SHIFTOUT(data, ERROR_BITS), INT_PARE)) {

sys/arch/arm/xilinx/zynq_usb.c

106

(int)__SHIFTOUT(id, ZYNQUSB_ID_ID),

sys/arch/arm/xilinx/zynq_usb.c

107

(int)__SHIFTOUT(id, ZYNQUSB_ID_REVISION),

sys/arch/arm/xilinx/zynq_usb.c

108

(int)__SHIFTOUT(id, ZYNQUSB_ID_VERSION));

sys/arch/arm/xilinx/zynq_usb.c

118

int n_ports = 1 + __SHIFTOUT(hwhost, HWHOST_NPORT);

sys/arch/arm/xilinx/zynq_usb.c

125

int n_endpoints = __SHIFTOUT(hwdevice, HWDEVICE_DEVEP);

sys/arch/arm/xilinx/zynq_usb.c

278

return __SHIFTOUT(data, ULPI_DATRD);

sys/arch/evbmips/rasoc/machdep.c

167

memsize = __SHIFTOUT(memsize, SYSCTL_CFG0_DRAM_SIZE);

sys/arch/evbppc/mpc85xx/cadmusreg.h

44

#define CM_VER_ID_GET(n) __SHIFTOUT((n), CM_VER_ID)

sys/arch/evbppc/mpc85xx/cadmusreg.h

46

#define CM_VER_REV_GET(n) __SHIFTOUT((n), CM_VER_ID)

sys/arch/evbppc/mpc85xx/cadmusreg.h

49

#define CM_CSR_USER_GET(n) __SHIFTOUT((n), CM_CSR_USER)

sys/arch/evbppc/mpc85xx/cadmusreg.h

51

#define CM_CSR_EPHY_GET(n) __SHIFTOUT((n), CM_CSR_EPHY)

sys/arch/evbppc/mpc85xx/pixisreg.h

38

#define PX_VER_ID_GET(n) __SHIFTOUT((n), PX_VER_ID)

sys/arch/evbppc/mpc85xx/pixisreg.h

40

#define PX_VER_REV_GET(n) __SHIFTOUT((n), PX_VER_ID)

sys/arch/evbppc/mpc85xx/pixisreg.h

45

#define PX_CSR_EVES_GET(n) __SHIFTOUT((n), PX_CSR_EVES)

sys/arch/evbppc/mpc85xx/pixisreg.h

63

#define PX_SPD_SYSCLK_GET(n) __SHIFTOUT((n), PX_SPD_SYSCLK)

sys/arch/evbppc/mpc85xx/pixisreg.h

73

#define PX_SPD_DDRCLK_GET(n) __SHIFTOUT((n), PX_SPD_DDRCLK)

sys/arch/evbppc/nintendo/dev/ahb.c

125

(unsigned)__SHIFTOUT(val, HWVER_MASK) + 1,

sys/arch/evbppc/nintendo/dev/ahb.c

126

(unsigned)__SHIFTOUT(val, HWREV_MASK));

sys/arch/evbppc/nintendo/dev/avenc.c

146

*left = __SHIFTOUT(val, AVENC_VOLUME_LEFT);

sys/arch/evbppc/nintendo/dev/avenc.c

147

*right = __SHIFTOUT(val, AVENC_VOLUME_RIGHT);

sys/arch/evbppc/nintendo/dev/avenc.c

198

if (__SHIFTOUT(in16(VI_BASE + VI_DCR), VI_DCR_FMT) == VI_DCR_FMT_PAL) {

sys/arch/evbppc/nintendo/dev/wiifb.c

701

sc->sc_format = __SHIFTOUT(dcr, VI_DCR_FMT);

sys/arch/evbppc/nintendo/machdep.c

250

if (__SHIFTOUT(val, LT_CHIPREVID_MAGIC) == LT_CHIPREVID_MAGIC_CAFE) {

sys/arch/evbppc/stand/wii/miniipc.c

137

while (__SHIFTOUT(in32(HW_IPC_ARMMSG), HW_IPC_ARMMSG_INDEX_OUT_MASK) ==

sys/arch/evbppc/stand/wii/miniipc.c

98

index_in = __SHIFTOUT(in32(HW_IPC_PPCMSG), HW_IPC_PPCMSG_INDEX_IN_MASK);

sys/arch/evbppc/stand/wii/miniipc.c

99

index_out = __SHIFTOUT(in32(HW_IPC_PPCMSG), HW_IPC_PPCMSG_INDEX_OUT_MASK);

sys/arch/hppa/hppa/trap.c

930

__SHIFTOUT(opcode, __PABITS(27, 31));

sys/arch/hppa/hppa/trap.c

936

pl = __SHIFTOUT(opcode, PROBE_PL) & PLMASK;

sys/arch/hppa/hppa/trap.c

939

__SHIFTOUT(opcode, PROBE_PL);

sys/arch/hppa/hppa/trap.c

953

__SHIFTOUT(opcode, PROBE_RW) == 0;

sys/arch/hppa/hppa/trap.c

965

__SHIFTOUT(opcode, __PABITS(27, 31));

sys/arch/i386/pci/elan520.c

409

win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW);

sys/arch/i386/pci/elan520.c

499

__SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID));

sys/arch/i386/pci/elan520.c

505

mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID);

sys/arch/i386/pci/elan520.c

519

tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID);

sys/arch/i386/pci/elan520.c

595

sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ);

sys/arch/i386/pci/elan520.c

596

addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR);

sys/arch/i386/pci/elan520.c

599

sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ);

sys/arch/i386/pci/elan520.c

600

addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR);

sys/arch/i386/pci/elan520.c

603

sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ);

sys/arch/i386/pci/elan520.c

604

addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR);

sys/arch/i386/pci/elan520.c

610

i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR),

sys/arch/m68k/include/mmu_40.h

91

#define LA40_RI(va) __SHIFTOUT((va), LA40_L1_MASK) /* root index */

sys/arch/m68k/include/mmu_40.h

92

#define LA40_PI(va) __SHIFTOUT((va), LA40_L2_MASK) /* pointer index */

sys/arch/m68k/include/mmu_40.h

93

#define LA40_PGI(va) __SHIFTOUT((va), LA40_L3_MASK) /* page index */

sys/arch/m68k/include/pcr.h

44

#define PCR_REVISION(x) __SHIFTOUT((x), PCR_REVMASK)

sys/arch/m68k/include/pcr.h

45

#define PCR_ID(x) __SHIFTOUT((x), PCR_IDMASK)

sys/arch/m68k/include/pmap_68k.h

296

#define LA2L_RI(va) __SHIFTOUT((va), LA2L_L1_MASK) /* root index */

sys/arch/m68k/include/pmap_68k.h

297

#define LA2L_PGI(va) __SHIFTOUT((va), LA2L_L2_MASK) /* page index */

sys/arch/m68k/m68k/mmu_tt.c

138

uint32_t lab = __SHIFTOUT(ttreg, TTR40_LAB);

sys/arch/m68k/m68k/mmu_tt.c

139

uint32_t lam = __SHIFTOUT(ttreg, TTR40_LAM);

sys/arch/m68k/m68k/mmu_tt.c

140

uint32_t pa_lab = __SHIFTOUT(pa, TTR40_LAB);

sys/arch/m68k/m68k/mmu_tt.c

58

uint32_t lab = __SHIFTOUT(ttreg, TT30_LAB);

sys/arch/m68k/m68k/mmu_tt.c

59

uint32_t lam = __SHIFTOUT(ttreg, TT30_LAM);

sys/arch/m68k/m68k/mmu_tt.c

60

uint32_t pa_lab = __SHIFTOUT(pa, TT30_LAB);

sys/arch/m68k/m68k/mmu_tt.c

61

uint32_t fcb = __SHIFTOUT(ttreg, TT30_FCBASE);

sys/arch/m68k/m68k/mmu_tt.c

62

uint32_t fcm = __SHIFTOUT(ttreg, TT30_FCMASK);

sys/arch/macppc/dev/ofw_i2c_machdep.c

82

addr = __SHIFTOUT(reg, OFW_I2C_ADDRESS_MASK);

sys/arch/macppc/dev/ofw_i2c_machdep.c

83

channel = __SHIFTOUT(reg, OFW_I2C_ADDRESS_CHMASK);

sys/arch/mips/adm5120/dev/admgpio.c

116

oe = __SHIFTOUT(admgpio_read(sc), ADM5120_GPIO0_OE);

sys/arch/mips/adm5120/dev/admpci.c

304

bus = __SHIFTOUT(tag, ADMPCI_TAG_BUS_MASK);

sys/arch/mips/adm5120/dev/admpci.c

305

device = __SHIFTOUT(tag, ADMPCI_TAG_DEVICE_MASK);

sys/arch/mips/adm5120/dev/admpci.c

306

function = __SHIFTOUT(tag, ADMPCI_TAG_FUNCTION_MASK);

sys/arch/mips/atheros/ar5312.c

151

predivisor = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_PREDIVIDE);

sys/arch/mips/atheros/ar5312.c

152

multiplier = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_MULTIPLIER);

sys/arch/mips/atheros/ar5312.c

154

predivisor = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_PREDIVIDE);

sys/arch/mips/atheros/ar5312.c

155

multiplier = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_MULTIPLIER);

sys/arch/mips/atheros/ar5312.c

93

bank0 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK0);

sys/arch/mips/atheros/ar5312.c

94

bank1 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK1);

sys/arch/mips/atheros/ar5315.c

101

cw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_COL_WIDTH);

sys/arch/mips/atheros/ar5315.c

103

rw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_ROW_WIDTH);

sys/arch/mips/atheros/ar5315.c

107

dw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_DATA_WIDTH);

sys/arch/mips/atheros/ar7100.c

156

ref_freq * (__SHIFTOUT(pll, AR7100_PLL_PLL_FB) + 1);

sys/arch/mips/atheros/ar7100.c

159

pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_CPU_DIV_SEL) + 1);

sys/arch/mips/atheros/ar7100.c

162

pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_DDR_DIV_SEL) + 1);

sys/arch/mips/atheros/ar7100.c

165

cpu_freq / ((__SHIFTOUT(pll, AR7100_CPU_PLL_AHB_DIV) + 1) * 2);

sys/arch/mips/atheros/ar9344.c

140

out_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_OUTDIV);

sys/arch/mips/atheros/ar9344.c

141

ref_div = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_REFDIV);

sys/arch/mips/atheros/ar9344.c

142

nint = __SHIFTOUT(pll, AR9344_CPU_PLL_CONFIG_NINT);

sys/arch/mips/atheros/ar9344.c

151

out_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_OUTDIV);

sys/arch/mips/atheros/ar9344.c

152

ref_div = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_REFDIV);

sys/arch/mips/atheros/ar9344.c

153

nint = __SHIFTOUT(pll, AR9344_DDR_PLL_CONFIG_NINT);

sys/arch/mips/atheros/ar9344.c

162

post_div = __SHIFTOUT(clk_ctl,

sys/arch/mips/atheros/ar9344.c

170

post_div = __SHIFTOUT(clk_ctl,

sys/arch/mips/atheros/ar9344.c

180

post_div = __SHIFTOUT(clk_ctl,

sys/arch/mips/cavium/dev/if_cnmac.c

1190

if (__SHIFTOUT(word2, PIP_WQE_WORD2_IP_BUFS) != 1)

sys/arch/mips/cavium/dev/if_cnmac.c

1192

__SHIFTOUT(word2, PIP_WQE_WORD2_IP_BUFS));

sys/arch/mips/cavium/dev/if_cnmac.c

1310

port = __SHIFTOUT(work[1], PIP_WQE_WORD1_IPRT);

sys/arch/mips/cavium/dev/octeon_gmx.c

784

switch (__SHIFTOUT(sc->sc_link, RXN_RX_INBND_SPEED)) {

sys/arch/mips/cavium/dev/octeon_gmx.c

837

switch (__SHIFTOUT(sc->sc_link, RXN_RX_INBND_SPEED)) {

sys/arch/mips/cavium/dev/octeon_gmx.c

947

if (__SHIFTOUT(sc->sc_link, RXN_RX_INBND_DUPLEX)) {

sys/arch/mips/cavium/dev/octeon_ipd.c

50

((uintptr_t)(data) + (uintptr_t)__SHIFTOUT(word2, PIP_WQE_WORD2_IP_OFFSET))

sys/arch/mips/cavium/dev/octeon_pip.c

289

pkts = __SHIFTOUT(tmp, PIP_STAT0_PRTN_DRP_PKTS);

sys/arch/mips/cavium/octeon_intr.c

555

KASSERT(__SHIFTOUT(ipi_mask, mbox_mask) < __BIT(NIPIS));

sys/arch/mips/cavium/octeon_intr.c

577

ipi_process(ci, __SHIFTOUT(ipi_mask, mbox_mask));

sys/arch/mips/cavium/octeon_misc.c

242

__SHIFTOUT(mio_rst_boot, MIO_RST_BOOT_PNR_MUL);

sys/arch/mips/cavium/octeon_misc.c

246

__SHIFTOUT(rst_boot, RST_BOOT_PNR_MUL);

sys/arch/mips/mips/mips_machdep.c

1251

if (__SHIFTOUT(cfg4, MIPSNN_CFG4_MMU_EXT_DEF) ==

sys/arch/mips/mips/mips_machdep.c

1254

__SHIFTOUT(cfg4, MIPSNN_CFG4_MMU_SIZE_EXT) <<

sys/arch/mips/mips/pmap_machdep.c

911

asid = __SHIFTOUT(tlbmask.tlb_hi, MIPS3_PG_ASID);

sys/arch/mips/mips/pmap_machdep.c

914

asid = __SHIFTOUT(tlbmask.tlb_hi, MIPS1_TLB_PID);

sys/arch/mips/mips/trap.c

679

if (__SHIFTOUT(cause, MIPS_CR_COP_ERR) == MIPS_CR_COP_ERR_CU1) {

sys/arch/powerpc/booke/dev/e500wdog.c

151

u_int wp = __SHIFTOUT(tcr, TCR_WP) | (__SHIFTOUT(tcr, TCR_WPEXT) << 2);

sys/arch/powerpc/booke/dev/pq3etsec.c

1000

sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL);

sys/arch/powerpc/booke/dev/pq3etsec.c

932

__SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN),

sys/arch/powerpc/booke/dev/pq3etsec.c

933

__SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN),

sys/arch/powerpc/booke/dev/pq3etsec.c

934

__SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX),

sys/arch/powerpc/booke/dev/pq3etsec.c

935

__SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP));

sys/arch/powerpc/booke/dev/pq3etsec.c

950

__SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN),

sys/arch/powerpc/booke/dev/pq3etsec.c

951

__SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN),

sys/arch/powerpc/booke/dev/pq3etsec.c

952

__SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

91

if (__SHIFTOUT(lbc->lbc_br,BR_MSEL) != BR_MSEL_FCM)

sys/arch/powerpc/booke/dev/pq3obio.c

164

[__SHIFTOUT(BR_MSEL_GPCM,BR_MSEL)] = "GPCM",

sys/arch/powerpc/booke/dev/pq3obio.c

165

[__SHIFTOUT(BR_MSEL_FCM,BR_MSEL)] = "FCM",

sys/arch/powerpc/booke/dev/pq3obio.c

166

[__SHIFTOUT(BR_MSEL_SDRAM,BR_MSEL)] = "SDRAM",

sys/arch/powerpc/booke/dev/pq3obio.c

167

[__SHIFTOUT(BR_MSEL_UPMA,BR_MSEL)] = "UPMA",

sys/arch/powerpc/booke/dev/pq3obio.c

168

[__SHIFTOUT(BR_MSEL_UPMB,BR_MSEL)] = "UPMB",

sys/arch/powerpc/booke/dev/pq3obio.c

169

[__SHIFTOUT(BR_MSEL_UPMC,BR_MSEL)] = "UPMC",

sys/arch/powerpc/booke/dev/pq3obio.c

246

1 << (__SHIFTOUT(lbc->lbc_br, BR_PS) + 2),

sys/arch/powerpc/booke/dev/pq3obio.c

247

br_msel_strings[__SHIFTOUT(lbc->lbc_br,BR_MSEL)],

sys/arch/powerpc/fpu/fpu_emu.c

312

exp = __SHIFTOUT(reg, __BITS(62, 52)) - 1023;

sys/arch/powerpc/fpu/fpu_emu.c

322

__SHIFTOUT(reg, __BITS(58, 52) | __BITS(51, 29));

sys/arch/powerpc/fpu/fpu_emu.c

326

frac = __SHIFTOUT(__BIT(52) | reg, __BITS(52, 29 + shift));

sys/arch/powerpc/include/booke/e500reg.h

202

#define PEXIWAR_IWS_GET(n) __SHIFTOUT((n), PEXIWAR_IWS)

sys/arch/powerpc/include/booke/e500reg.h

282

#define L2CTL_L2SIZ_GET(x) (1 << (17 + __SHIFTOUT((x), L2CTL_L2SIZ)))

sys/arch/powerpc/include/booke/e500reg.h

421

#define E500_RATIO2_GET(n) __SHIFTOUT(n, E500_RATIO2)

sys/arch/powerpc/include/booke/e500reg.h

423

#define E500_RATIO_GET(n) __SHIFTOUT(n, E500_RATIO)

sys/arch/powerpc/include/booke/e500reg.h

427

#define PLAT_RATIO_GET(n) __SHIFTOUT(n, PLAT_RATIO)

sys/arch/powerpc/include/booke/e500reg.h

431

#define PORBMSR_HA_GET(n) __SHIFTOUT(m, PORBMSR_HA)

sys/arch/powerpc/mpc5200/cdm.c

137

switch (__SHIFTOUT(cfg, CFG_PCI_CLK_SEL)) {

sys/arch/powerpc/mpc5200/cdm.c

149

ppc_cfg = __SHIFTOUT(porcfg, PORCFG_PPC_PLL_CFG);

sys/arch/powerpc/oea/oea_machdep.c

616

__SHIFTOUT(battable[i].batu, (BAT_XBL|BAT_BL) & ~BAT_BL_8M) + 1;

sys/arch/riscv/fdt/pcihost_fdt.c

279

const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) ==

sys/arch/riscv/fdt/pcihost_fdt.c

281

switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) {

sys/arch/riscv/fdt/pcihost_fdt.c

320

__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) {

sys/arch/riscv/fdt/pcihost_fdt.c

549

const int irq = __SHIFTOUT(ih, RISCV_PCI_INTR_IRQ);

sys/arch/riscv/fdt/pcihost_fdt.c

550

const int vec = __SHIFTOUT(ih, RISCV_PCI_INTR_MSI_VEC);

sys/arch/riscv/include/mutex.h

77

return (ipl_cookie_t){._spl = __SHIFTOUT(__mtx->mtx_owner, MTX_IPL)};

sys/arch/riscv/include/pmap.h

243

const register_t ret = __SHIFTOUT(csr_satp_read(), SATP_ASID);

sys/arch/riscv/include/pte.h

120

#define PTE_TO_PA(pte) (__SHIFTOUT((pte), PTE_PPN) << PGSHIFT)

sys/arch/riscv/include/sysreg.h

330

return __SHIFTOUT(satp, SATP_ASID);

sys/arch/riscv/riscv/kobj_machdep.c

342

const uint32_t immA = __SHIFTOUT(addend, __BIT(12));

sys/arch/riscv/riscv/kobj_machdep.c

343

const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 5));

sys/arch/riscv/riscv/kobj_machdep.c

344

const uint32_t immC = __SHIFTOUT(addend, __BITS( 4, 1));

sys/arch/riscv/riscv/kobj_machdep.c

345

const uint32_t immD = __SHIFTOUT(addend, __BIT(11));

sys/arch/riscv/riscv/kobj_machdep.c

364

const uint32_t immA = __SHIFTOUT(addend, __BIT(20));

sys/arch/riscv/riscv/kobj_machdep.c

365

const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 1));

sys/arch/riscv/riscv/kobj_machdep.c

366

const uint32_t immC = __SHIFTOUT(addend, __BIT(11));

sys/arch/riscv/riscv/kobj_machdep.c

367

const uint32_t immD = __SHIFTOUT(addend, __BITS(19, 12));

sys/arch/riscv/riscv/kobj_machdep.c

407

const uint32_t immA = __SHIFTOUT(addend, __BITS(11, 5));

sys/arch/riscv/riscv/kobj_machdep.c

408

const uint32_t immB = __SHIFTOUT(addend, __BITS( 4, 0));

sys/arch/riscv/riscv/kobj_machdep.c

440

const uint32_t immA = __SHIFTOUT(addend, __BIT(20));

sys/arch/riscv/riscv/kobj_machdep.c

441

const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 1));

sys/arch/riscv/riscv/kobj_machdep.c

442

const uint32_t immC = __SHIFTOUT(addend, __BIT(11));

sys/arch/riscv/riscv/kobj_machdep.c

443

const uint32_t immD = __SHIFTOUT(addend, __BITS(19, 12));

sys/arch/riscv/riscv/kobj_machdep.c

473

const uint16_t immA = __SHIFTOUT(addend, __BIT(8));

sys/arch/riscv/riscv/kobj_machdep.c

474

const uint16_t immB = __SHIFTOUT(addend, __BITS(4, 3));

sys/arch/riscv/riscv/kobj_machdep.c

475

const uint16_t immC = __SHIFTOUT(addend, __BITS(7, 6));

sys/arch/riscv/riscv/kobj_machdep.c

476

const uint16_t immD = __SHIFTOUT(addend, __BITS(2, 1));

sys/arch/riscv/riscv/kobj_machdep.c

477

const uint16_t immE = __SHIFTOUT(addend, __BIT(5));

sys/arch/riscv/riscv/kobj_machdep.c

497

const uint16_t immA = __SHIFTOUT(addend, __BIT(11));

sys/arch/riscv/riscv/kobj_machdep.c

498

const uint16_t immB = __SHIFTOUT(addend, __BIT(4));

sys/arch/riscv/riscv/kobj_machdep.c

499

const uint16_t immC = __SHIFTOUT(addend, __BITS(9, 8));

sys/arch/riscv/riscv/kobj_machdep.c

500

const uint16_t immD = __SHIFTOUT(addend, __BIT(10));

sys/arch/riscv/riscv/kobj_machdep.c

501

const uint16_t immE = __SHIFTOUT(addend, __BIT(6));

sys/arch/riscv/riscv/kobj_machdep.c

502

const uint16_t immF = __SHIFTOUT(addend, __BIT(7));

sys/arch/riscv/riscv/kobj_machdep.c

503

const uint16_t immG = __SHIFTOUT(addend, __BITS(3, 1));

sys/arch/riscv/riscv/kobj_machdep.c

504

const uint16_t immH = __SHIFTOUT(addend, __BIT(5));

sys/arch/riscv/riscv/kobj_machdep.c

527

const uint16_t immA = __SHIFTOUT(addend, __BIT(17));

sys/arch/riscv/riscv/kobj_machdep.c

528

const uint16_t immB = __SHIFTOUT(addend, __BITS(16,12));

sys/arch/riscv/riscv/mainbus.c

70

return __SHIFTOUT(csr_satp_read(), SATP_MODE);

sys/arch/riscv/riscv/riscv_machdep.c

1016

const paddr_t satp_pa = __SHIFTOUT(satp, SATP_PPN) << PGSHIFT;

sys/arch/riscv/riscv/riscv_machdep.c

1017

const uint8_t mode = __SHIFTOUT(satp, SATP_MODE);

sys/arch/riscv/riscv/riscv_machdep.c

177

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0);

sys/arch/riscv/riscv/riscv_machdep.c

178

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SPP) == 0);

sys/arch/riscv/riscv/riscv_machdep.c

179

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SPIE) != 0);

sys/arch/riscv/riscv/riscv_machdep.c

200

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0);

sys/arch/riscv/riscv/riscv_machdep.c

201

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SPP) == 0);

sys/arch/riscv/riscv/riscv_machdep.c

202

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SPIE) != 0);

sys/arch/riscv/riscv/riscv_machdep.c

985

paddr_t pa = __SHIFTOUT(entry, PTE_PPN) << PGSHIFT;

sys/arch/riscv/riscv/trap.c

533

if (__SHIFTOUT(tf->tf_sr, SR_FS) == SR_FS_OFF) {

sys/arch/riscv/riscv/trap.c

587

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0);

sys/arch/riscv/riscv/trap.c

634

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0);

sys/arch/riscv/riscv/trap.c

635

KASSERT(__SHIFTOUT(tf->tf_sr, SR_SPIE) != 0 ||

sys/arch/riscv/riscv/trap.c

636

__SHIFTOUT(tf->tf_sr, SR_SPP) != 0);

sys/arch/riscv/sifive/fu540_ccache.c

208

__SHIFTOUT(l2config, CCACHE_CONFIG_BANKS_MASK));

sys/arch/riscv/sifive/fu540_ccache.c

210

__SHIFTOUT(l2config, CCACHE_CONFIG_WAYS_MASK));

sys/arch/riscv/sifive/fu540_ccache.c

212

1UL << __SHIFTOUT(l2config, CCACHE_CONFIG_LGSETS_MASK));

sys/arch/riscv/sifive/fu540_ccache.c

214

1UL << __SHIFTOUT(l2config, CCACHE_CONFIG_LGBLOCKBYTES_MASK));

sys/arch/riscv/sifive/fu540_prci.c

121

divr = __SHIFTOUT(val, PLL0_DIVR) + 1;

sys/arch/riscv/sifive/fu540_prci.c

122

divf = __SHIFTOUT(val, PLL0_DIVF) + 1;

sys/arch/riscv/sifive/fu540_prci.c

123

divq = __SHIFTOUT(val, PLL0_DIVQ);

sys/arch/riscv/starfive/jh7100_pinctrl.c

287

pin_no = __SHIFTOUT(p, DT_GPIOMUX_GPIO_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

288

u_int dout = __SHIFTOUT(p, DT_GPIOMUX_DOUT_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

289

u_int doen = __SHIFTOUT(p, DT_GPIOMUX_DOEN_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

290

u_int din = __SHIFTOUT(p, DT_GPIOMUX_DIN_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

291

u_int doutrev = __SHIFTOUT(p, DT_GPIOMUX_DOUTREV_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

292

u_int doenrev = __SHIFTOUT(p, DT_GPIOMUX_DOENREV_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

396

int val = __SHIFTOUT(bank, mask);

sys/arch/riscv/starfive/jh7110_pcie.c

207

*busp = __SHIFTOUT(tag, ECAM_BUS_MASK);

sys/arch/riscv/starfive/jh7110_pcie.c

209

*devp = __SHIFTOUT(tag, ECAM_DEV_MASK);

sys/arch/riscv/starfive/jh7110_pcie.c

211

*fnp = __SHIFTOUT(tag, ECAM_FUNC_MASK);

sys/arch/riscv/starfive/jh7110_pinctrl.c

568

u_int din = __SHIFTOUT(p, DT_PINMUX_DIN_MASK);

sys/arch/riscv/starfive/jh7110_pinctrl.c

569

u_int dout = __SHIFTOUT(p, DT_PINMUX_DOUT_MASK);

sys/arch/riscv/starfive/jh7110_pinctrl.c

570

u_int doen = __SHIFTOUT(p, DT_PINMUX_DOEN_MASK);

sys/arch/riscv/starfive/jh7110_pinctrl.c

571

u_int func = __SHIFTOUT(p, DT_PINMUX_FUNC_MASK);

sys/arch/riscv/starfive/jh7110_pinctrl.c

572

pin_no = __SHIFTOUT(p, DT_PINMUX_PIN_MASK);

sys/arch/riscv/starfive/jh7110_pinctrl.c

649

int val = __SHIFTOUT(bank, mask);

sys/arch/riscv/starfive/jh71x0_clkc.c

174

size_t pindex = __SHIFTOUT(val, JH71X0_CLK_MUX_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

232

uint32_t div = __SHIFTOUT(val, JH71X0_CLK_DIV_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

303

100UL * __SHIFTOUT(val, JH71X0_CLK_INT_MASK) +

sys/arch/riscv/starfive/jh71x0_clkc.c

304

__SHIFTOUT(val, JH71X0_CLK_FRAC_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

394

size_t pindex = __SHIFTOUT(val, JH71X0_CLK_MUX_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

421

uint32_t div = __SHIFTOUT(val, JH71X0_CLK_DIV_MASK);

sys/arch/riscv/starfive/jh71x0_temp.c

73

uint32_t dout = __SHIFTOUT(temp, JH71X0_TEMP_DOUT_MASK);

sys/arch/shark/ofw/vlpci.c

145

size = 0x00010000 << __SHIFTOUT(attr, VLPCI_PCI_WND_ATTR_SZ);

sys/arch/x86/acpi/acpi_cpu_md.c

797

fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID);

sys/arch/x86/acpi/acpi_cpu_md.c

798

vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID);

sys/arch/x86/acpi/acpi_cpu_md.c

823

fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID);

sys/arch/x86/acpi/acpi_cpu_md.c

824

vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID);

sys/arch/x86/acpi/acpi_cpu_md.c

825

irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT);

sys/arch/x86/acpi/acpi_cpu_md.c

826

vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST);

sys/arch/x86/acpi/acpi_cpu_md.c

827

pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL);

sys/arch/x86/acpi/acpi_cpu_md.c

838

val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS);

sys/arch/x86/acpi/acpi_cpu_md.c

848

i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO);

sys/arch/x86/acpi/acpi_cpu_md.c

916

} while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0);

sys/arch/x86/acpi/acpi_cpu_md.c

922

*cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID);

sys/arch/x86/acpi/acpi_cpu_md.c

925

*cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID);

sys/arch/x86/include/i82093var.h

95

#define MSI_INT_DEV(x) __SHIFTOUT((x), MSI_INT_DEV_MASK)

sys/arch/x86/include/i82093var.h

96

#define MSI_INT_VEC(x) __SHIFTOUT((x), MSI_INT_VEC_MASK)

sys/arch/x86/pci/amdtemp.c

507

value = __SHIFTOUT(status, F10_TEMP_CURTMP);

sys/arch/x86/pci/amdzentemp.c

304

temp = __SHIFTOUT(val, F10_TEMP_CURTMP);

sys/arch/x86/pci/amdzentemp.c

317

if (__SHIFTOUT(val, F15M60_CURTMP_TJSEL) == 0x3)

sys/arch/x86/pci/amdzentemp.c

341

temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);

sys/arch/x86/pci/ichlpcib.c

992

return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW);

sys/arch/x86/pci/pci_ranges.c

230

baser = __SHIFTOUT(io, PCI_BRIDGE_STATIO_IOBASE) >> 4;

sys/arch/x86/pci/pci_ranges.c

231

limitr = __SHIFTOUT(io, PCI_BRIDGE_STATIO_IOLIMIT) >> 4;

sys/arch/x86/pci/pci_ranges.c

240

baseh = __SHIFTOUT(iohigh, PCI_BRIDGE_IOHIGH_BASE);

sys/arch/x86/pci/pci_ranges.c

241

limith = __SHIFTOUT(iohigh, PCI_BRIDGE_IOHIGH_LIMIT);

sys/arch/x86/x86/coretemp.c

172

msr = __SHIFTOUT(msr, MSR_THERM_STATUS_RESOLUTION);

sys/arch/x86/x86/coretemp.c

325

tjmax = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);

sys/arch/x86/x86/coretemp.c

375

edata->value_cur -= __SHIFTOUT(msr, MSR_THERM_STATUS_READOUT);

sys/arch/x86/x86/cpu_rng.c

231

nbytes = __SHIFTOUT(status, VIA_RNG_STATUS_NBYTES);

sys/arch/x86/x86/cpu_topology.c

117

lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);

sys/arch/x86/x86/cpu_topology.c

128

core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG)

sys/arch/x86/x86/cpu_topology.c

148

core_max = __SHIFTOUT(descs[2], CPUID_CAPEX_NC) + 1;

sys/arch/x86/x86/cpu_topology.c

150

n = __SHIFTOUT(descs[2], CPUID_CAPEX_ApicIdSize);

sys/arch/x86/x86/cpu_topology.c

191

const u_int threads = __SHIFTOUT(descs[1],

sys/arch/x86/x86/cpu_topology.c

208

core_id = __SHIFTOUT(apic_id, core_mask);

sys/arch/x86/x86/cpu_topology.c

212

smt_id = __SHIFTOUT(apic_id, smt_mask);

sys/arch/x86/x86/identcpu.c

941

= __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3;

sys/arch/x86/x86/identcpu.c

942

ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID);

sys/arch/x86/x86/identcpu_subr.c

225

type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);

sys/arch/x86/x86/identcpu_subr.c

228

level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);

sys/arch/x86/x86/identcpu_subr.c

257

ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;

sys/arch/x86/x86/identcpu_subr.c

258

partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)

sys/arch/x86/x86/identcpu_subr.c

260

linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)

sys/crypto/aes/arch/arm/aes_armv8.c

300

switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_AES)) {

sys/crypto/aes/arch/arm/aes_neon_impl.c

202

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {

sys/crypto/chacha/arch/arm/chacha_neon_impl.c

149

switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {

sys/dev/acpi/acpi_cpu.h

310

return (uint32_t)__SHIFTOUT(val.u64, reg_mask);

sys/dev/acpi/acpi_pcc.c

319

*val = __SHIFTOUT(tmp, mask);

sys/dev/acpi/apei.c

1118

nentries = __SHIFTOUT(status, ACPI_HEST_ERROR_ENTRY_COUNT);

sys/dev/acpi/apei.c

633

dsr = __SHIFTOUT(dcsr, __BITS(31,16));

sys/dev/acpi/apei.c

727

unsigned first = __SHIFTOUT(control,

sys/dev/acpi/qcomipcc.c

160

client_id = __SHIFTOUT(reg, IPCC_CLIENT_ID_MASK);

sys/dev/acpi/qcomipcc.c

161

signal_id = __SHIFTOUT(reg, IPCC_SIGNAL_ID_MASK);

sys/dev/fdt/dwc3_fdt.c

320

const u_int rev = __SHIFTOUT(snpsid, DWC3_SNPSID_REV);

sys/dev/gpio/gpiobutton.c

109

const u_int type = __SHIFTOUT(ga->ga_flags, GPIOBUTTON_TYPE_MASK);

sys/dev/gpio/gpiobutton.c

110

const u_int pol = __SHIFTOUT(ga->ga_flags, GPIOBUTTON_POLARITY_MASK);

sys/dev/gpio/gpiobutton.c

90

const u_int type = __SHIFTOUT(ga->ga_flags, GPIOBUTTON_TYPE_MASK);

sys/dev/i2c/act8846.c

279

*pvol = act8846_vset[__SHIFTOUT(val, ACT_VSET_VSET)];

sys/dev/i2c/axp20x.c

648

*pmvolt = __SHIFTOUT(reg, AXP_DCDC2_VOLT_MASK) * 25 + 700;

sys/dev/i2c/axp20x.c

654

*pmvolt = __SHIFTOUT(reg, AXP_DCDC3_VOLT_MASK) * 25 + 700;

sys/dev/i2c/axp809.c

264

reg_val = __SHIFTOUT(val, c->c_voltage_mask);

sys/dev/i2c/axppmic.c

1052

sc->sc_warn_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV1) + 5;

sys/dev/i2c/axppmic.c

1053

sc->sc_shut_thres = __SHIFTOUT(val, AXP_BATT_CAP_WARN_LV2);

sys/dev/i2c/axppmic.c

652

reg_val = __SHIFTOUT(val, c->c_voltage_mask);

sys/dev/i2c/axppmic.c

781

val = __SHIFTOUT(data, data_mask);

sys/dev/i2c/axppmic.c

868

const u_int batt_val = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT);

sys/dev/i2c/axppmic.c

886

e->value_cur = __SHIFTOUT(val, AXP_BATT_CAP_PERCENT);

sys/dev/i2c/cwfg.c

154

tmp = __SHIFTOUT(val, VCELL_HI) << 8;

sys/dev/i2c/cwfg.c

157

tmp |= __SHIFTOUT(val, VCELL_LO);

sys/dev/i2c/cwfg.c

179

rtt = __SHIFTOUT(val, RTT_HI) << 8;

sys/dev/i2c/cwfg.c

182

rtt |= __SHIFTOUT(val, RTT_LO);

sys/dev/i2c/cwfg.c

255

alert_level = __SHIFTOUT(config, CONFIG_ATHD);

sys/dev/i2c/cwfg.c

327

if (__SHIFTOUT(mode, MODE_SLEEP) == MODE_SLEEP_SLEEP) {

sys/dev/i2c/es8316ac.c

413

nvol = __SHIFTOUT(val, mix->mask[ch]);

sys/dev/i2c/es8316ac.c

508

const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);

sys/dev/i2c/es8316ac.c

509

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/dev/i2c/es8316ac.c

510

const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);

sys/dev/i2c/fan53555.c

175

cur_uvol = __SHIFTOUT(oval, VSEL_NSEL) * sc->sc_step + sc->sc_base;

sys/dev/i2c/fan53555.c

201

*puvol = __SHIFTOUT(val, VSEL_NSEL) * sc->sc_step + sc->sc_base;

sys/dev/i2c/fan53555.c

224

const u_int die_id = __SHIFTOUT(id1, ID1_DIE_ID);

sys/dev/i2c/max77620.c

213

val = __SHIFTOUT(gpio, MAX_GPIO_INPUT_VAL);

sys/dev/i2c/max77620.c

220

(int)__SHIFTOUT(gpio, MAX_GPIO_INPUT_VAL), val);

sys/dev/i2c/rkpmic.c

611

*puvol = __SHIFTOUT(val, c->vsel_mask) * c->step + c->base;

sys/dev/i2c/sdtemp.c

300

= __SHIFTOUT(sc->sc_capability, SDTEMP_CAP_RESOLUTION);

sys/dev/i2c/sy8106a.c

144

cur_uvol = __SHIFTOUT(oval, SEL_VOLTAGE) * SEL_VOLTAGE_STEP +

sys/dev/i2c/sy8106a.c

170

*puvol = __SHIFTOUT(val, SEL_VOLTAGE) * SEL_VOLTAGE_STEP +

sys/dev/i2c/tcagpio.c

195

val = __SHIFTOUT(gpio, PORT_BIT(gpin->pin_num));

sys/dev/i2c/tcagpio.c

202

(int)__SHIFTOUT(gpio, PORT_BIT(gpin->pin_num)), val);

sys/dev/i2c/tcakp.c

171

const bool pressed = __SHIFTOUT(ev, TCA_EVENT_STATE);

sys/dev/i2c/tcakp.c

172

const uint8_t code = __SHIFTOUT(ev, TCA_EVENT_CODE);

sys/dev/i2c/tcakp.c

324

const bool pressed = __SHIFTOUT(ev, TCA_EVENT_STATE);

sys/dev/i2c/tcakp.c

325

const uint8_t code = __SHIFTOUT(ev, TCA_EVENT_CODE);

sys/dev/i2c/twl4030.c

303

val = __SHIFTOUT(gpio, PIN_BIT(gpin->pin_num));

sys/dev/ic/ahcisata_core.c

965

if ((__SHIFTOUT(sig, AHCI_P_TFD_ST) & WDCS_BSY) == 0)

sys/dev/ic/ahcisatareg.h

146

#define AHCI_VS_MJR(v) ((unsigned int)__SHIFTOUT(v, __BITS(31, 16)))

sys/dev/ic/ahcisatareg.h

147

#define AHCI_VS_MNR(v) ((unsigned int)__SHIFTOUT(v, __BITS(15, 8)) * 10 + (unsigned int)__SHIFTOUT(v, __BITS(7, 0) * 1))

sys/dev/ic/anx_dp.c

166

#define AUX_STATUS(x) __SHIFTOUT((x), __BITS(3,0))

sys/dev/ic/anx_dp.c

179

#define AUX_TX_COMM(x) __SHIFTOUT(x, __BITS(3,0))

sys/dev/ic/atw.c

1862

*val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK);

sys/dev/ic/atw.c

1952

*val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL),

sys/dev/ic/atw.c

2464

__SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU,

sys/dev/ic/atw.c

2765

if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) ==

sys/dev/ic/atw.c

2766

__SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) {

sys/dev/ic/atw.c

3029

atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]);

sys/dev/ic/atw.c

3038

atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)]));

sys/dev/ic/atw.c

3113

rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK);

sys/dev/ic/atw.c

3172

len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK);

sys/dev/ic/atw.c

3348

__SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK));

sys/dev/ic/atw.c

3369

__SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK));

sys/dev/ic/atw.c

373

__SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK));

sys/dev/ic/atw.c

620

sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],

sys/dev/ic/atw.c

623

sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],

sys/dev/ic/atw.c

691

srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION],

sys/dev/ic/atw.c

698

__SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03],

sys/dev/ic/atw.c

703

sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],

sys/dev/ic/atw.c

706

country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],

sys/dev/ic/atw.c

745

ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK);

sys/dev/ic/atw.c

746

ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK);

sys/dev/ic/atw.c

747

ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK);

sys/dev/ic/atw.c

748

ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK);

sys/dev/ic/atw.c

750

ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK);

sys/dev/ic/atw.c

751

ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK);

sys/dev/ic/bcmgenet.c

1058

min = __SHIFTOUT(rev, SYS_REV_MINOR);

sys/dev/ic/bcmgenet.c

1059

maj = __SHIFTOUT(rev, SYS_REV_MAJOR);

sys/dev/ic/bcmgenet.c

736

len = __SHIFTOUT(status, GENET_RX_DESC_STATUS_BUFLEN);

sys/dev/ic/bwi.c

10027

tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS_0_TXID_MASK);

sys/dev/ic/bwi.c

10028

tx_cnt = __SHIFTOUT(tx_status0, BWI_TXSTATUS_0_DATA_TXCNT_MASK);

sys/dev/ic/bwi.c

10136

busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);

sys/dev/ic/bwi.c

1016

sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),

sys/dev/ic/bwi.c

2240

ofs = __SHIFTOUT(iv_ofs, BWI_FW_IV_OFS_MASK);

sys/dev/ic/bwi.c

2644

if (__SHIFTOUT(val, BWI_STATE_HI_FLAGS_MASK) &

sys/dev/ic/bwi.c

3069

phyrev = __SHIFTOUT(val, BWI_PHYINFO_REV_MASK);

sys/dev/ic/bwi.c

3070

phytype = __SHIFTOUT(val, BWI_PHYINFO_TYPE_MASK);

sys/dev/ic/bwi.c

3071

phyver = __SHIFTOUT(val, BWI_PHYINFO_VER_MASK);

sys/dev/ic/bwi.c

3929

val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);

sys/dev/ic/bwi.c

4022

manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);

sys/dev/ic/bwi.c

4023

type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);

sys/dev/ic/bwi.c

4024

rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);

sys/dev/ic/bwi.c

4782

idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);

sys/dev/ic/bwi.c

4862

rf->rf_txpower_max = __SHIFTOUT(val,

sys/dev/ic/bwi.c

4865

rf->rf_txpower_max = __SHIFTOUT(val,

sys/dev/ic/bwi.c

4887

ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);

sys/dev/ic/bwi.c

4889

ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);

sys/dev/ic/bwi.c

4986

rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);

sys/dev/ic/bwi.c

6143

tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);

sys/dev/ic/bwi.c

6144

tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);

sys/dev/ic/bwi.c

6217

lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),

sys/dev/ic/bwi.c

6472

addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);

sys/dev/ic/bwi.c

6473

addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);

sys/dev/ic/bwi.c

6623

__SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));

sys/dev/ic/bwi.c

6643

val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);

sys/dev/ic/bwi.c

6644

val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);

sys/dev/ic/bwi.c

6647

val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);

sys/dev/ic/bwi.c

6648

val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);

sys/dev/ic/bwi.c

6658

led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);

sys/dev/ic/bwi.c

6870

bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);

sys/dev/ic/bwi.c

6901

nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);

sys/dev/ic/bwi.c

6918

sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);

sys/dev/ic/bwi.c

6919

sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);

sys/dev/ic/bwi.c

7151

src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);

sys/dev/ic/bwi.c

7155

div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;

sys/dev/ic/bwi.c

7165

div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;

sys/dev/ic/bwi.c

7211

clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);

sys/dev/ic/bwi.c

8564

addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);

sys/dev/ic/bwi.c

8565

addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);

sys/dev/ic/bwi.c

8585

addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);

sys/dev/ic/bwi.c

8586

addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);

sys/dev/ic/bwi.c

9150

end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /

sys/dev/ic/bwi.c

9180

if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==

sys/dev/ic/bwi.c

9250

state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);

sys/dev/ic/bwi.c

9265

state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);

sys/dev/ic/bwi.c

9407

plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);

sys/dev/ic/bwi.c

9911

end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /

sys/dev/ic/bwi.c

9945

ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);

sys/dev/ic/bwi.c

9946

buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);

sys/dev/ic/com.c

699

sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16;

sys/dev/ic/dwc_eqos.c

1502

machi = __SHIFTOUT(RD4(sc, GMAC_MAC_ADDRESS0_HIGH),

sys/dev/ic/dwc_eqos.c

791

tqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1],

sys/dev/ic/dwc_eqos.c

798

rqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1],

sys/dev/ic/dwc_gmac.c

1537

return __SHIFTOUT(le32toh(desc->ddesc_status0), DDESC_STATUS_FRMLENMSK);

sys/dev/ic/dwc_gmac.c

1592

return __SHIFTOUT(le32toh(desc->ddesc_status0), DDESC_RDES0_FL);

sys/dev/ic/dwc_gmac.c

227

__SHIFTOUT(ver, AWIN_GMAC_MAC_VERSION_SNPSVER_MASK);

sys/dev/ic/dwc_mmc.c

838

sc->sc_verid = __SHIFTOUT(val, DWC_MMC_VERID_ID);

sys/dev/ic/dwc_mmc.c

859

sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1;

sys/dev/ic/pl181.c

166

__SHIFTOUT(MMCI_READ(sc, MMCI_FIFO_CNT_REG), MMCI_FIFO_CNT) * 4;

sys/dev/ic/rng200.c

89

count = __SHIFTOUT(w, RNG200_COUNT_MASK);

sys/dev/ic/rtw.c

1128

(*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7));

sys/dev/ic/rtw.c

1129

(*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15));

sys/dev/ic/rtw.c

1130

(*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23));

sys/dev/ic/rtw.c

1131

(*addr)[3] = __SHIFTOUT(idr0, __BITS(24, 31));

sys/dev/ic/rtw.c

1133

(*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7));

sys/dev/ic/rtw.c

1134

(*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15));

sys/dev/ic/rtw.c

1530

len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK);

sys/dev/ic/rtw.c

1544

hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK);

sys/dev/ic/rtw.c

1548

__SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK));

sys/dev/ic/rtw.c

1587

sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ);

sys/dev/ic/rtw.c

1592

rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI);

sys/dev/ic/rtw.c

1722

rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK);

sys/dev/ic/rtw.c

1723

data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK);

sys/dev/ic/rtw.c

211

__SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK));

sys/dev/ic/rtw.c

868

*rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),

sys/dev/ic/rtwphyio.c

103

if (__SHIFTOUT(RTW_READ(regs, RTW_BB),

sys/dev/ic/rtwphyio.c

307

lodata = __SHIFTOUT(val, RTW_MAXIM_LODATA_MASK);

sys/dev/ic/rtwphyio.c

308

hidata = __SHIFTOUT(val, RTW_MAXIM_HIDATA_MASK);

sys/dev/ic/rtwphyio.c

70

return __SHIFTOUT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK);

sys/dev/ic/siisatareg.h

255

#define PR_PS_ACTIVE_SLOT(x) __SHIFTOUT((x), PR_PS_ACTIVE_SLOT_MASK)

sys/dev/mii/mcommphy.c

445

switch (__SHIFTOUT(data, YT8521_CFG_LDO_MASK)) {

sys/dev/mii/mcommphy.c

472

__SHIFTOUT(rx_data_ds, YT8531_RGMII_RXD_DS_HIBITS);

sys/dev/mii/mcommphy.c

474

__SHIFTOUT(rx_data_ds, YT8531_RGMII_RXD_DS_LOBITS);

sys/dev/mii/rgephy.c

378

switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) {

sys/dev/nand/nand_toshiba.c

100

(8 << __SHIFTOUT(params2, NAND_TOSHIBA_OOBMASK)) *

sys/dev/nvmm/x86/nvmm_x86_svm.c

1205

exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1208

KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1209

exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1847

exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1976

seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1977

seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1978

seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1979

seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1980

seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1981

seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1982

seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1983

seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2213

state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v,

sys/dev/nvmm/x86/nvmm_x86_svm.c

2742

if (__SHIFTOUT(descs[0], CPUID_AMD_SVM_REV) != 1) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1224

if (__SHIFTOUT(qual, INTR_INFO_TYPE) != INTR_TYPE_NMI) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1648

type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1653

gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1716

type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1721

gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1756

type = __SHIFTOUT(qual, VMX_QUAL_CR_TYPE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1765

gpr = __SHIFTOUT(qual, VMX_QUAL_CR_GPR);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1800

switch (__SHIFTOUT(qual, VMX_QUAL_CR_NUM)) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1848

exit->u.io.port = __SHIFTOUT(qual, VMX_QUAL_IO_PORT);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1850

KASSERT(__SHIFTOUT(info, VMX_INFO_IO_SEG) < 6);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1851

exit->u.io.seg = __SHIFTOUT(info, VMX_INFO_IO_SEG);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1853

if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_64) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1855

} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_32) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1857

} else if (__SHIFTOUT(info, VMX_INFO_IO_ADRSIZE) == IO_ADRSIZE_16) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1861

if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_32) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1863

} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_16) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1865

} else if (__SHIFTOUT(qual, VMX_QUAL_IO_SIZE) == IO_SIZE_8) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2378

switch (__SHIFTOUT(info, INTR_INFO_TYPE)) {

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2704

segs[idx].attrib.type = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_TYPE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2705

segs[idx].attrib.s = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_S);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2706

segs[idx].attrib.dpl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DPL);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2707

segs[idx].attrib.p = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_P);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2708

segs[idx].attrib.avl = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_AVL);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2709

segs[idx].attrib.l = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_L);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2710

segs[idx].attrib.def = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_DEF);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2711

segs[idx].attrib.g = __SHIFTOUT(attrib, VMX_SEG_ATTRIB_G);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3612

if (__SHIFTOUT(msr, IA32_VMX_BASIC_MEM_TYPE) != MEM_TYPE_WB) {

sys/dev/pci/agp_i810.c

737

hi = __SHIFTOUT(addr, __BITS(63, 32));

sys/dev/pci/agp_i810.c

738

lo = __SHIFTOUT(addr, __BITS(31, 0));

sys/dev/pci/if_aq.c

2735

*modep = __SHIFTOUT(mpistate, FW1X_MPI_STATE_MODE);

sys/dev/pci/if_aq.c

2737

mpi_speed = __SHIFTOUT(mpistate, FW1X_MPI_STATE_SPEED);

sys/dev/pci/if_aq.c

2991

celsius = __SHIFTOUT(value, PHYINFO2_TEMPERATURE);

sys/dev/pci/if_aq.c

3325

if (__SHIFTOUT(tid0, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A) !=

sys/dev/pci/if_aq.c

3326

__SHIFTOUT(tid0, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B)) {

sys/dev/pci/if_aq.c

3406

__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MAJOR) << 24 |

sys/dev/pci/if_aq.c

3407

__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MINOR) << 16 |

sys/dev/pci/if_aq.c

3408

__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_BUILD);

sys/dev/pci/if_aq.c

3412

switch (__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER)) {

sys/dev/pci/if_aq.c

3431

sc->sc_filter_art_base_index = __SHIFTOUT(sc->sc_filter_caps.caps3,

sys/dev/pci/if_aq.c

3441

(int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MAJOR),

sys/dev/pci/if_aq.c

3442

(int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MINOR),

sys/dev/pci/if_aq.c

3443

(int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_BUILD));

sys/dev/pci/if_aq.c

3448

(int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MAJOR),

sys/dev/pci/if_aq.c

3449

(int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MINOR),

sys/dev/pci/if_aq.c

3450

(int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_BUILD));

sys/dev/pci/if_aq.c

3454

(int)__SHIFTOUT(v, __BITS(31, 24)),

sys/dev/pci/if_aq.c

3455

(int)__SHIFTOUT(v, __BITS(23, 16)),

sys/dev/pci/if_aq.c

3456

(int)__SHIFTOUT(v, __BITS(15, 8)),

sys/dev/pci/if_aq.c

3457

(int)__SHIFTOUT(v, __BITS(7, 0)));

sys/dev/pci/if_aq.c

3581

switch (__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE)) {

sys/dev/pci/if_aq.c

3699

data = __SHIFTOUT(health.data1, HEALTH_MONITOR_DATA1_TEMPERATURE);

sys/dev/pci/if_aq.c

5580

(__SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_VLAN) ||

sys/dev/pci/if_aq.c

5581

__SHIFTOUT(rxd_type,

sys/dev/pci/if_aq.c

5588

__SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_ETHER);

sys/dev/pci/if_aq.c

5591

__SHIFTOUT(rxd_type,

sys/dev/pci/if_aq.c

5594

if (__SHIFTOUT(rxd_status,

sys/dev/pci/if_aq.c

5605

if (__SHIFTOUT(rxd_type,

sys/dev/pci/if_aq.c

5609

__SHIFTOUT(rxd_type,

sys/dev/pci/if_aq.c

5648

(__SHIFTOUT(rxd_status,

sys/dev/pci/if_aq.c

5650

!__SHIFTOUT(rxd_status,

sys/dev/pci/if_aq.c

993

__SHIFTOUT(AQ_READ_REG(sc, reg), mask)

sys/dev/pci/if_et.c

1745

rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX);

sys/dev/pci/if_et.c

1760

buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN);

sys/dev/pci/if_et.c

1761

buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX);

sys/dev/pci/if_et.c

1762

ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX);

sys/dev/pci/if_et.c

1979

end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX);

sys/dev/pci/if_et.c

395

*val = __SHIFTOUT(data, ET_MII_STAT_VALUE);

sys/dev/pci/if_iavf.c

2594

switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) {

sys/dev/pci/if_iavf.c

2707

vtag = __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK);

sys/dev/pci/if_ixl.c

3136

switch (__SHIFTOUT(qword, IXL_RX_DESC_PTYPE_MASK)) {

sys/dev/pci/if_ixl.c

3248

vtag = __SHIFTOUT(word0, IXL_RX_DESC_L2TAG1_MASK);

sys/dev/pci/if_ixl.c

4049

nvm_maj_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_HI_MASK);

sys/dev/pci/if_ixl.c

4050

nvm_min_ver = (uint16_t)__SHIFTOUT(nvmver, IXL_NVM_VERSION_LO_MASK);

sys/dev/pci/if_ixl.c

4053

oem_ver = __SHIFTOUT(oem, IXL_NVM_OEMVERSION_MASK);

sys/dev/pci/if_ixl.c

4054

oem_build = __SHIFTOUT(oem, IXL_NVM_OEMBUILD_MASK);

sys/dev/pci/if_ixl.c

4055

oem_patch = __SHIFTOUT(oem, IXL_NVM_OEMPATCH_MASK);

sys/dev/pci/if_ixl.c

7023

*data = (uint16_t)__SHIFTOUT(reg, I40E_GLNVM_SRDATA_RDDATA_MASK);

sys/dev/pci/if_wm.c

10548

uint32_t speed = __SHIFTOUT(status, STATUS_SPEED);

sys/dev/pci/if_wm.c

13965

switch (__SHIFTOUT(reg, PCS_LSTS_SPEED)) {

sys/dev/pci/if_wm.c

14313

size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);

sys/dev/pci/if_wm.c

14326

size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);

sys/dev/pci/if_wm.c

15237

dword = __SHIFTOUT(dword, INVM_VER_1);

sys/dev/pci/if_wm.c

15238

sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR);

sys/dev/pci/if_wm.c

15239

sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR);

sys/dev/pci/if_wm.c

15984

&& (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))

sys/dev/pci/if_wm.c

16010

if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE)

sys/dev/pci/if_wm.c

16036

&& (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))

sys/dev/pci/if_wm.c

16551

moff = __SHIFTOUT(mreg, RCTL_MO);

sys/dev/pci/if_wm.c

17156

if (__SHIFTOUT(status, STATUS_SPEED) != STATUS_SPEED_1000)

sys/dev/pci/if_wm.c

17595

uint32_t speed = __SHIFTOUT(status, STATUS_SPEED);

sys/dev/pci/if_wm.c

18053

switch (__SHIFTOUT(status, STATUS_SPEED)) {

sys/dev/pci/if_wm.c

18111

lat_ns = __SHIFTOUT(lat_enc, PCI_LTR_MAXSNOOPLAT_VAL)

sys/dev/pci/if_wm.c

18113

__SHIFTOUT(lat_enc,

sys/dev/pci/if_wm.c

4338

wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),

sys/dev/pci/if_wm.c

4492

i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);

sys/dev/pci/if_wm.c

4885

freq = __SHIFTOUT(strap, STRAP_FREQ);

sys/dev/pci/if_wm.c

4892

phy_data |= __SHIFTOUT(strap, STRAP_SMBUSADDR);

sys/dev/pci/if_wm.c

4967

word_addr = __SHIFTOUT(extcnfctr, EXTCNFCTR_EXT_CNF_POINTER) << 1;

sys/dev/pci/if_wm.c

4970

cnf_size = __SHIFTOUT(reg, EXTCNFSIZE_LENGTH);

sys/dev/pci/if_wmreg.h

161

#define EXTRXC_IP_ID(rsshash) __SHIFTOUT(rsshash,ERXC_IP_ID_MASK)

sys/dev/pci/if_wmreg.h

162

#define EXTRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,ERXC_FRAG_CSUM_MASK)

sys/dev/pci/if_wmreg.h

169

#define EXTRXC_RSS_TYPE(mrq) __SHIFTOUT(mrq,EXTRXC_RSS_TYPE_MASK)

sys/dev/pci/if_wmreg.h

170

#define EXTRXC_QUEUE(mrq) __SHIFTOUT(mrq,EXTRXC_QUEUE_MASK)

sys/dev/pci/if_wmreg.h

182

#define EXTRXC_STATUS(err_stat) __SHIFTOUT(err_stat,EXTRXC_STATUS_MASK)

sys/dev/pci/if_wmreg.h

183

#define EXTRXC_ERROR(err_stat) __SHIFTOUT(err_stat,EXTRXC_ERROR_MASK)

sys/dev/pci/if_wmreg.h

209

#define EXTRXC_STATUS_PKTTYPE(status) __SHIFTOUT(status,EXTRXC_STATUS_PKTTYPE_MASK)

sys/dev/pci/if_wmreg.h

249

#define NQRXC_IP_ID(rsshash) __SHIFTOUT(rsshash,NRXC_IP_ID_MASK)

sys/dev/pci/if_wmreg.h

250

#define NQRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,NRXC_FRAG_CSUM_MASK)

sys/dev/pci/if_wmreg.h

264

#define NQRXC_RSS_TYPE(misc) __SHIFTOUT(misc,NQRXC_RSS_TYPE_MASK)

sys/dev/pci/if_wmreg.h

266

__SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ID_MASK)

sys/dev/pci/if_wmreg.h

267

#define NQRXC_PKT_TYPE(misc) __SHIFTOUT(misc,NQRXC_PKT_TYPE_MASK)

sys/dev/pci/if_wmreg.h

269

__SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ETQF_INDEX_MASK)

sys/dev/pci/if_wmreg.h

272

#define NQRXC_HEADER_LEN(misc) (__SHIFTOUT(misc,NQRXC_HDRLEN_LOW_MASK) \

sys/dev/pci/if_wmreg.h

273

| __SHIFTOUT(misc,NQRXC_HDRLEN_HIGH_MASK) << 10)

sys/dev/pci/if_wmreg.h

299

#define NQRXC_STATUS(err_stat) __SHIFTOUT(err_stat,NQRXC_STATUS_MASK)

sys/dev/pci/if_wmreg.h

300

#define NQRXC_ERROR(err_stat) __SHIFTOUT(err_stat,NQRXC_ERROR_MASK)

sys/dev/pci/ixgbe/ixgbe_osdep.c

59

return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),

sys/dev/pci/pci.c

1061

if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) {

sys/dev/pci/pci.c

981

if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) {

sys/dev/pci/pci_map.c

317

num_entries = __SHIFTOUT(val, PCI_EA_CAP1_NUMENTRIES);

sys/dev/pci/pci_map.c

327

unsigned int entry_size = __SHIFTOUT(val, PCI_EA_ES);

sys/dev/pci/pci_map.c

329

entry.bei = __SHIFTOUT(val, PCI_EA_BEI);

sys/dev/pci/pci_map.c

330

entry.props[0] = __SHIFTOUT(val, PCI_EA_PP);

sys/dev/pci/pci_map.c

331

entry.props[1] = __SHIFTOUT(val, PCI_EA_SP);

sys/dev/pci/pci_resource.c

540

iostart |= __SHIFTOUT(reshigh, PCI_BRIDGE_IOHIGH_BASE) << 16;

sys/dev/pci/pci_resource.c

541

ioend |= __SHIFTOUT(reshigh, PCI_BRIDGE_IOHIGH_LIMIT) << 16;

sys/dev/pci/pci_subr.c

85

#define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b)))

sys/dev/pci/pcireg.h

1283

#define PCI_SATA_BAR_NUM(x) (__SHIFTOUT((x), PCI_SATA_BAR_SPEC) - 4)

sys/dev/pci/pcireg.h

1360

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_PRIMARY))

sys/dev/pci/pcireg.h

1362

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SECONDARY))

sys/dev/pci/pcireg.h

1364

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SUBORDINATE))

sys/dev/pci/pcireg.h

1366

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SEC_LATTIMER))

sys/dev/pci/pcireg.h

1380

((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOBASE) \

sys/dev/pci/pcireg.h

1383

(((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOLIMIT) \

sys/dev/pci/pcireg.h

1393

((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_BASE) \

sys/dev/pci/pcireg.h

1396

(((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_LIMIT) \

sys/dev/pci/pcireg.h

1404

((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_BASE) \

sys/dev/pci/pcireg.h

1407

(((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_LIMIT) \

sys/dev/pci/pcireg.h

556

__SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK)

sys/dev/pci/pcireg.h

559

__SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK)

sys/dev/pci/pcireg.h

718

#define PCI_MSI_CTL_MME(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK)

sys/dev/pci/pcireg.h

720

#define PCI_MSI_CTL_MMC(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK)

sys/dev/pci/pcireg.h

984

#define PCIE_XCAP_VER(x) __SHIFTOUT((x), PCIE_XCAP_VER_MASK)

sys/dev/pci/pcireg.h

988

#define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK)

sys/dev/pci/piixpm.c

569

old_sda = __SHIFTOUT(reg, mask);

sys/dev/pci/ppb.c

174

u_int mlw = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);

sys/dev/pci/ppb.c

175

u_int mls = __SHIFTOUT(reg, PCIE_LCAP_MAX_SPEED);

sys/dev/pci/ppb.c

187

u_int lw = __SHIFTOUT(reg, PCIE_LCSR_NLW);

sys/dev/pci/ppb.c

188

u_int ls = __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED);

sys/dev/pci/ppb.c

369

base |= __SHIFTOUT(reg, PCI_BRIDGE_IOHIGH_BASE) << 16;

sys/dev/pci/ppb.c

370

limit |= __SHIFTOUT(reg, PCI_BRIDGE_IOHIGH_LIMIT) <<16;

sys/dev/pci/qat/qat_ae.c

1394

if (__SHIFTOUT(misc, AE_MISC_CONTROL_CS_RELOAD))

sys/dev/pci/qat/qat_ae.c

2617

sts = __SHIFTOUT(fcu, FCU_STATUS_STS);

sys/dev/pci/qat/qat_ae.c

2660

sts = __SHIFTOUT(fcu, FCU_STATUS_STS);

sys/dev/pci/qat/qat_ae.c

2661

loaded = __SHIFTOUT(fcu, FCU_STATUS_LOADED_AE);

sys/dev/pci/qat/qat_ae.c

2778

__SHIFTOUT(image->ui_ae_mode, AE_MODE_CTX_MODE));

sys/dev/pci/qat/qat_ae.c

2780

nn_mode = __SHIFTOUT(image->ui_ae_mode, AE_MODE_NN_MODE);

sys/dev/pci/qat/qat_ae.c

2785

__SHIFTOUT(image->ui_ae_mode, AE_MODE_LMEM0));

sys/dev/pci/qat/qat_ae.c

2787

__SHIFTOUT(image->ui_ae_mode, AE_MODE_LMEM1));

sys/dev/pci/qat/qat_ae.c

2790

__SHIFTOUT(image->ui_ae_mode, AE_MODE_SHARED_USTORE));

sys/dev/pci/qat/qat_ae.c

2792

__SHIFTOUT(image->ui_ae_mode, AE_MODE_RELOAD_CTX_SHARED),

sys/dev/pci/qat/qat_ae.c

3162

if (__SHIFTOUT(qui->qui_image->ui_ae_mode,

sys/dev/pci/qat/qat_ae.c

3173

if (__SHIFTOUT(qui->qui_image->ui_ae_mode,

sys/dev/pci/qat/qat_ae.c

3430

if (__SHIFTOUT(ui->ui_ae_mode, AE_MODE_CTX_MODE) == MAX_AE_CTX)

sys/dev/pci/qat/qat_hw15.c

507

__SHIFTOUT(init_resp->comn_resp.comn_status,

sys/dev/pckbport/alps.c

467

nibble = __SHIFTOUT(val, __BITS(7, 4));

sys/dev/pckbport/alps.c

472

nibble = __SHIFTOUT(val, __BITS(3, 0));

sys/dev/pckbport/alps.c

508

x_pitch = __SHIFTOUT(ret, __BITS(7, 4)); /* Higher 4-bit */

sys/dev/pckbport/alps.c

521

x_elec = __SHIFTOUT(ret, __BITS(7, 4)); /* Higher 4-bit */

sys/dev/pckbport/alps.c

678

nibble = __SHIFTOUT(val, __BITS(7, 4));

sys/dev/pckbport/alps.c

682

nibble = __SHIFTOUT(val, __BITS(3, 0));

sys/dev/pckbport/alps.c

729

if ((ecsig[0] == 0x88) && (__SHIFTOUT(ecsig[1], __BITS(7, 4)) == 0x0b)) {

sys/dev/pckbport/synaptics.c

372

if ((__SHIFTOUT(sc->caps, SYNAPTICS_CAP_EXTNUM) + 0x08)

sys/dev/pckbport/synaptics.c

409

if ((__SHIFTOUT(sc->caps, SYNAPTICS_CAP_EXTNUM) + 0x08) >=

sys/dev/pckbport/synapticsreg.h

94

((__SHIFTOUT((v), SYN_CCAP_CLICKPAD_BIT_1) << 1) | \

sys/dev/pckbport/synapticsreg.h

95

__SHIFTOUT((v), SYN_CCAP_CLICKPAD_BIT_0))

sys/dev/tprof/tprof_armv7.c

136

return __SHIFTOUT(armreg_pmcr_read(), PMCR_N);

sys/dev/tprof/tprof_armv8.c

113

return __SHIFTOUT(reg_pmcr_el0_read(), PMCR_N);

sys/dev/tprof/tprof_armv8.c

270

const u_int pmuver = __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_PMUVER);

sys/dev/tprof/tprof_armv8.c

289

const u_int pmuver = __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_PMUVER);

sys/dev/tprof/tprof_x86_intel.c

111

return __SHIFTOUT(descs[0], CPUID_PERF_NGPPC);

sys/dev/tprof/tprof_x86_intel.c

252

counter_bitwidth = __SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC);

sys/dev/usb/ehci.c

2581

i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;

sys/dev/usb/ehcireg.h

213

#define EHCI_ITD_GET_STATUS(x) __SHIFTOUT((x), EHCI_ITD_STATUS_MASK)

sys/dev/usb/ehcireg.h

220

#define EHCI_ITD_GET_LEN(x) __SHIFTOUT((x), EHCI_ITD_LEN_MASK)

sys/dev/usb/ehcireg.h

223

#define EHCI_ITD_GET_IOC(x) __SHIFTOUT((x), EHCI_ITD_IOC)

sys/dev/usb/ehcireg.h

226

#define EHCI_ITD_GET_PG(x) __SHIFTOUT((x), EHCI_ITD_PG_MASK)

sys/dev/usb/ehcireg.h

229

#define EHCI_ITD_GET_OFFS(x) __SHIFTOUT((x), EHCI_ITD_OFFSET_MASK)

sys/dev/usb/ehcireg.h

236

#define EHCI_ITD_GET_EP(x) __SHIFTOUT((x), EHCI_ITD_EP_MASK)

sys/dev/usb/ehcireg.h

239

#define EHCI_ITD_GET_DADDR(x) __SHIFTOUT((x), EHCI_ITD_DADDR_MASK)

sys/dev/usb/ehcireg.h

242

#define EHCI_ITD_GET_DIR(x) __SHIFTOUT((x), EHCI_ITD_DIR_MASK)

sys/dev/usb/ehcireg.h

245

#define EHCI_ITD_GET_MAXPKT(x) __SHIFTOUT((x), EHCI_ITD_MAXPKT_MASK)

sys/dev/usb/ehcireg.h

248

#define EHCI_ITD_GET_MULTI(x) __SHIFTOUT((x), EHCI_ITD_MULTI_MASK)

sys/dev/usb/ehcireg.h

280

#define EHCI_SITD_GET_LEN(x) __SHIFTOUT((x), EHCI_SITD_LENGTH_MASK)

sys/dev/usb/ehcireg.h

315

#define EHCI_QTD_GET_STATUS(x) __SHIFTOUT((x), EHCI_QTD_STATUS_MASK)

sys/dev/usb/ehcireg.h

327

#define EHCI_QTD_GET_PID(x) __SHIFTOUT((x), EHCI_QTD_PID_MASK)

sys/dev/usb/ehcireg.h

333

#define EHCI_QTD_GET_CERR(x) __SHIFTOUT((x), EHCI_QTD_CERR_MASK)

sys/dev/usb/ehcireg.h

336

#define EHCI_QTD_GET_C_PAGE(x) __SHIFTOUT((x), EHCI_QTD_C_PAGE_MASK)

sys/dev/usb/ehcireg.h

339

#define EHCI_QTD_GET_IOC(x) __SHIFTOUT((x), EHCI_QTD_IOC)

sys/dev/usb/ehcireg.h

341

#define EHCI_QTD_GET_BYTES(x) __SHIFTOUT((x), EHCI_QTD_BYTES_MASK)

sys/dev/usb/ehcireg.h

344

#define EHCI_QTD_GET_TOGGLE(x) __SHIFTOUT((x), EHCI_QTD_TOGGLE_MASK)

sys/dev/usb/ehcireg.h

359

#define EHCI_QH_GET_ADDR(x) __SHIFTOUT((x), EHCI_QH_ADDR_MASK)

sys/dev/usb/ehcireg.h

362

#define EHCI_QH_GET_INACT(x) __SHIFTOUT((x), EHCI_QH_INACT)

sys/dev/usb/ehcireg.h

364

#define EHCI_QH_GET_ENDPT(x) __SHIFTOUT((x), EHCI_QH_ENDPT_MASK)

sys/dev/usb/ehcireg.h

367

#define EHCI_QH_GET_EPS(x) __SHIFTOUT((x), EHCI_QH_EPS_MASK)

sys/dev/usb/ehcireg.h

373

#define EHCI_QH_GET_DTC(x) __SHIFTOUT((x), EHCI_QH_DTC)

sys/dev/usb/ehcireg.h

375

#define EHCI_QH_GET_HRECL(x) __SHIFTOUT((x), EHCI_QH_HRECL)

sys/dev/usb/ehcireg.h

377

#define EHCI_QH_GET_MPL(x) __SHIFTOUT((x), EHCI_QH_MPL_MASK)

sys/dev/usb/ehcireg.h

380

#define EHCI_QH_GET_CTL(x) __SHIFTOUT((x), EHCI_QH_CTL)

sys/dev/usb/ehcireg.h

382

#define EHCI_QH_GET_NRL(x) __SHIFTOUT((x), EHCI_QH_NRL_MASK)

sys/dev/usb/ehcireg.h

386

#define EHCI_QH_GET_SMASK(x) __SHIFTOUT((x), EHCI_QH_SMASK_MASK)

sys/dev/usb/ehcireg.h

389

#define EHCI_QH_GET_CMASK(x) __SHIFTOUT((x), EHCI_QH_CMASK_MASK)

sys/dev/usb/ehcireg.h

392

#define EHCI_QH_GET_HUBA(x) __SHIFTOUT((x), EHCI_QH_HUBA_MASK)

sys/dev/usb/ehcireg.h

395

#define EHCI_QH_GET_PORT(x) __SHIFTOUT((x), EHCI_QH_PORT_MASK)

sys/dev/usb/ehcireg.h

398

#define EHCI_QH_GET_MULT(x) __SHIFTOUT((x), EHCI_QH_MULTI_MASK)

sys/dev/usb/ehcireg.h

92

#define EHCI_HCC_GET_IST_THRESHOLD(x) __SHIFTOUT((x), EHCI_HCC_IST_THRESHOLD_MASK)

sys/dev/usb/if_mue.c

865

(unsigned)__SHIFTOUT(id_rev, MUE_ID_REV_ID),

sys/dev/usb/if_mue.c

866

(unsigned)__SHIFTOUT(id_rev, MUE_ID_REV_REV));

sys/dev/usb/ohci.c

2064

__SHIFTOUT(flags, OHCI_ED_SPEED),

sys/dev/usb/ohci.c

2065

__SHIFTOUT(flags, OHCI_ED_SKIP),

sys/dev/usb/ohcireg.h

102

#define OHCI_FM_GET_IVAL(x) __SHIFTOUT((x), OHCI_FM_IVAL_MASK)

sys/dev/usb/ohcireg.h

104

#define OHCI_FM_GET_FSMPS(x) __SHIFTOUT((x), OHCI_FM_FSMPS_MASK)

sys/dev/usb/ohcireg.h

113

#define OHCI_RHD_GET_NDP(x) __SHIFTOUT((x), OHCI_RHD_NDP_MASK)

sys/dev/usb/ohcireg.h

120

#define OHCI_RHD_GET_POTPGT(x) __SHIFTOUT((x), OHCI_RHD_POTPGT_MASK)

sys/dev/usb/ohcireg.h

159

#define OHCI_ED_GET_FA(x) __SHIFTOUT((x), OHCI_ED_ADDR_MASK)

sys/dev/usb/ohcireg.h

162

#define OHCI_ED_GET_EN(x) __SHIFTOUT((x), OHCI_ED_EN_MASK)

sys/dev/usb/ohcireg.h

165

#define OHCI_ED_GET_DIR(x) __SHIFTOUT((x), OHCI_ED_DIR_MASK)

sys/dev/usb/ohcireg.h

173

#define OHCI_ED_GET_FORMAT(x) __SHIFTOUT((x), OHCI_ED_FORMAT_MASK)

sys/dev/usb/ohcireg.h

178

#define OHCI_ED_GET_MAXP(x) __SHIFTOUT((x), OHCI_ED_MAXP_MASK)

sys/dev/usb/ohcireg.h

198

#define OHCI_TD_GET_DP(x) __SHIFTOUT((x), OHCI_TD_DP_MASK)

sys/dev/usb/ohcireg.h

204

#define OHCI_TD_GET_DI(x) __SHIFTOUT((x), OHCI_TD_DI_MASK)

sys/dev/usb/ohcireg.h

208

#define OHCI_TD_GET_TOGGLE(x) __SHIFTOUT((x), OHCI_TD_TOGGLE_MASK)

sys/dev/usb/ohcireg.h

214

#define OHCI_TD_GET_EC(x) __SHIFTOUT((x), OHCI_TD_EC_MASK)

sys/dev/usb/ohcireg.h

216

#define OHCI_TD_GET_CC(x) __SHIFTOUT((x), OHCI_TD_CC_MASK)

sys/dev/usb/ohcireg.h

236

#define OHCI_ITD_GET_SF(x) __SHIFTOUT((x), OHCI_ITD_SF_MASK)

sys/dev/usb/ohcireg.h

239

#define OHCI_ITD_GET_DI(x) __SHIFTOUT((x), OHCI_ITD_DI_MASK)

sys/dev/usb/ohcireg.h

242

#define OHCI_ITD_GET_FC(x) (__SHIFTOUT((x), OHCI_ITD_FC_MASK) + 1)

sys/dev/usb/ohcireg.h

245

#define OHCI_ITD_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_CC_MASK)

sys/dev/usb/ohcireg.h

257

#define OHCI_ITD_PSW_SIZE(x) __SHIFTOUT((x), OHCI_ITD_PSW_SIZE_MASK)

sys/dev/usb/ohcireg.h

259

#define OHCI_ITD_PSW_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_PSW_CC_MASK)

sys/dev/usb/ohcireg.h

48

#define OHCI_REV_LO(rev) __SHIFTOUT((rev), OHCI_REV_LO_MASK)

sys/dev/usb/ohcireg.h

49

#define OHCI_REV_HI(rev) __SHIFTOUT((rev), OHCI_REV_HI_MASK)

sys/dev/usb/ohcireg.h

51

#define OHCI_REV_LEGACY(rev) __SHIFTOUT((rev), OHCI_REV_LEGACY_MASK)

sys/dev/usb/ohcireg.h

66

#define OHCI_GET_HCFS(x) __SHIFTOUT((x), OHCI_HCFS_MASK)

sys/dev/usb/slurm.c

267

switch (__SHIFTOUT(sysconfig2, SI470X_SPACE)) {

sys/dev/usb/slurm.c

280

switch (__SHIFTOUT(sysconfig2, SI470X_BAND)) {

sys/dev/usb/slurm.c

295

readchannel = __SHIFTOUT(readchannel, SI470X_READCHAN);

sys/dev/usb/slurm.c

302

return (__SHIFTOUT(statusrssi, SI470X_ST) ? RADIO_INFO_STEREO : 0)

sys/dev/usb/slurm.c

303

| (__SHIFTOUT(statusrssi, SI470X_AFCRL) ? 0 : RADIO_INFO_SIGNAL);

sys/dev/usb/slurm.c

309

return __SHIFTOUT(powercfg, SI470X_DMUTE) ? 0 : 1;

sys/dev/usb/slurm.c

315

return __SHIFTOUT(powercfg, SI470X_MONO) ? 0 : 1;

sys/dev/usb/slurm.c

321

return __SHIFTOUT(sysconfig2, SI470X_VOLUME) * SI470X_VOLFACT;

sys/dev/usb/uhcireg.h

105

#define UHCI_PORTSC_GET_LS(p) __SHIFTOUT((p), UHCI_PORTSC_LS_MASK)

sys/dev/usb/uhcireg.h

151

((__SHIFTOUT((s), UHCI_TD_ACTLEN_MASK) + 1) & __SHIFTOUT_MASK(UHCI_TD_ACTLEN_MASK))

sys/dev/usb/uhcireg.h

165

#define UHCI_TD_GET_ERRCNT(s) __SHIFTOUT((s), UHCI_TD_ERRCNT_MASK)

sys/dev/usb/uhcireg.h

174

#define UHCI_TD_GET_PID(s) __SHIFTOUT((s), UHCI_TD_PID_MASK)

sys/dev/usb/uhcireg.h

177

#define UHCI_TD_GET_DEVADDR(s) __SHIFTOUT((s), UHCI_TD_DEVADDR_MASK)

sys/dev/usb/uhcireg.h

180

#define UHCI_TD_GET_ENDPT(s) __SHIFTOUT((s), UHCI_TD_ENDPT_MASK)

sys/dev/usb/uhcireg.h

183

#define UHCI_TD_GET_DT(s) __SHIFTOUT((s), UHCI_TD_DT_MASK)

sys/dev/usb/uhcireg.h

188

(__SHIFTOUT((s), UHCI_TD_MAXLEN_MASK) + 1)

sys/dev/usb/usb.h

319

#define UE_GET_BULK_STREAMS(x) __SHIFTOUT(x, UE_GET_BULK_STREAMS_MASK)

sys/dev/usb/usb.h

321

#define UE_GET_SS_ISO_MULT(x) __SHIFTOUT(x, UE_GET_SS_ISO_MULT_MASK)

sys/dev/usb/usb.h

323

#define UE_GET_SS_ISO_SSP(x) __SHIFTOUT(x, UE_GET_SS_ISO_SSP_MASK)

sys/dev/usb/usb.h

372

#define USB_DEVCAP_V2EXT_BESL_BASELINE_GET(x) __SHIFTOUT(x, USB_V2EXT_BESL_BASELINE_MASK)

sys/dev/usb/usb.h

374

#define USB_DEVCAP_V2EXT_BESL_DEEP_GET(x) __SHIFTOUT(x, USB_V2EXT_BESL_DEEP_MASK)

sys/dev/usb/usb.h

423

#define USB_DEVCAP_SSP_SSAC(x) __SHIFTOUT(x, __BITS(4,0))

sys/dev/usb/usb.h

424

#define USB_DEVCAP_SSP_SSIC(x) __SHIFTOUT(x, __BITS(8,5))

sys/dev/usb/usb.h

426

#define USB_DEVCAP_SSP_SSID(x) __SHIFTOUT(x, __BITS(3,0))

sys/dev/usb/usb.h

427

#define USB_DEVCAP_SSP_MIN_RXLANE_COUNT(x) __SHIFTOUT(x, __BITS(11,8))

sys/dev/usb/usb.h

428

#define USB_DEVCAP_SSP_MIN_TXLANE_COUNT(x) __SHIFTOUT(x, __BITS(15,12))

sys/dev/usb/usb.h

431

#define USB_DEVCAP_SSP_SSID(x) __SHIFTOUT(x, __BITS(3,0))

sys/dev/usb/usb.h

432

#define USB_DEVCAP_SSP_LSE(x) __SHIFTOUT(x, __BITS(5,4))

sys/dev/usb/usb.h

433

#define USB_DEVCAP_SSP_ST(x) __SHIFTOUT(x, __BITS(7,6))

sys/dev/usb/usb.h

434

#define USB_DEVCAP_SSP_LP(x) __SHIFTOUT(x, __BITS(15,14))

sys/dev/usb/usb.h

435

#define USB_DEVCAP_SSP_LSM(x) __SHIFTOUT(x, __BITS(31,16))

sys/dev/usb/usb.h

599

#define UPS_PORT_LS_GET(x) __SHIFTOUT(x, UPS_PORT_LS_MASK)

sys/dev/usb/xhci.c

1244

const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16));

sys/dev/usb/xhci.c

3817

__SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK);

sys/dev/usb/xhci.c

593

return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit);

sys/dev/usb/xhcireg.h

104

#define XHCI_HCC2_U3C(x) __SHIFTOUT((x), __BIT(0)) /* U3 Entry capable */

sys/dev/usb/xhcireg.h

105

#define XHCI_HCC2_CMC(x) __SHIFTOUT((x), __BIT(1)) /* CEC MaxExLatTooLg */

sys/dev/usb/xhcireg.h

106

#define XHCI_HCC2_FSC(x) __SHIFTOUT((x), __BIT(2)) /* Force Save Context */

sys/dev/usb/xhcireg.h

107

#define XHCI_HCC2_CTC(x) __SHIFTOUT((x), __BIT(3)) /* Compliance Transc */

sys/dev/usb/xhcireg.h

108

#define XHCI_HCC2_LEC(x) __SHIFTOUT((x), __BIT(4)) /* Large ESIT Payload */

sys/dev/usb/xhcireg.h

109

#define XHCI_HCC2_CIC(x) __SHIFTOUT((x), __BIT(5)) /* Configuration Inf */

sys/dev/usb/xhcireg.h

110

#define XHCI_HCC2_ETC(x) __SHIFTOUT((x), __BIT(6)) /* Extended TBC */

sys/dev/usb/xhcireg.h

111

#define XHCI_HCC2_ETC_TSC(x) __SHIFTOUT((x), __BIT(7)) /* ExtTBC TRB Status */

sys/dev/usb/xhcireg.h

112

#define XHCI_HCC2_GSC(x) __SHIFTOUT((x), __BIT(8)) /* Get/Set Extended Property */

sys/dev/usb/xhcireg.h

113

#define XHCI_HCC2_VTC(x) __SHIFTOUT((x), __BIT(9)) /* Virt. Based Trust */

sys/dev/usb/xhcireg.h

197

#define XHCI_PS_PLS_GET(x) __SHIFTOUT((x), XHCI_PS_PLS_MASK) /* RW - port link state */

sys/dev/usb/xhcireg.h

223

#define XHCI_PS_SPEED_GET(x) __SHIFTOUT((x), XHCI_PS_SPEED_MASK)

sys/dev/usb/xhcireg.h

229

#define XHCI_PS_PIC_GET(x) __SHIFTOUT((x), XHCI_PS_PIC_MASK)

sys/dev/usb/xhcireg.h

251

#define XHCI_PM3_U1TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U1TO_MASK)

sys/dev/usb/xhcireg.h

254

#define XHCI_PM3_U2TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U2TO_MASK)

sys/dev/usb/xhcireg.h

260

#define XHCI_PM2_L1S_GET(x) __SHIFTOUT((x), XHCI_PM2_L1S_MASK)

sys/dev/usb/xhcireg.h

263

#define XHCI_PM2_BESL_GET(x) __SHIFTOUT((x), XHCI_PM2_BESL_MASK)

sys/dev/usb/xhcireg.h

266

#define XHCI_PM2_L1SLOT_GET(x) __SHIFTOUT((x), XHCI_PM2_L1SLOT_MASK)

sys/dev/usb/xhcireg.h

270

#define XHCI_PM2_PTC_GET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK)

sys/dev/usb/xhcireg.h

271

#define XHCI_PM2_PTC_SET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK)

sys/dev/usb/xhcireg.h

277

#define XHCI_PLI3_ERR_GET(x) __SHIFTOUT((x), XHCI_PLI3_ERR_MASK)

sys/dev/usb/xhcireg.h

279

#define XHCI_PLI3_RLC_GET __SHIFTOUT((x), XHCI_PLI3_RLC_MASK)

sys/dev/usb/xhcireg.h

281

#define XHCI_PLI3_TLC_GET __SHIFTOUT((x), XHCI_PLI3_TLC_MASK)

sys/dev/usb/xhcireg.h

287

#define XHCI_PLMC3_LSEC_GET(x) __SHIFTOUT((x), XHCI_PLMC3_LSEC_MASK)

sys/dev/usb/xhcireg.h

293

#define XHCI_MFINDEX_GET(x) __SHIFTOUT((x), XHCI_MFINDEX_MASK)

sys/dev/usb/xhcireg.h

304

#define XHCI_IMOD_IVAL_GET(x) __SHIFTOUT((x), XHCI_IMOD_IVAL_MASK)

sys/dev/usb/xhcireg.h

307

#define XHCI_IMOD_ICNT_GET(x) __SHIFTOUT((x), XHCI_IMOD_ICNT_MASK)

sys/dev/usb/xhcireg.h

316

#define XHCI_ERSTS_GET(x) __SHIFTOUT((x), XHCI_ERSTS_MASK)

sys/dev/usb/xhcireg.h

327

#define XHCI_ERDP_GET_DESI(x) __SHIFTOUT(x), XHCI_ERDP_DESI_MASK)

sys/dev/usb/xhcireg.h

335

#define XHCI_DB_TARGET_GET(x) __SHIFTOUT((x), XHCI_DB_TARGET_MASK)

sys/dev/usb/xhcireg.h

338

#define XHCI_DB_SID_GET(x) __SHIFTOUT((x), XHCI_DB_SID_MASK)

sys/dev/usb/xhcireg.h

343

#define XHCI_XECP_ID(x) __SHIFTOUT((x), XHCI_XECP_ID_MASK)

sys/dev/usb/xhcireg.h

345

#define XHCI_XECP_NEXT(x) __SHIFTOUT((x), XHCI_XECP_NEXT_MASK)

sys/dev/usb/xhcireg.h

367

#define XHCI_XECP_SP_W0_MINOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MINOR_MASK)

sys/dev/usb/xhcireg.h

369

#define XHCI_XECP_SP_W0_MAJOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MAJOR_MASK)

sys/dev/usb/xhcireg.h

372

#define XHCI_XECP_SP_W8_CPO(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPO_MASK)

sys/dev/usb/xhcireg.h

374

#define XHCI_XECP_SP_W8_CPC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPC_MASK)

sys/dev/usb/xhcireg.h

376

#define XHCI_XECP_SP_W8_PD(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PD_MASK)

sys/dev/usb/xhcireg.h

378

#define XHCI_XECP_SP_W8_PSIC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PSIC_MASK)

sys/dev/usb/xhcireg.h

404

#define XHCI_TRB_2_ERROR_GET(x) __SHIFTOUT((x), XHCI_TRB_2_ERROR_MASK)

sys/dev/usb/xhcireg.h

408

#define XHCI_TRB_2_TDSZ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_TDSZ_MASK)

sys/dev/usb/xhcireg.h

411

#define XHCI_TRB_2_REM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_REM_MASK)

sys/dev/usb/xhcireg.h

415

#define XHCI_TRB_2_BYTES_GET(x) __SHIFTOUT((x), XHCI_TRB_2_BYTES_MASK)

sys/dev/usb/xhcireg.h

418

#define XHCI_TRB_2_IRQ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_IRQ_MASK)

sys/dev/usb/xhcireg.h

421

#define XHCI_TRB_2_STREAM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_STREAM_MASK)

sys/dev/usb/xhcireg.h

425

#define XHCI_TRB_3_TYPE_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TYPE_MASK)

sys/dev/usb/xhcireg.h

436

#define XHCI_TRB_3_TBC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TBC_MASK)

sys/dev/usb/xhcireg.h

449

#define XHCI_TRB_3_TLBPC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TLBPC_MASK)

sys/dev/usb/xhcireg.h

452

#define XHCI_TRB_3_EP_GET(x) __SHIFTOUT((x), XHCI_TRB_3_EP_MASK)

sys/dev/usb/xhcireg.h

455

#define XHCI_TRB_3_FRID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_FRID_MASK)

sys/dev/usb/xhcireg.h

460

#define XHCI_TRB_3_VFID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_VFID_MASK)

sys/dev/usb/xhcireg.h

463

#define XHCI_TRB_3_SLOT_GET(x) __SHIFTOUT((x), XHCI_TRB_3_SLOT_MASK)

sys/dev/usb/xhcireg.h

546

#define XHCI_SCTX_0_ROUTE_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_ROUTE_MASK)

sys/dev/usb/xhcireg.h

549

#define XHCI_SCTX_0_SPEED_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_SPEED_MASK)

sys/dev/usb/xhcireg.h

553

#define XHCI_SCTX_0_MTT_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_MTT_MASK)

sys/dev/usb/xhcireg.h

556

#define XHCI_SCTX_0_HUB_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_HUB_MASK)

sys/dev/usb/xhcireg.h

559

#define XHCI_SCTX_0_CTX_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_CTX_NUM_MASK)

sys/dev/usb/xhcireg.h

563

#define XHCI_SCTX_1_MAX_EL_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_MAX_EL_MASK)

sys/dev/usb/xhcireg.h

566

#define XHCI_SCTX_1_RH_PORT_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_RH_PORT_MASK)

sys/dev/usb/xhcireg.h

569

#define XHCI_SCTX_1_NUM_PORTS_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_NUM_PORTS_MASK)

sys/dev/usb/xhcireg.h

573

#define XHCI_SCTX_2_TT_HUB_SID_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_HUB_SID_MASK)

sys/dev/usb/xhcireg.h

576

#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_PORT_NUM_MASK)

sys/dev/usb/xhcireg.h

579

#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_THINK_TIME_MASK)

sys/dev/usb/xhcireg.h

58

#define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXSLOTS_MASK)

sys/dev/usb/xhcireg.h

582

#define XHCI_SCTX_2_IRQ_TARGET_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_IRQ_TARGET_MASK)

sys/dev/usb/xhcireg.h

586

#define XHCI_SCTX_3_DEV_ADDR_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_DEV_ADDR_MASK)

sys/dev/usb/xhcireg.h

589

#define XHCI_SCTX_3_SLOT_STATE_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_SLOT_STATE_MASK)

sys/dev/usb/xhcireg.h

60

#define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT((x), XHCI_HCS1_MAXINTRS_MASK)

sys/dev/usb/xhcireg.h

601

#define XHCI_EPCTX_0_EPSTATE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_EPSTATE_MASK)

sys/dev/usb/xhcireg.h

609

#define XHCI_EPCTX_0_MULT_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MULT_MASK)

sys/dev/usb/xhcireg.h

612

#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK)

sys/dev/usb/xhcireg.h

615

#define XHCI_EPCTX_0_LSA_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_LSA_MASK)

sys/dev/usb/xhcireg.h

618

#define XHCI_EPCTX_0_IVAL_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_IVAL_MASK)

sys/dev/usb/xhcireg.h

62

#define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXPORTS_MASK)

sys/dev/usb/xhcireg.h

621

#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK)

sys/dev/usb/xhcireg.h

625

#define XHCI_EPCTX_1_CERR_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_CERR_MASK)

sys/dev/usb/xhcireg.h

628

#define XHCI_EPCTX_1_EPTYPE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_EPTYPE_MASK)

sys/dev/usb/xhcireg.h

631

#define XHCI_EPCTX_1_HID_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_HID_MASK)

sys/dev/usb/xhcireg.h

634

#define XHCI_EPCTX_1_MAXB_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXB_MASK)

sys/dev/usb/xhcireg.h

637

#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXP_SIZE_MASK)

sys/dev/usb/xhcireg.h

642

#define XHCI_EPCTX_2_DCS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_2_DCS_MASK)

sys/dev/usb/xhcireg.h

647

#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK)

sys/dev/usb/xhcireg.h

650

#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK)

sys/dev/usb/xhcireg.h

66

#define XHCI_HCS2_IST(x) __SHIFTOUT((x), XHCI_HCS2_IST_MASK)

sys/dev/usb/xhcireg.h

68

#define XHCI_HCS2_ERSTMAX(x) __SHIFTOUT((x), XHCI_HCS2_ERSTMAX_MASK)

sys/dev/usb/xhcireg.h

71

#define XHCI_HCS2_SPR(x) __SHIFTOUT((x), XHCI_HCS2_SPR_MASK)

sys/dev/usb/xhcireg.h

74

(__SHIFTOUT((x), XHCI_HCS2_SPBUFHI_MASK) << 5) | \

sys/dev/usb/xhcireg.h

75

(__SHIFTOUT((x), XHCI_HCS2_SPBUFLO_MASK))

sys/dev/usb/xhcireg.h

79

#define XHCI_HCS3_U1_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U1_DEL_MASK)

sys/dev/usb/xhcireg.h

81

#define XHCI_HCS3_U2_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U2_DEL_MASK)

sys/dev/usb/xhcireg.h

84

#define XHCI_HCC_AC64(x) __SHIFTOUT((x), __BIT(0)) /* 64-bit capable */

sys/dev/usb/xhcireg.h

85

#define XHCI_HCC_BNC(x) __SHIFTOUT((x), __BIT(1)) /* BW negotiation */

sys/dev/usb/xhcireg.h

86

#define XHCI_HCC_CSZ(x) __SHIFTOUT((x), __BIT(2)) /* context size */

sys/dev/usb/xhcireg.h

87

#define XHCI_HCC_PPC(x) __SHIFTOUT((x), __BIT(3)) /* port power control */

sys/dev/usb/xhcireg.h

88

#define XHCI_HCC_PIND(x) __SHIFTOUT((x), __BIT(4)) /* port indicators */

sys/dev/usb/xhcireg.h

89

#define XHCI_HCC_LHRC(x) __SHIFTOUT((x), __BIT(5)) /* light HC reset */

sys/dev/usb/xhcireg.h

90

#define XHCI_HCC_LTC(x) __SHIFTOUT((x), __BIT(6)) /* latency tolerance msg */

sys/dev/usb/xhcireg.h

91

#define XHCI_HCC_NSS(x) __SHIFTOUT((x), __BIT(7)) /* no secondary sid */

sys/dev/usb/xhcireg.h

92

#define XHCI_HCC_PAE(x) __SHIFTOUT((x), __BIT(8)) /* Parse All Event Data */

sys/dev/usb/xhcireg.h

93

#define XHCI_HCC_SPC(x) __SHIFTOUT((x), __BIT(9)) /* Short packet */

sys/dev/usb/xhcireg.h

94

#define XHCI_HCC_SEC(x) __SHIFTOUT((x), __BIT(10)) /* Stopped EDTLA */

sys/dev/usb/xhcireg.h

95

#define XHCI_HCC_CFC(x) __SHIFTOUT((x), __BIT(11)) /* Contiguous Frame ID */

sys/dev/usb/xhcireg.h

97

#define XHCI_HCC_MAXPSASIZE(x) __SHIFTOUT((x), XHCI_HCC_MAXPSASIZE_MASK)

sys/dev/usb/xhcireg.h

99

#define XHCI_HCC_XECP(x) __SHIFTOUT((x), XHCI_HCC_XECP_MASK)

sys/dev/vmt/vmt_subr.c

1010

if (__SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) != VM_RPC_ENH_DATA) {

sys/dev/vmt/vmt_subr.c

1027

if (__SHIFTOUT(frame.ecx, VM_REG_HIGH_MASK) == 0) {

sys/dev/vmt/vmt_subr.c

1052

if ((__SHIFTOUT(frame.ecx, VM_REG_HIGH_MASK) & VM_RPC_REPLY_SUCCESS) ==

sys/dev/vmt/vmt_subr.c

1059

if ((__SHIFTOUT(frame.ecx, VM_REG_HIGH_MASK) & VM_RPC_REPLY_DORECV) ==

sys/dev/vmt/vmt_subr.c

1064

*length = __SHIFTOUT(frame.ebx, VM_REG_WORD_MASK);

sys/dev/vmt/vmt_subr.c

1065

*dataid = __SHIFTOUT(frame.edx, VM_REG_HIGH_MASK);

sys/dev/vmt/vmt_subr.c

157

if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) == 0xffffffff ||

sys/dev/vmt/vmt_subr.c

158

__SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) != VM_MAGIC)

sys/dev/vmt/vmt_subr.c

162

if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) == VM_MAGIC)

sys/dev/vmt/vmt_subr.c

180

if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) == 0xffffffff ||

sys/dev/vmt/vmt_subr.c

181

__SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) != VM_MAGIC) {

sys/dev/vmt/vmt_subr.c

193

bswap32(__SHIFTOUT(frame.eax, VM_REG_WORD_MASK));

sys/dev/vmt/vmt_subr.c

194

u = bswap32(__SHIFTOUT(frame.ebx, VM_REG_WORD_MASK));

sys/dev/vmt/vmt_subr.c

197

u = bswap32(__SHIFTOUT(frame.ecx, VM_REG_WORD_MASK));

sys/dev/vmt/vmt_subr.c

202

u = bswap32(__SHIFTOUT(frame.edx, VM_REG_WORD_MASK));

sys/dev/vmt/vmt_subr.c

476

if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) != 0xffffffff) {

sys/dev/vmt/vmt_subr.c

478

__SHIFTOUT(frame.esi, VM_REG_WORD_MASK) << 32)) |

sys/dev/vmt/vmt_subr.c

479

__SHIFTOUT(frame.edx, VM_REG_WORD_MASK);

sys/dev/vmt/vmt_subr.c

480

ts.tv_nsec = __SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) * 1000;

sys/dev/vmt/vmt_subr.c

888

if (__SHIFTOUT(frame.ecx, VM_REG_HIGH_MASK) != 1 ||

sys/dev/vmt/vmt_subr.c

889

__SHIFTOUT(frame.edx, VM_REG_LOW_MASK) != 0) {

sys/dev/vmt/vmt_subr.c

897

rpc->channel = __SHIFTOUT(frame.edx, VM_REG_HIGH_MASK);

sys/dev/vmt/vmt_subr.c

898

rpc->cookie1 = __SHIFTOUT(frame.esi, VM_REG_WORD_MASK);

sys/dev/vmt/vmt_subr.c

899

rpc->cookie2 = __SHIFTOUT(frame.edi, VM_REG_WORD_MASK);

sys/dev/vmt/vmt_subr.c

919

if (__SHIFTOUT(frame.ecx, VM_REG_HIGH_MASK) == 0 ||

sys/dev/vmt/vmt_subr.c

920

__SHIFTOUT(frame.ecx, VM_REG_LOW_MASK) != 0) {

sys/dev/vmt/vmt_subr.c

950

if ((__SHIFTOUT(frame.ecx, VM_REG_HIGH_MASK) & VM_RPC_REPLY_SUCCESS) ==

sys/dev/vmt/vmt_subr.c

973

if (__SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) != VM_RPC_ENH_DATA) {

sys/dev/vmt/vmtvar.h

205

regs[0] = __SHIFTOUT(frame.eax, VM_REG_WORD_MASK);

sys/dev/vmt/vmtvar.h

206

regs[1] = __SHIFTOUT(frame.ebx, VM_REG_WORD_MASK);

sys/dev/vmt/vmtvar.h

207

regs[2] = __SHIFTOUT(frame.ecx, VM_REG_WORD_MASK);

sys/dev/vmt/vmtvar.h

208

regs[3] = __SHIFTOUT(frame.edx, VM_REG_WORD_MASK);

sys/dev/vmt/vmtvar.h

209

regs[4] = __SHIFTOUT(frame.esi, VM_REG_WORD_MASK);

sys/dev/vmt/vmtvar.h

210

regs[5] = __SHIFTOUT(frame.edi, VM_REG_WORD_MASK);

sys/kern/subr_xcall.c

225

return __SHIFTOUT(flags, XC_IPL_MASK);

sys/kern/sys_futex.c

1441

return arg - 0x1000*__SHIFTOUT(arg, __BIT(11));

sys/kern/sys_futex.c

1452

int op = __SHIFTOUT(opcmp, FUTEX_OP_OP_MASK);

sys/kern/sys_futex.c

1453

int cmp = __SHIFTOUT(opcmp, FUTEX_OP_CMP_MASK);

sys/kern/sys_futex.c

1457

futex_opcmp_arg(__SHIFTOUT(opcmp, FUTEX_OP_OPARG_MASK));

sys/kern/sys_futex.c

1499

int op = __SHIFTOUT(opcmp, FUTEX_OP_OP_MASK);

sys/kern/sys_futex.c

1500

int oparg = futex_opcmp_arg(__SHIFTOUT(opcmp, FUTEX_OP_OPARG_MASK));

sys/kern/sys_futex.c

1543

int cmp = __SHIFTOUT(opcmp, FUTEX_OP_CMP_MASK);

sys/kern/sys_futex.c

1544

int cmparg = futex_opcmp_arg(__SHIFTOUT(opcmp, FUTEX_OP_CMPARG_MASK));

sys/stand/efiboot/bootaa64/efibootaa64.c

86

return __SHIFTOUT(id_aa64mmfr0_el1, __BITS(11, 8)) == 1;

sys/sys/agpio.h

46

#define AGP_MODE_GET_RQ(x) __SHIFTOUT((x), AGP_MODE_RQ)

sys/sys/agpio.h

47

#define AGP_MODE_GET_ARQSZ(x) __SHIFTOUT((x), AGP_MODE_ARQSZ)

sys/sys/agpio.h

48

#define AGP_MODE_GET_CAL(x) __SHIFTOUT((x), AGP_MODE_CAL)

sys/sys/agpio.h

49

#define AGP_MODE_GET_SBA(x) __SHIFTOUT((x), AGP_MODE_SBA)

sys/sys/agpio.h

50

#define AGP_MODE_GET_AGP(x) __SHIFTOUT((x), AGP_MODE_AGP)

sys/sys/agpio.h

51

#define AGP_MODE_GET_4G(x) __SHIFTOUT((x), AGP_MODE_4G)

sys/sys/agpio.h

52

#define AGP_MODE_GET_FW(x) __SHIFTOUT((x), AGP_MODE_FW)

sys/sys/agpio.h

53

#define AGP_MODE_GET_MODE_3(x) __SHIFTOUT((x), AGP_MODE_MODE_3)

sys/sys/agpio.h

54

#define AGP_MODE_GET_RATE(x) __SHIFTOUT((x), AGP_MODE_RATE)

sys/sys/bus.h

253

#define BUS_ADDR_HI32(a) ((uint32_t) __SHIFTOUT(a, __BITS(32,63)))

sys/sys/bus.h

254

#define BUS_ADDR_LO32(a) ((uint32_t) __SHIFTOUT(a, __BITS(0,31)))

sys/sys/cdefs.h

685

#define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask))

sys/uvm/uvm_page.h

449

unsigned fl = __SHIFTOUT(pg->phys_addr, UVM_PHYSADDR_FREELIST);

sys/uvm/uvm_page.h

457

return __SHIFTOUT(pg->phys_addr, UVM_PHYSADDR_BUCKET);

tests/kernel/arch/x86/sig_fpu.c

144

if (__SHIFTOUT(rcpc_exc, X87_CW_PC) == 1) /* reserved */

usr.sbin/acpitools/acpidump/acpi.c

2277

httuo = __SHIFTOUT(smmu->Flags, ACPI_IORT_SMMU_V3_HTTU_OVERRIDE);

usr.sbin/btconfig/btconfig.c

1008

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

1019

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

901

switch(__SHIFTOUT(class, __BITS(0, 1))) {

usr.sbin/btconfig/btconfig.c

913

switch (__SHIFTOUT(class, __BITS(8, 12))) {

usr.sbin/btconfig/btconfig.c

915

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

927

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

939

switch (__SHIFTOUT(class, __BITS(5, 7))) {

usr.sbin/btconfig/btconfig.c

952

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/btconfig/btconfig.c

974

switch (__SHIFTOUT(class, __BITS(2, 5))) {

usr.sbin/btconfig/btconfig.c

997

switch (__SHIFTOUT(class, __BITS(2, 7))) {

usr.sbin/cpuctl/arch/aarch64.c

1051

variant = __SHIFTOUT(cpuid, CPU_ID_VARIANT_MASK);

usr.sbin/cpuctl/arch/aarch64.c

1052

revision = __SHIFTOUT(cpuid, CPU_ID_REVISION_MASK);

usr.sbin/cpuctl/arch/aarch64.c

1093

__SHIFTOUT(mpidr, MPIDR_AFF3),

usr.sbin/cpuctl/arch/aarch64.c

1094

__SHIFTOUT(mpidr, MPIDR_AFF2),

usr.sbin/cpuctl/arch/aarch64.c

1095

__SHIFTOUT(mpidr, MPIDR_AFF1),

usr.sbin/cpuctl/arch/aarch64.c

1096

__SHIFTOUT(mpidr, MPIDR_AFF0));

usr.sbin/cpuctl/arch/aarch64.c

1117

cpuname, setname, __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_CTX_CMPS) + 1);

usr.sbin/cpuctl/arch/aarch64.c

1119

cpuname, setname, __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_WRPS) + 1);

usr.sbin/cpuctl/arch/aarch64.c

1121

cpuname, setname, __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_BRPS) + 1);

usr.sbin/cpuctl/arch/i386.c

1035

type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE);

usr.sbin/cpuctl/arch/i386.c

1038

level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL);

usr.sbin/cpuctl/arch/i386.c

1039

pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE);

usr.sbin/cpuctl/arch/i386.c

1168

ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);

usr.sbin/cpuctl/arch/i386.c

1595

ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX);

usr.sbin/cpuctl/arch/i386.c

1597

ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID);

usr.sbin/cpuctl/arch/i386.c

1784

lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);

usr.sbin/cpuctl/arch/i386.c

1787

core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1;

usr.sbin/cpuctl/arch/i386.c

1798

ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid,

usr.sbin/cpuctl/arch/i386.c

1802

ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid,

usr.sbin/cpuctl/arch/i386.c

1828

shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM);

usr.sbin/cpuctl/arch/i386.c

1829

lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE);

usr.sbin/cpuctl/arch/i386.c

1854

ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid,

usr.sbin/cpuctl/arch/i386.c

1858

ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid,

usr.sbin/cpuctl/arch/i386.c

1894

lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);

usr.sbin/cpuctl/arch/i386.c

1937

ci->ci_coreid = __SHIFTOUT(apic_id, core_mask);

usr.sbin/cpuctl/arch/i386.c

1941

ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask);

usr.sbin/cpuctl/arch/i386.c

2211

lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE);

usr.sbin/cpuctl/arch/i386.c

2212

lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE);

usr.sbin/cpuctl/arch/i386.c

2308

ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC);

usr.sbin/cpuctl/arch/i386.c

2309

nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC);

usr.sbin/cpuctl/arch/i386.c

2310

numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC);

usr.sbin/cpuctl/arch/i386.c

2311

nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK);

usr.sbin/cpuctl/arch/i386.c

2322

classes = __SHIFTOUT(descs[0], CPUID_HWC_NWC);

usr.sbin/cpuctl/arch/i386.c

2331

pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION);

usr.sbin/cpuctl/arch/i386.c

2332

ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC);

usr.sbin/cpuctl/arch/i386.c

2333

veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN);

usr.sbin/cpuctl/arch/i386.c

2345

(uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC),

usr.sbin/cpuctl/arch/i386.c

2358

ncounter = __SHIFTOUT(descs[3],

usr.sbin/cpuctl/arch/i386.c

2362

(uint32_t)__SHIFTOUT(descs[3],

usr.sbin/cpuctl/arch/i386.c

2377

(uint8_t)__SHIFTOUT(descs[0],

usr.sbin/cpuctl/arch/i386.c

2379

(uint32_t)__SHIFTOUT(descs[0],

usr.sbin/tprof/arch/tprof_x86.c

113

vectorlen = __SHIFTOUT(eax, CPUID_PERF_BVECLEN);

usr.sbin/tprof/tprof_analyze.c

251

c = __SHIFTOUT(sample.s_flags, TPROF_SAMPLE_COUNTER_MASK);

usr.sbin/tprof/tprof_top.c

477

eventid = __SHIFTOUT(s->s_flags, TPROF_SAMPLE_COUNTER_MASK);