bin/chio/chio.c
161
int val;
bin/chio/chio.c
211
val = parse_special(*argv);
bin/chio/chio.c
212
switch (val) {
bin/chio/chio.c
240
int val;
bin/chio/chio.c
299
val = parse_special(*argv);
bin/chio/chio.c
301
switch (val) {
bin/chio/chio.c
334
int val;
bin/chio/chio.c
365
val = parse_special(*argv);
bin/chio/chio.c
366
switch (val) {
bin/chio/chio.c
818
int val;
bin/chio/chio.c
820
val = is_special(cp);
bin/chio/chio.c
821
if (val)
bin/chio/chio.c
822
return (val);
bin/chmod/chmod.c
161
val = strtoul(flags, &ep, 8);
bin/chmod/chmod.c
162
if (val > UINT_MAX)
bin/chmod/chmod.c
168
fset = val;
bin/chmod/chmod.c
180
val = strtoul(mode, &ep, 8);
bin/chmod/chmod.c
181
if (val > INT_MAX)
bin/chmod/chmod.c
187
omode = val;
bin/chmod/chmod.c
61
unsigned long val;
bin/csh/func.c
939
Setenv(Char *name, Char *val)
bin/csh/func.c
951
cp = Strspl(STRequal, val);
bin/csh/func.c
960
blk[0] = strip(Strspl(cp, val));
bin/csh/set.c
400
set(Char *var, Char *val)
bin/csh/set.c
404
vec[0] = val;
bin/csh/set.c
564
exportpath(Char **val)
bin/csh/set.c
569
if (val)
bin/csh/set.c
570
while (*val) {
bin/csh/set.c
571
if (Strlen(*val) + Strlen(exppath) + 2 > BUFSIZ) {
bin/csh/set.c
576
(void) Strlcat(exppath, *val++, sizeof exppath/sizeof(Char));
bin/csh/set.c
577
if (*val == 0 || eq(*val, STRRparen))
bin/dd/args.c
323
get_bsz(char *val)
bin/dd/args.c
328
if (strchr(val, '-'))
bin/dd/args.c
332
num = strtoul(val, &expr, 0);
bin/dd/args.c
335
if (expr == val) /* No digits. */
bin/dd/args.c
406
get_off(char *val)
bin/dd/args.c
412
num = strtoll(val, &expr, 0);
bin/dd/args.c
415
if (expr == val) /* No digits. */
bin/df/ext2fs_df.c
95
sfsp->f_fsid.val[0] = 0;
bin/df/ext2fs_df.c
96
sfsp->f_fsid.val[1] = 0;
bin/df/ffs_df.c
87
sfsp->f_fsid.val[0] = 0;
bin/df/ffs_df.c
88
sfsp->f_fsid.val[1] = 0;
bin/expr/expr.c
122
to_integer(struct val *vp, const char **errstr)
bin/expr/expr.c
145
to_string(struct val *vp)
bin/expr/expr.c
160
is_zero_or_null(struct val *vp)
bin/expr/expr.c
19
struct val *make_int(int64_t);
bin/expr/expr.c
20
struct val *make_str(char *);
bin/expr/expr.c
21
void free_value(struct val *);
bin/expr/expr.c
214
struct val *
bin/expr/expr.c
217
struct val *v;
bin/expr/expr.c
22
int is_integer(struct val *, int64_t *, const char **);
bin/expr/expr.c
23
int to_integer(struct val *, const char **);
bin/expr/expr.c
234
struct val *
bin/expr/expr.c
24
void to_string(struct val *);
bin/expr/expr.c
241
struct val *l, *r;
bin/expr/expr.c
242
struct val *v;
bin/expr/expr.c
25
int is_zero_or_null(struct val *);
bin/expr/expr.c
28
struct val *eval6(void);
bin/expr/expr.c
289
struct val *
bin/expr/expr.c
29
struct val *eval5(void);
bin/expr/expr.c
293
struct val *l, *r;
bin/expr/expr.c
30
struct val *eval4(void);
bin/expr/expr.c
31
struct val *eval3(void);
bin/expr/expr.c
32
struct val *eval2(void);
bin/expr/expr.c
33
struct val *eval1(void);
bin/expr/expr.c
336
struct val *
bin/expr/expr.c
34
struct val *eval0(void);
bin/expr/expr.c
340
struct val *l, *r;
bin/expr/expr.c
375
struct val *
bin/expr/expr.c
378
struct val *l, *r;
bin/expr/expr.c
448
struct val *
bin/expr/expr.c
451
struct val *l, *r;
bin/expr/expr.c
471
struct val *
bin/expr/expr.c
474
struct val *l, *r;
bin/expr/expr.c
496
struct val *vp;
bin/expr/expr.c
54
struct val *tokval;
bin/expr/expr.c
57
struct val *
bin/expr/expr.c
60
struct val *vp;
bin/expr/expr.c
72
struct val *
bin/expr/expr.c
75
struct val *vp;
bin/expr/expr.c
87
free_value(struct val *vp)
bin/expr/expr.c
97
is_integer(struct val *vp, int64_t *r, const char **errstr)
bin/ksh/c_ksh.c
1019
afree(ap->val.s, APERM);
bin/ksh/c_ksh.c
1030
afree(ap->val.s, APERM);
bin/ksh/c_ksh.c
1043
int64_t val;
bin/ksh/c_ksh.c
1049
if (!evaluate(*wp, &val, KSH_RETURN_ERROR, true)) {
bin/ksh/c_ksh.c
1053
rv = val == 0;
bin/ksh/c_ksh.c
1258
getopts_reset(int val)
bin/ksh/c_ksh.c
1260
if (val >= 1) {
bin/ksh/c_ksh.c
1263
user_opt.optind = user_opt.uoptind = val;
bin/ksh/c_ksh.c
489
print_value_quoted(tp->val.s);
bin/ksh/c_ksh.c
522
shprintf("%s", tp->val.s);
bin/ksh/c_ksh.c
724
"%s() %T\n", wp[i], f->val.t);
bin/ksh/c_ksh.c
743
vp->name, vp->val.t);
bin/ksh/c_ksh.c
925
print_value_quoted(ap->val.s);
bin/ksh/c_ksh.c
933
char *val = strchr(alias, '=');
bin/ksh/c_ksh.c
938
if (val)
bin/ksh/c_ksh.c
939
alias = str_nsave(alias, val++ - alias, ATEMP);
bin/ksh/c_ksh.c
941
if (val == NULL && !tflag && !xflag) {
bin/ksh/c_ksh.c
949
print_value_quoted(ap->val.s);
bin/ksh/c_ksh.c
961
if ((val && !tflag) || (!val && tflag && !Uflag)) {
bin/ksh/c_ksh.c
964
afree(ap->val.s, APERM);
bin/ksh/c_ksh.c
968
: val;
bin/ksh/c_ksh.c
970
ap->val.s = str_save(newval, APERM);
bin/ksh/c_ksh.c
980
if (val)
bin/ksh/c_sh.c
36
int64_t val;
bin/ksh/c_sh.c
44
evaluate(arg, &val, KSH_UNWIND_ERROR, false);
bin/ksh/c_sh.c
45
n = val;
bin/ksh/c_ulimit.c
137
rlim_t val = 0;
bin/ksh/c_ulimit.c
141
val = RLIM_INFINITY;
bin/ksh/c_ulimit.c
157
val = (rlim_t)rval * l->factor;
bin/ksh/c_ulimit.c
162
limit.rlim_cur = val;
bin/ksh/c_ulimit.c
164
limit.rlim_max = val;
bin/ksh/c_ulimit.c
179
rlim_t val = 0;
bin/ksh/c_ulimit.c
184
val = limit.rlim_cur;
bin/ksh/c_ulimit.c
186
val = limit.rlim_max;
bin/ksh/c_ulimit.c
187
if (val == RLIM_INFINITY)
bin/ksh/c_ulimit.c
190
val /= l->factor;
bin/ksh/c_ulimit.c
191
shprintf("%" PRIi64 "\n", (int64_t) val);
bin/ksh/edit.c
429
dp = tp->val.s;
bin/ksh/edit.c
646
afree(tp->val.s, APERM);
bin/ksh/eval.c
1255
ap->val.s = str_save(pw->pw_dir, APERM);
bin/ksh/eval.c
1258
return ap->val.s;
bin/ksh/exec.c
1034
rv = (*tp->val.f)(wp);
bin/ksh/exec.c
1167
else if (tp && tp->type == CSHELL && tp->val.f == c_exec) {
bin/ksh/exec.c
121
if (tp && tp->val.f != c_exec &&
bin/ksh/exec.c
448
if (tp->val.f == c_builtin) {
bin/ksh/exec.c
457
} else if (tp->val.f == c_exec) {
bin/ksh/exec.c
462
} else if (tp->val.f == c_command) {
bin/ksh/exec.c
618
exstat = execute(tp->val.t, flags & XERROK, xerrok);
bin/ksh/exec.c
631
tfree(tp->val.t, tp->areap);
bin/ksh/exec.c
677
tp->val.s, KSH_RETURN_ERROR);
bin/ksh/exec.c
692
texec.str = tp->val.s;
bin/ksh/exec.c
754
tp->val.t = NULL;
bin/ksh/exec.c
789
tfree(tp->val.t, tp->areap);
bin/ksh/exec.c
797
tp->val.t = tcopy(t->left, tp->areap);
bin/ksh/exec.c
829
tp->val.f = func;
bin/ksh/exec.c
883
if (tp && (tp->flag & ISSET) && access(tp->val.s, X_OK) != 0) {
bin/ksh/exec.c
886
afree(tp->val.s, APERM);
bin/ksh/exec.c
909
tp->val.s = npath;
bin/ksh/exec.c
911
tp->val.s = str_save(npath, APERM);
bin/ksh/exec.c
944
if ((tp->flag&ISSET) && (all || tp->val.s[0] != '/')) {
bin/ksh/exec.c
947
afree(tp->val.s, APERM);
bin/ksh/expr.c
127
struct tbl *val; /* value from token() */
bin/ksh/expr.c
159
*rval = v.val.i;
bin/ksh/expr.c
181
curstate.val = NULL;
bin/ksh/expr.c
205
es->val = tempvar();
bin/ksh/expr.c
235
s = es->val->name;
bin/ksh/expr.c
238
s = str_val(es->val);
bin/ksh/expr.c
295
vl->val.i = ~vl->val.i;
bin/ksh/expr.c
297
vl->val.i = !vl->val.i;
bin/ksh/expr.c
299
vl->val.i = -vl->val.i;
bin/ksh/expr.c
309
vl = do_ppmm(es, op, es->val, true);
bin/ksh/expr.c
312
vl = es->val;
bin/ksh/expr.c
337
op == O_MODASN) && vr->val.i == 0) {
bin/ksh/expr.c
339
vr->val.i = 1;
bin/ksh/expr.c
346
res = vl->val.i * vr->val.i;
bin/ksh/expr.c
350
if (vl->val.i == LONG_MIN && vr->val.i == -1)
bin/ksh/expr.c
353
res = vl->val.i / vr->val.i;
bin/ksh/expr.c
357
if (vl->val.i == LONG_MIN && vr->val.i == -1)
bin/ksh/expr.c
360
res = vl->val.i % vr->val.i;
bin/ksh/expr.c
364
res = vl->val.i + vr->val.i;
bin/ksh/expr.c
368
res = vl->val.i - vr->val.i;
bin/ksh/expr.c
372
res = vl->val.i << vr->val.i;
bin/ksh/expr.c
376
res = vl->val.i >> vr->val.i;
bin/ksh/expr.c
379
res = vl->val.i < vr->val.i;
bin/ksh/expr.c
382
res = vl->val.i <= vr->val.i;
bin/ksh/expr.c
385
res = vl->val.i > vr->val.i;
bin/ksh/expr.c
388
res = vl->val.i >= vr->val.i;
bin/ksh/expr.c
391
res = vl->val.i == vr->val.i;
bin/ksh/expr.c
394
res = vl->val.i != vr->val.i;
bin/ksh/expr.c
398
res = vl->val.i & vr->val.i;
bin/ksh/expr.c
402
res = vl->val.i ^ vr->val.i;
bin/ksh/expr.c
406
res = vl->val.i | vr->val.i;
bin/ksh/expr.c
409
if (!vl->val.i)
bin/ksh/expr.c
412
res = vl->val.i && vr->val.i;
bin/ksh/expr.c
413
if (!vl->val.i)
bin/ksh/expr.c
417
if (vl->val.i)
bin/ksh/expr.c
420
res = vl->val.i || vr->val.i;
bin/ksh/expr.c
421
if (vl->val.i)
bin/ksh/expr.c
426
int e = vl->val.i != 0;
bin/ksh/expr.c
445
res = vr->val.i;
bin/ksh/expr.c
448
res = vr->val.i;
bin/ksh/expr.c
452
vr->val.i = res;
bin/ksh/expr.c
459
vl->val.i = res;
bin/ksh/expr.c
496
es->val = tempvar();
bin/ksh/expr.c
497
es->val->flag |= EXPRLVALUE;
bin/ksh/expr.c
500
es->val = global(tvar);
bin/ksh/expr.c
508
es->val = tempvar();
bin/ksh/expr.c
509
es->val->flag &= ~INTEGER;
bin/ksh/expr.c
510
es->val->type = 0;
bin/ksh/expr.c
511
es->val->val.s = tvar;
bin/ksh/expr.c
512
if (setint_v(es->val, es->val, es->arith) == NULL)
bin/ksh/expr.c
542
oval = op == O_PLUSPLUS ? vl->val.i++ : vl->val.i--;
bin/ksh/expr.c
546
setint(vasn, vl->val.i);
bin/ksh/expr.c
548
vl->val.i = oval;
bin/ksh/expr.c
572
vp->val.i = 0;
bin/ksh/lex.c
1018
} else if (*s->u.tblp->val.s &&
bin/ksh/lex.c
1019
isspace((unsigned char)strchr(s->u.tblp->val.s, 0)[-1])) {
bin/ksh/lex.c
831
(!(cf & ESACONLY) || p->val.i == ESAC || p->val.i == '}')) {
bin/ksh/lex.c
833
return p->val.i;
bin/ksh/lex.c
844
s->start = s->str = p->val.s;
bin/ksh/syn.c
629
short val;
bin/ksh/syn.c
676
p->val.i = tt->val;
bin/ksh/syn.c
716
if (tt->val == c)
bin/ksh/table.h
25
} val; /* value */
bin/ksh/var.c
1064
ksh_tmout = vp->val.i >= 0 ? vp->val.i : 0;
bin/ksh/var.c
1133
arraysearch(struct tbl *vp, int val)
bin/ksh/var.c
1141
if (val == 0)
bin/ksh/var.c
1145
while (curr && curr->index < val) {
bin/ksh/var.c
1149
if (curr && curr->index == val) {
bin/ksh/var.c
1162
new->index = val;
bin/ksh/var.c
177
int val;
bin/ksh/var.c
180
n = array_index_calc(n, &array, &val);
bin/ksh/var.c
206
vp->val.i = kshpid;
bin/ksh/var.c
210
if ((vp->val.i = j_async()) == 0)
bin/ksh/var.c
214
vp->val.i = exstat;
bin/ksh/var.c
217
vp->val.i = l->argc;
bin/ksh/var.c
221
vp->val.s = getoptions();
bin/ksh/var.c
232
return arraysearch(vp, val);
bin/ksh/var.c
241
vp = arraysearch(vp, val);
bin/ksh/var.c
258
int val;
bin/ksh/var.c
261
n = array_index_calc(n, &array, &val);
bin/ksh/var.c
287
vp = arraysearch(vp, val);
bin/ksh/var.c
305
s = vp->val.s + vp->type;
bin/ksh/var.c
318
n = (uint64_t) vp->val.i;
bin/ksh/var.c
320
n = (vp->val.i < 0) ? -vp->val.i : vp->val.i;
bin/ksh/var.c
336
if (!(vp->flag & INT_U) && vp->val.i < 0)
bin/ksh/var.c
376
if (s >= vq->val.s &&
bin/ksh/var.c
377
s <= vq->val.s + strlen(vq->val.s))
bin/ksh/var.c
380
afree(vq->val.s, vq->areap);
bin/ksh/var.c
389
vq->val.s = str_save(s, vq->areap);
bin/ksh/var.c
412
vp->val.i = n;
bin/ksh/var.c
416
vq->val.i = n;
bin/ksh/var.c
434
if (!(vp->flag&ISSET) || (!(vp->flag&INTEGER) && vp->val.s == NULL))
bin/ksh/var.c
437
*nump = vp->val.i;
bin/ksh/var.c
440
s = vp->val.s + vp->type;
bin/ksh/var.c
501
afree(vq->val.s, vq->areap);
bin/ksh/var.c
503
vq->val.i = num;
bin/ksh/var.c
575
export(struct tbl *vp, const char *val)
bin/ksh/var.c
578
char *op = (vp->flag&ALLOC) ? vp->val.s : NULL;
bin/ksh/var.c
580
int vallen = strlen(val) + 1;
bin/ksh/var.c
584
memcpy(vp->val.s = xp, vp->name, namelen);
bin/ksh/var.c
587
vp->type = xp - vp->val.s; /* offset to value */
bin/ksh/var.c
588
memcpy(xp, val, vallen);
bin/ksh/var.c
603
const char *val;
bin/ksh/var.c
606
val = skip_varname(var, false);
bin/ksh/var.c
607
if (val == var)
bin/ksh/var.c
609
if (*val == '[') {
bin/ksh/var.c
612
len = array_ref_len(val);
bin/ksh/var.c
624
if (!digit(val[i]))
bin/ksh/var.c
627
val += len;
bin/ksh/var.c
629
if (*val == '=')
bin/ksh/var.c
630
tvar = str_nsave(var, val++ - var, ATEMP);
bin/ksh/var.c
636
val = NULL;
bin/ksh/var.c
655
(val || clr || (set & ~EXPORT)))
bin/ksh/var.c
658
if (val)
bin/ksh/var.c
673
fake_assign = (t->flag & ISSET) && (!val || t != vp) &&
bin/ksh/var.c
682
s = t->val.s + t->type;
bin/ksh/var.c
683
free_me = (t->flag & ALLOC) ? t->val.s :
bin/ksh/var.c
700
if ((set & INTEGER) && base > 0 && (!val || t != vp))
bin/ksh/var.c
715
afree(t->val.s, t->areap);
bin/ksh/var.c
727
if (val != NULL) {
bin/ksh/var.c
730
setstr(vp, val, KSH_UNWIND_ERROR | KSH_IGNORE_RDONLY);
bin/ksh/var.c
736
setstr(vp, val, KSH_RETURN_ERROR | KSH_IGNORE_RDONLY);
bin/ksh/var.c
742
export(vpbase, (vpbase->flag&ISSET) ? vpbase->val.s : null);
bin/ksh/var.c
754
afree(vp->val.s, vp->areap);
bin/ksh/var.c
763
afree(tmp->val.s, tmp->areap);
bin/ksh/var.c
870
char *val;
bin/ksh/var.c
871
val = str_val(vp);
bin/ksh/var.c
874
setstr(vp, val, KSH_RETURN_ERROR);
bin/ksh/var.c
876
XPput(env, vp->val.s);
bin/ksh/vi.c
749
nlen = strlen(ap->val.s) + 1;
bin/ksh/vi.c
753
memcpy(nbuf, ap->val.s, nlen);
bin/pax/cpio.c
272
unsigned long long val;
bin/pax/cpio.c
295
val = asc_ull(hd->c_mtime, sizeof(hd->c_mtime), OCT);
bin/pax/cpio.c
296
if (val > MAX_TIME_T)
bin/pax/cpio.c
299
arcn->sb.st_mtime = val;
bin/pax/cpio.h
111
#define CHR_WR_0(val) ((char)(((val) >> 24) & 0xff))
bin/pax/cpio.h
112
#define CHR_WR_1(val) ((char)(((val) >> 16) & 0xff))
bin/pax/cpio.h
113
#define CHR_WR_2(val) ((char)(((val) >> 8) & 0xff))
bin/pax/cpio.h
114
#define CHR_WR_3(val) ((char)((val) & 0xff))
bin/pax/gen_subs.c
242
ul_asc(u_long val, char *str, int len, int base)
bin/pax/gen_subs.c
259
if ((digit = (val & 0xf)) < 10)
bin/pax/gen_subs.c
263
val >>= 4;
bin/pax/gen_subs.c
264
if (val == 0)
bin/pax/gen_subs.c
269
*pt-- = '0' + (char)(val & 0x7);
bin/pax/gen_subs.c
270
val >>= 3;
bin/pax/gen_subs.c
271
if (val == 0)
bin/pax/gen_subs.c
281
if (val != 0)
bin/pax/gen_subs.c
340
ull_asc(unsigned long long val, char *str, int len, int base)
bin/pax/gen_subs.c
357
if ((digit = (val & 0xf)) < 10)
bin/pax/gen_subs.c
361
val >>= 4;
bin/pax/gen_subs.c
362
if (val == 0)
bin/pax/gen_subs.c
367
*pt-- = '0' + (char)(val & 0x7);
bin/pax/gen_subs.c
368
val >>= 3;
bin/pax/gen_subs.c
369
if (val == 0)
bin/pax/gen_subs.c
379
if (val != 0)
bin/pax/options.c
1607
str_offt(char *val)
bin/pax/options.c
1612
num = strtoll(val, &expr, 0);
bin/pax/options.c
1613
if ((num == LLONG_MAX) || (num <= 0) || (expr == val))
bin/pax/tables.c
1738
u_int val;
bin/pax/tables.c
1765
dest = (char *)&val;
bin/pax/tables.c
1768
key += val;
bin/pax/tables.c
1775
val = 0;
bin/pax/tables.c
1777
dest = (char *)&val;
bin/pax/tables.c
1780
key += val;
bin/pax/tar.c
173
ul_oct(u_long val, char *str, int len, int term)
bin/pax/tar.c
203
*pt-- = '0' + (char)(val & 0x7);
bin/pax/tar.c
204
val >>= 3;
bin/pax/tar.c
205
if (val == 0)
bin/pax/tar.c
211
if (val != 0)
bin/pax/tar.c
228
ull_oct(unsigned long long val, char *str, int len, int term)
bin/pax/tar.c
258
*pt-- = '0' + (char)(val & 0x7);
bin/pax/tar.c
259
val >>= 3;
bin/pax/tar.c
260
if (val == 0)
bin/pax/tar.c
266
if (val != 0)
bin/pax/tar.c
398
unsigned long long val;
bin/pax/tar.c
425
val = asc_ull(hd->mtime, sizeof(hd->mtime), OCT);
bin/pax/tar.c
426
if (val > MAX_TIME_T)
bin/pax/tar.c
429
arcn->sb.st_mtime = val;
bin/pax/tar.c
730
unsigned long long val;
bin/pax/tar.c
802
val = asc_ull(hd->mtime, sizeof(hd->mtime), OCT);
bin/pax/tar.c
803
if (val > MAX_TIME_T)
bin/pax/tar.c
806
arcn->sb.st_mtime = val;
bin/stty/cchar.c
115
val = strtol(arg, &ep, 10);
bin/stty/cchar.c
116
if (val > UCHAR_MAX || val < 0) {
bin/stty/cchar.c
125
ip->t.c_cc[cp->sub] = val;
bin/stty/cchar.c
92
long val;
distrib/special/more/more.c
875
#define ret(val) retval=val;done++;break
games/adventure/hdr.h
83
int val; /* word type &index (ktab) */
games/adventure/vocab.c
150
if (h->val) /* already got an entry? */
games/adventure/vocab.c
152
h->val = value;
games/adventure/vocab.c
163
if (h->val == 0)
games/adventure/vocab.c
171
return (h->val);
games/adventure/vocab.c
173
if (h->val == 0)
games/adventure/vocab.c
179
if (h->val / 1000 != type)
games/adventure/vocab.c
181
return (h->val%1000);
games/adventure/vocab.c
204
if (h->val == 0) {
games/backgammon/common_source/odds.c
35
odds(int r1, int r2, int val)
games/backgammon/common_source/odds.c
48
table[i][r1] += val;
games/backgammon/common_source/odds.c
49
table[r1][i] += val;
games/backgammon/common_source/odds.c
52
table[r2][r1] += val;
games/backgammon/common_source/odds.c
53
table[r1][r2] += val;
games/bcd/bcd.c
279
unsigned int val = 0;
games/bcd/bcd.c
282
val |= 1 << (11 - i);
games/bcd/bcd.c
285
if (holes[i] == val && holes[i]) {
games/factor/factor.c
117
val = strtoull(buf, &p, 10);
games/factor/factor.c
124
pr_fact(val);
games/factor/factor.c
132
val = strtoull(argv[0], &p, 10);
games/factor/factor.c
137
pr_fact(val);
games/factor/factor.c
156
pr_fact(u_int64_t val) /* Factor this value. */
games/factor/factor.c
161
if (val == 0) /* Historical practice; 0 just exits. */
games/factor/factor.c
163
if (val == 1) {
games/factor/factor.c
169
(void)printf("%llu:", val);
games/factor/factor.c
171
for (fact = &prime[0]; val > 1; ++fact) {
games/factor/factor.c
174
if (val % (long)*fact == 0)
games/factor/factor.c
180
if (val > BIG)
games/factor/factor.c
181
pr_bigfact(val);
games/factor/factor.c
183
(void)printf(" %llu", val);
games/factor/factor.c
190
val /= (long)*fact;
games/factor/factor.c
191
} while ((val % (long)*fact) == 0);
games/factor/factor.c
205
pr_bigfact(u_int64_t val) /* Factor this value. */
games/factor/factor.c
216
stop = usqrt(val) + 1;
games/factor/factor.c
269
if (val % start == 0) {
games/factor/factor.c
272
val /= start;
games/factor/factor.c
273
} while ((val % start) == 0);
games/factor/factor.c
275
stop = usqrt(val) + 1;
games/factor/factor.c
282
if (val > 1)
games/factor/factor.c
283
printf(" %llu", val);
games/factor/factor.c
84
u_int64_t val;
games/gomoku/makemove.c
104
val = weight[5 - cp->c.a - cp->c.b];
games/gomoku/makemove.c
106
val = 0;
games/gomoku/makemove.c
109
val += weight[5 - cp->c.a - cp->c.b];
games/gomoku/makemove.c
119
sp->s_wval -= val;
games/gomoku/makemove.c
128
sp->s_wval -= val;
games/gomoku/makemove.c
149
val = weight[n];
games/gomoku/makemove.c
153
sp->s_wval += val;
games/gomoku/makemove.c
60
int space, val, bmask;
games/monop/prop.c
58
int val;
games/monop/prop.c
65
val = value(op->sqr);
games/monop/prop.c
67
for (tp = *head; tp && value(tp->sqr) < val; tp = tp->next)
games/monop/prop.c
68
if (val == value(tp->sqr)) {
games/number/number.c
273
int val, rval;
games/number/number.c
285
val = (p[1] - '0') + (p[0] - '0') * 10;
games/number/number.c
286
if (val) {
games/number/number.c
289
if (val < 20)
games/number/number.c
290
(void)printf("%s", name1[val]);
games/number/number.c
292
(void)printf("%s", name2[val / 10]);
games/number/number.c
293
if (val % 10)
games/number/number.c
294
(void)printf("-%s", name1[val % 10]);
games/primes/primes.c
150
ubig val;
games/primes/primes.c
164
val = strtonum(buf, 0, BIG, &errstr);
games/primes/primes.c
167
return (val);
include/getopt.h
56
int val;
include/rpcsvc/yp_prot.h
151
struct ypresp_key_val val;
lib/libarch/alpha/bwx.c
156
bwx_outb(u_int32_t port, u_int8_t val)
lib/libarch/alpha/bwx.c
158
alpha_stb(bwx_int1_ports + port, val);
lib/libarch/alpha/bwx.c
164
bwx_outw(u_int32_t port, u_int16_t val)
lib/libarch/alpha/bwx.c
166
alpha_stw(bwx_int2_ports + port, val);
lib/libarch/alpha/bwx.c
172
bwx_outl(u_int32_t port, u_int32_t val)
lib/libarch/alpha/bwx.c
174
alpha_stl(bwx_int4_ports + port, val);
lib/libarch/alpha/bwx.c
259
bwx_writeb(void *handle, u_int32_t offset, u_int8_t val)
lib/libarch/alpha/bwx.c
263
alpha_stb(h->virt1 + offset, val);
lib/libarch/alpha/bwx.c
267
bwx_writew(void *handle, u_int32_t offset, u_int16_t val)
lib/libarch/alpha/bwx.c
271
alpha_stw(h->virt2 + offset, val);
lib/libarch/alpha/bwx.c
275
bwx_writel(void *handle, u_int32_t offset, u_int32_t val)
lib/libarch/alpha/bwx.c
279
alpha_stl(h->virt4 + offset, val);
lib/libarch/alpha/io.c
130
writeb(void *handle, u_int32_t offset, u_int8_t val)
lib/libarch/alpha/io.c
132
ops->writeb(handle, offset, val);
lib/libarch/alpha/io.c
137
writew(void *handle, u_int32_t offset, u_int16_t val)
lib/libarch/alpha/io.c
139
ops->writew(handle, offset, val);
lib/libarch/alpha/io.c
144
writel(void *handle, u_int32_t offset, u_int32_t val)
lib/libarch/alpha/io.c
146
ops->writel(handle, offset, val);
lib/libarch/alpha/io.c
151
writeb_nb(void *handle, u_int32_t offset, u_int8_t val)
lib/libarch/alpha/io.c
153
ops->writeb(handle, offset, val);
lib/libarch/alpha/io.c
157
writew_nb(void *handle, u_int32_t offset, u_int16_t val)
lib/libarch/alpha/io.c
159
ops->writew(handle, offset, val);
lib/libarch/alpha/io.c
163
writel_nb(void *handle, u_int32_t offset, u_int32_t val)
lib/libarch/alpha/io.c
165
ops->writel(handle, offset, val);
lib/libarch/alpha/io.c
82
outb(u_int32_t port, u_int8_t val)
lib/libarch/alpha/io.c
84
ops->outb(port, val);
lib/libarch/alpha/io.c
88
outw(u_int32_t port, u_int16_t val)
lib/libarch/alpha/io.c
90
ops->outw(port, val);
lib/libarch/alpha/io.c
94
outl(u_int32_t port, u_int32_t val)
lib/libarch/alpha/io.c
96
ops->outl(port, val);
lib/libc/arch/aarch64/gen/usertc.c
24
uint64_t val;
lib/libc/arch/aarch64/gen/usertc.c
29
__asm volatile("mrs %x0, CNTVCT_EL0" : "=r" (val));
lib/libc/arch/aarch64/gen/usertc.c
31
if (((val + 1) & 0x1ff) > 1)
lib/libc/arch/aarch64/gen/usertc.c
35
return val;
lib/libc/arch/aarch64/gen/usertc.c
41
uint64_t val;
lib/libc/arch/aarch64/gen/usertc.c
48
__asm volatile("mrs %x0, CNTVCT_EL0" : "=r" (val));
lib/libc/arch/aarch64/gen/usertc.c
49
return (val & 0xffffffff);
lib/libc/arch/hppa/gen/fabs.c
11
fabs(double val)
lib/libc/arch/hppa/gen/fabs.c
14
__asm__ volatile("fabs,dbl %0,%0" : "+f" (val));
lib/libc/arch/hppa/gen/fabs.c
15
return (val);
lib/libc/crypt/arc4random.c
172
_rs_random_u32(uint32_t *val)
lib/libc/crypt/arc4random.c
176
_rs_stir_if_needed(sizeof(*val));
lib/libc/crypt/arc4random.c
177
if (rs->rs_have < sizeof(*val))
lib/libc/crypt/arc4random.c
180
memcpy(val, keystream, sizeof(*val));
lib/libc/crypt/arc4random.c
181
memset(keystream, 0, sizeof(*val));
lib/libc/crypt/arc4random.c
182
rs->rs_have -= sizeof(*val);
lib/libc/crypt/arc4random.c
188
uint32_t val;
lib/libc/crypt/arc4random.c
191
_rs_random_u32(&val);
lib/libc/crypt/arc4random.c
193
return val;
lib/libc/db/hash/hash.c
562
hash_access(HTAB *hashp, ACTION action, DBT *key, DBT *val)
lib/libc/db/hash/hash.c
640
if (__addel(hashp, rbufp, key, val)) {
lib/libc/db/hash/hash.c
662
if (__big_return(hashp, rbufp, ndx, val, 0))
lib/libc/db/hash/hash.c
665
val->data = (u_char *)rbufp->page + (int)bp[ndx + 1];
lib/libc/db/hash/hash.c
666
val->size = bp[ndx] - bp[ndx + 1];
lib/libc/db/hash/hash.c
671
(__addel(hashp, rbufp, key, val))) {
lib/libc/db/hash/hash_bigkey.c
126
if (space == val_size && val_size == val->size)
lib/libc/db/hash/hash_bigkey.c
154
if (space == val_size && val_size == val->size)
lib/libc/db/hash/hash_bigkey.c
354
__big_return(HTAB *hashp, BUFHEAD *bufp, int ndx, DBT *val, int set_current)
lib/libc/db/hash/hash_bigkey.c
399
val->data = (u_char *)tp + off;
lib/libc/db/hash/hash_bigkey.c
400
val->size = bp[1] - off;
lib/libc/db/hash/hash_bigkey.c
423
val->size = (size_t)collect_data(hashp, bufp, (int)len, set_current);
lib/libc/db/hash/hash_bigkey.c
424
if (val->size == (size_t)-1)
lib/libc/db/hash/hash_bigkey.c
432
val->data = (u_char *)hashp->tmp_buf;
lib/libc/db/hash/hash_bigkey.c
492
__big_keydata(HTAB *hashp, BUFHEAD *bufp, DBT *key, DBT *val, int set)
lib/libc/db/hash/hash_bigkey.c
494
key->size = (size_t)collect_key(hashp, bufp, 0, val, set);
lib/libc/db/hash/hash_bigkey.c
506
collect_key(HTAB *hashp, BUFHEAD *bufp, int len, DBT *val, int set)
lib/libc/db/hash/hash_bigkey.c
523
if (__big_return(hashp, bufp, 1, val, set))
lib/libc/db/hash/hash_bigkey.c
528
collect_key(hashp, xbp, totlen, val, set)) < 1))
lib/libc/db/hash/hash_bigkey.c
554
DBT key, val;
lib/libc/db/hash/hash_bigkey.c
561
if (__big_keydata(hashp, big_keyp, &key, &val, 0))
lib/libc/db/hash/hash_bigkey.c
82
__big_insert(HTAB *hashp, BUFHEAD *bufp, const DBT *key, const DBT *val)
lib/libc/db/hash/hash_bigkey.c
94
val_data = (char *)val->data;
lib/libc/db/hash/hash_bigkey.c
95
val_size = val->size;
lib/libc/db/hash/hash_page.c
102
off -= val->size;
lib/libc/db/hash/hash_page.c
103
memmove(p + off, val->data, val->size);
lib/libc/db/hash/hash_page.c
180
DBT key, val;
lib/libc/db/hash/hash_page.c
228
val.data = (u_char *)op + ino[n + 1];
lib/libc/db/hash/hash_page.c
229
val.size = ino[n] - ino[n + 1];
lib/libc/db/hash/hash_page.c
230
putpair(np, &key, &val);
lib/libc/db/hash/hash_page.c
282
DBT key, val;
lib/libc/db/hash/hash_page.c
344
val.data = (u_char *)cino + ino[n + 1];
lib/libc/db/hash/hash_page.c
345
val.size = ino[n] - ino[n + 1];
lib/libc/db/hash/hash_page.c
350
if (PAIRFITS(op, (&key), (&val)))
lib/libc/db/hash/hash_page.c
351
putpair((char *)op, &key, &val);
lib/libc/db/hash/hash_page.c
358
putpair((char *)op, &key, &val);
lib/libc/db/hash/hash_page.c
363
if (PAIRFITS(np, (&key), (&val)))
lib/libc/db/hash/hash_page.c
364
putpair((char *)np, &key, &val);
lib/libc/db/hash/hash_page.c
371
putpair((char *)np, &key, &val);
lib/libc/db/hash/hash_page.c
390
__addel(HTAB *hashp, BUFHEAD *bufp, const DBT *key, const DBT *val)
lib/libc/db/hash/hash_page.c
414
FREESPACE(bp) >= PAIRSIZE(key, val)) {
lib/libc/db/hash/hash_page.c
415
squeeze_key(bp, key, val);
lib/libc/db/hash/hash_page.c
425
if (PAIRFITS(bp, key, val))
lib/libc/db/hash/hash_page.c
426
putpair(bufp->page, key, val);
lib/libc/db/hash/hash_page.c
434
if (PAIRFITS(sop, key, val))
lib/libc/db/hash/hash_page.c
435
putpair((char *)sop, key, val);
lib/libc/db/hash/hash_page.c
437
if (__big_insert(hashp, bufp, key, val))
lib/libc/db/hash/hash_page.c
870
squeeze_key(u_int16_t *sp, const DBT *key, const DBT *val)
lib/libc/db/hash/hash_page.c
88
putpair(char *p, const DBT *key, const DBT *val)
lib/libc/db/hash/hash_page.c
884
off -= val->size;
lib/libc/db/hash/hash_page.c
886
memmove(p + off, val->data, val->size);
lib/libc/db/hash/hash_page.c
890
FREESPACE(sp) = free_space - PAIRSIZE(key, val);
lib/libc/gen/modf.c
45
modf(double val, double *iptr)
lib/libc/gen/modf.c
56
u.v = val;
lib/libc/gen/setproctitle.c
73
ps = (struct ps_strings *)_ps.val;
lib/libc/gen/statvfs.c
37
vfsp->f_fsid = fsp->f_fsid.val[0]; /* XXX */
lib/libc/net/inet_addr.c
109
val = (val * base) + (c - '0');
lib/libc/net/inet_addr.c
114
val = (val << 4) |
lib/libc/net/inet_addr.c
129
*pp++ = val;
lib/libc/net/inet_addr.c
154
if ((val > 0xffffff) || (parts[0] > 0xff))
lib/libc/net/inet_addr.c
156
val |= parts[0] << 24;
lib/libc/net/inet_addr.c
160
if ((val > 0xffff) || (parts[0] > 0xff) || (parts[1] > 0xff))
lib/libc/net/inet_addr.c
162
val |= (parts[0] << 24) | (parts[1] << 16);
lib/libc/net/inet_addr.c
166
if ((val > 0xff) || (parts[0] > 0xff) || (parts[1] > 0xff) || (parts[2] > 0xff))
lib/libc/net/inet_addr.c
168
val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
lib/libc/net/inet_addr.c
172
addr->s_addr = htonl(val);
lib/libc/net/inet_addr.c
66
struct in_addr val;
lib/libc/net/inet_addr.c
68
if (inet_aton(cp, &val))
lib/libc/net/inet_addr.c
69
return (val.s_addr);
lib/libc/net/inet_addr.c
83
in_addr_t val;
lib/libc/net/inet_addr.c
98
val = 0; base = 10;
lib/libc/net/inet_network.c
44
in_addr_t val, base, n;
lib/libc/net/inet_network.c
50
val = 0; base = 10;
lib/libc/net/inet_network.c
57
val = (val * base) + (c - '0');
lib/libc/net/inet_network.c
62
val = (val << 4) + (c + 10 - (islower(c) ? 'a' : 'A'));
lib/libc/net/inet_network.c
71
*pp++ = val, cp++;
lib/libc/net/inet_network.c
76
*pp++ = val;
lib/libc/net/inet_network.c
78
for (val = 0, i = 0; i < 4; i++) {
lib/libc/net/inet_network.c
79
val <<= 8;
lib/libc/net/inet_network.c
81
val |= parts[i] & 0xff;
lib/libc/net/inet_network.c
83
return (val);
lib/libc/net/inet_pton.c
131
u_int val;
lib/libc/net/inet_pton.c
142
val = 0;
lib/libc/net/inet_pton.c
151
val <<= 4;
lib/libc/net/inet_pton.c
152
val |= (pch - xdigits);
lib/libc/net/inet_pton.c
153
if (val > 0xffff)
lib/libc/net/inet_pton.c
171
*tp++ = (u_char) (val >> 8) & 0xff;
lib/libc/net/inet_pton.c
172
*tp++ = (u_char) val & 0xff;
lib/libc/net/inet_pton.c
175
val = 0;
lib/libc/net/inet_pton.c
190
*tp++ = (u_char) (val >> 8) & 0xff;
lib/libc/net/inet_pton.c
191
*tp++ = (u_char) val & 0xff;
lib/libc/net/ip6opt.c
181
inet6_opt_set_val(void *databuf, int offset, void *val, socklen_t vallen)
lib/libc/net/ip6opt.c
184
memcpy((u_int8_t *)databuf + offset, val, vallen);
lib/libc/net/ip6opt.c
278
inet6_opt_get_val(void *databuf, int offset, void *val, socklen_t vallen)
lib/libc/net/ip6opt.c
282
memcpy(val, (u_int8_t *)databuf + offset, vallen);
lib/libc/rpc/getrpcent.c
152
interpret(char *val, int len)
lib/libc/rpc/getrpcent.c
161
strlcpy(d->line, val, sizeof(d->line));
lib/libc/rpc/getrpcent.c
53
static struct rpcent *interpret(char *val, int len);
lib/libc/stdio/vfprintf.c
424
#define APPEND_DIGIT(val, dig) do { \
lib/libc/stdio/vfprintf.c
425
if ((val) > INT_MAX / 10) \
lib/libc/stdio/vfprintf.c
427
(val) *= 10; \
lib/libc/stdio/vfprintf.c
428
if ((val) > INT_MAX - to_digit((dig))) \
lib/libc/stdio/vfprintf.c
430
(val) += to_digit((dig)); \
lib/libc/stdio/vfprintf.c
437
#define GETASTER(val) \
lib/libc/stdio/vfprintf.c
455
val = GETARG(int); \
lib/libc/stdio/vfprintf.c
459
val = GETARG(int); \
lib/libc/stdio/vfwprintf.c
401
#define APPEND_DIGIT(val, dig) do { \
lib/libc/stdio/vfwprintf.c
402
if ((val) > INT_MAX / 10) \
lib/libc/stdio/vfwprintf.c
404
(val) *= 10; \
lib/libc/stdio/vfwprintf.c
405
if ((val) > INT_MAX - to_digit((dig))) \
lib/libc/stdio/vfwprintf.c
407
(val) += to_digit((dig)); \
lib/libc/stdio/vfwprintf.c
414
#define GETASTER(val) \
lib/libc/stdio/vfwprintf.c
432
val = GETARG(int); \
lib/libc/stdio/vfwprintf.c
436
val = GETARG(int); \
lib/libc/stdlib/getopt_long.c
209
long_options[i].val != long_options[match].val)
lib/libc/stdlib/getopt_long.c
229
optopt = long_options[match].val;
lib/libc/stdlib/getopt_long.c
259
optopt = long_options[match].val;
lib/libc/stdlib/getopt_long.c
278
*long_options[match].flag = long_options[match].val;
lib/libc/stdlib/getopt_long.c
281
return (long_options[match].val);
lib/libc/stdlib/random.c
201
div_t val;
lib/libc/stdlib/random.c
217
val = div(state[i-1], 127773);
lib/libc/stdlib/random.c
218
test = 16807 * val.rem - 2836 * val.quot;
lib/libc/thread/synch.h
29
_twait(volatile uint32_t *p, int val, clockid_t clockid, const struct timespec *abs)
lib/libc/thread/synch.h
36
error = futex(p, FUTEX_WAIT_PRIVATE, val, NULL, NULL);
lib/libc/thread/synch.h
51
error = futex(p, FUTEX_WAIT_PRIVATE, val, &rel, NULL);
lib/libc/yp/xdr_ypresp_all.c
41
return xdr_ypresp_key_val(xdrs, &objp->ypresp_all_u.val);
lib/libc/yp/xdr_ypresp_key_val.c
39
if (!xdr_valdat(xdrs, &objp->val)) {
lib/libc/yp/xdr_ypresp_val.c
39
return xdr_valdat(xdrs, &objp->val);
lib/libc/yp/yp_all.c
49
char *key, *val;
lib/libc/yp/yp_all.c
63
status = out.ypresp_all_u.val.stat;
lib/libc/yp/yp_all.c
65
size = out.ypresp_all_u.val.key.keydat_len;
lib/libc/yp/yp_all.c
70
(void)memcpy(key, out.ypresp_all_u.val.key.keydat_val,
lib/libc/yp/yp_all.c
74
size = out.ypresp_all_u.val.val.valdat_len;
lib/libc/yp/yp_all.c
75
if ((val = malloc(size + 1)) == NULL) {
lib/libc/yp/yp_all.c
80
(void)memcpy(val, out.ypresp_all_u.val.val.valdat_val,
lib/libc/yp/yp_all.c
82
val[size] = '\0';
lib/libc/yp/yp_all.c
85
out.ypresp_all_u.val.key.keydat_len, val,
lib/libc/yp/yp_all.c
86
out.ypresp_all_u.val.val.valdat_len, ypresp_data);
lib/libc/yp/yp_all.c
88
free(val);
lib/libc/yp/yp_first.c
77
*outvallen = yprkv.val.valdat_len;
lib/libc/yp/yp_first.c
85
(void)memcpy(*outval, yprkv.val.valdat_val, *outvallen);
lib/libc/yp/ypmatch_cache.c
100
ep->val = newval;
lib/libc/yp/ypmatch_cache.c
108
ypmatch_find(const char *map, const char *key, u_int keylen, char **val,
lib/libc/yp/ypmatch_cache.c
129
*val = ep->val;
lib/libc/yp/ypmatch_cache.c
162
inkeylen, &yprv.val.valdat_val, &yprv.val.valdat_len)) {
lib/libc/yp/ypmatch_cache.c
163
*outvallen = yprv.val.valdat_len;
lib/libc/yp/ypmatch_cache.c
168
(void)memcpy(*outval, yprv.val.valdat_val, *outvallen);
lib/libc/yp/ypmatch_cache.c
194
*outvallen = yprv.val.valdat_len;
lib/libc/yp/ypmatch_cache.c
199
(void)memcpy(*outval, yprv.val.valdat_val, *outvallen);
lib/libc/yp/ypmatch_cache.c
256
*outvallen = yprkv.val.valdat_len;
lib/libc/yp/ypmatch_cache.c
264
(void)memcpy(*outval, yprkv.val.valdat_val, *outvallen);
lib/libc/yp/ypmatch_cache.c
45
char *val;
lib/libc/yp/ypmatch_cache.c
53
ypmatch_add(const char *map, const char *key, u_int keylen, char *val,
lib/libc/yp/ypmatch_cache.c
90
free(ep->val);
lib/libc/yp/ypmatch_cache.c
97
(void)memcpy(newval, val, vallen);
lib/libcbor/src/cbor/encoding.c
130
uint32_t val = ((union _cbor_float_helper){.as_float = value}).as_uint;
lib/libcbor/src/cbor/encoding.c
132
uint8_t exp = (uint8_t)((val & 0x7F800000u) >>
lib/libcbor/src/cbor/encoding.c
135
val & 0x7FFFFFu; /* 0b0000_0000_0111_1111_1111_1111_1111_1111 */
lib/libcbor/src/cbor/encoding.c
148
res = (uint16_t)((val & 0x80000000u) >> 16u | 0x7C00u);
lib/libcbor/src/cbor/encoding.c
151
res = (uint16_t)((val & 0x80000000u) >> 16u | mant >> 13u);
lib/libcbor/src/cbor/encoding.c
166
res = (uint16_t)((val & 0x80000000u) >> 16u) | // Extract sign bit
lib/libcbor/src/cbor/encoding.c
171
res = (uint16_t)((val & 0x80000000u) >> 16u |
lib/libcbor/src/cbor/internal/loaders.c
57
double val;
lib/libcbor/src/cbor/internal/loaders.c
59
val = ldexp(mant, -24);
lib/libcbor/src/cbor/internal/loaders.c
61
val = ldexp(mant + 1024, exp - 25);
lib/libcbor/src/cbor/internal/loaders.c
63
val = mant == 0 ? INFINITY : NAN;
lib/libcbor/src/cbor/internal/loaders.c
64
return (float)(half & 0x8000 ? -val : val);
lib/libcbor/src/cbor/strings.c
41
cbor_item_t *cbor_build_string(const char *val) {
lib/libcbor/src/cbor/strings.c
44
size_t len = strlen(val);
lib/libcbor/src/cbor/strings.c
47
memcpy(handle, val, len);
lib/libcbor/src/cbor/strings.c
52
cbor_item_t *cbor_build_stringn(const char *val, size_t length) {
lib/libcbor/src/cbor/strings.c
57
memcpy(handle, val, length);
lib/libcbor/src/cbor/strings.h
146
_CBOR_NODISCARD CBOR_EXPORT cbor_item_t *cbor_build_string(const char *val);
lib/libcbor/src/cbor/strings.h
155
_CBOR_NODISCARD CBOR_EXPORT cbor_item_t *cbor_build_stringn(const char *val,
lib/libcrypto/arch/aarch64/crypto_cpu_caps.c
32
extract_bits(uint64_t val, int start, int end)
lib/libcrypto/arch/aarch64/crypto_cpu_caps.c
34
return (val >> end) & (1ULL << (1 + start - end)) - 1;
lib/libcrypto/asn1/a_enum.c
131
ASN1_ENUMERATED_set_int64(ASN1_ENUMERATED *aenum, int64_t val)
lib/libcrypto/asn1/a_enum.c
137
uval = (uint64_t)val;
lib/libcrypto/asn1/a_enum.c
139
if (val < 0) {
lib/libcrypto/asn1/a_enum.c
151
int64_t val;
lib/libcrypto/asn1/a_enum.c
155
if (!ASN1_ENUMERATED_get_int64(&val, aenum))
lib/libcrypto/asn1/a_enum.c
157
if (val < LONG_MIN || val > LONG_MAX) {
lib/libcrypto/asn1/a_enum.c
162
return (long)val;
lib/libcrypto/asn1/a_enum.c
167
ASN1_ENUMERATED_set(ASN1_ENUMERATED *aenum, long val)
lib/libcrypto/asn1/a_enum.c
169
return ASN1_ENUMERATED_set_int64(aenum, val);
lib/libcrypto/asn1/a_int.c
137
uint64_t val = 0;
lib/libcrypto/asn1/a_int.c
145
if (val > (UINT64_MAX >> 8)) {
lib/libcrypto/asn1/a_int.c
149
val = val << 8 | u8;
lib/libcrypto/asn1/a_int.c
152
*out_val = val;
lib/libcrypto/asn1/a_int.c
158
asn1_aint_set_uint64(uint64_t val, uint8_t **out_data, int *out_len)
lib/libcrypto/asn1/a_int.c
177
u8 = (val >> (i * 8)) & 0xff;
lib/libcrypto/asn1/a_int.c
205
uint64_t val;
lib/libcrypto/asn1/a_int.c
207
if (!asn1_aint_get_uint64(cbs, &val))
lib/libcrypto/asn1/a_int.c
211
if (val > (uint64_t)INT64_MIN) {
lib/libcrypto/asn1/a_int.c
215
*out_val = (int64_t)-val;
lib/libcrypto/asn1/a_int.c
217
if (val > (uint64_t)INT64_MAX) {
lib/libcrypto/asn1/a_int.c
221
*out_val = (int64_t)val;
lib/libcrypto/asn1/a_int.c
230
uint64_t val;
lib/libcrypto/asn1/a_int.c
249
if (!asn1_aint_get_uint64(&cbs, &val))
lib/libcrypto/asn1/a_int.c
252
*out_val = val;
lib/libcrypto/asn1/a_int.c
259
ASN1_INTEGER_set_uint64(ASN1_INTEGER *aint, uint64_t val)
lib/libcrypto/asn1/a_int.c
263
return asn1_aint_set_uint64(val, &aint->data, &aint->length);
lib/libcrypto/asn1/a_int.c
291
ASN1_INTEGER_set_int64(ASN1_INTEGER *aint, int64_t val)
lib/libcrypto/asn1/a_int.c
297
uval = (uint64_t)val;
lib/libcrypto/asn1/a_int.c
299
if (val < 0) {
lib/libcrypto/asn1/a_int.c
311
int64_t val;
lib/libcrypto/asn1/a_int.c
315
if (!ASN1_INTEGER_get_int64(&val, aint))
lib/libcrypto/asn1/a_int.c
317
if (val < LONG_MIN || val > LONG_MAX) {
lib/libcrypto/asn1/a_int.c
322
return (long)val;
lib/libcrypto/asn1/a_int.c
327
ASN1_INTEGER_set(ASN1_INTEGER *aint, long val)
lib/libcrypto/asn1/a_int.c
329
return ASN1_INTEGER_set_int64(aint, val);
lib/libcrypto/asn1/a_int.c
566
uint8_t padding, val;
lib/libcrypto/asn1/a_int.c
584
if (!CBS_peek_u8(&cbs, &val))
lib/libcrypto/asn1/a_int.c
586
if (val != 0)
lib/libcrypto/asn1/a_int.c
666
uint8_t padding, val;
lib/libcrypto/asn1/a_int.c
683
if (!CBS_peek_u8(cbs, &val))
lib/libcrypto/asn1/a_int.c
687
negative = (val >> 7);
lib/libcrypto/asn1/a_int.c
694
if (CBS_len(cbs) > 1 && val == padding) {
lib/libcrypto/asn1/a_int.c
698
if (!CBS_peek_u8(cbs, &val))
lib/libcrypto/asn1/a_int.c
700
if ((val >> 7) == (padding >> 7)) {
lib/libcrypto/asn1/a_object.c
134
uint8_t val;
lib/libcrypto/asn1/a_object.c
138
val = (arc >> (i * 7)) & 0x7f;
lib/libcrypto/asn1/a_object.c
139
if (!started && i != 0 && val == 0)
lib/libcrypto/asn1/a_object.c
142
val |= 0x80;
lib/libcrypto/asn1/a_object.c
143
if (!CBB_add_u8(cbb, val))
lib/libcrypto/asn1/a_object.c
155
uint8_t val;
lib/libcrypto/asn1/a_object.c
158
if (!CBS_get_u8(cbs, &val))
lib/libcrypto/asn1/a_object.c
160
if (arc == 0 && val == 0x80)
lib/libcrypto/asn1/a_object.c
164
arc = (arc << 7) | (val & 0x7f);
lib/libcrypto/asn1/a_object.c
165
} while (val & 0x80);
lib/libcrypto/asn1/a_object.c
196
uint8_t val;
lib/libcrypto/asn1/a_object.c
199
if (!CBS_get_u8(cbs, &val))
lib/libcrypto/asn1/a_object.c
201
if ((*separator == 0 && val != '.' && val != ' ') ||
lib/libcrypto/asn1/a_object.c
202
(*separator != 0 && val != *separator)) {
lib/libcrypto/asn1/a_object.c
206
*separator = val;
lib/libcrypto/asn1/a_object.c
210
if (!CBS_peek_u8(cbs, &val))
lib/libcrypto/asn1/a_object.c
212
if (val == '.' || val == ' ')
lib/libcrypto/asn1/a_object.c
215
if (!CBS_get_u8(cbs, &val))
lib/libcrypto/asn1/a_object.c
217
if (val < '0' || val > '9') {
lib/libcrypto/asn1/a_object.c
226
val -= '0';
lib/libcrypto/asn1/a_object.c
228
if (digits > 0 && arc == 0 && val == 0) {
lib/libcrypto/asn1/a_object.c
238
arc = arc * 10 + val;
lib/libcrypto/asn1/a_strex.c
435
ASN1_STRING *val;
lib/libcrypto/asn1/a_strex.c
517
val = X509_NAME_ENTRY_get_data(ent);
lib/libcrypto/asn1/a_strex.c
560
len = do_print_ex(io_ch, arg, flags | orflags, val);
lib/libcrypto/asn1/a_time_tm.c
201
int year, month, day, hour, min, sec, val;
lib/libcrypto/asn1/a_time_tm.c
208
if (!cbs_get_two_digit_value(©, &val))
lib/libcrypto/asn1/a_time_tm.c
210
year = val * 100;
lib/libcrypto/asn1/a_time_tm.c
211
if (!cbs_get_two_digit_value(©, &val))
lib/libcrypto/asn1/a_time_tm.c
213
year += val;
lib/libcrypto/asn1/a_time_tm.c
216
if (!cbs_get_two_digit_value(©, &val))
lib/libcrypto/asn1/a_time_tm.c
218
year += val;
lib/libcrypto/asn1/a_utf8.c
137
*val = value;
lib/libcrypto/asn1/a_utf8.c
79
UTF8_getc(const unsigned char *str, int len, unsigned long *val)
lib/libcrypto/asn1/asn1.h
705
int ASN1_INTEGER_set_uint64(ASN1_INTEGER *aint, uint64_t val);
lib/libcrypto/asn1/asn1.h
707
int ASN1_INTEGER_set_int64(ASN1_INTEGER *aint, int64_t val);
lib/libcrypto/asn1/asn1.h
714
int ASN1_ENUMERATED_set_int64(ASN1_ENUMERATED *aenum, int64_t val);
lib/libcrypto/asn1/asn1.h
828
void ASN1_item_free(ASN1_VALUE *val, const ASN1_ITEM *it);
lib/libcrypto/asn1/asn1.h
829
ASN1_VALUE *ASN1_item_d2i(ASN1_VALUE **val, const unsigned char **in,
lib/libcrypto/asn1/asn1.h
831
int ASN1_item_i2d(ASN1_VALUE *val, unsigned char **out, const ASN1_ITEM *it);
lib/libcrypto/asn1/asn1_gen.c
79
#define ASN1_GEN_STR(str,val){str, sizeof(str) - 1, val}
lib/libcrypto/asn1/asn1_lib.c
100
if (val < 0x80) {
lib/libcrypto/asn1/asn1_lib.c
101
*out_length = val;
lib/libcrypto/asn1/asn1_lib.c
109
if (val == 0x80) {
lib/libcrypto/asn1/asn1_lib.c
120
if ((len_bytes = val & 0x7f) == 0x7f)
lib/libcrypto/asn1/asn1_lib.c
126
if (!CBS_get_u8(cbs, &val))
lib/libcrypto/asn1/asn1_lib.c
128
if (der_mode && length == 0 && val == 0)
lib/libcrypto/asn1/asn1_lib.c
132
length = (length << 8) | val;
lib/libcrypto/asn1/asn1_lib.c
85
uint8_t val;
lib/libcrypto/asn1/asn1_lib.c
94
if (!CBS_get_u8(cbs, &val))
lib/libcrypto/asn1/asn1_local.h
122
int UTF8_getc(const unsigned char *str, int len, unsigned long *val);
lib/libcrypto/asn1/asn1_local.h
147
int asn1_aint_set_uint64(uint64_t val, uint8_t **out_data, int *out_len);
lib/libcrypto/asn1/asn1_local.h
172
int ASN1_item_ndef_i2d(ASN1_VALUE *val, unsigned char **out, const ASN1_ITEM *it);
lib/libcrypto/asn1/asn1_local.h
176
BIO *BIO_new_NDEF(BIO *out, ASN1_VALUE *val, const ASN1_ITEM *it);
lib/libcrypto/asn1/asn1_local.h
178
int i2d_ASN1_bio_stream(BIO *out, ASN1_VALUE *val, BIO *in, int flags,
lib/libcrypto/asn1/asn1_local.h
180
int PEM_write_bio_ASN1_stream(BIO *out, ASN1_VALUE *val, BIO *in, int flags,
lib/libcrypto/asn1/asn1_local.h
182
int SMIME_write_ASN1(BIO *bio, ASN1_VALUE *val, BIO *data, int flags,
lib/libcrypto/asn1/asn1t.h
512
#define ADB_ENTRY(val, template) \
lib/libcrypto/asn1/asn1t.h
514
.value = val, \
lib/libcrypto/asn1/asn_mime.c
117
i2d_ASN1_bio_stream(BIO *out, ASN1_VALUE *val, BIO *in, int flags,
lib/libcrypto/asn1/asn_mime.c
125
return ASN1_item_i2d_bio(it, out, val);
lib/libcrypto/asn1/asn_mime.c
128
if ((bio = BIO_new_NDEF(out, val, it)) == NULL) {
lib/libcrypto/asn1/asn_mime.c
149
B64_write_ASN1(BIO *out, ASN1_VALUE *val, BIO *in, int flags,
lib/libcrypto/asn1/asn_mime.c
163
r = i2d_ASN1_bio_stream(out, val, in, flags, it);
lib/libcrypto/asn1/asn_mime.c
173
PEM_write_bio_ASN1_stream(BIO *out, ASN1_VALUE *val, BIO *in, int flags,
lib/libcrypto/asn1/asn_mime.c
179
r = B64_write_ASN1(out, val, in, flags, it);
lib/libcrypto/asn1/asn_mime.c
188
ASN1_VALUE *val;
lib/libcrypto/asn1/asn_mime.c
194
val = ASN1_item_d2i_bio(it, bio, NULL);
lib/libcrypto/asn1/asn_mime.c
195
if (!val)
lib/libcrypto/asn1/asn_mime.c
200
return val;
lib/libcrypto/asn1/asn_mime.c
278
SMIME_write_ASN1(BIO *bio, ASN1_VALUE *val, BIO *data, int flags,
lib/libcrypto/asn1/asn_mime.c
320
if (!asn1_output_data(bio, data, val, flags, it))
lib/libcrypto/asn1/asn_mime.c
333
B64_write_ASN1(bio, val, NULL, 0, it);
lib/libcrypto/asn1/asn_mime.c
364
if (!B64_write_ASN1(bio, val, data, flags, it))
lib/libcrypto/asn1/asn_mime.c
374
asn1_output_data(BIO *out, BIO *data, ASN1_VALUE *val, int flags,
lib/libcrypto/asn1/asn_mime.c
402
if (aux->asn1_cb(ASN1_OP_DETACHED_PRE, &val, it, &sarg) <= 0)
lib/libcrypto/asn1/asn_mime.c
409
if (aux->asn1_cb(ASN1_OP_DETACHED_POST, &val, it, &sarg) <= 0)
lib/libcrypto/asn1/asn_mime.c
436
ASN1_VALUE *val;
lib/libcrypto/asn1/asn_mime.c
500
if (!(val = b64_read_asn1(asnin, it))) {
lib/libcrypto/asn1/asn_mime.c
512
return val;
lib/libcrypto/asn1/asn_mime.c
527
if (!(val = b64_read_asn1(bio, it))) {
lib/libcrypto/asn1/asn_mime.c
531
return val;
lib/libcrypto/asn1/asn_mime.c
92
static int asn1_output_data(BIO *out, BIO *data, ASN1_VALUE *val, int flags,
lib/libcrypto/asn1/bio_ndef.c
106
BIO_new_NDEF(BIO *out, ASN1_VALUE *val, const ASN1_ITEM *it)
lib/libcrypto/asn1/bio_ndef.c
155
if (aux->asn1_cb(ASN1_OP_STREAM_PRE, &val, it, &sarg) <= 0)
lib/libcrypto/asn1/bio_ndef.c
158
ndef_aux->val = val;
lib/libcrypto/asn1/bio_ndef.c
185
if ((derlen = ASN1_item_ndef_i2d(ndef_aux->val, &p, ndef_aux->it)) <= 0)
lib/libcrypto/asn1/bio_ndef.c
254
&ndef_aux->val, ndef_aux->it, &sarg) <= 0)
lib/libcrypto/asn1/bio_ndef.c
257
if ((derlen = ASN1_item_ndef_i2d(ndef_aux->val, &p, ndef_aux->it)) <= 0)
lib/libcrypto/asn1/bio_ndef.c
88
ASN1_VALUE *val;
lib/libcrypto/asn1/tasn_dec.c
281
uint8_t val;
lib/libcrypto/asn1/tasn_dec.c
310
if (!CBS_get_u8(content, &val))
lib/libcrypto/asn1/tasn_dec.c
312
*abool = val;
lib/libcrypto/asn1/tasn_enc.c
107
asn1_item_flags_i2d(ASN1_VALUE *val, unsigned char **out, const ASN1_ITEM *it,
lib/libcrypto/asn1/tasn_enc.c
114
return ASN1_item_ex_i2d(&val, out, it, -1, flags);
lib/libcrypto/asn1/tasn_enc.c
116
if ((len = ASN1_item_ex_i2d(&val, NULL, it, -1, flags)) <= 0)
lib/libcrypto/asn1/tasn_enc.c
123
if (ASN1_item_ex_i2d(&val, &p, it, -1, flags) != len) {
lib/libcrypto/asn1/tasn_enc.c
75
static int asn1_item_flags_i2d(ASN1_VALUE *val, unsigned char **out,
lib/libcrypto/asn1/tasn_enc.c
85
ASN1_item_ndef_i2d(ASN1_VALUE *val, unsigned char **out, const ASN1_ITEM *it)
lib/libcrypto/asn1/tasn_enc.c
87
return asn1_item_flags_i2d(val, out, it, ASN1_TFLG_NDEF);
lib/libcrypto/asn1/tasn_enc.c
91
ASN1_item_i2d(ASN1_VALUE *val, unsigned char **out, const ASN1_ITEM *it)
lib/libcrypto/asn1/tasn_enc.c
93
return asn1_item_flags_i2d(val, out, it, 0);
lib/libcrypto/asn1/tasn_fre.c
72
ASN1_item_free(ASN1_VALUE *val, const ASN1_ITEM *it)
lib/libcrypto/asn1/tasn_fre.c
74
asn1_item_free(&val, it);
lib/libcrypto/asn1/x_attrib.c
136
ASN1_TYPE *val = NULL;
lib/libcrypto/asn1/x_attrib.c
144
if ((val = ASN1_TYPE_new()) == NULL)
lib/libcrypto/asn1/x_attrib.c
146
if (!sk_ASN1_TYPE_push(ret->set, val))
lib/libcrypto/asn1/x_attrib.c
149
ASN1_TYPE_set(val, atrtype, value);
lib/libcrypto/asn1/x_attrib.c
155
if (val != NULL)
lib/libcrypto/asn1/x_attrib.c
156
ASN1_TYPE_free(val);
lib/libcrypto/asn1/x_long.c
127
long_set(ASN1_VALUE **pval, long val)
lib/libcrypto/asn1/x_long.c
129
memcpy(pval, &val, sizeof(long));
lib/libcrypto/asn1/x_long.c
159
long val;
lib/libcrypto/asn1/x_long.c
162
long_get(pval, &val);
lib/libcrypto/asn1/x_long.c
169
if (val == it->size)
lib/libcrypto/asn1/x_long.c
174
if (!ASN1_INTEGER_set_int64(aint, (int64_t)val))
lib/libcrypto/asn1/x_long.c
192
int64_t val = 0;
lib/libcrypto/asn1/x_long.c
205
if (!ASN1_INTEGER_get_int64(&val, aint))
lib/libcrypto/asn1/x_long.c
209
if (val < LONG_MIN || val > LONG_MAX) {
lib/libcrypto/asn1/x_long.c
218
if (val == (int64_t)it->size) {
lib/libcrypto/asn1/x_long.c
223
long_set(pval, (long)val);
lib/libcrypto/asn1/x_long.c
237
long val;
lib/libcrypto/asn1/x_long.c
239
long_get(pval, &val);
lib/libcrypto/asn1/x_long.c
241
if (BIO_printf(out, "%ld\n", val) <= 0)
lib/libcrypto/asn1/x_name.c
255
x509_name_ex_new(ASN1_VALUE **val, const ASN1_ITEM *it)
lib/libcrypto/asn1/x_name.c
269
*val = (ASN1_VALUE *)ret;
lib/libcrypto/asn1/x_name.c
299
x509_name_ex_d2i(ASN1_VALUE **val, const unsigned char **in, long len,
lib/libcrypto/asn1/x_name.c
323
if (*val)
lib/libcrypto/asn1/x_name.c
324
x509_name_ex_free(val, NULL);
lib/libcrypto/asn1/x_name.c
348
*val = nm.a;
lib/libcrypto/asn1/x_name.c
360
x509_name_ex_i2d(ASN1_VALUE **val, unsigned char **out, const ASN1_ITEM *it,
lib/libcrypto/asn1/x_name.c
364
X509_NAME *a = (X509_NAME *)*val;
lib/libcrypto/asn1/x_name.c
73
static int x509_name_ex_d2i(ASN1_VALUE **val, const unsigned char **in,
lib/libcrypto/asn1/x_name.c
77
static int x509_name_ex_i2d(ASN1_VALUE **val, unsigned char **out,
lib/libcrypto/asn1/x_name.c
79
static int x509_name_ex_new(ASN1_VALUE **val, const ASN1_ITEM *it);
lib/libcrypto/asn1/x_name.c
80
static void x509_name_ex_free(ASN1_VALUE **val, const ASN1_ITEM *it);
lib/libcrypto/bn/bn_exp.c
1003
if (!BN_mod_sqr_reciprocal(aa, val[0], recp, ctx))
lib/libcrypto/bn/bn_exp.c
1007
if (((val[i] = BN_CTX_get(ctx)) == NULL) ||
lib/libcrypto/bn/bn_exp.c
1008
!BN_mod_mul_reciprocal(val[i], val[i - 1],
lib/libcrypto/bn/bn_exp.c
1061
if (!BN_mod_mul_reciprocal(r, r, val[wvalue >> 1], recp, ctx))
lib/libcrypto/bn/bn_exp.c
186
BIGNUM *val[TABLE_SIZE];
lib/libcrypto/bn/bn_exp.c
216
if ((val[0] = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_exp.c
219
if (!BN_nnmod(val[0], a, m, ctx))
lib/libcrypto/bn/bn_exp.c
221
if (BN_is_zero(val[0])) {
lib/libcrypto/bn/bn_exp.c
230
if (!BN_mod_mul(d, val[0], val[0], m, ctx))
lib/libcrypto/bn/bn_exp.c
234
if (((val[i] = BN_CTX_get(ctx)) == NULL) ||
lib/libcrypto/bn/bn_exp.c
235
!BN_mod_mul(val[i], val[i - 1], d,m, ctx))
lib/libcrypto/bn/bn_exp.c
287
if (!BN_mod_mul(r, r, val[wvalue >> 1], m, ctx))
lib/libcrypto/bn/bn_exp.c
652
BIGNUM *val[TABLE_SIZE];
lib/libcrypto/bn/bn_exp.c
681
if ((val[0] = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_exp.c
689
if (!BN_nnmod(val[0], a,m, ctx))
lib/libcrypto/bn/bn_exp.c
691
aa = val[0];
lib/libcrypto/bn/bn_exp.c
697
if (!BN_to_montgomery(val[0], aa, mont, ctx))
lib/libcrypto/bn/bn_exp.c
702
if (!BN_mod_mul_montgomery(d, val[0], val[0], mont, ctx))
lib/libcrypto/bn/bn_exp.c
706
if (((val[i] = BN_CTX_get(ctx)) == NULL) ||
lib/libcrypto/bn/bn_exp.c
707
!BN_mod_mul_montgomery(val[i], val[i - 1],
lib/libcrypto/bn/bn_exp.c
760
if (!BN_mod_mul_montgomery(r, r, val[wvalue >> 1], mont, ctx))
lib/libcrypto/bn/bn_exp.c
960
BIGNUM *val[TABLE_SIZE];
lib/libcrypto/bn/bn_exp.c
986
if ((val[0] = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_exp.c
992
if (!BN_nnmod(val[0], a, m, ctx))
lib/libcrypto/bn/bn_exp.c
994
if (BN_is_zero(val[0])) {
lib/libcrypto/crypto.h
306
int CRYPTO_set_ex_data(CRYPTO_EX_DATA *ad, int idx, void *val);
lib/libcrypto/crypto.h
337
void CRYPTO_THREADID_set_numeric(CRYPTO_THREADID *id, unsigned long val);
lib/libcrypto/crypto_ex_data.c
277
void *val;
lib/libcrypto/crypto_ex_data.c
317
val = src_ced->slots[i];
lib/libcrypto/crypto_ex_data.c
319
if (!index->dup_func(dst, src, &val, i, index->argl,
lib/libcrypto/crypto_ex_data.c
326
dst_ced->slots[i] = val;
lib/libcrypto/crypto_ex_data.c
380
CRYPTO_set_ex_data(CRYPTO_EX_DATA *exdata, int idx, void *val)
lib/libcrypto/crypto_ex_data.c
399
ced->slots[idx] = val;
lib/libcrypto/crypto_legacy.c
249
CRYPTO_THREADID_set_numeric(CRYPTO_THREADID *id, unsigned long val)
lib/libcrypto/ct/ct_x509v3.c
69
i2s_poison(const X509V3_EXT_METHOD *method, void *val)
lib/libcrypto/ec/ec_mult.c
162
EC_POINT **val = NULL;
lib/libcrypto/ec/ec_mult.c
170
if ((val = calloc(len, sizeof(*val))) == NULL) {
lib/libcrypto/ec/ec_mult.c
174
memcpy(&val[0], points0, sizeof(*val) * len0);
lib/libcrypto/ec/ec_mult.c
175
memcpy(&val[len0], points1, sizeof(*val) * len1);
lib/libcrypto/ec/ec_mult.c
177
if (!group->meth->points_make_affine(group, len, val, ctx))
lib/libcrypto/ec/ec_mult.c
183
free(val);
lib/libcrypto/modes/ccm128.c
343
size_t n = 8, val = 0;
lib/libcrypto/modes/ccm128.c
348
val += counter[n] + (inc & 0xff);
lib/libcrypto/modes/ccm128.c
349
counter[n] = (unsigned char)val;
lib/libcrypto/modes/ccm128.c
350
val >>= 8; /* carry bit */
lib/libcrypto/modes/ccm128.c
352
} while (n && (inc || val));
lib/libcrypto/ocsp/ocsp.h
209
int OCSP_request_add1_nonce(OCSP_REQUEST *req, unsigned char *val, int len);
lib/libcrypto/ocsp/ocsp.h
210
int OCSP_basic_add1_nonce(OCSP_BASICRESP *resp, unsigned char *val, int len);
lib/libcrypto/ocsp/ocsp_ext.c
367
ocsp_add1_nonce(STACK_OF(X509_EXTENSION) **exts, unsigned char *val, int len)
lib/libcrypto/ocsp/ocsp_ext.c
386
if (val)
lib/libcrypto/ocsp/ocsp_ext.c
387
memcpy(tmpval, val, len);
lib/libcrypto/ocsp/ocsp_ext.c
402
OCSP_request_add1_nonce(OCSP_REQUEST *req, unsigned char *val, int len)
lib/libcrypto/ocsp/ocsp_ext.c
404
return ocsp_add1_nonce(&req->tbsRequest->requestExtensions, val, len);
lib/libcrypto/ocsp/ocsp_ext.c
410
OCSP_basic_add1_nonce(OCSP_BASICRESP *resp, unsigned char *val, int len)
lib/libcrypto/ocsp/ocsp_ext.c
412
return ocsp_add1_nonce(&resp->tbsResponseData->responseExtensions, val,
lib/libcrypto/stack/safestack.h
1011
#define sk_PKCS7_set(st, i, val) SKM_sk_set(PKCS7, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1013
#define sk_PKCS7_push(st, val) SKM_sk_push(PKCS7, (st), (val))
lib/libcrypto/stack/safestack.h
1014
#define sk_PKCS7_unshift(st, val) SKM_sk_unshift(PKCS7, (st), (val))
lib/libcrypto/stack/safestack.h
1015
#define sk_PKCS7_find(st, val) SKM_sk_find(PKCS7, (st), (val))
lib/libcrypto/stack/safestack.h
1018
#define sk_PKCS7_insert(st, val, i) SKM_sk_insert(PKCS7, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1032
#define sk_PKCS7_RECIP_INFO_set(st, i, val) SKM_sk_set(PKCS7_RECIP_INFO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1034
#define sk_PKCS7_RECIP_INFO_push(st, val) SKM_sk_push(PKCS7_RECIP_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1035
#define sk_PKCS7_RECIP_INFO_unshift(st, val) SKM_sk_unshift(PKCS7_RECIP_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1036
#define sk_PKCS7_RECIP_INFO_find(st, val) SKM_sk_find(PKCS7_RECIP_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1039
#define sk_PKCS7_RECIP_INFO_insert(st, val, i) SKM_sk_insert(PKCS7_RECIP_INFO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1053
#define sk_PKCS7_SIGNER_INFO_set(st, i, val) SKM_sk_set(PKCS7_SIGNER_INFO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1055
#define sk_PKCS7_SIGNER_INFO_push(st, val) SKM_sk_push(PKCS7_SIGNER_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1056
#define sk_PKCS7_SIGNER_INFO_unshift(st, val) SKM_sk_unshift(PKCS7_SIGNER_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1057
#define sk_PKCS7_SIGNER_INFO_find(st, val) SKM_sk_find(PKCS7_SIGNER_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1060
#define sk_PKCS7_SIGNER_INFO_insert(st, val, i) SKM_sk_insert(PKCS7_SIGNER_INFO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1074
#define sk_POLICYINFO_set(st, i, val) SKM_sk_set(POLICYINFO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1076
#define sk_POLICYINFO_push(st, val) SKM_sk_push(POLICYINFO, (st), (val))
lib/libcrypto/stack/safestack.h
1077
#define sk_POLICYINFO_unshift(st, val) SKM_sk_unshift(POLICYINFO, (st), (val))
lib/libcrypto/stack/safestack.h
1078
#define sk_POLICYINFO_find(st, val) SKM_sk_find(POLICYINFO, (st), (val))
lib/libcrypto/stack/safestack.h
1081
#define sk_POLICYINFO_insert(st, val, i) SKM_sk_insert(POLICYINFO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1095
#define sk_POLICYQUALINFO_set(st, i, val) SKM_sk_set(POLICYQUALINFO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1097
#define sk_POLICYQUALINFO_push(st, val) SKM_sk_push(POLICYQUALINFO, (st), (val))
lib/libcrypto/stack/safestack.h
1098
#define sk_POLICYQUALINFO_unshift(st, val) SKM_sk_unshift(POLICYQUALINFO, (st), (val))
lib/libcrypto/stack/safestack.h
1099
#define sk_POLICYQUALINFO_find(st, val) SKM_sk_find(POLICYQUALINFO, (st), (val))
lib/libcrypto/stack/safestack.h
1102
#define sk_POLICYQUALINFO_insert(st, val, i) SKM_sk_insert(POLICYQUALINFO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1116
#define sk_POLICY_MAPPING_set(st, i, val) SKM_sk_set(POLICY_MAPPING, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1118
#define sk_POLICY_MAPPING_push(st, val) SKM_sk_push(POLICY_MAPPING, (st), (val))
lib/libcrypto/stack/safestack.h
1119
#define sk_POLICY_MAPPING_unshift(st, val) SKM_sk_unshift(POLICY_MAPPING, (st), (val))
lib/libcrypto/stack/safestack.h
1120
#define sk_POLICY_MAPPING_find(st, val) SKM_sk_find(POLICY_MAPPING, (st), (val))
lib/libcrypto/stack/safestack.h
1123
#define sk_POLICY_MAPPING_insert(st, val, i) SKM_sk_insert(POLICY_MAPPING, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1137
#define sk_SCT_set(st, i, val) SKM_sk_set(SCT, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1139
#define sk_SCT_push(st, val) SKM_sk_push(SCT, (st), (val))
lib/libcrypto/stack/safestack.h
1140
#define sk_SCT_unshift(st, val) SKM_sk_unshift(SCT, (st), (val))
lib/libcrypto/stack/safestack.h
1141
#define sk_SCT_find(st, val) SKM_sk_find(SCT, (st), (val))
lib/libcrypto/stack/safestack.h
1144
#define sk_SCT_insert(st, val, i) SKM_sk_insert(SCT, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1158
#define sk_SRTP_PROTECTION_PROFILE_set(st, i, val) SKM_sk_set(SRTP_PROTECTION_PROFILE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1160
#define sk_SRTP_PROTECTION_PROFILE_push(st, val) SKM_sk_push(SRTP_PROTECTION_PROFILE, (st), (val))
lib/libcrypto/stack/safestack.h
1161
#define sk_SRTP_PROTECTION_PROFILE_unshift(st, val) SKM_sk_unshift(SRTP_PROTECTION_PROFILE, (st), (val))
lib/libcrypto/stack/safestack.h
1162
#define sk_SRTP_PROTECTION_PROFILE_find(st, val) SKM_sk_find(SRTP_PROTECTION_PROFILE, (st), (val))
lib/libcrypto/stack/safestack.h
1165
#define sk_SRTP_PROTECTION_PROFILE_insert(st, val, i) SKM_sk_insert(SRTP_PROTECTION_PROFILE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1179
#define sk_SSL_CIPHER_set(st, i, val) SKM_sk_set(SSL_CIPHER, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1181
#define sk_SSL_CIPHER_push(st, val) SKM_sk_push(SSL_CIPHER, (st), (val))
lib/libcrypto/stack/safestack.h
1182
#define sk_SSL_CIPHER_unshift(st, val) SKM_sk_unshift(SSL_CIPHER, (st), (val))
lib/libcrypto/stack/safestack.h
1183
#define sk_SSL_CIPHER_find(st, val) SKM_sk_find(SSL_CIPHER, (st), (val))
lib/libcrypto/stack/safestack.h
1186
#define sk_SSL_CIPHER_insert(st, val, i) SKM_sk_insert(SSL_CIPHER, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1200
#define sk_SSL_COMP_set(st, i, val) SKM_sk_set(SSL_COMP, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1202
#define sk_SSL_COMP_push(st, val) SKM_sk_push(SSL_COMP, (st), (val))
lib/libcrypto/stack/safestack.h
1203
#define sk_SSL_COMP_unshift(st, val) SKM_sk_unshift(SSL_COMP, (st), (val))
lib/libcrypto/stack/safestack.h
1204
#define sk_SSL_COMP_find(st, val) SKM_sk_find(SSL_COMP, (st), (val))
lib/libcrypto/stack/safestack.h
1207
#define sk_SSL_COMP_insert(st, val, i) SKM_sk_insert(SSL_COMP, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1221
#define sk_STACK_OF_X509_NAME_ENTRY_set(st, i, val) SKM_sk_set(STACK_OF_X509_NAME_ENTRY, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1223
#define sk_STACK_OF_X509_NAME_ENTRY_push(st, val) SKM_sk_push(STACK_OF_X509_NAME_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
1224
#define sk_STACK_OF_X509_NAME_ENTRY_unshift(st, val) SKM_sk_unshift(STACK_OF_X509_NAME_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
1225
#define sk_STACK_OF_X509_NAME_ENTRY_find(st, val) SKM_sk_find(STACK_OF_X509_NAME_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
1228
#define sk_STACK_OF_X509_NAME_ENTRY_insert(st, val, i) SKM_sk_insert(STACK_OF_X509_NAME_ENTRY, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1242
#define sk_STORE_ATTR_INFO_set(st, i, val) SKM_sk_set(STORE_ATTR_INFO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1244
#define sk_STORE_ATTR_INFO_push(st, val) SKM_sk_push(STORE_ATTR_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1245
#define sk_STORE_ATTR_INFO_unshift(st, val) SKM_sk_unshift(STORE_ATTR_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1246
#define sk_STORE_ATTR_INFO_find(st, val) SKM_sk_find(STORE_ATTR_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1249
#define sk_STORE_ATTR_INFO_insert(st, val, i) SKM_sk_insert(STORE_ATTR_INFO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1263
#define sk_STORE_OBJECT_set(st, i, val) SKM_sk_set(STORE_OBJECT, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1265
#define sk_STORE_OBJECT_push(st, val) SKM_sk_push(STORE_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
1266
#define sk_STORE_OBJECT_unshift(st, val) SKM_sk_unshift(STORE_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
1267
#define sk_STORE_OBJECT_find(st, val) SKM_sk_find(STORE_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
1270
#define sk_STORE_OBJECT_insert(st, val, i) SKM_sk_insert(STORE_OBJECT, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1284
#define sk_UI_STRING_set(st, i, val) SKM_sk_set(UI_STRING, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1286
#define sk_UI_STRING_push(st, val) SKM_sk_push(UI_STRING, (st), (val))
lib/libcrypto/stack/safestack.h
1287
#define sk_UI_STRING_unshift(st, val) SKM_sk_unshift(UI_STRING, (st), (val))
lib/libcrypto/stack/safestack.h
1288
#define sk_UI_STRING_find(st, val) SKM_sk_find(UI_STRING, (st), (val))
lib/libcrypto/stack/safestack.h
1291
#define sk_UI_STRING_insert(st, val, i) SKM_sk_insert(UI_STRING, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1305
#define sk_X509_set(st, i, val) SKM_sk_set(X509, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1307
#define sk_X509_push(st, val) SKM_sk_push(X509, (st), (val))
lib/libcrypto/stack/safestack.h
1308
#define sk_X509_unshift(st, val) SKM_sk_unshift(X509, (st), (val))
lib/libcrypto/stack/safestack.h
1309
#define sk_X509_find(st, val) SKM_sk_find(X509, (st), (val))
lib/libcrypto/stack/safestack.h
1312
#define sk_X509_insert(st, val, i) SKM_sk_insert(X509, (st), (val), (i))
lib/libcrypto/stack/safestack.h
132
#define SKM_sk_set(type, st,i,val) \
lib/libcrypto/stack/safestack.h
1326
#define sk_X509V3_EXT_METHOD_set(st, i, val) SKM_sk_set(X509V3_EXT_METHOD, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1328
#define sk_X509V3_EXT_METHOD_push(st, val) SKM_sk_push(X509V3_EXT_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
1329
#define sk_X509V3_EXT_METHOD_unshift(st, val) SKM_sk_unshift(X509V3_EXT_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
133
sk_set(CHECKED_STACK_OF(type, st), i, CHECKED_PTR_OF(type, val))
lib/libcrypto/stack/safestack.h
1330
#define sk_X509V3_EXT_METHOD_find(st, val) SKM_sk_find(X509V3_EXT_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
1333
#define sk_X509V3_EXT_METHOD_insert(st, val, i) SKM_sk_insert(X509V3_EXT_METHOD, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1347
#define sk_X509_ALGOR_set(st, i, val) SKM_sk_set(X509_ALGOR, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1349
#define sk_X509_ALGOR_push(st, val) SKM_sk_push(X509_ALGOR, (st), (val))
lib/libcrypto/stack/safestack.h
1350
#define sk_X509_ALGOR_unshift(st, val) SKM_sk_unshift(X509_ALGOR, (st), (val))
lib/libcrypto/stack/safestack.h
1351
#define sk_X509_ALGOR_find(st, val) SKM_sk_find(X509_ALGOR, (st), (val))
lib/libcrypto/stack/safestack.h
1354
#define sk_X509_ALGOR_insert(st, val, i) SKM_sk_insert(X509_ALGOR, (st), (val), (i))
lib/libcrypto/stack/safestack.h
136
#define SKM_sk_push(type, st, val) \
lib/libcrypto/stack/safestack.h
1368
#define sk_X509_ATTRIBUTE_set(st, i, val) SKM_sk_set(X509_ATTRIBUTE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
137
sk_push(CHECKED_STACK_OF(type, st), CHECKED_PTR_OF(type, val))
lib/libcrypto/stack/safestack.h
1370
#define sk_X509_ATTRIBUTE_push(st, val) SKM_sk_push(X509_ATTRIBUTE, (st), (val))
lib/libcrypto/stack/safestack.h
1371
#define sk_X509_ATTRIBUTE_unshift(st, val) SKM_sk_unshift(X509_ATTRIBUTE, (st), (val))
lib/libcrypto/stack/safestack.h
1372
#define sk_X509_ATTRIBUTE_find(st, val) SKM_sk_find(X509_ATTRIBUTE, (st), (val))
lib/libcrypto/stack/safestack.h
1375
#define sk_X509_ATTRIBUTE_insert(st, val, i) SKM_sk_insert(X509_ATTRIBUTE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
138
#define SKM_sk_unshift(type, st, val) \
lib/libcrypto/stack/safestack.h
1389
#define sk_X509_CRL_set(st, i, val) SKM_sk_set(X509_CRL, (st), (i), (val))
lib/libcrypto/stack/safestack.h
139
sk_unshift(CHECKED_STACK_OF(type, st), CHECKED_PTR_OF(type, val))
lib/libcrypto/stack/safestack.h
1391
#define sk_X509_CRL_push(st, val) SKM_sk_push(X509_CRL, (st), (val))
lib/libcrypto/stack/safestack.h
1392
#define sk_X509_CRL_unshift(st, val) SKM_sk_unshift(X509_CRL, (st), (val))
lib/libcrypto/stack/safestack.h
1393
#define sk_X509_CRL_find(st, val) SKM_sk_find(X509_CRL, (st), (val))
lib/libcrypto/stack/safestack.h
1396
#define sk_X509_CRL_insert(st, val, i) SKM_sk_insert(X509_CRL, (st), (val), (i))
lib/libcrypto/stack/safestack.h
140
#define SKM_sk_find(type, st, val) \
lib/libcrypto/stack/safestack.h
141
sk_find(CHECKED_STACK_OF(type, st), CHECKED_PTR_OF(type, val))
lib/libcrypto/stack/safestack.h
1410
#define sk_X509_EXTENSION_set(st, i, val) SKM_sk_set(X509_EXTENSION, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1412
#define sk_X509_EXTENSION_push(st, val) SKM_sk_push(X509_EXTENSION, (st), (val))
lib/libcrypto/stack/safestack.h
1413
#define sk_X509_EXTENSION_unshift(st, val) SKM_sk_unshift(X509_EXTENSION, (st), (val))
lib/libcrypto/stack/safestack.h
1414
#define sk_X509_EXTENSION_find(st, val) SKM_sk_find(X509_EXTENSION, (st), (val))
lib/libcrypto/stack/safestack.h
1417
#define sk_X509_EXTENSION_insert(st, val, i) SKM_sk_insert(X509_EXTENSION, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1431
#define sk_X509_INFO_set(st, i, val) SKM_sk_set(X509_INFO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1433
#define sk_X509_INFO_push(st, val) SKM_sk_push(X509_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1434
#define sk_X509_INFO_unshift(st, val) SKM_sk_unshift(X509_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1435
#define sk_X509_INFO_find(st, val) SKM_sk_find(X509_INFO, (st), (val))
lib/libcrypto/stack/safestack.h
1438
#define sk_X509_INFO_insert(st, val, i) SKM_sk_insert(X509_INFO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1452
#define sk_X509_LOOKUP_set(st, i, val) SKM_sk_set(X509_LOOKUP, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1454
#define sk_X509_LOOKUP_push(st, val) SKM_sk_push(X509_LOOKUP, (st), (val))
lib/libcrypto/stack/safestack.h
1455
#define sk_X509_LOOKUP_unshift(st, val) SKM_sk_unshift(X509_LOOKUP, (st), (val))
lib/libcrypto/stack/safestack.h
1456
#define sk_X509_LOOKUP_find(st, val) SKM_sk_find(X509_LOOKUP, (st), (val))
lib/libcrypto/stack/safestack.h
1459
#define sk_X509_LOOKUP_insert(st, val, i) SKM_sk_insert(X509_LOOKUP, (st), (val), (i))
lib/libcrypto/stack/safestack.h
146
#define SKM_sk_insert(type, st,val, i) \
lib/libcrypto/stack/safestack.h
147
sk_insert(CHECKED_STACK_OF(type, st), CHECKED_PTR_OF(type, val), i)
lib/libcrypto/stack/safestack.h
1473
#define sk_X509_NAME_set(st, i, val) SKM_sk_set(X509_NAME, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1475
#define sk_X509_NAME_push(st, val) SKM_sk_push(X509_NAME, (st), (val))
lib/libcrypto/stack/safestack.h
1476
#define sk_X509_NAME_unshift(st, val) SKM_sk_unshift(X509_NAME, (st), (val))
lib/libcrypto/stack/safestack.h
1477
#define sk_X509_NAME_find(st, val) SKM_sk_find(X509_NAME, (st), (val))
lib/libcrypto/stack/safestack.h
1480
#define sk_X509_NAME_insert(st, val, i) SKM_sk_insert(X509_NAME, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1494
#define sk_X509_NAME_ENTRY_set(st, i, val) SKM_sk_set(X509_NAME_ENTRY, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1496
#define sk_X509_NAME_ENTRY_push(st, val) SKM_sk_push(X509_NAME_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
1497
#define sk_X509_NAME_ENTRY_unshift(st, val) SKM_sk_unshift(X509_NAME_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
1498
#define sk_X509_NAME_ENTRY_find(st, val) SKM_sk_find(X509_NAME_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
1501
#define sk_X509_NAME_ENTRY_insert(st, val, i) SKM_sk_insert(X509_NAME_ENTRY, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1515
#define sk_X509_OBJECT_set(st, i, val) SKM_sk_set(X509_OBJECT, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1517
#define sk_X509_OBJECT_push(st, val) SKM_sk_push(X509_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
1518
#define sk_X509_OBJECT_unshift(st, val) SKM_sk_unshift(X509_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
1519
#define sk_X509_OBJECT_find(st, val) SKM_sk_find(X509_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
1522
#define sk_X509_OBJECT_insert(st, val, i) SKM_sk_insert(X509_OBJECT, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1536
#define sk_X509_REVOKED_set(st, i, val) SKM_sk_set(X509_REVOKED, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1538
#define sk_X509_REVOKED_push(st, val) SKM_sk_push(X509_REVOKED, (st), (val))
lib/libcrypto/stack/safestack.h
1539
#define sk_X509_REVOKED_unshift(st, val) SKM_sk_unshift(X509_REVOKED, (st), (val))
lib/libcrypto/stack/safestack.h
1540
#define sk_X509_REVOKED_find(st, val) SKM_sk_find(X509_REVOKED, (st), (val))
lib/libcrypto/stack/safestack.h
1543
#define sk_X509_REVOKED_insert(st, val, i) SKM_sk_insert(X509_REVOKED, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1557
#define sk_X509_VERIFY_PARAM_set(st, i, val) SKM_sk_set(X509_VERIFY_PARAM, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1559
#define sk_X509_VERIFY_PARAM_push(st, val) SKM_sk_push(X509_VERIFY_PARAM, (st), (val))
lib/libcrypto/stack/safestack.h
1560
#define sk_X509_VERIFY_PARAM_unshift(st, val) SKM_sk_unshift(X509_VERIFY_PARAM, (st), (val))
lib/libcrypto/stack/safestack.h
1561
#define sk_X509_VERIFY_PARAM_find(st, val) SKM_sk_find(X509_VERIFY_PARAM, (st), (val))
lib/libcrypto/stack/safestack.h
1564
#define sk_X509_VERIFY_PARAM_insert(st, val, i) SKM_sk_insert(X509_VERIFY_PARAM, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1578
#define sk_void_set(st, i, val) SKM_sk_set(void, (st), (i), (val))
lib/libcrypto/stack/safestack.h
1580
#define sk_void_push(st, val) SKM_sk_push(void, (st), (val))
lib/libcrypto/stack/safestack.h
1581
#define sk_void_unshift(st, val) SKM_sk_unshift(void, (st), (val))
lib/libcrypto/stack/safestack.h
1582
#define sk_void_find(st, val) SKM_sk_find(void, (st), (val))
lib/libcrypto/stack/safestack.h
1585
#define sk_void_insert(st, val, i) SKM_sk_insert(void, (st), (val), (i))
lib/libcrypto/stack/safestack.h
1596
#define sk_OPENSSL_STRING_push(st, val) sk_push(CHECKED_STACK_OF(OPENSSL_STRING, st), CHECKED_PTR_OF(char, val))
lib/libcrypto/stack/safestack.h
1597
#define sk_OPENSSL_STRING_find(st, val) sk_find(CHECKED_STACK_OF(OPENSSL_STRING, st), CHECKED_PTR_OF(char, val))
lib/libcrypto/stack/safestack.h
1601
#define sk_OPENSSL_STRING_insert(st, val, i) sk_insert(CHECKED_STACK_OF(OPENSSL_STRING, st), CHECKED_PTR_OF(char, val), i)
lib/libcrypto/stack/safestack.h
1603
#define sk_OPENSSL_STRING_set(st, i, val) sk_set(CHECKED_STACK_OF(OPENSSL_STRING, st), i, CHECKED_PTR_OF(char, val))
lib/libcrypto/stack/safestack.h
1605
#define sk_OPENSSL_STRING_unshift(st, val) sk_unshift(CHECKED_STACK_OF(OPENSSL_STRING, st), CHECKED_PTR_OF(char, val))
lib/libcrypto/stack/safestack.h
1619
#define sk_OPENSSL_PSTRING_push(st, val) sk_push(CHECKED_STACK_OF(OPENSSL_PSTRING, st), CHECKED_PTR_OF(OPENSSL_STRING, val))
lib/libcrypto/stack/safestack.h
1620
#define sk_OPENSSL_PSTRING_find(st, val) sk_find(CHECKED_STACK_OF(OPENSSL_PSTRING, st), CHECKED_PTR_OF(OPENSSL_STRING, val))
lib/libcrypto/stack/safestack.h
1624
#define sk_OPENSSL_PSTRING_insert(st, val, i) sk_insert(CHECKED_STACK_OF(OPENSSL_PSTRING, st), CHECKED_PTR_OF(OPENSSL_STRING, val), i)
lib/libcrypto/stack/safestack.h
1626
#define sk_OPENSSL_PSTRING_set(st, i, val) sk_set(CHECKED_STACK_OF(OPENSSL_PSTRING, st), i, CHECKED_PTR_OF(OPENSSL_STRING, val))
lib/libcrypto/stack/safestack.h
1628
#define sk_OPENSSL_PSTRING_unshift(st, val) sk_unshift(CHECKED_STACK_OF(OPENSSL_PSTRING, st), CHECKED_PTR_OF(OPENSSL_STRING, val))
lib/libcrypto/stack/safestack.h
169
#define sk_ACCESS_DESCRIPTION_set(st, i, val) SKM_sk_set(ACCESS_DESCRIPTION, (st), (i), (val))
lib/libcrypto/stack/safestack.h
171
#define sk_ACCESS_DESCRIPTION_push(st, val) SKM_sk_push(ACCESS_DESCRIPTION, (st), (val))
lib/libcrypto/stack/safestack.h
172
#define sk_ACCESS_DESCRIPTION_unshift(st, val) SKM_sk_unshift(ACCESS_DESCRIPTION, (st), (val))
lib/libcrypto/stack/safestack.h
173
#define sk_ACCESS_DESCRIPTION_find(st, val) SKM_sk_find(ACCESS_DESCRIPTION, (st), (val))
lib/libcrypto/stack/safestack.h
176
#define sk_ACCESS_DESCRIPTION_insert(st, val, i) SKM_sk_insert(ACCESS_DESCRIPTION, (st), (val), (i))
lib/libcrypto/stack/safestack.h
190
#define sk_ASIdOrRange_set(st, i, val) SKM_sk_set(ASIdOrRange, (st), (i), (val))
lib/libcrypto/stack/safestack.h
192
#define sk_ASIdOrRange_push(st, val) SKM_sk_push(ASIdOrRange, (st), (val))
lib/libcrypto/stack/safestack.h
193
#define sk_ASIdOrRange_unshift(st, val) SKM_sk_unshift(ASIdOrRange, (st), (val))
lib/libcrypto/stack/safestack.h
194
#define sk_ASIdOrRange_find(st, val) SKM_sk_find(ASIdOrRange, (st), (val))
lib/libcrypto/stack/safestack.h
197
#define sk_ASIdOrRange_insert(st, val, i) SKM_sk_insert(ASIdOrRange, (st), (val), (i))
lib/libcrypto/stack/safestack.h
211
#define sk_ASN1_GENERALSTRING_set(st, i, val) SKM_sk_set(ASN1_GENERALSTRING, (st), (i), (val))
lib/libcrypto/stack/safestack.h
213
#define sk_ASN1_GENERALSTRING_push(st, val) SKM_sk_push(ASN1_GENERALSTRING, (st), (val))
lib/libcrypto/stack/safestack.h
214
#define sk_ASN1_GENERALSTRING_unshift(st, val) SKM_sk_unshift(ASN1_GENERALSTRING, (st), (val))
lib/libcrypto/stack/safestack.h
215
#define sk_ASN1_GENERALSTRING_find(st, val) SKM_sk_find(ASN1_GENERALSTRING, (st), (val))
lib/libcrypto/stack/safestack.h
218
#define sk_ASN1_GENERALSTRING_insert(st, val, i) SKM_sk_insert(ASN1_GENERALSTRING, (st), (val), (i))
lib/libcrypto/stack/safestack.h
232
#define sk_ASN1_INTEGER_set(st, i, val) SKM_sk_set(ASN1_INTEGER, (st), (i), (val))
lib/libcrypto/stack/safestack.h
234
#define sk_ASN1_INTEGER_push(st, val) SKM_sk_push(ASN1_INTEGER, (st), (val))
lib/libcrypto/stack/safestack.h
235
#define sk_ASN1_INTEGER_unshift(st, val) SKM_sk_unshift(ASN1_INTEGER, (st), (val))
lib/libcrypto/stack/safestack.h
236
#define sk_ASN1_INTEGER_find(st, val) SKM_sk_find(ASN1_INTEGER, (st), (val))
lib/libcrypto/stack/safestack.h
239
#define sk_ASN1_INTEGER_insert(st, val, i) SKM_sk_insert(ASN1_INTEGER, (st), (val), (i))
lib/libcrypto/stack/safestack.h
253
#define sk_ASN1_OBJECT_set(st, i, val) SKM_sk_set(ASN1_OBJECT, (st), (i), (val))
lib/libcrypto/stack/safestack.h
255
#define sk_ASN1_OBJECT_push(st, val) SKM_sk_push(ASN1_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
256
#define sk_ASN1_OBJECT_unshift(st, val) SKM_sk_unshift(ASN1_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
257
#define sk_ASN1_OBJECT_find(st, val) SKM_sk_find(ASN1_OBJECT, (st), (val))
lib/libcrypto/stack/safestack.h
260
#define sk_ASN1_OBJECT_insert(st, val, i) SKM_sk_insert(ASN1_OBJECT, (st), (val), (i))
lib/libcrypto/stack/safestack.h
274
#define sk_ASN1_TYPE_set(st, i, val) SKM_sk_set(ASN1_TYPE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
276
#define sk_ASN1_TYPE_push(st, val) SKM_sk_push(ASN1_TYPE, (st), (val))
lib/libcrypto/stack/safestack.h
277
#define sk_ASN1_TYPE_unshift(st, val) SKM_sk_unshift(ASN1_TYPE, (st), (val))
lib/libcrypto/stack/safestack.h
278
#define sk_ASN1_TYPE_find(st, val) SKM_sk_find(ASN1_TYPE, (st), (val))
lib/libcrypto/stack/safestack.h
281
#define sk_ASN1_TYPE_insert(st, val, i) SKM_sk_insert(ASN1_TYPE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
295
#define sk_ASN1_UTF8STRING_set(st, i, val) SKM_sk_set(ASN1_UTF8STRING, (st), (i), (val))
lib/libcrypto/stack/safestack.h
297
#define sk_ASN1_UTF8STRING_push(st, val) SKM_sk_push(ASN1_UTF8STRING, (st), (val))
lib/libcrypto/stack/safestack.h
298
#define sk_ASN1_UTF8STRING_unshift(st, val) SKM_sk_unshift(ASN1_UTF8STRING, (st), (val))
lib/libcrypto/stack/safestack.h
299
#define sk_ASN1_UTF8STRING_find(st, val) SKM_sk_find(ASN1_UTF8STRING, (st), (val))
lib/libcrypto/stack/safestack.h
302
#define sk_ASN1_UTF8STRING_insert(st, val, i) SKM_sk_insert(ASN1_UTF8STRING, (st), (val), (i))
lib/libcrypto/stack/safestack.h
316
#define sk_ASN1_VALUE_set(st, i, val) SKM_sk_set(ASN1_VALUE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
318
#define sk_ASN1_VALUE_push(st, val) SKM_sk_push(ASN1_VALUE, (st), (val))
lib/libcrypto/stack/safestack.h
319
#define sk_ASN1_VALUE_unshift(st, val) SKM_sk_unshift(ASN1_VALUE, (st), (val))
lib/libcrypto/stack/safestack.h
320
#define sk_ASN1_VALUE_find(st, val) SKM_sk_find(ASN1_VALUE, (st), (val))
lib/libcrypto/stack/safestack.h
323
#define sk_ASN1_VALUE_insert(st, val, i) SKM_sk_insert(ASN1_VALUE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
337
#define sk_BIO_set(st, i, val) SKM_sk_set(BIO, (st), (i), (val))
lib/libcrypto/stack/safestack.h
339
#define sk_BIO_push(st, val) SKM_sk_push(BIO, (st), (val))
lib/libcrypto/stack/safestack.h
340
#define sk_BIO_unshift(st, val) SKM_sk_unshift(BIO, (st), (val))
lib/libcrypto/stack/safestack.h
341
#define sk_BIO_find(st, val) SKM_sk_find(BIO, (st), (val))
lib/libcrypto/stack/safestack.h
344
#define sk_BIO_insert(st, val, i) SKM_sk_insert(BIO, (st), (val), (i))
lib/libcrypto/stack/safestack.h
358
#define sk_BY_DIR_ENTRY_set(st, i, val) SKM_sk_set(BY_DIR_ENTRY, (st), (i), (val))
lib/libcrypto/stack/safestack.h
360
#define sk_BY_DIR_ENTRY_push(st, val) SKM_sk_push(BY_DIR_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
361
#define sk_BY_DIR_ENTRY_unshift(st, val) SKM_sk_unshift(BY_DIR_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
362
#define sk_BY_DIR_ENTRY_find(st, val) SKM_sk_find(BY_DIR_ENTRY, (st), (val))
lib/libcrypto/stack/safestack.h
365
#define sk_BY_DIR_ENTRY_insert(st, val, i) SKM_sk_insert(BY_DIR_ENTRY, (st), (val), (i))
lib/libcrypto/stack/safestack.h
379
#define sk_BY_DIR_HASH_set(st, i, val) SKM_sk_set(BY_DIR_HASH, (st), (i), (val))
lib/libcrypto/stack/safestack.h
381
#define sk_BY_DIR_HASH_push(st, val) SKM_sk_push(BY_DIR_HASH, (st), (val))
lib/libcrypto/stack/safestack.h
382
#define sk_BY_DIR_HASH_unshift(st, val) SKM_sk_unshift(BY_DIR_HASH, (st), (val))
lib/libcrypto/stack/safestack.h
383
#define sk_BY_DIR_HASH_find(st, val) SKM_sk_find(BY_DIR_HASH, (st), (val))
lib/libcrypto/stack/safestack.h
386
#define sk_BY_DIR_HASH_insert(st, val, i) SKM_sk_insert(BY_DIR_HASH, (st), (val), (i))
lib/libcrypto/stack/safestack.h
400
#define sk_CMS_CertificateChoices_set(st, i, val) SKM_sk_set(CMS_CertificateChoices, (st), (i), (val))
lib/libcrypto/stack/safestack.h
402
#define sk_CMS_CertificateChoices_push(st, val) SKM_sk_push(CMS_CertificateChoices, (st), (val))
lib/libcrypto/stack/safestack.h
403
#define sk_CMS_CertificateChoices_unshift(st, val) SKM_sk_unshift(CMS_CertificateChoices, (st), (val))
lib/libcrypto/stack/safestack.h
404
#define sk_CMS_CertificateChoices_find(st, val) SKM_sk_find(CMS_CertificateChoices, (st), (val))
lib/libcrypto/stack/safestack.h
407
#define sk_CMS_CertificateChoices_insert(st, val, i) SKM_sk_insert(CMS_CertificateChoices, (st), (val), (i))
lib/libcrypto/stack/safestack.h
421
#define sk_CMS_RecipientEncryptedKey_set(st, i, val) SKM_sk_set(CMS_RecipientEncryptedKey, (st), (i), (val))
lib/libcrypto/stack/safestack.h
423
#define sk_CMS_RecipientEncryptedKey_push(st, val) SKM_sk_push(CMS_RecipientEncryptedKey, (st), (val))
lib/libcrypto/stack/safestack.h
424
#define sk_CMS_RecipientEncryptedKey_unshift(st, val) SKM_sk_unshift(CMS_RecipientEncryptedKey, (st), (val))
lib/libcrypto/stack/safestack.h
425
#define sk_CMS_RecipientEncryptedKey_find(st, val) SKM_sk_find(CMS_RecipientEncryptedKey, (st), (val))
lib/libcrypto/stack/safestack.h
428
#define sk_CMS_RecipientEncryptedKey_insert(st, val, i) SKM_sk_insert(CMS_RecipientEncryptedKey, (st), (val), (i))
lib/libcrypto/stack/safestack.h
442
#define sk_CMS_RecipientInfo_set(st, i, val) SKM_sk_set(CMS_RecipientInfo, (st), (i), (val))
lib/libcrypto/stack/safestack.h
444
#define sk_CMS_RecipientInfo_push(st, val) SKM_sk_push(CMS_RecipientInfo, (st), (val))
lib/libcrypto/stack/safestack.h
445
#define sk_CMS_RecipientInfo_unshift(st, val) SKM_sk_unshift(CMS_RecipientInfo, (st), (val))
lib/libcrypto/stack/safestack.h
446
#define sk_CMS_RecipientInfo_find(st, val) SKM_sk_find(CMS_RecipientInfo, (st), (val))
lib/libcrypto/stack/safestack.h
449
#define sk_CMS_RecipientInfo_insert(st, val, i) SKM_sk_insert(CMS_RecipientInfo, (st), (val), (i))
lib/libcrypto/stack/safestack.h
463
#define sk_CMS_RevocationInfoChoice_set(st, i, val) SKM_sk_set(CMS_RevocationInfoChoice, (st), (i), (val))
lib/libcrypto/stack/safestack.h
465
#define sk_CMS_RevocationInfoChoice_push(st, val) SKM_sk_push(CMS_RevocationInfoChoice, (st), (val))
lib/libcrypto/stack/safestack.h
466
#define sk_CMS_RevocationInfoChoice_unshift(st, val) SKM_sk_unshift(CMS_RevocationInfoChoice, (st), (val))
lib/libcrypto/stack/safestack.h
467
#define sk_CMS_RevocationInfoChoice_find(st, val) SKM_sk_find(CMS_RevocationInfoChoice, (st), (val))
lib/libcrypto/stack/safestack.h
470
#define sk_CMS_RevocationInfoChoice_insert(st, val, i) SKM_sk_insert(CMS_RevocationInfoChoice, (st), (val), (i))
lib/libcrypto/stack/safestack.h
484
#define sk_CMS_SignerInfo_set(st, i, val) SKM_sk_set(CMS_SignerInfo, (st), (i), (val))
lib/libcrypto/stack/safestack.h
486
#define sk_CMS_SignerInfo_push(st, val) SKM_sk_push(CMS_SignerInfo, (st), (val))
lib/libcrypto/stack/safestack.h
487
#define sk_CMS_SignerInfo_unshift(st, val) SKM_sk_unshift(CMS_SignerInfo, (st), (val))
lib/libcrypto/stack/safestack.h
488
#define sk_CMS_SignerInfo_find(st, val) SKM_sk_find(CMS_SignerInfo, (st), (val))
lib/libcrypto/stack/safestack.h
491
#define sk_CMS_SignerInfo_insert(st, val, i) SKM_sk_insert(CMS_SignerInfo, (st), (val), (i))
lib/libcrypto/stack/safestack.h
505
#define sk_CONF_IMODULE_set(st, i, val) SKM_sk_set(CONF_IMODULE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
507
#define sk_CONF_IMODULE_push(st, val) SKM_sk_push(CONF_IMODULE, (st), (val))
lib/libcrypto/stack/safestack.h
508
#define sk_CONF_IMODULE_unshift(st, val) SKM_sk_unshift(CONF_IMODULE, (st), (val))
lib/libcrypto/stack/safestack.h
509
#define sk_CONF_IMODULE_find(st, val) SKM_sk_find(CONF_IMODULE, (st), (val))
lib/libcrypto/stack/safestack.h
512
#define sk_CONF_IMODULE_insert(st, val, i) SKM_sk_insert(CONF_IMODULE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
526
#define sk_CONF_MODULE_set(st, i, val) SKM_sk_set(CONF_MODULE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
528
#define sk_CONF_MODULE_push(st, val) SKM_sk_push(CONF_MODULE, (st), (val))
lib/libcrypto/stack/safestack.h
529
#define sk_CONF_MODULE_unshift(st, val) SKM_sk_unshift(CONF_MODULE, (st), (val))
lib/libcrypto/stack/safestack.h
530
#define sk_CONF_MODULE_find(st, val) SKM_sk_find(CONF_MODULE, (st), (val))
lib/libcrypto/stack/safestack.h
533
#define sk_CONF_MODULE_insert(st, val, i) SKM_sk_insert(CONF_MODULE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
547
#define sk_CONF_VALUE_set(st, i, val) SKM_sk_set(CONF_VALUE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
549
#define sk_CONF_VALUE_push(st, val) SKM_sk_push(CONF_VALUE, (st), (val))
lib/libcrypto/stack/safestack.h
550
#define sk_CONF_VALUE_unshift(st, val) SKM_sk_unshift(CONF_VALUE, (st), (val))
lib/libcrypto/stack/safestack.h
551
#define sk_CONF_VALUE_find(st, val) SKM_sk_find(CONF_VALUE, (st), (val))
lib/libcrypto/stack/safestack.h
554
#define sk_CONF_VALUE_insert(st, val, i) SKM_sk_insert(CONF_VALUE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
568
#define sk_CRYPTO_dynlock_set(st, i, val) SKM_sk_set(CRYPTO_dynlock, (st), (i), (val))
lib/libcrypto/stack/safestack.h
570
#define sk_CRYPTO_dynlock_push(st, val) SKM_sk_push(CRYPTO_dynlock, (st), (val))
lib/libcrypto/stack/safestack.h
571
#define sk_CRYPTO_dynlock_unshift(st, val) SKM_sk_unshift(CRYPTO_dynlock, (st), (val))
lib/libcrypto/stack/safestack.h
572
#define sk_CRYPTO_dynlock_find(st, val) SKM_sk_find(CRYPTO_dynlock, (st), (val))
lib/libcrypto/stack/safestack.h
575
#define sk_CRYPTO_dynlock_insert(st, val, i) SKM_sk_insert(CRYPTO_dynlock, (st), (val), (i))
lib/libcrypto/stack/safestack.h
589
#define sk_CTLOG_set(st, i, val) SKM_sk_set(CTLOG, (st), (i), (val))
lib/libcrypto/stack/safestack.h
591
#define sk_CTLOG_push(st, val) SKM_sk_push(CTLOG, (st), (val))
lib/libcrypto/stack/safestack.h
592
#define sk_CTLOG_unshift(st, val) SKM_sk_unshift(CTLOG, (st), (val))
lib/libcrypto/stack/safestack.h
593
#define sk_CTLOG_find(st, val) SKM_sk_find(CTLOG, (st), (val))
lib/libcrypto/stack/safestack.h
596
#define sk_CTLOG_insert(st, val, i) SKM_sk_insert(CTLOG, (st), (val), (i))
lib/libcrypto/stack/safestack.h
610
#define sk_DIST_POINT_set(st, i, val) SKM_sk_set(DIST_POINT, (st), (i), (val))
lib/libcrypto/stack/safestack.h
612
#define sk_DIST_POINT_push(st, val) SKM_sk_push(DIST_POINT, (st), (val))
lib/libcrypto/stack/safestack.h
613
#define sk_DIST_POINT_unshift(st, val) SKM_sk_unshift(DIST_POINT, (st), (val))
lib/libcrypto/stack/safestack.h
614
#define sk_DIST_POINT_find(st, val) SKM_sk_find(DIST_POINT, (st), (val))
lib/libcrypto/stack/safestack.h
617
#define sk_DIST_POINT_insert(st, val, i) SKM_sk_insert(DIST_POINT, (st), (val), (i))
lib/libcrypto/stack/safestack.h
631
#define sk_ESS_CERT_ID_set(st, i, val) SKM_sk_set(ESS_CERT_ID, (st), (i), (val))
lib/libcrypto/stack/safestack.h
633
#define sk_ESS_CERT_ID_push(st, val) SKM_sk_push(ESS_CERT_ID, (st), (val))
lib/libcrypto/stack/safestack.h
634
#define sk_ESS_CERT_ID_unshift(st, val) SKM_sk_unshift(ESS_CERT_ID, (st), (val))
lib/libcrypto/stack/safestack.h
635
#define sk_ESS_CERT_ID_find(st, val) SKM_sk_find(ESS_CERT_ID, (st), (val))
lib/libcrypto/stack/safestack.h
638
#define sk_ESS_CERT_ID_insert(st, val, i) SKM_sk_insert(ESS_CERT_ID, (st), (val), (i))
lib/libcrypto/stack/safestack.h
653
#define sk_ESS_CERT_ID_V2_set(st, i, val) SKM_sk_set(ESS_CERT_ID_V2, (st), (i), (val))
lib/libcrypto/stack/safestack.h
655
#define sk_ESS_CERT_ID_V2_push(st, val) SKM_sk_push(ESS_CERT_ID_V2, (st), (val))
lib/libcrypto/stack/safestack.h
656
#define sk_ESS_CERT_ID_V2_unshift(st, val) SKM_sk_unshift(ESS_CERT_ID_V2, (st), (val))
lib/libcrypto/stack/safestack.h
657
#define sk_ESS_CERT_ID_V2_find(st, val) SKM_sk_find(ESS_CERT_ID_V2, (st), (val))
lib/libcrypto/stack/safestack.h
660
#define sk_ESS_CERT_ID_V2_insert(st, val, i) SKM_sk_insert(ESS_CERT_ID_V2, (st), (val), (i))
lib/libcrypto/stack/safestack.h
675
#define sk_EVP_MD_set(st, i, val) SKM_sk_set(EVP_MD, (st), (i), (val))
lib/libcrypto/stack/safestack.h
677
#define sk_EVP_MD_push(st, val) SKM_sk_push(EVP_MD, (st), (val))
lib/libcrypto/stack/safestack.h
678
#define sk_EVP_MD_unshift(st, val) SKM_sk_unshift(EVP_MD, (st), (val))
lib/libcrypto/stack/safestack.h
679
#define sk_EVP_MD_find(st, val) SKM_sk_find(EVP_MD, (st), (val))
lib/libcrypto/stack/safestack.h
682
#define sk_EVP_MD_insert(st, val, i) SKM_sk_insert(EVP_MD, (st), (val), (i))
lib/libcrypto/stack/safestack.h
696
#define sk_EVP_PKEY_ASN1_METHOD_set(st, i, val) SKM_sk_set(EVP_PKEY_ASN1_METHOD, (st), (i), (val))
lib/libcrypto/stack/safestack.h
698
#define sk_EVP_PKEY_ASN1_METHOD_push(st, val) SKM_sk_push(EVP_PKEY_ASN1_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
699
#define sk_EVP_PKEY_ASN1_METHOD_unshift(st, val) SKM_sk_unshift(EVP_PKEY_ASN1_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
700
#define sk_EVP_PKEY_ASN1_METHOD_find(st, val) SKM_sk_find(EVP_PKEY_ASN1_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
703
#define sk_EVP_PKEY_ASN1_METHOD_insert(st, val, i) SKM_sk_insert(EVP_PKEY_ASN1_METHOD, (st), (val), (i))
lib/libcrypto/stack/safestack.h
717
#define sk_EVP_PKEY_METHOD_set(st, i, val) SKM_sk_set(EVP_PKEY_METHOD, (st), (i), (val))
lib/libcrypto/stack/safestack.h
719
#define sk_EVP_PKEY_METHOD_push(st, val) SKM_sk_push(EVP_PKEY_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
720
#define sk_EVP_PKEY_METHOD_unshift(st, val) SKM_sk_unshift(EVP_PKEY_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
721
#define sk_EVP_PKEY_METHOD_find(st, val) SKM_sk_find(EVP_PKEY_METHOD, (st), (val))
lib/libcrypto/stack/safestack.h
724
#define sk_EVP_PKEY_METHOD_insert(st, val, i) SKM_sk_insert(EVP_PKEY_METHOD, (st), (val), (i))
lib/libcrypto/stack/safestack.h
738
#define sk_GENERAL_NAME_set(st, i, val) SKM_sk_set(GENERAL_NAME, (st), (i), (val))
lib/libcrypto/stack/safestack.h
740
#define sk_GENERAL_NAME_push(st, val) SKM_sk_push(GENERAL_NAME, (st), (val))
lib/libcrypto/stack/safestack.h
741
#define sk_GENERAL_NAME_unshift(st, val) SKM_sk_unshift(GENERAL_NAME, (st), (val))
lib/libcrypto/stack/safestack.h
742
#define sk_GENERAL_NAME_find(st, val) SKM_sk_find(GENERAL_NAME, (st), (val))
lib/libcrypto/stack/safestack.h
745
#define sk_GENERAL_NAME_insert(st, val, i) SKM_sk_insert(GENERAL_NAME, (st), (val), (i))
lib/libcrypto/stack/safestack.h
759
#define sk_GENERAL_NAMES_set(st, i, val) SKM_sk_set(GENERAL_NAMES, (st), (i), (val))
lib/libcrypto/stack/safestack.h
761
#define sk_GENERAL_NAMES_push(st, val) SKM_sk_push(GENERAL_NAMES, (st), (val))
lib/libcrypto/stack/safestack.h
762
#define sk_GENERAL_NAMES_unshift(st, val) SKM_sk_unshift(GENERAL_NAMES, (st), (val))
lib/libcrypto/stack/safestack.h
763
#define sk_GENERAL_NAMES_find(st, val) SKM_sk_find(GENERAL_NAMES, (st), (val))
lib/libcrypto/stack/safestack.h
766
#define sk_GENERAL_NAMES_insert(st, val, i) SKM_sk_insert(GENERAL_NAMES, (st), (val), (i))
lib/libcrypto/stack/safestack.h
780
#define sk_GENERAL_SUBTREE_set(st, i, val) SKM_sk_set(GENERAL_SUBTREE, (st), (i), (val))
lib/libcrypto/stack/safestack.h
782
#define sk_GENERAL_SUBTREE_push(st, val) SKM_sk_push(GENERAL_SUBTREE, (st), (val))
lib/libcrypto/stack/safestack.h
783
#define sk_GENERAL_SUBTREE_unshift(st, val) SKM_sk_unshift(GENERAL_SUBTREE, (st), (val))
lib/libcrypto/stack/safestack.h
784
#define sk_GENERAL_SUBTREE_find(st, val) SKM_sk_find(GENERAL_SUBTREE, (st), (val))
lib/libcrypto/stack/safestack.h
787
#define sk_GENERAL_SUBTREE_insert(st, val, i) SKM_sk_insert(GENERAL_SUBTREE, (st), (val), (i))
lib/libcrypto/stack/safestack.h
801
#define sk_IPAddressFamily_set(st, i, val) SKM_sk_set(IPAddressFamily, (st), (i), (val))
lib/libcrypto/stack/safestack.h
803
#define sk_IPAddressFamily_push(st, val) SKM_sk_push(IPAddressFamily, (st), (val))
lib/libcrypto/stack/safestack.h
804
#define sk_IPAddressFamily_unshift(st, val) SKM_sk_unshift(IPAddressFamily, (st), (val))
lib/libcrypto/stack/safestack.h
805
#define sk_IPAddressFamily_find(st, val) SKM_sk_find(IPAddressFamily, (st), (val))
lib/libcrypto/stack/safestack.h
808
#define sk_IPAddressFamily_insert(st, val, i) SKM_sk_insert(IPAddressFamily, (st), (val), (i))
lib/libcrypto/stack/safestack.h
822
#define sk_IPAddressOrRange_set(st, i, val) SKM_sk_set(IPAddressOrRange, (st), (i), (val))
lib/libcrypto/stack/safestack.h
824
#define sk_IPAddressOrRange_push(st, val) SKM_sk_push(IPAddressOrRange, (st), (val))
lib/libcrypto/stack/safestack.h
825
#define sk_IPAddressOrRange_unshift(st, val) SKM_sk_unshift(IPAddressOrRange, (st), (val))
lib/libcrypto/stack/safestack.h
826
#define sk_IPAddressOrRange_find(st, val) SKM_sk_find(IPAddressOrRange, (st), (val))
lib/libcrypto/stack/safestack.h
829
#define sk_IPAddressOrRange_insert(st, val, i) SKM_sk_insert(IPAddressOrRange, (st), (val), (i))
lib/libcrypto/stack/safestack.h
843
#define sk_MIME_HEADER_set(st, i, val) SKM_sk_set(MIME_HEADER, (st), (i), (val))
lib/libcrypto/stack/safestack.h
845
#define sk_MIME_HEADER_push(st, val) SKM_sk_push(MIME_HEADER, (st), (val))
lib/libcrypto/stack/safestack.h
846
#define sk_MIME_HEADER_unshift(st, val) SKM_sk_unshift(MIME_HEADER, (st), (val))
lib/libcrypto/stack/safestack.h
847
#define sk_MIME_HEADER_find(st, val) SKM_sk_find(MIME_HEADER, (st), (val))
lib/libcrypto/stack/safestack.h
850
#define sk_MIME_HEADER_insert(st, val, i) SKM_sk_insert(MIME_HEADER, (st), (val), (i))
lib/libcrypto/stack/safestack.h
864
#define sk_MIME_PARAM_set(st, i, val) SKM_sk_set(MIME_PARAM, (st), (i), (val))
lib/libcrypto/stack/safestack.h
866
#define sk_MIME_PARAM_push(st, val) SKM_sk_push(MIME_PARAM, (st), (val))
lib/libcrypto/stack/safestack.h
867
#define sk_MIME_PARAM_unshift(st, val) SKM_sk_unshift(MIME_PARAM, (st), (val))
lib/libcrypto/stack/safestack.h
868
#define sk_MIME_PARAM_find(st, val) SKM_sk_find(MIME_PARAM, (st), (val))
lib/libcrypto/stack/safestack.h
871
#define sk_MIME_PARAM_insert(st, val, i) SKM_sk_insert(MIME_PARAM, (st), (val), (i))
lib/libcrypto/stack/safestack.h
885
#define sk_NAME_FUNCS_set(st, i, val) SKM_sk_set(NAME_FUNCS, (st), (i), (val))
lib/libcrypto/stack/safestack.h
887
#define sk_NAME_FUNCS_push(st, val) SKM_sk_push(NAME_FUNCS, (st), (val))
lib/libcrypto/stack/safestack.h
888
#define sk_NAME_FUNCS_unshift(st, val) SKM_sk_unshift(NAME_FUNCS, (st), (val))
lib/libcrypto/stack/safestack.h
889
#define sk_NAME_FUNCS_find(st, val) SKM_sk_find(NAME_FUNCS, (st), (val))
lib/libcrypto/stack/safestack.h
892
#define sk_NAME_FUNCS_insert(st, val, i) SKM_sk_insert(NAME_FUNCS, (st), (val), (i))
lib/libcrypto/stack/safestack.h
906
#define sk_OCSP_CERTID_set(st, i, val) SKM_sk_set(OCSP_CERTID, (st), (i), (val))
lib/libcrypto/stack/safestack.h
908
#define sk_OCSP_CERTID_push(st, val) SKM_sk_push(OCSP_CERTID, (st), (val))
lib/libcrypto/stack/safestack.h
909
#define sk_OCSP_CERTID_unshift(st, val) SKM_sk_unshift(OCSP_CERTID, (st), (val))
lib/libcrypto/stack/safestack.h
910
#define sk_OCSP_CERTID_find(st, val) SKM_sk_find(OCSP_CERTID, (st), (val))
lib/libcrypto/stack/safestack.h
913
#define sk_OCSP_CERTID_insert(st, val, i) SKM_sk_insert(OCSP_CERTID, (st), (val), (i))
lib/libcrypto/stack/safestack.h
927
#define sk_OCSP_ONEREQ_set(st, i, val) SKM_sk_set(OCSP_ONEREQ, (st), (i), (val))
lib/libcrypto/stack/safestack.h
929
#define sk_OCSP_ONEREQ_push(st, val) SKM_sk_push(OCSP_ONEREQ, (st), (val))
lib/libcrypto/stack/safestack.h
930
#define sk_OCSP_ONEREQ_unshift(st, val) SKM_sk_unshift(OCSP_ONEREQ, (st), (val))
lib/libcrypto/stack/safestack.h
931
#define sk_OCSP_ONEREQ_find(st, val) SKM_sk_find(OCSP_ONEREQ, (st), (val))
lib/libcrypto/stack/safestack.h
934
#define sk_OCSP_ONEREQ_insert(st, val, i) SKM_sk_insert(OCSP_ONEREQ, (st), (val), (i))
lib/libcrypto/stack/safestack.h
948
#define sk_OCSP_RESPID_set(st, i, val) SKM_sk_set(OCSP_RESPID, (st), (i), (val))
lib/libcrypto/stack/safestack.h
950
#define sk_OCSP_RESPID_push(st, val) SKM_sk_push(OCSP_RESPID, (st), (val))
lib/libcrypto/stack/safestack.h
951
#define sk_OCSP_RESPID_unshift(st, val) SKM_sk_unshift(OCSP_RESPID, (st), (val))
lib/libcrypto/stack/safestack.h
952
#define sk_OCSP_RESPID_find(st, val) SKM_sk_find(OCSP_RESPID, (st), (val))
lib/libcrypto/stack/safestack.h
955
#define sk_OCSP_RESPID_insert(st, val, i) SKM_sk_insert(OCSP_RESPID, (st), (val), (i))
lib/libcrypto/stack/safestack.h
969
#define sk_OCSP_SINGLERESP_set(st, i, val) SKM_sk_set(OCSP_SINGLERESP, (st), (i), (val))
lib/libcrypto/stack/safestack.h
971
#define sk_OCSP_SINGLERESP_push(st, val) SKM_sk_push(OCSP_SINGLERESP, (st), (val))
lib/libcrypto/stack/safestack.h
972
#define sk_OCSP_SINGLERESP_unshift(st, val) SKM_sk_unshift(OCSP_SINGLERESP, (st), (val))
lib/libcrypto/stack/safestack.h
973
#define sk_OCSP_SINGLERESP_find(st, val) SKM_sk_find(OCSP_SINGLERESP, (st), (val))
lib/libcrypto/stack/safestack.h
976
#define sk_OCSP_SINGLERESP_insert(st, val, i) SKM_sk_insert(OCSP_SINGLERESP, (st), (val), (i))
lib/libcrypto/stack/safestack.h
990
#define sk_PKCS12_SAFEBAG_set(st, i, val) SKM_sk_set(PKCS12_SAFEBAG, (st), (i), (val))
lib/libcrypto/stack/safestack.h
992
#define sk_PKCS12_SAFEBAG_push(st, val) SKM_sk_push(PKCS12_SAFEBAG, (st), (val))
lib/libcrypto/stack/safestack.h
993
#define sk_PKCS12_SAFEBAG_unshift(st, val) SKM_sk_unshift(PKCS12_SAFEBAG, (st), (val))
lib/libcrypto/stack/safestack.h
994
#define sk_PKCS12_SAFEBAG_find(st, val) SKM_sk_find(PKCS12_SAFEBAG, (st), (val))
lib/libcrypto/stack/safestack.h
997
#define sk_PKCS12_SAFEBAG_insert(st, val, i) SKM_sk_insert(PKCS12_SAFEBAG, (st), (val), (i))
lib/libcrypto/ts/ts_conf.c
330
CONF_VALUE *val = sk_CONF_VALUE_value(list, i);
lib/libcrypto/ts/ts_conf.c
331
const char *extval = val->value ? val->value : val->name;
lib/libcrypto/ts/ts_conf.c
371
CONF_VALUE *val = sk_CONF_VALUE_value(list, i);
lib/libcrypto/ts/ts_conf.c
372
const char *extval = val->value ? val->value : val->name;
lib/libcrypto/ts/ts_conf.c
405
CONF_VALUE *val = sk_CONF_VALUE_value(list, i);
lib/libcrypto/ts/ts_conf.c
406
if (strcmp(val->name, ENV_VALUE_SECS) == 0) {
lib/libcrypto/ts/ts_conf.c
407
if (val->value) {
lib/libcrypto/ts/ts_conf.c
408
secs = strtonum(val->value, 0, INT_MAX,
lib/libcrypto/ts/ts_conf.c
416
} else if (strcmp(val->name, ENV_VALUE_MILLISECS) == 0) {
lib/libcrypto/ts/ts_conf.c
417
if (val->value) {
lib/libcrypto/ts/ts_conf.c
418
millis = strtonum(val->value, 1, 999, &errstr);
lib/libcrypto/ts/ts_conf.c
425
} else if (strcmp(val->name, ENV_VALUE_MICROSECS) == 0) {
lib/libcrypto/ts/ts_conf.c
426
if (val->value) {
lib/libcrypto/ts/ts_conf.c
427
micros = strtonum(val->value, 1, 999, &errstr);
lib/libcrypto/x509/x509_addr.c
1548
CONF_VALUE *val = sk_CONF_VALUE_value(values, i);
lib/libcrypto/x509/x509_addr.c
1555
if (!name_cmp(val->name, "IPv4")) {
lib/libcrypto/x509/x509_addr.c
1557
} else if (!name_cmp(val->name, "IPv6")) {
lib/libcrypto/x509/x509_addr.c
1559
} else if (!name_cmp(val->name, "IPv4-SAFI")) {
lib/libcrypto/x509/x509_addr.c
1562
} else if (!name_cmp(val->name, "IPv6-SAFI")) {
lib/libcrypto/x509/x509_addr.c
1567
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1592
parsed_safi = strtoul(val->value, &t, 0);
lib/libcrypto/x509/x509_addr.c
1595
if (val->value[0] == '\0' ||
lib/libcrypto/x509/x509_addr.c
1598
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1605
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1616
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1628
s = strdup(val->value);
lib/libcrypto/x509/x509_addr.c
1642
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1657
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1669
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1683
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1688
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1693
X509V3_conf_err(val);
lib/libcrypto/x509/x509_addr.c
1710
X509V3_conf_err(val);
lib/libcrypto/x509/x509_alt.c
397
GENERAL_NAME *val = sk_GENERAL_NAME_value(ialt, i);
lib/libcrypto/x509/x509_alt.c
399
if ((gen = GENERAL_NAME_dup(val)) == NULL)
lib/libcrypto/x509/x509_asid.c
847
CONF_VALUE *val = sk_CONF_VALUE_value(values, i);
lib/libcrypto/x509/x509_asid.c
853
if (!name_cmp(val->name, "AS")) {
lib/libcrypto/x509/x509_asid.c
855
} else if (!name_cmp(val->name, "RDI")) {
lib/libcrypto/x509/x509_asid.c
859
X509V3_conf_err(val);
lib/libcrypto/x509/x509_asid.c
866
if (strcmp(val->value, "inherit") == 0) {
lib/libcrypto/x509/x509_asid.c
870
X509V3_conf_err(val);
lib/libcrypto/x509/x509_asid.c
877
i1 = strspn(val->value, "0123456789");
lib/libcrypto/x509/x509_asid.c
878
if (val->value[i1] == '\0') {
lib/libcrypto/x509/x509_asid.c
882
i2 = i1 + strspn(val->value + i1, " \t");
lib/libcrypto/x509/x509_asid.c
883
if (val->value[i2] != '-') {
lib/libcrypto/x509/x509_asid.c
885
X509V3_conf_err(val);
lib/libcrypto/x509/x509_asid.c
889
i2 = i2 + strspn(val->value + i2, " \t");
lib/libcrypto/x509/x509_asid.c
890
i3 = i2 + strspn(val->value + i2, "0123456789");
lib/libcrypto/x509/x509_asid.c
891
if (val->value[i3] != '\0') {
lib/libcrypto/x509/x509_asid.c
893
X509V3_conf_err(val);
lib/libcrypto/x509/x509_asid.c
902
if (!X509V3_get_value_int(val, &min)) {
lib/libcrypto/x509/x509_asid.c
907
char *s = strdup(val->value);
lib/libcrypto/x509/x509_bcons.c
186
CONF_VALUE *val;
lib/libcrypto/x509/x509_bcons.c
194
val = sk_CONF_VALUE_value(values, i);
lib/libcrypto/x509/x509_bcons.c
195
if (!strcmp(val->name, "CA")) {
lib/libcrypto/x509/x509_bcons.c
196
if (!X509V3_get_value_bool(val, &bcons->ca))
lib/libcrypto/x509/x509_bcons.c
198
} else if (!strcmp(val->name, "pathlen")) {
lib/libcrypto/x509/x509_bcons.c
199
if (!X509V3_get_value_int(val, &bcons->pathlen))
lib/libcrypto/x509/x509_bcons.c
203
X509V3_conf_err(val);
lib/libcrypto/x509/x509_bitst.c
208
CONF_VALUE *val;
lib/libcrypto/x509/x509_bitst.c
218
val = sk_CONF_VALUE_value(nval, i);
lib/libcrypto/x509/x509_bitst.c
220
if (!strcmp(bnam->sname, val->name) ||
lib/libcrypto/x509/x509_bitst.c
221
!strcmp(bnam->lname, val->name) ) {
lib/libcrypto/x509/x509_bitst.c
233
X509V3_conf_err(val);
lib/libcrypto/x509/x509_conf.c
349
CONF_VALUE *val;
lib/libcrypto/x509/x509_conf.c
355
val = sk_CONF_VALUE_value(nval, i);
lib/libcrypto/x509/x509_conf.c
356
if (!(ext = X509V3_EXT_nconf(conf, ctx, val->name, val->value)))
lib/libcrypto/x509/x509_crld.c
695
char *name, *val;
lib/libcrypto/x509/x509_crld.c
704
val = cnf->value;
lib/libcrypto/x509/x509_crld.c
727
if (!set_reasons(&idp->onlysomereasons, val))
lib/libcrypto/x509/x509_extku.c
208
CONF_VALUE *val;
lib/libcrypto/x509/x509_extku.c
217
val = sk_CONF_VALUE_value(nval, i);
lib/libcrypto/x509/x509_extku.c
218
if (val->value)
lib/libcrypto/x509/x509_extku.c
219
extval = val->value;
lib/libcrypto/x509/x509_extku.c
221
extval = val->name;
lib/libcrypto/x509/x509_extku.c
225
X509V3_conf_err(val);
lib/libcrypto/x509/x509_ncons.c
204
CONF_VALUE tval, *val;
lib/libcrypto/x509/x509_ncons.c
213
val = sk_CONF_VALUE_value(nval, i);
lib/libcrypto/x509/x509_ncons.c
214
if (!strncmp(val->name, "permitted", 9) && val->name[9]) {
lib/libcrypto/x509/x509_ncons.c
216
tval.name = val->name + 10;
lib/libcrypto/x509/x509_ncons.c
217
} else if (!strncmp(val->name, "excluded", 8) && val->name[8]) {
lib/libcrypto/x509/x509_ncons.c
219
tval.name = val->name + 9;
lib/libcrypto/x509/x509_ncons.c
224
tval.value = val->value;
lib/libcrypto/x509/x509_pcons.c
174
CONF_VALUE *val;
lib/libcrypto/x509/x509_pcons.c
182
val = sk_CONF_VALUE_value(values, i);
lib/libcrypto/x509/x509_pcons.c
183
if (!strcmp(val->name, "requireExplicitPolicy")) {
lib/libcrypto/x509/x509_pcons.c
184
if (!X509V3_get_value_int(val,
lib/libcrypto/x509/x509_pcons.c
186
} else if (!strcmp(val->name, "inhibitPolicyMapping")) {
lib/libcrypto/x509/x509_pcons.c
187
if (!X509V3_get_value_int(val,
lib/libcrypto/x509/x509_pcons.c
191
X509V3_conf_err(val);
lib/libcrypto/x509/x509_pmaps.c
202
CONF_VALUE *val;
lib/libcrypto/x509/x509_pmaps.c
211
val = sk_CONF_VALUE_value(nval, i);
lib/libcrypto/x509/x509_pmaps.c
212
if (!val->value || !val->name) {
lib/libcrypto/x509/x509_pmaps.c
216
obj1 = OBJ_txt2obj(val->name, 0);
lib/libcrypto/x509/x509_pmaps.c
217
obj2 = OBJ_txt2obj(val->value, 0);
lib/libcrypto/x509/x509_pmaps.c
242
X509V3_conf_err(val);
lib/libcrypto/x509/x509_policy.c
100
#define sk_X509_POLICY_NODE_push(st, val) SKM_sk_push(X509_POLICY_NODE, (st), (val))
lib/libcrypto/x509/x509_policy.c
101
#define sk_X509_POLICY_NODE_unshift(st, val) SKM_sk_unshift(X509_POLICY_NODE, (st), (val))
lib/libcrypto/x509/x509_policy.c
102
#define sk_X509_POLICY_NODE_find(st, val) SKM_sk_find(X509_POLICY_NODE, (st), (val))
lib/libcrypto/x509/x509_policy.c
105
#define sk_X509_POLICY_NODE_insert(st, val, i) SKM_sk_insert(X509_POLICY_NODE, (st), (val), (i))
lib/libcrypto/x509/x509_policy.c
140
#define sk_X509_POLICY_LEVEL_set(st, i, val) SKM_sk_set(X509_POLICY_LEVEL, (st), (i), (val))
lib/libcrypto/x509/x509_policy.c
142
#define sk_X509_POLICY_LEVEL_push(st, val) SKM_sk_push(X509_POLICY_LEVEL, (st), (val))
lib/libcrypto/x509/x509_policy.c
143
#define sk_X509_POLICY_LEVEL_unshift(st, val) SKM_sk_unshift(X509_POLICY_LEVEL, (st), (val))
lib/libcrypto/x509/x509_policy.c
144
#define sk_X509_POLICY_LEVEL_find(st, val) SKM_sk_find(X509_POLICY_LEVEL, (st), (val))
lib/libcrypto/x509/x509_policy.c
147
#define sk_X509_POLICY_LEVEL_insert(st, val, i) SKM_sk_insert(X509_POLICY_LEVEL, (st), (val), (i))
lib/libcrypto/x509/x509_policy.c
98
#define sk_X509_POLICY_NODE_set(st, i, val) SKM_sk_set(X509_POLICY_NODE, (st), (i), (val))
lib/libcrypto/x509/x509_prn.c
67
X509V3_EXT_val_prn(BIO *out, STACK_OF(CONF_VALUE) *val, int indent, int ml)
lib/libcrypto/x509/x509_prn.c
72
if (!val)
lib/libcrypto/x509/x509_prn.c
74
if (!ml || !sk_CONF_VALUE_num(val)) {
lib/libcrypto/x509/x509_prn.c
76
if (!sk_CONF_VALUE_num(val))
lib/libcrypto/x509/x509_prn.c
79
for (i = 0; i < sk_CONF_VALUE_num(val); i++) {
lib/libcrypto/x509/x509_prn.c
84
nval = sk_CONF_VALUE_value(val, i);
lib/libcrypto/x509/x509v3.h
337
#define X509V3_conf_err(val) ERR_asprintf_error_data( \
lib/libcrypto/x509/x509v3.h
338
"section:%s,name:%s,value:%s", val->section, \
lib/libcrypto/x509/x509v3.h
339
val->name, val->value);
lib/libcrypto/x509/x509v3.h
603
void X509V3_conf_free(CONF_VALUE *val);
lib/libcrypto/x509/x509v3.h
648
void X509V3_EXT_val_prn(BIO *out, STACK_OF(CONF_VALUE) *val, int indent,
lib/libedit/keymacro.c
131
el->el_keymacro.val.cmd = (el_action_t) cmd;
lib/libedit/keymacro.c
132
return &el->el_keymacro.val;
lib/libedit/keymacro.c
143
el->el_keymacro.val.str = str;
lib/libedit/keymacro.c
144
return &el->el_keymacro.val;
lib/libedit/keymacro.c
173
keymacro_get(EditLine *el, wchar_t *ch, keymacro_value_t *val)
lib/libedit/keymacro.c
176
return node_trav(el, el->el_keymacro.map, ch, val);
lib/libedit/keymacro.c
187
keymacro_add(EditLine *el, const wchar_t *key, keymacro_value_t *val,
lib/libedit/keymacro.c
196
if (ntype == XK_CMD && val->cmd == ED_SEQUENCE_LEAD_IN) {
lib/libedit/keymacro.c
207
(void) node__try(el, el->el_keymacro.map, key, val, ntype);
lib/libedit/keymacro.c
277
keymacro_value_t *val)
lib/libedit/keymacro.c
286
return node_trav(el, ptr->next, ch, val);
lib/libedit/keymacro.c
288
*val = ptr->val;
lib/libedit/keymacro.c
297
return node_trav(el, ptr->sibling, ch, val);
lib/libedit/keymacro.c
300
val->str = NULL;
lib/libedit/keymacro.c
312
keymacro_value_t *val, int ntype)
lib/libedit/keymacro.c
337
if (ptr->val.str)
lib/libedit/keymacro.c
338
free(ptr->val.str);
lib/libedit/keymacro.c
348
ptr->val = *val;
lib/libedit/keymacro.c
351
if ((ptr->val.str = wcsdup(val->str)) == NULL)
lib/libedit/keymacro.c
362
(void) node__try(el, ptr->next, str, val, ntype);
lib/libedit/keymacro.c
436
if (ptr->val.str != NULL)
lib/libedit/keymacro.c
437
free(ptr->val.str);
lib/libedit/keymacro.c
460
ptr->val.str = NULL;
lib/libedit/keymacro.c
511
&ptr->val, ptr->type);
lib/libedit/keymacro.c
560
keymacro_kprint(el, el->el_keymacro.buf, &ptr->val, ptr->type);
lib/libedit/keymacro.c
576
keymacro_kprint(EditLine *el, const wchar_t *key, keymacro_value_t *val,
lib/libedit/keymacro.c
583
if (val != NULL)
lib/libedit/keymacro.c
586
(void) keymacro__decode_str(val->str, unparsbuf,
lib/libedit/keymacro.c
594
if (val->cmd == fp->func) {
lib/libedit/keymacro.c
73
keymacro_value_t val; /* command code or pointer to str, */
lib/libedit/keymacro.h
54
keymacro_value_t val; /* Local conversion buffer */
lib/libedit/read.c
186
keymacro_value_t val;
lib/libedit/read.c
187
switch (keymacro_get(el, ch, &val)) {
lib/libedit/read.c
189
cmd = val.cmd;
lib/libedit/read.c
192
el_wpush(el, val.str);
lib/libexpat/lib/xmltok.c
1160
const char *val = NULL;
lib/libexpat/lib/xmltok.c
1165
if (! parsePseudoAttribute(enc, ptr, end, &name, &nameEnd, &val, &ptr)
lib/libexpat/lib/xmltok.c
1177
*versionPtr = val;
lib/libexpat/lib/xmltok.c
1180
if (! parsePseudoAttribute(enc, ptr, end, &name, &nameEnd, &val, &ptr)) {
lib/libexpat/lib/xmltok.c
1194
int c = toAscii(enc, val, end);
lib/libexpat/lib/xmltok.c
1196
*badPtr = val;
lib/libexpat/lib/xmltok.c
1200
*encodingName = val;
lib/libexpat/lib/xmltok.c
1202
*encoding = encodingFinder(enc, val, ptr - enc->minBytesPerChar);
lib/libexpat/lib/xmltok.c
1203
if (! parsePseudoAttribute(enc, ptr, end, &name, &nameEnd, &val, &ptr)) {
lib/libexpat/lib/xmltok.c
1215
if (XmlNameMatchesAscii(enc, val, ptr - enc->minBytesPerChar, KW_yes)) {
lib/libexpat/lib/xmltok.c
1218
} else if (XmlNameMatchesAscii(enc, val, ptr - enc->minBytesPerChar, KW_no)) {
lib/libexpat/lib/xmltok.c
1222
*badPtr = val;
lib/libfido2/src/assert.c
15
adjust_assert_count(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/assert.c
28
if (cbor_decode_uint64(val, &n) < 0 || n > SIZE_MAX) {
lib/libfido2/src/assert.c
51
parse_assert_reply(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/assert.c
63
return (cbor_decode_cred_id(val, &stmt->id));
lib/libfido2/src/assert.c
65
return (cbor_decode_assert_authdata(val, &stmt->authdata_cbor,
lib/libfido2/src/assert.c
68
return (fido_blob_decode(val, &stmt->sig));
lib/libfido2/src/assert.c
70
return (cbor_decode_user(val, &stmt->user));
lib/libfido2/src/assert.c
72
return (fido_blob_decode(val, &stmt->largeblob_key));
lib/libfido2/src/authkey.c
10
parse_authkey(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/authkey.c
21
return (es256_pk_decode(val, authkey));
lib/libfido2/src/bio.c
149
decode_template(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/bio.c
161
return (fido_blob_decode(val, &t->id));
lib/libfido2/src/bio.c
163
return (cbor_string_copy(val, &t->name));
lib/libfido2/src/bio.c
196
bio_parse_template_array(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/bio.c
208
if (cbor_isa_array(val) == false ||
lib/libfido2/src/bio.c
209
cbor_array_is_definite(val) == false) {
lib/libfido2/src/bio.c
220
if ((ta->ptr = calloc(cbor_array_size(val), sizeof(*ta->ptr))) == NULL)
lib/libfido2/src/bio.c
223
ta->n_alloc = cbor_array_size(val);
lib/libfido2/src/bio.c
225
if (cbor_array_iter(val, ta, decode_template_array) < 0) {
lib/libfido2/src/bio.c
334
bio_parse_enroll_status(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/bio.c
348
if (cbor_decode_uint64(val, &x) < 0 || x > UINT8_MAX) {
lib/libfido2/src/bio.c
355
if (cbor_decode_uint64(val, &x) < 0 || x > UINT8_MAX) {
lib/libfido2/src/bio.c
369
bio_parse_template_id(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/bio.c
381
return (fido_blob_decode(val, id));
lib/libfido2/src/bio.c
621
bio_parse_info(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/bio.c
634
if (cbor_decode_uint64(val, &x) < 0 || x > UINT8_MAX) {
lib/libfido2/src/bio.c
641
if (cbor_decode_uint64(val, &x) < 0 || x > UINT8_MAX) {
lib/libfido2/src/cbor.c
1125
decode_cred_extension(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/cbor.c
1138
if (cbor_isa_float_ctrl(val) == false ||
lib/libfido2/src/cbor.c
1139
cbor_float_get_width(val) != CBOR_FLOAT_0 ||
lib/libfido2/src/cbor.c
1140
cbor_is_bool(val) == false) {
lib/libfido2/src/cbor.c
1144
if (cbor_ctrl_value(val) == CBOR_CTRL_TRUE)
lib/libfido2/src/cbor.c
1147
if (cbor_isa_uint(val) == false ||
lib/libfido2/src/cbor.c
1148
cbor_int_get_width(val) != CBOR_INT_8) {
lib/libfido2/src/cbor.c
1153
authdata_ext->prot = cbor_get_uint8(val);
lib/libfido2/src/cbor.c
1155
if (cbor_isa_float_ctrl(val) == false ||
lib/libfido2/src/cbor.c
1156
cbor_float_get_width(val) != CBOR_FLOAT_0 ||
lib/libfido2/src/cbor.c
1157
cbor_is_bool(val) == false) {
lib/libfido2/src/cbor.c
1161
if (cbor_ctrl_value(val) == CBOR_CTRL_TRUE)
lib/libfido2/src/cbor.c
1164
if (cbor_isa_uint(val) == false ||
lib/libfido2/src/cbor.c
1165
cbor_int_get_width(val) != CBOR_INT_8) {
lib/libfido2/src/cbor.c
1170
authdata_ext->minpinlen = cbor_get_uint8(val);
lib/libfido2/src/cbor.c
1216
decode_assert_extension(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/cbor.c
1230
if (fido_blob_decode(val, &authdata_ext->hmac_secret_enc) < 0) {
lib/libfido2/src/cbor.c
1236
if (fido_blob_decode(val, &authdata_ext->blob) < 0) {
lib/libfido2/src/cbor.c
1391
decode_attstmt_entry(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/cbor.c
1404
if (cbor_isa_negint(val) == false ||
lib/libfido2/src/cbor.c
1405
cbor_get_int(val) > UINT16_MAX) {
lib/libfido2/src/cbor.c
1409
attstmt->alg = -(int)cbor_get_int(val) - 1;
lib/libfido2/src/cbor.c
1417
if (fido_blob_decode(val, &attstmt->sig) < 0) {
lib/libfido2/src/cbor.c
1422
if (cbor_isa_array(val) == false ||
lib/libfido2/src/cbor.c
1423
cbor_array_is_definite(val) == false ||
lib/libfido2/src/cbor.c
1424
cbor_array_iter(val, &attstmt->x5c, decode_x5c) < 0) {
lib/libfido2/src/cbor.c
1429
if (fido_blob_decode(val, &attstmt->certinfo) < 0) {
lib/libfido2/src/cbor.c
1434
if (fido_blob_decode(val, &attstmt->pubarea) < 0) {
lib/libfido2/src/cbor.c
1483
decode_cred_id_entry(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/cbor.c
1496
if (fido_blob_decode(val, id) < 0) {
lib/libfido2/src/cbor.c
1522
decode_user_entry(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/cbor.c
1535
if (cbor_string_copy(val, &user->icon) < 0) {
lib/libfido2/src/cbor.c
1540
if (cbor_string_copy(val, &user->name) < 0) {
lib/libfido2/src/cbor.c
1545
if (cbor_string_copy(val, &user->display_name) < 0) {
lib/libfido2/src/cbor.c
1550
if (fido_blob_decode(val, &user->id) < 0) {
lib/libfido2/src/cbor.c
1577
decode_rp_entity_entry(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/cbor.c
1591
if (cbor_string_copy(val, &rp->id) < 0) {
lib/libfido2/src/cbor.c
1596
if (cbor_string_copy(val, &rp->name) < 0) {
lib/libfido2/src/cbor.c
936
find_cose_alg(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/cbor.c
944
if (cbor_isa_uint(val) == false ||
lib/libfido2/src/cbor.c
945
cbor_get_int(val) > INT_MAX || cose_key->kty != 0) {
lib/libfido2/src/cbor.c
950
cose_key->kty = (int)cbor_get_int(val);
lib/libfido2/src/cbor.c
954
if (cbor_isa_negint(val) == false ||
lib/libfido2/src/cbor.c
955
cbor_get_int(val) > INT_MAX || cose_key->alg != 0) {
lib/libfido2/src/cbor.c
960
cose_key->alg = -(int)cbor_get_int(val) - 1;
lib/libfido2/src/cbor.c
968
if (cbor_isa_uint(val) == true &&
lib/libfido2/src/cbor.c
969
cbor_get_int(val) <= INT_MAX &&
lib/libfido2/src/cbor.c
971
cose_key->crv = (int)cbor_get_int(val);
lib/libfido2/src/cred.c
18
parse_makecred_reply(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/cred.c
30
return (cbor_decode_fmt(val, &cred->fmt));
lib/libfido2/src/cred.c
32
if (fido_blob_decode(val, &cred->authdata_raw) < 0) {
lib/libfido2/src/cred.c
36
return (cbor_decode_cred_authdata(val, cred->type,
lib/libfido2/src/cred.c
40
return (cbor_decode_attstmt(val, &cred->attstmt));
lib/libfido2/src/cred.c
42
return (fido_blob_decode(val, &cred->largeblob_key));
lib/libfido2/src/credman.c
178
credman_parse_metadata(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/credman.c
191
return (cbor_decode_uint64(val, &metadata->rk_existing));
lib/libfido2/src/credman.c
193
return (cbor_decode_uint64(val, &metadata->rk_remaining));
lib/libfido2/src/credman.c
248
credman_parse_rk(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/credman.c
261
return (cbor_decode_user(val, &cred->user));
lib/libfido2/src/credman.c
263
return (cbor_decode_cred_id(val, &cred->attcred.id));
lib/libfido2/src/credman.c
265
if (cbor_decode_pubkey(val, &cred->attcred.type,
lib/libfido2/src/credman.c
271
if (cbor_decode_uint64(val, &prot) < 0 || prot > INT_MAX ||
lib/libfido2/src/credman.c
276
return (fido_blob_decode(val, &cred->largeblob_key));
lib/libfido2/src/credman.c
297
credman_parse_rk_count(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/credman.c
311
if (cbor_decode_uint64(val, &n) < 0 || n > SIZE_MAX) {
lib/libfido2/src/credman.c
468
credman_parse_rp(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/credman.c
480
return (cbor_decode_rp_entity(val, &rp->rp_entity));
lib/libfido2/src/credman.c
482
return (fido_blob_decode(val, &rp->rp_id_hash));
lib/libfido2/src/credman.c
506
credman_parse_rp_count(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/credman.c
520
if (cbor_decode_uint64(val, &n) < 0 || n > SIZE_MAX) {
lib/libfido2/src/dev.c
41
const bool *val = fido_cbor_info_options_value_ptr(info);
lib/libfido2/src/dev.c
46
dev->flags |= val[i] ?
lib/libfido2/src/dev.c
50
if (val[i])
lib/libfido2/src/dev.c
53
dev->flags |= val[i] ?
lib/libfido2/src/dev.c
56
if (val[i])
lib/libfido2/src/eddsa.c
75
decode_pubkey_point(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/eddsa.c
85
return (decode_coord(val, &k->x, sizeof(k->x)));
lib/libfido2/src/es256.c
38
decode_pubkey_point(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/es256.c
48
return (decode_coord(val, &k->x, sizeof(k->x)));
lib/libfido2/src/es256.c
50
return (decode_coord(val, &k->y, sizeof(k->y)));
lib/libfido2/src/hid.c
27
get_key_val(const void *body, size_t key_len, uint32_t *val)
lib/libfido2/src/hid.c
33
*val = 0;
lib/libfido2/src/hid.c
36
*val = ptr[0];
lib/libfido2/src/hid.c
39
*val = (uint32_t)((ptr[1] << 8) | ptr[0]);
lib/libfido2/src/info.c
155
decode_algorithm_entry(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/info.c
169
if (cbor_isa_negint(val) == false ||
lib/libfido2/src/info.c
170
cbor_get_int(val) > INT_MAX || alg->cose != 0) {
lib/libfido2/src/info.c
174
alg->cose = -(int)cbor_get_int(val) - 1;
lib/libfido2/src/info.c
176
if (cbor_string_copy(val, &alg->type) < 0) {
lib/libfido2/src/info.c
240
parse_reply_element(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/info.c
252
return (decode_string_array(val, &ci->versions));
lib/libfido2/src/info.c
254
return (decode_string_array(val, &ci->extensions));
lib/libfido2/src/info.c
256
return (decode_aaguid(val, ci->aaguid, sizeof(ci->aaguid)));
lib/libfido2/src/info.c
258
return (decode_options(val, &ci->options));
lib/libfido2/src/info.c
260
return (cbor_decode_uint64(val, &ci->maxmsgsiz));
lib/libfido2/src/info.c
262
return (decode_protocols(val, &ci->protocols));
lib/libfido2/src/info.c
264
return (cbor_decode_uint64(val, &ci->maxcredcntlst));
lib/libfido2/src/info.c
266
return (cbor_decode_uint64(val, &ci->maxcredidlen));
lib/libfido2/src/info.c
268
return (decode_string_array(val, &ci->transports));
lib/libfido2/src/info.c
270
return (decode_algorithms(val, &ci->algorithms));
lib/libfido2/src/info.c
272
return (cbor_decode_uint64(val, &ci->maxlargeblob));
lib/libfido2/src/info.c
274
return (cbor_decode_uint64(val, &ci->fwversion));
lib/libfido2/src/info.c
276
return (cbor_decode_uint64(val, &ci->maxcredbloblen));
lib/libfido2/src/info.c
66
decode_option(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/info.c
71
if (cbor_isa_float_ctrl(val) == false ||
lib/libfido2/src/info.c
72
cbor_float_get_width(val) != CBOR_FLOAT_0 ||
lib/libfido2/src/info.c
73
cbor_is_bool(val) == false) {
lib/libfido2/src/info.c
84
o->value[i] = cbor_ctrl_value(val) == CBOR_CTRL_TRUE;
lib/libfido2/src/largeblob.c
187
parse_largeblob_reply(const cbor_item_t *key, const cbor_item_t *val,
lib/libfido2/src/largeblob.c
197
return fido_blob_decode(val, arg);
lib/libfido2/src/largeblob.c
265
largeblob_do_decode(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/largeblob.c
278
if (fido_blob_decode(val, &blob->ciphertext) < 0 ||
lib/libfido2/src/largeblob.c
283
if (fido_blob_decode(val, &blob->nonce) < 0 ||
lib/libfido2/src/largeblob.c
288
if (!cbor_isa_uint(val) ||
lib/libfido2/src/largeblob.c
289
(origsiz = cbor_get_int(val)) > SIZE_MAX)
lib/libfido2/src/pin.c
268
parse_uv_token(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/pin.c
279
return (fido_blob_decode(val, token));
lib/libfido2/src/pin.c
514
const cbor_item_t *val, void *arg)
lib/libfido2/src/pin.c
526
if (cbor_decode_uint64(val, &n) < 0 || n > INT_MAX) {
lib/libfido2/src/pin.c
537
parse_pin_retry_count(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/pin.c
539
return (parse_retry_count(3, key, val, arg));
lib/libfido2/src/pin.c
543
parse_uv_retry_count(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/pin.c
545
return (parse_retry_count(5, key, val, arg));
lib/libfido2/src/rs256.c
47
decode_rsa_pubkey(const cbor_item_t *key, const cbor_item_t *val, void *arg)
lib/libfido2/src/rs256.c
57
return (decode_bignum(val, &k->n, sizeof(k->n)));
lib/libfido2/src/rs256.c
59
return (decode_bignum(val, &k->e, sizeof(k->e)));
lib/libform/fty_int.c
230
long val = atol(s);
lib/libform/fty_int.c
234
if (val < low || val > high)
lib/libform/fty_int.c
242
"%.*ld", (prec > 0 ? prec : 0), val);
lib/libform/fty_num.c
268
double val = atof(s);
lib/libform/fty_num.c
272
if (val < low || val > high)
lib/libform/fty_num.c
280
"%.*f", (prec > 0 ? prec : 0), val);
lib/libfuse/fuse_opt.c
194
const char *val;
lib/libfuse/fuse_opt.c
206
val = opt;
lib/libfuse/fuse_opt.c
210
val = &opt[sep + 1];
lib/libfuse/fuse_opt.c
216
val = &opt[sep];
lib/libfuse/fuse_opt.c
220
if (o->val == FUSE_OPT_KEY_DISCARD)
lib/libfuse/fuse_opt.c
222
else if (o->val == FUSE_OPT_KEY_KEEP)
lib/libfuse/fuse_opt.c
228
ret = f(data, val, o->val, arg);
lib/libfuse/fuse_opt.c
232
*((int *)(data + o->off)) = o->val;
lib/libfuse/fuse_opt.c
235
*((char **)(data + o->off)) = strdup(val);
lib/libfuse/fuse_opt.c
241
"option %s\n", val, o->templ);
lib/libfuse/fuse_opt.h
34
int val;
lib/libossaudio/ossaudio.c
153
i->value = val;
lib/libossaudio/ossaudio.c
93
mixer_ondesc(void *unused, struct sioctl_desc *d, int val)
lib/libpcap/gencode.c
2843
gen_loadi(int val)
lib/libpcap/gencode.c
2854
s->s.k = val;
lib/libpcap/gencode.c
2972
gen_byteop(int op, int idx, int val)
lib/libpcap/gencode.c
2982
return gen_cmp((u_int)idx, BPF_B, (bpf_int32)val);
lib/libpcap/gencode.c
2985
b = gen_cmp((u_int)idx, BPF_B, (bpf_int32)val);
lib/libpcap/gencode.c
2991
b = gen_cmp((u_int)idx, BPF_B, (bpf_int32)val);
lib/libpcap/gencode.c
3003
s->s.k = val;
lib/libpcap/gencode.h
139
int val[N_ATOMS];
lib/libpcap/optimize.c
1003
vstore(s, &val[X_ATOM], val[A_ATOM], alter);
lib/libpcap/optimize.c
1007
v = val[s->k];
lib/libpcap/optimize.c
1013
vstore(s, &val[X_ATOM], v, alter);
lib/libpcap/optimize.c
1017
vstore(s, &val[s->k], val[A_ATOM], alter);
lib/libpcap/optimize.c
1021
vstore(s, &val[s->k], val[X_ATOM], alter);
lib/libpcap/optimize.c
1095
memset((char *)b->val, 0, sizeof(b->val));
lib/libpcap/optimize.c
1097
memcpy((char *)b->val, (char *)p->pred->val, sizeof(b->val));
lib/libpcap/optimize.c
1100
if (b->val[i] != p->pred->val[i])
lib/libpcap/optimize.c
1101
b->val[i] = 0;
lib/libpcap/optimize.c
1104
aval = b->val[A_ATOM];
lib/libpcap/optimize.c
1106
opt_stmt(&s->s, b->val, do_stmts);
lib/libpcap/optimize.c
1115
((b->out_use == 0 && aval != 0 &&b->val[A_ATOM] == aval) ||
lib/libpcap/optimize.c
1131
b->oval = b->val[X_ATOM];
lib/libpcap/optimize.c
1152
if (b->val[atom] != succ->val[atom])
lib/libpcap/optimize.c
1173
aval0 = child->val[A_ATOM];
lib/libpcap/optimize.c
1175
aval1 = ep->pred->val[A_ATOM];
lib/libpcap/optimize.c
1259
int val, at_top;
lib/libpcap/optimize.c
1272
val = ep->pred->val[A_ATOM];
lib/libpcap/optimize.c
1274
if (val != ep->pred->val[A_ATOM])
lib/libpcap/optimize.c
1293
if ((*diffp)->val[A_ATOM] != val)
lib/libpcap/optimize.c
1310
if ((*samep)->val[A_ATOM] == val)
lib/libpcap/optimize.c
1321
if ((*samep)->val[i] != pred->val[i])
lib/libpcap/optimize.c
1351
int val, at_top;
lib/libpcap/optimize.c
1363
val = ep->pred->val[A_ATOM];
lib/libpcap/optimize.c
1365
if (val != ep->pred->val[A_ATOM])
lib/libpcap/optimize.c
1384
if ((*diffp)->val[A_ATOM] != val)
lib/libpcap/optimize.c
1401
if ((*samep)->val[A_ATOM] == val)
lib/libpcap/optimize.c
1412
if ((*samep)->val[i] != pred->val[i])
lib/libpcap/optimize.c
491
int val;
lib/libpcap/optimize.c
526
int val;
lib/libpcap/optimize.c
534
return p->val;
lib/libpcap/optimize.c
536
val = ++curval;
lib/libpcap/optimize.c
539
vmap[val].const_val = v0;
lib/libpcap/optimize.c
540
vmap[val].is_const = 1;
lib/libpcap/optimize.c
543
p->val = val;
lib/libpcap/optimize.c
550
return val;
lib/libpcap/optimize.c
639
int val;
lib/libpcap/optimize.c
744
val = b->val[X_ATOM];
lib/libpcap/optimize.c
745
if (vmap[val].is_const) {
lib/libpcap/optimize.c
748
b->s.k += vmap[val].const_val;
lib/libpcap/optimize.c
803
val = b->val[A_ATOM];
lib/libpcap/optimize.c
804
if (vmap[val].is_const && BPF_SRC(b->s.code) == BPF_K) {
lib/libpcap/optimize.c
805
bpf_int32 v = vmap[val].const_val;
lib/libpcap/optimize.c
843
opt_stmt(struct stmt *s, int val[], int alter)
lib/libpcap/optimize.c
854
vstore(s, &val[A_ATOM], v, alter);
lib/libpcap/optimize.c
860
v = val[X_ATOM];
lib/libpcap/optimize.c
869
vstore(s, &val[A_ATOM], v, alter);
lib/libpcap/optimize.c
875
vstore(s, &val[A_ATOM], v, alter);
lib/libpcap/optimize.c
880
vstore(s, &val[A_ATOM], v, alter);
lib/libpcap/optimize.c
885
vstore(s, &val[X_ATOM], v, alter);
lib/libpcap/optimize.c
890
vstore(s, &val[X_ATOM], v, alter);
lib/libpcap/optimize.c
894
if (alter && vmap[val[A_ATOM]].is_const) {
lib/libpcap/optimize.c
896
s->k = -vmap[val[A_ATOM]].const_val;
lib/libpcap/optimize.c
897
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
900
val[A_ATOM] = F(s->code, val[A_ATOM], 0L);
lib/libpcap/optimize.c
922
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
926
if (vmap[val[A_ATOM]].is_const) {
lib/libpcap/optimize.c
927
fold_op(s, val[A_ATOM], K(s->k));
lib/libpcap/optimize.c
928
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
932
val[A_ATOM] = F(s->code, val[A_ATOM], K(s->k));
lib/libpcap/optimize.c
944
if (alter && vmap[val[X_ATOM]].is_const) {
lib/libpcap/optimize.c
945
if (vmap[val[A_ATOM]].is_const) {
lib/libpcap/optimize.c
946
fold_op(s, val[A_ATOM], val[X_ATOM]);
lib/libpcap/optimize.c
947
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
951
s->k = vmap[val[X_ATOM]].const_val;
lib/libpcap/optimize.c
953
val[A_ATOM] =
lib/libpcap/optimize.c
954
F(s->code, val[A_ATOM], K(s->k));
lib/libpcap/optimize.c
965
if (alter && vmap[val[A_ATOM]].is_const
lib/libpcap/optimize.c
966
&& vmap[val[A_ATOM]].const_val == 0) {
lib/libpcap/optimize.c
970
vstore(s, &val[A_ATOM], val[X_ATOM], alter);
lib/libpcap/optimize.c
977
vstore(s, &val[A_ATOM], K(s->k), alter);
lib/libpcap/optimize.c
985
val[A_ATOM] = F(s->code, val[A_ATOM], val[X_ATOM]);
lib/libpcap/optimize.c
989
vstore(s, &val[A_ATOM], val[X_ATOM], alter);
lib/libpcap/optimize.c
993
v = val[s->k];
lib/libpcap/optimize.c
999
vstore(s, &val[A_ATOM], v, alter);
lib/libradius/radius_attr.c
427
uint8_t type, tname *val) \
lib/libradius/radius_attr.c
438
*val = ntoh(nval); \
lib/libradius/radius_attr.c
443
uint32_t vendor, uint8_t vtype, tname *val) \
lib/libradius/radius_attr.c
455
*val = ntoh(nval); \
lib/libradius/radius_attr.c
460
uint8_t type, tname val) \
lib/libradius/radius_attr.c
464
nval = hton(val); \
lib/libradius/radius_attr.c
469
uint32_t vendor, uint8_t vtype, tname val) \
lib/libradius/radius_attr.c
473
nval = hton(val); \
lib/libradius/radius_attr.c
479
uint8_t type, tname val) \
lib/libradius/radius_attr.c
483
nval = hton(val); \
lib/libradius/radius_attr.c
488
uint32_t vendor, uint8_t vtype, tname val) \
lib/libradius/radius_attr.c
492
nval = hton(val); \
lib/libradius/radius_attr.c
499
uint8_t type, tname *val) \
lib/libradius/radius_attr.c
508
memcpy(val, p, sizeof(tname)); \
lib/libradius/radius_attr.c
513
uint32_t vendor, uint8_t vtype, tname *val) \
lib/libradius/radius_attr.c
523
memcpy(val, p, sizeof(tname)); \
lib/libradius/radius_attr.c
528
uint8_t type, const tname *val) \
lib/libradius/radius_attr.c
530
return radius_put_raw_attr(packet, type, val, sizeof(tname)); \
lib/libradius/radius_attr.c
534
uint32_t vendor, uint8_t vtype, const tname *val) \
lib/libradius/radius_attr.c
537
val, sizeof(tname)); \
lib/libradius/radius_attr.c
541
uint8_t type, const tname *val) \
lib/libradius/radius_attr.c
543
return radius_set_raw_attr(packet, type, val, sizeof(tname)); \
lib/libradius/radius_attr.c
547
uint32_t vendor, uint8_t vtype, const tname *val) \
lib/libradius/radius_attr.c
550
val, sizeof(tname)); \
lib/librthread/rthread_attr.c
159
char val = p[i];
lib/librthread/rthread_attr.c
161
p[i] = val;
lib/librthread/rthread_np.c
124
sinfo->ss_sp = _ps.val;
lib/librthread/rthread_np.c
126
sinfo->ss_sp = (void *)ROUND_TO_PAGE((uintptr_t)_ps.val);
lib/librthread/rthread_rwlock.c
100
unsigned int val;
lib/librthread/rthread_rwlock.c
103
val = rwlock->value;
lib/librthread/rthread_rwlock.c
104
if (COUNT(val) == WRITER)
lib/librthread/rthread_rwlock.c
106
if (COUNT(val) == MAXREADER)
lib/librthread/rthread_rwlock.c
108
} while (atomic_cas_uint(&rwlock->value, val, val + 1) != val);
lib/librthread/rthread_rwlock.c
120
unsigned int val, new;
lib/librthread/rthread_rwlock.c
137
val = rwlock->value;
lib/librthread/rthread_rwlock.c
138
if (val == UNLOCKED || (val & WAITING))
lib/librthread/rthread_rwlock.c
145
val = rwlock->value;
lib/librthread/rthread_rwlock.c
146
if (val == UNLOCKED || (COUNT(val)) != WRITER)
lib/librthread/rthread_rwlock.c
148
new = val | WAITING;
lib/librthread/rthread_rwlock.c
149
if (atomic_cas_uint(&rwlock->value, val, new) == val) {
lib/librthread/rthread_rwlock.c
197
unsigned int val, new;
lib/librthread/rthread_rwlock.c
214
val = rwlock->value;
lib/librthread/rthread_rwlock.c
215
if (val == UNLOCKED || (val & WAITING))
lib/librthread/rthread_rwlock.c
222
val = rwlock->value;
lib/librthread/rthread_rwlock.c
223
if (val == UNLOCKED)
lib/librthread/rthread_rwlock.c
225
new = val | WAITING;
lib/librthread/rthread_rwlock.c
226
if (atomic_cas_uint(&rwlock->value, val, new) == val) {
lib/librthread/rthread_rwlock.c
261
unsigned int val, new;
lib/librthread/rthread_rwlock.c
268
val = rwlock->value;
lib/librthread/rthread_rwlock.c
269
if (COUNT(val) == WRITER || COUNT(val) == 1)
lib/librthread/rthread_rwlock.c
272
new = val - 1;
lib/librthread/rthread_rwlock.c
273
} while (atomic_cas_uint(&rwlock->value, val, new) != val);
lib/librthread/rthread_rwlock.c
275
if (new == UNLOCKED && (val & WAITING))
lib/librthread/rthread_sem.c
284
unsigned int val;
lib/librthread/rthread_sem.c
291
while ((val = sem->value) > 0) {
lib/librthread/rthread_sem.c
292
if (atomic_cas_uint(&sem->value, val, val - 1) == val) {
lib/librthread/rthread_sem.c
61
unsigned int val;
lib/librthread/rthread_sem.c
66
while ((val = sem->value) > 0) {
lib/librthread/rthread_sem.c
67
if (atomic_cas_uint(&sem->value, val, val - 1) == val) {
lib/librthread/synch.h
29
_twait(volatile uint32_t *p, int val, clockid_t clockid, const struct timespec *abs)
lib/librthread/synch.h
36
error = futex(p, FUTEX_WAIT, val, NULL, NULL);
lib/librthread/synch.h
51
error = futex(p, FUTEX_WAIT, val, &rel, NULL);
lib/libskey/skey.h
27
char *val;
lib/libskey/skeylogin.c
163
if ((mp->val = strtok_r(NULL, " \t\n\r", &last)) == NULL)
lib/libskey/skeylogin.c
291
if ((mp->val = strtok_r(NULL, " \t\r\n", &last)) == NULL)
lib/libskey/skeylogin.c
295
atob8(filekey, mp->val);
lib/libskey/skeylogin.c
303
btoa8(mp->val,key);
lib/libskey/skeylogin.c
307
skey_get_algorithm(), mp->n, mp->seed, mp->val);
lib/libskey/skeysubr.c
234
int val;
lib/libskey/skeysubr.c
242
if ((val = htoi(*in++)) == -1)
lib/libskey/skeysubr.c
244
*out = val << 4;
lib/libskey/skeysubr.c
248
if ((val = htoi(*in++)) == -1)
lib/libskey/skeysubr.c
250
*out++ |= val;
lib/libsndio/amsg.h
131
uint8_t desc, val;
lib/libsndio/amsg.h
134
uint16_t addr, val;
lib/libsndio/debug.c
61
unsigned int dig, maxq, maxr, val;
lib/libsndio/debug.c
63
val = 0;
lib/libsndio/debug.c
70
if (val > maxq || (val == maxq && dig > maxr)) {
lib/libsndio/debug.c
74
val = val * 10 + dig;
lib/libsndio/debug.c
81
*num = val;
lib/libsndio/sioctl.c
149
struct sioctl_desc *desc, unsigned int val)
lib/libsndio/sioctl.c
157
val);
lib/libsndio/sioctl.c
160
hdl->desc_cb(hdl->desc_arg, desc, val);
lib/libsndio/sioctl.c
164
_sioctl_onval_cb(struct sioctl_hdl *hdl, unsigned int addr, unsigned int val)
lib/libsndio/sioctl.c
166
DPRINTF("_sioctl_onval_cb: %u -> %u\n", addr, val);
lib/libsndio/sioctl.c
168
hdl->ctl_cb(hdl->ctl_arg, addr, val);
lib/libsndio/sioctl.c
172
sioctl_setval(struct sioctl_hdl *hdl, unsigned int addr, unsigned int val)
lib/libsndio/sioctl.c
176
return hdl->ops->setctl(hdl, addr, val);
lib/libsndio/sioctl_aucat.c
122
ntohs(hdl->aucat.rmsg.u.ctlset.val));
lib/libsndio/sioctl_aucat.c
183
hdl->aucat.wmsg.u.ctlsub.val = 0;
lib/libsndio/sioctl_aucat.c
210
hdl->aucat.wmsg.u.ctlsub.val = 1;
lib/libsndio/sioctl_aucat.c
226
hdl->aucat.wmsg.u.ctlset.val = htons(v);
lib/libsndio/sioctl_sun.c
181
setvol(struct sioctl_sun_hdl *hdl, struct volume *vol, int addr, int val)
lib/libsndio/sioctl_sun.c
188
if (vol->level_val[addr] == val) {
lib/libsndio/sioctl_sun.c
189
DPRINTF("level %d, no change\n", val);
lib/libsndio/sioctl_sun.c
192
vol->level_val[addr] = val;
lib/libsndio/sioctl_sun.c
203
_sioctl_onval_cb(&hdl->sioctl, vol->base_addr + addr, val);
lib/libsndio/sioctl_sun.c
209
val = val ? 1 : 0;
lib/libsndio/sioctl_sun.c
210
if (vol->mute_val == val) {
lib/libsndio/sioctl_sun.c
211
DPRINTF("mute %d, no change\n", val);
lib/libsndio/sioctl_sun.c
214
vol->mute_val = val;
lib/libsndio/sioctl_sun.c
217
ctrl.un.ord = val;
lib/libsndio/sioctl_sun.c
218
DPRINTF("mute setting to %d\n", val);
lib/libsndio/sioctl_sun.c
225
vol->base_addr + 32 + i, val);
lib/libsndio/sioctl_sun.c
237
int i, val;
lib/libsndio/sioctl_sun.c
257
val = ctrl.un.value.level[i];
lib/libsndio/sioctl_sun.c
258
vol->level_val[i] = val;
lib/libsndio/sioctl_sun.c
259
_sioctl_ondesc_cb(&hdl->sioctl, &desc, val);
lib/libsndio/sioctl_sun.c
275
val = ctrl.un.ord ? 1 : 0;
lib/libsndio/sioctl_sun.c
276
vol->mute_val = val;
lib/libsndio/sioctl_sun.c
280
_sioctl_ondesc_cb(&hdl->sioctl, &desc, val);
lib/libsndio/sioctl_sun.c
290
int val, i;
lib/libsndio/sioctl_sun.c
305
val = ctrl.un.ord ? 1 : 0;
lib/libsndio/sioctl_sun.c
306
if (vol->mute_val == val)
lib/libsndio/sioctl_sun.c
308
vol->mute_val = val;
lib/libsndio/sioctl_sun.c
311
vol->base_addr + 32 + i, val);
lib/libsndio/sioctl_sun.c
315
val = ctrl.un.value.level[i];
lib/libsndio/sioctl_sun.c
316
if (vol->level_val[i] == val)
lib/libsndio/sioctl_sun.c
318
vol->level_val[i] = val;
lib/libsndio/sioctl_sun.c
320
vol->base_addr + i, val);
lib/libsndio/sioctl_sun.c
452
sioctl_sun_setctl(struct sioctl_hdl *arg, unsigned int addr, unsigned int val)
lib/libsndio/sioctl_sun.c
456
if (!setvol(hdl, &hdl->output, addr, val) ||
lib/libsndio/sioctl_sun.c
457
!setvol(hdl, &hdl->input, addr, val)) {
lib/libssl/bio_ssl.c
449
void (**fptr)(const SSL *xssl, int type, int val);
lib/libssl/bio_ssl.c
451
fptr = (void (**)(const SSL *xssl, int type, int val))
lib/libssl/ssl.h
1394
void (*cb)(const SSL *ssl, int type, int val));
lib/libssl/ssl.h
1395
void (*SSL_get_info_callback(const SSL *ssl))(const SSL *ssl, int type, int val);
lib/libssl/ssl.h
582
int type, int val));
lib/libssl/ssl.h
584
int val);
lib/libssl/ssl.h
722
void SSL_CTX_set_post_handshake_auth(SSL_CTX *ctx, int val);
lib/libssl/ssl.h
723
void SSL_set_post_handshake_auth(SSL *s, int val);
lib/libssl/ssl_lib.c
3281
SSL_set_info_callback(SSL *ssl, void (*cb)(const SSL *ssl, int type, int val))
lib/libssl/ssl_lib.c
3287
void (*SSL_get_info_callback(const SSL *ssl))(const SSL *ssl, int type, int val)
lib/libssl/ssl_lib.c
3329
SSL_CTX_set_post_handshake_auth(SSL_CTX *ctx, int val)
lib/libssl/ssl_lib.c
3336
SSL_set_post_handshake_auth(SSL *ssl, int val)
lib/libssl/ssl_local.h
652
typedef void (ssl_info_callback_fn)(const SSL *s, int type, int val);
lib/libssl/ssl_sess.c
1279
void (*cb)(const SSL *ssl, int type, int val))
lib/libssl/ssl_sess.c
1286
(*SSL_CTX_get_info_callback(SSL_CTX *ctx))(const SSL *ssl, int type, int val)
lib/libutil/ber.c
1269
long long val = 0;
lib/libutil/ber.c
1357
val <<= 8;
lib/libutil/ber.c
1358
val |= c;
lib/libutil/ber.c
1364
(val >> ((len - 1) * 8) & 0x80))
lib/libutil/ber.c
1365
val |= ULLONG_MAX << (len * 8);
lib/libutil/ber.c
1366
elm->be_numeric = val;
lib/libutil/ber.c
153
ober_add_enumerated(struct ber_element *prev, long long val)
lib/libutil/ber.c
162
elm->be_numeric = val;
lib/libutil/ber.c
165
cur = val & 0xff;
lib/libutil/ber.c
171
val >>= 8;
lib/libutil/ber.c
182
ober_add_integer(struct ber_element *prev, long long val)
lib/libutil/ber.c
191
elm->be_numeric = val;
lib/libutil/ber.c
194
cur = val & 0xff;
lib/libutil/ber.c
200
val >>= 8;
lib/libutil/uucplock.c
50
#define GORET(level, val) { err = errno; uuerr = (val); \
lib/libz/crc32.c
507
uLong val;
lib/libz/crc32.c
527
val = *buf++;
lib/libz/crc32.c
528
__asm__ volatile("crc32b %w0, %w0, %w1" : "+r"(crc) : "r"(val));
lib/libz/crc32.c
573
val = x2nmodp((int)last, 6);
lib/libz/crc32.c
574
crc = multmodp(val, crc) ^ crc1;
lib/libz/crc32.c
575
crc = multmodp(val, crc) ^ crc2;
lib/libz/crc32.c
589
val = *buf++;
lib/libz/crc32.c
590
__asm__ volatile("crc32b %w0, %w0, %w1" : "+r"(crc) : "r"(val));
lib/libz/deflate.c
1143
int val;
lib/libz/deflate.c
1154
val = s->gzhead->name[s->gzindex++];
lib/libz/deflate.c
1155
put_byte(s, val);
lib/libz/deflate.c
1156
} while (val != 0);
lib/libz/deflate.c
1165
int val;
lib/libz/deflate.c
1176
val = s->gzhead->comment[s->gzindex++];
lib/libz/deflate.c
1177
put_byte(s, val);
lib/libz/deflate.c
1178
} while (val != 0);
lib/libz/infback.c
358
if (here.val < 16) {
lib/libz/infback.c
360
state->lens[state->have++] = here.val;
lib/libz/infback.c
363
if (here.val == 16) {
lib/libz/infback.c
380
else if (here.val == 17) {
lib/libz/infback.c
480
here = state->lencode[last.val +
lib/libz/infback.c
488
state->length = (unsigned)here.val;
lib/libz/infback.c
492
Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?
lib/libz/infback.c
494
"inflate: literal 0x%02x\n", here.val));
lib/libz/infback.c
538
here = state->distcode[last.val +
lib/libz/infback.c
555
state->offset = (unsigned)here.val;
lib/libz/inffast.c
114
Tracevv((stderr, here->val >= 0x20 && here->val < 0x7f ?
lib/libz/inffast.c
116
"inflate: literal 0x%02x\n", here->val));
lib/libz/inffast.c
117
*out++ = (unsigned char)(here->val);
lib/libz/inffast.c
120
len = (unsigned)(here->val);
lib/libz/inffast.c
145
dist = (unsigned)(here->val);
lib/libz/inffast.c
269
here = dcode + here->val + (hold & ((1U << op) - 1));
lib/libz/inffast.c
283
here = lcode + here->val + (hold & ((1U << op) - 1));
lib/libz/inflate.c
1004
state->length = (unsigned)here.val;
lib/libz/inflate.c
1006
Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?
lib/libz/inflate.c
1008
"inflate: literal 0x%02x\n", here.val));
lib/libz/inflate.c
1050
here = state->distcode[last.val +
lib/libz/inflate.c
1069
state->offset = (unsigned)here.val;
lib/libz/inflate.c
871
if (here.val < 16) {
lib/libz/inflate.c
873
state->lens[state->have++] = here.val;
lib/libz/inflate.c
876
if (here.val == 16) {
lib/libz/inflate.c
893
else if (here.val == 17) {
lib/libz/inflate.c
994
here = state->lencode[last.val +
lib/libz/inftrees.c
127
here.val = (unsigned short)0;
lib/libz/inftrees.c
224
here.val = work[sym];
lib/libz/inftrees.c
228
here.val = base[work[sym] - match];
lib/libz/inftrees.c
232
here.val = 0;
lib/libz/inftrees.c
291
(*table)[low].val = (unsigned short)(next - *table);
lib/libz/inftrees.c
301
here.val = (unsigned short)0;
lib/libz/inftrees.c
404
state.lencode[low].bits, state.lencode[low].val);
lib/libz/inftrees.c
415
state.distcode[low].val);
lib/libz/inftrees.h
27
unsigned short val; /* offset in table or code value */
lib/libz/trees.c
275
int val = (int)value;\
lib/libz/trees.c
276
s->bi_buf |= (ush)val << s->bi_valid;\
lib/libz/trees.c
278
s->bi_buf = (ush)val >> (Buf_size - s->bi_valid);\
libexec/ftpd/ftpd.c
334
long val = 0;
libexec/ftpd/ftpd.c
338
val = strtol(optarg, &p, 8);
libexec/ftpd/ftpd.c
339
if (*optarg == '\0' || *p != '\0' || val < 0 ||
libexec/ftpd/ftpd.c
340
(val & ~ACCESSPERMS)) {
libexec/ftpd/ftpd.c
346
defumask = val;
libexec/ld.so/alpha/archdep.h
46
Elf_Addr val = v + s->st_value + r->r_addend -
libexec/ld.so/alpha/archdep.h
48
*p = val;
libexec/ld.so/m88k/rtld_machine.c
220
_dl_md_reloc_gotp_ent(Elf_Addr got_addr, Elf_Addr plt_addr, Elf_Addr val)
libexec/ld.so/m88k/rtld_machine.c
225
*(Elf_Addr *)got_addr = val;
libexec/ld.so/mips64/archdep.h
40
#define RELOC_DYN(relp, symp, adrp, val) \
libexec/ld.so/mips64/archdep.h
44
*adrp += symp->st_value + val; \
libexec/ld.so/mips64/archdep.h
46
*adrp += val; \
libexec/ld.so/powerpc/archdep.h
56
Elf_Addr val = v + s->st_value + r->r_addend -
libexec/ld.so/powerpc/archdep.h
58
if (((val & 0xfe000000) != 0) &&
libexec/ld.so/powerpc/archdep.h
59
((val & 0xfe000000) != 0xfe000000)) {
libexec/ld.so/powerpc/archdep.h
63
val &= ~0xfc000000;
libexec/ld.so/powerpc/archdep.h
64
val |= 0x48000000;
libexec/ld.so/powerpc/archdep.h
65
*p = val;
libexec/ld.so/powerpc/rtld_machine.c
160
Elf_Addr val = prev_ooff + prev_value +
libexec/ld.so/powerpc/rtld_machine.c
162
if (!B24_VALID_RANGE(val)) {
libexec/ld.so/powerpc/rtld_machine.c
165
object->load_name, "REL24", val,
libexec/ld.so/powerpc/rtld_machine.c
168
val &= ~0xfc000003;
libexec/ld.so/powerpc/rtld_machine.c
169
val |= (*r_addr & 0xfc000003);
libexec/ld.so/powerpc/rtld_machine.c
170
*r_addr = val;
libexec/ld.so/powerpc/rtld_machine.c
179
Elf_Addr val;
libexec/ld.so/powerpc/rtld_machine.c
181
val = loff + relas->r_addend;
libexec/ld.so/powerpc/rtld_machine.c
182
*(Elf_Half *)r_addr = val;
libexec/ld.so/powerpc/rtld_machine.c
191
Elf_Addr val;
libexec/ld.so/powerpc/rtld_machine.c
193
val = loff + relas->r_addend;
libexec/ld.so/powerpc/rtld_machine.c
194
*(Elf_Half *)r_addr = (val >> 16);
libexec/ld.so/powerpc/rtld_machine.c
203
Elf_Addr val;
libexec/ld.so/powerpc/rtld_machine.c
205
val = loff + relas->r_addend;
libexec/ld.so/powerpc/rtld_machine.c
206
*(Elf_Half *)r_addr = ((val + 0x8000) >> 16);
libexec/ld.so/powerpc/rtld_machine.c
217
Elf_Addr val = prev_ooff + prev_value +
libexec/ld.so/powerpc/rtld_machine.c
219
if (((val & 0xffff8000) != 0) &&
libexec/ld.so/powerpc/rtld_machine.c
220
((val & 0xffff8000) != 0xffff8000)) {
libexec/ld.so/powerpc/rtld_machine.c
223
object->load_name, "REL14", val,
libexec/ld.so/powerpc/rtld_machine.c
226
val &= ~0xffff0003;
libexec/ld.so/powerpc/rtld_machine.c
227
val |= (*r_addr & 0xffff0003);
libexec/ld.so/powerpc/rtld_machine.c
228
*r_addr = val;
libexec/ld.so/powerpc64/archdep.h
57
Elf_Addr val = v + s->st_value + r->r_addend -
libexec/ld.so/powerpc64/archdep.h
59
if (((val & 0xfe000000) != 0) &&
libexec/ld.so/powerpc64/archdep.h
60
((val & 0xfe000000) != 0xfe000000)) {
libexec/ld.so/powerpc64/archdep.h
64
val &= ~0xfc000000;
libexec/ld.so/powerpc64/archdep.h
65
val |= 0x48000000;
libexec/ld.so/powerpc64/archdep.h
66
*p = val;
libexec/ld.so/powerpc64/rtld_machine.c
156
Elf_Addr val = prev_ooff + prev_value +
libexec/ld.so/powerpc64/rtld_machine.c
158
if (!B24_VALID_RANGE(val)) {
libexec/ld.so/powerpc64/rtld_machine.c
161
object->load_name, "REL24", val,
libexec/ld.so/powerpc64/rtld_machine.c
164
val &= ~0xfc000003;
libexec/ld.so/powerpc64/rtld_machine.c
165
val |= (*r_addr & 0xfc000003);
libexec/ld.so/powerpc64/rtld_machine.c
166
*r_addr = val;
libexec/ld.so/powerpc64/rtld_machine.c
175
Elf_Addr val;
libexec/ld.so/powerpc64/rtld_machine.c
177
val = loff + relas->r_addend;
libexec/ld.so/powerpc64/rtld_machine.c
178
*(Elf_Half *)r_addr = val;
libexec/ld.so/powerpc64/rtld_machine.c
187
Elf_Addr val;
libexec/ld.so/powerpc64/rtld_machine.c
189
val = loff + relas->r_addend;
libexec/ld.so/powerpc64/rtld_machine.c
190
*(Elf_Half *)r_addr = (val >> 16);
libexec/ld.so/powerpc64/rtld_machine.c
199
Elf_Addr val;
libexec/ld.so/powerpc64/rtld_machine.c
201
val = loff + relas->r_addend;
libexec/ld.so/powerpc64/rtld_machine.c
202
*(Elf_Half *)r_addr = ((val + 0x8000) >> 16);
libexec/ld.so/powerpc64/rtld_machine.c
214
Elf_Addr val = prev_ooff + prev_value +
libexec/ld.so/powerpc64/rtld_machine.c
216
if (((val & 0xffff8000) != 0) &&
libexec/ld.so/powerpc64/rtld_machine.c
217
((val & 0xffff8000) != 0xffff8000)) {
libexec/ld.so/powerpc64/rtld_machine.c
220
object->load_name, "REL14", val,
libexec/ld.so/powerpc64/rtld_machine.c
223
val &= ~0xffff0003;
libexec/ld.so/powerpc64/rtld_machine.c
224
val |= (*r_addr & 0xffff0003);
libexec/ld.so/powerpc64/rtld_machine.c
225
*r_addr = val;
libexec/login_radius/login_radius.c
193
char *val = auth_mkvalue(challenge);
libexec/login_radius/login_radius.c
194
if (val != NULL) {
libexec/login_radius/login_radius.c
196
val);
libexec/login_token/login_token.c
155
char *val = auth_mkvalue(challenge);
libexec/login_token/login_token.c
156
if (val == NULL) {
libexec/login_token/login_token.c
162
fprintf(back, BI_VALUE " challenge %s\n", val);
libexec/snmpd/snmpd_metrics/mib.c
332
int val;
libexec/snmpd/snmpd_metrics/mib.c
347
sizeof(struct kinfo_proc), &val) == NULL) {
libexec/snmpd/snmpd_metrics/mib.c
354
agentx_varbind_gauge32(vb, val);
libexec/snmpd/snmpd_metrics/mib.c
358
len = sizeof(val);
libexec/snmpd/snmpd_metrics/mib.c
359
if (sysctl(mib, 2, &val, &len, NULL, 0) == -1) {
libexec/snmpd/snmpd_metrics/mib.c
365
agentx_varbind_integer(vb, val);
libexec/snmpd/snmpd_metrics/mib.c
597
int64_t *cptime2, val;
libexec/snmpd/snmpd_metrics/mib.c
635
val = 100 -
libexec/snmpd/snmpd_metrics/mib.c
637
agentx_varbind_integer(vb, val);
libexec/tradcpp/array.h
173
INLINE void ARRAY##_set(struct ARRAY *a, unsigned index_, T *val); \
libexec/tradcpp/array.h
175
INLINE void ARRAY##_add(struct ARRAY *a, T *val, unsigned *index_ret);\
libexec/tradcpp/array.h
223
ARRAY##_set(struct ARRAY *a, unsigned index_, T *val) \
libexec/tradcpp/array.h
225
array_set(&a->arr, index_, (void *)val); \
libexec/tradcpp/array.h
235
ARRAY##_add(struct ARRAY *a, T *val, unsigned *ret) \
libexec/tradcpp/array.h
237
array_add(&a->arr, (void *)val, ret); \
libexec/tradcpp/array.h
63
ARRAYINLINE void array_set(const struct array *, unsigned index_, void *val);
libexec/tradcpp/array.h
65
ARRAYINLINE void array_add(struct array *, void *val, unsigned *index_ret);
libexec/tradcpp/array.h
86
array_set(const struct array *a, unsigned index_, void *val)
libexec/tradcpp/array.h
89
a->v[index_] = val;
libexec/tradcpp/array.h
93
array_add(struct array *a, void *val, unsigned *index_ret)
libexec/tradcpp/array.h
97
a->v[index_] = val;
libexec/tradcpp/directive.c
184
bool val;
libexec/tradcpp/directive.c
198
val = eval(&p3, expr);
libexec/tradcpp/directive.c
200
val = 0;
libexec/tradcpp/directive.c
202
ifstate_push(&lp->current, val);
libexec/tradcpp/directive.c
473
unsigned long val;
libexec/tradcpp/directive.c
491
val = strtoul(text, &moretext, 10);
libexec/tradcpp/directive.c
498
if (val > UINT_MAX) {
libexec/tradcpp/directive.c
520
lp->nextline.line = val;
libexec/tradcpp/eval.c
133
int val;
libexec/tradcpp/eval.c
142
token_create(const struct place *p, enum tokens tok, int val)
libexec/tradcpp/eval.c
149
t->val = val;
libexec/tradcpp/eval.c
176
case T_VAL: fprintf(stderr, " %d", t->val); break;
libexec/tradcpp/eval.c
289
eval_uop(enum tokens op, int val)
libexec/tradcpp/eval.c
292
case T_BANG: val = !val; break;
libexec/tradcpp/eval.c
293
case T_TILDE: val = (int)~(unsigned)val; break;
libexec/tradcpp/eval.c
294
case T_MINUS: val = -val; break;
libexec/tradcpp/eval.c
298
return val;
libexec/tradcpp/eval.c
461
t1->val = eval_uop(t2->tok, t1->val);
libexec/tradcpp/eval.c
487
t4->val = eval_bop(&t3->place,
libexec/tradcpp/eval.c
488
t4->val, t3->tok, t2->val);
libexec/tradcpp/eval.c
509
t6->val = t6->val ? t4->val : t2->val;
libexec/tradcpp/eval.c
527
t1->val = 0;
libexec/tradcpp/eval.c
596
token(struct place *p, enum tokens tok, int val)
libexec/tradcpp/eval.c
600
t = token_create(p, tok, val);
libexec/tradcpp/eval.c
610
unsigned long val;
libexec/tradcpp/eval.c
615
val = strtoul(word, &t, 0);
libexec/tradcpp/eval.c
629
if (val > INT_MAX) {
libexec/tradcpp/eval.c
634
return val;
libexec/tradcpp/eval.c
654
int val;
libexec/tradcpp/eval.c
663
val = wordval(p, expr + pos);
libexec/tradcpp/eval.c
665
token(p, T_VAL, val);
libexec/tradcpp/eval.c
760
result = t2->val != 0;
libexec/tradcpp/macro.c
879
const char *name, *val;
libexec/tradcpp/macro.c
893
val = (m != NULL) ? "1" : "0";
libexec/tradcpp/macro.c
894
debuglog(p, "defined(%s): %s", name, val);
libexec/tradcpp/macro.c
895
expand_send(es, p, val, 1);
libexec/tradcpp/main.c
144
char *val;
libexec/tradcpp/main.c
151
val = strchr(str, '=');
libexec/tradcpp/main.c
152
if (val != NULL) {
libexec/tradcpp/main.c
153
*val = '\0';
libexec/tradcpp/main.c
154
val++;
libexec/tradcpp/main.c
157
if (val) {
libexec/tradcpp/main.c
163
commandline_macro_add(p, str, &p2, val ? val : "1");
libexec/tradcpp/main.c
210
apply_builtin_macro(unsigned num, const char *name, const char *val)
libexec/tradcpp/main.c
215
macro_define_plain(&p, name, &p, val);
libexec/tradcpp/main.c
576
unsigned long val;
libexec/tradcpp/main.c
588
val = strtoul(t, &t, 10);
libexec/tradcpp/main.c
593
if (val > 64) {
libexec/tradcpp/main.c
597
mode.input_tabstop = val;
regress/lib/libc/fread/fread.c
81
int sv[2], val;
regress/lib/libc/fread/fread.c
88
val = 16;
regress/lib/libc/fread/fread.c
89
if (setsockopt(sv[0], SOL_SOCKET, SO_SNDBUF, &val, sizeof(val)) == -1)
regress/lib/libc/fread/fread.c
91
if (setsockopt(sv[0], SOL_SOCKET, SO_RCVBUF, &val, sizeof(val)) == -1)
regress/lib/libc/fread/fread.c
93
if (setsockopt(sv[1], SOL_SOCKET, SO_SNDBUF, &val, sizeof(val)) == -1)
regress/lib/libc/fread/fread.c
95
if (setsockopt(sv[1], SOL_SOCKET, SO_RCVBUF, &val, sizeof(val)) == -1)
regress/lib/libc/qsort/antiqsort.c
16
static int *val; /* item values */
regress/lib/libc/qsort/antiqsort.c
22
#define freeze(x) (val[(x)] = nsolid++)
regress/lib/libc/qsort/antiqsort.c
31
if (val[x] == gas && val[y] == gas) {
regress/lib/libc/qsort/antiqsort.c
37
if (val[x] == gas)
regress/lib/libc/qsort/antiqsort.c
39
else if (val[y] == gas)
regress/lib/libc/qsort/antiqsort.c
41
return val[x] > val[y] ? 1 : val[x] < val[y] ? -1 : 0;
regress/lib/libc/qsort/antiqsort.c
49
val = a;
regress/lib/libc/qsort/antiqsort.c
54
val[i] = gas;
regress/lib/libc/setjmp-fpu/_setjmp.c
12
#define LONGJMP(env, val) _longjmp(env, val)
regress/lib/libc/setjmp-fpu/setjmp.c
12
#define LONGJMP(env, val) longjmp(env, val)
regress/lib/libc/setjmp-fpu/sigsetjmp.c
12
#define LONGJMP(env, val) siglongjmp(env, val)
regress/lib/libc/strerror/strerror_test.c
24
check_strerror_r(int val)
regress/lib/libc/strerror/strerror_test.c
31
(void)strerror_r(val, NULL, 0); /* XXX */
regress/lib/libc/strerror/strerror_test.c
33
r = strerror_r(val, buffer, i);
regress/lib/libc/strerror/strerror_test.c
39
check_strsignal(int val)
regress/lib/libc/strerror/strerror_test.c
41
printf("%s\n", strsignal(val));
regress/lib/libc/strtonum/strtonumtest.c
27
long long val;
regress/lib/libc/strtonum/strtonumtest.c
30
val = strtonum(p, lb, ub, &q);
regress/lib/libc/strtonum/strtonumtest.c
36
fprintf(stderr, "%s [%lld-%lld] %lld ", p, lb, ub, val);
regress/lib/libc/sys/t_connect.c
52
int sd, val, slist;
regress/lib/libc/sys/t_connect.c
71
val = IP_PORTRANGE_LOW;
regress/lib/libc/sys/t_connect.c
72
if (setsockopt(sd, IPPROTO_IP, IP_PORTRANGE, &val,
regress/lib/libc/sys/t_connect.c
73
sizeof(val)) == -1)
regress/lib/libc/sys/t_getgroups.c
146
const gid_t val = 123456789;
regress/lib/libc/sys/t_getgroups.c
156
gidset[i] = val;
regress/lib/libc/sys/t_getgroups.c
162
if (gidset[i] != val)
regress/lib/libc/sys/t_listen.c
110
int sd, val;
regress/lib/libc/sys/t_listen.c
115
val = IP_PORTRANGE_LOW;
regress/lib/libc/sys/t_listen.c
116
if (setsockopt(sd, IPPROTO_IP, IP_PORTRANGE, &val,
regress/lib/libc/sys/t_listen.c
117
sizeof(val)) == -1)
regress/lib/libc/sys/t_mmap.c
108
int val;
regress/lib/libc/sys/t_mmap.c
110
val = BUFSIZE;
regress/lib/libc/sys/t_mmap.c
118
val = BUFSIZE;
regress/lib/libc/sys/t_mmap.c
120
if (setsockopt(fds[1], SOL_SOCKET, SO_RCVBUF, &val, sizeof(val)) != 0)
regress/lib/libc/sys/t_mmap.c
123
val = BUFSIZE;
regress/lib/libc/sys/t_mmap.c
125
if (setsockopt(fds[0], SOL_SOCKET, SO_SNDBUF, &val, sizeof(val)) != 0)
regress/lib/libc/sys/t_mmap.c
546
int val;
regress/lib/libc/sys/t_mmap.c
552
if (sysctlbyname("vm.user_va0_disable", &val, &len, NULL, 0) != 0)
regress/lib/libc/sys/t_mmap.c
556
map_check(map, val);
regress/lib/libc/sys/t_mmap.c
559
map_check(map, val);
regress/lib/libc/sys/t_mmap.c
562
map_check(map, val);
regress/lib/libc/sys/t_mmap.c
565
map_check(map, val);
regress/lib/libc/sys/t_mmap.c
568
map_check(map, val);
regress/lib/libcrypto/asn1/asn1basic.c
1017
int64_t val;
regress/lib/libcrypto/asn1/asn1basic.c
1054
if (ASN1_INTEGER_get_int64(&val, aint)) {
regress/lib/libcrypto/asn1/asn1basic.c
1065
if (!ASN1_INTEGER_get_int64(&val, aint)) {
regress/lib/libcrypto/asn1/asn1basic.c
1070
if (val != INT64_MIN) {
regress/lib/libcrypto/asn1/asn1basic.c
1085
if (!ASN1_INTEGER_get_int64(&val, aint)) {
regress/lib/libcrypto/asn1/asn1basic.c
1090
if (val != INT64_MAX) {
regress/lib/libcrypto/exdata/exdata_test.c
79
int val;
regress/lib/libcrypto/mlkem/parse_test_file.c
37
int val;
regress/lib/libcrypto/mlkem/parse_test_file.c
385
parse_state_set_int(struct parse *p, int val)
regress/lib/libcrypto/mlkem/parse_test_file.c
390
line_data_set_int(parse_state_data(p)[parse_cur(p)], val);
regress/lib/libcrypto/mlkem/parse_test_file.c
67
*out = ld->val;
regress/lib/libcrypto/mlkem/parse_test_file.c
77
line_data_set_int(struct line_data *ld, int val)
regress/lib/libcrypto/mlkem/parse_test_file.c
79
ld->val = val;
regress/lib/libedit/keymacro/test_get.c
105
irc = keymacro_get(&el, &ch, &val);
regress/lib/libedit/keymacro/test_get.c
108
if (val.str != NULL)
regress/lib/libedit/keymacro/test_get.c
109
errx(1, "ix %ls != NULL", val.str);
regress/lib/libedit/keymacro/test_get.c
115
irc = keymacro_get(&el, &ch, &val);
regress/lib/libedit/keymacro/test_get.c
72
keymacro_value_t val;
regress/lib/libedit/keymacro/test_get.c
85
irc = keymacro_get(&el, &ch, &val);
regress/lib/libedit/keymacro/test_get.c
88
if (val.cmd != VI_ADD)
regress/lib/libedit/keymacro/test_get.c
89
errx(1, "ad %u != VI_ADD", val.cmd);
regress/lib/libedit/keymacro/test_get.c
95
irc = keymacro_get(&el, &ch, &val);
regress/lib/libedit/keymacro/test_get.c
98
if (wcscmp(val.str, L"repl") != 0)
regress/lib/libedit/keymacro/test_get.c
99
errx(1, "al %ls != repl", val.str);
regress/lib/libedit/read/glue.c
44
keymacro_get(EL, wchar_t *ch, keymacro_value_t *val)
regress/lib/libedit/read/glue.c
50
val->cmd = ED_COMMAND;
regress/lib/libedit/read/glue.c
53
val->str = value;
regress/lib/libedit/read/glue.c
56
val->str = NULL;
regress/lib/libm/fpaccuracy/Gamma.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/INV.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/Pix.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/acos.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/acosh.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/asin.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/asinh.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/atan.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/atanh.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/cos.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/cosh.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/erf.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/erfc.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/exp.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/j0.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/j1.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/lgamma.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/log.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/log10.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/pow2_x.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/powx_275.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/sin.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/sincos.c
31
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/sincos2.c
33
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/sinh.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/sqrt.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/tan.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/tanh.c
29
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/trailer.h
60
t = F(q->arg)*t1*t2 - p->val;
regress/lib/libm/fpaccuracy/trailer.h
64
t = F(q->arg)*t1 - p->val;
regress/lib/libm/fpaccuracy/trailer.h
68
t = scalb(q->res,p->val_e) - p->val;
regress/lib/libm/fpaccuracy/y0.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libm/fpaccuracy/y1.c
30
static struct input_point { double arg_m, val, eps;
regress/lib/libpthread/dlopen/dlopen.c
512
int val;
regress/lib/libpthread/dlopen/dlopen.c
516
unsigned short val;
regress/lib/libpthread/dlopen/dlopen.c
519
semarg.array = &val;
regress/lib/libpthread/dlopen/dlopen.c
520
val = 0;
regress/lib/libpthread/semaphore/sem_destroy/sem_destroy.c
12
int val;
regress/lib/libpthread/semaphore/sem_destroy/sem_destroy.c
28
val = 0;
regress/lib/libpthread/semaphore/sem_destroy/sem_destroy.c
55
val++;
regress/lib/libpthread/semaphore/sem_destroy/sem_destroy.c
70
val--;
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
15
int val;
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
18
CHECKe(sem_getvalue(&sem, &val));
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
19
ASSERT(val == 0);
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
22
CHECKe(sem_getvalue(&sem, &val));
regress/lib/libpthread/semaphore/sem_getvalue/sem_getvalue.c
23
ASSERT(val == 1);
regress/lib/libpthread/semaphore/sem_trywait/sem_trywait.c
16
int val;
regress/lib/libpthread/semaphore/sem_trywait/sem_trywait.c
29
CHECKe(sem_getvalue(&sem, &val));
regress/lib/libpthread/semaphore/sem_trywait/sem_trywait.c
30
ASSERT(val == 0);
regress/lib/libsndio/vol/vol.c
27
onvol(void *addr, unsigned val)
regress/lib/libsndio/vol/vol.c
29
vol = val;
regress/lib/libssl/bytestring/bytestringtest.c
288
int val;
regress/lib/libssl/bytestring/bytestringtest.c
295
val = 2;
regress/lib/libssl/bytestring/bytestringtest.c
296
CHECK(CBS_get_optional_asn1_bool(&data, &val, 0x0a, 0));
regress/lib/libssl/bytestring/bytestringtest.c
297
CHECK(val == 0);
regress/lib/libssl/bytestring/bytestringtest.c
300
val = 2;
regress/lib/libssl/bytestring/bytestringtest.c
301
CHECK(CBS_get_optional_asn1_bool(&data, &val, 0x0a, 0));
regress/lib/libssl/bytestring/bytestringtest.c
302
CHECK(val == 1);
regress/lib/libssl/bytestring/bytestringtest.c
305
val = 2;
regress/lib/libssl/bytestring/bytestringtest.c
306
CHECK(CBS_get_optional_asn1_bool(&data, &val, 0x0a, 1));
regress/lib/libssl/bytestring/bytestringtest.c
307
CHECK(val == 0);
regress/lib/libssl/bytestring/bytestringtest.c
310
CHECK(!CBS_get_optional_asn1_bool(&data, &val, 0x0a, 1));
regress/lib/libssl/dtls/dtlstest.c
404
dtls_info_callback(const SSL *ssl, int type, int val)
regress/lib/libutil/ber/ber_test.c
329
long long val;
regress/lib/libutil/ber/ber_test.c
368
if (ober_scanf_elements(elm, ".", &val) == -1) {
regress/lib/libutil/ber/ber_test.c
384
if (ober_get_integer(elm, &val) == -1) {
regress/lib/libutil/ber/ber_test.c
388
if (ober_scanf_elements(elm, "i", &val) == -1) {
regress/lib/libutil/ber/ber_test.c
392
if (ober_scanf_elements(elm, "d", &val) == -1) {
regress/lib/libutil/ber/ber_test.c
398
if (ober_get_enumerated(elm, &val) == -1) {
regress/lib/libutil/ber/ber_test.c
402
if (ober_scanf_elements(elm, "E", &val) == -1) {
regress/lib/libutil/ber/ber_test.c
428
if (ober_scanf_elements(elm, "0", &val) == -1) {
regress/lib/libutil/ber/ber_test.c
500
int val = 1, len = 0;
regress/lib/libutil/ber/ber_test.c
506
elm = ober_printf_elements(elm, "d", val);
regress/lib/libutil/ber/ber_test.c
683
long long val;
regress/lib/libutil/ber/ber_test.c
687
if (ober_scanf_elements(elm, "0", &val) != -1) {
regress/lib/libutil/ber/ber_test.c
700
if (ober_scanf_elements(elm, "{i}", &val) != 0) {
regress/lib/libutil/ber/ber_test.c
708
if (ober_scanf_elements(elm, "{lS}", &val) != -1) {
regress/lib/libutil/ber/ber_test_int_i.c
527
long long val;
regress/lib/libutil/ber/ber_test_int_i.c
555
if (ober_get_integer(elm, &val) == -1) {
regress/lib/libutil/ber/ber_test_int_i.c
559
if (val != test_vectors[i].value) {
regress/lib/libutil/ber/ber_test_int_i.c
561
val, test_vectors[i].value);
regress/lib/libutil/ber/ber_test_int_i.c
564
if (ober_scanf_elements(elm, "i", &val) == -1) {
regress/lib/libutil/ber/ber_test_int_i.c
569
if (val != test_vectors[i].value) {
regress/lib/libutil/ber/ber_test_int_i.c
570
printf("got %lld, expected %lld\n", val,
regress/lib/libutil/ber/ber_test_int_i.c
622
long long val;
regress/lib/libutil/ber/ber_test_int_i.c
639
if (ober_get_integer(elm, &val) == -1) {
regress/lib/libutil/ber/ber_test_int_i.c
643
if (val != test_vectors[i].value) {
regress/lib/libutil/ber/ber_test_int_i.c
645
val, test_vectors[i].value);
regress/lib/libutil/ber/ber_test_int_i.c
648
if (ober_scanf_elements(elm, "i", &val) == -1) {
regress/lib/libutil/ber/ber_test_int_i.c
653
if (val != test_vectors[i].value) {
regress/lib/libutil/ber/ber_test_int_i.c
654
printf("got %lld, expected %lld\n", val,
regress/lib/libz/infcover.c
248
unsigned next, val;
regress/lib/libz/infcover.c
254
val = 1;
regress/lib/libz/infcover.c
257
val = (val << 4) + *hex - '0';
regress/lib/libz/infcover.c
259
val = (val << 4) + *hex - 'A' + 10;
regress/lib/libz/infcover.c
261
val = (val << 4) + *hex - 'a' + 10;
regress/lib/libz/infcover.c
262
else if (val != 1 && val < 32) /* one digit followed by delimiter */
regress/lib/libz/infcover.c
263
val += 240; /* make it look like two digits */
regress/lib/libz/infcover.c
264
if (val > 255) { /* have two digits */
regress/lib/libz/infcover.c
265
in[next++] = val & 0xff; /* save the decoded byte */
regress/lib/libz/infcover.c
266
val = 1; /* start over */
regress/sbin/ifconfig/ifaddr.c
168
int prefix(void *val, int);
regress/sbin/ifconfig/ifaddr.c
1787
prefix(void *val, int size)
regress/sbin/ifconfig/ifaddr.c
1789
u_char *nam = (u_char *)val;
regress/sbin/ifconfig/ifaddr.c
793
setia6pltime(const char *val, int d)
regress/sbin/ifconfig/ifaddr.c
796
setia6lifetime("pltime", val);
regress/sbin/ifconfig/ifaddr.c
800
setia6vltime(const char *val, int d)
regress/sbin/ifconfig/ifaddr.c
803
setia6lifetime("vltime", val);
regress/sbin/ifconfig/ifaddr.c
807
setia6lifetime(const char *cmd, const char *val)
regress/sbin/ifconfig/ifaddr.c
812
newval = strtonum(val, 0, 1000000, &errmsg);
regress/sbin/ifconfig/ifaddr.c
814
errx(1, "invalid %s %s: %s", cmd, val, errmsg);
regress/sbin/ifconfig/ifaddr.c
830
setia6eui64(const char *cmd, int val)
regress/sbin/ifconfig/ifaddr.c
866
get_string(const char *val, const char *sep, u_int8_t *buf, int *lenp)
regress/sbin/ifconfig/ifaddr.c
871
hexstr = (val[0] == '0' && tolower((u_char)val[1]) == 'x');
regress/sbin/ifconfig/ifaddr.c
873
val += 2;
regress/sbin/ifconfig/ifaddr.c
875
if (*val == '\0')
regress/sbin/ifconfig/ifaddr.c
877
if (sep != NULL && strchr(sep, *val) != NULL) {
regress/sbin/ifconfig/ifaddr.c
878
val++;
regress/sbin/ifconfig/ifaddr.c
882
if (!isxdigit((u_char)val[0]) ||
regress/sbin/ifconfig/ifaddr.c
883
!isxdigit((u_char)val[1])) {
regress/sbin/ifconfig/ifaddr.c
897
*p++ = (tohex((u_char)val[0]) << 4) |
regress/sbin/ifconfig/ifaddr.c
898
tohex((u_char)val[1]);
regress/sbin/ifconfig/ifaddr.c
900
val += 2;
regress/sbin/ifconfig/ifaddr.c
902
if (*val == '\\' &&
regress/sbin/ifconfig/ifaddr.c
903
sep != NULL && strchr(sep, *(val + 1)) != NULL)
regress/sbin/ifconfig/ifaddr.c
904
val++;
regress/sbin/ifconfig/ifaddr.c
905
*p++ = *val++;
regress/sbin/ifconfig/ifaddr.c
912
return val;
regress/sys/crypto/aesctr/aesctr.c
210
u_long val;
regress/sys/crypto/aesctr/aesctr.c
227
val = strtoul(&from[j*3], &ep, 16);
regress/sys/crypto/aesctr/aesctr.c
228
p[j] = (u_char)val;
regress/sys/crypto/chachapoly/chachapoly_test.c
376
u_long val;
regress/sys/crypto/chachapoly/chachapoly_test.c
399
val = strtoul(&from[j*3], &ep, 16);
regress/sys/crypto/chachapoly/chachapoly_test.c
400
p[j] = (u_char)val;
regress/sys/crypto/gmac/gmac_test.c
698
u_long val;
regress/sys/crypto/gmac/gmac_test.c
720
val = strtoul(&from[j*3], &ep, 16);
regress/sys/crypto/gmac/gmac_test.c
721
p[j] = (u_char)val;
regress/sys/kern/futex/futex.h
25
futex_wait(volatile uint32_t *p, int val, int priv)
regress/sys/kern/futex/futex.h
27
while (*p != (uint32_t)val)
regress/sys/kern/futex/futex.h
28
futex(p, FUTEX_WAIT | priv, val, NULL, NULL);
regress/sys/kern/futex/futex.h
32
futex_twait(volatile uint32_t *p, int val, clockid_t clockid,
regress/sys/kern/futex/futex.h
35
return futex(p, FUTEX_WAIT | priv, val, timeout, NULL);
regress/sys/kern/signal/sigpthread/sigpthread.c
198
val = runner(0);
regress/sys/kern/signal/sigpthread/sigpthread.c
199
ret = (int)val;
regress/sys/kern/signal/sigpthread/sigpthread.c
202
errno = pthread_join(threads[tnum], &val);
regress/sys/kern/signal/sigpthread/sigpthread.c
205
ret = (int)val;
regress/sys/kern/signal/sigpthread/sigpthread.c
62
void *val;
regress/sys/kern/sysvsem/semtest.c
196
sun.val = 1;
regress/sys/kern/sysvsem/semtest.c
69
int val; /* value for SETVAL */
regress/sys/net/rtable/kern_compat.h
104
#define WRITE_ONCE(x, val) ({ \
regress/sys/net/rtable/kern_compat.h
105
typeof(x) __tmp = (val); \
regress/sys/netinet/udpthread/udpthread.c
194
int sock, val;
regress/sys/netinet/udpthread/udpthread.c
200
val = 1;
regress/sys/netinet/udpthread/udpthread.c
201
len = sizeof(val);
regress/sys/netinet/udpthread/udpthread.c
202
if (setsockopt(sock, SOL_SOCKET, SO_REUSEPORT, &val, len) < 0)
regress/sys/netinet/udpthread/udpthread.c
648
int af, val;
regress/sys/netinet/udpthread/udpthread.c
670
val = 1;
regress/sys/netinet/udpthread/udpthread.c
671
len = sizeof(val);
regress/sys/netinet/udpthread/udpthread.c
673
&val, len) < 0)
regress/sys/netinet/udpthread/udpthread.c
693
val = 1;
regress/sys/netinet/udpthread/udpthread.c
694
len = sizeof(val);
regress/sys/netinet/udpthread/udpthread.c
696
SO_REUSEPORT, &val, len) < 0)
regress/sys/nfs/mmap-sysctl-copyin.c
33
int fd, val;
regress/sys/nfs/mmap-sysctl-copyin.c
44
if (sysctl(mib, miblen, &val, &len, NULL, 0) == -1)
regress/sys/nfs/mmap-sysctl-copyin.c
48
if (write(fd, &val, len) == -1)
regress/usr.bin/mandoc/db/binedit/binedit.c
33
int32_t val; /* Value to be written. */
regress/usr.bin/mandoc/db/binedit/binedit.c
39
dest = pos = val = 0;
regress/usr.bin/mandoc/db/binedit/binedit.c
57
dest = val;
regress/usr.bin/mandoc/db/binedit/binedit.c
69
val += i;
regress/usr.bin/mandoc/db/binedit/binedit.c
79
val = be32toh(i);
regress/usr.bin/mandoc/db/binedit/binedit.c
96
val = getint(&cmd);
regress/usr.bin/mandoc/db/binedit/binedit.c
97
i = htobe32(val);
regress/usr.bin/ssh/unittests/authopt/tests.c
198
#define FLAG_TEST(keyword, var, val) \
regress/usr.bin/ssh/unittests/authopt/tests.c
202
expected->var = val; \
regress/usr.bin/ssh/unittests/authopt/tests.c
206
expected->var = val; \
regress/usr.bin/ssh/unittests/authopt/tests.c
228
#define STRING_TEST(keyword, var, val) \
regress/usr.bin/ssh/unittests/authopt/tests.c
232
expected->var = strdup(val); \
regress/usr.bin/ssh/unittests/authopt/tests.c
234
opts = sshauthopt_parse(keyword "=" #val, &errstr); \
regress/usr.bin/ssh/unittests/authopt/tests.c
237
expected->var = strdup(val); \
regress/usr.bin/ssh/unittests/authopt/tests.c
240
"restrict," keyword "=" #val ",restrict", &errstr); \
regress/usr.bin/ssh/unittests/authopt/tests.c
253
#define ARRAY_TEST(label, keywords, var, nvar, val) \
regress/usr.bin/ssh/unittests/authopt/tests.c
257
expected->var = commasplit(val, &expected->nvar); \
regress/usr.bin/ssh/unittests/authopt/tests.c
262
expected->var = commasplit(val, &expected->nvar); \
regress/usr.bin/ssh/unittests/authopt/tests.c
419
#define FLAG_CASE(keybase, label, keyname, keywords, mostly_off, var, val) \
regress/usr.bin/ssh/unittests/authopt/tests.c
424
expected->var = val; \
regress/usr.bin/ssh/unittests/misc/test_expand.c
72
#define CHECK_ONE(val, expect) \
regress/usr.bin/ssh/unittests/misc/test_expand.c
73
ASSERT_STRING_EQ(val, expect); \
regress/usr.bin/ssh/unittests/misc/test_expand.c
74
free(val);
regress/usr.sbin/syslogd/logflush.c
41
int pair[2], klog, val;
regress/usr.sbin/syslogd/logflush.c
49
val = 1<<20;
regress/usr.sbin/syslogd/logflush.c
50
if (setsockopt(pair[0], SOL_SOCKET, SO_RCVBUF, &val, sizeof(val)) == -1)
regress/usr.sbin/syslogd/logflush.c
52
if (setsockopt(pair[1], SOL_SOCKET, SO_SNDBUF, &val, sizeof(val)) == -1)
sbin/atactl/atactl.c
1285
int val;
sbin/atactl/atactl.c
1296
if ((val = strtoval(argv[1], smart_autosave)) == -1)
sbin/atactl/atactl.c
1298
req.sec_num = val;
sbin/atactl/atactl.c
1316
int val;
sbin/atactl/atactl.c
1327
if ((val = strtoval(argv[1], smart_offline)) == -1)
sbin/atactl/atactl.c
1329
req.sec_num = val;
sbin/atactl/atactl.c
1405
int val;
sbin/atactl/atactl.c
1422
if ((val = strtoval(argv[1], smart_readlog)) == -1)
sbin/atactl/atactl.c
1424
req.sec_num = val;
sbin/atactl/atactl.c
488
valtostr(int val, struct valinfo *vinfo, const char *def)
sbin/atactl/atactl.c
491
if (val == vinfo->value)
sbin/dhcp6leased/parse.y
371
char *p, *val;
sbin/dhcp6leased/parse.y
401
val = symget(buf);
sbin/dhcp6leased/parse.y
402
if (val == NULL) {
sbin/dhcp6leased/parse.y
406
p = val + strlen(val) - 1;
sbin/dhcp6leased/parse.y
408
while (p >= val) {
sbin/dhcp6leased/parse.y
626
free(sym->val);
sbin/dhcp6leased/parse.y
646
symset(const char *nam, const char *val, int persist)
sbin/dhcp6leased/parse.y
660
free(sym->val);
sbin/dhcp6leased/parse.y
673
sym->val = strdup(val);
sbin/dhcp6leased/parse.y
674
if (sym->val == NULL) {
sbin/dhcp6leased/parse.y
693
return (sym->val);
sbin/dhcp6leased/parse.y
71
char *val;
sbin/dhcpleased/parse.y
216
int not_hex = 0, val;
sbin/dhcpleased/parse.y
232
if (sscanf(p, "%x%c", &val, &excess) != 1 ||
sbin/dhcpleased/parse.y
233
val < 0 || val > 0xff) {
sbin/dhcpleased/parse.y
237
buf[i++] = (val & 0xff);
sbin/dhcpleased/parse.y
499
char *p, *val;
sbin/dhcpleased/parse.y
529
val = symget(buf);
sbin/dhcpleased/parse.y
530
if (val == NULL) {
sbin/dhcpleased/parse.y
534
p = val + strlen(val) - 1;
sbin/dhcpleased/parse.y
536
while (p >= val) {
sbin/dhcpleased/parse.y
756
free(sym->val);
sbin/dhcpleased/parse.y
771
symset(const char *nam, const char *val, int persist)
sbin/dhcpleased/parse.y
785
free(sym->val);
sbin/dhcpleased/parse.y
798
sym->val = strdup(val);
sbin/dhcpleased/parse.y
799
if (sym->val == NULL) {
sbin/dhcpleased/parse.y
813
char *sym, *val;
sbin/dhcpleased/parse.y
816
if ((val = strrchr(s, '=')) == NULL)
sbin/dhcpleased/parse.y
818
sym = strndup(s, val - s);
sbin/dhcpleased/parse.y
821
ret = symset(sym, val + 1, 1);
sbin/dhcpleased/parse.y
835
return (sym->val);
sbin/dhcpleased/parse.y
88
char *val;
sbin/disklabel/editor.c
1932
apply_unit(double val, u_char unit, u_int64_t *n)
sbin/disklabel/editor.c
1953
val *= factor / DEV_BSIZE;
sbin/disklabel/editor.c
1954
if (val > (double)ULLONG_MAX)
sbin/disklabel/editor.c
1956
*n = val;
sbin/disklabel/editor.c
1961
parse_sizespec(const char *buf, double *val, char **unit)
sbin/disklabel/editor.c
1964
*val = strtod(buf, unit);
sbin/disklabel/editor.c
1965
if (errno == ERANGE || *val < 0 || *val > (double)ULLONG_MAX)
sbin/disklabel/editor.c
1967
if (*val == 0 && *unit == buf)
sbin/dump/main.c
629
long long val;
sbin/dump/main.c
634
val = strtonum(optarg, vmin, vmax, &errstr);
sbin/dump/main.c
639
return (val);
sbin/fdisk/cmd.c
182
uint64_t val;
sbin/fdisk/cmd.c
187
val = strtoull(flagstr, &ep, 16);
sbin/fdisk/cmd.c
189
(gh.gh_sig != GPTSIGNATURE && val > 0xff)) {
sbin/fdisk/cmd.c
197
val = strtonum(flagstr, 0, INT64_MAX, &errstr);
sbin/fdisk/cmd.c
199
val = strtonum(flagstr, 0, 0xff, &errstr);
sbin/fdisk/cmd.c
206
*flagvalue = val;
sbin/fdisk/cmd.c
503
uint64_t val;
sbin/fdisk/cmd.c
519
if (parseflag(flag, &val) == -1)
sbin/fdisk/cmd.c
522
gp[pn].gp_attrs = val;
sbin/fdisk/cmd.c
524
mbr->mbr_prt[pn].prt_flag = val;
sbin/fdisk/cmd.c
525
printf("Partition %d flag value set to 0x%llx.\n", pn, val);
sbin/fsck_ffs/fsck.h
126
#define IBLK_SET(bp, i, val) do { \
sbin/fsck_ffs/fsck.h
128
(bp)->b_un.b_indir1[i] = (val); \
sbin/fsck_ffs/fsck.h
130
(bp)->b_un.b_indir2[i] = (val); \
sbin/fsck_ffs/fsck.h
58
#define DIP_SET(dp, field, val) do { \
sbin/fsck_ffs/fsck.h
60
(dp)->dp1.field = (val); \
sbin/fsck_ffs/fsck.h
62
(dp)->dp2.field = (val); \
sbin/fsdb/fsdb.c
485
char *p, *val;
sbin/fsdb/fsdb.c
500
while ((val = strsep(&p, "/")) != NULL && *val == '\0')
sbin/fsdb/fsdb.c
502
if (val) {
sbin/fsdb/fsdb.c
503
printf("component `%s': ", val);
sbin/fsdb/fsdb.c
505
if (!dolookup(val)) {
sbin/fsdb/fsdb.c
858
char *p, *val;
sbin/fsdb/fsdb.c
866
nsec = strtoul(++p, &val, 0);
sbin/fsdb/fsdb.c
867
if (val == p || *val != '\0' || nsec >= 1000000000 || nsec < 0) {
sbin/fsdb/fsdbutil.c
57
char *p, *val;
sbin/fsdb/fsdbutil.c
60
while ((val = strsep(&p, " \t\n")) != NULL && *val == '\0')
sbin/fsdb/fsdbutil.c
62
if (val)
sbin/fsdb/fsdbutil.c
63
argv[i] = val;
sbin/growfs/growfs.c
106
#define DIP_SET(dp, field, val) do { \
sbin/growfs/growfs.c
108
(dp)->dp1.field = (val); \
sbin/growfs/growfs.c
110
(dp)->dp2.field = (val); \
sbin/ifconfig/brconfig.c
103
setdiscover(const char *val, int d)
sbin/ifconfig/brconfig.c
105
bridge_ifsetflag(val, IFBIF_DISCOVER);
sbin/ifconfig/brconfig.c
109
unsetdiscover(const char *val, int d)
sbin/ifconfig/brconfig.c
111
bridge_ifclrflag(val, IFBIF_DISCOVER);
sbin/ifconfig/brconfig.c
115
setblocknonip(const char *val, int d)
sbin/ifconfig/brconfig.c
117
bridge_ifsetflag(val, IFBIF_BLOCKNONIP);
sbin/ifconfig/brconfig.c
121
unsetblocknonip(const char *val, int d)
sbin/ifconfig/brconfig.c
123
bridge_ifclrflag(val, IFBIF_BLOCKNONIP);
sbin/ifconfig/brconfig.c
127
setlearn(const char *val, int d)
sbin/ifconfig/brconfig.c
129
bridge_ifsetflag(val, IFBIF_LEARNING);
sbin/ifconfig/brconfig.c
133
unsetlearn(const char *val, int d)
sbin/ifconfig/brconfig.c
135
bridge_ifclrflag(val, IFBIF_LEARNING);
sbin/ifconfig/brconfig.c
139
setlocked(const char *val, int d)
sbin/ifconfig/brconfig.c
141
bridge_ifsetflag(val, IFBIF_LOCKED);
sbin/ifconfig/brconfig.c
145
unsetlocked(const char *val, int d)
sbin/ifconfig/brconfig.c
147
bridge_ifclrflag(val, IFBIF_LOCKED);
sbin/ifconfig/brconfig.c
151
setpvptags(const char *val, int d)
sbin/ifconfig/brconfig.c
153
bridge_ifsetflag(val, IFBIF_PVLAN_PTAGS);
sbin/ifconfig/brconfig.c
157
unsetpvptags(const char *val, int d)
sbin/ifconfig/brconfig.c
159
bridge_ifclrflag(val, IFBIF_PVLAN_PTAGS);
sbin/ifconfig/brconfig.c
163
setstp(const char *val, int d)
sbin/ifconfig/brconfig.c
165
bridge_ifsetflag(val, IFBIF_STP);
sbin/ifconfig/brconfig.c
169
unsetstp(const char *val, int d)
sbin/ifconfig/brconfig.c
171
bridge_ifclrflag(val, IFBIF_STP);
sbin/ifconfig/brconfig.c
175
setedge(const char *val, int d)
sbin/ifconfig/brconfig.c
177
bridge_ifsetflag(val, IFBIF_BSTP_EDGE);
sbin/ifconfig/brconfig.c
181
unsetedge(const char *val, int d)
sbin/ifconfig/brconfig.c
183
bridge_ifclrflag(val, IFBIF_BSTP_EDGE);
sbin/ifconfig/brconfig.c
187
setautoedge(const char *val, int d)
sbin/ifconfig/brconfig.c
189
bridge_ifsetflag(val, IFBIF_BSTP_AUTOEDGE);
sbin/ifconfig/brconfig.c
193
unsetautoedge(const char *val, int d)
sbin/ifconfig/brconfig.c
195
bridge_ifclrflag(val, IFBIF_BSTP_AUTOEDGE);
sbin/ifconfig/brconfig.c
199
setptp(const char *val, int d)
sbin/ifconfig/brconfig.c
201
bridge_ifsetflag(val, IFBIF_BSTP_PTP);
sbin/ifconfig/brconfig.c
205
unsetptp(const char *val, int d)
sbin/ifconfig/brconfig.c
207
bridge_ifclrflag(val, IFBIF_BSTP_PTP);
sbin/ifconfig/brconfig.c
211
setautoptp(const char *val, int d)
sbin/ifconfig/brconfig.c
213
bridge_ifsetflag(val, IFBIF_BSTP_AUTOPTP);
sbin/ifconfig/brconfig.c
217
unsetautoptp(const char *val, int d)
sbin/ifconfig/brconfig.c
219
bridge_ifclrflag(val, IFBIF_BSTP_AUTOPTP);
sbin/ifconfig/brconfig.c
275
bridge_flushall(const char *val, int p)
sbin/ifconfig/brconfig.c
286
bridge_flush(const char *val, int p)
sbin/ifconfig/brconfig.c
505
bridge_protect(const char *ifsname, const char *val)
sbin/ifconfig/brconfig.c
517
optlist = strdup(val);
sbin/ifconfig/brconfig.c
531
err(1, "%s: %s", ifname, val);
sbin/ifconfig/brconfig.c
551
bridge_pvid(const char *ifsname, const char *val)
sbin/ifconfig/brconfig.c
558
if (strcmp(val, "default") == 0)
sbin/ifconfig/brconfig.c
560
else if (strcmp(val, "none") == 0)
sbin/ifconfig/brconfig.c
562
else if (strcmp(val, "passthrough") == 0 ||
sbin/ifconfig/brconfig.c
563
strcmp(val, "passthru") == 0)
sbin/ifconfig/brconfig.c
568
breq.ifbr_pvid = strtonum(val,
sbin/ifconfig/brconfig.c
572
ifname, ifsname, val, errstr);
sbin/ifconfig/brconfig.c
577
err(1, "%s untagged %s %s", ifname, ifsname, val);
sbin/ifconfig/brconfig.c
663
const char *val;
sbin/ifconfig/brconfig.c
669
val = arg + 1;
sbin/ifconfig/brconfig.c
673
val = arg + 1;
sbin/ifconfig/brconfig.c
677
val = arg + 1;
sbin/ifconfig/brconfig.c
681
val = arg;
sbin/ifconfig/brconfig.c
685
str = strdup(val);
sbin/ifconfig/brconfig.c
869
bridge_ifprio(const char *ifsname, const char *val)
sbin/ifconfig/brconfig.c
874
breq.ifbr_priority = strtonum(val, 0, UINT8_MAX, &errstr);
sbin/ifconfig/brconfig.c
876
errx(1, "ifpriority %s is: %s", val, errstr);
sbin/ifconfig/brconfig.c
882
err(1, "%s: %s", ifname, val);
sbin/ifconfig/brconfig.c
886
bridge_ifcost(const char *ifsname, const char *val)
sbin/ifconfig/brconfig.c
891
breq.ifbr_path_cost = strtonum(val, 0, UINT32_MAX, &errstr);
sbin/ifconfig/brconfig.c
893
errx(1, "ifcost %s is: %s", val, errstr);
sbin/ifconfig/brconfig.c
899
err(1, "%s: %s", ifname, val);
sbin/ifconfig/ifconfig.c
1390
setifdesc(const char *val, int ignored)
sbin/ifconfig/ifconfig.c
1392
ifr.ifr_data = (caddr_t)val;
sbin/ifconfig/ifconfig.c
1521
setia6pltime(const char *val, int d)
sbin/ifconfig/ifconfig.c
1524
setia6lifetime("pltime", val);
sbin/ifconfig/ifconfig.c
1528
setia6vltime(const char *val, int d)
sbin/ifconfig/ifconfig.c
1531
setia6lifetime("vltime", val);
sbin/ifconfig/ifconfig.c
1535
setia6lifetime(const char *cmd, const char *val)
sbin/ifconfig/ifconfig.c
1540
newval = strtonum(val, 0, 1000000, &errmsg);
sbin/ifconfig/ifconfig.c
1542
errx(1, "invalid %s %s: %s", cmd, val, errmsg);
sbin/ifconfig/ifconfig.c
1558
setia6eui64(const char *cmd, int val)
sbin/ifconfig/ifconfig.c
1594
setautoconf(const char *cmd, int val)
sbin/ifconfig/ifconfig.c
1598
setifxflags("inet", val * IFXF_AUTOCONF4);
sbin/ifconfig/ifconfig.c
1601
if (val > 0)
sbin/ifconfig/ifconfig.c
1613
settemporary(const char *cmd, int val)
sbin/ifconfig/ifconfig.c
1617
setifxflags("inet6", val * IFXF_AUTOCONF6TEMP);
sbin/ifconfig/ifconfig.c
1626
setifmetric(const char *val, int ignored)
sbin/ifconfig/ifconfig.c
1632
ifr.ifr_metric = strtonum(val, 0, INT_MAX, &errmsg);
sbin/ifconfig/ifconfig.c
1634
errx(1, "metric %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
1641
setifmtu(const char *val, int d)
sbin/ifconfig/ifconfig.c
1647
ifr.ifr_mtu = strtonum(val, 0, INT_MAX, &errmsg);
sbin/ifconfig/ifconfig.c
1649
errx(1, "mtu %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
1655
setifllprio(const char *val, int d)
sbin/ifconfig/ifconfig.c
1661
ifr.ifr_llprio = strtonum(val, 0, UCHAR_MAX, &errmsg);
sbin/ifconfig/ifconfig.c
1663
errx(1, "llprio %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
1707
get_string(const char *val, const char *sep, u_int8_t *buf, int *lenp)
sbin/ifconfig/ifconfig.c
1712
hexstr = (val[0] == '0' && tolower((u_char)val[1]) == 'x');
sbin/ifconfig/ifconfig.c
1714
val += 2;
sbin/ifconfig/ifconfig.c
1716
if (*val == '\0')
sbin/ifconfig/ifconfig.c
1718
if (sep != NULL && strchr(sep, *val) != NULL) {
sbin/ifconfig/ifconfig.c
1719
val++;
sbin/ifconfig/ifconfig.c
1723
if (!isxdigit((u_char)val[0]) ||
sbin/ifconfig/ifconfig.c
1724
!isxdigit((u_char)val[1])) {
sbin/ifconfig/ifconfig.c
1738
*p++ = (tohex((u_char)val[0]) << 4) |
sbin/ifconfig/ifconfig.c
1739
tohex((u_char)val[1]);
sbin/ifconfig/ifconfig.c
1741
val += 2;
sbin/ifconfig/ifconfig.c
1743
if (*val == '\\' &&
sbin/ifconfig/ifconfig.c
1744
sep != NULL && strchr(sep, *(val + 1)) != NULL)
sbin/ifconfig/ifconfig.c
1745
val++;
sbin/ifconfig/ifconfig.c
1746
*p++ = *val++;
sbin/ifconfig/ifconfig.c
1753
return val;
sbin/ifconfig/ifconfig.c
1810
setifnwid(const char *val, int d)
sbin/ifconfig/ifconfig.c
1829
if (get_string(val, NULL, nwid.i_nwid, &len) == NULL)
sbin/ifconfig/ifconfig.c
1853
setifjoin(const char *val, int d)
sbin/ifconfig/ifconfig.c
1871
if (get_string(val, NULL, join.i_nwid, &len) == NULL)
sbin/ifconfig/ifconfig.c
1884
delifjoin(const char *val, int d)
sbin/ifconfig/ifconfig.c
1900
if (get_string(val, NULL, join.i_nwid, &len) == NULL)
sbin/ifconfig/ifconfig.c
1912
delifjoinlist(const char *val, int d)
sbin/ifconfig/ifconfig.c
1925
setifbssid(const char *val, int d)
sbin/ifconfig/ifconfig.c
1935
ea = ether_aton((char*)val);
sbin/ifconfig/ifconfig.c
1937
warnx("malformed BSSID: %s", val);
sbin/ifconfig/ifconfig.c
1949
setifnwkey(const char *val, int d)
sbin/ifconfig/ifconfig.c
1964
} else if (strcasecmp("persist", val) == 0) {
sbin/ifconfig/ifconfig.c
1970
} else if (strncasecmp("persist:", val, 8) == 0) {
sbin/ifconfig/ifconfig.c
1971
val += 8;
sbin/ifconfig/ifconfig.c
1977
if (isdigit((unsigned char)val[0]) && val[1] == ':') {
sbin/ifconfig/ifconfig.c
1979
nwkey.i_defkid = val[0] - '0';
sbin/ifconfig/ifconfig.c
1980
val += 2;
sbin/ifconfig/ifconfig.c
1983
val = get_string(val, ",", keybuf[i], &len);
sbin/ifconfig/ifconfig.c
1984
if (val == NULL)
sbin/ifconfig/ifconfig.c
1989
if (*val != '\0') {
sbin/ifconfig/ifconfig.c
2003
size_t vlen = strlen(val);
sbin/ifconfig/ifconfig.c
2008
j = asprintf(&tmp, "0x%s", val);
sbin/ifconfig/ifconfig.c
2013
val = tmp;
sbin/ifconfig/ifconfig.c
2026
val = get_string(val, NULL, keybuf[0], &len);
sbin/ifconfig/ifconfig.c
2028
if (val == NULL)
sbin/ifconfig/ifconfig.c
2048
setifwpa(const char *val, int d)
sbin/ifconfig/ifconfig.c
2068
setifwpaprotos(const char *val, int d)
sbin/ifconfig/ifconfig.c
2074
if ((optlist = strdup(val)) == NULL)
sbin/ifconfig/ifconfig.c
2108
setifwpaakms(const char *val, int d)
sbin/ifconfig/ifconfig.c
2114
if ((optlist = strdup(val)) == NULL)
sbin/ifconfig/ifconfig.c
2173
setifwpaciphers(const char *val, int d)
sbin/ifconfig/ifconfig.c
2179
if ((optlist = strdup(val)) == NULL)
sbin/ifconfig/ifconfig.c
2209
setifwpagroupcipher(const char *val, int d)
sbin/ifconfig/ifconfig.c
2214
cipher = getwpacipher(val);
sbin/ifconfig/ifconfig.c
2216
errx(1, "wpagroupcipher: unknown cipher: %s", val);
sbin/ifconfig/ifconfig.c
2235
setifwpakey(const char *val, int d)
sbin/ifconfig/ifconfig.c
2262
passlen = strlen(val);
sbin/ifconfig/ifconfig.c
2264
val[0] == '0' && val[1] == 'x') {
sbin/ifconfig/ifconfig.c
2267
val = get_string(val, NULL, psk.i_psk, &passlen);
sbin/ifconfig/ifconfig.c
2268
if (val == NULL || passlen != sizeof(psk.i_psk))
sbin/ifconfig/ifconfig.c
2277
if (pkcs5_pbkdf2(val, passlen, nwid.i_nwid, nwid.i_len,
sbin/ifconfig/ifconfig.c
2309
setifchan(const char *val, int d)
sbin/ifconfig/ifconfig.c
2315
if (val == NULL) {
sbin/ifconfig/ifconfig.c
2324
chan = strtonum(val, 1, 256, &errstr);
sbin/ifconfig/ifconfig.c
2326
warnx("invalid channel %s: %s", val, errstr);
sbin/ifconfig/ifconfig.c
2338
setifscan(const char *val, int d)
sbin/ifconfig/ifconfig.c
2348
setifnwflag(const char *val, int d)
sbin/ifconfig/ifconfig.c
2354
if (strcmp(val, nwflags[i].f_name) == 0) {
sbin/ifconfig/ifconfig.c
2360
errx(1, "Invalid nwflag: %s", val);
sbin/ifconfig/ifconfig.c
2375
unsetifnwflag(const char *val, int d)
sbin/ifconfig/ifconfig.c
2377
setifnwflag(val, 1);
sbin/ifconfig/ifconfig.c
2381
setifpowersave(const char *val, int d)
sbin/ifconfig/ifconfig.c
2392
if (d != -1 && val != NULL) {
sbin/ifconfig/ifconfig.c
2393
power.i_maxsleep = strtonum(val, 0, INT_MAX, &errmsg);
sbin/ifconfig/ifconfig.c
2395
errx(1, "powersave %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
240
int prefix(void *val, int);
sbin/ifconfig/ifconfig.c
2604
showjoin(const char *cmd, int val)
sbin/ifconfig/ifconfig.c
2926
setmedia(const char *val, int d)
sbin/ifconfig/ifconfig.c
2930
if (val == NULL) {
sbin/ifconfig/ifconfig.c
2960
subtype = get_media_subtype(type, val);
sbin/ifconfig/ifconfig.c
2969
setmediamode(const char *val, int d)
sbin/ifconfig/ifconfig.c
2984
if ((mode = get_media_mode(type, val)) == -1)
sbin/ifconfig/ifconfig.c
2985
errx(1, "invalid media mode: %s", val);
sbin/ifconfig/ifconfig.c
2991
unsetmediamode(const char *val, int d)
sbin/ifconfig/ifconfig.c
3012
setmediaopt(const char *val, int d)
sbin/ifconfig/ifconfig.c
3025
mediaopt_set = get_media_options(IFM_TYPE(media_current), val);
sbin/ifconfig/ifconfig.c
3031
unsetmediaopt(const char *val, int d)
sbin/ifconfig/ifconfig.c
3049
mediaopt_clear = get_media_options(IFM_TYPE(media_current), val);
sbin/ifconfig/ifconfig.c
3055
setmediainst(const char *val, int d)
sbin/ifconfig/ifconfig.c
3074
inst = strtonum(val, 0, IFM_INST_MAX, &errmsg);
sbin/ifconfig/ifconfig.c
3076
errx(1, "media instance %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
3124
get_media_subtype(uint64_t type, const char *val)
sbin/ifconfig/ifconfig.c
3128
rval = lookup_media_word(ifm_subtype_descriptions, type, val);
sbin/ifconfig/ifconfig.c
3131
get_media_type_string(type), val);
sbin/ifconfig/ifconfig.c
3137
get_media_mode(uint64_t type, const char *val)
sbin/ifconfig/ifconfig.c
3141
rval = lookup_media_word(ifm_mode_descriptions, type, val);
sbin/ifconfig/ifconfig.c
3144
get_media_type_string(type), val);
sbin/ifconfig/ifconfig.c
3149
get_media_options(uint64_t type, const char *val)
sbin/ifconfig/ifconfig.c
3155
optlist = strdup(val);
sbin/ifconfig/ifconfig.c
3177
const char *val)
sbin/ifconfig/ifconfig.c
3182
strcasecmp(desc->ifmt_string, val) == 0)
sbin/ifconfig/ifconfig.c
4081
setmplslabel(const char *val, int d)
sbin/ifconfig/ifconfig.c
4088
shim.shim_label = strtonum(val, 0, MPLS_LABEL_MAX, &estr);
sbin/ifconfig/ifconfig.c
4091
errx(1, "mpls label %s is %s", val, estr);
sbin/ifconfig/ifconfig.c
4097
unsetmplslabel(const char *val, int d)
sbin/ifconfig/ifconfig.c
4127
setpwe3cw(const char *val, int d)
sbin/ifconfig/ifconfig.c
4133
unsetpwe3cw(const char *val, int d)
sbin/ifconfig/ifconfig.c
4139
setpwe3fat(const char *val, int d)
sbin/ifconfig/ifconfig.c
4145
unsetpwe3fat(const char *val, int d)
sbin/ifconfig/ifconfig.c
4191
unsetpwe3neighbor(const char *val, int d)
sbin/ifconfig/ifconfig.c
4346
settxprio(const char *val, int d)
sbin/ifconfig/ifconfig.c
4354
if (strcmp(val, "packet") == 0)
sbin/ifconfig/ifconfig.c
4356
else if (strcmp(val, "payload") == 0)
sbin/ifconfig/ifconfig.c
4359
ifr.ifr_hdrprio = strtonum(val,
sbin/ifconfig/ifconfig.c
4362
errx(1, "tx prio %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
4384
setrxprio(const char *val, int d)
sbin/ifconfig/ifconfig.c
4392
if (strcmp(val, "packet") == 0)
sbin/ifconfig/ifconfig.c
4394
else if (strcmp(val, "payload") == 0)
sbin/ifconfig/ifconfig.c
4396
else if (strcmp(val, "outer") == 0)
sbin/ifconfig/ifconfig.c
4399
ifr.ifr_hdrprio = strtonum(val,
sbin/ifconfig/ifconfig.c
4402
errx(1, "rx prio %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
4490
settrunkport(const char *val, int d)
sbin/ifconfig/ifconfig.c
4496
strlcpy(rp.rp_portname, val, sizeof(rp.rp_portname));
sbin/ifconfig/ifconfig.c
4503
unsettrunkport(const char *val, int d)
sbin/ifconfig/ifconfig.c
4509
strlcpy(rp.rp_portname, val, sizeof(rp.rp_portname));
sbin/ifconfig/ifconfig.c
4517
settrunkproto(const char *val, int d)
sbin/ifconfig/ifconfig.c
4527
if (strcmp(val, tpr[i].tpr_name) == 0) {
sbin/ifconfig/ifconfig.c
4533
errx(1, "Invalid trunk protocol: %s", val);
sbin/ifconfig/ifconfig.c
4541
settrunklacpmode(const char *val, int d)
sbin/ifconfig/ifconfig.c
4555
if (strcmp(val, lacpmodeactive) != 0 &&
sbin/ifconfig/ifconfig.c
4556
strcmp(val, lacpmodepassive) != 0)
sbin/ifconfig/ifconfig.c
4564
if (strcmp(val, lacpmodeactive) == 0)
sbin/ifconfig/ifconfig.c
4574
settrunklacptimeout(const char *val, int d)
sbin/ifconfig/ifconfig.c
4588
if (strcmp(val, lacptimeoutfast) != 0 &&
sbin/ifconfig/ifconfig.c
4589
strcmp(val, lacptimeoutslow) != 0)
sbin/ifconfig/ifconfig.c
4597
if (strcmp(val, lacptimeoutfast) == 0)
sbin/ifconfig/ifconfig.c
4766
setcarp_passwd(const char *val, int d)
sbin/ifconfig/ifconfig.c
4777
strlcpy((char *)carpr.carpr_key, val, CARP_KEY_LEN);
sbin/ifconfig/ifconfig.c
4784
setcarp_vhid(const char *val, int d)
sbin/ifconfig/ifconfig.c
4790
vhid = strtonum(val, 1, 255, &errmsg);
sbin/ifconfig/ifconfig.c
4792
errx(1, "vhid %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
4808
setcarp_advskew(const char *val, int d)
sbin/ifconfig/ifconfig.c
4814
advskew = strtonum(val, 0, 254, &errmsg);
sbin/ifconfig/ifconfig.c
4816
errx(1, "advskew %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
4831
setcarp_advbase(const char *val, int d)
sbin/ifconfig/ifconfig.c
4837
advbase = strtonum(val, 0, 254, &errmsg);
sbin/ifconfig/ifconfig.c
4839
errx(1, "advbase %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
4854
setcarppeer(const char *val, int d)
sbin/ifconfig/ifconfig.c
4870
if ((ecode = getaddrinfo(val, NULL, &hints, &peerres)) != 0)
sbin/ifconfig/ifconfig.c
4887
unsetcarppeer(const char *val, int d)
sbin/ifconfig/ifconfig.c
4904
setcarp_state(const char *val, int d)
sbin/ifconfig/ifconfig.c
4916
if (!strcasecmp(val, carp_states[i])) {
sbin/ifconfig/ifconfig.c
4927
setcarpdev(const char *val, int d)
sbin/ifconfig/ifconfig.c
4937
strlcpy(carpr.carpr_carpdev, val, sizeof(carpr.carpr_carpdev));
sbin/ifconfig/ifconfig.c
4944
setcarp_nodes(const char *val, int d)
sbin/ifconfig/ifconfig.c
4959
optlist = strdup(val);
sbin/ifconfig/ifconfig.c
4988
setcarp_balancing(const char *val, int d)
sbin/ifconfig/ifconfig.c
5000
if (!strcasecmp(val, carp_bal_modes[i]))
sbin/ifconfig/ifconfig.c
5004
errx(1, "balancing %s: unknown mode", val);
sbin/ifconfig/ifconfig.c
5013
setpfsync_syncdev(const char *val, int d)
sbin/ifconfig/ifconfig.c
5023
strlcpy(preq.pfsyncr_syncdev, val, sizeof(preq.pfsyncr_syncdev));
sbin/ifconfig/ifconfig.c
5030
unsetpfsync_syncdev(const char *val, int d)
sbin/ifconfig/ifconfig.c
5047
setpfsync_syncpeer(const char *val, int d)
sbin/ifconfig/ifconfig.c
5063
if ((ecode = getaddrinfo(val, NULL, &hints, &peerres)) != 0)
sbin/ifconfig/ifconfig.c
5080
unsetpfsync_syncpeer(const char *val, int d)
sbin/ifconfig/ifconfig.c
5097
setpfsync_maxupd(const char *val, int d)
sbin/ifconfig/ifconfig.c
5103
maxupdates = strtonum(val, 0, 255, &errmsg);
sbin/ifconfig/ifconfig.c
5105
errx(1, "maxupd %s: %s", val, errmsg);
sbin/ifconfig/ifconfig.c
5120
setpfsync_defer(const char *val, int d)
sbin/ifconfig/ifconfig.c
5238
pflow_addr(const char *val, struct sockaddr_storage *ss) {
sbin/ifconfig/ifconfig.c
5243
if (strlcpy(buf, val, sizeof(buf)) >= sizeof(buf))
sbin/ifconfig/ifconfig.c
5244
errx(1, "%s bad value", val);
sbin/ifconfig/ifconfig.c
5290
setpflow_sender(const char *val, int d)
sbin/ifconfig/ifconfig.c
5297
pflow_addr(val, &preq.flowsrc);
sbin/ifconfig/ifconfig.c
5304
unsetpflow_sender(const char *val, int d)
sbin/ifconfig/ifconfig.c
5316
setpflow_receiver(const char *val, int d)
sbin/ifconfig/ifconfig.c
5323
pflow_addr(val, &preq.flowdst);
sbin/ifconfig/ifconfig.c
5330
unsetpflow_receiver(const char *val, int d)
sbin/ifconfig/ifconfig.c
5343
setpflowproto(const char *val, int d)
sbin/ifconfig/ifconfig.c
5353
if (strcmp(val, ppr[i].ppr_name) == 0) {
sbin/ifconfig/ifconfig.c
5359
errx(1, "Invalid pflow protocol: %s", val);
sbin/ifconfig/ifconfig.c
5441
setpppoe_dev(const char *val, int d)
sbin/ifconfig/ifconfig.c
5449
strlcpy(parms.eth_ifname, val, sizeof(parms.eth_ifname));
sbin/ifconfig/ifconfig.c
5456
setpppoe_svc(const char *val, int d)
sbin/ifconfig/ifconfig.c
5465
strlcpy(parms.service_name, val, sizeof(parms.service_name));
sbin/ifconfig/ifconfig.c
5474
setpppoe_ac(const char *val, int d)
sbin/ifconfig/ifconfig.c
5483
strlcpy(parms.ac_name, val, sizeof(parms.ac_name));
sbin/ifconfig/ifconfig.c
5514
setspppproto(const char *val, int d)
sbin/ifconfig/ifconfig.c
5520
if (strcmp(val, "pap") == 0)
sbin/ifconfig/ifconfig.c
5522
else if (strcmp(val, "chap") == 0)
sbin/ifconfig/ifconfig.c
5524
else if (strcmp(val, "none") == 0)
sbin/ifconfig/ifconfig.c
5535
setsppppeerproto(const char *val, int d)
sbin/ifconfig/ifconfig.c
5537
setspppproto(val, 1);
sbin/ifconfig/ifconfig.c
5541
setspppname(const char *val, int d)
sbin/ifconfig/ifconfig.c
5549
if (strlcpy(spa.name, val, sizeof(spa.name)) >= sizeof(spa.name))
sbin/ifconfig/ifconfig.c
5558
setsppppeername(const char *val, int d)
sbin/ifconfig/ifconfig.c
5560
setspppname(val, 1);
sbin/ifconfig/ifconfig.c
5564
setspppkey(const char *val, int d)
sbin/ifconfig/ifconfig.c
5572
if (strlcpy(spa.secret, val, sizeof(spa.secret)) >= sizeof(spa.secret))
sbin/ifconfig/ifconfig.c
5581
setsppppeerkey(const char *val, int d)
sbin/ifconfig/ifconfig.c
5583
setspppkey(val, 1);
sbin/ifconfig/ifconfig.c
5587
setsppppeerflag(const char *val, int d)
sbin/ifconfig/ifconfig.c
5596
if (strcmp(val, "callin") == 0)
sbin/ifconfig/ifconfig.c
5598
else if (strcmp(val, "norechallenge") == 0)
sbin/ifconfig/ifconfig.c
5614
unsetsppppeerflag(const char *val, int d)
sbin/ifconfig/ifconfig.c
5616
setsppppeerflag(val, 1);
sbin/ifconfig/ifconfig.c
5723
unsetkeepalive(const char *val, int d)
sbin/ifconfig/ifconfig.c
6077
return vdp->val;
sbin/ifconfig/ifconfig.c
6290
if (umb_dataclass[i].val & c) {
sbin/ifconfig/ifconfig.c
6383
umb_setclass(const char *val, int d)
sbin/ifconfig/ifconfig.c
6387
if (val == NULL) {
sbin/ifconfig/ifconfig.c
6399
mp.preferredclasses = umb_parse_classes(val);
sbin/ifconfig/ifconfig.c
6407
umb_roaming(const char *val, int d)
sbin/ifconfig/ifconfig.c
6656
prefix(void *val, int size)
sbin/ifconfig/ifconfig.c
6658
u_char *nam = (u_char *)val;
sbin/ifconfig/ifconfig.c
6822
setpair(const char *val, int d)
sbin/ifconfig/ifconfig.c
6825
if ((ifr.ifr_index = if_nametoindex(val)) == 0) {
sbin/ifconfig/ifconfig.c
6827
err(1, "patch %s", val);
sbin/ifconfig/ifconfig.c
6834
unsetpair(const char *val, int d)
sbin/iked/ca.c
213
void *val = ibuf_data(id->id_buf);
sbin/iked/ca.c
218
ibuf_add(buf, val, len) != 0)
sbin/iked/parse.y
1770
char *p, *val;
sbin/iked/parse.y
1800
val = symget(buf);
sbin/iked/parse.y
1801
if (val == NULL) {
sbin/iked/parse.y
1805
p = val + strlen(val) - 1;
sbin/iked/parse.y
1807
while (p >= val) {
sbin/iked/parse.y
2072
free(sym->val);
sbin/iked/parse.y
2084
symset(const char *nam, const char *val, int persist)
sbin/iked/parse.y
2098
free(sym->val);
sbin/iked/parse.y
2111
sym->val = strdup(val);
sbin/iked/parse.y
2112
if (sym->val == NULL) {
sbin/iked/parse.y
2126
char *sym, *val;
sbin/iked/parse.y
2129
if ((val = strrchr(s, '=')) == NULL)
sbin/iked/parse.y
2132
sym = strndup(s, val - s);
sbin/iked/parse.y
2135
ret = symset(sym, val + 1, 1);
sbin/iked/parse.y
2149
return (sym->val);
sbin/iked/parse.y
91
char *val;
sbin/iked/util.c
162
int s, val;
sbin/iked/util.c
182
val = 1;
sbin/iked/util.c
183
if (setsockopt(s, SOL_SOCKET, SO_REUSEPORT, &val, sizeof(int)) == -1) {
sbin/iked/util.c
187
val = 1;
sbin/iked/util.c
188
if (setsockopt(s, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(int)) == -1) {
sbin/iked/util.c
194
val = 1;
sbin/iked/util.c
196
&val, sizeof(int)) == -1) {
sbin/iked/util.c
202
val = 1;
sbin/iked/util.c
204
&val, sizeof(int)) == -1) {
sbin/ipsecctl/parse.y
1210
char *p, *val;
sbin/ipsecctl/parse.y
1240
val = symget(buf);
sbin/ipsecctl/parse.y
1241
if (val == NULL) {
sbin/ipsecctl/parse.y
1245
parsebuf = val;
sbin/ipsecctl/parse.y
1455
free(sym->val);
sbin/ipsecctl/parse.y
1464
symset(const char *nam, const char *val, int persist)
sbin/ipsecctl/parse.y
1478
free(sym->val);
sbin/ipsecctl/parse.y
1491
sym->val = strdup(val);
sbin/ipsecctl/parse.y
1492
if (sym->val == NULL) {
sbin/ipsecctl/parse.y
1506
char *sym, *val;
sbin/ipsecctl/parse.y
1509
if ((val = strrchr(s, '=')) == NULL)
sbin/ipsecctl/parse.y
1512
sym = strndup(s, val - s);
sbin/ipsecctl/parse.y
1515
ret = symset(sym, val + 1, 1);
sbin/ipsecctl/parse.y
1529
return (sym->val);
sbin/ipsecctl/parse.y
80
char *val;
sbin/isakmpd/conf.c
202
char *val;
sbin/isakmpd/conf.c
242
val = line + i + 1 + strspn(line + i + 1, " \t");
sbin/isakmpd/conf.c
244
for (j = sz - (val - line) - 1; j > 0 &&
sbin/isakmpd/conf.c
245
isspace((unsigned char)val[j]); j--)
sbin/isakmpd/conf.c
246
val[j] = '\0';
sbin/isakmpd/conf.c
248
conf_set(trans, section, line, val, 0, 0);
sbin/isakmpd/conf.c
704
int val, min, max, n;
sbin/isakmpd/conf.c
708
n = sscanf(value, "%d,%d:%d", &val, &min, &max);
sbin/isakmpd/conf.c
712
section, tag, val, x));
sbin/isakmpd/conf.c
713
return x == val;
sbin/isakmpd/field.c
100
u_int32_t val;
sbin/isakmpd/field.c
102
if (extract_val(buf, len, &val))
sbin/isakmpd/field.c
104
if (asprintf(&retval, "%u", val) == -1)
sbin/isakmpd/field.c
116
u_int32_t val;
sbin/isakmpd/field.c
121
if (extract_val(buf, len, &val))
sbin/isakmpd/field.c
132
if (val & bit) {
sbin/isakmpd/field.c
166
u_int32_t val;
sbin/isakmpd/field.c
168
if (extract_val(buf, len, &val))
sbin/isakmpd/field.c
171
return strdup(constant_name_maps(maps, val));
sbin/isakmpd/field.c
201
u_int32_t val;
sbin/isakmpd/field.c
203
if (extract_val(buf + f->offset, f->len, &val))
sbin/isakmpd/field.c
205
return val;
sbin/isakmpd/field.c
210
field_set_num(struct field *f, u_int8_t *buf, u_int32_t val)
sbin/isakmpd/field.c
214
buf[f->offset] = val;
sbin/isakmpd/field.c
217
encode_16(buf + f->offset, val);
sbin/isakmpd/field.c
220
encode_32(buf + f->offset, val);
sbin/isakmpd/field.c
227
field_get_raw(struct field *f, u_int8_t *buf, u_int8_t *val)
sbin/isakmpd/field.c
229
memcpy(val, buf + f->offset, f->len);
sbin/isakmpd/field.c
234
field_set_raw(struct field *f, u_int8_t *buf, u_int8_t *val)
sbin/isakmpd/field.c
236
memcpy(buf + f->offset, val, f->len);
sbin/isakmpd/field.c
73
extract_val(u_int8_t *buf, size_t len, u_int32_t *val)
sbin/isakmpd/field.c
77
*val = *buf;
sbin/isakmpd/field.c
80
*val = decode_16(buf);
sbin/isakmpd/field.c
83
*val = decode_32(buf);
sbin/isakmpd/ipsec.c
1404
char val[20];
sbin/isakmpd/ipsec.c
1408
snprintf(val, sizeof val, "%d", decode_16(value));
sbin/isakmpd/ipsec.c
1410
snprintf(val, sizeof val, "%d", decode_32(value));
sbin/isakmpd/ipsec.c
1412
snprintf(val, sizeof val, "unrepresentable");
sbin/isakmpd/ipsec.c
1416
ipsec_attr_cst, type), val));
sbin/isakmpd/util.c
356
long val;
sbin/isakmpd/util.c
381
val = strtol(token, &ep, 10);
sbin/isakmpd/util.c
382
if (ep == token || val < (long)0 ||
sbin/isakmpd/util.c
383
val > (long)UCHAR_MAX) {
sbin/isakmpd/util.c
388
addrlen - strlen(*address), "%03ld", val);
sbin/isakmpd/x509.c
1042
free(aca->name1.val);
sbin/isakmpd/x509.c
1045
free(aca->name2.val);
sbin/isakmpd/x509.h
45
char *val;
sbin/mount/getmntopts.c
49
union mntval val;
sbin/mount/getmntopts.c
56
ret |= getmntopt(&p, &val, m0, flagp);
sbin/mountd/mountd.c
1190
if (ep->ex_fs.val[0] != fsb.f_fsid.val[0] ||
sbin/mountd/mountd.c
1191
ep->ex_fs.val[1] != fsb.f_fsid.val[1]) {
sbin/mountd/mountd.c
1216
fsb.f_fsid.val[0],
sbin/mountd/mountd.c
1217
fsb.f_fsid.val[1]);
sbin/mountd/mountd.c
1221
fsb.f_fsid.val[0],
sbin/mountd/mountd.c
1222
fsb.f_fsid.val[1]);
sbin/mountd/mountd.c
1484
if (ep->ex_fs.val[0] == fsid->val[0] &&
sbin/mountd/mountd.c
1485
ep->ex_fs.val[1] == fsid->val[1])
sbin/ncheck_ffs/ncheck_ffs.c
130
matchino(const void *key, const void *val)
sbin/ncheck_ffs/ncheck_ffs.c
133
ufsino_t v = *(ufsino_t *)val;
sbin/ncheck_ffs/ncheck_ffs.c
146
matchcache(const void *key, const void *val)
sbin/ncheck_ffs/ncheck_ffs.c
149
struct icache_s *ic = (struct icache_s *)val;
sbin/newfs/mkfs.c
1160
ilog2(int val)
sbin/newfs/mkfs.c
1165
if (1 << n == val)
sbin/newfs/mkfs.c
1168
errx(1, "ilog2: %d is not a power of 2\n", val);
sbin/newfs_ext2fs/mke2fs.c
1393
ilog2(uint val)
sbin/newfs_ext2fs/mke2fs.c
1396
if (val == 0 || !powerof2(val))
sbin/newfs_ext2fs/mke2fs.c
1398
__func__, val);
sbin/newfs_ext2fs/mke2fs.c
1400
return ffs(val) - 1;
sbin/newfs_msdos/newfs_msdos.c
800
ckgeom(const char *fname, u_int val, const char *msg)
sbin/newfs_msdos/newfs_msdos.c
802
if (!val)
sbin/newfs_msdos/newfs_msdos.c
804
if (val > MAXU16)
sbin/newfs_msdos/newfs_msdos.c
806
return val;
sbin/pfctl/parse.y
104
char *val;
sbin/pfctl/parse.y
3748
int val;
sbin/pfctl/parse.y
3751
if (map_tos($1, &val))
sbin/pfctl/parse.y
3752
$$ = val;
sbin/pfctl/parse.y
5736
char *p, *val;
sbin/pfctl/parse.y
5766
val = symget(buf);
sbin/pfctl/parse.y
5767
if (val == NULL) {
sbin/pfctl/parse.y
5771
p = val + strlen(val) - 1;
sbin/pfctl/parse.y
5773
while (p >= val) {
sbin/pfctl/parse.y
6023
free(sym->val);
sbin/pfctl/parse.y
6032
symset(const char *nam, const char *val, int persist)
sbin/pfctl/parse.y
6046
free(sym->val);
sbin/pfctl/parse.y
6059
sym->val = strdup(val);
sbin/pfctl/parse.y
6060
if (sym->val == NULL) {
sbin/pfctl/parse.y
6074
char *sym, *val;
sbin/pfctl/parse.y
6077
if ((val = strrchr(s, '=')) == NULL)
sbin/pfctl/parse.y
6080
sym = strndup(s, val - s);
sbin/pfctl/parse.y
6083
ret = symset(sym, val + 1, 1);
sbin/pfctl/parse.y
6097
return (sym->val);
sbin/pfctl/parse.y
6350
map_tos(char *s, int *val)
sbin/pfctl/parse.y
6389
*val = p->k_val;
sbin/pfctl/parse.y
794
double val;
sbin/pfctl/parse.y
797
val = strtod($2, &cp);
sbin/pfctl/parse.y
800
if (val <= 0 || val > 100) {
sbin/pfctl/parse.y
805
syncookie_opts.hi = val;
sbin/pfctl/parse.y
807
syncookie_opts.lo = val;
sbin/pfctl/pfctl.c
2507
pfctl_set_syncookies(struct pfctl *pf, u_int8_t val, struct pfctl_watermarks *w)
sbin/pfctl/pfctl.c
2509
if (val != PF_SYNCOOKIES_ADAPTIVE && w != NULL) {
sbin/pfctl/pfctl.c
2513
if (val == PF_SYNCOOKIES_ADAPTIVE && w != NULL) {
sbin/pfctl/pfctl.c
2528
if (val == PF_SYNCOOKIES_NEVER)
sbin/pfctl/pfctl.c
2530
else if (val == PF_SYNCOOKIES_ALWAYS)
sbin/pfctl/pfctl.c
2532
else if (val == PF_SYNCOOKIES_ADAPTIVE) {
sbin/pfctl/pfctl.c
2546
pf->syncookies = val;
sbin/pfctl/pfctl.c
2647
pfctl_load_syncookies(struct pfctl *pf, u_int8_t val)
sbin/pfctl/pfctl.c
2649
if (ioctl(dev, DIOCSETSYNCOOKIES, &val) == -1) {
sbin/pfctl/pfctl.c
975
uint32_t val, inc;
sbin/pfctl/pfctl.c
978
val = ntohl(addr->addr32[i]);
sbin/pfctl/pfctl.c
979
inc = val + 1;
sbin/pfctl/pfctl.c
981
if (inc > val)
sbin/pfctl/pfctl_osfp.c
771
long val = 0;
sbin/pfctl/pfctl_osfp.c
835
val = val * 10 + field[i] - '0';
sbin/pfctl/pfctl_osfp.c
836
if (val < 0) {
sbin/pfctl/pfctl_osfp.c
843
if (val > max) {
sbin/pfctl/pfctl_osfp.c
845
name, val, max);
sbin/pfctl/pfctl_osfp.c
848
*var = (int)val;
sbin/pfctl/pfctl_parser.c
320
int val;
sbin/pfctl/pfctl_parser.c
322
val = strtonum(name, 0, LOG_DEBUG, &errstr);
sbin/pfctl/pfctl_parser.c
325
return val;
sbin/ping/ping.c
1796
map_tos(char *key, int *val)
sbin/ping/ping.c
1801
int val;
sbin/ping/ping.c
1836
*val = t->val;
sbin/restore/dirs.c
64
#define INOHASH(val) (val % HASHSIZE)
sbin/scsi/libscsi.c
567
u_char val;
sbin/scsi/libscsi.c
576
val = 0;
sbin/scsi/libscsi.c
612
val |= (value << (8 - shift));
sbin/scsi/libscsi.c
616
buff[ind++] = val;
sbin/scsi/libscsi.c
617
val = 0;
sbin/scsi/libscsi.c
624
buff[ind++] = val;
sbin/scsi/libscsi.c
625
val = 0;
sbin/scsi/libscsi.c
669
buff[ind++] = val;
sbin/scsi/libscsi.c
670
val = 0;
sbin/scsi/libscsi.c
882
u_long val;
sbin/scsi/libscsi.c
916
val = g_u_long(s + 3);
sbin/scsi/libscsi.c
918
valid ? "" : " not valid but contains", (long)val, (long)val);
sbin/scsi/libscsi.c
920
val = g_u_long(s + 8);
sbin/scsi/libscsi.c
922
(long)val, (long)val);
sbin/sysctl/sysctl.c
631
(void)printf("%p\n", _ps.val);
sbin/unwind/frontend.c
1381
add_new_ta(struct trust_anchor_head *tah, char *val)
sbin/unwind/frontend.c
1388
if ((ta->ta = strdup(val)) == NULL)
sbin/unwind/libunbound/libunbound/libunbound.c
413
ub_ctx_set_option(struct ub_ctx* ctx, const char* opt, const char* val)
sbin/unwind/libunbound/libunbound/libunbound.c
420
if(!config_set_option(ctx->env->cfg, opt, val)) {
sbin/unwind/libunbound/libunbound/unbound.h
293
int ub_ctx_set_option(struct ub_ctx* ctx, const char* opt, const char* val);
sbin/unwind/libunbound/libunbound/unbound.h
668
long long val;
sbin/unwind/libunbound/services/listen_dnsport.c
512
int val=(v6only==2)?0:1;
sbin/unwind/libunbound/services/listen_dnsport.c
514
(void*)&val, (socklen_t)sizeof(val)) < 0) {
sbin/unwind/libunbound/sldns/parseutil.c
323
uint16_t val;
sbin/unwind/libunbound/sldns/parseutil.c
329
val = (uint16_t)(((*str_p)[0] - '0') * 100 +
sbin/unwind/libunbound/sldns/parseutil.c
333
if (val > 255) {
sbin/unwind/libunbound/sldns/parseutil.c
336
*ch_p = (uint8_t)val;
sbin/unwind/libunbound/sldns/str2wire.c
1174
sldns_str2wire_svcparam_port(const char* val, uint8_t* rd, size_t* rd_len)
sbin/unwind/libunbound/sldns/str2wire.c
1182
port = strtoul(val, &endptr, 10);
sbin/unwind/libunbound/sldns/str2wire.c
1184
if (endptr > val /* digits seen */
sbin/unwind/libunbound/sldns/str2wire.c
1200
sldns_str2wire_svcbparam_ipv4hint(const char* val, uint8_t* rd, size_t* rd_len)
sbin/unwind/libunbound/sldns/str2wire.c
1207
for (i = 0, count = 1; val[i]; i++) {
sbin/unwind/libunbound/sldns/str2wire.c
1208
if (val[i] == ',')
sbin/unwind/libunbound/sldns/str2wire.c
1226
if (!(next_ip_str = strchr(val, ','))) {
sbin/unwind/libunbound/sldns/str2wire.c
1227
if (inet_pton(AF_INET, val, rd + *rd_len) != 1)
sbin/unwind/libunbound/sldns/str2wire.c
1233
} else if (next_ip_str - val >= (int)sizeof(ip_str))
sbin/unwind/libunbound/sldns/str2wire.c
1237
memcpy(ip_str, val, next_ip_str - val);
sbin/unwind/libunbound/sldns/str2wire.c
1238
ip_str[next_ip_str - val] = 0;
sbin/unwind/libunbound/sldns/str2wire.c
1244
val = next_ip_str + 1;
sbin/unwind/libunbound/sldns/str2wire.c
1255
sldns_str2wire_svcbparam_ipv6hint(const char* val, uint8_t* rd, size_t* rd_len)
sbin/unwind/libunbound/sldns/str2wire.c
1262
for (i = 0, count = 1; val[i]; i++) {
sbin/unwind/libunbound/sldns/str2wire.c
1263
if (val[i] == ',')
sbin/unwind/libunbound/sldns/str2wire.c
1281
if (!(next_ip_str = strchr(val, ','))) {
sbin/unwind/libunbound/sldns/str2wire.c
1282
if (inet_pton(AF_INET6, val, rd + *rd_len) != 1)
sbin/unwind/libunbound/sldns/str2wire.c
1288
} else if (next_ip_str - val >= (int)sizeof(ip_str))
sbin/unwind/libunbound/sldns/str2wire.c
1292
memcpy(ip_str, val, next_ip_str - val);
sbin/unwind/libunbound/sldns/str2wire.c
1293
ip_str[next_ip_str - val] = 0;
sbin/unwind/libunbound/sldns/str2wire.c
1299
val = next_ip_str + 1;
sbin/unwind/libunbound/sldns/str2wire.c
1317
sldns_str2wire_svcbparam_mandatory(const char* val, uint8_t* rd, size_t* rd_len)
sbin/unwind/libunbound/sldns/str2wire.c
1322
val_len = strlen(val);
sbin/unwind/libunbound/sldns/str2wire.c
1324
for (i = 0, count = 1; val[i]; i++) {
sbin/unwind/libunbound/sldns/str2wire.c
1325
if (val[i] == ',')
sbin/unwind/libunbound/sldns/str2wire.c
1341
if (!(next_key = strchr(val, ','))) {
sbin/unwind/libunbound/sldns/str2wire.c
1342
svcparamkey = sldns_str2wire_svcparam_key_lookup(val, val_len);
sbin/unwind/libunbound/sldns/str2wire.c
1352
svcparamkey = sldns_str2wire_svcparam_key_lookup(val, next_key - val);
sbin/unwind/libunbound/sldns/str2wire.c
1363
val_len -= next_key - val + 1;
sbin/unwind/libunbound/sldns/str2wire.c
1364
val = next_key + 1; /* skip the comma */
sbin/unwind/libunbound/sldns/str2wire.c
1402
sldns_str2wire_svcbparam_ech_value(const char* val, uint8_t* rd, size_t* rd_len)
sbin/unwind/libunbound/sldns/str2wire.c
1408
if(strcmp(val, "0") == 0) {
sbin/unwind/libunbound/sldns/str2wire.c
1417
wire_len = sldns_b64_pton(val, buffer, LDNS_MAX_RDFLEN);
sbin/unwind/libunbound/sldns/str2wire.c
1434
sldns_str2wire_svcbparam_parse_next_unescaped_comma(const char *val)
sbin/unwind/libunbound/sldns/str2wire.c
1436
while (*val) {
sbin/unwind/libunbound/sldns/str2wire.c
1438
if (*val == '\\'){
sbin/unwind/libunbound/sldns/str2wire.c
1439
++val;
sbin/unwind/libunbound/sldns/str2wire.c
1440
if (!*val)
sbin/unwind/libunbound/sldns/str2wire.c
1442
} else if (*val == ',')
sbin/unwind/libunbound/sldns/str2wire.c
1443
return val;
sbin/unwind/libunbound/sldns/str2wire.c
1445
val++;
sbin/unwind/libunbound/sldns/str2wire.c
1476
sldns_str2wire_svcbparam_alpn_value(const char* val,
sbin/unwind/libunbound/sldns/str2wire.c
1486
val_len = strlen(val);
sbin/unwind/libunbound/sldns/str2wire.c
1494
str_len = (next_str = sldns_str2wire_svcbparam_parse_next_unescaped_comma(val))
sbin/unwind/libunbound/sldns/str2wire.c
1495
? (size_t)(next_str - val) : val_len;
sbin/unwind/libunbound/sldns/str2wire.c
1501
key_len = sldns_str2wire_svcbparam_parse_copy_unescaped(dst + 1, val, str_len);
sbin/unwind/libunbound/sldns/str2wire.c
1509
val_len -= next_str - val + 1;
sbin/unwind/libunbound/sldns/str2wire.c
1510
val = next_str + 1;
sbin/unwind/libunbound/sldns/str2wire.c
1524
sldns_str2wire_svcbparam_dohpath_value(const char* val,
sbin/unwind/libunbound/sldns/str2wire.c
1536
val_len = strlen(val);
sbin/unwind/libunbound/sldns/str2wire.c
1544
memcpy(rd + 4, val, val_len);
sbin/unwind/libunbound/sldns/str2wire.c
1552
const char *val, uint8_t* rd, size_t* rd_len)
sbin/unwind/libunbound/sldns/str2wire.c
1562
if (val == NULL) {
sbin/unwind/libunbound/sldns/str2wire.c
1587
return sldns_str2wire_svcparam_port(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1589
return sldns_str2wire_svcbparam_ipv4hint(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1591
return sldns_str2wire_svcbparam_ipv6hint(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1593
return sldns_str2wire_svcbparam_mandatory(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1599
return sldns_str2wire_svcbparam_ech_value(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1601
return sldns_str2wire_svcbparam_alpn_value(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1603
return sldns_str2wire_svcbparam_dohpath_value(val, rd, rd_len);
sbin/unwind/libunbound/sldns/str2wire.c
1605
str_len = strlen(val);
sbin/unwind/libunbound/sldns/str2wire.c
1610
memcpy(rd + 4, val, str_len);
sbin/unwind/libunbound/sldns/str2wire.c
2225
uint32_t meters = 0, cm = 0, val;
sbin/unwind/libunbound/sldns/str2wire.c
2240
val = meters;
sbin/unwind/libunbound/sldns/str2wire.c
2243
val = cm;
sbin/unwind/libunbound/sldns/str2wire.c
2245
while(val >= 10) {
sbin/unwind/libunbound/sldns/str2wire.c
2247
val /= 10;
sbin/unwind/libunbound/sldns/str2wire.c
2249
*m = (uint8_t)val;
sbin/unwind/libunbound/util/config_file.c
1478
#define SET_AUTO_SLAB(var, name, val) \
sbin/unwind/libunbound/util/config_file.c
1481
cfg->var = val; \
sbin/unwind/libunbound/util/config_file.c
1482
verbose(VERB_QUERY, "setting "name": %lu", (unsigned long)val); \
sbin/unwind/libunbound/util/config_file.c
2674
cfg_parse_local_zone(struct config_file* cfg, const char* val)
sbin/unwind/libunbound/util/config_file.c
2680
name = val;
sbin/unwind/libunbound/util/config_file.c
2684
log_err("syntax error: too short: %s", val);
sbin/unwind/libunbound/util/config_file.c
2689
log_err("syntax error: expected zone type: %s", val);
sbin/unwind/libunbound/util/config_file.c
2693
log_err("syntax error: bad zone name: %s", val);
sbin/unwind/libunbound/util/config_file.c
2703
log_err("syntax error: expected zone type: %s", val);
sbin/unwind/libunbound/util/config_file.c
474
if(atoi(val) == 0 && strcmp(val, "0") != 0) return 0
sbin/unwind/libunbound/util/config_file.c
477
if(atoi(val) == 0) return 0
sbin/unwind/libunbound/util/config_file.c
480
if(atoi(val) == 0 || !is_pow2((size_t)atoi(val))) return 0
sbin/unwind/libunbound/util/config_file.c
483
if(strcmp(val, "yes") != 0 && strcmp(val, "no") != 0) return 0
sbin/unwind/libunbound/util/config_file.c
486
{ IS_NUMBER_OR_ZERO; cfg->var = atoi(val); }
sbin/unwind/libunbound/util/config_file.c
489
{ IS_NONZERO_NUMBER; cfg->var = atoi(val); }
sbin/unwind/libunbound/util/config_file.c
492
{ IS_NUMBER_OR_ZERO; cfg->var = (unsigned)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
495
{ IS_NUMBER_OR_ZERO; cfg->var = (size_t)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
498
{ IS_NONZERO_NUMBER; cfg->var = (size_t)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
501
{ IS_YES_OR_NO; cfg->var = (strcmp(val, "yes") == 0); }
sbin/unwind/libunbound/util/config_file.c
504
{ return cfg_parse_memsize(val, &cfg->var); }
sbin/unwind/libunbound/util/config_file.c
507
{ IS_POW2_NUMBER; cfg->var = (size_t)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
510
{ free(cfg->var); return (cfg->var = strdup(val)) != NULL; }
sbin/unwind/libunbound/util/config_file.c
513
{ return cfg_strlist_insert(&cfg->var, strdup(val)); }
sbin/unwind/libunbound/util/config_file.c
516
{ if(cfg_strlist_find(cfg->var, val)) { return 0;} \
sbin/unwind/libunbound/util/config_file.c
517
return cfg_strlist_insert(&cfg->var, strdup(val)); }
sbin/unwind/libunbound/util/config_file.c
520
{ return cfg_strlist_append(&cfg->var, strdup(val)); }
sbin/unwind/libunbound/util/config_file.c
542
const char* val)
sbin/unwind/libunbound/util/config_file.c
552
if(strcmp(val, "0") == 0 || strcmp(val, "") == 0)
sbin/unwind/libunbound/util/config_file.c
554
else if(atoi(val) == 0)
sbin/unwind/libunbound/util/config_file.c
556
else cfg->stat_interval = atoi(val);
sbin/unwind/libunbound/util/config_file.c
561
return cfg_mark_ports(val, 1,
sbin/unwind/libunbound/util/config_file.c
564
return cfg_mark_ports(val, 0,
sbin/unwind/libunbound/util/config_file.c
567
return cfg_parse_local_zone(cfg, val);
sbin/unwind/libunbound/util/config_file.c
569
if(strcmp(val, "") == 0 || strcmp(val, "0") == 0) {
sbin/unwind/libunbound/util/config_file.c
571
} else if(strlen(val) == 14) {
sbin/unwind/libunbound/util/config_file.c
572
cfg->val_date_override = cfg_convert_timeval(val);
sbin/unwind/libunbound/util/config_file.c
575
if(atoi(val) == 0) return 0;
sbin/unwind/libunbound/util/config_file.c
576
cfg->val_date_override = (uint32_t)atoi(val);
sbin/unwind/libunbound/util/config_file.c
584
return (cfg->logfile = strdup(val)) != NULL;
sbin/unwind/libunbound/util/config_file.c
587
{ IS_YES_OR_NO; cfg->log_time_ascii = (strcmp(val, "yes") == 0);
sbin/unwind/libunbound/util/config_file.c
590
{ IS_YES_OR_NO; cfg->log_time_iso = (strcmp(val, "yes") == 0);
sbin/unwind/libunbound/util/config_file.c
639
if(!cfg_tls_protocols_is_valid(val)) return 0;
sbin/unwind/libunbound/util/config_file.c
641
return (cfg->tls_protocols = strdup(val)) != NULL;
sbin/unwind/libunbound/util/config_file.c
679
{ IS_NUMBER_OR_ZERO; cfg->max_ttl = atoi(val); MAX_TTL=(time_t)cfg->max_ttl;}
sbin/unwind/libunbound/util/config_file.c
681
{ IS_NUMBER_OR_ZERO; cfg->max_negative_ttl = atoi(val); MAX_NEG_TTL=(time_t)cfg->max_negative_ttl;}
sbin/unwind/libunbound/util/config_file.c
683
{ IS_NUMBER_OR_ZERO; cfg->min_negative_ttl = atoi(val); MIN_NEG_TTL=(time_t)cfg->min_negative_ttl;}
sbin/unwind/libunbound/util/config_file.c
685
{ IS_NUMBER_OR_ZERO; cfg->min_ttl = atoi(val); MIN_TTL=(time_t)cfg->min_ttl;}
sbin/unwind/libunbound/util/config_file.c
687
IS_NUMBER_OR_ZERO; cfg->infra_cache_min_rtt = atoi(val);
sbin/unwind/libunbound/util/config_file.c
691
IS_NUMBER_OR_ZERO; cfg->infra_cache_max_rtt = atoi(val);
sbin/unwind/libunbound/util/config_file.c
713
if (!(cfg->nsid_cfg_str = strdup(val)))
sbin/unwind/libunbound/util/config_file.c
716
if (*val == 0) {
sbin/unwind/libunbound/util/config_file.c
722
cfg->nsid = cfg_parse_nsid(val, &cfg->nsid_len);
sbin/unwind/libunbound/util/config_file.c
766
{ IS_YES_OR_NO; cfg->serve_expired = (strcmp(val, "yes") == 0);
sbin/unwind/libunbound/util/config_file.c
769
{ IS_NUMBER_OR_ZERO; cfg->serve_expired_ttl = atoi(val); SERVE_EXPIRED_TTL=(time_t)cfg->serve_expired_ttl;}
sbin/unwind/libunbound/util/config_file.c
771
{ IS_YES_OR_NO; cfg->serve_expired_ttl_reset = (strcmp(val, "yes") == 0);
sbin/unwind/libunbound/util/config_file.c
774
{ IS_NUMBER_OR_ZERO; cfg->serve_expired_reply_ttl = atoi(val); SERVE_EXPIRED_REPLY_TTL=(time_t)cfg->serve_expired_reply_ttl;}
sbin/unwind/libunbound/util/config_file.c
791
{ IS_YES_OR_NO; cfg->permit_small_holddown = (strcmp(val, "yes") == 0);
sbin/unwind/libunbound/util/config_file.c
868
IS_NUMBER_OR_ZERO; cfg->ip_ratelimit_cookie = atoi(val);
sbin/unwind/libunbound/util/config_file.c
872
IS_NUMBER_OR_ZERO; cfg->ip_ratelimit = atoi(val);
sbin/unwind/libunbound/util/config_file.c
876
IS_NUMBER_OR_ZERO; cfg->ratelimit = atoi(val);
sbin/unwind/libunbound/util/config_file.c
903
{ IS_NUMBER_OR_ZERO; cfg->ipsecmod_max_ttl = atoi(val); }
sbin/unwind/libunbound/util/config_file.c
913
return config_add_tag(cfg, val);
sbin/unwind/libunbound/util/config_file.c
917
{ IS_NUMBER_OR_ZERO; cfg->val_sig_skew_min = (int32_t)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
919
{ IS_NUMBER_OR_ZERO; cfg->val_sig_skew_max = (int32_t)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
921
{ IS_NUMBER_OR_ZERO; cfg->val_max_restart = (int32_t)atoi(val); }
sbin/unwind/libunbound/util/config_file.c
923
char* d = strdup(val);
sbin/unwind/libunbound/util/config_file.h
1326
int cfg_parse_local_zone(struct config_file* cfg, const char* val);
sbin/unwind/libunbound/util/configlexer.c
3658
if(num_args > 0) { BEGIN(val); } \
sbin/unwind/libunbound/util/configlexer.c
6061
else { BEGIN(val); }
sbin/unwind/libunbound/util/configlexer.c
6082
else { BEGIN(val); }
sbin/unwind/libunbound/util/configlexer.c
6101
else { BEGIN(val); }
sbin/unwind/libunbound/util/configlexer.c
6122
else { BEGIN(val); }
sbin/unwind/libunbound/util/configlexer.c
6199
case YY_STATE_EOF(val):
sbin/unwind/libunbound/util/netevent.c
1215
unsigned int val = ecn;
sbin/unwind/libunbound/util/netevent.c
1217
if(setsockopt(fd, IPPROTO_IPV6, IPV6_TCLASS, &val,
sbin/unwind/libunbound/util/netevent.c
1218
(socklen_t)sizeof(val)) == -1) {
sbin/unwind/libunbound/util/netevent.c
1224
if(setsockopt(fd, IPPROTO_IP, IP_TOS, &val,
sbin/unwind/libunbound/util/netevent.c
1225
(socklen_t)sizeof(val)) == -1) {
sbin/unwind/parse.y
563
char *p, *val;
sbin/unwind/parse.y
593
val = symget(buf);
sbin/unwind/parse.y
594
if (val == NULL) {
sbin/unwind/parse.y
598
p = val + strlen(val) - 1;
sbin/unwind/parse.y
600
while (p >= val) {
sbin/unwind/parse.y
78
char *val;
sbin/unwind/parse.y
834
free(sym->val);
sbin/unwind/parse.y
849
symset(const char *nam, const char *val, int persist)
sbin/unwind/parse.y
863
free(sym->val);
sbin/unwind/parse.y
876
sym->val = strdup(val);
sbin/unwind/parse.y
877
if (sym->val == NULL) {
sbin/unwind/parse.y
891
char *sym, *val;
sbin/unwind/parse.y
894
if ((val = strrchr(s, '=')) == NULL)
sbin/unwind/parse.y
896
sym = strndup(s, val - s);
sbin/unwind/parse.y
899
ret = symset(sym, val + 1, 1);
sbin/unwind/parse.y
913
return (sym->val);
sbin/wsconsctl/mousecfg.c
310
read_param(struct wsmouse_parameters *field, char *val)
sbin/wsconsctl/mousecfg.c
314
n = sscanf(val, "%d:%d,%d:%d,%d:%d,%d:%d",
sbin/wsconsctl/mousecfg.c
328
n = sscanf(val, "%d,%d,%d,%d",
sbin/wsconsctl/mousecfg.c
379
mousecfg_rd_field(struct wsmouse_parameters *field, char *val)
sbin/wsconsctl/mousecfg.c
386
if (read_param(field, val))
sbin/wsconsctl/mousecfg.c
392
if (set_tapping(field, val))
sbin/wsconsctl/mousecfg.c
398
if (sscanf(val, "%f", &f) == 1) {
sbin/wsconsctl/mousecfg.c
411
if (set_edges(field, val))
sbin/wsconsctl/mousecfg.c
416
s = val;
sbin/wsconsctl/mousecfg.c
424
errx(1, "invalid input '%s'", val);
sbin/wsconsctl/util.c
219
int2name(int val, int uflag, const struct nameint *tab, int len)
sbin/wsconsctl/util.c
225
if (tab[i].value == val)
sbin/wsconsctl/util.c
229
snprintf(tmp, sizeof(tmp), "unknown_%d", val);
sbin/wsconsctl/util.c
236
name2int(char *val, const struct nameint *tab, int len)
sbin/wsconsctl/util.c
241
if (strcmp(tab[i].name, val) == 0)
sbin/wsconsctl/util.c
331
rd_field(struct field *f, char *val, int merge)
sbin/wsconsctl/util.c
341
if (sscanf(val, "%u", &u) != 1)
sbin/wsconsctl/util.c
342
errx(1, "%s: not a number", val);
sbin/wsconsctl/util.c
349
if (sscanf(val, "%d", &i) != 1)
sbin/wsconsctl/util.c
350
errx(1, "%s: not a number", val);
sbin/wsconsctl/util.c
357
if (*val != 'o' || (val[1] != 'n' &&
sbin/wsconsctl/util.c
358
(val[1] != 'f' || val[2] != 'f')))
sbin/wsconsctl/util.c
359
errx(1, "%s: invalid value (on/off)", val);
sbin/wsconsctl/util.c
360
*((u_int *) f->valp) = val[1] == 'n'? 1 : 0;
sbin/wsconsctl/util.c
364
if ((i = sscanf(val, "%u.%u%%", &u, &fr)) != 2 && i != 1)
sbin/wsconsctl/util.c
365
errx(1, "%s: not a valid number", val);
sbin/wsconsctl/util.c
381
p = strchr(val, '.');
sbin/wsconsctl/util.c
385
i = name2int(val, kbdenc_tab, TABLEN(kbdenc_tab));
sbin/wsconsctl/util.c
387
errx(1, "%s: not a valid encoding", val);
sbin/wsconsctl/util.c
391
val = p;
sbin/wsconsctl/util.c
395
i = name2int(val, kbdvar_tab, TABLEN(kbdvar_tab));
sbin/wsconsctl/util.c
397
errx(1, "%s: not a valid variant", val);
sbin/wsconsctl/util.c
404
map_scan_setinput(val);
sbin/wsconsctl/util.c
429
val = (void *)strtok(val, ",");
sbin/wsconsctl/util.c
430
if (val != NULL) {
sbin/wsconsctl/util.c
431
wmcoords.minx = (int)strtonum(val,
sbin/wsconsctl/util.c
433
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
435
if (!errstr && val != NULL) {
sbin/wsconsctl/util.c
436
wmcoords.maxx = (int)strtonum(val,
sbin/wsconsctl/util.c
438
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
440
if (!errstr && val != NULL) {
sbin/wsconsctl/util.c
441
wmcoords.miny = (int)strtonum(val,
sbin/wsconsctl/util.c
443
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
445
if (!errstr && val != NULL) {
sbin/wsconsctl/util.c
446
wmcoords.maxy = (int)strtonum(val,
sbin/wsconsctl/util.c
448
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
450
if (!errstr && val != NULL) {
sbin/wsconsctl/util.c
451
wmcoords.swapxy = (int)strtonum(val,
sbin/wsconsctl/util.c
453
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
455
if (!errstr && val != NULL) {
sbin/wsconsctl/util.c
456
wmcoords.resx = (int)strtonum(val,
sbin/wsconsctl/util.c
458
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
460
if (!errstr && val != NULL) {
sbin/wsconsctl/util.c
461
wmcoords.resy = (int)strtonum(val,
sbin/wsconsctl/util.c
463
val = (void *)strtok(NULL, ",");
sbin/wsconsctl/util.c
467
if (val != NULL)
sbin/wsconsctl/util.c
473
strlcpy(f->valp, val, WSFONT_NAME_SIZE);
sbin/wsconsctl/util.c
476
mousecfg_rd_field((struct wsmouse_parameters *) f->valp, val);
sys/arch/alpha/alpha/pmap.c
687
#define PMAP_SET_PTE(ptep, val) *(ptep) = (val)
sys/arch/alpha/eisa/eisa_machdep.c
297
u_int32_t val = 0;
sys/arch/alpha/eisa/eisa_machdep.c
300
for (i = 0; i < sizeof(val); i++) {
sys/arch/alpha/eisa/eisa_machdep.c
301
val |= (u_int32_t)*src << (i * 8);
sys/arch/alpha/eisa/eisa_machdep.c
305
*valp = val;
sys/arch/alpha/include/_types.h
40
long val[10];
sys/arch/alpha/include/alpha_cpu.h
547
alpha_pal_wrval(unsigned long val)
sys/arch/alpha/include/alpha_cpu.h
549
register unsigned long a0 __asm("$16") = val;
sys/arch/alpha/pci/apecsreg.h
338
u_int64_t val;
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
474
u_int8_t val)
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
479
alpha_stb((u_int8_t *)addr, val);
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
485
u_int16_t val)
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
495
alpha_stw((u_int16_t *)addr, val);
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
501
u_int32_t val)
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
511
*(u_int32_t *)addr = val;
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
517
u_int64_t val)
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
561
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
565
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
566
__C(CHIP,_io_barrier)(v, h, o, sizeof val, \
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
578
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
582
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_bwx_bus_io_chipdep.c
583
o += sizeof val; \
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
501
u_int8_t val)
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
506
alpha_stb((u_int8_t *)addr, val);
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
512
u_int16_t val)
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
522
alpha_stw((u_int16_t *)addr, val);
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
528
u_int32_t val)
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
538
*(u_int32_t *)addr = val;
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
544
u_int64_t val)
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
588
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
592
__C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
593
__C(CHIP,_mem_barrier)(v, h, o, sizeof val, \
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
605
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
609
__C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_bwx_bus_mem_chipdep.c
610
o += sizeof val; \
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
478
register u_int32_t *port, val;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
487
val = *port;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
488
rval = ((val) >> (8 * offset)) & 0xff;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
497
register u_int32_t *port, val;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
506
val = *port;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
507
rval = ((val) >> (8 * offset)) & 0xffff;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
516
register u_int32_t *port, val;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
525
val = *port;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
527
rval = ((val) >> (8 * offset)) & 0xffffffff;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
529
rval = val;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
578
u_int8_t val)
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
586
nval = val << (8 * offset);
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
594
u_int16_t val)
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
602
nval = val << (8 * offset);
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
610
u_int32_t val)
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
618
nval = val /*<< (8 * offset)*/;
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
626
u_int64_t val)
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
670
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
674
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
675
__C(CHIP,_io_barrier)(v, h, o, sizeof val, \
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
687
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
691
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_swiz_bus_io_chipdep.c
692
o += sizeof val; \
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
707
register u_int32_t *port, val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
719
val = *port;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
720
rval = ((val) >> (8 * offset)) & 0xff;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
729
register u_int32_t *port, val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
741
val = *port;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
742
rval = ((val) >> (8 * offset)) & 0xffff;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
751
register u_int32_t *port, val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
763
val = *port;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
765
rval = ((val) >> (8 * offset)) & 0xffffffff;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
767
rval = val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
821
u_int8_t val)
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
828
(*(u_int8_t *)(memh + off)) = val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
832
nval = val << (8 * offset);
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
841
u_int16_t val)
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
848
(*(u_int16_t *)(memh + off)) = val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
852
nval = val << (8 * offset);
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
861
u_int32_t val)
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
868
(*(u_int32_t *)(memh + off)) = val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
872
nval = val /*<< (8 * offset)*/;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
881
u_int64_t val)
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
885
(*(u_int64_t *)(memh + off)) = val;
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
930
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
934
__C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
935
__C(CHIP,_mem_barrier)(v, h, o, sizeof val, \
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
947
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
951
__C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \
sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
952
o += sizeof val; \
sys/arch/alpha/pci/sio_pic.c
195
i82378_write_elcr(int elcr, u_int8_t val)
sys/arch/alpha/pci/sio_pic.c
198
bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val);
sys/arch/alpha/pci/sio_pic.c
257
cy82c693_write_elcr(int elcr, u_int8_t val)
sys/arch/alpha/pci/sio_pic.c
260
cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val);
sys/arch/alpha/pci/tsciic.c
173
tsciic_write_byte(void *cookie, uint8_t val, int flags)
sys/arch/alpha/pci/tsciic.c
175
return i2c_bitbang_write_byte(cookie, val, flags, &tsciicbb_ops);
sys/arch/alpha/pci/tsciic.c
182
uint64_t val;
sys/arch/alpha/pci/tsciic.c
184
val = (bits & MPD_BIT_SDA ? MPD_DS : 0) |
sys/arch/alpha/pci/tsciic.c
187
STQP(TS_C_MPD) = val;
sys/arch/alpha/pci/tsciic.c
200
uint64_t val;
sys/arch/alpha/pci/tsciic.c
203
val = LDQP(TS_C_MPD);
sys/arch/alpha/pci/tsciic.c
204
bits = (val & MPD_DR ? MPD_BIT_SDA : 0) |
sys/arch/alpha/pci/tsciic.c
205
(val & MPD_CKR ? MPD_BIT_SCL : 0);
sys/arch/alpha/tc/ioasic.c
273
ioasic_intrnull(void *val)
sys/arch/alpha/tc/ioasic.c
277
(u_long)val);
sys/arch/alpha/tc/ioasic.c
284
ioasic_intr(void *val)
sys/arch/alpha/tc/ioasic.c
286
register struct ioasic_softc *sc = val;
sys/arch/alpha/tc/tc_3000_300.c
178
tc_3000_300_intrnull(void *val)
sys/arch/alpha/tc/tc_3000_300.c
182
(u_long)val);
sys/arch/alpha/tc/tc_3000_500.c
176
tc_3000_500_intrnull(void *val)
sys/arch/alpha/tc/tc_3000_500.c
180
(u_long)val);
sys/arch/alpha/tc/tc_bus_mem.c
414
tc_mem_write_1(void *v, bus_space_handle_t memh, bus_size_t off, u_int8_t val)
sys/arch/alpha/tc/tc_bus_mem.c
427
v = (msk << 32) | (((u_int64_t)val) << (shift * 8));
sys/arch/alpha/tc/tc_bus_mem.c
429
*p = val;
sys/arch/alpha/tc/tc_bus_mem.c
434
*p = val;
sys/arch/alpha/tc/tc_bus_mem.c
440
tc_mem_write_2(void *v, bus_space_handle_t memh, bus_size_t off, u_int16_t val)
sys/arch/alpha/tc/tc_bus_mem.c
453
v = (msk << 32) | (((u_int64_t)val) << (shift * 8));
sys/arch/alpha/tc/tc_bus_mem.c
455
*p = val;
sys/arch/alpha/tc/tc_bus_mem.c
460
*p = val;
sys/arch/alpha/tc/tc_bus_mem.c
466
tc_mem_write_4(void *v, bus_space_handle_t memh, bus_size_t off, u_int32_t val)
sys/arch/alpha/tc/tc_bus_mem.c
475
*p = val;
sys/arch/alpha/tc/tc_bus_mem.c
480
tc_mem_write_8(void *v, bus_space_handle_t memh, bus_size_t off, u_int64_t val)
sys/arch/alpha/tc/tc_bus_mem.c
488
*p = val;
sys/arch/alpha/tc/tc_bus_mem.c
527
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/tc/tc_bus_mem.c
531
__C(tc_mem_write_,BYTES)(v, h, o, val); \
sys/arch/alpha/tc/tc_bus_mem.c
532
tc_mem_barrier(v, h, o, sizeof val, BUS_SPACE_BARRIER_WRITE); \
sys/arch/alpha/tc/tc_bus_mem.c
543
bus_size_t o, TYPE val, bus_size_t c) \
sys/arch/alpha/tc/tc_bus_mem.c
547
__C(tc_mem_write_,BYTES)(v, h, o, val); \
sys/arch/alpha/tc/tc_bus_mem.c
548
o += sizeof val; \
sys/arch/amd64/amd64/amd64_mem.c
109
mtrr2mrt(int val)
sys/arch/amd64/amd64/amd64_mem.c
111
if (val < 0 || val >= nitems(mtrrtomrt))
sys/arch/amd64/amd64/amd64_mem.c
113
return mtrrtomrt[val];
sys/arch/amd64/amd64/amd64_mem.c
261
int val;
sys/arch/amd64/amd64/amd64_mem.c
263
val = mtrrtype(flags);
sys/arch/amd64/amd64/amd64_mem.c
265
return val & 0xff;
sys/arch/amd64/amd64/amd64_mem.c
86
int mtrr2mrt(int val);
sys/arch/amd64/amd64/amd64errata.c
262
uint64_t val;
sys/arch/amd64/amd64/amd64errata.c
266
val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
sys/arch/amd64/amd64/amd64errata.c
267
if ((val & e->e_data2) != 0)
sys/arch/amd64/amd64/amd64errata.c
277
uint64_t val;
sys/arch/amd64/amd64/amd64errata.c
281
val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
sys/arch/amd64/amd64/amd64errata.c
282
if ((val & e->e_data2) != 0)
sys/arch/amd64/amd64/amd64errata.c
285
wrmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE, val | e->e_data2);
sys/arch/amd64/amd64/amd64errata.c
289
val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
sys/arch/amd64/amd64/amd64errata.c
290
if ((val & e->e_data2) != 0)
sys/arch/amd64/amd64/ghcb.c
283
_ghcb_mem_rw(vaddr_t addr, int valsz, void *val, bool read)
sys/arch/amd64/amd64/ghcb.c
292
KASSERT(val != NULL);
sys/arch/amd64/amd64/ghcb.c
330
ghcb_regs.data = val;
sys/arch/amd64/amd64/ghcb.c
355
ghcb_regs.data = val;
sys/arch/amd64/amd64/ghcb.c
373
_ghcb_io_rw(uint16_t port, int valsz, uint32_t *val, bool read)
sys/arch/amd64/amd64/ghcb.c
381
KASSERT(val != NULL);
sys/arch/amd64/amd64/ghcb.c
405
frame.tf_rax = *val;
sys/arch/amd64/amd64/ghcb.c
435
*val = frame.tf_rax;
sys/arch/amd64/amd64/identcpu.c
152
uint64_t mperf, aperf, mdelta, adelta, val;
sys/arch/amd64/amd64/identcpu.c
168
val = (adelta * 1000000) / mdelta * tsc_frequency;
sys/arch/amd64/amd64/identcpu.c
169
val = ((val + FREQ_50MHZ / 2) / FREQ_50MHZ) * FREQ_50MHZ;
sys/arch/amd64/amd64/identcpu.c
170
ci->ci_hz_sensor.value = val;
sys/arch/amd64/amd64/identcpu.c
186
u_int32_t regs[4], val;
sys/arch/amd64/amd64/identcpu.c
192
val = regs[0];
sys/arch/amd64/amd64/identcpu.c
193
if (val >= 0xC0000001) {
sys/arch/amd64/amd64/identcpu.c
195
val = regs[3];
sys/arch/amd64/amd64/identcpu.c
197
val = 0;
sys/arch/amd64/amd64/identcpu.c
199
if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
sys/arch/amd64/amd64/identcpu.c
203
if (val & C3_CPUID_HAS_RNG) {
sys/arch/amd64/amd64/identcpu.c
206
if (!(val & C3_CPUID_DO_RNG)) {
sys/arch/amd64/amd64/identcpu.c
216
if (val & C3_CPUID_HAS_ACE) {
sys/arch/amd64/amd64/identcpu.c
218
if (!(val & C3_CPUID_DO_ACE)) {
sys/arch/amd64/amd64/identcpu.c
229
if (val & C3_CPUID_HAS_ACE2) {
sys/arch/amd64/amd64/identcpu.c
231
if (!(val & C3_CPUID_DO_ACE2)) {
sys/arch/amd64/amd64/identcpu.c
242
if (val & C3_CPUID_HAS_PHE) {
sys/arch/amd64/amd64/identcpu.c
244
if (!(val & C3_CPUID_DO_PHE)) {
sys/arch/amd64/amd64/identcpu.c
255
if (val & C3_CPUID_HAS_PMM) {
sys/arch/amd64/amd64/identcpu.c
257
if (!(val & C3_CPUID_DO_PMM)) {
sys/arch/amd64/amd64/identcpu.c
378
pcpuid(struct cpu_info *ci, const char *id, char reg, uint32_t val,
sys/arch/amd64/amd64/identcpu.c
382
pcpu0id3(id, reg, val, bits, 0, 0, NULL, 0, 0, NULL);
sys/arch/amd64/amd64/identcpu.c
383
else if (val != prev_val) {
sys/arch/amd64/amd64/identcpu.c
385
pbitdiff(val, prev_val, bits);
sys/arch/amd64/amd64/ioapic.c
136
ioapic_write_ul(struct ioapic_softc *sc,int regid, u_int32_t val)
sys/arch/amd64/amd64/ioapic.c
139
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOAPIC_DATA, val);
sys/arch/amd64/amd64/ioapic.c
145
u_int32_t val;
sys/arch/amd64/amd64/ioapic.c
149
val = ioapic_read_ul(sc, regid);
sys/arch/amd64/amd64/ioapic.c
151
return val;
sys/arch/amd64/amd64/ioapic.c
155
ioapic_write(struct ioapic_softc *sc,int regid, int val)
sys/arch/amd64/amd64/ioapic.c
160
ioapic_write_ul(sc, regid, val);
sys/arch/amd64/amd64/lapic.c
106
void x2apic_writereg(int reg, u_int32_t val);
sys/arch/amd64/amd64/lapic.c
111
void i82489_writereg(int reg, u_int32_t val);
sys/arch/amd64/amd64/lapic.c
134
i82489_writereg(int reg, u_int32_t val)
sys/arch/amd64/amd64/lapic.c
137
val;
sys/arch/amd64/amd64/lapic.c
153
x2apic_writereg(int reg, u_int32_t val)
sys/arch/amd64/amd64/lapic.c
155
wrmsr(MSR_X2APIC_BASE + (reg >> 4), val);
sys/arch/amd64/amd64/lapic.c
723
u_int32_t val;
sys/arch/amd64/amd64/lapic.c
726
val = lapic_readreg(reg);
sys/arch/amd64/amd64/lapic.c
727
val |= LAPIC_LVT_MASKED;
sys/arch/amd64/amd64/lapic.c
728
lapic_writereg(reg, val);
sys/arch/amd64/amd64/lapic.c
735
u_int32_t val;
sys/arch/amd64/amd64/lapic.c
738
val = lapic_readreg(reg);
sys/arch/amd64/amd64/lapic.c
739
val &= ~LAPIC_LVT_MASKED;
sys/arch/amd64/amd64/lapic.c
740
lapic_writereg(reg, val);
sys/arch/amd64/amd64/powernow-k8.c
189
u_int val;
sys/arch/amd64/amd64/powernow-k8.c
212
val = cvid - (1 << cstate->mvs);
sys/arch/amd64/amd64/powernow-k8.c
213
WRITE_FIDVID(cfid, (val > 0) ? val : 0, 1ULL);
sys/arch/amd64/amd64/powernow-k8.c
242
val = cfid + 2;
sys/arch/amd64/amd64/powernow-k8.c
244
val = FID_TO_VCO_FID(cfid) + 2;
sys/arch/amd64/amd64/powernow-k8.c
246
val = cfid - 2;
sys/arch/amd64/amd64/powernow-k8.c
247
WRITE_FIDVID(val, cvid, (uint64_t)cstate->pll * 1000 / 5);
sys/arch/amd64/amd64/tsc.c
364
volatile uint64_t val; /* [a] Latest RDTSC value */
sys/arch/amd64/amd64/tsc.c
543
bp_val = tsc_bp_status.val;
sys/arch/amd64/amd64/tsc.c
545
tsc_ap_status.val = ap_val;
sys/arch/amd64/amd64/tsc.c
572
ap_val = tsc_ap_status.val;
sys/arch/amd64/amd64/tsc.c
574
tsc_bp_status.val = bp_val;
sys/arch/amd64/amd64/vmm_machdep.c
5959
uint64_t *rdx, *rcx, val, mask = xsave_mask & XFEATURE_XCR0_MASK;
sys/arch/amd64/amd64/vmm_machdep.c
5979
val = *rax + (*rdx << 32);
sys/arch/amd64/amd64/vmm_machdep.c
5980
if (val & ~mask) {
sys/arch/amd64/amd64/vmm_machdep.c
5982
__func__, val);
sys/arch/amd64/amd64/vmm_machdep.c
5986
vcpu->vc_gueststate.vg_xcr0 = val;
sys/arch/amd64/amd64/vmm_machdep.c
6036
uint64_t insn_length, val;
sys/arch/amd64/amd64/vmm_machdep.c
6054
val = (*rdx << 32) | (*rax & 0xFFFFFFFFULL);
sys/arch/amd64/amd64/vmm_machdep.c
6058
if (!vmm_pat_is_valid(val)) {
sys/arch/amd64/amd64/vmm_machdep.c
6062
vcpu->vc_shadow_pat = val;
sys/arch/amd64/amd64/vmm_machdep.c
6114
uint64_t insn_length, val;
sys/arch/amd64/amd64/vmm_machdep.c
6128
val = (*rdx << 32) | (*rax & 0xFFFFFFFFULL);
sys/arch/amd64/amd64/vmm_machdep.c
6132
if (!vmm_pat_is_valid(val)) {
sys/arch/amd64/amd64/vmm_machdep.c
6136
vcpu->vc_shadow_pat = val;
sys/arch/amd64/amd64/vmm_machdep.c
7559
uint64_t val;
sys/arch/amd64/amd64/vmm_machdep.c
7563
if (vmread(fieldid, &val))
sys/arch/amd64/amd64/vmm_machdep.c
7576
case 0: DPRINTF("0x%04llx ", val); break;
sys/arch/amd64/amd64/vmm_machdep.c
7578
case 3: DPRINTF("0x%016llx ", val); break;
sys/arch/amd64/amd64/vmm_machdep.c
7579
case 2: DPRINTF("0x%08llx ", val);
sys/arch/amd64/amd64/vmm_machdep.c
8476
vmm_segment_desc_decode(uint64_t val)
sys/arch/amd64/amd64/vmm_machdep.c
8483
unusable = val & 0x10000;
sys/arch/amd64/amd64/vmm_machdep.c
8489
ar = (uint16_t)val;
sys/arch/amd64/amd64/vmm_machdep.c
8688
vmm_decode_mtrrcap_value(uint64_t val)
sys/arch/amd64/amd64/vmm_machdep.c
8700
if (val & mtrrcap_info[i].vrdi_bit)
sys/arch/amd64/amd64/vmm_machdep.c
8705
if (val & MTRRcap_FIXED)
sys/arch/amd64/amd64/vmm_machdep.c
8707
(val & 0xff));
sys/arch/amd64/amd64/vmm_machdep.c
8713
vmm_decode_perf_status_value(uint64_t val)
sys/arch/amd64/amd64/vmm_machdep.c
8715
DPRINTF("(pstate ratio = 0x%llx)\n", (val & 0xffff));
sys/arch/amd64/amd64/vmm_machdep.c
8719
vmm_decode_perf_ctl_value(uint64_t val)
sys/arch/amd64/amd64/vmm_machdep.c
8721
DPRINTF("(%s ", (val & PERF_CTL_TURBO) ? "TURBO" : "turbo");
sys/arch/amd64/amd64/vmm_machdep.c
8722
DPRINTF("pstate req = 0x%llx)\n", (val & 0xfffF));
sys/arch/amd64/amd64/vmm_machdep.c
8783
vmm_decode_msr_value(uint64_t msr, uint64_t val)
sys/arch/amd64/amd64/vmm_machdep.c
8786
case MSR_APICBASE: vmm_decode_apicbase_msr_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8787
case MSR_IA32_FEATURE_CONTROL: vmm_decode_ia32_fc_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8788
case MSR_MTRRcap: vmm_decode_mtrrcap_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8789
case MSR_PERF_STATUS: vmm_decode_perf_status_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8790
case MSR_PERF_CTL: vmm_decode_perf_ctl_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8791
case MSR_MTRRdefType: vmm_decode_mtrrdeftype_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8792
case MSR_EFER: vmm_decode_efer_value(val); break;
sys/arch/amd64/amd64/vmm_machdep.c
8793
case MSR_MISC_ENABLE: vmm_decode_misc_enable_value(val); break;
sys/arch/amd64/include/_types.h
56
long val[8];
sys/arch/amd64/include/cpufunc.h
105
lcr0(u_int val)
sys/arch/amd64/include/cpufunc.h
107
u_int64_t val64 = val;
sys/arch/amd64/include/cpufunc.h
115
u_int val;
sys/arch/amd64/include/cpufunc.h
117
val = val64;
sys/arch/amd64/include/cpufunc.h
118
return val;
sys/arch/amd64/include/cpufunc.h
124
u_int64_t val;
sys/arch/amd64/include/cpufunc.h
125
__asm volatile("movq %%cr2,%0" : "=r" (val));
sys/arch/amd64/include/cpufunc.h
126
return val;
sys/arch/amd64/include/cpufunc.h
130
lcr3(u_int64_t val)
sys/arch/amd64/include/cpufunc.h
132
__asm volatile("movq %0,%%cr3" : : "r" (val));
sys/arch/amd64/include/cpufunc.h
138
u_int64_t val;
sys/arch/amd64/include/cpufunc.h
139
__asm volatile("movq %%cr3,%0" : "=r" (val));
sys/arch/amd64/include/cpufunc.h
140
return val;
sys/arch/amd64/include/cpufunc.h
147
lcr4(u_int val)
sys/arch/amd64/include/cpufunc.h
149
u_int64_t val64 = val;
sys/arch/amd64/include/cpufunc.h
168
u_int64_t val;
sys/arch/amd64/include/cpufunc.h
169
__asm volatile("movq %%dr6,%0" : "=r" (val));
sys/arch/amd64/include/cpufunc.h
170
return val;
sys/arch/amd64/include/cpufunc.h
176
u_int64_t val;
sys/arch/amd64/include/cpufunc.h
177
__asm volatile("movq %%dr7,%0" : "=r" (val));
sys/arch/amd64/include/cpufunc.h
178
return val;
sys/arch/amd64/include/cpufunc.h
184
u_int64_t val;
sys/arch/amd64/include/cpufunc.h
185
__asm volatile("movq %%cr3,%0" : "=r" (val));
sys/arch/amd64/include/cpufunc.h
186
__asm volatile("movq %0,%%cr3" : : "r" (val));
sys/arch/amd64/include/cpufunc.h
95
lcr8(u_int val)
sys/arch/amd64/include/cpufunc.h
97
u_int64_t val64 = val;
sys/arch/amd64/include/ghcb.h
144
uint8_t val;
sys/arch/amd64/include/ghcb.h
146
_ghcb_mem_rw(addr, GHCB_SZ8, &val, true);
sys/arch/amd64/include/ghcb.h
147
return val;
sys/arch/amd64/include/ghcb.h
153
uint16_t val;
sys/arch/amd64/include/ghcb.h
155
_ghcb_mem_rw(addr, GHCB_SZ16, &val, true);
sys/arch/amd64/include/ghcb.h
156
return val;
sys/arch/amd64/include/ghcb.h
162
uint32_t val;
sys/arch/amd64/include/ghcb.h
164
_ghcb_mem_rw(addr, GHCB_SZ32, &val, true);
sys/arch/amd64/include/ghcb.h
165
return val;
sys/arch/amd64/include/ghcb.h
171
uint64_t val;
sys/arch/amd64/include/ghcb.h
173
_ghcb_mem_rw(addr, GHCB_SZ64, &val, true);
sys/arch/amd64/include/ghcb.h
174
return val;
sys/arch/amd64/include/ghcb.h
204
uint32_t val;
sys/arch/amd64/include/ghcb.h
206
_ghcb_io_rw(port, GHCB_SZ8, &val, true);
sys/arch/amd64/include/ghcb.h
207
return val;
sys/arch/amd64/include/ghcb.h
213
uint32_t val;
sys/arch/amd64/include/ghcb.h
215
_ghcb_io_rw(port, GHCB_SZ16, &val, true);
sys/arch/amd64/include/ghcb.h
216
return val;
sys/arch/amd64/include/ghcb.h
222
uint32_t val;
sys/arch/amd64/include/ghcb.h
224
_ghcb_io_rw(port, GHCB_SZ32, &val, true);
sys/arch/amd64/include/ghcb.h
225
return val;
sys/arch/amd64/include/ghcb.h
231
uint32_t val = v;
sys/arch/amd64/include/ghcb.h
233
_ghcb_io_rw(port, GHCB_SZ8, &val, false);
sys/arch/amd64/include/ghcb.h
239
uint32_t val = v;
sys/arch/amd64/include/ghcb.h
241
_ghcb_io_rw(port, GHCB_SZ16, &val, false);
sys/arch/amd64/include/tcb.h
42
void *val;
sys/arch/amd64/include/tcb.h
43
__asm__ ("movq %%fs:(%1),%0" : "=r" (val) : "r" (offset));
sys/arch/amd64/include/tcb.h
44
return val;
sys/arch/amd64/pci/vga_post.c
102
vm86_emu_outw(struct x86emu *emu, uint16_t port, uint16_t val)
sys/arch/amd64/pci/vga_post.c
107
outw(port, val);
sys/arch/amd64/pci/vga_post.c
111
vm86_emu_outl(struct x86emu *emu, uint16_t port, uint32_t val)
sys/arch/amd64/pci/vga_post.c
116
outl(port, val);
sys/arch/amd64/pci/vga_post.c
90
vm86_emu_outb(struct x86emu *emu, uint16_t port, uint8_t val)
sys/arch/amd64/pci/vga_post.c
98
outb(port, val);
sys/arch/arm/arm/vfp.c
29
set_vfp_fpexc(uint32_t val)
sys/arch/arm/arm/vfp.c
33
"vmsr fpexc, %0" :: "r" (val));
sys/arch/arm/arm/vfp.c
39
uint32_t val;
sys/arch/arm/arm/vfp.c
42
"vmrs %0, fpexc" : "=r" (val));
sys/arch/arm/arm/vfp.c
43
return val;
sys/arch/arm/arm/vfp.c
53
uint32_t val;
sys/arch/arm/arm/vfp.c
58
__asm volatile("mrc p15, 0, %0, c1, c0, 2" : "=r" (val));
sys/arch/arm/arm/vfp.c
59
val |= COPROC10 | COPROC11;
sys/arch/arm/arm/vfp.c
60
__asm volatile("mcr p15, 0, %0, c1, c0, 2" :: "r" (val));
sys/arch/arm/cortex/agtimer.c
102
uint32_t val;
sys/arch/arm/cortex/agtimer.c
104
__asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
sys/arch/arm/cortex/agtimer.c
106
return (val);
sys/arch/arm/cortex/agtimer.c
110
agtimer_set_ctrl(uint32_t val)
sys/arch/arm/cortex/agtimer.c
113
[val] "r" (val));
sys/arch/arm/cortex/agtimer.c
122
agtimer_set_tval(uint32_t val)
sys/arch/arm/cortex/agtimer.c
125
[val] "r" (val));
sys/arch/arm/cortex/agtimer.c
92
uint64_t val;
sys/arch/arm/cortex/agtimer.c
94
__asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
sys/arch/arm/cortex/agtimer.c
96
return (val);
sys/arch/arm/cortex/ampintc.c
567
uint8_t mask, val;
sys/arch/arm/cortex/ampintc.c
572
val = bus_space_read_1(sc->sc_iot, sc->sc_d_ioh, ICD_IPTRn(irq));
sys/arch/arm/cortex/ampintc.c
574
val |= mask;
sys/arch/arm/cortex/ampintc.c
576
val &= ~mask;
sys/arch/arm/cortex/ampintc.c
577
bus_space_write_1(sc->sc_iot, sc->sc_d_ioh, ICD_IPTRn(irq), val);
sys/arch/arm/cortex/arml2cc.c
197
arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val)
sys/arch/arm/cortex/arml2cc.c
199
bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
sys/arch/arm/include/_types.h
40
long val[11];
sys/arch/arm64/arm64/intr.c
372
void *val = NULL;
sys/arch/arm64/arm64/intr.c
425
val = ic->ic_establish(ic->ic_cookie, cell, level,
sys/arch/arm64/arm64/intr.c
436
if (val == NULL)
sys/arch/arm64/arm64/intr.c
441
ih->ih_ih = val;
sys/arch/arm64/arm64/intr.c
463
void *val = NULL;
sys/arch/arm64/arm64/intr.c
497
val = ic->ic_establish(ic->ic_cookie, &cell[5 + acells],
sys/arch/arm64/arm64/intr.c
506
if (val == NULL) {
sys/arch/arm64/arm64/intr.c
513
ih->ih_ih = val;
sys/arch/arm64/arm64/intr.c
535
void *val = NULL;
sys/arch/arm64/arm64/intr.c
546
val = ic->ic_establish_msi(ic->ic_cookie, addr, data,
sys/arch/arm64/arm64/intr.c
548
if (val == NULL)
sys/arch/arm64/arm64/intr.c
553
ih->ih_ih = val;
sys/arch/arm64/arm64/intr.c
600
void *val;
sys/arch/arm64/arm64/intr.c
610
val = ic->ic_establish(ic->ic_cookie, cell, level, ci, func, arg, name);
sys/arch/arm64/arm64/intr.c
611
if (val == NULL)
sys/arch/arm64/arm64/intr.c
616
ih->ih_ih = val;
sys/arch/arm64/arm64/trap.c
223
uint64_t val;
sys/arch/arm64/arm64/trap.c
238
val = READ_SPECIALREG(midr_el1);
sys/arch/arm64/arm64/trap.c
245
val = 0x80000000;
sys/arch/arm64/arm64/trap.c
248
val = 0;
sys/arch/arm64/arm64/trap.c
257
val = cpu_id_aa64pfr0;
sys/arch/arm64/arm64/trap.c
260
val = cpu_id_aa64pfr1;
sys/arch/arm64/arm64/trap.c
265
val = 0;
sys/arch/arm64/arm64/trap.c
274
val = cpu_id_aa64isar0;
sys/arch/arm64/arm64/trap.c
277
val = cpu_id_aa64isar1;
sys/arch/arm64/arm64/trap.c
280
val = cpu_id_aa64isar2;
sys/arch/arm64/arm64/trap.c
293
val = 0;
sys/arch/arm64/arm64/trap.c
304
frame->tf_x[rt] = val;
sys/arch/arm64/arm64/trap.c
306
frame->tf_lr = val;
sys/arch/arm64/dev/acpipci.c
511
struct aml_value *val)
sys/arch/arm64/dev/acpipci.c
517
if (val->type == AML_OBJTYPE_NAMEREF) {
sys/arch/arm64/dev/acpipci.c
518
node = aml_searchrel(node, aml_getname(val->v_nameref));
sys/arch/arm64/dev/acpipci.c
520
val = node->value;
sys/arch/arm64/dev/acpipci.c
522
if (val->type == AML_OBJTYPE_OBJREF)
sys/arch/arm64/dev/acpipci.c
523
val = val->v_objref.ref;
sys/arch/arm64/dev/acpipci.c
524
if (val->type != AML_OBJTYPE_DEVICE)
sys/arch/arm64/dev/acpipci.c
527
sta = acpi_getsta(sc->sc_acpi, val->node);
sys/arch/arm64/dev/acpipci.c
531
if (aml_evalname(sc->sc_acpi, val->node, "_CRS", 0, NULL, &res))
sys/arch/arm64/dev/acpipci.c
567
struct aml_value *val = res.v_package[i];
sys/arch/arm64/dev/acpipci.c
569
if (val->type != AML_OBJTYPE_PACKAGE)
sys/arch/arm64/dev/acpipci.c
571
if (val->length != 4)
sys/arch/arm64/dev/acpipci.c
573
if (val->v_package[0]->type != AML_OBJTYPE_INTEGER ||
sys/arch/arm64/dev/acpipci.c
574
val->v_package[1]->type != AML_OBJTYPE_INTEGER ||
sys/arch/arm64/dev/acpipci.c
575
val->v_package[3]->type != AML_OBJTYPE_INTEGER)
sys/arch/arm64/dev/acpipci.c
578
addr = val->v_package[0]->v_integer;
sys/arch/arm64/dev/acpipci.c
579
pin = val->v_package[1]->v_integer;
sys/arch/arm64/dev/acpipci.c
585
if (val->v_package[2]->type == AML_OBJTYPE_INTEGER) {
sys/arch/arm64/dev/acpipci.c
586
source = val->v_package[2]->v_integer;
sys/arch/arm64/dev/acpipci.c
587
index = val->v_package[3]->v_integer;
sys/arch/arm64/dev/acpipci.c
590
index = acpipci_intr_link(sc, node, val->v_package[2]);
sys/arch/arm64/dev/agtimer.c
112
uint64_t val;
sys/arch/arm64/dev/agtimer.c
117
__asm volatile("mrs %x0, CNTVCT_EL0" : "=r" (val));
sys/arch/arm64/dev/agtimer.c
119
if (((val + 1) & 0x1ff) > 1)
sys/arch/arm64/dev/agtimer.c
124
return val;
sys/arch/arm64/dev/agtimer.c
132
uint64_t val;
sys/arch/arm64/dev/agtimer.c
134
__asm volatile("mrs %x0, CNTFRQ_EL0" : "=r" (val));
sys/arch/arm64/dev/agtimer.c
136
return (val);
sys/arch/arm64/dev/agtimer.c
142
uint32_t val;
sys/arch/arm64/dev/agtimer.c
144
__asm volatile("mrs %x0, CNTV_CTL_EL0" : "=r" (val));
sys/arch/arm64/dev/agtimer.c
146
return (val);
sys/arch/arm64/dev/agtimer.c
150
agtimer_set_ctrl(uint32_t val)
sys/arch/arm64/dev/agtimer.c
152
__asm volatile("msr CNTV_CTL_EL0, %x0" :: "r" (val));
sys/arch/arm64/dev/agtimer.c
159
agtimer_set_tval(uint32_t val)
sys/arch/arm64/dev/agtimer.c
161
__asm volatile("msr CNTV_TVAL_EL0, %x0" :: "r" (val));
sys/arch/arm64/dev/agtimer.c
225
uint64_t val;
sys/arch/arm64/dev/agtimer.c
232
__asm volatile("mrs %x0, CNTVCT_EL0" : "=r" (val));
sys/arch/arm64/dev/agtimer.c
233
return (val & 0xffffffff);
sys/arch/arm64/dev/ampintc.c
594
uint8_t mask, val;
sys/arch/arm64/dev/ampintc.c
599
val = bus_space_read_1(sc->sc_iot, sc->sc_d_ioh, ICD_IPTRn(irq));
sys/arch/arm64/dev/ampintc.c
601
val |= mask;
sys/arch/arm64/dev/ampintc.c
603
val &= ~mask;
sys/arch/arm64/dev/ampintc.c
604
bus_space_write_1(sc->sc_iot, sc->sc_d_ioh, ICD_IPTRn(irq), val);
sys/arch/arm64/dev/apldart.c
140
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldart.c
141
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apldc.c
66
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldc.c
67
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apldma.c
74
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldma.c
75
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apldog.c
40
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldog.c
41
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apliic.c
58
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apliic.c
59
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplintc.c
46
#define AIC_INFO_NDIE(val) (((val) >> 24) & 0xf)
sys/arch/arm64/dev/aplintc.c
47
#define AIC_INFO_NIRQ(val) ((val) & 0xffff)
sys/arch/arm64/dev/aplintc.c
50
#define AIC_EVENT_DIE(val) (((val) >> 24) & 0xff)
sys/arch/arm64/dev/aplintc.c
51
#define AIC_EVENT_TYPE(val) (((val) >> 16) & 0xff)
sys/arch/arm64/dev/aplintc.c
55
#define AIC_EVENT_IRQ(val) ((val) & 0xffff)
sys/arch/arm64/dev/aplintc.c
80
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplintc.c
81
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplmbox.c
46
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplmbox.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplmbox.c
48
#define HWRITE8(sc, reg, val) \
sys/arch/arm64/dev/aplmbox.c
49
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplmca.c
98
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplmca.c
99
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplnco.c
44
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplnco.c
45
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpcie.c
103
#define LWRITE4(sc, port, reg, val) \
sys/arch/arm64/dev/aplpcie.c
104
bus_space_write_4((sc)->sc_iot, (sc)->sc_phy_ioh[port], (reg), (val))
sys/arch/arm64/dev/aplpcie.c
112
#define PWRITE4(sc, port, reg, val) \
sys/arch/arm64/dev/aplpcie.c
113
bus_space_write_4((sc)->sc_iot, (sc)->sc_port_ioh[(port)], (reg), (val))
sys/arch/arm64/dev/aplpcie.c
89
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpcie.c
90
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpcie.c
94
#define RWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpcie.c
95
bus_space_write_4((sc)->sc_iot, (sc)->sc_rc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpinctrl.c
243
int val;
sys/arch/arm64/dev/aplpinctrl.c
248
val = !!(reg & GPIO_PIN_DATA);
sys/arch/arm64/dev/aplpinctrl.c
250
val = !val;
sys/arch/arm64/dev/aplpinctrl.c
251
return val;
sys/arch/arm64/dev/aplpinctrl.c
255
aplpinctrl_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/arm64/dev/aplpinctrl.c
264
val = !val;
sys/arch/arm64/dev/aplpinctrl.c
265
if (val)
sys/arch/arm64/dev/aplpinctrl.c
56
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpinctrl.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpmgr.c
162
uint32_t val;
sys/arch/arm64/dev/aplpmgr.c
185
val = HREAD4(sc, ps->ps_offset);
sys/arch/arm64/dev/aplpmgr.c
186
val &= ~PMGR_PS_TARGET_MASK;
sys/arch/arm64/dev/aplpmgr.c
187
val |= (pstate << PMGR_PS_TARGET_SHIFT);
sys/arch/arm64/dev/aplpmgr.c
188
HWRITE4(sc, ps->ps_offset, val);
sys/arch/arm64/dev/aplpmgr.c
191
val = HREAD4(sc, ps->ps_offset);
sys/arch/arm64/dev/aplpmgr.c
192
val &= PMGR_PS_ACTUAL_MASK;
sys/arch/arm64/dev/aplpmgr.c
193
if ((val >> PMGR_PS_ACTUAL_SHIFT) == pstate)
sys/arch/arm64/dev/aplpmgr.c
210
uint32_t val;
sys/arch/arm64/dev/aplpmgr.c
213
val = HREAD4(sc, ps->ps_offset);
sys/arch/arm64/dev/aplpmgr.c
214
val &= ~(PMGR_WAS_CLKGATED | PMGR_WAS_PWRGATED);
sys/arch/arm64/dev/aplpmgr.c
215
HWRITE4(sc, ps->ps_offset, val | PMGR_DEV_DISABLE);
sys/arch/arm64/dev/aplpmgr.c
216
val = HREAD4(sc, ps->ps_offset);
sys/arch/arm64/dev/aplpmgr.c
217
val &= ~(PMGR_WAS_CLKGATED | PMGR_WAS_PWRGATED);
sys/arch/arm64/dev/aplpmgr.c
218
HWRITE4(sc, ps->ps_offset, val | PMGR_RESET);
sys/arch/arm64/dev/aplpmgr.c
220
val = HREAD4(sc, ps->ps_offset);
sys/arch/arm64/dev/aplpmgr.c
221
val &= ~(PMGR_WAS_CLKGATED | PMGR_WAS_PWRGATED);
sys/arch/arm64/dev/aplpmgr.c
222
HWRITE4(sc, ps->ps_offset, val & ~PMGR_RESET);
sys/arch/arm64/dev/aplpmgr.c
223
val = HREAD4(sc, ps->ps_offset);
sys/arch/arm64/dev/aplpmgr.c
224
val &= ~(PMGR_WAS_CLKGATED | PMGR_WAS_PWRGATED);
sys/arch/arm64/dev/aplpmgr.c
225
HWRITE4(sc, ps->ps_offset, val & ~PMGR_DEV_DISABLE);
sys/arch/arm64/dev/aplpmgr.c
45
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpmgr.c
46
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpwm.c
42
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpwm.c
43
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplrtk.c
37
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplrtk.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplsart.c
50
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplsart.c
51
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplsmc.c
713
aplsmc_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/arm64/dev/aplsmc.c
728
val = !val;
sys/arch/arm64/dev/aplsmc.c
729
data = SMC_GPIO_CMD_OUTPUT | !!val;
sys/arch/arm64/dev/aplsmc.c
882
uint8_t val;
sys/arch/arm64/dev/aplsmc.c
887
val = 0;
sys/arch/arm64/dev/aplsmc.c
889
&val, sizeof(val));
sys/arch/arm64/dev/aplsmc.c
892
val = 1;
sys/arch/arm64/dev/aplsmc.c
894
&val, sizeof(val));
sys/arch/arm64/dev/aplsmc.c
899
val = 0;
sys/arch/arm64/dev/aplsmc.c
901
&val, sizeof(val));
sys/arch/arm64/dev/aplsmc.c
904
val = 1;
sys/arch/arm64/dev/aplsmc.c
906
&val, sizeof(val));
sys/arch/arm64/dev/aplsmc.c
911
val = 0;
sys/arch/arm64/dev/aplsmc.c
913
&val, sizeof(val));
sys/arch/arm64/dev/aplsmc.c
916
val = 0;
sys/arch/arm64/dev/aplsmc.c
918
&val, sizeof(val));
sys/arch/arm64/dev/aplspi.c
97
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplspi.c
98
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplspmi.c
43
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplspmi.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/bcm2712_mip.c
47
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/bcm2712_mip.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/rpiclock.c
57
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/rpiclock.c
58
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/rpigpio.c
284
uint32_t val;
sys/arch/arm64/dev/rpigpio.c
315
val = bus_space_read_4(sc->sc_iot, sc->sc_pads_ioh,
sys/arch/arm64/dev/rpigpio.c
319
val &= ~PAD_BIAS_MASK;
sys/arch/arm64/dev/rpigpio.c
320
val |= bias;
sys/arch/arm64/dev/rpigpio.c
323
val &= ~PAD_CTRL_OUT_DIS;
sys/arch/arm64/dev/rpigpio.c
324
val |= PAD_CTRL_IN_EN;
sys/arch/arm64/dev/rpigpio.c
327
bank->pads + PAD_CTRL(pin), val);
sys/arch/arm64/dev/rpigpio.c
330
val = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh,
sys/arch/arm64/dev/rpigpio.c
333
val &= ~GPIOx_CTRL_FUNCSEL_MASK;
sys/arch/arm64/dev/rpigpio.c
334
val |= GPIOx_CTRL_FUNCSEL(func);
sys/arch/arm64/dev/rpigpio.c
335
val &= ~GPIOx_CTRL_OEOVER_MASK;
sys/arch/arm64/dev/rpigpio.c
336
val |= GPIOx_CTRL_OEOVER_NRMFUNC;
sys/arch/arm64/dev/rpigpio.c
337
val &= ~GPIOx_CTRL_OUTOVER_MASK;
sys/arch/arm64/dev/rpigpio.c
338
val |= GPIOx_CTRL_OUTOVER_NRMFUNC;
sys/arch/arm64/dev/rpigpio.c
341
bank->gpio + GPIOx_CTRL(pin), val);
sys/arch/arm64/dev/rpigpio.c
350
uint32_t val;
sys/arch/arm64/dev/rpigpio.c
358
val = bus_space_read_4(sc->sc_iot, sc->sc_rio_ioh, bank->rio + RIO_OE);
sys/arch/arm64/dev/rpigpio.c
360
val |= 1 << pin;
sys/arch/arm64/dev/rpigpio.c
362
val &= ~(1 << pin);
sys/arch/arm64/dev/rpigpio.c
363
bus_space_write_4(sc->sc_iot, sc->sc_rio_ioh, bank->rio + RIO_OE, val);
sys/arch/arm64/dev/rpigpio.c
366
val = bus_space_read_4(sc->sc_iot, sc->sc_pads_ioh, bank->pads +
sys/arch/arm64/dev/rpigpio.c
368
val &= ~PAD_CTRL_OUT_DIS;
sys/arch/arm64/dev/rpigpio.c
369
val |= PAD_CTRL_IN_EN;
sys/arch/arm64/dev/rpigpio.c
371
PAD_CTRL(pin), val);
sys/arch/arm64/dev/rpigpio.c
374
val = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, bank->gpio +
sys/arch/arm64/dev/rpigpio.c
376
val &= ~(GPIOx_CTRL_FUNCSEL_MASK | GPIOx_CTRL_OUTOVER_MASK |
sys/arch/arm64/dev/rpigpio.c
378
val |= (GPIOx_CTRL_FUNCSEL_GPIO | GPIOx_CTRL_OUTOVER_NRMFUNC |
sys/arch/arm64/dev/rpigpio.c
381
GPIOx_CTRL(pin), val);
sys/arch/arm64/dev/rpigpio.c
392
int val;
sys/arch/arm64/dev/rpigpio.c
401
val = (reg >> pin) & 1;
sys/arch/arm64/dev/rpigpio.c
403
val = !val;
sys/arch/arm64/dev/rpigpio.c
404
return val;
sys/arch/arm64/dev/rpigpio.c
408
rpigpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/arm64/dev/rpigpio.c
423
val = !val;
sys/arch/arm64/dev/rpigpio.c
424
if (val)
sys/arch/arm64/dev/rpipwm.c
34
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/rpipwm.c
35
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/smmu.c
1958
smmu_v3_write_4(struct smmu_softc *sc, bus_size_t off, uint32_t val)
sys/arch/arm64/dev/smmu.c
1960
bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
sys/arch/arm64/dev/smmu.c
1970
smmu_v3_write_8(struct smmu_softc *sc, bus_size_t off, uint64_t val)
sys/arch/arm64/dev/smmu.c
1972
bus_space_write_8(sc->sc_iot, sc->sc_ioh, off, val);
sys/arch/arm64/dev/smmu.c
1977
uint32_t val)
sys/arch/arm64/dev/smmu.c
1981
smmu_v3_write_4(sc, off, val);
sys/arch/arm64/dev/smmu.c
1984
if (smmu_v3_read_4(sc, ack_off) == val)
sys/arch/arm64/dev/smmu.c
472
smmu_gr0_write_4(struct smmu_softc *sc, bus_size_t off, uint32_t val)
sys/arch/arm64/dev/smmu.c
476
bus_space_write_4(sc->sc_iot, sc->sc_ioh, base + off, val);
sys/arch/arm64/dev/smmu.c
488
smmu_gr1_write_4(struct smmu_softc *sc, bus_size_t off, uint32_t val)
sys/arch/arm64/dev/smmu.c
492
bus_space_write_4(sc->sc_iot, sc->sc_ioh, base + off, val);
sys/arch/arm64/dev/smmu.c
507
smmu_cb_write_4(struct smmu_softc *sc, int idx, bus_size_t off, uint32_t val)
sys/arch/arm64/dev/smmu.c
514
bus_space_write_4(sc->sc_iot, sc->sc_ioh, base + off, val);
sys/arch/arm64/dev/smmu.c
537
smmu_cb_write_8(struct smmu_softc *sc, int idx, bus_size_t off, uint64_t val)
sys/arch/arm64/dev/smmu.c
546
val >> 32);
sys/arch/arm64/dev/smmu.c
548
val & 0xffffffff);
sys/arch/arm64/dev/smmu.c
552
bus_space_write_8(sc->sc_iot, sc->sc_ioh, base + off, val);
sys/arch/arm64/include/_types.h
39
long val[13];
sys/arch/arm64/include/armreg.h
40
({ uint64_t val; \
sys/arch/arm64/include/armreg.h
41
__asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
sys/arch/arm64/include/armreg.h
42
val; \
sys/arch/arm64/include/armreg.h
44
#define WRITE_SPECIALREG(reg, val) \
sys/arch/arm64/include/armreg.h
45
__asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
sys/arch/arm64/include/cpu.h
249
uint64_t val, rval;
sys/arch/arm64/include/cpu.h
252
: "=r" (val), "=r" (rval));
sys/arch/arm64/include/cpu.h
254
return (val ^ rval);
sys/arch/armv7/armv7/intr.c
348
void *val = NULL;
sys/arch/armv7/armv7/intr.c
401
val = ic->ic_establish(ic->ic_cookie, cell, level,
sys/arch/armv7/armv7/intr.c
412
if (val == NULL)
sys/arch/armv7/armv7/intr.c
417
ih->ih_ih = val;
sys/arch/armv7/armv7/intr.c
439
void *val = NULL;
sys/arch/armv7/armv7/intr.c
473
val = ic->ic_establish(ic->ic_cookie, &cell[5 + acells],
sys/arch/armv7/armv7/intr.c
482
if (val == NULL) {
sys/arch/armv7/armv7/intr.c
489
ih->ih_ih = val;
sys/arch/armv7/armv7/intr.c
511
void *val = NULL;
sys/arch/armv7/armv7/intr.c
522
val = ic->ic_establish_msi(ic->ic_cookie, addr, data,
sys/arch/armv7/armv7/intr.c
524
if (val == NULL)
sys/arch/armv7/armv7/intr.c
529
ih->ih_ih = val;
sys/arch/armv7/armv7/intr.c
576
void *val;
sys/arch/armv7/armv7/intr.c
586
val = ic->ic_establish(ic->ic_cookie, cell, level, ci, func, arg, name);
sys/arch/armv7/armv7/intr.c
587
if (val == NULL)
sys/arch/armv7/armv7/intr.c
592
ih->ih_ih = val;
sys/arch/armv7/armv7/platform.c
76
uint32_t op, uint32_t val)
sys/arch/armv7/armv7/platform.c
79
platform->smc_write(iot, ioh, off, op, val);
sys/arch/armv7/armv7/platform.c
81
bus_space_write_4(iot, ioh, off, val);
sys/arch/armv7/exynos/ec_commands.h
1123
uint8_t val;
sys/arch/armv7/exynos/ec_commands.h
1133
uint8_t val;
sys/arch/armv7/exynos/exclock.c
58
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/exclock.c
59
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/exehci.c
222
uint32_t val;
sys/arch/armv7/exynos/exehci.c
236
val = regmap_read_4(sysrm, USB20PHY_CFG);
sys/arch/armv7/exynos/exehci.c
237
val |= USB20PHY_CFG_HOST_LINK_EN;
sys/arch/armv7/exynos/exehci.c
238
regmap_write_4(sysrm, USB20PHY_CFG, val);
sys/arch/armv7/exynos/exehci.c
251
val = regmap_read_4(pmurm, offset);
sys/arch/armv7/exynos/exehci.c
252
val |= USB_HOST_POWER_EN;
sys/arch/armv7/exynos/exehci.c
253
regmap_write_4(pmurm, offset, val);
sys/arch/armv7/exynos/exehci.c
259
val = bus_space_read_4(sc->sc.iot, sc->ph_ioh, USBPHY_CTRL0);
sys/arch/armv7/exynos/exehci.c
260
val &= ~(HOST_CTRL0_FSEL_MASK |
sys/arch/armv7/exynos/exehci.c
267
val |= (/* Setting up the ref freq */
sys/arch/armv7/exynos/exehci.c
273
bus_space_write_4(sc->sc.iot, sc->ph_ioh, USBPHY_CTRL0, val);
sys/arch/armv7/exynos/exehci.c
297
val = bus_space_read_4(sc->sc.iot, sc->ph_ioh, HSICPHY_CTRL1);
sys/arch/armv7/exynos/exehci.c
298
val &= ~(HOST_CTRL0_SIDDQ |
sys/arch/armv7/exynos/exehci.c
301
bus_space_write_4(sc->sc.iot, sc->ph_ioh, HSICPHY_CTRL1, val);
sys/arch/armv7/exynos/exehci.c
302
val |= HOST_CTRL0_PHYSWRST;
sys/arch/armv7/exynos/exehci.c
303
bus_space_write_4(sc->sc.iot, sc->ph_ioh, HSICPHY_CTRL1, val);
sys/arch/armv7/exynos/exehci.c
305
val &= ~HOST_CTRL0_PHYSWRST;
sys/arch/armv7/exynos/exehci.c
306
bus_space_write_4(sc->sc.iot, sc->ph_ioh, HSICPHY_CTRL1, val);
sys/arch/armv7/exynos/exgpio.c
211
uint32_t func, val, pud, drv;
sys/arch/armv7/exynos/exgpio.c
229
val = OF_getpropint(node, "samsung,pin-val", 0);
sys/arch/armv7/exynos/exgpio.c
253
if (val)
sys/arch/armv7/exynos/exgpio.c
285
uint32_t val;
sys/arch/armv7/exynos/exgpio.c
292
val = HREAD4(ec->ec_sc, GPXCON(ec->ec_bank->addr));
sys/arch/armv7/exynos/exgpio.c
293
val &= ~(0xf << (pin * 4));
sys/arch/armv7/exynos/exgpio.c
294
val |= (func << (pin * 4));
sys/arch/armv7/exynos/exgpio.c
295
HWRITE4(ec->ec_sc, GPXCON(ec->ec_bank->addr), val);
sys/arch/armv7/exynos/exgpio.c
305
int val;
sys/arch/armv7/exynos/exgpio.c
312
val = (reg >> pin) & 1;
sys/arch/armv7/exynos/exgpio.c
314
val = !val;
sys/arch/armv7/exynos/exgpio.c
315
return val;
sys/arch/armv7/exynos/exgpio.c
319
exgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/armv7/exynos/exgpio.c
331
val = !val;
sys/arch/armv7/exynos/exgpio.c
332
if (val)
sys/arch/armv7/exynos/exgpio.c
44
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/exgpio.c
45
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/exiic.c
95
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/exiic.c
96
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/expower.c
33
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/expower.c
34
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/tps65090.c
151
uint8_t val, check;
sys/arch/armv7/exynos/tps65090.c
153
val = REG_FETx_CTRL_ADENFET | REG_FETx_CTRL_WAIT;
sys/arch/armv7/exynos/tps65090.c
155
val |= REG_FETx_CTRL_ENFET;
sys/arch/armv7/exynos/tps65090.c
157
tps65090_write_reg(sc, REG_FETx_CTRL(fet), val);
sys/arch/armv7/exynos/tps65090.c
179
uint8_t val = tps65090_read_reg(sc, REG_FETx_CTRL(fet));
sys/arch/armv7/exynos/tps65090.c
180
return val & REG_FETx_CTRL_ENFET;
sys/arch/armv7/exynos/tps65090.c
187
uint8_t val = tps65090_read_reg(sc, REG_CG_CTRL0);
sys/arch/armv7/exynos/tps65090.c
188
return val & REG_CG_CTRL0_ENC_MASK;
sys/arch/armv7/exynos/tps65090.c
195
uint8_t val = tps65090_read_reg(sc, REG_CG_CTRL0);
sys/arch/armv7/exynos/tps65090.c
197
val |= REG_CG_CTRL0_ENC_MASK;
sys/arch/armv7/exynos/tps65090.c
199
val &= REG_CG_CTRL0_ENC_MASK;
sys/arch/armv7/exynos/tps65090.c
200
tps65090_write_reg(sc, REG_CG_CTRL0, val);
sys/arch/armv7/exynos/tps65090.c
206
uint8_t val;
sys/arch/armv7/exynos/tps65090.c
210
sc->sc_addr, &cmd, 1, &val, 1, 0);
sys/arch/armv7/exynos/tps65090.c
213
return val;
sys/arch/armv7/exynos/tps65090.c
217
tps65090_write_reg(struct tps65090_softc *sc, uint8_t cmd, uint8_t val)
sys/arch/armv7/exynos/tps65090.c
221
sc->sc_addr, &cmd, 1, &val, 1, 0);
sys/arch/armv7/imx/imxtemp.c
63
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/imx/imxtemp.c
64
regmap_write_4((sc)->sc_rm, (reg), (val))
sys/arch/armv7/marvell/mvacc.c
36
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvacc.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvagc.c
30
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvagc.c
31
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvahci.c
37
#define MVAHCI_WRITE(sc, reg, val) \
sys/arch/armv7/marvell/mvahci.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvodog.c
35
#define HWRITE4(sc, ioh, reg, val) \
sys/arch/armv7/marvell/mvodog.c
36
bus_space_write_4((sc)->sc_iot, (ioh), (reg), (val))
sys/arch/armv7/marvell/mvortc.c
164
mvortc_write(struct mvortc_softc *sc, int reg, uint32_t val)
sys/arch/armv7/marvell/mvortc.c
168
HWRITE4(sc, reg, val);
sys/arch/armv7/marvell/mvortc.c
47
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvortc.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvpcie.c
79
#define HWRITE4(po, reg, val) \
sys/arch/armv7/marvell/mvpcie.c
80
bus_space_write_4((po)->po_iot, (po)->po_ioh, (reg), (val))
sys/arch/armv7/marvell/mvpxa.c
38
#define MVPXA_WRITE(sc, reg, val) \
sys/arch/armv7/marvell/mvpxa.c
39
bus_space_write_4((sc)->sc_iot, (sc)->mbus_ioh, (reg), (val))
sys/arch/armv7/marvell/mvsysctrl.c
35
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvsysctrl.c
36
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvxhci.c
40
#define MVXHCI_WRITE(sc, reg, val) \
sys/arch/armv7/marvell/mvxhci.c
41
bus_space_write_4((sc)->sc.iot, (sc)->mbus_ioh, (reg), (val))
sys/arch/armv7/omap/amdisplay.c
56
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/amdisplay.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/edma.c
74
#define TPCC_WRITE_4(sc, reg, val) \
sys/arch/armv7/omap/edma.c
75
(bus_space_write_4((sc)->sc_iot, (sc)->sc_tpcc, (reg), (val)))
sys/arch/armv7/omap/edma.c
76
#define TPCC_SET(sc, reg, val) \
sys/arch/armv7/omap/edma.c
77
(TPCC_WRITE_4((sc), (reg), (TPCC_READ_4(sc, reg) | (val))))
sys/arch/armv7/omap/edma.c
78
#define TPCC_FILTSET(sc, reg, val, filt) \
sys/arch/armv7/omap/edma.c
79
(TPCC_WRITE_4((sc), (reg), (TPCC_READ_4(sc, reg) & (filt)) | (val)))
sys/arch/armv7/omap/if_cpsw.c
719
cpsw_mii_writereg(struct device *dev, int phy, int reg, int val)
sys/arch/armv7/omap/if_cpsw.c
724
KASSERT((val & 0xffff0000UL) == 0);
sys/arch/armv7/omap/if_cpsw.c
730
((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val);
sys/arch/armv7/omap/nxphdmi.c
413
nxphdmi_cec_write(struct nxphdmi_softc *sc, uint8_t addr, uint8_t val)
sys/arch/armv7/omap/nxphdmi.c
416
uint8_t sendbuf[] = { addr, val };
sys/arch/armv7/omap/nxphdmi.c
422
DEVNAME(sc), val, addr, ret));
sys/arch/armv7/omap/nxphdmi.c
426
DPRINTF(3,("%s: (CEC) wrote 0x%02x to 0x%02x\n", DEVNAME(sc), val,
sys/arch/armv7/omap/nxphdmi.c
454
nxphdmi_write(struct nxphdmi_softc *sc, uint16_t reg, uint8_t val)
sys/arch/armv7/omap/nxphdmi.c
457
uint8_t sendbuf[] = { REGADDR(reg), val };
sys/arch/armv7/omap/nxphdmi.c
465
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg), ret));
sys/arch/armv7/omap/nxphdmi.c
470
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg)));
sys/arch/armv7/omap/nxphdmi.c
476
nxphdmi_write2(struct nxphdmi_softc *sc, uint16_t reg, uint16_t val)
sys/arch/armv7/omap/nxphdmi.c
479
uint8_t sendbuf[] = { REGADDR(reg), val >> 8, val & 0xff };
sys/arch/armv7/omap/nxphdmi.c
487
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg), ret));
sys/arch/armv7/omap/nxphdmi.c
492
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg)));
sys/arch/armv7/omap/omap_machdep.c
34
bus_size_t off, uint32_t op, uint32_t val)
sys/arch/armv7/omap/omap_machdep.c
44
omap4_smc_call(op, val);
sys/arch/armv7/omap/omclock.c
40
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/omclock.c
41
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/omgpio.c
189
#define WRITE4(sc, reg, val) omgpio_write4(sc, reg, val)
sys/arch/armv7/omap/omgpio.c
229
omgpio_write4(struct omgpio_softc *sc, u_int32_t reg, u_int32_t val)
sys/arch/armv7/omap/omgpio.c
234
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val));
sys/arch/armv7/omap/omgpio.c
423
int val;
sys/arch/armv7/omap/omgpio.c
428
val = omgpio_pin_read(sc, pin);
sys/arch/armv7/omap/omgpio.c
430
val = !val;
sys/arch/armv7/omap/omgpio.c
431
return val;
sys/arch/armv7/omap/omgpio.c
435
omgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/armv7/omap/omgpio.c
445
val = !val;
sys/arch/armv7/omap/omgpio.c
446
omgpio_pin_write(sc, pin, val);
sys/arch/armv7/omap/ommmc.c
223
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/ommmc.c
224
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/ommmc.c
602
int inverted, val;
sys/arch/armv7/omap/ommmc.c
604
val = gpio_controller_get_pin(sc->sc_gpio);
sys/arch/armv7/omap/ommmc.c
607
return inverted ? !val : val;
sys/arch/armv7/omap/omrng.c
57
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/omrng.c
58
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/omusbtll.c
139
uint32_t val;
sys/arch/armv7/omap/omusbtll.c
144
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/arch/armv7/omap/omusbtll.c
146
val &= ~(USBTLL_CHANNEL_CONF_ULPINOBITSTUFF |
sys/arch/armv7/omap/omusbtll.c
150
USBTLL_CHANNEL_CONF_(i), val);
sys/arch/armv7/omap/omusbtll.c
153
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, USBTLL_SHARED_CONF);
sys/arch/armv7/omap/omusbtll.c
154
val |= (USBTLL_SHARED_CONF_USB_180D_SDR_EN |
sys/arch/armv7/omap/omusbtll.c
157
val &= ~(USBTLL_SHARED_CONF_USB_90D_DDR_EN);
sys/arch/armv7/omap/omusbtll.c
158
bus_space_write_4(sc->sc_iot, sc->sc_ioh, USBTLL_SHARED_CONF, val);
sys/arch/armv7/omap/omusbtll.c
162
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/arch/armv7/omap/omusbtll.c
165
val |= USBTLL_CHANNEL_CONF_CHANEN;
sys/arch/armv7/omap/omusbtll.c
167
USBTLL_CHANNEL_CONF_(i), val);
sys/arch/armv7/omap/prcm.c
571
uint32_t val;
sys/arch/armv7/omap/prcm.c
578
val = ((120 & 0x7ff) << 8) | ((SYS_CLK - 1) & 0x7f);
sys/arch/armv7/omap/prcm.c
579
bus_space_write_4(sc->sc_iot, sc->sc_prcm, CM_CLKSEL4_PLL, val);
sys/arch/armv7/omap/prcm.c
582
bus_space_write_4(sc->sc_iot, sc->sc_prcm, CM_CLKSEL5_PLL, val);
sys/arch/armv7/omap/prcm.c
589
val = (7 << 4) | (7 << 0);
sys/arch/armv7/omap/prcm.c
590
bus_space_write_4(sc->sc_iot, sc->sc_prcm, CM_CLKEN2_PLL, val);
sys/arch/armv7/omap/prcm.c
596
while ((val = bus_space_read_4(sc->sc_iot, sc->sc_prcm,
sys/arch/armv7/omap/prcm.c
599
printf("CM_IDLEST_PLL = 0x%08x\n", val);
sys/arch/armv7/omap/ti_iic.c
114
#define I2C_WRITE_REG(sc, reg, val) \
sys/arch/armv7/omap/ti_iic.c
115
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/ti_iic.c
116
#define I2C_WRITE_DATA(sc, val) \
sys/arch/armv7/omap/ti_iic.c
117
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA, (val))
sys/arch/armv7/omap/ti_iic.c
527
ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags)
sys/arch/armv7/omap/ti_iic.c
531
DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags));
sys/arch/armv7/omap/ti_iic.c
533
while (((v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW)) & mask) != val) {
sys/arch/armv7/omap/ti_iic.c
537
DEVNAME(sc), mask, val, v);
sys/arch/armv7/stand/efiboot/exec.c
53
uint32_t val;
sys/arch/armv7/stand/efiboot/exec.c
78
val = (way << wshift) | (set << sshift) |
sys/arch/armv7/stand/efiboot/exec.c
81
:: "r"(val));
sys/arch/armv7/sunxi/sxie.c
712
sxie_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/arch/armv7/sunxi/sxie.c
730
SXIWRITE4(sc, SXIE_MACMWTD, val);
sys/arch/armv7/vexpress/pciecam.c
51
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/vexpress/pciecam.c
52
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/xilinx/zqclock.c
156
uint32_t reg, val;
sys/arch/armv7/xilinx/zqclock.c
170
val = zynq_slcr_read(sc->sc_rm, reg);
sys/arch/armv7/xilinx/zqclock.c
171
return sc->sc_psclk_freq * ((val >> SLCR_PLL_CTRL_FDIV_SHIFT) &
sys/arch/armv7/xilinx/zqreset.c
105
zynq_slcr_write(struct regmap *rm, uint32_t reg, uint32_t val)
sys/arch/armv7/xilinx/zqreset.c
110
regmap_write_4(rm, reg, val);
sys/arch/hppa/dev/apic.c
81
u_int32_t val);
sys/arch/hppa/dev/apic.c
85
apic_write(volatile struct elroy_regs *r, u_int32_t reg, u_int32_t val)
sys/arch/hppa/dev/apic.c
88
elroy_write32(&r->apic_data, htole32(val));
sys/arch/hppa/gsc/gsckbc.c
442
pckbc_send_cmd(bus_space_tag_t iot, bus_space_handle_t ioh, u_char val)
sys/arch/hppa/gsc/gsckbc.c
446
bus_space_write_1(iot, ioh, KBOUTP, val);
sys/arch/hppa/gsc/gsckbc.c
472
pckbc_send_devcmd(struct pckbc_internal *t, pckbc_slot_t slot, u_char val)
sys/arch/hppa/gsc/gsckbc.c
474
return pckbc_send_cmd(t->t_iot, t->t_ioh_d, val);
sys/arch/hppa/gsc/harmony.c
1054
u_int32_t bits, mask, val, old;
sys/arch/hppa/gsc/harmony.c
1067
val = mask - (sc->sc_output_lvl.left >> (8 - GAINCTL_OUTPUT_BITS));
sys/arch/hppa/gsc/harmony.c
1068
bits |= (val << GAINCTL_OUTPUT_LEFT_S) & GAINCTL_OUTPUT_LEFT_M;
sys/arch/hppa/gsc/harmony.c
1069
val = mask - (sc->sc_output_lvl.right >> (8 - GAINCTL_OUTPUT_BITS));
sys/arch/hppa/gsc/harmony.c
1070
bits |= (val << GAINCTL_OUTPUT_RIGHT_S) & GAINCTL_OUTPUT_RIGHT_M;
sys/arch/hppa/gsc/harmony.c
1074
val = mask - (sc->sc_monitor_lvl.left >> (8 - GAINCTL_MONITOR_BITS));
sys/arch/hppa/gsc/harmony.c
1075
bits |= (val << GAINCTL_MONITOR_S) & GAINCTL_MONITOR_M;
sys/arch/hppa/gsc/harmonyvar.h
110
#define WRITE_REG(sc, reg, val) \
sys/arch/hppa/gsc/harmonyvar.h
111
bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, (reg), (val))
sys/arch/hppa/include/_types.h
40
long val[19];
sys/arch/hppa/include/tcb.h
38
void *val;
sys/arch/hppa/include/tcb.h
39
__asm__ ("mfctl %%cr27, %0" : "=r" (val));
sys/arch/hppa/include/tcb.h
40
return val;
sys/arch/i386/i386/amd64errata.c
263
uint64_t val;
sys/arch/i386/i386/amd64errata.c
267
val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
sys/arch/i386/i386/amd64errata.c
268
if ((val & e->e_data2) != 0)
sys/arch/i386/i386/amd64errata.c
278
uint64_t val;
sys/arch/i386/i386/amd64errata.c
282
val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
sys/arch/i386/i386/amd64errata.c
283
if ((val & e->e_data2) != 0)
sys/arch/i386/i386/amd64errata.c
286
wrmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE, val | e->e_data2);
sys/arch/i386/i386/amd64errata.c
290
val = rdmsr_locked(e->e_data1, OPTERON_MSR_PASSCODE);
sys/arch/i386/i386/amd64errata.c
291
if ((val & e->e_data2) != 0)
sys/arch/i386/i386/amdmsr.c
132
req->val = rdmsr(req->addr);
sys/arch/i386/i386/amdmsr.c
135
wrmsr(req->addr, req->val);
sys/arch/i386/i386/esm.c
364
struct esm_smb_resp_val *val = &resp.resp_val;
sys/arch/i386/i386/esm.c
397
es->es_sensor->value = esm_val2temp(val->v_reading);
sys/arch/i386/i386/esm.c
400
es->es_sensor->value = esm_val2volts(val->v_reading);
sys/arch/i386/i386/esm.c
404
esm_val2volts(val->v_reading) * 10;
sys/arch/i386/i386/esm.c
407
es->es_sensor->value = esm_val2amps(val->v_reading);
sys/arch/i386/i386/esm.c
412
(val->v_reading >> i * 8) & 0xf;
sys/arch/i386/i386/esm.c
418
(val->v_reading >> i) & 0x1;
sys/arch/i386/i386/esm.c
422
es->es_sensor->value = val->v_reading;
sys/arch/i386/i386/esm.c
431
if (val->v_reading >= es->es_thresholds.th_hi_crit ||
sys/arch/i386/i386/esm.c
432
val->v_reading <= es->es_thresholds.th_lo_crit) {
sys/arch/i386/i386/esm.c
437
if (val->v_reading >= es->es_thresholds.th_hi_warn ||
sys/arch/i386/i386/esm.c
438
val->v_reading <= es->es_thresholds.th_lo_warn) {
sys/arch/i386/i386/esm.c
447
if (val->v_status & ESM2_VS_PSU_FAIL) {
sys/arch/i386/i386/esm.c
834
struct esm_smb_resp_val *val = &resp.resp_val;
sys/arch/i386/i386/esm.c
858
val->v_reading, val->v_status, val->v_checksum);
sys/arch/i386/i386/esm.c
862
if (val->v_status == 0x00)
sys/arch/i386/i386/esm.c
866
if (!(val->v_status & ESM2_VS_VALID))
sys/arch/i386/i386/esm.c
987
esm_bmc_ready(struct esm_softc *sc, int port, u_int8_t mask, u_int8_t val,
sys/arch/i386/i386/esm.c
993
if ((EREAD(sc, port) & mask) == val)
sys/arch/i386/i386/i686_mem.c
108
mtrr2mrt(int val)
sys/arch/i386/i386/i686_mem.c
110
if (val < 0 || val >= nitems(mtrrtomrt))
sys/arch/i386/i386/i686_mem.c
112
return mtrrtomrt[val];
sys/arch/i386/i386/i686_mem.c
260
int val;
sys/arch/i386/i386/i686_mem.c
262
val = mtrrtype(flags);
sys/arch/i386/i386/i686_mem.c
264
return val & 0xff;
sys/arch/i386/i386/i686_mem.c
85
int mtrr2mrt(int val);
sys/arch/i386/i386/ioapic.c
139
u_int32_t val;
sys/arch/i386/i386/ioapic.c
142
val = *sc->sc_data;
sys/arch/i386/i386/ioapic.c
144
return (val);
sys/arch/i386/i386/ioapic.c
148
ioapic_write_ul(struct ioapic_softc *sc,int regid, u_int32_t val)
sys/arch/i386/i386/ioapic.c
151
*(sc->sc_data) = val;
sys/arch/i386/i386/ioapic.c
157
u_int32_t val;
sys/arch/i386/i386/ioapic.c
161
val = ioapic_read_ul(sc, regid);
sys/arch/i386/i386/ioapic.c
163
return val;
sys/arch/i386/i386/ioapic.c
167
ioapic_write(struct ioapic_softc *sc,int regid, int val)
sys/arch/i386/i386/ioapic.c
172
ioapic_write_ul(sc, regid, val);
sys/arch/i386/i386/machdep.c
1100
unsigned int val;
sys/arch/i386/i386/machdep.c
1120
val = regs[3];
sys/arch/i386/i386/machdep.c
1121
if (val & (1U << 31)) {
sys/arch/i386/i386/machdep.c
1164
val = regs[0];
sys/arch/i386/i386/machdep.c
1165
if (val >= 0xC0000001) {
sys/arch/i386/i386/machdep.c
1167
val = regs[3];
sys/arch/i386/i386/machdep.c
1169
val = 0;
sys/arch/i386/i386/machdep.c
1171
if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
sys/arch/i386/i386/machdep.c
1175
if (val & C3_CPUID_HAS_RNG) {
sys/arch/i386/i386/machdep.c
1178
if (!(val & C3_CPUID_DO_RNG)) {
sys/arch/i386/i386/machdep.c
1188
if (val & C3_CPUID_HAS_ACE) {
sys/arch/i386/i386/machdep.c
1190
if (!(val & C3_CPUID_DO_ACE)) {
sys/arch/i386/i386/machdep.c
1201
if (val & C3_CPUID_HAS_ACE2) {
sys/arch/i386/i386/machdep.c
1203
if (!(val & C3_CPUID_DO_ACE2)) {
sys/arch/i386/i386/machdep.c
1214
if (val & C3_CPUID_HAS_PHE) {
sys/arch/i386/i386/machdep.c
1216
if (!(val & C3_CPUID_DO_PHE)) {
sys/arch/i386/i386/machdep.c
1227
if (val & C3_CPUID_HAS_PMM) {
sys/arch/i386/i386/machdep.c
1229
if (!(val & C3_CPUID_DO_PMM)) {
sys/arch/i386/i386/machdep.c
1990
uint32_t dummy, val;
sys/arch/i386/i386/machdep.c
1992
CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy);
sys/arch/i386/i386/machdep.c
1994
if (val & cpu_xsave_extfeatures[i].feature_bit)
sys/arch/i386/i386/powernow-k8.c
191
u_int val;
sys/arch/i386/i386/powernow-k8.c
214
val = cvid - (1 << cstate->mvs);
sys/arch/i386/i386/powernow-k8.c
215
WRITE_FIDVID(cfid, (val > 0) ? val : 0, 1ULL);
sys/arch/i386/i386/powernow-k8.c
244
val = cfid + 2;
sys/arch/i386/i386/powernow-k8.c
246
val = FID_TO_VCO_FID(cfid) + 2;
sys/arch/i386/i386/powernow-k8.c
248
val = cfid - 2;
sys/arch/i386/i386/powernow-k8.c
249
WRITE_FIDVID(val, cvid, (uint64_t)cstate->pll * 1000 / 5);
sys/arch/i386/include/_types.h
56
long val[6];
sys/arch/i386/include/amdmsr.h
24
u_int64_t val; /* 64-bit MSR value */
sys/arch/i386/include/atomic.h
274
i386_atomic_testset_uq(volatile u_int64_t *ptr, u_int64_t val)
sys/arch/i386/include/atomic.h
276
__asm__ volatile ("\n1:\t" _LOCK " cmpxchg8b (%1); jnz 1b" : "+A" (val) :
sys/arch/i386/include/atomic.h
277
"r" (ptr), "b" ((u_int32_t)val), "c" ((u_int32_t)(val >> 32)));
sys/arch/i386/include/atomic.h
278
return val;
sys/arch/i386/include/atomic.h
282
i386_atomic_testset_ul(volatile u_int32_t *ptr, unsigned long val)
sys/arch/i386/include/atomic.h
284
__asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
sys/arch/i386/include/atomic.h
285
return val;
sys/arch/i386/include/atomic.h
289
i386_atomic_testset_i(volatile int *ptr, unsigned long val)
sys/arch/i386/include/atomic.h
291
__asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
sys/arch/i386/include/atomic.h
292
return val;
sys/arch/i386/include/cpufunc.h
101
u_int val;
sys/arch/i386/include/cpufunc.h
102
__asm volatile("movl %%cr0,%0" : "=r" (val));
sys/arch/i386/include/cpufunc.h
103
return val;
sys/arch/i386/include/cpufunc.h
109
u_int val;
sys/arch/i386/include/cpufunc.h
110
__asm volatile("movl %%cr2,%0" : "=r" (val));
sys/arch/i386/include/cpufunc.h
111
return val;
sys/arch/i386/include/cpufunc.h
115
lcr3(u_int val)
sys/arch/i386/include/cpufunc.h
117
__asm volatile("movl %0,%%cr3" : : "r" (val));
sys/arch/i386/include/cpufunc.h
123
u_int val;
sys/arch/i386/include/cpufunc.h
124
__asm volatile("movl %%cr3,%0" : "=r" (val));
sys/arch/i386/include/cpufunc.h
125
return val;
sys/arch/i386/include/cpufunc.h
129
lcr4(u_int val)
sys/arch/i386/include/cpufunc.h
131
__asm volatile("movl %0,%%cr4" : : "r" (val));
sys/arch/i386/include/cpufunc.h
137
u_int val;
sys/arch/i386/include/cpufunc.h
138
__asm volatile("movl %%cr4,%0" : "=r" (val));
sys/arch/i386/include/cpufunc.h
139
return val;
sys/arch/i386/include/cpufunc.h
145
u_int val;
sys/arch/i386/include/cpufunc.h
146
__asm volatile("movl %%cr3,%0" : "=r" (val));
sys/arch/i386/include/cpufunc.h
147
__asm volatile("movl %0,%%cr3" : : "r" (val));
sys/arch/i386/include/cpufunc.h
93
lcr0(u_int val)
sys/arch/i386/include/cpufunc.h
95
__asm volatile("movl %0,%%cr0" : : "r" (val));
sys/arch/i386/include/i82489var.h
51
i82489_writereg(int reg, u_int32_t val)
sys/arch/i386/include/i82489var.h
54
val;
sys/arch/i386/include/i82489var.h
61
val = *((volatile u_int32_t *)(((volatile u_int8_t *)local_apic) +
sys/arch/i386/include/tcb.h
40
void *val;
sys/arch/i386/include/tcb.h
41
__asm__ ("movl %%gs:(%1),%0" : "=r" (val) : "r" (offset));
sys/arch/i386/include/tcb.h
42
return val;
sys/arch/i386/pci/ali1543.c
181
int val;
sys/arch/i386/pci/ali1543.c
190
val = ALI1543_PIRQ(reg, clink);
sys/arch/i386/pci/ali1543.c
191
*irqp = (val == 0) ?
sys/arch/i386/pci/ali1543.c
192
I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
sys/arch/i386/pci/ali1543.c
201
int shift, val;
sys/arch/i386/pci/ali1543.c
208
ali1543_get_intr(v, clink, &val);
sys/arch/i386/pci/ali1543.c
213
if (ali1543_get_intr(v, clink, &val) != 0 || val != irq)
sys/arch/i386/pci/amd756.c
139
int val;
sys/arch/i386/pci/amd756.c
145
val = (reg >> (4*clink)) & 0x0f;
sys/arch/i386/pci/amd756.c
146
*irqp = (val == 0) ?
sys/arch/i386/pci/amd756.c
147
I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
sys/arch/i386/pci/amd756.c
156
int val;
sys/arch/i386/pci/amd756.c
163
amd756_get_intr(v, clink, &val);
sys/arch/i386/pci/gscpmreg.h
31
#define GSCPM_P_CNT_CLK(val) ((val) & 0x7)
sys/arch/i386/pci/opti82c558.c
152
int val;
sys/arch/i386/pci/opti82c558.c
158
val = VIPER_PIRQ(reg, clink);
sys/arch/i386/pci/opti82c558.c
159
*irqp = (val == VIPER_PIRQ_NONE) ? 0xff : viper_pirq_decode[val];
sys/arch/i386/pci/opti82c700.c
194
int val, addrofs, ofs;
sys/arch/i386/pci/opti82c700.c
200
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
202
*irqp = (val == FIRESTAR_PIRQ_NONE) ?
sys/arch/i386/pci/opti82c700.c
203
I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
sys/arch/i386/pci/opti82c700.c
233
int i, val, addrofs, ofs;
sys/arch/i386/pci/opti82c700.c
249
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
250
if (val != irq)
sys/arch/i386/pci/opti82c700.c
252
val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) &
sys/arch/i386/pci/opti82c700.c
254
*triggerp = val ? IST_LEVEL : IST_EDGE;
sys/arch/i386/pci/opti82c700.c
265
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
266
if (val != irq)
sys/arch/i386/pci/opti82c700.c
279
int i, val, addrofs, ofs;
sys/arch/i386/pci/opti82c700.c
294
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
295
if (val != irq)
sys/arch/i386/pci/opti82c700.c
314
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
315
if (val != irq)
sys/arch/i386/pci/pci_addr_fixup.c
182
pcireg_t val, mask;
sys/arch/i386/pci/pci_addr_fixup.c
187
val = pci_conf_read(pc, tag, PCI_BHLC_REG);
sys/arch/i386/pci/pci_addr_fixup.c
188
switch (PCI_HDRTYPE_TYPE(val)) {
sys/arch/i386/pci/pci_addr_fixup.c
191
PCI_HDRTYPE_TYPE(val));
sys/arch/i386/pci/pci_addr_fixup.c
211
val = pci_conf_read(pc, tag, mapreg);
sys/arch/i386/pci/pci_addr_fixup.c
215
pci_conf_write(pc, tag, mapreg, val);
sys/arch/i386/pci/pci_addr_fixup.c
217
type = PCI_MAPREG_TYPE(val);
sys/arch/i386/pci/pci_addr_fixup.c
220
if (PCI_MAPREG_MEM_TYPE(val) ==
sys/arch/i386/pci/pci_addr_fixup.c
233
addr = PCI_MAPREG_MEM_ADDR(val);
sys/arch/i386/pci/pci_addr_fixup.c
238
addr = PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END;
sys/arch/i386/pci/pci_addr_fixup.c
311
pcireg_t val;
sys/arch/i386/pci/pci_addr_fixup.c
317
val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
sys/arch/i386/pci/pci_addr_fixup.c
319
(val & PCI_COMMAND_MEM_ENABLE) != PCI_COMMAND_MEM_ENABLE)
sys/arch/i386/pci/pci_addr_fixup.c
322
(val & PCI_COMMAND_IO_ENABLE) != PCI_COMMAND_IO_ENABLE)
sys/arch/i386/pci/pci_addr_fixup.c
340
pcireg_t val;
sys/arch/i386/pci/pci_addr_fixup.c
346
val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
sys/arch/i386/pci/pci_addr_fixup.c
348
(val & PCI_COMMAND_MEM_ENABLE) == PCI_COMMAND_MEM_ENABLE)
sys/arch/i386/pci/pci_addr_fixup.c
351
(val & PCI_COMMAND_IO_ENABLE) == PCI_COMMAND_IO_ENABLE)
sys/arch/i386/pci/pci_addr_fixup.c
368
pciaddr_ioaddr(u_int32_t val)
sys/arch/i386/pci/pci_addr_fixup.c
370
return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM)
sys/arch/i386/pci/pci_addr_fixup.c
371
? PCI_MAPREG_MEM_ADDR(val)
sys/arch/i386/pci/pci_addr_fixup.c
372
: (PCI_MAPREG_IO_ADDR(val) & PCIADDR_PORT_END));
sys/arch/i386/pci/pci_machdep.c
525
u_int32_t sav, val;
sys/arch/i386/pci/pci_machdep.c
588
val = inl(PCI_MODE1_ADDRESS_REG);
sys/arch/i386/pci/pci_machdep.c
589
if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) {
sys/arch/i386/pci/pci_machdep.c
592
val);
sys/arch/i386/pci/pci_machdep.c
597
val = inl(PCI_MODE1_ADDRESS_REG);
sys/arch/i386/pci/pci_machdep.c
598
if ((val & 0x80fffffc) != 0)
sys/arch/i386/pci/vga_post.c
102
vm86_emu_outw(struct x86emu *emu, uint16_t port, uint16_t val)
sys/arch/i386/pci/vga_post.c
107
outw(port, val);
sys/arch/i386/pci/vga_post.c
111
vm86_emu_outl(struct x86emu *emu, uint16_t port, uint32_t val)
sys/arch/i386/pci/vga_post.c
116
outl(port, val);
sys/arch/i386/pci/vga_post.c
90
vm86_emu_outb(struct x86emu *emu, uint16_t port, uint8_t val)
sys/arch/i386/pci/vga_post.c
98
outb(port, val);
sys/arch/i386/pci/via8231.c
181
int reg, val;
sys/arch/i386/pci/via8231.c
188
val = VIA8231_GET_ROUTING_CNFG(reg, clink);
sys/arch/i386/pci/via8231.c
191
val = (reg >> ((clink & 3) * 4)) & 0xf;
sys/arch/i386/pci/via8231.c
194
*irqp = (val == VIA8231_ROUTING_CNFG_DISABLED) ?
sys/arch/i386/pci/via8231.c
195
I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
sys/arch/i386/pci/via82c586.c
152
int val;
sys/arch/i386/pci/via82c586.c
158
val = VP3_PIRQ(reg, clink);
sys/arch/i386/pci/via82c586.c
159
*irqp = (val == VP3_PIRQ_NONE)?
sys/arch/i386/pci/via82c586.c
160
I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
sys/arch/i386/pci/via82c586.c
169
int shift, val;
sys/arch/i386/pci/via82c586.c
176
via82c586_get_intr(v, clink, &val);
sys/arch/i386/pci/via82c586.c
181
if (via82c586_get_intr(v, clink, &val) != 0 ||
sys/arch/i386/pci/via82c586.c
182
val != irq)
sys/arch/landisk/dev/obio.c
418
uint8_t val, bus_size_t count);
sys/arch/landisk/dev/obio.c
420
uint16_t val, bus_size_t count);
sys/arch/landisk/dev/obio.c
422
uint32_t val, bus_size_t count);
sys/arch/landisk/dev/obio.c
424
bus_size_t offset, uint8_t val, bus_size_t count);
sys/arch/landisk/dev/obio.c
426
bus_size_t offset, uint16_t val, bus_size_t count);
sys/arch/landisk/dev/obio.c
428
bus_size_t offset, uint32_t val, bus_size_t count);
sys/arch/landisk/dev/obio.c
839
bus_size_t offset, uint8_t val, bus_size_t count)
sys/arch/landisk/dev/obio.c
844
*p = val;
sys/arch/landisk/dev/obio.c
850
bus_size_t offset, uint16_t val, bus_size_t count)
sys/arch/landisk/dev/obio.c
855
*p = val;
sys/arch/landisk/dev/obio.c
861
bus_size_t offset, uint32_t val, bus_size_t count)
sys/arch/landisk/dev/obio.c
866
*p = val;
sys/arch/landisk/dev/obio.c
872
bus_size_t offset, uint8_t val, bus_size_t count)
sys/arch/landisk/dev/obio.c
877
*addr++ = val;
sys/arch/landisk/dev/obio.c
883
bus_size_t offset, uint16_t val, bus_size_t count)
sys/arch/landisk/dev/obio.c
888
*addr++ = val;
sys/arch/landisk/dev/obio.c
894
bus_size_t offset, uint32_t val, bus_size_t count)
sys/arch/landisk/dev/obio.c
899
*addr++ = val;
sys/arch/landisk/dev/wdc_obio.c
161
wdc_obio_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/arch/landisk/dev/wdc_obio.c
165
(reg & _WDC_REGMASK) << 1, val);
sys/arch/landisk/dev/wdc_obio.c
168
(reg & _WDC_REGMASK) << 1, val);
sys/arch/landisk/dev/wdc_obio.c
69
u_int8_t val);
sys/arch/loongson/dev/kb3310.c
238
u_int val;
sys/arch/loongson/dev/kb3310.c
240
val = ykbec_read(mcsc, reg);
sys/arch/loongson/dev/kb3310.c
241
return (val << 8) | ykbec_read(mcsc, reg + 1);
sys/arch/loongson/dev/kb3310.c
345
u_int val, bat_charge, bat_status, charge_status, bat_state, power_flag;
sys/arch/loongson/dev/kb3310.c
352
val = ykbec_read16(sc, REG_FAN_SPEED_HIGH) & 0xfffff;
sys/arch/loongson/dev/kb3310.c
353
if (val != 0) {
sys/arch/loongson/dev/kb3310.c
354
val = KB3310_FAN_SPEED_DIVIDER / val;
sys/arch/loongson/dev/kb3310.c
355
sc->sc_sensor[YKBEC_FAN].value = val;
sys/arch/loongson/dev/kb3310.c
360
val = ykbec_read(sc, ECTEMP_CURRENT_REG);
sys/arch/loongson/dev/kb3310.c
361
sc->sc_sensor[YKBEC_ITEMP].value = val * 1000000 + 273150000;
sys/arch/loongson/dev/kb3310.c
374
val = ykbec_read16(sc, REG_TEMPERATURE_HIGH);
sys/arch/loongson/dev/kb3310.c
375
sc->sc_sensor[YKBEC_BTEMP].value = val * 1000000 + 273150000;
sys/arch/loongson/dev/sisfb.c
140
uint val;
sys/arch/loongson/dev/sisfb.c
142
val = bus_space_read_1(fb->iot, fb->ioh, CRTC_DATA);
sys/arch/loongson/dev/sisfb.c
144
printf("CRTC %04x -> %02x\n", idx, val);
sys/arch/loongson/dev/sisfb.c
146
return val;
sys/arch/loongson/dev/sisfb.c
152
uint val;
sys/arch/loongson/dev/sisfb.c
154
val = bus_space_read_1(fb->iot, fb->ioh, SEQ_DATA);
sys/arch/loongson/dev/sisfb.c
156
printf("SEQ %04x -> %02x\n", idx, val);
sys/arch/loongson/dev/sisfb.c
158
return val;
sys/arch/loongson/dev/sisfb.c
162
sisfb_seq_write(struct sisfb *fb, uint idx, uint val)
sys/arch/loongson/dev/sisfb.c
165
printf("SEQ %04x <- %02x\n", idx, val);
sys/arch/loongson/dev/sisfb.c
168
bus_space_write_1(fb->iot, fb->ioh, SEQ_DATA, val);
sys/arch/loongson/dev/smfb.c
74
#define DCR_WRITE(fb, reg, val) \
sys/arch/loongson/dev/smfb.c
75
bus_space_write_4((fb)->dcrt, (fb)->dcrh, (reg), (val))
sys/arch/loongson/dev/smfb.c
78
#define DPR_WRITE(fb, reg, val) \
sys/arch/loongson/dev/smfb.c
79
bus_space_write_4((fb)->dprt, (fb)->dprh, (reg), (val))
sys/arch/loongson/dev/stsec.c
234
stsec_write(struct stsec_softc *sc, uint reg, int val)
sys/arch/loongson/dev/stsec.c
240
data[0] = (uint8_t)val;
sys/arch/loongson/dev/voyager.c
322
voyager_gpio_pin_write(void *cookie, int pin, int val)
sys/arch/loongson/dev/voyager.c
336
if (val)
sys/arch/loongson/loongson/loongson2_machdep.c
276
uint32_t step, val;
sys/arch/loongson/loongson/loongson2_machdep.c
278
val = REGVAL(LOONGSON_CHIP_CONFIG0);
sys/arch/loongson/loongson/loongson2_machdep.c
279
step = (val & 0x7) + 1;
sys/arch/loongson/loongson/loongson2_machdep.c
288
uint32_t step, val;
sys/arch/loongson/loongson/loongson2_machdep.c
297
val = REGVAL(LOONGSON_CHIP_CONFIG0);
sys/arch/loongson/loongson/loongson2_machdep.c
298
val = (val & ~0x7) | (step - 1);
sys/arch/loongson/loongson/loongson2_machdep.c
299
REGVAL(LOONGSON_CHIP_CONFIG0) = val;
sys/arch/loongson/loongson/machdep.c
1147
u_long val = 0;
sys/arch/loongson/loongson/machdep.c
1195
val *= base;
sys/arch/loongson/loongson/machdep.c
1196
val += d;
sys/arch/loongson/loongson/machdep.c
1200
return neg ? -val : val;
sys/arch/luna88k/cbus/i82365_cbus.c
175
int val, found;
sys/arch/luna88k/cbus/i82365_cbus.c
208
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/arch/luna88k/cbus/i82365_cbus.c
209
if (pcic_ident_ok(val))
sys/arch/luna88k/cbus/i82365_cbus.c
213
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/arch/luna88k/cbus/i82365_cbus.c
214
if (pcic_ident_ok(val))
sys/arch/luna88k/cbus/i82365_cbus.c
218
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/arch/luna88k/cbus/i82365_cbus.c
219
if (pcic_ident_ok(val))
sys/arch/luna88k/cbus/i82365_cbus.c
223
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/arch/luna88k/cbus/i82365_cbus.c
224
if (pcic_ident_ok(val))
sys/arch/luna88k/dev/if_le.c
103
ler1->ler1_rdp = val;
sys/arch/luna88k/dev/if_le.c
110
uint16_t val;
sys/arch/luna88k/dev/if_le.c
113
val = ler1->ler1_rdp;
sys/arch/luna88k/dev/if_le.c
114
return (val);
sys/arch/luna88k/dev/if_le.c
98
lewrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
sys/arch/luna88k/dev/lcd.c
189
int val;
sys/arch/luna88k/dev/lcd.c
215
val = *(int *)addr;
sys/arch/luna88k/dev/lcd.c
216
switch (val) {
sys/arch/luna88k/dev/lcd.c
221
lcdctrl(val);
sys/arch/luna88k/dev/lcd.c
229
val = *(int *)addr;
sys/arch/luna88k/dev/lcd.c
230
if ((val & 0x7) != val)
sys/arch/luna88k/dev/lcd.c
232
lcdctrl(val | 0x8);
sys/arch/luna88k/dev/lcd.c
236
val = *(int *)addr;
sys/arch/luna88k/dev/lcd.c
237
switch (val) {
sys/arch/luna88k/dev/lcd.c
242
lcdctrl(val);
sys/arch/luna88k/dev/lcd.c
250
val = *(int *)addr & 0x7f;
sys/arch/luna88k/dev/lcd.c
251
lcdctrl(val | 0x80);
sys/arch/luna88k/dev/lunafb.c
639
u_int8_t val = i % 2 ? 255 : 0;
sys/arch/luna88k/dev/lunafb.c
641
odac->bt_cmap = dc->dc_cmap.r[i] = val;
sys/arch/luna88k/dev/lunafb.c
642
odac->bt_cmap = dc->dc_cmap.g[i] = val;
sys/arch/luna88k/dev/lunafb.c
643
odac->bt_cmap = dc->dc_cmap.b[i] = val;
sys/arch/luna88k/dev/lunafb.c
677
u_int8_t val = i % 2 ? 255 : 0;
sys/arch/luna88k/dev/lunafb.c
679
ndac->bt_cmap = dc->dc_cmap.r[i] = val;
sys/arch/luna88k/dev/lunafb.c
680
ndac->bt_cmap = dc->dc_cmap.g[i] = val;
sys/arch/luna88k/dev/lunafb.c
681
ndac->bt_cmap = dc->dc_cmap.b[i] = val;
sys/arch/luna88k/dev/siotty.c
414
int val, s, wr5, rr;
sys/arch/luna88k/dev/siotty.c
416
val = 0;
sys/arch/luna88k/dev/siotty.c
418
val |= WR5_BREAK;
sys/arch/luna88k/dev/siotty.c
420
val |= WR5_DTR;
sys/arch/luna88k/dev/siotty.c
422
val |= WR5_RTS;
sys/arch/luna88k/dev/siotty.c
430
wr5 |= val;
sys/arch/luna88k/dev/siotty.c
433
wr5 &= ~val;
sys/arch/luna88k/dev/siotty.c
436
val = 0;
sys/arch/luna88k/dev/siotty.c
439
val |= TIOCM_DTR;
sys/arch/luna88k/dev/siotty.c
441
val |= TIOCM_RTS;
sys/arch/luna88k/dev/siotty.c
443
val |= TIOCM_CTS;
sys/arch/luna88k/dev/siotty.c
445
val |= TIOCM_CD;
sys/arch/luna88k/dev/siotty.c
450
val = 0;
sys/arch/luna88k/dev/siotty.c
453
return val;
sys/arch/luna88k/dev/siotty.c
617
setsioreg(struct sioreg *sio, int regno, int val)
sys/arch/luna88k/dev/siotty.c
621
sio->sio_cmd = val; /* DELAY(); */
sys/arch/luna88k/dev/siotty.c
627
int val;
sys/arch/luna88k/dev/siotty.c
629
val = sio->sio_stat << 8; /* DELAY(); */
sys/arch/luna88k/dev/siotty.c
631
val |= sio->sio_stat; /* DELAY(); */
sys/arch/luna88k/dev/siotty.c
632
return val;
sys/arch/luna88k/stand/boot/fault.c
30
long val[19];
sys/arch/luna88k/stand/boot/samachdep.h
43
long val[19];
sys/arch/luna88k/stand/boot/sio.c
227
sioreg(int reg, int val)
sys/arch/luna88k/stand/boot/sio.c
240
sio_addr[chan]->sio_cmd = val;
sys/arch/luna88k/stand/boot/sio.c
241
return(val);
sys/arch/m88k/include/_types.h
40
long val[19];
sys/arch/m88k/include/asm_macro.h
68
ff1(u_int val)
sys/arch/m88k/include/asm_macro.h
70
__asm__ volatile ("ff1 %0, %0" : "=r" (val) : "0" (val));
sys/arch/m88k/include/asm_macro.h
71
return (val);
sys/arch/m88k/include/tcb.h
59
void *val;
sys/arch/m88k/include/tcb.h
60
__asm__ ("or %0,%%r27,%%r0" : "=r" (val));
sys/arch/m88k/include/tcb.h
61
return val;
sys/arch/m88k/m88k/m8820x_machdep.c
218
m8820x_cmmu_set_reg(const struct m8820x_cmmu *cmmu, int reg, u_int val)
sys/arch/m88k/m88k/m8820x_machdep.c
221
cmmu->cmmu_regs[reg] = val;
sys/arch/m88k/m88k/m8820x_machdep.c
227
u_int val)
sys/arch/m88k/m88k/m8820x_machdep.c
233
cmmu->cmmu_regs[reg] = val;
sys/arch/macppc/dev/akbd_machdep.c
77
int key, press, val;
sys/arch/macppc/dev/akbd_machdep.c
94
val = ADBK_KEYVAL(key);
sys/arch/macppc/dev/akbd_machdep.c
96
*data = val;
sys/arch/macppc/dev/awacs.c
409
awacs_write_reg(struct awacs_softc *sc, int reg, int val)
sys/arch/macppc/dev/awacs.c
413
out32rb(addr + reg, val);
sys/arch/macppc/dev/if_bm.c
146
bmac_write_reg(struct bmac_softc *sc, int off, int val)
sys/arch/macppc/dev/if_bm.c
148
out16rb(sc->sc_regs + off, val);
sys/arch/macppc/dev/if_bm.c
152
bmac_set_bits(struct bmac_softc *sc, int off, int val)
sys/arch/macppc/dev/if_bm.c
154
val |= bmac_read_reg(sc, off);
sys/arch/macppc/dev/if_bm.c
155
bmac_write_reg(sc, off, val);
sys/arch/macppc/dev/if_bm.c
159
bmac_reset_bits(struct bmac_softc *sc, int off, int val)
sys/arch/macppc/dev/if_bm.c
161
bmac_write_reg(sc, off, bmac_read_reg(sc, off) & ~val);
sys/arch/macppc/dev/if_bm.c
891
bmac_mii_writereg(struct device *dev, int phy, int reg, int val)
sys/arch/macppc/dev/if_bm.c
893
mii_bitbang_writereg(dev, &bmac_mbo, phy, reg, val);
sys/arch/macppc/dev/if_bm.c
905
bmac_mbo_write(struct device *dev, u_int32_t val)
sys/arch/macppc/dev/if_bm.c
909
bmac_write_reg(sc, MIFCSR, val);
sys/arch/macppc/dev/if_mc.c
79
#define NIC_PUT(sc, reg, val) (out8rb(sc->sc_reg + MACE_REG(reg), (val)))
sys/arch/macppc/dev/kiic.c
154
kiic_writereg(struct kiic_softc *sc, int reg, u_int val)
sys/arch/macppc/dev/kiic.c
158
*addr = val;
sys/arch/macppc/dev/openpic.c
161
openpic_write(int reg, u_int val)
sys/arch/macppc/dev/openpic.c
166
out32(addr, val);
sys/arch/macppc/dev/openpic.c
168
out32rb(addr, val);
sys/arch/macppc/dev/openpic.c
89
void openpic_write(int reg, u_int val);
sys/arch/macppc/dev/smu.c
202
u_int32_t reg, intr, gpio, val;
sys/arch/macppc/dev/smu.c
298
if (OF_getprop(node, "min-value", &val, sizeof val) <= 0)
sys/arch/macppc/dev/smu.c
299
val = 0;
sys/arch/macppc/dev/smu.c
300
fan->min_rpm = val;
sys/arch/macppc/dev/smu.c
301
if (OF_getprop(node, "max-value", &val, sizeof val) <= 0)
sys/arch/macppc/dev/smu.c
302
val = 0xffff;
sys/arch/macppc/dev/smu.c
303
fan->max_rpm = val;
sys/arch/macppc/dev/smu.c
304
if (OF_getprop(node, "unmanage-value", &val, sizeof val) > 0)
sys/arch/macppc/dev/smu.c
305
fan->unmanaged_rpm = val;
sys/arch/macppc/dev/smu.c
306
else if (OF_getprop(node, "safe-value", &val, sizeof val) > 0)
sys/arch/macppc/dev/smu.c
307
fan->unmanaged_rpm = val;
sys/arch/macppc/dev/smu.c
354
if (OF_getprop(node, "min-value", &val, sizeof val) <= 0)
sys/arch/macppc/dev/smu.c
355
val = 0;
sys/arch/macppc/dev/smu.c
356
fan->min_pwm = val;
sys/arch/macppc/dev/smu.c
357
if (OF_getprop(node, "max-value", &val, sizeof val) <= 0)
sys/arch/macppc/dev/smu.c
358
val = 0xffff;
sys/arch/macppc/dev/smu.c
359
fan->max_pwm = val;
sys/arch/macppc/dev/smu.c
360
if (OF_getprop(node, "unmanage-value", &val, sizeof val) > 0)
sys/arch/macppc/dev/smu.c
361
fan->unmanaged_pwm = val;
sys/arch/macppc/dev/smu.c
362
else if (OF_getprop(node, "safe-value", &val, sizeof val) > 0)
sys/arch/macppc/dev/smu.c
363
fan->unmanaged_pwm = val;
sys/arch/macppc/dev/smu.c
406
if (OF_getprop(node, "reg", &val, sizeof val) <= 0 ||
sys/arch/macppc/dev/smu.c
417
sensor->reg = val;
sys/arch/macppc/dev/snapper.c
546
uint8_t val = 0;
sys/arch/macppc/dev/snapper.c
550
val = DEQ_ACR_ADM | DEQ_ACR_LRB | DEQ_ACR_INP_B;
sys/arch/macppc/dev/snapper.c
553
val = 0;
sys/arch/macppc/dev/snapper.c
556
tas3004_write(sc, DEQ_ACR, &val);
sys/arch/macppc/dev/viareg.h
104
write_via_reg(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
108
out8(addr, val);
sys/arch/macppc/dev/viareg.h
72
via_reg_and(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
76
out8(addr, in8(addr) & val);
sys/arch/macppc/dev/viareg.h
80
via_reg_or(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
84
out8(addr, in8(addr) | val);
sys/arch/macppc/dev/viareg.h
88
via_reg_xor(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
92
out8(addr, in8(addr) ^ val);
sys/arch/macppc/dev/wdc_obio.c
609
wdc_obio_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/arch/macppc/dev/wdc_obio.c
619
(reg & _WDC_REGMASK) << 4, val);
sys/arch/macppc/dev/wdc_obio.c
622
(reg & _WDC_REGMASK) << 4, val);
sys/arch/macppc/dev/xlights.c
236
uint32_t val;
sys/arch/macppc/dev/xlights.c
257
val = (1 << ledpos_high);
sys/arch/macppc/dev/xlights.c
259
val |= (1 << ledpos_med);
sys/arch/macppc/dev/xlights.c
261
val |= (1 << ledpos_dim);
sys/arch/macppc/dev/xlights.c
262
*p = val;
sys/arch/macppc/dev/zs.c
775
u_char val;
sys/arch/macppc/dev/zs.c
779
val = in8(cs->cs_reg_csr);
sys/arch/macppc/dev/zs.c
781
return val;
sys/arch/macppc/dev/zs.c
785
zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
sys/arch/macppc/dev/zs.c
789
out8(cs->cs_reg_csr, val);
sys/arch/macppc/dev/zs.c
796
u_char val;
sys/arch/macppc/dev/zs.c
798
val = in8(cs->cs_reg_csr);
sys/arch/macppc/dev/zs.c
801
val ^= ZSRR0_CTS;
sys/arch/macppc/dev/zs.c
802
return val;
sys/arch/macppc/dev/zs.c
806
zs_write_csr(struct zs_chanstate *cs, u_char val)
sys/arch/macppc/dev/zs.c
809
out8(cs->cs_reg_csr, val);
sys/arch/macppc/dev/zs.c
816
u_char val;
sys/arch/macppc/dev/zs.c
818
val = in8(cs->cs_reg_data);
sys/arch/macppc/dev/zs.c
820
return val;
sys/arch/macppc/dev/zs.c
824
zs_write_data(struct zs_chanstate *cs, u_char val)
sys/arch/macppc/dev/zs.c
826
out8(cs->cs_reg_data, val);
sys/arch/macppc/include/bus.h
381
bus_size_t offset, u_int8_t val, size_t count)
sys/arch/macppc/include/bus.h
386
*d = val;
sys/arch/macppc/include/bus.h
392
bus_size_t offset, u_int16_t val, size_t count)
sys/arch/macppc/include/bus.h
398
"r"(val), "r"(d));
sys/arch/macppc/include/bus.h
404
bus_size_t offset, u_int32_t val, size_t count)
sys/arch/macppc/include/bus.h
410
"r"(val), "r"(d));
sys/arch/macppc/include/bus.h
437
u_int8_t val, bus_size_t c);
sys/arch/macppc/include/bus.h
440
u_int16_t val, bus_size_t c);
sys/arch/macppc/include/bus.h
443
u_int32_t val, bus_size_t c);
sys/arch/macppc/include/z8530var.h
121
void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);
sys/arch/macppc/include/z8530var.h
122
void zs_write_csr(struct zs_chanstate *cs, u_char val);
sys/arch/macppc/include/z8530var.h
123
void zs_write_data(struct zs_chanstate *cs, u_char val);
sys/arch/macppc/macppc/autoconf.c
213
int val = 0, digit;
sys/arch/macppc/macppc/autoconf.c
223
val = val * 16 + digit;
sys/arch/macppc/macppc/autoconf.c
227
return (val);
sys/arch/macppc/pci/ht.c
155
uint32_t val;
sys/arch/macppc/pci/ht.c
157
val = PCITAG_OFFSET(tag);
sys/arch/macppc/pci/ht.c
159
printf("ht_conf_read: tag=%x, offset=%x\n", val, offset);
sys/arch/macppc/pci/ht.c
163
val |= (offset << 2);
sys/arch/macppc/pci/ht.c
164
reg = bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
sys/arch/macppc/pci/ht.c
170
val |= offset;
sys/arch/macppc/pci/ht.c
171
reg = bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
sys/arch/macppc/pci/ht.c
173
val |= offset;
sys/arch/macppc/pci/ht.c
174
reg = bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
sys/arch/macppc/pci/ht.c
187
uint32_t val;
sys/arch/macppc/pci/ht.c
189
val = PCITAG_OFFSET(tag);
sys/arch/macppc/pci/ht.c
192
val, offset, data);
sys/arch/macppc/pci/ht.c
196
val |= (offset << 2);
sys/arch/macppc/pci/ht.c
198
bus_space_write_4(sc->sc_iot, sc->sc_config0_ioh, val, data);
sys/arch/macppc/pci/ht.c
199
bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
sys/arch/macppc/pci/ht.c
204
val |= offset;
sys/arch/macppc/pci/ht.c
205
bus_space_write_4(sc->sc_memt, sc->sc_config0_memh, val, data);
sys/arch/macppc/pci/ht.c
206
bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
sys/arch/macppc/pci/ht.c
208
val |= offset;
sys/arch/macppc/pci/ht.c
209
bus_space_write_4(sc->sc_memt, sc->sc_config1_memh, val, data);
sys/arch/macppc/pci/ht.c
210
bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
sys/arch/macppc/pci/macobio.c
283
u_int32_t val;
sys/arch/macppc/pci/macobio.c
287
val = in32rb(sc->obiomem + 0x40);
sys/arch/macppc/pci/macobio.c
289
val = val & ~((u_int32_t)1<<25);
sys/arch/macppc/pci/macobio.c
291
val = val | ((u_int32_t)1<<25);
sys/arch/macppc/pci/macobio.c
292
out32rb(sc->obiomem + 0x40, val);
sys/arch/macppc/pci/mpcpcibus.c
444
u_int32_t reg, val = PCITAG_OFFSET(tag);
sys/arch/macppc/pci/mpcpcibus.c
449
reg = val | offset | 1;
sys/arch/macppc/pci/mpcpcibus.c
469
reg = val | offset | 1;
sys/arch/macppc/pci/mpcpcibus.c
475
reg = 0x80000000 | val | offset;
sys/arch/macppc/pci/pci_machdep.c
250
uint32_t val = 0;
sys/arch/macppc/pci/pci_machdep.c
276
val = 0;
sys/arch/macppc/pci/pci_machdep.c
278
&val, sizeof(val)) < sizeof(val)) || val != 1)
sys/arch/macppc/pci/pci_machdep.c
308
val = 0;
sys/arch/macppc/pci/pci_machdep.c
309
if ((OF_getprop(node, "shasta-interrupt-sequencer", &val,
sys/arch/macppc/pci/pci_machdep.c
310
sizeof(val)) >= sizeof(val)) && val == 1)
sys/arch/mips64/include/_types.h
147
long val[14];
sys/arch/mips64/include/pcb.h
52
register_t val[13];
sys/arch/mips64/mips64/interrupt.c
206
pcb->pcb_context.val[11] = (pcb->pcb_regs.sr & ~SR_INT_MASK) |
sys/arch/mips64/mips64/vm_machdep.c
118
pcb->pcb_context.val[11] = (pcb->pcb_regs.sr & ~SR_INT_MASK) |
sys/arch/mips64/mips64/vm_machdep.c
121
pcb->pcb_context.val[10] = (register_t)proc_trampoline;
sys/arch/mips64/mips64/vm_machdep.c
122
pcb->pcb_context.val[8] = (register_t)pcb +
sys/arch/mips64/mips64/vm_machdep.c
124
pcb->pcb_context.val[1] = (register_t)arg;
sys/arch/mips64/mips64/vm_machdep.c
125
pcb->pcb_context.val[0] = (register_t)func;
sys/arch/octeon/dev/amdcf.c
906
uint8_t val)
sys/arch/octeon/dev/amdcf.c
909
base | (offset * sc->sc_shift), val);
sys/arch/octeon/dev/cn30xxgmx.c
1004
val = AGL_GMX_RD8(sc, AGL_PRT_CTL(port));
sys/arch/octeon/dev/cn30xxgmx.c
1005
SET(val, AGL_PRT_CTL_CLKRST);
sys/arch/octeon/dev/cn30xxgmx.c
1006
AGL_GMX_WR8(sc, AGL_PRT_CTL(port), val);
sys/arch/octeon/dev/cn30xxgmx.c
1008
val = AGL_GMX_RD8(sc, AGL_PRT_CTL(port));
sys/arch/octeon/dev/cn30xxgmx.c
1009
SET(val, AGL_PRT_CTL_ENABLE);
sys/arch/octeon/dev/cn30xxgmx.c
1010
AGL_GMX_WR8(sc, AGL_PRT_CTL(port), val);
sys/arch/octeon/dev/cn30xxgmx.c
1539
uint64_t val;
sys/arch/octeon/dev/cn30xxgmx.c
1554
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT0);
sys/arch/octeon/dev/cn30xxgmx.c
1555
kstat_kv_u64(&kvs[cnmac_stat_tx_coll]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1556
kstat_kv_u64(&kvs[cnmac_stat_tx_defer]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1558
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT1);
sys/arch/octeon/dev/cn30xxgmx.c
1559
kstat_kv_u64(&kvs[cnmac_stat_tx_mcol]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1560
kstat_kv_u64(&kvs[cnmac_stat_tx_scol]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1567
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT4);
sys/arch/octeon/dev/cn30xxgmx.c
1568
kstat_kv_u64(&kvs[cnmac_stat_tx_hmin]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1569
kstat_kv_u64(&kvs[cnmac_stat_tx_h64]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1571
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT5);
sys/arch/octeon/dev/cn30xxgmx.c
1572
kstat_kv_u64(&kvs[cnmac_stat_tx_h127]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1573
kstat_kv_u64(&kvs[cnmac_stat_tx_h255]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1575
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT6);
sys/arch/octeon/dev/cn30xxgmx.c
1576
kstat_kv_u64(&kvs[cnmac_stat_tx_h511]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1577
kstat_kv_u64(&kvs[cnmac_stat_tx_h1023]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1579
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT7);
sys/arch/octeon/dev/cn30xxgmx.c
1580
kstat_kv_u64(&kvs[cnmac_stat_tx_h1518]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1581
kstat_kv_u64(&kvs[cnmac_stat_tx_hmax]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1583
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT8);
sys/arch/octeon/dev/cn30xxgmx.c
1584
kstat_kv_u64(&kvs[cnmac_stat_tx_bcast]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1585
kstat_kv_u64(&kvs[cnmac_stat_tx_mcast]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
1587
val = _GMX_PORT_RD8(sc, GMX0_TX0_STAT9);
sys/arch/octeon/dev/cn30xxgmx.c
1588
kstat_kv_u64(&kvs[cnmac_stat_tx_ctl]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxgmx.c
1589
kstat_kv_u64(&kvs[cnmac_stat_tx_uflow]) += val >> 32;
sys/arch/octeon/dev/cn30xxgmx.c
480
uint64_t val;
sys/arch/octeon/dev/cn30xxgmx.c
482
val = bus_space_read_8(sc->sc_regt, sc->sc_regh,
sys/arch/octeon/dev/cn30xxgmx.c
484
if ((val & AGL_PRT_CTL_MODE_M) ==
sys/arch/octeon/dev/cn30xxgmx.c
64
#define AGL_GMX_WR8(sc, reg, val) \
sys/arch/octeon/dev/cn30xxgmx.c
66
(sc)->sc_port_gmx->sc_regh, (reg), (val))
sys/arch/octeon/dev/cn30xxgmx.c
70
#define AGL_GMX_PORT_WR8(sc, reg, val) \
sys/arch/octeon/dev/cn30xxgmx.c
72
(sc)->sc_port_regh, (reg), (val))
sys/arch/octeon/dev/cn30xxgmx.c
77
#define PCS_WRITE_8(sc, reg, val) \
sys/arch/octeon/dev/cn30xxgmx.c
79
(reg), (val))
sys/arch/octeon/dev/cn30xxgmx.c
840
uint64_t val;
sys/arch/octeon/dev/cn30xxgmx.c
844
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_PRT_CFG);
sys/arch/octeon/dev/cn30xxgmx.c
845
CLR(val, AGL_GMX_PRT_CFG_EN);
sys/arch/octeon/dev/cn30xxgmx.c
846
AGL_GMX_PORT_WR8(sc, AGL_GMX_PRT_CFG, val);
sys/arch/octeon/dev/cn30xxgmx.c
849
val = AGL_GMX_RD8(sc, AGL_PRT_CTL(port));
sys/arch/octeon/dev/cn30xxgmx.c
850
CLR(val, AGL_PRT_CTL_CLKRST);
sys/arch/octeon/dev/cn30xxgmx.c
851
CLR(val, AGL_PRT_CTL_DLLRST);
sys/arch/octeon/dev/cn30xxgmx.c
852
CLR(val, AGL_PRT_CTL_CLKTX_BYP);
sys/arch/octeon/dev/cn30xxgmx.c
853
CLR(val, AGL_PRT_CTL_CLKTX_SET_M);
sys/arch/octeon/dev/cn30xxgmx.c
854
CLR(val, AGL_PRT_CTL_CLKRX_BYP);
sys/arch/octeon/dev/cn30xxgmx.c
855
CLR(val, AGL_PRT_CTL_CLKRX_SET_M);
sys/arch/octeon/dev/cn30xxgmx.c
856
CLR(val, AGL_PRT_CTL_REFCLK_SEL_M);
sys/arch/octeon/dev/cn30xxgmx.c
857
AGL_GMX_WR8(sc, AGL_PRT_CTL(port), val);
sys/arch/octeon/dev/cn30xxgmx.c
863
val = AGL_GMX_RD8(sc, AGL_PRT_CTL(port));
sys/arch/octeon/dev/cn30xxgmx.c
864
CLR(val, AGL_PRT_CTL_DRV_BYP);
sys/arch/octeon/dev/cn30xxgmx.c
865
AGL_GMX_WR8(sc, AGL_PRT_CTL(port), val);
sys/arch/octeon/dev/cn30xxgmx.c
868
val = AGL_GMX_RD8(sc, AGL_PRT_CTL(port));
sys/arch/octeon/dev/cn30xxgmx.c
869
SET(val, AGL_PRT_CTL_COMP);
sys/arch/octeon/dev/cn30xxgmx.c
870
AGL_GMX_WR8(sc, AGL_PRT_CTL(port), val);
sys/arch/octeon/dev/cn30xxgmx.c
876
val = AGL_GMX_RX_FRM_CTL_PRE_ALIGN
sys/arch/octeon/dev/cn30xxgmx.c
885
AGL_GMX_PORT_WR8(sc, AGL_GMX_RX_FRM_CTL, val);
sys/arch/octeon/dev/cn30xxgmx.c
892
uint64_t val;
sys/arch/octeon/dev/cn30xxgmx.c
894
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_PRT_CFG);
sys/arch/octeon/dev/cn30xxgmx.c
895
SET(val, AGL_GMX_PRT_CFG_RX_EN);
sys/arch/octeon/dev/cn30xxgmx.c
896
SET(val, AGL_GMX_PRT_CFG_TX_EN);
sys/arch/octeon/dev/cn30xxgmx.c
897
AGL_GMX_PORT_WR8(sc, AGL_GMX_PRT_CFG, val);
sys/arch/octeon/dev/cn30xxgmx.c
899
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_PRT_CFG);
sys/arch/octeon/dev/cn30xxgmx.c
900
SET(val, AGL_GMX_PRT_CFG_EN);
sys/arch/octeon/dev/cn30xxgmx.c
901
AGL_GMX_PORT_WR8(sc, AGL_GMX_PRT_CFG, val);
sys/arch/octeon/dev/cn30xxgmx.c
908
uint64_t val;
sys/arch/octeon/dev/cn30xxgmx.c
911
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_PRT_CFG);
sys/arch/octeon/dev/cn30xxgmx.c
912
CLR(val, AGL_GMX_PRT_CFG_EN);
sys/arch/octeon/dev/cn30xxgmx.c
913
AGL_GMX_PORT_WR8(sc, AGL_GMX_PRT_CFG, val);
sys/arch/octeon/dev/cn30xxgmx.c
915
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_PRT_CFG);
sys/arch/octeon/dev/cn30xxgmx.c
916
CLR(val, AGL_GMX_PRT_CFG_RX_EN);
sys/arch/octeon/dev/cn30xxgmx.c
917
CLR(val, AGL_GMX_PRT_CFG_TX_EN);
sys/arch/octeon/dev/cn30xxgmx.c
918
AGL_GMX_PORT_WR8(sc, AGL_GMX_PRT_CFG, val);
sys/arch/octeon/dev/cn30xxgmx.c
925
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_PRT_CFG);
sys/arch/octeon/dev/cn30xxgmx.c
926
if ((val & idlemask) == idlemask)
sys/arch/octeon/dev/cn30xxgmx.c
946
uint64_t clk_cnt, prt_cfg, val;
sys/arch/octeon/dev/cn30xxgmx.c
990
val = AGL_GMX_PORT_RD8(sc, AGL_GMX_TX_CLK);
sys/arch/octeon/dev/cn30xxgmx.c
991
CLR(val, AGL_GMX_TX_CLK_CLK_CNT_M);
sys/arch/octeon/dev/cn30xxgmx.c
992
SET(val, clk_cnt << AGL_GMX_TX_CLK_CLK_CNT_S);
sys/arch/octeon/dev/cn30xxgmx.c
993
AGL_GMX_PORT_WR8(sc, AGL_GMX_TX_CLK, val);
sys/arch/octeon/dev/cn30xxpip.c
185
uint64_t val;
sys/arch/octeon/dev/cn30xxpip.c
187
val = _PIP_STAT_RD8(sc, PIP_STAT0_PRT);
sys/arch/octeon/dev/cn30xxpip.c
188
kstat_kv_u64(&kvs[cnmac_stat_rx_qdpo]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
189
kstat_kv_u64(&kvs[cnmac_stat_rx_qdpp]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
191
val = _PIP_STAT_RD8(sc, PIP_STAT1_PRT);
sys/arch/octeon/dev/cn30xxpip.c
192
kstat_kv_u64(&kvs[cnmac_stat_rx_toto_pip]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
194
val = _PIP_STAT_RD8(sc, PIP_STAT2_PRT);
sys/arch/octeon/dev/cn30xxpip.c
195
kstat_kv_u64(&kvs[cnmac_stat_rx_raw]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
196
kstat_kv_u64(&kvs[cnmac_stat_rx_totp_pip]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
198
val = _PIP_STAT_RD8(sc, PIP_STAT3_PRT);
sys/arch/octeon/dev/cn30xxpip.c
199
kstat_kv_u64(&kvs[cnmac_stat_rx_mcast]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
200
kstat_kv_u64(&kvs[cnmac_stat_rx_bcast]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
202
val = _PIP_STAT_RD8(sc, PIP_STAT4_PRT);
sys/arch/octeon/dev/cn30xxpip.c
203
kstat_kv_u64(&kvs[cnmac_stat_rx_h64]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
204
kstat_kv_u64(&kvs[cnmac_stat_rx_h127]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
206
val = _PIP_STAT_RD8(sc, PIP_STAT5_PRT);
sys/arch/octeon/dev/cn30xxpip.c
207
kstat_kv_u64(&kvs[cnmac_stat_rx_h255]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
208
kstat_kv_u64(&kvs[cnmac_stat_rx_h511]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
210
val = _PIP_STAT_RD8(sc, PIP_STAT6_PRT);
sys/arch/octeon/dev/cn30xxpip.c
211
kstat_kv_u64(&kvs[cnmac_stat_rx_h1023]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
212
kstat_kv_u64(&kvs[cnmac_stat_rx_h1518]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
214
val = _PIP_STAT_RD8(sc, PIP_STAT7_PRT);
sys/arch/octeon/dev/cn30xxpip.c
215
kstat_kv_u64(&kvs[cnmac_stat_rx_hmax]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
216
kstat_kv_u64(&kvs[cnmac_stat_rx_fcs]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
218
val = _PIP_STAT_RD8(sc, PIP_STAT8_PRT);
sys/arch/octeon/dev/cn30xxpip.c
219
kstat_kv_u64(&kvs[cnmac_stat_rx_undersz]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
220
kstat_kv_u64(&kvs[cnmac_stat_rx_frag]) += val >> 32;
sys/arch/octeon/dev/cn30xxpip.c
222
val = _PIP_STAT_RD8(sc, PIP_STAT9_PRT);
sys/arch/octeon/dev/cn30xxpip.c
223
kstat_kv_u64(&kvs[cnmac_stat_rx_oversz]) += (uint32_t)val;
sys/arch/octeon/dev/cn30xxpip.c
224
kstat_kv_u64(&kvs[cnmac_stat_rx_jabber]) += val >> 32;
sys/arch/octeon/dev/cn30xxpko.c
143
uint64_t mem_queue_ptrs, val;
sys/arch/octeon/dev/cn30xxpko.c
158
val = _PKO_RD8(sc, PKO_MEM_PORT_PTRS_OFFSET);
sys/arch/octeon/dev/cn30xxpko.c
159
if ((val & PKO_MEM_PORT_PTRS_PID_M) == 24) {
sys/arch/octeon/dev/cn30xxpko.c
160
CLR(val, PKO_MEM_PORT_PTRS_EID_M);
sys/arch/octeon/dev/cn30xxpko.c
161
SET(val, 10ULL << PKO_MEM_PORT_PTRS_EID_S);
sys/arch/octeon/dev/cn30xxpko.c
162
CLR(val, PKO_MEM_PORT_PTRS_BP_PORT_M);
sys/arch/octeon/dev/cn30xxpko.c
163
SET(val, 40ULL << PKO_MEM_PORT_PTRS_BP_PORT_S);
sys/arch/octeon/dev/cn30xxpko.c
164
_PKO_WR8(sc, PKO_MEM_PORT_PTRS_OFFSET, val);
sys/arch/octeon/dev/if_ogx.c
1407
uint64_t val;
sys/arch/octeon/dev/if_ogx.c
1410
val = PORT_RD_8(sc, BGX_GMP_GMI_TX_APPEND);
sys/arch/octeon/dev/if_ogx.c
1411
val |= BGX_GMP_GMI_TX_APPEND_FCS;
sys/arch/octeon/dev/if_ogx.c
1412
val |= BGX_GMP_GMI_TX_APPEND_PAD;
sys/arch/octeon/dev/if_ogx.c
1413
if (ISSET(val, BGX_GMP_GMI_TX_APPEND_PREAMBLE))
sys/arch/octeon/dev/if_ogx.c
1415
PORT_WR_8(sc, BGX_GMP_GMI_TX_APPEND, val);
sys/arch/octeon/dev/if_ogx.c
1419
val = PORT_RD_8(sc, BGX_GMP_GMI_TX_SGMII_CTL);
sys/arch/octeon/dev/if_ogx.c
1421
val |= BGX_GMP_GMI_TX_SGMII_CTL_ALIGN;
sys/arch/octeon/dev/if_ogx.c
1423
val &= ~BGX_GMP_GMI_TX_SGMII_CTL_ALIGN;
sys/arch/octeon/dev/if_ogx.c
1424
PORT_WR_8(sc, BGX_GMP_GMI_TX_SGMII_CTL, val);
sys/arch/octeon/dev/if_ogx.c
1427
val = PORT_RD_8(sc, BGX_GMP_PCS_LINK_TIMER);
sys/arch/octeon/dev/if_ogx.c
1428
val &= ~BGX_GMP_PCS_LINK_TIMER_COUNT_M;
sys/arch/octeon/dev/if_ogx.c
1429
val |= (1600 * cpu_freq) >> 10;
sys/arch/octeon/dev/if_ogx.c
1430
PORT_WR_8(sc, BGX_GMP_PCS_LINK_TIMER, val);
sys/arch/octeon/dev/if_ogx.c
1438
uint64_t val;
sys/arch/octeon/dev/if_ogx.c
1445
val = PORT_RD_8(sc, BGX_GMP_GMI_PRT_CFG);
sys/arch/octeon/dev/if_ogx.c
1446
if ((val & idlemask) == idlemask)
sys/arch/octeon/dev/if_ogx.c
1454
val = PORT_RD_8(sc, BGX_GMP_PCS_MR_CONTROL);
sys/arch/octeon/dev/if_ogx.c
1455
val &= ~BGX_GMP_PCS_MR_CONTROL_AN_EN;
sys/arch/octeon/dev/if_ogx.c
1456
val |= BGX_GMP_PCS_MR_CONTROL_PWR_DN;
sys/arch/octeon/dev/if_ogx.c
1457
PORT_WR_8(sc, BGX_GMP_PCS_MR_CONTROL, val);
sys/arch/octeon/dev/if_ogx.c
1469
uint64_t val;
sys/arch/octeon/dev/if_ogx.c
1479
val = PORT_RD_8(sc, BGX_CMR_CONFIG);
sys/arch/octeon/dev/if_ogx.c
1480
val |= BGX_CMR_CONFIG_ENABLE;
sys/arch/octeon/dev/if_ogx.c
1481
PORT_WR_8(sc, BGX_CMR_CONFIG, val);
sys/arch/octeon/dev/if_ogx.c
1484
val = PORT_RD_8(sc, BGX_GMP_PCS_MR_CONTROL);
sys/arch/octeon/dev/if_ogx.c
1485
val |= BGX_GMP_PCS_MR_CONTROL_RESET;
sys/arch/octeon/dev/if_ogx.c
1486
PORT_WR_8(sc, BGX_GMP_PCS_MR_CONTROL_RESET, val);
sys/arch/octeon/dev/if_ogx.c
1491
val = PORT_RD_8(sc, BGX_GMP_PCS_MR_CONTROL);
sys/arch/octeon/dev/if_ogx.c
1492
if (!ISSET(val, BGX_GMP_PCS_MR_CONTROL_RESET))
sys/arch/octeon/dev/if_ogx.c
1500
val = PORT_RD_8(sc, BGX_GMP_PCS_MISC_CTL);
sys/arch/octeon/dev/if_ogx.c
1501
val &= ~BGX_GMP_PCS_MISC_CTL_MAC_PHY;
sys/arch/octeon/dev/if_ogx.c
1502
val &= ~BGX_GMP_PCS_MISC_CTL_MODE;
sys/arch/octeon/dev/if_ogx.c
1503
PORT_WR_8(sc, BGX_GMP_PCS_MISC_CTL, val);
sys/arch/octeon/dev/if_ogx.c
1506
val = PORT_RD_8(sc, BGX_GMP_PCS_MR_CONTROL);
sys/arch/octeon/dev/if_ogx.c
1507
val |= BGX_GMP_PCS_MR_CONTROL_AN_EN;
sys/arch/octeon/dev/if_ogx.c
1508
val |= BGX_GMP_PCS_MR_CONTROL_RST_AN;
sys/arch/octeon/dev/if_ogx.c
1509
val &= ~BGX_GMP_PCS_MR_CONTROL_PWR_DN;
sys/arch/octeon/dev/if_ogx.c
1510
PORT_WR_8(sc, BGX_GMP_PCS_MR_CONTROL, val);
sys/arch/octeon/dev/if_ogx.c
1515
val = PORT_RD_8(sc, BGX_GMP_PCS_MR_STATUS);
sys/arch/octeon/dev/if_ogx.c
1516
if (ISSET(val, BGX_GMP_PCS_MR_STATUS_AN_CPT))
sys/arch/octeon/dev/if_ogx.c
1818
uint64_t delta, val;
sys/arch/octeon/dev/if_ogx.c
1825
val = PORT_RD_8(sc, c->c_reg);
sys/arch/octeon/dev/if_ogx.c
1826
delta = (val - counter_vals[i]) & BGX_CMR_STAT_MASK;
sys/arch/octeon/dev/if_ogx.c
1827
counter_vals[i] = val;
sys/arch/octeon/dev/if_ogx.c
1837
val = bus_space_read_8(sc->sc_iot,
sys/arch/octeon/dev/if_ogx.c
1839
if (val != ~0ULL) {
sys/arch/octeon/dev/if_ogx.c
184
#define PORT_WR_8(sc, reg, val) \
sys/arch/octeon/dev/if_ogx.c
1840
delta = (val - counter_vals[i]) &
sys/arch/octeon/dev/if_ogx.c
1842
counter_vals[i] = val;
sys/arch/octeon/dev/if_ogx.c
185
bus_space_write_8((sc)->sc_iot, (sc)->sc_port_ioh, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
189
#define NEXUS_WR_8(sc, reg, val) \
sys/arch/octeon/dev/if_ogx.c
190
bus_space_write_8((sc)->sc_iot, (sc)->sc_nexus_ioh, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
1915
uint64_t val;
sys/arch/octeon/dev/if_ogx.c
194
#define FPA3_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
195
bus_space_write_8((node)->node_iot, (node)->node_fpa3, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
198
#define PKI_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
1986
val = SSO_AW_CFG_LDWB | SSO_AW_CFG_LDT | SSO_AW_CFG_STT;
sys/arch/octeon/dev/if_ogx.c
1987
SSO_WR_8(node, SSO_AW_CFG, val);
sys/arch/octeon/dev/if_ogx.c
1989
val = node->node_id << SSO_XAQ_AURA_NODE_S;
sys/arch/octeon/dev/if_ogx.c
199
bus_space_write_8((node)->node_iot, (node)->node_pki, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
1990
val |= (uint64_t)OGX_AURA_SSO << SSO_XAQ_AURA_LAURA_S;
sys/arch/octeon/dev/if_ogx.c
1991
SSO_WR_8(node, SSO_XAQ_AURA, val);
sys/arch/octeon/dev/if_ogx.c
2011
val = SSO_RD_8(node, SSO_AW_CFG);
sys/arch/octeon/dev/if_ogx.c
2012
val |= SSO_AW_CFG_RWEN;
sys/arch/octeon/dev/if_ogx.c
2013
SSO_WR_8(node, SSO_AW_CFG, val);
sys/arch/octeon/dev/if_ogx.c
202
#define PKO3_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
203
bus_space_write_8((node)->node_iot, (node)->node_pko3, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
2042
val = PKI_RD_8(node, PKI_BUF_CTL);
sys/arch/octeon/dev/if_ogx.c
2043
val |= PKI_BUF_CTL_PBP_EN;
sys/arch/octeon/dev/if_ogx.c
2044
PKI_WR_8(node, PKI_BUF_CTL, val);
sys/arch/octeon/dev/if_ogx.c
2048
val = PKI_RD_8(node, PKI_ICG_CFG(cl));
sys/arch/octeon/dev/if_ogx.c
2049
val &= ~PKI_ICG_CFG_PENA;
sys/arch/octeon/dev/if_ogx.c
2050
PKI_WR_8(node, PKI_ICG_CFG(cl), val);
sys/arch/octeon/dev/if_ogx.c
2053
val = PKI_RD_8(node, PKI_GBL_PEN);
sys/arch/octeon/dev/if_ogx.c
2054
val &= ~PKI_GBL_PEN_M;
sys/arch/octeon/dev/if_ogx.c
2055
val |= PKI_GBL_PEN_L3;
sys/arch/octeon/dev/if_ogx.c
2056
val |= PKI_GBL_PEN_L4;
sys/arch/octeon/dev/if_ogx.c
2057
PKI_WR_8(node, PKI_GBL_PEN, val);
sys/arch/octeon/dev/if_ogx.c
206
#define SSO_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
2060
val = PKI_RD_8(node, PKI_LTYPE_MAP(i));
sys/arch/octeon/dev/if_ogx.c
2061
val &= ~0x7;
sys/arch/octeon/dev/if_ogx.c
2062
val |= ogx_ltypes[i];
sys/arch/octeon/dev/if_ogx.c
2063
PKI_WR_8(node, PKI_LTYPE_MAP(i), val);
sys/arch/octeon/dev/if_ogx.c
2069
val = PKI_RD_8(node, PKI_BUF_CTL);
sys/arch/octeon/dev/if_ogx.c
207
bus_space_write_8((node)->node_iot, (node)->node_sso, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
2070
val |= PKI_BUF_CTL_PKI_EN;
sys/arch/octeon/dev/if_ogx.c
2071
PKI_WR_8(node, PKI_BUF_CTL, val);
sys/arch/octeon/dev/if_ogx.c
2079
val = PKO3_RD_8(node, PKO3_MAC_CFG(i));
sys/arch/octeon/dev/if_ogx.c
2080
val |= PKO3_MAC_CFG_FIFO_NUM_M;
sys/arch/octeon/dev/if_ogx.c
2081
PKO3_WR_8(node, PKO3_MAC_CFG(i), val);
sys/arch/octeon/dev/if_ogx.c
2086
val = (uint64_t)cfg->cfg_nullmac << PKO3_L1_SQ_TOPOLOGY_LINK_S;
sys/arch/octeon/dev/if_ogx.c
2087
PKO3_WR_8(node, PKO3_L1_SQ_TOPOLOGY(i), val);
sys/arch/octeon/dev/if_ogx.c
2088
val = (uint64_t)cfg->cfg_nullmac << PKO3_L1_SQ_SHAPE_LINK_S;
sys/arch/octeon/dev/if_ogx.c
2089
PKO3_WR_8(node, PKO3_L1_SQ_SHAPE(i), val);
sys/arch/octeon/dev/if_ogx.c
2090
val = (uint64_t)cfg->cfg_nullmac << PKO3_L1_SQ_LINK_LINK_S;
sys/arch/octeon/dev/if_ogx.c
2091
PKO3_WR_8(node, PKO3_L1_SQ_LINK(i), val);
sys/arch/octeon/dev/if_ogx.c
2096
val = PKO3_RD_8(node, PKO3_PTGF_CFG(i));
sys/arch/octeon/dev/if_ogx.c
2097
val &= ~PKO3_PTGF_CFG_SIZE_M;
sys/arch/octeon/dev/if_ogx.c
2098
val &= ~PKO3_PTGF_CFG_RATE_M;
sys/arch/octeon/dev/if_ogx.c
2099
val |= 2 << PKO3_PTGF_CFG_RATE_S;
sys/arch/octeon/dev/if_ogx.c
2100
val |= PKO3_PTGF_CFG_RESET;
sys/arch/octeon/dev/if_ogx.c
2101
PKO3_WR_8(node, PKO3_PTGF_CFG(i), val);
sys/arch/octeon/dev/if_ogx.c
2103
val = PKO3_RD_8(node, PKO3_PTGF_CFG(i));
sys/arch/octeon/dev/if_ogx.c
2104
val &= ~PKO3_PTGF_CFG_RESET;
sys/arch/octeon/dev/if_ogx.c
2105
PKO3_WR_8(node, PKO3_PTGF_CFG(i), val);
sys/arch/octeon/dev/if_ogx.c
2111
val = ((uint64_t)node->node_id << PKO3_DPFI_FPA_AURA_NODE_S) |
sys/arch/octeon/dev/if_ogx.c
2113
PKO3_WR_8(node, PKO3_DPFI_FPA_AURA, val);
sys/arch/octeon/dev/if_ogx.c
2120
val = PKO3_RD_8(node, PKO3_STATUS);
sys/arch/octeon/dev/if_ogx.c
2121
if (ISSET(val, PKO3_STATUS_PKO_RDY))
sys/arch/octeon/dev/if_ogx.c
2128
val = 72 << PKO3_PTF_IOBP_CFG_MAX_RD_SZ_S;
sys/arch/octeon/dev/if_ogx.c
2129
PKO3_WR_8(node, PKO3_PTF_IOBP_CFG, val);
sys/arch/octeon/dev/if_ogx.c
2131
val = 60 << PKO3_PDM_CFG_MIN_PAD_LEN_S;
sys/arch/octeon/dev/if_ogx.c
2132
PKO3_WR_8(node, PKO3_PDM_CFG, val);
sys/arch/octeon/dev/if_ogx.c
2281
uint64_t *imem, val;
sys/arch/octeon/dev/if_ogx.c
2308
val = PKI_RD_8(node, PKI_ICG_CFG(cl));
sys/arch/octeon/dev/if_ogx.c
2309
val |= PKI_ICG_CFG_PENA;
sys/arch/octeon/dev/if_ogx.c
2310
PKI_WR_8(node, PKI_ICG_CFG(cl), val);
sys/arch/octeon/dev/if_ogx.c
371
uint64_t lmac_type, lut_index, val;
sys/arch/octeon/dev/if_ogx.c
422
val = PORT_RD_8(sc, BGX_CMR_RX_ID_MAP);
sys/arch/octeon/dev/if_ogx.c
423
val &= ~BGX_CMR_RX_ID_MAP_RID_M;
sys/arch/octeon/dev/if_ogx.c
424
val &= ~BGX_CMR_RX_ID_MAP_PKND_M;
sys/arch/octeon/dev/if_ogx.c
425
val |= (uint64_t)(sc->sc_bgxid * 4 + 2 + sc->sc_lmacid) <<
sys/arch/octeon/dev/if_ogx.c
427
val |= (uint64_t)PORT_PKIND(sc) << BGX_CMR_RX_ID_MAP_PKND_S;
sys/arch/octeon/dev/if_ogx.c
428
PORT_WR_8(sc, BGX_CMR_RX_ID_MAP, val);
sys/arch/octeon/dev/if_ogx.c
430
val = PORT_RD_8(sc, BGX_CMR_CHAN_MSK_AND);
sys/arch/octeon/dev/if_ogx.c
431
val |= 0xffffULL << (sc->sc_lmacid * 16);
sys/arch/octeon/dev/if_ogx.c
432
PORT_WR_8(sc, BGX_CMR_CHAN_MSK_AND, val);
sys/arch/octeon/dev/if_ogx.c
434
val = PORT_RD_8(sc, BGX_CMR_CHAN_MSK_OR);
sys/arch/octeon/dev/if_ogx.c
435
val |= 0xffffULL << (sc->sc_lmacid * 16);
sys/arch/octeon/dev/if_ogx.c
436
PORT_WR_8(sc, BGX_CMR_CHAN_MSK_OR, val);
sys/arch/octeon/dev/if_ogx.c
451
val = PORT_RD_8(sc, BGX_CMR_CONFIG);
sys/arch/octeon/dev/if_ogx.c
452
lmac_type = (val & BGX_CMR_CONFIG_LMAC_TYPE_M) >>
sys/arch/octeon/dev/if_ogx.c
509
val = (uint64_t)PORT_GROUP_RX(sc) << PKI_QPG_TBL_GRP_OK_S;
sys/arch/octeon/dev/if_ogx.c
510
val |= (uint64_t)PORT_GROUP_RX(sc) << PKI_QPG_TBL_GRP_BAD_S;
sys/arch/octeon/dev/if_ogx.c
511
val |= OGX_AURA_PKT(sc) << PKI_QPG_TBL_LAURA_S;
sys/arch/octeon/dev/if_ogx.c
512
PKI_WR_8(node, PKI_QPG_TBL(PORT_QPG(sc)), val);
sys/arch/octeon/dev/if_ogx.c
515
val = (uint64_t)PORT_QPG(sc) << PKI_CL_STYLE_CFG_QPG_BASE_S;
sys/arch/octeon/dev/if_ogx.c
516
PKI_WR_8(node, PKI_CL_STYLE_CFG(cl, PORT_STYLE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
520
val = PKI_RD_8(node, PKI_CL_PKIND_STYLE(cl, PORT_PKIND(sc)));
sys/arch/octeon/dev/if_ogx.c
521
val &= ~PKI_CL_PKIND_STYLE_PM_M;
sys/arch/octeon/dev/if_ogx.c
522
val &= ~PKI_CL_PKIND_STYLE_STYLE_M;
sys/arch/octeon/dev/if_ogx.c
523
val |= PORT_STYLE(sc) << PKI_CL_PKIND_STYLE_STYLE_S;
sys/arch/octeon/dev/if_ogx.c
524
PKI_WR_8(node, PKI_CL_PKIND_STYLE(cl, PORT_PKIND(sc)), val);
sys/arch/octeon/dev/if_ogx.c
527
val = 5ULL << PKI_STYLE_BUF_FIRST_SKIP_S;
sys/arch/octeon/dev/if_ogx.c
528
val |= ((MCLBYTES - CACHELINESIZE) / sizeof(uint64_t)) <<
sys/arch/octeon/dev/if_ogx.c
530
PKI_WR_8(node, PKI_STYLE_BUF(PORT_STYLE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
545
val = PKO3_RD_8(node, PKO3_L3_L2_SQ_CHANNEL(L2_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
546
val &= ~PKO3_L3_L2_SQ_CHANNEL_CC_ENABLE;
sys/arch/octeon/dev/if_ogx.c
547
val &= ~PKO3_L3_L2_SQ_CHANNEL_M;
sys/arch/octeon/dev/if_ogx.c
548
val |= (uint64_t)sc->sc_ipdport << PKO3_L3_L2_SQ_CHANNEL_S;
sys/arch/octeon/dev/if_ogx.c
549
PKO3_WR_8(node, PKO3_L3_L2_SQ_CHANNEL(L2_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
551
val = PKO3_RD_8(node, PKO3_MAC_CFG(PORT_MAC(sc)));
sys/arch/octeon/dev/if_ogx.c
552
val &= ~PKO3_MAC_CFG_MIN_PAD_ENA;
sys/arch/octeon/dev/if_ogx.c
553
val &= ~PKO3_MAC_CFG_FCS_ENA;
sys/arch/octeon/dev/if_ogx.c
554
val &= ~PKO3_MAC_CFG_FCS_SOP_OFF_M;
sys/arch/octeon/dev/if_ogx.c
555
val &= ~PKO3_MAC_CFG_FIFO_NUM_M;
sys/arch/octeon/dev/if_ogx.c
556
val |= PORT_FIFO(sc) << PKO3_MAC_CFG_FIFO_NUM_S;
sys/arch/octeon/dev/if_ogx.c
557
PKO3_WR_8(node, PKO3_MAC_CFG(PORT_MAC(sc)), val);
sys/arch/octeon/dev/if_ogx.c
559
val = PKO3_RD_8(node, PKO3_MAC_CFG(PORT_MAC(sc)));
sys/arch/octeon/dev/if_ogx.c
560
val &= ~PKO3_MAC_CFG_SKID_MAX_CNT_M;
sys/arch/octeon/dev/if_ogx.c
561
PKO3_WR_8(node, PKO3_MAC_CFG(PORT_MAC(sc)), val);
sys/arch/octeon/dev/if_ogx.c
568
val = (uint64_t)PORT_MAC(sc) << PKO3_L1_SQ_TOPOLOGY_LINK_S;
sys/arch/octeon/dev/if_ogx.c
569
PKO3_WR_8(node, PKO3_L1_SQ_TOPOLOGY(L1_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
571
val = (uint64_t)PORT_MAC(sc) << PKO3_L1_SQ_SHAPE_LINK_S;
sys/arch/octeon/dev/if_ogx.c
572
PKO3_WR_8(node, PKO3_L1_SQ_SHAPE(L1_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
574
val = (uint64_t)PORT_MAC(sc) << PKO3_L1_SQ_LINK_LINK_S;
sys/arch/octeon/dev/if_ogx.c
575
PKO3_WR_8(node, PKO3_L1_SQ_LINK(L1_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
579
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
580
PKO3_WR_8(node, PKO3_L1_SQ_SCHEDULE(L1_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
582
val = PKO3_RD_8(node, PKO3_L1_SQ_TOPOLOGY(L1_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
583
val &= ~PKO3_L1_SQ_TOPOLOGY_PRIO_ANCHOR_M;
sys/arch/octeon/dev/if_ogx.c
584
val &= ~PKO3_L1_SQ_TOPOLOGY_RR_PRIO_M;
sys/arch/octeon/dev/if_ogx.c
585
val |= (uint64_t)L2_QUEUE(sc) << PKO3_L1_SQ_TOPOLOGY_PRIO_ANCHOR_S;
sys/arch/octeon/dev/if_ogx.c
586
val |= (uint64_t)0xf << PKO3_L1_SQ_TOPOLOGY_RR_PRIO_S;
sys/arch/octeon/dev/if_ogx.c
587
PKO3_WR_8(node, PKO3_L1_SQ_TOPOLOGY(L1_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
591
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
592
PKO3_WR_8(node, PKO3_L2_SQ_SCHEDULE(L2_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
594
val = PKO3_RD_8(node, PKO3_L2_SQ_TOPOLOGY(L2_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
595
val &= ~PKO3_L2_SQ_TOPOLOGY_PRIO_ANCHOR_M;
sys/arch/octeon/dev/if_ogx.c
596
val &= ~PKO3_L2_SQ_TOPOLOGY_PARENT_M;
sys/arch/octeon/dev/if_ogx.c
597
val &= ~PKO3_L2_SQ_TOPOLOGY_RR_PRIO_M;
sys/arch/octeon/dev/if_ogx.c
598
val |= (uint64_t)L3_QUEUE(sc) << PKO3_L2_SQ_TOPOLOGY_PRIO_ANCHOR_S;
sys/arch/octeon/dev/if_ogx.c
599
val |= (uint64_t)L1_QUEUE(sc) << PKO3_L2_SQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
600
val |= (uint64_t)0xf << PKO3_L2_SQ_TOPOLOGY_RR_PRIO_S;
sys/arch/octeon/dev/if_ogx.c
601
PKO3_WR_8(node, PKO3_L2_SQ_TOPOLOGY(L2_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
607
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
608
PKO3_WR_8(node, PKO3_L3_SQ_SCHEDULE(L3_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
610
val = PKO3_RD_8(node, PKO3_L3_SQ_TOPOLOGY(L3_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
611
val &= ~PKO3_L3_SQ_TOPOLOGY_PRIO_ANCHOR_M;
sys/arch/octeon/dev/if_ogx.c
612
val &= ~PKO3_L3_SQ_TOPOLOGY_PARENT_M;
sys/arch/octeon/dev/if_ogx.c
613
val &= ~PKO3_L3_SQ_TOPOLOGY_RR_PRIO_M;
sys/arch/octeon/dev/if_ogx.c
614
val |= (uint64_t)DESC_QUEUE(sc) <<
sys/arch/octeon/dev/if_ogx.c
616
val |= (uint64_t)L2_QUEUE(sc) << PKO3_L3_SQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
617
val |= (uint64_t)0xf << PKO3_L3_SQ_TOPOLOGY_RR_PRIO_S;
sys/arch/octeon/dev/if_ogx.c
618
PKO3_WR_8(node, PKO3_L3_SQ_TOPOLOGY(L3_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
622
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
623
PKO3_WR_8(node, PKO3_DQ_SCHEDULE(DESC_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
625
val = (uint64_t)L3_QUEUE(sc) << PKO3_DQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
626
PKO3_WR_8(node, PKO3_DQ_TOPOLOGY(DESC_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
633
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
634
PKO3_WR_8(node, PKO3_L3_SQ_SCHEDULE(L3_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
636
val = PKO3_RD_8(node, PKO3_L3_SQ_TOPOLOGY(L3_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
637
val &= ~PKO3_L3_SQ_TOPOLOGY_PRIO_ANCHOR_M;
sys/arch/octeon/dev/if_ogx.c
638
val &= ~PKO3_L3_SQ_TOPOLOGY_PARENT_M;
sys/arch/octeon/dev/if_ogx.c
639
val &= ~PKO3_L3_SQ_TOPOLOGY_RR_PRIO_M;
sys/arch/octeon/dev/if_ogx.c
640
val |= (uint64_t)L4_QUEUE(sc) <<
sys/arch/octeon/dev/if_ogx.c
642
val |= (uint64_t)L2_QUEUE(sc) << PKO3_L3_SQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
643
val |= (uint64_t)0xf << PKO3_L3_SQ_TOPOLOGY_RR_PRIO_S;
sys/arch/octeon/dev/if_ogx.c
644
PKO3_WR_8(node, PKO3_L3_SQ_TOPOLOGY(L3_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
648
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
649
PKO3_WR_8(node, PKO3_L4_SQ_SCHEDULE(L4_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
651
val = PKO3_RD_8(node, PKO3_L4_SQ_TOPOLOGY(L4_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
652
val &= ~PKO3_L4_SQ_TOPOLOGY_PRIO_ANCHOR_M;
sys/arch/octeon/dev/if_ogx.c
653
val &= ~PKO3_L4_SQ_TOPOLOGY_PARENT_M;
sys/arch/octeon/dev/if_ogx.c
654
val &= ~PKO3_L4_SQ_TOPOLOGY_RR_PRIO_M;
sys/arch/octeon/dev/if_ogx.c
655
val |= (uint64_t)L5_QUEUE(sc) <<
sys/arch/octeon/dev/if_ogx.c
657
val |= (uint64_t)L3_QUEUE(sc) << PKO3_L4_SQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
658
val |= (uint64_t)0xf << PKO3_L4_SQ_TOPOLOGY_RR_PRIO_S;
sys/arch/octeon/dev/if_ogx.c
659
PKO3_WR_8(node, PKO3_L4_SQ_TOPOLOGY(L4_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
663
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
664
PKO3_WR_8(node, PKO3_L5_SQ_SCHEDULE(L5_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
666
val = PKO3_RD_8(node, PKO3_L5_SQ_TOPOLOGY(L5_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
667
val &= ~PKO3_L5_SQ_TOPOLOGY_PRIO_ANCHOR_M;
sys/arch/octeon/dev/if_ogx.c
668
val &= ~PKO3_L5_SQ_TOPOLOGY_PARENT_M;
sys/arch/octeon/dev/if_ogx.c
669
val &= ~PKO3_L5_SQ_TOPOLOGY_RR_PRIO_M;
sys/arch/octeon/dev/if_ogx.c
670
val |= (uint64_t)DESC_QUEUE(sc) <<
sys/arch/octeon/dev/if_ogx.c
672
val |= (uint64_t)L4_QUEUE(sc) << PKO3_L5_SQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
673
val |= (uint64_t)0xf << PKO3_L5_SQ_TOPOLOGY_RR_PRIO_S;
sys/arch/octeon/dev/if_ogx.c
674
PKO3_WR_8(node, PKO3_L5_SQ_TOPOLOGY(L5_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
678
val = (uint64_t)0x10 << PKO3_LX_SQ_SCHEDULE_RR_QUANTUM_S;
sys/arch/octeon/dev/if_ogx.c
679
PKO3_WR_8(node, PKO3_DQ_SCHEDULE(DESC_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
681
val = (uint64_t)L5_QUEUE(sc) << PKO3_DQ_TOPOLOGY_PARENT_S;
sys/arch/octeon/dev/if_ogx.c
682
PKO3_WR_8(node, PKO3_DQ_TOPOLOGY(DESC_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
696
val = PKO3_RD_8(node, PKO3_PDM_DQ_MINPAD(DESC_QUEUE(sc)));
sys/arch/octeon/dev/if_ogx.c
697
val &= ~PKO3_PDM_DQ_MINPAD_MINPAD;
sys/arch/octeon/dev/if_ogx.c
698
PKO3_WR_8(node, PKO3_PDM_DQ_MINPAD(DESC_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
701
val = PKO3_LUT_VALID | (L1_QUEUE(sc) << PKO3_LUT_PQ_IDX_S) |
sys/arch/octeon/dev/if_ogx.c
703
PKO3_WR_8(node, PKO3_LUT(lut_index), val);
sys/arch/octeon/dev/if_ogx.c
726
uint64_t grprate, val;
sys/arch/octeon/dev/if_ogx.c
738
val = PKO3_RD_8(node, PKO3_PTGF_CFG(fgindex));
sys/arch/octeon/dev/if_ogx.c
739
val &= ~PKO3_PTGF_CFG_RATE_M;
sys/arch/octeon/dev/if_ogx.c
740
val |= grprate << PKO3_PTGF_CFG_RATE_S;
sys/arch/octeon/dev/if_ogx.c
741
PKO3_WR_8(node, PKO3_PTGF_CFG(fgindex), val);
sys/arch/octeon/dev/if_ogx.c
845
uint64_t op, val;
sys/arch/octeon/dev/if_ogx.c
851
val = PKO3_LX_SQ_SW_XOFF_DRAIN;
sys/arch/octeon/dev/if_ogx.c
852
val |= PKO3_LX_SQ_SW_XOFF_DRAIN_NULL_LINK;
sys/arch/octeon/dev/if_ogx.c
853
PKO3_WR_8(node, PKO3_DQ_SW_XOFF(DESC_QUEUE(sc)), val);
sys/arch/octeon/dev/if_ogx.c
870
val = PORT_RD_8(sc, BGX_CMR_CONFIG);
sys/arch/octeon/dev/if_ogx.c
871
val &= ~BGX_CMR_CONFIG_DATA_PKT_RX_EN;
sys/arch/octeon/dev/if_ogx.c
872
val &= ~BGX_CMR_CONFIG_DATA_PKT_TX_EN;
sys/arch/octeon/dev/if_ogx.c
873
PORT_WR_8(sc, BGX_CMR_CONFIG, val);
sys/arch/octeon/dev/if_ogx.c
902
uint64_t val;
sys/arch/octeon/dev/if_ogx.c
928
val = BGX_CMR_RX_ADR_CAM_EN | ((uint64_t)sc->sc_lmacid
sys/arch/octeon/dev/if_ogx.c
931
val |= (uint64_t)ac->ac_enaddr[i] <<
sys/arch/octeon/dev/if_ogx.c
934
NEXUS_WR_8(sc, BGX_CMR_RX_ADR_CAM(cidx++), val);
sys/arch/octeon/dev/if_ogx.c
940
val = BGX_CMR_RX_ADR_CAM_EN | ((uint64_t)sc->sc_lmacid
sys/arch/octeon/dev/if_ogx.c
943
val |= (uint64_t)enm->enm_addrlo[i] << (i * 8);
sys/arch/octeon/dev/if_ogx.c
945
NEXUS_WR_8(sc, BGX_CMR_RX_ADR_CAM(cidx++), val);
sys/arch/octeon/dev/octcf.c
156
#define OCTCF_REG_WRITE(wd, reg, val) \
sys/arch/octeon/dev/octcf.c
157
bus_space_write_2(wd->sc_iot, wd->sc_ioh, reg & 0x6, val)
sys/arch/octeon/dev/octcib.c
227
uint64_t val;
sys/arch/octeon/dev/octcib.c
254
val = CIB_EN_RD(sc);
sys/arch/octeon/dev/octcib.c
255
val &= ~(1ul << bit);
sys/arch/octeon/dev/octcib.c
256
CIB_EN_WR(sc, val);
sys/arch/octeon/dev/octcib.c
42
#define CIB_EN_WR(sc, val) \
sys/arch/octeon/dev/octcib.c
43
bus_space_write_8((sc)->sc_iot, (sc)->sc_en_ioh, 0, (val))
sys/arch/octeon/dev/octcib.c
46
#define CIB_RAW_WR(sc, val) \
sys/arch/octeon/dev/octcib.c
47
bus_space_write_8((sc)->sc_iot, (sc)->sc_raw_ioh, 0, (val))
sys/arch/octeon/dev/octcit.c
146
uint64_t val;
sys/arch/octeon/dev/octcit.c
166
val = CIU3_RD_8(sc, CIU3_ISC_CTL(intsn));
sys/arch/octeon/dev/octcit.c
167
if (ISSET(val, CIU3_ISC_CTL_IMP)) {
sys/arch/octeon/dev/octcit.c
260
uint64_t val;
sys/arch/octeon/dev/octcit.c
291
val = CIU3_ISC_CTL_EN | (CIU3_IDT(ci->ci_cpuid, 0) <<
sys/arch/octeon/dev/octcit.c
294
CIU3_WR_8(sc, CIU3_ISC_CTL(intsn), val);
sys/arch/octeon/dev/octcit.c
517
uint64_t val;
sys/arch/octeon/dev/octcit.c
524
val = CIU3_ISC_CTL_EN | (CIU3_IDT(cpuid, 1) << CIU3_ISC_CTL_IDT_SHIFT);
sys/arch/octeon/dev/octcit.c
526
CIU3_WR_8(sc, CIU3_ISC_CTL(intsn), val);
sys/arch/octeon/dev/octcit.c
70
#define CIU3_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octcit.c
71
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/octgpio.c
49
#define GPIO_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octgpio.c
50
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/octiic.c
394
octiic_reg_write(struct octiic_softc *sc, uint8_t reg, uint8_t val)
sys/arch/octeon/dev/octiic.c
401
((uint64_t)reg << TWSI_SW_TWSI_EOP_IA_S) | val);
sys/arch/octeon/dev/octiic.c
79
#define TWSI_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octiic.c
80
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/octmmc.c
61
#define MMC_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octmmc.c
62
bus_space_write_8((sc)->sc_iot, (sc)->sc_mmc_ioh, (reg), (val))
sys/arch/octeon/dev/octmmc.c
63
#define DMA_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octmmc.c
64
bus_space_write_8((sc)->sc_iot, (sc)->sc_dma_ioh, (reg), (val))
sys/arch/octeon/dev/octmmc.c
65
#define FIFO_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octmmc.c
66
bus_space_write_8((sc)->sc_iot, (sc)->sc_fifo_ioh, (reg), (val))
sys/arch/octeon/dev/octpcie.c
283
uint64_t val;
sys/arch/octeon/dev/octpcie.c
321
val = bus_space_read_8(sc->sc_iot, sc->sc_sli_ioh, SLI_MEM_ACCESS_CTL);
sys/arch/octeon/dev/octpcie.c
322
val &= ~SLI_MEM_ACCESS_CTL_MAXW_M;
sys/arch/octeon/dev/octpcie.c
323
val &= ~SLI_MEM_ACCESS_CTL_TIMER_M;
sys/arch/octeon/dev/octpcie.c
324
val |= 127 << SLI_MEM_ACCESS_CTL_TIMER_S;
sys/arch/octeon/dev/octpcie.c
325
bus_space_write_8(sc->sc_iot, sc->sc_sli_ioh, SLI_MEM_ACCESS_CTL, val);
sys/arch/octeon/dev/octpcie.c
435
uint64_t val;
sys/arch/octeon/dev/octpcie.c
464
val = octeon_xkphys_read_8(rst_reg);
sys/arch/octeon/dev/octpcie.c
465
octeon_xkphys_write_8(rst_reg, val);
sys/arch/octeon/dev/octpcie.c
470
val &= ~PRST_SOFT_PRST;
sys/arch/octeon/dev/octpcie.c
471
octeon_xkphys_write_8(rst_reg, val);
sys/arch/octeon/dev/octpcie.c
477
val = octeon_xkphys_read_8(ctl_reg);
sys/arch/octeon/dev/octpcie.c
478
if (val & RST_CTL_RST_DONE)
sys/arch/octeon/dev/octpcie.c
504
val = bus_space_read_8(sc->sc_iot, sc->sc_dpi_ioh,
sys/arch/octeon/dev/octpcie.c
506
val &= ~DPI_SLI_PRT_CFG_MPS_M;
sys/arch/octeon/dev/octpcie.c
507
val &= ~DPI_SLI_PRT_CFG_MRRS_M;
sys/arch/octeon/dev/octpcie.c
508
val |= 0 << DPI_SLI_PRT_CFG_MPS_S;
sys/arch/octeon/dev/octpcie.c
509
val |= 3 << DPI_SLI_PRT_CFG_MRRS_S;
sys/arch/octeon/dev/octpcie.c
510
val &= ~DPI_SLI_PRT_CFG_MOLR_M;
sys/arch/octeon/dev/octpcie.c
511
val |= 32 << DPI_SLI_PRT_CFG_MOLR_S;
sys/arch/octeon/dev/octpcie.c
513
DPI_SLI_PRT_CFG(port->port_index), val);
sys/arch/octeon/dev/octpcie.c
517
val = bus_space_read_8(sc->sc_iot, sc->sc_sli_ioh,
sys/arch/octeon/dev/octpcie.c
519
val &= ~SLI_S2M_PORT_CTL_MRRS_M;
sys/arch/octeon/dev/octpcie.c
520
val |= 32 << SLI_S2M_PORT_CTL_MRRS_S;
sys/arch/octeon/dev/octpcie.c
522
SLI_S2M_PORT_CTL(port->port_index), val);
sys/arch/octeon/dev/octpcie.c
589
val = bus_space_read_8(port->port_iot, port->port_pem_ioh,
sys/arch/octeon/dev/octpcie.c
591
val |= PEM_CTL_STATUS_LNK_ENB;
sys/arch/octeon/dev/octpcie.c
593
PEM_CTL_STATUS, val);
sys/arch/octeon/dev/octpcie.c
612
val = (uint64_t)port->port_index << SLI_MEM_ACCESS_SUBID_PORT_S;
sys/arch/octeon/dev/octpcie.c
613
val |= 3ULL << SLI_MEM_ACCESS_SUBID_ESR_S;
sys/arch/octeon/dev/octpcie.c
614
val |= 3ULL << SLI_MEM_ACCESS_SUBID_ESW_S;
sys/arch/octeon/dev/octpcie.c
617
SLI_MEM_ACCESS_SUBID(i + port->port_index * 4), val);
sys/arch/octeon/dev/octpcie.c
618
val += 1ULL << SLI_MEM_ACCESS_SUBID_BA_S;
sys/arch/octeon/dev/octpcie.c
647
val = bus_space_read_8(port->port_iot, port->port_pem_ioh,
sys/arch/octeon/dev/octpcie.c
649
val &= ~PEM_BAR_CTL_BAR1_SIZ_M;
sys/arch/octeon/dev/octpcie.c
650
val |= PEM_BAR_CTL_BAR1_SIZ_256M;
sys/arch/octeon/dev/octpcie.c
651
val |= PEM_BAR_CTL_BAR2_ENB;
sys/arch/octeon/dev/octpcie.c
652
val &= ~PEM_BAR_CTL_BAR2_ESX_M;
sys/arch/octeon/dev/octpcie.c
653
val |= 1UL << PEM_BAR_CTL_BAR2_ESX_S;
sys/arch/octeon/dev/octpcie.c
654
val |= PEM_BAR_CTL_BAR2_CAX;
sys/arch/octeon/dev/octpcie.c
656
PEM_BAR_CTL(cfg), val);
sys/arch/octeon/dev/octpcie.c
851
uint64_t val;
sys/arch/octeon/dev/octpcie.c
854
val = bus_space_read_8(port->port_iot, port->port_pem_ioh, PEM_CFG_RD);
sys/arch/octeon/dev/octpcie.c
856
return (uint32_t)(val >> 32);
sys/arch/octeon/dev/octpcie.c
860
octpcie_cfgreg_write(struct octpcie_port *port, uint32_t off, uint32_t val)
sys/arch/octeon/dev/octpcie.c
863
((uint64_t)val << 32) | off);
sys/arch/octeon/dev/octsctl.c
112
val = bus_space_read_8(sc->sc_iot, sc->sc_ioh, SCTL_SHIM_CFG);
sys/arch/octeon/dev/octsctl.c
113
val &= ~SCTL_SHIM_CFG_CSR_BYTE_SWAP;
sys/arch/octeon/dev/octsctl.c
114
val &= ~SCTL_SHIM_CFG_DMA_BYTE_SWAP;
sys/arch/octeon/dev/octsctl.c
115
val |= 3ul << SCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT;
sys/arch/octeon/dev/octsctl.c
116
val |= 1ul << SCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT;
sys/arch/octeon/dev/octsctl.c
117
val |= SCTL_SHIM_CFG_READ_CMD;
sys/arch/octeon/dev/octsctl.c
118
bus_space_write_8(sc->sc_iot, sc->sc_ioh, SCTL_SHIM_CFG, val);
sys/arch/octeon/dev/octsctl.c
72
uint64_t val;
sys/arch/octeon/dev/octxctl.c
190
uint64_t i, val;
sys/arch/octeon/dev/octxctl.c
200
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
201
val |= XCTL_CTL_UCTL_RST;
sys/arch/octeon/dev/octxctl.c
202
val |= XCTL_CTL_UAHC_RST;
sys/arch/octeon/dev/octxctl.c
203
val |= XCTL_CTL_UPHY_RST;
sys/arch/octeon/dev/octxctl.c
204
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
205
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
206
val |= XCTL_CTL_CLKDIV_RST;
sys/arch/octeon/dev/octxctl.c
207
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
216
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
217
val &= ~XCTL_CTL_CLKDIV_SEL;
sys/arch/octeon/dev/octxctl.c
218
val |= (i << XCTL_CTL_CLKDIV_SEL_SHIFT) & XCTL_CTL_CLKDIV_SEL;
sys/arch/octeon/dev/octxctl.c
219
val |= XCTL_CTL_CLK_EN;
sys/arch/octeon/dev/octxctl.c
220
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
223
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
224
val &= ~XCTL_CTL_CLKDIV_RST;
sys/arch/octeon/dev/octxctl.c
225
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
248
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
249
val &= ~XCTL_CTL_REFCLK_SEL;
sys/arch/octeon/dev/octxctl.c
250
val |= clock_sel << XCTL_CTL_REFCLK_SEL_SHIFT;
sys/arch/octeon/dev/octxctl.c
251
val &= ~XCTL_CTL_REFCLK_DIV2;
sys/arch/octeon/dev/octxctl.c
252
val &= ~XCTL_CTL_REFCLK_FSEL;
sys/arch/octeon/dev/octxctl.c
253
val |= refclk_fsel << XCTL_CTL_REFCLK_FSEL_SHIFT;
sys/arch/octeon/dev/octxctl.c
254
val &= ~XCTL_CTL_MPLL_MULT;
sys/arch/octeon/dev/octxctl.c
255
val |= mpll_mult << XCTL_CTL_MPLL_MULT_SHIFT;
sys/arch/octeon/dev/octxctl.c
256
val |= XCTL_CTL_SSC_EN;
sys/arch/octeon/dev/octxctl.c
257
val |= XCTL_CTL_REFCLK_SSP_EN;
sys/arch/octeon/dev/octxctl.c
258
val |= XCTL_CTL_SSPOWER_EN;
sys/arch/octeon/dev/octxctl.c
259
val |= XCTL_CTL_HSPOWER_EN;
sys/arch/octeon/dev/octxctl.c
260
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
265
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
266
val &= ~XCTL_CTL_UCTL_RST;
sys/arch/octeon/dev/octxctl.c
267
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
280
val = XCTL_RD_8(sc, XCTL_HOST_CFG);
sys/arch/octeon/dev/octxctl.c
281
val |= XCTL_HOST_CFG_PPC_EN;
sys/arch/octeon/dev/octxctl.c
283
val &= ~XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
sys/arch/octeon/dev/octxctl.c
285
val |= XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN;
sys/arch/octeon/dev/octxctl.c
286
XCTL_WR_8(sc, XCTL_HOST_CFG, val);
sys/arch/octeon/dev/octxctl.c
289
val = XCTL_RD_8(sc, XCTL_HOST_CFG);
sys/arch/octeon/dev/octxctl.c
290
val &= ~XCTL_HOST_CFG_PPC_EN;
sys/arch/octeon/dev/octxctl.c
291
XCTL_WR_8(sc, XCTL_HOST_CFG, val);
sys/arch/octeon/dev/octxctl.c
295
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
296
val &= ~XCTL_CTL_DRD_MODE;
sys/arch/octeon/dev/octxctl.c
297
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
302
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
303
val &= ~XCTL_CTL_UAHC_RST;
sys/arch/octeon/dev/octxctl.c
304
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
308
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
309
val |= XCTL_CTL_CSCLK_EN;
sys/arch/octeon/dev/octxctl.c
310
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
313
val = XCTL_RD_8(sc, XCTL_CTL);
sys/arch/octeon/dev/octxctl.c
314
val &= ~XCTL_CTL_UPHY_RST;
sys/arch/octeon/dev/octxctl.c
315
XCTL_WR_8(sc, XCTL_CTL, val);
sys/arch/octeon/dev/octxctl.c
319
val = XCTL_RD_8(sc, XCTL_SHIM_CFG);
sys/arch/octeon/dev/octxctl.c
320
val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP;
sys/arch/octeon/dev/octxctl.c
321
val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP;
sys/arch/octeon/dev/octxctl.c
322
val |= 3ull << XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT;
sys/arch/octeon/dev/octxctl.c
323
val |= 1ull << XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT;
sys/arch/octeon/dev/octxctl.c
324
XCTL_WR_8(sc, XCTL_SHIM_CFG, val);
sys/arch/octeon/dev/octxctl.c
333
uint32_t val;
sys/arch/octeon/dev/octxctl.c
341
val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GSNPSID);
sys/arch/octeon/dev/octxctl.c
342
if ((val & 0xffff0000u) != 0x55330000u) {
sys/arch/octeon/dev/octxctl.c
347
rev = val & 0xffffu;
sys/arch/octeon/dev/octxctl.c
350
val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GUSB3PIPECTL(0));
sys/arch/octeon/dev/octxctl.c
351
val &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
sys/arch/octeon/dev/octxctl.c
352
val |= DWC3_GUSB3PIPECTL_SUSPHY;
sys/arch/octeon/dev/octxctl.c
353
bus_space_write_4(sc->sc_iot, ioh, DWC3_GUSB3PIPECTL(0), val);
sys/arch/octeon/dev/octxctl.c
355
val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GUSB2PHYCFG(0));
sys/arch/octeon/dev/octxctl.c
356
val |= DWC3_GUSB2PHYCFG_SUSPHY;
sys/arch/octeon/dev/octxctl.c
357
bus_space_write_4(sc->sc_iot, ioh, DWC3_GUSB2PHYCFG(0), val);
sys/arch/octeon/dev/octxctl.c
360
val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GCTL);
sys/arch/octeon/dev/octxctl.c
361
val &= ~DWC3_GCTL_PRTCAP_MASK;
sys/arch/octeon/dev/octxctl.c
362
val |= DWC3_GCTL_PRTCAP_HOST;
sys/arch/octeon/dev/octxctl.c
363
bus_space_write_4(sc->sc_iot, ioh, DWC3_GCTL, val);
sys/arch/octeon/dev/octxctl.c
365
val = bus_space_read_4(sc->sc_iot, ioh, DWC3_GCTL);
sys/arch/octeon/dev/octxctl.c
366
val &= ~DWC3_GCTL_SCALEDOWN_MASK;
sys/arch/octeon/dev/octxctl.c
367
val &= ~DWC3_GCTL_DISSCRAMBLE;
sys/arch/octeon/dev/octxctl.c
369
val |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
sys/arch/octeon/dev/octxctl.c
371
val &= ~DWC3_GCTL_DSBLCLKGTNG;
sys/arch/octeon/dev/octxctl.c
372
bus_space_write_4(sc->sc_iot, ioh, DWC3_GCTL, val);
sys/arch/octeon/dev/octxctl.c
40
#define XCTL_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octxctl.c
41
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/ogxnexus.c
45
#define NEXUS_WR_8(sc, reg, val) \
sys/arch/octeon/dev/ogxnexus.c
46
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/include/octeonvar.h
453
octeon_set_cvmmemctl(uint64_t val)
sys/arch/octeon/include/octeonvar.h
459
: : [tmp]"r"(val) : "memory");
sys/arch/octeon/include/pci_machdep.h
103
tag, reg, val);
sys/arch/octeon/include/pci_machdep.h
104
(*(pc)->pc_conf_write)(pc->pc_conf_v, tag, reg, val);
sys/arch/octeon/include/pci_machdep.h
88
pcireg_t val;
sys/arch/octeon/include/pci_machdep.h
90
val = (*(pc)->pc_conf_read)(pc->pc_conf_v, tag, reg);
sys/arch/octeon/include/pci_machdep.h
92
tag, reg, val);
sys/arch/octeon/include/pci_machdep.h
93
return val;
sys/arch/octeon/include/pci_machdep.h
97
pci_conf_write_db(void *cookie, pcitag_t tag, int reg, pcireg_t val,
sys/arch/octeon/octeon/machdep.c
706
uint64_t clk_reg, cvmmemctl, frac, cmul, imul, val;
sys/arch/octeon/octeon/machdep.c
756
val = octeon_xkphys_read_8(MIO_RST_BOOT);
sys/arch/octeon/octeon/machdep.c
757
cmul = (val >> MIO_RST_BOOT_C_MUL_SHIFT) &
sys/arch/octeon/octeon/machdep.c
759
imul = (val >> MIO_RST_BOOT_PNR_MUL_SHIFT) &
sys/arch/octeon/octeon/machdep.c
763
val = octeon_xkphys_read_8(RST_BOOT);
sys/arch/octeon/octeon/machdep.c
764
cmul = (val >> RST_BOOT_C_MUL_SHIFT) &
sys/arch/octeon/octeon/machdep.c
766
imul = (val >> RST_BOOT_PNR_MUL_SHIFT) &
sys/arch/powerpc/include/_types.h
40
long val[25];
sys/arch/powerpc/include/cpu.h
268
static __inline void ppc_mt ## name(u_int32_t val) \
sys/arch/powerpc/include/cpu.h
270
__asm volatile ("mtspr "# n ",%0" :: "r" (val)); \
sys/arch/powerpc/include/cpu.h
370
ppc_mtmsr(u_int32_t val)
sys/arch/powerpc/include/cpu.h
372
__asm volatile ("mtmsr %0" :: "r" (val));
sys/arch/powerpc/include/cpu.h
376
ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted)
sys/arch/powerpc/include/cpu.h
378
__asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted));
sys/arch/powerpc/powerpc/bus_space.c
297
u_int8_t val, bus_size_t c)
sys/arch/powerpc/powerpc/bus_space.c
305
dst[i] = val;
sys/arch/powerpc/powerpc/bus_space.c
310
u_int16_t val, bus_size_t c)
sys/arch/powerpc/powerpc/bus_space.c
316
val = swap16(val);
sys/arch/powerpc/powerpc/bus_space.c
319
dst[i] = val;
sys/arch/powerpc/powerpc/bus_space.c
323
u_int32_t val, bus_size_t c)
sys/arch/powerpc/powerpc/bus_space.c
329
val = swap32(val);
sys/arch/powerpc/powerpc/bus_space.c
332
dst[i] = val;
sys/arch/powerpc/powerpc/cpu_subr.c
100
__asm volatile ("mtspr 276,%0; isync" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
105
ppc_mtscomd(u_int32_t val)
sys/arch/powerpc/powerpc/cpu_subr.c
110
__asm volatile ("mtspr 277,%0; isync" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
128
ppc64_mtscomc(u_int64_t val)
sys/arch/powerpc/powerpc/cpu_subr.c
134
" mtspr 276,%0; isync" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
192
ppc_mthid0(u_int32_t val)
sys/arch/powerpc/powerpc/cpu_subr.c
199
return ppc64_mthid0(val, lo);
sys/arch/powerpc/powerpc/cpu_subr.c
202
__asm volatile ("mtspr 1008,%0; isync" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
216
ppc64_mthid1(u_int64_t val)
sys/arch/powerpc/powerpc/cpu_subr.c
219
"mtspr 1009,%0; mtspr 1009,%0; isync;" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
233
ppc64_mthid4(u_int64_t val)
sys/arch/powerpc/powerpc/cpu_subr.c
236
"sync; mtspr 1012,%0; isync;" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
250
ppc64_mthid5(u_int64_t val)
sys/arch/powerpc/powerpc/cpu_subr.c
253
"sync; mtspr 1014,%0; isync;" :: "r" (val));
sys/arch/powerpc/powerpc/cpu_subr.c
95
ppc_mtscomc(u_int32_t val)
sys/arch/powerpc64/dev/xicp.c
71
xicp_write_1(struct xicp_softc *sc, bus_size_t off, uint8_t val)
sys/arch/powerpc64/dev/xicp.c
73
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
sys/arch/powerpc64/dev/xicp.c
83
xicp_write_4(struct xicp_softc *sc, bus_size_t off, uint32_t val)
sys/arch/powerpc64/dev/xicp.c
85
bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
sys/arch/powerpc64/dev/xive.c
122
xive_write_1(struct xive_softc *sc, bus_size_t off, uint8_t val)
sys/arch/powerpc64/dev/xive.c
124
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
sys/arch/powerpc64/include/_types.h
39
long val[22];
sys/arch/powerpc64/powerpc64/db_interface.c
109
if (db_symbol_by_name("db_machine_init", &val) != NULL) {
sys/arch/powerpc64/powerpc64/db_interface.c
116
offset = (Elf_Addr)db_machine_init - (Elf_Addr)val;
sys/arch/powerpc64/powerpc64/db_interface.c
83
db_expr_t val;
sys/arch/powerpc64/powerpc64/intr.c
259
void *val = NULL;
sys/arch/powerpc64/powerpc64/intr.c
312
val = ic->ic_establish(ic->ic_cookie, cell, level,
sys/arch/powerpc64/powerpc64/intr.c
323
if (val == NULL)
sys/arch/powerpc64/powerpc64/intr.c
328
ih->ih_ih = val;
sys/arch/powerpc64/powerpc64/intr.c
350
void *val = NULL;
sys/arch/powerpc64/powerpc64/intr.c
384
val = ic->ic_establish(ic->ic_cookie, &cell[5 + acells],
sys/arch/powerpc64/powerpc64/intr.c
393
if (val == NULL) {
sys/arch/powerpc64/powerpc64/intr.c
400
ih->ih_ih = val;
sys/arch/riscv64/dev/aplic.c
51
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/aplic.c
52
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/if_smte.c
1029
uint32_t val;
sys/arch/riscv64/dev/if_smte.c
1033
val = MAC_ADDR_CTRL_MAC_ADDR1_ENABLE;
sys/arch/riscv64/dev/if_smte.c
1039
val |= MAC_ADDR_CTRL_PROMISCUOUS_MODE;
sys/arch/riscv64/dev/if_smte.c
1061
HWRITE4(sc, MAC_ADDR_CTRL, val);
sys/arch/riscv64/dev/if_smte.c
181
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/if_smte.c
182
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/if_smte.c
442
uint32_t val;
sys/arch/riscv64/dev/if_smte.c
454
val = regmap_read_4(sc->sc_apmu,
sys/arch/riscv64/dev/if_smte.c
456
val |= APMU_EMAC_AXI_MST_ID;
sys/arch/riscv64/dev/if_smte.c
458
sc->sc_apmu_offset + APMU_EMAC_CLK_RST_CTRL, val);
sys/arch/riscv64/dev/if_smte.c
465
val = regmap_read_4(sc->sc_apmu,
sys/arch/riscv64/dev/if_smte.c
467
val = APMU_EMAC_RGMII_DLINE_RX_EN | APMU_EMAC_RGMII_DLINE_TX_EN;
sys/arch/riscv64/dev/if_smte.c
468
val &= ~APMU_EMAC_RGMII_DLINE_RX_STEP_MASK;
sys/arch/riscv64/dev/if_smte.c
469
val &= ~APMU_EMAC_RGMII_DLINE_RX_DELAY_MASK;
sys/arch/riscv64/dev/if_smte.c
470
val |= APMU_EMAC_RGMII_DLINE_RX_STEP_15P6;
sys/arch/riscv64/dev/if_smte.c
471
val |= rx_delay << APMU_EMAC_RGMII_DLINE_RX_DELAY_SHIFT;
sys/arch/riscv64/dev/if_smte.c
472
val &= ~APMU_EMAC_RGMII_DLINE_TX_STEP_MASK;
sys/arch/riscv64/dev/if_smte.c
473
val &= ~APMU_EMAC_RGMII_DLINE_TX_DELAY_MASK;
sys/arch/riscv64/dev/if_smte.c
474
val |= APMU_EMAC_RGMII_DLINE_TX_STEP_15P6;
sys/arch/riscv64/dev/if_smte.c
475
val |= tx_delay << APMU_EMAC_RGMII_DLINE_TX_DELAY_SHIFT;
sys/arch/riscv64/dev/if_smte.c
477
sc->sc_apmu_offset + APMU_EMAC_RGMII_DLINE, val);
sys/arch/riscv64/dev/if_smte.c
673
smte_mii_writereg(struct device *self, int phy, int reg, int val)
sys/arch/riscv64/dev/if_smte.c
679
HWRITE4(sc, MAC_MDIO_DATA, val);
sys/arch/riscv64/dev/imsic.c
192
imsic_csr_write(uint64_t reg, uint64_t val)
sys/arch/riscv64/dev/imsic.c
195
csr_write(sireg, val);
sys/arch/riscv64/dev/imsic.c
42
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/imsic.c
43
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/mpfclock.c
202
uint32_t bit, val;
sys/arch/riscv64/dev/mpfclock.c
210
val = HREAD4(sc, SUBBLK_CLOCK_CR);
sys/arch/riscv64/dev/mpfclock.c
211
val |= bit;
sys/arch/riscv64/dev/mpfclock.c
212
HWRITE4(sc, SUBBLK_CLOCK_CR, val);
sys/arch/riscv64/dev/mpfclock.c
214
val = HREAD4(sc, SUBBLK_RESET_CR);
sys/arch/riscv64/dev/mpfclock.c
215
val &= ~bit;
sys/arch/riscv64/dev/mpfclock.c
216
HWRITE4(sc, SUBBLK_RESET_CR, val);
sys/arch/riscv64/dev/mpfclock.c
218
val = HREAD4(sc, SUBBLK_RESET_CR);
sys/arch/riscv64/dev/mpfclock.c
219
val |= bit;
sys/arch/riscv64/dev/mpfclock.c
220
HWRITE4(sc, SUBBLK_RESET_CR, val);
sys/arch/riscv64/dev/mpfclock.c
222
val = HREAD4(sc, SUBBLK_CLOCK_CR);
sys/arch/riscv64/dev/mpfclock.c
223
val &= ~bit;
sys/arch/riscv64/dev/mpfclock.c
224
HWRITE4(sc, SUBBLK_CLOCK_CR, val);
sys/arch/riscv64/dev/mpfclock.c
92
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/mpfclock.c
93
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/mpfgpio.c
153
uint32_t val;
sys/arch/riscv64/dev/mpfgpio.c
158
val = HREAD4(sc, MPFGPIO_CONFIG(pin));
sys/arch/riscv64/dev/mpfgpio.c
160
val &= ~MPFGPIO_CONFIG_EN_IN;
sys/arch/riscv64/dev/mpfgpio.c
161
val |= MPFGPIO_CONFIG_EN_OUT;
sys/arch/riscv64/dev/mpfgpio.c
163
val |= MPFGPIO_CONFIG_EN_IN;
sys/arch/riscv64/dev/mpfgpio.c
164
val &= ~MPFGPIO_CONFIG_EN_OUT;
sys/arch/riscv64/dev/mpfgpio.c
166
val &= ~MPFGPIO_CONFIG_EN_INT;
sys/arch/riscv64/dev/mpfgpio.c
167
HWRITE4(sc, MPFGPIO_CONFIG(pin), val);
sys/arch/riscv64/dev/mpfgpio.c
178
int val;
sys/arch/riscv64/dev/mpfgpio.c
183
val = (HREAD4(sc, MPFGPIO_GPIN) >> pin) & 1;
sys/arch/riscv64/dev/mpfgpio.c
185
val = !val;
sys/arch/riscv64/dev/mpfgpio.c
186
return val;
sys/arch/riscv64/dev/mpfgpio.c
190
mpfgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/riscv64/dev/mpfgpio.c
200
val = !val;
sys/arch/riscv64/dev/mpfgpio.c
201
if (val)
sys/arch/riscv64/dev/mpfgpio.c
221
mpfgpio_pin_write(void *cookie, int pin, int val)
sys/arch/riscv64/dev/mpfgpio.c
229
mpfgpio_set_pin(sc, cells, val);
sys/arch/riscv64/dev/mpfgpio.c
67
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/mpfgpio.c
68
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/mpfiic.c
83
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/mpfiic.c
84
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/plic.c
697
uint32_t val, mask;
sys/arch/riscv64/dev/plic.c
705
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/arch/riscv64/dev/plic.c
708
val |= mask;
sys/arch/riscv64/dev/plic.c
710
val &= ~mask;
sys/arch/riscv64/dev/plic.c
713
PLIC_ENABLE(sc, irq, cpu), val);
sys/arch/riscv64/dev/sfclock.c
55
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sfclock.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sfgpio.c
183
int val;
sys/arch/riscv64/dev/sfgpio.c
189
val = (reg >> pin) & 1;
sys/arch/riscv64/dev/sfgpio.c
191
val = !val;
sys/arch/riscv64/dev/sfgpio.c
192
return val;
sys/arch/riscv64/dev/sfgpio.c
196
sfgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/riscv64/dev/sfgpio.c
206
val = !val;
sys/arch/riscv64/dev/sfgpio.c
207
if (val)
sys/arch/riscv64/dev/sfgpio.c
55
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sfgpio.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sfuart.c
196
uint32_t val;
sys/arch/riscv64/dev/sfuart.c
212
val = HREAD4(sc, UART_RXDATA);
sys/arch/riscv64/dev/sfuart.c
213
while (!ISSET(val, UART_RXDATA_EMPTY)) {
sys/arch/riscv64/dev/sfuart.c
214
c = val & 0xff;
sys/arch/riscv64/dev/sfuart.c
221
val = HREAD4(sc, UART_RXDATA);
sys/arch/riscv64/dev/sfuart.c
60
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sfuart.c
601
uint32_t val;
sys/arch/riscv64/dev/sfuart.c
604
val = bus_space_read_4(sfuartconsiot, sfuartconsioh, UART_RXDATA);
sys/arch/riscv64/dev/sfuart.c
605
if (val & UART_RXDATA_EMPTY)
sys/arch/riscv64/dev/sfuart.c
607
} while ((val & UART_RXDATA_EMPTY));
sys/arch/riscv64/dev/sfuart.c
609
return (val & 0xff);
sys/arch/riscv64/dev/sfuart.c
61
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtclock.c
266
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtclock.c
267
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtclock.c
734
uint32_t mask, val;
sys/arch/riscv64/dev/smtclock.c
771
val = HREAD4(sc, reset->reg) & ~mask;
sys/arch/riscv64/dev/smtclock.c
773
val |= assert_mask;
sys/arch/riscv64/dev/smtclock.c
775
val |= deassert_mask;
sys/arch/riscv64/dev/smtclock.c
776
HWRITE4(sc, reset->reg, val);
sys/arch/riscv64/dev/smtcomphy.c
168
uint32_t apmu, val;
sys/arch/riscv64/dev/smtcomphy.c
178
val = regmap_read_4(sc->sc_apmu, APMU_PCIE_CLK_RES_CTRL_PORTA);
sys/arch/riscv64/dev/smtcomphy.c
179
val &= ~APMU_PCIE_APP_HOLD_PHY_RST;
sys/arch/riscv64/dev/smtcomphy.c
180
regmap_write_4(sc->sc_apmu, APMU_PCIE_CLK_RES_CTRL_PORTA, val);
sys/arch/riscv64/dev/smtcomphy.c
182
val = HREAD4(sc, PCIE_RCAL_RESULT);
sys/arch/riscv64/dev/smtcomphy.c
183
if ((val & R_TUNE_DONE) == 0) {
sys/arch/riscv64/dev/smtcomphy.c
190
val = regmap_read_4(sc->sc_apmu, APMU_PMUA_USB_PHY_CTRL0);
sys/arch/riscv64/dev/smtcomphy.c
191
val &= ~APMU_COMBO_PHY_SEL;
sys/arch/riscv64/dev/smtcomphy.c
192
regmap_write_4(sc->sc_apmu, APMU_PMUA_USB_PHY_CTRL0, val);
sys/arch/riscv64/dev/smtcomphy.c
202
val = HREAD4(sc, PCIE_RCAL_RESULT);
sys/arch/riscv64/dev/smtcomphy.c
203
if (val & R_TUNE_DONE)
sys/arch/riscv64/dev/smtcomphy.c
215
if (val & R_TUNE_DONE) {
sys/arch/riscv64/dev/smtcomphy.c
220
rx_rterm = RTERM_VALUE_RX(val);
sys/arch/riscv64/dev/smtcomphy.c
221
tx_rterm = RTERM_VALUE_TX(val);
sys/arch/riscv64/dev/smtcomphy.c
232
uint32_t val;
sys/arch/riscv64/dev/smtcomphy.c
235
val = HREAD4(sc, PCIE_PU_PLL_1);
sys/arch/riscv64/dev/smtcomphy.c
236
val &= ~REF_100_WSSC;
sys/arch/riscv64/dev/smtcomphy.c
237
val &= ~FREF_SEL_MASK;
sys/arch/riscv64/dev/smtcomphy.c
238
val |= FREF_SEL_24M;
sys/arch/riscv64/dev/smtcomphy.c
239
HWRITE4(sc, PCIE_PU_PLL_1, val);
sys/arch/riscv64/dev/smtcomphy.c
242
val = HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(lane));
sys/arch/riscv64/dev/smtcomphy.c
243
val |= CFG_SW_PHY_INIT_DONE;
sys/arch/riscv64/dev/smtcomphy.c
244
HWRITE4(sc, PCIE_PU_ADDR_CLK_CFG(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
259
uint32_t val;
sys/arch/riscv64/dev/smtcomphy.c
261
val = HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(0));
sys/arch/riscv64/dev/smtcomphy.c
262
val &= ~CFG_INTERNAL_TIMER_ADJ_MASK;
sys/arch/riscv64/dev/smtcomphy.c
263
val |= CFG_INTERNAL_TIMER_ADJ_USB3;
sys/arch/riscv64/dev/smtcomphy.c
264
HWRITE4(sc, PCIE_PU_ADDR_CLK_CFG(0), val);
sys/arch/riscv64/dev/smtcomphy.c
266
val = HREAD4(sc, PCIE_PU_PLL_1);
sys/arch/riscv64/dev/smtcomphy.c
267
val &= ~SSC_DEP_SEL_MASK;
sys/arch/riscv64/dev/smtcomphy.c
268
val |= SSC_DEP_SEL_5000PPM;
sys/arch/riscv64/dev/smtcomphy.c
269
HWRITE4(sc, PCIE_PU_PLL_1, val);
sys/arch/riscv64/dev/smtcomphy.c
277
uint32_t val;
sys/arch/riscv64/dev/smtcomphy.c
281
val = HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(lane));
sys/arch/riscv64/dev/smtcomphy.c
282
val &= ~CFG_INTERNAL_TIMER_ADJ_MASK;
sys/arch/riscv64/dev/smtcomphy.c
283
val |= CFG_INTERNAL_TIMER_ADJ_PCIE;
sys/arch/riscv64/dev/smtcomphy.c
284
HWRITE4(sc, PCIE_PU_ADDR_CLK_CFG(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
287
val = HREAD4(sc, PCIE_RC_DONE_STATUS);
sys/arch/riscv64/dev/smtcomphy.c
288
val |= CFG_FORCE_RCV_RETRY;
sys/arch/riscv64/dev/smtcomphy.c
289
HWRITE4(sc, PCIE_RC_DONE_STATUS, val);
sys/arch/riscv64/dev/smtcomphy.c
291
val = HREAD4(sc, PCIE_PU_PLL_1);
sys/arch/riscv64/dev/smtcomphy.c
292
val &= ~SSC_DEP_SEL_MASK;
sys/arch/riscv64/dev/smtcomphy.c
293
val |= SSC_DEP_SEL_NONE;
sys/arch/riscv64/dev/smtcomphy.c
294
HWRITE4(sc, PCIE_PU_PLL_1, val);
sys/arch/riscv64/dev/smtcomphy.c
296
val = HREAD4(sc, PCIE_PU_PLL_2);
sys/arch/riscv64/dev/smtcomphy.c
297
val |= GEN_REF100;
sys/arch/riscv64/dev/smtcomphy.c
298
HWRITE4(sc, PCIE_PU_PLL_2, val);
sys/arch/riscv64/dev/smtcomphy.c
308
uint32_t val, oval;
sys/arch/riscv64/dev/smtcomphy.c
318
val = oval = regmap_read_4(sc->sc_apmu, APMU_PMUA_USB_PHY_CTRL0);
sys/arch/riscv64/dev/smtcomphy.c
320
val |= APMU_COMBO_PHY_SEL;
sys/arch/riscv64/dev/smtcomphy.c
322
val &= ~APMU_COMBO_PHY_SEL;
sys/arch/riscv64/dev/smtcomphy.c
323
if (val != oval)
sys/arch/riscv64/dev/smtcomphy.c
324
regmap_write_4(sc->sc_apmu, APMU_PMUA_USB_PHY_CTRL0, val);
sys/arch/riscv64/dev/smtcomphy.c
339
uint32_t val;
sys/arch/riscv64/dev/smtcomphy.c
343
val = HREAD4(sc, PCIE_RX_REG1(lane));
sys/arch/riscv64/dev/smtcomphy.c
344
val &= ~AFE_RTERM_REG_MASK;
sys/arch/riscv64/dev/smtcomphy.c
345
val |= rx_rterm << AFE_RTERM_REG_SHIFT;
sys/arch/riscv64/dev/smtcomphy.c
346
val |= EN_RTERM;
sys/arch/riscv64/dev/smtcomphy.c
347
HWRITE4(sc, PCIE_RX_REG1(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
349
val = HREAD4(sc, PCIE_RX_REG2(lane));
sys/arch/riscv64/dev/smtcomphy.c
350
val &= ~RX_RTERM_SEL;
sys/arch/riscv64/dev/smtcomphy.c
351
HWRITE4(sc, PCIE_RX_REG2(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
353
val = HREAD4(sc, PCIE_TX_REG1(lane));
sys/arch/riscv64/dev/smtcomphy.c
354
val &= ~TX_RTERM_REG_MASK;
sys/arch/riscv64/dev/smtcomphy.c
355
val |= tx_rterm << TX_RTERM_REG_SHIFT;
sys/arch/riscv64/dev/smtcomphy.c
356
val |= TX_RTERM_SEL;
sys/arch/riscv64/dev/smtcomphy.c
357
HWRITE4(sc, PCIE_TX_REG1(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
359
val = HREAD4(sc, PCIE_RC_CAL_REG2(lane));
sys/arch/riscv64/dev/smtcomphy.c
360
val &= ~CLKSEL_MASK;
sys/arch/riscv64/dev/smtcomphy.c
361
val |= CLKSEL_24M;
sys/arch/riscv64/dev/smtcomphy.c
362
val &= ~RC_CAL_TOGGLE;
sys/arch/riscv64/dev/smtcomphy.c
363
HWRITE4(sc, PCIE_RC_CAL_REG2(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
364
val |= RC_CAL_TOGGLE;
sys/arch/riscv64/dev/smtcomphy.c
365
HWRITE4(sc, PCIE_RC_CAL_REG2(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
367
val = HREAD4(sc, PCIE_LTSSM_DIS_ENTRY(lane));
sys/arch/riscv64/dev/smtcomphy.c
368
val |= OVRD_REFCLK_MODE;
sys/arch/riscv64/dev/smtcomphy.c
369
val &= ~CFG_REFCLK_MODE_MASK;
sys/arch/riscv64/dev/smtcomphy.c
370
val |= CFG_REFCLK_MODE_DRIVER;
sys/arch/riscv64/dev/smtcomphy.c
371
HWRITE4(sc, PCIE_LTSSM_DIS_ENTRY(lane), val);
sys/arch/riscv64/dev/smtcomphy.c
82
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtcomphy.c
83
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtgpio.c
148
int val;
sys/arch/riscv64/dev/smtgpio.c
154
val = (reg >> pin) & 1;
sys/arch/riscv64/dev/smtgpio.c
156
val = !val;
sys/arch/riscv64/dev/smtgpio.c
157
return val;
sys/arch/riscv64/dev/smtgpio.c
161
smtgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/riscv64/dev/smtgpio.c
173
val = !val;
sys/arch/riscv64/dev/smtgpio.c
174
if (val)
sys/arch/riscv64/dev/smtgpio.c
38
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtgpio.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtiic.c
272
smtiic_write_byte(void *v, uint8_t val, int flags)
sys/arch/riscv64/dev/smtiic.c
279
HWRITE4(sc, IDBR, val);
sys/arch/riscv64/dev/smtiic.c
78
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtiic.c
79
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtpinctrl.c
164
uint32_t val, pd_val;
sys/arch/riscv64/dev/smtpinctrl.c
186
val = HREAD4(sc, offset);
sys/arch/riscv64/dev/smtpinctrl.c
189
val &= ~MFPR_AF_SEL_MASK;
sys/arch/riscv64/dev/smtpinctrl.c
190
val |= (func << MFPR_AF_SEL_SHIFT);
sys/arch/riscv64/dev/smtpinctrl.c
194
val &= ~(MFPR_PULL_SEL | MFPR_PULLUP_EN | MFPR_PULLDN_EN);
sys/arch/riscv64/dev/smtpinctrl.c
195
val &= ~MFPR_SPU;
sys/arch/riscv64/dev/smtpinctrl.c
196
val |= bias;
sys/arch/riscv64/dev/smtpinctrl.c
254
val &= ~MFPR_DRIVE_MASK_K1;
sys/arch/riscv64/dev/smtpinctrl.c
255
val |= (ds << MFPR_DRIVE_SHIFT_K1);
sys/arch/riscv64/dev/smtpinctrl.c
258
HWRITE4(sc, offset, val);
sys/arch/riscv64/dev/smtpinctrl.c
269
uint32_t val, pd_val;
sys/arch/riscv64/dev/smtpinctrl.c
295
val = HREAD4(sc, offset);
sys/arch/riscv64/dev/smtpinctrl.c
298
val &= ~MFPR_AF_SEL_MASK;
sys/arch/riscv64/dev/smtpinctrl.c
299
val |= (func << MFPR_AF_SEL_SHIFT);
sys/arch/riscv64/dev/smtpinctrl.c
303
val &= ~(MFPR_PULL_SEL | MFPR_PULLUP_EN | MFPR_PULLDN_EN);
sys/arch/riscv64/dev/smtpinctrl.c
304
val &= ~MFPR_SPU;
sys/arch/riscv64/dev/smtpinctrl.c
305
val |= bias;
sys/arch/riscv64/dev/smtpinctrl.c
363
val &= ~MFPR_DRIVE_MASK_K3;
sys/arch/riscv64/dev/smtpinctrl.c
364
val |= (ds << MFPR_DRIVE_SHIFT_K3);
sys/arch/riscv64/dev/smtpinctrl.c
367
HWRITE4(sc, offset, val);
sys/arch/riscv64/dev/smtpinctrl.c
64
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtpinctrl.c
65
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtpmic.c
122
uint8_t val;
sys/arch/riscv64/dev/smtpmic.c
127
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/arch/riscv64/dev/smtpmic.c
133
val = 0xff;
sys/arch/riscv64/dev/smtpmic.c
136
return val;
sys/arch/riscv64/dev/smtpmic.c
140
smtpmic_reg_write(struct smtpmic_softc *sc, int reg, uint8_t val)
sys/arch/riscv64/dev/smtpmic.c
147
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/arch/riscv64/dev/stfclock.c
181
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfclock.c
182
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stfpcie.c
101
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfpcie.c
102
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stfpciephy.c
36
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfpciephy.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stfpinctrl.c
215
int val;
sys/arch/riscv64/dev/stfpinctrl.c
221
val = (reg >> (pin % 32)) & 1;
sys/arch/riscv64/dev/stfpinctrl.c
223
val = !val;
sys/arch/riscv64/dev/stfpinctrl.c
224
return val;
sys/arch/riscv64/dev/stfpinctrl.c
228
stfpinctrl_jh7100_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/riscv64/dev/stfpinctrl.c
238
val = !val;
sys/arch/riscv64/dev/stfpinctrl.c
240
GPIO_DOUT_CFG(pin), val);
sys/arch/riscv64/dev/stfpinctrl.c
286
int val;
sys/arch/riscv64/dev/stfpinctrl.c
293
val = (reg >> (pin % 32)) & 1;
sys/arch/riscv64/dev/stfpinctrl.c
295
val = !val;
sys/arch/riscv64/dev/stfpinctrl.c
296
return val;
sys/arch/riscv64/dev/stfpinctrl.c
300
stfpinctrl_jh7110_set_pin(void *cookie, uint32_t *cells, int val)
sys/arch/riscv64/dev/stfpinctrl.c
311
val = !val;
sys/arch/riscv64/dev/stfpinctrl.c
315
reg |= (val << JH7110_DOUT_SHIFT(pin));
sys/arch/riscv64/dev/stfrng.c
52
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfrng.c
53
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stftemp.c
41
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stftemp.c
42
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sxitimer.c
48
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sxitimer.c
49
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/include/_types.h
40
long val[14];
sys/arch/riscv64/include/cpufunc.h
97
load_satp(uint64_t val)
sys/arch/riscv64/include/cpufunc.h
99
__asm volatile("csrw satp, %0" :: "r"(val));
sys/arch/riscv64/include/riscvreg.h
214
#define CSR_ZIMM(val) \
sys/arch/riscv64/include/riscvreg.h
215
(__builtin_constant_p(val) && ((u_long)(val) < 32))
sys/arch/riscv64/include/riscvreg.h
217
#define csr_swap(csr, val) \
sys/arch/riscv64/include/riscvreg.h
219
if (CSR_ZIMM(val)) \
sys/arch/riscv64/include/riscvreg.h
221
: "=r" (ret) : "i" (val)); \
sys/arch/riscv64/include/riscvreg.h
224
: "=r" (ret) : "r" (val)); \
sys/arch/riscv64/include/riscvreg.h
228
#define csr_write(csr, val) \
sys/arch/riscv64/include/riscvreg.h
229
({ if (CSR_ZIMM(val)) \
sys/arch/riscv64/include/riscvreg.h
230
__asm volatile("csrwi " #csr ", %0" :: "i" (val)); \
sys/arch/riscv64/include/riscvreg.h
232
__asm volatile("csrw " #csr ", %0" :: "r" (val)); \
sys/arch/riscv64/include/riscvreg.h
235
#define csr_set(csr, val) \
sys/arch/riscv64/include/riscvreg.h
236
({ if (CSR_ZIMM(val)) \
sys/arch/riscv64/include/riscvreg.h
237
__asm volatile("csrsi " #csr ", %0" :: "i" (val)); \
sys/arch/riscv64/include/riscvreg.h
239
__asm volatile("csrs " #csr ", %0" :: "r" (val)); \
sys/arch/riscv64/include/riscvreg.h
242
#define csr_clear(csr, val) \
sys/arch/riscv64/include/riscvreg.h
243
({ if (CSR_ZIMM(val)) \
sys/arch/riscv64/include/riscvreg.h
244
__asm volatile("csrci " #csr ", %0" :: "i" (val)); \
sys/arch/riscv64/include/riscvreg.h
246
__asm volatile("csrc " #csr ", %0" :: "r" (val)); \
sys/arch/riscv64/include/riscvreg.h
250
({ u_long val; \
sys/arch/riscv64/include/riscvreg.h
251
__asm volatile("csrr %0, " #csr : "=r" (val)); \
sys/arch/riscv64/include/riscvreg.h
252
val; \
sys/arch/riscv64/include/sbi.h
211
sbi_set_timer(uint64_t val)
sys/arch/riscv64/include/sbi.h
214
(void)SBI_CALL1(SBI_SET_TIMER, 0, val);
sys/arch/riscv64/riscv64/bus_space.c
67
uint8_t val = *(volatile uint8_t *)(h + o);
sys/arch/riscv64/riscv64/bus_space.c
69
return val;
sys/arch/riscv64/riscv64/bus_space.c
75
uint16_t val = *(volatile uint16_t *)(h + o);
sys/arch/riscv64/riscv64/bus_space.c
77
return val;
sys/arch/riscv64/riscv64/bus_space.c
83
uint32_t val = *(volatile uint32_t *)(h + o);
sys/arch/riscv64/riscv64/bus_space.c
85
return val;
sys/arch/riscv64/riscv64/bus_space.c
91
uint64_t val = *(volatile uint64_t *)(h + o);
sys/arch/riscv64/riscv64/bus_space.c
93
return val;
sys/arch/riscv64/riscv64/db_disasm.c
359
uint32_t val;
sys/arch/riscv64/riscv64/db_disasm.c
541
val = (insn >> 20) & 0x3f;
sys/arch/riscv64/riscv64/db_disasm.c
542
db_printf("0x%x", val);
sys/arch/riscv64/riscv64/db_disasm.c
545
val = (insn >> 20) & 0x1f;
sys/arch/riscv64/riscv64/db_disasm.c
546
db_printf("0x%x", val);
sys/arch/riscv64/riscv64/db_disasm.c
549
val = (insn >> 20) & 0xfff;
sys/arch/riscv64/riscv64/db_disasm.c
551
switch (val) {
sys/arch/riscv64/riscv64/db_disasm.c
559
db_printf("0x%x", val);
sys/arch/riscv64/riscv64/intr.c
335
void *val = NULL;
sys/arch/riscv64/riscv64/intr.c
388
val = ic->ic_establish(ic->ic_cookie, cell, level,
sys/arch/riscv64/riscv64/intr.c
399
if (val == NULL)
sys/arch/riscv64/riscv64/intr.c
404
ih->ih_ih = val;
sys/arch/riscv64/riscv64/intr.c
418
void *val = NULL;
sys/arch/riscv64/riscv64/intr.c
452
val = ic->ic_establish(ic->ic_cookie, &cell[5 + acells],
sys/arch/riscv64/riscv64/intr.c
461
if (val == NULL) {
sys/arch/riscv64/riscv64/intr.c
468
ih->ih_ih = val;
sys/arch/riscv64/riscv64/intr.c
482
void *val = NULL;
sys/arch/riscv64/riscv64/intr.c
493
val = ic->ic_establish_msi(ic->ic_cookie, addr, data,
sys/arch/riscv64/riscv64/intr.c
495
if (val == NULL)
sys/arch/riscv64/riscv64/intr.c
500
ih->ih_ih = val;
sys/arch/sh/dev/shpcicvar.h
199
bus_size_t offset, uint8_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
201
bus_size_t offset, uint16_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
203
bus_size_t offset, uint32_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
205
bus_size_t offset, uint8_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
207
bus_size_t offset, uint16_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
209
bus_size_t offset, uint32_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
213
bus_size_t offset, uint8_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
215
bus_size_t offset, uint16_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
217
bus_size_t offset, uint32_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
219
bus_size_t offset, uint8_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
221
bus_size_t offset, uint16_t val, bus_size_t count);
sys/arch/sh/dev/shpcicvar.h
223
bus_size_t offset, uint32_t val, bus_size_t count);
sys/arch/sh/include/_types.h
40
long val[9];
sys/arch/sparc64/dev/cbus.c
269
arc = elem[idx].d.val;
sys/arch/sparc64/dev/ce4231.c
590
u_int8_t val;
sys/arch/sparc64/dev/ce4231.c
592
val = ce4231_read(sc, CS_MONO_IO_CONTROL) & ~MONO_OUTPUT_MUTE;
sys/arch/sparc64/dev/ce4231.c
594
val |= MONO_OUTPUT_MUTE;
sys/arch/sparc64/dev/ce4231.c
595
ce4231_write(sc, CS_MONO_IO_CONTROL, val);
sys/arch/sparc64/dev/ce4231.c
597
val = ce4231_read(sc, SP_PIN_CONTROL) & ~(XCTL0_ENABLE | XCTL1_ENABLE);
sys/arch/sparc64/dev/ce4231.c
599
val |= XCTL0_ENABLE;
sys/arch/sparc64/dev/ce4231.c
601
val |= XCTL1_ENABLE;
sys/arch/sparc64/dev/ce4231.c
602
ce4231_write(sc, SP_PIN_CONTROL, val);
sys/arch/sparc64/dev/ce4231.c
609
u_int8_t val;
sys/arch/sparc64/dev/ce4231.c
614
val = ce4231_read(sc, SP_PIN_CONTROL);
sys/arch/sparc64/dev/ce4231.c
615
if (!(val & XCTL0_ENABLE))
sys/arch/sparc64/dev/ce4231.c
617
if (!(val & XCTL1_ENABLE))
sys/arch/sparc64/dev/clkbrd.c
184
u_int8_t val;
sys/arch/sparc64/dev/clkbrd.c
187
val = bus_space_read_1(sc->sc_bt, sc->sc_creg, CLK_TEMP);
sys/arch/sparc64/dev/clkbrd.c
188
if (val == 0xff) {
sys/arch/sparc64/dev/clkbrd.c
193
if (val < sizeof(clkbrd_temp))
sys/arch/sparc64/dev/clkbrd.c
194
temp = clkbrd_temp[val];
sys/arch/sparc64/dev/clkbrd.c
198
sc->sc_sensor.value = val * 1000000 + 273150000;
sys/arch/sparc64/dev/environ.c
138
u_int8_t val;
sys/arch/sparc64/dev/environ.c
141
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0);
sys/arch/sparc64/dev/environ.c
143
if (val == 0xff) {
sys/arch/sparc64/dev/environ.c
148
if (val < sizeof(environ_cpu2_temp))
sys/arch/sparc64/dev/environ.c
149
temp = environ_cpu2_temp[val];
sys/arch/sparc64/dev/environ.c
153
sc->sc_sensor.value = val * 1000000 + 273150000;
sys/arch/sparc64/dev/lom.c
380
lom_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
383
return lom1_read(sc, reg, val);
sys/arch/sparc64/dev/lom.c
385
return lom2_read(sc, reg, val);
sys/arch/sparc64/dev/lom.c
389
lom_write(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
392
return lom1_write(sc, reg, val);
sys/arch/sparc64/dev/lom.c
394
return lom2_write(sc, reg, val);
sys/arch/sparc64/dev/lom.c
422
lom1_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
428
return lom1_read_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
438
*val = lc.lc_data;
sys/arch/sparc64/dev/lom.c
444
lom1_write(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
450
return lom1_write_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
453
lc.lc_data = val;
sys/arch/sparc64/dev/lom.c
464
lom1_read_polled(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
491
*val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LOM1_DATA);
sys/arch/sparc64/dev/lom.c
496
lom1_write_polled(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
524
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM1_DATA, val);
sys/arch/sparc64/dev/lom.c
610
lom2_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
616
return lom2_read_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
626
*val = lc.lc_data;
sys/arch/sparc64/dev/lom.c
632
lom2_read_polled(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
659
*val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LOM2_DATA);
sys/arch/sparc64/dev/lom.c
664
lom2_write(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
670
return lom2_write_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
673
lc.lc_data = val;
sys/arch/sparc64/dev/lom.c
684
lom2_write_polled(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
726
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM2_DATA, val);
sys/arch/sparc64/dev/lom.c
742
sc->sc_space = val;
sys/arch/sparc64/dev/lom.c
817
uint8_t val;
sys/arch/sparc64/dev/lom.c
836
error = lom_read(sc, k++, &val);
sys/arch/sparc64/dev/lom.c
840
if (val == 0xff)
sys/arch/sparc64/dev/lom.c
844
sc->sc_temp[i].desc[j++] = val;
sys/arch/sparc64/dev/lom.c
846
if (val == '\0') {
sys/arch/sparc64/dev/lom.c
867
error = lom_read(sc, k++, &val);
sys/arch/sparc64/dev/lom.c
871
if (val == 0xff)
sys/arch/sparc64/dev/lom.c
875
sc->sc_fan[i].desc[j++] = val;
sys/arch/sparc64/dev/lom.c
877
if (val == '\0') {
sys/arch/sparc64/dev/lom.c
896
uint8_t val;
sys/arch/sparc64/dev/lom.c
900
if (lom_read(sc, LOM_IDX_FAN1 + i, &val)) {
sys/arch/sparc64/dev/lom.c
905
sc->sc_fan[i].value = (60 * sc->sc_fan_cal[i] * val) / 100;
sys/arch/sparc64/dev/lom.c
906
if (val < sc->sc_fan_low[i])
sys/arch/sparc64/dev/lom.c
914
if (lom_read(sc, LOM_IDX_PSU1 + i, &val) ||
sys/arch/sparc64/dev/lom.c
915
!ISSET(val, LOM_PSU_PRESENT)) {
sys/arch/sparc64/dev/lom.c
920
if (val & LOM_PSU_STANDBY) {
sys/arch/sparc64/dev/lom.c
925
if (ISSET(val, LOM_PSU_INPUTA) &&
sys/arch/sparc64/dev/lom.c
926
ISSET(val, LOM_PSU_INPUTB) &&
sys/arch/sparc64/dev/lom.c
927
ISSET(val, LOM_PSU_OUTPUT))
sys/arch/sparc64/dev/lom.c
936
if (lom_read(sc, LOM_IDX_TEMP1 + i, &val)) {
sys/arch/sparc64/dev/lom.c
941
sc->sc_temp[i].value = val * 1000000 + 273150000;
sys/arch/sparc64/dev/mgiic.c
346
u_int64_t val = v;
sys/arch/sparc64/dev/mgiic.c
348
bus_space_write_8(sc->sc_bt, sc->sc_regh, r, val);
sys/arch/sparc64/dev/mgiic.c
356
u_int8_t val;
sys/arch/sparc64/dev/mgiic.c
358
val = (mgiic_read(sc, MGCONTROL) | on) & ~off;
sys/arch/sparc64/dev/mgiic.c
359
mgiic_write(sc, MGCONTROL, val);
sys/arch/sparc64/dev/pci_machdep.c
347
int val = 0;
sys/arch/sparc64/dev/pci_machdep.c
350
val = pc->conf_size(pc, tag);
sys/arch/sparc64/dev/pci_machdep.c
352
return (val);
sys/arch/sparc64/dev/pci_machdep.c
358
pcireg_t val = (pcireg_t)~0;
sys/arch/sparc64/dev/pci_machdep.c
361
val = pc->conf_read(pc, tag, reg);
sys/arch/sparc64/dev/pci_machdep.c
363
return (val);
sys/arch/sparc64/dev/psycho.c
1122
pcireg_t val;
sys/arch/sparc64/dev/psycho.c
1128
val = bus_space_read_4(pc->bustag, pc->bushandle,
sys/arch/sparc64/dev/psycho.c
1132
val = 0xffffffff;
sys/arch/sparc64/dev/psycho.c
1136
return (val);
sys/arch/sparc64/dev/pyro.c
452
pcireg_t val;
sys/arch/sparc64/dev/pyro.c
458
val = bus_space_read_4(pc->bustag, pc->bushandle,
sys/arch/sparc64/dev/pyro.c
462
val = 0xffffffff;
sys/arch/sparc64/dev/pyro.c
466
return (val);
sys/arch/sparc64/dev/rtc.c
231
rtc_write_reg(struct rtc_softc *sc, bus_size_t reg, u_int8_t val)
sys/arch/sparc64/dev/rtc.c
234
bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_DATA, val);
sys/arch/sparc64/dev/schizo.c
474
pcireg_t val;
sys/arch/sparc64/dev/schizo.c
480
val = bus_space_read_4(pc->bustag, pc->bushandle,
sys/arch/sparc64/dev/schizo.c
484
val = 0xffffffff;
sys/arch/sparc64/dev/schizo.c
488
return (val);
sys/arch/sparc64/dev/vcc.c
131
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vcc.c
90
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vds.c
128
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vds.c
90
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vldc.c
132
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vldc.c
91
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vsw.c
128
arc = elem[idx].d.val;
sys/arch/sparc64/dev/vsw.c
90
arc = elem[idx].d.val;
sys/arch/sparc64/dev/zs.c
568
u_char val;
sys/arch/sparc64/dev/zs.c
572
val = *cs->cs_reg_csr;
sys/arch/sparc64/dev/zs.c
574
return (val);
sys/arch/sparc64/dev/zs.c
578
zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
sys/arch/sparc64/dev/zs.c
582
*cs->cs_reg_csr = val;
sys/arch/sparc64/dev/zs.c
589
u_char val;
sys/arch/sparc64/dev/zs.c
591
val = *cs->cs_reg_csr;
sys/arch/sparc64/dev/zs.c
593
return (val);
sys/arch/sparc64/dev/zs.c
597
zs_write_csr(struct zs_chanstate *cs, u_char val)
sys/arch/sparc64/dev/zs.c
599
*cs->cs_reg_csr = val;
sys/arch/sparc64/dev/zs.c
606
u_char val;
sys/arch/sparc64/dev/zs.c
608
val = *cs->cs_reg_data;
sys/arch/sparc64/dev/zs.c
610
return (val);
sys/arch/sparc64/dev/zs.c
614
zs_write_data(struct zs_chanstate *cs, u_char val)
sys/arch/sparc64/dev/zs.c
616
*cs->cs_reg_data = val;
sys/arch/sparc64/include/_types.h
40
long val[2];
sys/arch/sparc64/include/autoconf.h
144
long val[3]; /* up to three optional values */
sys/arch/sparc64/include/ctlreg.h
507
#define sparc_wr(name, val, xor) \
sys/arch/sparc64/include/ctlreg.h
511
: : "rI" ((val) ^ (xor)) : "%g0"); \
sys/arch/sparc64/include/ctlreg.h
514
: : "r" (val), "rI" (xor) : "%g0"); \
sys/arch/sparc64/include/ctlreg.h
517
#define sparc_wrpr(name, val, xor) \
sys/arch/sparc64/include/ctlreg.h
521
: : "rI" ((val) ^ (xor)) : "%g0"); \
sys/arch/sparc64/include/ctlreg.h
524
: : "r" (val), "rI" (xor) : "%g0"); \
sys/arch/sparc64/include/ctlreg.h
631
o ## _asi(paddr_t va, tp val) \
sys/arch/sparc64/include/ctlreg.h
636
: "r" (val), "r" ((volatile tp *)va) \
sys/arch/sparc64/include/ctlreg.h
641
o ## _nc(paddr_t va, int asi, tp val) \
sys/arch/sparc64/include/ctlreg.h
644
o ## _asi(va, val); \
sys/arch/sparc64/include/ctlreg.h
654
#define STC_GEN(va, asi, val, op, opa, type) ({ \
sys/arch/sparc64/include/ctlreg.h
657
*((volatile type *)va) = val; \
sys/arch/sparc64/include/ctlreg.h
660
: : "r" (val), "r" ((volatile type *)va) \
sys/arch/sparc64/include/ctlreg.h
665
#define ST_GENERIC(va, asi, val, op, type) (__builtin_constant_p(asi) ? \
sys/arch/sparc64/include/ctlreg.h
666
STC_GEN((va), (asi), (val), op, op ## a, type) : \
sys/arch/sparc64/include/ctlreg.h
667
op ## a_nc((va), asi, (val)))
sys/arch/sparc64/include/ctlreg.h
669
#define ST_GENERIC(va, asi, val, op, type) (op ## a_nc((va), asi, (val)))
sys/arch/sparc64/include/ctlreg.h
672
#define stba(va, asi, val) ST_GENERIC(va, asi, val, stb, u_int8_t)
sys/arch/sparc64/include/ctlreg.h
673
#define stha(va, asi, val) ST_GENERIC(va, asi, val, sth, u_int16_t)
sys/arch/sparc64/include/ctlreg.h
674
#define stwa(va, asi, val) ST_GENERIC(va, asi, val, stw, u_int32_t)
sys/arch/sparc64/include/ctlreg.h
675
#define stxa(va, asi, val) ST_GENERIC(va, asi, val, stx, u_int64_t)
sys/arch/sparc64/include/mdesc.h
35
uint64_t val;
sys/arch/sparc64/include/psl.h
284
stxa_sync(u_int64_t va, u_int64_t asi, u_int64_t val)
sys/arch/sparc64/include/psl.h
287
stxa_nc(va, asi, val);
sys/arch/sparc64/include/z8530var.h
70
void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);
sys/arch/sparc64/include/z8530var.h
71
void zs_write_csr(struct zs_chanstate *cs, u_char val);
sys/arch/sparc64/include/z8530var.h
72
void zs_write_data(struct zs_chanstate *cs, u_char val);
sys/arch/sparc64/sparc64/autoconf.c
1396
(bp + 1)->val[0] = 0;
sys/arch/sparc64/sparc64/autoconf.c
1397
(bp + 1)->val[1] = 0;
sys/arch/sparc64/sparc64/autoconf.c
1420
if (strcmp(bp->name, "fp") == 0 && bp->val[0] == 0) {
sys/arch/sparc64/sparc64/autoconf.c
1438
u_int target = bp->val[0];
sys/arch/sparc64/sparc64/autoconf.c
1439
u_int lun = bp->val[1];
sys/arch/sparc64/sparc64/autoconf.c
1441
if (bp->val[0] & 0xffffffff00000000 && bp->val[0] != -1) {
sys/arch/sparc64/sparc64/autoconf.c
1443
if (bp->val[0] == sl->port_wwn && lun == sl->lun) {
sys/arch/sparc64/sparc64/autoconf.c
1453
memcmp(sl->id + 1, &bp->val[0], 8) == 0)
sys/arch/sparc64/sparc64/autoconf.c
1485
bp->val[0] == aa->aa_channel) {
sys/arch/sparc64/sparc64/autoconf.c
1486
channel = bp->val[0]; bp++;
sys/arch/sparc64/sparc64/autoconf.c
1487
drive = bp->val[0];
sys/arch/sparc64/sparc64/autoconf.c
1489
channel = bp->val[0] / 2;
sys/arch/sparc64/sparc64/autoconf.c
1490
drive = bp->val[0] % 2;
sys/arch/sparc64/sparc64/autoconf.c
511
cp = str2hex(++cp, &bp->val[0]);
sys/arch/sparc64/sparc64/autoconf.c
513
cp = str2hex(++cp, &bp->val[1]);
sys/arch/sparc64/sparc64/autoconf.c
522
bp->val[2] = DL_PARTNAME2NUM(*++cp);
sys/arch/sparc64/sparc64/autoconf.c
527
bp->val[0] = -1; /* no #'s: assume unit 0, no
sys/arch/sparc64/sparc64/autoconf.c
603
if (bp->val[0] == -1)
sys/arch/sparc64/sparc64/autoconf.c
604
printf("/%s%lx", bp->name, bp->val[1]);
sys/arch/sparc64/sparc64/autoconf.c
606
printf("/%s@%lx,%lx", bp->name, bp->val[0], bp->val[1]);
sys/arch/sparc64/sparc64/autoconf.c
607
if (bp->val[2] != 0)
sys/arch/sparc64/sparc64/autoconf.c
608
printf(":%c", DL_PARTNUM2NAME((int)bp->val[2]));
sys/arch/sparc64/sparc64/autoconf.c
803
setroot(bootdv, bp->val[2], RB_USERREQ | RB_HALT);
sys/arch/sparc64/sparc64/db_disasm.c
1002
val = SIGNEX(insn, 13);
sys/arch/sparc64/sparc64/db_disasm.c
1003
db_printf("%s0x%x", SIGN(val), (int)abs(val));
sys/arch/sparc64/sparc64/db_disasm.c
1007
val = SIGNEX(insn, 11);
sys/arch/sparc64/sparc64/db_disasm.c
1008
db_printf("%s0x%x", SIGN(val), (int)abs(val));
sys/arch/sparc64/sparc64/db_disasm.c
1011
val = (((insn>>20)&0x3)<<13)|(insn & 0x1fff);
sys/arch/sparc64/sparc64/db_disasm.c
1012
val = SIGNEX(val, 16);
sys/arch/sparc64/sparc64/db_disasm.c
1013
db_printsym((vaddr_t)(loc + (4 * val)),
sys/arch/sparc64/sparc64/db_disasm.c
1047
val = SIGNEX(insn, 13);
sys/arch/sparc64/sparc64/db_disasm.c
1050
(int)((val<0)?'-':'+'),
sys/arch/sparc64/sparc64/db_disasm.c
1051
(int)abs(val));
sys/arch/sparc64/sparc64/db_disasm.c
981
int64_t val;
sys/arch/sparc64/sparc64/emul.c
162
u_int64_t val, ret = 0;
sys/arch/sparc64/sparc64/emul.c
167
val = tf->tf_global[ins.i_asi.i_rs2];
sys/arch/sparc64/sparc64/emul.c
169
val = SIGN_EXT13(ins.i_simm13.i_simm13);
sys/arch/sparc64/sparc64/emul.c
171
for (; val != 0; val >>= 1)
sys/arch/sparc64/sparc64/emul.c
172
ret += val & 1;
sys/arch/sparc64/sparc64/mdesc.c
192
return (elem[idx].d.val);
sys/arch/sparc64/sparc64/mdesc.c
255
uint64_t val;
sys/arch/sparc64/sparc64/mdesc.c
261
for (idx = 0; elem[idx].tag == 'N'; idx = elem[idx].d.val) {
sys/arch/sparc64/sparc64/mdesc.c
263
val = mdesc_get_prop_val(idx, "cfg-handle");
sys/arch/sparc64/sparc64/mdesc.c
264
if (str && strcmp(str, name) == 0 && val == cfg_handle)
sys/arch/sparc64/sparc64/mdesc.c
278
uint64_t val;
sys/arch/sparc64/sparc64/mdesc.c
290
arc = elem[idx].d.val;
sys/arch/sparc64/sparc64/mdesc.c
292
val = mdesc_get_prop_val(arc, "cfg-handle");
sys/arch/sparc64/sparc64/mdesc.c
293
if (str && strcmp(str, name) == 0 && val == cfg_handle)
sys/arch/sparc64/sparc64/mdesc.c
313
for (idx = 0; elem[idx].tag == 'N'; idx = elem[idx].d.val) {
sys/ddb/db_ctf.c
418
db_expr_t val;
sys/ddb/db_ctf.c
448
val = db_get_value(addr, sizeof(val), 0);
sys/ddb/db_ctf.c
449
db_printf("%lx", (unsigned long)val);
sys/ddb/db_ctf.c
477
val = db_get_value(addr, CTF_INT_BITS(eob) / 8,
sys/ddb/db_ctf.c
480
db_printf("%ld", val);
sys/ddb/db_ctf.c
482
db_printf("%lu", val);
sys/ddb/db_ctf.c
568
int32_t val;
sys/ddb/db_ctf.c
574
val = (int32_t)db_get_value(addr, sizeof(val), 1);
sys/ddb/db_ctf.c
579
if (val == cte->cte_value) {
sys/ddb/db_ctf.c
588
db_printf("#%d", val);
sys/ddb/db_output.c
204
db_format(char *buf, size_t bufsize, long val, int format, int alt, int width)
sys/ddb/db_output.c
216
if (val < 0 && format != DB_FORMAT_N)
sys/ddb/db_output.c
217
val = -val;
sys/ddb/db_output.c
221
snprintf(buf, bufsize, fmt, width, val);
sys/ddb/db_sym.c
106
sym = db_elf_sym_search(val, strategy, &newdiff);
sys/ddb/db_sym.c
99
db_search_symbol(vaddr_t val, db_strategy_t strategy, db_expr_t *offp)
sys/ddb/db_sym.h
76
#define db_find_sym_and_offset(val,namep,offp) \
sys/ddb/db_sym.h
77
db_symbol_values(db_search_symbol(val,DB_STGY_ANY,offp),namep,NULL)
sys/ddb/db_sym.h
80
#define db_find_xtrn_sym_and_offset(val,namep,offp) \
sys/ddb/db_sym.h
81
db_symbol_values(db_search_symbol(val,DB_STGY_XTRN,offp),namep,NULL)
sys/dev/acpi/abl.c
170
uint8_t val;
sys/dev/acpi/abl.c
174
val = bus_space_read_1(sc->sc_bt, sc->sc_bh, ABL_IO_HI);
sys/dev/acpi/abl.c
176
return (val >> 4);
sys/dev/acpi/abl.c
180
abl_set_brightness(struct abl_softc *sc, uint8_t val)
sys/dev/acpi/abl.c
182
bus_space_write_1(sc->sc_bt, sc->sc_bh, ABL_IO_HI, 0x04 | (val << 4));
sys/dev/acpi/acpi.c
192
uint32_t val = pci_conf_read(pc, tag, reg & ~0x3);
sys/dev/acpi/acpi.c
193
return (val >> ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
199
uint32_t val = pci_conf_read(pc, tag, reg & ~0x2);
sys/dev/acpi/acpi.c
200
return (val >> ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
210
acpi_pci_conf_write_1(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint8_t val)
sys/dev/acpi/acpi.c
214
tmp |= (val << ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
219
acpi_pci_conf_write_2(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint16_t val)
sys/dev/acpi/acpi.c
223
tmp |= (val << ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
228
acpi_pci_conf_write_4(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint32_t val)
sys/dev/acpi/acpi.c
230
pci_conf_write(pc, tag, reg, val);
sys/dev/acpi/acpi.c
2958
struct aml_value *val;
sys/dev/acpi/acpi.c
2966
val = res->v_package[1];
sys/dev/acpi/acpi.c
2967
if (val->type == AML_OBJTYPE_OBJREF)
sys/dev/acpi/acpi.c
2968
val = val->v_objref.ref;
sys/dev/acpi/acpi.c
2970
len = val->length;
sys/dev/acpi/acpi.c
2971
switch (val->type) {
sys/dev/acpi/acpi.c
2973
memcpy(buf, val->v_buffer, min(len, buflen));
sys/dev/acpi/acpi.c
2976
memcpy(buf, val->v_string, min(len, buflen));
sys/dev/acpi/acpi.c
3013
struct aml_value *val;
sys/dev/acpi/acpi.c
3020
val = res->v_package[1];
sys/dev/acpi/acpi.c
3021
if (val->type == AML_OBJTYPE_OBJREF)
sys/dev/acpi/acpi.c
3022
val = val->v_objref.ref;
sys/dev/acpi/acpi.c
3024
if (val->type == AML_OBJTYPE_INTEGER)
sys/dev/acpi/acpi.c
3025
return val->v_integer;
sys/dev/acpi/acpi.c
3124
struct aml_value res, *val;
sys/dev/acpi/acpi.c
3135
val = res.v_package[i];
sys/dev/acpi/acpi.c
3136
if (val->type == AML_OBJTYPE_NAMEREF) {
sys/dev/acpi/acpi.c
3138
aml_getname(val->v_nameref));
sys/dev/acpi/acpi.c
3140
val = node->value;
sys/dev/acpi/acpi.c
3142
if (val->type == AML_OBJTYPE_OBJREF)
sys/dev/acpi/acpi.c
3143
val = val->v_objref.ref;
sys/dev/acpi/acpi.c
3144
if (val->type != AML_OBJTYPE_DEVICE)
sys/dev/acpi/acpi.c
3146
dep = val->node;
sys/dev/acpi/acpi.c
580
struct aml_value *val;
sys/dev/acpi/acpi.c
587
val = res->v_package[1];
sys/dev/acpi/acpi.c
588
if (val->type == AML_OBJTYPE_OBJREF)
sys/dev/acpi/acpi.c
589
val = val->v_objref.ref;
sys/dev/acpi/acpi.c
591
if (val->type == AML_OBJTYPE_INTEGER)
sys/dev/acpi/acpi.c
592
return val->v_integer;
sys/dev/acpi/acpi.c
608
uint64_t val;
sys/dev/acpi/acpi.c
626
if (!aml_evalinteger(sc, node, "_SEG", 0, NULL, &val))
sys/dev/acpi/acpi.c
627
pci->seg = val;
sys/dev/acpi/acpi.c
634
if (!aml_evalinteger(sc, node, "_BBN", 0, NULL, &val)) {
sys/dev/acpi/acpi.c
636
aml_nodename(node), pci->bus, val);
sys/dev/acpi/acpi.c
638
pci->bus = val;
sys/dev/acpi/acpi.c
653
if (aml_evalinteger(sc, node, "_ADR", 0, NULL, &val))
sys/dev/acpi/acpi.c
659
pci->dev = ACPI_ADR_PCIDEV(val);
sys/dev/acpi/acpi.c
660
pci->fun = ACPI_ADR_PCIFUN(val);
sys/dev/acpi/acpi.c
669
if (aml_evalinteger(sc, node, "_S0W", 0, NULL, &val) == 0)
sys/dev/acpi/acpi.c
670
pci->_s0w = val;
sys/dev/acpi/acpi.c
673
if (aml_evalinteger(sc, node, "_S3D", 0, NULL, &val) == 0)
sys/dev/acpi/acpi.c
674
pci->_s3d = val;
sys/dev/acpi/acpi.c
677
if (aml_evalinteger(sc, node, "_S3W", 0, NULL, &val) == 0)
sys/dev/acpi/acpi.c
678
pci->_s3w = val;
sys/dev/acpi/acpi.c
681
if (aml_evalinteger(sc, node, "_S4D", 0, NULL, &val) == 0)
sys/dev/acpi/acpi.c
682
pci->_s4d = val;
sys/dev/acpi/acpi.c
685
if (aml_evalinteger(sc, node, "_S4W", 0, NULL, &val) == 0)
sys/dev/acpi/acpi.c
686
pci->_s4w = val;
sys/dev/acpi/acpibtn.c
109
lid->abl_softc->sc_devnode, "_LID", 0, NULL, &val) &&
sys/dev/acpi/acpibtn.c
110
val != 0)
sys/dev/acpi/acpibtn.c
118
struct aml_value val;
sys/dev/acpi/acpibtn.c
120
bzero(&val, sizeof val);
sys/dev/acpi/acpibtn.c
121
val.type = AML_OBJTYPE_INTEGER;
sys/dev/acpi/acpibtn.c
122
val.v_integer = psw;
sys/dev/acpi/acpibtn.c
123
val.length = 1;
sys/dev/acpi/acpibtn.c
125
return (aml_evalname(sc->sc_acpi, sc->sc_devnode, "_PSW", 1, &val,
sys/dev/acpi/acpibtn.c
96
int64_t val;
sys/dev/acpi/acpicpu_x86.c
370
acpicpu_add_cstatepkg(struct aml_value *val, void *arg)
sys/dev/acpi/acpicpu_x86.c
378
aml_showvalue(val);
sys/dev/acpi/acpicpu_x86.c
380
if (val->type != AML_OBJTYPE_PACKAGE || val->length != 4)
sys/dev/acpi/acpicpu_x86.c
384
state = val->v_package[1]->v_integer;
sys/dev/acpi/acpicpu_x86.c
387
if (val->v_package[0]->type != AML_OBJTYPE_BUFFER) {
sys/dev/acpi/acpicpu_x86.c
389
state, val->v_package[0]->type);
sys/dev/acpi/acpicpu_x86.c
392
grd = (struct acpi_grd *)val->v_package[0]->v_buffer;
sys/dev/acpi/acpicpu_x86.c
393
if (val->v_package[0]->length != sizeof(*grd) + 2 ||
sys/dev/acpi/acpicpu_x86.c
396
val->v_package[0]->v_buffer[sizeof(*grd)] != SRT_ENDTAG) {
sys/dev/acpi/acpicpu_x86.c
466
val->v_package[2]->v_integer, val->v_package[3]->v_integer, addr);
sys/dev/acpi/acpicpu_x86.c
472
acpicpu_add_cdeppkg(struct aml_value *val, void *arg)
sys/dev/acpi/acpicpu_x86.c
480
if (val->type != AML_OBJTYPE_PACKAGE || val->length < 6 ||
sys/dev/acpi/acpicpu_x86.c
481
val->length != val->v_package[0]->v_integer ||
sys/dev/acpi/acpicpu_x86.c
482
val->v_package[1]->v_integer != 0) {
sys/dev/acpi/acpicpu_x86.c
484
aml_showvalue(val);
sys/dev/acpi/acpicpu_x86.c
491
num_proc = val->v_package[4]->v_integer;
sys/dev/acpi/acpicpu_x86.c
496
coord_type = val->v_package[3]->v_integer;
sys/dev/acpi/acpicpu_x86.c
500
domain = val->v_package[2]->v_integer;
sys/dev/acpi/acpicpu_x86.c
501
cindex = val->v_package[5]->v_integer;
sys/dev/acpi/acpidebug.c
184
db_aml_objtype(struct aml_value *val)
sys/dev/acpi/acpidebug.c
186
if (val == NULL)
sys/dev/acpi/acpidebug.c
189
switch (val->type) {
sys/dev/acpi/acpidebug.c
224
return aml_mnem(val->v_field.type, NULL);
sys/dev/acpi/acpidmar.c
1379
uint64_t val;
sys/dev/acpi/acpidmar.c
1381
val = IOTLB_IVT;
sys/dev/acpi/acpidmar.c
1384
val |= IIG_GLOBAL;
sys/dev/acpi/acpidmar.c
1387
val |= IIG_DOMAIN | IOTLB_DID(did);
sys/dev/acpi/acpidmar.c
1394
val |= IIG_DOMAIN | IOTLB_DID(did);
sys/dev/acpi/acpidmar.c
1400
val |= IOTLB_DR;
sys/dev/acpi/acpidmar.c
1402
val |= IOTLB_DW;
sys/dev/acpi/acpidmar.c
1406
iommu_write_8(iommu, DMAR_IOTLB_REG(iommu), val);
sys/dev/acpi/acpidmar.c
1408
val = iommu_read_8(iommu, DMAR_IOTLB_REG(iommu));
sys/dev/acpi/acpidmar.c
1409
if ((val & IOTLB_IVT) == 0)
sys/dev/acpi/acpidmar.c
1413
if (val & IOTLB_IVT)
sys/dev/acpi/acpidmar.c
1445
uint64_t val, iva;
sys/dev/acpi/acpidmar.c
1481
val = IOTLB_IVT | IIG_PAGE | IOTLB_DID(did);
sys/dev/acpi/acpidmar.c
1483
val |= IOTLB_DR;
sys/dev/acpi/acpidmar.c
1485
val |= IOTLB_DW;
sys/dev/acpi/acpidmar.c
1492
iommu_write_8(iommu, DMAR_IOTLB_REG(iommu), val);
sys/dev/acpi/acpidmar.c
1494
val = iommu_read_8(iommu, DMAR_IOTLB_REG(iommu));
sys/dev/acpi/acpidmar.c
1495
if ((val & IOTLB_IVT) == 0)
sys/dev/acpi/acpidmar.c
1499
if (val & IOTLB_IVT)
sys/dev/acpi/acpidmar.c
1721
uint64_t val;
sys/dev/acpi/acpidmar.c
1731
val = CCMD_ICC;
sys/dev/acpi/acpidmar.c
1734
val |= CIG_GLOBAL;
sys/dev/acpi/acpidmar.c
1737
val |= CIG_DOMAIN | CCMD_DID(did);
sys/dev/acpi/acpidmar.c
1740
val |= CIG_DEVICE | CCMD_DID(did) |
sys/dev/acpi/acpidmar.c
1747
iommu_write_8(iommu, DMAR_CCMD_REG, val);
sys/dev/acpi/acpidmar.c
1749
val = iommu_read_8(iommu, DMAR_CCMD_REG);
sys/dev/acpi/acpidmar.c
1750
if ((val & CCMD_ICC) == 0)
sys/dev/acpi/acpidmar.c
1754
if (val & CCMD_ICC)
sys/dev/acpi/acpidmar.c
2873
if (pte[i].val & PTE_P) {
sys/dev/acpi/acpidmar.c
2875
npte = (void *)PMAP_DIRECT_MAP((pte[i].val & PTE_PADDR_MASK));
sys/dev/acpi/acpidmar.c
2877
pte[i].val, (pte[i].val >> 9) & 7);
sys/dev/acpi/acpidmar.c
2881
pte[i].val, va | sh);
sys/dev/acpi/acpidmar.c
3901
if (!(pte[i].val & PTE_P))
sys/dev/acpi/acpidmar.c
3904
pb = pte[i].val & ~VTD_PAGE_MASK;
sys/dev/acpi/acpidmar.c
3908
pte[i].val == PTE_R ? 'r' : ' ',
sys/dev/acpi/acpidmar.c
3909
pte[i].val & PTE_W ? 'w' : ' ',
sys/dev/acpi/acpidmar.c
547
uint64_t val;
sys/dev/acpi/acpidmar.c
564
pte->val = create ? (pa | flags) : 0;
sys/dev/acpi/acpidmar.c
569
val = pte->val;
sys/dev/acpi/acpidmar.c
570
if (val & PTE_P) {
sys/dev/acpi/acpidmar.c
571
npte = (void *)PMAP_DIRECT_MAP((val & VTD_PTE_MASK));
sys/dev/acpi/acpidmar.c
584
val = pte->val;
sys/dev/acpi/acpidmar.c
585
if (!(val & PTE_P)) {
sys/dev/acpi/acpidmar.c
586
pte->val = paddr | PTE_P | PTE_R | PTE_W;
sys/dev/acpi/acpidmar.c
588
val = pte->val;
sys/dev/acpi/acpidmar.c
596
npte = (void *)PMAP_DIRECT_MAP((val & VTD_PTE_MASK));
sys/dev/acpi/acpidmar.c
623
uint64_t val;
sys/dev/acpi/acpidmar.c
627
val = pte[idx].val;
sys/dev/acpi/acpidmar.c
629
if (!(val & PTE_P)) {
sys/dev/acpi/acpidmar.c
642
val = pte[idx].val;
sys/dev/acpi/acpidmar.c
643
if (!(val & PTE_P)) {
sys/dev/acpi/acpidmar.c
644
pte[idx].val = paddr | flags;
sys/dev/acpi/acpidmar.c
646
val = pte[idx].val;
sys/dev/acpi/acpidmar.c
655
return (void *)PMAP_DIRECT_MAP((val & PTE_PADDR_MASK));
sys/dev/acpi/acpidmar.c
692
pte[idx].val = create ? (pa | flags) : 0;
sys/dev/acpi/acpidmar.h
448
uint64_t val;
sys/dev/acpi/acpiec.c
101
while (((stat = acpiec_status(sc)) & mask) != val) {
sys/dev/acpi/acpiec.c
121
acpiec_write_data(struct acpiec_softc *sc, uint8_t val)
sys/dev/acpi/acpiec.c
124
dnprintf(40, "acpiec: write_data -- %d\n", (int)val);
sys/dev/acpi/acpiec.c
125
bus_space_write_1(sc->sc_data_bt, sc->sc_data_bh, 0, val);
sys/dev/acpi/acpiec.c
129
acpiec_write_cmd(struct acpiec_softc *sc, uint8_t val)
sys/dev/acpi/acpiec.c
132
dnprintf(40, "acpiec: write_cmd -- %d\n", (int)val);
sys/dev/acpi/acpiec.c
133
bus_space_write_1(sc->sc_cmd_bt, sc->sc_cmd_bh, 0, val);
sys/dev/acpi/acpiec.c
139
uint8_t val;
sys/dev/acpi/acpiec.c
142
val = bus_space_read_1(sc->sc_data_bt, sc->sc_data_bh, 0);
sys/dev/acpi/acpiec.c
144
dnprintf(40, "acpiec: read_data %d\n", (int)val);
sys/dev/acpi/acpiec.c
146
return (val);
sys/dev/acpi/acpiec.c
172
uint8_t val;
sys/dev/acpi/acpiec.c
180
val = acpiec_read_data(sc);
sys/dev/acpi/acpiec.c
182
return (val);
sys/dev/acpi/acpiec.c
91
acpiec_wait(struct acpiec_softc *sc, uint8_t mask, uint8_t val)
sys/dev/acpi/acpiec.c
99
"\20\x8IGN\x7SMI\x6SCI\05BURST\04CMD\03IGN\02IBF\01OBF", (int)val);
sys/dev/acpi/acpihpet.c
100
bus_space_write_4(iot, ioh, ioa + 4, val >> 32);
sys/dev/acpi/acpihpet.c
101
bus_space_write_4(iot, ioh, ioa, val & 0xffffffff);
sys/dev/acpi/acpihpet.c
88
uint64_t val;
sys/dev/acpi/acpihpet.c
90
val = bus_space_read_4(iot, ioh, ioa + 4);
sys/dev/acpi/acpihpet.c
91
val = val << 32;
sys/dev/acpi/acpihpet.c
92
val |= bus_space_read_4(iot, ioh, ioa);
sys/dev/acpi/acpihpet.c
93
return (val);
sys/dev/acpi/acpihpet.c
98
uint64_t val)
sys/dev/acpi/acpisbs.c
170
int64_t sbs, val;
sys/dev/acpi/acpisbs.c
188
NULL, &val))
sys/dev/acpi/acpisbs.c
190
sc->sc_ec_base = (val >> 8) & 0xff;
sys/dev/acpi/acpisbs.c
420
uint8_t val;
sys/dev/acpi/acpisbs.c
427
acpiec_read(sc->sc_ec, sc->sc_ec_base + SMBUS_PRTCL, 1, &val);
sys/dev/acpi/acpisbs.c
428
if (val == 0)
sys/dev/acpi/acpisbs.c
437
acpiec_read(sc->sc_ec, sc->sc_ec_base + SMBUS_STS, 1, &val);
sys/dev/acpi/acpisbs.c
438
if (val & SMBUS_STS_MASK) {
sys/dev/acpi/acpisbs.c
458
acpiec_read(sc->sc_ec, sc->sc_ec_base + SMBUS_BCNT, 1, &val);
sys/dev/acpi/acpisbs.c
459
val &= 0x1f;
sys/dev/acpi/acpisbs.c
460
if (len > val)
sys/dev/acpi/acpisbs.c
461
len = val;
sys/dev/acpi/acpisbs.c
465
1, &val);
sys/dev/acpi/acpisbs.c
466
((char *)buf)[j] = val;
sys/dev/acpi/acpisbs.c
55
#define CHECK(kind, cmd, val, senst, sens) { \
sys/dev/acpi/acpisbs.c
57
offsetof(struct acpisbs_battery, val), \
sys/dev/acpi/acpisbs.c
59
#val, senst, sens }
sys/dev/acpi/acpisony.c
136
int val, key = 0;
sys/dev/acpi/acpisony.c
152
val = acpisony_set_hotkey(sc, key, 0x200);
sys/dev/acpi/acpisony.c
153
if (val < 0) {
sys/dev/acpi/acpisony.c
154
printf("returned val = %X", val);
sys/dev/acpi/acpisony.c
157
notify = val & 0xff;
sys/dev/acpi/acpisony.c
249
int val;
sys/dev/acpi/acpisony.c
256
val = aml_val2int(&res);
sys/dev/acpi/acpisony.c
258
if (val == key) {
sys/dev/acpi/acpisony.c
259
DPRINTF(("Matched key %X\n", val));
sys/dev/acpi/acpisony.c
268
acpisony_set_hotkey(struct acpisony_softc *sc, int key, int val)
sys/dev/acpi/acpisony.c
281
arg.v_integer = off | val;
sys/dev/acpi/acpisony.c
292
int val;
sys/dev/acpi/acpisony.c
294
val = acpisony_get_brightness(sc);
sys/dev/acpi/acpisony.c
295
DPRINTF(("current value = %X", val));
sys/dev/acpi/acpisony.c
296
if (val > 0)
sys/dev/acpi/acpisony.c
297
val--;
sys/dev/acpi/acpisony.c
299
val = 0;
sys/dev/acpi/acpisony.c
300
DPRINTF(("next value = %X", val));
sys/dev/acpi/acpisony.c
301
acpisony_set_brightness(sc, val);
sys/dev/acpi/acpisony.c
308
int val;
sys/dev/acpi/acpisony.c
311
val = aml_val2int(&res);
sys/dev/acpi/acpisony.c
314
return val;
sys/dev/acpi/acpitoshiba.c
236
int i, val;
sys/dev/acpi/acpitoshiba.c
257
val = aml_val2int(res.v_package[HCI_REG_CX]);
sys/dev/acpi/acpitoshiba.c
260
return (val);
sys/dev/acpi/acpitz.c
444
uint64_t val;
sys/dev/acpi/acpitz.c
446
if (!aml_evalinteger(sc->sc_acpi, sc->sc_devnode, name, 0, NULL, &val))
sys/dev/acpi/acpitz.c
447
return (val);
sys/dev/acpi/acpiwmi.c
289
asus_dev_set(struct wmiasus *wh, uint32_t devid, uint32_t val)
sys/dev/acpi/acpiwmi.c
291
return wmi_eval_method(&wh->w_wmi, 0, ASUS_METHOD_DSET, devid, val);
sys/dev/acpi/acpiwmi.c
294
asus_toggle(struct wmiasus *wh, int devid, int *val)
sys/dev/acpi/acpiwmi.c
308
*val += 1;
sys/dev/acpi/acpiwmi.c
309
if (*val > maxval)
sys/dev/acpi/acpiwmi.c
310
*val = 0;
sys/dev/acpi/acpiwmi.c
311
asus_dev_set(wh, devid, *val | mask);
sys/dev/acpi/amdpmc.c
452
uint32_t val;
sys/dev/acpi/amdpmc.c
456
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PMC_RESP);
sys/dev/acpi/amdpmc.c
457
if (val)
sys/dev/acpi/amdpmc.c
469
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PMC_RESP);
sys/dev/acpi/amdpmc.c
470
if (val)
sys/dev/acpi/amdpmc.c
477
switch (val) {
sys/dev/acpi/asmc.c
436
asmc_write(struct asmc_softc *sc, uint8_t off, uint8_t val)
sys/dev/acpi/asmc.c
441
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
sys/dev/acpi/asmc.c
449
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
sys/dev/acpi/ccpmic.c
139
uint8_t val;
sys/dev/acpi/ccpmic.c
144
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/ccpmic.c
150
val = 0xff;
sys/dev/acpi/ccpmic.c
153
return val;
sys/dev/acpi/ccpmic.c
157
ccpmic_write_1(struct ccpmic_softc *sc, uint8_t reg, uint8_t val, int flags)
sys/dev/acpi/ccpmic.c
163
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/ccpmic.c
280
uint8_t reg, val;
sys/dev/acpi/ccpmic.c
297
val = ccpmic_read_1(sc, reg, 0);
sys/dev/acpi/ccpmic.c
299
if ((val & CCPMIC_PWR_SEL) && (val & CCPMIC_PWR_ON))
sys/dev/acpi/ccpmic.c
305
val |= CCPMIC_PWR_ON;
sys/dev/acpi/ccpmic.c
307
val &= ~CCPMIC_PWR_ON;
sys/dev/acpi/ccpmic.c
308
ccpmic_write_1(sc, reg, val | CCPMIC_PWR_SEL, 0);
sys/dev/acpi/chvgpio.c
102
chvgpio_write_pad_cfg1(struct chvgpio_softc *sc, int pin, uint32_t val)
sys/dev/acpi/chvgpio.c
105
chvgpio_pad_cfg0_offset(pin) + 4, val);
sys/dev/acpi/chvgpio.c
88
chvgpio_write_pad_cfg0(struct chvgpio_softc *sc, int pin, uint32_t val)
sys/dev/acpi/chvgpio.c
91
chvgpio_pad_cfg0_offset(pin), val);
sys/dev/acpi/dsdt.c
1028
aml_freevalue(struct aml_value *val)
sys/dev/acpi/dsdt.c
1032
if (val == NULL)
sys/dev/acpi/dsdt.c
1034
switch (val->type) {
sys/dev/acpi/dsdt.c
1036
acpi_os_free(val->v_string);
sys/dev/acpi/dsdt.c
1039
acpi_os_free(val->v_buffer);
sys/dev/acpi/dsdt.c
1042
for (idx = 0; idx < val->length; idx++)
sys/dev/acpi/dsdt.c
1043
aml_delref(&val->v_package[idx], "");
sys/dev/acpi/dsdt.c
1044
acpi_os_free(val->v_package);
sys/dev/acpi/dsdt.c
1047
aml_delref(&val->v_objref.ref, "");
sys/dev/acpi/dsdt.c
1051
aml_delref(&val->v_field.ref1, "");
sys/dev/acpi/dsdt.c
1052
aml_delref(&val->v_field.ref2, "");
sys/dev/acpi/dsdt.c
1055
val->type = 0;
sys/dev/acpi/dsdt.c
1056
memset(&val->_, 0, sizeof(val->_));
sys/dev/acpi/dsdt.c
1066
aml_convradix(uint64_t val, int iradix, int oradix)
sys/dev/acpi/dsdt.c
1072
while (val) {
sys/dev/acpi/dsdt.c
1073
rv += (val % iradix) * pwr;
sys/dev/acpi/dsdt.c
1074
val /= iradix;
sys/dev/acpi/dsdt.c
1082
aml_lsb(uint64_t val)
sys/dev/acpi/dsdt.c
1086
if (val == 0)
sys/dev/acpi/dsdt.c
1089
for (lsb = 1; !(val & 0x1); lsb++)
sys/dev/acpi/dsdt.c
1090
val >>= 1;
sys/dev/acpi/dsdt.c
1097
aml_msb(uint64_t val)
sys/dev/acpi/dsdt.c
1101
if (val == 0)
sys/dev/acpi/dsdt.c
1104
for (msb = 1; val != 0x1; msb++)
sys/dev/acpi/dsdt.c
1105
val >>= 1;
sys/dev/acpi/dsdt.c
1519
aml_callosi(struct aml_scope *scope, struct aml_value *val)
sys/dev/acpi/dsdt.c
1707
struct aml_value *val = arg;
sys/dev/acpi/dsdt.c
1714
else if (val->type == AML_OBJTYPE_NAMEREF) {
sys/dev/acpi/dsdt.c
1715
node = aml_searchname(node, aml_getname(val->v_nameref));
sys/dev/acpi/dsdt.c
1717
_aml_setvalue(val, AML_OBJTYPE_OBJREF, AMLOP_NAMECHAR,
sys/dev/acpi/dsdt.c
1720
} else if (val->type == AML_OBJTYPE_PACKAGE) {
sys/dev/acpi/dsdt.c
1721
for (i = 0; i < val->length; i++)
sys/dev/acpi/dsdt.c
1722
aml_fixup_node(node, val->v_package[i]);
sys/dev/acpi/dsdt.c
1735
aml_val_to_string(const struct aml_value *val)
sys/dev/acpi/dsdt.c
1741
switch (val->type) {
sys/dev/acpi/dsdt.c
1743
len = val->length;
sys/dev/acpi/dsdt.c
1746
memcpy(buffer, val->v_buffer, len);
sys/dev/acpi/dsdt.c
1750
strlcpy(buffer, val->v_string, sizeof(buffer));
sys/dev/acpi/dsdt.c
1753
snprintf(buffer, sizeof(buffer), "%llx", val->v_integer);
sys/dev/acpi/dsdt.c
1757
"Failed to convert type %d to string!", val->type);
sys/dev/acpi/dsdt.c
1801
aml_addref(struct aml_value *val, const char *lbl)
sys/dev/acpi/dsdt.c
1803
if (val == NULL)
sys/dev/acpi/dsdt.c
1806
val, lbl,
sys/dev/acpi/dsdt.c
1807
val->node ? aml_nodename(val->node) : "INTERNAL",
sys/dev/acpi/dsdt.c
1808
val->refcnt);
sys/dev/acpi/dsdt.c
1809
val->refcnt++;
sys/dev/acpi/dsdt.c
1816
struct aml_value *val;
sys/dev/acpi/dsdt.c
1820
val = *pv;
sys/dev/acpi/dsdt.c
1821
val->refcnt--;
sys/dev/acpi/dsdt.c
1822
if (val->refcnt == 0) {
sys/dev/acpi/dsdt.c
1824
val, lbl,
sys/dev/acpi/dsdt.c
1825
val->refcnt,
sys/dev/acpi/dsdt.c
1826
val->node ? aml_nodename(val->node) : "INTERNAL",
sys/dev/acpi/dsdt.c
1827
val->refcnt ? "" : "---------------- FREEING");
sys/dev/acpi/dsdt.c
1829
aml_freevalue(val);
sys/dev/acpi/dsdt.c
1830
acpi_os_free(val);
sys/dev/acpi/dsdt.c
2288
aml_evalhid(struct aml_node *node, struct aml_value *val)
sys/dev/acpi/dsdt.c
2290
if (aml_evalname(acpi_softc, node, "_HID", 0, NULL, val))
sys/dev/acpi/dsdt.c
2294
if (val->type == AML_OBJTYPE_INTEGER)
sys/dev/acpi/dsdt.c
2295
_aml_setvalue(val, AML_OBJTYPE_STRING, -1, aml_eisaid(val->v_integer));
sys/dev/acpi/dsdt.c
2368
void aml_rwindexfield(struct aml_value *, struct aml_value *val, int);
sys/dev/acpi/dsdt.c
2504
aml_rwgen(struct aml_value *rgn, int bpos, int blen, struct aml_value *val,
sys/dev/acpi/dsdt.c
2545
vbit = &val->v_integer;
sys/dev/acpi/dsdt.c
2563
_aml_setvalue(val, AML_OBJTYPE_BUFFER, (blen + 7) >> 3, 0);
sys/dev/acpi/dsdt.c
2566
val = aml_convert(val, AML_OBJTYPE_BUFFER, -1);
sys/dev/acpi/dsdt.c
2568
if (blen > (val->length << 3))
sys/dev/acpi/dsdt.c
2569
blen = val->length << 3;
sys/dev/acpi/dsdt.c
2571
vbit = val->v_buffer;
sys/dev/acpi/dsdt.c
2575
_aml_setvalue(val, AML_OBJTYPE_INTEGER, 0, 0);
sys/dev/acpi/dsdt.c
2578
val = aml_convert(val, AML_OBJTYPE_INTEGER, -1);
sys/dev/acpi/dsdt.c
2601
aml_delref(&val, "fld.write");
sys/dev/acpi/dsdt.c
2607
aml_rwgpio(struct aml_value *conn, int bpos, int blen, struct aml_value *val,
sys/dev/acpi/dsdt.c
2629
v = aml_val2int(val);
sys/dev/acpi/dsdt.c
2633
_aml_setvalue(val, AML_OBJTYPE_INTEGER, v, NULL);
sys/dev/acpi/dsdt.c
2641
struct aml_value *val, int mode, int flag)
sys/dev/acpi/dsdt.c
2719
_aml_setvalue(val, AML_OBJTYPE_BUFFER, buflen + 2, NULL);
sys/dev/acpi/dsdt.c
2725
buf = val->v_buffer;
sys/dev/acpi/dsdt.c
2762
struct aml_value *val, int mode, int flag)
sys/dev/acpi/dsdt.c
2803
_aml_setvalue(val, AML_OBJTYPE_BUFFER, buflen + 2, NULL);
sys/dev/acpi/dsdt.c
2805
buf = val->v_buffer;
sys/dev/acpi/dsdt.c
2812
aml_rwindexfield(struct aml_value *fld, struct aml_value *val, int mode)
sys/dev/acpi/dsdt.c
2847
_aml_setvalue(val, AML_OBJTYPE_BUFFER,
sys/dev/acpi/dsdt.c
2850
vbit = val->v_buffer;
sys/dev/acpi/dsdt.c
2854
_aml_setvalue(val, AML_OBJTYPE_INTEGER, 0, 0);
sys/dev/acpi/dsdt.c
2856
vbit = &val->v_integer;
sys/dev/acpi/dsdt.c
2886
aml_rwfield(struct aml_value *fld, int bpos, int blen, struct aml_value *val,
sys/dev/acpi/dsdt.c
2900
aml_rwindexfield(fld, val, mode);
sys/dev/acpi/dsdt.c
2905
val, mode, fld->v_field.flags);
sys/dev/acpi/dsdt.c
2909
aml_rwgpio(ref2, bpos, blen, val, mode,
sys/dev/acpi/dsdt.c
2915
val, mode, fld->v_field.flags);
sys/dev/acpi/dsdt.c
2919
val, mode, fld->v_field.flags);
sys/dev/acpi/dsdt.c
2924
_aml_setvalue(val, AML_OBJTYPE_INTEGER, 0, 0);
sys/dev/acpi/dsdt.c
2925
aml_bufcpy(&val->v_integer, 0, ref1->v_buffer,
sys/dev/acpi/dsdt.c
2929
val = aml_convert(val, AML_OBJTYPE_INTEGER, -1);
sys/dev/acpi/dsdt.c
2930
aml_bufcpy(ref1->v_buffer, fld->v_field.bitpos, &val->v_integer,
sys/dev/acpi/dsdt.c
2932
aml_delref(&val, "wrbuffld");
sys/dev/acpi/dsdt.c
3834
aml_gettgt(struct aml_value *val, int opcode)
sys/dev/acpi/dsdt.c
3836
while (val && val->type == AML_OBJTYPE_OBJREF) {
sys/dev/acpi/dsdt.c
3844
val->v_objref.type == AMLOP_PACKAGE)
sys/dev/acpi/dsdt.c
3845
return val;
sys/dev/acpi/dsdt.c
3846
val = val->v_objref.ref;
sys/dev/acpi/dsdt.c
3848
return val;
sys/dev/acpi/dsdt.c
4723
aml_node_setval(struct acpi_softc *sc, struct aml_node *node, int64_t val)
sys/dev/acpi/dsdt.c
4732
env.v_integer = val;
sys/dev/acpi/dsdt.c
4826
struct aml_value *val;
sys/dev/acpi/dsdt.c
4831
val = pkg->v_package[idx];
sys/dev/acpi/dsdt.c
4832
if (val->type == AML_OBJTYPE_NAMEREF) {
sys/dev/acpi/dsdt.c
4833
node = aml_searchrel(root, aml_getname(val->v_nameref));
sys/dev/acpi/dsdt.c
4836
aml_getname(val->v_nameref));
sys/dev/acpi/dsdt.c
4839
val = node->value;
sys/dev/acpi/dsdt.c
4841
if (val->type == AML_OBJTYPE_OBJREF)
sys/dev/acpi/dsdt.c
4842
val = val->v_objref.ref;
sys/dev/acpi/dsdt.c
4843
if (val->node) {
sys/dev/acpi/dsdt.c
4846
dl->dev_node = val->node;
sys/dev/acpi/dsdt.c
502
aml_setbit(uint8_t *pb, int bit, int val)
sys/dev/acpi/dsdt.c
506
if (val)
sys/dev/acpi/dsdt.c
793
aml_showvalue(struct aml_value *val)
sys/dev/acpi/dsdt.c
797
if (val == NULL)
sys/dev/acpi/dsdt.c
800
if (val->node)
sys/dev/acpi/dsdt.c
801
printf(" [%s]", aml_nodename(val->node));
sys/dev/acpi/dsdt.c
802
printf(" %p cnt:%.2x stk:%.2x", val, val->refcnt, val->stack);
sys/dev/acpi/dsdt.c
803
switch (val->type) {
sys/dev/acpi/dsdt.c
805
printf(" integer: %llx\n", val->v_integer);
sys/dev/acpi/dsdt.c
808
printf(" string: %s\n", val->v_string);
sys/dev/acpi/dsdt.c
811
printf(" method: %.2x\n", val->v_method.flags);
sys/dev/acpi/dsdt.c
814
printf(" package: %.2x\n", val->length);
sys/dev/acpi/dsdt.c
815
for (idx = 0; idx < val->length; idx++)
sys/dev/acpi/dsdt.c
816
aml_showvalue(val->v_package[idx]);
sys/dev/acpi/dsdt.c
819
printf(" buffer: %.2x {", val->length);
sys/dev/acpi/dsdt.c
820
for (idx = 0; idx < val->length; idx++)
sys/dev/acpi/dsdt.c
821
printf("%s%.2x", idx ? ", " : "", val->v_buffer[idx]);
sys/dev/acpi/dsdt.c
827
val->v_field.bitpos, val->v_field.bitlen,
sys/dev/acpi/dsdt.c
828
val->v_field.ref1, val->v_field.ref2,
sys/dev/acpi/dsdt.c
829
aml_mnem(val->v_field.type, NULL));
sys/dev/acpi/dsdt.c
830
if (val->v_field.ref1)
sys/dev/acpi/dsdt.c
831
printf(" ref1: %s\n", aml_nodename(val->v_field.ref1->node));
sys/dev/acpi/dsdt.c
832
if (val->v_field.ref2)
sys/dev/acpi/dsdt.c
833
printf(" ref2: %s\n", aml_nodename(val->v_field.ref2->node));
sys/dev/acpi/dsdt.c
837
val->v_mutex ? val->v_mutex->amt_name : "",
sys/dev/acpi/dsdt.c
838
val->v_mutex ? val->v_mutex->amt_ref_count : 0);
sys/dev/acpi/dsdt.c
845
val->v_opregion.iospace, val->v_opregion.iobase,
sys/dev/acpi/dsdt.c
846
val->v_opregion.iolen);
sys/dev/acpi/dsdt.c
849
printf(" nameref: %s\n", aml_getname(val->v_nameref));
sys/dev/acpi/dsdt.c
856
val->v_processor.proc_id, val->v_processor.proc_addr,
sys/dev/acpi/dsdt.c
857
val->v_processor.proc_len);
sys/dev/acpi/dsdt.c
864
val->v_powerrsrc.pwr_level, val->v_powerrsrc.pwr_order);
sys/dev/acpi/dsdt.c
867
printf(" objref: %p index:%x opcode:%s\n", val->v_objref.ref,
sys/dev/acpi/dsdt.c
868
val->v_objref.index, aml_mnem(val->v_objref.type, 0));
sys/dev/acpi/dsdt.c
869
aml_showvalue(val->v_objref.ref);
sys/dev/acpi/dsdt.c
872
printf(" !!type: %x\n", val->type);
sys/dev/acpi/dwgpio.c
207
int val;
sys/dev/acpi/dwgpio.c
213
val = (reg >> pin) & 1;
sys/dev/acpi/dwgpio.c
214
return val;
sys/dev/acpi/dwgpio.c
218
dwgpio_write_pin(void *cookie, int pin, int val)
sys/dev/acpi/dwgpio.c
225
if (val)
sys/dev/acpi/dwgpio.c
45
#define HWRITE4(sc, reg, val) \
sys/dev/acpi/dwgpio.c
46
bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
sys/dev/acpi/inthid.c
165
uint64_t val;
sys/dev/acpi/inthid.c
174
if (inthid_eval(sc, INTHID_FUNC_HDMM, 0, &val) != 0) {
sys/dev/acpi/inthid.c
177
} else if (val != 0) {
sys/dev/acpi/inthid.c
178
printf(", unknown mode %lld\n", val);
sys/dev/acpi/inthid.c
182
if ((inthid_eval(sc, INTHID_FUNC_HEBC_V2, 0, &val) == 0 &&
sys/dev/acpi/inthid.c
183
(val & 0x60000)) ||
sys/dev/acpi/inthid.c
184
(inthid_eval(sc, INTHID_FUNC_HEBC_V1, 0, &val) == 0 &&
sys/dev/acpi/inthid.c
185
(val & 0x20000)))
sys/dev/acpi/pckbc_acpi.c
472
struct aml_value val;
sys/dev/acpi/pckbc_acpi.c
477
0, NULL, &val) != 0)
sys/dev/acpi/pckbc_acpi.c
479
if (val.type == AML_OBJTYPE_BUFFER && val.length >= 5)
sys/dev/acpi/pckbc_acpi.c
480
aml_parse_resource(&val, walker, crsdata);
sys/dev/acpi/pckbc_acpi.c
481
aml_freevalue(&val);
sys/dev/acpi/qcgpio.c
453
qcgpio_write_pin(void *cookie, int pin, int val)
sys/dev/acpi/qcgpio.c
462
if (val) {
sys/dev/acpi/qcgpio.c
61
#define HWRITE4(sc, reg, val) \
sys/dev/acpi/qcgpio.c
62
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/acpi/qciic.c
49
#define GENI_RX_FIFO_STATUS_WC(val) ((val) & 0xffffff)
sys/dev/acpi/qciic.c
53
#define HWRITE4(sc, reg, val) \
sys/dev/acpi/qciic.c
54
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/acpi/tipmic.c
166
uint8_t val;
sys/dev/acpi/tipmic.c
171
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/tipmic.c
177
val = 0xff;
sys/dev/acpi/tipmic.c
180
return val;
sys/dev/acpi/tipmic.c
184
tipmic_write_1(struct tipmic_softc *sc, uint8_t reg, uint8_t val, int flags)
sys/dev/acpi/tipmic.c
190
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/tipmic.c
407
uint8_t reg, val;
sys/dev/acpi/tipmic.c
424
val = tipmic_read_1(sc, reg, 0);
sys/dev/acpi/tipmic.c
426
*value = val & 0x1;
sys/dev/acpi/tipmic.c
429
val |= 0x1;
sys/dev/acpi/tipmic.c
431
val &= ~0x1;
sys/dev/acpi/tipmic.c
432
tipmic_write_1(sc, reg, val, 0);
sys/dev/acpi/tpm.c
694
uint32_t val, int msecs)
sys/dev/acpi/tpm.c
702
if ((r & mask) == val)
sys/dev/acpi/tpm.c
707
if ((r & mask) == val)
sys/dev/adb/akbd.c
530
int press, val;
sys/dev/adb/akbd.c
534
val = ADBK_KEYVAL(key);
sys/dev/adb/akbd.c
537
val = akbd_iso_swap(val);
sys/dev/adb/akbd.c
550
c = keyboard[val];
sys/dev/adb/akbd.c
565
wskbd_input(sc->sc_wskbddev, type, val);
sys/dev/audio.c
2304
vol->val = vol->mute = -1;
sys/dev/audio.c
2318
vol->val = dev->index;
sys/dev/audio.c
2331
return (vol->val != -1);
sys/dev/audio.c
2409
if (vol->val >= 0 && val_pending) {
sys/dev/audio.c
2410
ctrl.dev = vol->val;
sys/dev/audio.c
2433
audio_event(sc, vol->val);
sys/dev/audio.c
93
int val; /* index of the value control */
sys/dev/cardbus/cardbus_exrom.c
107
u_int16_t val;
sys/dev/cardbus/cardbus_exrom.c
111
val = READ_INT16(romt, romh, addr + CARDBUS_EXROM_SIGNATURE);
sys/dev/cardbus/cardbus_exrom.c
112
if (val != 0xaa55) {
sys/dev/cardbus/cardbus_exrom.c
114
"%u: 0x%04x\n", __func__, rom_image, val));
sys/dev/cardbus/if_athn_cardbus.c
274
athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
sys/dev/cardbus/if_athn_cardbus.c
278
bus_space_write_4(csc->sc_st, csc->sc_sh, addr, val);
sys/dev/cardbus/if_bwi_cardbus.c
245
bwi_cardbus_conf_write(void *self, uint32_t reg, uint32_t val)
sys/dev/cardbus/if_bwi_cardbus.c
250
pci_conf_write(pc, csc->csc_tag, reg, val);
sys/dev/cardbus/rbus.c
112
val = 1;
sys/dev/cardbus/rbus.c
115
val = extent_alloc_subregion(
sys/dev/cardbus/rbus.c
123
if (val == 0)
sys/dev/cardbus/rbus.c
127
if (val != 0) {
sys/dev/cardbus/rbus.c
70
int val;
sys/dev/dec/if_le_dec.c
102
LERDWR(port, val, ler1->ler1_rdp);
sys/dev/dec/if_le_dec.c
109
u_int16_t val;
sys/dev/dec/if_le_dec.c
112
LERDWR(0, ler1->ler1_rdp, val);
sys/dev/dec/if_le_dec.c
113
return (val);
sys/dev/dec/if_le_dec.c
122
le_dec_writereg(volatile u_short *regptr, u_short val)
sys/dev/dec/if_le_dec.c
126
while (*regptr != val) {
sys/dev/dec/if_le_dec.c
127
*regptr = val;
sys/dev/dec/if_le_dec.c
130
printf("le: Reg did not settle (to x%x): x%x\n", val,
sys/dev/dec/if_le_dec.c
64
void le_dec_writereg(volatile u_short *regptr, u_short val);
sys/dev/dec/if_le_dec.c
97
le_dec_wrcsr(struct lance_softc *sc, u_int16_t port, u_int16_t val)
sys/dev/fdt/amlclock.c
108
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlclock.c
109
regmap_write_4((sc)->sc_rm, (reg) << 2, (val))
sys/dev/fdt/amldwusb.c
107
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amldwusb.c
108
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amliic.c
60
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amliic.c
61
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlmmc.c
110
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlmmc.c
111
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlmmc.c
469
int inverted, val;
sys/dev/fdt/amlmmc.c
471
val = gpio_controller_get_pin(sc->sc_gpio);
sys/dev/fdt/amlmmc.c
474
return inverted ? !val : val;
sys/dev/fdt/amlpciephy.c
47
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlpciephy.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlpinctrl.c
686
int val;
sys/dev/fdt/amlpinctrl.c
699
val = (reg >> (pin + bank->in_bit)) & 1;
sys/dev/fdt/amlpinctrl.c
701
val = !val;
sys/dev/fdt/amlpinctrl.c
703
return val;
sys/dev/fdt/amlpinctrl.c
707
amlpinctrl_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/amlpinctrl.c
725
val = !val;
sys/dev/fdt/amlpinctrl.c
732
if (val)
sys/dev/fdt/amlpinctrl.c
737
if (val)
sys/dev/fdt/amlpinctrl.c
744
if (val)
sys/dev/fdt/amlpwm.c
52
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlpwm.c
53
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2, (val))
sys/dev/fdt/amlpwrc.c
121
uint32_t val;
sys/dev/fdt/amlpwrc.c
123
val = regmap_read_4(rm, reg << 2);
sys/dev/fdt/amlpwrc.c
125
val &= ~mask;
sys/dev/fdt/amlpwrc.c
127
val |= mask;
sys/dev/fdt/amlpwrc.c
128
regmap_write_4(rm, reg << 2, val);
sys/dev/fdt/amlpwrc.c
49
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlpwrc.c
50
regmap_write_4((sc)->sc_rm, (reg) << 2, (val))
sys/dev/fdt/amlreset.c
37
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlreset.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amltemp.c
50
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amltemp.c
51
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2, (val))
sys/dev/fdt/amluart.c
56
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amluart.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlusbphy.c
85
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlusbphy.c
86
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2711_pcie.c
158
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2711_pcie.c
159
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2711_rng.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2711_rng.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_bsc.c
66
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_bsc.c
67
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_dmac.c
141
uint32_t val;
sys/dev/fdt/bcm2835_dmac.c
192
val = bcmdmac_read(sc, DMAC_CS(index));
sys/dev/fdt/bcm2835_dmac.c
193
val |= DMAC_CS_RESET;
sys/dev/fdt/bcm2835_dmac.c
194
bcmdmac_write(sc, DMAC_CS(index), val);
sys/dev/fdt/bcm2835_dmac.c
271
uint32_t val;
sys/dev/fdt/bcm2835_dmac.c
276
val = bcmdmac_read(sc, DMAC_CS(ch->ch_index));
sys/dev/fdt/bcm2835_dmac.c
277
val |= DMAC_CS_RESET;
sys/dev/fdt/bcm2835_dmac.c
278
val &= ~DMAC_CS_ACTIVE;
sys/dev/fdt/bcm2835_dmac.c
279
bcmdmac_write(sc, DMAC_CS(ch->ch_index), val);
sys/dev/fdt/bcm2835_dmac.c
301
uint32_t val;
sys/dev/fdt/bcm2835_dmac.c
303
val = bcmdmac_read(sc, DMAC_CS(ch->ch_index));
sys/dev/fdt/bcm2835_dmac.c
304
if (ISSET(val, DMAC_CS_ACTIVE))
sys/dev/fdt/bcm2835_dmac.c
307
val |= DMAC_CS_ACTIVE;
sys/dev/fdt/bcm2835_dmac.c
308
bcmdmac_write(sc, DMAC_CS(ch->ch_index), val);
sys/dev/fdt/bcm2835_dmac.c
317
uint32_t val;
sys/dev/fdt/bcm2835_dmac.c
320
val = bcmdmac_read(sc, DMAC_CS(ch->ch_index));
sys/dev/fdt/bcm2835_dmac.c
321
val &= ~DMAC_CS_ACTIVE;
sys/dev/fdt/bcm2835_dmac.c
322
bcmdmac_write(sc, DMAC_CS(ch->ch_index), val);
sys/dev/fdt/bcm2835_dmac.c
330
val |= DMAC_CS_ACTIVE | DMAC_CS_ABORT;
sys/dev/fdt/bcm2835_dmac.c
331
bcmdmac_write(sc, DMAC_CS(ch->ch_index), val);
sys/dev/fdt/bcm2835_dog.c
46
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_dog.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_gpio.c
153
uint32_t val;
sys/dev/fdt/bcm2835_gpio.c
155
val = HREAD4(sc, GPFSEL(reg));
sys/dev/fdt/bcm2835_gpio.c
156
val &= ~(GPFSEL_MASK << shift);
sys/dev/fdt/bcm2835_gpio.c
157
HWRITE4(sc, GPFSEL(reg), val);
sys/dev/fdt/bcm2835_gpio.c
158
val |= ((func & GPFSEL_MASK) << shift);
sys/dev/fdt/bcm2835_gpio.c
159
HWRITE4(sc, GPFSEL(reg), val);
sys/dev/fdt/bcm2835_gpio.c
167
uint32_t val;
sys/dev/fdt/bcm2835_gpio.c
169
val = HREAD4(sc, GPPULL(reg));
sys/dev/fdt/bcm2835_gpio.c
170
val &= ~(GPPULL_MASK << shift);
sys/dev/fdt/bcm2835_gpio.c
172
val |= (pull << shift);
sys/dev/fdt/bcm2835_gpio.c
173
HWRITE4(sc, GPPULL(reg), val);
sys/dev/fdt/bcm2835_gpio.c
263
int val;
sys/dev/fdt/bcm2835_gpio.c
269
val = (reg >> (pin % 32)) & 1;
sys/dev/fdt/bcm2835_gpio.c
271
val = !val;
sys/dev/fdt/bcm2835_gpio.c
272
return val;
sys/dev/fdt/bcm2835_gpio.c
276
bcmgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/bcm2835_gpio.c
286
val = !val;
sys/dev/fdt/bcm2835_gpio.c
287
if (val)
sys/dev/fdt/bcm2835_gpio.c
320
bcmgpio_pin_write(void *cookie, int pin, int val)
sys/dev/fdt/bcm2835_gpio.c
328
bcmgpio_set_pin(sc, cells, val);
sys/dev/fdt/bcm2835_gpio.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_gpio.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_mbox.c
198
bcmmbox_reg_write(struct bcmmbox_softc *sc, int addr, uint32_t val)
sys/dev/fdt/bcm2835_mbox.c
200
bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, val);
sys/dev/fdt/bcm2835_rng.c
38
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_rng.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_temp.c
37
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_temp.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbgpio.c
182
int val;
sys/dev/fdt/bcmstbgpio.c
188
val = !!(reg & (1U << pin));
sys/dev/fdt/bcmstbgpio.c
190
val = !val;
sys/dev/fdt/bcmstbgpio.c
191
return val;
sys/dev/fdt/bcmstbgpio.c
195
bcmstbgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/bcmstbgpio.c
206
val = !val;
sys/dev/fdt/bcmstbgpio.c
207
if (val)
sys/dev/fdt/bcmstbgpio.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbgpio.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbintc.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbintc.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbpinctrl.c
175
uint32_t val;
sys/dev/fdt/bcmstbpinctrl.c
198
val = HREAD4(sc, sc->sc_pins[pin].func_reg * 4);
sys/dev/fdt/bcmstbpinctrl.c
199
val &= ~(FUNC_MASK << (sc->sc_pins[pin].func_off * 4));
sys/dev/fdt/bcmstbpinctrl.c
200
val |= (func << (sc->sc_pins[pin].func_off * 4));
sys/dev/fdt/bcmstbpinctrl.c
201
HWRITE4(sc, sc->sc_pins[pin].func_reg * 4, val);
sys/dev/fdt/bcmstbpinctrl.c
204
val = HREAD4(sc, sc->sc_pins[pin].bias_reg * 4);
sys/dev/fdt/bcmstbpinctrl.c
205
val &= ~(BIAS_MASK << (sc->sc_pins[pin].bias_off * 2));
sys/dev/fdt/bcmstbpinctrl.c
206
val |= (bias << (sc->sc_pins[pin].bias_off * 2));
sys/dev/fdt/bcmstbpinctrl.c
207
HWRITE4(sc, sc->sc_pins[pin].bias_reg * 4, val);
sys/dev/fdt/bcmstbpinctrl.c
41
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbpinctrl.c
42
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbrescal.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbrescal.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbreset.c
36
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbreset.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bd718x7.c
194
uint8_t val;
sys/dev/fdt/bd718x7.c
199
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/bd718x7.c
205
val = 0xff;
sys/dev/fdt/bd718x7.c
208
return val;
sys/dev/fdt/bd718x7.c
212
bdpmic_reg_write(struct bdpmic_softc *sc, int reg, uint8_t val)
sys/dev/fdt/bd718x7.c
219
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/cdpcie.c
63
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/cdpcie.c
64
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/cdsdhc.c
147
uint32_t mode, val;
sys/dev/fdt/cdsdhc.c
164
val = HREAD4(sc, HRS06);
sys/dev/fdt/cdsdhc.c
165
val &= ~HRS06_EMM_MASK;
sys/dev/fdt/cdsdhc.c
166
val |= mode;
sys/dev/fdt/cdsdhc.c
167
HWRITE4(sc, HRS06, val);
sys/dev/fdt/cdsdhc.c
70
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/cdsdhc.c
71
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/cduart.c
167
cduart_write(struct cduart_softc *sc, uint32_t reg, uint32_t val)
sys/dev/fdt/cduart.c
169
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/fdt/cwfg.c
257
uint8_t config, mode, val;
sys/dev/fdt/cwfg.c
273
if ((error = cwfg_read(sc, BATINFO_REG(n), &val)) != 0)
sys/dev/fdt/cwfg.c
275
if (sc->sc_batinfo[n] != val) {
sys/dev/fdt/cwfg.c
286
val = sc->sc_batinfo[n];
sys/dev/fdt/cwfg.c
287
if ((error = cwfg_write(sc, BATINFO_REG(n), val)) != 0)
sys/dev/fdt/cwfg.c
317
uint8_t val;
sys/dev/fdt/cwfg.c
339
if ((error = cwfg_read(sc, VCELL_HI_REG, &val)) != 0)
sys/dev/fdt/cwfg.c
341
tmp = ((val >> VCELL_HI_SHIFT) & VCELL_HI_MASK) << 8;
sys/dev/fdt/cwfg.c
342
if ((error = cwfg_read(sc, VCELL_LO_REG, &val)) != 0)
sys/dev/fdt/cwfg.c
344
tmp |= ((val >> VCELL_LO_SHIFT) & VCELL_LO_MASK);
sys/dev/fdt/cwfg.c
353
if ((error = cwfg_read(sc, SOC_HI_REG, &val)) != 0)
sys/dev/fdt/cwfg.c
355
if (val != 0xff) {
sys/dev/fdt/cwfg.c
356
sc->sc_sensor[CWFG_SENSOR_SOC].value = val * 1000;
sys/dev/fdt/cwfg.c
359
cwfg_power.battery_life = val;
sys/dev/fdt/cwfg.c
360
if (val > 50)
sys/dev/fdt/cwfg.c
362
else if (val > 25)
sys/dev/fdt/cwfg.c
370
if ((error = cwfg_read(sc, RTT_ALRT_HI_REG, &val)) != 0)
sys/dev/fdt/cwfg.c
372
rtt = ((val >> RTT_HI_SHIFT) & RTT_HI_MASK) << 8;
sys/dev/fdt/cwfg.c
373
if ((error = cwfg_read(sc, RTT_ALRT_LO_REG, &val)) != 0)
sys/dev/fdt/cwfg.c
375
rtt |= ((val >> RTT_LO_SHIFT) & RTT_LO_MASK);
sys/dev/fdt/cwfg.c
401
cwfg_read(struct cwfg_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/fdt/cwfg.c
403
return iic_smbus_read_byte(sc->sc_tag, sc->sc_addr, reg, val, 0);
sys/dev/fdt/cwfg.c
407
cwfg_write(struct cwfg_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/cwfg.c
409
return iic_smbus_write_byte(sc->sc_tag, sc->sc_addr, reg, val, 0);
sys/dev/fdt/dapmic.c
176
uint8_t val;
sys/dev/fdt/dapmic.c
181
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/dapmic.c
187
val = 0xff;
sys/dev/fdt/dapmic.c
190
return val;
sys/dev/fdt/dapmic.c
194
dapmic_reg_write(struct dapmic_softc *sc, int reg, uint8_t val)
sys/dev/fdt/dapmic.c
201
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/dwdog.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/dwdog.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/dwmmc.c
158
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/dwmmc.c
159
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/dwmmc.c
623
int inverted, val;
sys/dev/fdt/dwmmc.c
625
val = gpio_controller_get_pin(sc->sc_gpio);
sys/dev/fdt/dwmmc.c
628
return inverted ? !val : val;
sys/dev/fdt/dwpcie.c
1405
uint32_t apmu[2], val;
sys/dev/fdt/dwpcie.c
1423
val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
sys/dev/fdt/dwpcie.c
1424
val |= APMU_PCIE_APP_HOLD_PHY_RST;
sys/dev/fdt/dwpcie.c
1425
val &= ~APMU_PCIE_LTSSM_EN;
sys/dev/fdt/dwpcie.c
1426
regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL, val);
sys/dev/fdt/dwpcie.c
1429
val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CTRL_LOGIC);
sys/dev/fdt/dwpcie.c
1431
val | APMU_PCIE_SOFT_RESET);
sys/dev/fdt/dwpcie.c
1435
val &= ~APMU_PCIE_SOFT_RESET);
sys/dev/fdt/dwpcie.c
1448
val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
sys/dev/fdt/dwpcie.c
1450
val | APMU_PCIE_RC_PERST);
sys/dev/fdt/dwpcie.c
1455
val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
sys/dev/fdt/dwpcie.c
1457
val | APMU_PCIE_DEVICE_TYPE_SEL | APMU_PCIE_SYS_AUX_PWR_DET);
sys/dev/fdt/dwpcie.c
1462
val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
sys/dev/fdt/dwpcie.c
1464
val & ~APMU_PCIE_RC_PERST);
sys/dev/fdt/dwpcie.c
1470
val = HREAD4(sc, off + PCI_PCIE_LCAP);
sys/dev/fdt/dwpcie.c
1471
val &= ~PCI_PCIE_LCAP_ASPM_L1;
sys/dev/fdt/dwpcie.c
1472
HWRITE4(sc, off + PCI_PCIE_LCAP, val);
sys/dev/fdt/dwpcie.c
1479
val = regmap_read_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL);
sys/dev/fdt/dwpcie.c
1480
val &= ~APMU_PCIE_APP_HOLD_PHY_RST;
sys/dev/fdt/dwpcie.c
1481
val |= APMU_PCIE_LTSSM_EN;
sys/dev/fdt/dwpcie.c
1482
regmap_write_4(apmu_rm, apmu[1] + APMU_PCIE_CLK_RES_CTRL, val);
sys/dev/fdt/dwpcie.c
1484
val = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);
sys/dev/fdt/dwpcie.c
1485
val |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE;
sys/dev/fdt/dwpcie.c
1486
HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, val);
sys/dev/fdt/dwpcie.c
1491
val = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, K1_PHY_AHB_IRQ);
sys/dev/fdt/dwpcie.c
1493
val | K1_PHY_AHB_IRQ_EN);
sys/dev/fdt/dwpcie.c
1734
uint32_t val)
sys/dev/fdt/dwpcie.c
1738
IATU_OFFSET_UNROLL(index) + reg, val);
sys/dev/fdt/dwpcie.c
1747
HWRITE4(sc, IATU_OFFSET_VIEWPORT + reg, val);
sys/dev/fdt/dwpcie.c
192
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/dwpcie.c
193
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/ehci_fdt.c
294
uint32_t *reg, val;
sys/dev/fdt/ehci_fdt.c
332
val = bus_space_read_4(sc->sc.iot, ioh, 0x10);
sys/dev/fdt/ehci_fdt.c
333
val &= ~(1 << 3); /* clear SIDDQ */
sys/dev/fdt/ehci_fdt.c
334
bus_space_write_4(sc->sc.iot, ioh, 0x10, val);
sys/dev/fdt/ehci_fdt.c
351
uint32_t val;
sys/dev/fdt/ehci_fdt.c
363
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, SUNXI_HCI_ICR);
sys/dev/fdt/ehci_fdt.c
364
val |= SUNXI_AHB_INCR8 | SUNXI_AHB_INCR4;
sys/dev/fdt/ehci_fdt.c
365
val |= SUNXI_AHB_INCRX_ALIGN;
sys/dev/fdt/ehci_fdt.c
366
val |= SUNXI_ULPI_BYPASS;
sys/dev/fdt/ehci_fdt.c
367
bus_space_write_4(sc->sc.iot, sc->sc.ioh, SUNXI_HCI_ICR, val);
sys/dev/fdt/ehci_fdt.c
377
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
sys/dev/fdt/ehci_fdt.c
378
val &= ~(1 << 1);
sys/dev/fdt/ehci_fdt.c
379
bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
sys/dev/fdt/ehci_fdt.c
383
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
sys/dev/fdt/ehci_fdt.c
384
val &= ~(1 << 3);
sys/dev/fdt/ehci_fdt.c
385
bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
sys/dev/fdt/ehci_fdt.c
389
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
sys/dev/fdt/ehci_fdt.c
390
val |= 1 << 5;
sys/dev/fdt/ehci_fdt.c
391
bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
sys/dev/fdt/ehci_fdt.c
422
uint32_t val;
sys/dev/fdt/ehci_fdt.c
433
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, SUNXI_HCI_ICR);
sys/dev/fdt/ehci_fdt.c
434
val |= SUNXI_AHB_INCR16 | SUNXI_AHB_INCR8 | SUNXI_AHB_INCR4;
sys/dev/fdt/ehci_fdt.c
435
val |= SUNXI_AHB_INCRX_ALIGN;
sys/dev/fdt/ehci_fdt.c
436
val |= SUNXI_ULPI_BYPASS;
sys/dev/fdt/ehci_fdt.c
437
bus_space_write_4(sc->sc.iot, sc->sc.ioh, SUNXI_HCI_ICR, val);
sys/dev/fdt/es8316ac.c
187
uint8_t val;
sys/dev/fdt/es8316ac.c
199
val = escodec_read(sc, ESCODEC_SD_ADC_REG);
sys/dev/fdt/es8316ac.c
200
val &= ~SD_FMT_WL_MASK;
sys/dev/fdt/es8316ac.c
201
val |= SD_FMT_WL_16;
sys/dev/fdt/es8316ac.c
202
escodec_write(sc, ESCODEC_SD_ADC_REG, val);
sys/dev/fdt/es8316ac.c
204
val = escodec_read(sc, ESCODEC_SD_DAC_REG);
sys/dev/fdt/es8316ac.c
205
val &= ~SD_FMT_WL_MASK;
sys/dev/fdt/es8316ac.c
206
val |= SD_FMT_WL_16;
sys/dev/fdt/es8316ac.c
207
escodec_write(sc, ESCODEC_SD_DAC_REG, val);
sys/dev/fdt/es8316ac.c
213
val = HPMIXRT_LD2LHPMIX | HPMIXRT_RD2RHPMIX;
sys/dev/fdt/es8316ac.c
214
escodec_write(sc, ESCODEC_HPMIXRT_REG, val);
sys/dev/fdt/es8316ac.c
223
val = escodec_read(sc, ESCODEC_HPPWR_REG);
sys/dev/fdt/es8316ac.c
224
val &= ~HPPWR_PDN_CPHP;
sys/dev/fdt/es8316ac.c
225
escodec_write(sc, ESCODEC_HPPWR_REG, val);
sys/dev/fdt/es8316ac.c
228
val = escodec_read(sc, ESCODEC_CPPWR_REG);
sys/dev/fdt/es8316ac.c
229
val &= ~CPPWR_PDN_CP;
sys/dev/fdt/es8316ac.c
230
escodec_write(sc, ESCODEC_CPPWR_REG, val);
sys/dev/fdt/es8316ac.c
236
val = escodec_read(sc, ESCODEC_HPVOL_REG);
sys/dev/fdt/es8316ac.c
237
val &= ~HPVOL_PDN_LICAL;
sys/dev/fdt/es8316ac.c
238
val &= ~HPVOL_PDN_RICAL;
sys/dev/fdt/es8316ac.c
239
escodec_write(sc, ESCODEC_HPVOL_REG, val);
sys/dev/fdt/es8316ac.c
252
val = HPOUTEN_EN_HPL | HPOUTEN_EN_HPR |
sys/dev/fdt/es8316ac.c
254
escodec_write(sc, ESCODEC_HPOUTEN_REG, val);
sys/dev/fdt/es8316ac.c
264
uint8_t sd_clk, sd_fmt, val;
sys/dev/fdt/es8316ac.c
293
val = escodec_read(sc, ESCODEC_SD_CLK_REG);
sys/dev/fdt/es8316ac.c
294
val &= ~(SD_CLK_MSC|SD_CLK_BCLK_INV);
sys/dev/fdt/es8316ac.c
295
val |= sd_clk;
sys/dev/fdt/es8316ac.c
296
escodec_write(sc, ESCODEC_SD_CLK_REG, val);
sys/dev/fdt/es8316ac.c
298
val = escodec_read(sc, ESCODEC_SD_ADC_REG);
sys/dev/fdt/es8316ac.c
299
val &= ~SD_FMT_MASK;
sys/dev/fdt/es8316ac.c
300
val |= SD_FMT_I2S;
sys/dev/fdt/es8316ac.c
301
val &= ~SD_FMT_LRP;
sys/dev/fdt/es8316ac.c
302
val |= sd_fmt;
sys/dev/fdt/es8316ac.c
303
escodec_write(sc, ESCODEC_SD_ADC_REG, val);
sys/dev/fdt/es8316ac.c
305
val = escodec_read(sc, ESCODEC_SD_DAC_REG);
sys/dev/fdt/es8316ac.c
306
val &= ~SD_FMT_MASK;
sys/dev/fdt/es8316ac.c
307
val |= SD_FMT_I2S;
sys/dev/fdt/es8316ac.c
308
val &= ~SD_FMT_LRP;
sys/dev/fdt/es8316ac.c
309
val |= sd_fmt;
sys/dev/fdt/es8316ac.c
310
escodec_write(sc, ESCODEC_SD_DAC_REG, val);
sys/dev/fdt/es8316ac.c
312
val = escodec_read(sc, ESCODEC_CLKMAN1_REG);
sys/dev/fdt/es8316ac.c
313
val |= CLKMAN1_MCLK_ON;
sys/dev/fdt/es8316ac.c
314
val |= CLKMAN1_BCLK_ON;
sys/dev/fdt/es8316ac.c
315
val |= CLKMAN1_CLK_CP_ON;
sys/dev/fdt/es8316ac.c
316
val |= CLKMAN1_CLK_DAC_ON;
sys/dev/fdt/es8316ac.c
317
val |= CLKMAN1_ANACLK_DAC_ON;
sys/dev/fdt/es8316ac.c
318
escodec_write(sc, ESCODEC_CLKMAN1_REG, val);
sys/dev/fdt/es8316ac.c
356
uint8_t val;
sys/dev/fdt/es8316ac.c
358
if (iic_smbus_read_byte(sc->sc_tag, sc->sc_addr, reg, &val, 0) != 0)
sys/dev/fdt/es8316ac.c
359
val = 0xff;
sys/dev/fdt/es8316ac.c
361
return val;
sys/dev/fdt/es8316ac.c
365
escodec_write(struct escodec_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/es8316ac.c
367
(void)iic_smbus_write_byte(sc->sc_tag, sc->sc_addr, reg, val, 0);
sys/dev/fdt/es8316ac.c
529
uint8_t val;
sys/dev/fdt/es8316ac.c
539
val = escodec_read(sc, mix->reg[ch]);
sys/dev/fdt/es8316ac.c
547
val &= ~(mix->mask[ch] << mix->shift[ch]);
sys/dev/fdt/es8316ac.c
548
val |= (nvol & mix->mask[ch]) << mix->shift[ch];
sys/dev/fdt/es8316ac.c
549
escodec_write(sc, mix->reg[ch], val);
sys/dev/fdt/es8316ac.c
558
val = escodec_read(sc, mix->reg[0]);
sys/dev/fdt/es8316ac.c
560
val |= mix->mask[0];
sys/dev/fdt/es8316ac.c
562
val &= ~mix->mask[0];
sys/dev/fdt/es8316ac.c
563
escodec_write(sc, mix->reg[0], val);
sys/dev/fdt/es8316ac.c
578
uint8_t val;
sys/dev/fdt/es8316ac.c
588
val = escodec_read(sc, mix->reg[ch]);
sys/dev/fdt/es8316ac.c
590
nvol = (val >> mix->shift[ch]) & mix->mask[ch];
sys/dev/fdt/es8316ac.c
601
val = escodec_read(sc, mix->reg[0]);
sys/dev/fdt/es8316ac.c
602
mc->un.ord = (val & mix->mask[0]) != 0;
sys/dev/fdt/exrtc.c
133
uint32_t val;
sys/dev/fdt/exrtc.c
144
val = HREAD4(sc, RTCCTRL);
sys/dev/fdt/exrtc.c
145
HWRITE4(sc, RTCCTRL, val | RTCCTRL_RTCEN);
sys/dev/fdt/exrtc.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/exrtc.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/fanpwr.c
261
uint8_t val;
sys/dev/fdt/fanpwr.c
266
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/fanpwr.c
273
val = 0xff;
sys/dev/fdt/fanpwr.c
276
return val;
sys/dev/fdt/fanpwr.c
280
fanpwr_write(struct fanpwr_softc *sc, int reg, uint8_t val)
sys/dev/fdt/fanpwr.c
287
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/fusbtc.c
647
fusbtc_set_reg(struct fusbtc_softc *sc, uint8_t off, uint8_t val)
sys/dev/fdt/fusbtc.c
651
reg |= val;
sys/dev/fdt/fusbtc.c
656
fusbtc_clr_reg(struct fusbtc_softc *sc, uint8_t off, uint8_t val)
sys/dev/fdt/fusbtc.c
660
reg &= ~val;
sys/dev/fdt/fusbtc.c
667
uint8_t val = 0;
sys/dev/fdt/fusbtc.c
671
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/fusbtc.c
677
return val;
sys/dev/fdt/fusbtc.c
681
fusbtc_write_reg(struct fusbtc_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/fusbtc.c
685
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/gpiokeys.c
213
int val;
sys/dev/fdt/gpiokeys.c
215
val = gpio_controller_get_pin(key->key_pin);
sys/dev/fdt/gpiokeys.c
228
if (!val)
sys/dev/fdt/gpiokeys.c
238
key->key_sensor.value = !val;
sys/dev/fdt/gpiokeys.c
243
simplefb_burn_hook(!val);
sys/dev/fdt/gpiokeys.c
247
if (val)
sys/dev/fdt/hiclock.c
33
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/hiclock.c
34
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_cad.c
1047
uint64_t val = 0;
sys/dev/fdt/if_cad.c
1052
val = (val << 8) | eaddr[i];
sys/dev/fdt/if_cad.c
1055
hash ^= val;
sys/dev/fdt/if_cad.c
1056
val >>= 6;
sys/dev/fdt/if_cad.c
1604
int val;
sys/dev/fdt/if_cad.c
1608
val = HREAD4(sc, GEM_PHYMNTNC) & GEM_PHYMNTNC_DATA_MASK;
sys/dev/fdt/if_cad.c
1612
val &= ~EXTSR_1000THDX;
sys/dev/fdt/if_cad.c
1614
return val;
sys/dev/fdt/if_cad.c
1618
cad_mii_writereg(struct device *self, int phy_no, int reg, int val)
sys/dev/fdt/if_cad.c
1623
(val & GEM_PHYMNTNC_DATA_MASK));
sys/dev/fdt/if_cad.c
313
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/if_cad.c
314
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_cad.c
397
uint32_t val;
sys/dev/fdt/if_cad.c
476
val = HREAD4(sc, GEM_CFG6);
sys/dev/fdt/if_cad.c
477
if (val & GEM_CFG6_DMA64) {
sys/dev/fdt/if_cad.c
481
sc->sc_qmask |= GEM_CFG6_PRIQ_MASK(val);
sys/dev/fdt/if_cad.c
483
val = HREAD4(sc, GEM_CFG8);
sys/dev/fdt/if_cad.c
484
sc->sc_ntype1scr = GEM_CFG8_NUM_TYPE1_SCR(val);
sys/dev/fdt/if_cad.c
485
sc->sc_ntype2scr = GEM_CFG8_NUM_TYPE2_SCR(val);
sys/dev/fdt/if_cad.c
709
uint32_t val;
sys/dev/fdt/if_cad.c
891
val = HREAD4(sc, GEM_NETCFG);
sys/dev/fdt/if_cad.c
893
val |= GEM_NETCFG_FCSREM | GEM_NETCFG_RXCSUMEN | GEM_NETCFG_1000 |
sys/dev/fdt/if_cad.c
895
val &= ~GEM_NETCFG_RXOFFS_MASK;
sys/dev/fdt/if_cad.c
896
val |= ETHER_ALIGN << GEM_NETCFG_RXOFFS_SHIFT;
sys/dev/fdt/if_cad.c
897
val &= ~GEM_NETCFG_BCASTDI;
sys/dev/fdt/if_cad.c
900
val |= GEM_NETCFG_SGMIIEN | GEM_NETCFG_PCSSEL;
sys/dev/fdt/if_cad.c
902
val &= ~(GEM_NETCFG_SGMIIEN | GEM_NETCFG_PCSSEL);
sys/dev/fdt/if_cad.c
904
HWRITE4(sc, GEM_NETCFG, val);
sys/dev/fdt/if_cad.c
906
val = HREAD4(sc, GEM_DMACR);
sys/dev/fdt/if_cad.c
909
val |= GEM_DMACR_DMA64;
sys/dev/fdt/if_cad.c
911
val &= ~GEM_DMACR_DMA64;
sys/dev/fdt/if_cad.c
914
val |= GEM_DMACR_ES_DESCR;
sys/dev/fdt/if_cad.c
916
val &= ~GEM_DMACR_ES_DESCR;
sys/dev/fdt/if_cad.c
918
val &= ~GEM_DMACR_ES_PDATA;
sys/dev/fdt/if_cad.c
919
val |= GEM_DMACR_AHBDISC | GEM_DMACR_TXSIZE;
sys/dev/fdt/if_cad.c
920
val &= ~GEM_DMACR_RXSIZE_MASK;
sys/dev/fdt/if_cad.c
921
val |= GEM_DMACR_RXSIZE_8K;
sys/dev/fdt/if_cad.c
922
val &= ~GEM_DMACR_RXBUF_MASK;
sys/dev/fdt/if_cad.c
923
val |= (MCLBYTES / 64) << GEM_DMACR_RXBUF_SHIFT;
sys/dev/fdt/if_cad.c
924
val &= ~GEM_DMACR_BLEN_MASK;
sys/dev/fdt/if_cad.c
925
val |= GEM_DMACR_BLEN_16;
sys/dev/fdt/if_cad.c
928
val |= GEM_DMACR_TXCSUMEN;
sys/dev/fdt/if_cad.c
930
HWRITE4(sc, GEM_DMACR, val);
sys/dev/fdt/if_dwge.c
1607
#define RK3288_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 7) << 16 | ((val) << 7))
sys/dev/fdt/if_dwge.c
1609
#define RK3288_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0))
sys/dev/fdt/if_dwge.c
1613
#define RK3328_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 7) << 16 | ((val) << 7))
sys/dev/fdt/if_dwge.c
1614
#define RK3328_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0))
sys/dev/fdt/if_dwge.c
1638
#define RK3399_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 8) << 16 | ((val) << 8))
sys/dev/fdt/if_dwge.c
1640
#define RK3399_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0))
sys/dev/fdt/if_dwge.c
881
dwge_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/fdt/if_dwge.c
886
dwge_write(sc, GMAC_GMII_DATA, val);
sys/dev/fdt/if_dwqe_fdt.c
374
#define RK3568_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 8) << 16 | ((val) << 8))
sys/dev/fdt/if_dwqe_fdt.c
375
#define RK3568_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0))
sys/dev/fdt/if_dwqe_fdt.c
404
#define RK3588_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 8) << 16 | ((val) << 8))
sys/dev/fdt/if_dwqe_fdt.c
405
#define RK3588_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0))
sys/dev/fdt/if_dwxe.c
792
dwxe_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/fdt/if_dwxe.c
797
dwxe_write(sc, DWXE_MDIO_DATA, val);
sys/dev/fdt/if_fec.c
1187
fec_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/fdt/if_fec.c
1196
(val & 0xffff));
sys/dev/fdt/if_fec.c
140
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/if_fec.c
141
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_fec.c
513
uint32_t val, phy;
sys/dev/fdt/if_fec.c
533
val = ((rxc & 0xf) << 12) | ((rxdv & 0xf) << 8) |
sys/dev/fdt/if_fec.c
536
fec_miibus_writereg(dev, phy, 0x0c, val);
sys/dev/fdt/if_fec.c
538
val = ((rxd3 & 0xf) << 12) | ((rxd2 & 0xf) << 8) |
sys/dev/fdt/if_fec.c
541
fec_miibus_writereg(dev, phy, 0x0c, val);
sys/dev/fdt/if_fec.c
543
val = ((txd3 & 0xf) << 12) | ((txd2 & 0xf) << 8) |
sys/dev/fdt/if_fec.c
546
fec_miibus_writereg(dev, phy, 0x0c, val);
sys/dev/fdt/if_fec.c
554
uint32_t val, phy;
sys/dev/fdt/if_fec.c
574
val = ((rxdv & 0xf) << 4) || ((txen & 0xf) << 0);
sys/dev/fdt/if_fec.c
578
fec_miibus_writereg(dev, phy, 0x0e, val);
sys/dev/fdt/if_fec.c
580
val = ((rxd3 & 0xf) << 12) | ((rxd2 & 0xf) << 8) |
sys/dev/fdt/if_fec.c
585
fec_miibus_writereg(dev, phy, 0x0e, val);
sys/dev/fdt/if_fec.c
587
val = ((txd3 & 0xf) << 12) | ((txd2 & 0xf) << 8) |
sys/dev/fdt/if_fec.c
592
fec_miibus_writereg(dev, phy, 0x0e, val);
sys/dev/fdt/if_fec.c
594
val = ((txc & 0x1f) << 5) || ((rxc & 0x1f) << 0);
sys/dev/fdt/if_fec.c
598
fec_miibus_writereg(dev, phy, 0x0e, val);
sys/dev/fdt/if_mvneta.c
244
mvneta_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/fdt/if_mvneta.c
247
return sc->sc_mdio->md_writereg(sc->sc_mdio->md_cookie, phy, reg, val);
sys/dev/fdt/if_mvneta.c
86
#define MVNETA_WRITE(sc, reg, val) \
sys/dev/fdt/if_mvneta.c
87
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_mvneta.c
88
#define MVNETA_READ_FILTER(sc, reg, val, c) \
sys/dev/fdt/if_mvneta.c
89
bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
sys/dev/fdt/if_mvneta.c
90
#define MVNETA_WRITE_FILTER(sc, reg, val, c) \
sys/dev/fdt/if_mvneta.c
91
bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
sys/dev/fdt/if_mvpp.c
1925
mvpp2_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/fdt/if_mvpp.c
1928
return sc->sc_mdio->md_writereg(sc->sc_mdio->md_cookie, phy, reg, val);
sys/dev/fdt/if_mvpp.c
3020
uint32_t val;
sys/dev/fdt/if_mvpp.c
3026
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(prxq));
sys/dev/fdt/if_mvpp.c
3027
val &= ~MVPP2_RXQ_POOL_LONG_MASK;
sys/dev/fdt/if_mvpp.c
3028
val |= ((pool << MVPP2_RXQ_POOL_LONG_OFFS) & MVPP2_RXQ_POOL_LONG_MASK);
sys/dev/fdt/if_mvpp.c
3030
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(prxq), val);
sys/dev/fdt/if_mvpp.c
3036
uint32_t val;
sys/dev/fdt/if_mvpp.c
3042
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(prxq));
sys/dev/fdt/if_mvpp.c
3043
val &= ~MVPP2_RXQ_POOL_SHORT_MASK;
sys/dev/fdt/if_mvpp.c
3044
val |= ((pool << MVPP2_RXQ_POOL_SHORT_OFFS) & MVPP2_RXQ_POOL_SHORT_MASK);
sys/dev/fdt/if_mvpp.c
3046
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(prxq), val);
sys/dev/fdt/if_mvpp.c
3190
int val, queue;
sys/dev/fdt/if_mvpp.c
3201
val = mvpp2_read(port->sc, MVPP2_TXP_SCHED_REFILL_REG);
sys/dev/fdt/if_mvpp.c
3202
val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
sys/dev/fdt/if_mvpp.c
3203
val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
sys/dev/fdt/if_mvpp.c
3204
val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
sys/dev/fdt/if_mvpp.c
3205
mvpp2_write(port->sc, MVPP2_TXP_SCHED_REFILL_REG, val);
sys/dev/fdt/if_mvpp.c
3206
val = MVPP2_TXP_TOKEN_SIZE_MAX;
sys/dev/fdt/if_mvpp.c
3207
mvpp2_write(port->sc, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
sys/dev/fdt/if_mvpp.c
3221
uint32_t val;
sys/dev/fdt/if_mvpp.c
3226
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(queue));
sys/dev/fdt/if_mvpp.c
3227
val &= ~MVPP2_RXQ_DISABLE_MASK;
sys/dev/fdt/if_mvpp.c
3228
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(queue), val);
sys/dev/fdt/if_mvpp.c
3235
uint32_t val;
sys/dev/fdt/if_mvpp.c
3240
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(queue));
sys/dev/fdt/if_mvpp.c
3241
val |= MVPP2_RXQ_DISABLE_MASK;
sys/dev/fdt/if_mvpp.c
3242
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(queue), val);
sys/dev/fdt/if_mvpp.c
3297
uint32_t val;
sys/dev/fdt/if_mvpp.c
3301
val = mvpp2_xlg_read(port, MV_XLG_PORT_MAC_CTRL0_REG);
sys/dev/fdt/if_mvpp.c
3302
val |= MV_XLG_MAC_CTRL0_PORTEN;
sys/dev/fdt/if_mvpp.c
3303
val &= ~MV_XLG_MAC_CTRL0_MIBCNTDIS;
sys/dev/fdt/if_mvpp.c
3304
mvpp2_xlg_write(port, MV_XLG_PORT_MAC_CTRL0_REG, val);
sys/dev/fdt/if_mvpp.c
3306
val = mvpp2_gmac_read(port, MVPP2_GMAC_CTRL_0_REG);
sys/dev/fdt/if_mvpp.c
3307
val |= MVPP2_GMAC_PORT_EN_MASK;
sys/dev/fdt/if_mvpp.c
3308
val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
sys/dev/fdt/if_mvpp.c
3309
mvpp2_gmac_write(port, MVPP2_GMAC_CTRL_0_REG, val);
sys/dev/fdt/if_mvpp.c
3316
uint32_t val;
sys/dev/fdt/if_mvpp.c
3320
val = mvpp2_xlg_read(port, MV_XLG_PORT_MAC_CTRL0_REG);
sys/dev/fdt/if_mvpp.c
3321
val &= ~MV_XLG_MAC_CTRL0_PORTEN;
sys/dev/fdt/if_mvpp.c
3322
mvpp2_xlg_write(port, MV_XLG_PORT_MAC_CTRL0_REG, val);
sys/dev/fdt/if_mvpp.c
3325
val = mvpp2_gmac_read(port, MVPP2_GMAC_CTRL_0_REG);
sys/dev/fdt/if_mvpp.c
3326
val &= ~MVPP2_GMAC_PORT_EN_MASK;
sys/dev/fdt/if_mvpp.c
3327
mvpp2_gmac_write(port, MVPP2_GMAC_CTRL_0_REG, val);
sys/dev/fdt/if_mvpp.c
3333
uint32_t val = mvpp2_read(port->sc, MVPP2_RXQ_STATUS_REG(rxq_id));
sys/dev/fdt/if_mvpp.c
3335
return val & MVPP2_RXQ_OCCUPIED_MASK;
sys/dev/fdt/if_mvpp.c
3342
uint32_t val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
sys/dev/fdt/if_mvpp.c
3343
mvpp2_write(port->sc, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
sys/dev/fdt/if_mvpp.c
3349
uint32_t val;
sys/dev/fdt/if_mvpp.c
3352
val = mvpp2_read(port->sc, MVPP2_RXQ_CONFIG_REG(prxq));
sys/dev/fdt/if_mvpp.c
3353
val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
sys/dev/fdt/if_mvpp.c
3354
val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
sys/dev/fdt/if_mvpp.c
3356
mvpp2_write(port->sc, MVPP2_RXQ_CONFIG_REG(prxq), val);
sys/dev/fdt/if_mvpp.c
3362
uint32_t val, size, mtu;
sys/dev/fdt/if_mvpp.c
3377
val = mvpp2_read(port->sc, MVPP2_TXP_SCHED_MTU_REG);
sys/dev/fdt/if_mvpp.c
3378
val &= ~MVPP2_TXP_MTU_MAX;
sys/dev/fdt/if_mvpp.c
3379
val |= mtu;
sys/dev/fdt/if_mvpp.c
3380
mvpp2_write(port->sc, MVPP2_TXP_SCHED_MTU_REG, val);
sys/dev/fdt/if_mvpp.c
3383
val = mvpp2_read(port->sc, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
sys/dev/fdt/if_mvpp.c
3384
size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
sys/dev/fdt/if_mvpp.c
3387
val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
sys/dev/fdt/if_mvpp.c
3388
val |= size;
sys/dev/fdt/if_mvpp.c
3389
mvpp2_write(port->sc, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
sys/dev/fdt/if_mvpp.c
3393
val = mvpp2_read(port->sc, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
sys/dev/fdt/if_mvpp.c
3394
size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
sys/dev/fdt/if_mvpp.c
3398
val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
sys/dev/fdt/if_mvpp.c
3399
val |= size;
sys/dev/fdt/if_mvpp.c
3400
mvpp2_write(port->sc, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), val);
sys/dev/fdt/if_mvpp.c
3435
uint32_t val;
sys/dev/fdt/if_mvpp.c
3437
val = (port->sc->sc_tclk / (1000 * 1000)) * usec;
sys/dev/fdt/if_mvpp.c
3438
mvpp2_write(port->sc, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
sys/dev/fdt/if_mvpp.c
3446
uint32_t val;
sys/dev/fdt/if_mvpp.c
3448
val = (port->sc->sc_tclk / (1000 * 1000)) * usec;
sys/dev/fdt/if_mvpp.c
3449
mvpp2_write(port->sc, MVPP2_ISR_TX_THRESHOLD_REG(port->sc_id), val);
sys/dev/fdt/if_mvpp.c
3576
mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, uint32_t bit, uint32_t val)
sys/dev/fdt/if_mvpp.c
3578
pe->sram.byte[bit / 8] |= (val << (bit % 8));
sys/dev/fdt/if_mvpp.c
3582
mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, uint32_t bit, uint32_t val)
sys/dev/fdt/if_mvpp.c
3584
pe->sram.byte[bit / 8] &= ~(val << (bit % 8));
sys/dev/fdt/if_mvpp.c
4572
uint32_t val;
sys/dev/fdt/if_mvpp.c
4574
val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
sys/dev/fdt/if_mvpp.c
4575
mvpp2_write(sc, MVPP2_CLS_LKP_INDEX_REG, val);
sys/dev/fdt/if_mvpp.c
4606
uint32_t val;
sys/dev/fdt/if_mvpp.c
4609
val = mvpp2_read(port->sc, MVPP2_CLS_PORT_WAY_REG);
sys/dev/fdt/if_mvpp.c
4610
val &= ~MVPP2_CLS_PORT_WAY_MASK(port->sc_id);
sys/dev/fdt/if_mvpp.c
4611
mvpp2_write(port->sc, MVPP2_CLS_PORT_WAY_REG, val);
sys/dev/fdt/if_mvpp.c
4635
uint32_t val;
sys/dev/fdt/if_mvpp.c
4641
val = mvpp2_read(port->sc, MVPP2_CLS_SWFWD_PCTRL_REG);
sys/dev/fdt/if_mvpp.c
4642
val &= ~MVPP2_CLS_SWFWD_PCTRL_MASK(port->sc_id);
sys/dev/fdt/if_mvpp.c
4643
mvpp2_write(port->sc, MVPP2_CLS_SWFWD_PCTRL_REG, val);
sys/dev/fdt/if_mvppreg.h
102
#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
sys/dev/fdt/if_mvppreg.h
105
#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
sys/dev/fdt/if_mvppreg.h
167
#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
sys/dev/fdt/if_mvppreg.h
268
#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
sys/dev/fdt/if_mvppreg.h
272
#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
sys/dev/fdt/if_mvppreg.h
99
#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
sys/dev/fdt/imxanatop.c
93
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxanatop.c
94
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxccm.c
178
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxccm.c
179
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxehci.c
220
uint32_t val = EOREAD4(&sc->sc, EHCI_USBCMD);
sys/dev/fdt/imxehci.c
221
val &= ~EHCI_CMD_RS;
sys/dev/fdt/imxehci.c
222
EOWRITE4(&sc->sc, EHCI_USBCMD, val);
sys/dev/fdt/imxehci.c
227
val = EOREAD4(&sc->sc, EHCI_USBCMD);
sys/dev/fdt/imxehci.c
228
val |= EHCI_CMD_HCRESET;
sys/dev/fdt/imxehci.c
229
EOWRITE4(&sc->sc, EHCI_USBCMD, val);
sys/dev/fdt/imxesdhc.c
222
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxesdhc.c
223
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxgpio.c
154
uint32_t val;
sys/dev/fdt/imxgpio.c
159
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR);
sys/dev/fdt/imxgpio.c
161
val |= 1 << pin;
sys/dev/fdt/imxgpio.c
163
val &= ~(1 << pin);
sys/dev/fdt/imxgpio.c
164
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR, val);
sys/dev/fdt/imxgpio.c
174
int val;
sys/dev/fdt/imxgpio.c
178
val = (reg >> pin) & 1;
sys/dev/fdt/imxgpio.c
180
val = !val;
sys/dev/fdt/imxgpio.c
181
return val;
sys/dev/fdt/imxgpio.c
185
imxgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/imxgpio.c
194
val = !val;
sys/dev/fdt/imxgpio.c
195
if (val)
sys/dev/fdt/imxgpio.c
240
int s, val, reg, shift;
sys/dev/fdt/imxgpio.c
280
val = 2;
sys/dev/fdt/imxgpio.c
283
val = 3;
sys/dev/fdt/imxgpio.c
286
val = 1;
sys/dev/fdt/imxgpio.c
289
val = 0;
sys/dev/fdt/imxgpio.c
306
bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) | val << shift);
sys/dev/fdt/imxiomuxc.c
130
uint32_t val;
sys/dev/fdt/imxiomuxc.c
153
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/imxiomuxc.c
155
val &= ~clr;
sys/dev/fdt/imxiomuxc.c
156
val |= set;
sys/dev/fdt/imxiomuxc.c
158
input_reg, val);
sys/dev/fdt/imxpwm.c
55
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxpwm.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxrtc.c
41
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxrtc.c
42
regmap_write_4((sc)->sc_rm, (reg), (val))
sys/dev/fdt/imxspi.c
123
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxspi.c
124
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxsrc.c
94
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxsrc.c
95
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxtmu.c
56
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxtmu.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mtxhci.c
185
uint32_t mask, val;
sys/dev/fdt/mtxhci.c
189
val = HREAD4(sc, MTXHCI_CAPS);
sys/dev/fdt/mtxhci.c
190
sc->sc_ports_usb3 = MIN(MTXHCI_MAX_PORTS, CAP_USB3_PORTS(val));
sys/dev/fdt/mtxhci.c
191
sc->sc_ports_usb2 = MIN(MTXHCI_MAX_PORTS, CAP_USB2_PORTS(val));
sys/dev/fdt/mtxhci.c
200
val = HREAD4(sc, MTXHCI_RESET);
sys/dev/fdt/mtxhci.c
201
val |= RESET_ASSERT;
sys/dev/fdt/mtxhci.c
202
HWRITE4(sc, MTXHCI_RESET, val);
sys/dev/fdt/mtxhci.c
204
val &= ~RESET_ASSERT;
sys/dev/fdt/mtxhci.c
205
HWRITE4(sc, MTXHCI_RESET, val);
sys/dev/fdt/mtxhci.c
209
val = HREAD4(sc, MTXHCI_CFG_DEV);
sys/dev/fdt/mtxhci.c
210
val |= CFG_PWRDN;
sys/dev/fdt/mtxhci.c
211
HWRITE4(sc, MTXHCI_CFG_DEV, val);
sys/dev/fdt/mtxhci.c
214
val = HREAD4(sc, MTXHCI_CFG_HOST);
sys/dev/fdt/mtxhci.c
215
val &= ~CFG_PWRDN;
sys/dev/fdt/mtxhci.c
216
HWRITE4(sc, MTXHCI_CFG_HOST, val);
sys/dev/fdt/mtxhci.c
223
val = HREAD4(sc, MTXHCI_CFG_PCIE);
sys/dev/fdt/mtxhci.c
224
val |= CFG_PWRDN;
sys/dev/fdt/mtxhci.c
225
HWRITE4(sc, MTXHCI_CFG_PCIE, val);
sys/dev/fdt/mtxhci.c
230
val = HREAD4(sc, MTXHCI_USB3_PORT(i));
sys/dev/fdt/mtxhci.c
231
val &= ~(CFG_PORT_DISABLE | CFG_PORT_PWRDN);
sys/dev/fdt/mtxhci.c
232
val |= CFG_PORT_HOST;
sys/dev/fdt/mtxhci.c
233
HWRITE4(sc, MTXHCI_USB3_PORT(i), val);
sys/dev/fdt/mtxhci.c
236
val = HREAD4(sc, MTXHCI_USB2_PORT(i));
sys/dev/fdt/mtxhci.c
237
val &= ~(CFG_PORT_DISABLE | CFG_PORT_PWRDN);
sys/dev/fdt/mtxhci.c
238
val |= CFG_PORT_HOST;
sys/dev/fdt/mtxhci.c
239
HWRITE4(sc, MTXHCI_USB2_PORT(i), val);
sys/dev/fdt/mtxhci.c
243
val = HREAD4(sc, MTXHCI_STA);
sys/dev/fdt/mtxhci.c
244
if ((val & mask) == mask)
sys/dev/fdt/mtxhci.c
64
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mtxhci.c
65
bus_space_write_4((sc)->sc.iot, (sc)->sc_port_ioh, (reg), (val))
sys/dev/fdt/mvclock.c
33
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvclock.c
34
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvdog.c
38
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvdog.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvgpio.c
122
int val;
sys/dev/fdt/mvgpio.c
130
val = (reg >> pin) & 1;
sys/dev/fdt/mvgpio.c
132
val = !val;
sys/dev/fdt/mvgpio.c
133
return val;
sys/dev/fdt/mvgpio.c
137
mvgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/mvgpio.c
147
val = !val;
sys/dev/fdt/mvgpio.c
148
if (val)
sys/dev/fdt/mvgpio.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvgpio.c
40
regmap_write_4((sc)->sc_rm, (sc)->sc_offset + (reg), (val))
sys/dev/fdt/mvicu.c
61
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvicu.c
62
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mviic.c
281
mviic_write_byte(void *v, uint8_t val, int flags)
sys/dev/fdt/mviic.c
287
HWRITE4(sc, IDBR, val);
sys/dev/fdt/mviic.c
86
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mviic.c
87
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvkpcie.c
129
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvkpcie.c
130
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvmdio.c
123
uint32_t smi, val;
sys/dev/fdt/mvmdio.c
152
val = smi & MVNETA_SMI_DATA_MASK;
sys/dev/fdt/mvmdio.c
154
return val;
sys/dev/fdt/mvmdio.c
158
mvmdio_smi_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/fdt/mvmdio.c
178
MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK);
sys/dev/fdt/mvmdio.c
52
#define MVNETA_WRITE(sc, reg, val) \
sys/dev/fdt/mvmdio.c
53
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvpinctrl.c
301
int val;
sys/dev/fdt/mvpinctrl.c
308
val = (reg >> pin) & 1;
sys/dev/fdt/mvpinctrl.c
310
val = !val;
sys/dev/fdt/mvpinctrl.c
311
return val;
sys/dev/fdt/mvpinctrl.c
315
mvpinctrl_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/mvpinctrl.c
325
val = !val;
sys/dev/fdt/mvpinctrl.c
326
if (val)
sys/dev/fdt/mvpinctrl.c
42
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvpinctrl.c
43
regmap_write_4((sc)->sc_rm, (reg), (val))
sys/dev/fdt/mvpinctrl.c
87
#define MPP(id, func, val) { STR(mpp ## id), func, val, id }
sys/dev/fdt/mvrng.c
50
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvrng.c
51
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvrtc.c
46
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvrtc.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvspi.c
83
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvspi.c
84
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvsw.c
171
mvsw_write(struct mvsw_softc *sc, int reg, int val)
sys/dev/fdt/mvsw.c
174
md->md_writereg(md->md_cookie, sc->sc_reg, reg, val);
sys/dev/fdt/mvsw.c
209
mvsw_smi_write(struct mvsw_softc *sc, int phy, int reg, int val)
sys/dev/fdt/mvsw.c
214
mvsw_write(sc, MVSW_SMI_DATA, val);
sys/dev/fdt/mvsw.c
255
mvsw_phy_write(struct mvsw_softc *sc, int phy, int reg, int val)
sys/dev/fdt/mvsw.c
260
mvsw_smi_write(sc, MVSW_G2, MVSW_G2_SMI_PHY_DATA, val);
sys/dev/fdt/mvsw.c
291
mvsw_serdes_write(struct mvsw_softc *sc, int port, int dev, int addr, int val)
sys/dev/fdt/mvsw.c
304
mvsw_smi_write(sc, MVSW_G2, MVSW_G2_SMI_PHY_DATA, val);
sys/dev/fdt/mvsw.c
313
uint16_t val;
sys/dev/fdt/mvsw.c
321
val = mvsw_smi_read(sc, MVSW_PORT(port), MVSW_PORT_CTRL);
sys/dev/fdt/mvsw.c
322
val &= ~MVSW_PORT_CTRL_STATE_MASK;
sys/dev/fdt/mvsw.c
323
val |= MVSW_PORT_CTRL_STATE_FORWARD;
sys/dev/fdt/mvsw.c
324
mvsw_smi_write(sc, MVSW_PORT(port), MVSW_PORT_CTRL, val);
sys/dev/fdt/mvsw.c
330
uint16_t val;
sys/dev/fdt/mvsw.c
338
val = mvsw_phy_read(sc, phy, MII_BMCR);
sys/dev/fdt/mvsw.c
339
val &= ~BMCR_PDOWN;
sys/dev/fdt/mvsw.c
340
mvsw_phy_write(sc, phy, MII_BMCR, val);
sys/dev/fdt/mvsw.c
346
uint16_t val;
sys/dev/fdt/mvsw.c
354
val = mvsw_serdes_read(sc, MVSW_SERDES(port),
sys/dev/fdt/mvsw.c
356
val &= ~BMCR_PDOWN;
sys/dev/fdt/mvsw.c
357
val |= BMCR_AUTOEN;
sys/dev/fdt/mvsw.c
359
MDIO_MMD_PHYXS, MVSW_SERDES_BMCR, val);
sys/dev/fdt/mvtemp.c
201
mvtemp_write(struct mvtemp_softc *sc, int reg, uint32_t val)
sys/dev/fdt/mvtemp.c
204
regmap_write_4(sc->sc_rm, sc->sc_offs[reg], val);
sys/dev/fdt/mvtemp.c
206
bus_space_write_4(sc->sc_iot, sc->sc_stat_ioh, sc->sc_offs[reg], val);
sys/dev/fdt/mvtemp.c
208
bus_space_write_4(sc->sc_iot, sc->sc_ctrl_ioh, sc->sc_offs[reg], val);
sys/dev/fdt/mvuart.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvuart.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/pciecam.c
57
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/pciecam.c
58
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/pinctrl.c
109
pinctrl_set2(int node, char *setting, uint32_t val)
sys/dev/fdt/pinctrl.c
115
return val;
sys/dev/fdt/pinctrl.c
117
val &= ~values[1];
sys/dev/fdt/pinctrl.c
118
val |= (values[0] & values[1]);
sys/dev/fdt/pinctrl.c
119
return val;
sys/dev/fdt/pinctrl.c
123
pinctrl_set4(int node, char *setting, uint32_t val)
sys/dev/fdt/pinctrl.c
129
return val;
sys/dev/fdt/pinctrl.c
131
val &= ~values[3];
sys/dev/fdt/pinctrl.c
132
val |= (values[0] & values[3]);
sys/dev/fdt/pinctrl.c
133
return val;
sys/dev/fdt/pinctrl.c
157
uint32_t val = 0;
sys/dev/fdt/pinctrl.c
163
val = HREAD2(sc, reg);
sys/dev/fdt/pinctrl.c
165
val = HREAD4(sc, reg);
sys/dev/fdt/pinctrl.c
167
val &= ~sc->sc_func_mask;
sys/dev/fdt/pinctrl.c
168
val |= (func & sc->sc_func_mask);
sys/dev/fdt/pinctrl.c
170
val = pinctrl_set2(node, "pinctrl-single,drive-strength", val);
sys/dev/fdt/pinctrl.c
171
val = pinctrl_set4(node, "pinctrl-single,bias-pulldown", val);
sys/dev/fdt/pinctrl.c
172
val = pinctrl_set4(node, "pinctrl-single,bias-pullup", val);
sys/dev/fdt/pinctrl.c
175
HWRITE2(sc, reg, val);
sys/dev/fdt/pinctrl.c
177
HWRITE4(sc, reg, val);
sys/dev/fdt/pinctrl.c
34
#define HWRITE2(sc, reg, val) \
sys/dev/fdt/pinctrl.c
35
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/pinctrl.c
38
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/pinctrl.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/plgpio.c
125
int val;
sys/dev/fdt/plgpio.c
131
val = !!reg;
sys/dev/fdt/plgpio.c
133
val = !val;
sys/dev/fdt/plgpio.c
134
return val;
sys/dev/fdt/plgpio.c
138
plgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/plgpio.c
148
val = !val;
sys/dev/fdt/plgpio.c
149
if (val)
sys/dev/fdt/plgpio.c
36
#define HWRITE1(sc, reg, val) \
sys/dev/fdt/plgpio.c
37
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcaoss.c
55
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcaoss.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qccpucp.c
134
uint64_t val;
sys/dev/fdt/qccpucp.c
147
val = RXREAD8(sc, CPUCP_REG_RX_EN);
sys/dev/fdt/qccpucp.c
148
val |= (1 << i);
sys/dev/fdt/qccpucp.c
149
RXWRITE8(sc, CPUCP_REG_RX_EN, val);
sys/dev/fdt/qccpucp.c
42
#define RXWRITE8(sc, reg, val) \
sys/dev/fdt/qccpucp.c
43
bus_space_write_8((sc)->sc_iot, (sc)->sc_rx_ioh, (reg), (val))
sys/dev/fdt/qccpucp.c
45
#define TXWRITE4(sc, reg, val) \
sys/dev/fdt/qccpucp.c
46
bus_space_write_4((sc)->sc_iot, (sc)->sc_tx_ioh, (reg), (val))
sys/dev/fdt/qcdpc.c
319
uint32_t val, stat;
sys/dev/fdt/qcdpc.c
339
val = buf[i] << DP_AUX_DATA_SHIFT;
sys/dev/fdt/qcdpc.c
340
val |= DP_AUX_DATA_WRITE;
sys/dev/fdt/qcdpc.c
342
val |= DP_AUX_DATA_INDEX_WRITE;
sys/dev/fdt/qcdpc.c
344
DP_AUX_DATA, val);
sys/dev/fdt/qcdpc.c
385
uint32_t val;
sys/dev/fdt/qcdpc.c
390
val = DP_AUX_DATA_INDEX_WRITE | DP_AUX_DATA_READ;
sys/dev/fdt/qcdpc.c
391
bus_space_write_4(sc->sc_iot, sc->sc_aux_ioh, DP_AUX_DATA, val);
sys/dev/fdt/qcdpc.c
397
val = bus_space_read_4(sc->sc_iot, sc->sc_aux_ioh,
sys/dev/fdt/qcdpc.c
399
*p++ = val >> DP_AUX_DATA_SHIFT;
sys/dev/fdt/qcdpc.c
400
j = (val & DP_AUX_DATA_INDEX_MASK) >> DP_AUX_DATA_INDEX_SHIFT;
sys/dev/fdt/qcgpio_fdt.c
222
int val;
sys/dev/fdt/qcgpio_fdt.c
228
val = !!(reg & TLMM_GPIO_IN_OUT_GPIO_IN);
sys/dev/fdt/qcgpio_fdt.c
230
val = !val;
sys/dev/fdt/qcgpio_fdt.c
231
return val;
sys/dev/fdt/qcgpio_fdt.c
235
qcgpio_fdt_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/qcgpio_fdt.c
245
val = !val;
sys/dev/fdt/qcgpio_fdt.c
247
if (val) {
sys/dev/fdt/qcgpio_fdt.c
54
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcgpio_fdt.c
55
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qciic_fdt.c
50
#define GENI_RX_FIFO_STATUS_WC(val) ((val) & 0xffffff)
sys/dev/fdt/qciic_fdt.c
54
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qciic_fdt.c
55
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcipcc.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcipcc.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcmtx.c
36
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcmtx.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcpas.c
51
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcpas.c
52
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcpdc.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcpdc.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcpmicgpio.c
175
int val;
sys/dev/fdt/qcpmicgpio.c
181
val = GPIO_PIN_MODE_DIR_DIGITAL_OUT;
sys/dev/fdt/qcpmicgpio.c
183
val = GPIO_PIN_MODE_DIR_DIGITAL_IN;
sys/dev/fdt/qcpmicgpio.c
186
qcpmicgpio_write(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_MODE, val);
sys/dev/fdt/qcpmicgpio.c
190
reg |= val << GPIO_PIN_MODE_DIR_SHIFT;
sys/dev/fdt/qcpmicgpio.c
202
int val = 0;
sys/dev/fdt/qcpmicgpio.c
219
val = !!(reg & GPIO_PIN_STATUS_ON);
sys/dev/fdt/qcpmicgpio.c
226
val = !!(reg & GPIO_PIN_LVMV_DOUT_CTL_INVERT);
sys/dev/fdt/qcpmicgpio.c
230
val = !!(reg & GPIO_PIN_MODE_VALUE);
sys/dev/fdt/qcpmicgpio.c
235
val = !val;
sys/dev/fdt/qcpmicgpio.c
236
return val;
sys/dev/fdt/qcpmicgpio.c
240
qcpmicgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/qcpmicgpio.c
251
val = !val;
sys/dev/fdt/qcpmicgpio.c
257
if (val)
sys/dev/fdt/qcpmicgpio.c
264
if (val)
sys/dev/fdt/qcpmicgpio.c
273
uint8_t val = 0;
sys/dev/fdt/qcpmicgpio.c
277
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcpmicgpio.c
281
return val;
sys/dev/fdt/qcpmicgpio.c
285
qcpmicgpio_write(struct qcpmicgpio_softc *sc, uint16_t reg, uint8_t val)
sys/dev/fdt/qcpmicgpio.c
290
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcpwm.c
332
uint8_t val = 0;
sys/dev/fdt/qcpwm.c
336
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcpwm.c
340
return val;
sys/dev/fdt/qcpwm.c
344
qcpwm_write(struct qcpwm_softc *sc, uint16_t reg, uint8_t val)
sys/dev/fdt/qcpwm.c
349
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcsmptp.c
266
uint32_t changed, val;
sys/dev/fdt/qcsmptp.c
301
val = *e->e_value;
sys/dev/fdt/qcsmptp.c
302
if (val == e->e_last_value)
sys/dev/fdt/qcsmptp.c
304
changed = val ^ e->e_last_value;
sys/dev/fdt/qcsmptp.c
305
e->e_last_value = val;
sys/dev/fdt/qcspmi.c
103
#define HWRITE4(sc, obj, reg, val) \
sys/dev/fdt/qcspmi.c
104
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh[obj], (reg), (val))
sys/dev/fdt/qcspmi.c
200
uint32_t val, ppid, irq_own;
sys/dev/fdt/qcspmi.c
261
val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_VERSION);
sys/dev/fdt/qcspmi.c
262
if (val < SPMI_VERSION_V5_MIN) {
sys/dev/fdt/qcspmi.c
263
printf(": unsupported version 0x%08x\n", val);
sys/dev/fdt/qcspmi.c
267
if (val < SPMI_VERSION_V7_MIN) {
sys/dev/fdt/qcspmi.c
303
val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_ARB_APID_MAP(sc, i));
sys/dev/fdt/qcspmi.c
304
if (!val)
sys/dev/fdt/qcspmi.c
306
ppid = (val >> SPMI_ARB_APID_MAP_PPID_SHIFT) &
sys/dev/fdt/qcspmi.c
308
irq_own = val & SPMI_ARB_APID_MAP_IRQ_OWNER;
sys/dev/fdt/qcspmi.c
309
val = HREAD4(sc, QCSPMI_REG_CNFG, SPMI_OWNERSHIP_TABLE(sc, i));
sys/dev/fdt/qcspmi.c
311
apid->write_ee = SPMI_OWNERSHIP_TABLE_OWNER(val);
sys/dev/fdt/rkclock.c
262
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkclock.c
263
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkcomphy.c
109
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkcomphy.c
110
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkemmcphy.c
64
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkemmcphy.c
65
regmap_write_4((sc)->sc_rm, (sc)->sc_off + (reg), (val))
sys/dev/fdt/rkgpio.c
235
int val;
sys/dev/fdt/rkgpio.c
244
val = (reg >> pin) & 1;
sys/dev/fdt/rkgpio.c
246
val = !val;
sys/dev/fdt/rkgpio.c
247
return val;
sys/dev/fdt/rkgpio.c
251
rkgpio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/rkgpio.c
262
val = !val;
sys/dev/fdt/rkgpio.c
265
if (val)
sys/dev/fdt/rkgpio.c
269
if (val)
sys/dev/fdt/rkgpio.c
73
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkgpio.c
74
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkiic.c
71
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkiic.c
72
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkiis.c
133
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkiis.c
134
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkiis.c
235
uint32_t grf, val;
sys/dev/fdt/rkiis.c
258
val = sc->sc_conf->oe_val << sc->sc_conf->oe_shift;
sys/dev/fdt/rkiis.c
259
val |= (sc->sc_conf->oe_mask << sc->sc_conf->oe_shift) << 16;
sys/dev/fdt/rkiis.c
260
regmap_write_4(rm, sc->sc_conf->oe_reg, val);
sys/dev/fdt/rkiis.c
292
uint32_t sr, val;
sys/dev/fdt/rkiis.c
301
val = HREAD4(sc, I2S_RXFIFOLR);
sys/dev/fdt/rkiis.c
302
fifolr = val & RXFIFOLR_RFL_MASK(0);
sys/dev/fdt/rkiis.c
316
val = HREAD4(sc, I2S_TXFIFOLR);
sys/dev/fdt/rkiis.c
317
fifolr = val & TXFIFOLR_TFL_MASK(0);
sys/dev/fdt/rkiis.c
532
uint32_t val;
sys/dev/fdt/rkiis.c
535
val = HREAD4(sc, I2S_XFER);
sys/dev/fdt/rkiis.c
536
val |= (XFER_TXS | XFER_RXS);
sys/dev/fdt/rkiis.c
537
HWRITE4(sc, I2S_XFER, val);
sys/dev/fdt/rkiis.c
542
val = HREAD4(sc, I2S_INTCR);
sys/dev/fdt/rkiis.c
543
val |= INTCR_TXEIE;
sys/dev/fdt/rkiis.c
544
val &= ~INTCR_TFT_MASK;
sys/dev/fdt/rkiis.c
545
val |= (RK_I2S_FIFO_DEPTH / 2) << INTCR_TFT_SHIFT;
sys/dev/fdt/rkiis.c
546
HWRITE4(sc, I2S_INTCR, val);
sys/dev/fdt/rkiis.c
570
uint32_t val;
sys/dev/fdt/rkiis.c
574
val = HREAD4(sc, I2S_XFER);
sys/dev/fdt/rkiis.c
575
val &= ~(XFER_TXS|XFER_RXS);
sys/dev/fdt/rkiis.c
576
HWRITE4(sc, I2S_XFER, val);
sys/dev/fdt/rkiis.c
579
val = HREAD4(sc, I2S_INTCR);
sys/dev/fdt/rkiis.c
580
val &= ~INTCR_TXEIE;
sys/dev/fdt/rkiis.c
581
HWRITE4(sc, I2S_INTCR, val);
sys/dev/fdt/rkiis.c
583
val = HREAD4(sc, I2S_CLR);
sys/dev/fdt/rkiis.c
584
val |= CLR_TXC;
sys/dev/fdt/rkiis.c
585
HWRITE4(sc, I2S_CLR, val);
sys/dev/fdt/rkiis.c
601
uint32_t val;
sys/dev/fdt/rkiis.c
605
val = HREAD4(sc, I2S_XFER);
sys/dev/fdt/rkiis.c
606
val &= ~(XFER_TXS|XFER_RXS);
sys/dev/fdt/rkiis.c
607
HWRITE4(sc, I2S_XFER, val);
sys/dev/fdt/rkiis.c
610
val = HREAD4(sc, I2S_INTCR);
sys/dev/fdt/rkiis.c
611
val &= ~INTCR_RXFIE;
sys/dev/fdt/rkiis.c
612
HWRITE4(sc, I2S_INTCR, val);
sys/dev/fdt/rkotp.c
111
uint32_t stat, val;
sys/dev/fdt/rkotp.c
139
val = HREAD4(sc, RK3588_OTPC_DOUT0);
sys/dev/fdt/rkotp.c
141
val >>= 8;
sys/dev/fdt/rkotp.c
143
buf[pos++] = val & 0xff;
sys/dev/fdt/rkotp.c
144
val >>= 8;
sys/dev/fdt/rkotp.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkotp.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkpcie.c
93
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkpcie.c
94
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkpinctrl.c
1157
regmap_write_4(rm, route->reg, route->val);
sys/dev/fdt/rkpinctrl.c
122
uint32_t val;
sys/dev/fdt/rkpinctrl.c
123
#define ROUTE_VAL(bit, val) ((0x3 << (bit)) << 16 | ((val) << (bit)))
sys/dev/fdt/rkpmic.c
488
uint8_t val;
sys/dev/fdt/rkpmic.c
560
val = rkpmic_reg_read(sc, RK809_PMIC_GPIO_INT_CONFIG);
sys/dev/fdt/rkpmic.c
562
val & ~RK809_PMIC_GPIO_INT_CONFIG_INT_POL);
sys/dev/fdt/rkpmic.c
588
uint8_t val;
sys/dev/fdt/rkpmic.c
593
val = rkpmic_reg_read(sc, RK809_PMIC_SYS_CFG3);
sys/dev/fdt/rkpmic.c
594
val &= ~RK809_PMIC_SYS_CFG3_SLP_FUN_MASK;
sys/dev/fdt/rkpmic.c
595
val |= RK809_PMIC_SYS_CFG3_SLP_FUN_SLEEP;
sys/dev/fdt/rkpmic.c
596
rkpmic_reg_write(sc, RK809_PMIC_SYS_CFG3, val);
sys/dev/fdt/rkpmic.c
601
val = rkpmic_reg_read(sc, RK809_PMIC_SYS_CFG3);
sys/dev/fdt/rkpmic.c
602
val &= ~RK809_PMIC_SYS_CFG3_SLP_FUN_MASK;
sys/dev/fdt/rkpmic.c
603
val |= RK809_PMIC_SYS_CFG3_SLP_FUN_NONE;
sys/dev/fdt/rkpmic.c
604
rkpmic_reg_write(sc, RK809_PMIC_SYS_CFG3, val);
sys/dev/fdt/rkpmic.c
652
uint8_t val;
sys/dev/fdt/rkpmic.c
680
val = rkpmic_reg_read(sc, sc->sc_regdata[i].sreg);
sys/dev/fdt/rkpmic.c
682
val |= sc->sc_regdata[i].smask;
sys/dev/fdt/rkpmic.c
684
val &= ~sc->sc_regdata[i].smask;
sys/dev/fdt/rkpmic.c
685
rkpmic_reg_write(sc, sc->sc_regdata[i].sreg, val);
sys/dev/fdt/rkpmic.c
842
uint8_t val;
sys/dev/fdt/rkpmic.c
844
if (sc->sc_read(sc, cmd, &val, sizeof(val))) {
sys/dev/fdt/rkpmic.c
847
val = 0xff;
sys/dev/fdt/rkpmic.c
850
return val;
sys/dev/fdt/rkpmic.c
854
rkpmic_reg_write(struct rkpmic_softc *sc, int reg, uint8_t val)
sys/dev/fdt/rkpmic.c
858
if (sc->sc_write(sc, cmd, &val, sizeof(val))) {
sys/dev/fdt/rkpwm.c
46
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkpwm.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkrng.c
84
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkrng.c
85
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkspi.c
120
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkspi.c
121
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rktcphy.c
106
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rktcphy.c
107
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rktemp.c
82
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rktemp.c
83
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkusbdpphy.c
212
uint16_t reg, val;
sys/dev/fdt/rkusbdpphy.c
300
rkusbdpphy_init_regs[i].val);
sys/dev/fdt/rkusbdpphy.c
309
rkusbdpphy_24m_refclk_init_regs[i].val);
sys/dev/fdt/rkusbdpphy.c
316
rkusbdpphy_26m_refclk_init_regs[i].val);
sys/dev/fdt/rkusbdpphy.c
53
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkusbdpphy.c
54
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkvop.c
150
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkvop.c
151
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkvop.c
297
uint32_t val;
sys/dev/fdt/rkvop.c
299
val = WIN0_ACT_WIDTH(act_width - 1) |
sys/dev/fdt/rkvop.c
301
HWRITE4(sc, VOP_WIN0_ACT_INFO, val);
sys/dev/fdt/rkvop.c
303
val = WIN0_DSP_WIDTH(drm_rect_width(dst) - 1) |
sys/dev/fdt/rkvop.c
305
HWRITE4(sc, VOP_WIN0_DSP_INFO, val);
sys/dev/fdt/rkvop.c
307
val = WIN0_DSP_XST(dst->x1 + htotal - hsync_start) |
sys/dev/fdt/rkvop.c
309
HWRITE4(sc, VOP_WIN0_DSP_ST, val);
sys/dev/fdt/rkvop.c
322
val = WIN0_LB_MODE(lb_mode) |
sys/dev/fdt/rkvop.c
325
HWRITE4(sc, VOP_WIN0_CTRL, val);
sys/dev/fdt/rkvop.c
327
val = WIN0_VIR_STRIDE(fb->pitches[0] / 4);
sys/dev/fdt/rkvop.c
328
HWRITE4(sc, VOP_WIN0_VIR, val);
sys/dev/fdt/rkvop.c
357
uint32_t val;
sys/dev/fdt/rkvop.c
359
val = HREAD4(sc, VOP_SYS_CTRL);
sys/dev/fdt/rkvop.c
363
val &= ~VOP_STANDBY_EN;
sys/dev/fdt/rkvop.c
368
val |= VOP_STANDBY_EN;
sys/dev/fdt/rkvop.c
372
HWRITE4(sc, VOP_SYS_CTRL, val);
sys/dev/fdt/rkvop.c
404
uint32_t val;
sys/dev/fdt/rkvop.c
447
val = HREAD4(sc, VOP_SYS_CTRL);
sys/dev/fdt/rkvop.c
448
val &= ~VOP_STANDBY_EN;
sys/dev/fdt/rkvop.c
449
val &= ~(MIPI_OUT_EN|EDP_OUT_EN|HDMI_OUT_EN|RGB_OUT_EN);
sys/dev/fdt/rkvop.c
453
val |= HDMI_OUT_EN;
sys/dev/fdt/rkvop.c
456
val |= EDP_OUT_EN;
sys/dev/fdt/rkvop.c
459
HWRITE4(sc, VOP_SYS_CTRL, val);
sys/dev/fdt/rkvop.c
461
val = HREAD4(sc, VOP_DSP_CTRL0);
sys/dev/fdt/rkvop.c
462
val &= ~DSP_OUT_MODE(DSP_OUT_MODE_MASK);
sys/dev/fdt/rkvop.c
463
val |= DSP_OUT_MODE(sc->sc_conf->out_mode);
sys/dev/fdt/rkvop.c
464
HWRITE4(sc, VOP_DSP_CTRL0, val);
sys/dev/fdt/rkvop.c
466
val = DSP_HACT_ST_POST(hsync_len + hback_porch) |
sys/dev/fdt/rkvop.c
468
HWRITE4(sc, VOP_POST_DSP_HACT_INFO, val);
sys/dev/fdt/rkvop.c
470
val = DSP_HACT_ST(hsync_len + hback_porch) |
sys/dev/fdt/rkvop.c
472
HWRITE4(sc, VOP_DSP_HACT_ST_END, val);
sys/dev/fdt/rkvop.c
474
val = DSP_HTOTAL(hsync_len) |
sys/dev/fdt/rkvop.c
476
HWRITE4(sc, VOP_DSP_HTOTAL_HS_END, val);
sys/dev/fdt/rkvop.c
478
val = DSP_VACT_ST_POST(vsync_len + vback_porch) |
sys/dev/fdt/rkvop.c
480
HWRITE4(sc, VOP_POST_DSP_VACT_INFO, val);
sys/dev/fdt/rkvop.c
482
val = DSP_VACT_ST(vsync_len + vback_porch) |
sys/dev/fdt/rkvop.c
484
HWRITE4(sc, VOP_DSP_VACT_ST_END, val);
sys/dev/fdt/rkvop.c
486
val = DSP_VTOTAL(vsync_len) |
sys/dev/fdt/rkvop.c
488
HWRITE4(sc, VOP_DSP_VTOTAL_VS_END, val);
sys/dev/fdt/rkvop.c
571
uint32_t val;
sys/dev/fdt/rkvop.c
573
val = HREAD4(sc, VOP_SYS_CTRL);
sys/dev/fdt/rkvop.c
574
val |= RK3399_VOP_SYS_CTRL_ENABLE;
sys/dev/fdt/rkvop.c
575
HWRITE4(sc, VOP_SYS_CTRL, val);
sys/dev/fdt/rkvop.c
581
uint32_t mask, val;
sys/dev/fdt/rkvop.c
605
val = HREAD4(sc, VOP_DSP_CTRL1);
sys/dev/fdt/rkvop.c
606
val &= ~mask;
sys/dev/fdt/rkvop.c
607
val |= pol;
sys/dev/fdt/rkvop.c
608
HWRITE4(sc, VOP_DSP_CTRL1, val);
sys/dev/fdt/sncodec.c
387
uint8_t val;
sys/dev/fdt/sncodec.c
392
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/sncodec.c
398
val = 0xff;
sys/dev/fdt/sncodec.c
401
return val;
sys/dev/fdt/sncodec.c
405
sncodec_write(struct sncodec_softc *sc, int reg, uint8_t val)
sys/dev/fdt/sncodec.c
412
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/ssdfb.c
481
uint8_t *bit, val;
sys/dev/fdt/ssdfb.c
504
val = *(ri->ri_bits + off);
sys/dev/fdt/ssdfb.c
505
val &= (1 << ((x1 + j) % 8));
sys/dev/fdt/ssdfb.c
506
*bit |= !!val << k;
sys/dev/fdt/sunxireg.h
20
#define SXIWRITE1(sc, reg, val) \
sys/dev/fdt/sunxireg.h
21
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sunxireg.h
31
#define SXIWRITE4(sc, reg, val) \
sys/dev/fdt/sunxireg.h
32
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sximmc.c
284
#define MMC_WRITE(sc, reg, val) \
sys/dev/fdt/sximmc.c
285
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
sys/dev/fdt/sximmc.c
658
int inverted, val;
sys/dev/fdt/sximmc.c
665
val = gpio_controller_get_pin(sc->sc_gpio);
sys/dev/fdt/sximmc.c
668
return inverted ? !val : val;
sys/dev/fdt/sximmc.c
854
uint32_t val;
sys/dev/fdt/sximmc.c
895
val = MMC_READ(sc, SXIMMC_GCTRL);
sys/dev/fdt/sximmc.c
896
val |= SXIMMC_GCTRL_DMAEN;
sys/dev/fdt/sximmc.c
897
val |= SXIMMC_GCTRL_INTEN;
sys/dev/fdt/sximmc.c
898
MMC_WRITE(sc, SXIMMC_GCTRL, val);
sys/dev/fdt/sximmc.c
899
val |= SXIMMC_GCTRL_DMARESET;
sys/dev/fdt/sximmc.c
900
MMC_WRITE(sc, SXIMMC_GCTRL, val);
sys/dev/fdt/sximmc.c
904
val = MMC_READ(sc, SXIMMC_IDIE);
sys/dev/fdt/sximmc.c
905
val &= ~(SXIMMC_IDST_RECEIVE_INT|SXIMMC_IDST_TRANSMIT_INT);
sys/dev/fdt/sximmc.c
907
val |= SXIMMC_IDST_RECEIVE_INT;
sys/dev/fdt/sximmc.c
909
val |= SXIMMC_IDST_TRANSMIT_INT;
sys/dev/fdt/sximmc.c
910
MMC_WRITE(sc, SXIMMC_IDIE, val);
sys/dev/fdt/sxipio.c
427
int val;
sys/dev/fdt/sxipio.c
434
val = (reg >> pin) & 1;
sys/dev/fdt/sxipio.c
436
val = !val;
sys/dev/fdt/sxipio.c
437
return val;
sys/dev/fdt/sxipio.c
441
sxipio_set_pin(void *cookie, uint32_t *cells, int val)
sys/dev/fdt/sxipio.c
454
val = !val;
sys/dev/fdt/sxipio.c
455
if (val)
sys/dev/fdt/sxipio.c
511
sxipio_pin_write(void *cookie, int pin, int val)
sys/dev/fdt/sxipio.c
520
sxipio_set_pin(gpio->sc, cells, val);
sys/dev/fdt/sxipwm.c
47
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxipwm.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxirintc.c
34
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxirintc.c
35
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxirsb.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxirsb.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxisid.c
129
uint32_t val;
sys/dev/fdt/sxisid.c
148
val = HREAD4(sc, SID_RDKEY);
sys/dev/fdt/sxisid.c
150
buf[pos++] = val & 0xff;
sys/dev/fdt/sxisid.c
151
val >>= 8;
sys/dev/fdt/sxisid.c
41
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxisid.c
42
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxitemp.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxitemp.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxits.c
48
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxits.c
49
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxitwi.c
343
sxitwi_write_4(struct sxitwi_softc *sc, u_int reg, u_int val)
sys/dev/fdt/sxitwi.c
346
bus_space_write_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg], val);
sys/dev/fdt/sxitwi.c
353
u_int val;
sys/dev/fdt/sxitwi.c
355
val = sxitwi_read_4(sc, TWSI_CONTROL);
sys/dev/fdt/sxitwi.c
356
if (val & CONTROL_IFLG) {
sys/dev/fdt/sxitwi.c
357
sxitwi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
sys/dev/fdt/sxitwi.c
480
sxitwi_write_byte(void *v, uint8_t val, int flags)
sys/dev/fdt/sxitwi.c
485
sxitwi_write_4(sc, TWSI_DATA, val);
sys/dev/fdt/sypwr.c
135
uint8_t val;
sys/dev/fdt/sypwr.c
140
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/sypwr.c
147
val = 0xff;
sys/dev/fdt/sypwr.c
150
return val;
sys/dev/fdt/sypwr.c
154
sypwr_write(struct sypwr_softc *sc, int reg, uint8_t val)
sys/dev/fdt/sypwr.c
161
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/tascodec.c
375
uint8_t val;
sys/dev/fdt/tascodec.c
380
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/tascodec.c
386
val = 0xff;
sys/dev/fdt/tascodec.c
389
return val;
sys/dev/fdt/tascodec.c
393
tascodec_write(struct tascodec_softc *sc, int reg, uint8_t val)
sys/dev/fdt/tascodec.c
400
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/fdt/tcpci.c
553
uint8_t val = 0;
sys/dev/fdt/tcpci.c
557
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
563
return val;
sys/dev/fdt/tcpci.c
567
tcpci_write_reg8(struct tcpci_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/tcpci.c
571
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
581
uint16_t val = 0;
sys/dev/fdt/tcpci.c
585
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
591
return val;
sys/dev/fdt/tcpci.c
595
tcpci_write_reg16(struct tcpci_softc *sc, uint8_t reg, uint16_t val)
sys/dev/fdt/tcpci.c
599
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tipd.c
231
tipd_read_4(struct tipd_softc *sc, uint8_t reg, uint32_t *val)
sys/dev/fdt/tipd.c
242
*val = lemtoh32(&buf[1]);
sys/dev/fdt/tipd.c
248
tipd_read_8(struct tipd_softc *sc, uint8_t reg, uint64_t *val)
sys/dev/fdt/tipd.c
259
*val = lemtoh64(&buf[1]);
sys/dev/fdt/tipd.c
265
tipd_write_4(struct tipd_softc *sc, uint8_t reg, uint32_t val)
sys/dev/fdt/tipd.c
271
htolem32(&buf[1], val);
sys/dev/fdt/tipd.c
282
tipd_write_8(struct tipd_softc *sc, uint8_t reg, uint64_t val)
sys/dev/fdt/tipd.c
288
htolem64(&buf[1], val);
sys/dev/fdt/tipd.c
303
uint32_t val;
sys/dev/fdt/tipd.c
313
error = tipd_read_4(sc, TPS_CMD1, &val);
sys/dev/fdt/tipd.c
314
if (error == 0 && val == TPS_CMD("!CMD"))
sys/dev/fdt/tipd.c
335
error = tipd_read_4(sc, TPS_CMD1, &val);
sys/dev/fdt/tipd.c
336
if (error == 0 && val == TPS_CMD("!CMD"))
sys/dev/fdt/tipd.c
340
if (val == 0)
sys/dev/fdt/xhci_fdt.c
525
uint32_t val;
sys/dev/fdt/xhci_fdt.c
553
val = regmap_read_4(pmurm, offset);
sys/dev/fdt/xhci_fdt.c
554
val |= EXYNOS5_USBDRD_POWER_EN;
sys/dev/fdt/xhci_fdt.c
555
regmap_write_4(pmurm, offset, val);
sys/dev/fdt/xhci_fdt.c
559
val = bus_space_read_4(sc->sc.iot, sc->ph_ioh, EXYNOS5_PHYTEST);
sys/dev/fdt/xhci_fdt.c
560
CLR(val, EXYNOS5_PHYTEST_POWERDOWN_SSP);
sys/dev/fdt/xhci_fdt.c
561
CLR(val, EXYNOS5_PHYTEST_POWERDOWN_HSP);
sys/dev/fdt/xhci_fdt.c
562
bus_space_write_4(sc->sc.iot, sc->ph_ioh, EXYNOS5_PHYTEST, val);
sys/dev/fdt/xhci_fdt.c
567
val = bus_space_read_4(sc->sc.iot, sc->ph_ioh, EXYNOS5_PHYCLKRST);
sys/dev/fdt/xhci_fdt.c
568
SET(val, EXYNOS5_PHYCLKRST_SSC_EN);
sys/dev/fdt/xhci_fdt.c
569
SET(val, EXYNOS5_PHYCLKRST_REF_SSP_EN);
sys/dev/fdt/xhci_fdt.c
570
SET(val, EXYNOS5_PHYCLKRST_COMMONONN);
sys/dev/fdt/xhci_fdt.c
571
SET(val, EXYNOS5_PHYCLKRST_PORTRESET);
sys/dev/fdt/xhci_fdt.c
572
bus_space_write_4(sc->sc.iot, sc->ph_ioh, EXYNOS5_PHYCLKRST, val);
sys/dev/fdt/xhci_fdt.c
574
CLR(val, EXYNOS5_PHYCLKRST_PORTRESET);
sys/dev/fdt/xhci_fdt.c
575
bus_space_write_4(sc->sc.iot, sc->ph_ioh, EXYNOS5_PHYCLKRST, val);
sys/dev/i2c/abx80x.c
173
uint8_t val[2];
sys/dev/i2c/abx80x.c
178
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/abx80x.c
187
return val[1];
sys/dev/i2c/abx80x.c
194
uint8_t val[2];
sys/dev/i2c/abx80x.c
197
val[0] = 1;
sys/dev/i2c/abx80x.c
198
val[1] = data;
sys/dev/i2c/abx80x.c
202
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/ds3231.c
136
uint8_t val;
sys/dev/i2c/ds3231.c
141
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/ds3231.c
147
val = 0xff;
sys/dev/i2c/ds3231.c
150
return val;
sys/dev/i2c/ds3231.c
154
dsxrtc_reg_write(struct dsxrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/ds3231.c
161
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/i2c_bitbang.c
130
uint8_t val = 0;
sys/dev/i2c/i2c_bitbang.c
137
val <<= 1;
sys/dev/i2c/i2c_bitbang.c
143
val |= 1;
sys/dev/i2c/i2c_bitbang.c
166
*valp = val;
sys/dev/i2c/i2c_bitbang.c
171
i2c_bitbang_write_byte(void *v, uint8_t val, int flags,
sys/dev/i2c/i2c_bitbang.c
181
bit = (val & mask) ? SDA : 0;
sys/dev/i2c/i2c_exec.c
123
uint8_t val, int flags)
sys/dev/i2c/i2c_exec.c
127
&cmd, sizeof cmd, &val, sizeof val, flags));
sys/dev/i2c/i2c_scan.c
358
u_int8_t reg, val;
sys/dev/i2c/i2c_scan.c
361
val = iicprobe(0x00);
sys/dev/i2c/i2c_scan.c
367
if (val == iicprobe(reg))
sys/dev/i2c/i2c_scan.c
372
val = iicprobe(0x09);
sys/dev/i2c/i2c_scan.c
374
if (iicprobe(reg) != val)
sys/dev/i2c/i2c_scan.c
408
u_int8_t val, val2, max;
sys/dev/i2c/i2c_scan.c
418
val = iicprobe(0);
sys/dev/i2c/i2c_scan.c
419
iicvalcnt[val]++;
sys/dev/i2c/i2c_scan.c
423
if (val == val2)
sys/dev/i2c/i2c_scan.c
427
for (val = max = i = 0; i <= 0xff; i++)
sys/dev/i2c/i2c_scan.c
430
val = i;
sys/dev/i2c/i2c_scan.c
438
if (iicprobe(i) != val)
sys/dev/i2c/iasuskbd.c
249
iasuskbd_do_set_backlight(struct iasuskbd_softc *sc, unsigned int val)
sys/dev/i2c/iasuskbd.c
254
if (val > 3)
sys/dev/i2c/iasuskbd.c
259
sc->sc_cmdbuf[3] = val;
sys/dev/i2c/iatp.c
677
iatp_read_reg(struct iatp_softc *sc, uint16_t reg, size_t len, void *val)
sys/dev/i2c/iatp.c
685
sizeof(cmd), val, len, I2C_F_POLL);
sys/dev/i2c/iatp.c
693
iatp_write_reg(struct iatp_softc *sc, uint16_t reg, size_t len, void *val)
sys/dev/i2c/iatp.c
701
memcpy(&cmd[2], val, len);
sys/dev/i2c/ietp.c
350
uint16_t val;
sys/dev/i2c/ietp.c
374
val = enable ? IETP_CTRL_ABSOLUTE : IETP_CTRL_STANDARD;
sys/dev/i2c/ietp.c
375
if (ietp_iic_write_reg(sc, IETP_CONTROL, val) != 0) {
sys/dev/i2c/ietp.c
391
ietp_iic_read_reg(struct ietp_softc *sc, uint16_t reg, size_t len, void *val)
sys/dev/i2c/ietp.c
399
&cmd, 2, val, len, 0);
sys/dev/i2c/ietp.c
403
ietp_iic_write_reg(struct ietp_softc *sc, uint16_t reg, uint16_t val)
sys/dev/i2c/ietp.c
408
val & 0xff,
sys/dev/i2c/ietp.c
409
val >> 8,
sys/dev/i2c/isl1208.c
134
uint8_t val;
sys/dev/i2c/isl1208.c
139
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/isl1208.c
145
val = 0xff;
sys/dev/i2c/isl1208.c
148
return val;
sys/dev/i2c/isl1208.c
152
islrtc_reg_write(struct islrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/isl1208.c
159
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/lm75.c
243
int val;
sys/dev/i2c/lm75.c
246
error = lmtemp_temp_read(sc, LM75_REG_TEMP, &val);
sys/dev/i2c/lm75.c
256
sc->sc_sensor.value = val * sc->sc_ratio + 273150000;
sys/dev/i2c/lm78_i2c.c
116
lm_i2c_writereg(struct lm_softc *lmsc, int reg, int val)
sys/dev/i2c/lm78_i2c.c
124
data = val;
sys/dev/i2c/mcp794xx.c
139
uint8_t val;
sys/dev/i2c/mcp794xx.c
144
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/mcp794xx.c
150
val = 0xff;
sys/dev/i2c/mcp794xx.c
153
return val;
sys/dev/i2c/mcp794xx.c
157
mcprtc_reg_write(struct mcprtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/mcp794xx.c
164
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL);
sys/dev/i2c/pcf85063.c
171
uint8_t val;
sys/dev/i2c/pcf85063.c
177
NULL, 0, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/pcf85063.c
184
return val;
sys/dev/i2c/pcf85063.c
188
pcyrtc_reg_write(struct pcyrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/pcf85063.c
194
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/pcf8523.c
194
uint8_t val;
sys/dev/i2c/pcf8523.c
200
NULL, 0, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/pcf8523.c
207
return val;
sys/dev/i2c/pcf8523.c
211
pcfrtc_reg_write(struct pcfrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/pcf8523.c
217
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/pcf8563.c
166
uint8_t val;
sys/dev/i2c/pcf8563.c
170
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/pcf8563.c
177
return val;
sys/dev/i2c/pcf8563.c
181
pcxrtc_reg_write(struct pcxrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/pcf8563.c
187
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/rs5c372.c
226
ricohrtc_reg_write(struct ricohrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/rs5c372.c
234
&cmd, sizeof cmd, &val, sizeof val, I2C_F_POLL)) {
sys/dev/i2c/spdmem_i2c.c
115
uint8_t val = 0xff;
sys/dev/i2c/spdmem_i2c.c
119
®, sizeof reg, &val, sizeof val, 0);
sys/dev/i2c/spdmem_i2c.c
122
return val;
sys/dev/ic/aacvar.h
202
#define AAC_SETREG4(sc, reg, val) \
sys/dev/ic/aacvar.h
203
bus_space_write_4((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
sys/dev/ic/aacvar.h
206
#define AAC_SETREG2(sc, reg, val) \
sys/dev/ic/aacvar.h
207
bus_space_write_2((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
sys/dev/ic/aacvar.h
210
#define AAC_SETREG1(sc, reg, val) \
sys/dev/ic/aacvar.h
211
bus_space_write_1((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
sys/dev/ic/ac97.c
1040
u_int16_t val, newval;
sys/dev/ic/ac97.c
1056
ac97_read(as, si->reg, &val);
sys/dev/ic/ac97.c
1058
DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
sys/dev/ic/ac97.c
1125
error = ac97_write(as, si->reg, (val & ~mask) | newval);
sys/dev/ic/ac97.c
1321
u_int16_t val;
sys/dev/ic/ac97.c
1331
ac97_read(as, si->reg, &val);
sys/dev/ic/ac97.c
1333
DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
sys/dev/ic/ac97.c
1339
cp->un.ord = (val >> si->ofs) & mask;
sys/dev/ic/ac97.c
1340
DPRINTFN(4, ("AUDIO_MIXER_ENUM: %x %d %x %d\n", val, si->ofs,
sys/dev/ic/ac97.c
1353
l = r = (val >> si->ofs) & mask;
sys/dev/ic/ac97.c
1356
l = (val >> si->ofs) & mask;
sys/dev/ic/ac97.c
1357
r = (val >> (si->ofs + 8)) & mask;
sys/dev/ic/ac97.c
1359
r = (val >> si->ofs) & mask;
sys/dev/ic/ac97.c
1360
l = (val >> (si->ofs + 8)) & mask;
sys/dev/ic/ac97.c
598
ac97_read(struct ac97_softc *as, u_int8_t reg, u_int16_t *val)
sys/dev/ic/ac97.c
606
*val = as->shadow_reg[reg >> 1];
sys/dev/ic/ac97.c
610
if ((error = as->host_if->read(as->host_if->arg, reg, val)))
sys/dev/ic/ac97.c
611
*val = as->shadow_reg[reg >> 1];
sys/dev/ic/ac97.c
616
ac97_write(struct ac97_softc *as, u_int8_t reg, u_int16_t val)
sys/dev/ic/ac97.c
618
as->shadow_reg[reg >> 1] = val;
sys/dev/ic/ac97.c
619
return (as->host_if->write(as->host_if->arg, reg, val));
sys/dev/ic/ac97.c
769
u_int16_t id1, id2, val;
sys/dev/ic/ac97.c
873
ac97_read(as, AC97_REG_SPDIF_CTRL, &val);
sys/dev/ic/ac97.c
874
val = (val & ~AC97_SPDIF_SPSR_MASK) |
sys/dev/ic/ac97.c
876
ac97_write(as, AC97_REG_SPDIF_CTRL, val);
sys/dev/ic/ac97.c
935
u_int16_t val, extstat;
sys/dev/ic/ac97.c
965
ac97_read(as, AC97_REG_SPDIF_CTRL, &val);
sys/dev/ic/ac97.c
966
val = (val & ~AC97_SPDIF_SPSR_MASK) |
sys/dev/ic/ac97.c
968
ac97_write(as, AC97_REG_SPDIF_CTRL, val);
sys/dev/ic/ac97.h
47
int (*read)(void *arg, u_int8_t reg, u_int16_t *val);
sys/dev/ic/ac97.h
48
int (*write)(void *arg, u_int8_t reg, u_int16_t val);
sys/dev/ic/acx.c
1453
acx_read_eeprom(struct acx_softc *sc, uint32_t offset, uint8_t *val)
sys/dev/ic/acx.c
1474
*val = CSR_READ_1(sc, ACXREG_EEPROM_DATA);
sys/dev/ic/acx.c
1480
acx_read_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t *val)
sys/dev/ic/acx.c
1501
*val = CSR_READ_1(sc, ACXREG_PHY_DATA);
sys/dev/ic/acx.c
1507
acx_write_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t val)
sys/dev/ic/acx.c
1509
CSR_WRITE_4(sc, ACXREG_PHY_DATA, val);
sys/dev/ic/acx.c
1688
uint32_t val;
sys/dev/ic/acx.c
1693
val = CSR_READ_4(sc, ACXREG_FWMEM_DATA);
sys/dev/ic/acx.c
1694
if (betoh32(fw[i]) != val) {
sys/dev/ic/acx.c
1696
ifp->if_xname, fw[i], val);
sys/dev/ic/acx.c
261
uint8_t val;
sys/dev/ic/acx.c
263
error = acx_read_eeprom(sc, i, &val);
sys/dev/ic/acx.c
268
printf("%02x ", val);
sys/dev/ic/acxreg.h
443
#define CMD_WRITE_4(sc, val) \
sys/dev/ic/acxreg.h
445
(sc)->sc_cmd, (val))
sys/dev/ic/acxreg.h
88
#define ACXREG(reg, val) [ACXREG_##reg] = val
sys/dev/ic/acxvar.h
102
#define FW_TXDESC_SETFIELD_1(sc, mb, field, val) \
sys/dev/ic/acxvar.h
104
(mb)->tb_fwdesc_ofs + offsetof(struct acx_fw_txdesc, field), (val))
sys/dev/ic/acxvar.h
105
#define FW_TXDESC_SETFIELD_2(sc, mb, field, val) \
sys/dev/ic/acxvar.h
107
(mb)->tb_fwdesc_ofs + offsetof(struct acx_fw_txdesc, field), (val))
sys/dev/ic/acxvar.h
108
#define FW_TXDESC_SETFIELD_4(sc, mb, field, val) \
sys/dev/ic/acxvar.h
110
(mb)->tb_fwdesc_ofs + offsetof(struct acx_fw_txdesc, field), (val))
sys/dev/ic/acxvar.h
86
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/acxvar.h
88
(sc)->chip_ioreg[(reg)], val)
sys/dev/ic/acxvar.h
89
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/acxvar.h
91
(sc)->chip_ioreg[(reg)], val)
sys/dev/ic/advlib.c
1869
u_int16_t val;
sys/dev/ic/advlib.c
1873
val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
sys/dev/ic/advlib.c
1874
scsiq->d2.ccb_ptr = MAKELONG(val, ASC_GET_CHIP_LRAM_DATA(iot, ioh));
sys/dev/ic/advlib.c
1875
val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
sys/dev/ic/advlib.c
1876
scsiq->d2.target_ix = LO_BYTE(val);
sys/dev/ic/advlib.c
1877
scsiq->d2.flag = HI_BYTE(val);
sys/dev/ic/advlib.c
1878
val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
sys/dev/ic/advlib.c
1879
scsiq->d2.cdb_len = LO_BYTE(val);
sys/dev/ic/advlib.c
1880
scsiq->d2.tag_code = HI_BYTE(val);
sys/dev/ic/advlib.c
1883
val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
sys/dev/ic/advlib.c
1884
scsiq->d3.done_stat = LO_BYTE(val);
sys/dev/ic/advlib.c
1885
scsiq->d3.host_stat = HI_BYTE(val);
sys/dev/ic/advlib.c
1886
val = ASC_GET_CHIP_LRAM_DATA(iot, ioh);
sys/dev/ic/advlib.c
1887
scsiq->d3.scsi_stat = LO_BYTE(val);
sys/dev/ic/advlib.c
1888
scsiq->d3.scsi_msg = HI_BYTE(val);
sys/dev/ic/advlib.c
2581
u_int16_t val;
sys/dev/ic/advlib.c
2586
val = MAKEWORD(scsiq->q1.cntl, scsiq->q1.sg_queue_cnt);
sys/dev/ic/advlib.c
2587
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2588
val = MAKEWORD(scsiq->q1.target_id, scsiq->q1.target_lun);
sys/dev/ic/advlib.c
2589
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2590
val = LO_WORD(scsiq->q1.data_addr);
sys/dev/ic/advlib.c
2591
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2592
val = HI_WORD(scsiq->q1.data_addr);
sys/dev/ic/advlib.c
2593
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2594
val = LO_WORD(scsiq->q1.data_cnt);
sys/dev/ic/advlib.c
2595
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2596
val = HI_WORD(scsiq->q1.data_cnt);
sys/dev/ic/advlib.c
2597
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2598
val = LO_WORD(scsiq->q1.sense_addr);
sys/dev/ic/advlib.c
2599
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2600
val = HI_WORD(scsiq->q1.sense_addr);
sys/dev/ic/advlib.c
2601
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2602
val = MAKEWORD(scsiq->q1.sense_len, scsiq->q1.extra_bytes);
sys/dev/ic/advlib.c
2603
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2606
val = LO_WORD(scsiq->q2.ccb_ptr);
sys/dev/ic/advlib.c
2607
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2608
val = HI_WORD(scsiq->q2.ccb_ptr);
sys/dev/ic/advlib.c
2609
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2610
val = MAKEWORD(scsiq->q2.target_ix, scsiq->q2.flag);
sys/dev/ic/advlib.c
2611
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
2612
val = MAKEWORD(scsiq->q2.cdb_len, scsiq->q2.tag_code);
sys/dev/ic/advlib.c
2613
ASC_SET_CHIP_LRAM_DATA(iot, ioh, val);
sys/dev/ic/advlib.c
745
u_int8_t val;
sys/dev/ic/advlib.c
747
val = ASC_GET_CHIP_CONTROL(iot, ioh) &
sys/dev/ic/advlib.c
754
val |= ASC_CC_BANK_ONE;
sys/dev/ic/advlib.c
758
val |= ASC_CC_DIAG | ASC_CC_BANK_ONE;
sys/dev/ic/advlib.c
762
val &= ~ASC_CC_BANK_ONE;
sys/dev/ic/advlib.c
765
ASC_SET_CHIP_CONTROL(iot, ioh, val);
sys/dev/ic/advlib.h
1234
#define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val)
sys/dev/ic/advlib.h
1237
#define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val)
sys/dev/ic/advlib.h
1238
#define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val)
sys/dev/ic/advlib.h
1241
#define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val)
sys/dev/ic/advlib.h
1242
#define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val)
sys/dev/ic/aic6915.c
109
#define sf_funcreg_write(sc, reg, val) \
sys/dev/ic/aic6915.c
110
bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
sys/dev/ic/aic6915.c
127
sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
sys/dev/ic/aic6915.c
134
val);
sys/dev/ic/aic6915.c
138
bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
sys/dev/ic/aic6915.c
1389
sf_mii_write(struct device *self, int phy, int reg, int val)
sys/dev/ic/aic6915.c
1394
sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
sys/dev/ic/aic6915.c
143
#define sf_genreg_write(sc, reg, val) \
sys/dev/ic/aic6915.c
144
sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
sys/dev/ic/an.c
166
#define an_switch32(val) (val >> 16 | (val & 0xFFFF) << 16)
sys/dev/ic/an.c
169
#define an_switch32(val) val
sys/dev/ic/an.c
574
an_cmd(struct an_softc *sc, int cmd, int val)
sys/dev/ic/an.c
586
CSR_WRITE_2(sc, AN_PARAM0, val);
sys/dev/ic/an.c
614
sc->sc_dev.dv_xname, cmd, val);
sys/dev/ic/an.c
621
sc->sc_dev.dv_xname, cmd, val, stat,
sys/dev/ic/anvar.h
49
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/anvar.h
50
bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
sys/dev/ic/anvar.h
60
#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
sys/dev/ic/anvar.h
61
bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)
sys/dev/ic/anxdp.c
370
uint32_t val;
sys/dev/ic/anxdp.c
372
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST);
sys/dev/ic/anxdp.c
373
val |= MACRO_RST;
sys/dev/ic/anxdp.c
374
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val);
sys/dev/ic/anxdp.c
376
val &= ~MACRO_RST;
sys/dev/ic/anxdp.c
377
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val);
sys/dev/ic/anxdp.c
428
uint32_t val;
sys/dev/ic/anxdp.c
438
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/ic/anxdp.c
440
val &= ~(PRE_EMPHASIS_SET(3)|DRIVE_CURRENT_SET(3));
sys/dev/ic/anxdp.c
441
val |= PRE_EMPHASIS_SET(0);
sys/dev/ic/anxdp.c
443
ANXDP_LNx_LINK_TRAINING_CTL(i), val);
sys/dev/ic/anxdp.c
578
uint32_t val;
sys/dev/ic/anxdp.c
580
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1);
sys/dev/ic/anxdp.c
581
val &= ~VIDEO_EN;
sys/dev/ic/anxdp.c
582
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val);
sys/dev/ic/anxdp.c
584
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1);
sys/dev/ic/anxdp.c
585
val &= ~VIDEO_MUTE;
sys/dev/ic/anxdp.c
586
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val);
sys/dev/ic/anxdp.c
588
val = SW_FUNC_EN_N;
sys/dev/ic/anxdp.c
590
val |= RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N;
sys/dev/ic/anxdp.c
592
val |= MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
sys/dev/ic/anxdp.c
595
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val);
sys/dev/ic/anxdp.c
631
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1);
sys/dev/ic/anxdp.c
632
val &= ~SW_FUNC_EN_N;
sys/dev/ic/anxdp.c
633
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val);
sys/dev/ic/anxdp.c
640
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL);
sys/dev/ic/anxdp.c
641
val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
sys/dev/ic/anxdp.c
642
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL, val);
sys/dev/ic/anxdp.c
648
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2);
sys/dev/ic/anxdp.c
649
val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N |
sys/dev/ic/anxdp.c
651
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, val);
sys/dev/ic/anxdp.c
661
uint32_t val;
sys/dev/ic/anxdp.c
663
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1);
sys/dev/ic/anxdp.c
665
val &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
sys/dev/ic/anxdp.c
667
val &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
sys/dev/ic/anxdp.c
668
val |= MASTER_VID_FUNC_EN_N;
sys/dev/ic/anxdp.c
670
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val);
sys/dev/ic/anxdp.c
672
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10);
sys/dev/ic/anxdp.c
673
val &= ~(SLAVE_I_SCAN_CFG|SLAVE_VSYNC_P_CFG|SLAVE_HSYNC_P_CFG);
sys/dev/ic/anxdp.c
675
val |= SLAVE_I_SCAN_CFG;
sys/dev/ic/anxdp.c
677
val |= SLAVE_VSYNC_P_CFG;
sys/dev/ic/anxdp.c
679
val |= SLAVE_HSYNC_P_CFG;
sys/dev/ic/anxdp.c
680
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10, val);
sys/dev/ic/anxdp.c
687
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1);
sys/dev/ic/anxdp.c
688
val |= VIDEO_EN;
sys/dev/ic/anxdp.c
689
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val);
sys/dev/ic/anxdp.c
746
uint32_t val;
sys/dev/ic/anxdp.c
753
val = AUX_LENGTH(dpmsg->size);
sys/dev/ic/anxdp.c
755
val |= AUX_TX_COMM_MOT;
sys/dev/ic/anxdp.c
761
val |= AUX_TX_COMM_READ;
sys/dev/ic/anxdp.c
764
val |= AUX_TX_COMM_DP;
sys/dev/ic/anxdp.c
767
val |= AUX_TX_COMM_READ | AUX_TX_COMM_DP;
sys/dev/ic/anxdp.c
771
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_1, val);
sys/dev/ic/anxdp.c
793
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2);
sys/dev/ic/anxdp.c
794
while ((val & AUX_EN) != 0) {
sys/dev/ic/anxdp.c
800
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/ic/anxdp.c
805
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA);
sys/dev/ic/anxdp.c
806
while (!(val & RPLY_RECEIV)) {
sys/dev/ic/anxdp.c
812
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/ic/anxdp.c
819
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA);
sys/dev/ic/anxdp.c
820
if ((val & AUX_ERR) != 0) {
sys/dev/ic/anxdp.c
827
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_STA);
sys/dev/ic/anxdp.c
828
if (AUX_STATUS(val) != 0) {
sys/dev/ic/anxdp.c
835
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/ic/anxdp.c
837
((uint8_t *)(dpmsg->buffer))[i] = val & 0xffU;
sys/dev/ic/anxdp.c
842
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_RX_COMM);
sys/dev/ic/anxdp.c
843
if (val == AUX_RX_COMM_AUX_DEFER)
sys/dev/ic/anxdp.c
845
else if (val == AUX_RX_COMM_I2C_DEFER)
sys/dev/ic/ar5008.c
2544
uint32_t val = pvals[i];
sys/dev/ic/ar5008.c
2549
val &= ~AR_AN_TOP2_PWDCLKIND;
sys/dev/ic/ar5008.c
2550
AR_WRITE(sc, ini->regs[i], val);
sys/dev/ic/ar5008.c
2679
int16_t ss, delta, vpdstep, val;
sys/dev/ic/ar5008.c
2739
val = vpd[0] + ss * vpdstep;
sys/dev/ic/ar5008.c
2740
pdadcs[npdadcs++] = MAX(val, 0);
sys/dev/ic/ar5008.c
2758
val = vpd[nvpds - 1] + (ss - maxidx + 1) * vpdstep;
sys/dev/ic/ar5008.c
2759
pdadcs[npdadcs++] = MIN(val, 255);
sys/dev/ic/ar5008.c
279
ar5008_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
sys/dev/ic/ar5008.c
289
*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
sys/dev/ic/ar5008.c
294
*val = 0xffff;
sys/dev/ic/ar5210.c
1630
ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
sys/dev/ic/ar5210.c
1641
data |= (val&1) << gpio;
sys/dev/ic/ar5210.c
239
ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val)
sys/dev/ic/ar5210.c
242
u_int32_t mask = val ? val : ~0;
sys/dev/ic/ar5210.c
247
AR5K_REG_WRITE(AR5K_AR5210_RC, val);
sys/dev/ic/ar5210.c
252
val &=
sys/dev/ic/ar5210.c
260
ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE);
sys/dev/ic/ar5210.c
265
if ((val & AR5K_AR5210_RC_MAC) == 0) {
sys/dev/ic/ar5211.c
1736
ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
sys/dev/ic/ar5211.c
1747
data |= (val&1) << gpio;
sys/dev/ic/ar5211.c
236
ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val)
sys/dev/ic/ar5211.c
239
u_int32_t mask = val ? val : ~0;
sys/dev/ic/ar5211.c
247
AR5K_REG_WRITE(AR5K_AR5211_RC, val);
sys/dev/ic/ar5211.c
252
val &=
sys/dev/ic/ar5211.c
258
ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE);
sys/dev/ic/ar5211.c
263
if ((val & AR5K_AR5211_RC_PCU) == 0)
sys/dev/ic/ar5212.c
2059
ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
sys/dev/ic/ar5212.c
2070
data |= (val&1) << gpio;
sys/dev/ic/ar5212.c
281
ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val)
sys/dev/ic/ar5212.c
284
u_int32_t mask = val ? val : ~0;
sys/dev/ic/ar5212.c
292
AR5K_REG_WRITE(AR5K_AR5212_RC, val);
sys/dev/ic/ar5212.c
297
val &=
sys/dev/ic/ar5212.c
303
ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE);
sys/dev/ic/ar5212.c
308
if ((val & AR5K_AR5212_RC_PCU) == 0)
sys/dev/ic/ar5416.c
762
ar5416_rw_rfbits(uint32_t *buf, int col, int off, uint32_t val, int nbits)
sys/dev/ic/ar5416.c
773
buf[idx] |= ((val >> nbits) & 1) << (bit + col * 8);
sys/dev/ic/ar5xxx.c
1002
ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
sys/dev/ic/ar5xxx.c
1005
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
1006
ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
sys/dev/ic/ar5xxx.c
1007
ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
sys/dev/ic/ar5xxx.c
1010
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
1011
ee->ee_cck_ofdm_gain_delta = val & 0xff;
sys/dev/ic/ar5xxx.c
498
ar5k_printver(enum ar5k_srev_type type, u_int32_t val)
sys/dev/ic/ar5xxx.c
507
names[i].sr_val == val) {
sys/dev/ic/ar5xxx.c
520
if ((val & 0xff) < names[i + 1].sr_val) {
sys/dev/ic/ar5xxx.c
603
ar5k_bitswap(u_int32_t val, u_int bits)
sys/dev/ic/ar5xxx.c
606
val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4);
sys/dev/ic/ar5xxx.c
607
val = ((val & 0xCC) >> 2) | ((val & 0x33) << 2);
sys/dev/ic/ar5xxx.c
608
val = ((val & 0xAA) >> 1) | ((val & 0x55) << 1);
sys/dev/ic/ar5xxx.c
610
return val;
sys/dev/ic/ar5xxx.c
615
bit = (val >> i) & 1;
sys/dev/ic/ar5xxx.c
647
u_int32_t val, HAL_BOOL is_set)
sys/dev/ic/ar5xxx.c
656
else if ((data & flag) == val)
sys/dev/ic/ar5xxx.c
674
u_int16_t val;
sys/dev/ic/ar5xxx.c
681
val = (5 * bin) + 4800;
sys/dev/ic/ar5xxx.c
683
val = bin > 62 ?
sys/dev/ic/ar5xxx.c
688
val = bin + 2300;
sys/dev/ic/ar5xxx.c
690
val = bin + 2400;
sys/dev/ic/ar5xxx.c
693
return (val);
sys/dev/ic/ar5xxx.c
701
u_int16_t val;
sys/dev/ic/ar5xxx.c
704
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
705
ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
sys/dev/ic/ar5xxx.c
706
ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
sys/dev/ic/ar5xxx.c
707
ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
sys/dev/ic/ar5xxx.c
709
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
710
ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
sys/dev/ic/ar5xxx.c
711
ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
sys/dev/ic/ar5xxx.c
712
ee->ee_ant_control[mode][i++] = val & 0x3f;
sys/dev/ic/ar5xxx.c
714
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
715
ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
sys/dev/ic/ar5xxx.c
716
ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
sys/dev/ic/ar5xxx.c
717
ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
sys/dev/ic/ar5xxx.c
719
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
720
ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
sys/dev/ic/ar5xxx.c
721
ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
sys/dev/ic/ar5xxx.c
722
ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
sys/dev/ic/ar5xxx.c
723
ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
sys/dev/ic/ar5xxx.c
725
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
726
ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
sys/dev/ic/ar5xxx.c
727
ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
sys/dev/ic/ar5xxx.c
728
ee->ee_ant_control[mode][i++] = val & 0x3f;
sys/dev/ic/ar5xxx.c
757
u_int16_t val;
sys/dev/ic/ar5xxx.c
760
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
761
ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
sys/dev/ic/ar5xxx.c
762
ee->ee_thr_62[mode] = val & 0xff;
sys/dev/ic/ar5xxx.c
768
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
769
ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
sys/dev/ic/ar5xxx.c
770
ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
sys/dev/ic/ar5xxx.c
772
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
773
ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
sys/dev/ic/ar5xxx.c
775
if ((val & 0xff) & 0x80)
sys/dev/ic/ar5xxx.c
776
ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
sys/dev/ic/ar5xxx.c
778
ee->ee_noise_floor_thr[mode] = val & 0xff;
sys/dev/ic/ar5xxx.c
784
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
785
ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
sys/dev/ic/ar5xxx.c
786
ee->ee_x_gain[mode] = (val >> 1) & 0xf;
sys/dev/ic/ar5xxx.c
787
ee->ee_xpd[mode] = val & 0x1;
sys/dev/ic/ar5xxx.c
790
ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
sys/dev/ic/ar5xxx.c
793
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
794
ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
sys/dev/ic/ar5xxx.c
797
ee->ee_xr_power[mode] = val & 0x3f;
sys/dev/ic/ar5xxx.c
799
ee->ee_ob[mode][0] = val & 0x7;
sys/dev/ic/ar5xxx.c
800
ee->ee_db[mode][0] = (val >> 3) & 0x7;
sys/dev/ic/ar5xxx.c
808
ee->ee_i_gain[mode] = (val >> 13) & 0x7;
sys/dev/ic/ar5xxx.c
810
AR5K_EEPROM_READ(o++, val);
sys/dev/ic/ar5xxx.c
811
ee->ee_i_gain[mode] |= (val << 3) & 0x38;
sys/dev/ic/ar5xxx.c
814
ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
sys/dev/ic/ar5xxx.c
819
ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
sys/dev/ic/ar5xxx.c
820
ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
sys/dev/ic/ar5xxx.c
825
ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
sys/dev/ic/ar5xxx.c
838
u_int16_t val;
sys/dev/ic/ar5xxx.c
866
AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
sys/dev/ic/ar5xxx.c
867
cksum ^= val;
sys/dev/ic/ar5xxx.c
884
AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
sys/dev/ic/ar5xxx.c
885
ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
sys/dev/ic/ar5xxx.c
886
ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
sys/dev/ic/ar5xxx.c
888
AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
sys/dev/ic/ar5xxx.c
889
ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
sys/dev/ic/ar5xxx.c
890
ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
sys/dev/ic/ar5xxx.c
900
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
901
ee->ee_ctl[i] = (val >> 8) & 0xff;
sys/dev/ic/ar5xxx.c
902
ee->ee_ctl[i + 1] = val & 0xff;
sys/dev/ic/ar5xxx.c
915
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
916
ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
sys/dev/ic/ar5xxx.c
917
ee->ee_ob[mode][3] = (val >> 5) & 0x7;
sys/dev/ic/ar5xxx.c
918
ee->ee_db[mode][3] = (val >> 2) & 0x7;
sys/dev/ic/ar5xxx.c
919
ee->ee_ob[mode][2] = (val << 1) & 0x7;
sys/dev/ic/ar5xxx.c
921
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
922
ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
sys/dev/ic/ar5xxx.c
923
ee->ee_db[mode][2] = (val >> 12) & 0x7;
sys/dev/ic/ar5xxx.c
924
ee->ee_ob[mode][1] = (val >> 9) & 0x7;
sys/dev/ic/ar5xxx.c
925
ee->ee_db[mode][1] = (val >> 6) & 0x7;
sys/dev/ic/ar5xxx.c
926
ee->ee_ob[mode][0] = (val >> 3) & 0x7;
sys/dev/ic/ar5xxx.c
927
ee->ee_db[mode][0] = val & 0x7;
sys/dev/ic/ar5xxx.c
933
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
934
ee->ee_margin_tx_rx[mode] = val & 0x3f;
sys/dev/ic/ar5xxx.c
946
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
947
ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
sys/dev/ic/ar5xxx.c
948
ee->ee_ob[mode][1] = (val >> 4) & 0x7;
sys/dev/ic/ar5xxx.c
949
ee->ee_db[mode][1] = val & 0x7;
sys/dev/ic/ar5xxx.c
955
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
957
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
sys/dev/ic/ar5xxx.c
959
ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
sys/dev/ic/ar5xxx.c
961
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
963
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
sys/dev/ic/ar5xxx.c
967
ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
sys/dev/ic/ar5xxx.c
979
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
980
ee->ee_adc_desired_size[mode] = (int8_t)((val >> 8) & 0xff);
sys/dev/ic/ar5xxx.c
981
ee->ee_ob[mode][1] = (val >> 4) & 0x7;
sys/dev/ic/ar5xxx.c
982
ee->ee_db[mode][1] = val & 0x7;
sys/dev/ic/ar5xxx.c
988
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
990
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
sys/dev/ic/ar5xxx.c
992
ar5k_eeprom_bin2freq(hal, (val >> 8) & 0xff, mode);
sys/dev/ic/ar5xxx.c
994
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
995
ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
sys/dev/ic/ar5xxx.c
997
AR5K_EEPROM_READ(offset++, val);
sys/dev/ic/ar5xxx.c
999
ar5k_eeprom_bin2freq(hal, val & 0xff, mode);
sys/dev/ic/ar5xxx.h
996
u_int32_t val); \
sys/dev/ic/ar9003.c
2227
} val[2][2];
sys/dev/ic/ar9003.c
2235
val[0][0].m = res[0] & 0xfff;
sys/dev/ic/ar9003.c
2236
val[0][0].p = (res[0] >> 12) & 0xfff;
sys/dev/ic/ar9003.c
2237
val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8;
sys/dev/ic/ar9003.c
2239
val[0][1].m = (res[1] >> 4) & 0xfff;
sys/dev/ic/ar9003.c
2240
val[0][1].p = res[2] & 0xfff;
sys/dev/ic/ar9003.c
2241
val[0][1].c = (res[2] >> 12) & 0xfff;
sys/dev/ic/ar9003.c
2243
val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8;
sys/dev/ic/ar9003.c
2244
val[1][0].p = (res[3] >> 4) & 0xfff;
sys/dev/ic/ar9003.c
2245
val[1][0].c = res[4] & 0xfff;
sys/dev/ic/ar9003.c
2247
val[1][1].m = (res[4] >> 12) & 0xfff;
sys/dev/ic/ar9003.c
2248
val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8;
sys/dev/ic/ar9003.c
2249
val[1][1].c = (res[5] >> 4) & 0xfff;
sys/dev/ic/ar9003.c
2253
m = SIGN_EXT(val[i][j].m);
sys/dev/ic/ar9003.c
2254
p = SIGN_EXT(val[i][j].p);
sys/dev/ic/ar9003.c
2255
c = SIGN_EXT(val[i][j].c);
sys/dev/ic/ar9003.c
235
ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
sys/dev/ic/ar9003.c
245
*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
sys/dev/ic/ar9003.c
250
*val = 0xffff;
sys/dev/ic/ar9003.c
262
uint16_t val;
sys/dev/ic/ar9003.c
2657
get_scale(int val)
sys/dev/ic/ar9003.c
2662
while (val >>= 1)
sys/dev/ic/ar9003.c
268
error = ar9003_read_eep_word(sc, addr, &val);
sys/dev/ic/ar9003.c
271
*dst++ = val & 0xff;
sys/dev/ic/ar9003.c
277
error = ar9003_read_eep_word(sc, addr, &val);
sys/dev/ic/ar9003.c
280
*dst++ = val >> 8;
sys/dev/ic/ar9003.c
281
*dst++ = val & 0xff;
sys/dev/ic/ar9003.c
284
error = ar9003_read_eep_word(sc, addr, &val);
sys/dev/ic/ar9003.c
287
*dst++ = val >> 8;
sys/dev/ic/ar9003.c
296
ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val)
sys/dev/ic/ar9003.c
305
*val = AR_READ(sc, AR_OTP_READ_DATA);
sys/dev/ic/ar9003.c
321
uint32_t val;
sys/dev/ic/ar9003.c
326
error = ar9003_read_otp_word(sc, addr >> 2, &val);
sys/dev/ic/ar9003.c
329
*dst++ = (val >> ((addr & 3) * 8)) & 0xff;
sys/dev/ic/ar9380.c
462
ar9485_pmu_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
sys/dev/ic/ar9380.c
466
AR_WRITE(sc, addr, val);
sys/dev/ic/ar9380.c
469
if (AR_READ(sc, addr) == val)
sys/dev/ic/ar9380.c
471
AR_WRITE(sc, addr, val); /* Insist. */
sys/dev/ic/ath.c
1073
u_int32_t val;
sys/dev/ic/ath.c
1076
val = LE_READ_4(dl + 0);
sys/dev/ic/ath.c
1077
pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
sys/dev/ic/ath.c
1078
val = LE_READ_4(dl + 3);
sys/dev/ic/ath.c
1079
pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
sys/dev/ic/athn.c
2897
uint32_t val, lo, hi;
sys/dev/ic/athn.c
2912
val = addr[0] | addr[1] << 8 | addr[2] << 16;
sys/dev/ic/athn.c
2913
bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
sys/dev/ic/athn.c
2914
val = addr[3] | addr[4] << 8 | addr[5] << 16;
sys/dev/ic/athn.c
2915
bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
sys/dev/ic/athnreg.h
1474
#define AR_WRITE(sc, reg, val) \
sys/dev/ic/athnreg.h
1475
(sc)->ops.write((sc), (reg), (val))
sys/dev/ic/athnreg.h
1490
#define MS(val, field) \
sys/dev/ic/athnreg.h
1491
(((uint32_t)(val) & field##_M) >> field##_S)
sys/dev/ic/athnreg.h
1494
#define SM(field, val) \
sys/dev/ic/athnreg.h
1495
(((uint32_t)(val) << field##_S) & field##_M)
sys/dev/ic/athnreg.h
1498
#define RW(var, field, val) \
sys/dev/ic/athnreg.h
1499
(((var) & ~field##_M) | SM(field, val))
sys/dev/ic/atw.c
1511
u_int addr, val;
sys/dev/ic/atw.c
1518
if (atw_si4126_read(sc, addr, &val) == 0) {
sys/dev/ic/atw.c
1522
printf("%05x\n", val);
sys/dev/ic/atw.c
1738
u_int addr, val;
sys/dev/ic/atw.c
1745
if (atw_rf3000_read(sc, addr, &val) != 0) {
sys/dev/ic/atw.c
1749
printf("%08x\n", val);
sys/dev/ic/atw.c
1828
atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val)
sys/dev/ic/atw.c
1834
LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) |
sys/dev/ic/atw.c
1866
atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val)
sys/dev/ic/atw.c
1900
if (val != NULL)
sys/dev/ic/atw.c
1901
*val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK);
sys/dev/ic/atw.c
1914
atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val)
sys/dev/ic/atw.c
1922
val &= 0x3ffff;
sys/dev/ic/atw.c
1924
bits = val | (addr << 18);
sys/dev/ic/atw.c
1929
KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
sys/dev/ic/atw.c
1931
bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
sys/dev/ic/atw.c
1963
atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val)
sys/dev/ic/atw.c
1999
if (val != NULL)
sys/dev/ic/atw.c
2000
*val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL),
sys/dev/ic/atwreg.h
79
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
sys/dev/ic/atwvar.h
423
#define ATW_WRITE(sc, reg, val) \
sys/dev/ic/atwvar.h
424
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/ax88190.c
145
ax88190_mii_bitbang_write(struct device *self, u_int32_t val)
sys/dev/ic/ax88190.c
149
bus_space_write_1(sc->sc_asict, sc->sc_asich, AX88190_MEMR, val);
sys/dev/ic/ax88190.c
159
ax88190_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/ax88190.c
161
mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);
sys/dev/ic/bcmgenet.c
133
genet_mii_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/ic/bcmgenet.c
139
val | GENET_MDIO_WRITE | GENET_MDIO_START_BUSY |
sys/dev/ic/bcmgenet.c
156
uint32_t val;
sys/dev/ic/bcmgenet.c
167
val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);
sys/dev/ic/bcmgenet.c
168
val &= ~GENET_EXT_RGMII_OOB_OOB_DISABLE;
sys/dev/ic/bcmgenet.c
169
val |= GENET_EXT_RGMII_OOB_RGMII_LINK;
sys/dev/ic/bcmgenet.c
170
val |= GENET_EXT_RGMII_OOB_RGMII_MODE_EN;
sys/dev/ic/bcmgenet.c
172
val |= GENET_EXT_RGMII_OOB_ID_MODE_DISABLE;
sys/dev/ic/bcmgenet.c
174
val &= ~GENET_EXT_RGMII_OOB_ID_MODE_DISABLE;
sys/dev/ic/bcmgenet.c
175
WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
sys/dev/ic/bcmgenet.c
177
val = RD4(sc, GENET_UMAC_CMD);
sys/dev/ic/bcmgenet.c
178
val &= ~GENET_UMAC_CMD_SPEED;
sys/dev/ic/bcmgenet.c
179
val |= __SHIFTIN(speed, GENET_UMAC_CMD_SPEED);
sys/dev/ic/bcmgenet.c
180
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
438
uint32_t val;
sys/dev/ic/bcmgenet.c
441
val = RD4(sc, GENET_UMAC_CMD);
sys/dev/ic/bcmgenet.c
442
val &= ~GENET_UMAC_CMD_RXEN;
sys/dev/ic/bcmgenet.c
443
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
446
val = RD4(sc, GENET_RX_DMA_CTRL);
sys/dev/ic/bcmgenet.c
447
val &= ~GENET_RX_DMA_CTRL_EN;
sys/dev/ic/bcmgenet.c
448
val &= ~GENET_RX_DMA_CTRL_RBUF_EN(GENET_DMA_DEFAULT_QUEUE);
sys/dev/ic/bcmgenet.c
449
WR4(sc, GENET_RX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
452
val = RD4(sc, GENET_TX_DMA_CTRL);
sys/dev/ic/bcmgenet.c
453
val &= ~GENET_TX_DMA_CTRL_EN;
sys/dev/ic/bcmgenet.c
454
val &= ~GENET_TX_DMA_CTRL_RBUF_EN(GENET_DMA_DEFAULT_QUEUE);
sys/dev/ic/bcmgenet.c
455
WR4(sc, GENET_TX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
463
val = RD4(sc, GENET_UMAC_CMD);
sys/dev/ic/bcmgenet.c
464
val &= ~GENET_UMAC_CMD_TXEN;
sys/dev/ic/bcmgenet.c
465
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
471
uint32_t val;
sys/dev/ic/bcmgenet.c
475
val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
sys/dev/ic/bcmgenet.c
476
val |= GENET_SYS_RBUF_FLUSH_RESET;
sys/dev/ic/bcmgenet.c
477
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
sys/dev/ic/bcmgenet.c
480
val &= ~GENET_SYS_RBUF_FLUSH_RESET;
sys/dev/ic/bcmgenet.c
481
WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
sys/dev/ic/bcmgenet.c
499
val = RD4(sc, GENET_RBUF_CTRL);
sys/dev/ic/bcmgenet.c
500
val |= GENET_RBUF_ALIGN_2B;
sys/dev/ic/bcmgenet.c
501
WR4(sc, GENET_RBUF_CTRL, val);
sys/dev/ic/bcmgenet.c
511
uint32_t val;
sys/dev/ic/bcmgenet.c
540
val = RD4(sc, GENET_TX_DMA_CTRL);
sys/dev/ic/bcmgenet.c
541
val |= GENET_TX_DMA_CTRL_EN;
sys/dev/ic/bcmgenet.c
542
val |= GENET_TX_DMA_CTRL_RBUF_EN(qid);
sys/dev/ic/bcmgenet.c
543
WR4(sc, GENET_TX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
577
val = RD4(sc, GENET_RX_DMA_CTRL);
sys/dev/ic/bcmgenet.c
578
val |= GENET_RX_DMA_CTRL_EN;
sys/dev/ic/bcmgenet.c
579
val |= GENET_RX_DMA_CTRL_RBUF_EN(qid);
sys/dev/ic/bcmgenet.c
580
WR4(sc, GENET_RX_DMA_CTRL, val);
sys/dev/ic/bcmgenet.c
588
uint32_t val;
sys/dev/ic/bcmgenet.c
602
val = enaddr[3] | (enaddr[2] << 8) | (enaddr[1] << 16) |
sys/dev/ic/bcmgenet.c
604
WR4(sc, GENET_UMAC_MAC0, val);
sys/dev/ic/bcmgenet.c
605
val = enaddr[5] | (enaddr[4] << 8);
sys/dev/ic/bcmgenet.c
606
WR4(sc, GENET_UMAC_MAC1, val);
sys/dev/ic/bcmgenet.c
615
val = RD4(sc, GENET_UMAC_CMD);
sys/dev/ic/bcmgenet.c
616
val |= GENET_UMAC_CMD_TXEN;
sys/dev/ic/bcmgenet.c
617
val |= GENET_UMAC_CMD_RXEN;
sys/dev/ic/bcmgenet.c
618
WR4(sc, GENET_UMAC_CMD, val);
sys/dev/ic/bcmgenet.c
81
#define WR4(sc, reg, val) \
sys/dev/ic/bcmgenet.c
819
uint32_t val;
sys/dev/ic/bcmgenet.c
82
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
sys/dev/ic/bcmgenet.c
821
val = RD4(sc, GENET_INTRL2_CPU_STAT);
sys/dev/ic/bcmgenet.c
822
val &= ~RD4(sc, GENET_INTRL2_CPU_STAT_MASK);
sys/dev/ic/bcmgenet.c
823
WR4(sc, GENET_INTRL2_CPU_CLEAR, val);
sys/dev/ic/bcmgenet.c
825
if (val & GENET_IRQ_RXDMA_DONE)
sys/dev/ic/bcmgenet.c
828
if (val & GENET_IRQ_TXDMA_DONE) {
sys/dev/ic/bt463.c
160
#define BTWREG(data, addr, val) do { bt463_wraddr((data), (addr)); \
sys/dev/ic/bt463.c
161
(data)->ramdac_wr((data)->cookie, BT463_REG_IREG_DATA, (val)); } while (0)
sys/dev/ic/bt463.c
162
#define BTWNREG(data, val) (data)->ramdac_wr((data)->cookie, \
sys/dev/ic/bt463.c
163
BT463_REG_IREG_DATA, (val))
sys/dev/ic/bt463.c
506
u_int8_t val;
sys/dev/ic/bt463.c
510
val = BTRREG(data, i);
sys/dev/ic/bt463.c
511
printf(" $%04x %02x\n", i, val);
sys/dev/ic/bt463.c
515
val = BTRREG(data, 0x220);
sys/dev/ic/bt463.c
516
printf(" $%04x %02x\n", 0x220, val);
sys/dev/ic/bt485.c
488
bt485_wr_i(struct bt485data *data, u_int8_t ireg, u_int8_t val)
sys/dev/ic/bt485.c
491
data->ramdac_wr(data->cookie, BT485_REG_EXTENDED, val);
sys/dev/ic/bwfm.c
1065
uint32_t val;
sys/dev/ic/bwfm.c
1068
val = sc->sc_buscore_ops->bc_read(sc,
sys/dev/ic/bwfm.c
1070
if ((val & BWFM_AGENT_RESET_CTL_RESET) == 0) {
sys/dev/ic/bwfm.c
1130
uint32_t erom, val, base, wrap;
sys/dev/ic/bwfm.c
1139
val = sc->sc_buscore_ops->bc_read(sc, erom);
sys/dev/ic/bwfm.c
1140
type = val & BWFM_DMP_DESC_MASK;
sys/dev/ic/bwfm.c
1146
id = (val & BWFM_DMP_COMP_PARTNUM)
sys/dev/ic/bwfm.c
1149
val = sc->sc_buscore_ops->bc_read(sc, erom);
sys/dev/ic/bwfm.c
1150
type = val & BWFM_DMP_DESC_MASK;
sys/dev/ic/bwfm.c
1158
nmw = (val & BWFM_DMP_COMP_NUM_MWRAP)
sys/dev/ic/bwfm.c
1160
nsw = (val & BWFM_DMP_COMP_NUM_SWRAP)
sys/dev/ic/bwfm.c
1162
rev = (val & BWFM_DMP_COMP_REVISION)
sys/dev/ic/bwfm.c
1187
uint32_t val;
sys/dev/ic/bwfm.c
1192
val = sc->sc_buscore_ops->bc_read(sc, *erom);
sys/dev/ic/bwfm.c
1193
type = val & BWFM_DMP_DESC_MASK;
sys/dev/ic/bwfm.c
1195
mpnum = (val & BWFM_DMP_MASTER_PORT_NUM)
sys/dev/ic/bwfm.c
1207
val = sc->sc_buscore_ops->bc_read(sc, *erom);
sys/dev/ic/bwfm.c
1208
type = val & BWFM_DMP_DESC_MASK;
sys/dev/ic/bwfm.c
1220
sztype = (val & BWFM_DMP_SLAVE_SIZE_TYPE)
sys/dev/ic/bwfm.c
1223
val = sc->sc_buscore_ops->bc_read(sc, *erom);
sys/dev/ic/bwfm.c
1224
type = val & BWFM_DMP_DESC_MASK;
sys/dev/ic/bwfm.c
1234
stype = (val & BWFM_DMP_SLAVE_TYPE) >> BWFM_DMP_SLAVE_TYPE_S;
sys/dev/ic/bwfm.c
1236
*base = val & BWFM_DMP_SLAVE_ADDR_BASE;
sys/dev/ic/bwfm.c
1238
*wrap = val & BWFM_DMP_SLAVE_ADDR_BASE;
sys/dev/ic/bwfm.c
1291
uint32_t val;
sys/dev/ic/bwfm.c
1295
val = sc->sc_buscore_ops->bc_read(sc,
sys/dev/ic/bwfm.c
1298
val & BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
sys/dev/ic/bwfm.c
1326
uint32_t val;
sys/dev/ic/bwfm.c
1330
val = sc->sc_buscore_ops->bc_read(sc,
sys/dev/ic/bwfm.c
1333
val & BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
sys/dev/ic/bwfm.c
888
uint32_t val;
sys/dev/ic/bwfm.c
897
val = sc->sc_buscore_ops->bc_read(sc,
sys/dev/ic/bwfm.c
899
sc->sc_chip.ch_chip = BWFM_CHIP_CHIPID_ID(val);
sys/dev/ic/bwfm.c
900
sc->sc_chip.ch_chiprev = BWFM_CHIP_CHIPID_REV(val);
sys/dev/ic/bwfm.c
909
switch (BWFM_CHIP_CHIPID_TYPE(val))
sys/dev/ic/bwfm.c
923
DEVNAME(sc), BWFM_CHIP_CHIPID_TYPE(val));
sys/dev/ic/bwi.c
1341
uint32_t orig_val, val;
sys/dev/ic/bwi.c
1350
val = MOBJ_READ_4(mac, BWI_COMM_MOBJ, 0);
sys/dev/ic/bwi.c
1351
if (val != TEST_VAL1) {
sys/dev/ic/bwi.c
1358
val = MOBJ_READ_4(mac, BWI_COMM_MOBJ, 0);
sys/dev/ic/bwi.c
1359
if (val != TEST_VAL2) {
sys/dev/ic/bwi.c
1367
val = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
1368
if ((val & ~BWI_MAC_STATUS_PHYLNK) != BWI_MAC_STATUS_IHREN) {
sys/dev/ic/bwi.c
1370
sc->sc_dev.dv_xname, __func__, val);
sys/dev/ic/bwi.c
1374
val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
sys/dev/ic/bwi.c
1375
if (val != 0) {
sys/dev/ic/bwi.c
1377
sc->sc_dev.dv_xname, __func__, val);
sys/dev/ic/bwi.c
2395
uint32_t val;
sys/dev/ic/bwi.c
2400
val = CSR_READ_4(sc, BWI_MAC_STATUS);
sys/dev/ic/bwi.c
2401
if (val & BWI_MAC_STATUS_BSWAP) {
sys/dev/ic/bwi.c
2411
val = CSR_READ_4(sc, BWI_STATE_HI);
sys/dev/ic/bwi.c
2412
if (__SHIFTOUT(val, BWI_STATE_HI_FLAGS_MASK) &
sys/dev/ic/bwi.c
2833
uint16_t val;
sys/dev/ic/bwi.c
2837
val = CSR_READ_2(sc, BWI_PHYINFO);
sys/dev/ic/bwi.c
2838
phyrev = __SHIFTOUT(val, BWI_PHYINFO_REV_MASK);
sys/dev/ic/bwi.c
2839
phytype = __SHIFTOUT(val, BWI_PHYINFO_TYPE_MASK);
sys/dev/ic/bwi.c
2840
phyver = __SHIFTOUT(val, BWI_PHYINFO_VER_MASK);
sys/dev/ic/bwi.c
3013
uint16_t val;
sys/dev/ic/bwi.c
3015
val = PHY_READ(mac, 0x400) & 0xff;
sys/dev/ic/bwi.c
3016
if (val == 3 || val == 5) {
sys/dev/ic/bwi.c
3019
if (val == 5) {
sys/dev/ic/bwi.c
3113
uint16_t val, ofs;
sys/dev/ic/bwi.c
3123
for (ofs = 0, val = 0x3c3d; ofs < 30; ++ofs, val -= 0x202)
sys/dev/ic/bwi.c
3124
PHY_WRITE(mac, 0x89 + ofs, val);
sys/dev/ic/bwi.c
3190
uint16_t ofs, val;
sys/dev/ic/bwi.c
3192
val = 0x2120;
sys/dev/ic/bwi.c
3194
PHY_WRITE(mac, ofs, val);
sys/dev/ic/bwi.c
3195
val += 0x202;
sys/dev/ic/bwi.c
3284
uint16_t val, ofs;
sys/dev/ic/bwi.c
3322
val = 0x1e1f;
sys/dev/ic/bwi.c
3324
PHY_WRITE(mac, ofs, val);
sys/dev/ic/bwi.c
3325
val -= 0x202;
sys/dev/ic/bwi.c
3328
val = 0x3e3f;
sys/dev/ic/bwi.c
3330
PHY_WRITE(mac, ofs, val);
sys/dev/ic/bwi.c
3331
val -= 0x202;
sys/dev/ic/bwi.c
3334
val = 0x2120;
sys/dev/ic/bwi.c
3336
PHY_WRITE(mac, ofs, (val & 0x3f3f));
sys/dev/ic/bwi.c
3337
val += 0x202;
sys/dev/ic/bwi.c
3697
int16_t val;
sys/dev/ic/bwi.c
3700
val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
sys/dev/ic/bwi.c
3701
if (val >= 32)
sys/dev/ic/bwi.c
3702
val -= 64;
sys/dev/ic/bwi.c
3704
return (val);
sys/dev/ic/bwi.c
3784
uint32_t val;
sys/dev/ic/bwi.c
3787
val = CSR_READ_2(sc, BWI_RF_DATA_HI);
sys/dev/ic/bwi.c
3788
val <<= 16;
sys/dev/ic/bwi.c
3791
val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
sys/dev/ic/bwi.c
3793
manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
sys/dev/ic/bwi.c
3794
type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
sys/dev/ic/bwi.c
3795
rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
sys/dev/ic/bwi.c
4173
uint16_t val;
sys/dev/ic/bwi.c
4175
val = (uint8_t)lo->ctrl_lo;
sys/dev/ic/bwi.c
4176
val |= ((uint8_t)lo->ctrl_hi) << 8;
sys/dev/ic/bwi.c
4178
PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
sys/dev/ic/bwi.c
4195
bwi_bitswap4(uint16_t val)
sys/dev/ic/bwi.c
4199
ret = (val & 0x8) >> 3;
sys/dev/ic/bwi.c
4200
ret |= (val & 0x4) >> 1;
sys/dev/ic/bwi.c
4201
ret |= (val & 0x2) << 1;
sys/dev/ic/bwi.c
4202
ret |= (val & 0x1) << 3;
sys/dev/ic/bwi.c
4544
uint16_t val, calib;
sys/dev/ic/bwi.c
4553
val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
sys/dev/ic/bwi.c
4554
idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
sys/dev/ic/bwi.c
4558
if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
sys/dev/ic/bwi.c
4621
uint16_t sprom_ofs, val, mask;
sys/dev/ic/bwi.c
4628
val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
sys/dev/ic/bwi.c
4630
rf->rf_txpower_max = __SHIFTOUT(val,
sys/dev/ic/bwi.c
4633
rf->rf_txpower_max = __SHIFTOUT(val,
sys/dev/ic/bwi.c
4653
val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
sys/dev/ic/bwi.c
4655
ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
sys/dev/ic/bwi.c
4657
ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
sys/dev/ic/bwi.c
4738
val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
sys/dev/ic/bwi.c
4739
DPRINTF(1, "%s: sprom idle tssi: 0x%04x\n", sc->sc_dev.dv_xname, val);
sys/dev/ic/bwi.c
4746
rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
sys/dev/ic/bwi.c
5019
int val;
sys/dev/ic/bwi.c
5021
val = rf_atten * 2 + bbp_atten;
sys/dev/ic/bwi.c
5022
if (val > 14) {
sys/dev/ic/bwi.c
5024
if (val > 17)
sys/dev/ic/bwi.c
5026
if (val > 19)
sys/dev/ic/bwi.c
5608
int val;
sys/dev/ic/bwi.c
5610
val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
sys/dev/ic/bwi.c
5611
if (val < 0)
sys/dev/ic/bwi.c
5612
val = 0;
sys/dev/ic/bwi.c
5613
else if (val > 0x3f)
sys/dev/ic/bwi.c
5614
val = 0x3f;
sys/dev/ic/bwi.c
5616
rf->rf_nrssi_table[i] = val;
sys/dev/ic/bwi.c
5626
int16_t val;
sys/dev/ic/bwi.c
5628
val = bwi_nrssi_read(mac, i);
sys/dev/ic/bwi.c
5630
val -= adjust;
sys/dev/ic/bwi.c
5631
if (val < -32)
sys/dev/ic/bwi.c
5632
val = -32;
sys/dev/ic/bwi.c
5633
else if (val > 31)
sys/dev/ic/bwi.c
5634
val = 31;
sys/dev/ic/bwi.c
5636
bwi_nrssi_write(mac, i, val);
sys/dev/ic/bwi.c
5681
_nrssi_threshold(const struct bwi_rf *rf, int32_t val)
sys/dev/ic/bwi.c
5683
val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
sys/dev/ic/bwi.c
5684
val += (rf->rf_nrssi[0] << 6);
sys/dev/ic/bwi.c
5685
if (val < 32)
sys/dev/ic/bwi.c
5686
val += 31;
sys/dev/ic/bwi.c
5688
val += 32;
sys/dev/ic/bwi.c
5689
val >>= 6;
sys/dev/ic/bwi.c
5690
if (val < -31)
sys/dev/ic/bwi.c
5691
val = -31;
sys/dev/ic/bwi.c
5692
else if (val > 31)
sys/dev/ic/bwi.c
5693
val = 31;
sys/dev/ic/bwi.c
5695
return (val);
sys/dev/ic/bwi.c
5744
uint16_t val;
sys/dev/ic/bwi.c
5747
val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
sys/dev/ic/bwi.c
5752
BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
sys/dev/ic/bwi.c
5757
BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
sys/dev/ic/bwi.c
5812
uint16_t val;
sys/dev/ic/bwi.c
5823
val = BWI_ANT_MODE_AUTO;
sys/dev/ic/bwi.c
5825
val = ant_mode;
sys/dev/ic/bwi.c
5826
val <<= 7;
sys/dev/ic/bwi.c
5827
PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
sys/dev/ic/bwi.c
5830
val = ant_mode << 7;
sys/dev/ic/bwi.c
5831
PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
sys/dev/ic/bwi.c
5864
val = ant_mode << 8;
sys/dev/ic/bwi.c
5866
0xfc3f, val);
sys/dev/ic/bwi.c
5868
0xfc3f, val);
sys/dev/ic/bwi.c
5870
0xfc3f, val);
sys/dev/ic/bwi.c
5889
uint16_t val;
sys/dev/ic/bwi.c
5891
val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
sys/dev/ic/bwi.c
5892
tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
sys/dev/ic/bwi.c
5893
tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
sys/dev/ic/bwi.c
6062
uint16_t val;
sys/dev/ic/bwi.c
6065
val = 0;
sys/dev/ic/bwi.c
6074
val += PHY_READ(mac, 0x2c);
sys/dev/ic/bwi.c
6077
return (val);
sys/dev/ic/bwi.c
6086
uint16_t rf_val, phy_val, min_val, val;
sys/dev/ic/bwi.c
6144
val = bwi_rf_lo_measure_11b(mac) / 10;
sys/dev/ic/bwi.c
6145
if (val < min_val) {
sys/dev/ic/bwi.c
6146
min_val = val;
sys/dev/ic/bwi.c
6169
val = bwi_rf_lo_measure_11b(mac) / 10;
sys/dev/ic/bwi.c
6170
if (val < min_val) {
sys/dev/ic/bwi.c
6171
min_val = val;
sys/dev/ic/bwi.c
6353
uint32_t val;
sys/dev/ic/bwi.c
6355
val = CSR_READ_4(sc, BWI_ID_HI);
sys/dev/ic/bwi.c
6356
*type = BWI_ID_HI_REGWIN_TYPE(val);
sys/dev/ic/bwi.c
6357
*rev = BWI_ID_HI_REGWIN_REV(val);
sys/dev/ic/bwi.c
6361
*type, *rev, __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
sys/dev/ic/bwi.c
6368
uint16_t gpio, val[BWI_LED_MAX];
sys/dev/ic/bwi.c
6381
val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
sys/dev/ic/bwi.c
6382
val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
sys/dev/ic/bwi.c
6385
val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
sys/dev/ic/bwi.c
6386
val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
sys/dev/ic/bwi.c
6391
if (val[i] == 0xff) {
sys/dev/ic/bwi.c
6394
if (val[i] & BWI_LED_ACT_LOW)
sys/dev/ic/bwi.c
6396
led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
sys/dev/ic/bwi.c
6425
bwi_led_onoff(struct bwi_led *led, uint16_t val, int on)
sys/dev/ic/bwi.c
6430
val |= led->l_mask;
sys/dev/ic/bwi.c
6432
val &= ~led->l_mask;
sys/dev/ic/bwi.c
6434
return (val);
sys/dev/ic/bwi.c
6441
uint16_t val;
sys/dev/ic/bwi.c
6453
val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
sys/dev/ic/bwi.c
6493
val = bwi_led_onoff(led, val, on);
sys/dev/ic/bwi.c
6495
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/ic/bwi.c
6537
uint16_t val;
sys/dev/ic/bwi.c
6539
val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
sys/dev/ic/bwi.c
6540
val = bwi_led_onoff(led, val, 1);
sys/dev/ic/bwi.c
6541
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/ic/bwi.c
6558
uint16_t val;
sys/dev/ic/bwi.c
6560
val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
sys/dev/ic/bwi.c
6561
val = bwi_led_onoff(sc->sc_blink_led, val, 0);
sys/dev/ic/bwi.c
6562
CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
sys/dev/ic/bwi.c
6721
uint32_t val;
sys/dev/ic/bwi.c
6734
val = CSR_READ_4(sc, BWI_FLAGS);
sys/dev/ic/bwi.c
6740
CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
sys/dev/ic/bwi.c
6750
val = (sc->sc_conf_read)(sc, BWI_PCIR_INTCTL);
sys/dev/ic/bwi.c
6751
val |= mac_mask << 8;
sys/dev/ic/bwi.c
6752
(sc->sc_conf_write)(sc, BWI_PCIR_INTCTL, val);
sys/dev/ic/bwi.c
6848
uint32_t val;
sys/dev/ic/bwi.c
6865
val = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_OUT);
sys/dev/ic/bwi.c
6866
if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
sys/dev/ic/bwi.c
6874
val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
sys/dev/ic/bwi.c
6876
src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
sys/dev/ic/bwi.c
6880
div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
sys/dev/ic/bwi.c
6887
val = CSR_READ_4(sc, BWI_CLOCK_INFO);
sys/dev/ic/bwi.c
6890
div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
sys/dev/ic/bwi.c
8053
uint32_t val, addr_hi, addr_lo;
sys/dev/ic/bwi.c
8069
val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
sys/dev/ic/bwi.c
8072
CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
sys/dev/ic/bwi.c
8074
val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
sys/dev/ic/bwi.c
8076
CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
sys/dev/ic/bwi.c
8085
uint32_t val, addr_hi, addr_lo;
sys/dev/ic/bwi.c
8090
val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
sys/dev/ic/bwi.c
8093
CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
sys/dev/ic/bwi.c
8095
val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
sys/dev/ic/bwi.c
8098
CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
sys/dev/ic/bwi.c
8483
uint32_t val, rx_ctrl;
sys/dev/ic/bwi.c
8488
val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
sys/dev/ic/bwi.c
8489
end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
sys/dev/ic/bwi.c
8557
uint32_t state, val;
sys/dev/ic/bwi.c
8566
val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
sys/dev/ic/bwi.c
8567
state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
sys/dev/ic/bwi.c
8582
val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
sys/dev/ic/bwi.c
8583
state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
sys/dev/ic/bwi.c
9044
uint32_t val, ctrl_base;
sys/dev/ic/bwi.c
9049
val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
sys/dev/ic/bwi.c
9050
end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
sys/dev/ic/bwi.c
9169
uint32_t val;
sys/dev/ic/bwi.c
918
bwi_tmplt_write_4(struct bwi_mac *mac, uint32_t ofs, uint32_t val)
sys/dev/ic/bwi.c
9184
val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
sys/dev/ic/bwi.c
9185
sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
sys/dev/ic/bwi.c
923
val = swap32(val);
sys/dev/ic/bwi.c
9251
uint32_t val, disable_bits;
sys/dev/ic/bwi.c
9254
val = CSR_READ_4(sc, BWI_STATE_LO);
sys/dev/ic/bwi.c
9256
if ((val & (BWI_STATE_LO_CLOCK |
sys/dev/ic/bwi.c
926
CSR_WRITE_4(sc, BWI_MAC_TMPLT_DATA, val);
sys/dev/ic/bwi.c
932
uint64_t val;
sys/dev/ic/bwi.c
934
val = flags & 0xffff;
sys/dev/ic/bwi.c
935
MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_HFLAGS_LO, val);
sys/dev/ic/bwi.c
937
val = (flags >> 16) & 0xffff;
sys/dev/ic/bwi.c
938
MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_HFLAGS_MI, val);
sys/dev/ic/bwi.c
9400
uint32_t val;
sys/dev/ic/bwi.c
9411
n = sizeof(buf) / sizeof(val);
sys/dev/ic/bwi.c
9416
val = 0;
sys/dev/ic/bwi.c
9417
for (j = 0; j < sizeof(val); ++j)
sys/dev/ic/bwi.c
9418
val |= ((uint32_t)(*p++)) << (j * 8);
sys/dev/ic/bwi.c
9420
TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
sys/dev/ic/bwi.c
946
uint64_t flags, val;
sys/dev/ic/bwi.c
951
val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_HFLAGS_MI);
sys/dev/ic/bwi.c
952
flags |= val << 16;
sys/dev/ic/bwi.c
954
val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_HFLAGS_LO);
sys/dev/ic/bwi.c
955
flags |= val;
sys/dev/ic/bwivar.h
633
#define MOBJ_WRITE_2(mac, objid, ofs, val) \
sys/dev/ic/bwivar.h
634
bwi_memobj_write_2((mac), (objid), (ofs), (val))
sys/dev/ic/bwivar.h
635
#define MOBJ_WRITE_4(mac, objid, ofs, val) \
sys/dev/ic/bwivar.h
636
bwi_memobj_write_4((mac), (objid), (ofs), (val))
sys/dev/ic/bwivar.h
653
#define TMPLT_WRITE_4(mac, ofs, val) bwi_tmplt_write_4((mac), (ofs), (val))
sys/dev/ic/bwivar.h
676
#define PHY_WRITE(mac, ctrl, val) bwi_phy_write((mac), (ctrl), (val))
sys/dev/ic/bwivar.h
731
#define RF_WRITE(mac, ofs, val) bwi_rf_write((mac), (ofs), (val))
sys/dev/ic/bwivar.h
79
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/bwivar.h
80
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/ic/bwivar.h
81
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/bwivar.h
82
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/ic/cacvar.h
47
#define cac_outb(sc, port, val) \
sys/dev/ic/cacvar.h
48
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, port, val)
sys/dev/ic/cacvar.h
49
#define cac_outw(sc, port, val) \
sys/dev/ic/cacvar.h
50
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, port, val)
sys/dev/ic/cacvar.h
51
#define cac_outl(sc, port, val) \
sys/dev/ic/cacvar.h
52
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, port, val)
sys/dev/ic/cyreg.h
108
#define cd_write_reg(cy,reg,val) bus_space_write_1(cy->cy_memt, cy->cy_memh, \
sys/dev/ic/cyreg.h
110
(val))
sys/dev/ic/cyreg.h
120
#define cd_write_reg_sc(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
sys/dev/ic/cyreg.h
124
(val))
sys/dev/ic/dcreg.h
778
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/dcreg.h
779
bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
sys/dev/ic/dl10019.c
185
dl10019_mii_bitbang_write(struct device *self, u_int32_t val)
sys/dev/ic/dl10019.c
193
(val & ~DL0_GPIO_PRESERVE) | (gpio & DL0_GPIO_PRESERVE));
sys/dev/ic/dl10019.c
209
dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/dl10019.c
217
mii_bitbang_writereg(self, ops, phy, reg, val);
sys/dev/ic/dp8390var.h
149
#define NIC_PUT(t, h, reg, val) bus_space_write_1(t, h, \
sys/dev/ic/dp8390var.h
150
((sc)->sc_reg_map[reg]), (val))
sys/dev/ic/dwhdmi.c
269
uint8_t block, operation, val;
sys/dev/ic/dwhdmi.c
303
val = dwhdmi_read(sc, HDMI_IH_I2CM_STAT0);
sys/dev/ic/dwhdmi.c
304
if (val & HDMI_IH_I2CM_STAT0_ERROR) {
sys/dev/ic/dwhdmi.c
307
if (val & HDMI_IH_I2CM_STAT0_DONE) {
sys/dev/ic/dwhdmi.c
308
dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, val);
sys/dev/ic/dwhdmi.c
327
uint8_t val;
sys/dev/ic/dwhdmi.c
331
val = bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg);
sys/dev/ic/dwhdmi.c
334
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg * 4) & 0xff;
sys/dev/ic/dwhdmi.c
337
val = 0;
sys/dev/ic/dwhdmi.c
341
return val;
sys/dev/ic/dwhdmi.c
345
dwhdmi_write(struct dwhdmi_softc *sc, bus_size_t reg, uint8_t val)
sys/dev/ic/dwhdmi.c
349
bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, val);
sys/dev/ic/dwhdmi.c
352
bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg * 4, val);
sys/dev/ic/dwhdmi.c
360
uint8_t val;
sys/dev/ic/dwhdmi.c
363
val = HDMI_VP_PR_CD_COLOR_DEPTH_24 << 4 |
sys/dev/ic/dwhdmi.c
365
dwhdmi_write(sc, HDMI_VP_PR_CD, val);
sys/dev/ic/dwhdmi.c
368
val = HDMI_VP_STUFF_IDEFAULT_PHASE |
sys/dev/ic/dwhdmi.c
372
dwhdmi_write(sc, HDMI_VP_STUFF, val);
sys/dev/ic/dwhdmi.c
375
val = HDMI_VP_REMAP_YCC422_SIZE_16 << 0;
sys/dev/ic/dwhdmi.c
376
dwhdmi_write(sc, HDMI_VP_REMAP, val);
sys/dev/ic/dwhdmi.c
379
val = HDMI_VP_CONF_BYPASS_EN |
sys/dev/ic/dwhdmi.c
382
dwhdmi_write(sc, HDMI_VP_CONF, val);
sys/dev/ic/dwhdmi.c
388
uint8_t val;
sys/dev/ic/dwhdmi.c
391
val = HDMI_TX_INVID0_VIDEO_MAPPING_DEFAULT;
sys/dev/ic/dwhdmi.c
392
dwhdmi_write(sc, HDMI_TX_INVID0, val);
sys/dev/ic/dwhdmi.c
395
val = HDMI_TX_INSTUFFING_BCBDATA_STUFFING |
sys/dev/ic/dwhdmi.c
398
dwhdmi_write(sc, HDMI_TX_INSTUFFING, val);
sys/dev/ic/dwhdmi.c
418
uint8_t val;
sys/dev/ic/dwhdmi.c
431
val = HDMI_FC_INVIDCONF_DE_IN_POLARITY;
sys/dev/ic/dwhdmi.c
433
val |= HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY;
sys/dev/ic/dwhdmi.c
435
val |= HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY;
sys/dev/ic/dwhdmi.c
437
val |= HDMI_FC_INVIDCONF_IN_I_P;
sys/dev/ic/dwhdmi.c
439
val |= HDMI_FC_INVIDCONF_DVI_MODE;
sys/dev/ic/dwhdmi.c
441
val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC;
sys/dev/ic/dwhdmi.c
442
dwhdmi_write(sc, HDMI_FC_INVIDCONF, val);
sys/dev/ic/dwhdmi.c
473
uint8_t val;
sys/dev/ic/dwhdmi.c
480
val = HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
sys/dev/ic/dwhdmi.c
484
dwhdmi_write(sc, HDMI_MC_CLKDIS, val);
sys/dev/ic/dwhdmi.c
487
val = 0xff & ~HDMI_MC_SWRSTZREQ_TMDSSWRST_REQ;
sys/dev/ic/dwhdmi.c
488
dwhdmi_write(sc, HDMI_MC_SWRSTZREQ, val);
sys/dev/ic/dwhdmi.c
492
val = dwhdmi_read(sc, HDMI_FC_INVIDCONF);
sys/dev/ic/dwhdmi.c
494
dwhdmi_write(sc, HDMI_FC_INVIDCONF, val);
sys/dev/ic/dwhdmi.c
507
uint8_t val;
sys/dev/ic/dwhdmi.c
536
val = dwhdmi_read(sc, HDMI_AUD_CONF0);
sys/dev/ic/dwhdmi.c
537
val |= HDMI_AUD_CONF0_I2S_SELECT; /* XXX i2s mode */
sys/dev/ic/dwhdmi.c
538
val &= ~HDMI_AUD_CONF0_I2S_IN_EN;
sys/dev/ic/dwhdmi.c
539
val |= (1 << 0); /* XXX 2ch */
sys/dev/ic/dwhdmi.c
540
dwhdmi_write(sc, HDMI_AUD_CONF0, val);
sys/dev/ic/dwhdmi.c
542
val = (16 << 0);
sys/dev/ic/dwhdmi.c
543
dwhdmi_write(sc, HDMI_AUD_CONF1, val);
sys/dev/ic/dwhdmi.c
552
val = dwhdmi_read(sc, HDMI_MC_CLKDIS);
sys/dev/ic/dwhdmi.c
553
val &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
sys/dev/ic/dwhdmi.c
554
dwhdmi_write(sc, HDMI_MC_CLKDIS, val);
sys/dev/ic/dwhdmi.c
854
uint8_t val;
sys/dev/ic/dwhdmi.c
895
val = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmi.c
896
val |= HDMI_PHY_CONF0_ENHPDRXSENSE;
sys/dev/ic/dwhdmi.c
897
dwhdmi_write(sc, HDMI_PHY_CONF0, val);
sys/dev/ic/dwhdmiphy.c
147
uint8_t val;
sys/dev/ic/dwhdmiphy.c
149
val = dwhdmi_read(sc, HDMI_IH_I2CMPHY_STAT0) &
sys/dev/ic/dwhdmiphy.c
151
while (val == 0) {
sys/dev/ic/dwhdmiphy.c
156
val = dwhdmi_read(sc, HDMI_IH_I2CMPHY_STAT0) &
sys/dev/ic/dwhdmiphy.c
256
uint8_t val;
sys/dev/ic/dwhdmiphy.c
258
val = dwhdmi_read(sc, HDMI_PHY_TST0);
sys/dev/ic/dwhdmiphy.c
259
val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
sys/dev/ic/dwhdmiphy.c
260
val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
sys/dev/ic/dwhdmiphy.c
262
dwhdmi_write(sc, HDMI_PHY_TST0, val);
sys/dev/ic/dwhdmiphy.c
270
uint8_t val;
sys/dev/ic/dwhdmiphy.c
340
val = dwhdmi_read(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
sys/dev/ic/dwhdmiphy.c
341
while (val == 0) {
sys/dev/ic/dwhdmiphy.c
348
val = dwhdmi_read(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
sys/dev/ic/dwhdmiphy.c
374
uint8_t val;
sys/dev/ic/dwhdmiphy.c
376
val = dwhdmi_read(sc, HDMI_PHY_STAT0);
sys/dev/ic/dwhdmiphy.c
378
return ((val & HDMI_PHY_STAT0_HPD) != 0) ?
sys/dev/ic/dwiic.c
106
dwiic_write(struct dwiic_softc *sc, int offset, uint32_t val)
sys/dev/ic/dwiic.c
109
val));
sys/dev/ic/dwiic.c
111
bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, val);
sys/dev/ic/dwqe.c
530
dwqe_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/dwqe.c
535
dwqe_write(sc, GMAC_MAC_MDIO_DATA, val);
sys/dev/ic/elink3.c
1642
u_int16_t val;
sys/dev/ic/elink3.c
1645
val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT);
sys/dev/ic/elink3.c
1647
val | bit);
sys/dev/ic/elink3.c
1653
u_int16_t val;
sys/dev/ic/elink3.c
1656
val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT);
sys/dev/ic/elink3.c
1658
val & ~bit);
sys/dev/ic/elink3.c
1706
int val = 0, i, err;
sys/dev/ic/elink3.c
1732
val <<= 1;
sys/dev/ic/elink3.c
1735
val |= 1;
sys/dev/ic/elink3.c
1743
return (err ? 0 : val);
sys/dev/ic/elink3.c
1747
ep_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/elink3.c
1763
ep_mii_sendbits(sc, val, 16);
sys/dev/ic/fxpvar.h
155
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/fxpvar.h
156
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/fxpvar.h
157
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/fxpvar.h
158
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/gem.c
1316
gem_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/gem.c
1327
phy, reg, val);
sys/dev/ic/gem.c
1334
(val & GEM_MIF_FRAME_DATA);
sys/dev/ic/gem.c
1445
gem_pcs_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/gem.c
1455
phy, reg, val);
sys/dev/ic/gem.c
1466
reset = (val & GEM_MII_CONTROL_RESET);
sys/dev/ic/gem.c
1482
bus_space_write_4(t, pcs, reg, val);
sys/dev/ic/hme.c
1020
hme_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/hme.c
1054
(val & HME_MIF_FO_DATA);
sys/dev/ic/i82596.c
900
int n, off, val;
sys/dev/ic/i82596.c
904
val = sc->ie_bus_read16(sc, off);
sys/dev/ic/i82596.c
905
if ((n == sc->rbtail) ^ ((val & IE_RBD_EOL) != 0)) {
sys/dev/ic/i82596.c
918
val = sc->ie_bus_read16(sc, off);
sys/dev/ic/i82596.c
919
if ((n == sc->rftail) ^ ((val & (IE_FD_EOL|IE_FD_SUSP)) != 0)) {
sys/dev/ic/ibm561.c
472
ibm561_regcont10bit(struct ibm561data *data, u_int16_t reg, u_int16_t val)
sys/dev/ic/ibm561.c
474
data->ramdac_wr(data->cookie, IBM561_CMD_GAMMA, (val >> 2) & 0xff);
sys/dev/ic/ibm561.c
475
data->ramdac_wr(data->cookie, IBM561_CMD_GAMMA, (val & 0x3) << 6);
sys/dev/ic/ibm561.c
486
ibm561_regcont(struct ibm561data *data, u_int16_t reg, u_int8_t val)
sys/dev/ic/ibm561.c
488
data->ramdac_wr(data->cookie, reg, val);
sys/dev/ic/ibm561.c
492
ibm561_regwr(struct ibm561data *data, u_int16_t reg, u_int8_t val)
sys/dev/ic/ibm561.c
495
ibm561_regcont(data, IBM561_CMD, val);
sys/dev/ic/if_wi.c
1135
u_int16_t val = 0;
sys/dev/ic/if_wi.c
1170
val = PRIVACY_INVOKED;
sys/dev/ic/if_wi.c
1181
val |= EXCLUDE_UNENCRYPTED;
sys/dev/ic/if_wi.c
1190
val |= HOST_ENCRYPT;
sys/dev/ic/if_wi.c
1193
val |= HOST_ENCRYPT|HOST_DECRYPT;
sys/dev/ic/if_wi.c
1196
p2ltv.wi_val = htole16(val);
sys/dev/ic/if_wireg.h
343
#define WI_SETVAL(recno, val) \
sys/dev/ic/if_wireg.h
349
g.wi_val = htole16(val); \
sys/dev/ic/if_wireg.h
84
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/if_wireg.h
86
(sc->sc_pci ? reg * 2: reg), (val))
sys/dev/ic/if_wireg.h
87
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/if_wireg.h
89
(sc->sc_pci ? reg * 2: reg), (val))
sys/dev/ic/if_wireg.h
90
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/ic/if_wireg.h
92
(sc->sc_pci ? reg * 2: reg), val)
sys/dev/ic/imxiic.c
125
sc->frequency = sc->sc_clk_div[i].val;
sys/dev/ic/imxiic.c
305
imxiic_write_1(struct imxiic_softc *sc, int reg, uint8_t val)
sys/dev/ic/imxiic.c
309
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/ic/imxiic.c
64
#define HWRITE1(sc, reg, val) \
sys/dev/ic/imxiic.c
65
imxiic_write_1((sc), (reg), (val))
sys/dev/ic/imxiicvar.h
61
uint16_t val;
sys/dev/ic/ispi.c
164
uint32_t val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/ic/ispi.c
166
val));
sys/dev/ic/ispi.c
167
return val;
sys/dev/ic/ispi.c
171
ispi_write(struct ispi_softc *sc, int reg, uint32_t val)
sys/dev/ic/ispi.c
174
val));
sys/dev/ic/ispi.c
175
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/ic/ispi.c
185
ispi_lpss_write(struct ispi_softc *sc, int reg, uint32_t val)
sys/dev/ic/ispi.c
187
ispi_write(sc, sc->sc_lpss_reg_offset + reg, val);
sys/dev/ic/ispivar.h
81
void ispi_write(struct ispi_softc *sc, int reg, uint32_t val);
sys/dev/ic/mtd8xx.c
278
mtd_miibus_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/mtd8xx.c
284
CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val);
sys/dev/ic/mtd8xx.c
291
if (mask & (u_int32_t)val)
sys/dev/ic/mtd8xxreg.h
201
#define CSR_WRITE_1(reg, val) \
sys/dev/ic/mtd8xxreg.h
202
bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val)
sys/dev/ic/mtd8xxreg.h
206
bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val)
sys/dev/ic/mtd8xxreg.h
209
#define CSR_WRITE_4(reg, val) \
sys/dev/ic/mtd8xxreg.h
210
bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val)
sys/dev/ic/mtd8xxreg.h
212
#define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
sys/dev/ic/mtd8xxreg.h
213
#define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
sys/dev/ic/mtwreg.h
880
uint32_t val;
sys/dev/ic/ncr53c9xvar.h
388
#define NCR_WRITE_REG(sc, reg, val) \
sys/dev/ic/ncr53c9xvar.h
389
(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
sys/dev/ic/osiopvar.h
66
#define osiop_write_1(sc, reg, val) \
sys/dev/ic/osiopvar.h
67
bus_space_write_1((sc)->sc_bst, (sc)->sc_reg, reg, val)
sys/dev/ic/osiopvar.h
71
#define osiop_write_4(sc, reg, val) \
sys/dev/ic/osiopvar.h
72
bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)
sys/dev/ic/pcdisplay_subr.c
229
u_int16_t val;
sys/dev/ic/pcdisplay_subr.c
234
val = (fillattr << 8) | ' ';
sys/dev/ic/pcdisplay_subr.c
239
val, ncols);
sys/dev/ic/pcdisplay_subr.c
242
scr->mem[off + i] = val;
sys/dev/ic/pcdisplay_subr.c
282
u_int16_t val;
sys/dev/ic/pcdisplay_subr.c
287
val = (fillattr << 8) | ' ';
sys/dev/ic/pcdisplay_subr.c
292
val, count);
sys/dev/ic/pcdisplay_subr.c
295
scr->mem[off + n] = val;
sys/dev/ic/pcdisplayvar.h
65
_pcdisplay_6845_write(struct pcdisplay_handle *ph, int reg, u_int8_t val)
sys/dev/ic/pcdisplayvar.h
68
bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_DATA, val);
sys/dev/ic/pcdisplayvar.h
73
#define pcdisplay_6845_write(ph, reg, val) \
sys/dev/ic/pcdisplayvar.h
74
_pcdisplay_6845_write(ph, offsetof(struct reg_mc6845, reg), val)
sys/dev/ic/pckbc.c
132
pckbc_send_cmd(bus_space_tag_t iot, bus_space_handle_t ioh_c, u_char val)
sys/dev/ic/pckbc.c
136
bus_space_write_1(iot, ioh_c, 0, val);
sys/dev/ic/pckbc.c
216
pckbc_send_devcmd(struct pckbc_internal *t, pckbc_slot_t slot, u_char val)
sys/dev/ic/pckbc.c
228
bus_space_write_1(iot, ioh_d, 0, val);
sys/dev/ic/qcuart.c
64
#define HWRITE4(sc, reg, val) \
sys/dev/ic/qcuart.c
65
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/ic/qla.c
2407
u_int16_t req, cmd, val;
sys/dev/ic/qla.c
2441
val = 0;
sys/dev/ic/qla.c
2443
val <<= 1;
sys/dev/ic/qla.c
2448
val |= 1;
sys/dev/ic/qla.c
2460
data[i] = letoh16(val);
sys/dev/ic/qlw.c
1447
u_int16_t req, cmd, val;
sys/dev/ic/qlw.c
1492
val = 0;
sys/dev/ic/qlw.c
1494
val <<= 1;
sys/dev/ic/qlw.c
1499
val |= 1;
sys/dev/ic/qlw.c
1511
data[i] = letoh16(val);
sys/dev/ic/qwx.c
1331
uint32_t val;
sys/dev/ic/qwx.c
1342
val = sc->ops.read32(sc, reo_base + HAL_REO1_GEN_ENABLE);
sys/dev/ic/qwx.c
1344
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
sys/dev/ic/qwx.c
1345
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
sys/dev/ic/qwx.c
1349
sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val);
sys/dev/ic/qwx.c
1434
uint32_t val;
sys/dev/ic/qwx.c
1445
val = sc->ops.read32(sc, reo_base + HAL_REO1_GEN_ENABLE);
sys/dev/ic/qwx.c
1446
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
sys/dev/ic/qwx.c
1448
sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val);
sys/dev/ic/qwx.c
1450
val = sc->ops.read32(sc, reo_base + HAL_REO1_MISC_CTL(sc));
sys/dev/ic/qwx.c
1451
val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
sys/dev/ic/qwx.c
1452
val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING,
sys/dev/ic/qwx.c
1454
sc->ops.write32(sc, reo_base + HAL_REO1_MISC_CTL(sc), val);
sys/dev/ic/qwx.c
1475
uint32_t val;
sys/dev/ic/qwx.c
1487
val = sc->ops.read32(sc, reo_base + HAL_REO1_GEN_ENABLE);
sys/dev/ic/qwx.c
1489
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
sys/dev/ic/qwx.c
1490
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
sys/dev/ic/qwx.c
1494
sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val);
sys/dev/ic/qwx.c
21594
uint32_t val;
sys/dev/ic/qwx.c
21605
val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR,
sys/dev/ic/qwx.c
21609
reg_base + HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc), val);
sys/dev/ic/qwx.c
21618
val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
sys/dev/ic/qwx.c
21623
reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(sc), val);
sys/dev/ic/qwx.c
21625
val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) |
sys/dev/ic/qwx.c
21627
sc->ops.write32(sc, reg_base + HAL_REO1_RING_ID_OFFSET(sc), val);
sys/dev/ic/qwx.c
21630
val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD,
sys/dev/ic/qwx.c
21633
val |= FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD,
sys/dev/ic/qwx.c
21637
reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc), val);
sys/dev/ic/qwx.c
21653
val = 0;
sys/dev/ic/qwx.c
21655
val |= HAL_REO1_RING_MISC_DATA_TLV_SWAP;
sys/dev/ic/qwx.c
21657
val |= HAL_REO1_RING_MISC_HOST_FW_SWAP;
sys/dev/ic/qwx.c
21659
val |= HAL_REO1_RING_MISC_MSI_SWAP;
sys/dev/ic/qwx.c
21660
val |= HAL_REO1_RING_MISC_SRNG_ENABLE;
sys/dev/ic/qwx.c
21662
sc->ops.write32(sc, reg_base + HAL_REO1_RING_MISC_OFFSET(sc), val);
sys/dev/ic/qwx.c
21669
uint32_t val;
sys/dev/ic/qwx.c
21680
val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR,
sys/dev/ic/qwx.c
21685
val);
sys/dev/ic/qwx.c
21694
val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
sys/dev/ic/qwx.c
21698
sc->ops.write32(sc, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(sc), val);
sys/dev/ic/qwx.c
21700
val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
sys/dev/ic/qwx.c
21701
sc->ops.write32(sc, reg_base + HAL_TCL1_RING_ID_OFFSET(sc), val);
sys/dev/ic/qwx.c
21705
val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
sys/dev/ic/qwx.c
21711
reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(sc), val);
sys/dev/ic/qwx.c
21718
val = FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD,
sys/dev/ic/qwx.c
21721
val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD,
sys/dev/ic/qwx.c
21725
reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc), val);
sys/dev/ic/qwx.c
21727
val = 0;
sys/dev/ic/qwx.c
21729
val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD,
sys/dev/ic/qwx.c
21733
reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc), val);
sys/dev/ic/qwx.c
21754
val = 0;
sys/dev/ic/qwx.c
21756
val |= HAL_TCL1_RING_MISC_DATA_TLV_SWAP;
sys/dev/ic/qwx.c
21758
val |= HAL_TCL1_RING_MISC_HOST_FW_SWAP;
sys/dev/ic/qwx.c
21760
val |= HAL_TCL1_RING_MISC_MSI_SWAP;
sys/dev/ic/qwx.c
21763
val |= HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE;
sys/dev/ic/qwx.c
21765
val |= HAL_TCL1_RING_MISC_SRNG_ENABLE;
sys/dev/ic/qwx.c
21767
sc->ops.write32(sc, reg_base + HAL_TCL1_RING_MISC_OFFSET(sc), val);
sys/dev/ic/qwx.c
21784
uint32_t val;
sys/dev/ic/qwx.c
21790
val = sc->ops.read32(sc, addr);
sys/dev/ic/qwx.c
21791
val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN;
sys/dev/ic/qwx.c
21792
val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN,
sys/dev/ic/qwx.c
21794
sc->ops.write32(sc, addr, val);
sys/dev/ic/qwx.c
27049
uint32_t val;
sys/dev/ic/qwx.c
27056
val = WMI_PEER_SMPS_STATIC;
sys/dev/ic/qwx.c
27059
val = WMI_PEER_SMPS_DYNAMIC;
sys/dev/ic/qwx.c
27063
val = WMI_PEER_SMPS_PS_NONE;
sys/dev/ic/qwx.c
27068
pdev_id, WMI_PEER_MIMO_PS_STATE, val);
sys/dev/ic/qwx.c
7912
uint16_t val;
sys/dev/ic/qwx.c
7914
if (ei->elem_size != sizeof(val)) {
sys/dev/ic/qwx.c
7922
memcpy(&val, input + ei->offset + (i * ei->elem_size), ei->elem_size);
sys/dev/ic/qwx.c
7923
val = htole16(val);
sys/dev/ic/qwx.c
7924
memcpy(p, &val, sizeof(val));
sys/dev/ic/qwx.c
7932
uint32_t val;
sys/dev/ic/qwx.c
7934
if (ei->elem_size != sizeof(val)) {
sys/dev/ic/qwx.c
7942
memcpy(&val, input + ei->offset + (i * ei->elem_size), ei->elem_size);
sys/dev/ic/qwx.c
7943
val = htole32(val);
sys/dev/ic/qwx.c
7944
memcpy(p, &val, sizeof(val));
sys/dev/ic/qwx.c
7952
uint64_t val;
sys/dev/ic/qwx.c
7954
if (ei->elem_size != sizeof(val)) {
sys/dev/ic/qwx.c
7962
memcpy(&val, input + ei->offset + (i * ei->elem_size), ei->elem_size);
sys/dev/ic/qwx.c
7963
val = htole64(val);
sys/dev/ic/qwx.c
7964
memcpy(p, &val, sizeof(val));
sys/dev/ic/qwxreg.h
7963
#define HAL_RX_MSDU_PKT_LENGTH_GET(val) \
sys/dev/ic/qwxreg.h
7964
(FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val)))
sys/dev/ic/qwz.c
1053
uint32_t val;
sys/dev/ic/qwz.c
1055
val = sc->ops.read32(sc, reo_base + HAL_REO1_GEN_ENABLE);
sys/dev/ic/qwz.c
1056
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
sys/dev/ic/qwz.c
1058
sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val);
sys/dev/ic/qwz.c
1060
val = sc->ops.read32(sc, reo_base + HAL_REO1_MISC_CTRL_ADDR(sc));
sys/dev/ic/qwz.c
1061
val &= ~HAL_REO1_MISC_CTL_FRAG_DST_RING;
sys/dev/ic/qwz.c
1062
val &= ~HAL_REO1_MISC_CTL_BAR_DST_RING;
sys/dev/ic/qwz.c
1063
val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAG_DST_RING,
sys/dev/ic/qwz.c
1065
val |= FIELD_PREP(HAL_REO1_MISC_CTL_BAR_DST_RING,
sys/dev/ic/qwz.c
1067
sc->ops.write32(sc, reo_base + HAL_REO1_MISC_CTRL_ADDR(sc), val);
sys/dev/ic/qwz.c
19500
uint32_t val;
sys/dev/ic/qwz.c
19511
val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR,
sys/dev/ic/qwz.c
19515
reg_base + HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc), val);
sys/dev/ic/qwz.c
19524
val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
sys/dev/ic/qwz.c
19529
reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(sc), val);
sys/dev/ic/qwz.c
19531
val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) |
sys/dev/ic/qwz.c
19533
sc->ops.write32(sc, reg_base + HAL_REO1_RING_ID_OFFSET(sc), val);
sys/dev/ic/qwz.c
19536
val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD,
sys/dev/ic/qwz.c
19539
val |= FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD,
sys/dev/ic/qwz.c
19543
reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc), val);
sys/dev/ic/qwz.c
19559
val = 0;
sys/dev/ic/qwz.c
19561
val |= HAL_REO1_RING_MISC_DATA_TLV_SWAP;
sys/dev/ic/qwz.c
19563
val |= HAL_REO1_RING_MISC_HOST_FW_SWAP;
sys/dev/ic/qwz.c
19565
val |= HAL_REO1_RING_MISC_MSI_SWAP;
sys/dev/ic/qwz.c
19566
val |= HAL_REO1_RING_MISC_SRNG_ENABLE;
sys/dev/ic/qwz.c
19568
sc->ops.write32(sc, reg_base + HAL_REO1_RING_MISC_OFFSET(sc), val);
sys/dev/ic/qwz.c
19575
uint32_t val;
sys/dev/ic/qwz.c
19586
val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR,
sys/dev/ic/qwz.c
19591
val);
sys/dev/ic/qwz.c
19600
val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
sys/dev/ic/qwz.c
19604
sc->ops.write32(sc, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET, val);
sys/dev/ic/qwz.c
19606
val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
sys/dev/ic/qwz.c
19607
sc->ops.write32(sc, reg_base + HAL_TCL1_RING_ID_OFFSET(sc), val);
sys/dev/ic/qwz.c
19613
val = FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD,
sys/dev/ic/qwz.c
19616
val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD,
sys/dev/ic/qwz.c
19620
reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc), val);
sys/dev/ic/qwz.c
19622
val = 0;
sys/dev/ic/qwz.c
19624
val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD,
sys/dev/ic/qwz.c
19628
reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc), val);
sys/dev/ic/qwz.c
19649
val = 0;
sys/dev/ic/qwz.c
19651
val |= HAL_TCL1_RING_MISC_DATA_TLV_SWAP;
sys/dev/ic/qwz.c
19653
val |= HAL_TCL1_RING_MISC_HOST_FW_SWAP;
sys/dev/ic/qwz.c
19655
val |= HAL_TCL1_RING_MISC_MSI_SWAP;
sys/dev/ic/qwz.c
19658
val |= HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE;
sys/dev/ic/qwz.c
19660
val |= HAL_TCL1_RING_MISC_SRNG_ENABLE;
sys/dev/ic/qwz.c
19663
val |= HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE;
sys/dev/ic/qwz.c
19665
sc->ops.write32(sc, reg_base + HAL_TCL1_RING_MISC_OFFSET(sc), val);
sys/dev/ic/qwz.c
19682
uint32_t val;
sys/dev/ic/qwz.c
19688
val = sc->ops.read32(sc, addr);
sys/dev/ic/qwz.c
19689
val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN;
sys/dev/ic/qwz.c
19690
val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN,
sys/dev/ic/qwz.c
19692
sc->ops.write32(sc, addr, val);
sys/dev/ic/qwz.c
5430
uint16_t val;
sys/dev/ic/qwz.c
5432
if (ei->elem_size != sizeof(val)) {
sys/dev/ic/qwz.c
5440
memcpy(&val, input + ei->offset + (i * ei->elem_size), ei->elem_size);
sys/dev/ic/qwz.c
5441
val = htole16(val);
sys/dev/ic/qwz.c
5442
memcpy(p, &val, sizeof(val));
sys/dev/ic/qwz.c
5450
uint32_t val;
sys/dev/ic/qwz.c
5452
if (ei->elem_size != sizeof(val)) {
sys/dev/ic/qwz.c
5460
memcpy(&val, input + ei->offset + (i * ei->elem_size), ei->elem_size);
sys/dev/ic/qwz.c
5461
val = htole32(val);
sys/dev/ic/qwz.c
5462
memcpy(p, &val, sizeof(val));
sys/dev/ic/qwz.c
5470
uint64_t val;
sys/dev/ic/qwz.c
5472
if (ei->elem_size != sizeof(val)) {
sys/dev/ic/qwz.c
5480
memcpy(&val, input + ei->offset + (i * ei->elem_size), ei->elem_size);
sys/dev/ic/qwz.c
5481
val = htole64(val);
sys/dev/ic/qwz.c
5482
memcpy(p, &val, sizeof(val));
sys/dev/ic/qwz.c
7393
uint32_t val;
sys/dev/ic/qwz.c
7457
val = HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE;
sys/dev/ic/qwz.c
7458
val |= HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE;
sys/dev/ic/qwz.c
7461
val);
sys/dev/ic/qwz.c
8312
uint32_t val = 0;
sys/dev/ic/qwz.c
8316
val |= FIELD_PREP(HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB, ATH12K_CMEM_ADDR_MSB) |
sys/dev/ic/qwz.c
8323
sc->ops.write32(sc, reo_base + HAL_REO1_SW_COOKIE_CFG1(sc), val);
sys/dev/ic/qwz.c
8328
val = FIELD_PREP(HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB, ATH12K_CMEM_ADDR_MSB) |
sys/dev/ic/qwz.c
8333
sc->ops.write32(sc, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
sys/dev/ic/qwz.c
8336
val = sc->ops.read32(sc, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
sys/dev/ic/qwz.c
8337
val |= FIELD_PREP(HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN, 1) |
sys/dev/ic/qwz.c
8341
sc->ops.write32(sc, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
sys/dev/ic/qwz.c
8344
val = sc->ops.read32(sc, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
sys/dev/ic/qwz.c
8345
val |= FIELD_PREP(HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN, 1) |
sys/dev/ic/qwz.c
8348
sc->ops.write32(sc, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
sys/dev/ic/qwzreg.h
8280
#define HAL_RX_MSDU_PKT_LENGTH_GET(val) \
sys/dev/ic/qwzreg.h
8281
(FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val)))
sys/dev/ic/r92creg.h
1102
#define MS(val, field) \
sys/dev/ic/r92creg.h
1103
(((val) & field##_M) >> field##_S)
sys/dev/ic/r92creg.h
1106
#define SM(field, val) \
sys/dev/ic/r92creg.h
1107
(((val) << field##_S) & field##_M)
sys/dev/ic/r92creg.h
1110
#define RW(var, field, val) \
sys/dev/ic/r92creg.h
1111
(((var) & ~field##_M) | SM(field, val))
sys/dev/ic/r92creg.h
1813
uint8_t val;
sys/dev/ic/re.c
2374
u_int8_t val;
sys/dev/ic/re.c
2394
val = CSR_READ_1(sc, sc->rl_cfg5);
sys/dev/ic/re.c
2395
val &= ~(RL_CFG5_WOL_UCAST | RL_CFG5_WOL_MCAST |
sys/dev/ic/re.c
2397
CSR_WRITE_1(sc, sc->rl_cfg5, val);
sys/dev/ic/re.c
2399
val = CSR_READ_1(sc, sc->rl_cfg3);
sys/dev/ic/re.c
2400
val |= RL_CFG3_WOL_MAGIC;
sys/dev/ic/re.c
2401
val &= ~RL_CFG3_WOL_LINK;
sys/dev/ic/re.c
2402
CSR_WRITE_1(sc, sc->rl_cfg3, val);
sys/dev/ic/re.c
2404
val = CSR_READ_1(sc, sc->rl_cfg5);
sys/dev/ic/re.c
2405
val &= ~(RL_CFG5_WOL_UCAST | RL_CFG5_WOL_MCAST |
sys/dev/ic/re.c
2407
CSR_WRITE_1(sc, sc->rl_cfg5, val);
sys/dev/ic/re.c
2409
val = CSR_READ_1(sc, sc->rl_cfg3);
sys/dev/ic/re.c
2410
val &= ~(RL_CFG3_WOL_MAGIC | RL_CFG3_WOL_LINK);
sys/dev/ic/re.c
2411
CSR_WRITE_1(sc, sc->rl_cfg3, val);
sys/dev/ic/rt2560.c
145
uint32_t val;
sys/dev/ic/rt2560.c
152
uint8_t val;
sys/dev/ic/rt2560.c
2051
rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2560.c
2066
tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
sys/dev/ic/rt2560.c
2069
DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
sys/dev/ic/rt2560.c
2075
uint32_t val;
sys/dev/ic/rt2560.c
2088
val = RT2560_BBP_BUSY | reg << 8;
sys/dev/ic/rt2560.c
2089
RAL_WRITE(sc, RT2560_BBPCSR, val);
sys/dev/ic/rt2560.c
2092
val = RAL_READ(sc, RT2560_BBPCSR);
sys/dev/ic/rt2560.c
2093
if (!(val & RT2560_BBP_BUSY))
sys/dev/ic/rt2560.c
2094
return val & 0xff;
sys/dev/ic/rt2560.c
2103
rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
sys/dev/ic/rt2560.c
2118
tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
sys/dev/ic/rt2560.c
2123
sc->rf_regs[reg] = val;
sys/dev/ic/rt2560.c
2125
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
sys/dev/ic/rt2560.c
2505
uint16_t val;
sys/dev/ic/rt2560.c
2508
val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0);
sys/dev/ic/rt2560.c
2509
sc->rf_rev = (val >> 11) & 0x1f;
sys/dev/ic/rt2560.c
2510
sc->hw_radio = (val >> 10) & 0x1;
sys/dev/ic/rt2560.c
2511
sc->led_mode = (val >> 6) & 0x7;
sys/dev/ic/rt2560.c
2512
sc->rx_ant = (val >> 4) & 0x3;
sys/dev/ic/rt2560.c
2513
sc->tx_ant = (val >> 2) & 0x3;
sys/dev/ic/rt2560.c
2514
sc->nb_ant = val & 0x3;
sys/dev/ic/rt2560.c
2518
val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i);
sys/dev/ic/rt2560.c
2519
sc->bbp_prom[i].reg = val >> 8;
sys/dev/ic/rt2560.c
2520
sc->bbp_prom[i].val = val & 0xff;
sys/dev/ic/rt2560.c
2525
val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i);
sys/dev/ic/rt2560.c
2526
sc->txpow[i * 2] = val >> 8;
sys/dev/ic/rt2560.c
2527
sc->txpow[i * 2 + 1] = val & 0xff;
sys/dev/ic/rt2560.c
2550
rt2560_def_bbp[i].val);
sys/dev/ic/rt2560.c
2557
rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/ic/rt2560.c
2605
RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
sys/dev/ic/rt2560.c
819
uint16_t val;
sys/dev/ic/rt2560.c
851
val = 0;
sys/dev/ic/rt2560.c
855
val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
sys/dev/ic/rt2560.c
866
return val;
sys/dev/ic/rt2560reg.h
306
#define RAL_WRITE(sc, reg, val) \
sys/dev/ic/rt2560reg.h
307
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/rt2560reg.h
312
#define RT2560_EEPROM_CTL(sc, val) do { \
sys/dev/ic/rt2560reg.h
313
RAL_WRITE((sc), RT2560_CSR21, (val)); \
sys/dev/ic/rt2560var.h
138
uint8_t val;
sys/dev/ic/rt2661.c
1024
val = 0;
sys/dev/ic/rt2661.c
1028
val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
sys/dev/ic/rt2661.c
1039
return val;
sys/dev/ic/rt2661.c
1054
const uint32_t val = RAL_READ(sc, RT2661_STA_CSR4);
sys/dev/ic/rt2661.c
1055
if (!(val & RT2661_TX_STAT_VALID))
sys/dev/ic/rt2661.c
1059
amrr_id = RT2661_TX_PRIV_DATA(val);
sys/dev/ic/rt2661.c
1062
switch (RT2661_TX_RESULT(val)) {
sys/dev/ic/rt2661.c
1064
retrycnt = RT2661_TX_RETRYCNT(val);
sys/dev/ic/rt2661.c
1088
sc->sc_dev.dv_xname, val);
sys/dev/ic/rt2661.c
167
uint32_t val;
sys/dev/ic/rt2661.c
174
uint8_t val;
sys/dev/ic/rt2661.c
193
uint32_t val;
sys/dev/ic/rt2661.c
2045
rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2661.c
2060
tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/ic/rt2661.c
2063
DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
sys/dev/ic/rt2661.c
2069
uint32_t val;
sys/dev/ic/rt2661.c
207
if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
sys/dev/ic/rt2661.c
2082
val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
sys/dev/ic/rt2661.c
2083
RAL_WRITE(sc, RT2661_PHY_CSR3, val);
sys/dev/ic/rt2661.c
2086
val = RAL_READ(sc, RT2661_PHY_CSR3);
sys/dev/ic/rt2661.c
2087
if (!(val & RT2661_BBP_BUSY))
sys/dev/ic/rt2661.c
2088
return val & 0xff;
sys/dev/ic/rt2661.c
2097
rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
sys/dev/ic/rt2661.c
2112
tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
sys/dev/ic/rt2661.c
2117
sc->rf_regs[reg] = val;
sys/dev/ic/rt2661.c
2119
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));
sys/dev/ic/rt2661.c
221
printf("%s: MAC/BBP RT%X, RF %s\n", sc->sc_dev.dv_xname, val,
sys/dev/ic/rt2661.c
2428
uint16_t val;
sys/dev/ic/rt2661.c
2432
val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
sys/dev/ic/rt2661.c
2433
ic->ic_myaddr[0] = val & 0xff;
sys/dev/ic/rt2661.c
2434
ic->ic_myaddr[1] = val >> 8;
sys/dev/ic/rt2661.c
2436
val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
sys/dev/ic/rt2661.c
2437
ic->ic_myaddr[2] = val & 0xff;
sys/dev/ic/rt2661.c
2438
ic->ic_myaddr[3] = val >> 8;
sys/dev/ic/rt2661.c
2440
val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
sys/dev/ic/rt2661.c
2441
ic->ic_myaddr[4] = val & 0xff;
sys/dev/ic/rt2661.c
2442
ic->ic_myaddr[5] = val >> 8;
sys/dev/ic/rt2661.c
2444
val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
sys/dev/ic/rt2661.c
2446
sc->rf_rev = (val >> 11) & 0x1f;
sys/dev/ic/rt2661.c
2447
sc->hw_radio = (val >> 10) & 0x1;
sys/dev/ic/rt2661.c
2448
sc->rx_ant = (val >> 4) & 0x3;
sys/dev/ic/rt2661.c
2449
sc->tx_ant = (val >> 2) & 0x3;
sys/dev/ic/rt2661.c
2450
sc->nb_ant = val & 0x3;
sys/dev/ic/rt2661.c
2454
val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
sys/dev/ic/rt2661.c
2455
sc->ext_5ghz_lna = (val >> 6) & 0x1;
sys/dev/ic/rt2661.c
2456
sc->ext_2ghz_lna = (val >> 4) & 0x1;
sys/dev/ic/rt2661.c
2461
val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
sys/dev/ic/rt2661.c
2462
if ((val & 0xff) != 0xff)
sys/dev/ic/rt2661.c
2463
sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
sys/dev/ic/rt2661.c
2465
val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
sys/dev/ic/rt2661.c
2466
if ((val & 0xff) != 0xff)
sys/dev/ic/rt2661.c
2467
sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
sys/dev/ic/rt2661.c
2478
val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
sys/dev/ic/rt2661.c
2479
if ((val >> 8) != 0xff)
sys/dev/ic/rt2661.c
2480
sc->rfprog = (val >> 8) & 0x3;
sys/dev/ic/rt2661.c
2481
if ((val & 0xff) != 0xff)
sys/dev/ic/rt2661.c
2482
sc->rffreq = val & 0xff;
sys/dev/ic/rt2661.c
2488
val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
sys/dev/ic/rt2661.c
2489
sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
sys/dev/ic/rt2661.c
2492
sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
sys/dev/ic/rt2661.c
2499
val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
sys/dev/ic/rt2661.c
2500
if (val == 0 || val == 0xffff)
sys/dev/ic/rt2661.c
2502
sc->bbp_prom[i].reg = val >> 8;
sys/dev/ic/rt2661.c
2503
sc->bbp_prom[i].val = val & 0xff;
sys/dev/ic/rt2661.c
2505
sc->bbp_prom[i].val));
sys/dev/ic/rt2661.c
2516
const uint8_t val = rt2661_bbp_read(sc, 0);
sys/dev/ic/rt2661.c
2517
if (val != 0 && val != 0xff)
sys/dev/ic/rt2661.c
2529
rt2661_def_bbp[i].val);
sys/dev/ic/rt2661.c
2536
rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/ic/rt2661.c
2613
RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
sys/dev/ic/rt2661.c
992
uint16_t val;
sys/dev/ic/rt2661reg.h
345
RAL_WRITE(struct rt2661_softc *sc, bus_size_t reg, uint32_t val)
sys/dev/ic/rt2661reg.h
348
bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
sys/dev/ic/rt2661reg.h
352
RAL_WRITE_1(struct rt2661_softc *sc, bus_size_t reg, uint8_t val)
sys/dev/ic/rt2661reg.h
355
bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val);
sys/dev/ic/rt2661reg.h
374
#define RT2661_EEPROM_CTL(sc, val) do { \
sys/dev/ic/rt2661reg.h
375
RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \
sys/dev/ic/rt2661var.h
148
uint8_t val;
sys/dev/ic/rt2860.c
1092
uint16_t val;
sys/dev/ic/rt2860.c
1124
val = 0;
sys/dev/ic/rt2860.c
1128
val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
sys/dev/ic/rt2860.c
1139
return val;
sys/dev/ic/rt2860.c
168
uint32_t val;
sys/dev/ic/rt2860.c
175
uint8_t val;
sys/dev/ic/rt2860.c
1882
rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2860.c
1898
RT2860_BBP_CSR_KICK | reg << 8 | val);
sys/dev/ic/rt2860.c
1908
uint32_t val;
sys/dev/ic/rt2860.c
1930
val = RAL_READ(sc, RT2860_H2M_BBPAGENT);
sys/dev/ic/rt2860.c
1931
if (!(val & RT2860_BBP_CSR_KICK))
sys/dev/ic/rt2860.c
1932
return val & 0xff;
sys/dev/ic/rt2860.c
1945
rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
sys/dev/ic/rt2860.c
1962
(val & 0x3fffff) << 2 | (reg & 3);
sys/dev/ic/rt2860.c
199
uint8_t val;
sys/dev/ic/rt2860.c
2000
rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2860.c
2015
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/ic/rt2860.c
2484
rt3572_def_rf[i].val);
sys/dev/ic/rt2860.c
2489
rt3090_def_rf[i].val);
sys/dev/ic/rt2860.c
2586
rt5392_def_rf[i].val);
sys/dev/ic/rt2860.c
2591
rt3290_def_rf[i].val);
sys/dev/ic/rt2860.c
2596
rt5390_def_rf[i].val);
sys/dev/ic/rt2860.c
2754
uint8_t *val)
sys/dev/ic/rt2860.c
2803
*val = rf24;
sys/dev/ic/rt2860.c
2844
rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
sys/dev/ic/rt2860.c
3036
uint32_t val = arc4random();
sys/dev/ic/rt2860.c
3038
if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
sys/dev/ic/rt2860.c
3039
val += 0x000100;
sys/dev/ic/rt2860.c
3040
iv[0] = val;
sys/dev/ic/rt2860.c
3041
iv[1] = val >> 8;
sys/dev/ic/rt2860.c
3042
iv[2] = val >> 16;
sys/dev/ic/rt2860.c
3178
uint16_t val;
sys/dev/ic/rt2860.c
3196
val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION);
sys/dev/ic/rt2860.c
3197
DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
sys/dev/ic/rt2860.c
3200
val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01);
sys/dev/ic/rt2860.c
3201
ic->ic_myaddr[0] = val & 0xff;
sys/dev/ic/rt2860.c
3202
ic->ic_myaddr[1] = val >> 8;
sys/dev/ic/rt2860.c
3203
val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23);
sys/dev/ic/rt2860.c
3204
ic->ic_myaddr[2] = val & 0xff;
sys/dev/ic/rt2860.c
3205
ic->ic_myaddr[3] = val >> 8;
sys/dev/ic/rt2860.c
3206
val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45);
sys/dev/ic/rt2860.c
3207
ic->ic_myaddr[4] = val & 0xff;
sys/dev/ic/rt2860.c
3208
ic->ic_myaddr[5] = val >> 8;
sys/dev/ic/rt2860.c
3211
val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY);
sys/dev/ic/rt2860.c
3212
DPRINTF(("EEPROM region code=0x%04x\n", val));
sys/dev/ic/rt2860.c
3216
val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i);
sys/dev/ic/rt2860.c
3217
sc->bbp[i].val = val & 0xff;
sys/dev/ic/rt2860.c
3218
sc->bbp[i].reg = val >> 8;
sys/dev/ic/rt2860.c
3219
DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
sys/dev/ic/rt2860.c
3224
val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i);
sys/dev/ic/rt2860.c
3225
sc->rf[i].val = val & 0xff;
sys/dev/ic/rt2860.c
3226
sc->rf[i].reg = val >> 8;
sys/dev/ic/rt2860.c
3228
sc->rf[i].val));
sys/dev/ic/rt2860.c
3233
val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS);
sys/dev/ic/rt2860.c
3234
sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
sys/dev/ic/rt2860.c
3236
if ((val >> 8) != 0xff) {
sys/dev/ic/rt2860.c
3238
sc->leds = val >> 8;
sys/dev/ic/rt2860.c
3253
val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA);
sys/dev/ic/rt2860.c
3254
DPRINTF(("EEPROM ANT 0x%04x\n", val));
sys/dev/ic/rt2860.c
3258
sc->rf_rev = (val >> 8) & 0xf;
sys/dev/ic/rt2860.c
3259
sc->ntxchains = (val >> 4) & 0xf;
sys/dev/ic/rt2860.c
3260
sc->nrxchains = val & 0xf;
sys/dev/ic/rt2860.c
3265
val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG);
sys/dev/ic/rt2860.c
3266
DPRINTF(("EEPROM CFG 0x%04x\n", val));
sys/dev/ic/rt2860.c
3268
if ((val >> 8) != 0xff)
sys/dev/ic/rt2860.c
3269
sc->patch_dac = (val >> 15) & 1;
sys/dev/ic/rt2860.c
3270
if ((val & 0xff) != 0xff) {
sys/dev/ic/rt2860.c
3271
sc->ext_5ghz_lna = (val >> 3) & 1;
sys/dev/ic/rt2860.c
3272
sc->ext_2ghz_lna = (val >> 2) & 1;
sys/dev/ic/rt2860.c
3276
sc->rfswitch = val & 1;
sys/dev/ic/rt2860.c
3280
val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
sys/dev/ic/rt2860.c
3281
if ((val & 0xff) != 0xff) {
sys/dev/ic/rt2860.c
3282
sc->pslevel = val & 0x3;
sys/dev/ic/rt2860.c
3283
val = rt2860_srom_read(sc, RT2860_EEPROM_REV);
sys/dev/ic/rt2860.c
3284
if ((val & 0xff80) != 0x9280)
sys/dev/ic/rt2860.c
3292
val = rt2860_srom_read(sc,
sys/dev/ic/rt2860.c
3294
sc->txpow1[i + 0] = (int8_t)(val & 0xff);
sys/dev/ic/rt2860.c
3295
sc->txpow1[i + 1] = (int8_t)(val >> 8);
sys/dev/ic/rt2860.c
3298
val = rt2860_srom_read(sc,
sys/dev/ic/rt2860.c
3300
sc->txpow2[i + 0] = (int8_t)(val & 0xff);
sys/dev/ic/rt2860.c
3301
sc->txpow2[i + 1] = (int8_t)(val >> 8);
sys/dev/ic/rt2860.c
3319
val = rt2860_srom_read(sc,
sys/dev/ic/rt2860.c
3321
sc->txpow1[i + 14] = (int8_t)(val & 0xff);
sys/dev/ic/rt2860.c
3322
sc->txpow1[i + 15] = (int8_t)(val >> 8);
sys/dev/ic/rt2860.c
3324
val = rt2860_srom_read(sc,
sys/dev/ic/rt2860.c
3326
sc->txpow2[i + 14] = (int8_t)(val & 0xff);
sys/dev/ic/rt2860.c
3327
sc->txpow2[i + 15] = (int8_t)(val >> 8);
sys/dev/ic/rt2860.c
3341
val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR);
sys/dev/ic/rt2860.c
3343
if ((val & 0xff) != 0xff && (val & 0x80)) {
sys/dev/ic/rt2860.c
3344
delta_2ghz = val & 0xf;
sys/dev/ic/rt2860.c
3345
if (!(val & 0x40)) /* negative number */
sys/dev/ic/rt2860.c
3348
val >>= 8;
sys/dev/ic/rt2860.c
3349
if ((val & 0xff) != 0xff && (val & 0x80)) {
sys/dev/ic/rt2860.c
3350
delta_5ghz = val & 0xf;
sys/dev/ic/rt2860.c
3351
if (!(val & 0x40)) /* negative number */
sys/dev/ic/rt2860.c
3360
val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2);
sys/dev/ic/rt2860.c
3361
reg = val;
sys/dev/ic/rt2860.c
3362
val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1);
sys/dev/ic/rt2860.c
3363
reg |= (uint32_t)val << 16;
sys/dev/ic/rt2860.c
3375
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
sys/dev/ic/rt2860.c
3376
sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
sys/dev/ic/rt2860.c
3377
sc->tssi_2ghz[1] = val >> 8; /* [-3] */
sys/dev/ic/rt2860.c
3378
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
sys/dev/ic/rt2860.c
3379
sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
sys/dev/ic/rt2860.c
3380
sc->tssi_2ghz[3] = val >> 8; /* [-1] */
sys/dev/ic/rt2860.c
3381
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
sys/dev/ic/rt2860.c
3382
sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
sys/dev/ic/rt2860.c
3383
sc->tssi_2ghz[5] = val >> 8; /* [+1] */
sys/dev/ic/rt2860.c
3384
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
sys/dev/ic/rt2860.c
3385
sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
sys/dev/ic/rt2860.c
3386
sc->tssi_2ghz[7] = val >> 8; /* [+3] */
sys/dev/ic/rt2860.c
3387
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
sys/dev/ic/rt2860.c
3388
sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
sys/dev/ic/rt2860.c
3389
sc->step_2ghz = val >> 8;
sys/dev/ic/rt2860.c
3399
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
sys/dev/ic/rt2860.c
3400
sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
sys/dev/ic/rt2860.c
3401
sc->tssi_5ghz[1] = val >> 8; /* [-3] */
sys/dev/ic/rt2860.c
3402
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
sys/dev/ic/rt2860.c
3403
sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
sys/dev/ic/rt2860.c
3404
sc->tssi_5ghz[3] = val >> 8; /* [-1] */
sys/dev/ic/rt2860.c
3405
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
sys/dev/ic/rt2860.c
3406
sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
sys/dev/ic/rt2860.c
3407
sc->tssi_5ghz[5] = val >> 8; /* [+1] */
sys/dev/ic/rt2860.c
3408
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
sys/dev/ic/rt2860.c
3409
sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
sys/dev/ic/rt2860.c
3410
sc->tssi_5ghz[7] = val >> 8; /* [+3] */
sys/dev/ic/rt2860.c
3411
val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
sys/dev/ic/rt2860.c
3412
sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
sys/dev/ic/rt2860.c
3413
sc->step_5ghz = val >> 8;
sys/dev/ic/rt2860.c
3424
val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
sys/dev/ic/rt2860.c
3425
sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
sys/dev/ic/rt2860.c
3426
sc->rssi_2ghz[1] = val >> 8; /* Ant B */
sys/dev/ic/rt2860.c
3427
val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
sys/dev/ic/rt2860.c
3433
if ((val & 0xff) != 0xff)
sys/dev/ic/rt2860.c
3434
sc->txmixgain_2ghz = val & 0x7;
sys/dev/ic/rt2860.c
3437
sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
sys/dev/ic/rt2860.c
3438
sc->lna[2] = val >> 8; /* channel group 2 */
sys/dev/ic/rt2860.c
3440
val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
sys/dev/ic/rt2860.c
3441
sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
sys/dev/ic/rt2860.c
3442
sc->rssi_5ghz[1] = val >> 8; /* Ant B */
sys/dev/ic/rt2860.c
3443
val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
sys/dev/ic/rt2860.c
3444
sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
sys/dev/ic/rt2860.c
3445
sc->lna[3] = val >> 8; /* channel group 3 */
sys/dev/ic/rt2860.c
3447
val = rt2860_srom_read(sc, RT2860_EEPROM_LNA);
sys/dev/ic/rt2860.c
3451
sc->lna[0] = val & 0xff;
sys/dev/ic/rt2860.c
3452
sc->lna[1] = val >> 8; /* channel group 1 */
sys/dev/ic/rt2860.c
3505
rt2860_def_bbp[i].val);
sys/dev/ic/rt2860.c
3543
rt3290_def_bbp[i].val);
sys/dev/ic/rt2860.c
3548
rt5390_def_bbp[i].val);
sys/dev/ic/rt2860.c
3756
RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
sys/dev/ic/rt2860.c
3850
rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
sys/dev/ic/rt2860reg.h
1102
#define RAL_WRITE(sc, reg, val) \
sys/dev/ic/rt2860reg.h
1103
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/rt2860reg.h
1117
#define RAL_SET_REGION_4(sc, offset, val, count) \
sys/dev/ic/rt2860reg.h
1119
(val), (count))
sys/dev/ic/rt2860reg.h
1124
#define RT2860_EEPROM_CTL(sc, val) do { \
sys/dev/ic/rt2860reg.h
1125
RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \
sys/dev/ic/rt2860var.h
176
uint8_t val;
sys/dev/ic/rtl81x9.c
1290
rl_miibus_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/rtl81x9.c
1320
CSR_WRITE_2(sc, rl8139_reg, val);
sys/dev/ic/rtl81x9.c
1327
frame.mii_data = val;
sys/dev/ic/rtl81x9reg.h
958
#define CSR_WRITE_RAW_4(sc, csr, val) \
sys/dev/ic/rtl81x9reg.h
959
bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4)
sys/dev/ic/rtl81x9reg.h
960
#define CSR_WRITE_4(sc, csr, val) \
sys/dev/ic/rtl81x9reg.h
961
bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val)
sys/dev/ic/rtl81x9reg.h
962
#define CSR_WRITE_2(sc, csr, val) \
sys/dev/ic/rtl81x9reg.h
963
bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val)
sys/dev/ic/rtl81x9reg.h
964
#define CSR_WRITE_1(sc, csr, val) \
sys/dev/ic/rtl81x9reg.h
965
bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val)
sys/dev/ic/rtl81x9reg.h
974
#define CSR_SETBIT_1(sc, offset, val) \
sys/dev/ic/rtl81x9reg.h
975
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
sys/dev/ic/rtl81x9reg.h
977
#define CSR_CLRBIT_1(sc, offset, val) \
sys/dev/ic/rtl81x9reg.h
978
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
sys/dev/ic/rtl81x9reg.h
980
#define CSR_SETBIT_2(sc, offset, val) \
sys/dev/ic/rtl81x9reg.h
981
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
sys/dev/ic/rtl81x9reg.h
983
#define CSR_CLRBIT_2(sc, offset, val) \
sys/dev/ic/rtl81x9reg.h
984
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
sys/dev/ic/rtl81x9reg.h
986
#define CSR_SETBIT_4(sc, offset, val) \
sys/dev/ic/rtl81x9reg.h
987
CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
sys/dev/ic/rtl81x9reg.h
989
#define CSR_CLRBIT_4(sc, offset, val) \
sys/dev/ic/rtl81x9reg.h
990
CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
sys/dev/ic/rtsx.c
70
#define WRITE4(sc, reg, val) \
sys/dev/ic/rtsx.c
71
bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val))
sys/dev/ic/rtsx.c
728
rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val)
sys/dev/ic/rtsx.c
73
#define RTSX_READ(sc, reg, val) \
sys/dev/ic/rtsx.c
742
*val = (reg & 0xff);
sys/dev/ic/rtsx.c
747
rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val)
sys/dev/ic/rtsx.c
75
int err = rtsx_read((sc), (reg), (val)); \
sys/dev/ic/rtsx.c
755
(mask << 8) | val));
sys/dev/ic/rtsx.c
760
if (val != (reg & 0xff))
sys/dev/ic/rtsx.c
771
rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val)
sys/dev/ic/rtsx.c
792
*val = data0 | (data1 << 8);
sys/dev/ic/rtsx.c
799
rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val)
sys/dev/ic/rtsx.c
80
#define RTSX_WRITE(sc, reg, val) \
sys/dev/ic/rtsx.c
804
RTSX_WRITE(sc, RTSX_PHY_DATA0, val);
sys/dev/ic/rtsx.c
805
RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8);
sys/dev/ic/rtsx.c
82
int err = rtsx_write((sc), (reg), 0xff, (val)); \
sys/dev/ic/rtsx.c
823
u_int32_t *val)
sys/dev/ic/rtsx.c
846
*val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0;
sys/dev/ic/rtsx.c
854
u_int32_t mask, u_int32_t val)
sys/dev/ic/rtsx.c
861
RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff);
sys/dev/ic/rtsx.c
865
val >>= 8;
sys/dev/ic/rtw.c
2512
u_int8_t mask, newval, val;
sys/dev/ic/rtw.c
2544
val = RTW_READ8(regs, ofs);
sys/dev/ic/rtw.c
2546
("%s: read % from reg[%#02]\n", __func__, val,
sys/dev/ic/rtw.c
2548
val &= ~mask;
sys/dev/ic/rtw.c
2549
val |= newval;
sys/dev/ic/rtw.c
2550
RTW_WRITE8(regs, ofs, val);
sys/dev/ic/rtw.c
2552
("%s: wrote % to reg[%#02]\n", __func__, val,
sys/dev/ic/rtw.c
4139
#define RTW_BBP_WRITE_OR_RETURN(reg, val) \
sys/dev/ic/rtw.c
4140
if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
sys/dev/ic/rtw.c
4169
rtw_verify_syna(u_int freq, u_int32_t val)
sys/dev/ic/rtw.c
4171
u_int32_t expected_val = ~val;
sys/dev/ic/rtw.c
4217
KASSERT(val == expected_val);
sys/dev/ic/rtw.c
4688
rtw_bbp_write(struct rtw_regs *regs, u_int addr, u_int val)
sys/dev/ic/rtw.c
4696
("%s: bbp[%u] <- %u\n", __func__, addr, val));
sys/dev/ic/rtw.c
4699
KASSERT((val & ~PRESHIFT(RTW_BB_WR_MASK)) == 0);
sys/dev/ic/rtw.c
4702
LSHIFT(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK,
sys/dev/ic/rtw.c
4718
RTW_BB_RD_MASK) == val) {
sys/dev/ic/rtw.c
4879
rtw_grf5101_host_crypt(u_int addr, u_int32_t val)
sys/dev/ic/rtw.c
4886
rtw_grf5101_mac_crypt(u_int addr, u_int32_t val)
sys/dev/ic/rtw.c
4897
caesar[EXTRACT_NIBBLE(val, 2)] |
sys/dev/ic/rtw.c
4898
(caesar[EXTRACT_NIBBLE(val, 1)] << 4) |
sys/dev/ic/rtw.c
4899
(caesar[EXTRACT_NIBBLE(val, 0)] << 8) |
sys/dev/ic/rtw.c
4902
(caesar[EXTRACT_NIBBLE(val, 3)] << 24);
sys/dev/ic/rtw.c
4910
rtw_rf_hostwrite(struct rtw_softc *sc, u_int addr, u_int32_t val)
sys/dev/ic/rtw.c
4919
addr, val));
sys/dev/ic/rtw.c
4925
bits = LSHIFT(val, MAX2820_TWI_DATA_MASK) |
sys/dev/ic/rtw.c
4930
KASSERT((val & ~PRESHIFT(SA2400_TWI_DATA_MASK)) == 0);
sys/dev/ic/rtw.c
4931
bits = LSHIFT(val, SA2400_TWI_DATA_MASK) |
sys/dev/ic/rtw.c
4938
KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
sys/dev/ic/rtw.c
4939
bits = rtw_grf5101_host_crypt(addr, val);
sys/dev/ic/rtw.c
4945
KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
sys/dev/ic/rtw.c
4946
bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
sys/dev/ic/rtw.c
4955
bits = LSHIFT(val, RTL8225_TWI_DATA_MASK) |
sys/dev/ic/rtw.c
4973
rtw_maxim_swizzle(u_int addr, u_int32_t val)
sys/dev/ic/rtw.c
4977
KASSERT((val & ~(RTW_MAXIM_LODATA_MASK|RTW_MAXIM_HIDATA_MASK)) == 0);
sys/dev/ic/rtw.c
4978
lodata = MASK_AND_RSHIFT(val, RTW_MAXIM_LODATA_MASK);
sys/dev/ic/rtw.c
4979
hidata = MASK_AND_RSHIFT(val, RTW_MAXIM_HIDATA_MASK);
sys/dev/ic/rtw.c
4987
rtw_rf_macwrite(struct rtw_softc *sc, u_int addr, u_int32_t val)
sys/dev/ic/rtw.c
4992
addr, val));
sys/dev/ic/rtw.c
4996
reg = rtw_grf5101_mac_crypt(addr, val);
sys/dev/ic/rtw.c
4999
reg = rtw_maxim_swizzle(addr, val);
sys/dev/ic/rtw.c
5005
KASSERT((val &
sys/dev/ic/rtw.c
5009
LSHIFT(val, RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK);
sys/dev/ic/rtw.c
5055
rtw_write8(void *arg, u_int32_t off, u_int8_t val)
sys/dev/ic/rtw.c
5058
bus_space_write_1(regs->r_bt, regs->r_bh, off, val);
sys/dev/ic/rtw.c
5062
rtw_write16(void *arg, u_int32_t off, u_int16_t val)
sys/dev/ic/rtw.c
5065
bus_space_write_2(regs->r_bt, regs->r_bh, off, val);
sys/dev/ic/rtw.c
5069
rtw_write32(void *arg, u_int32_t off, u_int32_t val)
sys/dev/ic/rtw.c
5072
bus_space_write_4(regs->r_bt, regs->r_bh, off, val);
sys/dev/ic/rtwn.c
198
#define RTWN_SIGN4TO8(val) (((val) & 0x08) ? (val) | 0xf0 : (val))
sys/dev/ic/rtwn.c
2906
uint32_t reg, val, x;
sys/dev/ic/rtwn.c
2913
val = ((reg >> 22) & 0x3ff);
sys/dev/ic/rtwn.c
2918
reg |= (((x * val) >> 8) & 0x3ff);
sys/dev/ic/rtwn.c
2922
if (((x * val) >> 7) & 0x01)
sys/dev/ic/rtwn.c
2931
tx_c = (y * val) >> 8;
sys/dev/ic/rtwn.c
2943
if (((y * val) >> 7) & 0x01)
sys/dev/ic/rtwn.c
359
rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val)
sys/dev/ic/rtwn.c
361
sc->sc_ops.write_1(sc->sc_ops.cookie, addr, val);
sys/dev/ic/rtwn.c
365
rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val)
sys/dev/ic/rtwn.c
367
sc->sc_ops.write_2(sc->sc_ops.cookie, addr, val);
sys/dev/ic/rtwn.c
371
rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val)
sys/dev/ic/rtwn.c
373
sc->sc_ops.write_4(sc->sc_ops.cookie, addr, val);
sys/dev/ic/rtwn.c
438
rtwn_rf_write(struct rtwn_softc *sc, int chain, uint16_t addr, uint32_t val)
sys/dev/ic/rtwn.c
453
param_addr | SM(R92C_LSSI_PARAM_DATA, val));
sys/dev/ic/rtwn.c
466
uint32_t reg[R92C_MAX_CHAINS], val;
sys/dev/ic/rtwn.c
488
val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
sys/dev/ic/rtwn.c
490
val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
sys/dev/ic/rtwn.c
491
return (MS(val, R92C_LSSI_READBACK_DATA));
sys/dev/ic/rtwreg.h
1126
#define RTW_WRITE8(regs, ofs, val) \
sys/dev/ic/rtwreg.h
1127
((*(regs)->r_write8)(regs, ofs, val))
sys/dev/ic/rtwreg.h
1129
#define RTW_WRITE16(regs, ofs, val) \
sys/dev/ic/rtwreg.h
1130
((*(regs)->r_write16)(regs, ofs, val))
sys/dev/ic/rtwreg.h
1132
#define RTW_WRITE(regs, ofs, val) \
sys/dev/ic/rtwreg.h
1133
((*(regs)->r_write32)(regs, ofs, val))
sys/dev/ic/rtwreg.h
71
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
sys/dev/ic/siop.c
157
siop_script_write(struct siop_softc *sc, u_int offset, u_int32_t val)
sys/dev/ic/siop.c
161
offset * 4, val);
sys/dev/ic/siop.c
163
sc->sc_c.sc_script[offset] = siop_htoc32(&sc->sc_c, val);
sys/dev/ic/smc83c170.c
1338
epic_mii_write(struct device *self, int phy, int reg, int val)
sys/dev/ic/smc83c170.c
1345
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val);
sys/dev/ic/smc91cxx.c
1152
smc91cxx_mii_bitbang_write(struct device *self, u_int32_t val)
sys/dev/ic/smc91cxx.c
1157
bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val);
sys/dev/ic/smc91cxx.c
1164
int val;
sys/dev/ic/smc91cxx.c
1168
val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
sys/dev/ic/smc91cxx.c
1172
return (val);
sys/dev/ic/smc91cxx.c
1176
smc91cxx_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/smc91cxx.c
1182
mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
sys/dev/ic/tcic2.c
109
int val, auxreg;
sys/dev/ic/tcic2.c
113
val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK)
sys/dev/ic/tcic2.c
115
if (val > 1)
sys/dev/ic/tcic2.c
120
val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
sys/dev/ic/tcic2.c
121
if (val & TCIC_SCTRL_RSVD)
sys/dev/ic/tcic2.c
126
val = bus_space_read_1(iot, ioh, TCIC_R_ICSR);
sys/dev/ic/tcic2.c
127
if (((val >> 1) & 1) != ((val >> 2) & 1))
sys/dev/ic/tcic2.c
1294
int val;
sys/dev/ic/tcic2.c
1301
val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
sys/dev/ic/tcic2.c
1302
val &= TCIC_SCF1_IRQ_MASK;
sys/dev/ic/tcic2.c
1303
tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val);
sys/dev/ic/tcic2.c
1307
val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
sys/dev/ic/tcic2.c
1308
val &= ~TCIC_ILOCK_CRESENA;
sys/dev/ic/tcic2.c
1309
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val);
sys/dev/ic/tcic2.c
132
val = bus_space_read_1(iot, ioh, TCIC_R_IENA);
sys/dev/ic/tcic2.c
133
if (val & TCIC_IENA_RSVD)
sys/dev/ic/tcic2.c
1330
tcic_log2(u_int val)
sys/dev/ic/tcic2.c
1335
while (val) {
sys/dev/ic/tcic2.c
1336
if (val & 1)
sys/dev/ic/tcic2.c
1339
val >>= 1;
sys/dev/ic/tcic2.c
141
val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
sys/dev/ic/tcic2.c
142
DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val));
sys/dev/ic/tcic2.c
145
if (INVALID_AR_SYSCFG(val))
sys/dev/ic/tcic2.c
149
if (INVALID_AR_ILOCK(val))
sys/dev/ic/tcic2.c
153
if (INVALID_AR_TEST(val))
sys/dev/ic/tcic2.c
161
val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
sys/dev/ic/tcic2.c
162
if (val & TCIC_SCTRL_RESET) {
sys/dev/ic/tcic2.c
165
val = bus_space_read_2(iot, ioh, TCIC_R_ADDR);
sys/dev/ic/tcic2.c
166
if (val != 0)
sys/dev/ic/tcic2.c
168
val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2);
sys/dev/ic/tcic2.c
169
if (val != 0)
sys/dev/ic/tcic2.c
173
val = bus_space_read_2(iot, ioh, TCIC_R_EDC);
sys/dev/ic/tcic2.c
174
if (val != 0)
sys/dev/ic/tcic2.c
184
val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT);
sys/dev/ic/tcic2.c
185
if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME))
sys/dev/ic/tcic2.c
731
int val, reg;
sys/dev/ic/tcic2.c
750
val = tcic_read_ind_2(h, reg);
sys/dev/ic/tcic2.c
751
tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
sys/dev/ic/tcic2.c
753
val = tcic_read_ind_2(h, reg);
sys/dev/ic/tcic2.c
755
(val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY
sys/dev/ic/tcic2var.h
204
int val;
sys/dev/ic/tcic2var.h
205
val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
sys/dev/ic/tcic2var.h
206
val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
sys/dev/ic/tcic2var.h
207
return val;
sys/dev/ic/tcic2var.h
236
int r_addr, val;
sys/dev/ic/tcic2var.h
239
val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA);
sys/dev/ic/tcic2var.h
241
return val;
sys/dev/ic/tcic2var.h
288
int mode, val;
sys/dev/ic/tcic2var.h
291
val = bus_space_read_1(iot, ioh, reg);
sys/dev/ic/tcic2var.h
292
return val;
sys/dev/ic/tcic2var.h
299
int mode, val;
sys/dev/ic/tcic2var.h
302
val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
sys/dev/ic/tcic2var.h
303
return val;
sys/dev/ic/tcic2var.h
309
int reg, int val)
sys/dev/ic/tcic2var.h
314
bus_space_write_1(iot, ioh, reg, val);
sys/dev/ic/tcic2var.h
320
int val)
sys/dev/ic/tcic2var.h
325
bus_space_write_2(iot, ioh, TCIC_R_AUX, val);
sys/dev/ic/tireg.h
988
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/tireg.h
989
bus_space_write_4(sc->ti_btag, sc->ti_bhandle, (reg), (val))
sys/dev/ic/vgavar.h
122
_vga_attr_write(struct vga_handle *vh, int reg, u_int8_t val)
sys/dev/ic/vgavar.h
128
vga_raw_write(vh, VGA_ATC_DATAW, val);
sys/dev/ic/vgavar.h
144
_vga_ts_write(struct vga_handle *vh, int reg, u_int8_t val)
sys/dev/ic/vgavar.h
147
vga_raw_write(vh, VGA_TS_DATA, val);
sys/dev/ic/vgavar.h
158
_vga_gdc_write(struct vga_handle *vh, int reg, u_int8_t val)
sys/dev/ic/vgavar.h
161
vga_raw_write(vh, VGA_GDC_DATA, val);
sys/dev/ic/vgavar.h
166
#define vga_attr_write(vh, reg, val) \
sys/dev/ic/vgavar.h
167
_vga_attr_write(vh, offsetof(struct reg_vgaattr, reg), val)
sys/dev/ic/vgavar.h
170
#define vga_ts_write(vh, reg, val) \
sys/dev/ic/vgavar.h
171
_vga_ts_write(vh, offsetof(struct reg_vgats, reg), val)
sys/dev/ic/vgavar.h
174
#define vga_gdc_write(vh, reg, val) \
sys/dev/ic/vgavar.h
175
_vga_gdc_write(vh, offsetof(struct reg_vgagdc, reg), val)
sys/dev/ic/vgavar.h
179
#define vga_6845_write(vh, reg, val) \
sys/dev/ic/vgavar.h
180
pcdisplay_6845_write(&(vh)->vh_ph, reg, val)
sys/dev/ic/w83l518d.c
52
wb_idx_write(struct wb_softc *wb, uint8_t reg, uint8_t val)
sys/dev/ic/w83l518d.c
55
bus_space_write_1(wb->wb_iot, wb->wb_ioh, WB_SD_DATA, val);
sys/dev/ic/w83l518d.c
65
wb_write(struct wb_softc *wb, uint8_t reg, uint8_t val)
sys/dev/ic/w83l518d.c
67
bus_space_write_1(wb->wb_iot, wb->wb_ioh, reg, val);
sys/dev/ic/w83l518d.c
73
uint8_t val;
sys/dev/ic/w83l518d.c
75
val = wb_read(wb, WB_SD_CSR);
sys/dev/ic/w83l518d.c
77
val |= WB_CSR_MS_LED;
sys/dev/ic/w83l518d.c
79
val &= ~WB_CSR_MS_LED;
sys/dev/ic/w83l518d.c
80
wb_write(wb, WB_SD_CSR, val);
sys/dev/ic/w83l518d_sdmmc.c
164
uint8_t val;
sys/dev/ic/w83l518d_sdmmc.c
168
val = wb_read(wb, WB_SD_CSR);
sys/dev/ic/w83l518d_sdmmc.c
169
val |= WB_CSR_POWER_N;
sys/dev/ic/w83l518d_sdmmc.c
170
wb_write(wb, WB_SD_CSR, val);
sys/dev/ic/w83l518d_sdmmc.c
426
uint8_t val;
sys/dev/ic/w83l518d_sdmmc.c
463
val = wb_idx_read(wb, WB_INDEX_SETUP);
sys/dev/ic/w83l518d_sdmmc.c
464
val |= WB_SETUP_FIFO_RST;
sys/dev/ic/w83l518d_sdmmc.c
465
wb_idx_write(wb, WB_INDEX_SETUP, val);
sys/dev/ic/w83l518d_sdmmc.c
565
uint8_t val;
sys/dev/ic/w83l518d_sdmmc.c
567
val = wb_read(wb, WB_SD_INTSTS);
sys/dev/ic/w83l518d_sdmmc.c
568
if (val == 0xff || val == 0x00)
sys/dev/ic/w83l518d_sdmmc.c
574
wb->wb_sdmmc_intsts |= val;
sys/dev/ic/w83l518d_sdmmc.c
576
REPORT(wb, "WB_SD_INTSTS = %b\n", val,
sys/dev/ic/w83l518d_sdmmc.c
580
if (val & WB_INT_CARD)
sys/dev/ic/wdc.c
152
unsigned int size, char val[])
sys/dev/ic/wdc.c
210
memcpy(ptr, val, size);
sys/dev/ic/wdc.c
309
wdc_default_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/ic/wdc.c
319
reg & _WDC_REGMASK, val);
sys/dev/ic/wdc.c
322
reg & _WDC_REGMASK, val);
sys/dev/ic/wdc.c
327
u_int16_t val)
sys/dev/ic/wdc.c
330
CHP_WRITE_REG(chp, reg, val >> 8);
sys/dev/ic/wdc.c
331
CHP_WRITE_REG(chp, reg, val);
sys/dev/ic/wdcevent.h
101
enum wdc_regs reg, u_int16_t val) {
sys/dev/ic/wdcevent.h
105
record[1] = (val >> 8);
sys/dev/ic/wdcevent.h
106
record[2] = val & 0xff;
sys/dev/ic/wdcevent.h
129
#define WDC_LOG_REG(chp, reg, val)
sys/dev/ic/wdcevent.h
48
unsigned int size, char val[]);
sys/dev/ic/xlreg.h
643
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/xlreg.h
644
bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
sys/dev/ic/xlreg.h
645
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/xlreg.h
646
bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
sys/dev/ic/xlreg.h
647
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/ic/xlreg.h
648
bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
sys/dev/ipmi.c
1161
ipow(long val, int exp)
sys/dev/ipmi.c
1164
val *= 10;
sys/dev/ipmi.c
1169
val /= 10;
sys/dev/ipmi.c
1173
return (val);
sys/dev/ipmi.c
1178
signextend(unsigned long val, int bits)
sys/dev/ipmi.c
1182
return (-(val & ~msk) | val);
sys/dev/ipmi.c
1191
long val;
sys/dev/ipmi.c
1204
val = ipow(M * v, K2 + adj) + ipow(B, K1 + K2 + adj);
sys/dev/ipmi.c
1210
return (val);
sys/dev/ipmi.c
259
bmc_write(struct ipmi_softc *sc, int offset, u_int8_t val)
sys/dev/ipmi.c
263
offset * sc->sc_if_iospacing, val);
sys/dev/ipmi.c
266
offset * sc->sc_if_iospacing, val);
sys/dev/ipmi.c
463
smic_wait(struct ipmi_softc *sc, u_int8_t mask, u_int8_t val, const char *lbl)
sys/dev/ipmi.c
471
a.value = val;
sys/dev/isa/ess.c
2392
ess_write_x_reg(struct ess_softc *sc, u_char reg, u_char val)
sys/dev/isa/ess.c
2396
DPRINTFN(2,("ess_write_x_reg: %02x=%02x\n", reg, val));
sys/dev/isa/ess.c
2398
error = ess_wdsp(sc, val);
sys/dev/isa/ess.c
2410
int val;
sys/dev/isa/ess.c
2417
val = ess_rdsp(sc);
sys/dev/isa/ess.c
2418
DPRINTFN(2,("ess_read_x_reg: %02x=%02x\n", reg, val));
sys/dev/isa/ess.c
2419
return val;
sys/dev/isa/ess.c
2443
ess_write_mix_reg(struct ess_softc *sc, u_char reg, u_char val)
sys/dev/isa/ess.c
2448
DPRINTFN(2,("ess_write_mix_reg: %x=%x\n", reg, val));
sys/dev/isa/ess.c
2452
EWRITE1(iot, ioh, ESS_MIX_REG_DATA, val);
sys/dev/isa/ess.c
2464
u_char val;
sys/dev/isa/ess.c
2468
val = EREAD1(iot, ioh, ESS_MIX_REG_DATA);
sys/dev/isa/ess.c
2471
DPRINTFN(2,("ess_read_mix_reg: %x=%x\n", reg, val));
sys/dev/isa/ess.c
2472
return val;
sys/dev/isa/fins.c
333
u_int16_t val;
sys/dev/isa/fins.c
336
val = bus_space_read_1(iot, ioh, FINS_DATA) << 8;
sys/dev/isa/fins.c
338
return (val | bus_space_read_1(iot, ioh, FINS_DATA));
sys/dev/isa/fins.c
342
fins_write(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, u_int8_t val)
sys/dev/isa/fins.c
345
bus_space_write_1(iot, ioh, FINS_DATA, val);
sys/dev/isa/fins.c
367
fins_write_wdog(struct fins_softc *sc, int reg, u_int8_t val)
sys/dev/isa/fins.c
369
bus_space_write_1(sc->sc_iot, sc->sc_ioh_wdog, reg, val);
sys/dev/isa/gscsio.c
96
#define ACB_WRITE(reg, val) \
sys/dev/isa/gscsio.c
97
bus_space_write_1(sc->sc_iot, acb->ioh, (reg), (val))
sys/dev/isa/i82365_isa.c
121
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/dev/isa/i82365_isa.c
122
if (pcic_ident_ok(val))
sys/dev/isa/i82365_isa.c
126
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/dev/isa/i82365_isa.c
127
if (pcic_ident_ok(val))
sys/dev/isa/i82365_isa.c
131
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/dev/isa/i82365_isa.c
132
if (pcic_ident_ok(val))
sys/dev/isa/i82365_isa.c
136
val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
sys/dev/isa/i82365_isa.c
137
if (pcic_ident_ok(val))
sys/dev/isa/i82365_isa.c
93
int val, found;
sys/dev/isa/ics2101.c
60
#define cvt_value(val) ((val) >> 1)
sys/dev/isa/if_ef_isapnp.c
790
int i, ack, s, val = 0;
sys/dev/isa/if_ef_isapnp.c
842
val |= i;
sys/dev/isa/if_ef_isapnp.c
854
return (val);
sys/dev/isa/if_ef_isapnp.c
858
ef_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/isa/if_ef_isapnp.c
888
ef_mii_writeb(sc, (val & i) ? 1 : 0);
sys/dev/isa/if_le.c
70
le_isa_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
sys/dev/isa/if_le.c
77
bus_space_write_2(iot, ioh, lesc->sc_rdp, val);
sys/dev/isa/if_le.c
86
uint16_t val;
sys/dev/isa/if_le.c
89
val = bus_space_read_2(iot, ioh, lesc->sc_rdp);
sys/dev/isa/if_le.c
90
return (val);
sys/dev/isa/if_le_isa.c
313
u_char *mem, val;
sys/dev/isa/if_le_isa.c
318
val = 0xff;
sys/dev/isa/if_le_isa.c
321
mem[i] = val;
sys/dev/isa/if_le_isa.c
323
if (mem[i] != val) {
sys/dev/isa/if_le_isa.c
328
if (val == 0x00)
sys/dev/isa/if_le_isa.c
330
val -= 0x55;
sys/dev/isa/lm78_isa.c
265
lm_isa_writereg(struct lm_softc *lmsc, int reg, int val)
sys/dev/isa/lm78_isa.c
270
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_DATA, val);
sys/dev/isa/nsclpcsio_isa.c
186
#define GPIO_WRITE(sc, reg, val) \
sys/dev/isa/nsclpcsio_isa.c
188
(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))
sys/dev/isa/nsclpcsio_isa.c
189
#define TMS_WRITE(sc, reg, val) \
sys/dev/isa/nsclpcsio_isa.c
191
(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))
sys/dev/isa/nsclpcsio_isa.c
195
#define VLM_WRITE(sc, reg, val) \
sys/dev/isa/nsclpcsio_isa.c
197
(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))
sys/dev/isa/pcdisplay.c
128
u_int16_t oldval, val;
sys/dev/isa/pcdisplay.c
134
val = bus_space_read_2(memt, memh, 0);
sys/dev/isa/pcdisplay.c
137
if (val != 0xa55a)
sys/dev/isa/pcdisplay.c
151
u_int16_t oldval, val;
sys/dev/isa/pcdisplay.c
157
val = bus_space_read_2(memt, memh, 0);
sys/dev/isa/pcdisplay.c
160
if (val != 0xa55a)
sys/dev/isa/sbdsp.c
1378
sbdsp_adjust(int val, int mask)
sys/dev/isa/sbdsp.c
1380
val += (MAXVAL - mask) >> 1;
sys/dev/isa/sbdsp.c
1381
if (val >= MAXVAL)
sys/dev/isa/sbdsp.c
1382
val = MAXVAL-1;
sys/dev/isa/sbdsp.c
1383
return val & mask;
sys/dev/isa/sbdsp.c
405
sbdsp_mix_write(struct sbdsp_softc *sc, int mixerport, int val)
sys/dev/isa/sbdsp.c
413
bus_space_write_1(iot, ioh, SBP_MIXER_DATA, val);
sys/dev/isa/sbdsp.c
423
int val;
sys/dev/isa/sbdsp.c
428
val = bus_space_read_1(iot, ioh, SBP_MIXER_DATA);
sys/dev/isa/sbdsp.c
431
return val;
sys/dev/isa/sch311x.c
171
u_int8_t reg, u_int8_t val);
sys/dev/isa/sch311x.c
217
u_int8_t reg, u_int8_t val)
sys/dev/isa/sch311x.c
220
bus_space_write_1(iot, ioh, SCHSIO_PORT_DATA, val);
sys/dev/isa/sch311x.c
510
uint8_t val, minute, reg;
sys/dev/isa/sch311x.c
515
val = period / 60;
sys/dev/isa/sch311x.c
518
val = period;
sys/dev/isa/sch311x.c
534
bus_space_write_1(sc->sc_iot, sc->sc_ioh_rr, SCHSIO_WDT_VAL, val);
sys/dev/isa/sch311x.c
537
return val;
sys/dev/isa/sch311x.c
539
return val * 60;
sys/dev/isa/tcic2_isa.c
145
int val, found;
sys/dev/isa/tcic2_isa.c
169
if ((val = tcic_chipid(iot, ioh))) {
sys/dev/isa/tcic2_isa.c
170
DPRINTF(("tcic id: 0x%02x\n", val));
sys/dev/isa/tcic2_isa.c
171
if (tcic_chipid_known(val))
sys/dev/isa/tcic2_isa.c
310
int irq, ist, val, reg;
sys/dev/isa/tcic2_isa.c
341
val = (tcic_read_ind_2(h, reg) & (~TCIC_SCF1_IRQ_MASK)) | irqmap[irq];
sys/dev/isa/tcic2_isa.c
342
tcic_write_ind_2(h, reg, val);
sys/dev/isa/tcic2_isa.c
352
int val, reg;
sys/dev/isa/tcic2_isa.c
359
val = tcic_read_ind_2(h, reg);
sys/dev/isa/tcic2_isa.c
360
val &= ~TCIC_SCF1_IRQ_MASK;
sys/dev/isa/tcic2_isa.c
361
tcic_write_ind_2(h, reg, val);
sys/dev/isa/uguru.c
39
#define UGURU_WRITE(iot, ioh, reg, val) \
sys/dev/isa/uguru.c
40
bus_space_write_1((iot), (ioh), (reg), (val))
sys/dev/isa/uguru.c
938
uint8_t val = 0x00;
sys/dev/isa/uguru.c
948
uguru_read_multi(iot, ioh, &val, sizeof(val)))
sys/dev/isa/uguru.c
960
sc->cs.reading = val;
sys/dev/isa/uguru.c
966
idx, reg, val, data[0], data[1], data[2]);
sys/dev/isa/uguru.c
975
uint8_t val = 0x00;
sys/dev/isa/uguru.c
979
if (uguru_ac5_read(sc->sc_iot, sc->sc_ioh, reg, &val, sizeof(val)))
sys/dev/isa/uguru.c
982
sc->cs.reading = val;
sys/dev/isa/viasio.c
338
int64_t val, rfact;
sys/dev/isa/viasio.c
345
val = (reg0 << 2) | reg1;
sys/dev/isa/viasio.c
349
val = viasio_raw2temp(val);
sys/dev/isa/viasio.c
350
if (val == -1) {
sys/dev/isa/viasio.c
354
sc->sc_hm_sensors[VT1211_HMS_TEMP1].value = val;
sys/dev/isa/viasio.c
373
val = (reg0 << 2) | reg1;
sys/dev/isa/viasio.c
377
val = viasio_raw2temp(val);
sys/dev/isa/viasio.c
378
if (val == -1) {
sys/dev/isa/viasio.c
385
i - 1].value = val;
sys/dev/isa/viasio.c
391
val = reg0;
sys/dev/isa/viasio.c
397
((val * 100000000000ULL) / (rfact * 958));
sys/dev/isa/viasio.c
403
val = reg0;
sys/dev/isa/viasio.c
408
sc->sc_hm_sensors[VT1211_HMS_33V].value = ((val * 100000000000ULL) /
sys/dev/isa/viasio.c
415
val = reg0 << reg1;
sys/dev/isa/viasio.c
419
if (val != 0) {
sys/dev/isa/viasio.c
421
(sc->sc_hm_clock * 60 / 2) / val;
sys/dev/isa/viasio.c
431
val = reg0 << reg1;
sys/dev/isa/viasio.c
435
if (val != 0) {
sys/dev/isa/viasio.c
437
(sc->sc_hm_clock * 60 / 2) / val;
sys/dev/isa/wds.c
188
int val)
sys/dev/isa/wds.c
190
while ((bus_space_read_1(iot, ioh, port) & mask) != val)
sys/dev/kcov.c
240
__sanitizer_cov_trace_switch(uint64_t val, uint64_t *cases)
sys/dev/kcov.c
273
trace_cmp(kd, type, cases[i + 2], val, pc);
sys/dev/microcode/esa/esadsp.h
46
u_int16_t addr, val;
sys/dev/microcode/esa/esadsp.h
71
u_int16_t addr, val;
sys/dev/microcode/siop/ncr53cxxx.c
468
void setarch(char *val)
sys/dev/microcode/siop/ncr53cxxx.c
470
switch (atoi(val)) {
sys/dev/mii/brgphy.c
1006
uint16_t val;
sys/dev/mii/brgphy.c
1024
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1034
uint16_t val;
sys/dev/mii/brgphy.c
1044
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1071
uint16_t val;
sys/dev/mii/brgphy.c
1080
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1088
uint16_t val;
sys/dev/mii/brgphy.c
1101
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1109
uint16_t val;
sys/dev/mii/brgphy.c
1118
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1126
uint16_t val;
sys/dev/mii/brgphy.c
1141
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1150
uint16_t val;
sys/dev/mii/brgphy.c
1161
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1167
uint32_t val;
sys/dev/mii/brgphy.c
1170
val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
sys/dev/mii/brgphy.c
1171
val &= ~(1 << 8);
sys/dev/mii/brgphy.c
1172
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
sys/dev/mii/brgphy.c
1179
u_int32_t val;
sys/dev/mii/brgphy.c
1188
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
sys/dev/mii/brgphy.c
1190
val | BRGPHY_AUXCTL_LONG_PKT);
sys/dev/mii/brgphy.c
1193
val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
sys/dev/mii/brgphy.c
1195
val | BRGPHY_PHY_EXTCTL_HIGH_LA);
sys/dev/mii/brgphy.c
1201
uint16_t val;
sys/dev/mii/brgphy.c
1206
val = PHY_READ(sc, BRGPHY_MII_AUXCTL) & BRGPHY_AUXCTL_MISC_DATA_MASK;
sys/dev/mii/brgphy.c
1207
val |= BRGPHY_AUXCTL_MISC_WIRESPEED_EN;
sys/dev/mii/brgphy.c
1209
BRGPHY_AUXCTL_SHADOW_MISC | val);
sys/dev/mii/brgphy.c
1215
uint16_t val;
sys/dev/mii/brgphy.c
1219
val = PHY_READ(sc, BRGPHY_MII_AUXCTL) & BRGPHY_AUXCTL_MISC_DATA_MASK;
sys/dev/mii/brgphy.c
1221
val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
sys/dev/mii/brgphy.c
1223
val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
sys/dev/mii/brgphy.c
1225
BRGPHY_AUXCTL_SHADOW_MISC | val);
sys/dev/mii/brgphy.c
1228
val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & BRGPHY_SHADOW_1C_DATA_MASK;
sys/dev/mii/brgphy.c
1230
val |= BRGPHY_SHADOW_1C_GTXCLK_EN;
sys/dev/mii/brgphy.c
1232
val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN;
sys/dev/mii/brgphy.c
1234
BRGPHY_SHADOW_1C_CLK_CTRL | val);
sys/dev/mii/brgphy.c
567
int val;
sys/dev/mii/brgphy.c
577
val = PHY_READ(sc, MII_ANAR) & PHY_READ(sc, MII_ANLPAR);
sys/dev/mii/brgphy.c
579
if (val & ANAR_X_FD)
sys/dev/mii/brswphy.c
169
uint16_t *val);
sys/dev/mii/brswphy.c
171
uint32_t *val);
sys/dev/mii/brswphy.c
366
brswphy_read16(struct mii_softc *sc, uint8_t page, uint8_t reg, uint16_t *val)
sys/dev/mii/brswphy.c
374
*val = BRSW_PHY_READ(sc, REG_MII_DATA0);
sys/dev/mii/brswphy.c
380
brswphy_read32(struct mii_softc *sc, uint8_t page, uint8_t reg, uint32_t *val)
sys/dev/mii/brswphy.c
388
*val = BRSW_PHY_READ(sc, REG_MII_DATA0);
sys/dev/mii/brswphy.c
389
*val |= BRSW_PHY_READ(sc, REG_MII_DATA1) << 16;
sys/dev/mii/eephy.c
468
uint32_t val = 0;
sys/dev/mii/eephy.c
472
val = PHY_READ(sc, reg);
sys/dev/mii/eephy.c
473
val &= keep;
sys/dev/mii/eephy.c
475
val |= set;
sys/dev/mii/eephy.c
476
PHY_WRITE(sc, reg, val);
sys/dev/mii/mii_bitbang.c
117
int val = 0, err = 0, i;
sys/dev/mii/mii_bitbang.c
141
val <<= 1;
sys/dev/mii/mii_bitbang.c
144
val |= 1;
sys/dev/mii/mii_bitbang.c
153
return (err ? 0 : val);
sys/dev/mii/mii_bitbang.c
163
int phy, int reg, int val)
sys/dev/mii/mii_bitbang.c
173
mii_bitbang_sendbits(sc, ops, val, 16);
sys/dev/mii/rgephy.c
453
int page, val;
sys/dev/mii/rgephy.c
459
val = PHY_READ(sc, RGEPHY_MIICR1);
sys/dev/mii/rgephy.c
461
val |= RGEPHY_MIICR1_TXDLY_EN;
sys/dev/mii/rgephy.c
463
val &= ~RGEPHY_MIICR1_TXDLY_EN;
sys/dev/mii/rgephy.c
464
PHY_WRITE(sc, RGEPHY_MIICR1, val);
sys/dev/mii/rgephy.c
466
val = PHY_READ(sc, RGEPHY_MIICR2);
sys/dev/mii/rgephy.c
468
val |= RGEPHY_MIICR2_RXDLY_EN;
sys/dev/mii/rgephy.c
470
val &= ~RGEPHY_MIICR2_RXDLY_EN;
sys/dev/mii/rgephy.c
471
PHY_WRITE(sc, RGEPHY_MIICR2, val);
sys/dev/mii/rgephy.c
493
int val;
sys/dev/mii/rgephy.c
503
val = PHY_READ(sc, 4) & 0xFFF;
sys/dev/mii/rgephy.c
504
PHY_WRITE(sc, 4, val);
sys/dev/mii/rgephy.c
511
val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
sys/dev/mii/rgephy.c
512
PHY_WRITE(sc, 4, val);
sys/dev/mii/rgephy.c
517
val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
sys/dev/mii/rgephy.c
518
PHY_WRITE(sc, 4, val);
sys/dev/mii/rgephy.c
523
val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
sys/dev/mii/rgephy.c
524
PHY_WRITE(sc, 4, val);
sys/dev/mii/rgephy.c
529
val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
sys/dev/mii/rgephy.c
530
PHY_WRITE(sc, 4, val);
sys/dev/ofw/fdt.c
1055
uint32_t val;
sys/dev/ofw/fdt.c
1058
len = OF_getprop(handle, prop, &val, sizeof(val));
sys/dev/ofw/fdt.c
1059
if (len != sizeof(val))
sys/dev/ofw/fdt.c
1062
return betoh32(val);
sys/dev/ofw/fdt.c
1084
uint64_t val;
sys/dev/ofw/fdt.c
1087
len = OF_getprop(handle, prop, &val, sizeof(val));
sys/dev/ofw/fdt.c
1088
if (len != sizeof(val))
sys/dev/ofw/fdt.c
1091
return betoh64(val);
sys/dev/ofw/ofw_gpio.c
106
int val = 0;
sys/dev/ofw/ofw_gpio.c
114
val = gc->gc_get_pin(gc->gc_cookie, &cells[1]);
sys/dev/ofw/ofw_gpio.c
116
return val;
sys/dev/ofw/ofw_gpio.c
120
gpio_controller_set_pin(uint32_t *cells, int val)
sys/dev/ofw/ofw_gpio.c
131
gc->gc_set_pin(gc->gc_cookie, &cells[1], val);
sys/dev/onewire/owtemp.c
145
int count_perc, count_remain, val;
sys/dev/onewire/owtemp.c
182
val = temp * (1000000 / 16);
sys/dev/onewire/owtemp.c
191
val = temp * 500000 - 250000 +
sys/dev/onewire/owtemp.c
195
val = temp * 500000;
sys/dev/onewire/owtemp.c
198
sc->sc_sensor.value = 273150000 + val;
sys/dev/pci/amdiic.c
208
amdiic_write(struct amdiic_softc *sc, u_int8_t reg, u_int8_t val)
sys/dev/pci/amdiic.c
219
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMD8111_SMB_SC_DATA, val);
sys/dev/pci/auacer.c
277
int val = READ1(sc, ALI_CSPSR);
sys/dev/pci/auacer.c
278
if (val & mask)
sys/dev/pci/auacer.c
299
auacer_read_codec(void *v, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auacer.c
314
*val = READ2(sc, ALI_SPR);
sys/dev/pci/auacer.c
317
reg, *val));
sys/dev/pci/auacer.c
323
auacer_write_codec(void *v, u_int8_t reg, u_int16_t val)
sys/dev/pci/auacer.c
328
reg, val));
sys/dev/pci/auacer.c
332
WRITE2(sc, ALI_CPR, val);
sys/dev/pci/auacer.c
509
uint32_t val;
sys/dev/pci/auacer.c
519
val = READ4(sc, ALI_DMACR);
sys/dev/pci/auacer.c
520
val |= 1 << (slot+16); /* pause */
sys/dev/pci/auacer.c
521
val &= ~(1 << slot); /* no start */
sys/dev/pci/auacer.c
522
WRITE4(sc, ALI_DMACR, val);
sys/dev/pci/auacer.c
717
uint32_t offs, val;
sys/dev/pci/auacer.c
740
val = READ4(sc, ALI_DMACR);
sys/dev/pci/auacer.c
741
val &= ~(1 << (slot+16)); /* no pause */
sys/dev/pci/auacer.c
742
val |= 1 << slot; /* start */
sys/dev/pci/auacer.c
743
WRITE4(sc, ALI_DMACR, val);
sys/dev/pci/auglx.c
332
auglx_read_codec(void *v, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auglx.c
367
*val = codec_status & 0xffff;
sys/dev/pci/auglx.c
369
sc->sc_dev.dv_xname, reg, *val));
sys/dev/pci/auglx.c
374
auglx_write_codec(void *v, u_int8_t reg, u_int16_t val)
sys/dev/pci/auglx.c
381
sc->sc_dev.dv_xname, reg, val));
sys/dev/pci/auglx.c
384
codec_cntl = ((u_int32_t)reg << 24) | CMD_NEW | val;
sys/dev/pci/auich.c
538
auich_read_codec(void *v, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auich.c
553
*val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg);
sys/dev/pci/auich.c
555
sc->sc_dev.dv_xname, reg, *val));
sys/dev/pci/auich.c
560
auich_write_codec(void *v, u_int8_t reg, u_int16_t val)
sys/dev/pci/auich.c
571
sc->sc_dev.dv_xname, reg, val));
sys/dev/pci/auich.c
572
bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val);
sys/dev/pci/auvia.c
422
auvia_write_codec(void *addr, u_int8_t reg, u_int16_t val)
sys/dev/pci/auvia.c
430
AUVIA_CODEC_PRIVALID | AUVIA_CODEC_INDEX(reg) | val);
sys/dev/pci/auvia.c
437
auvia_read_codec(void *addr, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auvia.c
453
*val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, AUVIA_CODEC_CTL);
sys/dev/pci/azalia.c
348
azalia_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val)
sys/dev/pci/azalia.c
354
pcival |= (val << ((reg & 0x03) * 8));
sys/dev/pci/azalia_codec.c
2587
azalia_pin_config_ov(widget_t *w, int mask, int val)
sys/dev/pci/azalia_codec.c
2603
val &= bits;
sys/dev/pci/azalia_codec.c
2605
w->d.pin.config |= val << offset;
sys/dev/pci/azalia_codec.c
2607
w->d.pin.device = val;
sys/dev/pci/berkwdt.c
104
msb = *val / 256;
sys/dev/pci/berkwdt.c
105
lsb = *val % 256;
sys/dev/pci/berkwdt.c
124
*val = (msb << 8) + lsb;
sys/dev/pci/berkwdt.c
52
int berkwdt_send_command(struct berkwdt_softc *sc, u_int8_t cmd, int *val);
sys/dev/pci/berkwdt.c
97
berkwdt_send_command(struct berkwdt_softc *sc, u_int8_t cmd, int *val)
sys/dev/pci/bktr/bktr_audio.c
348
bctv_gpio_write( bktr_ptr_t bktr, int port, int val )
sys/dev/pci/bktr/bktr_audio.c
356
data = ((val << BCTV_GPIO_VAL_SHIFT) & BCTV_GPIO_VAL_MASK) |
sys/dev/pci/bktr/bktr_audio.c
65
void bctv_gpio_write( bktr_ptr_t bktr, int port, int val );
sys/dev/pci/cmpci.c
1221
cmpci_adjust(int val, int mask)
sys/dev/pci/cmpci.c
1223
val += (MAXVAL - mask) >> 1;
sys/dev/pci/cmpci.c
1224
if (val >= MAXVAL)
sys/dev/pci/cmpci.c
1225
val = MAXVAL-1;
sys/dev/pci/cmpci.c
1226
return val & mask;
sys/dev/pci/cmpci.c
184
cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val)
sys/dev/pci/cmpci.c
188
bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val);
sys/dev/pci/cmpci.c
195
unsigned mask, unsigned val)
sys/dev/pci/cmpci.c
198
(val<<shift) |
sys/dev/pci/cmpci.c
205
uint32_t mask, uint32_t val)
sys/dev/pci/cmpci.c
208
(val<<shift) |
sys/dev/pci/com_pci.c
34
#define HWRITE4(sc, reg, val) \
sys/dev/pci/com_pci.c
35
bus_space_write_4((sc)->sc.sc_iot, (sc)->sc.sc_ioh, (reg), (val))
sys/dev/pci/cs4280.c
1110
int val;
sys/dev/pci/cs4280.c
1112
val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
sys/dev/pci/cs4280.c
1113
DPRINTFN(3,("mixer_set_port: val=%d\n", val));
sys/dev/pci/cs4280.c
1114
return (val);
sys/dev/pci/cs4281.c
1107
int val;
sys/dev/pci/cs4281.c
1110
val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
sys/dev/pci/cs4281.c
1111
DPRINTFN(3,("mixer_set_port: val=%d\n", val));
sys/dev/pci/cs4281.c
1112
return (val);
sys/dev/pci/cs4281.c
329
u_int32_t intr, val;
sys/dev/pci/cs4281.c
341
val = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
sys/dev/pci/cs4281.c
343
val = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
sys/dev/pci/cs4281.c
360
val = BA0READ4(sc, CS4281_HDSR1);
sys/dev/pci/cy82c693.c
90
cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
sys/dev/pci/cy82c693.c
96
bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1, val);
sys/dev/pci/cz.c
203
#define CZ_PLX_WRITE(cz, reg, val) \
sys/dev/pci/cz.c
205
(reg), (val))
sys/dev/pci/cz.c
213
#define CZ_FPGA_WRITE(cz, reg, val) \
sys/dev/pci/cz.c
214
bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))
sys/dev/pci/cz.c
223
#define CZ_FWCTL_WRITE(cz, off, val) \
sys/dev/pci/cz.c
225
(cz)->cz_fwctl + (off), (val))
sys/dev/pci/cz.c
233
#define CZTTY_CHAN_WRITE(sc, off, val) \
sys/dev/pci/cz.c
235
(off), (val))
sys/dev/pci/cz.c
240
#define CZTTY_BUF_WRITE(sc, off, val) \
sys/dev/pci/cz.c
242
(off), (val))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1505
#define WREG32_P(reg, val, mask) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1509
tmp_ |= ((val) & ~(mask)); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1514
#define WREG32_PLL_P(reg, val, mask) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1518
tmp_ |= ((val) & ~(mask)); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1542
#define WREG32_FIELD(reg, field, val) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1543
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1545
#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1546
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
885
static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
890
ret = amdgpu_ras_set_aca_debug_mode(adev, val ? true : false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
894
dev_info(adev->dev, "amdgpu set smu aca debug mode %s success\n", val ? "on" : "off");
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
229
u32 val = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
447
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
449
val |= ACP_SOFT_RESET__SoftResetAud_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
450
cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
454
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
456
(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
466
val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
467
val = val | ACP_CONTROL__ClkEn_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
468
cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
473
val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
474
if (val & (u32) 0x1)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
484
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
485
val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
486
cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
505
u32 val = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
516
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
518
val |= ACP_SOFT_RESET__SoftResetAud_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
519
cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
523
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
525
(val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
534
val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
535
val &= ~ACP_CONTROL__ClkEn_MASK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
536
cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
541
val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
542
if (val & (u32) 0x1)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1228
unsigned long val,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1740
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1768
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1782
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1786
WREG32(reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
447
uint64_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
469
new_coherent_mode = val ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
485
if (amdgpu_connector->audio != val) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
486
amdgpu_connector->audio = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
500
if (amdgpu_connector->dither != val) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
501
amdgpu_connector->dither = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
514
if (amdgpu_encoder->underscan_type != val) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
515
amdgpu_encoder->underscan_type = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
528
if (amdgpu_encoder->underscan_hborder != val) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
529
amdgpu_encoder->underscan_hborder = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
542
if (amdgpu_encoder->underscan_vborder != val) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
543
amdgpu_encoder->underscan_vborder = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
552
if (val == 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
569
switch (val) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1710
static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1722
*val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1731
static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1743
*val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1751
static int amdgpu_debugfs_benchmark(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1763
r = amdgpu_benchmark(adev, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1912
static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1919
if (val >= AMDGPU_MAX_RINGS)
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1922
ring = adev->rings[val];
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1987
static int amdgpu_debugfs_sclk_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
2007
if (ret || val > max_freq || val < min_freq) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
2012
ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
1035
static int gpu_recover_get(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
1050
*val = atomic_read(&adev->reset_domain->reset_res);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2365
static int amdgpu_debugfs_gfx_sched_mask_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2376
if ((val & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2381
if (val & (1 << i))
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2391
static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2406
*val = mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2435
static int amdgpu_debugfs_compute_sched_mask_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2446
if ((val & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2451
if (val & (1 << i))
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2462
static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2477
*val = mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
108
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
111
val = RREG32(rec->y_clk_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
112
val &= rec->y_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
114
return (val != 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
123
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
126
val = RREG32(rec->y_data_reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
127
val &= rec->y_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
129
return (val != 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
137
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
140
val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
141
val |= clock ? 0 : rec->en_clk_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
142
WREG32(rec->en_clk_reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
150
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
153
val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
154
val |= data ? 0 : rec->en_data_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
155
WREG32(rec->en_data_reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
374
u8 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
401
*val = in_buf[0];
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
402
DRM_DEBUG("val = 0x%02x\n", *val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
410
u8 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
421
out_buf[1] = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
424
DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", addr, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
435
u8 val = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
445
0x3, &val))
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
447
val &= ~amdgpu_connector->router.ddc_mux_control_pin;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
450
0x3, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
453
0x1, &val))
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
455
val &= ~amdgpu_connector->router.ddc_mux_control_pin;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
456
val |= amdgpu_connector->router.ddc_mux_state;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
459
0x1, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
466
u8 val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
476
0x3, &val))
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
478
val &= ~amdgpu_connector->router.cd_mux_control_pin;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
481
0x3, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
484
0x1, &val))
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
486
val &= ~amdgpu_connector->router.cd_mux_control_pin;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
487
val |= amdgpu_connector->router.cd_mux_state;
sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c
490
0x1, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
358
static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
369
if ((val & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
375
if (val & (BIT_ULL((i * adev->jpeg.num_jpeg_rings) + j)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
386
static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
402
*val = mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c
33
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c
37
val = RREG32(reg_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c
38
if ((val & mask) == reg_val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
519
static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
524
ret = amdgpu_ras_set_mca_debug_mode(adev, val ? true : false);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
528
dev_info(adev->dev, "amdgpu set smu mca debug mode %s success\n", val ? "on" : "off");
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
442
int r, val = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
468
val = *(read_val_ptr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
473
return val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
477
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
484
op_input.write_reg.reg_value = val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
429
uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
583
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
591
val = RREG32(reg_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
593
if (val != reg_val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
596
if ((val & mask) == reg_val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
605
reg_index, mask, val, reg_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
613
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
621
val = RREG32(reg_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
622
if ((val & mask) == reg_val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
173
int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
523
#define psp_reg_program_no_ring(psp, val, id) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
525
(psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
621
int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
281
char val[128];
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
293
s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
303
if (copy_to_user(buf, &val[*pos], s))
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3308
u64 val = adev->gmc.mc_vram_size;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3310
do_div(val, RAS_BAD_PAGE_COVER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3311
con->bad_page_cnt_threshold = min(lower_32_bits(val),
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4764
unsigned long val, void *data)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
70
#define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
627
static int amdgpu_debugfs_ring_error(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
631
amdgpu_fence_driver_set_error(ring, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
275
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
277
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
351
static int amdgpu_debugfs_sdma_sched_mask_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
374
if ((val & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
381
if (val & BIT_ULL(i * num_ring))
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
387
if (val & BIT_ULL(i * num_ring + 1))
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
398
static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
434
*val = mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1398
static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1409
if ((val & mask) == 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1413
if (val & (1ULL << i))
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1423
static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1437
*val = mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
337
uint64_t val;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
592
static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
598
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
602
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
612
amdgpu_ring_write(ring, val); /* reference */
sys/dev/pci/drm/amd/amdgpu/atom.c
1028
uint32_t src, val, target;
sys/dev/pci/drm/amd/amdgpu/atom.c
1035
val =
sys/dev/pci/drm/amd/amdgpu/atom.c
1039
if (val == src) {
sys/dev/pci/drm/amd/amdgpu/atom.c
1080
uint8_t val = U8((*ptr)++);
sys/dev/pci/drm/amd/amdgpu/atom.c
1081
SDEBUG("DEBUG output: 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
1086
uint16_t val = U16(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
1087
(*ptr) += val + 2;
sys/dev/pci/drm/amd/amdgpu/atom.c
1088
SDEBUG("PROCESSDS output: 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
189
uint32_t idx, val = 0xCDCDCDCD, align, arg;
sys/dev/pci/drm/amd/amdgpu/atom.c
202
val = gctx->card->reg_read(gctx->card, idx);
sys/dev/pci/drm/amd/amdgpu/atom.c
220
val =
sys/dev/pci/drm/amd/amdgpu/atom.c
232
val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
sys/dev/pci/drm/amd/amdgpu/atom.c
236
DEBUG("PS[0x%02X,0x%04X]", idx, val);
sys/dev/pci/drm/amd/amdgpu/atom.c
245
val = gctx->divmul[0];
sys/dev/pci/drm/amd/amdgpu/atom.c
248
val = gctx->divmul[1];
sys/dev/pci/drm/amd/amdgpu/atom.c
251
val = gctx->data_block;
sys/dev/pci/drm/amd/amdgpu/atom.c
254
val = gctx->shift;
sys/dev/pci/drm/amd/amdgpu/atom.c
257
val = 1 << gctx->shift;
sys/dev/pci/drm/amd/amdgpu/atom.c
260
val = ~(1 << gctx->shift);
sys/dev/pci/drm/amd/amdgpu/atom.c
263
val = gctx->fb_base;
sys/dev/pci/drm/amd/amdgpu/atom.c
266
val = gctx->io_attr;
sys/dev/pci/drm/amd/amdgpu/atom.c
269
val = gctx->reg_block;
sys/dev/pci/drm/amd/amdgpu/atom.c
273
val = ctx->ws[idx];
sys/dev/pci/drm/amd/amdgpu/atom.c
287
val = U32(idx + gctx->data_block);
sys/dev/pci/drm/amd/amdgpu/atom.c
295
val = 0;
sys/dev/pci/drm/amd/amdgpu/atom.c
297
val = gctx->scratch[(gctx->fb_base / 4) + idx];
sys/dev/pci/drm/amd/amdgpu/atom.c
304
val = U32(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
307
DEBUG("IMM 0x%08X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
312
val = U16(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
315
DEBUG("IMM 0x%04X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
321
val = U8(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
324
DEBUG("IMM 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
327
return val;
sys/dev/pci/drm/amd/amdgpu/atom.c
333
val = gctx->card->pll_read(gctx->card, idx);
sys/dev/pci/drm/amd/amdgpu/atom.c
340
val = gctx->card->mc_read(gctx->card, idx);
sys/dev/pci/drm/amd/amdgpu/atom.c
344
*saved = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
345
val &= atom_arg_mask[align];
sys/dev/pci/drm/amd/amdgpu/atom.c
346
val >>= atom_arg_shift[align];
sys/dev/pci/drm/amd/amdgpu/atom.c
350
DEBUG(".[31:0] -> 0x%08X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
353
DEBUG(".[15:0] -> 0x%04X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
356
DEBUG(".[23:8] -> 0x%04X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
359
DEBUG(".[31:16] -> 0x%04X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
362
DEBUG(".[7:0] -> 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
365
DEBUG(".[15:8] -> 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
368
DEBUG(".[23:16] -> 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
371
DEBUG(".[31:24] -> 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.c
374
return val;
sys/dev/pci/drm/amd/amdgpu/atom.c
419
uint32_t val = 0xCDCDCDCD;
sys/dev/pci/drm/amd/amdgpu/atom.c
423
val = U32(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
429
val = U16(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
436
val = U8(*ptr);
sys/dev/pci/drm/amd/amdgpu/atom.c
440
return val;
sys/dev/pci/drm/amd/amdgpu/atom.c
460
int *ptr, uint32_t val, uint32_t saved)
sys/dev/pci/drm/amd/amdgpu/atom.c
464
val, idx;
sys/dev/pci/drm/amd/amdgpu/atom.c
467
val <<= atom_arg_shift[align];
sys/dev/pci/drm/amd/amdgpu/atom.c
468
val &= atom_arg_mask[align];
sys/dev/pci/drm/amd/amdgpu/atom.c
470
val |= saved;
sys/dev/pci/drm/amd/amdgpu/atom.c
481
val << 2);
sys/dev/pci/drm/amd/amdgpu/atom.c
483
gctx->card->reg_write(gctx->card, idx, val);
sys/dev/pci/drm/amd/amdgpu/atom.c
502
idx, val);
sys/dev/pci/drm/amd/amdgpu/atom.c
513
ctx->ps[idx] = cpu_to_le32(val);
sys/dev/pci/drm/amd/amdgpu/atom.c
521
gctx->divmul[0] = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
524
gctx->divmul[1] = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
527
gctx->data_block = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
530
gctx->shift = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
536
gctx->fb_base = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
539
gctx->io_attr = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
542
gctx->reg_block = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
549
ctx->ws[idx] = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
559
gctx->scratch[(gctx->fb_base / 4) + idx] = val;
sys/dev/pci/drm/amd/amdgpu/atom.c
566
gctx->card->pll_write(gctx->card, idx, val);
sys/dev/pci/drm/amd/amdgpu/atom.c
572
gctx->card->mc_write(gctx->card, idx, val);
sys/dev/pci/drm/amd/amdgpu/atom.c
867
uint8_t val = U8((*ptr)++);
sys/dev/pci/drm/amd/amdgpu/atom.c
868
SDEBUG("POST card output: 0x%02X\n", val);
sys/dev/pci/drm/amd/amdgpu/atom.h
122
u32 reg, uint32_t val); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
125
u32 reg, uint32_t val); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
128
u32 reg, uint32_t val); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/cik.c
1127
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/cik.c
1146
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/cik.c
1151
return val;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
866
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
870
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1536
uint32_t offset, val;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1566
val = RREG32(mmHDMI_CONTROL + offset);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1567
val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1568
val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1580
val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1581
val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1586
val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1587
val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1593
WREG32(mmHDMI_CONTROL + offset, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4001
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4008
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9005
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9024
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9028
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9030
gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
342
uint32_t val);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4972
u32 i, tmp, val;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4980
val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4982
if (val == tmp)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4989
if (val != tmp)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
516
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
523
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6291
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6310
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6314
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6316
gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
282
uint32_t val);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4655
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4674
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4678
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4680
gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2408
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2417
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3180
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3189
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6324
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6344
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6769
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6772
val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6792
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6800
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6807
val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6808
amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1161
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1169
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5872
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5891
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5895
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5897
gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7103
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7107
val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7127
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7133
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7141
val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7144
val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3012
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3033
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3037
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3039
gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3416
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3420
val = enable ? 0x1 : 0x7f;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3440
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3446
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3453
val = enable ? 0x1f : 0x07ffffff;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3456
val);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
376
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
385
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
288
u32 val, inst_index;
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
293
val = inst_index >> 5;
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
295
val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 |
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
302
return val;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
102
ring->ring[ptr++] = val;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
123
val = 0;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
124
jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
129
val = 0x12;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
130
jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
354
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
366
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
399
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
416
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
42
static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
54
ring->ring[(*ptr)++] = val;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
61
uint32_t reg, reg_offset, val, mask, i;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
66
val = lower_32_bits(ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
67
jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
72
val = upper_32_bits(ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
73
jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
84
val = 0x13;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
85
jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
90
val = 0x1;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
91
jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
96
val = 0x1;
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
614
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
624
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
655
void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
670
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h
55
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h
58
void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
927
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
943
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
974
void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
995
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h
70
void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h
72
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
383
u32 i, tmp, val;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
391
val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
393
if (val == tmp)
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
400
if (val != tmp)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
42
static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
44
WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
41
static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
43
WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
343
static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
349
TRN_MSG_VALID, val ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/nv.c
360
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/nv.c
366
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/nv.c
371
return val;
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
924
static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
934
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
804
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
809
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1077
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1082
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1723
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1728
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1732
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1734
sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1319
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1324
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1328
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1330
sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
165
u32 val;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
169
val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
170
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
171
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
173
WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
175
val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
176
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
178
val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
180
WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1298
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1303
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1307
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1314
amdgpu_ring_write(ring, val); /* reference */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1219
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1224
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1228
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1235
amdgpu_ring_write(ring, val); /* reference */
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1222
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1227
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1231
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1238
amdgpu_ring_write(ring, val); /* reference */
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1222
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1229
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1233
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1240
amdgpu_ring_write(ring, val); /* reference */
sys/dev/pci/drm/amd/amdgpu/si.c
1183
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/si.c
1200
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/si.c
1205
return val;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
469
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/si_dma.c
473
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/soc15.c
407
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/soc15.c
413
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc15.c
418
return val;
sys/dev/pci/drm/amd/amdgpu/soc15.h
105
#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift)
sys/dev/pci/drm/amd/amdgpu/soc15.h
107
#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
184
#define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
188
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
210
#define WREG64_MCA(ext, mca_base, idx, val) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
211
WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
50
#define WREG32_FIELD15(ip, idx, reg, field, val) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
55
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
58
#define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
63
~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \
sys/dev/pci/drm/amd/amdgpu/soc21.c
281
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/soc21.c
287
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc21.c
292
return val;
sys/dev/pci/drm/amd/amdgpu/soc24.c
140
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/soc24.c
146
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/soc24.c
151
return val;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1067
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1072
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1369
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1378
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1385
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1394
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1437
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1443
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1460
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1464
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
553
uint32_t val = 0;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
556
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
558
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
731
uint32_t val = 0;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
734
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
736
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
742
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
747
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
764
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
768
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
776
uint32_t val = 0;
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
780
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
782
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
57
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
62
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
81
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
85
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h
38
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h
42
uint32_t val);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1617
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1627
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1652
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1661
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1772
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1778
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1795
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1799
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2103
uint32_t val = amdgpu_ib_get_value(ib, i + 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2106
msg_lo = val;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2108
msg_hi = val;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1594
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1602
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1628
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1636
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1764
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1769
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1785
void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1789
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
35
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
39
uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
48
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
51
extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2021
uint32_t val = amdgpu_ib_get_value(ib, i + 1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2024
msg_lo = val;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2026
msg_hi = val;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2028
val == 0) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1946
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1954
val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1955
if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1965
} else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1532
uint32_t val, uint32_t mask)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1541
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1545
uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1553
amdgpu_ring_write(ring, val);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h
36
uint32_t val, uint32_t mask);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h
39
uint32_t val);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
288
u32 val = 0;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
290
val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
291
val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
293
return val;
sys/dev/pci/drm/amd/amdgpu/vi.c
749
uint32_t val;
sys/dev/pci/drm/amd/amdgpu/vi.c
768
val = RREG32(reg_offset);
sys/dev/pci/drm/amd/amdgpu/vi.c
773
return val;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
357
static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val)
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
360
return get_user(*val, q_rptr + 1);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
104
uint64_t val;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
192
val = 0;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
193
ret = read_sdma_queue_counter(sdma_q->rptr, &val);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
198
sdma_q->sdma_val = val;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
199
workarea->sdma_activity_counter += val;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
721
uint32_t val = attrs[i].value;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
726
if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM &&
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
727
val != KFD_IOCTL_SVM_LOCATION_UNDEFINED)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
728
gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
731
if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
732
gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
737
gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
751
pr_debug("no GPU 0x%x found\n", val);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
755
pr_debug("GPU 0x%x not supported\n", val);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7382
uint64_t val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7396
switch (val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7418
dm_new_state->underscan_hborder = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7421
dm_new_state->underscan_vborder = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7424
dm_new_state->underscan_enable = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7434
uint64_t *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7445
*val = DRM_MODE_SCALE_CENTER;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7448
*val = DRM_MODE_SCALE_ASPECT;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7451
*val = DRM_MODE_SCALE_FULLSCREEN;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7455
*val = DRM_MODE_SCALE_NONE;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7460
*val = dm_state->underscan_hborder;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7463
*val = dm_state->underscan_vborder;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7466
*val = dm_state->underscan_enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7491
u8 val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7494
val = to_dm_connector_state(connector->state)->abm_level ==
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7499
return sysfs_emit(buf, "%u\n", val);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7510
long val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7513
ret = kstrtol(buf, 0, &val);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7518
if (val < 0 || val > 4)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7522
to_dm_connector_state(connector->state)->abm_level = val ?:
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1020
uint64_t val);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1025
uint64_t *val);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
90
struct fixed31_32 val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
96
val.value = x;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
97
return val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
531
uint64_t val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
537
if (acrtc_state->regamma_tf != val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
538
acrtc_state->regamma_tf = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
556
uint64_t *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
562
*val = acrtc_state->regamma_tf;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3075
static int force_yuv420_output_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3079
connector->force_yuv420_output = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3087
static int force_yuv420_output_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3091
*val = connector->force_yuv420_output;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3102
static int replay_get_state(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3110
*val = state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3118
static int replay_set_residency(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3122
bool is_start = (val != 0);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3132
static int replay_get_residency(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3139
*val = (u64)residency;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3147
static int psr_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3155
*val = state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3163
static int psr_read_residency(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3171
*val = (u64)residency;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3177
static int allow_edp_hotplug_detection_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3184
*val = adev->dm.dc->config.allow_edp_hotplug_detection;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3190
static int allow_edp_hotplug_detection_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3197
adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3206
static int disallow_edp_enter_psr_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3210
*val = (u64) aconnector->disallow_edp_enter_psr;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3241
static int disallow_edp_enter_psr_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3245
aconnector->disallow_edp_enter_psr = val ? true : false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3249
static int dmub_trace_mask_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3263
res = (val & mask) >> shift;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3292
static int dmub_trace_mask_show(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3320
*val = res;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3333
static int dmcub_trace_event_state_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3337
if (val == 1 || val == 0) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3338
dc_dmub_trace_event_control(adev->dm.dc, val);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3339
adev->dm.dmcub_trace_event_en = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3351
static int dmcub_trace_event_state_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3355
*val = adev->dm.dmcub_trace_event_en;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3579
static int crc_win_x_start_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3586
acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3596
static int crc_win_x_start_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3603
*val = acrtc->dm_irq_params.window_param[0].x_start;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3616
static int crc_win_y_start_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3623
acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3633
static int crc_win_y_start_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3640
*val = acrtc->dm_irq_params.window_param[0].y_start;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3652
static int crc_win_x_end_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3659
acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3669
static int crc_win_x_end_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3676
*val = acrtc->dm_irq_params.window_param[0].x_end;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3688
static int crc_win_y_end_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3695
acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3705
static int crc_win_y_end_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3712
*val = acrtc->dm_irq_params.window_param[0].y_end;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3723
static int crc_win_update_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3729
if (val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3754
static int crc_win_update_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3756
*val = 0;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3885
static int trigger_hpd_mst_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3895
if (val == 1) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3913
} else if (val == 0) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3943
static int trigger_hpd_mst_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3945
*val = 0;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3958
static int force_timing_sync_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3962
adev->dm.force_timing_sync = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3973
static int force_timing_sync_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3977
*val = adev->dm.force_timing_sync;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3990
static int disable_hpd_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3994
adev->dm.disable_hpd_irq = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4004
static int disable_hpd_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4008
*val = adev->dm.disable_hpd_irq;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4050
static int dp_force_sst_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4054
adev->dm.dc->debug.set_mst_en_for_sst = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4059
static int dp_force_sst_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4063
*val = adev->dm.dc->debug.set_mst_en_for_sst;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4074
static int dp_ignore_cable_id_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4078
adev->dm.dc->debug.ignore_cable_id = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4083
static int dp_ignore_cable_id_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4087
*val = adev->dm.dc->debug.ignore_cable_id;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4098
static int visual_confirm_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4102
adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4111
static int visual_confirm_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4115
*val = adev->dm.dc->debug.visual_confirm;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4129
static int skip_detection_link_training_set(void *data, u64 val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4133
if (val == 0)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4145
static int skip_detection_link_training_get(void *data, u64 *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4149
*val = adev->dm.dc->debug.skip_detection_link_training;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1673
uint64_t val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1683
val, -1,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1689
if (dm_plane_state->degamma_tf != val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1690
dm_plane_state->degamma_tf = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1694
if (dm_plane_state->hdr_mult != val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1695
dm_plane_state->hdr_mult = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1701
val,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1709
val, -1,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1715
if (dm_plane_state->shaper_tf != val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1716
dm_plane_state->shaper_tf = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1722
val, -1,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1730
val, -1,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1736
if (dm_plane_state->blend_tf != val) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1737
dm_plane_state->blend_tf = val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1755
uint64_t *val)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1761
*val = (dm_plane_state->degamma_lut) ?
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1764
*val = dm_plane_state->degamma_tf;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1766
*val = dm_plane_state->hdr_mult;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1768
*val = (dm_plane_state->ctm) ?
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1771
*val = (dm_plane_state->shaper_lut) ?
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1774
*val = dm_plane_state->shaper_tf;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1776
*val = (dm_plane_state->lut3d) ?
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1779
*val = (dm_plane_state->blend_lut) ?
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1782
*val = dm_plane_state->blend_tf;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
225
const uint16_t *val = NULL;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
231
val = output_csc_matrix[i].regval;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
236
return val;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2071
uint32_t val = 0;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2085
val,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2092
val,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2097
dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERTICAL_INTERRUPT0_POSITION), val);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
48
#define CRTC_REG_UPDATE(reg, field, val) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
49
CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
63
#define CRTC_REG_SET(reg, field, val) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
64
CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1377
#define HPD_REG_UPDATE(reg_name, field, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1379
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1408
#define AUX_REG_UPDATE(reg_name, field, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1410
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
306
#define AUX_REG_WRITE(reg_name, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
307
dm_write_reg(CTX, AUX_REG(reg_name), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
214
#define AUX_REG_WRITE(reg_name, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
215
dm_write_reg(CTX, AUX_REG(reg_name), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
63
#define AUX_REG_WRITE(reg_name, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
64
dm_write_reg(CTX, AUX_REG(reg_name), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
62
#define AUX_REG_WRITE(reg_name, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
63
dm_write_reg(CTX, AUX_REG(reg_name), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
59
#define AUX_REG_WRITE(reg_name, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
60
dm_write_reg(CTX, AUX_REG(reg_name), val)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
61
#define AUX_REG_WRITE(reg_name, val) \
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
62
dm_write_reg(CTX, AUX_REG(reg_name), val)
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
109
static inline double dml_fmod(double f, int val)
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
111
return (double) dcn_bw_mod(f, val);
sys/dev/pci/drm/amd/display/dc/dml2/cmntypes.h
70
uint32 val;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
179
dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
186
double ceil = dml_ceil(val, 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
187
double floor = dml_floor(val, 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
189
if (val - floor >= round_pt)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
46
dml_bool_t val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
50
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
53
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
56
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
59
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
62
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
65
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
68
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
74
return val;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
49
__DML_DLL_EXPORT__ dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
704
enum dml2_uclk_pstate_change_strategy val = dml2_uclk_pstate_change_strategy_auto;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
708
val = dml2_uclk_pstate_change_strategy_force_vactive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
711
val = dml2_uclk_pstate_change_strategy_force_vblank;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
714
val = dml2_uclk_pstate_change_strategy_force_drr;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
717
val = dml2_uclk_pstate_change_strategy_force_mall_svp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
721
val = dml2_uclk_pstate_change_strategy_auto;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
724
return val;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
444
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
448
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
451
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
454
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
457
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
460
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
463
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
466
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
469
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
472
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
475
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
478
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
481
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
484
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
487
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
490
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
493
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
496
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
502
return val;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
100
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
103
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
106
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
109
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
112
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
115
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
118
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
121
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
124
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
127
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
130
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
133
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
136
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
139
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
142
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
145
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
151
return val;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
156
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
160
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
163
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
166
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
169
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
172
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
175
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
178
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
181
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
184
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
187
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
190
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
193
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
196
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
199
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
202
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
205
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
208
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
214
return val;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
30
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
34
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
37
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
40
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
43
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
46
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
49
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
52
val = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
55
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
58
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
61
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
64
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
67
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
70
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
73
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
76
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
79
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
82
val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
88
return val;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
93
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
97
val = 0;
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
52
uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
60
val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
71
REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
76
REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
156
#define REG_GET(reg_name, field, val) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
158
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
218
#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
220
REG(reg_name), FN(reg_name, field), val,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
230
#define REG_UPDATE(reg_name, field, val) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
232
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
383
{ uint32_t val = REG_UPDATE(reg, f1, v1); \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
384
REG_SET(reg, val, f2, v2); }
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
387
{ uint32_t val = REG_UPDATE(reg, f1, v1); \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
388
val = REG_SET(reg, val, f2, v2); \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
389
REG_SET(reg, val, f3, v3); }
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
466
#define IX_REG_GET(index_reg_name, data_reg_name, index, field, val) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
468
FN(data_reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
525
#define IX_REG_GET_SYNC(index, field, val) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
527
FN(data_reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
63
#define REG_SET(reg_name, initial_val, field, val) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
65
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
226
uint8_t val;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
233
val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
235
if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
470
uint32_t val = 0xf;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
473
REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
475
return val;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
171
#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
111
#define REG_GET(reg_name, field, val) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
112
dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
53
#define REG_WRITE(reg, val) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
54
((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
61
#define REG_SET(reg_name, initial_val, field, val) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
63
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
88
#define REG_UPDATE(reg_name, field, val) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
90
FN(reg_name, field), val)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
91
static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
93
return (val + factor - 1) / factor * factor;
sys/dev/pci/drm/amd/include/cgs_common.h
130
#define CGS_WREG32_FIELD(device, reg, field, val) \
sys/dev/pci/drm/amd/include/cgs_common.h
131
cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/include/cgs_common.h
133
#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
sys/dev/pci/drm/amd/include/cgs_common.h
134
cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2422
long val;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2435
ret = kstrtol(param, 0, &val);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
2453
ret = amdgpu_dpm_set_pm_policy(adev, policy_attr->id, val);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3284
ssize_t val;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3286
val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3287
if (val < 0)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3288
return val;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3290
return sysfs_emit(buf, "%zd\n", val);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3297
ssize_t val;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3299
val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3300
if (val < 0)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3301
return val;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
3303
return sysfs_emit(buf, "%zd\n", val);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
115
entry[i].shift, entry[i].val, entry[i].timeout))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
94
entry[i].shift, entry[i].val, entry[i].timeout))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h
42
uint32_t val;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h
54
uint32_t val;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1713
uint32_t val = cgs_read_ind_register(hwmgr->device,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1715
uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1717
if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
368
uint32_t val;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
389
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
391
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
392
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
393
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
394
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
395
val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
399
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
436
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
450
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
451
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
452
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
454
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
178
uint32_t val;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
189
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
191
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
192
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
193
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
194
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
195
val &= ~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
196
val &= ~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
197
val &= ~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
199
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
212
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
214
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
215
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
216
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
218
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
249
uint32_t val;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
260
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
262
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
263
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
264
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
265
val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
266
val &= ~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
267
val &= ~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
268
val &= ~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
270
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
283
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
285
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
286
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
287
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
289
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
186
uint32_t val;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
211
val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
214
ixSMC_SYSCON_MISC_CNTL, val | 1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
80
uint32_t val = cgs_read_register(hwmgr->device,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
83
__func__, msg, val);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
458
uint32_t val;
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
462
val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
464
(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
372
uint32_t val;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
376
val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
378
(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2511
uint32_t val;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2530
val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2531
return val != 0x0;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
369
uint32_t val;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
372
val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
374
(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1341
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1346
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1347
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1348
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1349
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1354
val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1355
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1356
WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1366
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1367
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1368
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1369
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1370
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1371
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1372
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1373
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1374
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1376
val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1377
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1378
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1379
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1382
val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1383
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1384
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1385
WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1387
val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1388
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1389
WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
2009
uint32_t val;
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
2027
val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
2029
return val != 0x0;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1196
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1201
val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1202
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1203
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1204
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1209
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1210
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1211
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1221
val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1222
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1223
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1224
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1225
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1226
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1227
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1228
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1229
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1231
val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1232
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1233
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1234
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1237
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1238
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1239
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1240
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1242
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1243
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1244
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1926
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1931
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1932
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1933
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1938
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1939
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1940
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1941
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1943
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1944
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1945
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3285
int idx, int offset, uint32_t *val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3302
return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3306
int idx, int offset, uint32_t *val, int count)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3310
if (!val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3314
ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3353
int idx, int reg_idx, uint64_t *val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3359
if (!val || reg_idx >= MCA_REG_IDX_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3366
*val = (uint64_t)data[1] << 32 | data[0];
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3369
type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3394
static int mca_decode_ipid_to_hwip(uint64_t val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3400
hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3401
mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3769
int idx, int offset, u32 *val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3786
return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3790
int idx, int offset, u32 *val, int count)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3794
if (!val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3798
ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3807
int idx, int reg_idx, u64 *val)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3813
if (!val || reg_idx >= ACA_REG_IDX_COUNT)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3820
*val = (u64)data[1] << 32 | data[0];
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3823
type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
872
uint32_t val = 0;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
877
val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
878
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
879
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
880
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
886
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
887
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
888
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
890
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
891
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
892
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
902
val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
903
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
904
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
905
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
906
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
907
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
908
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
909
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
910
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
912
val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
913
val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
914
val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
915
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
919
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
920
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
921
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
922
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
924
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
925
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
926
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
928
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
929
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
930
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
931
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
933
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
934
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
935
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
sys/dev/pci/drm/apple/dcp_backlight.c
102
if (WARN(index + 1 >= tbl_size, "invalid index %zu for brightness %u\n", index, val))
sys/dev/pci/drm/apple/dcp_backlight.c
112
static u32 calculate_dac(struct apple_dcp *dcp, int val)
sys/dev/pci/drm/apple/dcp_backlight.c
116
if (val <= MIN_BRIGHTNESS_PART1)
sys/dev/pci/drm/apple/dcp_backlight.c
118
else if (val == MAX_BRIGHTNESS_PART1)
sys/dev/pci/drm/apple/dcp_backlight.c
120
else if (val == MIN_BRIGHTNESS_PART2)
sys/dev/pci/drm/apple/dcp_backlight.c
122
else if (val >= MAX_BRIGHTNESS_PART2)
sys/dev/pci/drm/apple/dcp_backlight.c
125
if (val < MAX_BRIGHTNESS_PART1) {
sys/dev/pci/drm/apple/dcp_backlight.c
126
dac = interpolate(val, MIN_BRIGHTNESS_PART1, MAX_BRIGHTNESS_PART1,
sys/dev/pci/drm/apple/dcp_backlight.c
128
} else if (val > MIN_BRIGHTNESS_PART2) {
sys/dev/pci/drm/apple/dcp_backlight.c
129
dac = interpolate(val, MIN_BRIGHTNESS_PART2, MAX_BRIGHTNESS_PART2,
sys/dev/pci/drm/apple/dcp_backlight.c
132
dac = interpolate(val, MAX_BRIGHTNESS_PART1, MIN_BRIGHTNESS_PART2,
sys/dev/pci/drm/apple/dcp_backlight.c
94
static u32 interpolate(int val, int min, int max, u32 *tbl, size_t tbl_size)
sys/dev/pci/drm/apple/dcp_backlight.c
98
u32 interpolated = (tbl_size - 1) * ((val - min) * SCALE_FACTOR) / (max - min);
sys/dev/pci/drm/apple/iomfb_template.c
1453
u32 val = 0;
sys/dev/pci/drm/apple/iomfb_template.c
1454
dcp_enable_disable_video_power_savings(dcp, false, &val, init_2, NULL);
sys/dev/pci/drm/display/drm_dp_helper.c
2963
u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
sys/dev/pci/drm/display/drm_dp_helper.c
2965
int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val);
sys/dev/pci/drm/display/drm_dp_helper.c
360
u8 val;
sys/dev/pci/drm/display/drm_dp_helper.c
362
if (drm_dp_dpcd_read_byte(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) < 0) {
sys/dev/pci/drm/display/drm_dp_helper.c
366
val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
sys/dev/pci/drm/display/drm_dp_helper.c
369
unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
sys/dev/pci/drm/display/drm_dp_helper.c
370
val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
sys/dev/pci/drm/display/drm_dp_helper.c
372
return (val + 1) * unit * 1000;
sys/dev/pci/drm/display/drm_dp_helper.c
476
u8 val = 1;
sys/dev/pci/drm/display/drm_dp_helper.c
489
ret = drm_dp_dpcd_readb(aux, DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST, &val);
sys/dev/pci/drm/display/drm_dp_helper.c
496
val = (val < sizeof(timeout_mapping) && timeout_mapping[val]) ?
sys/dev/pci/drm/display/drm_dp_helper.c
497
timeout_mapping[val] : 1;
sys/dev/pci/drm/display/drm_dp_helper.c
499
if (val > 1)
sys/dev/pci/drm/display/drm_dp_helper.c
504
ret = drm_dp_dpcd_readb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &val);
sys/dev/pci/drm/display/drm_dp_helper.c
511
val = (val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) ?
sys/dev/pci/drm/display/drm_dp_helper.c
512
(val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) * 10 : 1;
sys/dev/pci/drm/display/drm_dp_helper.c
514
if (val > 1)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1053
u8 val;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1056
if (drm_dp_dpcd_read_byte(aux, DP_TUNNELING_STATUS, &val) < 0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1059
*status_changed = val & status_change_mask;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1061
val &= bw_req_mask;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1063
if (!val)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1070
return val == DP_BW_REQUEST_SUCCEEDED ? 0 : -ENOSPC;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1198
u8 val;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1200
if (drm_dp_dpcd_read_byte(tunnel->aux, DP_TUNNELING_STATUS, &val) < 0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1203
val &= mask;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1205
if (val) {
sys/dev/pci/drm/display/drm_dp_tunnel.c
1206
if (drm_dp_dpcd_write_byte(tunnel->aux, DP_TUNNELING_STATUS, val) < 0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1219
if (drm_dp_dpcd_read_byte(tunnel->aux, DP_ESTIMATED_BW, &val) < 0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1222
if (val * tunnel->bw_granularity != tunnel->estimated_bw)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1302
u8 val;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1304
if (drm_dp_dpcd_read_byte(aux, DP_TUNNELING_STATUS, &val) < 0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1307
if (val & (DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED))
sys/dev/pci/drm/display/drm_dp_tunnel.c
1310
if (val & (DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED))
sys/dev/pci/drm/display/drm_dp_tunnel.c
915
u8 val;
sys/dev/pci/drm/display/drm_dp_tunnel.c
917
if (drm_dp_dpcd_read_byte(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL, &val) < 0)
sys/dev/pci/drm/display/drm_dp_tunnel.c
921
val |= mask;
sys/dev/pci/drm/display/drm_dp_tunnel.c
923
val &= ~mask;
sys/dev/pci/drm/display/drm_dp_tunnel.c
925
if (drm_dp_dpcd_write_byte(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL, val) < 0)
sys/dev/pci/drm/display/drm_hdcp_helper.c
21
drm_hdcp_update_content_protection(struct drm_connector *connector, u64 val)
sys/dev/pci/drm/drm_atomic_state_helper.c
249
u64 val;
sys/dev/pci/drm/drm_atomic_state_helper.c
260
&val))
sys/dev/pci/drm/drm_atomic_state_helper.c
261
plane_state->color_encoding = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
267
&val))
sys/dev/pci/drm/drm_atomic_state_helper.c
268
plane_state->color_range = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
274
&val)) {
sys/dev/pci/drm/drm_atomic_state_helper.c
275
plane_state->zpos = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
276
plane_state->normalized_zpos = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
283
&val))
sys/dev/pci/drm/drm_atomic_state_helper.c
284
plane_state->hotspot_x = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
290
&val))
sys/dev/pci/drm/drm_atomic_state_helper.c
291
plane_state->hotspot_y = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
512
uint64_t val;
sys/dev/pci/drm/drm_atomic_state_helper.c
517
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
518
state->tv.mode = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
526
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
527
state->tv.select_subconnector = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
532
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
533
state->tv.subconnector = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
538
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
539
state->tv.brightness = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
544
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
545
state->tv.contrast = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
550
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
551
state->tv.flicker_reduction = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
556
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
557
state->tv.overscan = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
562
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
563
state->tv.saturation = val;
sys/dev/pci/drm/drm_atomic_state_helper.c
568
prop, &val))
sys/dev/pci/drm/drm_atomic_state_helper.c
569
state->tv.hue = val;
sys/dev/pci/drm/drm_atomic_uapi.c
370
uint64_t val)
sys/dev/pci/drm/drm_atomic_uapi.c
378
state->active = val;
sys/dev/pci/drm/drm_atomic_uapi.c
381
drm_property_lookup_blob(dev, val);
sys/dev/pci/drm/drm_atomic_uapi.c
386
state->vrr_enabled = val;
sys/dev/pci/drm/drm_atomic_uapi.c
390
val,
sys/dev/pci/drm/drm_atomic_uapi.c
398
val,
sys/dev/pci/drm/drm_atomic_uapi.c
406
val,
sys/dev/pci/drm/drm_atomic_uapi.c
412
s32 __user *fence_ptr = u64_to_user_ptr(val);
sys/dev/pci/drm/drm_atomic_uapi.c
422
state->scaling_filter = val;
sys/dev/pci/drm/drm_atomic_uapi.c
424
return crtc->funcs->atomic_set_property(crtc, state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
439
struct drm_property *property, uint64_t *val)
sys/dev/pci/drm/drm_atomic_uapi.c
445
*val = drm_atomic_crtc_effectively_active(state);
sys/dev/pci/drm/drm_atomic_uapi.c
447
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
449
*val = state->vrr_enabled;
sys/dev/pci/drm/drm_atomic_uapi.c
451
*val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
453
*val = (state->ctm) ? state->ctm->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
455
*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
457
*val = 0;
sys/dev/pci/drm/drm_atomic_uapi.c
459
*val = state->scaling_filter;
sys/dev/pci/drm/drm_atomic_uapi.c
461
return crtc->funcs->atomic_get_property(crtc, state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
475
struct drm_property *property, uint64_t val)
sys/dev/pci/drm/drm_atomic_uapi.c
485
fb = drm_framebuffer_lookup(dev, file_priv, val);
sys/dev/pci/drm/drm_atomic_uapi.c
493
if (U642I64(val) == -1)
sys/dev/pci/drm/drm_atomic_uapi.c
496
state->fence = sync_file_get_fence(val);
sys/dev/pci/drm/drm_atomic_uapi.c
501
struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val);
sys/dev/pci/drm/drm_atomic_uapi.c
503
if (val && !crtc) {
sys/dev/pci/drm/drm_atomic_uapi.c
506
property->base.id, property->name, val);
sys/dev/pci/drm/drm_atomic_uapi.c
511
state->crtc_x = U642I64(val);
sys/dev/pci/drm/drm_atomic_uapi.c
513
state->crtc_y = U642I64(val);
sys/dev/pci/drm/drm_atomic_uapi.c
515
state->crtc_w = val;
sys/dev/pci/drm/drm_atomic_uapi.c
517
state->crtc_h = val;
sys/dev/pci/drm/drm_atomic_uapi.c
519
state->src_x = val;
sys/dev/pci/drm/drm_atomic_uapi.c
521
state->src_y = val;
sys/dev/pci/drm/drm_atomic_uapi.c
523
state->src_w = val;
sys/dev/pci/drm/drm_atomic_uapi.c
525
state->src_h = val;
sys/dev/pci/drm/drm_atomic_uapi.c
527
state->alpha = val;
sys/dev/pci/drm/drm_atomic_uapi.c
529
state->pixel_blend_mode = val;
sys/dev/pci/drm/drm_atomic_uapi.c
531
if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK)) {
sys/dev/pci/drm/drm_atomic_uapi.c
534
plane->base.id, plane->name, val);
sys/dev/pci/drm/drm_atomic_uapi.c
537
state->rotation = val;
sys/dev/pci/drm/drm_atomic_uapi.c
539
state->zpos = val;
sys/dev/pci/drm/drm_atomic_uapi.c
541
state->color_encoding = val;
sys/dev/pci/drm/drm_atomic_uapi.c
543
state->color_range = val;
sys/dev/pci/drm/drm_atomic_uapi.c
547
val,
sys/dev/pci/drm/drm_atomic_uapi.c
553
state->scaling_filter = val;
sys/dev/pci/drm/drm_atomic_uapi.c
556
property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
561
plane->base.id, plane->name, val);
sys/dev/pci/drm/drm_atomic_uapi.c
564
state->hotspot_x = val;
sys/dev/pci/drm/drm_atomic_uapi.c
569
plane->base.id, plane->name, val);
sys/dev/pci/drm/drm_atomic_uapi.c
572
state->hotspot_y = val;
sys/dev/pci/drm/drm_atomic_uapi.c
587
struct drm_property *property, uint64_t *val)
sys/dev/pci/drm/drm_atomic_uapi.c
593
*val = (state->fb) ? state->fb->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
595
*val = -1;
sys/dev/pci/drm/drm_atomic_uapi.c
597
*val = (state->crtc) ? state->crtc->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
599
*val = I642U64(state->crtc_x);
sys/dev/pci/drm/drm_atomic_uapi.c
601
*val = I642U64(state->crtc_y);
sys/dev/pci/drm/drm_atomic_uapi.c
603
*val = state->crtc_w;
sys/dev/pci/drm/drm_atomic_uapi.c
605
*val = state->crtc_h;
sys/dev/pci/drm/drm_atomic_uapi.c
607
*val = state->src_x;
sys/dev/pci/drm/drm_atomic_uapi.c
609
*val = state->src_y;
sys/dev/pci/drm/drm_atomic_uapi.c
611
*val = state->src_w;
sys/dev/pci/drm/drm_atomic_uapi.c
613
*val = state->src_h;
sys/dev/pci/drm/drm_atomic_uapi.c
615
*val = state->alpha;
sys/dev/pci/drm/drm_atomic_uapi.c
617
*val = state->pixel_blend_mode;
sys/dev/pci/drm/drm_atomic_uapi.c
619
*val = state->rotation;
sys/dev/pci/drm/drm_atomic_uapi.c
621
*val = state->zpos;
sys/dev/pci/drm/drm_atomic_uapi.c
623
*val = state->color_encoding;
sys/dev/pci/drm/drm_atomic_uapi.c
625
*val = state->color_range;
sys/dev/pci/drm/drm_atomic_uapi.c
627
*val = (state->fb_damage_clips) ?
sys/dev/pci/drm/drm_atomic_uapi.c
630
*val = state->scaling_filter;
sys/dev/pci/drm/drm_atomic_uapi.c
632
return plane->funcs->atomic_get_property(plane, state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
634
*val = state->hotspot_x;
sys/dev/pci/drm/drm_atomic_uapi.c
636
*val = state->hotspot_y;
sys/dev/pci/drm/drm_atomic_uapi.c
673
struct drm_property *property, uint64_t val)
sys/dev/pci/drm/drm_atomic_uapi.c
681
struct drm_crtc *crtc = drm_crtc_find(dev, file_priv, val);
sys/dev/pci/drm/drm_atomic_uapi.c
683
if (val && !crtc) {
sys/dev/pci/drm/drm_atomic_uapi.c
686
property->base.id, property->name, val);
sys/dev/pci/drm/drm_atomic_uapi.c
700
state->tv.select_subconnector = val;
sys/dev/pci/drm/drm_atomic_uapi.c
702
state->tv.subconnector = val;
sys/dev/pci/drm/drm_atomic_uapi.c
704
state->tv.margins.left = val;
sys/dev/pci/drm/drm_atomic_uapi.c
706
state->tv.margins.right = val;
sys/dev/pci/drm/drm_atomic_uapi.c
708
state->tv.margins.top = val;
sys/dev/pci/drm/drm_atomic_uapi.c
710
state->tv.margins.bottom = val;
sys/dev/pci/drm/drm_atomic_uapi.c
712
state->tv.legacy_mode = val;
sys/dev/pci/drm/drm_atomic_uapi.c
714
state->tv.mode = val;
sys/dev/pci/drm/drm_atomic_uapi.c
716
state->tv.brightness = val;
sys/dev/pci/drm/drm_atomic_uapi.c
718
state->tv.contrast = val;
sys/dev/pci/drm/drm_atomic_uapi.c
720
state->tv.flicker_reduction = val;
sys/dev/pci/drm/drm_atomic_uapi.c
722
state->tv.overscan = val;
sys/dev/pci/drm/drm_atomic_uapi.c
724
state->tv.saturation = val;
sys/dev/pci/drm/drm_atomic_uapi.c
726
state->tv.hue = val;
sys/dev/pci/drm/drm_atomic_uapi.c
740
state->link_status = val;
sys/dev/pci/drm/drm_atomic_uapi.c
744
val,
sys/dev/pci/drm/drm_atomic_uapi.c
749
state->picture_aspect_ratio = val;
sys/dev/pci/drm/drm_atomic_uapi.c
751
state->content_type = val;
sys/dev/pci/drm/drm_atomic_uapi.c
753
state->scaling_mode = val;
sys/dev/pci/drm/drm_atomic_uapi.c
755
if (val == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
sys/dev/pci/drm/drm_atomic_uapi.c
759
state->content_protection = val;
sys/dev/pci/drm/drm_atomic_uapi.c
761
state->hdcp_content_type = val;
sys/dev/pci/drm/drm_atomic_uapi.c
763
state->colorspace = val;
sys/dev/pci/drm/drm_atomic_uapi.c
768
fb = drm_framebuffer_lookup(dev, file_priv, val);
sys/dev/pci/drm/drm_atomic_uapi.c
774
s32 __user *fence_ptr = u64_to_user_ptr(val);
sys/dev/pci/drm/drm_atomic_uapi.c
779
state->max_requested_bpc = val;
sys/dev/pci/drm/drm_atomic_uapi.c
781
state->privacy_screen_sw_state = val;
sys/dev/pci/drm/drm_atomic_uapi.c
783
state->hdmi.broadcast_rgb = val;
sys/dev/pci/drm/drm_atomic_uapi.c
786
state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
801
struct drm_property *property, uint64_t *val)
sys/dev/pci/drm/drm_atomic_uapi.c
807
*val = (state->crtc) ? state->crtc->base.id : 0;
sys/dev/pci/drm/drm_atomic_uapi.c
810
*val = DRM_MODE_DPMS_ON;
sys/dev/pci/drm/drm_atomic_uapi.c
812
*val = connector->dpms;
sys/dev/pci/drm/drm_atomic_uapi.c
814
*val = state->tv.select_subconnector;
sys/dev/pci/drm/drm_atomic_uapi.c
816
*val = state->tv.subconnector;
sys/dev/pci/drm/drm_atomic_uapi.c
818
*val = state->tv.margins.left;
sys/dev/pci/drm/drm_atomic_uapi.c
820
*val = state->tv.margins.right;
sys/dev/pci/drm/drm_atomic_uapi.c
822
*val = state->tv.margins.top;
sys/dev/pci/drm/drm_atomic_uapi.c
824
*val = state->tv.margins.bottom;
sys/dev/pci/drm/drm_atomic_uapi.c
826
*val = state->tv.legacy_mode;
sys/dev/pci/drm/drm_atomic_uapi.c
828
*val = state->tv.mode;
sys/dev/pci/drm/drm_atomic_uapi.c
830
*val = state->tv.brightness;
sys/dev/pci/drm/drm_atomic_uapi.c
832
*val = state->tv.contrast;
sys/dev/pci/drm/drm_atomic_uapi.c
834
*val = state->tv.flicker_reduction;
sys/dev/pci/drm/drm_atomic_uapi.c
836
*val = state->tv.overscan;
sys/dev/pci/drm/drm_atomic_uapi.c
838
*val = state->tv.saturation;
sys/dev/pci/drm/drm_atomic_uapi.c
840
*val = state->tv.hue;
sys/dev/pci/drm/drm_atomic_uapi.c
842
*val = state->link_status;
sys/dev/pci/drm/drm_atomic_uapi.c
844
*val = state->picture_aspect_ratio;
sys/dev/pci/drm/drm_atomic_uapi.c
846
*val = state->content_type;
sys/dev/pci/drm/drm_atomic_uapi.c
848
*val = state->colorspace;
sys/dev/pci/drm/drm_atomic_uapi.c
850
*val = state->scaling_mode;
sys/dev/pci/drm/drm_atomic_uapi.c
852
*val = state->hdr_output_metadata ?
sys/dev/pci/drm/drm_atomic_uapi.c
855
*val = state->content_protection;
sys/dev/pci/drm/drm_atomic_uapi.c
857
*val = state->hdcp_content_type;
sys/dev/pci/drm/drm_atomic_uapi.c
860
*val = 0;
sys/dev/pci/drm/drm_atomic_uapi.c
862
*val = 0;
sys/dev/pci/drm/drm_atomic_uapi.c
864
*val = state->max_requested_bpc;
sys/dev/pci/drm/drm_atomic_uapi.c
866
*val = state->privacy_screen_sw_state;
sys/dev/pci/drm/drm_atomic_uapi.c
868
*val = state->hdmi.broadcast_rgb;
sys/dev/pci/drm/drm_atomic_uapi.c
871
state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
884
struct drm_property *property, uint64_t *val)
sys/dev/pci/drm/drm_atomic_uapi.c
895
connector->state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
903
crtc->state, property, val);
sys/dev/pci/drm/drm_atomic_uapi.c
911
plane->state, property, val);
sys/dev/pci/drm/drm_color_mgmt.c
140
s64 val;
sys/dev/pci/drm/drm_color_mgmt.c
144
val = clamp_val(mag, 0, negative ?
sys/dev/pci/drm/drm_color_mgmt.c
147
return negative ? -val : val;
sys/dev/pci/drm/drm_crtc_internal.h
265
struct drm_property *property, uint64_t *val);
sys/dev/pci/drm/drm_drv.c
1832
int val = 0;
sys/dev/pci/drm/drm_drv.c
1836
val = !list_empty(&file_priv->event_list);
sys/dev/pci/drm/drm_drv.c
1839
return (val);
sys/dev/pci/drm/drm_flip_work.c
64
void drm_flip_work_queue(struct drm_flip_work *work, void *val)
sys/dev/pci/drm/drm_flip_work.c
68
task = drm_flip_work_allocate_task(val,
sys/dev/pci/drm/drm_flip_work.c
74
work->func(work, val);
sys/dev/pci/drm/drm_linux.c
3652
hrtimer_forward_now(struct timeout *to, ktime_t val)
sys/dev/pci/drm/drm_linux.c
3657
NSEC_TO_TIMESPEC(ktime_to_ns(val), &ts);
sys/dev/pci/drm/drm_mode_object.c
288
struct drm_property *property, uint64_t val)
sys/dev/pci/drm/drm_mode_object.c
297
obj->properties->values[i] = val;
sys/dev/pci/drm/drm_mode_object.c
308
uint64_t *val)
sys/dev/pci/drm/drm_mode_object.c
314
*val = obj->properties->values[i];
sys/dev/pci/drm/drm_mode_object.c
324
uint64_t *val)
sys/dev/pci/drm/drm_mode_object.c
336
*val = bd->ops->get_brightness(bd);
sys/dev/pci/drm/drm_mode_object.c
338
*val = bd->props.brightness;
sys/dev/pci/drm/drm_mode_object.c
350
return drm_atomic_get_property(obj, property, val);
sys/dev/pci/drm/drm_mode_object.c
352
return __drm_object_property_get_prop_value(obj, property, val);
sys/dev/pci/drm/drm_mode_object.c
373
struct drm_property *property, uint64_t *val)
sys/dev/pci/drm/drm_mode_object.c
377
return __drm_object_property_get_value(obj, property, val);
sys/dev/pci/drm/drm_mode_object.c
399
uint64_t *val)
sys/dev/pci/drm/drm_mode_object.c
403
return __drm_object_property_get_prop_value(obj, property, val);
sys/dev/pci/drm/drm_mode_object.c
417
uint64_t val;
sys/dev/pci/drm/drm_mode_object.c
423
ret = __drm_object_property_get_value(obj, prop, &val);
sys/dev/pci/drm/drm_mode_object.c
430
if (put_user(val, prop_values + count))
sys/dev/pci/drm/i915/display/dvo_ch7017.c
171
static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)
sys/dev/pci/drm/i915/display/dvo_ch7017.c
184
.buf = val,
sys/dev/pci/drm/i915/display/dvo_ch7017.c
190
static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
sys/dev/pci/drm/i915/display/dvo_ch7017.c
192
u8 buf[2] = { addr, val };
sys/dev/pci/drm/i915/display/dvo_ch7017.c
208
u8 val;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
217
if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val))
sys/dev/pci/drm/i915/display/dvo_ch7017.c
220
switch (val) {
sys/dev/pci/drm/i915/display/dvo_ch7017.c
233
val, adapter->name, dvo->target_addr);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
339
u8 val;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
341
ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
354
val & ~CH7017_LVDS_POWER_DOWN_EN);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
358
val | CH7017_LVDS_POWER_DOWN_EN);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
367
u8 val;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
369
ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
371
if (val & CH7017_LVDS_POWER_DOWN_EN)
sys/dev/pci/drm/i915/display/dvo_ch7017.c
379
u8 val;
sys/dev/pci/drm/i915/display/dvo_ch7017.c
383
ch7017_read(dvo, reg, &val); \
sys/dev/pci/drm/i915/display/dvo_ch7017.c
384
DRM_DEBUG_KMS(#reg ": %02x\n", val); \
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
345
u8 val;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
347
ch7xxx_readb(dvo, CH7xxx_PM, &val);
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
349
if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP))
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
360
u8 val;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
363
ch7xxx_readb(dvo, i, &val);
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
364
DRM_DEBUG_KMS("%02X ", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
444
u16 val;
sys/dev/pci/drm/i915/display/dvo_ivch.c
446
ivch_read(dvo, VR00, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
447
DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
448
ivch_read(dvo, VR01, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
449
DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
450
ivch_read(dvo, VR10, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
451
DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
452
ivch_read(dvo, VR30, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
453
DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
454
ivch_read(dvo, VR40, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
455
DRM_DEBUG_KMS("VR40: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
458
ivch_read(dvo, VR80, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
459
DRM_DEBUG_KMS("VR80: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
460
ivch_read(dvo, VR81, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
461
DRM_DEBUG_KMS("VR81: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
462
ivch_read(dvo, VR82, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
463
DRM_DEBUG_KMS("VR82: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
464
ivch_read(dvo, VR83, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
465
DRM_DEBUG_KMS("VR83: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
466
ivch_read(dvo, VR84, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
467
DRM_DEBUG_KMS("VR84: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
468
ivch_read(dvo, VR85, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
469
DRM_DEBUG_KMS("VR85: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
470
ivch_read(dvo, VR86, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
471
DRM_DEBUG_KMS("VR86: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
472
ivch_read(dvo, VR87, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
473
DRM_DEBUG_KMS("VR87: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
474
ivch_read(dvo, VR88, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
475
DRM_DEBUG_KMS("VR88: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
478
ivch_read(dvo, VR8E, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
479
DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
482
ivch_read(dvo, VR8F, &val);
sys/dev/pci/drm/i915/display/dvo_ivch.c
483
DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
258
u8 val;
sys/dev/pci/drm/i915/display/dvo_sil164.c
260
sil164_readb(dvo, SIL164_FREQ_LO, &val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
261
DRM_DEBUG_KMS("SIL164_FREQ_LO: 0x%02x\n", val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
262
sil164_readb(dvo, SIL164_FREQ_HI, &val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
263
DRM_DEBUG_KMS("SIL164_FREQ_HI: 0x%02x\n", val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
264
sil164_readb(dvo, SIL164_REG8, &val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
265
DRM_DEBUG_KMS("SIL164_REG8: 0x%02x\n", val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
266
sil164_readb(dvo, SIL164_REG9, &val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
267
DRM_DEBUG_KMS("SIL164_REG9: 0x%02x\n", val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
268
sil164_readb(dvo, SIL164_REGC, &val);
sys/dev/pci/drm/i915/display/dvo_sil164.c
269
DRM_DEBUG_KMS("SIL164_REGC: 0x%02x\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
270
u8 val, val2;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
272
tfp410_readb(dvo, TFP410_REV, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
273
DRM_DEBUG_KMS("TFP410_REV: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
274
tfp410_readb(dvo, TFP410_CTL_1, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
275
DRM_DEBUG_KMS("TFP410_CTL1: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
276
tfp410_readb(dvo, TFP410_CTL_2, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
277
DRM_DEBUG_KMS("TFP410_CTL2: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
278
tfp410_readb(dvo, TFP410_CTL_3, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
279
DRM_DEBUG_KMS("TFP410_CTL3: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
280
tfp410_readb(dvo, TFP410_USERCFG, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
281
DRM_DEBUG_KMS("TFP410_USERCFG: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
282
tfp410_readb(dvo, TFP410_DE_DLY, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
283
DRM_DEBUG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
284
tfp410_readb(dvo, TFP410_DE_CTL, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
285
DRM_DEBUG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
286
tfp410_readb(dvo, TFP410_DE_TOP, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
287
DRM_DEBUG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
288
tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
290
DRM_DEBUG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
291
tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
293
DRM_DEBUG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
294
tfp410_readb(dvo, TFP410_H_RES_LO, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
296
DRM_DEBUG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
297
tfp410_readb(dvo, TFP410_V_RES_LO, &val);
sys/dev/pci/drm/i915/display/dvo_tfp410.c
299
DRM_DEBUG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
sys/dev/pci/drm/i915/display/g4x_dp.c
259
u32 val = intel_de_read(display, TRANS_DP_CTL(p));
sys/dev/pci/drm/i915/display/g4x_dp.c
261
if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
sys/dev/pci/drm/i915/display/g4x_dp.c
281
u32 val;
sys/dev/pci/drm/i915/display/g4x_dp.c
283
val = intel_de_read(display, dp_reg);
sys/dev/pci/drm/i915/display/g4x_dp.c
285
ret = val & DP_PORT_EN;
sys/dev/pci/drm/i915/display/g4x_dp.c
289
*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);
sys/dev/pci/drm/i915/display/g4x_dp.c
293
*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);
sys/dev/pci/drm/i915/display/g4x_dp.c
295
*pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);
sys/dev/pci/drm/i915/display/hsw_ips.c
22
u32 val;
sys/dev/pci/drm/i915/display/hsw_ips.c
297
static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
sys/dev/pci/drm/i915/display/hsw_ips.c
302
*val = display->ips.false_color;
sys/dev/pci/drm/i915/display/hsw_ips.c
307
static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
sys/dev/pci/drm/i915/display/hsw_ips.c
318
display->ips.false_color = val;
sys/dev/pci/drm/i915/display/hsw_ips.c
35
val = IPS_ENABLE;
sys/dev/pci/drm/i915/display/hsw_ips.c
38
val |= IPS_FALSE_COLOR;
sys/dev/pci/drm/i915/display/hsw_ips.c
43
val | IPS_PCODE_CONTROL));
sys/dev/pci/drm/i915/display/hsw_ips.c
51
intel_de_write(display, IPS_CTL, val);
sys/dev/pci/drm/i915/display/i9xx_plane.c
1170
u32 val, base, offset;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1191
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
sys/dev/pci/drm/i915/display/i9xx_plane.c
1194
if (val & DISP_TILED) {
sys/dev/pci/drm/i915/display/i9xx_plane.c
1199
if (val & DISP_ROTATE_180)
sys/dev/pci/drm/i915/display/i9xx_plane.c
1204
pipe == PIPE_B && val & DISP_MIRROR)
sys/dev/pci/drm/i915/display/i9xx_plane.c
1207
pixel_format = val & DISP_FORMAT_MASK;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1231
val = intel_de_read(display, PIPESRC(display, pipe));
sys/dev/pci/drm/i915/display/i9xx_plane.c
1232
fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1233
fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1235
val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));
sys/dev/pci/drm/i915/display/i9xx_plane.c
1236
fb->pitches[0] = val & 0xffffffc0;
sys/dev/pci/drm/i915/display/i9xx_plane.c
729
u32 val;
sys/dev/pci/drm/i915/display/i9xx_plane.c
741
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
sys/dev/pci/drm/i915/display/i9xx_plane.c
743
ret = val & DISP_ENABLE;
sys/dev/pci/drm/i915/display/i9xx_plane.c
748
*pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
117
u32 val;
sys/dev/pci/drm/i915/display/i9xx_wm.c
122
val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);
sys/dev/pci/drm/i915/display/i9xx_wm.c
124
val &= ~FORCE_DDR_HIGH_FREQ;
sys/dev/pci/drm/i915/display/i9xx_wm.c
126
val |= FORCE_DDR_HIGH_FREQ;
sys/dev/pci/drm/i915/display/i9xx_wm.c
127
val &= ~FORCE_DDR_LOW_FREQ;
sys/dev/pci/drm/i915/display/i9xx_wm.c
128
val |= FORCE_DDR_FREQ_REQ_ACK;
sys/dev/pci/drm/i915/display/i9xx_wm.c
129
vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
131
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
sys/dev/pci/drm/i915/display/i9xx_wm.c
132
(val & FORCE_DDR_FREQ_REQ_ACK) == 0,
sys/dev/pci/drm/i915/display/i9xx_wm.c
143
u32 val;
sys/dev/pci/drm/i915/display/i9xx_wm.c
147
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
sys/dev/pci/drm/i915/display/i9xx_wm.c
149
val |= DSP_MAXFIFO_PM5_ENABLE;
sys/dev/pci/drm/i915/display/i9xx_wm.c
151
val &= ~DSP_MAXFIFO_PM5_ENABLE;
sys/dev/pci/drm/i915/display/i9xx_wm.c
152
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
163
u32 val;
sys/dev/pci/drm/i915/display/i9xx_wm.c
174
val = intel_de_read(display, DSPFW3(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
175
was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
sys/dev/pci/drm/i915/display/i9xx_wm.c
177
val |= PINEVIEW_SELF_REFRESH_EN;
sys/dev/pci/drm/i915/display/i9xx_wm.c
179
val &= ~PINEVIEW_SELF_REFRESH_EN;
sys/dev/pci/drm/i915/display/i9xx_wm.c
180
intel_de_write(display, DSPFW3(display), val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
184
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
sys/dev/pci/drm/i915/display/i9xx_wm.c
186
intel_de_write(display, FW_BLC_SELF, val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
195
val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
sys/dev/pci/drm/i915/display/i9xx_wm.c
197
intel_de_write(display, INSTPM, val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3913
u32 val;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3924
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3925
if (val & DSP_MAXFIFO_PM5_ENABLE)
sys/dev/pci/drm/i915/display/i9xx_wm.c
3937
val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3938
val |= FORCE_DDR_FREQ_REQ_ACK;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3939
vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3941
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
sys/dev/pci/drm/i915/display/i9xx_wm.c
3942
(val & FORCE_DDR_FREQ_REQ_ACK) == 0,
sys/dev/pci/drm/i915/display/i9xx_wm.c
3950
val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3951
if ((val & FORCE_DDR_HIGH_FREQ) == 0)
sys/dev/pci/drm/i915/display/icl_dsi.c
1545
u32 val;
sys/dev/pci/drm/i915/display/icl_dsi.c
1552
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
sys/dev/pci/drm/i915/display/icl_dsi.c
1553
return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
sys/dev/pci/drm/i915/display/icl_dsi.c
255
u32 tmp, mask, val;
sys/dev/pci/drm/i915/display/icl_dsi.c
264
val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
sys/dev/pci/drm/i915/display/icl_dsi.c
268
tmp |= val;
sys/dev/pci/drm/i915/display/icl_dsi.c
270
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
sys/dev/pci/drm/i915/display/icl_dsi.c
274
val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
sys/dev/pci/drm/i915/display/icl_dsi.c
278
tmp |= val;
sys/dev/pci/drm/i915/display/icl_dsi.c
280
intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
sys/dev/pci/drm/i915/display/icl_dsi.c
284
val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
sys/dev/pci/drm/i915/display/icl_dsi.c
286
intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
sys/dev/pci/drm/i915/display/icl_dsi.c
291
mask, val);
sys/dev/pci/drm/i915/display/icl_dsi.c
679
u32 val;
sys/dev/pci/drm/i915/display/icl_dsi.c
683
val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
sys/dev/pci/drm/i915/display/icl_dsi.c
685
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
sys/dev/pci/drm/i915/display/icl_dsi.c
686
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
sys/dev/pci/drm/i915/display/icl_dsi.c
688
intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
sys/dev/pci/drm/i915/display/icl_dsi.c
691
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
sys/dev/pci/drm/i915/display/icl_dsi.c
693
intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
sys/dev/pci/drm/i915/display/intel_alpm.c
447
u8 val;
sys/dev/pci/drm/i915/display/intel_alpm.c
452
val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
sys/dev/pci/drm/i915/display/intel_alpm.c
456
val |= DP_ALPM_MODE_AUX_LESS;
sys/dev/pci/drm/i915/display/intel_alpm.c
458
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
sys/dev/pci/drm/i915/display/intel_alpm.c
528
i915_edp_lobf_debug_get(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_alpm.c
533
*val = intel_dp->alpm_parameters.lobf_disable_debug;
sys/dev/pci/drm/i915/display/intel_alpm.c
539
i915_edp_lobf_debug_set(void *data, u64 val)
sys/dev/pci/drm/i915/display/intel_alpm.c
544
intel_dp->alpm_parameters.lobf_disable_debug = val;
sys/dev/pci/drm/i915/display/intel_alpm.c
590
u8 val;
sys/dev/pci/drm/i915/display/intel_alpm.c
593
r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
sys/dev/pci/drm/i915/display/intel_alpm.c
599
if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
sys/dev/pci/drm/i915/display/intel_alpm.c
603
drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
sys/dev/pci/drm/i915/display/intel_atomic.c
100
intel_conn_state->force_audio = val;
sys/dev/pci/drm/i915/display/intel_atomic.c
105
intel_conn_state->broadcast_rgb = val;
sys/dev/pci/drm/i915/display/intel_atomic.c
61
u64 *val)
sys/dev/pci/drm/i915/display/intel_atomic.c
68
*val = intel_conn_state->force_audio;
sys/dev/pci/drm/i915/display/intel_atomic.c
70
*val = intel_conn_state->broadcast_rgb;
sys/dev/pci/drm/i915/display/intel_atomic.c
93
u64 val)
sys/dev/pci/drm/i915/display/intel_atomic.h
26
u64 *val);
sys/dev/pci/drm/i915/display/intel_atomic.h
30
u64 val);
sys/dev/pci/drm/i915/display/intel_audio.c
520
unsigned int val;
sys/dev/pci/drm/i915/display/intel_audio.c
525
val = intel_de_read(display, AUD_CONFIG_BE);
sys/dev/pci/drm/i915/display/intel_audio.c
528
val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_audio.c
530
val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_audio.c
536
val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_audio.c
539
val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32);
sys/dev/pci/drm/i915/display/intel_audio.c
541
val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64);
sys/dev/pci/drm/i915/display/intel_audio.c
543
val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96);
sys/dev/pci/drm/i915/display/intel_audio.c
545
val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128);
sys/dev/pci/drm/i915/display/intel_audio.c
548
val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_audio.c
551
val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room);
sys/dev/pci/drm/i915/display/intel_audio.c
553
val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0);
sys/dev/pci/drm/i915/display/intel_audio.c
556
intel_de_write(display, AUD_CONFIG_BE, val);
sys/dev/pci/drm/i915/display/intel_audio_regs.h
140
#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
sys/dev/pci/drm/i915/display/intel_audio_regs.h
142
#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
sys/dev/pci/drm/i915/display/intel_backlight.c
102
return panel->backlight.pwm_level_max - val + panel->backlight.pwm_level_min;
sys/dev/pci/drm/i915/display/intel_backlight.c
105
return val;
sys/dev/pci/drm/i915/display/intel_backlight.c
108
void intel_backlight_set_pwm_level(const struct drm_connector_state *conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
115
connector->base.base.id, connector->base.name, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
116
panel->backlight.pwm_funcs->set(conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
119
u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
1252
u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
sys/dev/pci/drm/i915/display/intel_backlight.c
127
val = scale(val, panel->backlight.min, panel->backlight.max,
sys/dev/pci/drm/i915/display/intel_backlight.c
1284
val = pch_get_backlight(connector, unused);
sys/dev/pci/drm/i915/display/intel_backlight.c
1290
lpt_set_backlight(connector->base.state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
130
return intel_backlight_invert_pwm_level(connector, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
133
u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
1340
u32 ctl, val;
sys/dev/pci/drm/i915/display/intel_backlight.c
1365
val = i9xx_get_backlight(connector, unused);
sys/dev/pci/drm/i915/display/intel_backlight.c
1366
val = intel_backlight_invert_pwm_level(connector, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
1367
val = clamp(val, panel->backlight.pwm_level_min, panel->backlight.pwm_level_max);
sys/dev/pci/drm/i915/display/intel_backlight.c
1369
panel->backlight.pwm_enabled = val != 0;
sys/dev/pci/drm/i915/display/intel_backlight.c
144
val = panel->backlight.pwm_level_max - (val - panel->backlight.pwm_level_min);
sys/dev/pci/drm/i915/display/intel_backlight.c
1448
u32 pwm_ctl, val;
sys/dev/pci/drm/i915/display/intel_backlight.c
1457
val = intel_de_read(display, UTIL_PIN_CTL);
sys/dev/pci/drm/i915/display/intel_backlight.c
1459
val & UTIL_PIN_POLARITY;
sys/dev/pci/drm/i915/display/intel_backlight.c
146
return scale(val, panel->backlight.pwm_level_min, panel->backlight.pwm_level_max,
sys/dev/pci/drm/i915/display/intel_backlight.c
168
u32 val;
sys/dev/pci/drm/i915/display/intel_backlight.c
170
val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/pci/drm/i915/display/intel_backlight.c
172
val >>= 1;
sys/dev/pci/drm/i915/display/intel_backlight.c
179
val *= lbpc;
sys/dev/pci/drm/i915/display/intel_backlight.c
182
return val;
sys/dev/pci/drm/i915/display/intel_backlight.c
220
u32 val;
sys/dev/pci/drm/i915/display/intel_backlight.c
222
val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
sys/dev/pci/drm/i915/display/intel_backlight.c
223
intel_de_write(display, BLC_PWM_PCH_CTL2, val | level);
sys/dev/pci/drm/i915/display/intel_backlight.c
375
static void pch_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
380
intel_backlight_set_pwm_level(old_conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
387
static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
389
intel_backlight_set_pwm_level(old_conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
392
static void i965_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
397
intel_backlight_set_pwm_level(old_conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
402
static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
408
intel_backlight_set_pwm_level(old_conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
413
static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
419
intel_backlight_set_pwm_level(old_conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
428
static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
434
intel_backlight_set_pwm_level(old_conn_state, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
697
u32 pwm_ctl, val;
sys/dev/pci/drm/i915/display/intel_backlight.c
701
val = intel_de_read(display, UTIL_PIN_CTL);
sys/dev/pci/drm/i915/display/intel_backlight.c
702
if (val & UTIL_PIN_ENABLE) {
sys/dev/pci/drm/i915/display/intel_backlight.c
706
val &= ~UTIL_PIN_ENABLE;
sys/dev/pci/drm/i915/display/intel_backlight.c
707
intel_de_write(display, UTIL_PIN_CTL, val);
sys/dev/pci/drm/i915/display/intel_backlight.c
710
val = 0;
sys/dev/pci/drm/i915/display/intel_backlight.c
712
val |= UTIL_PIN_POLARITY;
sys/dev/pci/drm/i915/display/intel_backlight.c
714
val | UTIL_PIN_PIPE(pipe) | UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
sys/dev/pci/drm/i915/display/intel_backlight.c
835
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_backlight.c
840
val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector));
sys/dev/pci/drm/i915/display/intel_backlight.c
844
drm_dbg_kms(display->drm, "get backlight PWM = %d\n", val);
sys/dev/pci/drm/i915/display/intel_backlight.c
845
return val;
sys/dev/pci/drm/i915/display/intel_backlight.c
90
u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 val)
sys/dev/pci/drm/i915/display/intel_backlight.c
98
return val;
sys/dev/pci/drm/i915/display/intel_backlight.h
37
u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val);
sys/dev/pci/drm/i915/display/intel_bios.c
2183
static u8 translate_iboost(struct intel_display *display, u8 val)
sys/dev/pci/drm/i915/display/intel_bios.c
2187
if (val >= ARRAY_SIZE(mapping)) {
sys/dev/pci/drm/i915/display/intel_bios.c
2189
"Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
sys/dev/pci/drm/i915/display/intel_bios.c
2192
return mapping[val];
sys/dev/pci/drm/i915/display/intel_bw.c
104
val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
sys/dev/pci/drm/i915/display/intel_bw.c
105
sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
106
sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
108
val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
sys/dev/pci/drm/i915/display/intel_bw.c
109
sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
110
sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
121
u32 val = 0, val2 = 0;
sys/dev/pci/drm/i915/display/intel_bw.c
127
&val, &val2);
sys/dev/pci/drm/i915/display/intel_bw.c
131
dclk = val & 0xffff;
sys/dev/pci/drm/i915/display/intel_bw.c
134
sp->t_rp = (val & 0xff0000) >> 16;
sys/dev/pci/drm/i915/display/intel_bw.c
135
sp->t_rcd = (val & 0xff000000) >> 24;
sys/dev/pci/drm/i915/display/intel_bw.c
148
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_bw.c
153
ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
sys/dev/pci/drm/i915/display/intel_bw.c
158
points[i].clk = val & 0xff;
sys/dev/pci/drm/i915/display/intel_bw.c
159
val >>= 8;
sys/dev/pci/drm/i915/display/intel_bw.c
223
u32 val, val2;
sys/dev/pci/drm/i915/display/intel_bw.c
226
val = intel_uncore_read(&i915->uncore,
sys/dev/pci/drm/i915/display/intel_bw.c
230
dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
232
sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
233
sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
87
u32 val;
sys/dev/pci/drm/i915/display/intel_bw.c
89
val = intel_uncore_read(&i915->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
sys/dev/pci/drm/i915/display/intel_bw.c
90
dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
sys/dev/pci/drm/i915/display/intel_bw.c
91
if (val & DG1_QCLK_REFERENCE)
sys/dev/pci/drm/i915/display/intel_bw.c
97
val = intel_uncore_read(&i915->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
sys/dev/pci/drm/i915/display/intel_bw.c
98
if (val & DG1_GEAR_TYPE)
sys/dev/pci/drm/i915/display/intel_cdclk.c
1008
MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
sys/dev/pci/drm/i915/display/intel_cdclk.c
1703
u32 val, ratio;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1712
val = intel_de_read(display, BXT_DE_PLL_ENABLE);
sys/dev/pci/drm/i915/display/intel_cdclk.c
1713
if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
sys/dev/pci/drm/i915/display/intel_cdclk.c
1714
(val & BXT_DE_PLL_LOCK) == 0) {
sys/dev/pci/drm/i915/display/intel_cdclk.c
1728
ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1847
u32 val;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1849
val = ICL_CDCLK_PLL_RATIO(ratio);
sys/dev/pci/drm/i915/display/intel_cdclk.c
1850
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
1852
val |= BXT_DE_PLL_PLL_ENABLE;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1853
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
1865
u32 val;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1868
val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1869
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
1872
val |= BXT_DE_PLL_FREQ_REQ;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1873
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
1880
val &= ~BXT_DE_PLL_FREQ_REQ;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1881
intel_de_write(display, BXT_DE_PLL_ENABLE, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2108
u32 val;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2112
val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
sys/dev/pci/drm/i915/display/intel_cdclk.c
2121
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2124
val |= xe2lpd_mdclk_source_sel(display);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2126
val |= skl_cdclk_decimal(cdclk);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2128
return val;
sys/dev/pci/drm/i915/display/intel_cdclk.c
609
u32 val;
sys/dev/pci/drm/i915/display/intel_cdclk.c
618
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
sys/dev/pci/drm/i915/display/intel_cdclk.c
624
cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
sys/dev/pci/drm/i915/display/intel_cdclk.c
627
cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
sys/dev/pci/drm/i915/display/intel_cdclk.c
675
u32 val, cmd = cdclk_config->voltage_level;
sys/dev/pci/drm/i915/display/intel_cdclk.c
704
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
sys/dev/pci/drm/i915/display/intel_cdclk.c
705
val &= ~DSPFREQGUAR_MASK;
sys/dev/pci/drm/i915/display/intel_cdclk.c
706
val |= (cmd << DSPFREQGUAR_SHIFT);
sys/dev/pci/drm/i915/display/intel_cdclk.c
707
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
709
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
sys/dev/pci/drm/i915/display/intel_cdclk.c
710
(val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
sys/dev/pci/drm/i915/display/intel_cdclk.c
722
val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL);
sys/dev/pci/drm/i915/display/intel_cdclk.c
723
val &= ~CCK_FREQUENCY_VALUES;
sys/dev/pci/drm/i915/display/intel_cdclk.c
724
val |= divider;
sys/dev/pci/drm/i915/display/intel_cdclk.c
725
vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
727
ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),
sys/dev/pci/drm/i915/display/intel_cdclk.c
728
(val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
sys/dev/pci/drm/i915/display/intel_cdclk.c
735
val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC);
sys/dev/pci/drm/i915/display/intel_cdclk.c
736
val &= ~0x7f;
sys/dev/pci/drm/i915/display/intel_cdclk.c
743
val |= 4500 / 250; /* 4.5 usec */
sys/dev/pci/drm/i915/display/intel_cdclk.c
745
val |= 3000 / 250; /* 3.0 usec */
sys/dev/pci/drm/i915/display/intel_cdclk.c
746
vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
765
u32 val, cmd = cdclk_config->voltage_level;
sys/dev/pci/drm/i915/display/intel_cdclk.c
789
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
sys/dev/pci/drm/i915/display/intel_cdclk.c
790
val &= ~DSPFREQGUAR_MASK_CHV;
sys/dev/pci/drm/i915/display/intel_cdclk.c
791
val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
sys/dev/pci/drm/i915/display/intel_cdclk.c
792
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
sys/dev/pci/drm/i915/display/intel_cdclk.c
794
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
sys/dev/pci/drm/i915/display/intel_cdclk.c
795
(val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
sys/dev/pci/drm/i915/display/intel_cdclk.c
975
u32 val;
sys/dev/pci/drm/i915/display/intel_cdclk.c
980
val = intel_de_read(display, LCPLL1_CTL);
sys/dev/pci/drm/i915/display/intel_cdclk.c
981
if ((val & LCPLL_PLL_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_cdclk.c
984
if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
sys/dev/pci/drm/i915/display/intel_cdclk.c
987
val = intel_de_read(display, DPLL_CTRL1);
sys/dev/pci/drm/i915/display/intel_cdclk.c
990
(val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
sys/dev/pci/drm/i915/display/intel_cdclk.c
996
switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
sys/dev/pci/drm/i915/display/intel_cmtg.c
105
u32 val;
sys/dev/pci/drm/i915/display/intel_cmtg.c
107
val = intel_de_read(display, TRANS_CMTG_CTL_A);
sys/dev/pci/drm/i915/display/intel_cmtg.c
108
cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
sys/dev/pci/drm/i915/display/intel_cmtg.c
111
val = intel_de_read(display, TRANS_CMTG_CTL_B);
sys/dev/pci/drm/i915/display/intel_cmtg.c
112
cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
sys/dev/pci/drm/i915/display/intel_cmtg.c
89
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cmtg.c
97
val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));
sys/dev/pci/drm/i915/display/intel_cmtg.c
99
return val & CMTG_SECONDARY_MODE;
sys/dev/pci/drm/i915/display/intel_color.c
1113
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_color.c
1124
val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
sys/dev/pci/drm/i915/display/intel_color.c
1126
val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
sys/dev/pci/drm/i915/display/intel_color.c
1127
intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), val);
sys/dev/pci/drm/i915/display/intel_color.c
1190
u16 val = 0xffff * i / (lut_size - 1);
sys/dev/pci/drm/i915/display/intel_color.c
1192
lut[i].red = val;
sys/dev/pci/drm/i915/display/intel_color.c
1193
lut[i].green = val;
sys/dev/pci/drm/i915/display/intel_color.c
1194
lut[i].blue = val;
sys/dev/pci/drm/i915/display/intel_color.c
1338
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1343
intel_dsb_reg_write(crtc_state->dsb_color, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1345
intel_de_write_fw(display, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1349
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1354
intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1356
intel_de_write_fw(display, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1586
static void glk_degamma_lut_pack(struct drm_color_lut *entry, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1589
entry->red = entry->green = entry->blue = min(val, 0xffffu);
sys/dev/pci/drm/i915/display/intel_color.c
1597
static void mtl_degamma_lut_pack(struct drm_color_lut *entry, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1601
intel_color_lut_pack(min(val, 0xffffffu), 24);
sys/dev/pci/drm/i915/display/intel_color.c
3300
u32 val = intel_de_read_fw(display,
sys/dev/pci/drm/i915/display/intel_color.c
3303
i9xx_lut_8_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
3504
u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));
sys/dev/pci/drm/i915/display/intel_color.c
3506
i9xx_lut_8_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
3529
u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));
sys/dev/pci/drm/i915/display/intel_color.c
3531
ilk_lut_10_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
3592
u32 val;
sys/dev/pci/drm/i915/display/intel_color.c
3596
val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
3598
ilk_lut_10_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
3663
u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
3665
ilk_lut_10_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
3733
u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));
sys/dev/pci/drm/i915/display/intel_color.c
3736
mtl_degamma_lut_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
3738
glk_degamma_lut_pack(&lut[i], val);
sys/dev/pci/drm/i915/display/intel_color.c
809
static u32 intel_color_lut_pack(u32 val, int bit_precision)
sys/dev/pci/drm/i915/display/intel_color.c
812
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16) - 1),
sys/dev/pci/drm/i915/display/intel_color.c
815
return DIV_ROUND_CLOSEST(val * ((1 << 16) - 1),
sys/dev/pci/drm/i915/display/intel_color.c
826
static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
828
entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8);
sys/dev/pci/drm/i915/display/intel_color.c
829
entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8);
sys/dev/pci/drm/i915/display/intel_color.c
830
entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8);
sys/dev/pci/drm/i915/display/intel_color.c
932
static u16 i965_lut_11p6_max_pack(u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
935
return min(val, 0xffffu);
sys/dev/pci/drm/i915/display/intel_color.c
945
static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
947
entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_RED_MASK, val), 10);
sys/dev/pci/drm/i915/display/intel_color.c
948
entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_GREEN_MASK, val), 10);
sys/dev/pci/drm/i915/display/intel_color.c
949
entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
100
if ((val & mask) != expected_val) {
sys/dev/pci/drm/i915/display/intel_combo_phy.c
105
reg.reg, val, mask, expected_val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
315
u32 val;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
337
val = intel_de_read(display, ICL_PHY_MISC(phy));
sys/dev/pci/drm/i915/display/intel_combo_phy.c
340
val &= ~ICL_PHY_MISC_MUX_DDID;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
343
val |= ICL_PHY_MISC_MUX_DDID;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
346
val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
347
intel_de_write(display, ICL_PHY_MISC(phy), val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
351
val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));
sys/dev/pci/drm/i915/display/intel_combo_phy.c
352
val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
353
val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
354
val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
355
intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
357
val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
sys/dev/pci/drm/i915/display/intel_combo_phy.c
358
val &= ~DCC_MODE_SELECT_MASK;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
359
val |= RUN_DCC_ONCE;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
360
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
60
u32 val;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
62
val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));
sys/dev/pci/drm/i915/display/intel_combo_phy.c
63
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
sys/dev/pci/drm/i915/display/intel_combo_phy.c
65
MISSING_CASE(val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
98
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_crt.c
100
*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val);
sys/dev/pci/drm/i915/display/intel_crt.c
102
*pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val);
sys/dev/pci/drm/i915/display/intel_crt.c
104
return val & ADPA_DAC_ENABLE;
sys/dev/pci/drm/i915/display/intel_crt.c
94
u32 val;
sys/dev/pci/drm/i915/display/intel_crt.c
96
val = intel_de_read(display, adpa_reg);
sys/dev/pci/drm/i915/display/intel_cursor.c
577
u32 val = intel_cursor_position(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
580
intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);
sys/dev/pci/drm/i915/display/intel_cursor.c
604
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cursor.c
607
val |= CUR_WM_EN;
sys/dev/pci/drm/i915/display/intel_cursor.c
609
val |= CUR_WM_IGNORE_LINES;
sys/dev/pci/drm/i915/display/intel_cursor.c
610
val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
sys/dev/pci/drm/i915/display/intel_cursor.c
611
val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
sys/dev/pci/drm/i915/display/intel_cursor.c
613
return val;
sys/dev/pci/drm/i915/display/intel_cursor.c
732
u32 val;
sys/dev/pci/drm/i915/display/intel_cursor.c
744
val = intel_de_read(display, CURCNTR(display, plane->pipe));
sys/dev/pci/drm/i915/display/intel_cursor.c
746
ret = val & MCURSOR_MODE_MASK;
sys/dev/pci/drm/i915/display/intel_cursor.c
751
*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
163
int command, int lane, u32 *val)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
174
XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
177
phy_name(phy), *val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
189
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
193
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
198
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
202
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
217
u32 val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
233
ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
247
return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2768
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2775
val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2777
val |= XELPDP_FORWARD_CLOCK_UNGATE;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2780
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2782
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2787
val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2789
val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2794
XELPDP_SSC_ENABLE_PLLB, val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2799
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2803
val |= XELPDP_LANE_POWERDOWN_UPDATE(lane);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2805
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2810
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2814
val |= XELPDP_LANE_POWERDOWN_NEW_STATE(lane, state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2816
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2873
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2877
val |= XELPDP_LANE_PCLK_REFCLK_REQUEST(lane);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2879
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2884
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2888
val |= XELPDP_LANE_PCLK_REFCLK_ACK(lane);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
289
u32 val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2890
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2999
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3003
val |= XELPDP_LANE_PCLK_PLL_REQUEST(lane);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3005
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3010
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3014
val |= XELPDP_LANE_PCLK_PLL_ACK(lane);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3016
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3112
u32 clock, val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3114
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3116
clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3118
drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3119
drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3120
drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
317
ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3176
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3185
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3189
val |= XELPDP_FORWARD_CLOCK_UNGATE;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3192
mask, val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3195
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3205
val |= XELPDP_TBT_CLOCK_REQUEST;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3206
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3410
u32 val, clock;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3416
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3417
clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
389
u16 val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
396
val = intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_H);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
397
val <<= 8;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
398
val |= intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_L);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
400
return val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
406
u8 old, val;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
409
val = (old & ~clear) | set;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
411
if (val != old)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
412
__intel_cx0_write(encoder, lane, addr, val, committed);
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
129
#define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
131
#define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
132
#define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
133
_XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
134
_XELPDP_LANE1_POWERDOWN_NEW_STATE(val))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
137
#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
149
#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
151
#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
199
#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
200
REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
201
REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
202
#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
203
REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
204
REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val)))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
223
#define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
262
#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
266
#define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
279
#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
304
#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
307
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
335
#define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
337
#define C20_PHY_TX_DCC_CAL_RANGE(val) \
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
338
REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
341
#define C20_PHY_TX_TERM_CTL(val) REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val))
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
368
#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
384
#define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
385
#define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
392
#define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
395
#define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
399
#define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
403
#define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
407
#define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
411
#define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
415
#define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
419
#define V2I(val) REG_FIELD_PREP16(V2I_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
423
#define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
54
#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
57
#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
sys/dev/pci/drm/i915/display/intel_cx0_phy_regs.h
73
#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
sys/dev/pci/drm/i915/display/intel_ddi.c
1043
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
1049
val = TGL_TRANS_CLK_SEL_PORT(phy);
sys/dev/pci/drm/i915/display/intel_ddi.c
1051
val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
sys/dev/pci/drm/i915/display/intel_ddi.c
1053
val = TRANS_CLK_SEL_PORT(encoder->port);
sys/dev/pci/drm/i915/display/intel_ddi.c
1055
intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1062
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
1068
val = TGL_TRANS_CLK_SEL_DISABLED;
sys/dev/pci/drm/i915/display/intel_ddi.c
1070
val = TRANS_CLK_SEL_DISABLED;
sys/dev/pci/drm/i915/display/intel_ddi.c
1072
intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1173
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
1182
val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
sys/dev/pci/drm/i915/display/intel_ddi.c
1184
intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val,
sys/dev/pci/drm/i915/display/intel_ddi.c
1185
intel_dp->hobl_active ? val : 0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1189
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
sys/dev/pci/drm/i915/display/intel_ddi.c
1190
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
sys/dev/pci/drm/i915/display/intel_ddi.c
1193
val |= SCALING_MODE_SEL(0x2);
sys/dev/pci/drm/i915/display/intel_ddi.c
1194
val |= RTERM_SELECT(0x6);
sys/dev/pci/drm/i915/display/intel_ddi.c
1195
val |= TAP3_DISABLE;
sys/dev/pci/drm/i915/display/intel_ddi.c
1196
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1236
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
1244
val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
sys/dev/pci/drm/i915/display/intel_ddi.c
1246
val &= ~COMMON_KEEPER_EN;
sys/dev/pci/drm/i915/display/intel_ddi.c
1248
val |= COMMON_KEEPER_EN;
sys/dev/pci/drm/i915/display/intel_ddi.c
1249
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1269
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
sys/dev/pci/drm/i915/display/intel_ddi.c
1270
val &= ~TX_TRAINING_EN;
sys/dev/pci/drm/i915/display/intel_ddi.c
1271
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1277
val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
sys/dev/pci/drm/i915/display/intel_ddi.c
1278
val |= TX_TRAINING_EN;
sys/dev/pci/drm/i915/display/intel_ddi.c
1279
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1442
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
1446
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1447
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
sys/dev/pci/drm/i915/display/intel_ddi.c
1449
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
sys/dev/pci/drm/i915/display/intel_ddi.c
1450
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
sys/dev/pci/drm/i915/display/intel_ddi.c
1453
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1454
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1460
val);
sys/dev/pci/drm/i915/display/intel_ddi.c
1731
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
1733
val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
sys/dev/pci/drm/i915/display/intel_ddi.c
1734
val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
sys/dev/pci/drm/i915/display/intel_ddi.c
1735
val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
sys/dev/pci/drm/i915/display/intel_ddi.c
1736
id = val;
sys/dev/pci/drm/i915/display/intel_ddi.c
2589
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_ddi.c
2591
val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
2594
val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
sys/dev/pci/drm/i915/display/intel_ddi.c
2596
val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
sys/dev/pci/drm/i915/display/intel_ddi.c
2599
val |= XELPDP_PORT_REVERSAL;
sys/dev/pci/drm/i915/display/intel_ddi.c
2603
val);
sys/dev/pci/drm/i915/display/intel_ddi.c
2610
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
2612
val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
sys/dev/pci/drm/i915/display/intel_ddi.c
2615
XELPDP_PORT_BUF_IO_SELECT_TBT, val);
sys/dev/pci/drm/i915/display/intel_ddi.c
3440
u32 val;
sys/dev/pci/drm/i915/display/intel_ddi.c
3442
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_ddi.c
3445
val |= DDIE_TRAINING_OVERRIDE_ENABLE |
sys/dev/pci/drm/i915/display/intel_ddi.c
3448
val |= DDI_TRAINING_OVERRIDE_ENABLE |
sys/dev/pci/drm/i915/display/intel_ddi.c
3451
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_ddi.c
3457
val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
sys/dev/pci/drm/i915/display/intel_ddi.c
3460
val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
sys/dev/pci/drm/i915/display/intel_ddi.c
3463
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_ddi.c
388
u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
sys/dev/pci/drm/i915/display/intel_ddi.c
390
switch (val) {
sys/dev/pci/drm/i915/display/intel_ddi.c
402
MISSING_CASE(val);
sys/dev/pci/drm/i915/display/intel_ddi.c
491
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_ddi.c
497
val = TRANS_DP2_128B132B_CHANNEL_CODING;
sys/dev/pci/drm/i915/display/intel_ddi.c
499
intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_de.h
100
val = __intel_de_rmw_nowl(display, reg, clear, set);
sys/dev/pci/drm/i915/display/intel_de.h
104
return val;
sys/dev/pci/drm/i915/display/intel_de.h
202
u32 val;
sys/dev/pci/drm/i915/display/intel_de.h
204
val = intel_uncore_read_fw(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
205
trace_i915_reg_rw(false, reg, val, sizeof(val), true);
sys/dev/pci/drm/i915/display/intel_de.h
207
return val;
sys/dev/pci/drm/i915/display/intel_de.h
211
intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
213
trace_i915_reg_rw(true, reg, val, sizeof(val), true);
sys/dev/pci/drm/i915/display/intel_de.h
214
intel_uncore_write_fw(__to_uncore(display), reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
224
intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
226
intel_uncore_write_notrace(__to_uncore(display), reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
23
u32 val;
sys/dev/pci/drm/i915/display/intel_de.h
231
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
234
intel_dsb_reg_write(dsb, reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
236
intel_de_write_fw(display, reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
27
val = intel_uncore_read(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
31
return val;
sys/dev/pci/drm/i915/display/intel_de.h
37
u8 val;
sys/dev/pci/drm/i915/display/intel_de.h
41
val = intel_uncore_read8(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
45
return val;
sys/dev/pci/drm/i915/display/intel_de.h
52
u64 val;
sys/dev/pci/drm/i915/display/intel_de.h
57
val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
sys/dev/pci/drm/i915/display/intel_de.h
63
return val;
sys/dev/pci/drm/i915/display/intel_de.h
77
intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
81
intel_uncore_write(__to_uncore(display), reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
96
u32 val;
sys/dev/pci/drm/i915/display/intel_display.c
159
u32 val;
sys/dev/pci/drm/i915/display/intel_display.c
162
val = vlv_cck_read(drm, reg);
sys/dev/pci/drm/i915/display/intel_display.c
163
divider = val & CCK_FREQUENCY_VALUES;
sys/dev/pci/drm/i915/display/intel_display.c
165
drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
sys/dev/pci/drm/i915/display/intel_display.c
2929
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_display.c
2937
val |= TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
2940
val |= TRANSCONF_DOUBLE_WIDE;
sys/dev/pci/drm/i915/display/intel_display.c
2947
val |= TRANSCONF_DITHER_EN |
sys/dev/pci/drm/i915/display/intel_display.c
2956
val |= TRANSCONF_BPC_6;
sys/dev/pci/drm/i915/display/intel_display.c
2959
val |= TRANSCONF_BPC_8;
sys/dev/pci/drm/i915/display/intel_display.c
2962
val |= TRANSCONF_BPC_10;
sys/dev/pci/drm/i915/display/intel_display.c
2970
val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
sys/dev/pci/drm/i915/display/intel_display.c
2972
val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
sys/dev/pci/drm/i915/display/intel_display.c
2974
val |= TRANSCONF_INTERLACE_PROGRESSIVE;
sys/dev/pci/drm/i915/display/intel_display.c
2979
val |= TRANSCONF_COLOR_RANGE_SELECT;
sys/dev/pci/drm/i915/display/intel_display.c
2981
val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_display.c
2984
val |= TRANSCONF_WGC_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
2986
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_display.c
2988
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_display.c
3129
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_display.c
3136
val |= TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
3144
val |= TRANSCONF_BPC_6;
sys/dev/pci/drm/i915/display/intel_display.c
3147
val |= TRANSCONF_BPC_8;
sys/dev/pci/drm/i915/display/intel_display.c
3150
val |= TRANSCONF_BPC_10;
sys/dev/pci/drm/i915/display/intel_display.c
3153
val |= TRANSCONF_BPC_12;
sys/dev/pci/drm/i915/display/intel_display.c
3158
val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
sys/dev/pci/drm/i915/display/intel_display.c
3161
val |= TRANSCONF_INTERLACE_IF_ID_ILK;
sys/dev/pci/drm/i915/display/intel_display.c
3163
val |= TRANSCONF_INTERLACE_PF_PD_ILK;
sys/dev/pci/drm/i915/display/intel_display.c
3174
val |= TRANSCONF_COLOR_RANGE_SELECT;
sys/dev/pci/drm/i915/display/intel_display.c
3177
val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
sys/dev/pci/drm/i915/display/intel_display.c
3179
val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_display.c
3181
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_display.c
3182
val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
sys/dev/pci/drm/i915/display/intel_display.c
3184
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_display.c
3192
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_display.c
3199
val |= TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
3202
val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
sys/dev/pci/drm/i915/display/intel_display.c
3205
val |= TRANSCONF_INTERLACE_IF_ID_ILK;
sys/dev/pci/drm/i915/display/intel_display.c
3207
val |= TRANSCONF_INTERLACE_PF_PD_ILK;
sys/dev/pci/drm/i915/display/intel_display.c
3211
val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
sys/dev/pci/drm/i915/display/intel_display.c
3213
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_display.c
3222
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_display.c
3226
val |= PIPE_MISC_BPC_6;
sys/dev/pci/drm/i915/display/intel_display.c
3229
val |= PIPE_MISC_BPC_8;
sys/dev/pci/drm/i915/display/intel_display.c
3232
val |= PIPE_MISC_BPC_10;
sys/dev/pci/drm/i915/display/intel_display.c
3237
val |= PIPE_MISC_BPC_12_ADLP;
sys/dev/pci/drm/i915/display/intel_display.c
3245
val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
sys/dev/pci/drm/i915/display/intel_display.c
3249
val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
sys/dev/pci/drm/i915/display/intel_display.c
3252
val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :
sys/dev/pci/drm/i915/display/intel_display.c
3256
val |= PIPE_MISC_HDR_MODE_PRECISION;
sys/dev/pci/drm/i915/display/intel_display.c
3259
val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
sys/dev/pci/drm/i915/display/intel_display.c
3263
val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
3265
intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
sys/dev/pci/drm/i915/display/intel_display.c
442
u32 val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
444
cur_state = !!(val & TRANSCONF_ENABLE);
sys/dev/pci/drm/i915/display/intel_display.c
489
u32 val;
sys/dev/pci/drm/i915/display/intel_display.c
532
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
533
if (val & TRANSCONF_ENABLE) {
sys/dev/pci/drm/i915/display/intel_display.c
542
val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
sys/dev/pci/drm/i915/display/intel_display.c
543
val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
sys/dev/pci/drm/i915/display/intel_display.c
548
val | TRANSCONF_ENABLE);
sys/dev/pci/drm/i915/display/intel_display.c
568
u32 val;
sys/dev/pci/drm/i915/display/intel_display.c
578
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_display.c
579
if ((val & TRANSCONF_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_display.c
587
val &= ~TRANSCONF_DOUBLE_WIDE;
sys/dev/pci/drm/i915/display/intel_display.c
591
val &= ~TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/display/intel_display.c
596
val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
sys/dev/pci/drm/i915/display/intel_display.c
598
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_display.c
604
if ((val & TRANSCONF_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_display_device.c
1520
u32 val;
sys/dev/pci/drm/i915/display/intel_display_device.c
1535
val = ioread32(addr);
sys/dev/pci/drm/i915/display/intel_display_device.c
1547
val = bus_space_read_4(bst, bsh, i915_mmio_reg_offset(GMD_ID_DISPLAY));
sys/dev/pci/drm/i915/display/intel_display_device.c
1552
if (val == 0) {
sys/dev/pci/drm/i915/display/intel_display_device.c
1557
gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
sys/dev/pci/drm/i915/display/intel_display_device.c
1558
gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
sys/dev/pci/drm/i915/display/intel_display_device.c
1559
gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1209
u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1210
drm_warn(display->drm, "Register Access Timeout = 0x%x\n", val);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1255
u32 val;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1261
val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));
sys/dev/pci/drm/i915/display/intel_display_irq.c
1262
val &= PORT_SYNC_MODE_ENABLE;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1268
port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
sys/dev/pci/drm/i915/display/intel_display_irq.c
1273
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
sys/dev/pci/drm/i915/display/intel_display_irq.c
1274
val = val & OP_MODE_MASK;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1276
if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
sys/dev/pci/drm/i915/display/intel_display_irq.c
1282
val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));
sys/dev/pci/drm/i915/display/intel_display_irq.c
1283
switch (val & TRANS_DDI_EDP_INPUT_MASK) {
sys/dev/pci/drm/i915/display/intel_display_params.c
144
const char *name, bool val)
sys/dev/pci/drm/i915/display/intel_display_params.c
146
drm_printf(p, "%s.%s=%s\n", driver_name, name, str_yes_no(val));
sys/dev/pci/drm/i915/display/intel_display_params.c
151
const char *name, int val)
sys/dev/pci/drm/i915/display/intel_display_params.c
153
drm_printf(p, "%s.%s=%d\n", driver_name, name, val);
sys/dev/pci/drm/i915/display/intel_display_params.c
158
const char *name, unsigned int val)
sys/dev/pci/drm/i915/display/intel_display_params.c
160
drm_printf(p, "%s.%s=%u\n", driver_name, name, val);
sys/dev/pci/drm/i915/display/intel_display_params.c
165
const char *name, unsigned long val)
sys/dev/pci/drm/i915/display/intel_display_params.c
167
drm_printf(p, "%s.%s=%lu\n", driver_name, name, val);
sys/dev/pci/drm/i915/display/intel_display_params.c
172
const char *name, const char *val)
sys/dev/pci/drm/i915/display/intel_display_params.c
174
drm_printf(p, "%s.%s=%s\n", driver_name, name, val);
sys/dev/pci/drm/i915/display/intel_display_params.c
177
#define _param_print(p, driver_name, name, val) \
sys/dev/pci/drm/i915/display/intel_display_params.c
178
_Generic(val, \
sys/dev/pci/drm/i915/display/intel_display_params.c
183
char * : _param_print_charp)(p, driver_name, name, val)
sys/dev/pci/drm/i915/display/intel_display_power.c
1157
u32 mask, val, i;
sys/dev/pci/drm/i915/display/intel_display_power.c
1166
val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
sys/dev/pci/drm/i915/display/intel_display_power.c
1180
intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1185
u32 val = intel_de_read(display, LCPLL_CTL);
sys/dev/pci/drm/i915/display/intel_display_power.c
1193
if (val & LCPLL_CD_SOURCE_FCLK)
sys/dev/pci/drm/i915/display/intel_display_power.c
1196
if (val & LCPLL_PLL_DISABLE)
sys/dev/pci/drm/i915/display/intel_display_power.c
1199
if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC)
sys/dev/pci/drm/i915/display/intel_display_power.c
1262
static void hsw_write_dcomp(struct intel_display *display, u32 val)
sys/dev/pci/drm/i915/display/intel_display_power.c
1265
if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val))
sys/dev/pci/drm/i915/display/intel_display_power.c
1268
intel_de_write(display, D_COMP_BDW, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1284
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power.c
1289
val = intel_de_read(display, LCPLL_CTL);
sys/dev/pci/drm/i915/display/intel_display_power.c
1292
val |= LCPLL_CD_SOURCE_FCLK;
sys/dev/pci/drm/i915/display/intel_display_power.c
1293
intel_de_write(display, LCPLL_CTL, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1301
val = intel_de_read(display, LCPLL_CTL);
sys/dev/pci/drm/i915/display/intel_display_power.c
1304
val |= LCPLL_PLL_DISABLE;
sys/dev/pci/drm/i915/display/intel_display_power.c
1305
intel_de_write(display, LCPLL_CTL, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1311
val = hsw_read_dcomp(display);
sys/dev/pci/drm/i915/display/intel_display_power.c
1312
val |= D_COMP_COMP_DISABLE;
sys/dev/pci/drm/i915/display/intel_display_power.c
1313
hsw_write_dcomp(display, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1316
ret = poll_timeout_us(val = hsw_read_dcomp(display),
sys/dev/pci/drm/i915/display/intel_display_power.c
1317
(val & D_COMP_RCOMP_IN_PROGRESS) == 0,
sys/dev/pci/drm/i915/display/intel_display_power.c
1335
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power.c
1338
val = intel_de_read(display, LCPLL_CTL);
sys/dev/pci/drm/i915/display/intel_display_power.c
1340
if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
sys/dev/pci/drm/i915/display/intel_display_power.c
1350
if (val & LCPLL_POWER_DOWN_ALLOW) {
sys/dev/pci/drm/i915/display/intel_display_power.c
1351
val &= ~LCPLL_POWER_DOWN_ALLOW;
sys/dev/pci/drm/i915/display/intel_display_power.c
1352
intel_de_write(display, LCPLL_CTL, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1356
val = hsw_read_dcomp(display);
sys/dev/pci/drm/i915/display/intel_display_power.c
1357
val |= D_COMP_COMP_FORCE;
sys/dev/pci/drm/i915/display/intel_display_power.c
1358
val &= ~D_COMP_COMP_DISABLE;
sys/dev/pci/drm/i915/display/intel_display_power.c
1359
hsw_write_dcomp(display, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1361
val = intel_de_read(display, LCPLL_CTL);
sys/dev/pci/drm/i915/display/intel_display_power.c
1362
val &= ~LCPLL_PLL_DISABLE;
sys/dev/pci/drm/i915/display/intel_display_power.c
1363
intel_de_write(display, LCPLL_CTL, val);
sys/dev/pci/drm/i915/display/intel_display_power.c
1368
if (val & LCPLL_CD_SOURCE_FCLK) {
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1129
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1138
val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1139
if ((val & mask) == state)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1147
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1148
(val & mask) == state,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1246
u32 val = intel_de_read(display, DPLL(display, pipe));
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1248
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1250
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1252
intel_de_write(display, DPLL(display, pipe), val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1352
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1560
u32 reg, val, expected, actual;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1578
val = vlv_dpio_read(display->drm, phy, reg);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1597
if (ch == DPIO_CH1 && val == 0)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1607
DPIO_ALLDL_POWERDOWN_CH0, val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1610
DPIO_ALLDL_POWERDOWN_CH1, val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1618
reg, val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
531
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
559
ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),
sys/dev/pci/drm/i915/display/intel_display_power_well.c
560
val & DKL_CMN_UC_DW27_UC_HEALTH,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
610
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
612
val = intel_de_read(display, regs->driver);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
622
val |= intel_de_read(display, regs->bios);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
624
return (val & mask) == mask;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
735
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
740
val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
744
power_domains->dc_state, val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
745
power_domains->dc_state = val;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
776
u32 val;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
788
val = intel_de_read(display, DC_STATE_EN);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
791
val & mask, state);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
794
if ((val & mask) != power_domains->dc_state)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
796
power_domains->dc_state, val & mask);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
803
val &= ~mask;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
804
val |= state;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
806
gen9_write_dc_state(display, val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
811
power_domains->dc_state = val & mask;
sys/dev/pci/drm/i915/display/intel_display_regs.h
2749
#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
sys/dev/pci/drm/i915/display/intel_display_regs.h
972
#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
sys/dev/pci/drm/i915/display/intel_display_regs.h
973
#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
49
u32 val;
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
54
val = intel_de_read(display, DKL_REG_MMIO(reg));
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
58
return val;
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
70
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
75
intel_de_write(display, DKL_REG_MMIO(reg), val);
sys/dev/pci/drm/i915/display/intel_dkl_phy.h
19
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
153
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
155
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
205
#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
62
#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
sys/dev/pci/drm/i915/display/intel_dp.c
3449
u8 val;
sys/dev/pci/drm/i915/display/intel_dp.c
3451
err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
sys/dev/pci/drm/i915/display/intel_dp.c
3456
val |= flag;
sys/dev/pci/drm/i915/display/intel_dp.c
3458
val &= ~flag;
sys/dev/pci/drm/i915/display/intel_dp.c
3460
return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
sys/dev/pci/drm/i915/display/intel_dp.c
4858
u32 val = intel_de_read(display, reg) & ~dip_enable;
sys/dev/pci/drm/i915/display/intel_dp.c
4862
val &= ~VDIP_ENABLE_PPS;
sys/dev/pci/drm/i915/display/intel_dp.c
4869
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
sys/dev/pci/drm/i915/display/intel_dp.c
4871
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_dp.c
5500
u8 val;
sys/dev/pci/drm/i915/display/intel_dp.c
5506
DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
sys/dev/pci/drm/i915/display/intel_dp.c
5509
drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
sys/dev/pci/drm/i915/display/intel_dp.c
5511
if (val & DP_AUTOMATED_TEST_REQUEST)
sys/dev/pci/drm/i915/display/intel_dp.c
5514
if (val & DP_CP_IRQ)
sys/dev/pci/drm/i915/display/intel_dp.c
5517
if (val & DP_SINK_SPECIFIC_IRQ)
sys/dev/pci/drm/i915/display/intel_dp.c
5525
u8 val;
sys/dev/pci/drm/i915/display/intel_dp.c
5531
DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
sys/dev/pci/drm/i915/display/intel_dp.c
5534
if ((val & DP_TUNNELING_IRQ) &&
sys/dev/pci/drm/i915/display/intel_dp.c
5540
DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
sys/dev/pci/drm/i915/display/intel_dp.c
5543
if (val & HDMI_LINK_STATUS_CHANGED)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
446
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
459
val |= buf[0] | buf[1] << 8 | buf[2] << 16;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
460
return val / 1000;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
808
u32 val;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
812
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
814
stream_type = REG_FIELD_GET(AUTH_STREAM_TYPE_MASK, val);
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
834
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
836
stream_type = REG_FIELD_GET(STREAM_TYPE_STATUS_MASK, val);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1097
u8 val = DP_TRAINING_PATTERN_DISABLE;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1099
return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
123
u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
127
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1932
static int i915_dp_max_link_rate_show(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1943
*val = intel_dp->link.max_rate;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1951
static int i915_dp_max_lane_count_show(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1962
*val = intel_dp->link.max_lane_count;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1970
static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1981
*val = intel_dp->link.force_train_failure;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1988
static int i915_dp_force_link_training_failure_write(void *data, u64 val)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1995
if (val > 2)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
2002
intel_dp->link.force_train_failure = val;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
2012
static int i915_dp_force_link_retrain_show(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
2023
*val = intel_dp->link.force_retrain;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
2030
static int i915_dp_force_link_retrain_write(void *data, u64 val)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
2041
intel_dp->link.force_retrain = val;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2121
u8 val;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2126
ret = drm_dp_dpcd_readb(intel_dp->mst.mgr.aux, DP_MSTM_CTRL, &val);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2129
if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) {
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2134
ret, val);
sys/dev/pci/drm/i915/display/intel_dp_test.c
563
int val = 0;
sys/dev/pci/drm/i915/display/intel_dp_test.c
588
status = kstrtoint(input_buffer, 10, &val);
sys/dev/pci/drm/i915/display/intel_dp_test.c
591
drm_dbg_kms(display->drm, "Got %d for test active\n", val);
sys/dev/pci/drm/i915/display/intel_dp_test.c
595
if (val == 1)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1000
val |= DPIO_TX2_STAGGER_MASK(0x1f);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1001
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1043
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1049
val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1050
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1051
vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1053
val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1054
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1055
vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1138
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1143
val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1145
val |= DPIO_PCS_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1146
val |= 0xc4;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1147
vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
286
u32 old, val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
289
val = (old & ~clear) | set;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
290
intel_de_write(display, reg_group, val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
329
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
336
val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
337
if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
385
u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
387
return REG_FIELD_GET(GRC_CODE_MASK, val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
400
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
460
val = bxt_get_grc(display, phy_info->rcomp_phy);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
461
display->state.bxt_phy_grc = val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
463
grc_code = GRC_CODE_FAST(val) |
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
464
GRC_CODE_SLOW(val) |
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
465
GRC_CODE_NOM(val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
520
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
522
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
523
if ((val & mask) == expected)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
532
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
649
u32 val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
652
if (val & LATENCY_OPTIM)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
724
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
730
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
731
val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
732
val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
733
val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
734
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
737
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
738
val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
739
val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
740
val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
741
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
744
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
745
val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
746
val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
747
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
750
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
751
val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
752
val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
753
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
758
val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
759
val &= ~DPIO_SWING_DEEMPH9P5_MASK;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
760
val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
761
vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
766
val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
768
val &= ~DPIO_SWING_MARGIN000_MASK;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
769
val |= DPIO_SWING_MARGIN000(margin_reg_value);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
776
val &= ~DPIO_UNIQ_TRANS_SCALE_MASK;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
777
val |= DPIO_UNIQ_TRANS_SCALE(0x9a);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
779
vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
789
val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
791
val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
793
val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
794
vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
798
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
799
val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
800
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
803
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
804
val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
805
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
819
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
821
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
823
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
825
val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
826
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
829
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
831
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
833
val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
834
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
837
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
838
val |= CHV_PCS_REQ_SOFTRESET_EN;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
840
val &= ~DPIO_PCS_CLK_SOFT_RESET;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
842
val |= DPIO_PCS_CLK_SOFT_RESET;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
843
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
846
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
847
val |= CHV_PCS_REQ_SOFTRESET_EN;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
849
val &= ~DPIO_PCS_CLK_SOFT_RESET;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
851
val |= DPIO_PCS_CLK_SOFT_RESET;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
852
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
878
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
897
val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
898
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
900
val |= CHV_BUFLEFTENA1_FORCE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
902
val |= CHV_BUFRIGHTENA1_FORCE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
903
vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
905
val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
906
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
908
val |= CHV_BUFLEFTENA2_FORCE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
910
val |= CHV_BUFRIGHTENA2_FORCE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
911
vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
915
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
916
val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
918
val |= DPIO_PCS_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
920
val &= ~DPIO_PCS_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
921
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
924
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
925
val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
927
val |= DPIO_PCS_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
929
val &= ~DPIO_PCS_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
930
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
938
val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
940
val |= CHV_CMN_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
942
val &= ~CHV_CMN_USEDCLKCHANNEL;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
943
vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
957
u32 val;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
962
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
963
val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
964
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
967
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
968
val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
969
vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
994
val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch));
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
995
val |= DPIO_TX2_STAGGER_MASK(0x1f);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
996
vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
999
val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
2231
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll.c
2236
val = DPLL_INTEGRATED_REF_CLK_VLV |
sys/dev/pci/drm/i915/display/intel_dpll.c
2239
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
sys/dev/pci/drm/i915/display/intel_dpll.c
2241
intel_de_write(display, DPLL(display, pipe), val);
sys/dev/pci/drm/i915/display/intel_dpll.c
2249
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll.c
2254
val = DPLL_SSC_REF_CLK_CHV |
sys/dev/pci/drm/i915/display/intel_dpll.c
2257
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
sys/dev/pci/drm/i915/display/intel_dpll.c
2259
intel_de_write(display, DPLL(display, pipe), val);
sys/dev/pci/drm/i915/display/intel_dpll.c
2265
val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch));
sys/dev/pci/drm/i915/display/intel_dpll.c
2266
val &= ~DPIO_DCLKP_EN;
sys/dev/pci/drm/i915/display/intel_dpll.c
2267
vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1436
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1445
val = intel_de_read(display, regs[id].ctl);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1446
if (!(val & LCPLL_PLL_ENABLE))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1449
val = intel_de_read(display, DPLL_CTRL1);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1450
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1453
if (val & DPLL_CTRL1_HDMI_MODE(id)) {
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1473
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1484
val = intel_de_read(display, regs[id].ctl);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1485
if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE)))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1488
val = intel_de_read(display, DPLL_CTRL1);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1489
hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2179
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2191
val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2192
if (!(val & PORT_PLL_ENABLE))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3119
u8 val = display->vbt.override_afc_startup_val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3121
hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3557
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3566
val = intel_de_read(display, enable_reg);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3567
if (!(val & PLL_ENABLE))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3624
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3631
val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3632
if (!(val & PLL_ENABLE))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3657
val = DKL_PLL_DIV0_MASK;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3659
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3660
hw_state->mg_pll_div0 &= val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3696
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3703
val = intel_de_read(display, enable_reg);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3704
if (!(val & PLL_ENABLE))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3854
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3861
val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3862
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3863
val |= hw_state->mg_refclkin_ctl;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3864
intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3866
val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3867
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3868
val |= hw_state->mg_clktop2_coreclkctl1;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3869
intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3871
val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3872
val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3876
val |= hw_state->mg_clktop2_hsclkctl;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3877
intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3879
val = DKL_PLL_DIV0_MASK;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3881
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3882
intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3885
val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3886
val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3888
val |= hw_state->mg_pll_div1;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3889
intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3891
val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3892
val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3896
val |= hw_state->mg_pll_ssc;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3897
intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3899
val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3900
val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3902
val |= hw_state->mg_pll_bias;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3903
intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3905
val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3906
val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3908
val |= hw_state->mg_pll_tdc_coldst_bias;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3909
intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3942
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3958
val = intel_de_read(display, TRANS_CMTG_CHICKEN);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3959
val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3960
if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3961
drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
535
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
542
val = intel_de_read(display, PCH_DPLL(id));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
543
hw_state->dpll = val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
549
return val & DPLL_VCO_ENABLE;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
554
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
557
val = intel_de_read(display, PCH_DREF_CONTROL);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
558
enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
756
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
763
val = intel_de_read(display, WRPLL_CTL(id));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
764
hw_state->wrpll = val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
768
return val & WRPLL_PLL_ENABLE;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
777
u32 val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
784
val = intel_de_read(display, SPLL_CTL);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
785
hw_state->spll = val;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
789
return val & SPLL_PLL_ENABLE;
sys/dev/pci/drm/i915/display/intel_drrs.c
352
static int intel_drrs_debugfs_ctl_set(void *data, u64 val)
sys/dev/pci/drm/i915/display/intel_drrs.c
377
drm_dbg_kms(display->drm, "Manually %sactivating DRRS\n", val ? "" : "de");
sys/dev/pci/drm/i915/display/intel_drrs.c
379
if (val)
sys/dev/pci/drm/i915/display/intel_dsb.c
328
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
359
intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val);
sys/dev/pci/drm/i915/display/intel_dsb.c
366
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
368
intel_dsb_emit(dsb, val,
sys/dev/pci/drm/i915/display/intel_dsb.c
384
i915_reg_t reg, u32 mask, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
386
intel_dsb_emit(dsb, val,
sys/dev/pci/drm/i915/display/intel_dsb.c
514
i915_reg_t reg, u32 mask, u32 val,
sys/dev/pci/drm/i915/display/intel_dsb.c
527
intel_dsb_emit(dsb, val,
sys/dev/pci/drm/i915/display/intel_dsb.h
40
i915_reg_t reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
42
i915_reg_t reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
44
i915_reg_t reg, u32 mask, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
62
i915_reg_t reg, u32 mask, u32 val,
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
18
void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
20
dsb_buf->cmd_buf[idx] = val;
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
28
void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
32
memset(&dsb_buf->cmd_buf[idx], val, size);
sys/dev/pci/drm/i915/display/intel_dsb_buffer.h
21
void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb_buffer.h
23
void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size);
sys/dev/pci/drm/i915/display/intel_fb.c
1476
#define assign_chk_ovf(display, var, val) ({ \
sys/dev/pci/drm/i915/display/intel_fb.c
1477
drm_WARN_ON((display)->drm, overflows_type(val, var)); \
sys/dev/pci/drm/i915/display/intel_fb.c
1478
(var) = (val); \
sys/dev/pci/drm/i915/display/intel_fb.c
1481
#define assign_bfld_chk_ovf(display, var, val) ({ \
sys/dev/pci/drm/i915/display/intel_fb.c
1482
(var) = (val); \
sys/dev/pci/drm/i915/display/intel_fb.c
1483
drm_WARN_ON((display)->drm, (var) != (val)); \
sys/dev/pci/drm/i915/display/intel_fbc.c
2189
static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_fbc.c
2193
*val = fbc->false_color;
sys/dev/pci/drm/i915/display/intel_fbc.c
2198
static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
sys/dev/pci/drm/i915/display/intel_fbc.c
2204
fbc->false_color = val;
sys/dev/pci/drm/i915/display/intel_fbc.c
622
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_fbc.c
625
val |= FBC_STRIDE_OVERRIDE |
sys/dev/pci/drm/i915/display/intel_fbc.c
628
intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val);
sys/dev/pci/drm/i915/display/intel_fbc.c
635
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_fbc.c
639
val |= CHICKEN_FBC_STRIDE_OVERRIDE |
sys/dev/pci/drm/i915/display/intel_fbc.c
644
CHICKEN_FBC_STRIDE_MASK, val);
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
105
#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val))
sys/dev/pci/drm/i915/display/intel_fbc_regs.h
107
#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))
sys/dev/pci/drm/i915/display/intel_fixed.h
101
tmp = (u64)val << 16;
sys/dev/pci/drm/i915/display/intel_fixed.h
107
static inline u32 div_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t d)
sys/dev/pci/drm/i915/display/intel_fixed.h
111
tmp = (u64)val << 16;
sys/dev/pci/drm/i915/display/intel_fixed.h
112
tmp = DIV_ROUND_UP_ULL(tmp, d.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
118
static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul)
sys/dev/pci/drm/i915/display/intel_fixed.h
122
tmp = mul_u32_u32(val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
132
tmp = (u64)add1.val + add2.val;
sys/dev/pci/drm/i915/display/intel_fixed.h
143
tmp = (u64)add1.val + tmp_add2.val;
sys/dev/pci/drm/i915/display/intel_fixed.h
15
u32 val;
sys/dev/pci/drm/i915/display/intel_fixed.h
18
#define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX })
sys/dev/pci/drm/i915/display/intel_fixed.h
20
static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
sys/dev/pci/drm/i915/display/intel_fixed.h
22
return val.val == 0;
sys/dev/pci/drm/i915/display/intel_fixed.h
25
static inline uint_fixed_16_16_t u32_to_fixed16(u32 val)
sys/dev/pci/drm/i915/display/intel_fixed.h
27
uint_fixed_16_16_t fp = { .val = val << 16 };
sys/dev/pci/drm/i915/display/intel_fixed.h
29
WARN_ON(val > U16_MAX);
sys/dev/pci/drm/i915/display/intel_fixed.h
36
return DIV_ROUND_UP(fp.val, 1 << 16);
sys/dev/pci/drm/i915/display/intel_fixed.h
41
return fp.val >> 16;
sys/dev/pci/drm/i915/display/intel_fixed.h
47
uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) };
sys/dev/pci/drm/i915/display/intel_fixed.h
55
uint_fixed_16_16_t max = { .val = max(max1.val, max2.val) };
sys/dev/pci/drm/i915/display/intel_fixed.h
60
static inline uint_fixed_16_16_t clamp_u64_to_fixed16(u64 val)
sys/dev/pci/drm/i915/display/intel_fixed.h
62
uint_fixed_16_16_t fp = { .val = (u32)val };
sys/dev/pci/drm/i915/display/intel_fixed.h
64
WARN_ON(val > U32_MAX);
sys/dev/pci/drm/i915/display/intel_fixed.h
69
static inline u32 div_round_up_fixed16(uint_fixed_16_16_t val,
sys/dev/pci/drm/i915/display/intel_fixed.h
72
return DIV_ROUND_UP(val.val, d.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
75
static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul)
sys/dev/pci/drm/i915/display/intel_fixed.h
79
tmp = mul_u32_u32(val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
86
static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
sys/dev/pci/drm/i915/display/intel_fixed.h
91
tmp = mul_u32_u32(val.val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
97
static inline uint_fixed_16_16_t div_fixed16(u32 val, u32 d)
sys/dev/pci/drm/i915/display/intel_gmbus.c
600
u32 val, loop = 0;
sys/dev/pci/drm/i915/display/intel_gmbus.c
606
val = intel_de_read_fw(display, GMBUS3(display));
sys/dev/pci/drm/i915/display/intel_gmbus.c
613
*buf++ = val & 0xff;
sys/dev/pci/drm/i915/display/intel_gmbus.c
614
val >>= 8;
sys/dev/pci/drm/i915/display/intel_gmbus.c
668
u32 val, loop;
sys/dev/pci/drm/i915/display/intel_gmbus.c
670
val = loop = 0;
sys/dev/pci/drm/i915/display/intel_gmbus.c
672
val |= *buf++ << (8 * loop++);
sys/dev/pci/drm/i915/display/intel_gmbus.c
676
intel_de_write_fw(display, GMBUS3(display), val);
sys/dev/pci/drm/i915/display/intel_gmbus.c
682
val = loop = 0;
sys/dev/pci/drm/i915/display/intel_gmbus.c
684
val |= *buf++ << (8 * loop);
sys/dev/pci/drm/i915/display/intel_gmbus.c
687
intel_de_write_fw(display, GMBUS3(display), val);
sys/dev/pci/drm/i915/display/intel_hdcp.c
378
u32 val;
sys/dev/pci/drm/i915/display/intel_hdcp.c
380
val = intel_de_read(display, HDCP_KEY_STATUS);
sys/dev/pci/drm/i915/display/intel_hdcp.c
381
if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS))
sys/dev/pci/drm/i915/display/intel_hdcp.c
415
10, 1, &val);
sys/dev/pci/drm/i915/display/intel_hdcp.c
418
else if (!(val & HDCP_KEY_LOAD_STATUS))
sys/dev/pci/drm/i915/display/intel_hdcp.c
818
u32 val;
sys/dev/pci/drm/i915/display/intel_hdcp.c
907
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
sys/dev/pci/drm/i915/display/intel_hdcp.c
908
val & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC),
sys/dev/pci/drm/i915/display/intel_hdcp.c
942
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
sys/dev/pci/drm/i915/display/intel_hdcp.c
943
val & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC),
sys/dev/pci/drm/i915/display/intel_hdcp.c
951
"Timed out waiting for Ri prime match (%x)\n", val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1060
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1066
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1069
if (!(val & VIDEO_DIP_ENABLE))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1071
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1074
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1079
if (port != (val & VIDEO_DIP_PORT_MASK)) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
1080
drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1082
(val & VIDEO_DIP_PORT_MASK) >> 29);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1083
val &= ~VIDEO_DIP_PORT_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1084
val |= port;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1087
val |= VIDEO_DIP_ENABLE;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1088
val &= ~(VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1093
val |= VIDEO_DIP_ENABLE_GCP;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1095
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1118
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1123
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1126
if (!(val & VIDEO_DIP_ENABLE))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1128
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1131
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1137
val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1138
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1142
val |= VIDEO_DIP_ENABLE_GCP;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1144
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1167
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1173
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1176
if (!(val & VIDEO_DIP_ENABLE))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1178
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1181
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1186
if (port != (val & VIDEO_DIP_PORT_MASK)) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
1187
drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1189
(val & VIDEO_DIP_PORT_MASK) >> 29);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1190
val &= ~VIDEO_DIP_PORT_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1191
val |= port;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1194
val |= VIDEO_DIP_ENABLE;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1195
val &= ~(VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1200
val |= VIDEO_DIP_ENABLE_GCP;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1202
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1223
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1227
(val & VIDEO_DIP_ENABLE_DRM_GLK) == 0)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1230
val &= ~(VIDEO_DIP_ENABLE_DRM_GLK);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1232
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1248
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1253
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
sys/dev/pci/drm/i915/display/intel_hdmi.c
1259
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1265
val |= VIDEO_DIP_ENABLE_GCP_HSW;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1267
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1418
u8 val;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1420
ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1426
*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1451
u8 val;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1453
ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1459
*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
sys/dev/pci/drm/i915/display/intel_hdmi.c
219
u32 val = intel_de_read(display, VIDEO_DIP_CTL);
sys/dev/pci/drm/i915/display/intel_hdmi.c
222
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
sys/dev/pci/drm/i915/display/intel_hdmi.c
225
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
sys/dev/pci/drm/i915/display/intel_hdmi.c
226
val |= g4x_infoframe_index(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
228
val &= ~g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
230
intel_de_write(display, VIDEO_DIP_CTL, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
240
val |= g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
241
val &= ~VIDEO_DIP_FREQ_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
242
val |= VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
244
intel_de_write(display, VIDEO_DIP_CTL, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
268
u32 val = intel_de_read(display, VIDEO_DIP_CTL);
sys/dev/pci/drm/i915/display/intel_hdmi.c
270
if ((val & VIDEO_DIP_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_hdmi.c
273
if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
sys/dev/pci/drm/i915/display/intel_hdmi.c
276
return val & (VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
289
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
292
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
sys/dev/pci/drm/i915/display/intel_hdmi.c
295
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
sys/dev/pci/drm/i915/display/intel_hdmi.c
296
val |= g4x_infoframe_index(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
298
val &= ~g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
300
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
311
val |= g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
312
val &= ~VIDEO_DIP_FREQ_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
313
val |= VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
315
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
342
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
344
if ((val & VIDEO_DIP_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_hdmi.c
347
if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
sys/dev/pci/drm/i915/display/intel_hdmi.c
350
return val & (VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
364
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
367
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
sys/dev/pci/drm/i915/display/intel_hdmi.c
370
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
sys/dev/pci/drm/i915/display/intel_hdmi.c
371
val |= g4x_infoframe_index(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
376
val &= ~g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
378
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
389
val |= g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
390
val &= ~VIDEO_DIP_FREQ_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
391
val |= VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
393
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
419
u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));
sys/dev/pci/drm/i915/display/intel_hdmi.c
421
if ((val & VIDEO_DIP_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_hdmi.c
424
return val & (VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
438
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
441
drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
sys/dev/pci/drm/i915/display/intel_hdmi.c
444
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
sys/dev/pci/drm/i915/display/intel_hdmi.c
445
val |= g4x_infoframe_index(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
447
val &= ~g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
449
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
461
val |= g4x_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
462
val &= ~VIDEO_DIP_FREQ_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
463
val |= VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
465
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
492
u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));
sys/dev/pci/drm/i915/display/intel_hdmi.c
494
if ((val & VIDEO_DIP_ENABLE) == 0)
sys/dev/pci/drm/i915/display/intel_hdmi.c
497
if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
sys/dev/pci/drm/i915/display/intel_hdmi.c
500
return val & (VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
516
u32 val = intel_de_read(display, ctl_reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
522
val &= ~hsw_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
523
intel_de_write(display, ctl_reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
540
val |= hsw_infoframe_enable(type);
sys/dev/pci/drm/i915/display/intel_hdmi.c
543
val |= VSC_DIP_HW_DATA_SW_HEA;
sys/dev/pci/drm/i915/display/intel_hdmi.c
545
intel_de_write(display, ctl_reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
567
u32 val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_hdmi.c
581
return val & mask;
sys/dev/pci/drm/i915/display/intel_hdmi.c
612
u32 val, ret = 0;
sys/dev/pci/drm/i915/display/intel_hdmi.c
615
val = dig_port->infoframes_enabled(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
622
if (val & hsw_infoframe_enable(type))
sys/dev/pci/drm/i915/display/intel_hdmi.c
625
if (val & g4x_infoframe_enable(type))
sys/dev/pci/drm/i915/display/intel_hdmi.c
875
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
889
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
sys/dev/pci/drm/i915/display/intel_hdmi.c
892
if (!(val & VIDEO_DIP_ENABLE))
sys/dev/pci/drm/i915/display/intel_hdmi.c
894
if (port != (val & VIDEO_DIP_PORT_MASK)) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
897
(val & VIDEO_DIP_PORT_MASK) >> 29);
sys/dev/pci/drm/i915/display/intel_hdmi.c
900
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
902
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
907
if (port != (val & VIDEO_DIP_PORT_MASK)) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
908
if (val & VIDEO_DIP_ENABLE) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
911
(val & VIDEO_DIP_PORT_MASK) >> 29);
sys/dev/pci/drm/i915/display/intel_hdmi.c
914
val &= ~VIDEO_DIP_PORT_MASK;
sys/dev/pci/drm/i915/display/intel_hdmi.c
915
val |= port;
sys/dev/pci/drm/i915/display/intel_hdmi.c
918
val |= VIDEO_DIP_ENABLE;
sys/dev/pci/drm/i915/display/intel_hdmi.c
919
val &= ~(VIDEO_DIP_ENABLE_AVI |
sys/dev/pci/drm/i915/display/intel_hdmi.c
922
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
1035
u32 val = (INVERT_DDIA_HPD |
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
1044
intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
19
typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
216
static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
225
return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
231
static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
235
return val & PORTA_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
237
return val & PORTB_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
239
return val & PORTC_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
245
static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
252
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
258
static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
267
return val & ICP_TC_HPD_LONG_DETECT(pin);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
273
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
277
return val & PORTE_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
283
static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
287
return val & PORTA_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
289
return val & PORTB_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
291
return val & PORTC_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
293
return val & PORTD_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
299
static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
303
return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
309
static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
313
return val & PORTB_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
315
return val & PORTC_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
317
return val & PORTD_HOTPLUG_LONG_DETECT;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
323
static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
327
return val & PORTB_HOTPLUG_INT_LONG_PULSE;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
329
return val & PORTC_HOTPLUG_INT_LONG_PULSE;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
331
return val & PORTD_HOTPLUG_INT_LONG_PULSE;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
348
bool long_pulse_detect(enum hpd_pin pin, u32 val))
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
526
u32 val;
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
533
val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
534
intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
536
if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
885
u32 val = (INVERT_DDIA_HPD |
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
889
intel_de_rmw(display, SOUTH_CHICKEN1, 0, val);
sys/dev/pci/drm/i915/display/intel_link_bw.c
342
unsigned int val;
sys/dev/pci/drm/i915/display/intel_link_bw.c
345
err = kstrtouint(str, 10, &val);
sys/dev/pci/drm/i915/display/intel_link_bw.c
349
if (val > INT_MAX >> 4)
sys/dev/pci/drm/i915/display/intel_link_bw.c
352
*val_x16 = fxp_q4_from_int(val);
sys/dev/pci/drm/i915/display/intel_lspcon.c
439
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_lspcon.c
445
while (val < len) {
sys/dev/pci/drm/i915/display/intel_lspcon.c
459
val++; reg++; data++;
sys/dev/pci/drm/i915/display/intel_lspcon.c
462
val = 0;
sys/dev/pci/drm/i915/display/intel_lspcon.c
464
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
471
val &= ~LSPCON_MCA_AVI_IF_HANDLED;
sys/dev/pci/drm/i915/display/intel_lspcon.c
472
val |= LSPCON_MCA_AVI_IF_KICKOFF;
sys/dev/pci/drm/i915/display/intel_lspcon.c
474
ret = drm_dp_dpcd_write(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
480
val = 0;
sys/dev/pci/drm/i915/display/intel_lspcon.c
481
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
487
if (val == LSPCON_MCA_AVI_IF_HANDLED)
sys/dev/pci/drm/i915/display/intel_lspcon.c
615
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_lspcon.c
618
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
624
return val & LSPCON_MCA_AVI_IF_KICKOFF;
sys/dev/pci/drm/i915/display/intel_lspcon.c
630
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_lspcon.c
633
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
639
return val & LSPCON_PARADE_AVI_IF_KICKOFF;
sys/dev/pci/drm/i915/display/intel_lspcon.c
649
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_lspcon.c
658
val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
sys/dev/pci/drm/i915/display/intel_lspcon.c
666
val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
sys/dev/pci/drm/i915/display/intel_lspcon.c
669
return val;
sys/dev/pci/drm/i915/display/intel_lvds.c
100
return val & LVDS_PORT_EN;
sys/dev/pci/drm/i915/display/intel_lvds.c
160
u32 val;
sys/dev/pci/drm/i915/display/intel_lvds.c
165
val = intel_de_read(display, PP_ON_DELAYS(display, 0));
sys/dev/pci/drm/i915/display/intel_lvds.c
166
pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
167
pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
168
pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
170
val = intel_de_read(display, PP_OFF_DELAYS(display, 0));
sys/dev/pci/drm/i915/display/intel_lvds.c
171
pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
172
pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
174
val = intel_de_read(display, PP_DIVISOR(display, 0));
sys/dev/pci/drm/i915/display/intel_lvds.c
175
pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
176
val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
182
if (val)
sys/dev/pci/drm/i915/display/intel_lvds.c
183
val--;
sys/dev/pci/drm/i915/display/intel_lvds.c
185
pps->delays.power_cycle = val * 1000;
sys/dev/pci/drm/i915/display/intel_lvds.c
214
u32 val;
sys/dev/pci/drm/i915/display/intel_lvds.c
216
val = intel_de_read(display, PP_CONTROL(display, 0));
sys/dev/pci/drm/i915/display/intel_lvds.c
218
(val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
sys/dev/pci/drm/i915/display/intel_lvds.c
220
val |= PANEL_POWER_RESET;
sys/dev/pci/drm/i915/display/intel_lvds.c
221
intel_de_write(display, PP_CONTROL(display, 0), val);
sys/dev/pci/drm/i915/display/intel_lvds.c
801
unsigned int val;
sys/dev/pci/drm/i915/display/intel_lvds.c
820
val = intel_de_read(display, lvds_encoder->reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
822
val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
sys/dev/pci/drm/i915/display/intel_lvds.c
824
val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
sys/dev/pci/drm/i915/display/intel_lvds.c
825
if (val == 0)
sys/dev/pci/drm/i915/display/intel_lvds.c
826
val = connector->panel.vbt.bios_lvds_val;
sys/dev/pci/drm/i915/display/intel_lvds.c
828
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
sys/dev/pci/drm/i915/display/intel_lvds.c
90
u32 val;
sys/dev/pci/drm/i915/display/intel_lvds.c
92
val = intel_de_read(display, lvds_reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
96
*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
sys/dev/pci/drm/i915/display/intel_lvds.c
98
*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
sys/dev/pci/drm/i915/display/intel_opregion.c
691
unsigned long val, void *data)
sys/dev/pci/drm/i915/display/intel_opregion.c
718
static void set_did(struct intel_opregion *opregion, int i, u32 val)
sys/dev/pci/drm/i915/display/intel_opregion.c
721
opregion->acpi->didl[i] = val;
sys/dev/pci/drm/i915/display/intel_opregion.c
728
opregion->acpi->did2[i] = val;
sys/dev/pci/drm/i915/display/intel_overlay.c
216
u8 val;
sys/dev/pci/drm/i915/display/intel_overlay.c
226
PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
sys/dev/pci/drm/i915/display/intel_overlay.c
228
val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
sys/dev/pci/drm/i915/display/intel_overlay.c
230
val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
sys/dev/pci/drm/i915/display/intel_overlay.c
232
PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
108
u32 val;
sys/dev/pci/drm/i915/display/intel_pch_display.c
111
val = intel_de_read(display, PCH_TRANSCONF(pipe));
sys/dev/pci/drm/i915/display/intel_pch_display.c
112
enabled = !!(val & TRANS_ENABLE);
sys/dev/pci/drm/i915/display/intel_pch_display.c
121
u32 val = intel_de_read(display, hdmi_reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
123
if (val & SDVO_ENABLE ||
sys/dev/pci/drm/i915/display/intel_pch_display.c
124
(val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
sys/dev/pci/drm/i915/display/intel_pch_display.c
131
val &= ~SDVO_PIPE_SEL_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
132
val |= SDVO_PIPE_SEL(PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
134
intel_de_write(display, hdmi_reg, val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
140
u32 val = intel_de_read(display, dp_reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
142
if (val & DP_PORT_EN ||
sys/dev/pci/drm/i915/display/intel_pch_display.c
143
(val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
sys/dev/pci/drm/i915/display/intel_pch_display.c
150
val &= ~DP_PIPE_SEL_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
151
val |= DP_PIPE_SEL(PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
153
intel_de_write(display, dp_reg, val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
252
u32 val, pipeconf_val;
sys/dev/pci/drm/i915/display/intel_pch_display.c
263
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
268
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
sys/dev/pci/drm/i915/display/intel_pch_display.c
270
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
271
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_pch_display.c
272
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
276
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
281
val &= ~TRANS_FRAME_START_DELAY_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
282
val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_pch_display.c
289
val &= ~TRANSCONF_BPC_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
291
val |= TRANSCONF_BPC_8;
sys/dev/pci/drm/i915/display/intel_pch_display.c
293
val |= pipeconf_val & TRANSCONF_BPC_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
296
val &= ~TRANS_INTERLACE_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
300
val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
sys/dev/pci/drm/i915/display/intel_pch_display.c
302
val |= TRANS_INTERLACE_INTERLACED;
sys/dev/pci/drm/i915/display/intel_pch_display.c
304
val |= TRANS_INTERLACE_PROGRESSIVE;
sys/dev/pci/drm/i915/display/intel_pch_display.c
307
intel_de_write(display, reg, val | TRANS_ENABLE);
sys/dev/pci/drm/i915/display/intel_pch_display.c
551
u32 val, pipeconf_val;
sys/dev/pci/drm/i915/display/intel_pch_display.c
557
val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));
sys/dev/pci/drm/i915/display/intel_pch_display.c
559
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
sys/dev/pci/drm/i915/display/intel_pch_display.c
561
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
sys/dev/pci/drm/i915/display/intel_pch_display.c
562
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_pch_display.c
563
intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
565
val = TRANS_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_display.c
570
val |= TRANS_INTERLACE_INTERLACED;
sys/dev/pci/drm/i915/display/intel_pch_display.c
572
val |= TRANS_INTERLACE_PROGRESSIVE;
sys/dev/pci/drm/i915/display/intel_pch_display.c
574
intel_de_write(display, LPT_TRANSCONF, val);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
506
u32 val, final;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
564
val = intel_de_read(display, PCH_DREF_CONTROL);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
570
final = val;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
600
if (final == val)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
604
val &= ~DREF_NONSPREAD_SOURCE_MASK;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
607
val |= DREF_NONSPREAD_CK505_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
609
val |= DREF_NONSPREAD_SOURCE_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
612
val &= ~DREF_SSC_SOURCE_MASK;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
613
val |= DREF_SSC_SOURCE_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
618
val |= DREF_SSC1_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
620
val &= ~DREF_SSC1_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
624
intel_de_write(display, PCH_DREF_CONTROL, val);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
628
val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
635
val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
637
val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
640
val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
643
intel_de_write(display, PCH_DREF_CONTROL, val);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
649
val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
652
val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
654
intel_de_write(display, PCH_DREF_CONTROL, val);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
662
val &= ~DREF_SSC_SOURCE_MASK;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
663
val |= DREF_SSC_SOURCE_DISABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
666
val &= ~DREF_SSC1_ENABLE;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
668
intel_de_write(display, PCH_DREF_CONTROL, val);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
674
drm_WARN_ON(display->drm, val != final);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
131
u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
140
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
143
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
147
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
153
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
157
*val = 0;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
198
u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
205
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
210
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
213
*val = 0;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
256
u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
263
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
266
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
269
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
272
*val = 0;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
339
u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
346
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
349
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
352
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
355
*val = 0;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
367
u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
374
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
377
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
380
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
383
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
386
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
389
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
392
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
395
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
398
*val = 0;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
409
enum intel_pipe_crc_source *source, u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
412
return i8xx_pipe_crc_ctl_reg(source, val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
414
return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
416
return vlv_pipe_crc_ctl_reg(display, pipe, source, val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
418
return ilk_pipe_crc_ctl_reg(source, val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
420
return ivb_pipe_crc_ctl_reg(display, pipe, source, val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
422
return skl_pipe_crc_ctl_reg(display, pipe, source, val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
59
u32 *val)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
591
u32 val = 0; /* shut up gcc */
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
612
ret = get_new_crc_ctl_reg(display, pipe, &source, &val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
617
intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
641
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
646
if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
652
intel_de_write(display, PIPE_CRC_CTL(display, pipe), val);
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
66
*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
69
*val = 0;
sys/dev/pci/drm/i915/display/intel_pps.c
1470
static int pps_units_to_msecs(int val)
sys/dev/pci/drm/i915/display/intel_pps.c
1473
return DIV_ROUND_UP(val, 10);
sys/dev/pci/drm/i915/display/intel_pps.c
1843
u32 val;
sys/dev/pci/drm/i915/display/intel_pps.c
1890
val = intel_de_read(display, pp_reg);
sys/dev/pci/drm/i915/display/intel_pps.c
1891
if (!(val & PANEL_POWER_ON) ||
sys/dev/pci/drm/i915/display/intel_pps.c
1892
((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
sys/dev/pci/drm/i915/display/intel_pps.c
613
u32 val;
sys/dev/pci/drm/i915/display/intel_pps.c
630
ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),
sys/dev/pci/drm/i915/display/intel_pps.c
631
(val & mask) == value,
sys/dev/pci/drm/i915/display/intel_psr.c
1011
u32 val = psr->su_region_et_enabled ?
sys/dev/pci/drm/i915/display/intel_psr.c
1015
val |= EDP_PSR2_SU_SDP_SCANLINE;
sys/dev/pci/drm/i915/display/intel_psr.c
1018
val);
sys/dev/pci/drm/i915/display/intel_psr.c
1033
u32 val = EDP_PSR2_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
1044
val |= EDP_PSR2_IDLE_FRAMES(idle_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
1047
val |= EDP_SU_TRACK_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
1050
val |= EDP_Y_COORDINATE_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
1052
val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));
sys/dev/pci/drm/i915/display/intel_psr.c
1054
val |= intel_psr2_get_tp_time(intel_dp);
sys/dev/pci/drm/i915/display/intel_psr.c
1058
val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
sys/dev/pci/drm/i915/display/intel_psr.c
1060
val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
sys/dev/pci/drm/i915/display/intel_psr.c
1083
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
sys/dev/pci/drm/i915/display/intel_psr.c
1086
val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
sys/dev/pci/drm/i915/display/intel_psr.c
1088
val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
sys/dev/pci/drm/i915/display/intel_psr.c
1090
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
sys/dev/pci/drm/i915/display/intel_psr.c
1091
val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);
sys/dev/pci/drm/i915/display/intel_psr.c
1093
val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
sys/dev/pci/drm/i915/display/intel_psr.c
1094
val |= EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);
sys/dev/pci/drm/i915/display/intel_psr.c
1098
val |= EDP_PSR2_SU_SDP_SCANLINE;
sys/dev/pci/drm/i915/display/intel_psr.c
1115
val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
1123
intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_psr.c
1780
u32 val;
sys/dev/pci/drm/i915/display/intel_psr.c
1810
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
1812
if (val & PSR2_MAN_TRK_CTL_ENABLE)
sys/dev/pci/drm/i915/display/intel_psr.c
1819
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
1821
pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);
sys/dev/pci/drm/i915/display/intel_psr.c
2012
u32 val;
sys/dev/pci/drm/i915/display/intel_psr.c
2025
val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_psr.c
2026
val &= psr_irq_psr_error_bit_get(intel_dp);
sys/dev/pci/drm/i915/display/intel_psr.c
2027
if (val) {
sys/dev/pci/drm/i915/display/intel_psr.c
2043
u32 val;
sys/dev/pci/drm/i915/display/intel_psr.c
2053
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
sys/dev/pci/drm/i915/display/intel_psr.c
2054
intel_dp->psr.dc3co_exit_delay = val;
sys/dev/pci/drm/i915/display/intel_psr.c
2112
u32 val;
sys/dev/pci/drm/i915/display/intel_psr.c
2116
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
2118
drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE);
sys/dev/pci/drm/i915/display/intel_psr.c
2121
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
2123
drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE);
sys/dev/pci/drm/i915/display/intel_psr.c
2134
val = intel_de_rmw(display,
sys/dev/pci/drm/i915/display/intel_psr.c
2138
drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));
sys/dev/pci/drm/i915/display/intel_psr.c
2147
val = intel_de_rmw(display,
sys/dev/pci/drm/i915/display/intel_psr.c
2151
drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE));
sys/dev/pci/drm/i915/display/intel_psr.c
2539
u32 val = man_trk_ctl_enable_bit_get(display);
sys/dev/pci/drm/i915/display/intel_psr.c
2542
val |= man_trk_ctl_partial_frame_bit_get(display);
sys/dev/pci/drm/i915/display/intel_psr.c
2545
val |= man_trk_ctl_continuos_full_frame(display);
sys/dev/pci/drm/i915/display/intel_psr.c
2553
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1);
sys/dev/pci/drm/i915/display/intel_psr.c
2554
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1);
sys/dev/pci/drm/i915/display/intel_psr.c
2560
val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(
sys/dev/pci/drm/i915/display/intel_psr.c
2562
val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(
sys/dev/pci/drm/i915/display/intel_psr.c
2566
crtc_state->psr2_man_track_ctl = val;
sys/dev/pci/drm/i915/display/intel_psr.c
2976
u32 val = man_trk_ctl_enable_bit_get(display);
sys/dev/pci/drm/i915/display/intel_psr.c
2979
val |= man_trk_ctl_partial_frame_bit_get(display);
sys/dev/pci/drm/i915/display/intel_psr.c
2980
val |= man_trk_ctl_continuos_full_frame(display);
sys/dev/pci/drm/i915/display/intel_psr.c
2983
intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val);
sys/dev/pci/drm/i915/display/intel_psr.c
3284
int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
sys/dev/pci/drm/i915/display/intel_psr.c
3287
const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
sys/dev/pci/drm/i915/display/intel_psr.c
3288
const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
sys/dev/pci/drm/i915/display/intel_psr.c
3293
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
sys/dev/pci/drm/i915/display/intel_psr.c
3297
drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val);
sys/dev/pci/drm/i915/display/intel_psr.c
3310
intel_dp->psr.debug = val;
sys/dev/pci/drm/i915/display/intel_psr.c
3672
u8 val;
sys/dev/pci/drm/i915/display/intel_psr.c
3675
r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
sys/dev/pci/drm/i915/display/intel_psr.c
3681
if (val & DP_PSR_CAPS_CHANGE) {
sys/dev/pci/drm/i915/display/intel_psr.c
3688
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
sys/dev/pci/drm/i915/display/intel_psr.c
395
u32 val, bool sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
397
drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val);
sys/dev/pci/drm/i915/display/intel_psr.c
398
if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
sys/dev/pci/drm/i915/display/intel_psr.c
400
if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
4014
u32 val, status_val;
sys/dev/pci/drm/i915/display/intel_psr.c
402
if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
sys/dev/pci/drm/i915/display/intel_psr.c
4031
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
4033
status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
sys/dev/pci/drm/i915/display/intel_psr.c
404
if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
sys/dev/pci/drm/i915/display/intel_psr.c
4047
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
4049
status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val);
sys/dev/pci/drm/i915/display/intel_psr.c
4054
seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
sys/dev/pci/drm/i915/display/intel_psr.c
406
if (val & PSR_EVENT_GRAPHICS_RESET)
sys/dev/pci/drm/i915/display/intel_psr.c
408
if (val & PSR_EVENT_PCH_INTERRUPT)
sys/dev/pci/drm/i915/display/intel_psr.c
410
if (val & PSR_EVENT_MEMORY_UP)
sys/dev/pci/drm/i915/display/intel_psr.c
4115
u32 val, psr2_ctl;
sys/dev/pci/drm/i915/display/intel_psr.c
412
if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
sys/dev/pci/drm/i915/display/intel_psr.c
4135
val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_psr.c
414
if (val & PSR_EVENT_WD_TIMER_EXPIRE)
sys/dev/pci/drm/i915/display/intel_psr.c
4142
enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
4144
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
4146
enabled = val & EDP_PSR2_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
4148
val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_psr.c
4149
enabled = val & EDP_PSR_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
4152
str_enabled_disabled(enabled), val);
sys/dev/pci/drm/i915/display/intel_psr.c
416
if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
sys/dev/pci/drm/i915/display/intel_psr.c
4163
val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_psr.c
4165
REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));
sys/dev/pci/drm/i915/display/intel_psr.c
418
if (val & PSR_EVENT_REGISTER_UPDATE)
sys/dev/pci/drm/i915/display/intel_psr.c
4187
val = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_psr.c
4189
su_frames_val[frame / 3] = val;
sys/dev/pci/drm/i915/display/intel_psr.c
420
if (val & PSR_EVENT_HDCP_ENABLE)
sys/dev/pci/drm/i915/display/intel_psr.c
422
if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
sys/dev/pci/drm/i915/display/intel_psr.c
4238
i915_edp_psr_debug_set(void *data, u64 val)
sys/dev/pci/drm/i915/display/intel_psr.c
424
if (val & PSR_EVENT_VBI_ENABLE)
sys/dev/pci/drm/i915/display/intel_psr.c
4250
drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val);
sys/dev/pci/drm/i915/display/intel_psr.c
4254
ret = intel_psr_debug_set(intel_dp, val);
sys/dev/pci/drm/i915/display/intel_psr.c
426
if (val & PSR_EVENT_LPSP_MODE_EXIT)
sys/dev/pci/drm/i915/display/intel_psr.c
4261
i915_edp_psr_debug_get(void *data, u64 *val)
sys/dev/pci/drm/i915/display/intel_psr.c
4273
*val = READ_ONCE(intel_dp->psr.debug);
sys/dev/pci/drm/i915/display/intel_psr.c
428
if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
452
u32 val;
sys/dev/pci/drm/i915/display/intel_psr.c
454
val = intel_de_rmw(display,
sys/dev/pci/drm/i915/display/intel_psr.c
458
psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
sys/dev/pci/drm/i915/display/intel_psr.c
486
u8 val = 8; /* assume the worst if we can't read the value */
sys/dev/pci/drm/i915/display/intel_psr.c
489
DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
sys/dev/pci/drm/i915/display/intel_psr.c
490
val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
sys/dev/pci/drm/i915/display/intel_psr.c
494
return val;
sys/dev/pci/drm/i915/display/intel_psr.c
757
u8 val = DP_PANEL_REPLAY_ENABLE |
sys/dev/pci/drm/i915/display/intel_psr.c
765
val |= DP_PANEL_REPLAY_SU_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
768
val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
sys/dev/pci/drm/i915/display/intel_psr.c
774
drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
sys/dev/pci/drm/i915/display/intel_psr.c
784
u8 val = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
787
val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
sys/dev/pci/drm/i915/display/intel_psr.c
790
val |= DP_PSR_MAIN_LINK_ACTIVE;
sys/dev/pci/drm/i915/display/intel_psr.c
793
val |= DP_PSR_CRC_VERIFICATION;
sys/dev/pci/drm/i915/display/intel_psr.c
797
val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
sys/dev/pci/drm/i915/display/intel_psr.c
800
val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
sys/dev/pci/drm/i915/display/intel_psr.c
803
val |= DP_PSR_FRAME_CAPTURE;
sys/dev/pci/drm/i915/display/intel_psr.c
804
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
sys/dev/pci/drm/i915/display/intel_psr.c
806
val |= DP_PSR_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
807
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
sys/dev/pci/drm/i915/display/intel_psr.c
839
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
842
val |= EDP_PSR_TP4_TIME_0us;
sys/dev/pci/drm/i915/display/intel_psr.c
845
val |= EDP_PSR_TP1_TIME_2500us;
sys/dev/pci/drm/i915/display/intel_psr.c
846
val |= EDP_PSR_TP2_TP3_TIME_2500us;
sys/dev/pci/drm/i915/display/intel_psr.c
851
val |= EDP_PSR_TP1_TIME_0us;
sys/dev/pci/drm/i915/display/intel_psr.c
853
val |= EDP_PSR_TP1_TIME_100us;
sys/dev/pci/drm/i915/display/intel_psr.c
855
val |= EDP_PSR_TP1_TIME_500us;
sys/dev/pci/drm/i915/display/intel_psr.c
857
val |= EDP_PSR_TP1_TIME_2500us;
sys/dev/pci/drm/i915/display/intel_psr.c
860
val |= EDP_PSR_TP2_TP3_TIME_0us;
sys/dev/pci/drm/i915/display/intel_psr.c
862
val |= EDP_PSR_TP2_TP3_TIME_100us;
sys/dev/pci/drm/i915/display/intel_psr.c
864
val |= EDP_PSR_TP2_TP3_TIME_500us;
sys/dev/pci/drm/i915/display/intel_psr.c
866
val |= EDP_PSR_TP2_TP3_TIME_2500us;
sys/dev/pci/drm/i915/display/intel_psr.c
875
val |= EDP_PSR_TP2_TP3_TIME_100us;
sys/dev/pci/drm/i915/display/intel_psr.c
880
val |= EDP_PSR_TP_TP1_TP3;
sys/dev/pci/drm/i915/display/intel_psr.c
882
val |= EDP_PSR_TP_TP1_TP2;
sys/dev/pci/drm/i915/display/intel_psr.c
884
return val;
sys/dev/pci/drm/i915/display/intel_psr.c
923
u32 val = EDP_PSR_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
925
val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
sys/dev/pci/drm/i915/display/intel_psr.c
928
val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
sys/dev/pci/drm/i915/display/intel_psr.c
931
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
sys/dev/pci/drm/i915/display/intel_psr.c
934
val |= EDP_PSR_LINK_STANDBY;
sys/dev/pci/drm/i915/display/intel_psr.c
936
val |= intel_psr1_get_tp_time(intel_dp);
sys/dev/pci/drm/i915/display/intel_psr.c
939
val |= EDP_PSR_CRC_ENABLE;
sys/dev/pci/drm/i915/display/intel_psr.c
942
val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
sys/dev/pci/drm/i915/display/intel_psr.c
945
~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);
sys/dev/pci/drm/i915/display/intel_psr.c
960
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
967
val |= EDP_PSR2_TP2_TIME_50us;
sys/dev/pci/drm/i915/display/intel_psr.c
969
val |= EDP_PSR2_TP2_TIME_100us;
sys/dev/pci/drm/i915/display/intel_psr.c
971
val |= EDP_PSR2_TP2_TIME_500us;
sys/dev/pci/drm/i915/display/intel_psr.c
973
val |= EDP_PSR2_TP2_TIME_2500us;
sys/dev/pci/drm/i915/display/intel_psr.c
975
return val;
sys/dev/pci/drm/i915/display/intel_psr_regs.h
240
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
242
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
247
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
249
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
296
#define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
301
#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
306
#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
308
#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
310
#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
312
#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
315
#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
322
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
324
#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
326
#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
334
#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
336
#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
338
#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
sys/dev/pci/drm/i915/display/intel_psr_regs.h
340
#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
sys/dev/pci/drm/i915/display/intel_sbi.c
18
u32 *val, bool is_read)
sys/dev/pci/drm/i915/display/intel_sbi.c
30
intel_de_write_fw(display, SBI_DATA, is_read ? 0 : *val);
sys/dev/pci/drm/i915/display/intel_sbi.c
51
*val = intel_de_read_fw(display, SBI_DATA);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1200
u8 val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1205
if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1))
sys/dev/pci/drm/i915/display/intel_sdvo.c
1208
if ((val & SDVO_AUDIO_ELD_VALID) == 0)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1462
val = input; \
sys/dev/pci/drm/i915/display/intel_sdvo.c
1463
intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
sys/dev/pci/drm/i915/display/intel_sdvo.c
1472
u16 val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1670
u32 val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1672
val = intel_de_read(display, sdvo_reg);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1676
*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1678
*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1680
*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1682
return val & SDVO_ENABLE;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1709
u8 val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1760
&val, 1)) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1761
switch (val) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1780
&val, 1)) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1781
if (val == SDVO_COLORIMETRY_RGB220)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1786
&val, 1)) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1787
if (val & SDVO_AUDIO_PRESENCE_DETECT)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1792
&val, 1)) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1793
if (val == SDVO_ENCODE_HDMI)
sys/dev/pci/drm/i915/display/intel_sdvo.c
214
static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
sys/dev/pci/drm/i915/display/intel_sdvo.c
217
u32 bval = val, cval = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
221
intel_de_write(display, intel_sdvo->sdvo_reg, val);
sys/dev/pci/drm/i915/display/intel_sdvo.c
228
intel_de_write(display, intel_sdvo->sdvo_reg, val);
sys/dev/pci/drm/i915/display/intel_sdvo.c
2376
u64 *val)
sys/dev/pci/drm/i915/display/intel_sdvo.c
2386
*val = i;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2392
*val = 0;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2395
*val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2398
*val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2400
*val = sdvo_state->tv.hpos;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2402
*val = sdvo_state->tv.vpos;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2404
*val = state->tv.saturation;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2406
*val = state->tv.contrast;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2408
*val = state->tv.hue;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2410
*val = state->tv.brightness;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2412
*val = sdvo_state->tv.sharpness;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2414
*val = sdvo_state->tv.flicker_filter;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2416
*val = sdvo_state->tv.flicker_filter_2d;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2418
*val = sdvo_state->tv.flicker_filter_adaptive;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2420
*val = sdvo_state->tv.chroma_filter;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2422
*val = sdvo_state->tv.luma_filter;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2424
*val = sdvo_state->tv.dot_crawl;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2426
return intel_digital_connector_atomic_get_property(connector, state, property, val);
sys/dev/pci/drm/i915/display/intel_sdvo.c
2435
u64 val)
sys/dev/pci/drm/i915/display/intel_sdvo.c
2441
state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val];
sys/dev/pci/drm/i915/display/intel_sdvo.c
2452
sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2456
sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2458
sdvo_state->tv.hpos = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2460
sdvo_state->tv.vpos = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2462
state->tv.saturation = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2464
state->tv.contrast = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2466
state->tv.hue = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2468
state->tv.brightness = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2470
sdvo_state->tv.sharpness = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2472
sdvo_state->tv.flicker_filter = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2474
sdvo_state->tv.flicker_filter_2d = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2476
sdvo_state->tv.flicker_filter_adaptive = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2478
sdvo_state->tv.chroma_filter = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2480
sdvo_state->tv.luma_filter = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2482
sdvo_state->tv.dot_crawl = val;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2484
return intel_digital_connector_atomic_set_property(connector, state, property, val);
sys/dev/pci/drm/i915/display/intel_sdvo.c
823
static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
sys/dev/pci/drm/i915/display/intel_sdvo.c
825
return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
56
u32 val;
sys/dev/pci/drm/i915/display/intel_snps_phy.c
61
val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
sys/dev/pci/drm/i915/display/intel_snps_phy.c
64
SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
81
u32 val = 0;
sys/dev/pci/drm/i915/display/intel_snps_phy.c
83
val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
84
val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
85
val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
87
intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val);
sys/dev/pci/drm/i915/display/intel_tc.c
1105
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
1112
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_tc.c
1114
val |= XELPDP_TCSS_POWER_REQUEST;
sys/dev/pci/drm/i915/display/intel_tc.c
1116
val &= ~XELPDP_TCSS_POWER_REQUEST;
sys/dev/pci/drm/i915/display/intel_tc.c
1117
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_tc.c
1152
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
1156
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_tc.c
1158
val |= XELPDP_TC_PHY_OWNERSHIP;
sys/dev/pci/drm/i915/display/intel_tc.c
1160
val &= ~XELPDP_TC_PHY_OWNERSHIP;
sys/dev/pci/drm/i915/display/intel_tc.c
1161
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_tc.c
302
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
316
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_tc.c
318
drm_WARN_ON(display->drm, val == 0xffffffff);
sys/dev/pci/drm/i915/display/intel_tc.c
321
pin_assignment = (val & mask) >> (ffs(mask) - 1);
sys/dev/pci/drm/i915/display/intel_tc.c
430
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
440
val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));
sys/dev/pci/drm/i915/display/intel_tc.c
441
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc->phy_fia_idx);
sys/dev/pci/drm/i915/display/intel_tc.c
445
val |= lane_reversal ?
sys/dev/pci/drm/i915/display/intel_tc.c
450
val |= lane_reversal ?
sys/dev/pci/drm/i915/display/intel_tc.c
455
val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc->phy_fia_idx);
sys/dev/pci/drm/i915/display/intel_tc.c
461
intel_de_write(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia), val);
sys/dev/pci/drm/i915/display/intel_tc.c
569
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
573
val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));
sys/dev/pci/drm/i915/display/intel_tc.c
574
if (val == 0xffffffff) {
sys/dev/pci/drm/i915/display/intel_tc.c
581
return val & DP_PHY_MODE_STATUS_COMPLETED(tc->phy_fia_idx);
sys/dev/pci/drm/i915/display/intel_tc.c
588
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
592
val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
sys/dev/pci/drm/i915/display/intel_tc.c
593
if (val == 0xffffffff) {
sys/dev/pci/drm/i915/display/intel_tc.c
601
val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);
sys/dev/pci/drm/i915/display/intel_tc.c
603
val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);
sys/dev/pci/drm/i915/display/intel_tc.c
605
intel_de_write(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia), val);
sys/dev/pci/drm/i915/display/intel_tc.c
613
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
617
val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
sys/dev/pci/drm/i915/display/intel_tc.c
618
if (val == 0xffffffff) {
sys/dev/pci/drm/i915/display/intel_tc.c
625
return val & DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);
sys/dev/pci/drm/i915/display/intel_tc.c
778
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
781
val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));
sys/dev/pci/drm/i915/display/intel_tc.c
783
drm_WARN_ON(display->drm, val == 0xffffffff);
sys/dev/pci/drm/i915/display/intel_tc.c
785
tc_phy_load_fia_params(tc, val & MODULAR_FIA_MASK);
sys/dev/pci/drm/i915/display/intel_tc.c
854
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
858
val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));
sys/dev/pci/drm/i915/display/intel_tc.c
859
if (val == 0xffffffff) {
sys/dev/pci/drm/i915/display/intel_tc.c
866
return val & TCSS_DDI_STATUS_READY;
sys/dev/pci/drm/i915/display/intel_tc.c
887
u32 val;
sys/dev/pci/drm/i915/display/intel_tc.c
891
val = intel_de_read(display, DDI_BUF_CTL(port));
sys/dev/pci/drm/i915/display/intel_tc.c
892
return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
sys/dev/pci/drm/i915/display/intel_vdsc.c
763
u32 val;
sys/dev/pci/drm/i915/display/intel_vdsc.c
768
val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame);
sys/dev/pci/drm/i915/display/intel_vdsc.c
769
val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines);
sys/dev/pci/drm/i915/display/intel_vdsc.c
771
intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
774
intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
865
u32 val;
sys/dev/pci/drm/i915/display/intel_vdsc.c
876
val = intel_de_read(display, dsc_reg[0]);
sys/dev/pci/drm/i915/display/intel_vdsc.c
879
if (intel_de_read(display, dsc_reg[i]) != val) {
sys/dev/pci/drm/i915/display/intel_vdsc.c
885
return val;
sys/dev/pci/drm/i915/display/intel_vdsc.c
891
u32 val;
sys/dev/pci/drm/i915/display/intel_vdsc.c
894
val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
sys/dev/pci/drm/i915/display/intel_vdsc.c
897
return val;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1484
u32 val;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1496
val = y << 16;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1497
val |= plane_state->uapi.dst.x1;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1498
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1511
val = y << 16 | x;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1513
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1516
val = (drm_rect_height(clip) - 1) << 16;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1517
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1518
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3013
u32 val, base, offset, stride_mult, tiling, alpha;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3042
val = intel_de_read(display, PLANE_CTL(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3045
pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3047
pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3055
alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3059
val & PLANE_CTL_ORDER_RGBX, alpha);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3062
tiling = val & PLANE_CTL_TILED_MASK;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3073
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3080
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3093
if ((val & rc_mask) == rc_mask)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3095
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3097
else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3102
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3123
switch (val & PLANE_CTL_ROTATE_MASK) {
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3138
if (DISPLAY_VER(display) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3151
val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3152
fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3153
fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3155
val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3158
fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
798
u32 val = 0;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
801
val |= PLANE_MIN_DBUF_BLOCKS(*min_ddb);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
804
val |= PLANE_INTERIM_DBUF_BLOCKS(*interim_ddb);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
806
val |= val ? PLANE_AUTO_MIN_DBUF_EN : 0;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
808
return val;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
813
u32 val = 0;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
816
val |= PLANE_WM_EN;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
818
val |= PLANE_WM_IGNORE_LINES;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
820
val |= PLANE_WM_AUTO_MIN_ALLOC_EN;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
822
val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
823
val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
825
return val;
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
393
#define PLANE_MIN_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
sys/dev/pci/drm/i915/display/skl_universal_plane_regs.h
395
#define PLANE_INTERIM_DBUF_BLOCKS(val) REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
sys/dev/pci/drm/i915/display/skl_watermark.c
106
u32 val;
sys/dev/pci/drm/i915/display/skl_watermark.c
108
val = intel_de_read(display, MTL_LATENCY_SAGV);
sys/dev/pci/drm/i915/display/skl_watermark.c
110
return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
112
u32 val = 0;
sys/dev/pci/drm/i915/display/skl_watermark.c
117
&val, NULL);
sys/dev/pci/drm/i915/display/skl_watermark.c
123
return val;
sys/dev/pci/drm/i915/display/skl_watermark.c
2998
u32 val, struct skl_wm_level *level)
sys/dev/pci/drm/i915/display/skl_watermark.c
3000
level->enable = val & PLANE_WM_EN;
sys/dev/pci/drm/i915/display/skl_watermark.c
3001
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
sys/dev/pci/drm/i915/display/skl_watermark.c
3002
level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3003
level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3005
val & PLANE_WM_AUTO_MIN_ALLOC_EN : 0;
sys/dev/pci/drm/i915/display/skl_watermark.c
3015
u32 val;
sys/dev/pci/drm/i915/display/skl_watermark.c
3022
val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));
sys/dev/pci/drm/i915/display/skl_watermark.c
3024
val = intel_de_read(display, CUR_WM(pipe, level));
sys/dev/pci/drm/i915/display/skl_watermark.c
3026
skl_wm_level_from_reg_val(display, val, &wm->wm[level]);
sys/dev/pci/drm/i915/display/skl_watermark.c
3030
val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_watermark.c
3032
val = intel_de_read(display, CUR_WM_TRANS(pipe));
sys/dev/pci/drm/i915/display/skl_watermark.c
3034
skl_wm_level_from_reg_val(display, val, &wm->trans_wm);
sys/dev/pci/drm/i915/display/skl_watermark.c
3038
val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_watermark.c
3040
val = intel_de_read(display, CUR_WM_SAGV(pipe));
sys/dev/pci/drm/i915/display/skl_watermark.c
3042
skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);
sys/dev/pci/drm/i915/display/skl_watermark.c
3045
val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_watermark.c
3047
val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
sys/dev/pci/drm/i915/display/skl_watermark.c
3049
skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);
sys/dev/pci/drm/i915/display/skl_watermark.c
3224
u32 val;
sys/dev/pci/drm/i915/display/skl_watermark.c
3226
val = intel_de_read(display, MTL_LATENCY_LP0_LP1);
sys/dev/pci/drm/i915/display/skl_watermark.c
3227
wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3228
wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3230
val = intel_de_read(display, MTL_LATENCY_LP2_LP3);
sys/dev/pci/drm/i915/display/skl_watermark.c
3231
wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3232
wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3234
val = intel_de_read(display, MTL_LATENCY_LP4_LP5);
sys/dev/pci/drm/i915/display/skl_watermark.c
3235
wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3236
wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
3246
u32 val;
sys/dev/pci/drm/i915/display/skl_watermark.c
3250
val = 0; /* data0 to be programmed to 0 for first set */
sys/dev/pci/drm/i915/display/skl_watermark.c
3251
ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
sys/dev/pci/drm/i915/display/skl_watermark.c
3257
wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3258
wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3259
wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3260
wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3263
val = 1; /* data0 to be programmed to 1 for second set */
sys/dev/pci/drm/i915/display/skl_watermark.c
3264
ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
sys/dev/pci/drm/i915/display/skl_watermark.c
3270
wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3271
wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3272
wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3273
wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;
sys/dev/pci/drm/i915/display/skl_watermark.c
3365
u32 val = 0;
sys/dev/pci/drm/i915/display/skl_watermark.c
3368
val |= MBUS_DBOX_I_CREDIT(2);
sys/dev/pci/drm/i915/display/skl_watermark.c
3371
val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
sys/dev/pci/drm/i915/display/skl_watermark.c
3372
val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
sys/dev/pci/drm/i915/display/skl_watermark.c
3373
val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
sys/dev/pci/drm/i915/display/skl_watermark.c
3377
val |= dbuf_state->joined_mbus ?
sys/dev/pci/drm/i915/display/skl_watermark.c
3381
val |= dbuf_state->joined_mbus ?
sys/dev/pci/drm/i915/display/skl_watermark.c
3384
val |= MBUS_DBOX_A_CREDIT(2);
sys/dev/pci/drm/i915/display/skl_watermark.c
3387
val |= MBUS_DBOX_B_CREDIT(0xA);
sys/dev/pci/drm/i915/display/skl_watermark.c
3389
val |= MBUS_DBOX_BW_CREDIT(2);
sys/dev/pci/drm/i915/display/skl_watermark.c
3390
val |= MBUS_DBOX_B_CREDIT(8);
sys/dev/pci/drm/i915/display/skl_watermark.c
3392
val |= MBUS_DBOX_BW_CREDIT(2);
sys/dev/pci/drm/i915/display/skl_watermark.c
3393
val |= MBUS_DBOX_B_CREDIT(12);
sys/dev/pci/drm/i915/display/skl_watermark.c
3395
val |= MBUS_DBOX_BW_CREDIT(1);
sys/dev/pci/drm/i915/display/skl_watermark.c
3396
val |= MBUS_DBOX_B_CREDIT(8);
sys/dev/pci/drm/i915/display/skl_watermark.c
3401
val |= MBUS_DBOX_BW_8CREDITS_MTL;
sys/dev/pci/drm/i915/display/skl_watermark.c
3403
val |= MBUS_DBOX_BW_4CREDITS_MTL;
sys/dev/pci/drm/i915/display/skl_watermark.c
3406
return val;
sys/dev/pci/drm/i915/display/skl_watermark.c
677
u32 val;
sys/dev/pci/drm/i915/display/skl_watermark.c
681
val = intel_de_read(display, CUR_BUF_CFG(pipe));
sys/dev/pci/drm/i915/display/skl_watermark.c
682
skl_ddb_entry_init_from_hw(ddb, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
686
val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_watermark.c
687
skl_ddb_entry_init_from_hw(ddb, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
690
val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_watermark.c
692
*min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
693
*interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val);
sys/dev/pci/drm/i915/display/skl_watermark.c
699
val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));
sys/dev/pci/drm/i915/display/skl_watermark.c
700
skl_ddb_entry_init_from_hw(ddb_y, val);
sys/dev/pci/drm/i915/display/skl_watermark_regs.h
44
#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
sys/dev/pci/drm/i915/display/vlv_dsi.c
109
u32 val = 0;
sys/dev/pci/drm/i915/display/vlv_dsi.c
112
val |= *data++ << 8 * j;
sys/dev/pci/drm/i915/display/vlv_dsi.c
114
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/vlv_dsi.c
125
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/vlv_dsi.c
128
*data++ = val >> 8 * j;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1312
u32 val, tmp;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1361
val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1363
val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1364
val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
sys/dev/pci/drm/i915/display/vlv_dsi.c
1366
val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
sys/dev/pci/drm/i915/display/vlv_dsi.c
1367
val |= pixel_format_to_reg(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1383
intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);
sys/dev/pci/drm/i915/display/vlv_dsi.c
436
u32 val;
sys/dev/pci/drm/i915/display/vlv_dsi.c
448
val = intel_de_read(display, MIPI_DEVICE_READY(display, port));
sys/dev/pci/drm/i915/display/vlv_dsi.c
449
val &= ~ULPS_STATE_MASK;
sys/dev/pci/drm/i915/display/vlv_dsi.c
450
intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
sys/dev/pci/drm/i915/display/vlv_dsi.c
452
val |= DEVICE_READY;
sys/dev/pci/drm/i915/display/vlv_dsi.c
453
intel_de_write(display, MIPI_DEVICE_READY(display, port), val);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
217
u32 val;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
236
ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL),
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
237
val & DSI_PLL_LOCK,
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
274
u32 val;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
278
val = intel_de_read(display, BXT_DSI_PLL_ENABLE);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
279
enabled = (val & mask) == mask;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
292
val = intel_de_read(display, BXT_DSI_PLL_CTL);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
294
if (!(val & BXT_DSIA_16X_MASK)) {
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
296
"Invalid PLL divider (%08x)\n", val);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
300
if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
302
"Invalid PLL divider (%08x)\n", val);
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
36
#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
37
(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
49
#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
50
(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
62
#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
63
(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
75
#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
sys/dev/pci/drm/i915/display/vlv_dsi_pll_regs.h
76
(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
sys/dev/pci/drm/i915/display/vlv_sideband.c
28
u32 val;
sys/dev/pci/drm/i915/display/vlv_sideband.c
30
val = vlv_iosf_sb_read(drm, unit, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.c
36
drm_WARN(display->drm, val == 0xffffffff,
sys/dev/pci/drm/i915/display/vlv_sideband.c
38
phy, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.c
40
return val;
sys/dev/pci/drm/i915/display/vlv_sideband.c
44
enum dpio_phy phy, int reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.c
49
vlv_iosf_sb_write(drm, unit, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
111
static inline void vlv_flisdsi_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
113
vlv_iosf_sb_write(drm, VLV_IOSF_SB_FLISDSI, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
146
static inline int vlv_punit_write(struct drm_device *drm, u32 addr, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
148
return vlv_iosf_sb_write(drm, VLV_IOSF_SB_PUNIT, addr, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
26
static inline void vlv_bunit_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
28
vlv_iosf_sb_write(drm, VLV_IOSF_SB_BUNIT, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
46
static inline void vlv_cck_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
48
vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCK, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
66
static inline void vlv_ccu_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
68
vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCU, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
84
enum dpio_phy phy, int reg, u32 val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
91
int phy, int reg, u32 val)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1058
u32 val)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1069
vma->size >> PAGE_SHIFT, val);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1073
__cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1090
if (ptr[dword] != val) {
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1092
n, dword, ptr[dword], val);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1108
static int __cpu_check_vmap(struct drm_i915_gem_object *obj, u32 dword, u32 val)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1124
if (*ptr != val) {
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1126
dword, *ptr, val);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1138
static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1141
return __cpu_check_shmem(obj, dword, val);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1143
return __cpu_check_vmap(obj, dword, val);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1149
u32 dword, u32 val)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1175
err = gpu_write(ce, vma, dword, val);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1181
err = cpu_check(obj, dword, val);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
333
static void fill_scratch(struct tiled_blits *t, u32 *vaddr, u32 val)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
337
t->scratch.start_val = val;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
339
vaddr[i] = val++;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1098
u32 *buf, val;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1127
val = *buf;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1128
cnt = (val & s_mask) >> s_shift;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1129
*rpcs = val;
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
113
unsigned long count, u32 val)
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
123
batch = igt_emit_store_dw(vma, offset, count, val);
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
45
u32 val)
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
73
*cmd++ = val;
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
79
*cmd++ = val;
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
83
*cmd++ = val;
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h
28
u32 val);
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h
32
unsigned long count, u32 val);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1168
u32 val;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1223
val = 1;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1226
val = 0;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1228
val = instance;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1231
val = BIT(val);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1235
engine->tlb_inv.done = val;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1242
engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1244
engine->tlb_inv.request = val;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1726
u32 val;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1731
val = intel_uncore_read(engine->uncore, _reg[engine->id]);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1734
return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
107
intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
108
intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
115
u32 val;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
117
val = 0;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
129
val = fence->start;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
131
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
132
val |= I915_FENCE_SIZE_BITS(fence->size);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
133
val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
135
val |= I830_FENCE_REG_VALID;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
142
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
149
u32 val;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
151
val = 0;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
155
val = fence->start;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
157
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
158
val |= I830_FENCE_SIZE_BITS(fence->size);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
159
val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
160
val |= I830_FENCE_REG_VALID;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
167
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
63
u64 val;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
76
val = 0;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
82
val = fence->start + fence->size - I965_FENCE_PAGE;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
83
val <<= 32;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
84
val |= fence->start;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
85
val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
87
val |= BIT(I965_FENCE_TILING_Y_SHIFT);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
88
val |= I965_FENCE_REG_VALID;
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
223
u64 val;
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
232
val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
234
val = div_u64_roundup(val, 25) * 25;
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
236
return val;
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
17
int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val)
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
23
*val = 1;
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
26
*val = 0;
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
33
void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
39
intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
40
"Manually reset engine mask to %llx", val);
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
47
static int __intel_gt_debugfs_reset_show(void *data, u64 *val)
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
49
return intel_gt_debugfs_reset_show(data, val);
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
54
static int __intel_gt_debugfs_reset_store(void *data, u64 val)
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c
56
intel_gt_debugfs_reset_store(data, val);
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.h
52
int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val);
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.h
53
void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
212
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
266
val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
281
return val;
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
292
u32 val;
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
304
val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
310
return val;
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
541
u32 val = intel_gt_mcr_read_any(gt, reg);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
543
intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
545
return val;
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
550
static int perf_limit_reasons_get(void *data, u64 *val)
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
556
*val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
561
static int perf_limit_reasons_clear(void *data, u64 val)
sys/dev/pci/drm/i915/gt/intel_gt_regs.h
454
#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
104
u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
107
return sysfs_emit(buff, "%u\n", val); \
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
126
u32 val; \
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
128
ret = kstrtou32(buff, 0, &val); \
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
132
ret = sysfs_gt_attribute_w_func(kobj, attr, _func, val); \
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
31
int (func)(struct intel_gt *gt, u32 val), u32 val)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
330
static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
332
return intel_rps_set_boost_frequency(>->rps, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
355
static int __set_max_freq(struct intel_gt *gt, u32 val)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
357
return intel_rps_set_max_frequency(>->rps, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
365
static int __set_min_freq(struct intel_gt *gt, u32 val)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
367
return intel_rps_set_min_frequency(>->rps, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
42
ret = func(gt, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
459
u32 val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
461
err = kstrtou32(buff, 0, &val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
465
err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
48
ret = func(gt, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
495
u32 val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
498
val = SLPC_POWER_PROFILES_POWER_SAVING;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
500
val = SLPC_POWER_PROFILES_BASE;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
504
err = intel_guc_slpc_set_power_profile(slpc, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
523
bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
525
return sysfs_emit(buff, "%u\n", val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
668
u32 val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
673
PCODE_MBOX_DOMAIN_MEDIAFF, &val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
679
val *= GT_FREQUENCY_MULTIPLIER;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
681
return sysfs_emit(buff, "%u\n", val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
689
u32 val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
694
PCODE_MBOX_DOMAIN_MEDIAFF, &val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
70
u32 val = func(gt);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
700
val *= GT_FREQUENCY_MULTIPLIER;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
702
return sysfs_emit(buff, "%u\n", val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
739
u8 val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
74
if (val < ret)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
741
ret = kstrtou8(buf, 10, &val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
745
ret = intel_rps_set_up_threshold(rps, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
75
ret = val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
773
u8 val;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
775
ret = kstrtou8(buf, 10, &val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
779
ret = intel_rps_set_down_threshold(rps, val);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
79
if (val > ret)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
80
ret = val;
sys/dev/pci/drm/i915/gt/intel_gtt.c
338
fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
sys/dev/pci/drm/i915/gt/intel_gtt.c
342
memset64(vaddr, val, count);
sys/dev/pci/drm/i915/gt/intel_gtt.c
349
u8 val;
sys/dev/pci/drm/i915/gt/intel_gtt.c
351
val = 0;
sys/dev/pci/drm/i915/gt/intel_gtt.c
353
val = POISON_FREE;
sys/dev/pci/drm/i915/gt/intel_gtt.c
355
memset(vaddr, val, scratch->base.size);
sys/dev/pci/drm/i915/gt/intel_gtt.h
625
fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
sys/dev/pci/drm/i915/gt/intel_renderstate.c
43
#define OUT_BATCH(batch, i, val) \
sys/dev/pci/drm/i915/gt/intel_renderstate.c
47
(batch)[(i)++] = (val); \
sys/dev/pci/drm/i915/gt/intel_rps.c
1077
int intel_rps_set(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1082
GEM_BUG_ON(val > rps->max_freq);
sys/dev/pci/drm/i915/gt/intel_rps.c
1083
GEM_BUG_ON(val < rps->min_freq);
sys/dev/pci/drm/i915/gt/intel_rps.c
1086
err = rps_set(rps, val, true);
sys/dev/pci/drm/i915/gt/intel_rps.c
1098
GEN6_RP_INTERRUPT_LIMITS, rps_limits(rps, val));
sys/dev/pci/drm/i915/gt/intel_rps.c
1100
set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val));
sys/dev/pci/drm/i915/gt/intel_rps.c
1104
rps->cur_freq = val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1290
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1292
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE);
sys/dev/pci/drm/i915/gt/intel_rps.c
1297
val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1301
val >>= FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1307
val >>= FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1311
return val & FB_GFX_FREQ_FUSE_MASK;
sys/dev/pci/drm/i915/gt/intel_rps.c
1317
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1319
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_GPU_DUTYCYCLE_REG);
sys/dev/pci/drm/i915/gt/intel_rps.c
1320
val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1322
return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
sys/dev/pci/drm/i915/gt/intel_rps.c
1328
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1330
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE);
sys/dev/pci/drm/i915/gt/intel_rps.c
1332
return val & FB_GFX_FREQ_FUSE_MASK;
sys/dev/pci/drm/i915/gt/intel_rps.c
1338
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1340
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, FB_GFX_FMIN_AT_VMIN_FUSE);
sys/dev/pci/drm/i915/gt/intel_rps.c
1341
val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1343
return val & FB_GFX_FREQ_FUSE_MASK;
sys/dev/pci/drm/i915/gt/intel_rps.c
1350
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1376
val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
sys/dev/pci/drm/i915/gt/intel_rps.c
1377
vlv_iosf_sb_write(&i915->drm, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1379
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
sys/dev/pci/drm/i915/gt/intel_rps.c
1384
drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
sys/dev/pci/drm/i915/gt/intel_rps.c
1388
str_yes_no(val & GPLLENABLE));
sys/dev/pci/drm/i915/gt/intel_rps.c
1389
drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1397
u32 val, rp1;
sys/dev/pci/drm/i915/gt/intel_rps.c
1399
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE);
sys/dev/pci/drm/i915/gt/intel_rps.c
1401
rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK;
sys/dev/pci/drm/i915/gt/intel_rps.c
1410
u32 val, rp0;
sys/dev/pci/drm/i915/gt/intel_rps.c
1412
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE);
sys/dev/pci/drm/i915/gt/intel_rps.c
1414
rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1424
u32 val, rpe;
sys/dev/pci/drm/i915/gt/intel_rps.c
1426
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
sys/dev/pci/drm/i915/gt/intel_rps.c
1427
rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
sys/dev/pci/drm/i915/gt/intel_rps.c
1428
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
sys/dev/pci/drm/i915/gt/intel_rps.c
1429
rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
sys/dev/pci/drm/i915/gt/intel_rps.c
1437
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1439
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_LFM) & 0xff;
sys/dev/pci/drm/i915/gt/intel_rps.c
1447
return max_t(u32, val, 0xc0);
sys/dev/pci/drm/i915/gt/intel_rps.c
1454
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1478
val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
sys/dev/pci/drm/i915/gt/intel_rps.c
1479
vlv_iosf_sb_write(&i915->drm, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1481
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
sys/dev/pci/drm/i915/gt/intel_rps.c
1486
drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
sys/dev/pci/drm/i915/gt/intel_rps.c
1490
str_yes_no(val & GPLLENABLE));
sys/dev/pci/drm/i915/gt/intel_rps.c
1491
drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1628
static int byt_gpu_freq(struct intel_rps *rps, int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1634
return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
sys/dev/pci/drm/i915/gt/intel_rps.c
1637
static int byt_freq_opcode(struct intel_rps *rps, int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1639
return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
sys/dev/pci/drm/i915/gt/intel_rps.c
1642
static int chv_gpu_freq(struct intel_rps *rps, int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1648
return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
sys/dev/pci/drm/i915/gt/intel_rps.c
1651
static int chv_freq_opcode(struct intel_rps *rps, int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1654
return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
sys/dev/pci/drm/i915/gt/intel_rps.c
1657
int intel_gpu_freq(struct intel_rps *rps, int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1662
return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
sys/dev/pci/drm/i915/gt/intel_rps.c
1665
return chv_gpu_freq(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1667
return byt_gpu_freq(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1669
return val * GT_FREQUENCY_MULTIPLIER;
sys/dev/pci/drm/i915/gt/intel_rps.c
1671
return val;
sys/dev/pci/drm/i915/gt/intel_rps.c
1674
int intel_freq_opcode(struct intel_rps *rps, int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
1679
return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
sys/dev/pci/drm/i915/gt/intel_rps.c
1682
return chv_freq_opcode(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1684
return byt_freq_opcode(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
1686
return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
sys/dev/pci/drm/i915/gt/intel_rps.c
1688
return val;
sys/dev/pci/drm/i915/gt/intel_rps.c
174
static u32 rps_pm_mask(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
179
if (val > rps->min_freq_softlimit)
sys/dev/pci/drm/i915/gt/intel_rps.c
184
if (val < rps->max_freq_softlimit)
sys/dev/pci/drm/i915/gt/intel_rps.c
2479
static int set_max_freq(struct intel_rps *rps, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
2486
val = intel_freq_opcode(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2487
if (val < rps->min_freq ||
sys/dev/pci/drm/i915/gt/intel_rps.c
2488
val > rps->max_freq ||
sys/dev/pci/drm/i915/gt/intel_rps.c
2489
val < rps->min_freq_softlimit) {
sys/dev/pci/drm/i915/gt/intel_rps.c
2494
if (val > rps->rp0_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
2496
intel_gpu_freq(rps, val));
sys/dev/pci/drm/i915/gt/intel_rps.c
2498
rps->max_freq_softlimit = val;
sys/dev/pci/drm/i915/gt/intel_rps.c
2500
val = clamp_t(int, rps->cur_freq,
sys/dev/pci/drm/i915/gt/intel_rps.c
2509
intel_rps_set(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2517
int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
2522
return intel_guc_slpc_set_max_freq(slpc, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2524
return set_max_freq(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2562
static int set_min_freq(struct intel_rps *rps, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
2568
val = intel_freq_opcode(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2569
if (val < rps->min_freq ||
sys/dev/pci/drm/i915/gt/intel_rps.c
2570
val > rps->max_freq ||
sys/dev/pci/drm/i915/gt/intel_rps.c
2571
val > rps->max_freq_softlimit) {
sys/dev/pci/drm/i915/gt/intel_rps.c
2576
rps->min_freq_softlimit = val;
sys/dev/pci/drm/i915/gt/intel_rps.c
2578
val = clamp_t(int, rps->cur_freq,
sys/dev/pci/drm/i915/gt/intel_rps.c
2587
intel_rps_set(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2595
int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
2600
return intel_guc_slpc_set_min_freq(slpc, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2602
return set_min_freq(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
2610
static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
2614
if (val > 100)
sys/dev/pci/drm/i915/gt/intel_rps.c
2621
if (*threshold == val)
sys/dev/pci/drm/i915/gt/intel_rps.c
2624
*threshold = val;
sys/dev/pci/drm/i915/gt/intel_rps.c
2720
u32 val;
sys/dev/pci/drm/i915/gt/intel_rps.c
2723
val = intel_uncore_read(gt->uncore, reg32);
sys/dev/pci/drm/i915/gt/intel_rps.c
2725
return val;
sys/dev/pci/drm/i915/gt/intel_rps.c
431
unsigned int val)
sys/dev/pci/drm/i915/gt/intel_rps.c
434
val = rps->max_freq - val;
sys/dev/pci/drm/i915/gt/intel_rps.c
435
val = rps->min_freq + val;
sys/dev/pci/drm/i915/gt/intel_rps.c
437
return val;
sys/dev/pci/drm/i915/gt/intel_rps.c
440
static int __gen5_rps_set(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
455
val = gen5_invert_freq(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
459
(val << MEMCTL_FREQ_SHIFT) |
sys/dev/pci/drm/i915/gt/intel_rps.c
470
static int gen5_rps_set(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
475
err = __gen5_rps_set(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
519
unsigned int val;
sys/dev/pci/drm/i915/gt/intel_rps.c
521
val = vid * vid * freq / 1000 * 255;
sys/dev/pci/drm/i915/gt/intel_rps.c
522
val /= 127 * 127 * 900;
sys/dev/pci/drm/i915/gt/intel_rps.c
524
pxw[i] = val;
sys/dev/pci/drm/i915/gt/intel_rps.c
656
static u32 rps_limits(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
670
if (val <= rps->min_freq_softlimit)
sys/dev/pci/drm/i915/gt/intel_rps.c
674
if (val <= rps->min_freq_softlimit)
sys/dev/pci/drm/i915/gt/intel_rps.c
747
static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
75
static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
754
if (val > rps->efficient_freq + 1 &&
sys/dev/pci/drm/i915/gt/intel_rps.c
755
val > rps->cur_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
760
if (val <= rps->efficient_freq &&
sys/dev/pci/drm/i915/gt/intel_rps.c
761
val < rps->cur_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
763
else if (val >= rps->rp0_freq &&
sys/dev/pci/drm/i915/gt/intel_rps.c
764
val > rps->cur_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
769
if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
sys/dev/pci/drm/i915/gt/intel_rps.c
77
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
770
val < rps->cur_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
775
if (val <= rps->min_freq_softlimit)
sys/dev/pci/drm/i915/gt/intel_rps.c
777
if (val >= rps->max_freq_softlimit)
sys/dev/pci/drm/i915/gt/intel_rps.c
803
static int gen6_rps_set(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
812
swreq = GEN9_FREQUENCY(val);
sys/dev/pci/drm/i915/gt/intel_rps.c
814
swreq = HSW_FREQUENCY(val);
sys/dev/pci/drm/i915/gt/intel_rps.c
816
swreq = (GEN6_FREQUENCY(val) |
sys/dev/pci/drm/i915/gt/intel_rps.c
822
val, intel_gpu_freq(rps, val), swreq);
sys/dev/pci/drm/i915/gt/intel_rps.c
827
static int vlv_rps_set(struct intel_rps *rps, u8 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
833
err = vlv_iosf_sb_write(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_REQ, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
837
val, intel_gpu_freq(rps, val));
sys/dev/pci/drm/i915/gt/intel_rps.c
842
static int rps_set(struct intel_rps *rps, u8 val, bool update)
sys/dev/pci/drm/i915/gt/intel_rps.c
847
if (val == rps->last_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
851
err = vlv_rps_set(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
853
err = gen6_rps_set(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
855
err = gen5_rps_set(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
860
gen6_rps_set_thresholds(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
861
rps->last_freq = val;
sys/dev/pci/drm/i915/gt/intel_rps.c
970
static int rps_set_boost_freq(struct intel_rps *rps, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
975
val = intel_freq_opcode(rps, val);
sys/dev/pci/drm/i915/gt/intel_rps.c
976
if (val < rps->min_freq || val > rps->max_freq)
sys/dev/pci/drm/i915/gt/intel_rps.c
980
if (val != rps->boost_freq) {
sys/dev/pci/drm/i915/gt/intel_rps.c
981
rps->boost_freq = val;
sys/dev/pci/drm/i915/gt/intel_rps.h
35
int intel_rps_set(struct intel_rps *rps, u8 val);
sys/dev/pci/drm/i915/gt/intel_rps.h
38
int intel_gpu_freq(struct intel_rps *rps, int val);
sys/dev/pci/drm/i915/gt/intel_rps.h
39
int intel_freq_opcode(struct intel_rps *rps, int val);
sys/dev/pci/drm/i915/gt/intel_rps.h
49
int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);
sys/dev/pci/drm/i915/gt/intel_rps.h
52
int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);
sys/dev/pci/drm/i915/gt/intel_sseu.c
719
u32 mask, val = slices;
sys/dev/pci/drm/i915/gt/intel_sseu.c
723
val <<= GEN11_RPCS_S_CNT_SHIFT;
sys/dev/pci/drm/i915/gt/intel_sseu.c
726
val <<= GEN8_RPCS_S_CNT_SHIFT;
sys/dev/pci/drm/i915/gt/intel_sseu.c
729
GEM_BUG_ON(val & ~mask);
sys/dev/pci/drm/i915/gt/intel_sseu.c
730
val &= mask;
sys/dev/pci/drm/i915/gt/intel_sseu.c
732
rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
sys/dev/pci/drm/i915/gt/intel_sseu.c
736
u32 val = subslices;
sys/dev/pci/drm/i915/gt/intel_sseu.c
738
val <<= GEN8_RPCS_SS_CNT_SHIFT;
sys/dev/pci/drm/i915/gt/intel_sseu.c
740
GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
sys/dev/pci/drm/i915/gt/intel_sseu.c
741
val &= GEN8_RPCS_SS_CNT_MASK;
sys/dev/pci/drm/i915/gt/intel_sseu.c
743
rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
sys/dev/pci/drm/i915/gt/intel_sseu.c
747
u32 val;
sys/dev/pci/drm/i915/gt/intel_sseu.c
749
val = req_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
sys/dev/pci/drm/i915/gt/intel_sseu.c
750
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
sys/dev/pci/drm/i915/gt/intel_sseu.c
751
val &= GEN8_RPCS_EU_MIN_MASK;
sys/dev/pci/drm/i915/gt/intel_sseu.c
753
rpcs |= val;
sys/dev/pci/drm/i915/gt/intel_sseu.c
755
val = req_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
sys/dev/pci/drm/i915/gt/intel_sseu.c
756
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
sys/dev/pci/drm/i915/gt/intel_sseu.c
757
val &= GEN8_RPCS_EU_MAX_MASK;
sys/dev/pci/drm/i915/gt/intel_sseu.c
759
rpcs |= val;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1025
u32 val;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1029
val = wa->set;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1031
val = wa->is_mcr ?
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1034
val &= ~wa->clr;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1035
val |= wa->set;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1039
*cs++ = val;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1776
u32 val, old = 0;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1783
val = (old & ~wa->clr) | wa->set;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1784
if (val != old || !wa->clr) {
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1786
intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1788
intel_uncore_write_fw(uncore, wa->reg, val);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1792
u32 val = wa->is_mcr ?
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1796
wa_verify(gt, wa, val, wal->name, "application");
sys/dev/pci/drm/i915/gt/intel_workarounds.c
299
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
301
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
305
wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
307
wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
311
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
313
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
317
wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
319
wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
324
u32 mask, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
326
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
331
u32 mask, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
333
wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
sys/dev/pci/drm/i915/gt/selftest_llc.c
28
u32 val;
sys/dev/pci/drm/i915/gt/selftest_llc.c
32
val = gpu_freq;
sys/dev/pci/drm/i915/gt/selftest_llc.c
34
&val, NULL)) {
sys/dev/pci/drm/i915/gt/selftest_llc.c
41
found = (val >> 0) & 0xff;
sys/dev/pci/drm/i915/gt/selftest_llc.c
51
found = (val >> 8) & 0xff;
sys/dev/pci/drm/i915/gt/selftest_migrate.c
267
u32 *vaddr, val = 0;
sys/dev/pci/drm/i915/gt/selftest_migrate.c
299
if (ccs_cap && !val) {
sys/dev/pci/drm/i915/gt/selftest_migrate.c
318
err = fn(migrate, &ww, obj, val, &rq);
sys/dev/pci/drm/i915/gt/selftest_migrate.c
337
if (vaddr[x] != val) {
sys/dev/pci/drm/i915/gt/selftest_migrate.c
339
fn, vaddr[x], val, x * sizeof(u32));
sys/dev/pci/drm/i915/gt/selftest_migrate.c
347
if (ccs_cap && !val) {
sys/dev/pci/drm/i915/gt/selftest_tlb.c
23
static void vma_set_qw(struct i915_vma *vma, u64 addr, u64 val)
sys/dev/pci/drm/i915/gt/selftest_tlb.c
26
GEM_BUG_ON(addr >= i915_vma_offset(vma) + i915_vma_size(vma) + sizeof(val));
sys/dev/pci/drm/i915/gt/selftest_tlb.c
28
(addr - i915_vma_offset(vma)), val, 1);
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
104
static int guc_sched_disable_gucid_threshold_get(void *data, u64 *val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
111
*val = guc->submission_state.sched_disable_gucid_threshold;
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
115
static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
122
if (val > intel_guc_sched_disable_gucid_threshold_max(guc))
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
126
guc->submission_state.sched_disable_gucid_threshold = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
76
static int guc_sched_disable_delay_ms_get(void *data, u64 *val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
83
*val = (u64)guc->submission_state.sched_disable_delay_ms;
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
88
static int guc_sched_disable_delay_ms_set(void *data, u64 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
96
guc->submission_state.sched_disable_delay_ms = min_t(u64, val, 60000);
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
109
u32 val = intel_uncore_read(uncore, GUC_STATUS);
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
110
u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
111
u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
113
*status = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
103
return intel_guc_log_set_level(log, val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
129
int val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
132
ret = kstrtoint_from_user(ubuf, cnt, 0, &val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
140
if (val == 1)
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
84
static int guc_log_level_get(void *data, u64 *val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
91
*val = intel_guc_log_get_level(log);
sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c
96
static int guc_log_level_set(void *data, u64 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
428
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
434
if (val < slpc->min_freq ||
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
435
val > slpc->rp0_freq ||
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
436
val < slpc->min_freq_softlimit)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
442
val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
450
slpc->max_freq_softlimit = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
465
int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
476
*val = slpc_decode_max_freq(slpc);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
482
int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
493
val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
496
val, ERR_PTR(ret));
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
498
slpc->ignore_eff_freq = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
501
if (val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
522
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
528
if (val < slpc->min_freq ||
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
529
val > slpc->rp0_freq ||
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
530
val > slpc->max_freq_softlimit)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
539
val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
542
slpc->min_freq_softlimit = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
564
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
575
*val = slpc_decode_min_freq(slpc);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
581
int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
590
val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
595
int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
607
val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
611
int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
617
if (val > SLPC_POWER_PROFILES_POWER_SAVING)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
625
val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
629
val, ERR_PTR(ret));
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
631
slpc->power_profile = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
810
int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
814
if (val < slpc->min_freq || val > slpc->rp0_freq)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
819
if (slpc->boost_freq != val) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
822
ret = slpc_force_min_freq(slpc, val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
829
slpc->boost_freq = val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
37
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
38
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
39
int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
40
int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
41
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
43
int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
47
int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
48
int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
49
int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4770
u32 val;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4776
val = GUC_SEM_INTR_ROUTE_TO_GUC | GUC_SEM_INTR_ENABLE_ALL;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4778
val = 0;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4780
intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, val);
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
190
u32 val;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
194
val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
195
guc->mmio_msg |= val & guc->msg_enabled_mask;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1189
u32 hws_pga, val;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1219
val = cmd_val(s, 1) & (~(1 << 21));
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1220
patch_value(s, cmd_ptr(s, 1), val);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1720
u32 hws_pga, val;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1747
val = cmd_val(s, 0) & (~(1 << 21));
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1748
patch_value(s, cmd_ptr(s, 0), val);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
843
#define patch_value(s, addr, val) do { \
sys/dev/pci/drm/i915/gvt/cmd_parser.c
844
*addr = val; \
sys/dev/pci/drm/i915/gvt/debugfs.c
128
vgpu_scan_nonprivbb_get(void *data, u64 *val)
sys/dev/pci/drm/i915/gvt/debugfs.c
132
*val = vgpu->scan_nonprivbb;
sys/dev/pci/drm/i915/gvt/debugfs.c
143
vgpu_scan_nonprivbb_set(void *data, u64 val)
sys/dev/pci/drm/i915/gvt/debugfs.c
147
vgpu->scan_nonprivbb = val;
sys/dev/pci/drm/i915/gvt/debugfs.c
155
static int vgpu_status_get(void *data, u64 *val)
sys/dev/pci/drm/i915/gvt/debugfs.c
159
*val = 0;
sys/dev/pci/drm/i915/gvt/debugfs.c
162
*val |= (1 << INTEL_VGPU_STATUS_ATTACHED);
sys/dev/pci/drm/i915/gvt/debugfs.c
164
*val |= (1 << INTEL_VGPU_STATUS_ACTIVE);
sys/dev/pci/drm/i915/gvt/edid.c
549
unsigned char val = edid_get_byte(vgpu);
sys/dev/pci/drm/i915/gvt/edid.c
551
aux_data_for_write = (val << 16);
sys/dev/pci/drm/i915/gvt/execlist.h
125
u32 val;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
217
u32 val, fmt;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
224
val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
225
plane->enabled = !!(val & DISP_ENABLE);
sys/dev/pci/drm/i915/gvt/fb_decoder.c
230
plane->tiled = val & PLANE_CTL_TILED_MASK;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
232
val & PLANE_CTL_FORMAT_MASK_SKL,
sys/dev/pci/drm/i915/gvt/fb_decoder.c
233
val & PLANE_CTL_ORDER_RGBX,
sys/dev/pci/drm/i915/gvt/fb_decoder.c
234
val & PLANE_CTL_ALPHA_MASK,
sys/dev/pci/drm/i915/gvt/fb_decoder.c
235
val & PLANE_CTL_YUV422_ORDER_MASK);
sys/dev/pci/drm/i915/gvt/fb_decoder.c
245
plane->tiled = val & DISP_TILED;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
246
fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
sys/dev/pci/drm/i915/gvt/fb_decoder.c
281
val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
282
plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
sys/dev/pci/drm/i915/gvt/fb_decoder.c
284
plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
sys/dev/pci/drm/i915/gvt/fb_decoder.c
348
u32 val, mode, index;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
356
val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
357
mode = val & MCURSOR_MODE_MASK;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
374
alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
sys/dev/pci/drm/i915/gvt/fb_decoder.c
376
alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
sys/dev/pci/drm/i915/gvt/fb_decoder.c
393
val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
394
plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
395
plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
396
plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
397
plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
sys/dev/pci/drm/i915/gvt/gvt.h
473
u32 offset, u32 val, bool low)
sys/dev/pci/drm/i915/gvt/gvt.h
486
*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
sys/dev/pci/drm/i915/gvt/gvt.h
488
*pval = val;
sys/dev/pci/drm/i915/gvt/handlers.c
1582
u32 val = *(u32 *)p_data;
sys/dev/pci/drm/i915/gvt/handlers.c
1586
offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
sys/dev/pci/drm/i915/gvt/interrupt.c
351
u32 val = vgpu_vreg(vgpu,
sys/dev/pci/drm/i915/gvt/interrupt.c
371
if (val & map->down_irq_bitmask)
sys/dev/pci/drm/i915/gvt/kvmgt.c
109
static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,
sys/dev/pci/drm/i915/gvt/kvmgt.c
1589
static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,
sys/dev/pci/drm/i915/gvt/kvmgt.c
1599
(void *)val, len);
sys/dev/pci/drm/i915/gvt/kvmgt.c
878
u64 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
880
ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val),
sys/dev/pci/drm/i915/gvt/kvmgt.c
885
if (copy_to_user(buf, &val, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
890
u32 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
892
ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val),
sys/dev/pci/drm/i915/gvt/kvmgt.c
897
if (copy_to_user(buf, &val, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
902
u16 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
904
ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val),
sys/dev/pci/drm/i915/gvt/kvmgt.c
909
if (copy_to_user(buf, &val, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
914
u8 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
916
ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos,
sys/dev/pci/drm/i915/gvt/kvmgt.c
921
if (copy_to_user(buf, &val, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
953
u64 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
955
if (copy_from_user(&val, buf, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
958
ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val),
sys/dev/pci/drm/i915/gvt/kvmgt.c
965
u32 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
967
if (copy_from_user(&val, buf, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
970
ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val),
sys/dev/pci/drm/i915/gvt/kvmgt.c
977
u16 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
979
if (copy_from_user(&val, buf, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
982
ret = intel_vgpu_rw(vgpu, (char *)&val,
sys/dev/pci/drm/i915/gvt/kvmgt.c
983
sizeof(val), ppos, true);
sys/dev/pci/drm/i915/gvt/kvmgt.c
989
u8 val;
sys/dev/pci/drm/i915/gvt/kvmgt.c
991
if (copy_from_user(&val, buf, sizeof(val)))
sys/dev/pci/drm/i915/gvt/kvmgt.c
994
ret = intel_vgpu_rw(vgpu, &val, sizeof(val),
sys/dev/pci/drm/i915/gvt/reg.h
90
#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
sys/dev/pci/drm/i915/gvt/reg.h
91
((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
sys/dev/pci/drm/i915/gvt/scheduler.c
1018
RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1033
RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
sys/dev/pci/drm/i915/gvt/scheduler.c
154
+ RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
sys/dev/pci/drm/i915/gvt/scheduler.c
157
+ RING_CTX_OFF(name.val),\
sys/dev/pci/drm/i915/gvt/scheduler.c
1574
gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
sys/dev/pci/drm/i915/gvt/scheduler.c
158
&shadow_ring_context->name.val, 4);\
sys/dev/pci/drm/i915/gvt/scheduler.c
159
shadow_ring_context->name.val |= 0xffff << 16;\
sys/dev/pci/drm/i915/gvt/scheduler.c
1649
RING_CTX_OFF(ring_header.val), &head, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1652
RING_CTX_OFF(ring_tail.val), &tail, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1679
RING_CTX_OFF(rb_start.val), &start, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1681
RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1683
RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1706
RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
1708
RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
sys/dev/pci/drm/i915/gvt/scheduler.c
211
if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val) || skip)
sys/dev/pci/drm/i915/gvt/scheduler.c
599
shadow_ring_context->bb_per_ctx_ptr.val =
sys/dev/pci/drm/i915/gvt/scheduler.c
60
ring_context->pdps[i].val = pdp[7 - i];
sys/dev/pci/drm/i915/gvt/scheduler.c
600
(shadow_ring_context->bb_per_ctx_ptr.val &
sys/dev/pci/drm/i915/gvt/scheduler.c
602
shadow_ring_context->rcs_indirect_ctx.val =
sys/dev/pci/drm/i915/gvt/scheduler.c
603
(shadow_ring_context->rcs_indirect_ctx.val &
sys/dev/pci/drm/i915/gvt/scheduler.c
913
gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
sys/dev/pci/drm/i915/gvt/scheduler.c
923
u64 shadow_pdp = c->pdps[7].val | (u64) c->pdps[6].val << 32;
sys/dev/pci/drm/i915/i915_debugfs.c
491
static int i915_wedged_get(void *data, u64 *val)
sys/dev/pci/drm/i915/i915_debugfs.c
497
*val = 0;
sys/dev/pci/drm/i915/i915_debugfs.c
502
ret = intel_gt_debugfs_reset_show(gt, val);
sys/dev/pci/drm/i915/i915_debugfs.c
507
if (*val)
sys/dev/pci/drm/i915/i915_debugfs.c
514
static int i915_wedged_set(void *data, u64 val)
sys/dev/pci/drm/i915/i915_debugfs.c
521
intel_gt_debugfs_reset_store(gt, val);
sys/dev/pci/drm/i915/i915_debugfs.c
531
i915_perf_noa_delay_set(void *data, u64 val)
sys/dev/pci/drm/i915/i915_debugfs.c
539
if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)
sys/dev/pci/drm/i915/i915_debugfs.c
542
atomic64_set(&i915->perf.noa_programming_delay, val);
sys/dev/pci/drm/i915/i915_debugfs.c
547
i915_perf_noa_delay_get(void *data, u64 *val)
sys/dev/pci/drm/i915/i915_debugfs.c
551
*val = atomic64_read(&i915->perf.noa_programming_delay);
sys/dev/pci/drm/i915/i915_debugfs.c
581
i915_drop_caches_get(void *data, u64 *val)
sys/dev/pci/drm/i915/i915_debugfs.c
583
*val = DROP_ALL;
sys/dev/pci/drm/i915/i915_debugfs.c
589
gt_drop_caches(struct intel_gt *gt, u64 val)
sys/dev/pci/drm/i915/i915_debugfs.c
593
if (val & DROP_RESET_ACTIVE &&
sys/dev/pci/drm/i915/i915_debugfs.c
597
if (val & DROP_RETIRE)
sys/dev/pci/drm/i915/i915_debugfs.c
600
if (val & (DROP_IDLE | DROP_ACTIVE)) {
sys/dev/pci/drm/i915/i915_debugfs.c
606
if (val & DROP_IDLE) {
sys/dev/pci/drm/i915/i915_debugfs.c
612
if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
sys/dev/pci/drm/i915/i915_debugfs.c
615
if (val & DROP_FREED)
sys/dev/pci/drm/i915/i915_debugfs.c
622
i915_drop_caches_set(void *data, u64 val)
sys/dev/pci/drm/i915/i915_debugfs.c
631
val, val & DROP_ALL);
sys/dev/pci/drm/i915/i915_debugfs.c
634
ret = gt_drop_caches(gt, val);
sys/dev/pci/drm/i915/i915_debugfs.c
641
if (val & DROP_BOUND)
sys/dev/pci/drm/i915/i915_debugfs.c
644
if (val & DROP_UNBOUND)
sys/dev/pci/drm/i915/i915_debugfs.c
647
if (val & DROP_SHRINK_ALL)
sys/dev/pci/drm/i915/i915_debugfs.c
652
if (val & DROP_RCU)
sys/dev/pci/drm/i915/i915_debugfs.c
655
if (val & DROP_FREED)
sys/dev/pci/drm/i915/i915_hwmon.c
206
unsigned long val;
sys/dev/pci/drm/i915/i915_hwmon.c
209
ret = kstrtoul(buf, 0, &val);
sys/dev/pci/drm/i915/i915_hwmon.c
229
if (val > max_win)
sys/dev/pci/drm/i915/i915_hwmon.c
233
val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
sys/dev/pci/drm/i915/i915_hwmon.c
235
if (!val) {
sys/dev/pci/drm/i915/i915_hwmon.c
240
y = ilog2(val);
sys/dev/pci/drm/i915/i915_hwmon.c
242
x = (val - (1ul << y)) << x_w >> y;
sys/dev/pci/drm/i915/i915_hwmon.c
328
hwm_temp_read(struct hwm_drvdata *ddat, u32 attr, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
340
*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
sys/dev/pci/drm/i915/i915_hwmon.c
361
hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
372
*val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10);
sys/dev/pci/drm/i915/i915_hwmon.c
408
hwm_power_max_read(struct hwm_drvdata *ddat, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
418
*val = PL1_DISABLE;
sys/dev/pci/drm/i915/i915_hwmon.c
422
*val = hwm_field_read_and_scale(ddat,
sys/dev/pci/drm/i915/i915_hwmon.c
436
*val = clamp_t(u64, *val, min, max);
sys/dev/pci/drm/i915/i915_hwmon.c
442
hwm_power_max_write(struct hwm_drvdata *ddat, long val)
sys/dev/pci/drm/i915/i915_hwmon.c
475
if (val == PL1_DISABLE) {
sys/dev/pci/drm/i915/i915_hwmon.c
486
nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);
sys/dev/pci/drm/i915/i915_hwmon.c
498
hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
506
return hwm_power_max_read(ddat, val);
sys/dev/pci/drm/i915/i915_hwmon.c
508
*val = hwm_field_read_and_scale(ddat,
sys/dev/pci/drm/i915/i915_hwmon.c
520
*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
sys/dev/pci/drm/i915/i915_hwmon.c
529
hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val)
sys/dev/pci/drm/i915/i915_hwmon.c
535
return hwm_power_max_write(ddat, val);
sys/dev/pci/drm/i915/i915_hwmon.c
537
uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
sys/dev/pci/drm/i915/i915_hwmon.c
598
hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
602
hwm_energy(ddat, val);
sys/dev/pci/drm/i915/i915_hwmon.c
625
hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
637
*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
sys/dev/pci/drm/i915/i915_hwmon.c
646
hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val)
sys/dev/pci/drm/i915/i915_hwmon.c
652
uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
sys/dev/pci/drm/i915/i915_hwmon.c
671
hwm_fan_input_read(struct hwm_drvdata *ddat, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
703
*val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time);
sys/dev/pci/drm/i915/i915_hwmon.c
714
hwm_fan_read(struct hwm_drvdata *ddat, u32 attr, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
717
return hwm_fan_input_read(ddat, val);
sys/dev/pci/drm/i915/i915_hwmon.c
748
int channel, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
754
return hwm_temp_read(ddat, attr, val);
sys/dev/pci/drm/i915/i915_hwmon.c
756
return hwm_in_read(ddat, attr, val);
sys/dev/pci/drm/i915/i915_hwmon.c
758
return hwm_power_read(ddat, attr, channel, val);
sys/dev/pci/drm/i915/i915_hwmon.c
760
return hwm_energy_read(ddat, attr, val);
sys/dev/pci/drm/i915/i915_hwmon.c
762
return hwm_curr_read(ddat, attr, val);
sys/dev/pci/drm/i915/i915_hwmon.c
764
return hwm_fan_read(ddat, attr, val);
sys/dev/pci/drm/i915/i915_hwmon.c
772
int channel, long val)
sys/dev/pci/drm/i915/i915_hwmon.c
778
return hwm_power_write(ddat, attr, channel, val);
sys/dev/pci/drm/i915/i915_hwmon.c
780
return hwm_curr_write(ddat, attr, val);
sys/dev/pci/drm/i915/i915_hwmon.c
813
int channel, long *val)
sys/dev/pci/drm/i915/i915_hwmon.c
819
return hwm_energy_read(ddat, attr, val);
sys/dev/pci/drm/i915/i915_ioctl.c
75
reg->val = intel_uncore_read64_2x32(uncore,
sys/dev/pci/drm/i915/i915_ioctl.c
79
reg->val = intel_uncore_read64(uncore,
sys/dev/pci/drm/i915/i915_ioctl.c
82
reg->val = intel_uncore_read(uncore, entry->offset_ldw);
sys/dev/pci/drm/i915/i915_ioctl.c
84
reg->val = intel_uncore_read16(uncore,
sys/dev/pci/drm/i915/i915_ioctl.c
87
reg->val = intel_uncore_read8(uncore,
sys/dev/pci/drm/i915/i915_irq.c
100
u32 val = intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/i915_irq.c
102
if (val == 0)
sys/dev/pci/drm/i915/i915_irq.c
107
i915_mmio_reg_offset(reg), val);
sys/dev/pci/drm/i915/i915_irq.c
591
u32 val;
sys/dev/pci/drm/i915/i915_irq.c
597
val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
sys/dev/pci/drm/i915/i915_irq.c
598
if (unlikely(!val))
sys/dev/pci/drm/i915/i915_irq.c
601
raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
sys/dev/pci/drm/i915/i915_irq.c
603
return val;
sys/dev/pci/drm/i915/i915_mitigations.c
32
static int mitigations_set(const char *val, const struct kernel_param *kp)
sys/dev/pci/drm/i915/i915_mitigations.c
41
str = kstrdup(val, GFP_KERNEL);
sys/dev/pci/drm/i915/i915_mitigations.c
87
DRIVER_NAME, val, tok);
sys/dev/pci/drm/i915/i915_params.c
139
bool val)
sys/dev/pci/drm/i915/i915_params.c
141
drm_printf(p, "i915.%s=%s\n", name, str_yes_no(val));
sys/dev/pci/drm/i915/i915_params.c
145
int val)
sys/dev/pci/drm/i915/i915_params.c
147
drm_printf(p, "i915.%s=%d\n", name, val);
sys/dev/pci/drm/i915/i915_params.c
151
unsigned int val)
sys/dev/pci/drm/i915/i915_params.c
153
drm_printf(p, "i915.%s=%u\n", name, val);
sys/dev/pci/drm/i915/i915_params.c
157
unsigned long val)
sys/dev/pci/drm/i915/i915_params.c
159
drm_printf(p, "i915.%s=%lu\n", name, val);
sys/dev/pci/drm/i915/i915_params.c
163
const char *val)
sys/dev/pci/drm/i915/i915_params.c
165
drm_printf(p, "i915.%s=%s\n", name, val);
sys/dev/pci/drm/i915/i915_params.c
168
#define _param_print(p, name, val) \
sys/dev/pci/drm/i915/i915_params.c
169
_Generic(val, \
sys/dev/pci/drm/i915/i915_params.c
174
char *: _param_print_charp)(p, name, val)
sys/dev/pci/drm/i915/i915_pci.c
909
u16 val;
sys/dev/pci/drm/i915/i915_pci.c
917
if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
sys/dev/pci/drm/i915/i915_perf.c
1384
u32 *val;
sys/dev/pci/drm/i915/i915_perf.c
1400
val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
sys/dev/pci/drm/i915/i915_perf.c
1401
if (IS_ERR(val)) {
sys/dev/pci/drm/i915/i915_perf.c
1402
err = PTR_ERR(val);
sys/dev/pci/drm/i915/i915_perf.c
1406
*ctx_id = *val;
sys/dev/pci/drm/i915/i915_perf.c
3051
u32 val;
sys/dev/pci/drm/i915/i915_perf.c
3063
val = (stream->oa_buffer.format->format << regs->oa_ctrl_counter_format_shift) |
sys/dev/pci/drm/i915/i915_perf.c
3066
intel_uncore_write(stream->uncore, regs->oa_ctrl, val);
sys/dev/pci/drm/i915/i915_perf.c
4526
static u32 mask_reg_value(u32 reg, u32 val)
sys/dev/pci/drm/i915/i915_perf.c
4534
val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
sys/dev/pci/drm/i915/i915_perf.c
4542
val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
sys/dev/pci/drm/i915/i915_perf.c
4544
return val;
sys/dev/pci/drm/i915/i915_pmu.c
100
val;
sys/dev/pci/drm/i915/i915_pmu.c
183
u64 val;
sys/dev/pci/drm/i915/i915_pmu.c
185
val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
sys/dev/pci/drm/i915/i915_pmu.c
188
val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
sys/dev/pci/drm/i915/i915_pmu.c
191
val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
sys/dev/pci/drm/i915/i915_pmu.c
193
return val;
sys/dev/pci/drm/i915/i915_pmu.c
207
store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
sys/dev/pci/drm/i915/i915_pmu.c
209
pmu->sample[gt_id][sample].cur = val;
sys/dev/pci/drm/i915/i915_pmu.c
213
add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul)
sys/dev/pci/drm/i915/i915_pmu.c
215
pmu->sample[gt_id][sample].cur += mul_u32_u32(val, mul);
sys/dev/pci/drm/i915/i915_pmu.c
225
u64 val;
sys/dev/pci/drm/i915/i915_pmu.c
229
val = __get_rc6(gt);
sys/dev/pci/drm/i915/i915_pmu.c
236
store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
sys/dev/pci/drm/i915/i915_pmu.c
245
val = ktime_since_raw(pmu->sleep_last[gt_id]);
sys/dev/pci/drm/i915/i915_pmu.c
246
val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
sys/dev/pci/drm/i915/i915_pmu.c
249
if (val < read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED))
sys/dev/pci/drm/i915/i915_pmu.c
250
val = read_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED);
sys/dev/pci/drm/i915/i915_pmu.c
252
store_sample(pmu, gt_id, __I915_SAMPLE_RC6_LAST_REPORTED, val);
sys/dev/pci/drm/i915/i915_pmu.c
256
return val;
sys/dev/pci/drm/i915/i915_pmu.c
269
u64 val = __get_rc6(gt);
sys/dev/pci/drm/i915/i915_pmu.c
271
store_sample(pmu, i, __I915_SAMPLE_RC6, val);
sys/dev/pci/drm/i915/i915_pmu.c
273
val);
sys/dev/pci/drm/i915/i915_pmu.c
341
add_sample(struct i915_pmu_sample *sample, u32 val)
sys/dev/pci/drm/i915/i915_pmu.c
343
sample->cur += val;
sys/dev/pci/drm/i915/i915_pmu.c
360
u32 val;
sys/dev/pci/drm/i915/i915_pmu.c
362
val = ENGINE_READ_FW(engine, RING_CTL);
sys/dev/pci/drm/i915/i915_pmu.c
363
if (val == 0) /* powerwell off => engine idle */
sys/dev/pci/drm/i915/i915_pmu.c
366
if (val & RING_WAIT)
sys/dev/pci/drm/i915/i915_pmu.c
368
if (val & RING_WAIT_SEMAPHORE)
sys/dev/pci/drm/i915/i915_pmu.c
382
busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
sys/dev/pci/drm/i915/i915_pmu.c
384
val = ENGINE_READ_FW(engine, RING_MI_MODE);
sys/dev/pci/drm/i915/i915_pmu.c
385
busy = !(val & MODE_IDLE);
sys/dev/pci/drm/i915/i915_pmu.c
475
u32 val;
sys/dev/pci/drm/i915/i915_pmu.c
486
val = intel_rps_read_actual_frequency_fw(rps);
sys/dev/pci/drm/i915/i915_pmu.c
487
if (!val)
sys/dev/pci/drm/i915/i915_pmu.c
488
val = intel_gpu_freq(rps, rps->cur_freq);
sys/dev/pci/drm/i915/i915_pmu.c
491
val, period_ns / 1000);
sys/dev/pci/drm/i915/i915_pmu.c
661
u64 val = 0;
sys/dev/pci/drm/i915/i915_pmu.c
677
val = ktime_to_ns(intel_engine_get_busy_time(engine,
sys/dev/pci/drm/i915/i915_pmu.c
680
val = engine->pmu.sample[sample].cur;
sys/dev/pci/drm/i915/i915_pmu.c
688
val =
sys/dev/pci/drm/i915/i915_pmu.c
694
val =
sys/dev/pci/drm/i915/i915_pmu.c
700
val = READ_ONCE(pmu->irq_count);
sys/dev/pci/drm/i915/i915_pmu.c
703
val = get_rc6(i915->gt[gt_id]);
sys/dev/pci/drm/i915/i915_pmu.c
706
val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
sys/dev/pci/drm/i915/i915_pmu.c
711
return val;
sys/dev/pci/drm/i915/i915_pmu.c
78
unsigned int val;
sys/dev/pci/drm/i915/i915_pmu.c
82
val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
sys/dev/pci/drm/i915/i915_pmu.c
85
val = __I915_PMU_REQUESTED_FREQUENCY_ENABLED;
sys/dev/pci/drm/i915/i915_pmu.c
88
val = __I915_PMU_RC6_RESIDENCY_ENABLED;
sys/dev/pci/drm/i915/i915_pmu.c
919
unsigned long val;
sys/dev/pci/drm/i915/i915_pmu.c
928
return sprintf(buf, "config=0x%lx\n", eattr->val);
sys/dev/pci/drm/i915/i915_pmu.c
960
attr->val = config;
sys/dev/pci/drm/i915/i915_request.c
239
static void __i915_request_fill(struct i915_request *rq, u8 val)
sys/dev/pci/drm/i915/i915_request.c
246
memset(vaddr + head, val, rq->ring->size - head);
sys/dev/pci/drm/i915/i915_request.c
249
memset(vaddr + head, val, rq->postfix - head);
sys/dev/pci/drm/i915/intel_clock_gating.c
208
u32 val;
sys/dev/pci/drm/i915/intel_clock_gating.c
223
val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
sys/dev/pci/drm/i915/intel_clock_gating.c
224
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
sys/dev/pci/drm/i915/intel_clock_gating.c
225
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
sys/dev/pci/drm/i915/intel_clock_gating.c
227
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
sys/dev/pci/drm/i915/intel_clock_gating.c
228
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
sys/dev/pci/drm/i915/intel_clock_gating.c
229
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
sys/dev/pci/drm/i915/intel_clock_gating.c
230
intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
sys/dev/pci/drm/i915/intel_clock_gating.c
331
u32 val;
sys/dev/pci/drm/i915/intel_clock_gating.c
337
val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
sys/dev/pci/drm/i915/intel_clock_gating.c
338
val &= ~L3_PRIO_CREDITS_MASK;
sys/dev/pci/drm/i915/intel_clock_gating.c
339
val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
sys/dev/pci/drm/i915/intel_clock_gating.c
340
val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
sys/dev/pci/drm/i915/intel_clock_gating.c
341
intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val);
sys/dev/pci/drm/i915/intel_device_info.c
303
u32 val;
sys/dev/pci/drm/i915/intel_device_info.c
312
val = ioread32(addr);
sys/dev/pci/drm/i915/intel_device_info.c
315
val = bus_space_read_4(i915->vga_regs->bst, i915->vga_regs->bsh,
sys/dev/pci/drm/i915/intel_device_info.c
319
ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
sys/dev/pci/drm/i915/intel_device_info.c
320
ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
sys/dev/pci/drm/i915/intel_device_info.c
321
ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
sys/dev/pci/drm/i915/intel_device_info.c
327
ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
sys/dev/pci/drm/i915/intel_memory_region.c
68
const u8 val[] = { 0x0, 0xa5, 0xc3, 0xf0 };
sys/dev/pci/drm/i915/intel_memory_region.c
81
for (i = 0; i < ARRAY_SIZE(val); i++) {
sys/dev/pci/drm/i915/intel_memory_region.c
82
err = __iopagetest(mem, va, PAGE_SIZE, val[i], offset, caller);
sys/dev/pci/drm/i915/intel_memory_region.c
86
err = __iopagetest(mem, va, PAGE_SIZE, ~val[i], offset, caller);
sys/dev/pci/drm/i915/intel_pcode.c
101
err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
sys/dev/pci/drm/i915/intel_pcode.c
113
int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
sys/dev/pci/drm/i915/intel_pcode.c
119
err = __snb_pcode_rw(uncore, mbox, &val, NULL, 250, timeout_ms, false);
sys/dev/pci/drm/i915/intel_pcode.c
125
val, mbox, __builtin_return_address(0), err);
sys/dev/pci/drm/i915/intel_pcode.c
245
int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
sys/dev/pci/drm/i915/intel_pcode.c
256
err = snb_pcode_read(uncore, mbox, val, NULL);
sys/dev/pci/drm/i915/intel_pcode.c
261
int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
sys/dev/pci/drm/i915/intel_pcode.c
272
err = snb_pcode_write(uncore, mbox, val);
sys/dev/pci/drm/i915/intel_pcode.c
278
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
sys/dev/pci/drm/i915/intel_pcode.c
282
return snb_pcode_read(&i915->uncore, mbox, val, val1);
sys/dev/pci/drm/i915/intel_pcode.c
285
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
sys/dev/pci/drm/i915/intel_pcode.c
289
return snb_pcode_write_timeout(&i915->uncore, mbox, val, timeout_ms);
sys/dev/pci/drm/i915/intel_pcode.c
57
u32 *val, u32 *val1,
sys/dev/pci/drm/i915/intel_pcode.c
72
intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
sys/dev/pci/drm/i915/intel_pcode.c
86
*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
sys/dev/pci/drm/i915/intel_pcode.c
96
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
sys/dev/pci/drm/i915/intel_pcode.h
14
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
sys/dev/pci/drm/i915/intel_pcode.h
15
int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms);
sys/dev/pci/drm/i915/intel_pcode.h
16
#define snb_pcode_write(uncore, mbox, val) \
sys/dev/pci/drm/i915/intel_pcode.h
17
snb_pcode_write_timeout((uncore), (mbox), (val), 1)
sys/dev/pci/drm/i915/intel_pcode.h
27
int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
sys/dev/pci/drm/i915/intel_pcode.h
28
int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
sys/dev/pci/drm/i915/intel_pcode.h
31
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
sys/dev/pci/drm/i915/intel_pcode.h
32
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
sys/dev/pci/drm/i915/intel_pcode.h
33
#define intel_pcode_write(drm, mbox, val) \
sys/dev/pci/drm/i915/intel_pcode.h
34
intel_pcode_write_timeout((drm), (mbox), (val), 1)
sys/dev/pci/drm/i915/intel_uncore.c
133
#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
sys/dev/pci/drm/i915/intel_uncore.c
134
#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
sys/dev/pci/drm/i915/intel_uncore.c
1851
u##x val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1852
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1853
return val; \
sys/dev/pci/drm/i915/intel_uncore.c
1861
u##x val = 0; \
sys/dev/pci/drm/i915/intel_uncore.c
1865
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1866
return val
sys/dev/pci/drm/i915/intel_uncore.c
1872
val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1881
val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1904
u##x val = 0; \
sys/dev/pci/drm/i915/intel_uncore.c
1913
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1914
return val
sys/dev/pci/drm/i915/intel_uncore.c
1952
val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1971
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1978
gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1980
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
1986
gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1989
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2010
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
2022
gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2026
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2035
fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2041
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2061
vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2062
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
2063
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
376
u32 val;
sys/dev/pci/drm/i915/intel_uncore.c
378
val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
sys/dev/pci/drm/i915/intel_uncore.c
379
val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
sys/dev/pci/drm/i915/intel_uncore.c
381
return val;
sys/dev/pci/drm/i915/intel_uncore.h
112
i915_reg_t r, u8 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
114
i915_reg_t r, u16 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
116
i915_reg_t r, u32 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
338
i915_reg_t reg, u##x__ val) \
sys/dev/pci/drm/i915/intel_uncore.h
343
write##s__(val, uncore->regs + offset); \
sys/dev/pci/drm/i915/intel_uncore.h
367
i915_reg_t reg, u##x__ val) \
sys/dev/pci/drm/i915/intel_uncore.h
369
uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
sys/dev/pci/drm/i915/intel_uncore.h
439
u32 old, val;
sys/dev/pci/drm/i915/intel_uncore.h
442
val = (old & ~clear) | set;
sys/dev/pci/drm/i915/intel_uncore.h
443
intel_uncore_write(uncore, reg, val);
sys/dev/pci/drm/i915/intel_uncore.h
450
u32 old, val;
sys/dev/pci/drm/i915/intel_uncore.h
453
val = (old & ~clear) | set;
sys/dev/pci/drm/i915/intel_uncore.h
454
if (val != old)
sys/dev/pci/drm/i915/intel_uncore.h
455
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/intel_uncore.h
489
i915_reg_t reg, u32 val,
sys/dev/pci/drm/i915/intel_uncore.h
494
intel_uncore_write(uncore, reg, val);
sys/dev/pci/drm/i915/pxp/intel_pxp.c
67
u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :
sys/dev/pci/drm/i915/pxp/intel_pxp.c
70
intel_uncore_write(pxp->ctrl_gt->uncore, KCR_INIT(pxp->kcr_base), val);
sys/dev/pci/drm/i915/pxp/intel_pxp_debugfs.c
39
static int pxp_terminate_get(void *data, u64 *val)
sys/dev/pci/drm/i915/pxp/intel_pxp_debugfs.c
45
static int pxp_terminate_set(void *data, u64 val)
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1411
u32 val;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1414
val = ioread32(vaddr + n);
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1417
if (val != n) {
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1419
val, n);
sys/dev/pci/drm/i915/selftests/i915_vma.c
1041
u32 val = y << 16 | x;
sys/dev/pci/drm/i915/selftests/i915_vma.c
1048
iowrite32(val, &map[offset / sizeof(*map)]);
sys/dev/pci/drm/i915/selftests/i915_vma.c
1073
u32 val;
sys/dev/pci/drm/i915/selftests/i915_vma.c
1081
val = ioread32(&map[offset / sizeof(*map)]);
sys/dev/pci/drm/i915/selftests/i915_vma.c
1082
if (val != exp) {
sys/dev/pci/drm/i915/selftests/i915_vma.c
1085
exp, val);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1099
u32 val;
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1112
val = prandom_u32_state(&prng);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1113
memset32(vaddr + offset / sizeof(u32), val ^ 0xdeadbeaf,
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1124
if (vaddr[dword] != (val ^ 0xdeadbeaf)) {
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1126
__func__, dword, vaddr[dword], val ^ 0xdeadbeaf,
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
675
static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
691
if (*ptr != val) {
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
693
dword, *ptr, val);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
882
u32 dword, val;
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
924
val = prandom_u32_state(&prng);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
926
memset32(vaddr, val, obj->base.size / sizeof(u32));
sys/dev/pci/drm/i915/selftests/intel_uncore.c
214
u32 val;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
235
val = readl(reg);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
254
if (!val) {
sys/dev/pci/drm/i915/selftests/mock_uncore.c
29
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
sys/dev/pci/drm/i915/soc/intel_dram.c
106
u32 val;
sys/dev/pci/drm/i915/soc/intel_dram.c
109
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG);
sys/dev/pci/drm/i915/soc/intel_dram.c
112
switch ((val >> 2) & 0x7) {
sys/dev/pci/drm/i915/soc/intel_dram.c
122
u32 val;
sys/dev/pci/drm/i915/soc/intel_dram.c
125
val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
sys/dev/pci/drm/i915/soc/intel_dram.c
128
switch ((val >> 6) & 3) {
sys/dev/pci/drm/i915/soc/intel_dram.c
269
static int skl_get_dimm_size(u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
271
return (val & SKL_DRAM_SIZE_MASK) * 8;
sys/dev/pci/drm/i915/soc/intel_dram.c
274
static int skl_get_dimm_width(u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
276
if (skl_get_dimm_size(val) == 0)
sys/dev/pci/drm/i915/soc/intel_dram.c
279
switch (val & SKL_DRAM_WIDTH_MASK) {
sys/dev/pci/drm/i915/soc/intel_dram.c
283
val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
sys/dev/pci/drm/i915/soc/intel_dram.c
284
return 8 << val;
sys/dev/pci/drm/i915/soc/intel_dram.c
286
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
291
static int skl_get_dimm_ranks(u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
293
if (skl_get_dimm_size(val) == 0)
sys/dev/pci/drm/i915/soc/intel_dram.c
296
val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
sys/dev/pci/drm/i915/soc/intel_dram.c
298
return val + 1;
sys/dev/pci/drm/i915/soc/intel_dram.c
302
static int icl_get_dimm_size(u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
304
return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
sys/dev/pci/drm/i915/soc/intel_dram.c
307
static int icl_get_dimm_width(u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
309
if (icl_get_dimm_size(val) == 0)
sys/dev/pci/drm/i915/soc/intel_dram.c
312
switch (val & ICL_DRAM_WIDTH_MASK) {
sys/dev/pci/drm/i915/soc/intel_dram.c
316
val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
sys/dev/pci/drm/i915/soc/intel_dram.c
317
return 8 << val;
sys/dev/pci/drm/i915/soc/intel_dram.c
319
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
324
static int icl_get_dimm_ranks(u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
326
if (icl_get_dimm_size(val) == 0)
sys/dev/pci/drm/i915/soc/intel_dram.c
329
val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
sys/dev/pci/drm/i915/soc/intel_dram.c
331
return val + 1;
sys/dev/pci/drm/i915/soc/intel_dram.c
344
int channel, char dimm_name, u16 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
347
dimm->size = icl_get_dimm_size(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
348
dimm->width = icl_get_dimm_width(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
349
dimm->ranks = icl_get_dimm_ranks(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
351
dimm->size = skl_get_dimm_size(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
352
dimm->width = skl_get_dimm_width(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
353
dimm->ranks = skl_get_dimm_ranks(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
365
int channel, u32 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
368
channel, 'L', val & 0xffff);
sys/dev/pci/drm/i915/soc/intel_dram.c
370
channel, 'S', val >> 16);
sys/dev/pci/drm/i915/soc/intel_dram.c
406
u32 val;
sys/dev/pci/drm/i915/soc/intel_dram.c
412
val = intel_uncore_read(&i915->uncore,
sys/dev/pci/drm/i915/soc/intel_dram.c
414
ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
sys/dev/pci/drm/i915/soc/intel_dram.c
418
val = intel_uncore_read(&i915->uncore,
sys/dev/pci/drm/i915/soc/intel_dram.c
420
ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
sys/dev/pci/drm/i915/soc/intel_dram.c
450
u32 val;
sys/dev/pci/drm/i915/soc/intel_dram.c
452
val = intel_uncore_read(&i915->uncore,
sys/dev/pci/drm/i915/soc/intel_dram.c
455
switch (val & SKL_DRAM_DDR_TYPE_MASK) {
sys/dev/pci/drm/i915/soc/intel_dram.c
465
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
485
static int bxt_get_dimm_size(u32 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
487
switch (val & BXT_DRAM_SIZE_MASK) {
sys/dev/pci/drm/i915/soc/intel_dram.c
499
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
504
static int bxt_get_dimm_width(u32 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
506
if (!bxt_get_dimm_size(val))
sys/dev/pci/drm/i915/soc/intel_dram.c
509
val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
sys/dev/pci/drm/i915/soc/intel_dram.c
511
return 8 << val;
sys/dev/pci/drm/i915/soc/intel_dram.c
514
static int bxt_get_dimm_ranks(u32 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
516
if (!bxt_get_dimm_size(val))
sys/dev/pci/drm/i915/soc/intel_dram.c
519
switch (val & BXT_DRAM_RANK_MASK) {
sys/dev/pci/drm/i915/soc/intel_dram.c
525
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
530
static enum intel_dram_type bxt_get_dimm_type(u32 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
532
if (!bxt_get_dimm_size(val))
sys/dev/pci/drm/i915/soc/intel_dram.c
535
switch (val & BXT_DRAM_TYPE_MASK) {
sys/dev/pci/drm/i915/soc/intel_dram.c
545
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
550
static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
sys/dev/pci/drm/i915/soc/intel_dram.c
552
dimm->width = bxt_get_dimm_width(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
553
dimm->ranks = bxt_get_dimm_ranks(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
559
dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
sys/dev/pci/drm/i915/soc/intel_dram.c
564
u32 val;
sys/dev/pci/drm/i915/soc/intel_dram.c
575
val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
sys/dev/pci/drm/i915/soc/intel_dram.c
576
if (val == 0xFFFFFFFF)
sys/dev/pci/drm/i915/soc/intel_dram.c
581
bxt_get_dimm_info(&dimm, val);
sys/dev/pci/drm/i915/soc/intel_dram.c
582
type = bxt_get_dimm_type(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
611
u32 val = 0;
sys/dev/pci/drm/i915/soc/intel_dram.c
615
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
sys/dev/pci/drm/i915/soc/intel_dram.c
620
switch (val & 0xf) {
sys/dev/pci/drm/i915/soc/intel_dram.c
640
MISSING_CASE(val & 0xf);
sys/dev/pci/drm/i915/soc/intel_dram.c
644
switch (val & 0xf) {
sys/dev/pci/drm/i915/soc/intel_dram.c
658
MISSING_CASE(val & 0xf);
sys/dev/pci/drm/i915/soc/intel_dram.c
663
dram_info->num_channels = (val & 0xf0) >> 4;
sys/dev/pci/drm/i915/soc/intel_dram.c
664
dram_info->num_qgv_points = (val & 0xf00) >> 8;
sys/dev/pci/drm/i915/soc/intel_dram.c
665
dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
sys/dev/pci/drm/i915/soc/intel_dram.c
688
u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
sys/dev/pci/drm/i915/soc/intel_dram.c
690
switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
sys/dev/pci/drm/i915/soc/intel_dram.c
718
MISSING_CASE(val);
sys/dev/pci/drm/i915/soc/intel_dram.c
722
dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
sys/dev/pci/drm/i915/soc/intel_dram.c
723
dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
sys/dev/pci/drm/i915/vlv_iosf_sb.c
110
intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
sys/dev/pci/drm/i915/vlv_iosf_sb.c
123
*val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
sys/dev/pci/drm/i915/vlv_iosf_sb.c
182
u32 devfn, port, opcode, val = 0;
sys/dev/pci/drm/i915/vlv_iosf_sb.c
193
vlv_sideband_rw(i915, devfn, port, opcode, addr, &val);
sys/dev/pci/drm/i915/vlv_iosf_sb.c
195
return val;
sys/dev/pci/drm/i915/vlv_iosf_sb.c
198
int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val)
sys/dev/pci/drm/i915/vlv_iosf_sb.c
212
return vlv_sideband_rw(i915, devfn, port, opcode, addr, &val);
sys/dev/pci/drm/i915/vlv_iosf_sb.c
88
u32 addr, u32 *val)
sys/dev/pci/drm/i915/vlv_iosf_sb.h
35
int vlv_iosf_sb_write(struct drm_device *drm, enum vlv_iosf_sb_unit unit, u32 addr, u32 val);
sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h
13
#define _SSPM0_SSC(val) ((val) << 0)
sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h
19
#define _SSPM0_SSS(val) ((val) << 24)
sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h
49
#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
sys/dev/pci/drm/i915/vlv_iosf_sb_reg.h
55
#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
sys/dev/pci/drm/i915/vlv_suspend.c
282
u32 mask, u32 val)
sys/dev/pci/drm/i915/vlv_suspend.c
297
== val, 3);
sys/dev/pci/drm/i915/vlv_suspend.c
333
u32 val;
sys/dev/pci/drm/i915/vlv_suspend.c
341
val = allow ? mask : 0;
sys/dev/pci/drm/i915/vlv_suspend.c
343
err = vlv_wait_for_pw_status(i915, mask, val);
sys/dev/pci/drm/i915/vlv_suspend.c
354
u32 val;
sys/dev/pci/drm/i915/vlv_suspend.c
357
val = wait_for_on ? mask : 0;
sys/dev/pci/drm/i915/vlv_suspend.c
366
if (vlv_wait_for_pw_status(dev_priv, mask, val))
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
267
void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
269
seq_num[0] = val >> 16;
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
270
seq_num[1] = val >> 8;
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
271
seq_num[2] = val;
sys/dev/pci/drm/include/drm/display/drm_hdcp_helper.h
20
void drm_hdcp_update_content_protection(struct drm_connector *connector, u64 val);
sys/dev/pci/drm/include/drm/drm_connector.h
1426
uint64_t val);
sys/dev/pci/drm/include/drm/drm_connector.h
1558
uint64_t val);
sys/dev/pci/drm/include/drm/drm_connector.h
1581
uint64_t *val);
sys/dev/pci/drm/include/drm/drm_connector.h
2430
const char *drm_get_dpms_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2431
const char *drm_get_dvi_i_subconnector_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2432
const char *drm_get_dvi_i_select_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2433
const char *drm_get_tv_mode_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2434
const char *drm_get_tv_subconnector_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2435
const char *drm_get_tv_select_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2436
const char *drm_get_dp_subconnector_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2437
const char *drm_get_content_protection_name(int val);
sys/dev/pci/drm/include/drm/drm_connector.h
2438
const char *drm_get_hdcp_content_type_name(int val);
sys/dev/pci/drm/include/drm/drm_crtc.h
48
static inline int64_t U642I64(uint64_t val)
sys/dev/pci/drm/include/drm/drm_crtc.h
50
return (int64_t)*((int64_t *)&val);
sys/dev/pci/drm/include/drm/drm_crtc.h
52
static inline uint64_t I642U64(int64_t val)
sys/dev/pci/drm/include/drm/drm_crtc.h
54
return (uint64_t)*((uint64_t *)&val);
sys/dev/pci/drm/include/drm/drm_crtc.h
616
struct drm_property *property, uint64_t val);
sys/dev/pci/drm/include/drm/drm_crtc.h
707
uint64_t val);
sys/dev/pci/drm/include/drm/drm_crtc.h
729
uint64_t *val);
sys/dev/pci/drm/include/drm/drm_flip_work.h
51
typedef void (*drm_flip_func_t)(struct drm_flip_work *work, void *val);
sys/dev/pci/drm/include/drm/drm_flip_work.h
71
void drm_flip_work_queue(struct drm_flip_work *work, void *val);
sys/dev/pci/drm/include/drm/drm_mode_object.h
111
const char *fnname(int val) \
sys/dev/pci/drm/include/drm/drm_mode_object.h
115
if (list[i].type == val) \
sys/dev/pci/drm/include/drm/drm_mode_object.h
129
uint64_t val);
sys/dev/pci/drm/include/drm/drm_mode_object.h
135
uint64_t *val);
sys/dev/pci/drm/include/drm/drm_plane.h
381
struct drm_property *property, uint64_t val);
sys/dev/pci/drm/include/drm/drm_plane.h
472
uint64_t val);
sys/dev/pci/drm/include/drm/drm_plane.h
495
uint64_t *val);
sys/dev/pci/drm/include/drm/gud.h
62
__le64 val;
sys/dev/pci/drm/include/linux/atomic.h
160
volatile int64_t val;
sys/dev/pci/drm/include/linux/atomic.h
169
v->val = i;
sys/dev/pci/drm/include/linux/atomic.h
176
int64_t val;
sys/dev/pci/drm/include/linux/atomic.h
179
val = v->val;
sys/dev/pci/drm/include/linux/atomic.h
182
return val;
sys/dev/pci/drm/include/linux/atomic.h
188
int64_t val;
sys/dev/pci/drm/include/linux/atomic.h
191
val = v->val;
sys/dev/pci/drm/include/linux/atomic.h
192
v->val = n;
sys/dev/pci/drm/include/linux/atomic.h
195
return val;
sys/dev/pci/drm/include/linux/atomic.h
202
v->val += i;
sys/dev/pci/drm/include/linux/atomic.h
211
int64_t val;
sys/dev/pci/drm/include/linux/atomic.h
214
val = v->val + i;
sys/dev/pci/drm/include/linux/atomic.h
215
v->val = val;
sys/dev/pci/drm/include/linux/atomic.h
218
return val;
sys/dev/pci/drm/include/linux/atomic.h
227
v->val -= i;
sys/dev/pci/drm/include/linux/hash.h
12
hash_32(uint32_t val, unsigned int bits)
sys/dev/pci/drm/include/linux/hash.h
14
return (val * GOLDEN_RATIO_32) >> (32 - bits);
sys/dev/pci/drm/include/linux/hash.h
21
hash_64(uint64_t val, unsigned int bits)
sys/dev/pci/drm/include/linux/hash.h
23
return (val * GOLDEN_RATIO_64) >> (64 - bits);
sys/dev/pci/drm/include/linux/hash.h
27
#define hash_long(val, bits) hash_64(val, bits)
sys/dev/pci/drm/include/linux/hash.h
29
#define hash_long(val, bits) hash_32(val, bits)
sys/dev/pci/drm/include/linux/io.h
102
*(volatile uint64_t *)addr = val;
sys/dev/pci/drm/include/linux/io.h
110
uint16_t val;
sys/dev/pci/drm/include/linux/io.h
113
val = lemtoh16(addr);
sys/dev/pci/drm/include/linux/io.h
115
return val;
sys/dev/pci/drm/include/linux/io.h
121
uint32_t val;
sys/dev/pci/drm/include/linux/io.h
124
val = lemtoh32(addr);
sys/dev/pci/drm/include/linux/io.h
126
return val;
sys/dev/pci/drm/include/linux/io.h
132
uint64_t val;
sys/dev/pci/drm/include/linux/io.h
135
val = lemtoh64(addr);
sys/dev/pci/drm/include/linux/io.h
137
return val;
sys/dev/pci/drm/include/linux/io.h
141
iowrite16(u16 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/io.h
144
htolem16(addr, val);
sys/dev/pci/drm/include/linux/io.h
148
iowrite32(u32 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/io.h
151
htolem32(addr, val);
sys/dev/pci/drm/include/linux/io.h
155
iowrite64(u64 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/io.h
158
htolem64(addr, val);
sys/dev/pci/drm/include/linux/io.h
28
uint8_t val;
sys/dev/pci/drm/include/linux/io.h
31
val = *(volatile uint8_t *)addr;
sys/dev/pci/drm/include/linux/io.h
33
return val;
sys/dev/pci/drm/include/linux/io.h
37
iowrite8(u8 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/io.h
40
*(volatile uint8_t *)addr = val;
sys/dev/pci/drm/include/linux/io.h
54
uint16_t val;
sys/dev/pci/drm/include/linux/io.h
57
val = *(volatile uint16_t *)addr;
sys/dev/pci/drm/include/linux/io.h
59
return val;
sys/dev/pci/drm/include/linux/io.h
65
uint32_t val;
sys/dev/pci/drm/include/linux/io.h
68
val = *(volatile uint32_t *)addr;
sys/dev/pci/drm/include/linux/io.h
70
return val;
sys/dev/pci/drm/include/linux/io.h
76
uint64_t val;
sys/dev/pci/drm/include/linux/io.h
79
val = *(volatile uint64_t *)addr;
sys/dev/pci/drm/include/linux/io.h
81
return val;
sys/dev/pci/drm/include/linux/io.h
85
iowrite16(u16 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/io.h
88
*(volatile uint16_t *)addr = val;
sys/dev/pci/drm/include/linux/io.h
92
iowrite32(u32 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/io.h
95
*(volatile uint32_t *)addr = val;
sys/dev/pci/drm/include/linux/io.h
99
iowrite64(u64 val, volatile void __iomem *addr)
sys/dev/pci/drm/include/linux/iopoll.h
41
#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
sys/dev/pci/drm/include/linux/iopoll.h
42
poll_timeout_us((val) = (op)(addr), cond, sleep_us, timeout_us, false)
sys/dev/pci/drm/include/linux/pci.h
143
pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
sys/dev/pci/drm/include/linux/pci.h
145
*val = pci_conf_read(pdev->pc, pdev->tag, reg);
sys/dev/pci/drm/include/linux/pci.h
150
pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
sys/dev/pci/drm/include/linux/pci.h
155
*val = (v >> ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
160
pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
sys/dev/pci/drm/include/linux/pci.h
165
*val = (v >> ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
170
pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
sys/dev/pci/drm/include/linux/pci.h
172
pci_conf_write(pdev->pc, pdev->tag, reg, val);
sys/dev/pci/drm/include/linux/pci.h
177
pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
sys/dev/pci/drm/include/linux/pci.h
183
v |= (val << ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
189
pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
sys/dev/pci/drm/include/linux/pci.h
195
v |= (val << ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
202
int reg, u16 *val)
sys/dev/pci/drm/include/linux/pci.h
209
*val = (v >> ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
215
int reg, u8 *val)
sys/dev/pci/drm/include/linux/pci.h
222
*val = (v >> ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
228
int reg, u8 val)
sys/dev/pci/drm/include/linux/pci.h
236
v |= (val << ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
281
pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val)
sys/dev/pci/drm/include/linux/pci.h
286
*val = 0;
sys/dev/pci/drm/include/linux/pci.h
289
*val = pci_conf_read(pdev->pc, pdev->tag, pos + off);
sys/dev/pci/drm/include/linux/pci.h
294
pcie_capability_read_word(struct pci_dev *pdev, int off, u16 *val)
sys/dev/pci/drm/include/linux/pci.h
299
*val = 0;
sys/dev/pci/drm/include/linux/pci.h
302
pci_read_config_word(pdev, pos + off, val);
sys/dev/pci/drm/include/linux/pci.h
307
pcie_capability_write_word(struct pci_dev *pdev, int off, u16 val)
sys/dev/pci/drm/include/linux/pci.h
313
pci_write_config_word(pdev, pos + off, val);
sys/dev/pci/drm/include/linux/pci.h
318
pcie_capability_set_word(struct pci_dev *pdev, int off, u16 val)
sys/dev/pci/drm/include/linux/pci.h
322
r |= val;
sys/dev/pci/drm/include/linux/pci.h
351
uint16_t val;
sys/dev/pci/drm/include/linux/pci.h
353
pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
sys/dev/pci/drm/include/linux/pci.h
355
return 128 << ((val & PCI_PCIE_DCSR_MPS) >> 12);
sys/dev/pci/drm/include/linux/pci.h
361
uint16_t val;
sys/dev/pci/drm/include/linux/pci.h
363
pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
sys/dev/pci/drm/include/linux/pci.h
364
val &= ~PCI_PCIE_DCSR_MPS;
sys/dev/pci/drm/include/linux/pci.h
365
val |= (ffs(rrq) - 8) << 12;
sys/dev/pci/drm/include/linux/pci.h
366
return pcie_capability_write_word(pdev, PCI_PCIE_DCSR, val);
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
1081
#define fourcc_mod_broadcom_code(val, params) \
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
1082
fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
1644
#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
491
#define fourcc_mod_code(vendor, val) \
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
492
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
sys/dev/pci/drm/include/uapi/drm/i915_drm.h
2656
__u64 val; /* Return value */
sys/dev/pci/drm/radeon/atom.c
1002
if (val == src) {
sys/dev/pci/drm/radeon/atom.c
187
uint32_t idx, val = 0xCDCDCDCD, align, arg;
sys/dev/pci/drm/radeon/atom.c
200
val = gctx->card->reg_read(gctx->card, idx);
sys/dev/pci/drm/radeon/atom.c
218
val =
sys/dev/pci/drm/radeon/atom.c
230
val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
sys/dev/pci/drm/radeon/atom.c
234
DEBUG("PS[0x%02X,0x%04X]", idx, val);
sys/dev/pci/drm/radeon/atom.c
243
val = gctx->divmul[0];
sys/dev/pci/drm/radeon/atom.c
246
val = gctx->divmul[1];
sys/dev/pci/drm/radeon/atom.c
249
val = gctx->data_block;
sys/dev/pci/drm/radeon/atom.c
252
val = gctx->shift;
sys/dev/pci/drm/radeon/atom.c
255
val = 1 << gctx->shift;
sys/dev/pci/drm/radeon/atom.c
258
val = ~(1 << gctx->shift);
sys/dev/pci/drm/radeon/atom.c
261
val = gctx->fb_base;
sys/dev/pci/drm/radeon/atom.c
264
val = gctx->io_attr;
sys/dev/pci/drm/radeon/atom.c
267
val = gctx->reg_block;
sys/dev/pci/drm/radeon/atom.c
271
val = ctx->ws[idx];
sys/dev/pci/drm/radeon/atom.c
285
val = U32(idx + gctx->data_block);
sys/dev/pci/drm/radeon/atom.c
293
val = 0;
sys/dev/pci/drm/radeon/atom.c
295
val = gctx->scratch[(gctx->fb_base / 4) + idx];
sys/dev/pci/drm/radeon/atom.c
302
val = U32(*ptr);
sys/dev/pci/drm/radeon/atom.c
305
DEBUG("IMM 0x%08X\n", val);
sys/dev/pci/drm/radeon/atom.c
306
return val;
sys/dev/pci/drm/radeon/atom.c
310
val = U16(*ptr);
sys/dev/pci/drm/radeon/atom.c
313
DEBUG("IMM 0x%04X\n", val);
sys/dev/pci/drm/radeon/atom.c
314
return val;
sys/dev/pci/drm/radeon/atom.c
319
val = U8(*ptr);
sys/dev/pci/drm/radeon/atom.c
322
DEBUG("IMM 0x%02X\n", val);
sys/dev/pci/drm/radeon/atom.c
323
return val;
sys/dev/pci/drm/radeon/atom.c
331
val = gctx->card->pll_read(gctx->card, idx);
sys/dev/pci/drm/radeon/atom.c
338
val = gctx->card->mc_read(gctx->card, idx);
sys/dev/pci/drm/radeon/atom.c
342
*saved = val;
sys/dev/pci/drm/radeon/atom.c
343
val &= atom_arg_mask[align];
sys/dev/pci/drm/radeon/atom.c
344
val >>= atom_arg_shift[align];
sys/dev/pci/drm/radeon/atom.c
348
DEBUG(".[31:0] -> 0x%08X\n", val);
sys/dev/pci/drm/radeon/atom.c
351
DEBUG(".[15:0] -> 0x%04X\n", val);
sys/dev/pci/drm/radeon/atom.c
354
DEBUG(".[23:8] -> 0x%04X\n", val);
sys/dev/pci/drm/radeon/atom.c
357
DEBUG(".[31:16] -> 0x%04X\n", val);
sys/dev/pci/drm/radeon/atom.c
360
DEBUG(".[7:0] -> 0x%02X\n", val);
sys/dev/pci/drm/radeon/atom.c
363
DEBUG(".[15:8] -> 0x%02X\n", val);
sys/dev/pci/drm/radeon/atom.c
366
DEBUG(".[23:16] -> 0x%02X\n", val);
sys/dev/pci/drm/radeon/atom.c
369
DEBUG(".[31:24] -> 0x%02X\n", val);
sys/dev/pci/drm/radeon/atom.c
372
return val;
sys/dev/pci/drm/radeon/atom.c
418
uint32_t val = 0xCDCDCDCD;
sys/dev/pci/drm/radeon/atom.c
422
val = U32(*ptr);
sys/dev/pci/drm/radeon/atom.c
428
val = U16(*ptr);
sys/dev/pci/drm/radeon/atom.c
435
val = U8(*ptr);
sys/dev/pci/drm/radeon/atom.c
439
return val;
sys/dev/pci/drm/radeon/atom.c
459
int *ptr, uint32_t val, uint32_t saved)
sys/dev/pci/drm/radeon/atom.c
463
val, idx;
sys/dev/pci/drm/radeon/atom.c
466
val <<= atom_arg_shift[align];
sys/dev/pci/drm/radeon/atom.c
467
val &= atom_arg_mask[align];
sys/dev/pci/drm/radeon/atom.c
469
val |= saved;
sys/dev/pci/drm/radeon/atom.c
480
val << 2);
sys/dev/pci/drm/radeon/atom.c
482
gctx->card->reg_write(gctx->card, idx, val);
sys/dev/pci/drm/radeon/atom.c
501
idx, val);
sys/dev/pci/drm/radeon/atom.c
512
ctx->ps[idx] = cpu_to_le32(val);
sys/dev/pci/drm/radeon/atom.c
520
gctx->divmul[0] = val;
sys/dev/pci/drm/radeon/atom.c
523
gctx->divmul[1] = val;
sys/dev/pci/drm/radeon/atom.c
526
gctx->data_block = val;
sys/dev/pci/drm/radeon/atom.c
529
gctx->shift = val;
sys/dev/pci/drm/radeon/atom.c
535
gctx->fb_base = val;
sys/dev/pci/drm/radeon/atom.c
538
gctx->io_attr = val;
sys/dev/pci/drm/radeon/atom.c
541
gctx->reg_block = val;
sys/dev/pci/drm/radeon/atom.c
548
ctx->ws[idx] = val;
sys/dev/pci/drm/radeon/atom.c
558
gctx->scratch[(gctx->fb_base / 4) + idx] = val;
sys/dev/pci/drm/radeon/atom.c
565
gctx->card->pll_write(gctx->card, idx, val);
sys/dev/pci/drm/radeon/atom.c
571
gctx->card->mc_write(gctx->card, idx, val);
sys/dev/pci/drm/radeon/atom.c
830
uint8_t val = U8((*ptr)++);
sys/dev/pci/drm/radeon/atom.c
831
SDEBUG("POST card output: 0x%02X\n", val);
sys/dev/pci/drm/radeon/atom.c
991
uint32_t src, val, target;
sys/dev/pci/drm/radeon/atom.c
998
val =
sys/dev/pci/drm/radeon/btc_dpm.c
1739
u32 val;
sys/dev/pci/drm/radeon/btc_dpm.c
1744
val = (arb_registers->mc_arb_rfsh_rate & POWERMODE0_MASK) >>
sys/dev/pci/drm/radeon/btc_dpm.c
1746
WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
sys/dev/pci/drm/radeon/btc_dpm.c
1748
val = (arb_registers->mc_arb_burst_time & STATE0_MASK) >>
sys/dev/pci/drm/radeon/btc_dpm.c
1750
WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
sys/dev/pci/drm/radeon/btc_dpm.c
1782
u32 val;
sys/dev/pci/drm/radeon/btc_dpm.c
1790
val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk);
sys/dev/pci/drm/radeon/btc_dpm.c
1791
WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
sys/dev/pci/drm/radeon/btc_dpm.c
1793
val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk);
sys/dev/pci/drm/radeon/btc_dpm.c
1794
WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
sys/dev/pci/drm/radeon/cik.c
154
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/cik.c
169
*val = RREG32(reg);
sys/dev/pci/drm/radeon/evergreen.c
1094
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/evergreen.c
1104
*val = RREG32(reg);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
324
uint32_t val;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
326
val = RREG32(HDMI_CONTROL + offset);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
327
val &= ~HDMI_DEEP_COLOR_ENABLE;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
328
val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
340
val |= HDMI_DEEP_COLOR_ENABLE;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
341
val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
346
val |= HDMI_DEEP_COLOR_ENABLE;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
347
val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
353
WREG32(HDMI_CONTROL + offset, val);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
457
uint32_t val;
sys/dev/pci/drm/radeon/evergreen_hdmi.c
467
val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
468
val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
471
val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
473
val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
sys/dev/pci/drm/radeon/evergreen_hdmi.c
475
WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
sys/dev/pci/drm/radeon/ni.c
836
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/ni.c
847
*val = RREG32(reg);
sys/dev/pci/drm/radeon/r100.c
4146
u32 val;
sys/dev/pci/drm/radeon/r100.c
4149
val = bus_space_read_4(rdev->iot, rdev->rio_mem, reg);
sys/dev/pci/drm/radeon/r100.c
4157
val = bus_space_read_4(rdev->iot, rdev->rio_mem,
sys/dev/pci/drm/radeon/r100.c
4163
return val;
sys/dev/pci/drm/radeon/r600.c
175
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/r600.c
183
*val = RREG32(reg);
sys/dev/pci/drm/radeon/r600.c
1984
int r600_count_pipe_bits(uint32_t val)
sys/dev/pci/drm/radeon/r600.c
1986
return hweight32(val);
sys/dev/pci/drm/radeon/r600_cs.c
1403
unsigned val;
sys/dev/pci/drm/radeon/r600_cs.c
1405
val = max(1U, size >> level);
sys/dev/pci/drm/radeon/r600_cs.c
1407
val = roundup_pow_of_two(val);
sys/dev/pci/drm/radeon/r600_cs.c
1408
return val;
sys/dev/pci/drm/radeon/radeon.h
1864
int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon.h
2580
#define WREG32_P(reg, val, mask) \
sys/dev/pci/drm/radeon/radeon.h
2584
tmp_ |= ((val) & ~(mask)); \
sys/dev/pci/drm/radeon/radeon.h
2589
#define WREG32_PLL_P(reg, val, mask) \
sys/dev/pci/drm/radeon/radeon.h
2593
tmp_ |= ((val) & ~(mask)); \
sys/dev/pci/drm/radeon/radeon.h
2596
#define WREG32_SMC_P(reg, val, mask) \
sys/dev/pci/drm/radeon/radeon.h
2600
tmp_ |= ((val) & ~(mask)); \
sys/dev/pci/drm/radeon/radeon_acpi.c
678
unsigned long val,
sys/dev/pci/drm/radeon/radeon_asic.c
140
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/radeon_asic.h
376
int r600_count_pipe_bits(uint32_t val);
sys/dev/pci/drm/radeon/radeon_asic.h
388
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
551
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
655
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
752
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
871
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_clocks.c
114
const u32 *val;
sys/dev/pci/drm/radeon/radeon_clocks.c
122
val = of_get_property(dp, "ATY,RefCLK", NULL);
sys/dev/pci/drm/radeon/radeon_clocks.c
123
if (!val || !*val) {
sys/dev/pci/drm/radeon/radeon_clocks.c
127
p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
sys/dev/pci/drm/radeon/radeon_clocks.c
161
val = of_get_property(dp, "ATY,SCLK", NULL);
sys/dev/pci/drm/radeon/radeon_clocks.c
162
if (val && *val)
sys/dev/pci/drm/radeon/radeon_clocks.c
163
rdev->clock.default_sclk = (*val) / 10;
sys/dev/pci/drm/radeon/radeon_clocks.c
168
val = of_get_property(dp, "ATY,MCLK", NULL);
sys/dev/pci/drm/radeon/radeon_clocks.c
169
if (val && *val)
sys/dev/pci/drm/radeon/radeon_clocks.c
170
rdev->clock.default_mclk = (*val) / 10;
sys/dev/pci/drm/radeon/radeon_clocks.c
197
uint32_t val;
sys/dev/pci/drm/radeon/radeon_clocks.c
203
if (OF_getprop(node, "ATY,RefCLK", &val, sizeof(val)) != sizeof(val) || !val)
sys/dev/pci/drm/radeon/radeon_clocks.c
205
p1pll->reference_freq = p2pll->reference_freq = (val) / 10;
sys/dev/pci/drm/radeon/radeon_clocks.c
239
if (OF_getprop(node, "ATY,SCLK", &val, sizeof(val)) == sizeof(val) && val)
sys/dev/pci/drm/radeon/radeon_clocks.c
240
rdev->clock.default_sclk = (val) / 10;
sys/dev/pci/drm/radeon/radeon_clocks.c
245
if (OF_getprop(node, "ATY,MCLK", &val, sizeof(val)) == sizeof(val) && val)
sys/dev/pci/drm/radeon/radeon_clocks.c
246
rdev->clock.default_mclk = (val) / 10;
sys/dev/pci/drm/radeon/radeon_combios.c
2889
uint32_t reg, val, and_mask, or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
2909
val = RBIOS32(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2911
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2919
val = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2920
val = (val & and_mask) | or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
2921
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2924
val = RBIOS16(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2926
udelay(val);
sys/dev/pci/drm/radeon/radeon_combios.c
2929
val = RBIOS16(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2931
mdelay(val);
sys/dev/pci/drm/radeon/radeon_combios.c
2939
val = RBIOS8(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2943
reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2964
val = RBIOS32(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2965
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2973
val = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2974
val = (val & and_mask) | or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
2975
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2978
val = RBIOS16(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2980
udelay(val);
sys/dev/pci/drm/radeon/radeon_combios.c
2988
val = RREG32_PLL(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2989
val = (val & and_mask) | or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
2990
WREG32_PLL(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2994
val = RBIOS8(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2998
reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3020
uint32_t val, and_mask, or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
3026
val = RBIOS32(offset);
sys/dev/pci/drm/radeon/radeon_combios.c
3028
WREG32(addr, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3031
val = RBIOS32(offset);
sys/dev/pci/drm/radeon/radeon_combios.c
3033
WREG32(addr, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3056
val = RBIOS16(offset);
sys/dev/pci/drm/radeon/radeon_combios.c
3058
udelay(val);
sys/dev/pci/drm/radeon/radeon_combios.c
3061
val = RBIOS16(offset);
sys/dev/pci/drm/radeon/radeon_combios.c
3065
while (val--) {
sys/dev/pci/drm/radeon/radeon_combios.c
3074
while (val--) {
sys/dev/pci/drm/radeon/radeon_combios.c
3099
uint32_t val, shift, tmp;
sys/dev/pci/drm/radeon/radeon_combios.c
3105
val = RBIOS32(offset);
sys/dev/pci/drm/radeon/radeon_combios.c
3107
WREG32_PLL(addr, val);
sys/dev/pci/drm/radeon/radeon_combios.c
3188
uint8_t val = RBIOS8(offset);
sys/dev/pci/drm/radeon/radeon_combios.c
3189
while (val != 0xff) {
sys/dev/pci/drm/radeon/radeon_combios.c
3192
if (val == 0x0f) {
sys/dev/pci/drm/radeon/radeon_combios.c
3217
or_mask = val << 24;
sys/dev/pci/drm/radeon/radeon_combios.c
3223
val = RBIOS8(offset);
sys/dev/pci/drm/radeon/radeon_connectors.c
516
uint64_t val)
sys/dev/pci/drm/radeon/radeon_connectors.c
538
new_coherent_mode = val ? true : false;
sys/dev/pci/drm/radeon/radeon_connectors.c
554
if (radeon_connector->audio != val) {
sys/dev/pci/drm/radeon/radeon_connectors.c
555
radeon_connector->audio = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
569
if (radeon_connector->dither != val) {
sys/dev/pci/drm/radeon/radeon_connectors.c
570
radeon_connector->dither = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
583
if (radeon_encoder->underscan_type != val) {
sys/dev/pci/drm/radeon/radeon_connectors.c
584
radeon_encoder->underscan_type = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
597
if (radeon_encoder->underscan_hborder != val) {
sys/dev/pci/drm/radeon/radeon_connectors.c
598
radeon_encoder->underscan_hborder = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
611
if (radeon_encoder->underscan_vborder != val) {
sys/dev/pci/drm/radeon/radeon_connectors.c
612
radeon_encoder->underscan_vborder = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
632
dac_int->tv_std = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
636
dac_int->tv_std = val;
sys/dev/pci/drm/radeon/radeon_connectors.c
645
if (val == 0)
sys/dev/pci/drm/radeon/radeon_connectors.c
665
if (val == 0) {
sys/dev/pci/drm/radeon/radeon_connectors.c
671
if (val == 1 || !ret)
sys/dev/pci/drm/radeon/radeon_connectors.c
687
switch (val) {
sys/dev/pci/drm/radeon/radeon_connectors.c
714
if (radeon_encoder->output_csc == val)
sys/dev/pci/drm/radeon/radeon_connectors.c
717
radeon_encoder->output_csc = val;
sys/dev/pci/drm/radeon/radeon_device.c
862
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
866
rdev->pll_wreg(rdev, reg, val);
sys/dev/pci/drm/radeon/radeon_device.c
896
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
900
rdev->mc_wreg(rdev, reg, val);
sys/dev/pci/drm/radeon/radeon_device.c
912
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
916
WREG32(reg*4, val);
sys/dev/pci/drm/radeon/radeon_device.c
946
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
950
WREG32_IO(reg*4, val);
sys/dev/pci/drm/radeon/radeon_fence.c
929
static int radeon_debugfs_gpu_reset(void *data, u64 *val)
sys/dev/pci/drm/radeon/radeon_fence.c
934
*val = rdev->needs_reset;
sys/dev/pci/drm/radeon/radeon_i2c.c
1155
u8 *val)
sys/dev/pci/drm/radeon/radeon_i2c.c
1178
*val = in_buf[0];
sys/dev/pci/drm/radeon/radeon_i2c.c
1179
DRM_DEBUG("val = 0x%02x\n", *val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1182
addr, *val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1189
u8 val)
sys/dev/pci/drm/radeon/radeon_i2c.c
1200
out_buf[1] = val;
sys/dev/pci/drm/radeon/radeon_i2c.c
1204
addr, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1210
u8 val;
sys/dev/pci/drm/radeon/radeon_i2c.c
1220
0x3, &val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1221
val &= ~radeon_connector->router.ddc_mux_control_pin;
sys/dev/pci/drm/radeon/radeon_i2c.c
1224
0x3, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1227
0x1, &val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1228
val &= ~radeon_connector->router.ddc_mux_control_pin;
sys/dev/pci/drm/radeon/radeon_i2c.c
1229
val |= radeon_connector->router.ddc_mux_state;
sys/dev/pci/drm/radeon/radeon_i2c.c
1232
0x1, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1238
u8 val;
sys/dev/pci/drm/radeon/radeon_i2c.c
1248
0x3, &val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1249
val &= ~radeon_connector->router.cd_mux_control_pin;
sys/dev/pci/drm/radeon/radeon_i2c.c
1252
0x3, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1255
0x1, &val);
sys/dev/pci/drm/radeon/radeon_i2c.c
1256
val &= ~radeon_connector->router.cd_mux_control_pin;
sys/dev/pci/drm/radeon/radeon_i2c.c
1257
val |= radeon_connector->router.cd_mux_state;
sys/dev/pci/drm/radeon/radeon_i2c.c
1260
0x1, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
182
uint32_t val;
sys/dev/pci/drm/radeon/radeon_i2c.c
185
val = RREG32(rec->y_clk_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
186
val &= rec->y_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
188
return (val != 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
197
uint32_t val;
sys/dev/pci/drm/radeon/radeon_i2c.c
200
val = RREG32(rec->y_data_reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
201
val &= rec->y_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
203
return (val != 0);
sys/dev/pci/drm/radeon/radeon_i2c.c
211
uint32_t val;
sys/dev/pci/drm/radeon/radeon_i2c.c
214
val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
215
val |= clock ? 0 : rec->en_clk_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
216
WREG32(rec->en_clk_reg, val);
sys/dev/pci/drm/radeon/radeon_i2c.c
224
uint32_t val;
sys/dev/pci/drm/radeon/radeon_i2c.c
227
val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
228
val |= data ? 0 : rec->en_data_mask;
sys/dev/pci/drm/radeon/radeon_i2c.c
229
WREG32(rec->en_data_reg, val);
sys/dev/pci/drm/radeon/radeon_mode.h
756
u8 *val);
sys/dev/pci/drm/radeon/radeon_mode.h
760
u8 val);
sys/dev/pci/drm/radeon/si.c
1288
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/si.c
1300
*val = RREG32(reg);
sys/dev/pci/drm/radeon/trinity_dpm.c
838
u32 val;
sys/dev/pci/drm/radeon/trinity_dpm.c
843
val = (p + tp - 1) / tp;
sys/dev/pci/drm/radeon/trinity_dpm.c
845
WREG32_SMC(SMU_UVD_DPM_CNTL, val);
sys/dev/pci/drm/radeon/vce_v1_0.c
182
if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
sys/dev/pci/drm/radeon/vce_v1_0.c
190
data[0] = sign->val[i].nonce[0];
sys/dev/pci/drm/radeon/vce_v1_0.c
191
data[1] = sign->val[i].nonce[1];
sys/dev/pci/drm/radeon/vce_v1_0.c
192
data[2] = sign->val[i].nonce[2];
sys/dev/pci/drm/radeon/vce_v1_0.c
193
data[3] = sign->val[i].nonce[3];
sys/dev/pci/drm/radeon/vce_v1_0.c
200
data[0] = sign->val[i].sigval[0];
sys/dev/pci/drm/radeon/vce_v1_0.c
201
data[1] = sign->val[i].sigval[1];
sys/dev/pci/drm/radeon/vce_v1_0.c
202
data[2] = sign->val[i].sigval[2];
sys/dev/pci/drm/radeon/vce_v1_0.c
203
data[3] = sign->val[i].sigval[3];
sys/dev/pci/drm/radeon/vce_v1_0.c
205
rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
sys/dev/pci/drm/radeon/vce_v1_0.c
49
} val[8];
sys/dev/pci/emuxki.c
1851
u_int32_t val;
sys/dev/pci/emuxki.c
1868
val = EMU_A_ADCCR_LCHANENABLE;
sys/dev/pci/emuxki.c
1870
val |= EMU_A_ADCCR_RCHANENABLE;
sys/dev/pci/emuxki.c
1872
val = EMU_ADCCR_LCHANENABLE;
sys/dev/pci/emuxki.c
1874
val |= EMU_ADCCR_RCHANENABLE;
sys/dev/pci/emuxki.c
1876
val |= emuxki_voice_adc_rate(voice);
sys/dev/pci/emuxki.c
1878
emuxki_write(voice->sc, 0, EMU_ADCCR, val);
sys/dev/pci/emuxki.c
1890
val = emu_rd(sc, INTE, 4);
sys/dev/pci/emuxki.c
1891
val |= emuxki_recsrc_intrmasks[voice->dataloc.source];
sys/dev/pci/emuxki.c
1892
emu_wr(sc, INTE, val, 4);
sys/dev/pci/emuxki.c
1925
val = emu_rd(sc, INTE, 4);
sys/dev/pci/emuxki.c
1926
val &= ~emuxki_recsrc_intrmasks[voice->dataloc.source];
sys/dev/pci/emuxki.c
1927
emu_wr(sc, INTE, val, 4);
sys/dev/pci/emuxki.c
2318
emuxki_ac97_read(void *arg, u_int8_t reg, u_int16_t *val)
sys/dev/pci/emuxki.c
2324
*val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EMU_AC97DATA);
sys/dev/pci/emuxki.c
2331
emuxki_ac97_write(void *arg, u_int8_t reg, u_int16_t val)
sys/dev/pci/emuxki.c
2337
bus_space_write_2(sc->sc_iot, sc->sc_ioh, EMU_AC97DATA, val);
sys/dev/pci/envy.c
1011
int val;
sys/dev/pci/envy.c
1013
val = bus_space_read_1(sc->ccs_iot, sc->ccs_ioh, reg);
sys/dev/pci/envy.c
1016
return val;
sys/dev/pci/envy.c
1020
envy_ccs_write(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1022
bus_space_write_1(sc->ccs_iot, sc->ccs_ioh, reg, val);
sys/dev/pci/envy.c
1030
int val;
sys/dev/pci/envy.c
1032
val = bus_space_read_1(sc->mt_iot, sc->mt_ioh, reg);
sys/dev/pci/envy.c
1035
return val;
sys/dev/pci/envy.c
1039
envy_mt_write_1(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1041
bus_space_write_1(sc->mt_iot, sc->mt_ioh, reg, val);
sys/dev/pci/envy.c
1049
int val;
sys/dev/pci/envy.c
1051
val = bus_space_read_2(sc->mt_iot, sc->mt_ioh, reg);
sys/dev/pci/envy.c
1054
return val;
sys/dev/pci/envy.c
1058
envy_mt_write_2(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1060
bus_space_write_2(sc->mt_iot, sc->mt_ioh, reg, val);
sys/dev/pci/envy.c
1068
int val;
sys/dev/pci/envy.c
1070
val = bus_space_read_4(sc->mt_iot, sc->mt_ioh, reg);
sys/dev/pci/envy.c
1073
return val;
sys/dev/pci/envy.c
1077
envy_mt_write_4(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1079
bus_space_write_4(sc->mt_iot, sc->mt_ioh, reg, val);
sys/dev/pci/envy.c
1196
envy_gpio_i2c_byte_out(struct envy_softc *sc, int sda, int scl, int val)
sys/dev/pci/envy.c
1204
reg |= (val & mask) ? sda : 0;
sys/dev/pci/envy.c
1283
int val;
sys/dev/pci/envy.c
1285
val = sc->eeprom[addr];
sys/dev/pci/envy.c
1287
val |= sc->eeprom[++addr] << 8;
sys/dev/pci/envy.c
1288
val |= sc->eeprom[++addr] << 16;
sys/dev/pci/envy.c
1290
return val;
sys/dev/pci/envy.c
1671
envy_mon_getvol(struct envy_softc *sc, int idx, int ch, int *val)
sys/dev/pci/envy.c
1677
*val = 0x7f - (reg & 0x7f);
sys/dev/pci/envy.c
1681
envy_mon_setvol(struct envy_softc *sc, int idx, int ch, int val)
sys/dev/pci/envy.c
1686
reg = 0x7f - val;
sys/dev/pci/envy.c
1687
DPRINTF("%s: mon=%d/%d <- %d\n", DEVNAME(sc), reg, ch, val);
sys/dev/pci/envy.c
2353
int val, idx, ndev;
sys/dev/pci/envy.c
2373
envy_mon_getvol(sc, idx / 2, idx % 2, &val);
sys/dev/pci/envy.c
2375
ctl->un.value.level[0] = 2 * val;
sys/dev/pci/envy.c
2397
int maxsrc, val, idx, ndev;
sys/dev/pci/envy.c
2425
val = ctl->un.value.level[0] / 2;
sys/dev/pci/envy.c
2426
envy_mon_setvol(sc, idx / 2, idx % 2, val);
sys/dev/pci/envy.c
767
int val;
sys/dev/pci/envy.c
769
val = envy_codec_read(sc, 0, AK4358_ATT(idx)) & ~AK4358_ATT_EN;
sys/dev/pci/envy.c
771
ctl->un.value.level[0] = 2 * val;
sys/dev/pci/envy.c
777
int val;
sys/dev/pci/envy.c
781
val = ctl->un.value.level[0] / 2;
sys/dev/pci/envy.c
782
envy_codec_write(sc, 0, AK4358_ATT(idx), val | AK4358_ATT_EN);
sys/dev/pci/envy.c
850
int val, ndev;
sys/dev/pci/envy.c
854
val = envy_codec_read(sc, idx / 2,
sys/dev/pci/envy.c
857
ctl->un.value.level[0] = 2 * val;
sys/dev/pci/envy.c
860
val = envy_codec_read(sc, idx, AK4524_DEEMVOL);
sys/dev/pci/envy.c
861
ctl->un.ord = (val & AK4524_MUTE) ? 1 : 0;
sys/dev/pci/envy.c
868
int val, ndev;
sys/dev/pci/envy.c
874
val = ctl->un.value.level[0] / 2;
sys/dev/pci/envy.c
876
(idx % 2) + AK4524_DAC_GAIN0, val);
sys/dev/pci/envy.c
881
val = AK4524_DEEM_OFF | (ctl->un.ord ? AK4524_MUTE : 0);
sys/dev/pci/envy.c
882
envy_codec_write(sc, idx, AK4524_DEEMVOL, val);
sys/dev/pci/envy.c
911
int val;
sys/dev/pci/envy.c
913
val = envy_codec_read(sc, idx / 2, (idx % 2) + AK4524_ADC_GAIN0);
sys/dev/pci/envy.c
915
ctl->un.value.level[0] = 2 * val;
sys/dev/pci/envy.c
921
int val;
sys/dev/pci/envy.c
925
val = ctl->un.value.level[0] / 2;
sys/dev/pci/envy.c
926
envy_codec_write(sc, idx / 2, (idx % 2) + AK4524_ADC_GAIN0, val);
sys/dev/pci/envy.c
972
int val, ndev;
sys/dev/pci/envy.c
976
val = envy_codec_read(sc, 1, AK5365_ATT(idx));
sys/dev/pci/envy.c
978
ctl->un.value.level[0] = 2 * val;
sys/dev/pci/envy.c
987
int val, ndev;
sys/dev/pci/envy.c
993
val = ctl->un.value.level[0] / 2;
sys/dev/pci/envy.c
994
envy_codec_write(sc, 1, AK5365_ATT(idx), val);
sys/dev/pci/envy.c
998
val = ctl->un.ord & AK5365_SRC_MASK;
sys/dev/pci/envy.c
999
envy_codec_write(sc, 1, AK5365_SRC, val);
sys/dev/pci/esa.c
1164
int i, val;
sys/dev/pci/esa.c
1169
val = bus_space_read_1(iot, ioh, ESA_CODEC_STATUS);
sys/dev/pci/esa.c
1170
if ((val & 1) == 0)
sys/dev/pci/esa.c
1441
u_int16_t val, int index)
sys/dev/pci/esa.c
1448
val);
sys/dev/pci/esa.c
1457
u_int16_t val;
sys/dev/pci/esa.c
1466
val = esa_read_assp(sc, ESA_MEMTYPE_INTERNAL_DATA,
sys/dev/pci/esa.c
1470
val);
sys/dev/pci/esa.c
585
esa_playvals[i].addr, esa_playvals[i].val);
sys/dev/pci/esa.c
715
esa_recvals[i].addr, esa_recvals[i].val);
sys/dev/pci/eso.c
473
eso_write_ctlreg(struct eso_softc *sc, uint8_t reg, uint8_t val)
sys/dev/pci/eso.c
479
eso_write_cmd(sc, val);
sys/dev/pci/eso.c
512
eso_write_mixreg(struct eso_softc *sc, uint8_t reg, uint8_t val)
sys/dev/pci/eso.c
517
bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERDATA, val);
sys/dev/pci/eso.c
523
uint8_t val;
sys/dev/pci/eso.c
526
val = bus_space_read_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERDATA);
sys/dev/pci/eso.c
527
return (val);
sys/dev/pci/fms.c
263
fms_read_codec(void *addr, u_int8_t reg, u_int16_t *val)
sys/dev/pci/fms.c
291
*val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA);
sys/dev/pci/fms.c
296
fms_write_codec(void *addr, u_int8_t reg, u_int16_t val)
sys/dev/pci/fms.c
311
bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA, val);
sys/dev/pci/gcu.c
60
int val;
sys/dev/pci/gcu.c
62
val = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
sys/dev/pci/gcu.c
63
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
sys/dev/pci/gcu.c
68
if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_MEM_TYPE(val), 0, &sc->tag,
sys/dev/pci/glxpcib.c
551
int n, reg[7], val[7], nreg = 0, off = 0;
sys/dev/pci/glxpcib.c
560
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
562
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
566
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
568
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
572
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
574
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
578
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
580
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
584
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
586
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
590
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
592
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
596
val[nreg++] = 1 << pin;
sys/dev/pci/glxpcib.c
598
val[nreg++] = 1 << (pin + 16);
sys/dev/pci/glxpcib.c
603
val[n]);
sys/dev/pci/ichwdt.c
77
ichwdt_unlock_write(struct ichwdt_softc *sc, int reg, u_int32_t val)
sys/dev/pci/ichwdt.c
84
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/pci/if_age.c
334
age_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_age.c
344
(val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
sys/dev/pci/if_agereg.h
863
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_agereg.h
864
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_agereg.h
865
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_agereg.h
866
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alc.c
1098
uint32_t cap, ctl, val;
sys/dev/pci/if_alc.c
1102
val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
sys/dev/pci/if_alc.c
1103
val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
sys/dev/pci/if_alc.c
1104
CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
sys/dev/pci/if_alc.c
1114
val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
sys/dev/pci/if_alc.c
1115
val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
sys/dev/pci/if_alc.c
1117
val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
sys/dev/pci/if_alc.c
1118
val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
sys/dev/pci/if_alc.c
1119
CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
sys/dev/pci/if_alc.c
1146
val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
sys/dev/pci/if_alc.c
1147
val &= ~PDLL_TRNS1_D3PLLOFF_ENB;
sys/dev/pci/if_alc.c
1148
CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
sys/dev/pci/if_alc.c
1149
val = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
1152
if ((val & MASTER_WAKEN_25M) == 0 ||
sys/dev/pci/if_alc.c
1153
(val & MASTER_CLK_SEL_DIS) == 0) {
sys/dev/pci/if_alc.c
1154
val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
sys/dev/pci/if_alc.c
1155
CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
sys/dev/pci/if_alc.c
1158
if ((val & MASTER_WAKEN_25M) == 0 ||
sys/dev/pci/if_alc.c
1159
(val & MASTER_CLK_SEL_DIS) != 0) {
sys/dev/pci/if_alc.c
1160
val |= MASTER_WAKEN_25M;
sys/dev/pci/if_alc.c
1161
val &= ~MASTER_CLK_SEL_DIS;
sys/dev/pci/if_alc.c
1162
CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
sys/dev/pci/if_alc.c
246
alc_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_alc.c
254
alc_mii_writereg_816x(dev, phy, reg, val);
sys/dev/pci/if_alc.c
256
alc_mii_writereg_813x(dev, phy, reg, val);
sys/dev/pci/if_alc.c
260
alc_mii_writereg_813x(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_alc.c
267
(val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
sys/dev/pci/if_alc.c
282
alc_mii_writereg_816x(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_alc.c
293
((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
sys/dev/pci/if_alc.c
361
alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
sys/dev/pci/if_alc.c
366
val);
sys/dev/pci/if_alc.c
400
alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
sys/dev/pci/if_alc.c
412
((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) |
sys/dev/pci/if_alc.c
429
uint16_t agc, len, val;
sys/dev/pci/if_alc.c
452
val = alc_miiext_readreg(sc, MII_EXT_ANEG,
sys/dev/pci/if_alc.c
454
val |= ANEG_AFEE_10BT_100M_TH;
sys/dev/pci/if_alc.c
456
MII_EXT_ANEG_AFE, val);
sys/dev/pci/if_alc.c
460
val = alc_miiext_readreg(sc, MII_EXT_ANEG,
sys/dev/pci/if_alc.c
462
val &= ~ANEG_AFEE_10BT_100M_TH;
sys/dev/pci/if_alc.c
464
val);
sys/dev/pci/if_alc.c
473
val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
sys/dev/pci/if_alc.c
474
val &= ~DBG_MSE20DB_TH_MASK;
sys/dev/pci/if_alc.c
475
val |= (DBG_MSE20DB_TH_HI <<
sys/dev/pci/if_alc.c
477
alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
sys/dev/pci/if_alc.c
483
val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
sys/dev/pci/if_alc.c
484
val &= ~ANEG_AFEE_10BT_100M_TH;
sys/dev/pci/if_alc.c
485
alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
sys/dev/pci/if_alc.c
490
val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
sys/dev/pci/if_alc.c
491
val &= ~DBG_MSE20DB_TH_MASK;
sys/dev/pci/if_alc.c
492
val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT);
sys/dev/pci/if_alc.c
493
alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
sys/dev/pci/if_alc.c
550
uint16_t val;
sys/dev/pci/if_alc.c
578
val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
sys/dev/pci/if_alc.c
581
ALC_MII_DBG_DATA, val & 0xFF7F);
sys/dev/pci/if_alc.c
584
val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
sys/dev/pci/if_alc.c
587
ALC_MII_DBG_DATA, val | 0x0008);
sys/dev/pci/if_alc.c
629
val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
sys/dev/pci/if_alc.c
632
ALC_MII_DBG_DATA, val | 0x0080);
sys/dev/pci/if_alc.c
635
val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
sys/dev/pci/if_alc.c
638
ALC_MII_DBG_DATA, val & 0xFFF7);
sys/dev/pci/if_alc.c
864
uint32_t val;
sys/dev/pci/if_alc.c
866
val = CSR_READ_4(sc, ALC_GPHY_CFG);
sys/dev/pci/if_alc.c
867
val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
sys/dev/pci/if_alc.c
870
val |= GPHY_CFG_SEL_ANA_RESET;
sys/dev/pci/if_alc.c
872
val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN);
sys/dev/pci/if_alc.c
873
CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
sys/dev/pci/if_alc.c
875
CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
sys/dev/pci/if_alc.c
885
val = CSR_READ_4(sc, ALC_LPI_CTL);
sys/dev/pci/if_alc.c
886
val &= ~LPI_CTL_ENB;
sys/dev/pci/if_alc.c
887
CSR_WRITE_4(sc, ALC_LPI_CTL, val);
sys/dev/pci/if_alc.c
894
val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
sys/dev/pci/if_alc.c
895
val &= ~DBG_GREENCFG2_GATE_DFSE_EN;
sys/dev/pci/if_alc.c
896
alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
sys/dev/pci/if_alc.c
904
val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
sys/dev/pci/if_alc.c
905
val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT;
sys/dev/pci/if_alc.c
906
alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
sys/dev/pci/if_alc.c
908
val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
sys/dev/pci/if_alc.c
909
val |= DBG_GREENCFG2_BP_GREEN;
sys/dev/pci/if_alc.c
910
alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
sys/dev/pci/if_alc.c
912
val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
sys/dev/pci/if_alc.c
913
val |= EXT_CLDCTL5_BP_VD_HLFBIAS;
sys/dev/pci/if_alc.c
914
alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
sys/dev/pci/if_alcreg.h
1473
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_alcreg.h
1474
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alcreg.h
1475
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_alcreg.h
1476
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alcreg.h
1477
#define CSR_WRITE_1(_sc, reg, val) \
sys/dev/pci/if_alcreg.h
1478
bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_ale.c
161
ale_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_ale.c
171
(val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
sys/dev/pci/if_alereg.h
947
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_alereg.h
948
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alereg.h
949
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_alereg.h
950
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alereg.h
951
#define CSR_WRITE_1(_sc, reg, val) \
sys/dev/pci/if_alereg.h
952
bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_aq_pci.c
619
#define AQ_WRITE_REG(sc, reg, val) \
sys/dev/pci/if_aq_pci.c
620
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/pci/if_aq_pci.c
622
#define AQ_WRITE_REG_BIT(sc, reg, mask, val) \
sys/dev/pci/if_aq_pci.c
627
if ((val) != 0) \
sys/dev/pci/if_aq_pci.c
628
_v |= __SHIFTIN((val), (mask)); \
sys/dev/pci/if_aq_pci.c
636
#define AQ_WRITE64_REG(sc, reg, val) \
sys/dev/pci/if_aq_pci.c
638
AQ_WRITE_REG(sc, reg, (uint32_t)val); \
sys/dev/pci/if_aq_pci.c
639
AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \
sys/dev/pci/if_athn_pci.c
252
athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_athn_pci.c
256
bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val);
sys/dev/pci/if_bce.c
1013
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1015
if (!(val & EC_ED))
sys/dev/pci/if_bce.c
1026
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1029
if (val & RS_ERROR) {
sys/dev/pci/if_bce.c
1031
val = bus_space_read_4(sc->bce_btag,
sys/dev/pci/if_bce.c
1033
if (val & RS_DMA_IDLE)
sys/dev/pci/if_bce.c
1048
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1050
if (!(val & EC_ES))
sys/dev/pci/if_bce.c
1091
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1093
if (val & SBTML_REJ)
sys/dev/pci/if_bce.c
1102
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1104
if (!(val & 0x4))
sys/dev/pci/if_bce.c
1115
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1125
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
sys/dev/pci/if_bce.c
1129
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI);
sys/dev/pci/if_bce.c
1130
if (val & 1)
sys/dev/pci/if_bce.c
1133
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE);
sys/dev/pci/if_bce.c
1134
if (val & SBIM_ERRORBITS)
sys/dev/pci/if_bce.c
1136
val & ~SBIM_ERRORBITS);
sys/dev/pci/if_bce.c
1141
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
sys/dev/pci/if_bce.c
1147
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
sys/dev/pci/if_bce.c
1154
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL);
sys/dev/pci/if_bce.c
1155
if (!(val & BCE_DC_IP)) {
sys/dev/pci/if_bce.c
1159
} else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */
sys/dev/pci/if_bce.c
1161
val & ~BCE_DC_ER);
sys/dev/pci/if_bce.c
1205
u_int32_t val;
sys/dev/pci/if_bce.c
1217
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
1219
if (val & BCE_MIINTR)
sys/dev/pci/if_bce.c
1223
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM);
sys/dev/pci/if_bce.c
1226
"0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
sys/dev/pci/if_bce.c
1229
return (val & BCE_MICOMM_DATA);
sys/dev/pci/if_bce.c
1234
bce_mii_write(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_bce.c
1247
(MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */
sys/dev/pci/if_bce.c
1261
"= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
sys/dev/pci/if_bce.c
960
u_int32_t val;
sys/dev/pci/if_bce.c
981
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
sys/dev/pci/if_bce.c
983
if (!(val & EC_ED))
sys/dev/pci/if_bce.c
998
u_int32_t val;
sys/dev/pci/if_bge.c
1007
u_int32_t val, autopoll;
sys/dev/pci/if_bge.c
1027
val = CSR_READ_4(sc, BGE_MI_COMM);
sys/dev/pci/if_bge.c
1028
if (!(val & BGE_MICOMM_BUSY))
sys/dev/pci/if_bge.c
1035
val = 0;
sys/dev/pci/if_bge.c
1039
val = CSR_READ_4(sc, BGE_MI_COMM);
sys/dev/pci/if_bge.c
1050
if (val & BGE_MICOMM_READFAIL)
sys/dev/pci/if_bge.c
1053
return (val & 0xFFFF);
sys/dev/pci/if_bge.c
1057
bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_bge.c
1080
BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
sys/dev/pci/if_bge.c
1866
u_int32_t dmactl, rdmareg, mimode, val;
sys/dev/pci/if_bge.c
1920
val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
sys/dev/pci/if_bge.c
1928
val |= BGE_BMANMODE_NO_TX_UNDERRUN;
sys/dev/pci/if_bge.c
1929
CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
sys/dev/pci/if_bge.c
2208
val = 0x2620;
sys/dev/pci/if_bge.c
2211
val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
sys/dev/pci/if_bge.c
2213
CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
sys/dev/pci/if_bge.c
2281
val = BGE_STATBLKSZ_FULL;
sys/dev/pci/if_bge.c
2284
val = BGE_STATBLKSZ_32BYTE;
sys/dev/pci/if_bge.c
2289
CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
sys/dev/pci/if_bge.c
2302
val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
sys/dev/pci/if_bge.c
2308
val |= BGE_PORTMODE_TBI;
sys/dev/pci/if_bge.c
2310
val |= BGE_PORTMODE_GMII;
sys/dev/pci/if_bge.c
2312
val |= BGE_PORTMODE_MII;
sys/dev/pci/if_bge.c
2316
val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
sys/dev/pci/if_bge.c
2319
CSR_WRITE_4(sc, BGE_MAC_MODE, val);
sys/dev/pci/if_bge.c
2337
val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
sys/dev/pci/if_bge.c
2341
val |= BGE_WDMAMODE_STATUS_TAG_FIX;
sys/dev/pci/if_bge.c
2344
val |= BGE_WDMAMODE_BURST_ALL_DATA;
sys/dev/pci/if_bge.c
2347
CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
sys/dev/pci/if_bge.c
2350
val = BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS;
sys/dev/pci/if_bge.c
2353
val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
sys/dev/pci/if_bge.c
2358
val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
sys/dev/pci/if_bge.c
2363
val |= BGE_RDMAMODE_FIFO_LONG_BURST;
sys/dev/pci/if_bge.c
2367
val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
sys/dev/pci/if_bge.c
2373
val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
sys/dev/pci/if_bge.c
2429
CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
sys/dev/pci/if_bge.c
2434
val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
sys/dev/pci/if_bge.c
2435
if ((val & 0xFFFF) > ETHER_MAX_LEN)
sys/dev/pci/if_bge.c
2437
if (((val >> 16) & 0xFFFF) > ETHER_MAX_LEN)
sys/dev/pci/if_bge.c
2441
val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
sys/dev/pci/if_bge.c
2443
val |= BGE_RDMA_TX_LENGTH_WA_5719;
sys/dev/pci/if_bge.c
2445
val |= BGE_RDMA_TX_LENGTH_WA_5720;
sys/dev/pci/if_bge.c
2446
CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
sys/dev/pci/if_bge.c
2467
val = BGE_SDCMODE_ENABLE;
sys/dev/pci/if_bge.c
2469
val |= BGE_SDCMODE_CDELAY;
sys/dev/pci/if_bge.c
2470
CSR_WRITE_4(sc, BGE_SDC_MODE, val);
sys/dev/pci/if_bge.c
3273
u_int32_t reset, mac_mode, mac_mode_mask, val;
sys/dev/pci/if_bge.c
3349
val = CSR_READ_4(sc, BGE_VCPU_STATUS);
sys/dev/pci/if_bge.c
3351
val | BGE_VCPU_STATUS_DRV_RESET);
sys/dev/pci/if_bge.c
3352
val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
sys/dev/pci/if_bge.c
3354
val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
sys/dev/pci/if_bge.c
3401
val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
sys/dev/pci/if_bge.c
3404
val |= BGE_PCISTATE_RETRY_SAME_DMA;
sys/dev/pci/if_bge.c
3406
val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
sys/dev/pci/if_bge.c
3409
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, val);
sys/dev/pci/if_bge.c
3417
val = pci_conf_read(pa->pa_pc, pa->pa_tag,
sys/dev/pci/if_bge.c
3421
val | PCI_MSI_MC_MSIE);
sys/dev/pci/if_bge.c
3422
val = CSR_READ_4(sc, BGE_MSI_MODE);
sys/dev/pci/if_bge.c
3424
val | BGE_MSIMODE_ENABLE);
sys/dev/pci/if_bge.c
3426
val = CSR_READ_4(sc, BGE_MARB_MODE);
sys/dev/pci/if_bge.c
3427
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
sys/dev/pci/if_bge.c
3434
val = CSR_READ_4(sc, BGE_MAC_MODE);
sys/dev/pci/if_bge.c
3435
val = (val & ~mac_mode_mask) | mac_mode;
sys/dev/pci/if_bge.c
3436
CSR_WRITE_4(sc, BGE_MAC_MODE, val);
sys/dev/pci/if_bge.c
3443
val = CSR_READ_4(sc, BGE_VCPU_STATUS);
sys/dev/pci/if_bge.c
3444
if (val & BGE_VCPU_STATUS_INIT_DONE)
sys/dev/pci/if_bge.c
3459
val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
sys/dev/pci/if_bge.c
3460
if (val == ~BGE_MAGIC_NUMBER)
sys/dev/pci/if_bge.c
3481
val = CSR_READ_4(sc, BGE_SERDES_CFG);
sys/dev/pci/if_bge.c
3482
val = (val & ~0xFFF) | 0x880;
sys/dev/pci/if_bge.c
3483
CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
sys/dev/pci/if_bge.c
3491
val = CSR_READ_4(sc, 0x7c00);
sys/dev/pci/if_bge.c
3492
CSR_WRITE_4(sc, 0x7c00, val | (1<<25));
sys/dev/pci/if_bge.c
3858
u_int32_t val;
sys/dev/pci/if_bge.c
3909
val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
sys/dev/pci/if_bge.c
3911
val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
sys/dev/pci/if_bge.c
3913
val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
sys/dev/pci/if_bge.c
3914
CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
sys/dev/pci/if_bge.c
503
u_int32_t val;
sys/dev/pci/if_bge.c
510
val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA);
sys/dev/pci/if_bge.c
512
return (val);
sys/dev/pci/if_bge.c
516
bge_writemem_ind(struct bge_softc *sc, int off, int val)
sys/dev/pci/if_bge.c
525
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
sys/dev/pci/if_bge.c
530
bge_writereg_ind(struct bge_softc *sc, int off, int val)
sys/dev/pci/if_bge.c
535
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
sys/dev/pci/if_bge.c
539
bge_writembx(struct bge_softc *sc, int off, int val)
sys/dev/pci/if_bge.c
544
CSR_WRITE_4(sc, off, val);
sys/dev/pci/if_bgereg.h
2276
#define BGE_MEMWIN_READ(pc, tag, x, val) \
sys/dev/pci/if_bgereg.h
2280
val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0x7FFF)); \
sys/dev/pci/if_bgereg.h
2283
#define BGE_MEMWIN_WRITE(pc, tag, x, val) \
sys/dev/pci/if_bgereg.h
2287
CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0x7FFF), val); \
sys/dev/pci/if_bgereg.h
2319
#define RCB_WRITE_4(sc, rcb, offset, val) \
sys/dev/pci/if_bgereg.h
2321
rcb + offsetof(struct bge_rcb, offset), val)
sys/dev/pci/if_bgereg.h
2323
#define RCB_WRITE_2(sc, rcb, offset, val) \
sys/dev/pci/if_bgereg.h
2325
rcb + offsetof(struct bge_rcb, offset), val)
sys/dev/pci/if_bgereg.h
2733
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_bgereg.h
2734
bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
sys/dev/pci/if_bgereg.h
2745
#define APE_WRITE_4(sc, reg, val) \
sys/dev/pci/if_bgereg.h
2746
bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val)
sys/dev/pci/if_bnx.c
1005
u_int32_t val;
sys/dev/pci/if_bnx.c
1006
val = pci_conf_read(pa->pa_pc, pa->pa_tag,
sys/dev/pci/if_bnx.c
1009
"val = 0x%08X\n", __FUNCTION__, offset, val);
sys/dev/pci/if_bnx.c
1010
return (val);
sys/dev/pci/if_bnx.c
1028
bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val)
sys/dev/pci/if_bnx.c
1033
__FUNCTION__, offset, val);
sys/dev/pci/if_bnx.c
1037
pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val);
sys/dev/pci/if_bnx.c
1054
u_int32_t val, retry_cnt = 5;
sys/dev/pci/if_bnx.c
1062
val = REG_RD(sc, BNX_CTX_CTX_CTRL);
sys/dev/pci/if_bnx.c
1063
if ((val & BNX_CTX_CTX_CTRL_WRITE_REQ) == 0)
sys/dev/pci/if_bnx.c
1069
if (val & BNX_CTX_CTX_CTRL_WRITE_REQ)
sys/dev/pci/if_bnx.c
1093
u_int32_t val;
sys/dev/pci/if_bnx.c
1107
val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
sys/dev/pci/if_bnx.c
1108
val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
sys/dev/pci/if_bnx.c
1110
REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
sys/dev/pci/if_bnx.c
1116
val = BNX_MIPHY(phy) | BNX_MIREG(reg) |
sys/dev/pci/if_bnx.c
1119
REG_WR(sc, BNX_EMAC_MDIO_COMM, val);
sys/dev/pci/if_bnx.c
1124
val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
sys/dev/pci/if_bnx.c
1125
if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) {
sys/dev/pci/if_bnx.c
1128
val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
sys/dev/pci/if_bnx.c
1129
val &= BNX_EMAC_MDIO_COMM_DATA;
sys/dev/pci/if_bnx.c
1135
if (val & BNX_EMAC_MDIO_COMM_START_BUSY) {
sys/dev/pci/if_bnx.c
1138
val = 0x0;
sys/dev/pci/if_bnx.c
1140
val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
sys/dev/pci/if_bnx.c
1144
(u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
sys/dev/pci/if_bnx.c
1147
val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
sys/dev/pci/if_bnx.c
1148
val |= BNX_EMAC_MDIO_MODE_AUTO_POLL;
sys/dev/pci/if_bnx.c
1150
REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
sys/dev/pci/if_bnx.c
1156
return (val & 0xffff);
sys/dev/pci/if_bnx.c
1168
bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_bnx.c
1176
phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
sys/dev/pci/if_bnx.c
1198
val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
sys/dev/pci/if_bnx.c
1244
int val;
sys/dev/pci/if_bnx.c
1246
val = REG_RD(sc, BNX_EMAC_MODE);
sys/dev/pci/if_bnx.c
1247
val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX |
sys/dev/pci/if_bnx.c
1267
val |= BNX_EMAC_MODE_PORT_MII_10;
sys/dev/pci/if_bnx.c
1273
val |= BNX_EMAC_MODE_PORT_MII;
sys/dev/pci/if_bnx.c
1277
val |= BNX_EMAC_MODE_25G;
sys/dev/pci/if_bnx.c
1282
val |= BNX_EMAC_MODE_PORT_GMII;
sys/dev/pci/if_bnx.c
1285
val |= BNX_EMAC_MODE_PORT_GMII;
sys/dev/pci/if_bnx.c
1294
val |= BNX_EMAC_MODE_HALF_DUPLEX;
sys/dev/pci/if_bnx.c
1298
REG_WR(sc, BNX_EMAC_MODE, val);
sys/dev/pci/if_bnx.c
1342
u_int32_t val;
sys/dev/pci/if_bnx.c
1350
val = REG_RD(sc, BNX_NVM_SW_ARB);
sys/dev/pci/if_bnx.c
1351
if (val & BNX_NVM_SW_ARB_ARB_ARB2)
sys/dev/pci/if_bnx.c
1379
u_int32_t val;
sys/dev/pci/if_bnx.c
1387
val = REG_RD(sc, BNX_NVM_SW_ARB);
sys/dev/pci/if_bnx.c
1388
if (!(val & BNX_NVM_SW_ARB_ARB_ARB2))
sys/dev/pci/if_bnx.c
1414
u_int32_t val;
sys/dev/pci/if_bnx.c
1418
val = REG_RD(sc, BNX_MISC_CFG);
sys/dev/pci/if_bnx.c
1419
REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI);
sys/dev/pci/if_bnx.c
1431
val = REG_RD(sc, BNX_NVM_COMMAND);
sys/dev/pci/if_bnx.c
1432
if (val & BNX_NVM_COMMAND_DONE)
sys/dev/pci/if_bnx.c
1457
u_int32_t val;
sys/dev/pci/if_bnx.c
1461
val = REG_RD(sc, BNX_MISC_CFG);
sys/dev/pci/if_bnx.c
1462
REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN);
sys/dev/pci/if_bnx.c
1478
u_int32_t val;
sys/dev/pci/if_bnx.c
1482
val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
sys/dev/pci/if_bnx.c
1485
val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN);
sys/dev/pci/if_bnx.c
1499
u_int32_t val;
sys/dev/pci/if_bnx.c
1503
val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
sys/dev/pci/if_bnx.c
1507
val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN));
sys/dev/pci/if_bnx.c
1546
u_int32_t val;
sys/dev/pci/if_bnx.c
1550
val = REG_RD(sc, BNX_NVM_COMMAND);
sys/dev/pci/if_bnx.c
1551
if (val & BNX_NVM_COMMAND_DONE)
sys/dev/pci/if_bnx.c
1600
u_int32_t val;
sys/dev/pci/if_bnx.c
1604
val = REG_RD(sc, BNX_NVM_COMMAND);
sys/dev/pci/if_bnx.c
1605
if (val & BNX_NVM_COMMAND_DONE) {
sys/dev/pci/if_bnx.c
1606
val = REG_RD(sc, BNX_NVM_READ);
sys/dev/pci/if_bnx.c
1608
val = bnx_be32toh(val);
sys/dev/pci/if_bnx.c
1609
memcpy(ret_val, &val, 4);
sys/dev/pci/if_bnx.c
1636
bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val,
sys/dev/pci/if_bnx.c
1657
memcpy(&val32, val, 4);
sys/dev/pci/if_bnx.c
1692
u_int32_t val;
sys/dev/pci/if_bnx.c
1704
val = REG_RD(sc, BNX_NVM_CFG1);
sys/dev/pci/if_bnx.c
1715
if (val & 0x40000000) {
sys/dev/pci/if_bnx.c
1723
if ((val & FLASH_BACKUP_STRAP_MASK) ==
sys/dev/pci/if_bnx.c
1736
if (val & (1 << 23))
sys/dev/pci/if_bnx.c
1745
if ((val & mask) == (flash->strapping & mask)) {
sys/dev/pci/if_bnx.c
1777
val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2);
sys/dev/pci/if_bnx.c
1778
val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK;
sys/dev/pci/if_bnx.c
1779
if (val)
sys/dev/pci/if_bnx.c
1780
sc->bnx_flash_size = val;
sys/dev/pci/if_bnx.c
2167
u_int32_t val;
sys/dev/pci/if_bnx.c
2172
u_int32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL);
sys/dev/pci/if_bnx.c
2173
u_int32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID;
sys/dev/pci/if_bnx.c
2191
if (val & BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
sys/dev/pci/if_bnx.c
2192
strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
sys/dev/pci/if_bnx.c
2194
strap = (val & BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP)
sys/dev/pci/if_bnx.c
2241
val = REG_RD_IND(sc, sc->bnx_shmem_base +
sys/dev/pci/if_bnx.c
2243
if (val & BNX_SHARED_HW_CFG_PHY_2_5G) {
sys/dev/pci/if_bnx.c
2709
u_int32_t val;
sys/dev/pci/if_bnx.c
2730
val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB);
sys/dev/pci/if_bnx.c
2731
if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ))
sys/dev/pci/if_bnx.c
2737
if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) &&
sys/dev/pci/if_bnx.c
2766
u_int32_t val;
sys/dev/pci/if_bnx.c
2781
val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR;
sys/dev/pci/if_bnx.c
2782
REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val);
sys/dev/pci/if_bnx.c
2784
val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR;
sys/dev/pci/if_bnx.c
2785
REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val);
sys/dev/pci/if_bnx.c
2810
u_int32_t val;
sys/dev/pci/if_bnx.c
2813
val = REG_RD_IND(sc, cpu_reg->mode);
sys/dev/pci/if_bnx.c
2814
val |= cpu_reg->mode_value_halt;
sys/dev/pci/if_bnx.c
2815
REG_WR_IND(sc, cpu_reg->mode, val);
sys/dev/pci/if_bnx.c
2869
val = REG_RD_IND(sc, cpu_reg->mode);
sys/dev/pci/if_bnx.c
2870
val &= ~cpu_reg->mode_value_halt;
sys/dev/pci/if_bnx.c
2872
REG_WR_IND(sc, cpu_reg->mode, val);
sys/dev/pci/if_bnx.c
3108
u_int32_t val;
sys/dev/pci/if_bnx.c
3115
val = BNX_CTX_COMMAND_ENABLED | BNX_CTX_COMMAND_MEM_INIT
sys/dev/pci/if_bnx.c
3117
val |= (BCM_PAGE_BITS - 8) << 16;
sys/dev/pci/if_bnx.c
3118
REG_WR(sc, BNX_CTX_COMMAND, val);
sys/dev/pci/if_bnx.c
3122
val = REG_RD(sc, BNX_CTX_COMMAND);
sys/dev/pci/if_bnx.c
3123
if (!(val & BNX_CTX_COMMAND_MEM_INIT))
sys/dev/pci/if_bnx.c
3134
val = (u_int32_t)(sc->ctx_segs[i].ds_addr);
sys/dev/pci/if_bnx.c
3135
REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val |
sys/dev/pci/if_bnx.c
3137
val = (u_int32_t)
sys/dev/pci/if_bnx.c
3139
REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val);
sys/dev/pci/if_bnx.c
3145
val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL);
sys/dev/pci/if_bnx.c
3146
if ((val & BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
sys/dev/pci/if_bnx.c
3228
u_int32_t val;
sys/dev/pci/if_bnx.c
3234
val = (mac_addr[0] << 8) | mac_addr[1];
sys/dev/pci/if_bnx.c
3236
REG_WR(sc, BNX_EMAC_MAC_MATCH0, val);
sys/dev/pci/if_bnx.c
3238
val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
sys/dev/pci/if_bnx.c
3241
REG_WR(sc, BNX_EMAC_MAC_MATCH1, val);
sys/dev/pci/if_bnx.c
3313
u_int32_t val;
sys/dev/pci/if_bnx.c
3324
val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
sys/dev/pci/if_bnx.c
3329
val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL);
sys/dev/pci/if_bnx.c
3330
val &= ~BNX_MISC_NEW_CORE_CTL_DMA_ENABLE;
sys/dev/pci/if_bnx.c
3331
REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);
sys/dev/pci/if_bnx.c
3347
val = REG_RD(sc, BNX_MISC_ID);
sys/dev/pci/if_bnx.c
3355
val = BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
sys/dev/pci/if_bnx.c
3359
val);
sys/dev/pci/if_bnx.c
3361
val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
sys/dev/pci/if_bnx.c
3364
REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val);
sys/dev/pci/if_bnx.c
3368
val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG);
sys/dev/pci/if_bnx.c
3369
if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
sys/dev/pci/if_bnx.c
3377
if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ |
sys/dev/pci/if_bnx.c
3387
val = REG_RD(sc, BNX_PCI_SWAP_DIAG0);
sys/dev/pci/if_bnx.c
3388
if (val != 0x01020304) {
sys/dev/pci/if_bnx.c
3414
u_int32_t val;
sys/dev/pci/if_bnx.c
3424
val = BNX_DMA_CONFIG_DATA_BYTE_SWAP |
sys/dev/pci/if_bnx.c
3433
val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY;
sys/dev/pci/if_bnx.c
3436
val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP;
sys/dev/pci/if_bnx.c
3446
val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA;
sys/dev/pci/if_bnx.c
3448
REG_WR(sc, BNX_DMA_CONFIG, val);
sys/dev/pci/if_bnx.c
3453
val = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD);
sys/dev/pci/if_bnx.c
3455
val & ~0x20000);
sys/dev/pci/if_bnx.c
3478
val = REG_RD(sc, BNX_MQ_CONFIG);
sys/dev/pci/if_bnx.c
3479
val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE;
sys/dev/pci/if_bnx.c
3480
val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
sys/dev/pci/if_bnx.c
3484
val |= BNX_MQ_CONFIG_BIN_MQ_MODE;
sys/dev/pci/if_bnx.c
3486
val |= BNX_MQ_CONFIG_HALT_DIS;
sys/dev/pci/if_bnx.c
3489
REG_WR(sc, BNX_MQ_CONFIG, val);
sys/dev/pci/if_bnx.c
3491
val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
sys/dev/pci/if_bnx.c
3492
REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);
sys/dev/pci/if_bnx.c
3493
REG_WR(sc, BNX_MQ_KNL_WIND_END, val);
sys/dev/pci/if_bnx.c
3495
val = (BCM_PAGE_BITS - 8) << 24;
sys/dev/pci/if_bnx.c
3496
REG_WR(sc, BNX_RV2P_CONFIG, val);
sys/dev/pci/if_bnx.c
3499
val = REG_RD(sc, BNX_TBDR_CONFIG);
sys/dev/pci/if_bnx.c
3500
val &= ~BNX_TBDR_CONFIG_PAGE_SIZE;
sys/dev/pci/if_bnx.c
3501
val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
sys/dev/pci/if_bnx.c
3502
REG_WR(sc, BNX_TBDR_CONFIG, val);
sys/dev/pci/if_bnx.c
3524
u_int32_t reg, val;
sys/dev/pci/if_bnx.c
3533
val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
sys/dev/pci/if_bnx.c
3535
REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val);
sys/dev/pci/if_bnx.c
3611
val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL);
sys/dev/pci/if_bnx.c
3612
val |= BNX_MISC_NEW_CORE_CTL_DMA_ENABLE;
sys/dev/pci/if_bnx.c
3613
REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);
sys/dev/pci/if_bnx.c
3747
u_int32_t val;
sys/dev/pci/if_bnx.c
3752
val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2;
sys/dev/pci/if_bnx.c
3753
CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE_XI, val);
sys/dev/pci/if_bnx.c
3754
val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
sys/dev/pci/if_bnx.c
3755
CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE_XI, val);
sys/dev/pci/if_bnx.c
3758
val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32);
sys/dev/pci/if_bnx.c
3760
BNX_L2CTX_TBDR_BHADDR_HI_XI, val);
sys/dev/pci/if_bnx.c
3761
val = (u_int32_t)(sc->tx_bd_chain_paddr[0]);
sys/dev/pci/if_bnx.c
3763
BNX_L2CTX_TBDR_BHADDR_LO_XI, val);
sys/dev/pci/if_bnx.c
3766
val = BNX_L2CTX_TYPE_TYPE_L2 | BNX_L2CTX_TYPE_SIZE_L2;
sys/dev/pci/if_bnx.c
3767
CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val);
sys/dev/pci/if_bnx.c
3768
val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
sys/dev/pci/if_bnx.c
3769
CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val);
sys/dev/pci/if_bnx.c
3772
val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32);
sys/dev/pci/if_bnx.c
3773
CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val);
sys/dev/pci/if_bnx.c
3774
val = (u_int32_t)(sc->tx_bd_chain_paddr[0]);
sys/dev/pci/if_bnx.c
3775
CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val);
sys/dev/pci/if_bnx.c
3894
u_int32_t val;
sys/dev/pci/if_bnx.c
3897
val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
sys/dev/pci/if_bnx.c
3921
val |= (lo_water << BNX_L2CTX_RX_LO_WATER_MARK_SHIFT) |
sys/dev/pci/if_bnx.c
3925
CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val);
sys/dev/pci/if_bnx.c
3929
val = REG_RD(sc, BNX_MQ_MAP_L2_5);
sys/dev/pci/if_bnx.c
3930
REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM);
sys/dev/pci/if_bnx.c
3934
val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32);
sys/dev/pci/if_bnx.c
3935
CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val);
sys/dev/pci/if_bnx.c
3936
val = (u_int32_t)(sc->rx_bd_chain_paddr[0]);
sys/dev/pci/if_bnx.c
3937
CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val);
sys/dev/pci/if_bnx.c
4608
u_int32_t val;
sys/dev/pci/if_bnx.c
4616
val = REG_RD(sc, BNX_HC_COMMAND);
sys/dev/pci/if_bnx.c
4617
REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW);
sys/dev/pci/if_bnx.c
4710
u_int32_t val;
sys/dev/pci/if_bnx.c
4719
val = (BCM_PAGE_BITS - 8) << 24;
sys/dev/pci/if_bnx.c
4720
REG_WR(sc, BNX_RV2P_CONFIG, val);
sys/dev/pci/if_bnx.c
647
u_int32_t val;
sys/dev/pci/if_bnx.c
687
val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE);
sys/dev/pci/if_bnx.c
688
if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG)
sys/dev/pci/if_bnx.c
701
val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
sys/dev/pci/if_bnx.c
702
if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) {
sys/dev/pci/if_bnx.c
735
} else if (val & BNX_PCICFG_MISC_STATUS_M66EN)
sys/dev/pci/if_bnx.c
740
if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET)
sys/dev/pci/if_bnxreg.h
676
#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
sys/dev/pci/if_bnxreg.h
677
#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
sys/dev/pci/if_bnxreg.h
680
#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val)
sys/dev/pci/if_bnxreg.h
681
#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val)
sys/dev/pci/if_bnxt.c
2383
uint64_t val, hi;
sys/dev/pci/if_bnxt.c
2385
val = ring->cons & DBC_DBC_INDEX_MASK;
sys/dev/pci/if_bnxt.c
2393
val |= (hi << 32);
sys/dev/pci/if_bnxt.c
2398
sc->sc_legacy_db_size, htole64(val));
sys/dev/pci/if_bnxt.c
2402
uint32_t val = CMPL_DOORBELL_KEY_CMPL;
sys/dev/pci/if_bnxt.c
2404
val |= CMPL_DOORBELL_MASK;
sys/dev/pci/if_bnxt.c
2411
ring->ring.doorbell, htole32(val));
sys/dev/pci/if_bnxt.c
2420
uint64_t val, hi;
sys/dev/pci/if_bnxt.c
2422
val = index & DBC_DBC_INDEX_MASK;
sys/dev/pci/if_bnxt.c
2430
val |= (hi << 32);
sys/dev/pci/if_bnxt.c
2435
sc->sc_legacy_db_size, htole64(val));
sys/dev/pci/if_bnxt.c
2439
uint32_t val = CMPL_DOORBELL_KEY_CMPL |
sys/dev/pci/if_bnxt.c
2442
val |= CMPL_DOORBELL_MASK;
sys/dev/pci/if_bnxt.c
2446
htole32(val));
sys/dev/pci/if_bnxt.c
2457
uint64_t val, hi;
sys/dev/pci/if_bnxt.c
2459
val = index & DBC_DBC_INDEX_MASK;
sys/dev/pci/if_bnxt.c
2464
val |= (hi << 32);
sys/dev/pci/if_bnxt.c
2469
sc->sc_legacy_db_size, htole64(val));
sys/dev/pci/if_bnxt.c
2473
uint32_t val = CMPL_DOORBELL_KEY_CMPL |
sys/dev/pci/if_bnxt.c
2478
htole32(val));
sys/dev/pci/if_bnxt.c
2488
uint64_t val, hi;
sys/dev/pci/if_bnxt.c
2490
val = index & DBC_DBC_INDEX_MASK;
sys/dev/pci/if_bnxt.c
2494
val |= (hi << 32);
sys/dev/pci/if_bnxt.c
2499
sc->sc_legacy_db_size, htole64(val));
sys/dev/pci/if_bnxt.c
2503
uint32_t val = RX_DOORBELL_KEY_RX | index;
sys/dev/pci/if_bnxt.c
2507
htole32(val));
sys/dev/pci/if_bnxt.c
2513
htole32(val));
sys/dev/pci/if_bnxt.c
2521
uint64_t val, hi;
sys/dev/pci/if_bnxt.c
2523
val = index & DBC_DBC_INDEX_MASK;
sys/dev/pci/if_bnxt.c
2526
val |= (hi << 32);
sys/dev/pci/if_bnxt.c
2531
sc->sc_legacy_db_size, htole64(val));
sys/dev/pci/if_bnxt.c
2535
uint32_t val = TX_DOORBELL_KEY_TX | index;
sys/dev/pci/if_bnxt.c
2539
htole32(val));
sys/dev/pci/if_bnxt.c
2545
htole32(val));
sys/dev/pci/if_bwfm_pci.c
1835
bwfm_pci_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)
sys/dev/pci/if_bwfm_pci.c
1843
bus_space_write_4(sc->sc_reg_iot, sc->sc_reg_ioh, offset, val);
sys/dev/pci/if_bwi_pci.c
234
bwi_pci_conf_write(void *self, uint32_t reg, uint32_t val)
sys/dev/pci/if_bwi_pci.c
238
pci_conf_write(psc->psc_pc, psc->psc_pcitag, reg, val);
sys/dev/pci/if_cas.c
1460
cas_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_cas.c
1471
phy, reg, val);
sys/dev/pci/if_cas.c
1478
(val & CAS_MIF_FRAME_DATA);
sys/dev/pci/if_cas.c
1579
cas_pcs_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_cas.c
1589
phy, reg, val);
sys/dev/pci/if_cas.c
1600
reset = (val & CAS_MII_CONTROL_RESET);
sys/dev/pci/if_cas.c
1616
bus_space_write_4(t, pcs, reg, val);
sys/dev/pci/if_devar.h
32
#define TULIP_CSR_WRITE(sc, csr, val) \
sys/dev/pci/if_devar.h
33
bus_space_write_4((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr, (val))
sys/dev/pci/if_devar.h
37
#define TULIP_CSR_WRITEBYTE(sc, csr, val) \
sys/dev/pci/if_devar.h
38
bus_space_write_1((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr, (val))
sys/dev/pci/if_em.c
1706
int val, rid;
sys/dev/pci/if_em.c
1710
val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA);
sys/dev/pci/if_em.c
1711
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
sys/dev/pci/if_em.c
1715
if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
sys/dev/pci/if_em.c
1731
val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid);
sys/dev/pci/if_em.c
1732
if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) {
sys/dev/pci/if_em.c
1737
if (PCI_MAPREG_MEM_TYPE(val) ==
sys/dev/pci/if_em.c
1764
val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH);
sys/dev/pci/if_em.c
1765
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
sys/dev/pci/if_em.c
1770
if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0,
sys/dev/pci/if_em.c
1806
pcireg_t val;
sys/dev/pci/if_em.c
1809
sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) {
sys/dev/pci/if_em.c
3321
pcireg_t val;
sys/dev/pci/if_em.c
3323
val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
sys/dev/pci/if_em.c
3325
val &= 0x0000ffff;
sys/dev/pci/if_em.c
3326
val |= (*value << 16);
sys/dev/pci/if_em.c
3328
val &= 0xffff0000;
sys/dev/pci/if_em.c
3329
val |= *value;
sys/dev/pci/if_em.c
3331
pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val);
sys/dev/pci/if_em.c
3338
pcireg_t val;
sys/dev/pci/if_em.c
3340
val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
sys/dev/pci/if_em.c
3342
*value = (val >> 16) & 0xffff;
sys/dev/pci/if_em.c
3344
*value = val & 0xffff;
sys/dev/pci/if_em.c
3434
pcireg_t val;
sys/dev/pci/if_em.c
3451
val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag,
sys/dev/pci/if_em.c
3457
val &= ~PCI_PCIE_LCSR_ASPM_L1;
sys/dev/pci/if_em.c
3461
val &= ~(PCI_PCIE_LCSR_ASPM_L0S |
sys/dev/pci/if_em.c
3469
offset + PCI_PCIE_LCSR, val);
sys/dev/pci/if_em_hw.h
445
#define E1000_WRITE_REG_IO(a, reg, val) \
sys/dev/pci/if_em_hw.h
446
em_write_reg_io((a), E1000_##reg, val)
sys/dev/pci/if_em_soc.c
109
data = val;
sys/dev/pci/if_em_soc.c
97
gcu_miibus_writereg(struct em_hw *hw, int phy, int reg, int val)
sys/dev/pci/if_et.c
1452
uint32_t val;
sys/dev/pci/if_et.c
1463
val = __SHIFTIN(56, ET_IPG_NONB2B_1) |
sys/dev/pci/if_et.c
1467
CSR_WRITE_4(sc, ET_IPG, val);
sys/dev/pci/if_et.c
1472
val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
sys/dev/pci/if_et.c
1476
CSR_WRITE_4(sc, ET_MAC_HDX, val);
sys/dev/pci/if_et.c
1487
val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24);
sys/dev/pci/if_et.c
1488
CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
sys/dev/pci/if_et.c
1489
val = (eaddr[0] << 16) | (eaddr[1] << 24);
sys/dev/pci/if_et.c
1490
CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
sys/dev/pci/if_et.c
1504
uint32_t val;
sys/dev/pci/if_et.c
1521
val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5];
sys/dev/pci/if_et.c
1522
CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
sys/dev/pci/if_et.c
1523
val = (eaddr[0] << 8) | eaddr[1];
sys/dev/pci/if_et.c
1524
CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
sys/dev/pci/if_et.c
1544
val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) |
sys/dev/pci/if_et.c
1547
val = 0;
sys/dev/pci/if_et.c
1549
CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
sys/dev/pci/if_et.c
1567
val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;
sys/dev/pci/if_et.c
1568
CSR_WRITE_4(sc, ET_PKTFILT, val);
sys/dev/pci/if_et.c
1597
uint32_t val = 0;
sys/dev/pci/if_et.c
1599
val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,
sys/dev/pci/if_et.c
1602
val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,
sys/dev/pci/if_et.c
1606
CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
sys/dev/pci/if_et.c
1628
uint32_t val;
sys/dev/pci/if_et.c
1631
val = CSR_READ_4(sc, ET_MAC_CFG1);
sys/dev/pci/if_et.c
1632
val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
sys/dev/pci/if_et.c
1633
val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
sys/dev/pci/if_et.c
1635
CSR_WRITE_4(sc, ET_MAC_CFG1, val);
sys/dev/pci/if_et.c
1642
val = CSR_READ_4(sc, ET_MAC_CFG1);
sys/dev/pci/if_et.c
1643
if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
sys/dev/pci/if_et.c
309
uint32_t val;
sys/dev/pci/if_et.c
315
val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
sys/dev/pci/if_et.c
317
CSR_WRITE_4(sc, ET_MII_ADDR, val);
sys/dev/pci/if_et.c
325
val = CSR_READ_4(sc, ET_MII_IND);
sys/dev/pci/if_et.c
326
if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0)
sys/dev/pci/if_et.c
339
val = CSR_READ_4(sc, ET_MII_STAT);
sys/dev/pci/if_et.c
340
ret = __SHIFTOUT(val, ET_MII_STAT_VALUE);
sys/dev/pci/if_et.c
352
uint32_t val;
sys/dev/pci/if_et.c
358
val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
sys/dev/pci/if_et.c
360
CSR_WRITE_4(sc, ET_MII_ADDR, val);
sys/dev/pci/if_et.c
368
val = CSR_READ_4(sc, ET_MII_IND);
sys/dev/pci/if_et.c
369
if ((val & ET_MII_IND_BUSY) == 0)
sys/dev/pci/if_et.c
474
uint32_t val; //, max_plsz;
sys/dev/pci/if_et.c
482
val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC);
sys/dev/pci/if_et.c
484
if (val & ET_PCIM_EEPROM_STATUS_ERROR) {
sys/dev/pci/if_et.c
486
sc->sc_dev.dv_xname, val);
sys/dev/pci/if_et.c
496
val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_DEVICE_CAPS);
sys/dev/pci/if_et.c
497
max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ;
sys/dev/pci/if_et.c
529
val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2);
sys/dev/pci/if_et.c
531
val << 24);
sys/dev/pci/if_et.c
536
val = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_et.c
538
val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ;
sys/dev/pci/if_et.c
539
val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
sys/dev/pci/if_et.c
541
val << 16);
sys/dev/pci/if_et.c
875
uint32_t val;
sys/dev/pci/if_et.c
893
val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
sys/dev/pci/if_et.c
897
CSR_WRITE_4(sc, ET_MAC_HDX, val);
sys/dev/pci/if_etreg.h
352
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_etreg.h
353
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_ice.c
11138
uint32_t val;
sys/dev/pci/if_ice.c
11142
val = (QINT_RQCTL_CAUSE_ENA_M |
sys/dev/pci/if_ice.c
11145
ICE_WRITE(hw, QINT_RQCTL(rxqid), val);
sys/dev/pci/if_ice.c
11182
uint32_t val;
sys/dev/pci/if_ice.c
11186
val = (QINT_TQCTL_CAUSE_ENA_M |
sys/dev/pci/if_ice.c
11189
ICE_WRITE(hw, QINT_TQCTL(txqid), val);
sys/dev/pci/if_ice.c
1151
uint32_t val = 0;
sys/dev/pci/if_ice.c
1158
val = GLGEN_RTRIG_CORER_M;
sys/dev/pci/if_ice.c
1162
val = GLGEN_RTRIG_GLOBR_M;
sys/dev/pci/if_ice.c
1168
val |= ICE_READ(hw, GLGEN_RTRIG);
sys/dev/pci/if_ice.c
1169
ICE_WRITE(hw, GLGEN_RTRIG, val);
sys/dev/pci/if_ice.c
13345
uint32_t reg, val;
sys/dev/pci/if_ice.c
13351
val = ICE_READ(hw, QINT_RQCTL(reg));
sys/dev/pci/if_ice.c
13352
val &= ~QINT_RQCTL_CAUSE_ENA_M;
sys/dev/pci/if_ice.c
13353
ICE_WRITE(hw, QINT_RQCTL(reg), val);
sys/dev/pci/if_ice.c
13400
uint32_t reg, val;
sys/dev/pci/if_ice.c
13406
val = ICE_READ(hw, QINT_TQCTL(reg));
sys/dev/pci/if_ice.c
13407
val &= ~QINT_TQCTL_CAUSE_ENA_M;
sys/dev/pci/if_ice.c
13408
ICE_WRITE(hw, QINT_TQCTL(reg), val);
sys/dev/pci/if_ice.c
16042
ice_add_tunnel_hint(struct ice_hw *hw, char *label_name, uint16_t val)
sys/dev/pci/if_ice.c
16063
hw->tnl.tbl[hw->tnl.count].boost_addr = val;
sys/dev/pci/if_ice.c
16087
uint16_t val;
sys/dev/pci/if_ice.c
16097
&val);
sys/dev/pci/if_ice.c
16102
ice_add_tunnel_hint(hw, label_name, val);
sys/dev/pci/if_ice.c
16104
label_name = ice_enum_labels(NULL, 0, &state, &val);
sys/dev/pci/if_ice.c
18416
ice_gen_key_word(uint8_t val, uint8_t valid, uint8_t dont_care,
sys/dev/pci/if_ice.c
18443
} else if (val & 0x01) { /* exact 1 match */
sys/dev/pci/if_ice.c
18454
val >>= 1;
sys/dev/pci/if_ice.c
18519
ice_set_key(uint8_t *key, uint16_t size, uint8_t *val, uint8_t *upd,
sys/dev/pci/if_ice.c
18542
if (ice_gen_key_word(val[i], upd ? upd[i] : 0xff,
sys/dev/pci/if_ice.c
1920
uint32_t val = 0;
sys/dev/pci/if_ice.c
1954
val = ICE_READ(hw, cq->sq.head);
sys/dev/pci/if_ice.c
1955
if (val >= cq->num_sq_entries) {
sys/dev/pci/if_ice.c
1957
"head overrun at %d in the Control Send Queue ring\n", val);
sys/dev/pci/if_ice.c
202
#define ICE_WRITE(hw, reg, val) \
sys/dev/pci/if_ice.c
203
bus_space_write_4((hw)->hw_sc->sc_st, (hw)->hw_sc->sc_sh, (reg), (val))
sys/dev/pci/if_ice.c
205
#define ICE_WRITE_RAW(hw, reg, val) \
sys/dev/pci/if_ice.c
207
(val))
sys/dev/pci/if_ice.c
21228
uint32_t val;
sys/dev/pci/if_ice.c
21234
val = (PFINT_OICR_ECC_ERR_M |
sys/dev/pci/if_ice.c
21242
ICE_WRITE(hw, PFINT_OICR_ENA, val);
sys/dev/pci/if_ice.c
21396
#define ICE_UP_TABLE_TRANSLATE(val, i) \
sys/dev/pci/if_ice.c
21397
(((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
sys/dev/pci/if_ice.c
25720
#define ICE_FLOW_SET_HDRS(seg, val) ((seg)->hdrs |= (uint32_t)(val))
sys/dev/pci/if_ice.c
25755
seg->fields[fld].src.val = val_loc;
sys/dev/pci/if_ice.c
25808
uint64_t val;
sys/dev/pci/if_ice.c
25843
val = (uint64_t)(seg->hdrs & ICE_FLOW_RSS_SEG_HDR_L3_MASKS);
sys/dev/pci/if_ice.c
25844
if (val && !ice_is_pow2(val))
sys/dev/pci/if_ice.c
25847
val = (uint64_t)(seg->hdrs & ICE_FLOW_RSS_SEG_HDR_L4_MASKS);
sys/dev/pci/if_ice.c
25848
if (val && !ice_is_pow2(val))
sys/dev/pci/if_ice.c
26863
uint32_t val;
sys/dev/pci/if_ice.c
26868
val = ICE_READ(hw, cq->rq.len);
sys/dev/pci/if_ice.c
26869
if (val & (PF_FW_ARQLEN_ARQVFE_M | PF_FW_ARQLEN_ARQOVFL_M |
sys/dev/pci/if_ice.c
26871
if (val & PF_FW_ARQLEN_ARQVFE_M)
sys/dev/pci/if_ice.c
26874
if (val & PF_FW_ARQLEN_ARQOVFL_M)
sys/dev/pci/if_ice.c
26877
if (val & PF_FW_ARQLEN_ARQCRIT_M)
sys/dev/pci/if_ice.c
26880
val &= ~(PF_FW_ARQLEN_ARQVFE_M | PF_FW_ARQLEN_ARQOVFL_M |
sys/dev/pci/if_ice.c
26882
ICE_WRITE(hw, cq->rq.len, val);
sys/dev/pci/if_ice.c
26885
val = ICE_READ(hw, cq->sq.len);
sys/dev/pci/if_ice.c
26886
if (val & (PF_FW_ATQLEN_ATQVFE_M | PF_FW_ATQLEN_ATQOVFL_M |
sys/dev/pci/if_ice.c
26888
if (val & PF_FW_ATQLEN_ATQVFE_M)
sys/dev/pci/if_ice.c
26891
if (val & PF_FW_ATQLEN_ATQOVFL_M)
sys/dev/pci/if_ice.c
26894
if (val & PF_FW_ATQLEN_ATQCRIT_M)
sys/dev/pci/if_ice.c
26897
val &= ~(PF_FW_ATQLEN_ATQVFE_M | PF_FW_ATQLEN_ATQOVFL_M |
sys/dev/pci/if_ice.c
26899
ICE_WRITE(hw, cq->sq.len, val);
sys/dev/pci/if_ice.c
5608
uint32_t val, clk_src;
sys/dev/pci/if_ice.c
5610
val = ICE_READ(hw, GLGEN_CLKSTAT_SRC);
sys/dev/pci/if_ice.c
5611
clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >>
sys/dev/pci/if_ice.c
6491
#define ice_arr_elem_idx(idx, val) [(idx)] = (val)
sys/dev/pci/if_ice.c
7194
uint32_t val;
sys/dev/pci/if_ice.c
7206
val = ICE_READ(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
sys/dev/pci/if_ice.c
7207
tx_timer_val = val &
sys/dev/pci/if_ice.c
7212
val = ICE_READ(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
sys/dev/pci/if_ice.c
7213
fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
sys/dev/pci/if_icevar.h
2217
uint32_t val;
sys/dev/pci/if_icevar.h
2925
#define ICE_FLOW_SET_HDRS(seg, val) ((seg)->hdrs |= (uint32_t)(val))
sys/dev/pci/if_icevar.h
2945
uint16_t val; /* Offset where the value is located */
sys/dev/pci/if_icevar.h
3709
uint32_t val;
sys/dev/pci/if_ipw.c
165
uint16_t val;
sys/dev/pci/if_ipw.c
239
val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0);
sys/dev/pci/if_ipw.c
240
ic->ic_myaddr[0] = val >> 8;
sys/dev/pci/if_ipw.c
241
ic->ic_myaddr[1] = val & 0xff;
sys/dev/pci/if_ipw.c
242
val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1);
sys/dev/pci/if_ipw.c
243
ic->ic_myaddr[2] = val >> 8;
sys/dev/pci/if_ipw.c
244
ic->ic_myaddr[3] = val & 0xff;
sys/dev/pci/if_ipw.c
245
val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2);
sys/dev/pci/if_ipw.c
246
ic->ic_myaddr[4] = val >> 8;
sys/dev/pci/if_ipw.c
247
ic->ic_myaddr[5] = val & 0xff;
sys/dev/pci/if_ipw.c
635
uint32_t val;
sys/dev/pci/if_ipw.c
643
uint32_t val;
sys/dev/pci/if_ipw.c
652
val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE);
sys/dev/pci/if_ipw.c
653
val &= 0xf;
sys/dev/pci/if_ipw.c
656
for (i = 0; i < nitems(rates) && rates[i].val != val; i++)
sys/dev/pci/if_ipw.c
724
uint16_t val;
sys/dev/pci/if_ipw.c
754
val = 0;
sys/dev/pci/if_ipw.c
759
val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n;
sys/dev/pci/if_ipw.c
769
return val;
sys/dev/pci/if_ipwreg.h
291
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_ipwreg.h
292
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ipwreg.h
294
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_ipwreg.h
295
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ipwreg.h
297
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_ipwreg.h
298
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ipwreg.h
307
#define MEM_WRITE_1(sc, addr, val) do { \
sys/dev/pci/if_ipwreg.h
309
CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_ipwreg.h
312
#define MEM_WRITE_2(sc, addr, val) do { \
sys/dev/pci/if_ipwreg.h
314
CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_ipwreg.h
317
#define MEM_WRITE_4(sc, addr, val) do { \
sys/dev/pci/if_ipwreg.h
319
CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_ipwreg.h
330
#define IPW_EEPROM_CTL(sc, val) do { \
sys/dev/pci/if_ipwreg.h
331
MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \
sys/dev/pci/if_iwi.c
164
uint16_t val;
sys/dev/pci/if_iwi.c
245
val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 0);
sys/dev/pci/if_iwi.c
246
ic->ic_myaddr[0] = val & 0xff;
sys/dev/pci/if_iwi.c
247
ic->ic_myaddr[1] = val >> 8;
sys/dev/pci/if_iwi.c
248
val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 1);
sys/dev/pci/if_iwi.c
249
ic->ic_myaddr[2] = val & 0xff;
sys/dev/pci/if_iwi.c
250
ic->ic_myaddr[3] = val >> 8;
sys/dev/pci/if_iwi.c
251
val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 2);
sys/dev/pci/if_iwi.c
252
ic->ic_myaddr[4] = val & 0xff;
sys/dev/pci/if_iwi.c
253
ic->ic_myaddr[5] = val >> 8;
sys/dev/pci/if_iwi.c
658
uint32_t val;
sys/dev/pci/if_iwi.c
667
val = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE);
sys/dev/pci/if_iwi.c
669
rate = iwi_rate(val);
sys/dev/pci/if_iwi.c
795
uint16_t val;
sys/dev/pci/if_iwi.c
825
val = 0;
sys/dev/pci/if_iwi.c
830
val |= ((tmp & IWI_EEPROM_Q) >> IWI_EEPROM_SHIFT_Q) << n;
sys/dev/pci/if_iwi.c
840
return val;
sys/dev/pci/if_iwireg.h
470
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwireg.h
471
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwireg.h
473
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_iwireg.h
474
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwireg.h
476
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_iwireg.h
477
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwireg.h
485
#define MEM_WRITE_1(sc, addr, val) do { \
sys/dev/pci/if_iwireg.h
487
CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_iwireg.h
490
#define MEM_WRITE_2(sc, addr, val) do { \
sys/dev/pci/if_iwireg.h
492
CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_iwireg.h
495
#define MEM_WRITE_4(sc, addr, val) do { \
sys/dev/pci/if_iwireg.h
497
CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
sys/dev/pci/if_iwireg.h
508
#define IWI_EEPROM_CTL(sc, val) do { \
sys/dev/pci/if_iwireg.h
509
MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \
sys/dev/pci/if_iwm.c
1061
iwm_write_prph_unlocked(struct iwm_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwm.c
1066
IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
sys/dev/pci/if_iwm.c
1070
iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwm.c
1073
iwm_write_prph_unlocked(sc, addr, val);
sys/dev/pci/if_iwm.c
1077
iwm_write_prph64(struct iwm_softc *sc, uint64_t addr, uint64_t val)
sys/dev/pci/if_iwm.c
1079
iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
sys/dev/pci/if_iwm.c
1080
iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32);
sys/dev/pci/if_iwm.c
1110
uint32_t val = vals ? vals[offs] : 0;
sys/dev/pci/if_iwm.c
1111
IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
sys/dev/pci/if_iwm.c
1121
iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwm.c
1123
return iwm_write_mem(sc, addr, &val, 1);
sys/dev/pci/if_iwm.c
1191
uint32_t val;
sys/dev/pci/if_iwm.c
1194
val = iwm_read_prph(sc, reg) & mask;
sys/dev/pci/if_iwm.c
1195
val |= bits;
sys/dev/pci/if_iwm.c
1196
iwm_write_prph(sc, reg, val);
sys/dev/pci/if_iwm.c
2152
uint32_t mask, val, reg_val = 0;
sys/dev/pci/if_iwm.c
2179
val = IWM_READ(sc, IWM_CSR_HW_IF_CONFIG_REG);
sys/dev/pci/if_iwm.c
2180
val &= ~mask;
sys/dev/pci/if_iwm.c
2181
val |= reg_val;
sys/dev/pci/if_iwm.c
2182
IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, val);
sys/dev/pci/if_iwm.c
4201
uint32_t val, last_read_idx = 0;
sys/dev/pci/if_iwm.c
4242
val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS);
sys/dev/pci/if_iwm.c
4243
val = val | (sec_num << shift_param);
sys/dev/pci/if_iwm.c
4244
IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val);
sys/dev/pci/if_iwm.c
4619
uint32_t val;
sys/dev/pci/if_iwm.c
4621
val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_ENERGY_ANT_ABC_IDX]);
sys/dev/pci/if_iwm.c
4622
energy_a = (val & IWM_RX_INFO_ENERGY_ANT_A_MSK) >>
sys/dev/pci/if_iwm.c
4625
energy_b = (val & IWM_RX_INFO_ENERGY_ANT_B_MSK) >>
sys/dev/pci/if_iwm.c
4628
energy_c = (val & IWM_RX_INFO_ENERGY_ANT_C_MSK) >>
sys/dev/pci/if_iwm.c
6552
uint16_t val;
sys/dev/pci/if_iwm.c
6560
val = htole16(sta_id << 12 | len);
sys/dev/pci/if_iwm.c
6566
scd_bc_tbl[qid].tfd_offset[idx] = val;
sys/dev/pci/if_iwm.c
6568
scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = val;
sys/dev/pci/if_iwm.c
6577
uint16_t val;
sys/dev/pci/if_iwm.c
6581
val = htole16(1 | (sta_id << 12));
sys/dev/pci/if_iwm.c
6587
scd_bc_tbl[qid].tfd_offset[idx] = val;
sys/dev/pci/if_iwm.c
6589
scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = val;
sys/dev/pci/if_iwmreg.h
6824
#define IWM_WRITE(sc, reg, val) \
sys/dev/pci/if_iwmreg.h
6825
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwmreg.h
6827
#define IWM_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwmreg.h
6828
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwn.c
1018
uint32_t val, tmp;
sys/dev/pci/if_iwn.c
1025
val = IWN_READ(sc, IWN_EEPROM);
sys/dev/pci/if_iwn.c
1026
if (val & IWN_EEPROM_READ_VALID)
sys/dev/pci/if_iwn.c
1049
*out++ = val >> 16;
sys/dev/pci/if_iwn.c
1051
*out++ = val >> 24;
sys/dev/pci/if_iwn.c
1413
uint16_t val;
sys/dev/pci/if_iwn.c
1447
iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
sys/dev/pci/if_iwn.c
1448
DPRINTF(("SKU capabilities=0x%04x\n", letoh16(val)));
sys/dev/pci/if_iwn.c
1450
if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
sys/dev/pci/if_iwn.c
1453
iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
sys/dev/pci/if_iwn.c
1454
sc->rfcfg = letoh16(val);
sys/dev/pci/if_iwn.c
1478
uint16_t val;
sys/dev/pci/if_iwn.c
1491
iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
sys/dev/pci/if_iwn.c
1492
sc->maxpwr2GHz = val & 0xff;
sys/dev/pci/if_iwn.c
1493
sc->maxpwr5GHz = val >> 8;
sys/dev/pci/if_iwn.c
1506
iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
sys/dev/pci/if_iwn.c
1507
sc->eeprom_voltage = (int16_t)letoh16(val);
sys/dev/pci/if_iwn.c
1560
uint16_t val;
sys/dev/pci/if_iwn.c
1564
iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
sys/dev/pci/if_iwn.c
1565
base = letoh16(val);
sys/dev/pci/if_iwn.c
1579
iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
sys/dev/pci/if_iwn.c
1580
base = letoh16(val);
sys/dev/pci/if_iwn.c
1591
iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
sys/dev/pci/if_iwn.c
1592
sc->eeprom_temp = letoh16(val);
sys/dev/pci/if_iwn.c
1593
iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2);
sys/dev/pci/if_iwn.c
1594
sc->eeprom_rawtemp = letoh16(val);
sys/dev/pci/if_iwn.c
1599
iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
sys/dev/pci/if_iwn.c
1600
sc->eeprom_temp = letoh16(val);
sys/dev/pci/if_iwn.c
1601
iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
sys/dev/pci/if_iwn.c
1602
volt = letoh16(val);
sys/dev/pci/if_iwn.c
1685
uint16_t val, base;
sys/dev/pci/if_iwn.c
1689
iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
sys/dev/pci/if_iwn.c
1690
base = letoh16(val);
sys/dev/pci/if_iwn.c
4073
uint64_t val, mod;
sys/dev/pci/if_iwn.c
4081
val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
sys/dev/pci/if_iwn.c
4082
mod = letoh64(cmd.tstamp) % val;
sys/dev/pci/if_iwn.c
4083
cmd.binitval = htole32((uint32_t)(val - mod));
sys/dev/pci/if_iwn.c
4086
ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod)));
sys/dev/pci/if_iwn.c
4441
uint32_t val;
sys/dev/pci/if_iwn.c
4454
val = MAX(calib->rssi[0], calib->rssi[1]);
sys/dev/pci/if_iwn.c
4455
val = MAX(calib->rssi[2], val);
sys/dev/pci/if_iwn.c
4460
if (val - calib->rssi[i] > 15 * 20)
sys/dev/pci/if_iwn.c
4586
#define inc(val, inc, max) \
sys/dev/pci/if_iwn.c
4587
if ((val) < (max)) { \
sys/dev/pci/if_iwn.c
4588
if ((val) < (max) - (inc)) \
sys/dev/pci/if_iwn.c
4589
(val) += (inc); \
sys/dev/pci/if_iwn.c
4591
(val) = (max); \
sys/dev/pci/if_iwn.c
4594
#define dec(val, dec, min) \
sys/dev/pci/if_iwn.c
4595
if ((val) > (min)) { \
sys/dev/pci/if_iwn.c
4596
if ((val) > (min) + (dec)) \
sys/dev/pci/if_iwn.c
4597
(val) -= (dec); \
sys/dev/pci/if_iwn.c
4599
(val) = (min); \
sys/dev/pci/if_iwn.c
4605
uint32_t val, rxena, fa;
sys/dev/pci/if_iwn.c
4643
val = MAX(noise[0], noise[1]);
sys/dev/pci/if_iwn.c
4644
val = MAX(noise[2], val);
sys/dev/pci/if_iwn.c
4646
calib->noise_samples[calib->cur_noise_sample] = val;
sys/dev/pci/if_iwn.c
4657
val = MIN(energy[0], energy[1]);
sys/dev/pci/if_iwn.c
4658
val = MIN(energy[2], val);
sys/dev/pci/if_iwn.c
4660
calib->energy_samples[calib->cur_energy_sample] = val;
sys/dev/pci/if_iwn.c
924
iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
sys/dev/pci/if_iwn.c
928
iwn_mem_write(sc, addr, val);
sys/dev/pci/if_iwnreg.h
2099
#define IWN_WRITE(sc, reg, val) \
sys/dev/pci/if_iwnreg.h
2100
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwnreg.h
2102
#define IWN_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwnreg.h
2103
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwx.c
12249
uint32_t val = 0;
sys/dev/pci/if_iwx.c
12253
val = iwx_read_umac_prph_unlocked(sc, IWX_WFPM_CTRL_REG);
sys/dev/pci/if_iwx.c
12254
val |= IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;
sys/dev/pci/if_iwx.c
12255
iwx_write_umac_prph_unlocked(sc, IWX_WFPM_CTRL_REG, val);
sys/dev/pci/if_iwx.c
1683
iwx_write_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwx.c
1688
IWX_WRITE(sc, IWX_HBUS_TARG_PRPH_WDAT, val);
sys/dev/pci/if_iwx.c
1692
iwx_write_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwx.c
1695
iwx_write_prph_unlocked(sc, addr, val);
sys/dev/pci/if_iwx.c
1711
iwx_write_umac_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwx.c
1713
iwx_write_prph_unlocked(sc, addr + sc->sc_umac_prph_offset, val);
sys/dev/pci/if_iwx.c
1717
iwx_write_umac_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwx.c
1719
iwx_write_prph(sc, addr + sc->sc_umac_prph_offset, val);
sys/dev/pci/if_iwx.c
1749
uint32_t val = vals ? vals[offs] : 0;
sys/dev/pci/if_iwx.c
1750
IWX_WRITE(sc, IWX_HBUS_TARG_MEM_WDAT, val);
sys/dev/pci/if_iwx.c
1760
iwx_write_mem32(struct iwx_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_iwx.c
1762
return iwx_write_mem(sc, addr, &val, 1);
sys/dev/pci/if_iwx.c
1844
uint32_t val;
sys/dev/pci/if_iwx.c
1847
val = iwx_read_prph(sc, reg) & mask;
sys/dev/pci/if_iwx.c
1848
val |= bits;
sys/dev/pci/if_iwx.c
1849
iwx_write_prph(sc, reg, val);
sys/dev/pci/if_iwx.c
2823
uint32_t mask, val, reg_val = 0;
sys/dev/pci/if_iwx.c
2850
val = IWX_READ(sc, IWX_CSR_HW_IF_CONFIG_REG);
sys/dev/pci/if_iwx.c
2851
val &= ~mask;
sys/dev/pci/if_iwx.c
2852
val |= reg_val;
sys/dev/pci/if_iwx.c
2853
IWX_WRITE(sc, IWX_CSR_HW_IF_CONFIG_REG, val);
sys/dev/pci/if_iwx.c
827
uint32_t addr, val;
sys/dev/pci/if_iwx.c
831
val = le32toh(dest_v1->reg_ops[i].val);
sys/dev/pci/if_iwx.c
834
DPRINTF(("%s: op=%u addr=%u val=%u\n", __func__, op, addr, val));
sys/dev/pci/if_iwx.c
837
IWX_WRITE(sc, addr, val);
sys/dev/pci/if_iwx.c
840
IWX_SETBITS(sc, addr, (1 << val));
sys/dev/pci/if_iwx.c
843
IWX_CLRBITS(sc, addr, (1 << val));
sys/dev/pci/if_iwx.c
846
iwx_write_prph(sc, addr, val);
sys/dev/pci/if_iwx.c
849
err = iwx_set_bits_prph(sc, addr, (1 << val));
sys/dev/pci/if_iwx.c
854
err = iwx_clear_bits_prph(sc, addr, (1 << val));
sys/dev/pci/if_iwx.c
859
if (iwx_read_prph(sc, addr) & (1 << val))
sys/dev/pci/if_iwxreg.h
2546
uint32_t val;
sys/dev/pci/if_iwxreg.h
8943
#define IWX_WRITE(sc, reg, val) \
sys/dev/pci/if_iwxreg.h
8944
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwxreg.h
8946
#define IWX_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwxreg.h
8947
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ix.c
1981
int val;
sys/dev/pci/if_ix.c
1983
val = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_BAR(0));
sys/dev/pci/if_ix.c
1984
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
sys/dev/pci/if_ix.c
1989
if (pci_mapreg_map(pa, PCIR_BAR(0), PCI_MAPREG_MEM_TYPE(val), 0,
sys/dev/pci/if_ixgb.c
1905
uint32_t val;
sys/dev/pci/if_ixgb.c
1907
val = IXGB_INT_RXT0 | IXGB_INT_TXDW | IXGB_INT_RXDMT0 |
sys/dev/pci/if_ixgb.c
1910
val |= IXGB_INT_GPI0;
sys/dev/pci/if_ixgb.c
1911
IXGB_WRITE_REG(&sc->hw, IMS, val);
sys/dev/pci/if_ixgb.c
905
int val;
sys/dev/pci/if_ixgb.c
911
val = pci_conf_read(pa->pa_pc, pa->pa_tag, IXGB_MMBA);
sys/dev/pci/if_ixgb.c
912
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
sys/dev/pci/if_ixgb.c
916
if (pci_mapreg_map(pa, IXGB_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
sys/dev/pci/if_ixl.c
1642
uint32_t port, ari, func, val;
sys/dev/pci/if_ixl.c
1666
val = ixl_rd(sc, I40E_PFLAN_QALLOC);
sys/dev/pci/if_ixl.c
1667
sc->sc_base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
sys/dev/pci/if_ixl.c
1669
nqueues = ((val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
sys/dev/pci/if_ixl.c
4321
*p = lemtoh32(¶m->val);
sys/dev/pci/if_ixl.c
4340
htolem32(¶m->val, v);
sys/dev/pci/if_ixl.c
4931
uint32_t val;
sys/dev/pci/if_ixl.c
4934
val = ixl_rd(sc, I40E_GLPCI_CNF2);
sys/dev/pci/if_ixl.c
4935
num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
sys/dev/pci/if_ixl.c
4937
num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
sys/dev/pci/if_ixl.c
4940
val = ixl_rd(sc, I40E_PFLAN_QALLOC);
sys/dev/pci/if_ixl.c
4941
base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
sys/dev/pci/if_ixl.c
4943
j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
sys/dev/pci/if_ixl.c
4945
if (val & I40E_PFLAN_QALLOC_VALID_MASK)
sys/dev/pci/if_ixl.c
4950
val = ixl_rd(sc, I40E_PF_VT_PFALLOC);
sys/dev/pci/if_ixl.c
4951
i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
sys/dev/pci/if_ixl.c
4953
j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
sys/dev/pci/if_ixl.c
4955
if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
sys/dev/pci/if_ixl.c
4962
val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
sys/dev/pci/if_ixl.c
4964
ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val);
sys/dev/pci/if_ixl.c
4967
val = I40E_QUEUE_TYPE_EOL << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
sys/dev/pci/if_ixl.c
4968
ixl_wr(sc, I40E_PFINT_LNKLST0, val);
sys/dev/pci/if_ixl.c
4970
ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val);
sys/dev/pci/if_ixl.c
4971
val = I40E_QUEUE_TYPE_EOL << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
sys/dev/pci/if_ixl.c
4973
ixl_wr(sc, I40E_VPINT_LNKLST0(i), val);
sys/dev/pci/if_ixl.c
4975
ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val);
sys/dev/pci/if_ixl.c
4987
val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block));
sys/dev/pci/if_ixl.c
4988
val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
sys/dev/pci/if_ixl.c
4989
val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
sys/dev/pci/if_ixl.c
4990
val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
sys/dev/pci/if_ixl.c
4992
ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
sys/dev/pci/if_ixl.c
640
uint32_t val;
sys/dev/pci/if_jme.c
143
uint32_t val;
sys/dev/pci/if_jme.c
155
if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
sys/dev/pci/if_jme.c
164
return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
sys/dev/pci/if_jme.c
171
jme_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_jme.c
181
((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
sys/dev/pci/if_jme.c
186
if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
sys/dev/pci/if_jme.c
361
jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
sys/dev/pci/if_jme.c
366
*val = 0;
sys/dev/pci/if_jme.c
394
*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
sys/dev/pci/if_jme.c
402
uint8_t fup, reg, val;
sys/dev/pci/if_jme.c
424
&val) != 0)
sys/dev/pci/if_jme.c
426
eaddr[reg - JME_PAR0] = val;
sys/dev/pci/if_jmevar.h
223
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_jmevar.h
224
bus_space_write_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg), (val))
sys/dev/pci/if_lge.c
180
u_int32_t val;
sys/dev/pci/if_lge.c
194
val = CSR_READ_4(sc, LGE_EEDATA);
sys/dev/pci/if_lge.c
197
*dest = (val >> 16) & 0xFFFF;
sys/dev/pci/if_lge.c
199
*dest = val & 0xFFFF;
sys/dev/pci/if_lgereg.h
527
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_lgereg.h
528
bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)
sys/dev/pci/if_lgereg.h
533
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_lgereg.h
534
bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)
sys/dev/pci/if_lgereg.h
539
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_lgereg.h
540
bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
sys/dev/pci/if_lii.c
1111
uint32_t crc, val;
sys/dev/pci/if_lii.c
1113
val = LII_READ_4(sc, LII_MACC);
sys/dev/pci/if_lii.c
1114
val &= ~(MACC_ALLMULTI_EN | MACC_BCAST_EN | MACC_PROMISC_EN);
sys/dev/pci/if_lii.c
1120
val |= MACC_BCAST_EN;
sys/dev/pci/if_lii.c
1125
val |= MACC_PROMISC_EN;
sys/dev/pci/if_lii.c
1127
val |= MACC_ALLMULTI_EN;
sys/dev/pci/if_lii.c
1147
LII_WRITE_4(sc, LII_MACC, val);
sys/dev/pci/if_lii.c
174
#define LII_WRITE_4(sc,reg,val) \
sys/dev/pci/if_lii.c
175
bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
sys/dev/pci/if_lii.c
176
#define LII_WRITE_2(sc,reg,val) \
sys/dev/pci/if_lii.c
177
bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
sys/dev/pci/if_lii.c
178
#define LII_WRITE_1(sc,reg,val) \
sys/dev/pci/if_lii.c
179
bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
sys/dev/pci/if_lii.c
335
uint32_t val;
sys/dev/pci/if_lii.c
337
val = LII_READ_4(sc, LII_SFC);
sys/dev/pci/if_lii.c
338
if (val & SFC_EN_VPD)
sys/dev/pci/if_lii.c
339
LII_WRITE_4(sc, LII_SFC, val & ~(SFC_EN_VPD));
sys/dev/pci/if_lii.c
346
lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
sys/dev/pci/if_lii.c
348
return pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val);
sys/dev/pci/if_lii.c
422
lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
sys/dev/pci/if_lii.c
446
*val = LII_READ_4(sc, LII_SF_DATA);
sys/dev/pci/if_lii.c
454
uint32_t val, val1, addr0 = 0, addr1 = 0;
sys/dev/pci/if_lii.c
457
while ((*sc->sc_memread)(sc, offset, &val) == 0) {
sys/dev/pci/if_lii.c
461
if ((val & 0xff) != 0x5a)
sys/dev/pci/if_lii.c
468
val >>= 16;
sys/dev/pci/if_lii.c
469
switch (val) {
sys/dev/pci/if_lii.c
509
uint32_t val;
sys/dev/pci/if_lii.c
512
val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
sys/dev/pci/if_lii.c
514
val |= MDIOC_START | MDIOC_SUP_PREAMBLE;
sys/dev/pci/if_lii.c
515
val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
sys/dev/pci/if_lii.c
517
val |= MDIOC_READ;
sys/dev/pci/if_lii.c
519
LII_WRITE_4(sc, LII_MDIOC, val);
sys/dev/pci/if_lii.c
523
val = LII_READ_4(sc, LII_MDIOC);
sys/dev/pci/if_lii.c
524
if ((val & (MDIOC_START | MDIOC_BUSY)) == 0)
sys/dev/pci/if_lii.c
533
return (val & 0x0000ffff);
sys/dev/pci/if_lii.c
540
uint32_t val;
sys/dev/pci/if_lii.c
543
val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
sys/dev/pci/if_lii.c
544
val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT;
sys/dev/pci/if_lii.c
546
val |= MDIOC_START | MDIOC_SUP_PREAMBLE;
sys/dev/pci/if_lii.c
547
val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
sys/dev/pci/if_lii.c
551
LII_WRITE_4(sc, LII_MDIOC, val);
sys/dev/pci/if_lii.c
555
val = LII_READ_4(sc, LII_MDIOC);
sys/dev/pci/if_lii.c
556
if ((val & (MDIOC_START | MDIOC_BUSY)) == 0)
sys/dev/pci/if_lii.c
570
uint32_t val;
sys/dev/pci/if_lii.c
574
val = LII_READ_4(sc, LII_MACC);
sys/dev/pci/if_lii.c
577
val |= MACC_FDX;
sys/dev/pci/if_lii.c
579
val &= ~MACC_FDX;
sys/dev/pci/if_lii.c
581
LII_WRITE_4(sc, LII_MACC, val);
sys/dev/pci/if_lii.c
612
uint32_t val;
sys/dev/pci/if_lii.c
695
val = LII_READ_4(sc, LII_MACC) & MACC_FDX;
sys/dev/pci/if_lii.c
697
val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY |
sys/dev/pci/if_lii.c
701
val |= 7 << MACC_PREAMBLE_LEN_SHIFT;
sys/dev/pci/if_lii.c
702
val |= 2 << MACC_HDX_LEFT_BUF_SHIFT;
sys/dev/pci/if_lii.c
704
LII_WRITE_4(sc, LII_MACC, val);
sys/dev/pci/if_mcx.c
2727
mcx_get_id(uint32_t val)
sys/dev/pci/if_mcx.c
2729
return betoh32(val) & 0x00ffffff;
sys/dev/pci/if_mcx.c
6990
uint32_t val;
sys/dev/pci/if_mcx.c
6993
val = ((cq->cq_count) & 3) << MCX_CQ_DOORBELL_ARM_CMD_SN_SHIFT;
sys/dev/pci/if_mcx.c
6994
val |= (cq->cq_cons & MCX_CQ_DOORBELL_ARM_CI_MASK);
sys/dev/pci/if_mcx.c
7002
htobem32(&db->db_arm_ci, val);
sys/dev/pci/if_mcx.c
7009
uval = (uint64_t)val << 32;
sys/dev/pci/if_mcx.c
7091
uint32_t val;
sys/dev/pci/if_mcx.c
7094
val = (eq->eq_n << 24) | (eq->eq_cons & 0xffffff);
sys/dev/pci/if_mcx.c
7096
mcx_wr(sc, offset, val);
sys/dev/pci/if_mcx.c
7097
mcx_bar(sc, offset, sizeof(val), BUS_SPACE_BARRIER_WRITE);
sys/dev/pci/if_msk.c
384
u_int16_t val;
sys/dev/pci/if_msk.c
392
val = SK_YU_READ_2(sc_if, YUKON_SMICR);
sys/dev/pci/if_msk.c
393
if (val & YU_SMICR_READ_VALID)
sys/dev/pci/if_msk.c
406
val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
sys/dev/pci/if_msk.c
409
phy, reg, val));
sys/dev/pci/if_msk.c
411
return (val);
sys/dev/pci/if_msk.c
415
msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_msk.c
421
phy, reg, val));
sys/dev/pci/if_msk.c
423
SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
sys/dev/pci/if_mwx.c
2781
uint32_t *txd, val;
sys/dev/pci/if_mwx.c
2805
val = (tot_len & MT_TXD0_TX_BYTES_MASK) |
sys/dev/pci/if_mwx.c
2807
txd[0] = htole32(val);
sys/dev/pci/if_mwx.c
2810
val = MT7925_HDR_FORMAT_CMD;
sys/dev/pci/if_mwx.c
2812
val = MT_TXD1_LONG_FORMAT | MT_HDR_FORMAT_CMD;
sys/dev/pci/if_mwx.c
2813
txd[1] = htole32(val);
sys/dev/pci/if_mwx.c
3030
mcu_int = le32toh(event->val);
sys/dev/pci/if_mwx.c
3044
uint32_t *val)
sys/dev/pci/if_mwx.c
3061
if (val != NULL)
sys/dev/pci/if_mwx.c
3062
*val = sc->sc_mcu_wait[seq].mcu_int;
sys/dev/pci/if_mwx.c
3617
uint32_t reg, val, mask;
sys/dev/pci/if_mwx.c
3622
val = (idx & mask) | MT7925_WTBL_UPDATE_ADM_COUNT_CLEAR;
sys/dev/pci/if_mwx.c
3626
val = (idx & mask) | MT_WTBL_UPDATE_ADM_COUNT_CLEAR;
sys/dev/pci/if_mwx.c
3629
mwx_rmw(sc, reg, val, mask);
sys/dev/pci/if_mwx.c
4114
mt7921_mcu_set_rts_thresh(struct mwx_softc *sc, uint32_t val, uint8_t band)
sys/dev/pci/if_mwx.c
4125
.len_thresh = htole32(val),
sys/dev/pci/if_mwx.c
4703
uint32_t val, reg_offset;
sys/dev/pci/if_mwx.c
4731
val = MT7921_CFEND_RATE_DEFAULT;
sys/dev/pci/if_mwx.c
4733
val = MT7921_CFEND_RATE_11B;
sys/dev/pci/if_mwx.c
4735
mwx_rmw(sc, MT_AGG_ACR0(0), val, MT_AGG_ACR_CFEND_RATE_MASK);
sys/dev/pci/if_mwx.c
5461
uint32_t val;
sys/dev/pci/if_mwx.c
5502
val = MT_HDR_FORMAT_802_11 | MT_TXD1_HDR_INFO(hdrlen / 2) |
sys/dev/pci/if_mwx.c
5504
txp->txwi[1] |= htole32(val);
sys/dev/pci/if_mwx.c
5506
val = MT_TXD2_FRAME_TYPE(type) | MT_TXD2_SUB_TYPE(subtype);
sys/dev/pci/if_mwx.c
5508
val |= MT_TXD2_MULTICAST;
sys/dev/pci/if_mwx.c
5513
val |= MT_TXD2_BIP;
sys/dev/pci/if_mwx.c
5522
val |= MT_TXD2_FIX_RATE;
sys/dev/pci/if_mwx.c
5524
val |= htole32(MT_TXD2_HTC_VLD);
sys/dev/pci/if_mwx.c
5534
txp->txwi[2] |= htole32(val);
sys/dev/pci/if_mwx.c
5552
val = MT_TXD3_SN_VALID |
sys/dev/pci/if_mwx.c
5554
txp->txwi[3] |= htole32(val);
sys/dev/pci/if_mwx.c
5559
val = MT_TXD7_TYPE(type) | MT_TXD7_SUB_TYPE(subtype);
sys/dev/pci/if_mwx.c
5560
txp->txwi[7] |= htole32(val);
sys/dev/pci/if_mwx.c
5612
uint32_t val, p_fmt, omac_idx;
sys/dev/pci/if_mwx.c
5639
val = ((m->m_pkthdr.len + MT_TXD_SIZE) & MT_TXD0_TX_BYTES_MASK) |
sys/dev/pci/if_mwx.c
5641
txp->txwi[0] = htole32(val);
sys/dev/pci/if_mwx.c
5643
val = MT_TXD1_LONG_FORMAT | (mn->wcid & MT_TXD1_WLAN_IDX_MASK) |
sys/dev/pci/if_mwx.c
5646
val |= MT_TXD1_TGID;
sys/dev/pci/if_mwx.c
5647
txp->txwi[1] = htole32(val);
sys/dev/pci/if_mwx.c
5650
val = 15 << MT_TXD3_REM_TX_COUNT_SHIFT;
sys/dev/pci/if_mwx.c
5652
val |= MT_TXD3_PROTECT_FRAME;
sys/dev/pci/if_mwx.c
5655
val |= MT_TXD3_NO_ACK;
sys/dev/pci/if_mwx.c
5657
txp->txwi[3] = htole32(val);
sys/dev/pci/if_mwx.c
5660
val = pid & MT_TXD5_PID;
sys/dev/pci/if_mwx.c
5662
val |= MT_TXD5_TX_STATUS_HOST;
sys/dev/pci/if_mwx.c
5663
txp->txwi[5] = htole32(val);
sys/dev/pci/if_mwx.c
644
mwx_write(struct mwx_softc *sc, uint32_t reg, uint32_t val)
sys/dev/pci/if_mwx.c
647
bus_space_write_4(sc->sc_st, sc->sc_memh, reg, val);
sys/dev/pci/if_mwx.c
658
mwx_rmw(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask)
sys/dev/pci/if_mwx.c
661
val |= bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & ~mask;
sys/dev/pci/if_mwx.c
662
bus_space_write_4(sc->sc_st, sc->sc_memh, reg, val);
sys/dev/pci/if_mwx.c
663
return val;
sys/dev/pci/if_mwx.c
708
mwx_poll(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask,
sys/dev/pci/if_mwx.c
717
if (cur == val)
sys/dev/pci/if_mwx.c
723
DEVNAME(sc), reg, val, mask, cur);
sys/dev/pci/if_mwxreg.h
1043
uint32_t val;
sys/dev/pci/if_nep.c
1056
val = pktread | (ptrread << RX_DMA_CTL_STAT_PTRREAD_SHIFT);
sys/dev/pci/if_nep.c
1057
val |= RX_DMA_CTL_STAT_MEX;
sys/dev/pci/if_nep.c
1058
nep_write(sc, RX_DMA_CTL_STAT(sc->sc_port), val);
sys/dev/pci/if_nep.c
1072
uint64_t val;
sys/dev/pci/if_nep.c
1076
val = nep_read(sc, TX_CS(sc->sc_port));
sys/dev/pci/if_nep.c
1077
pkt_cnt = (val & TX_CS_PKT_CNT_MASK) >> TX_CS_PKT_CNT_SHIFT;
sys/dev/pci/if_nep.c
1112
uint64_t val;
sys/dev/pci/if_nep.c
1127
val = nep_read(sc, IPP_CFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1128
val |= IPP_CFIG_SOFT_RST;
sys/dev/pci/if_nep.c
1129
nep_write(sc, IPP_CFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1132
val = nep_read(sc, IPP_CFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1133
if ((val & IPP_CFIG_SOFT_RST) == 0)
sys/dev/pci/if_nep.c
1139
val = nep_read(sc, IPP_CFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1140
val |= IPP_CFIG_IPP_ENABLE;
sys/dev/pci/if_nep.c
1141
nep_write(sc, IPP_CFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1149
uint64_t val;
sys/dev/pci/if_nep.c
1151
val = nep_read(sc, IPP_CFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1152
val |= IPP_CFIG_DFIFO_PIO_W;
sys/dev/pci/if_nep.c
1153
nep_write(sc, IPP_CFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1162
val &= ~IPP_CFIG_DFIFO_PIO_W;
sys/dev/pci/if_nep.c
1163
nep_write(sc, IPP_CFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1186
uint64_t val;
sys/dev/pci/if_nep.c
1193
val = nep_read(sc, XRXMAC_SW_RST(sc->sc_port));
sys/dev/pci/if_nep.c
1194
if ((val & (XRXMAC_SW_RST_REG_RST |
sys/dev/pci/if_nep.c
1227
uint64_t val;
sys/dev/pci/if_nep.c
1233
val = nep_read(sc, RXMAC_SW_RST(sc->sc_port));
sys/dev/pci/if_nep.c
1234
if ((val & RXMAC_SW_RST_SW_RST) == 0)
sys/dev/pci/if_nep.c
1240
val = nep_read(sc, RXMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1241
val &= ~RXMAC_CONFIG_ERROR_CHK_DIS;
sys/dev/pci/if_nep.c
1242
val &= ~RXMAC_CONFIG_PROMISCUOUS;
sys/dev/pci/if_nep.c
1243
val &= ~RXMAC_CONFIG_PROMISCUOUS_GROUP;
sys/dev/pci/if_nep.c
1244
val &= ~RXMAC_CONFIG_ADDR_FILTER_EN;
sys/dev/pci/if_nep.c
1245
val &= ~RXMAC_CONFIG_HASH_FILTER_EN;
sys/dev/pci/if_nep.c
1246
val &= ~RXMAC_CONFIG_STRIP_FCS;
sys/dev/pci/if_nep.c
1247
val &= ~RXMAC_CONFIG_STRIP_PAD;
sys/dev/pci/if_nep.c
1248
val &= ~RXMAC_CONFIG_RX_ENABLE;
sys/dev/pci/if_nep.c
1249
nep_write(sc, RXMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1276
uint64_t val;
sys/dev/pci/if_nep.c
1279
val = nep_read(sc, RXDMA_CFIG1(chan));
sys/dev/pci/if_nep.c
1280
val &= ~RXDMA_CFIG1_EN;
sys/dev/pci/if_nep.c
1281
val |= RXDMA_CFIG1_RST;
sys/dev/pci/if_nep.c
1286
val = nep_read(sc, RXDMA_CFIG1(chan));
sys/dev/pci/if_nep.c
1287
if ((val & RXDMA_CFIG1_RST) == 0)
sys/dev/pci/if_nep.c
1307
val = NEP_DMA_DVA(sc->sc_rxmbox) >> 32;
sys/dev/pci/if_nep.c
1308
nep_write(sc, RXDMA_CFIG1(chan), val);
sys/dev/pci/if_nep.c
1310
val = NEP_DMA_DVA(sc->sc_rxmbox) & 0xffffffc0;
sys/dev/pci/if_nep.c
1311
nep_write(sc, RXDMA_CFIG2(chan), val);
sys/dev/pci/if_nep.c
1313
val = NEP_DMA_DVA(sc->sc_rbring);
sys/dev/pci/if_nep.c
1314
val |= (uint64_t)NEP_NRBDESC << RBR_CFIG_A_LEN_SHIFT;
sys/dev/pci/if_nep.c
1315
nep_write(sc, RBR_CFIG_A(chan), val);
sys/dev/pci/if_nep.c
1317
val = RBR_CFIG_B_BLKSIZE_8K;
sys/dev/pci/if_nep.c
1318
val |= RBR_CFIG_B_BUFSZ1_8K | RBR_CFIG_B_VLD1;
sys/dev/pci/if_nep.c
1319
nep_write(sc, RBR_CFIG_B(chan), val);
sys/dev/pci/if_nep.c
1323
val = NEP_DMA_DVA(sc->sc_rcring);
sys/dev/pci/if_nep.c
1324
val |= (uint64_t)NEP_NRCDESC << RCRCFIG_A_LEN_SHIFT;
sys/dev/pci/if_nep.c
1325
nep_write(sc, RCRCFIG_A(chan), val);
sys/dev/pci/if_nep.c
1327
val = 8 | RCRCFIG_B_ENTOUT;
sys/dev/pci/if_nep.c
1328
val |= (16 << RCRCFIG_B_PTHRES_SHIFT);
sys/dev/pci/if_nep.c
1329
nep_write(sc, RCRCFIG_B(chan), val);
sys/dev/pci/if_nep.c
1348
uint64_t val;
sys/dev/pci/if_nep.c
1355
val = nep_read(sc, XTXMAC_SW_RST(sc->sc_port));
sys/dev/pci/if_nep.c
1356
if ((val & (XTXMAC_SW_RST_REG_RST |
sys/dev/pci/if_nep.c
1363
val = nep_read(sc, XMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1364
val &= ~XMAC_CONFIG_ALWAYS_NO_CRC;
sys/dev/pci/if_nep.c
1365
val &= ~XMAC_CONFIG_VAR_MIN_IPG_EN;
sys/dev/pci/if_nep.c
1366
val &= ~XMAC_CONFIG_STRETCH_MODE;
sys/dev/pci/if_nep.c
1367
val &= ~XMAC_CONFIG_TX_ENABLE;
sys/dev/pci/if_nep.c
1368
nep_write(sc, XMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1370
val = nep_read(sc, XMAC_IPG(sc->sc_port));
sys/dev/pci/if_nep.c
1371
val &= ~XMAC_IPG_IPG_VALUE1_MASK; /* MII/GMII mode */
sys/dev/pci/if_nep.c
1372
val |= XMAC_IPG_IPG_VALUE1_12;
sys/dev/pci/if_nep.c
1373
val &= ~XMAC_IPG_IPG_VALUE_MASK; /* XGMII mode */
sys/dev/pci/if_nep.c
1374
val |= XMAC_IPG_IPG_VALUE_12_15;
sys/dev/pci/if_nep.c
1375
nep_write(sc, XMAC_IPG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1377
val = nep_read(sc, XMAC_MIN(sc->sc_port));
sys/dev/pci/if_nep.c
1378
val &= ~XMAC_MIN_RX_MIN_PKT_SIZE_MASK;
sys/dev/pci/if_nep.c
1379
val &= ~XMAC_MIN_TX_MIN_PKT_SIZE_MASK;
sys/dev/pci/if_nep.c
1380
val |= (64 << XMAC_MIN_RX_MIN_PKT_SIZE_SHIFT);
sys/dev/pci/if_nep.c
1381
val |= (64 << XMAC_MIN_TX_MIN_PKT_SIZE_SHIFT);
sys/dev/pci/if_nep.c
1382
nep_write(sc, XMAC_MIN(sc->sc_port), val);
sys/dev/pci/if_nep.c
1392
uint64_t val;
sys/dev/pci/if_nep.c
1398
val = nep_read(sc, TXMAC_SW_RST(sc->sc_port));
sys/dev/pci/if_nep.c
1399
if ((val & TXMAC_SW_RST_SW_RST) == 0)
sys/dev/pci/if_nep.c
1415
uint64_t val;
sys/dev/pci/if_nep.c
1418
val = nep_read(sc, TXC_CONTROL);
sys/dev/pci/if_nep.c
1419
val |= TXC_CONTROL_TXC_ENABLED;
sys/dev/pci/if_nep.c
1420
val |= (1ULL << sc->sc_port);
sys/dev/pci/if_nep.c
1421
nep_write(sc, TXC_CONTROL, val);
sys/dev/pci/if_nep.c
1425
val = nep_read(sc, TXC_INT_MASK);
sys/dev/pci/if_nep.c
1426
val &= ~TXC_INT_MASK_PORT_INT_MASK(sc->sc_port);
sys/dev/pci/if_nep.c
1427
nep_write(sc, TXC_INT_MASK, val);
sys/dev/pci/if_nep.c
1429
val = nep_read(sc, TX_CS(chan));
sys/dev/pci/if_nep.c
1430
val |= TX_CS_RST;
sys/dev/pci/if_nep.c
1431
nep_write(sc, TX_CS(chan), val);
sys/dev/pci/if_nep.c
1435
val = nep_read(sc, TX_CS(chan));
sys/dev/pci/if_nep.c
1436
if ((val & TX_CS_RST) == 0)
sys/dev/pci/if_nep.c
1458
val = NEP_DMA_DVA(sc->sc_txring);
sys/dev/pci/if_nep.c
1459
val |= (NEP_DMA_LEN(sc->sc_txring) / 64) << TX_RNG_CFIG_LEN_SHIFT;
sys/dev/pci/if_nep.c
1460
nep_write(sc, TX_RNG_CFIG(chan), val);
sys/dev/pci/if_nep.c
1469
uint64_t val;
sys/dev/pci/if_nep.c
1472
val = nep_read(sc, XMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1473
val &= ~XMAC_CONFIG_PROMISCUOUS;
sys/dev/pci/if_nep.c
1474
val &= ~XMAC_CONFIG_PROMISCUOUS_GROUP;
sys/dev/pci/if_nep.c
1475
val &= ~XMAC_CONFIG_HASH_FILTER_EN;
sys/dev/pci/if_nep.c
1477
val |= XMAC_CONFIG_PROMISCUOUS;
sys/dev/pci/if_nep.c
1479
val |= XMAC_CONFIG_PROMISCUOUS_GROUP;
sys/dev/pci/if_nep.c
1481
val |= XMAC_CONFIG_HASH_FILTER_EN;
sys/dev/pci/if_nep.c
1482
val |= XMAC_CONFIG_RX_MAC_ENABLE;
sys/dev/pci/if_nep.c
1483
nep_write(sc, XMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1485
val = nep_read(sc, RXMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1486
val &= ~RXMAC_CONFIG_PROMISCUOUS;
sys/dev/pci/if_nep.c
1487
val &= ~RXMAC_CONFIG_PROMISCUOUS_GROUP;
sys/dev/pci/if_nep.c
1488
val &= ~RXMAC_CONFIG_HASH_FILTER_EN;
sys/dev/pci/if_nep.c
1490
val |= RXMAC_CONFIG_PROMISCUOUS;
sys/dev/pci/if_nep.c
1492
val |= RXMAC_CONFIG_PROMISCUOUS_GROUP;
sys/dev/pci/if_nep.c
1494
val |= RXMAC_CONFIG_HASH_FILTER_EN;
sys/dev/pci/if_nep.c
1495
val |= RXMAC_CONFIG_RX_ENABLE;
sys/dev/pci/if_nep.c
1496
nep_write(sc, RXMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1503
uint64_t val;
sys/dev/pci/if_nep.c
1506
val = nep_read(sc, XMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1507
val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
sys/dev/pci/if_nep.c
1508
nep_write(sc, XMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1510
val = nep_read(sc, RXMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1511
val &= ~RXMAC_CONFIG_RX_ENABLE;
sys/dev/pci/if_nep.c
1512
nep_write(sc, RXMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1519
uint64_t val;
sys/dev/pci/if_nep.c
1522
val = nep_read(sc, TX_CS(sc->sc_port));
sys/dev/pci/if_nep.c
1523
val |= TX_CS_STOP_N_GO;
sys/dev/pci/if_nep.c
1524
nep_write(sc, TX_CS(sc->sc_port), val);
sys/dev/pci/if_nep.c
1528
val = nep_read(sc, TX_CS(sc->sc_port));
sys/dev/pci/if_nep.c
1529
if (val & TX_CS_SNG_STATE)
sys/dev/pci/if_nep.c
1535
val = nep_read(sc, RXDMA_CFIG1(sc->sc_port));
sys/dev/pci/if_nep.c
1536
val &= ~RXDMA_CFIG1_EN;
sys/dev/pci/if_nep.c
1537
nep_write(sc, RXDMA_CFIG1(sc->sc_port), val);
sys/dev/pci/if_nep.c
1541
val = nep_read(sc, RXDMA_CFIG1(sc->sc_port));
sys/dev/pci/if_nep.c
1542
if (val & RXDMA_CFIG1_QST)
sys/dev/pci/if_nep.c
1555
uint64_t val;
sys/dev/pci/if_nep.c
1611
val = nep_read(sc, XMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1612
val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
sys/dev/pci/if_nep.c
1613
nep_write(sc, XMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1617
val = nep_read(sc, PCS_MII_CTL(sc->sc_port));
sys/dev/pci/if_nep.c
1618
val |= PCS_MII_CTL_RESET;
sys/dev/pci/if_nep.c
1619
nep_write(sc, PCS_MII_CTL(sc->sc_port), val);
sys/dev/pci/if_nep.c
1622
val = nep_read(sc, PCS_MII_CTL(sc->sc_port));
sys/dev/pci/if_nep.c
1623
if ((val & PCS_MII_CTL_RESET) == 0)
sys/dev/pci/if_nep.c
1640
val = nep_read(sc, XMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1641
val |= XMAC_CONFIG_TX_ENABLE;
sys/dev/pci/if_nep.c
1642
nep_write(sc, XMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1644
val = nep_read(sc, TXMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1645
val |= TXMAC_CONFIG_TX_ENABLE;
sys/dev/pci/if_nep.c
1646
nep_write(sc, TXMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1649
val = nep_read(sc, RXDMA_CFIG1(sc->sc_port));
sys/dev/pci/if_nep.c
1650
val |= RXDMA_CFIG1_EN;
sys/dev/pci/if_nep.c
1651
nep_write(sc, RXDMA_CFIG1(sc->sc_port), val);
sys/dev/pci/if_nep.c
1681
uint64_t val;
sys/dev/pci/if_nep.c
1697
val = nep_read(sc, IPP_CFIG(sc->sc_port));
sys/dev/pci/if_nep.c
1698
val &= ~IPP_CFIG_IPP_ENABLE;
sys/dev/pci/if_nep.c
1699
nep_write(sc, IPP_CFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
1983
uint64_t val;
sys/dev/pci/if_nep.c
2013
val = nep_read(sc, RX_DMA_CTL_STAT(sc->sc_port));
sys/dev/pci/if_nep.c
2014
val |= RX_DMA_CTL_STAT_RBR_EMPTY;
sys/dev/pci/if_nep.c
2015
nep_write(sc, RX_DMA_CTL_STAT(sc->sc_port), val);
sys/dev/pci/if_nep.c
543
uint64_t val;
sys/dev/pci/if_nep.c
611
val = nep_read(sc, MIF_CONFIG);
sys/dev/pci/if_nep.c
612
val &= ~MIF_CONFIG_INDIRECT_MODE;
sys/dev/pci/if_nep.c
613
nep_write(sc, MIF_CONFIG, val);
sys/dev/pci/if_nep.c
824
nep_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_nep.c
832
frame |= (val & MIF_FRAME_DATA);
sys/dev/pci/if_nep.c
860
uint64_t val;
sys/dev/pci/if_nep.c
862
val = nep_read(sc, XMAC_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
865
val |= XMAC_CONFIG_SEL_CLK_25MHZ;
sys/dev/pci/if_nep.c
867
val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
sys/dev/pci/if_nep.c
869
val |= XMAC_CONFIG_1G_PCS_BYPASS;
sys/dev/pci/if_nep.c
871
val &= ~XMAC_CONFIG_MODE_MASK;
sys/dev/pci/if_nep.c
874
val |= XMAC_CONFIG_MODE_GMII;
sys/dev/pci/if_nep.c
876
val |= XMAC_CONFIG_MODE_MII;
sys/dev/pci/if_nep.c
878
val |= XMAC_CONFIG_LFS_DISABLE;
sys/dev/pci/if_nep.c
881
val |= XMAC_CONFIG_LOOPBACK;
sys/dev/pci/if_nep.c
883
val &= ~XMAC_CONFIG_LOOPBACK;
sys/dev/pci/if_nep.c
885
val |= XMAC_CONFIG_TX_OUTPUT_EN;
sys/dev/pci/if_nep.c
887
nep_write(sc, XMAC_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
894
uint64_t val;
sys/dev/pci/if_nep.c
896
val = nep_read(sc, MAC_XIF_CONFIG(sc->sc_port));
sys/dev/pci/if_nep.c
899
val |= MAC_XIF_CONFIG_SEL_CLK_25MHZ;
sys/dev/pci/if_nep.c
901
val &= MAC_XIF_CONFIG_SEL_CLK_25MHZ;
sys/dev/pci/if_nep.c
905
val |= MAC_XIF_CONFIG_GMII_MODE;
sys/dev/pci/if_nep.c
907
val &= ~MAC_XIF_CONFIG_GMII_MODE;
sys/dev/pci/if_nep.c
910
val |= MAC_XIF_CONFIG_LOOPBACK;
sys/dev/pci/if_nep.c
912
val &= ~MAC_XIF_CONFIG_LOOPBACK;
sys/dev/pci/if_nep.c
914
val |= MAC_XIF_CONFIG_TX_OUTPUT_EN;
sys/dev/pci/if_nep.c
916
nep_write(sc, MAC_XIF_CONFIG(sc->sc_port), val);
sys/dev/pci/if_nep.c
980
uint64_t val;
sys/dev/pci/if_nep.c
991
val = nep_read(sc, RX_DMA_CTL_STAT(sc->sc_port));
sys/dev/pci/if_nfe.c
405
uint32_t val;
sys/dev/pci/if_nfe.c
434
val = NFE_READ(sc, NFE_PHY_DATA);
sys/dev/pci/if_nfe.c
435
if (val != 0xffffffff && val != 0)
sys/dev/pci/if_nfe.c
439
sc->sc_dev.dv_xname, phy, reg, val));
sys/dev/pci/if_nfe.c
441
return val;
sys/dev/pci/if_nfe.c
445
nfe_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_nfe.c
458
NFE_WRITE(sc, NFE_PHY_DATA, val);
sys/dev/pci/if_nfereg.h
196
#define NFE_WRITE(sc, reg, val) \
sys/dev/pci/if_nfereg.h
197
bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
sys/dev/pci/if_ngbe.c
2174
uint32_t val;
sys/dev/pci/if_ngbe.c
2177
val = (cmd << SPI_CLK_CMD_OFFSET) | cmd_addr |
sys/dev/pci/if_ngbe.c
2179
NGBE_WRITE_REG(hw, NGBE_SPI_CMD, val);
sys/dev/pci/if_ngbe.c
2583
uint32_t val;
sys/dev/pci/if_ngbe.c
2595
val = NGBE_READ_REG(hw, NGBE_PSR_CTL);
sys/dev/pci/if_ngbe.c
2596
val |= NGBE_PSR_CTL_SW_EN;
sys/dev/pci/if_ngbe.c
2597
NGBE_WRITE_REG(hw, NGBE_PSR_CTL, val);
sys/dev/pci/if_ngbe.c
2867
uint16_t val = 0;
sys/dev/pci/if_ngbe.c
2877
hw->phy.ops.read_reg(hw, MII_ANAR, 0, &val);
sys/dev/pci/if_ngbe.c
2878
val &= ~(ANAR_TX | ANAR_10);
sys/dev/pci/if_ngbe.c
2879
hw->phy.ops.write_reg(hw, MII_ANAR, 0x0, val);
sys/dev/pci/if_ngbe.c
2917
uint16_t val = 0;
sys/dev/pci/if_ngbe.c
2921
ngbe_phy_read_reg(hw, 29, NGBE_INTERNAL_PHY_PAGE_OFFSET, &val);
sys/dev/pci/if_ngbe.c
2922
if (val & 0x20)
sys/dev/pci/if_ngbe.c
374
uint32_t val;
sys/dev/pci/if_ngbe.c
376
val = NGBE_READ_REG(hw, reg);
sys/dev/pci/if_ngbe.c
377
if (val == NGBE_FAILED_READ_REG)
sys/dev/pci/if_ngbe.c
378
return val;
sys/dev/pci/if_ngbe.c
379
return val & mask;
sys/dev/pci/if_ngbe.c
386
uint32_t val;
sys/dev/pci/if_ngbe.c
388
val = NGBE_READ_REG(hw, reg);
sys/dev/pci/if_ngbe.c
389
if (val == NGBE_FAILED_READ_REG)
sys/dev/pci/if_ngbe.c
391
val = ((val & ~mask) | (field & mask));
sys/dev/pci/if_ngbe.c
392
NGBE_WRITE_REG(hw, reg, val);
sys/dev/pci/if_ngereg.h
659
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_ngereg.h
660
bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
sys/dev/pci/if_oce.c
740
oce_write_cfg(struct oce_softc *sc, bus_size_t off, uint32_t val)
sys/dev/pci/if_oce.c
742
bus_space_write_4(sc->sc_cfg_iot, sc->sc_cfg_ioh, off, val);
sys/dev/pci/if_oce.c
748
oce_write_csr(struct oce_softc *sc, bus_size_t off, uint32_t val)
sys/dev/pci/if_oce.c
750
bus_space_write_4(sc->sc_csr_iot, sc->sc_csr_ioh, off, val);
sys/dev/pci/if_oce.c
756
oce_write_db(struct oce_softc *sc, bus_size_t off, uint32_t val)
sys/dev/pci/if_oce.c
758
bus_space_write_4(sc->sc_db_iot, sc->sc_db_ioh, off, val);
sys/dev/pci/if_pcn.c
1991
pcn_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_pcn.c
1996
pcn_bcr_write(sc, LE_BCR34, val);
sys/dev/pci/if_pcn.c
496
pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)
sys/dev/pci/if_pcn.c
500
bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val);
sys/dev/pci/if_pcn.c
512
pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)
sys/dev/pci/if_pcn.c
516
bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val);
sys/dev/pci/if_pcn.c
622
uint32_t val;
sys/dev/pci/if_pcn.c
623
val = pcn_csr_read(sc, LE_CSR12 + i);
sys/dev/pci/if_pcn.c
624
enaddr[2*i] = val & 0x0ff;
sys/dev/pci/if_pcn.c
625
enaddr[2*i+1] = (val >> 8) & 0x0ff;
sys/dev/pci/if_qwx_pci.c
1480
qwx_pci_write(struct qwx_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_qwx_pci.c
1484
bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val);
sys/dev/pci/if_qwx_pci.c
1505
uint32_t val;
sys/dev/pci/if_qwx_pci.c
1517
val = qwx_pci_read(sc, offset);
sys/dev/pci/if_qwx_pci.c
1519
val = psc->sc_pci_ops->window_read32(sc, offset);
sys/dev/pci/if_qwx_pci.c
1524
return val;
sys/dev/pci/if_qwx_pci.c
1884
uint32_t window_start, val;
sys/dev/pci/if_qwx_pci.c
1893
val = qwx_pci_read(sc, window_start +
sys/dev/pci/if_qwx_pci.c
1899
val = qwx_pci_read(sc, window_start +
sys/dev/pci/if_qwx_pci.c
1903
return val;
sys/dev/pci/if_qwx_pci.c
1924
uint32_t val, msecs;
sys/dev/pci/if_qwx_pci.c
1926
val = qwx_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
sys/dev/pci/if_qwx_pci.c
1928
val |= PCIE_SOC_GLOBAL_RESET_V;
sys/dev/pci/if_qwx_pci.c
1930
qwx_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
sys/dev/pci/if_qwx_pci.c
1937
val &= ~PCIE_SOC_GLOBAL_RESET_V;
sys/dev/pci/if_qwx_pci.c
1939
qwx_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
sys/dev/pci/if_qwx_pci.c
1943
val = qwx_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
sys/dev/pci/if_qwx_pci.c
1944
if (val == 0xffffffff)
sys/dev/pci/if_qwx_pci.c
1952
uint32_t val;
sys/dev/pci/if_qwx_pci.c
1955
val = qwx_pcic_read32(sc, PCIE_Q6_COOKIE_ADDR);
sys/dev/pci/if_qwx_pci.c
1956
DPRINTF("%s: cookie:0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwx_pci.c
1958
val = qwx_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
sys/dev/pci/if_qwx_pci.c
1959
DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwx_pci.c
1970
val = qwx_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
sys/dev/pci/if_qwx_pci.c
1971
DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwx_pci.c
1976
val = qwx_pcic_read32(sc, WLAON_SOC_RESET_CAUSE_REG);
sys/dev/pci/if_qwx_pci.c
1977
DPRINTF("%s: soc reset cause:%d\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwx_pci.c
2054
uint32_t val;
sys/dev/pci/if_qwx_pci.c
2057
val = qwx_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
sys/dev/pci/if_qwx_pci.c
2060
for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
sys/dev/pci/if_qwx_pci.c
2061
if (val == 0xffffffff)
sys/dev/pci/if_qwx_pci.c
2065
val = qwx_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
sys/dev/pci/if_qwx_pci.c
2068
DPRINTF("%s: pci ltssm 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwx_pci.c
2070
val = qwx_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
sys/dev/pci/if_qwx_pci.c
2071
val |= GCC_GCC_PCIE_HOT_RST_VAL;
sys/dev/pci/if_qwx_pci.c
2072
qwx_pcic_write32(sc, GCC_GCC_PCIE_HOT_RST, val);
sys/dev/pci/if_qwx_pci.c
2073
val = qwx_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
sys/dev/pci/if_qwx_pci.c
2075
DPRINTF("%s: pci pcie_hot_rst 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwx_pci.c
2094
uint32_t val;
sys/dev/pci/if_qwx_pci.c
2096
val = qwx_pcic_read32(sc, WLAON_QFPROM_PWR_CTRL_REG);
sys/dev/pci/if_qwx_pci.c
2097
val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
sys/dev/pci/if_qwx_pci.c
2098
qwx_pcic_write32(sc, WLAON_QFPROM_PWR_CTRL_REG, val);
sys/dev/pci/if_qwx_pci.c
2131
uint32_t val;
sys/dev/pci/if_qwx_pci.c
2133
val = pci_conf_read(psc->sc_pc, psc->sc_tag,
sys/dev/pci/if_qwx_pci.c
2137
val |= PCI_MSI_MC_MSIE;
sys/dev/pci/if_qwx_pci.c
2139
val &= ~PCI_MSI_MC_MSIE;
sys/dev/pci/if_qwx_pci.c
2142
val);
sys/dev/pci/if_qwx_pci.c
2515
qwx_mhi_ring_doorbell(struct qwx_softc *sc, uint64_t db_addr, uint64_t val)
sys/dev/pci/if_qwx_pci.c
2517
qwx_pci_write(sc, db_addr + 4, val >> 32);
sys/dev/pci/if_qwx_pci.c
2518
qwx_pci_write(sc, db_addr, val & 0xffffffff);
sys/dev/pci/if_qwz_pci.c
1325
qwz_pci_write(struct qwz_softc *sc, uint32_t addr, uint32_t val)
sys/dev/pci/if_qwz_pci.c
1329
bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val);
sys/dev/pci/if_qwz_pci.c
1350
uint32_t val;
sys/dev/pci/if_qwz_pci.c
1362
val = qwz_pci_read(sc, offset);
sys/dev/pci/if_qwz_pci.c
1364
val = psc->sc_pci_ops->window_read32(sc, offset);
sys/dev/pci/if_qwz_pci.c
1369
return val;
sys/dev/pci/if_qwz_pci.c
1750
uint32_t window_start, val;
sys/dev/pci/if_qwz_pci.c
1762
val = qwz_pci_read(sc,
sys/dev/pci/if_qwz_pci.c
1765
val = qwz_pci_read(sc, window_start +
sys/dev/pci/if_qwz_pci.c
1772
val = qwz_pci_read(sc, window_start +
sys/dev/pci/if_qwz_pci.c
1776
return val;
sys/dev/pci/if_qwz_pci.c
1797
uint32_t val, msecs;
sys/dev/pci/if_qwz_pci.c
1799
val = qwz_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
sys/dev/pci/if_qwz_pci.c
1801
val |= PCIE_SOC_GLOBAL_RESET_V;
sys/dev/pci/if_qwz_pci.c
1803
qwz_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
sys/dev/pci/if_qwz_pci.c
1810
val &= ~PCIE_SOC_GLOBAL_RESET_V;
sys/dev/pci/if_qwz_pci.c
1812
qwz_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
sys/dev/pci/if_qwz_pci.c
1816
val = qwz_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
sys/dev/pci/if_qwz_pci.c
1817
if (val == 0xffffffff)
sys/dev/pci/if_qwz_pci.c
1825
uint32_t val;
sys/dev/pci/if_qwz_pci.c
1828
val = qwz_pcic_read32(sc, PCIE_Q6_COOKIE_ADDR);
sys/dev/pci/if_qwz_pci.c
1829
DPRINTF("%s: cookie:0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwz_pci.c
1831
val = qwz_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
sys/dev/pci/if_qwz_pci.c
1832
DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwz_pci.c
1843
val = qwz_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
sys/dev/pci/if_qwz_pci.c
1844
DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwz_pci.c
1849
val = qwz_pcic_read32(sc, WLAON_SOC_RESET_CAUSE_REG);
sys/dev/pci/if_qwz_pci.c
1850
DPRINTF("%s: soc reset cause:%d\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwz_pci.c
1927
uint32_t val;
sys/dev/pci/if_qwz_pci.c
1930
val = qwz_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
sys/dev/pci/if_qwz_pci.c
1933
for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
sys/dev/pci/if_qwz_pci.c
1934
if (val == 0xffffffff)
sys/dev/pci/if_qwz_pci.c
1938
val = qwz_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
sys/dev/pci/if_qwz_pci.c
1941
DPRINTF("%s: pci ltssm 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwz_pci.c
1943
val = qwz_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
sys/dev/pci/if_qwz_pci.c
1944
val |= GCC_GCC_PCIE_HOT_RST_VAL;
sys/dev/pci/if_qwz_pci.c
1945
qwz_pcic_write32(sc, GCC_GCC_PCIE_HOT_RST, val);
sys/dev/pci/if_qwz_pci.c
1946
val = qwz_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
sys/dev/pci/if_qwz_pci.c
1948
DPRINTF("%s: pci pcie_hot_rst 0x%x\n", sc->sc_dev.dv_xname, val);
sys/dev/pci/if_qwz_pci.c
1967
uint32_t val;
sys/dev/pci/if_qwz_pci.c
1969
val = qwz_pcic_read32(sc, WLAON_QFPROM_PWR_CTRL_REG);
sys/dev/pci/if_qwz_pci.c
1970
val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
sys/dev/pci/if_qwz_pci.c
1971
qwz_pcic_write32(sc, WLAON_QFPROM_PWR_CTRL_REG, val);
sys/dev/pci/if_qwz_pci.c
2004
uint32_t val;
sys/dev/pci/if_qwz_pci.c
2006
val = pci_conf_read(psc->sc_pc, psc->sc_tag,
sys/dev/pci/if_qwz_pci.c
2010
val |= PCI_MSI_MC_MSIE;
sys/dev/pci/if_qwz_pci.c
2012
val &= ~PCI_MSI_MC_MSIE;
sys/dev/pci/if_qwz_pci.c
2015
val);
sys/dev/pci/if_qwz_pci.c
2324
qwz_mhi_ring_doorbell(struct qwz_softc *sc, uint64_t db_addr, uint64_t val)
sys/dev/pci/if_qwz_pci.c
2326
qwz_pci_write(sc, db_addr + 4, val >> 32);
sys/dev/pci/if_qwz_pci.c
2327
qwz_pci_write(sc, db_addr, val & 0xffffffff);
sys/dev/pci/if_rge.c
1007
val |= RGE_ADV_2500TFDX;
sys/dev/pci/if_rge.c
1009
val |= RGE_ADV_5000TFDX;
sys/dev/pci/if_rge.c
1011
val |= RGE_ADV_5000TFDX | RGE_ADV_10000TFDX;
sys/dev/pci/if_rge.c
1014
val |= RGE_ADV_10000TFDX;
sys/dev/pci/if_rge.c
1018
val |= RGE_ADV_5000TFDX;
sys/dev/pci/if_rge.c
1022
val |= RGE_ADV_2500TFDX;
sys/dev/pci/if_rge.c
1050
rge_write_phy_ocp(sc, 0xa5d4, val);
sys/dev/pci/if_rge.c
145
uint16_t val;
sys/dev/pci/if_rge.c
1674
rtl8125_mac_bps[i].val);
sys/dev/pci/if_rge.c
1704
rtl8125b_mac_bps[i].val);
sys/dev/pci/if_rge.c
1752
rtl8125d_2_mac_bps[i].val);
sys/dev/pci/if_rge.c
1918
uint16_t val;
sys/dev/pci/if_rge.c
1922
rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val);
sys/dev/pci/if_rge.c
1924
val = rge_read_ephy(sc, 0x002a) & ~0x7000;
sys/dev/pci/if_rge.c
1925
rge_write_ephy(sc, 0x002a, val | 0x3000);
sys/dev/pci/if_rge.c
1931
val = rge_read_ephy(sc, 0x006a) & ~0x7000;
sys/dev/pci/if_rge.c
1932
rge_write_ephy(sc, 0x006a, val | 0x3000);
sys/dev/pci/if_rge.c
1946
rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val);
sys/dev/pci/if_rge.c
1956
mac_r27_ephy[i].val);
sys/dev/pci/if_rge.c
1965
uint16_t val = 0;
sys/dev/pci/if_rge.c
1979
val |= RGE_ADV_10000TFDX;
sys/dev/pci/if_rge.c
1983
val |= RGE_ADV_5000TFDX;
sys/dev/pci/if_rge.c
1986
val |= RGE_ADV_2500TFDX;
sys/dev/pci/if_rge.c
1989
RGE_PHY_CLRBIT(sc, 0xa5d4, val);
sys/dev/pci/if_rge.c
2061
uint16_t val;
sys/dev/pci/if_rge.c
2083
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2084
rge_write_phy_ocp(sc, 0xa438, val | 0x9300);
sys/dev/pci/if_rge.c
2086
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2087
rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
sys/dev/pci/if_rge.c
2089
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2090
rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
sys/dev/pci/if_rge.c
2092
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2093
rge_write_phy_ocp(sc, 0xa438, val | 0xb900);
sys/dev/pci/if_rge.c
2102
val = rge_read_phy_ocp(sc, 0xbf38) & ~0x01f0;
sys/dev/pci/if_rge.c
2103
rge_write_phy_ocp(sc, 0xbf38, val | 0x0160);
sys/dev/pci/if_rge.c
2104
val = rge_read_phy_ocp(sc, 0xbf3a) & ~0x001f;
sys/dev/pci/if_rge.c
2105
rge_write_phy_ocp(sc, 0xbf3a, val | 0x0014);
sys/dev/pci/if_rge.c
2108
val = rge_read_phy_ocp(sc, 0xbf28) & ~0x1fff;
sys/dev/pci/if_rge.c
2109
rge_write_phy_ocp(sc, 0xbf28, val | 0x0187);
sys/dev/pci/if_rge.c
2110
val = rge_read_phy_ocp(sc, 0xbf2a) & ~0x003f;
sys/dev/pci/if_rge.c
2111
rge_write_phy_ocp(sc, 0xbf2a, val | 0x0003);
sys/dev/pci/if_rge.c
2131
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2132
rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
sys/dev/pci/if_rge.c
2134
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2135
rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
sys/dev/pci/if_rge.c
2137
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2138
rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
sys/dev/pci/if_rge.c
2140
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2141
rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
sys/dev/pci/if_rge.c
2143
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2144
rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
sys/dev/pci/if_rge.c
2146
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2147
rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
sys/dev/pci/if_rge.c
2149
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2150
rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
sys/dev/pci/if_rge.c
2164
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2165
rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
sys/dev/pci/if_rge.c
2167
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2168
rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
sys/dev/pci/if_rge.c
2170
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2171
rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
sys/dev/pci/if_rge.c
2173
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2174
rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
sys/dev/pci/if_rge.c
2176
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2177
rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
sys/dev/pci/if_rge.c
2179
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2180
rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
sys/dev/pci/if_rge.c
2186
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2187
rge_write_phy_ocp(sc, 0xb87e, val | 0x2800);
sys/dev/pci/if_rge.c
2190
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2191
rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
sys/dev/pci/if_rge.c
2193
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2194
rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
sys/dev/pci/if_rge.c
2196
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2197
rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
sys/dev/pci/if_rge.c
2198
val = rge_read_phy_ocp(sc, 0xae4e) & ~0x000f;
sys/dev/pci/if_rge.c
2199
rge_write_phy_ocp(sc, 0xae4e, val | 0x0001);
sys/dev/pci/if_rge.c
2201
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000;
sys/dev/pci/if_rge.c
2202
rge_write_phy_ocp(sc, 0xb87e, val | 0x4000);
sys/dev/pci/if_rge.c
2210
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2211
rge_write_phy_ocp(sc, 0xb87e, val | 0x6000);
sys/dev/pci/if_rge.c
2221
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2222
rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
sys/dev/pci/if_rge.c
2230
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2231
rge_write_phy_ocp(sc, 0xb87e, val | 0xdc00);
sys/dev/pci/if_rge.c
2233
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xc000;
sys/dev/pci/if_rge.c
2234
rge_write_phy_ocp(sc, 0xb87e, val | 0x4000);
sys/dev/pci/if_rge.c
2242
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2243
rge_write_phy_ocp(sc, 0xb87e, val | 0x0e00);
sys/dev/pci/if_rge.c
2250
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2251
rge_write_phy_ocp(sc, 0xa438, val | 0x0700);
sys/dev/pci/if_rge.c
2253
val = rge_read_phy_ocp(sc, 0xb87e) & ~0x3f00;
sys/dev/pci/if_rge.c
2254
rge_write_phy_ocp(sc, 0xb87e, val | 0x2a00);
sys/dev/pci/if_rge.c
2256
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2257
rge_write_phy_ocp(sc, 0xa438, val | 0x0b00);
sys/dev/pci/if_rge.c
2259
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2260
rge_write_phy_ocp(sc, 0xb87e, val | 0x4e00);
sys/dev/pci/if_rge.c
2262
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2263
rge_write_phy_ocp(sc, 0xb87e, val | 0x2300);
sys/dev/pci/if_rge.c
2278
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2279
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2281
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2282
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2284
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2285
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2287
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2288
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2290
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2291
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2293
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2294
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2296
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2297
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2299
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2300
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2302
val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
sys/dev/pci/if_rge.c
2303
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2306
val = rge_read_phy_ocp(sc, 0xbfb4) & ~0x07ff;
sys/dev/pci/if_rge.c
2307
rge_write_phy_ocp(sc, 0xbfb4, val | 0x0328);
sys/dev/pci/if_rge.c
2317
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2318
rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
sys/dev/pci/if_rge.c
2320
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2321
rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
sys/dev/pci/if_rge.c
2323
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2324
rge_write_phy_ocp(sc, 0xa438, val | 0x1600);
sys/dev/pci/if_rge.c
2331
uint16_t val;
sys/dev/pci/if_rge.c
2350
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2351
rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
sys/dev/pci/if_rge.c
2353
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2354
rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
sys/dev/pci/if_rge.c
2356
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2357
rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
sys/dev/pci/if_rge.c
2359
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2360
rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
sys/dev/pci/if_rge.c
2366
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2367
rge_write_phy_ocp(sc, 0xa438, val | 0x4700);
sys/dev/pci/if_rge.c
2368
val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0;
sys/dev/pci/if_rge.c
2369
rge_write_phy_ocp(sc, 0xa80c, val | 0x0080);
sys/dev/pci/if_rge.c
2373
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2374
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
sys/dev/pci/if_rge.c
2377
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2378
rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
sys/dev/pci/if_rge.c
2383
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2384
rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00);
sys/dev/pci/if_rge.c
2386
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2387
rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
sys/dev/pci/if_rge.c
2390
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2391
rge_write_phy_ocp(sc, 0xb87e, val | 0x9900);
sys/dev/pci/if_rge.c
2393
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2394
rge_write_phy_ocp(sc, 0xb87e, val | 0xc100);
sys/dev/pci/if_rge.c
2398
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2399
rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
sys/dev/pci/if_rge.c
2401
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2402
rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
sys/dev/pci/if_rge.c
2404
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2405
rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
sys/dev/pci/if_rge.c
2413
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2414
rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
sys/dev/pci/if_rge.c
2418
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2419
rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
sys/dev/pci/if_rge.c
2429
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2430
rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
sys/dev/pci/if_rge.c
2432
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2433
rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
sys/dev/pci/if_rge.c
2435
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2436
rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
sys/dev/pci/if_rge.c
2438
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2439
rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
sys/dev/pci/if_rge.c
2440
val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
sys/dev/pci/if_rge.c
2441
rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
sys/dev/pci/if_rge.c
2445
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2446
rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
sys/dev/pci/if_rge.c
2471
val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00;
sys/dev/pci/if_rge.c
2472
rge_write_phy_ocp(sc, 0xbd96, val | 0x1000);
sys/dev/pci/if_rge.c
2473
val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007;
sys/dev/pci/if_rge.c
2474
rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007);
sys/dev/pci/if_rge.c
2476
val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380;
sys/dev/pci/if_rge.c
2477
rge_write_phy_ocp(sc, 0xbf40, val | 0x0280);
sys/dev/pci/if_rge.c
2478
val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080;
sys/dev/pci/if_rge.c
2479
rge_write_phy_ocp(sc, 0xbf90, val | 0x0060);
sys/dev/pci/if_rge.c
2480
val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010;
sys/dev/pci/if_rge.c
2481
rge_write_phy_ocp(sc, 0xbf90, val | 0x000c);
sys/dev/pci/if_rge.c
2485
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2486
rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
sys/dev/pci/if_rge.c
2488
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2489
rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
sys/dev/pci/if_rge.c
2498
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2499
rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
sys/dev/pci/if_rge.c
2501
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2502
rge_write_phy_ocp(sc, 0xb87e, val | 0);
sys/dev/pci/if_rge.c
2504
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2505
rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00);
sys/dev/pci/if_rge.c
2507
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2508
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2518
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2519
rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
sys/dev/pci/if_rge.c
2523
val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000;
sys/dev/pci/if_rge.c
2524
rge_write_phy_ocp(sc, 0xac3c, val | 0x2000);
sys/dev/pci/if_rge.c
2525
val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200;
sys/dev/pci/if_rge.c
2526
rge_write_phy_ocp(sc, 0xac42, val | 0x01c0);
sys/dev/pci/if_rge.c
2529
val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002;
sys/dev/pci/if_rge.c
2530
rge_write_phy_ocp(sc, 0xac42, val | 0x0005);
sys/dev/pci/if_rge.c
2535
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2536
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
sys/dev/pci/if_rge.c
2538
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2539
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
sys/dev/pci/if_rge.c
2541
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2542
rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
sys/dev/pci/if_rge.c
2544
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2545
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2547
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2548
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2550
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2551
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2553
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2554
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
sys/dev/pci/if_rge.c
2556
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2557
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
sys/dev/pci/if_rge.c
2559
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2560
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
sys/dev/pci/if_rge.c
2562
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2563
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2565
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2566
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2568
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2569
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2572
val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
sys/dev/pci/if_rge.c
2573
rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
sys/dev/pci/if_rge.c
2575
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2576
rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
sys/dev/pci/if_rge.c
2584
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2585
rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
sys/dev/pci/if_rge.c
2592
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2593
rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
sys/dev/pci/if_rge.c
2602
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2603
rge_write_phy_ocp(sc, 0xb87e, val | 0);
sys/dev/pci/if_rge.c
2604
val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
sys/dev/pci/if_rge.c
2605
rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
sys/dev/pci/if_rge.c
2611
uint16_t val;
sys/dev/pci/if_rge.c
2625
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2626
rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
sys/dev/pci/if_rge.c
2632
val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
sys/dev/pci/if_rge.c
2633
rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
sys/dev/pci/if_rge.c
2635
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2636
rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
sys/dev/pci/if_rge.c
2638
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2639
rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
sys/dev/pci/if_rge.c
2641
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2642
rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
sys/dev/pci/if_rge.c
2646
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2647
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2649
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2650
rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
sys/dev/pci/if_rge.c
2652
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2653
rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
sys/dev/pci/if_rge.c
2655
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2656
rge_write_phy_ocp(sc, 0xa438, val | 0x7700);
sys/dev/pci/if_rge.c
2665
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2666
rge_write_phy_ocp(sc, 0xa438, val | 0x2900);
sys/dev/pci/if_rge.c
2668
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2669
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
sys/dev/pci/if_rge.c
2671
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2672
rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
sys/dev/pci/if_rge.c
2674
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2675
rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
sys/dev/pci/if_rge.c
2677
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2678
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2680
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2681
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2683
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2684
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2686
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2687
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
sys/dev/pci/if_rge.c
2689
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2690
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
sys/dev/pci/if_rge.c
2692
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2693
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
sys/dev/pci/if_rge.c
2695
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2696
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2698
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2699
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2701
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2702
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2704
val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
sys/dev/pci/if_rge.c
2705
rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
sys/dev/pci/if_rge.c
2707
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2708
rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
sys/dev/pci/if_rge.c
2710
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2711
rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
sys/dev/pci/if_rge.c
2724
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2725
rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
sys/dev/pci/if_rge.c
2730
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2731
rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
sys/dev/pci/if_rge.c
2735
val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
sys/dev/pci/if_rge.c
2736
rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
sys/dev/pci/if_rge.c
2739
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2740
rge_write_phy_ocp(sc, 0xb87e, val | 0x5d00);
sys/dev/pci/if_rge.c
2742
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2743
rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
sys/dev/pci/if_rge.c
2745
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2746
rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
sys/dev/pci/if_rge.c
2752
uint16_t val;
sys/dev/pci/if_rge.c
2769
val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
sys/dev/pci/if_rge.c
2770
rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
sys/dev/pci/if_rge.c
2771
val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
sys/dev/pci/if_rge.c
2772
rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
sys/dev/pci/if_rge.c
2775
val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
sys/dev/pci/if_rge.c
2776
rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
sys/dev/pci/if_rge.c
2777
val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
sys/dev/pci/if_rge.c
2778
rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
sys/dev/pci/if_rge.c
2779
val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
sys/dev/pci/if_rge.c
2780
rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
sys/dev/pci/if_rge.c
2783
val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
sys/dev/pci/if_rge.c
2784
rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
sys/dev/pci/if_rge.c
2787
val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
sys/dev/pci/if_rge.c
2788
rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
sys/dev/pci/if_rge.c
2790
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2791
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
sys/dev/pci/if_rge.c
2793
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2794
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
sys/dev/pci/if_rge.c
2823
val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
sys/dev/pci/if_rge.c
2824
rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
sys/dev/pci/if_rge.c
2836
uint16_t val;
sys/dev/pci/if_rge.c
2842
val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0;
sys/dev/pci/if_rge.c
2843
rge_write_phy_ocp(sc, 0xac46, val | 0x0090);
sys/dev/pci/if_rge.c
2844
val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003;
sys/dev/pci/if_rge.c
2845
rge_write_phy_ocp(sc, 0xad30, val | 0x0001);
sys/dev/pci/if_rge.c
2851
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2852
rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
sys/dev/pci/if_rge.c
2853
val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000;
sys/dev/pci/if_rge.c
2854
rge_write_phy_ocp(sc, 0xbf00, val | 0xa000);
sys/dev/pci/if_rge.c
2855
val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
sys/dev/pci/if_rge.c
2856
rge_write_phy_ocp(sc, 0xbf46, val | 0x0300);
sys/dev/pci/if_rge.c
2862
val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000;
sys/dev/pci/if_rge.c
2863
rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
sys/dev/pci/if_rge.c
2865
val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700;
sys/dev/pci/if_rge.c
2866
rge_write_phy_ocp(sc, 0xa438, val | 0xd800);
sys/dev/pci/if_rge.c
2873
uint16_t val;
sys/dev/pci/if_rge.c
2882
val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007;
sys/dev/pci/if_rge.c
2883
rge_write_phy_ocp(sc, 0xbf94, val | 0x0005);
sys/dev/pci/if_rge.c
2884
val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00;
sys/dev/pci/if_rge.c
2885
rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800);
sys/dev/pci/if_rge.c
2886
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
sys/dev/pci/if_rge.c
2887
rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
sys/dev/pci/if_rge.c
2889
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
sys/dev/pci/if_rge.c
2890
rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
sys/dev/pci/if_rge.c
2891
val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
sys/dev/pci/if_rge.c
2892
rge_write_phy_ocp(sc, 0xbc80, val | 0x0004);
sys/dev/pci/if_rge.c
2895
val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
sys/dev/pci/if_rge.c
2896
rge_write_phy_ocp(sc, 0xbc80, val | 0x0005);
sys/dev/pci/if_rge.c
2897
val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0;
sys/dev/pci/if_rge.c
2898
rge_write_phy_ocp(sc, 0xbc82, val | 0x0040);
sys/dev/pci/if_rge.c
2901
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
sys/dev/pci/if_rge.c
2902
rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000);
sys/dev/pci/if_rge.c
2911
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2912
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
sys/dev/pci/if_rge.c
2913
val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700;
sys/dev/pci/if_rge.c
2914
rge_write_phy_ocp(sc, 0xb106, val | 0x0100);
sys/dev/pci/if_rge.c
2915
val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700;
sys/dev/pci/if_rge.c
2916
rge_write_phy_ocp(sc, 0xb206, val | 0x0200);
sys/dev/pci/if_rge.c
2917
val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700;
sys/dev/pci/if_rge.c
2918
rge_write_phy_ocp(sc, 0xb306, val | 0x0300);
sys/dev/pci/if_rge.c
2920
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2921
rge_write_phy_ocp(sc, 0xb87e, val | 0x0300);
sys/dev/pci/if_rge.c
2926
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2927
rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
sys/dev/pci/if_rge.c
2930
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2931
rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
sys/dev/pci/if_rge.c
2933
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2934
rge_write_phy_ocp(sc, 0xb87e, val | 0x0600);
sys/dev/pci/if_rge.c
2936
val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc;
sys/dev/pci/if_rge.c
2937
rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4);
sys/dev/pci/if_rge.c
2939
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2940
rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00);
sys/dev/pci/if_rge.c
2942
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2943
rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00);
sys/dev/pci/if_rge.c
2945
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2946
rge_write_phy_ocp(sc, 0xb87e, val | 0x7400);
sys/dev/pci/if_rge.c
2948
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
2949
rge_write_phy_ocp(sc, 0xb87e, val | 0x3400);
sys/dev/pci/if_rge.c
2951
val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f;
sys/dev/pci/if_rge.c
2952
rge_write_phy_ocp(sc, 0xad66, val | 0x0007);
sys/dev/pci/if_rge.c
2953
val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000;
sys/dev/pci/if_rge.c
2954
rge_write_phy_ocp(sc, 0xad68, val | 0x8000);
sys/dev/pci/if_rge.c
2955
val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00;
sys/dev/pci/if_rge.c
2956
rge_write_phy_ocp(sc, 0xad68, val | 0x0500);
sys/dev/pci/if_rge.c
2957
val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f;
sys/dev/pci/if_rge.c
2958
rge_write_phy_ocp(sc, 0xad68, val | 0x0002);
sys/dev/pci/if_rge.c
2959
val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000;
sys/dev/pci/if_rge.c
2960
rge_write_phy_ocp(sc, 0xad6a, val | 0x7000);
sys/dev/pci/if_rge.c
2963
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2964
rge_write_phy_ocp(sc, 0xa438, val | 0x5400);
sys/dev/pci/if_rge.c
2965
val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0;
sys/dev/pci/if_rge.c
2966
rge_write_phy_ocp(sc, 0xa864, val | 0x00c0);
sys/dev/pci/if_rge.c
2967
val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff;
sys/dev/pci/if_rge.c
2968
rge_write_phy_ocp(sc, 0xa42c, val | 0x0002);
sys/dev/pci/if_rge.c
2970
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2971
rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
sys/dev/pci/if_rge.c
2973
val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000;
sys/dev/pci/if_rge.c
2974
rge_write_phy_ocp(sc, 0xa438, val | 0x0700);
sys/dev/pci/if_rge.c
2979
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2980
rge_write_phy_ocp(sc, 0xa438, val | 0xca00);
sys/dev/pci/if_rge.c
2982
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2983
rge_write_phy_ocp(sc, 0xa438, val | 0xb300);
sys/dev/pci/if_rge.c
2987
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2988
rge_write_phy_ocp(sc, 0xa438, val | 0xca00);
sys/dev/pci/if_rge.c
2990
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2991
rge_write_phy_ocp(sc, 0xa438, val | 0xbb00);
sys/dev/pci/if_rge.c
2997
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
2998
rge_write_phy_ocp(sc, 0xa438, val | 0x5800);
sys/dev/pci/if_rge.c
3006
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3007
rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
sys/dev/pci/if_rge.c
3014
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3015
rge_write_phy_ocp(sc, 0xa438, val | 0x0600);
sys/dev/pci/if_rge.c
3017
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3018
rge_write_phy_ocp(sc, 0xa438, val | 0x0500);
sys/dev/pci/if_rge.c
3020
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3021
rge_write_phy_ocp(sc, 0xa438, val | 0x1f00);
sys/dev/pci/if_rge.c
3023
val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f;
sys/dev/pci/if_rge.c
3024
rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006);
sys/dev/pci/if_rge.c
3029
val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70;
sys/dev/pci/if_rge.c
3030
rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500);
sys/dev/pci/if_rge.c
3033
val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700;
sys/dev/pci/if_rge.c
3034
rge_write_phy_ocp(sc, 0xa438, val | 0x0200);
sys/dev/pci/if_rge.c
3045
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3046
rge_write_phy_ocp(sc, 0xa438, val | 0x2900);
sys/dev/pci/if_rge.c
3049
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3050
rge_write_phy_ocp(sc, 0xa438, val | 0x1700);
sys/dev/pci/if_rge.c
3053
val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
sys/dev/pci/if_rge.c
3054
rge_write_phy_ocp(sc, 0xa438, val | 0x1700);
sys/dev/pci/if_rge.c
3065
uint16_t val;
sys/dev/pci/if_rge.c
3072
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
sys/dev/pci/if_rge.c
3073
rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
sys/dev/pci/if_rge.c
3075
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
sys/dev/pci/if_rge.c
3076
rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
sys/dev/pci/if_rge.c
3077
val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
sys/dev/pci/if_rge.c
3078
rge_write_phy_ocp(sc, 0xbc80, val | 0x0004);
sys/dev/pci/if_rge.c
3081
val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
sys/dev/pci/if_rge.c
3082
rge_write_phy_ocp(sc, 0xbc80, val | 0x0005);
sys/dev/pci/if_rge.c
3083
val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0;
sys/dev/pci/if_rge.c
3084
rge_write_phy_ocp(sc, 0xbc82, val | 0x0040);
sys/dev/pci/if_rge.c
3087
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
sys/dev/pci/if_rge.c
3088
rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000);
sys/dev/pci/if_rge.c
3092
val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc;
sys/dev/pci/if_rge.c
3093
rge_write_phy_ocp(sc, 0xac7e, val | 0x00b4);
sys/dev/pci/if_rge.c
3095
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3096
rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00);
sys/dev/pci/if_rge.c
3098
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3099
rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00);
sys/dev/pci/if_rge.c
3101
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3102
rge_write_phy_ocp(sc, 0xb87e, val | 0x7400);
sys/dev/pci/if_rge.c
3104
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3105
rge_write_phy_ocp(sc, 0xb87e, val | 0x3400);
sys/dev/pci/if_rge.c
3107
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3108
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
sys/dev/pci/if_rge.c
3110
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3111
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
sys/dev/pci/if_rge.c
3113
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
sys/dev/pci/if_rge.c
3114
rge_write_phy_ocp(sc, 0xb87e, val | 0xef00);
sys/dev/pci/if_rge.c
3141
mac_r25_mcu[i].reg, mac_r25_mcu[i].val);
sys/dev/pci/if_rge.c
3153
mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);
sys/dev/pci/if_rge.c
3158
mac_r25d_1_mcu[i].val);
sys/dev/pci/if_rge.c
3165
mac_r25d_1_mcu[i].val);
sys/dev/pci/if_rge.c
3172
mac_r25d_1_mcu[i].val);
sys/dev/pci/if_rge.c
3177
mac_r25d_2_mcu[i].val);
sys/dev/pci/if_rge.c
3184
mac_r25d_2_mcu[i].val);
sys/dev/pci/if_rge.c
3188
mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
sys/dev/pci/if_rge.c
3194
mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
sys/dev/pci/if_rge.c
3198
mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val);
sys/dev/pci/if_rge.c
3202
mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
sys/dev/pci/if_rge.c
3208
mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
sys/dev/pci/if_rge.c
3435
uint16_t val;
sys/dev/pci/if_rge.c
3437
val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003;
sys/dev/pci/if_rge.c
3438
val |= page;
sys/dev/pci/if_rge.c
3439
rge_write_mac_ocp(sc, 0xe446, val);
sys/dev/pci/if_rge.c
3490
rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)
sys/dev/pci/if_rge.c
3494
RGE_WRITE_4(sc, RGE_CSIDR, val);
sys/dev/pci/if_rge.c
3527
rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3532
tmp += val;
sys/dev/pci/if_rge.c
3540
uint32_t val;
sys/dev/pci/if_rge.c
3542
val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3543
RGE_WRITE_4(sc, RGE_MACOCP, val);
sys/dev/pci/if_rge.c
3549
rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3555
tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK);
sys/dev/pci/if_rge.c
3570
uint32_t val;
sys/dev/pci/if_rge.c
3573
val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3574
RGE_WRITE_4(sc, RGE_EPHYAR, val);
sys/dev/pci/if_rge.c
3578
val = RGE_READ_4(sc, RGE_EPHYAR);
sys/dev/pci/if_rge.c
3579
if (val & RGE_EPHYAR_BUSY)
sys/dev/pci/if_rge.c
3585
return (val & RGE_EPHYAR_DATA_MASK);
sys/dev/pci/if_rge.c
3591
uint16_t val;
sys/dev/pci/if_rge.c
3593
val = (reg >> 12);
sys/dev/pci/if_rge.c
3594
rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, val);
sys/dev/pci/if_rge.c
3600
rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3602
rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val);
sys/dev/pci/if_rge.c
3606
rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3617
rge_write_phy_ocp(sc, phyaddr, val);
sys/dev/pci/if_rge.c
3636
rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3642
tmp |= RGE_PHYOCP_BUSY | val;
sys/dev/pci/if_rge.c
3655
uint32_t val;
sys/dev/pci/if_rge.c
3658
val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3659
RGE_WRITE_4(sc, RGE_PHYOCP, val);
sys/dev/pci/if_rge.c
3663
val = RGE_READ_4(sc, RGE_PHYOCP);
sys/dev/pci/if_rge.c
3664
if (val & RGE_PHYOCP_BUSY)
sys/dev/pci/if_rge.c
3668
return (val & RGE_PHYOCP_DATA_MASK);
sys/dev/pci/if_rge.c
683
uint32_t rxconf, val;
sys/dev/pci/if_rge.c
730
val = rge_read_csi(sc, 0x70c) & ~0x3f000000;
sys/dev/pci/if_rge.c
731
rge_write_csi(sc, 0x70c, val | 0x27000000);
sys/dev/pci/if_rge.c
735
val = rge_read_csi(sc, 0x890) & ~0x00000001;
sys/dev/pci/if_rge.c
736
rge_write_csi(sc, 0x890, val);
sys/dev/pci/if_rge.c
742
val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL) & ~0x001c;
sys/dev/pci/if_rge.c
743
RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2);
sys/dev/pci/if_rge.c
761
val = rge_read_mac_ocp(sc, 0xe614);
sys/dev/pci/if_rge.c
762
val &= (sc->rge_type == MAC_R27) ? ~0x0f00 : ~0x0700;
sys/dev/pci/if_rge.c
764
rge_write_mac_ocp(sc, 0xe614, val | 0x0300);
sys/dev/pci/if_rge.c
766
rge_write_mac_ocp(sc, 0xe614, val | 0x0200);
sys/dev/pci/if_rge.c
768
rge_write_mac_ocp(sc, 0xe614, val | 0x0300);
sys/dev/pci/if_rge.c
770
rge_write_mac_ocp(sc, 0xe614, val | 0x0f00);
sys/dev/pci/if_rge.c
772
val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00;
sys/dev/pci/if_rge.c
773
rge_write_mac_ocp(sc, 0xe63e, val |
sys/dev/pci/if_rge.c
776
val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030;
sys/dev/pci/if_rge.c
777
rge_write_mac_ocp(sc, 0xe63e, val | 0x0020);
sys/dev/pci/if_rge.c
784
val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff;
sys/dev/pci/if_rge.c
785
rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033);
sys/dev/pci/if_rge.c
787
val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0;
sys/dev/pci/if_rge.c
788
rge_write_mac_ocp(sc, 0xeb50, val | 0x0040);
sys/dev/pci/if_rge.c
796
val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003;
sys/dev/pci/if_rge.c
797
rge_write_mac_ocp(sc, 0xea1c, val | 0x0001);
sys/dev/pci/if_rge.c
807
val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff;
sys/dev/pci/if_rge.c
808
rge_write_mac_ocp(sc, 0xd430, val | 0x045f);
sys/dev/pci/if_rge.c
833
val = rge_read_mac_ocp(sc, 0xd40c) & ~0xe038;
sys/dev/pci/if_rge.c
834
rge_write_phy_ocp(sc, 0xd40c, val | 0x8020);
sys/dev/pci/if_rge.c
867
val = rge_read_csi(sc, 0x98) & ~0x0000ff00;
sys/dev/pci/if_rge.c
868
rge_write_csi(sc, 0x98, val);
sys/dev/pci/if_rge.c
871
val = rge_read_mac_ocp(sc, 0xe092) & ~0x00ff;
sys/dev/pci/if_rge.c
872
rge_write_mac_ocp(sc, 0xe092, val | 0x0008);
sys/dev/pci/if_rge.c
977
int anar, gig, val;
sys/dev/pci/if_rge.c
988
val = rge_read_phy_ocp(sc, 0xa5d4);
sys/dev/pci/if_rge.c
991
val &= ~RGE_ADV_10000TFDX;
sys/dev/pci/if_rge.c
995
val &= ~RGE_ADV_5000TFDX;
sys/dev/pci/if_rge.c
998
val &= ~RGE_ADV_2500TFDX;
sys/dev/pci/if_rgereg.h
443
#define RGE_WRITE_4(sc, reg, val) \
sys/dev/pci/if_rgereg.h
444
bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)
sys/dev/pci/if_rgereg.h
445
#define RGE_WRITE_2(sc, reg, val) \
sys/dev/pci/if_rgereg.h
446
bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)
sys/dev/pci/if_rgereg.h
447
#define RGE_WRITE_1(sc, reg, val) \
sys/dev/pci/if_rgereg.h
448
bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)
sys/dev/pci/if_rgereg.h
457
#define RGE_SETBIT_4(sc, reg, val) \
sys/dev/pci/if_rgereg.h
458
RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
459
#define RGE_SETBIT_2(sc, reg, val) \
sys/dev/pci/if_rgereg.h
460
RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
461
#define RGE_SETBIT_1(sc, reg, val) \
sys/dev/pci/if_rgereg.h
462
RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
464
#define RGE_CLRBIT_4(sc, reg, val) \
sys/dev/pci/if_rgereg.h
465
RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
466
#define RGE_CLRBIT_2(sc, reg, val) \
sys/dev/pci/if_rgereg.h
467
RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
468
#define RGE_CLRBIT_1(sc, reg, val) \
sys/dev/pci/if_rgereg.h
469
RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
471
#define RGE_EPHY_SETBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
472
rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
474
#define RGE_EPHY_CLRBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
475
rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
477
#define RGE_PHY_SETBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
478
rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
480
#define RGE_PHY_CLRBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
481
rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
483
#define RGE_MAC_SETBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
484
rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
486
#define RGE_MAC_CLRBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
487
rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
491
uint16_t val;
sys/dev/pci/if_rgereg.h
947
uint16_t val;
sys/dev/pci/if_rgereg.h
975
uint16_t val;
sys/dev/pci/if_rtwn.c
2159
rtl8188eu_mac[i].val);
sys/dev/pci/if_rtwn.c
2165
rtl8192cu_mac[i].val);
sys/dev/pci/if_rtwn.c
2171
rtl8192ce_mac[i].val);
sys/dev/pci/if_rtwn.c
757
rtwn_pci_write_1(void *cookie, uint16_t addr, uint8_t val)
sys/dev/pci/if_rtwn.c
761
bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val);
sys/dev/pci/if_rtwn.c
765
rtwn_pci_write_2(void *cookie, uint16_t addr, uint16_t val)
sys/dev/pci/if_rtwn.c
769
val = htole16(val);
sys/dev/pci/if_rtwn.c
770
bus_space_write_2(sc->sc_st, sc->sc_sh, addr, val);
sys/dev/pci/if_rtwn.c
774
rtwn_pci_write_4(void *cookie, uint16_t addr, uint32_t val)
sys/dev/pci/if_rtwn.c
778
val = htole32(val);
sys/dev/pci/if_rtwn.c
779
bus_space_write_4(sc->sc_st, sc->sc_sh, addr, val);
sys/dev/pci/if_rtwn.c
794
uint16_t val;
sys/dev/pci/if_rtwn.c
796
val = bus_space_read_2(sc->sc_st, sc->sc_sh, addr);
sys/dev/pci/if_rtwn.c
797
return le16toh(val);
sys/dev/pci/if_rtwn.c
804
uint32_t val;
sys/dev/pci/if_rtwn.c
806
val = bus_space_read_4(sc->sc_st, sc->sc_sh, addr);
sys/dev/pci/if_rtwn.c
807
return le32toh(val);
sys/dev/pci/if_se.c
186
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_se.c
187
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val)
sys/dev/pci/if_se.c
188
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_se.c
189
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, reg, val)
sys/dev/pci/if_se.c
190
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_se.c
191
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, reg, val)
sys/dev/pci/if_se.c
206
uint32_t val;
sys/dev/pci/if_se.c
215
val = CSR_READ_4(sc, ROMInterface);
sys/dev/pci/if_se.c
216
if ((val & EI_REQ) == 0)
sys/dev/pci/if_se.c
222
sc->sc_dev.dv_xname, val);
sys/dev/pci/if_se.c
226
return (val & EI_DATA) >> EI_DATA_SHIFT;
sys/dev/pci/if_se.c
232
uint16_t val;
sys/dev/pci/if_se.c
235
val = se_read_eeprom(sc, EEPROMSignature);
sys/dev/pci/if_se.c
236
if (val == 0xffff || val == 0x0000) {
sys/dev/pci/if_se.c
238
sc->sc_dev.dv_xname, val);
sys/dev/pci/if_se.c
243
val = se_read_eeprom(sc, EEPROMMACAddr + i / 2);
sys/dev/pci/if_se.c
244
dest[i + 0] = (uint8_t)val;
sys/dev/pci/if_se.c
245
dest[i + 1] = (uint8_t)(val >> 8);
sys/dev/pci/if_se.c
319
uint32_t val;
sys/dev/pci/if_se.c
324
val = CSR_READ_4(sc, GMIIControl);
sys/dev/pci/if_se.c
325
if ((val & GMI_REQ) == 0)
sys/dev/pci/if_se.c
326
return val;
sys/dev/pci/if_se.c
337
uint32_t ctrl, val;
sys/dev/pci/if_se.c
341
val = se_miibus_cmd(sc, ctrl);
sys/dev/pci/if_se.c
342
if ((val & GMI_REQ) != 0) {
sys/dev/pci/if_se.c
347
return (val & GMI_DATA) >> GMI_DATA_SHIFT;
sys/dev/pci/if_se.c
354
uint32_t ctrl, val;
sys/dev/pci/if_se.c
358
val = se_miibus_cmd(sc, ctrl);
sys/dev/pci/if_se.c
359
if ((val & GMI_REQ) != 0) {
sys/dev/pci/if_sis.c
576
int i, val = 0;
sys/dev/pci/if_sis.c
596
val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
sys/dev/pci/if_sis.c
598
if (val == 0xFFFF)
sys/dev/pci/if_sis.c
601
return (val);
sys/dev/pci/if_sisreg.h
474
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_sisreg.h
475
bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
sys/dev/pci/if_sk.c
1963
u_int32_t val;
sys/dev/pci/if_sk.c
1966
val = sk_win_read_4(sc, SK_GPIO);
sys/dev/pci/if_sk.c
1968
val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
sys/dev/pci/if_sk.c
1970
val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
sys/dev/pci/if_sk.c
1971
sk_win_write_4(sc, SK_GPIO, val);
sys/dev/pci/if_sk.c
1993
bhack[i].val);
sys/dev/pci/if_sk.c
2409
u_int32_t val;
sys/dev/pci/if_sk.c
2424
val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
sys/dev/pci/if_sk.c
2425
if (!(val & SK_TXBMU_TX_STOP))
sys/dev/pci/if_sk.c
2436
val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
sys/dev/pci/if_sk.c
2437
if (!(val & SK_RXBMU_RX_STOP))
sys/dev/pci/if_sk.c
2447
u_int32_t val;
sys/dev/pci/if_sk.c
2450
val = sk_win_read_4(sc, SK_GPIO);
sys/dev/pci/if_sk.c
2452
val |= SK_GPIO_DIR0;
sys/dev/pci/if_sk.c
2453
val &= ~SK_GPIO_DAT0;
sys/dev/pci/if_sk.c
2455
val |= SK_GPIO_DIR2;
sys/dev/pci/if_sk.c
2456
val &= ~SK_GPIO_DAT2;
sys/dev/pci/if_sk.c
2458
sk_win_write_4(sc, SK_GPIO, val);
sys/dev/pci/if_sk.c
270
sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_sk.c
289
SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
sys/dev/pci/if_sk.c
324
u_int16_t val;
sys/dev/pci/if_sk.c
340
val = SK_YU_READ_2(sc_if, YUKON_SMICR);
sys/dev/pci/if_sk.c
341
if (val & YU_SMICR_READ_VALID)
sys/dev/pci/if_sk.c
354
val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
sys/dev/pci/if_sk.c
357
phy, reg, val));
sys/dev/pci/if_sk.c
359
return (val);
sys/dev/pci/if_sk.c
363
sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_sk.c
369
phy, reg, val));
sys/dev/pci/if_sk.c
371
SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
sys/dev/pci/if_sk.c
892
u_int32_t chunk, val;
sys/dev/pci/if_sk.c
895
val = sc->sk_rboff / sizeof(u_int64_t);
sys/dev/pci/if_sk.c
896
sc_if->sk_rx_ramstart = val;
sys/dev/pci/if_sk.c
897
val += (chunk / sizeof(u_int64_t));
sys/dev/pci/if_sk.c
898
sc_if->sk_rx_ramend = val - 1;
sys/dev/pci/if_sk.c
899
sc_if->sk_tx_ramstart = val;
sys/dev/pci/if_sk.c
900
val += (chunk / sizeof(u_int64_t));
sys/dev/pci/if_sk.c
901
sc_if->sk_tx_ramend = val - 1;
sys/dev/pci/if_sk.c
903
u_int32_t chunk, val;
sys/dev/pci/if_sk.c
906
val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
sys/dev/pci/if_sk.c
908
sc_if->sk_rx_ramstart = val;
sys/dev/pci/if_sk.c
909
val += (chunk / sizeof(u_int64_t));
sys/dev/pci/if_sk.c
910
sc_if->sk_rx_ramend = val - 1;
sys/dev/pci/if_sk.c
911
sc_if->sk_tx_ramstart = val;
sys/dev/pci/if_sk.c
912
val += (chunk / sizeof(u_int64_t));
sys/dev/pci/if_sk.c
913
sc_if->sk_tx_ramend = val - 1;
sys/dev/pci/if_skreg.h
116
#define SK_IF_WRITE_4(sc_if, skip, reg, val) \
sys/dev/pci/if_skreg.h
118
reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
sys/dev/pci/if_skreg.h
119
#define SK_IF_WRITE_2(sc_if, skip, reg, val) \
sys/dev/pci/if_skreg.h
121
reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
sys/dev/pci/if_skreg.h
122
#define SK_IF_WRITE_1(sc_if, skip, reg, val) \
sys/dev/pci/if_skreg.h
124
reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
sys/dev/pci/if_skreg.h
1396
#define SK_XM_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1398
((val) & 0xFFFF)); \
sys/dev/pci/if_skreg.h
1400
((val) >> 16) & 0xFFFF)
sys/dev/pci/if_skreg.h
1405
#define SK_XM_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1406
sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
sys/dev/pci/if_skreg.h
1412
#define SK_XM_WRITE_2(sc, reg, val) \
sys/dev/pci/if_skreg.h
1413
sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
sys/dev/pci/if_skreg.h
1438
#define SK_YU_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1439
sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
sys/dev/pci/if_skreg.h
1441
#define SK_YU_WRITE_2(sc, reg, val) \
sys/dev/pci/if_skreg.h
1442
sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
sys/dev/pci/if_skreg.h
1517
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1518
bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
sys/dev/pci/if_skreg.h
1519
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_skreg.h
1520
bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
sys/dev/pci/if_skreg.h
1521
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_skreg.h
1522
bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
sys/dev/pci/if_skvar.h
164
int val;
sys/dev/pci/if_stereg.h
446
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_stereg.h
447
bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)
sys/dev/pci/if_stereg.h
448
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_stereg.h
449
bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)
sys/dev/pci/if_stereg.h
450
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_stereg.h
451
bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)
sys/dev/pci/if_stge.c
1538
stge_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_stge.c
1541
mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
sys/dev/pci/if_stge.c
1588
stge_mii_bitbang_write(struct device *self, uint32_t val)
sys/dev/pci/if_stge.c
1592
CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
sys/dev/pci/if_stgereg.h
47
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_stgereg.h
48
bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
sys/dev/pci/if_stgereg.h
49
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_stgereg.h
50
bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
sys/dev/pci/if_stgereg.h
51
#define CSR_WRITE_1(_sc, reg, val) \
sys/dev/pci/if_stgereg.h
52
bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
sys/dev/pci/if_tl.c
313
tl_dio_write8(struct tl_softc *sc, int reg, int val)
sys/dev/pci/if_tl.c
316
CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
sys/dev/pci/if_tl.c
320
tl_dio_write16(struct tl_softc *sc, int reg, int val)
sys/dev/pci/if_tl.c
323
CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
sys/dev/pci/if_tl.c
327
tl_dio_write32(struct tl_softc *sc, int reg, int val)
sys/dev/pci/if_tl.c
330
CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
sys/dev/pci/if_tlreg.h
500
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_tlreg.h
501
bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
sys/dev/pci/if_tlreg.h
502
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_tlreg.h
503
bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
sys/dev/pci/if_tlreg.h
504
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_tlreg.h
505
bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
sys/dev/pci/if_txpreg.h
614
#define WRITE_REG(sc,reg,val) \
sys/dev/pci/if_txpreg.h
615
bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
sys/dev/pci/if_vgevar.h
100
bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
sys/dev/pci/if_vgevar.h
101
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_vgevar.h
102
bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
sys/dev/pci/if_vgevar.h
103
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_vgevar.h
104
bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
sys/dev/pci/if_vgevar.h
99
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_vmx.c
183
#define WRITE_BAR0(sc, reg, val) \
sys/dev/pci/if_vmx.c
184
bus_space_write_4((sc)->sc_iot0, (sc)->sc_ioh0, reg, val)
sys/dev/pci/if_vmx.c
185
#define WRITE_BAR1(sc, reg, val) \
sys/dev/pci/if_vmx.c
186
bus_space_write_4((sc)->sc_iot1, (sc)->sc_ioh1, reg, val)
sys/dev/pci/if_vrreg.h
543
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_vrreg.h
544
bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
sys/dev/pci/if_vrreg.h
545
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_vrreg.h
546
bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
sys/dev/pci/if_vrreg.h
547
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_vrreg.h
548
bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
sys/dev/pci/if_vte.c
137
vte_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_vte.c
142
CSR_WRITE_2(sc, VTE_MMWD, val);
sys/dev/pci/if_vte.c
162
uint16_t val;
sys/dev/pci/if_vte.c
191
val = 18 << VTE_IM_TIMER_SHIFT;
sys/dev/pci/if_vte.c
193
val = 1 << VTE_IM_TIMER_SHIFT;
sys/dev/pci/if_vte.c
195
val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT;
sys/dev/pci/if_vte.c
197
CSR_WRITE_2(sc, VTE_MRICR, val);
sys/dev/pci/if_vte.c
200
val = 18 << VTE_IM_TIMER_SHIFT;
sys/dev/pci/if_vte.c
202
val = 1 << VTE_IM_TIMER_SHIFT;
sys/dev/pci/if_vte.c
204
val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT;
sys/dev/pci/if_vte.c
206
CSR_WRITE_2(sc, VTE_MTICR, val);
sys/dev/pci/if_vtereg.h
450
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_vtereg.h
451
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_wbreg.h
385
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_wbreg.h
386
bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
sys/dev/pci/if_wbreg.h
387
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_wbreg.h
388
bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
sys/dev/pci/if_wbreg.h
389
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_wbreg.h
390
bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
sys/dev/pci/if_wpi.c
2178
uint64_t val, mod;
sys/dev/pci/if_wpi.c
2186
val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */
sys/dev/pci/if_wpi.c
2187
mod = letoh64(cmd.tstamp) % val;
sys/dev/pci/if_wpi.c
2188
cmd.binitval = htole32((uint32_t)(val - mod));
sys/dev/pci/if_wpi.c
2191
ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod)));
sys/dev/pci/if_wpi.c
526
uint32_t val;
sys/dev/pci/if_wpi.c
537
val = WPI_READ(sc, WPI_EEPROM);
sys/dev/pci/if_wpi.c
538
if (val & WPI_EEPROM_READ_VALID)
sys/dev/pci/if_wpi.c
547
*out++ = val >> 16;
sys/dev/pci/if_wpi.c
549
*out++ = val >> 24;
sys/dev/pci/if_wpireg.h
821
#define WPI_WRITE(sc, reg, val) \
sys/dev/pci/if_wpireg.h
822
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_xge.c
1042
uint64_t val;
sys/dev/pci/if_xge.c
1051
for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) {
sys/dev/pci/if_xge.c
1052
val <<= 8;
sys/dev/pci/if_xge.c
1053
val |= enm->enm_addrlo[i];
sys/dev/pci/if_xge.c
1055
PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16);
sys/dev/pci/if_xge.c
1091
uint64_t val;
sys/dev/pci/if_xge.c
1093
val = PIF_RCSR(MAC_CFG);
sys/dev/pci/if_xge.c
1096
val |= RMAC_PROM_EN;
sys/dev/pci/if_xge.c
1098
val &= ~RMAC_PROM_EN;
sys/dev/pci/if_xge.c
1100
PIF_WCSR(MAC_CFG, val);
sys/dev/pci/if_xge.c
226
#define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val)
sys/dev/pci/if_xge.c
228
#define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val)
sys/dev/pci/if_xge.c
229
#define PIF_WKEY(csr, val) pif_wkey(sc, csr, val)
sys/dev/pci/if_xge.c
232
pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
sys/dev/pci/if_xge.c
235
bus_space_write_raw_8(sc->sc_st, sc->sc_sh, csr, val);
sys/dev/pci/if_xge.c
239
lval = val&0xffffffff;
sys/dev/pci/if_xge.c
240
hval = val>>32;
sys/dev/pci/if_xge.c
255
uint64_t val;
sys/dev/pci/if_xge.c
257
val = bus_space_read_raw_8(sc->sc_st, sc->sc_sh, csr);
sys/dev/pci/if_xge.c
261
val = bus_space_read_raw_4(sc->sc_st, sc->sc_sh, csr);
sys/dev/pci/if_xge.c
264
val |= (val2 << 32);
sys/dev/pci/if_xge.c
266
val = (val << 32 | val2);
sys/dev/pci/if_xge.c
269
return (val);
sys/dev/pci/if_xge.c
273
txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
sys/dev/pci/if_xge.c
276
bus_space_write_raw_8(sc->sc_txt, sc->sc_txh, csr, val);
sys/dev/pci/if_xge.c
280
lval = val&0xffffffff;
sys/dev/pci/if_xge.c
281
hval = val>>32;
sys/dev/pci/if_xge.c
294
pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val)
sys/dev/pci/if_xge.c
300
bus_space_write_raw_8(sc->sc_st, sc->sc_sh, csr, val);
sys/dev/pci/if_xge.c
304
lval = val&0xffffffff;
sys/dev/pci/if_xge.c
305
hval = val>>32;
sys/dev/pci/if_xge.c
373
uint64_t val;
sys/dev/pci/if_xge.c
407
val = (uint64_t)0xFFFFFFFFFFFFFFFFULL;
sys/dev/pci/if_xge.c
408
val &= ~(TxF_R_SE|RxF_W_SE);
sys/dev/pci/if_xge.c
409
PIF_WCSR(SWAPPER_CTRL, val);
sys/dev/pci/if_xge.c
410
PIF_WCSR(SWAPPER_CTRL, val);
sys/dev/pci/if_xge.c
412
if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) {
sys/dev/pci/if_xge.c
414
(unsigned long long)val, SWAPPER_MAGIC);
sys/dev/pci/if_xge.c
418
if ((val = PIF_RCSR(XMSI_ADDRESS)) != SWAPPER_MAGIC) {
sys/dev/pci/if_xge.c
420
(unsigned long long)val, SWAPPER_MAGIC);
sys/dev/pci/if_xge.c
450
val = (uint64_t)0xFFFFFFFFFFFFFFFFULL;
sys/dev/pci/if_xge.c
451
val &= ~(TxF_R_SE|RxF_W_SE);
sys/dev/pci/if_xge.c
452
PIF_WCSR(SWAPPER_CTRL, val);
sys/dev/pci/if_xge.c
453
PIF_WCSR(SWAPPER_CTRL, val);
sys/dev/pci/if_xge.c
456
if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) {
sys/dev/pci/if_xge.c
458
(unsigned long long)val, SWAPPER_MAGIC);
sys/dev/pci/if_xge.c
463
if ((val = PIF_RCSR(XMSI_ADDRESS)) != SWAPPER_MAGIC) {
sys/dev/pci/if_xge.c
465
(unsigned long long)val, SWAPPER_MAGIC);
sys/dev/pci/if_xge.c
478
val = PIF_RCSR(SW_RESET);
sys/dev/pci/if_xge.c
479
val &= 0xffff00ffffffffffULL;
sys/dev/pci/if_xge.c
480
PIF_WCSR(SW_RESET,val);
sys/dev/pci/if_xge.c
485
val = PIF_RCSR(SW_RESET);
sys/dev/pci/if_xge.c
486
val &= 0xffffff00ffffffffULL;
sys/dev/pci/if_xge.c
487
PIF_WCSR(SW_RESET, val);
sys/dev/pci/if_xge.c
495
val = PIF_RCSR(ADAPTER_STATUS);
sys/dev/pci/if_xge.c
496
if (!(val & RIC_RUNNING))
sys/dev/pci/if_xge.c
519
val = PIF_RCSR(RMAC_ADDR_DATA0_MEM);
sys/dev/pci/if_xge.c
521
enaddr[i] = (uint8_t)(val >> (56 - (8*i)));
sys/dev/pci/if_xge.c
540
val = PIF_RCSR(TX_FIFO_P0);
sys/dev/pci/if_xge.c
541
val |= TX_FIFO_ENABLE;
sys/dev/pci/if_xge.c
542
PIF_WCSR(TX_FIFO_P0, val);
sys/dev/pci/if_xge.c
604
val = RING_MODE_1;
sys/dev/pci/if_xge.c
606
val = RING_MODE_3;
sys/dev/pci/if_xge.c
608
val = RING_MODE_5;
sys/dev/pci/if_xge.c
610
PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val);
sys/dev/pci/if_xge.c
634
val = PIF_RCSR(MC_RLDRAM_MRS);
sys/dev/pci/if_xge.c
635
val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE;
sys/dev/pci/if_xge.c
636
PIF_WCSR(MC_RLDRAM_MRS, val);
sys/dev/pci/if_xge.c
732
uint64_t val;
sys/dev/pci/if_xge.c
735
val = PIF_RCSR(ADAPTER_CONTROL);
sys/dev/pci/if_xge.c
736
val |= ADAPTER_EN;
sys/dev/pci/if_xge.c
737
PIF_WCSR(ADAPTER_CONTROL, val);
sys/dev/pci/if_xge.c
740
val = PIF_RCSR(ADAPTER_CONTROL);
sys/dev/pci/if_xge.c
741
val |= LED_ON;
sys/dev/pci/if_xge.c
742
PIF_WCSR(ADAPTER_CONTROL, val);
sys/dev/pci/if_xge.c
752
uint64_t val;
sys/dev/pci/if_xge.c
769
val = PIF_RCSR(ADAPTER_STATUS);
sys/dev/pci/if_xge.c
770
if ((val & QUIESCENT) != QUIESCENT) {
sys/dev/pci/if_xge.c
775
val = (val & QUIESCENT) ^ QUIESCENT;
sys/dev/pci/if_xge.c
777
bitmask_snprintf(val, QUIESCENT_BMSK, buf, sizeof buf);
sys/dev/pci/if_xge.c
786
val = PIF_RCSR(RX_PA_CFG);
sys/dev/pci/if_xge.c
787
val &= ~STRIP_VLAN_TAG;
sys/dev/pci/if_xge.c
788
PIF_WCSR(RX_PA_CFG, val);
sys/dev/pci/if_xge.c
795
val = PIF_RCSR(ADAPTER_CONTROL);
sys/dev/pci/if_xge.c
796
val |= EOI_TX_ON;
sys/dev/pci/if_xge.c
797
PIF_WCSR(ADAPTER_CONTROL, val);
sys/dev/pci/if_xge.c
831
uint64_t val;
sys/dev/pci/if_xge.c
836
val = PIF_RCSR(ADAPTER_CONTROL);
sys/dev/pci/if_xge.c
837
val &= ~ADAPTER_EN;
sys/dev/pci/if_xge.c
838
PIF_WCSR(ADAPTER_CONTROL, val);
sys/dev/pci/if_xge.c
852
uint64_t val;
sys/dev/pci/if_xge.c
855
val = PIF_RCSR(GENERAL_INT_STATUS);
sys/dev/pci/if_xge.c
856
if (val == 0)
sys/dev/pci/if_xge.c
859
PIF_WCSR(GENERAL_INT_STATUS, val);
sys/dev/pci/if_xge.c
861
if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) {
sys/dev/pci/if_xge.c
870
val = PIF_RCSR(ADAPTER_STATUS);
sys/dev/pci/if_xge.c
871
if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0)
sys/dev/pci/if_xge.c
875
if ((val = PIF_RCSR(TX_TRAFFIC_INT)))
sys/dev/pci/if_xge.c
876
PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */
sys/dev/pci/if_xge.c
906
if ((val = PIF_RCSR(RX_TRAFFIC_INT)))
sys/dev/pci/if_xge.c
907
PIF_WCSR(RX_TRAFFIC_INT, val);
sys/dev/pci/if_xge.c
940
val = rxd->rxd_control1;
sys/dev/pci/if_xge.c
956
if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_IPv4)
sys/dev/pci/if_xge.c
958
if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP)
sys/dev/pci/if_xge.c
960
if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP)
sys/dev/pci/if_xge.c
964
if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_VLAN) {
sys/dev/pci/ixgbe.h
354
uint16_t *val, bool lock);
sys/dev/pci/ixgbe.h
356
uint16_t *val);
sys/dev/pci/ixgbe.h
358
uint16_t reg, uint16_t *val);
sys/dev/pci/ixgbe.h
360
uint16_t val, bool lock);
sys/dev/pci/ixgbe.h
362
uint16_t val);
sys/dev/pci/ixgbe.h
364
uint16_t reg, uint16_t val);
sys/dev/pci/ixgbe_82598.c
1083
int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val)
sys/dev/pci/ixgbe_82598.c
1094
*val = (uint8_t)atlas_ctl;
sys/dev/pci/ixgbe_82598.c
1107
int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val)
sys/dev/pci/ixgbe_82598.c
1113
atlas_ctl = (reg << 8) | val;
sys/dev/pci/ixgbe_82598.c
74
int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val);
sys/dev/pci/ixgbe_82598.c
75
int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val);
sys/dev/pci/ixgbe_82599.c
1214
uint8_t *val)
sys/dev/pci/ixgbe_82599.c
1225
*val = (uint8_t)core_ctl;
sys/dev/pci/ixgbe_82599.c
1239
uint8_t val)
sys/dev/pci/ixgbe_82599.c
1245
core_ctl = (reg << 8) | val;
sys/dev/pci/ixgbe_82599.c
70
uint8_t *val);
sys/dev/pci/ixgbe_82599.c
72
uint8_t val);
sys/dev/pci/ixgbe_phy.c
114
uint16_t reg, uint16_t *val,
sys/dev/pci/ixgbe_phy.c
165
*val = (high_bits << 8) | low_bits;
sys/dev/pci/ixgbe_phy.c
192
uint16_t reg, uint16_t *val)
sys/dev/pci/ixgbe_phy.c
194
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
sys/dev/pci/ixgbe_phy.c
207
uint16_t reg, uint16_t *val)
sys/dev/pci/ixgbe_phy.c
209
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
sys/dev/pci/ixgbe_phy.c
224
uint16_t reg, uint16_t val, bool lock)
sys/dev/pci/ixgbe_phy.c
234
csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
sys/dev/pci/ixgbe_phy.c
235
csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
sys/dev/pci/ixgbe_phy.c
251
if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
sys/dev/pci/ixgbe_phy.c
254
if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
sys/dev/pci/ixgbe_phy.c
288
uint8_t addr, uint16_t reg, uint16_t val)
sys/dev/pci/ixgbe_phy.c
290
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
sys/dev/pci/ixgbe_phy.c
304
uint8_t addr, uint16_t reg, uint16_t val)
sys/dev/pci/ixgbe_phy.c
306
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
sys/dev/pci/ixgbe_type.h
4040
int32_t (*read_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val);
sys/dev/pci/ixgbe_type.h
4041
int32_t (*write_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val);
sys/dev/pci/ixgbe_type.h
4058
int32_t (*read_link)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val);
sys/dev/pci/ixgbe_type.h
4060
uint16_t *val);
sys/dev/pci/ixgbe_type.h
4061
int32_t (*write_link)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val);
sys/dev/pci/ixgbe_type.h
4063
uint16_t val);
sys/dev/pci/pccbb.c
1016
pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val)
sys/dev/pci/pccbb.c
1022
val);
sys/dev/pci/pccbb.c
94
#define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
sys/dev/pci/pccbb.c
950
int retval = 0, val;
sys/dev/pci/pccbb.c
957
val = (*pil->pil_func)(pil->pil_arg);
sys/dev/pci/pccbb.c
958
if (val != 0)
sys/dev/pci/pccbb.c
963
if (retval == 0 || val != 0)
sys/dev/pci/pccbb.c
964
retval = val;
sys/dev/pci/pci_subr.c
362
if (class == classp->val)
sys/dev/pci/pci_subr.c
369
if (subclass == subclassp->val)
sys/dev/pci/pci_subr.c
57
int val; /* as wide as pci_{,sub}class_t */
sys/dev/pci/pciide.c
145
pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val)
sys/dev/pci/pciide.c
151
pcival |= (val << ((reg & 0x03) * 8));
sys/dev/pci/pciide.c
1972
pciide_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
sys/dev/pci/pciide.c
1975
IDEDMA_CMD(chan), val);
sys/dev/pci/pciide.c
1986
pciide_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
sys/dev/pci/pciide.c
1989
IDEDMA_CTL(chan), val);
sys/dev/pci/pciide.c
1993
pciide_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
sys/dev/pci/pciide.c
1996
IDEDMA_TBL(chan), val);
sys/dev/pci/pciide.c
4165
u_int16_t val;
sys/dev/pci/pciide.c
4206
val = pciide_pci_read(pc, pa, off) & ~0x3f;
sys/dev/pci/pciide.c
4208
val |= udma2_tbl[drvp->UDMA_mode];
sys/dev/pci/pciide.c
4210
val |= udma_tbl[drvp->UDMA_mode];
sys/dev/pci/pciide.c
4211
pciide_pci_write(pc, pa, off, val);
sys/dev/pci/pciide.c
4216
val = dma_tbl[drvp->DMA_mode];
sys/dev/pci/pciide.c
4217
pciide_pci_write(pc, pa, off, val & 0xff);
sys/dev/pci/pciide.c
4218
pciide_pci_write(pc, pa, off, val >> 8);
sys/dev/pci/pciide.c
4223
val = pio_tbl[drvp->PIO_mode];
sys/dev/pci/pciide.c
4224
pciide_pci_write(pc, pa, off, val & 0xff);
sys/dev/pci/pciide.c
4225
pciide_pci_write(pc, pa, off, val >> 8);
sys/dev/pci/pciide.c
4818
sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/pci/pciide.c
4826
sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
sys/dev/pci/pciide.c
4830
0, val);
sys/dev/pci/pciide.c
4843
sii3114_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
sys/dev/pci/pciide.c
4848
sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, val);
sys/dev/pci/pciide.c
4861
sii3114_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
sys/dev/pci/pciide.c
4866
sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0, val);
sys/dev/pci/pciide.c
4870
sii3114_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
sys/dev/pci/pciide.c
4875
sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val);
sys/dev/pci/pciide.c
7183
u_int8_t val;
sys/dev/pci/pciide.c
7189
val = bus_space_read_1(ps->regs[chp->channel].cmd_iot,
sys/dev/pci/pciide.c
7191
return (val);
sys/dev/pci/pciide.c
7196
pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/pci/pciide.c
7204
ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
sys/dev/pci/pciide.c
7208
0, val);
sys/dev/pci/pciide.c
7616
svwsata_dmacmd_write(struct pciide_softc *sc, int chan, u_int8_t val)
sys/dev/pci/pciide.c
7619
(chan << 8) + SVWSATA_DMA + IDEDMA_CMD(0), val);
sys/dev/pci/pciide.c
7630
svwsata_dmactl_write(struct pciide_softc *sc, int chan, u_int8_t val)
sys/dev/pci/pciide.c
7633
(chan << 8) + SVWSATA_DMA + IDEDMA_CTL(0), val);
sys/dev/pci/pciide.c
7637
svwsata_dmatbl_write(struct pciide_softc *sc, int chan, u_int32_t val)
sys/dev/pci/pciide.c
7640
(chan << 8) + SVWSATA_DMA + IDEDMA_TBL(0), val);
sys/dev/pci/pciide.c
7805
svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/pci/pciide.c
7809
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7812
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7817
svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val)
sys/dev/pci/pciide.c
7821
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7824
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide_acer_reg.h
70
#define ACER_FTH_VAL(chan, drv, val) \
sys/dev/pci/pciide_acer_reg.h
71
(((val) & 0x3) << ((drv) * 4 + (chan) * 8))
sys/dev/pci/pciide_acer_reg.h
72
#define ACER_FTH_OPL(chan, drv, val) \
sys/dev/pci/pciide_acer_reg.h
73
(((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
sys/dev/pci/pciide_acer_reg.h
76
#define ACER_UDMA_TIM(chan, drv, val) \
sys/dev/pci/pciide_acer_reg.h
77
(((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
sys/dev/pci/pciide_rdc_reg.h
37
#define RDCIDE_PATR_SETUP(val, chan) (((val) << 12) << ((chan) * 16))
sys/dev/pci/pciide_rdc_reg.h
39
#define RDCIDE_PATR_HOLD(val, chan) (((val) << 8) << ((chan) * 16))
sys/dev/pci/pciide_rdc_reg.h
48
#define RDCIDE_PSD1ATR_SETUP(val, chan) (((val) << 2) << (chan * 4))
sys/dev/pci/pciide_rdc_reg.h
50
#define RDCIDE_PSD1ATR_HOLD(val, chan) (((val) << 0) << (chan * 4))
sys/dev/pci/pciide_rdc_reg.h
59
#define RDCIDE_UDCCR_TIM(val, chan, drv) (((val) << ((drv) * 4)) << (chan * 8))
sys/dev/pci/pciide_rdc_reg.h
67
#define RDCIDE_IIOCR_CLK(val, chan, drv) (((val) << drv) << (chan * 2))
sys/dev/pci/pciide_sii3112_reg.h
369
ba5_write_4_ind(struct pciide_softc *sc, pcireg_t reg, uint32_t val)
sys/dev/pci/pciide_sii3112_reg.h
375
pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val);
sys/dev/pci/pciide_sii3112_reg.h
380
ba5_write_4(struct pciide_softc *sc, bus_size_t reg, uint32_t val)
sys/dev/pci/pciide_sii3112_reg.h
385
bus_space_write_4(sl->ba5_st, sl->ba5_sh, reg, val);
sys/dev/pci/pciide_sii3112_reg.h
387
ba5_write_4_ind(sc, reg, val);
sys/dev/pci/pciide_sii3112_reg.h
390
#define BA5_WRITE_4(sc, chan, reg, val) \
sys/dev/pci/pciide_sii3112_reg.h
391
ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
sys/dev/pci/pciidevar.h
130
#define PCIIDE_DMACMD_WRITE(sc, chan, val) \
sys/dev/pci/pciidevar.h
131
(sc)->sc_dmacmd_write((sc), (chan), (val))
sys/dev/pci/pciidevar.h
134
#define PCIIDE_DMACTL_WRITE(sc, chan, val) \
sys/dev/pci/pciidevar.h
135
(sc)->sc_dmactl_write((sc), (chan), (val))
sys/dev/pci/pciidevar.h
136
#define PCIIDE_DMATBL_WRITE(sc, chan, val) \
sys/dev/pci/pciidevar.h
137
(sc)->sc_dmatbl_write((sc), (chan), (val))
sys/dev/pci/pcscp.c
91
#define PCSCP_WRITE_REG(sc, reg, val) \
sys/dev/pci/pcscp.c
92
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val))
sys/dev/pci/piixpm.c
129
u_int16_t val, smb0en;
sys/dev/pci/piixpm.c
170
val = bus_space_read_1(sc->sc_iot, ioh, 1);
sys/dev/pci/piixpm.c
171
smb0en = val & AMDFCH41_SMBUS_EN;
sys/dev/pci/piixpm.c
175
val = bus_space_read_1(sc->sc_iot, ioh, 1) << 8;
sys/dev/pci/piixpm.c
176
base = val;
sys/dev/pci/piixpm.c
184
val = bus_space_read_1(sc->sc_iot, ioh, 1);
sys/dev/pci/piixpm.c
188
val |= (bus_space_read_1(sc->sc_iot, ioh, 1) << 8);
sys/dev/pci/piixpm.c
189
smb0en = val & SB800_SMB0EN_EN;
sys/dev/pci/piixpm.c
190
base = val & SB800_SMB0EN_BASE_MASK;
sys/dev/pci/piixpm.c
194
val = bus_space_read_1(sc->sc_iot, ioh, 1);
sys/dev/pci/piixpm.c
195
if (val & SB800_SMB0SELEN_EN) {
sys/dev/pci/sdhc_pci.c
265
sdhc_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint8_t val)
sys/dev/pci/sdhc_pci.c
271
tmp |= (val << ((reg & 0x3) * 8));
sys/dev/pci/sv.c
1086
int val;
sys/dev/pci/sv.c
1094
val = (cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] * SV_REC_GAIN_MASK)
sys/dev/pci/sv.c
1099
reg |= val;
sys/dev/pci/sv.c
1104
reg |= val;
sys/dev/pci/sv.c
1147
int val;
sys/dev/pci/sv.c
1179
val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
sys/dev/pci/sv.c
1182
cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = val;
sys/dev/pci/sv.c
1187
val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
sys/dev/pci/sv.c
1188
cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = val;
sys/dev/pci/sv.c
1190
cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = val;
sys/dev/pci/sv.c
173
sv_write(struct sv_softc *sc, u_int8_t reg, u_int8_t val)
sys/dev/pci/sv.c
175
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/pci/sv.c
199
sv_write_indirect(struct sv_softc *sc, u_int8_t reg, u_int8_t val)
sys/dev/pci/sv.c
217
sv_write (sc, SV_CODEC_IDATA, val);
sys/dev/pci/sv.c
558
u_int32_t mode, val;
sys/dev/pci/sv.c
599
val = p->sample_rate * 65536 / 48000;
sys/dev/pci/sv.c
601
sv_write_indirect(sc, SV_PCM_SAMPLE_RATE_0, (val & 0xff));
sys/dev/pci/sv.c
602
sv_write_indirect(sc, SV_PCM_SAMPLE_RATE_1, (val >> 8));
sys/dev/pci/tga.c
1434
tga_ramdac_wr(void *v, u_int btreg, u_int8_t val)
sys/dev/pci/tga.c
1441
TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
sys/dev/pci/tga.c
1446
tga2_ramdac_wr(void *v, u_int btreg, u_int8_t val)
sys/dev/pci/tga.c
1456
bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
sys/dev/pci/tga.c
1486
tga_bt463_wr(void *v, u_int btreg, u_int8_t val)
sys/dev/pci/tga.c
1501
TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
sys/dev/pci/tga.c
1503
TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
sys/dev/pci/tga.c
1505
TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
sys/dev/pci/tgavar.h
144
#define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
sys/dev/pci/tgavar.h
145
(reg) << 2, (val))
sys/dev/pci/tgavar.h
148
#define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
sys/dev/pci/tgavar.h
151
(val))
sys/dev/pci/viapm.c
682
val_to_uK(unsigned int val)
sys/dev/pci/viapm.c
684
int i = val / 4;
sys/dev/pci/viapm.c
685
int j = val % 4;
sys/dev/pci/viapm.c
698
val_to_rpm(unsigned int val, int div)
sys/dev/pci/viapm.c
700
if (val == 0)
sys/dev/pci/viapm.c
703
return 1350000 / val / div;
sys/dev/pci/viapm.c
707
val_to_uV(unsigned int val, int index)
sys/dev/pci/viapm.c
714
return (25LL * val + 133) * mult[index] / 2628;
sys/dev/pci/virtio_pci.c
191
uint64_t val;
sys/dev/pci/virtio_pci.c
194
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off);
sys/dev/pci/virtio_pci.c
197
val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
sys/dev/pci/virtio_pci.c
200
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
sys/dev/pci/virtio_pci.c
203
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/pci/virtio_pci.c
205
val <<= 32;
sys/dev/pci/virtio_pci.c
206
val += bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
sys/dev/pci/virtio_pci.c
209
return val;
sys/dev/pci/virtio_pci.c
215
#define CWRITE(sc, memb, val) \
sys/dev/pci/virtio_pci.c
222
__func__, __LINE__, off, size, (unsigned long long)val); \
sys/dev/pci/virtio_pci.c
225
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val); \
sys/dev/pci/virtio_pci.c
228
bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val); \
sys/dev/pci/virtio_pci.c
231
bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); \
sys/dev/pci/virtio_pci.c
235
(val) & 0xffffffff); \
sys/dev/pci/virtio_pci.c
237
(off) + sizeof(uint32_t), (uint64_t)(val) >> 32); \
sys/dev/pci/xhci_pci.c
101
pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val);
sys/dev/pci/xhci_pci.c
102
val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN);
sys/dev/pci/xhci_pci.c
104
psc->sc.sc_bus.bdev.dv_xname, val));
sys/dev/pci/xhci_pci.c
110
val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PRM);
sys/dev/pci/xhci_pci.c
112
"0x%08x\n", psc->sc.sc_bus.bdev.dv_xname, val));
sys/dev/pci/xhci_pci.c
114
pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val);
sys/dev/pci/xhci_pci.c
115
val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR);
sys/dev/pci/xhci_pci.c
117
psc->sc.sc_bus.bdev.dv_xname, val));
sys/dev/pci/xhci_pci.c
91
pcireg_t val;
sys/dev/pci/xhci_pci.c
97
val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM);
sys/dev/pci/xhci_pci.c
99
psc->sc.sc_bus.bdev.dv_xname, val));
sys/dev/pckbc/pckbd.c
1251
int val;
sys/dev/pckbc/pckbd.c
1254
val = pckbc_poll_data(t->t_kbctag, t->t_kbcslot);
sys/dev/pckbc/pckbd.c
1255
if (val == -1)
sys/dev/pckbc/pckbd.c
1258
val = pckbd_scancode_translate(t, val);
sys/dev/pckbc/pckbd.c
1259
if (val == 0)
sys/dev/pckbc/pckbd.c
1262
if (pckbd_decode(t, val, type, data))
sys/dev/pckbc/pms.c
1001
synaptics_query(struct pms_softc *sc, int query, int *val)
sys/dev/pckbc/pms.c
1009
if (val)
sys/dev/pckbc/pms.c
1010
*val = (resp[0] << 16) | (resp[1] << 8) | resp[2];
sys/dev/pcmcia/cfxga.c
172
#define cfxga_write_1(sc, addr, val) \
sys/dev/pcmcia/cfxga.c
174
(sc)->sc_offset + (addr), (val))
sys/dev/pcmcia/cfxga.c
175
#define cfxga_write_2(sc, addr, val) \
sys/dev/pcmcia/cfxga.c
177
(sc)->sc_offset + (addr), (val))
sys/dev/pcmcia/if_malovar.h
27
#define MALO_WRITE_1(sc, reg, val) \
sys/dev/pcmcia/if_malovar.h
28
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/pcmcia/if_malovar.h
29
#define MALO_WRITE_2(sc, reg, val) \
sys/dev/pcmcia/if_malovar.h
30
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/pcmcia/pcmcia.c
79
pcmcia_ccr_write(struct pcmcia_function *pf, int ccr, int val)
sys/dev/pcmcia/pcmcia.c
84
pf->pf_ccr_offset + ccr, val);
sys/dev/pv/hypervic.c
1127
hv_kvop(void *arg, int op, char *key, char *val, size_t vallen)
sys/dev/pv/hypervic.c
1133
char *vp = val;
sys/dev/pv/hypervic.c
1143
if (val + vallen < vp + HV_KVP_MAX_KEY_SIZE / 2)
sys/dev/pv/hypervic.c
1147
if (strlcat(val, "\n", vallen) >= vallen)
sys/dev/pv/hypervic.c
1152
if (vp > val)
sys/dev/pv/hypervic.c
1159
error = kvp_pool_update(kvpl, key, val, vallen,
sys/dev/pv/hypervic.c
1162
error = kvp_pool_insert(kvpl, key, val, vallen,
sys/dev/pv/hypervic.c
1167
error = kvp_pool_extract(kvpl, key, val, vallen);
sys/dev/pv/hypervic.c
543
kvp_pool_insert(struct kvp_pool *kvpl, const char *key, const char *val,
sys/dev/pv/hypervic.c
570
strlcpy(kpe->kpe_val, val, HV_KVP_MAX_KEY_SIZE / 2);
sys/dev/pv/hypervic.c
572
memcpy(kpe->kpe_val, val, vallen);
sys/dev/pv/hypervic.c
584
kvp_pool_update(struct kvp_pool *kvpl, const char *key, const char *val,
sys/dev/pv/hypervic.c
605
strlcpy(kpe->kpe_val, val, HV_KVP_MAX_KEY_SIZE / 2);
sys/dev/pv/hypervic.c
607
memcpy(kpe->kpe_val, val, vallen);
sys/dev/pv/hypervic.c
616
const char *val, uint32_t vallen, uint32_t valtype)
sys/dev/pv/hypervic.c
645
copyin_utf16le(kpe->kpe_val, val, HV_KVP_MAX_VAL_SIZE / 2, vallen);
sys/dev/pv/hypervic.c
655
uint32_t *keylen, char *val, uint32_t *vallen, uint32_t *valtype)
sys/dev/pv/hypervic.c
672
*vallen = copyout_utf16le(val, kpe->kpe_val, HV_KVP_MAX_VAL_SIZE,
sys/dev/pv/hypervic.c
707
kvp_pool_extract(struct kvp_pool *kvpl, const char *key, char *val,
sys/dev/pv/hypervic.c
728
strlcpy(val, kpe->kpe_val, HV_KVP_MAX_VAL_SIZE / 2);
sys/dev/pv/hypervic.c
731
snprintf(val, HV_KVP_MAX_VAL_SIZE / 2, "%u",
sys/dev/pv/hypervic.c
735
snprintf(val, HV_KVP_MAX_VAL_SIZE / 2, "%llu",
sys/dev/pv/pvclock.c
63
uint64_t val;
sys/dev/pv/pvclock.c
65
"lock cmpxchg8b %1" : "=&A" (val) : "m" (*ptr));
sys/dev/pv/pvclock.c
66
return val;
sys/dev/pv/xbf.c
909
char val[32];
sys/dev/pv/xbf.c
913
if ((error = xs_getprop(sc->sc_parent, sc->sc_backend, prop, val,
sys/dev/pv/xbf.c
914
sizeof(val))) != 0)
sys/dev/pv/xbf.c
916
snprintf(sc->sc_prod, sizeof(sc->sc_prod), "%s", val);
sys/dev/pv/xbf.c
919
if ((error = xs_getprop(sc->sc_parent, sc->sc_backend, prop, val,
sys/dev/pv/xbf.c
920
sizeof(val))) != 0)
sys/dev/pv/xbf.c
922
snprintf(sc->sc_prod, sizeof(sc->sc_prod), "%s %s", sc->sc_prod, val);
sys/dev/pv/xenstore.c
908
unsigned long long *val)
sys/dev/pv/xenstore.c
922
*val = atoull(buf, &error);
sys/dev/pv/xenstore.c
933
unsigned long long val)
sys/dev/pv/xenstore.c
938
ret = snprintf(buf, sizeof(buf), "%llu", val);
sys/dev/rnd.c
177
add_event_data(u_int val)
sys/dev/rnd.c
185
rep->re_val += val;
sys/dev/rnd.c
189
enqueue_randomness(u_int val)
sys/dev/rnd.c
191
add_event_data(val);
sys/dev/rnd.c
512
_rs_random_u32(u_int32_t *val)
sys/dev/rnd.c
514
_rs_stir_if_needed(sizeof(*val));
sys/dev/rnd.c
515
if (rs_have < sizeof(*val))
sys/dev/rnd.c
517
memcpy(val, rs_buf + sizeof(rs_buf) - rs_have, sizeof(*val));
sys/dev/rnd.c
518
memset(rs_buf + sizeof(rs_buf) - rs_have, 0, sizeof(*val));
sys/dev/rnd.c
519
rs_have -= sizeof(*val);
sys/dev/sbus/be.c
1235
int val = 0, i;
sys/dev/sbus/be.c
1250
val |= (be_tcvr_read_bit(sc, phy) << i);
sys/dev/sbus/be.c
1256
return (val);
sys/dev/sbus/be.c
1260
be_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/sbus/be.c
1278
be_tcvr_write_bit(sc, phy, (val >> i) & 1);
sys/dev/sbus/bwtwo.c
94
#define FBC_WRITE(sc, reg, val) \
sys/dev/sbus/bwtwo.c
95
bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
sys/dev/sbus/cgsixreg.h
314
#define BT_WRITE(sc, reg, val) \
sys/dev/sbus/cgsixreg.h
315
bus_space_write_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), (val))
sys/dev/sbus/cgthree.c
116
#define FBC_WRITE(sc, reg, val) \
sys/dev/sbus/cgthree.c
117
bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
sys/dev/sbus/cgthree.c
75
#define BT_WRITE(sc, reg, val) \
sys/dev/sbus/cgthree.c
76
bus_space_write_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
sys/dev/sbus/if_le.c
103
bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val);
sys/dev/sbus/if_le.c
96
le_sbus_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
sys/dev/sbus/if_le_lebuffer.c
100
le_lebuffer_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
sys/dev/sbus/if_le_lebuffer.c
107
bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val);
sys/dev/sbus/if_le_ledma.c
111
le_ledma_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
sys/dev/sbus/if_le_ledma.c
118
bus_space_write_2(lesc->sc_bustag, lesc->sc_reg, LEREG1_RDP, val);
sys/dev/sbus/mgx.c
326
mgx_write_1(vaddr_t regs, uint offs, uint8_t val)
sys/dev/sbus/mgx.c
329
*(volatile uint8_t *)(regs + offs) = val;
sys/dev/sbus/mgx.c
331
*(volatile uint8_t *)(regs + (offs ^ 3)) = val;
sys/dev/sbus/mgx.c
336
mgx_write_4(vaddr_t regs, uint offs, uint32_t val)
sys/dev/sbus/mgx.c
338
*(volatile uint32_t *)(regs + offs) = val;
sys/dev/sbus/spif.c
952
stty_write_ccr(struct spif_softc *sc, u_int8_t val)
sys/dev/sbus/spif.c
960
STC_WRITE(sc, STC_CCR, val);
sys/dev/sdmmc/if_bwfm_sdio.c
980
bwfm_sdio_dev_write(struct bwfm_sdio_softc *sc, uint32_t reg, uint32_t val)
sys/dev/sdmmc/if_bwfm_sdio.c
984
bwfm_sdio_write_4(sc, core->co_base + reg, val);
sys/dev/sdmmc/if_bwfm_sdio.c
995
bwfm_sdio_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)
sys/dev/sdmmc/if_bwfm_sdio.c
998
bwfm_sdio_write_4(sc, reg, val);
sys/dev/sdmmc/sdhc.c
79
#define HWRITE1(hp, reg, val) \
sys/dev/sdmmc/sdhc.c
80
sdhc_write_1((hp), (reg), (val))
sys/dev/sdmmc/sdhc.c
81
#define HWRITE2(hp, reg, val) \
sys/dev/sdmmc/sdhc.c
82
sdhc_write_2((hp), (reg), (val))
sys/dev/sdmmc/sdhc.c
83
#define HWRITE4(hp, reg, val) \
sys/dev/sdmmc/sdhc.c
84
bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
sys/dev/spdmem.c
356
uint8_t val;
sys/dev/spdmem.c
359
val = spdmem_read(sc, j);
sys/dev/spdmem.c
360
crc = crc ^ val << 8;
sys/dev/spdmem.c
854
uint8_t i, val, type;
sys/dev/spdmem.c
865
val = spdmem_read(sc, 63);
sys/dev/spdmem.c
867
if (cksum == 0 || (cksum & 0xff) != val) {
sys/dev/tc/asc.c
89
asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
sys/dev/tc/asc.c
94
reg * sizeof(u_int32_t), val);
sys/dev/tc/bba.c
585
bba_codec_iwrite(struct am7930_softc *sc, int reg, uint8_t val)
sys/dev/tc/bba.c
587
DPRINTF(("bba_codec_iwrite(): sc=%p, reg=%02x, val=%02x\n", sc, reg, val));
sys/dev/tc/bba.c
589
bba_codec_dwrite(sc, AM7930_DREG_DR, val);
sys/dev/tc/bba.c
594
bba_codec_iwrite16(struct am7930_softc *sc, int reg, uint16_t val)
sys/dev/tc/bba.c
596
DPRINTF(("bba_codec_iwrite16(): sc=%p, reg=%02x, val=%04x\n", sc, reg, val));
sys/dev/tc/bba.c
598
bba_codec_dwrite(sc, AM7930_DREG_DR, val);
sys/dev/tc/bba.c
599
bba_codec_dwrite(sc, AM7930_DREG_DR, val >> 8);
sys/dev/tc/bba.c
607
uint8_t val;
sys/dev/tc/bba.c
611
val = bba_codec_dread(sc, AM7930_DREG_DR);
sys/dev/tc/bba.c
613
DPRINTF(("read 0x%02x (%d)\n", val, val));
sys/dev/tc/bba.c
615
return val;
sys/dev/tc/bba.c
621
uint16_t val;
sys/dev/tc/bba.c
625
val = bba_codec_dread(sc, AM7930_DREG_DR);
sys/dev/tc/bba.c
626
val |= bba_codec_dread(sc, AM7930_DREG_DR) << 8;
sys/dev/tc/bba.c
628
return val;
sys/dev/tc/bba.c
634
bba_codec_dwrite(struct am7930_softc *asc, int reg, uint8_t val)
sys/dev/tc/bba.c
639
bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, reg << 2, val << 8);
sys/dev/tc/bba.c
641
bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, reg << 6, val);
sys/dev/tc/tcds.c
361
tcds_intrnull(void *val)
sys/dev/tc/tcds.c
365
(u_long)val);
sys/dev/tc/zs_ioasic.c
535
unsigned val;
sys/dev/tc/zs_ioasic.c
540
val = (zc->zc_csr >> 8) & 0xff;
sys/dev/tc/zs_ioasic.c
543
return (val);
sys/dev/tc/zs_ioasic.c
547
zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
sys/dev/tc/zs_ioasic.c
554
zc->zc_csr = val << 8;
sys/dev/tc/zs_ioasic.c
563
unsigned val;
sys/dev/tc/zs_ioasic.c
565
val = (zc->zc_csr >> 8) & 0xff;
sys/dev/tc/zs_ioasic.c
568
return (val);
sys/dev/tc/zs_ioasic.c
572
zs_write_csr(struct zs_chanstate *cs, uint8_t val)
sys/dev/tc/zs_ioasic.c
576
zc->zc_csr = val << 8;
sys/dev/tc/zs_ioasic.c
585
unsigned val;
sys/dev/tc/zs_ioasic.c
587
val = (zc->zc_data) >> 8 & 0xff;
sys/dev/tc/zs_ioasic.c
590
return (val);
sys/dev/tc/zs_ioasic.c
594
zs_write_data(struct zs_chanstate *cs, uint8_t val)
sys/dev/tc/zs_ioasic.c
598
zc->zc_data = val << 8;
sys/dev/usb/dwc2/dwc2_core.c
1002
val = HCFG_FSLSPCLKSEL_48_MHZ;
sys/dev/usb/dwc2/dwc2_core.c
1005
val = HCFG_FSLSPCLKSEL_30_60_MHZ;
sys/dev/usb/dwc2/dwc2_core.c
1008
dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
sys/dev/usb/dwc2/dwc2_core.c
1011
hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
sys/dev/usb/dwc2/dwc2_core.c
995
u32 hcfg, val;
sys/dev/usb/dwc2/dwc2_params.c
382
int val;
sys/dev/usb/dwc2/dwc2_params.c
385
val = DWC2_PHY_TYPE_PARAM_FS;
sys/dev/usb/dwc2/dwc2_params.c
389
val = DWC2_PHY_TYPE_PARAM_UTMI;
sys/dev/usb/dwc2/dwc2_params.c
391
val = DWC2_PHY_TYPE_PARAM_ULPI;
sys/dev/usb/dwc2/dwc2_params.c
397
hsotg->params.phy_type = val;
sys/dev/usb/dwc2/dwc2_params.c
402
int val;
sys/dev/usb/dwc2/dwc2_params.c
404
val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
sys/dev/usb/dwc2/dwc2_params.c
408
val = DWC2_SPEED_PARAM_FULL;
sys/dev/usb/dwc2/dwc2_params.c
411
val = DWC2_SPEED_PARAM_HIGH;
sys/dev/usb/dwc2/dwc2_params.c
413
hsotg->params.speed = val;
sys/dev/usb/dwc2/dwc2_params.c
419
int val;
sys/dev/usb/dwc2/dwc2_params.c
421
val = (hsotg->hw_params.utmi_phy_data_width ==
sys/dev/usb/dwc2/dwc2_params.c
430
val = 8;
sys/dev/usb/dwc2/dwc2_params.c
433
hsotg->params.phy_utmi_width = val;
sys/dev/usb/dwc2/dwc2_params.c
455
int val;
sys/dev/usb/dwc2/dwc2_params.c
458
val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
sys/dev/usb/dwc2/dwc2_params.c
460
val = DWC2_POWER_DOWN_PARAM_PARTIAL;
sys/dev/usb/dwc2/dwc2_params.c
462
val = DWC2_POWER_DOWN_PARAM_NONE;
sys/dev/usb/dwc2/dwc2_params.c
464
hsotg->params.power_down = val;
sys/dev/usb/if_athn_usb.c
949
uint32_t val;
sys/dev/usb/if_athn_usb.c
957
&addr, sizeof(addr), &val);
sys/dev/usb/if_athn_usb.c
960
return (betoh32(val));
sys/dev/usb/if_athn_usb.c
964
athn_usb_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
sys/dev/usb/if_athn_usb.c
969
usc->wbuf[usc->wcount].val = htobe32(val);
sys/dev/usb/if_athn_usb.h
94
uint32_t val;
sys/dev/usb/if_aue.c
264
uByte val = 0;
sys/dev/usb/if_aue.c
275
err = usbd_do_request(sc->aue_udev, &req, &val);
sys/dev/usb/if_aue.c
283
return (val);
sys/dev/usb/if_aue.c
291
uWord val;
sys/dev/usb/if_aue.c
302
err = usbd_do_request(sc->aue_udev, &req, &val);
sys/dev/usb/if_aue.c
310
return (UGETW(val));
sys/dev/usb/if_aue.c
318
uByte val;
sys/dev/usb/if_aue.c
323
val = aval;
sys/dev/usb/if_aue.c
326
USETW(req.wValue, val);
sys/dev/usb/if_aue.c
330
err = usbd_do_request(sc->aue_udev, &req, &val);
sys/dev/usb/if_aue.c
346
uWord val;
sys/dev/usb/if_aue.c
351
USETW(val, aval);
sys/dev/usb/if_aue.c
358
err = usbd_do_request(sc->aue_udev, &req, &val);
sys/dev/usb/if_aue.c
433
u_int16_t val;
sys/dev/usb/if_aue.c
473
val = aue_csr_read_2(sc, AUE_PHY_DATA);
sys/dev/usb/if_aue.c
476
sc->aue_dev.dv_xname, __func__, phy, reg, val));
sys/dev/usb/if_aue.c
479
return (val);
sys/dev/usb/if_axe.c
231
axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
sys/dev/usb/if_axe.c
244
USETW(req.wValue, val);
sys/dev/usb/if_axe.c
263
uWord val;
sys/dev/usb/if_axe.c
288
USETW(val, 0);
sys/dev/usb/if_axe.c
292
err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, val);
sys/dev/usb/if_axe.c
301
phy, reg, UGETW(val)));
sys/dev/usb/if_axe.c
303
ival = UGETW(val);
sys/dev/usb/if_axe.c
318
axe_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_axe.c
329
USETW(uval, val);
sys/dev/usb/if_axe.c
349
int val, err;
sys/dev/usb/if_axe.c
378
val = 0;
sys/dev/usb/if_axe.c
380
val |= AXE_MEDIA_FULL_DUPLEX;
sys/dev/usb/if_axe.c
383
val |= (AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC);
sys/dev/usb/if_axe.c
385
val |= AXE_178_MEDIA_ENCK;
sys/dev/usb/if_axe.c
389
val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
sys/dev/usb/if_axe.c
392
val |= AXE_178_MEDIA_100TX;
sys/dev/usb/if_axe.c
400
DPRINTF(("axe_miibus_statchg: val=0x%x\n", val));
sys/dev/usb/if_axe.c
401
err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
sys/dev/usb/if_axe.c
515
u_int16_t eeprom, val;
sys/dev/usb/if_axe.c
546
val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
sys/dev/usb/if_axe.c
548
AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, 30);
sys/dev/usb/if_axe.c
549
AXE_GPIO_WRITE(val | AXE_GPIO2_EN, 300);
sys/dev/usb/if_axe.c
550
AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, 30);
sys/dev/usb/if_axe.c
557
val = axe_miibus_readreg(&sc->axe_dev, sc->axe_phyno, 0x0001);
sys/dev/usb/if_axe.c
559
val | 0x0080);
sys/dev/usb/if_axe.c
580
uint16_t val;
sys/dev/usb/if_axe.c
593
axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODEID + i, &val);
sys/dev/usb/if_axe.c
594
val = ntohs(val);
sys/dev/usb/if_axe.c
595
*eaddr++ = (u_char)((val >> 8) & 0xff);
sys/dev/usb/if_axe.c
596
*eaddr++ = (u_char)(val & 0xff);
sys/dev/usb/if_axen.c
139
axen_cmd(struct axen_softc *sc, int cmd, int index, int val, void *buf)
sys/dev/usb/if_axen.c
152
USETW(req.wValue, val);
sys/dev/usb/if_axen.c
158
cmd, val, AXEN_CMD_LEN(cmd)));
sys/dev/usb/if_axen.c
173
uWord val;
sys/dev/usb/if_axen.c
185
err = axen_cmd(sc, AXEN_CMD_MII_READ_REG, reg, phy, &val);
sys/dev/usb/if_axen.c
193
ival = UGETW(val);
sys/dev/usb/if_axen.c
205
axen_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_axen.c
217
USETW(uval, val);
sys/dev/usb/if_axen.c
222
phy, reg, val));
sys/dev/usb/if_axen.c
237
uint16_t val;
sys/dev/usb/if_axen.c
267
val = 0;
sys/dev/usb/if_axen.c
269
val |= AXEN_MEDIUM_FDX;
sys/dev/usb/if_axen.c
271
val |= (AXEN_MEDIUM_RECV_EN | AXEN_MEDIUM_ALWAYS_ONE);
sys/dev/usb/if_axen.c
272
val |= (AXEN_MEDIUM_RXFLOW_CTRL_EN | AXEN_MEDIUM_TXFLOW_CTRL_EN);
sys/dev/usb/if_axen.c
276
val |= AXEN_MEDIUM_GIGA | AXEN_MEDIUM_EN_125MHZ;
sys/dev/usb/if_axen.c
279
val |= AXEN_MEDIUM_PS;
sys/dev/usb/if_axen.c
286
DPRINTF(("axen_miibus_statchg: val=0x%x\n", val));
sys/dev/usb/if_axen.c
287
USETW(wval, val);
sys/dev/usb/if_axen.c
409
uByte val;
sys/dev/usb/if_axen.c
416
axen_cmd(sc, AXEN_CMD_MAC_READ, 1, AXEN_UNK_05, &val);
sys/dev/usb/if_axen.c
417
DPRINTFN(5, ("AXEN_CMD_MAC_READ(0x05): 0x%02x\n", val));
sys/dev/usb/if_axen.c
420
axen_cmd(sc, AXEN_CMD_MAC_READ, 1, AXEN_GENERAL_STATUS, &val);
sys/dev/usb/if_axen.c
422
if (!(val & AXEN_GENERAL_STATUS_MASK)) {
sys/dev/usb/if_axen.c
439
val = AXEN_PHYCLK_ACS | AXEN_PHYCLK_BCS;
sys/dev/usb/if_axen.c
440
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_PHYCLK, &val);
sys/dev/usb/if_axen.c
444
val = AXEN_MONITOR_NONE;
sys/dev/usb/if_axen.c
445
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_MONITOR_MODE, &val);
sys/dev/usb/if_axen.c
453
val = 0;
sys/dev/usb/if_axen.c
454
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_PHYCLK, &val);
sys/dev/usb/if_axen.c
455
val = AXEN_PHYCLK_ULR;
sys/dev/usb/if_axen.c
456
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_PHYCLK, &val);
sys/dev/usb/if_axen.c
470
axen_cmd(sc, AXEN_CMD_MAC_READ, 1, AXEN_USB_UPLINK, &val);
sys/dev/usb/if_axen.c
471
switch (val) {
sys/dev/usb/if_axen.c
498
sc->axen_dev.dv_xname, val);
sys/dev/usb/if_axen.c
514
val = 0x34;
sys/dev/usb/if_axen.c
515
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_PAUSE_LOW_WATERMARK, &val);
sys/dev/usb/if_axen.c
516
val = 0x52;
sys/dev/usb/if_axen.c
517
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_PAUSE_HIGH_WATERMARK, &val);
sys/dev/usb/if_axen.c
522
val = AXEN_RXCOE_IPv4 | AXEN_RXCOE_TCPv4 | AXEN_RXCOE_UDPv4 |
sys/dev/usb/if_axen.c
525
val = AXEN_RXCOE_OFF;
sys/dev/usb/if_axen.c
527
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_RX_COE, &val);
sys/dev/usb/if_axen.c
530
val = AXEN_TXCOE_IPv4 | AXEN_TXCOE_TCPv4 | AXEN_TXCOE_UDPv4 |
sys/dev/usb/if_axen.c
533
val = AXEN_TXCOE_OFF;
sys/dev/usb/if_axen.c
535
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_TX_COE, &val);
sys/dev/usb/if_axen.c
545
val = AXEN_MONITOR_PMETYPE | AXEN_MONITOR_PMEPOL | AXEN_MONITOR_RWMP;
sys/dev/usb/if_axen.c
546
axen_cmd(sc, AXEN_CMD_MAC_WRITE, 1, AXEN_MONITOR_MODE, &val);
sys/dev/usb/if_axen.c
547
axen_cmd(sc, AXEN_CMD_MAC_READ, 1, AXEN_MONITOR_MODE, &val);
sys/dev/usb/if_axen.c
548
DPRINTF(("axen: Monitor mode = 0x%02x\n", val));
sys/dev/usb/if_axen.c
577
val = axen_miibus_readreg(&sc->axen_dev, sc->axen_phyno, 0x0001);
sys/dev/usb/if_axen.c
579
val | 0x0080);
sys/dev/usb/if_cue.c
153
u_int8_t val = 0;
sys/dev/usb/if_cue.c
164
err = usbd_do_request(sc->cue_udev, &req, &val);
sys/dev/usb/if_cue.c
173
sc->cue_dev.dv_xname, reg, val));
sys/dev/usb/if_cue.c
175
return (val);
sys/dev/usb/if_cue.c
183
uWord val;
sys/dev/usb/if_cue.c
194
err = usbd_do_request(sc->cue_udev, &req, &val);
sys/dev/usb/if_cue.c
197
sc->cue_dev.dv_xname, reg, UGETW(val)));
sys/dev/usb/if_cue.c
205
return (UGETW(val));
sys/dev/usb/if_cue.c
209
cue_csr_write_1(struct cue_softc *sc, int reg, int val)
sys/dev/usb/if_cue.c
218
sc->cue_dev.dv_xname, reg, val));
sys/dev/usb/if_cue.c
222
USETW(req.wValue, val);
sys/dev/usb/if_cue.c
246
uWord val;
sys/dev/usb/if_cue.c
255
USETW(val, aval);
sys/dev/usb/if_cue.c
258
USETW(req.wValue, val);
sys/dev/usb/if_kue.c
198
kue_ctl(struct kue_softc *sc, int rw, u_int8_t breq, u_int16_t val,
sys/dev/usb/if_kue.c
212
USETW(req.wValue, val);
sys/dev/usb/if_mos.c
192
uByte val = 0;
sys/dev/usb/if_mos.c
203
err = usbd_do_request(sc->mos_udev, &req, &val);
sys/dev/usb/if_mos.c
210
return (val);
sys/dev/usb/if_mos.c
218
uWord val;
sys/dev/usb/if_mos.c
220
USETW(val,0);
sys/dev/usb/if_mos.c
231
err = usbd_do_request(sc->mos_udev, &req, &val);
sys/dev/usb/if_mos.c
238
return(UGETW(val));
sys/dev/usb/if_mos.c
246
uByte val;
sys/dev/usb/if_mos.c
248
val = aval;
sys/dev/usb/if_mos.c
259
err = usbd_do_request(sc->mos_udev, &req, &val);
sys/dev/usb/if_mos.c
274
uWord val;
sys/dev/usb/if_mos.c
276
USETW(val, aval);
sys/dev/usb/if_mos.c
287
err = usbd_do_request(sc->mos_udev, &req, &val);
sys/dev/usb/if_mos.c
407
mos_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_mos.c
417
mos_reg_write_2(sc, MOS_PHY_DATA, val);
sys/dev/usb/if_mos.c
441
int val, err;
sys/dev/usb/if_mos.c
446
val = mos_reg_read_1(sc, MOS_CTL);
sys/dev/usb/if_mos.c
447
val &= ~(MOS_CTL_TX_ENB | MOS_CTL_RX_ENB);
sys/dev/usb/if_mos.c
448
mos_reg_write_1(sc, MOS_CTL, val);
sys/dev/usb/if_mos.c
454
val |= MOS_CTL_FDX_ENB;
sys/dev/usb/if_mos.c
456
val &= ~(MOS_CTL_FDX_ENB);
sys/dev/usb/if_mos.c
460
val |= MOS_CTL_SPEEDSEL;
sys/dev/usb/if_mos.c
463
val &= ~(MOS_CTL_SPEEDSEL);
sys/dev/usb/if_mos.c
468
val |= (MOS_CTL_TX_ENB | MOS_CTL_RX_ENB);
sys/dev/usb/if_mos.c
469
err = mos_reg_write_1(sc, MOS_CTL, val);
sys/dev/usb/if_mtw.c
1004
mtw_efuse_read_2(struct mtw_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_mtw.c
1035
*val = 0xffff; /* address not found */
sys/dev/usb/if_mtw.c
1043
*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/usb/if_mtw.c
1048
mtw_eeprom_read_2(struct mtw_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_mtw.c
1062
*val = letoh16(tmp);
sys/dev/usb/if_mtw.c
1064
*val = 0xffff;
sys/dev/usb/if_mtw.c
1069
mtw_srom_read(struct mtw_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_mtw.c
1072
return sc->sc_srom_read(sc, addr, val);
sys/dev/usb/if_mtw.c
1076
mtw_rf_read(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t *val)
sys/dev/usb/if_mtw.c
1108
*val = tmp & 0xff;
sys/dev/usb/if_mtw.c
1113
mtw_rf_write(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t val)
sys/dev/usb/if_mtw.c
1133
reg << 8 | val;
sys/dev/usb/if_mtw.c
1138
mtw_bbp_read(struct mtw_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/usb/if_mtw.c
1165
*val = tmp & 0xff;
sys/dev/usb/if_mtw.c
1170
mtw_bbp_write(struct mtw_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_mtw.c
1184
tmp = MTW_BBP_CSR_KICK | reg << MTW_BBP_ADDR_SHIFT | val;
sys/dev/usb/if_mtw.c
1189
mtw_usb_dma_read(struct mtw_softc *sc, uint32_t *val)
sys/dev/usb/if_mtw.c
1192
return mtw_read_cfg(sc, MTW_USB_U3DMA_CFG, val);
sys/dev/usb/if_mtw.c
1194
return mtw_read(sc, MTW_USB_DMA_CFG, val);
sys/dev/usb/if_mtw.c
1198
mtw_usb_dma_write(struct mtw_softc *sc, uint32_t val)
sys/dev/usb/if_mtw.c
1201
return mtw_write_cfg(sc, MTW_USB_U3DMA_CFG, val);
sys/dev/usb/if_mtw.c
1203
return mtw_write(sc, MTW_USB_DMA_CFG, val);
sys/dev/usb/if_mtw.c
1207
mtw_mcu_calibrate(struct mtw_softc *sc, int func, uint32_t val)
sys/dev/usb/if_mtw.c
1212
cmd.val = htole32(val);
sys/dev/usb/if_mtw.c
1229
mtw_mcu_radio(struct mtw_softc *sc, int func, uint32_t val)
sys/dev/usb/if_mtw.c
1234
cmd.r2 = htole32(val);
sys/dev/usb/if_mtw.c
1299
uint16_t val;
sys/dev/usb/if_mtw.c
1304
mtw_srom_read(sc, MTW_EEPROM_PWR2GHZ_BASE1 + i / 2, &val);
sys/dev/usb/if_mtw.c
1305
sc->txpow1[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_mtw.c
1306
sc->txpow1[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_mtw.c
1307
mtw_srom_read(sc, MTW_EEPROM_PWR2GHZ_BASE2 + i / 2, &val);
sys/dev/usb/if_mtw.c
1308
sc->txpow2[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_mtw.c
1309
sc->txpow2[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_mtw.c
1323
mtw_srom_read(sc, MTW_EEPROM_PWR5GHZ_BASE1 + i / 2, &val);
sys/dev/usb/if_mtw.c
1324
sc->txpow1[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_mtw.c
1325
sc->txpow1[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_mtw.c
1327
mtw_srom_read(sc, MTW_EEPROM_PWR5GHZ_BASE2 + i / 2, &val);
sys/dev/usb/if_mtw.c
1328
sc->txpow2[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_mtw.c
1329
sc->txpow2[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_mtw.c
1351
uint16_t val;
sys/dev/usb/if_mtw.c
1357
mtw_srom_read(sc, MTW_EEPROM_CHIPID, &val);
sys/dev/usb/if_mtw.c
1358
sc->rf_rev = val;
sys/dev/usb/if_mtw.c
1359
mtw_srom_read(sc, MTW_EEPROM_ANTENNA, &val);
sys/dev/usb/if_mtw.c
1360
sc->ntxchains = (val >> 4) & 0xf;
sys/dev/usb/if_mtw.c
1361
sc->nrxchains = val & 0xf;
sys/dev/usb/if_mtw.c
1366
mtw_srom_read(sc, MTW_EEPROM_VERSION, &val);
sys/dev/usb/if_mtw.c
1367
DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
sys/dev/usb/if_mtw.c
1370
mtw_srom_read(sc, MTW_EEPROM_MAC01, &val);
sys/dev/usb/if_mtw.c
1371
ic->ic_myaddr[0] = val & 0xff;
sys/dev/usb/if_mtw.c
1372
ic->ic_myaddr[1] = val >> 8;
sys/dev/usb/if_mtw.c
1373
mtw_srom_read(sc, MTW_EEPROM_MAC23, &val);
sys/dev/usb/if_mtw.c
1374
ic->ic_myaddr[2] = val & 0xff;
sys/dev/usb/if_mtw.c
1375
ic->ic_myaddr[3] = val >> 8;
sys/dev/usb/if_mtw.c
1376
mtw_srom_read(sc, MTW_EEPROM_MAC45, &val);
sys/dev/usb/if_mtw.c
1377
ic->ic_myaddr[4] = val & 0xff;
sys/dev/usb/if_mtw.c
1378
ic->ic_myaddr[5] = val >> 8;
sys/dev/usb/if_mtw.c
1384
mtw_srom_read(sc, i, &val);
sys/dev/usb/if_mtw.c
1385
printf(" %04x", val);
sys/dev/usb/if_mtw.c
1390
mtw_srom_read(sc, MTW_EEPROM_CONFIG, &val);
sys/dev/usb/if_mtw.c
1391
DPRINTF(("EEPROM CFG 0x%04x\n", val));
sys/dev/usb/if_mtw.c
1392
if ((val & 0xff) != 0xff) {
sys/dev/usb/if_mtw.c
1393
sc->ext_5ghz_lna = (val >> 3) & 1;
sys/dev/usb/if_mtw.c
1394
sc->ext_2ghz_lna = (val >> 2) & 1;
sys/dev/usb/if_mtw.c
1396
sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1;
sys/dev/usb/if_mtw.c
1398
sc->rfswitch = val & 1;
sys/dev/usb/if_mtw.c
1402
mtw_srom_read(sc, MTW_EEPROM_FREQ_OFFSET, &val);
sys/dev/usb/if_mtw.c
1403
if ((val & 0xff) != 0xff)
sys/dev/usb/if_mtw.c
1404
sc->rf_freq_offset = val;
sys/dev/usb/if_mtw.c
1413
mtw_srom_read(sc, MTW_EEPROM_DELTAPWR, &val);
sys/dev/usb/if_mtw.c
1415
if ((val & 0xff) != 0xff && (val & 0x80)) {
sys/dev/usb/if_mtw.c
1416
delta_2ghz = val & 0xf;
sys/dev/usb/if_mtw.c
1417
if (!(val & 0x40)) /* negative number */
sys/dev/usb/if_mtw.c
1420
val >>= 8;
sys/dev/usb/if_mtw.c
1421
if ((val & 0xff) != 0xff && (val & 0x80)) {
sys/dev/usb/if_mtw.c
1422
delta_5ghz = val & 0xf;
sys/dev/usb/if_mtw.c
1423
if (!(val & 0x40)) /* negative number */
sys/dev/usb/if_mtw.c
1432
mtw_srom_read(sc, MTW_EEPROM_RPWR + ridx * 2, &val);
sys/dev/usb/if_mtw.c
1433
reg = val;
sys/dev/usb/if_mtw.c
1434
mtw_srom_read(sc, MTW_EEPROM_RPWR + ridx * 2 + 1, &val);
sys/dev/usb/if_mtw.c
1435
reg |= (uint32_t)val << 16;
sys/dev/usb/if_mtw.c
1447
val = 0;
sys/dev/usb/if_mtw.c
1448
mtw_srom_read(sc, MTW_EEPROM_RSSI1_2GHZ, &val);
sys/dev/usb/if_mtw.c
1449
sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
sys/dev/usb/if_mtw.c
1450
sc->rssi_2ghz[1] = val >> 8; /* Ant B */
sys/dev/usb/if_mtw.c
1451
mtw_srom_read(sc, MTW_EEPROM_RSSI2_2GHZ, &val);
sys/dev/usb/if_mtw.c
1456
if ((val & 0xff) != 0xff)
sys/dev/usb/if_mtw.c
1457
sc->txmixgain_2ghz = val & 0x7;
sys/dev/usb/if_mtw.c
1459
sc->lna[2] = val >> 8; /* channel group 2 */
sys/dev/usb/if_mtw.c
1460
mtw_srom_read(sc, MTW_EEPROM_RSSI1_5GHZ, &val);
sys/dev/usb/if_mtw.c
1461
sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
sys/dev/usb/if_mtw.c
1462
sc->rssi_5ghz[1] = val >> 8; /* Ant B */
sys/dev/usb/if_mtw.c
1463
mtw_srom_read(sc, MTW_EEPROM_RSSI2_5GHZ, &val);
sys/dev/usb/if_mtw.c
1464
sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
sys/dev/usb/if_mtw.c
1466
sc->lna[3] = val >> 8; /* channel group 3 */
sys/dev/usb/if_mtw.c
1468
mtw_srom_read(sc, MTW_EEPROM_LNA, &val);
sys/dev/usb/if_mtw.c
1469
sc->lna[0] = val & 0xff; /* channel group 0 */
sys/dev/usb/if_mtw.c
1470
sc->lna[1] = val >> 8; /* channel group 1 */
sys/dev/usb/if_mtw.c
196
uint32_t val;
sys/dev/usb/if_mtw.c
203
uint8_t val;
sys/dev/usb/if_mtw.c
217
uint8_t val;
sys/dev/usb/if_mtw.c
2759
cmd.val = htole32(which);
sys/dev/usb/if_mtw.c
2832
mt7601_def_bbp[i].val)) != 0)
sys/dev/usb/if_mtw.c
2849
mt7601_rf_bank0[i].val);
sys/dev/usb/if_mtw.c
2856
mt7601_rf_bank4[i].val);
sys/dev/usb/if_mtw.c
2863
mt7601_rf_bank5[i].val);
sys/dev/usb/if_mtw.c
2933
mt7601_rf_temperature(struct mtw_softc *sc, int8_t *val)
sys/dev/usb/if_mtw.c
2960
mt7601_r49_read(sc, MT7601_R47_TEMP, val);
sys/dev/usb/if_mtw.c
2977
mt7601_r49_read(struct mtw_softc *sc, uint8_t flag, int8_t *val)
sys/dev/usb/if_mtw.c
2987
return mtw_bbp_read(sc, 49, val);
sys/dev/usb/if_mtw.c
3156
mt7601_def_mac[i].val);
sys/dev/usb/if_mtw.c
877
mtw_read(struct mtw_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_mtw.c
885
*val = letoh32(tmp);
sys/dev/usb/if_mtw.c
887
*val = 0xffffffff;
sys/dev/usb/if_mtw.c
892
mtw_read_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_mtw.c
906
*val = letoh32(tmp);
sys/dev/usb/if_mtw.c
908
*val = 0xffffffff;
sys/dev/usb/if_mtw.c
927
mtw_write_2(struct mtw_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_mtw.c
933
USETW(req.wValue, val);
sys/dev/usb/if_mtw.c
940
mtw_write(struct mtw_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_mtw.c
944
if ((error = mtw_write_2(sc, reg, val & 0xffff)) == 0)
sys/dev/usb/if_mtw.c
945
error = mtw_write_2(sc, reg + 2, val >> 16);
sys/dev/usb/if_mtw.c
950
mtw_write_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_mtw.c
960
val = htole32(val);
sys/dev/usb/if_mtw.c
961
error = usbd_do_request(sc->sc_udev, &req, &val);
sys/dev/usb/if_mtw.c
993
mtw_set_region_4(struct mtw_softc *sc, uint16_t reg, uint32_t val, int count)
sys/dev/usb/if_mtw.c
998
error = mtw_write(sc, reg, val);
sys/dev/usb/if_mue.c
178
uDWord val;
sys/dev/usb/if_mue.c
183
USETDW(val, 0);
sys/dev/usb/if_mue.c
190
err = usbd_do_request(sc->mue_udev, &req, &val);
sys/dev/usb/if_mue.c
197
return (UGETDW(val));
sys/dev/usb/if_mue.c
205
uDWord val;
sys/dev/usb/if_mue.c
210
USETDW(val, aval);
sys/dev/usb/if_mue.c
217
err = usbd_do_request(sc->mue_udev, &req, &val);
sys/dev/usb/if_mue.c
267
uint32_t val;
sys/dev/usb/if_mue.c
286
val = mue_csr_read(sc, MUE_MII_DATA);
sys/dev/usb/if_mue.c
288
return (val & 0xffff);
sys/dev/usb/if_mue.c
423
uint32_t val;
sys/dev/usb/if_mue.c
427
val = mue_csr_read(sc, MUE_E2P_CMD);
sys/dev/usb/if_mue.c
428
if (!(val & MUE_E2P_CMD_BUSY) || (val & MUE_E2P_CMD_TIMEOUT))
sys/dev/usb/if_mue.c
471
uint32_t val;
sys/dev/usb/if_mue.c
478
val = mue_csr_read(sc, MUE_HW_CFG);
sys/dev/usb/if_mue.c
492
mue_csr_write(sc, MUE_HW_CFG, val);
sys/dev/usb/if_mue.c
556
uint32_t val;
sys/dev/usb/if_mue.c
606
val = (sc->mue_udev->speed == USB_SPEED_SUPER) ?
sys/dev/usb/if_mue.c
608
mue_csr_write(sc, MUE_7800_BURST_CAP, val);
sys/dev/usb/if_mue.c
624
val = mue_csr_read(sc, MUE_PMT_CTL);
sys/dev/usb/if_mue.c
625
if (!(val & MUE_PMT_CTL_PHY_RST) && (val & MUE_PMT_CTL_READY))
sys/dev/usb/if_mue.c
672
uint32_t val, reg;
sys/dev/usb/if_mue.c
676
val = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0];
sys/dev/usb/if_mue.c
677
mue_csr_write(sc, MUE_RX_ADDRL, val);
sys/dev/usb/if_mue.c
678
mue_csr_write(sc, reg + 4, val);
sys/dev/usb/if_mue.c
679
val = (eaddr[5] << 8) | eaddr[4];
sys/dev/usb/if_mue.c
680
mue_csr_write(sc, MUE_RX_ADDRH, val);
sys/dev/usb/if_mue.c
681
mue_csr_write(sc, reg, val | MUE_ADDR_FILTX_VALID);
sys/dev/usb/if_otus.c
1572
#define EXP2(val) ((1 << (val)) - 1)
sys/dev/usb/if_otus.c
1573
#define AIFS(val) ((val) * 9 + 10)
sys/dev/usb/if_otus.c
858
otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)
sys/dev/usb/if_otus.c
861
sc->write_buf[sc->write_idx].val = htole32(val);
sys/dev/usb/if_otusreg.h
972
uint32_t val;
sys/dev/usb/if_ral.c
1367
uint16_t val;
sys/dev/usb/if_ral.c
1375
error = usbd_do_request(sc->sc_udev, &req, &val);
sys/dev/usb/if_ral.c
1381
return letoh16(val);
sys/dev/usb/if_ral.c
1404
ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_ral.c
1411
USETW(req.wValue, val);
sys/dev/usb/if_ral.c
1442
ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_ral.c
1456
tmp = reg << 8 | val;
sys/dev/usb/if_ral.c
1463
uint16_t val;
sys/dev/usb/if_ral.c
1466
val = RAL_BBP_WRITE | reg << 8;
sys/dev/usb/if_ral.c
1467
ural_write(sc, RAL_PHY_CSR7, val);
sys/dev/usb/if_ral.c
1481
ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/if_ral.c
1495
tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
sys/dev/usb/if_ral.c
1500
sc->rf_regs[reg] = val;
sys/dev/usb/if_ral.c
1502
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
sys/dev/usb/if_ral.c
157
uint16_t val;
sys/dev/usb/if_ral.c
164
uint8_t val;
sys/dev/usb/if_ral.c
1778
uint16_t val;
sys/dev/usb/if_ral.c
1781
ural_eeprom_read(sc, RAL_EEPROM_MACBBP, &val, 2);
sys/dev/usb/if_ral.c
1782
sc->macbbp_rev = letoh16(val);
sys/dev/usb/if_ral.c
1784
ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2);
sys/dev/usb/if_ral.c
1785
val = letoh16(val);
sys/dev/usb/if_ral.c
1786
sc->rf_rev = (val >> 11) & 0x7;
sys/dev/usb/if_ral.c
1787
sc->hw_radio = (val >> 10) & 0x1;
sys/dev/usb/if_ral.c
1788
sc->led_mode = (val >> 6) & 0x7;
sys/dev/usb/if_ral.c
1789
sc->rx_ant = (val >> 4) & 0x3;
sys/dev/usb/if_ral.c
1790
sc->tx_ant = (val >> 2) & 0x3;
sys/dev/usb/if_ral.c
1791
sc->nb_ant = val & 0x3;
sys/dev/usb/if_ral.c
1821
ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
sys/dev/usb/if_ral.c
1828
ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/usb/if_ral.c
1897
ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
sys/dev/usb/if_ralvar.h
114
uint8_t val;
sys/dev/usb/if_rsu.c
541
rsu_write_1(struct rsu_softc *sc, uint16_t addr, uint8_t val)
sys/dev/usb/if_rsu.c
543
rsu_write_region_1(sc, addr, &val, 1);
sys/dev/usb/if_rsu.c
547
rsu_write_2(struct rsu_softc *sc, uint16_t addr, uint16_t val)
sys/dev/usb/if_rsu.c
549
val = htole16(val);
sys/dev/usb/if_rsu.c
550
rsu_write_region_1(sc, addr, (uint8_t *)&val, 2);
sys/dev/usb/if_rsu.c
554
rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val)
sys/dev/usb/if_rsu.c
556
val = htole32(val);
sys/dev/usb/if_rsu.c
557
rsu_write_region_1(sc, addr, (uint8_t *)&val, 4);
sys/dev/usb/if_rsu.c
577
uint8_t val;
sys/dev/usb/if_rsu.c
579
if (rsu_read_region_1(sc, addr, &val, 1) != 0)
sys/dev/usb/if_rsu.c
581
return (val);
sys/dev/usb/if_rsu.c
587
uint16_t val;
sys/dev/usb/if_rsu.c
589
if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
sys/dev/usb/if_rsu.c
591
return (letoh16(val));
sys/dev/usb/if_rsu.c
597
uint32_t val;
sys/dev/usb/if_rsu.c
599
if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
sys/dev/usb/if_rsu.c
601
return (letoh32(val));
sys/dev/usb/if_rsureg.h
151
#define MS(val, field) \
sys/dev/usb/if_rsureg.h
152
(((val) & field##_M) >> field##_S)
sys/dev/usb/if_rsureg.h
155
#define SM(field, val) \
sys/dev/usb/if_rsureg.h
156
(((val) << field##_S) & field##_M)
sys/dev/usb/if_rsureg.h
159
#define RW(var, field, val) \
sys/dev/usb/if_rsureg.h
160
(((var) & ~field##_M) | SM(field, val))
sys/dev/usb/if_rum.c
1381
uint32_t val;
sys/dev/usb/if_rum.c
1383
rum_read_multi(sc, reg, &val, sizeof val);
sys/dev/usb/if_rum.c
1385
return letoh32(val);
sys/dev/usb/if_rum.c
1408
rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_rum.c
1410
uint32_t tmp = htole32(val);
sys/dev/usb/if_rum.c
1440
rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_rum.c
1454
tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/usb/if_rum.c
1461
uint32_t val;
sys/dev/usb/if_rum.c
1473
val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;
sys/dev/usb/if_rum.c
1474
rum_write(sc, RT2573_PHY_CSR3, val);
sys/dev/usb/if_rum.c
1477
val = rum_read(sc, RT2573_PHY_CSR3);
sys/dev/usb/if_rum.c
1478
if (!(val & RT2573_BBP_BUSY))
sys/dev/usb/if_rum.c
1479
return val & 0xff;
sys/dev/usb/if_rum.c
1488
rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/if_rum.c
1502
tmp = RT2573_RF_BUSY | RT2573_RF_20BIT | (val & 0xfffff) << 2 |
sys/dev/usb/if_rum.c
1507
sc->rf_regs[reg] = val;
sys/dev/usb/if_rum.c
1509
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff));
sys/dev/usb/if_rum.c
1815
uint16_t val;
sys/dev/usb/if_rum.c
1821
rum_eeprom_read(sc, RT2573_EEPROM_MACBBP, &val, 2);
sys/dev/usb/if_rum.c
1822
sc->macbbp_rev = letoh16(val);
sys/dev/usb/if_rum.c
1827
rum_eeprom_read(sc, RT2573_EEPROM_ANTENNA, &val, 2);
sys/dev/usb/if_rum.c
1828
val = letoh16(val);
sys/dev/usb/if_rum.c
1829
sc->rf_rev = (val >> 11) & 0x1f;
sys/dev/usb/if_rum.c
1830
sc->hw_radio = (val >> 10) & 0x1;
sys/dev/usb/if_rum.c
1831
sc->rx_ant = (val >> 4) & 0x3;
sys/dev/usb/if_rum.c
1832
sc->tx_ant = (val >> 2) & 0x3;
sys/dev/usb/if_rum.c
1833
sc->nb_ant = val & 0x3;
sys/dev/usb/if_rum.c
1837
rum_eeprom_read(sc, RT2573_EEPROM_CONFIG2, &val, 2);
sys/dev/usb/if_rum.c
1838
val = letoh16(val);
sys/dev/usb/if_rum.c
1839
sc->ext_5ghz_lna = (val >> 6) & 0x1;
sys/dev/usb/if_rum.c
1840
sc->ext_2ghz_lna = (val >> 4) & 0x1;
sys/dev/usb/if_rum.c
1845
rum_eeprom_read(sc, RT2573_EEPROM_RSSI_2GHZ_OFFSET, &val, 2);
sys/dev/usb/if_rum.c
1846
val = letoh16(val);
sys/dev/usb/if_rum.c
1847
if ((val & 0xff) != 0xff)
sys/dev/usb/if_rum.c
1848
sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
sys/dev/usb/if_rum.c
1850
rum_eeprom_read(sc, RT2573_EEPROM_RSSI_5GHZ_OFFSET, &val, 2);
sys/dev/usb/if_rum.c
1851
val = letoh16(val);
sys/dev/usb/if_rum.c
1852
if ((val & 0xff) != 0xff)
sys/dev/usb/if_rum.c
1853
sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
sys/dev/usb/if_rum.c
1858
rum_eeprom_read(sc, RT2573_EEPROM_FREQ_OFFSET, &val, 2);
sys/dev/usb/if_rum.c
1859
val = letoh16(val);
sys/dev/usb/if_rum.c
1860
if ((val & 0xff) != 0xff)
sys/dev/usb/if_rum.c
1861
sc->rffreq = val & 0xff;
sys/dev/usb/if_rum.c
188
uint32_t val;
sys/dev/usb/if_rum.c
1881
sc->bbp_prom[i].val));
sys/dev/usb/if_rum.c
1893
const uint8_t val = rum_bbp_read(sc, 0);
sys/dev/usb/if_rum.c
1894
if (val != 0 && val != 0xff)
sys/dev/usb/if_rum.c
1906
rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);
sys/dev/usb/if_rum.c
1912
rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/usb/if_rum.c
1931
rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);
sys/dev/usb/if_rum.c
195
uint8_t val;
sys/dev/usb/if_rumvar.h
116
uint8_t val;
sys/dev/usb/if_run.c
1018
*val = 0xffff; /* address not found */
sys/dev/usb/if_run.c
1027
*val = (addr & 1) ? tmp >> 16 : tmp & 0xffff;
sys/dev/usb/if_run.c
1033
run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_run.c
1064
*val = 0xffff; /* address not found */
sys/dev/usb/if_run.c
1072
*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
sys/dev/usb/if_run.c
1077
run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_run.c
1091
*val = letoh16(tmp);
sys/dev/usb/if_run.c
1093
*val = 0xffff;
sys/dev/usb/if_run.c
1098
run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_run.c
1101
return sc->sc_srom_read(sc, addr, val);
sys/dev/usb/if_run.c
1105
run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/if_run.c
1121
(val & 0x3fffff) << 2 | (reg & 3);
sys/dev/usb/if_run.c
1126
run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/usb/if_run.c
1153
*val = tmp & 0xff;
sys/dev/usb/if_run.c
1158
run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_run.c
1172
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/usb/if_run.c
1177
run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/usb/if_run.c
1204
*val = tmp & 0xff;
sys/dev/usb/if_run.c
1209
run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_run.c
1223
tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;
sys/dev/usb/if_run.c
1296
uint16_t addr, val;
sys/dev/usb/if_run.c
1303
run_srom_read(sc, addr + i / 2, &val);
sys/dev/usb/if_run.c
1304
sc->txpow1[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1305
sc->txpow1[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1309
run_srom_read(sc, addr + i / 2, &val);
sys/dev/usb/if_run.c
1310
sc->txpow2[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1311
sc->txpow2[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1315
&val);
sys/dev/usb/if_run.c
1316
sc->txpow3[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1317
sc->txpow3[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1333
run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val);
sys/dev/usb/if_run.c
1334
sc->txpow1[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1335
sc->txpow1[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1337
run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val);
sys/dev/usb/if_run.c
1338
sc->txpow2[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1339
sc->txpow2[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1343
&val);
sys/dev/usb/if_run.c
1344
sc->txpow3[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1345
sc->txpow3[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1353
uint16_t val;
sys/dev/usb/if_run.c
1358
run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val);
sys/dev/usb/if_run.c
1359
sc->txpow1[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1360
sc->txpow1[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1364
RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val);
sys/dev/usb/if_run.c
1365
sc->txpow2[i + 0] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1366
sc->txpow2[i + 1] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1390
run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val);
sys/dev/usb/if_run.c
1391
sc->txpow1[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1392
sc->txpow1[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1394
run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val);
sys/dev/usb/if_run.c
1395
sc->txpow2[i + 14] = (int8_t)(val & 0xff);
sys/dev/usb/if_run.c
1396
sc->txpow2[i + 15] = (int8_t)(val >> 8);
sys/dev/usb/if_run.c
1418
uint16_t val;
sys/dev/usb/if_run.c
1431
run_srom_read(sc, RT2860_EEPROM_VERSION, &val);
sys/dev/usb/if_run.c
1432
DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
sys/dev/usb/if_run.c
1435
run_srom_read(sc, RT2860_EEPROM_MAC01, &val);
sys/dev/usb/if_run.c
1436
ic->ic_myaddr[0] = val & 0xff;
sys/dev/usb/if_run.c
1437
ic->ic_myaddr[1] = val >> 8;
sys/dev/usb/if_run.c
1438
run_srom_read(sc, RT2860_EEPROM_MAC23, &val);
sys/dev/usb/if_run.c
1439
ic->ic_myaddr[2] = val & 0xff;
sys/dev/usb/if_run.c
1440
ic->ic_myaddr[3] = val >> 8;
sys/dev/usb/if_run.c
1441
run_srom_read(sc, RT2860_EEPROM_MAC45, &val);
sys/dev/usb/if_run.c
1442
ic->ic_myaddr[4] = val & 0xff;
sys/dev/usb/if_run.c
1443
ic->ic_myaddr[5] = val >> 8;
sys/dev/usb/if_run.c
1448
run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val);
sys/dev/usb/if_run.c
1449
sc->bbp[i].val = val & 0xff;
sys/dev/usb/if_run.c
1450
sc->bbp[i].reg = val >> 8;
sys/dev/usb/if_run.c
1452
sc->bbp[i].val));
sys/dev/usb/if_run.c
1458
&val);
sys/dev/usb/if_run.c
1459
sc->rf[i].val = val & 0xff;
sys/dev/usb/if_run.c
1460
sc->rf[i].reg = val >> 8;
sys/dev/usb/if_run.c
1462
sc->rf[i].val));
sys/dev/usb/if_run.c
1469
RT3593_EEPROM_FREQ, &val);
sys/dev/usb/if_run.c
1470
sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
sys/dev/usb/if_run.c
1473
RT3593_EEPROM_FREQ_LEDS, &val);
sys/dev/usb/if_run.c
1474
if ((val >> 8) != 0xff) {
sys/dev/usb/if_run.c
1476
sc->leds = val >> 8;
sys/dev/usb/if_run.c
1495
run_srom_read(sc, 0x00, &val);
sys/dev/usb/if_run.c
1497
run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val);
sys/dev/usb/if_run.c
1498
if (val == 0xffff) {
sys/dev/usb/if_run.c
1518
sc->rf_rev = val;
sys/dev/usb/if_run.c
1519
run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val);
sys/dev/usb/if_run.c
1521
sc->rf_rev = (val >> 8) & 0xf;
sys/dev/usb/if_run.c
1522
sc->ntxchains = (val >> 4) & 0xf;
sys/dev/usb/if_run.c
1523
sc->nrxchains = val & 0xf;
sys/dev/usb/if_run.c
1529
run_srom_read(sc, RT2860_EEPROM_CONFIG, &val);
sys/dev/usb/if_run.c
1530
DPRINTF(("EEPROM CFG 0x%04x\n", val));
sys/dev/usb/if_run.c
1532
if ((val >> 8) != 0xff)
sys/dev/usb/if_run.c
1533
sc->patch_dac = (val >> 15) & 1;
sys/dev/usb/if_run.c
1534
if ((val & 0xff) != 0xff) {
sys/dev/usb/if_run.c
1535
sc->ext_5ghz_lna = (val >> 3) & 1;
sys/dev/usb/if_run.c
1536
sc->ext_2ghz_lna = (val >> 2) & 1;
sys/dev/usb/if_run.c
1538
sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1;
sys/dev/usb/if_run.c
1540
sc->rfswitch = val & 1;
sys/dev/usb/if_run.c
1550
run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val);
sys/dev/usb/if_run.c
1552
if ((val & 0xff) != 0xff && (val & 0x80)) {
sys/dev/usb/if_run.c
1553
delta_2ghz = val & 0xf;
sys/dev/usb/if_run.c
1554
if (!(val & 0x40)) /* negative number */
sys/dev/usb/if_run.c
1557
val >>= 8;
sys/dev/usb/if_run.c
1558
if ((val & 0xff) != 0xff && (val & 0x80)) {
sys/dev/usb/if_run.c
1559
delta_5ghz = val & 0xf;
sys/dev/usb/if_run.c
1560
if (!(val & 0x40)) /* negative number */
sys/dev/usb/if_run.c
1569
run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val);
sys/dev/usb/if_run.c
1570
reg = val;
sys/dev/usb/if_run.c
1571
run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val);
sys/dev/usb/if_run.c
1572
reg |= (uint32_t)val << 16;
sys/dev/usb/if_run.c
1585
RT3593_EEPROM_RSSI1_2GHZ, &val);
sys/dev/usb/if_run.c
1586
sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
sys/dev/usb/if_run.c
1587
sc->rssi_2ghz[1] = val >> 8; /* Ant B */
sys/dev/usb/if_run.c
1589
RT3593_EEPROM_RSSI2_2GHZ, &val);
sys/dev/usb/if_run.c
1593
sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
sys/dev/usb/if_run.c
1599
if ((val & 0xff) != 0xff)
sys/dev/usb/if_run.c
1600
sc->txmixgain_2ghz = val & 0x7;
sys/dev/usb/if_run.c
1604
sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
sys/dev/usb/if_run.c
1606
run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val);
sys/dev/usb/if_run.c
1607
sc->lna[2] = val >> 8; /* channel group 2 */
sys/dev/usb/if_run.c
1610
RT3593_EEPROM_RSSI1_5GHZ, &val);
sys/dev/usb/if_run.c
1611
sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
sys/dev/usb/if_run.c
1612
sc->rssi_5ghz[1] = val >> 8; /* Ant B */
sys/dev/usb/if_run.c
1614
RT3593_EEPROM_RSSI2_5GHZ, &val);
sys/dev/usb/if_run.c
1620
if ((val & 0xff) != 0xff)
sys/dev/usb/if_run.c
1621
sc->txmixgain_5ghz = val & 0x7;
sys/dev/usb/if_run.c
1624
sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
sys/dev/usb/if_run.c
1627
run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val);
sys/dev/usb/if_run.c
1629
sc->lna[3] = val >> 8; /* channel group 3 */
sys/dev/usb/if_run.c
1632
RT3593_EEPROM_LNA, &val);
sys/dev/usb/if_run.c
1633
sc->lna[0] = val & 0xff; /* channel group 0 */
sys/dev/usb/if_run.c
1634
sc->lna[1] = val >> 8; /* channel group 1 */
sys/dev/usb/if_run.c
2670
uint16_t val;
sys/dev/usb/if_run.c
2675
run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val);
sys/dev/usb/if_run.c
2678
RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, &val);
sys/dev/usb/if_run.c
2681
RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, &val);
sys/dev/usb/if_run.c
2685
&val);
sys/dev/usb/if_run.c
2687
val = 0;
sys/dev/usb/if_run.c
2688
run_bbp_write(sc, 159, val);
sys/dev/usb/if_run.c
2693
run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, &val);
sys/dev/usb/if_run.c
2696
RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, &val);
sys/dev/usb/if_run.c
2699
RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, &val);
sys/dev/usb/if_run.c
2702
RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, &val);
sys/dev/usb/if_run.c
2704
val = 0;
sys/dev/usb/if_run.c
2705
run_bbp_write(sc, 159, val);
sys/dev/usb/if_run.c
2710
run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, &val);
sys/dev/usb/if_run.c
2713
RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, &val);
sys/dev/usb/if_run.c
2716
RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, &val);
sys/dev/usb/if_run.c
2719
RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, &val);
sys/dev/usb/if_run.c
2721
val = 0;
sys/dev/usb/if_run.c
2722
run_bbp_write(sc, 159, val);
sys/dev/usb/if_run.c
2727
run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, &val);
sys/dev/usb/if_run.c
2730
RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, &val);
sys/dev/usb/if_run.c
2733
RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, &val);
sys/dev/usb/if_run.c
2736
RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, &val);
sys/dev/usb/if_run.c
2738
val = 0;
sys/dev/usb/if_run.c
2739
run_bbp_write(sc, 159, val);
sys/dev/usb/if_run.c
2743
run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, &val);
sys/dev/usb/if_run.c
2744
run_bbp_write(sc, 159, val);
sys/dev/usb/if_run.c
2749
RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val);
sys/dev/usb/if_run.c
2750
run_bbp_write(sc, 159, val);
sys/dev/usb/if_run.c
3502
rt5592_2ghz_def_rf[i].val);
sys/dev/usb/if_run.c
3521
rt5592_5ghz_def_rf[i].val);
sys/dev/usb/if_run.c
3527
rt5592_chan_5ghz[i].val);
sys/dev/usb/if_run.c
3822
rt5592_def_bbp[i].val);
sys/dev/usb/if_run.c
3831
rt5390_def_bbp[i].val);
sys/dev/usb/if_run.c
3884
rt2860_def_bbp[i].val);
sys/dev/usb/if_run.c
3929
rt3572_def_rf[i].val);
sys/dev/usb/if_run.c
3934
rt3070_def_rf[i].val);
sys/dev/usb/if_run.c
4068
rt3593_def_rf[i].val);
sys/dev/usb/if_run.c
4124
rt5592_def_rf[i].val);
sys/dev/usb/if_run.c
4131
rt5392_def_rf[i].val);
sys/dev/usb/if_run.c
4144
rt5390_def_rf[i].val);
sys/dev/usb/if_run.c
4168
uint8_t *val)
sys/dev/usb/if_run.c
4217
*val = rf24;
sys/dev/usb/if_run.c
4305
run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
sys/dev/usb/if_run.c
433
uint32_t val;
sys/dev/usb/if_run.c
440
uint8_t val;
sys/dev/usb/if_run.c
4571
run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val);
sys/dev/usb/if_run.c
4651
run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
sys/dev/usb/if_run.c
488
uint8_t val;
sys/dev/usb/if_run.c
511
uint8_t val;
sys/dev/usb/if_run.c
901
run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_run.c
908
*val = letoh32(tmp);
sys/dev/usb/if_run.c
910
*val = 0xffffffff;
sys/dev/usb/if_run.c
928
run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_run.c
934
USETW(req.wValue, val);
sys/dev/usb/if_run.c
941
run_write(struct run_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_run.c
945
if ((error = run_write_2(sc, reg, val & 0xffff)) == 0)
sys/dev/usb/if_run.c
946
error = run_write_2(sc, reg + 2, val >> 16);
sys/dev/usb/if_run.c
977
run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count)
sys/dev/usb/if_run.c
982
error = run_write(sc, reg, val);
sys/dev/usb/if_run.c
988
run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val)
sys/dev/usb/if_runvar.h
172
uint8_t val;
sys/dev/usb/if_smsc.c
266
uint32_t val;
sys/dev/usb/if_smsc.c
270
if ((err = smsc_read_reg(sc, reg, &val)) != 0)
sys/dev/usb/if_smsc.c
272
if (!(val & bits))
sys/dev/usb/if_smsc.c
285
uint32_t val = 0;
sys/dev/usb/if_smsc.c
299
smsc_read_reg(sc, SMSC_MII_DATA, &val);
sys/dev/usb/if_smsc.c
303
return (val & 0xFFFF);
sys/dev/usb/if_smsc.c
307
smsc_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_smsc.c
322
smsc_write_reg(sc, SMSC_MII_DATA, val);
sys/dev/usb/if_smsc.c
494
uint32_t val;
sys/dev/usb/if_smsc.c
500
err = smsc_read_reg(sc, SMSC_COE_CTRL, &val);
sys/dev/usb/if_smsc.c
509
val |= SMSC_COE_CTRL_RX_EN;
sys/dev/usb/if_smsc.c
511
val &= ~SMSC_COE_CTRL_RX_EN;
sys/dev/usb/if_smsc.c
515
val |= SMSC_COE_CTRL_TX_EN;
sys/dev/usb/if_smsc.c
517
val &= ~SMSC_COE_CTRL_TX_EN;
sys/dev/usb/if_smsc.c
519
err = smsc_write_reg(sc, SMSC_COE_CTRL, val);
sys/dev/usb/if_smsc.c
533
uint32_t val;
sys/dev/usb/if_smsc.c
539
val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
sys/dev/usb/if_smsc.c
540
if ((err = smsc_write_reg(sc, SMSC_MAC_ADDRL, val)) != 0)
sys/dev/usb/if_smsc.c
543
val = (addr[5] << 8) | addr[4];
sys/dev/usb/if_smsc.c
544
err = smsc_write_reg(sc, SMSC_MAC_ADDRH, val);
sys/dev/usb/if_uaq.c
310
uaq_ctl(struct uaq_softc *sc, uint8_t rw, uint8_t cmd, uint16_t val,
sys/dev/usb/if_uaq.c
324
USETW(req.wValue, val);
sys/dev/usb/if_uaq.c
329
rw, val, index, len));
sys/dev/usb/if_uaq.c
356
uint8_t val;
sys/dev/usb/if_uaq.c
358
uaq_read_mem(sc, cmd, reg, index, &val, 1);
sys/dev/usb/if_uaq.c
360
index, val));
sys/dev/usb/if_uaq.c
361
return (val);
sys/dev/usb/if_uaq.c
367
uint16_t val;
sys/dev/usb/if_uaq.c
369
uaq_read_mem(sc, cmd, reg, index, &val, 2);
sys/dev/usb/if_uaq.c
371
index, UGETW(&val)));
sys/dev/usb/if_uaq.c
373
return (UGETW(&val));
sys/dev/usb/if_uaq.c
379
uint32_t val;
sys/dev/usb/if_uaq.c
381
uaq_read_mem(sc, cmd, reg, index, &val, 4);
sys/dev/usb/if_uaq.c
383
index, UGETDW(&val)));
sys/dev/usb/if_uaq.c
384
return (UGETDW(&val));
sys/dev/usb/if_uaq.c
389
uint32_t val)
sys/dev/usb/if_uaq.c
394
index, val));
sys/dev/usb/if_uaq.c
395
temp = val & 0xff;
sys/dev/usb/if_uaq.c
401
uint32_t val)
sys/dev/usb/if_uaq.c
406
index, val));
sys/dev/usb/if_uaq.c
407
USETW(&temp, val & 0xffff);
sys/dev/usb/if_uaq.c
413
uint32_t val)
sys/dev/usb/if_uaq.c
418
index, val));
sys/dev/usb/if_uaq.c
419
USETDW(temp, val);
sys/dev/usb/if_uath.c
1007
uath_write_reg(struct uath_softc *sc, uint32_t reg, uint32_t val)
sys/dev/usb/if_uath.c
1014
*(uint32_t *)write.data = htobe32(val);
sys/dev/usb/if_uath.c
1047
uath_read_reg(struct uath_softc *sc, uint32_t reg, uint32_t *val)
sys/dev/usb/if_uath.c
1060
*val = betoh32(*(uint32_t *)read.data);
sys/dev/usb/if_uath.c
1594
uint32_t reg, val;
sys/dev/usb/if_uath.c
1618
if ((error = uath_read_reg(sc, reg, &val)) != 0)
sys/dev/usb/if_uath.c
1620
DPRINTFN(2, ("reg 0x%02x=0x%08x\n", reg, val));
sys/dev/usb/if_uath.c
1782
uint32_t val;
sys/dev/usb/if_uath.c
1805
val = htobe32(0);
sys/dev/usb/if_uath.c
1806
error = uath_cmd_write(sc, UATH_CMD_SET_STATE, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
1821
uint32_t val;
sys/dev/usb/if_uath.c
1827
val = htobe32(0);
sys/dev/usb/if_uath.c
1828
(void)uath_cmd_write(sc, UATH_CMD_02, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
1856
error = uath_cmd_read(sc, UATH_CMD_07, NULL, 0, &val,
sys/dev/usb/if_uath.c
1863
DPRINTF(("command 07h return code: %x\n", betoh32(val)));
sys/dev/usb/if_uath.c
1890
val = htobe32(4);
sys/dev/usb/if_uath.c
1891
(void)uath_cmd_write(sc, UATH_CMD_27, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
1892
(void)uath_cmd_write(sc, UATH_CMD_27, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
1928
uint32_t val;
sys/dev/usb/if_uath.c
1940
val = htobe32(0);
sys/dev/usb/if_uath.c
1941
(void)uath_cmd_write(sc, UATH_CMD_SET_STATE, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
1944
val = htobe32(0);
sys/dev/usb/if_uath.c
1945
(void)uath_cmd_write(sc, UATH_CMD_15, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
835
uint32_t val;
sys/dev/usb/if_uath.c
854
val = htobe32(1);
sys/dev/usb/if_uath.c
855
(void)uath_cmd_write(sc, UATH_CMD_2E, &val, sizeof val, 0);
sys/dev/usb/if_uath.c
877
val = htobe32(1);
sys/dev/usb/if_uath.c
878
(void)uath_cmd_write(sc, UATH_CMD_SET_STATE, &val, sizeof val,
sys/dev/usb/if_udav.c
1427
u_int8_t val[2];
sys/dev/usb/if_udav.c
1468
udav_csr_read(sc, UDAV_EPDRL, val, 2);
sys/dev/usb/if_udav.c
1472
data16 = val[0] | (val[1] << 8);
sys/dev/usb/if_udav.c
1484
u_int8_t val[2];
sys/dev/usb/if_udav.c
1516
val[0] = data & 0xff;
sys/dev/usb/if_udav.c
1517
val[1] = (data >> 8) & 0xff;
sys/dev/usb/if_udav.c
1518
udav_csr_write(sc, UDAV_EPDRL, val, 2);
sys/dev/usb/if_udav.c
538
u_int8_t val = 0;
sys/dev/usb/if_udav.c
546
return (udav_csr_read(sc, offset, &val, 1) ? 0 : val);
sys/dev/usb/if_umb.c
2050
uint32_t val;
sys/dev/usb/if_umb.c
2129
val = letoh32(ic->ipv4_mtu);
sys/dev/usb/if_umb.c
2130
if (ifp->if_hardmtu != val && val <= sc->sc_maxpktlen) {
sys/dev/usb/if_umb.c
2132
ifp->if_hardmtu = val;
sys/dev/usb/if_umb.c
2133
if (ifp->if_mtu > val)
sys/dev/usb/if_umb.c
2134
ifp->if_mtu = val;
sys/dev/usb/if_umb.c
2198
val = letoh32(ic->ipv6_mtu);
sys/dev/usb/if_umb.c
2199
if (ifp->if_hardmtu != val && val <= sc->sc_maxpktlen) {
sys/dev/usb/if_umb.c
2201
ifp->if_hardmtu = val;
sys/dev/usb/if_umb.c
2202
if (ifp->if_mtu > val)
sys/dev/usb/if_umb.c
2203
ifp->if_mtu = val;
sys/dev/usb/if_umb.c
3044
uint32_t val;
sys/dev/usb/if_umb.c
3104
if (tlvlen != sizeof (val))
sys/dev/usb/if_umb.c
3106
val = UMB_GET32(&data[3]);
sys/dev/usb/if_umb.c
3109
if (val != 0) {
sys/dev/usb/if_umb.c
3112
val);
sys/dev/usb/if_umb.c
3118
if (val == 0)
sys/dev/usb/if_umb.c
3122
else if (val == 0x001a0001)
sys/dev/usb/if_umb.c
3128
"error 0x%x\n", DEVNAM(sc), val);
sys/dev/usb/if_umb.h
26
int val;
sys/dev/usb/if_umb.h
31
umb_val2descr(const struct umb_valdescr *vdp, int val)
sys/dev/usb/if_umb.h
36
if (vdp->val == val)
sys/dev/usb/if_umb.h
40
snprintf(sval, sizeof (sval), "#%d", val);
sys/dev/usb/if_ure.c
237
ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
sys/dev/usb/if_ure.c
251
USETW(req.wValue, val);
sys/dev/usb/if_ure.c
256
rw, val, index, len));
sys/dev/usb/if_ure.c
283
uint32_t val;
sys/dev/usb/if_ure.c
291
val = UGETDW(temp);
sys/dev/usb/if_ure.c
292
val >>= shift;
sys/dev/usb/if_ure.c
294
return (val & 0xff);
sys/dev/usb/if_ure.c
300
uint32_t val;
sys/dev/usb/if_ure.c
308
val = UGETDW(temp);
sys/dev/usb/if_ure.c
309
val >>= shift;
sys/dev/usb/if_ure.c
311
return (val & 0xffff);
sys/dev/usb/if_ure.c
324
ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
sys/dev/usb/if_ure.c
332
val &= 0xff;
sys/dev/usb/if_ure.c
336
val <<= (shift << 3);
sys/dev/usb/if_ure.c
340
USETDW(temp, val);
sys/dev/usb/if_ure.c
345
ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
sys/dev/usb/if_ure.c
353
val &= 0xffff;
sys/dev/usb/if_ure.c
357
val <<= (shift << 3);
sys/dev/usb/if_ure.c
361
USETDW(temp, val);
sys/dev/usb/if_ure.c
366
ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
sys/dev/usb/if_ure.c
370
USETDW(temp, val);
sys/dev/usb/if_ure.c
526
uint16_t val;
sys/dev/usb/if_ure.c
536
val = ure_phy_read(sc, URE_OCP_BASE_MII + reg * 2);
sys/dev/usb/if_ure.c
539
return val; /* letoh16? */
sys/dev/usb/if_ure.c
543
ure_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_ure.c
548
ure_phy_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */
sys/dev/usb/if_url.c
1271
u_int16_t val;
sys/dev/usb/if_url.c
1307
val = 0;
sys/dev/usb/if_url.c
1322
val = 0;
sys/dev/usb/if_url.c
1328
val = url_csr_read_1(sc, reg);
sys/dev/usb/if_url.c
1330
val = url_csr_read_2(sc, reg);
sys/dev/usb/if_url.c
1334
sc->sc_dev.dv_xname, __func__, phy, reg, val));
sys/dev/usb/if_url.c
1337
return (val);
sys/dev/usb/if_url.c
1430
u_int16_t val;
sys/dev/usb/if_url.c
1461
val = url_csr_read_2(sc, URL_PHYDAT);
sys/dev/usb/if_url.c
1464
sc->sc_dev.dv_xname, __func__, phy, reg, val));
sys/dev/usb/if_url.c
1467
return (val);
sys/dev/usb/if_url.c
394
u_int8_t val = 0;
sys/dev/usb/if_url.c
399
return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
sys/dev/usb/if_url.c
406
uWord val;
sys/dev/usb/if_url.c
411
USETW(val, 0);
sys/dev/usb/if_url.c
412
return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
sys/dev/usb/if_url.c
419
u_int8_t val = aval;
sys/dev/usb/if_url.c
424
return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
sys/dev/usb/if_url.c
431
uWord val;
sys/dev/usb/if_url.c
436
USETW(val, aval);
sys/dev/usb/if_url.c
438
return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
sys/dev/usb/if_url.c
445
uDWord val;
sys/dev/usb/if_url.c
450
USETDW(val, aval);
sys/dev/usb/if_url.c
452
return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
sys/dev/usb/if_urtw.c
101
#define urtw_read8_idx_m(sc, val, data, idx) do { \
sys/dev/usb/if_urtw.c
102
error = urtw_read8_c(sc, val, data, idx); \
sys/dev/usb/if_urtw.c
106
#define urtw_write8_m(sc, val, data) do { \
sys/dev/usb/if_urtw.c
107
error = urtw_write8_c(sc, val, data, 0); \
sys/dev/usb/if_urtw.c
111
#define urtw_write8_idx_m(sc, val, data, idx) do { \
sys/dev/usb/if_urtw.c
112
error = urtw_write8_c(sc, val, data, idx); \
sys/dev/usb/if_urtw.c
116
#define urtw_read16_m(sc, val, data) do { \
sys/dev/usb/if_urtw.c
117
error = urtw_read16_c(sc, val, data, 0); \
sys/dev/usb/if_urtw.c
121
#define urtw_read16_idx_m(sc, val, data, idx) do { \
sys/dev/usb/if_urtw.c
122
error = urtw_read16_c(sc, val, data, idx); \
sys/dev/usb/if_urtw.c
126
#define urtw_write16_m(sc, val, data) do { \
sys/dev/usb/if_urtw.c
127
error = urtw_write16_c(sc, val, data, 0); \
sys/dev/usb/if_urtw.c
131
#define urtw_write16_idx_m(sc, val, data, idx) do { \
sys/dev/usb/if_urtw.c
132
error = urtw_write16_c(sc, val, data, idx); \
sys/dev/usb/if_urtw.c
136
#define urtw_read32_m(sc, val, data) do { \
sys/dev/usb/if_urtw.c
137
error = urtw_read32_c(sc, val, data, 0); \
sys/dev/usb/if_urtw.c
141
#define urtw_read32_idx_m(sc, val, data, idx) do { \
sys/dev/usb/if_urtw.c
142
error = urtw_read32_c(sc, val, data, idx); \
sys/dev/usb/if_urtw.c
146
#define urtw_write32_m(sc, val, data) do { \
sys/dev/usb/if_urtw.c
147
error = urtw_write32_c(sc, val, data, 0); \
sys/dev/usb/if_urtw.c
151
#define urtw_write32_idx_m(sc, val, data, idx) do { \
sys/dev/usb/if_urtw.c
152
error = urtw_write32_c(sc, val, data, idx); \
sys/dev/usb/if_urtw.c
1541
urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx)
sys/dev/usb/if_urtw.c
1548
USETW(req.wValue, val | 0xff00);
sys/dev/usb/if_urtw.c
1557
urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
sys/dev/usb/if_urtw.c
156
#define urtw_8187_write_phy_ofdm(sc, val, data) do { \
sys/dev/usb/if_urtw.c
1564
USETW(req.wValue, val | 0xfe00);
sys/dev/usb/if_urtw.c
157
error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
sys/dev/usb/if_urtw.c
1573
urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx)
sys/dev/usb/if_urtw.c
1580
USETW(req.wValue, val | 0xff00);
sys/dev/usb/if_urtw.c
1590
urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx)
sys/dev/usb/if_urtw.c
1597
USETW(req.wValue, val | 0xff00);
sys/dev/usb/if_urtw.c
1607
urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx)
sys/dev/usb/if_urtw.c
161
#define urtw_8187_write_phy_cck(sc, val, data) do { \
sys/dev/usb/if_urtw.c
1613
USETW(req.wValue, val | 0xff00);
sys/dev/usb/if_urtw.c
162
error = urtw_8187_write_phy_cck_c(sc, val, data); \
sys/dev/usb/if_urtw.c
1621
urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
sys/dev/usb/if_urtw.c
1627
USETW(req.wValue, val | 0xfe00);
sys/dev/usb/if_urtw.c
1635
urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx)
sys/dev/usb/if_urtw.c
1641
USETW(req.wValue, val | 0xff00);
sys/dev/usb/if_urtw.c
1650
urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx)
sys/dev/usb/if_urtw.c
1656
USETW(req.wValue, val | 0xff00);
sys/dev/usb/if_urtw.c
166
#define urtw_8225_write(sc, val, data) do { \
sys/dev/usb/if_urtw.c
167
error = urtw_8225_write_c(sc, val, data); \
sys/dev/usb/if_urtw.c
1679
urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
sys/dev/usb/if_urtw.c
1690
urtw_write32_m(sc, URTW_ANAPARAM, val);
sys/dev/usb/if_urtw.c
1702
urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
sys/dev/usb/if_urtw.c
1713
urtw_write32_m(sc, URTW_ANAPARAM2, val);
sys/dev/usb/if_urtw.c
174
uint32_t val;
sys/dev/usb/if_urtw.c
179
uint8_t val;
sys/dev/usb/if_urtw.c
2029
return (urtw_ratetable[i].val);
sys/dev/usb/if_urtw.c
2041
if (rate == urtw_ratetable[i].val)
sys/dev/usb/if_urtw.c
2869
urtw_8225_rf_part1[i].val);
sys/dev/usb/if_urtw.c
2893
urtw_8225_rf_part2[i].val);
sys/dev/usb/if_urtw.c
2903
urtw_8225_rf_part3[i].val);
sys/dev/usb/if_urtw.c
3277
urtw_8225v2_rf_part1[i].val);
sys/dev/usb/if_urtw.c
3325
urtw_8225v2_rf_part2[i].val);
sys/dev/usb/if_urtw.c
3334
urtw_8225v2_rf_part3[i].val);
sys/dev/usb/if_urtw.c
3714
urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx);
sys/dev/usb/if_urtw.c
3834
urtw_8225v2_b_rf[i].val);
sys/dev/usb/if_urtw.c
96
#define urtw_read8_m(sc, val, data) do { \
sys/dev/usb/if_urtw.c
97
error = urtw_read8_c(sc, val, data, 0); \
sys/dev/usb/if_urtwn.c
2310
rtl8188eu_mac[i].val);
sys/dev/usb/if_urtwn.c
2316
rtl8188ftv_mac[i].val);
sys/dev/usb/if_urtwn.c
2321
rtl8192eu_mac[i].val);
sys/dev/usb/if_urtwn.c
2326
rtl8192cu_mac[i].val);
sys/dev/usb/if_urtwn.c
799
urtwn_write_1(void *cookie, uint16_t addr, uint8_t val)
sys/dev/usb/if_urtwn.c
803
urtwn_write_region_1(sc, addr, &val, 1);
sys/dev/usb/if_urtwn.c
807
urtwn_write_2(void *cookie, uint16_t addr, uint16_t val)
sys/dev/usb/if_urtwn.c
811
val = htole16(val);
sys/dev/usb/if_urtwn.c
812
urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
sys/dev/usb/if_urtwn.c
816
urtwn_write_4(void *cookie, uint16_t addr, uint32_t val)
sys/dev/usb/if_urtwn.c
820
val = htole32(val);
sys/dev/usb/if_urtwn.c
821
urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
sys/dev/usb/if_urtwn.c
842
uint8_t val;
sys/dev/usb/if_urtwn.c
844
if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
sys/dev/usb/if_urtwn.c
846
return (val);
sys/dev/usb/if_urtwn.c
853
uint16_t val;
sys/dev/usb/if_urtwn.c
855
if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
sys/dev/usb/if_urtwn.c
857
return (letoh16(val));
sys/dev/usb/if_urtwn.c
864
uint32_t val;
sys/dev/usb/if_urtwn.c
866
if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
sys/dev/usb/if_urtwn.c
868
return (letoh32(val));
sys/dev/usb/if_wi_usb.c
731
u_int16_t val = 0;
sys/dev/usb/if_wi_usb.c
776
val = PRIVACY_INVOKED;
sys/dev/usb/if_wi_usb.c
787
val |= EXCLUDE_UNENCRYPTED;
sys/dev/usb/if_wi_usb.c
796
val |= HOST_ENCRYPT;
sys/dev/usb/if_wi_usb.c
799
val |= HOST_ENCRYPT|HOST_DECRYPT;
sys/dev/usb/if_wi_usb.c
802
p2ltv.wi_val = htole16(val);
sys/dev/usb/if_zyd.c
1012
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1073
error = zyd_write16(sc, phyini_1[i].reg, phyini_1[i].val);
sys/dev/usb/if_zyd.c
1084
error = zyd_write16(sc, phyini_2[i].reg, phyini_2[i].val);
sys/dev/usb/if_zyd.c
1095
error = zyd_write16(sc, phyini_3[i].reg, phyini_3[i].val);
sys/dev/usb/if_zyd.c
1165
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1232
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1279
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1324
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1360
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1405
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1528
if ((error = zyd_write16(sc, phyp->reg, phyp->val)) != 0)
sys/dev/usb/if_zyd.c
1594
uint16_t val;
sys/dev/usb/if_zyd.c
1620
(void)zyd_read16(sc, ZYD_EEPROM_PWR_CAL + i, &val);
sys/dev/usb/if_zyd.c
1621
sc->pwr_cal[i * 2] = val >> 8;
sys/dev/usb/if_zyd.c
1622
sc->pwr_cal[i * 2 + 1] = val & 0xff;
sys/dev/usb/if_zyd.c
1624
(void)zyd_read16(sc, ZYD_EEPROM_PWR_INT + i, &val);
sys/dev/usb/if_zyd.c
1625
sc->pwr_int[i * 2] = val >> 8;
sys/dev/usb/if_zyd.c
1626
sc->pwr_int[i * 2 + 1] = val & 0xff;
sys/dev/usb/if_zyd.c
1628
(void)zyd_read16(sc, ZYD_EEPROM_36M_CAL + i, &val);
sys/dev/usb/if_zyd.c
1629
sc->ofdm36_cal[i * 2] = val >> 8;
sys/dev/usb/if_zyd.c
1630
sc->ofdm36_cal[i * 2 + 1] = val & 0xff;
sys/dev/usb/if_zyd.c
1632
(void)zyd_read16(sc, ZYD_EEPROM_48M_CAL + i, &val);
sys/dev/usb/if_zyd.c
1633
sc->ofdm48_cal[i * 2] = val >> 8;
sys/dev/usb/if_zyd.c
1634
sc->ofdm48_cal[i * 2 + 1] = val & 0xff;
sys/dev/usb/if_zyd.c
1636
(void)zyd_read16(sc, ZYD_EEPROM_54M_CAL + i, &val);
sys/dev/usb/if_zyd.c
1637
sc->ofdm54_cal[i * 2] = val >> 8;
sys/dev/usb/if_zyd.c
1638
sc->ofdm54_cal[i * 2 + 1] = val & 0xff;
sys/dev/usb/if_zyd.c
795
zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)
sys/dev/usb/if_zyd.c
804
*val = letoh16(odata[0].val);
sys/dev/usb/if_zyd.c
810
zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_zyd.c
821
*val = letoh16(odata[0].val) << 16 | letoh16(odata[1].val);
sys/dev/usb/if_zyd.c
854
zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_zyd.c
859
io.val = htole16(val);
sys/dev/usb/if_zyd.c
864
zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_zyd.c
869
io[0].val = htole16(val >> 16);
sys/dev/usb/if_zyd.c
871
io[1].val = htole16(val & 0xffff);
sys/dev/usb/if_zyd.c
877
zyd_rfwrite(struct zyd_softc *sc, uint32_t val)
sys/dev/usb/if_zyd.c
891
if (val & (1 << (rf->width - 1 - i)))
sys/dev/usb/if_zyd.c
930
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
982
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
989
phy2230s[i].val);
sys/dev/usb/if_zydreg.h
1071
uint16_t val;
sys/dev/usb/if_zydreg.h
1110
uint8_t val;
sys/dev/usb/if_zydreg.h
1115
uint32_t val;
sys/dev/usb/moscom.c
296
int val;
sys/dev/usb/moscom.c
300
val = onoff ? MOSCOM_MCR_DTR : 0;
sys/dev/usb/moscom.c
303
val = onoff ? MOSCOM_MCR_RTS : 0;
sys/dev/usb/moscom.c
306
val = sc->sc_lcr;
sys/dev/usb/moscom.c
308
val |= MOSCOM_LCR_BREAK;
sys/dev/usb/moscom.c
309
moscom_cmd(sc, MOSCOM_LCR, val);
sys/dev/usb/moscom.c
315
moscom_cmd(sc, MOSCOM_MCR, val);
sys/dev/usb/moscom.c
380
moscom_cmd(struct moscom_softc *sc, int reg, int val)
sys/dev/usb/moscom.c
387
USETW(req.wValue, val + MOSCOM_UART_REG);
sys/dev/usb/uaudio.c
2122
char *name, val;
sys/dev/usb/uaudio.c
2288
&val, 1)) {
sys/dev/usb/uaudio.c
2294
if (--val == 0)
sys/dev/usb/uaudio.c
3556
int32_t val;
sys/dev/usb/uaudio.c
3574
val = buf[0] | buf[1] << 8 | buf[2] << 16;
sys/dev/usb/uaudio.c
3576
val |= xfer->buf[3] << 24;
sys/dev/usb/uaudio.c
3578
val <<= 2;
sys/dev/usb/uaudio.c
3579
val *= UAUDIO_SPF_DIV / (1 << 16);
sys/dev/usb/uaudio.c
3584
__func__, tv.tv_sec, tv.tv_usec, val);
sys/dev/usb/uaudio.c
3587
if (val > s->spf_max)
sys/dev/usb/uaudio.c
3589
else if (val < s->spf_min)
sys/dev/usb/uaudio.c
3592
s->spf = val;
sys/dev/usb/uaudio.c
4318
int i, nch, val, req_num;
sys/dev/usb/uaudio.c
4345
if (!uaudio_getnum(&p, 1, &val))
sys/dev/usb/uaudio.c
4347
ctl->un.ord = !!val;
sys/dev/usb/uaudio.c
4365
if (!uaudio_getnum(&p, 2, &val))
sys/dev/usb/uaudio.c
4369
uaudio_sign_expand(val, 2));
sys/dev/usb/uaudio.c
4386
unsigned int val;
sys/dev/usb/uaudio.c
4412
val = uaudio_ranges_encode(&m->ranges,
sys/dev/usb/uaudio.c
4415
i, ctl->un.value.level[i], val);
sys/dev/usb/uaudio.c
4416
req_buf[0] = val;
sys/dev/usb/uaudio.c
4417
req_buf[1] = val >> 8;
sys/dev/usb/uaudio.c
516
uaudio_sign_expand(unsigned int val, int opsize)
sys/dev/usb/uaudio.c
521
return (val ^ s) - s;
sys/dev/usb/uaudio.c
832
uaudio_ranges_decode(struct uaudio_ranges *r, int val)
sys/dev/usb/uaudio.c
840
if (val >= e->min && val <= e->max) {
sys/dev/usb/uaudio.c
841
pos += val - e->min;
sys/dev/usb/uaudio.c
856
uaudio_ranges_encode(struct uaudio_ranges *r, int val)
sys/dev/usb/uaudio.c
861
pos = (val * (r->nval - 1) + 127) / 255;
sys/dev/usb/uchcom.c
512
uchcom_set_dtrrts_10(struct uchcom_softc *sc, uint8_t val)
sys/dev/usb/uchcom.c
514
return uchcom_write_reg(sc, UCHCOM_REG_STAT1, val, UCHCOM_REG_STAT1,
sys/dev/usb/uchcom.c
515
val);
sys/dev/usb/uchcom.c
519
uchcom_set_dtrrts_20(struct uchcom_softc *sc, uint8_t val)
sys/dev/usb/uchcom.c
521
return uchcom_generic_control_out(sc, UCHCOM_REQ_SET_DTRRTS, val, 0);
sys/dev/usb/uchcom.c
577
uint8_t val = 0;
sys/dev/usb/uchcom.c
579
if (dtr) val |= UCHCOM_DTR_MASK;
sys/dev/usb/uchcom.c
580
if (rts) val |= UCHCOM_RTS_MASK;
sys/dev/usb/uchcom.c
583
err = uchcom_set_dtrrts_10(sc, ~val);
sys/dev/usb/uchcom.c
585
err = uchcom_set_dtrrts_20(sc, ~val);
sys/dev/usb/uchcom.c
666
uchcom_set_dte_rate(struct uchcom_softc *sc, uint32_t rate, uint16_t val)
sys/dev/usb/uchcom.c
678
(err = uchcom_write_reg(sc, UCHCOM_REG_LCR, val >> 8,
sys/dev/usb/uchcom.c
684
UCHCOM_REQ_SET_BAUDRATE, val, idx)))
sys/dev/usb/uchcom.c
697
uchcom_set_line_control(struct uchcom_softc *sc, tcflag_t cflag, uint16_t *val)
sys/dev/usb/uchcom.c
748
*val = UCHCOM_T | UCHCOM_CL | UCHCOM_CT | lcr << 8;
sys/dev/usb/uchcom.c
749
*val |= (sc->sc_type != UCHCOM_TYPE_CH343) ? 0x10 : 0;
sys/dev/usb/uchcom.c
855
uint16_t val = 0;
sys/dev/usb/uchcom.c
866
ret = uchcom_set_line_control(sc, t->c_cflag, &val);
sys/dev/usb/uchcom.c
870
ret = uchcom_set_dte_rate(sc, t->c_ospeed, val);
sys/dev/usb/udl.c
1782
udl_cmd_write_reg_1(struct udl_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/udl.c
1787
udl_cmd_insert_int_1(sc, val);
sys/dev/usb/udl.c
1791
udl_cmd_write_reg_3(struct udl_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/udl.c
1793
udl_cmd_write_reg_1(sc, reg + 0, (val >> 16) & 0xff);
sys/dev/usb/udl.c
1794
udl_cmd_write_reg_1(sc, reg + 1, (val >> 8) & 0xff);
sys/dev/usb/udl.c
1795
udl_cmd_write_reg_1(sc, reg + 2, (val >> 0) & 0xff);
sys/dev/usb/umct.c
402
u_int val;
sys/dev/usb/umct.c
407
case 300: val = 0x01; break;
sys/dev/usb/umct.c
408
case 600: val = 0x02; break;
sys/dev/usb/umct.c
409
case 1200: val = 0x03; break;
sys/dev/usb/umct.c
410
case 2400: val = 0x04; break;
sys/dev/usb/umct.c
411
case 4800: val = 0x06; break;
sys/dev/usb/umct.c
412
case 9600: val = 0x08; break;
sys/dev/usb/umct.c
413
case 19200: val = 0x09; break;
sys/dev/usb/umct.c
414
case 38400: val = 0x0a; break;
sys/dev/usb/umct.c
415
case 57600: val = 0x0b; break;
sys/dev/usb/umct.c
416
case 115200: val = 0x0c; break;
sys/dev/usb/umct.c
417
default: val = -1; break;
sys/dev/usb/umct.c
420
val = UMCT_BAUD_RATE(rate);
sys/dev/usb/umct.c
422
USETDW(arate, val);
sys/dev/usb/uoak.h
99
uint8_t val[26];
sys/dev/usb/uoak_subr.c
183
sc->sc_rcmd.val[0] = (uint8_t)(rate & 0xff);
sys/dev/usb/uoak_subr.c
184
sc->sc_rcmd.val[1] = (uint8_t)((rate >> 8) & 0xff)
sys/dev/usb/uoak_subr.c
186
USETW(sc->sc_rcmd.val, rate);
sys/dev/usb/uoak_subr.c
221
sc->sc_rcmd.val[0] = mode;
sys/dev/usb/uoak_subr.c
320
uoak_sensor_update(struct uoak_sensor *s, int val)
sys/dev/usb/uoak_subr.c
327
s->vmax = s->vmin = s->vavg = val;
sys/dev/usb/uoak_subr.c
333
if (val > s->vmax)
sys/dev/usb/uoak_subr.c
334
s->vmax = val;
sys/dev/usb/uoak_subr.c
335
else if (val < s->vmin)
sys/dev/usb/uoak_subr.c
336
s->vmin = val;
sys/dev/usb/uoak_subr.c
339
s->vavg = (s->vavg * s->count + val) / (s->count + 1);
sys/dev/usb/uoaklux.c
224
int frame, val;
sys/dev/usb/uoaklux.c
231
val = (scc->sc_ibuf[3] << 8) + (scc->sc_ibuf[2]);
sys/dev/usb/uoaklux.c
232
uoak_sensor_update(&sc->sc_sensor.lux, val);
sys/dev/usb/uoakv.c
229
int16_t val;
sys/dev/usb/uoakv.c
239
val = (int16_t)((scc->sc_ibuf[idx+1] << 8) | scc->sc_ibuf[idx]);
sys/dev/usb/uoakv.c
240
uoak_sensor_update(&sc->sc_sensor[i].v, val);
sys/dev/usb/uplcom.c
224
uByte val;
sys/dev/usb/uplcom.c
273
err = usbd_do_request(sc->sc_udev, &req, &val);
sys/dev/usb/uslhcom.c
212
u_char val;
sys/dev/usb/uslhcom.c
214
len = sizeof(val);
sys/dev/usb/uslhcom.c
215
val = enable;
sys/dev/usb/uslhcom.c
218
GET_SET_UART_ENABLE, &val, len) != len;
sys/dev/usb/uslhcom.c
225
u_char val;
sys/dev/usb/uslhcom.c
227
len = sizeof(val);
sys/dev/usb/uslhcom.c
228
val = fifo;
sys/dev/usb/uslhcom.c
231
SET_CLEAR_FIFOS, &val, len) != len;
sys/dev/usb/uslhcom.c
260
u_char val;
sys/dev/usb/uslhcom.c
262
len = sizeof(val);
sys/dev/usb/uslhcom.c
265
val = 0; /* send break until SET_STOP_LINE_BREAK */
sys/dev/usb/uslhcom.c
268
val = 0; /* any value can be accepted */
sys/dev/usb/uslhcom.c
273
reportid, &val, len) != len;
sys/dev/usb/usps.c
328
usps_cmd(struct usps_softc *sc, uint8_t cmd, uint16_t val, uint16_t len)
sys/dev/usb/usps.c
335
USETW(req.wValue, val);
sys/dev/usb/usps.c
508
uint val;
sys/dev/usb/usps.c
534
val = (sc->sc_buf[1] << 8) + sc->sc_buf[0];
sys/dev/usb/usps.c
535
if (val == 0) {
sys/dev/usb/usps.c
542
f /= val;
sys/dev/usb/uthum.c
364
int val, dev_type;
sys/dev/usb/uthum.c
396
val = (dinfo.cal[1][0] - UTHUM_CAL_OFFSET) * 100;
sys/dev/usb/uthum.c
397
val += dinfo.cal[1][1] * 10;
sys/dev/usb/uthum.c
398
sc->sc_sensor[1].cal_offset = val;
sys/dev/usb/uthum.c
401
val = (dinfo.cal[0][0] - UTHUM_CAL_OFFSET) * 100;
sys/dev/usb/uthum.c
402
val += dinfo.cal[0][1] * 10;
sys/dev/usb/uthum.c
403
sc->sc_sensor[0].cal_offset = val;
sys/dev/usb/uthum.c
508
uthum_ntc_getdata(struct uthum_softc *sc, int *val)
sys/dev/usb/uthum.c
512
if (val == NULL)
sys/dev/usb/uthum.c
528
*val = (buf[0] << 8) + buf[1];
sys/dev/usb/uthum.c
533
uthum_ntc_tuning(struct uthum_softc *sc, int sensor, int *val)
sys/dev/usb/uthum.c
543
if (val == NULL) {
sys/dev/usb/uthum.c
554
curval = *val;
sys/dev/usb/uthum.c
605
if (val != NULL)
sys/dev/usb/uthum.c
606
*val = curval;
sys/dev/usb/uthum.c
706
int val;
sys/dev/usb/uthum.c
710
if (uthum_ntc_getdata(sc, &val)) {
sys/dev/usb/uthum.c
717
if ((val < UTHUM_NTC_MIN_THRESHOLD) ||
sys/dev/usb/uthum.c
718
(val > UTHUM_NTC_MAX_THRESHOLD)) {
sys/dev/usb/uthum.c
719
if (uthum_ntc_tuning(sc, UTHUM_TEMPER_NTC, &val)) {
sys/dev/usb/uthum.c
726
temp = uthum_ntc_temp(val, sc->sc_sensor[sensor].cur_state);
sys/dev/usb/uthum.c
742
int val;
sys/dev/usb/uthum.c
746
val = (msb << 8) | lsb;
sys/dev/usb/uthum.c
747
if (val >= 32768)
sys/dev/usb/uthum.c
748
val = val - 65536;
sys/dev/usb/uthum.c
749
val = (val * 100) >> 8;
sys/dev/usb/uthum.c
751
return val;
sys/dev/usb/uthum.c
788
uthum_ntc_temp(int64_t val, int state)
sys/dev/usb/uthum.c
801
temp = ((val * val * 2977) / 100000) - (val * 4300) + 152450000;
sys/dev/usb/uthum.c
804
temp = ((val * val * 3887) / 100000) - (val * 5300) + 197590000;
sys/dev/usb/uthum.c
807
temp = ((val * val * 3495) / 100000) - (val * 5000) + 210590000;
sys/dev/usb/uthum.c
810
if (val < UTHUM_NTC_MIN_THRESHOLD)
sys/dev/usb/uthum.c
811
temp = (val * -1700) + 149630000;
sys/dev/usb/uthum.c
813
temp = ((val * val * 3257) / 100000) - (val * 4900) +
sys/dev/usb/utwitch.c
202
uint32_t val;
sys/dev/usb/utwitch.c
229
val = (buf[2] << 24) + (buf[3] << 16) + (buf[4] << 8) + buf[5];
sys/dev/usb/utwitch.c
231
sc->sc_oldval = val;
sys/dev/usb/utwitch.c
234
sc->sc_sensor_val.value = val;
sys/dev/usb/utwitch.c
235
sc->sc_curval = val;
sys/dev/usb/utwitch.c
236
DPRINTF(("recv value update message: %d\n", val));
sys/dev/usb/utwitch.c
261
utwitch_set_mode(struct utwitch_softc *sc, uint8_t val)
sys/dev/usb/utwitch.c
269
req[1] = val;
sys/dev/usb/utwitch.c
302
utwitch_write_value_request(struct utwitch_softc *sc, uint32_t val)
sys/dev/usb/utwitch.c
313
v = htobe32(val);
sys/dev/videomode/vesagtf.c
192
print_value(int n, const char *name, unsigned val)
sys/dev/videomode/vesagtf.c
194
printf("%2d: %-27s: %u\n", n, name, val);
sys/dev/videomode/vesagtf.c
197
#define print_value(n, name, val)
sys/dev/wscons/wskbd.c
1943
int step, val;
sys/dev/wscons/wskbd.c
1957
val = (cmd == KBD_BACKLIGHT_UP) ? data.curval + step :
sys/dev/wscons/wskbd.c
1960
data.curval = (val > 0xff) ? 0xff : (val < 0) ? 0 : val;
sys/dev/wscons/wsmouse.c
1001
*rmdr = -(-val & 0xfff);
sys/dev/wscons/wsmouse.c
1002
return -(-val >> 12);
sys/dev/wscons/wsmouse.c
1525
int i, val, key, needreset = 0, error = 0;
sys/dev/wscons/wsmouse.c
1529
val = params[i].value;
sys/dev/wscons/wsmouse.c
1532
input->filter.pressure_lo = val;
sys/dev/wscons/wsmouse.c
1533
if (val > input->filter.pressure_hi)
sys/dev/wscons/wsmouse.c
1534
input->filter.pressure_hi = val;
sys/dev/wscons/wsmouse.c
1538
input->filter.pressure_hi = val;
sys/dev/wscons/wsmouse.c
1539
if (val < input->filter.pressure_lo)
sys/dev/wscons/wsmouse.c
1540
input->filter.pressure_lo = val;
sys/dev/wscons/wsmouse.c
1541
input->touch.min_pressure = val;
sys/dev/wscons/wsmouse.c
1544
input->filter.h.hysteresis = val;
sys/dev/wscons/wsmouse.c
1547
input->filter.v.hysteresis = val;
sys/dev/wscons/wsmouse.c
1550
input->filter.dclr = val;
sys/dev/wscons/wsmouse.c
1554
input->filter.h.scale = val;
sys/dev/wscons/wsmouse.c
1557
input->filter.v.scale = val;
sys/dev/wscons/wsmouse.c
1560
input->filter.tracking_maxdist = val;
sys/dev/wscons/wsmouse.c
1563
input->filter.swapxy = val;
sys/dev/wscons/wsmouse.c
1566
input->filter.h.inv = val;
sys/dev/wscons/wsmouse.c
1569
input->filter.v.inv = val;
sys/dev/wscons/wsmouse.c
1572
if (val)
sys/dev/wscons/wsmouse.c
1578
input->filter.h.dmax = val;
sys/dev/wscons/wsmouse.c
1581
input->filter.v.dmax = val;
sys/dev/wscons/wsmouse.c
1585
input->filter.mode |= (val & SMOOTHING_MASK);
sys/dev/wscons/wsmouse.c
1588
if (val)
sys/dev/wscons/wsmouse.c
1594
if (val)
sys/dev/wscons/wsmouse.c
1601
error = wstpad_set_param(input, key, val);
sys/dev/wscons/wsmouse.c
994
scale(int val, int factor, int *rmdr)
sys/dev/wscons/wsmouse.c
996
val = val * factor + *rmdr;
sys/dev/wscons/wsmouse.c
997
if (val >= 0) {
sys/dev/wscons/wsmouse.c
998
*rmdr = val & 0xfff;
sys/dev/wscons/wsmouse.c
999
return (val >> 12);
sys/dev/wscons/wstpad.c
1744
wstpad_set_param(struct wsmouseinput *input, int key, int val)
sys/dev/wscons/wstpad.c
1783
if (val)
sys/dev/wscons/wstpad.c
1789
tp->params.left_edge = val;
sys/dev/wscons/wstpad.c
1792
tp->params.right_edge = val;
sys/dev/wscons/wstpad.c
1795
tp->params.top_edge = val;
sys/dev/wscons/wstpad.c
1798
tp->params.bottom_edge = val;
sys/dev/wscons/wstpad.c
1801
tp->params.center_width = val;
sys/dev/wscons/wstpad.c
1804
tp->scroll.hdist = val;
sys/dev/wscons/wstpad.c
1807
tp->scroll.vdist = val;
sys/dev/wscons/wstpad.c
1810
tp->params.f2width = val;
sys/dev/wscons/wstpad.c
1813
tp->params.f2pressure = val;
sys/dev/wscons/wstpad.c
1816
tp->tap.maxtime.tv_nsec = imin(val, 999) * 1000000;
sys/dev/wscons/wstpad.c
1819
tp->tap.clicktime = val;
sys/dev/wscons/wstpad.c
1822
tp->tap.locktime = val;
sys/dev/wscons/wstpad.c
1825
tp->tap.btnmap[0] = BTNMASK(val);
sys/dev/wscons/wstpad.c
1828
tp->tap.btnmap[1] = BTNMASK(val);
sys/dev/wscons/wstpad.c
1831
tp->tap.btnmap[2] = BTNMASK(val);
sys/dev/wscons/wstpad.c
1835
tp->params.mtbtn_maxdist = val;
sys/dev/wscons/wstpad.c
250
normalize_abs(struct axis_filter *filter, int val)
sys/dev/wscons/wstpad.c
252
return (filter->inv ? filter->inv - val : val);
sys/dev/wscons/wstpad.c
256
normalize_rel(struct axis_filter *filter, int val)
sys/dev/wscons/wstpad.c
258
return (filter->inv ? -val : val);
sys/dev/x86emu/x86emu.c
1072
write_back_byte(struct x86emu *emu, uint8_t val)
sys/dev/x86emu/x86emu.c
1075
store_data_byte(emu, emu->cur_offset, val);
sys/dev/x86emu/x86emu.c
1077
*decode_rl_byte_register(emu) = val;
sys/dev/x86emu/x86emu.c
1081
write_back_word(struct x86emu *emu, uint16_t val)
sys/dev/x86emu/x86emu.c
1084
store_data_word(emu, emu->cur_offset, val);
sys/dev/x86emu/x86emu.c
1086
*decode_rl_word_register(emu) = val;
sys/dev/x86emu/x86emu.c
1090
write_back_long(struct x86emu *emu, uint32_t val)
sys/dev/x86emu/x86emu.c
1093
store_data_long(emu, emu->cur_offset, val);
sys/dev/x86emu/x86emu.c
1095
*decode_rl_long_register(emu) = val;
sys/dev/x86emu/x86emu.c
2578
uint8_t val;
sys/dev/x86emu/x86emu.c
2595
val = fetch_data_byte(emu, emu->x86.R_SI);
sys/dev/x86emu/x86emu.c
2596
store_byte(emu, emu->x86.R_ES, emu->x86.R_DI, val);
sys/dev/x86emu/x86emu.c
2609
uint32_t val;
sys/dev/x86emu/x86emu.c
2631
val = fetch_data_long(emu, emu->x86.R_SI);
sys/dev/x86emu/x86emu.c
2632
store_long(emu, emu->x86.R_ES, emu->x86.R_DI, val);
sys/dev/x86emu/x86emu.c
2634
val = fetch_data_word(emu, emu->x86.R_SI);
sys/dev/x86emu/x86emu.c
2636
(uint16_t) val);
sys/dev/x86emu/x86emu.c
2973
uint32_t val;
sys/dev/x86emu/x86emu.c
2988
val = fetch_long(emu, emu->x86.R_ES,
sys/dev/x86emu/x86emu.c
2990
cmp_long(emu, emu->x86.R_EAX, val);
sys/dev/x86emu/x86emu.c
2992
val = fetch_word(emu, emu->x86.R_ES,
sys/dev/x86emu/x86emu.c
2994
cmp_word(emu, emu->x86.R_AX, (uint16_t) val);
sys/dev/x86emu/x86emu.c
3007
val = fetch_long(emu, emu->x86.R_ES,
sys/dev/x86emu/x86emu.c
3009
cmp_long(emu, emu->x86.R_EAX, val);
sys/dev/x86emu/x86emu.c
3011
val = fetch_word(emu, emu->x86.R_ES,
sys/dev/x86emu/x86emu.c
3013
cmp_word(emu, emu->x86.R_AX, (uint16_t) val);
sys/dev/x86emu/x86emu.c
3023
val = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI);
sys/dev/x86emu/x86emu.c
3024
cmp_long(emu, emu->x86.R_EAX, val);
sys/dev/x86emu/x86emu.c
3026
val = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI);
sys/dev/x86emu/x86emu.c
3027
cmp_word(emu, emu->x86.R_AX, (uint16_t) val);
sys/dev/x86emu/x86emu.c
53
static void store_data_byte (struct x86emu *, uint32_t offset, uint8_t val);
sys/dev/x86emu/x86emu.c
539
store_data_byte(struct x86emu *emu, uint32_t offset, uint8_t val)
sys/dev/x86emu/x86emu.c
54
static void store_byte (struct x86emu *, uint32_t segment, uint32_t offset, uint8_t val);
sys/dev/x86emu/x86emu.c
541
store_byte(emu, get_data_segment(emu), offset, val);
sys/dev/x86emu/x86emu.c
55
static void store_data_word (struct x86emu *, uint32_t offset, uint16_t val);
sys/dev/x86emu/x86emu.c
556
store_data_word(struct x86emu *emu, uint32_t offset, uint16_t val)
sys/dev/x86emu/x86emu.c
558
store_word(emu, get_data_segment(emu), offset, val);
sys/dev/x86emu/x86emu.c
56
static void store_word (struct x86emu *, uint32_t segment, uint32_t offset, uint16_t val);
sys/dev/x86emu/x86emu.c
57
static void store_data_long (struct x86emu *, uint32_t offset, uint32_t val);
sys/dev/x86emu/x86emu.c
573
store_data_long(struct x86emu *emu, uint32_t offset, uint32_t val)
sys/dev/x86emu/x86emu.c
575
store_long(emu, get_data_segment(emu), offset, val);
sys/dev/x86emu/x86emu.c
58
static void store_long (struct x86emu *, uint32_t segment, uint32_t offset, uint32_t val);
sys/dev/x86emu/x86emu.c
590
store_byte(struct x86emu *emu, uint32_t segment, uint32_t offset, uint8_t val)
sys/dev/x86emu/x86emu.c
592
(*emu->emu_wrb) (emu, ((uint32_t) segment << 4) + offset, val);
sys/dev/x86emu/x86emu.c
607
store_word(struct x86emu *emu, uint32_t segment, uint32_t offset, uint16_t val)
sys/dev/x86emu/x86emu.c
609
(*emu->emu_wrw) (emu, ((uint32_t) segment << 4) + offset, val);
sys/dev/x86emu/x86emu.c
624
store_long(struct x86emu *emu, uint32_t segment, uint32_t offset, uint32_t val)
sys/dev/x86emu/x86emu.c
626
(*emu->emu_wrl) (emu, ((uint32_t) segment << 4) + offset, val);
sys/dev/x86emu/x86emu.h
159
void (*emu_wrb)(struct x86emu *, uint32_t addr,uint8_t val);
sys/dev/x86emu/x86emu.h
160
void (*emu_wrw)(struct x86emu *, uint32_t addr, uint16_t val);
sys/dev/x86emu/x86emu.h
161
void (*emu_wrl)(struct x86emu *, uint32_t addr, uint32_t val);
sys/dev/x86emu/x86emu.h
166
void (*emu_outb)(struct x86emu *, uint16_t addr, uint8_t val);
sys/dev/x86emu/x86emu.h
167
void (*emu_outw)(struct x86emu *, uint16_t addr, uint16_t val);
sys/dev/x86emu/x86emu.h
168
void (*emu_outl)(struct x86emu *, uint16_t addr, uint32_t val);
sys/dev/x86emu/x86emu_util.c
130
wrb(struct x86emu *emu, uint32_t addr, uint8_t val)
sys/dev/x86emu/x86emu_util.c
134
emu->mem_base[addr] = val;
sys/dev/x86emu/x86emu_util.c
146
wrw(struct x86emu *emu, uint32_t addr, uint16_t val)
sys/dev/x86emu/x86emu_util.c
154
*((a + 0)) = (val >> 0) & 0xff;
sys/dev/x86emu/x86emu_util.c
155
*((a + 1)) = (val >> 8) & 0xff;
sys/dev/x86emu/x86emu_util.c
157
*((u_int16_t *)(emu->mem_base + addr)) = htole16(val);
sys/dev/x86emu/x86emu_util.c
159
*((u_int16_t *)(emu->mem_base + addr)) = htole16(val);
sys/dev/x86emu/x86emu_util.c
172
wrl(struct x86emu *emu, uint32_t addr, uint32_t val)
sys/dev/x86emu/x86emu_util.c
180
*((a + 0) = (val >> 0) & 0xff;
sys/dev/x86emu/x86emu_util.c
181
*((a + 1) = (val >> 8) & 0xff;
sys/dev/x86emu/x86emu_util.c
182
*((a + 2) = (val >> 16) & 0xff;
sys/dev/x86emu/x86emu_util.c
183
*((a + 3) = (val >> 24) & 0xff;
sys/dev/x86emu/x86emu_util.c
185
*((u_int32_t *)(emu->mem_base + addr)) = htole32(val);
sys/dev/x86emu/x86emu_util.c
187
*((u_int32_t *)(emu->mem_base + addr)) = htole32(val);
sys/isofs/cd9660/cd9660_vfsops.c
359
mp->mnt_stat.f_fsid.val[0] = (long)dev;
sys/isofs/cd9660/cd9660_vfsops.c
360
mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
sys/isofs/udf/udf_vfsops.c
252
mp->mnt_stat.f_fsid.val[0] = devvp->v_rdev;
sys/isofs/udf/udf_vfsops.c
253
mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
sys/kern/kern_event.c
211
#define KN_HASH(val, mask) (((val) ^ (val >> 8)) & (mask))
sys/kern/kern_fork.c
311
int maxthread_local, val;
sys/kern/kern_fork.c
323
val = atomic_inc_int_nv(&nthreads);
sys/kern/kern_fork.c
324
if ((val > maxthread_local - 5 && uid != 0) ||
sys/kern/kern_fork.c
325
val > maxthread_local) {
sys/kern/kern_resource.c
796
rlim_t val;
sys/kern/kern_resource.c
801
val = pr->ps_limit->pl_rlimit[which].rlim_cur;
sys/kern/kern_resource.c
803
return (val);
sys/kern/kern_sig.c
2164
initsiginfo(siginfo_t *si, int sig, u_long trapno, int code, union sigval val)
sys/kern/kern_sig.c
2171
si->si_value = val;
sys/kern/kern_sig.c
2178
si->si_addr = val.sival_ptr;
sys/kern/kern_sysctl.c
1188
sysctl_rdint(void *oldp, size_t *oldlenp, void *newp, int val)
sys/kern/kern_sysctl.c
1198
error = copyout((caddr_t)&val, oldp, sizeof(int));
sys/kern/kern_sysctl.c
1321
sysctl_rdquad(void *oldp, size_t *oldlenp, void *newp, int64_t val)
sys/kern/kern_sysctl.c
1331
error = copyout((caddr_t)&val, oldp, sizeof(int64_t));
sys/kern/subr_kubsan.c
267
unsigned long val)
sys/kern/subr_kubsan.c
272
.kr_float_cast_overflow = { data, val },
sys/kern/subr_kubsan.c
292
unsigned long val)
sys/kern/subr_kubsan.c
297
.kr_invalid_value = { data, val },
sys/kern/subr_kubsan.c
329
__ubsan_handle_negate_overflow(struct overflow_data *data, unsigned long val)
sys/kern/subr_kubsan.c
334
.kr_negate_overflow = { data, val },
sys/kern/subr_kubsan.c
421
kubsan_deserialize_int(struct type_descriptor *typ, unsigned long val)
sys/kern/subr_kubsan.c
425
return ((int8_t)val);
sys/kern/subr_kubsan.c
427
return ((int16_t)val);
sys/kern/subr_kubsan.c
429
return ((int32_t)val);
sys/kern/subr_kubsan.c
432
return ((int64_t)val);
sys/kern/subr_kubsan.c
437
kubsan_deserialize_uint(struct type_descriptor *typ, unsigned long val)
sys/kern/subr_kubsan.c
441
return ((uint8_t)val);
sys/kern/subr_kubsan.c
443
return ((uint16_t)val);
sys/kern/subr_kubsan.c
445
return ((uint32_t)val);
sys/kern/subr_kubsan.c
448
return ((uint64_t)val);
sys/kern/subr_kubsan.c
475
kubsan_format_int(struct type_descriptor *typ, unsigned long val,
sys/kern/subr_kubsan.c
481
int64_t i = kubsan_deserialize_int(typ, val);
sys/kern/subr_kubsan.c
484
uint64_t u = kubsan_deserialize_uint(typ, val);
sys/kern/subr_kubsan.c
763
is_negative(struct type_descriptor *typ, unsigned long val)
sys/kern/subr_kubsan.c
765
return (SIGNED(typ) && kubsan_deserialize_int(typ, val) < 0);
sys/kern/subr_kubsan.c
769
is_shift_exponent_too_large(struct type_descriptor *typ, unsigned long val)
sys/kern/subr_kubsan.c
771
return (kubsan_deserialize_int(typ, val) >= NBITS(typ));
sys/kern/subr_pool.c
1305
#define PRWORD(ovflw, fmt, width, fixed, val) do { \
sys/kern/subr_pool.c
1309
(val)) - (width); \
sys/kern/subr_pool.c
1779
unsigned long val;
sys/kern/subr_pool.c
1782
val = pp->pr_cache_magic[0] ^ (u_long)ci;
sys/kern/subr_pool.c
1783
if (*entry != val)
sys/kern/subr_pool.c
1787
val = pp->pr_cache_magic[1] ^ (u_long)ci->ci_next;
sys/kern/subr_pool.c
1788
if (*entry != val)
sys/kern/subr_pool.c
1796
*entry, val);
sys/kern/subr_userconf.c
1018
*val = a;
sys/kern/subr_userconf.c
1041
long i = 0, val, orig;
sys/kern/subr_userconf.c
1066
'a', dev, len, &val);
sys/kern/subr_userconf.c
1068
if (val != -1) {
sys/kern/subr_userconf.c
1069
orig = val;
sys/kern/subr_userconf.c
1070
new = cfdata[val];
sys/kern/subr_userconf.c
1074
'i', dev, len, &val);
sys/kern/subr_userconf.c
1077
if (val != -1) {
sys/kern/subr_userconf.c
1083
userconf_hist_int(val);
sys/kern/subr_userconf.c
1087
for (i = userconf_maxdev; val <= i; i--)
sys/kern/subr_userconf.c
1089
cfdata[val] = new;
sys/kern/subr_userconf.c
1093
if (pv[i] != -1 && pv[i] >= val)
sys/kern/subr_userconf.c
1099
if (cfroots[i] != -1 && cfroots[i] >= val)
sys/kern/subr_userconf.c
1172
userconf_pdev(val);
sys/kern/subr_userconf.c
172
userconf_hist_int(long val)
sys/kern/subr_userconf.c
174
snprintf(userconf_histbuf, sizeof userconf_histbuf, " %ld", val);
sys/kern/subr_userconf.c
194
userconf_pnum(long val)
sys/kern/subr_userconf.c
196
if (val > -2 && val < 16) {
sys/kern/subr_userconf.c
197
printf("%ld",val);
sys/kern/subr_userconf.c
203
printf("0%lo",val);
sys/kern/subr_userconf.c
206
printf("%ld",val);
sys/kern/subr_userconf.c
210
printf("0x%lx",val);
sys/kern/subr_userconf.c
308
userconf_number(char *c, long *val, long limit)
sys/kern/subr_userconf.c
346
*val = neg ? - num : num;
sys/kern/subr_userconf.c
386
userconf_attr(char *cmd, long *val)
sys/kern/subr_userconf.c
409
*val = attr;
sys/kern/subr_userconf.c
415
userconf_modify(char *item, long *val, long limit)
sys/kern/subr_userconf.c
424
userconf_pnum(*val);
sys/kern/subr_userconf.c
434
*val = a;
sys/kern/subr_userconf.c
781
userconf_common_attr_val(short attr, long *val, char routine)
sys/kern/subr_userconf.c
796
if (val == NULL) {
sys/kern/subr_userconf.c
800
if (*val == *l) {
sys/kern/subr_userconf.c
990
userconf_add_read(char *prompt, char field, char *dev, int len, long *val)
sys/kern/subr_userconf.c
997
*val = -1;
sys/kern/sys_futex.c
141
syscallarg(inr) val;
sys/kern/sys_futex.c
147
uint32_t val = SCARG(uap, val);
sys/kern/sys_futex.c
155
error = futex_wait(p, uaddr, val, timeout, flags);
sys/kern/sys_futex.c
158
error = futex_wake(p, uaddr, val, flags, retval);
sys/kern/sys_futex.c
161
error = futex_requeue(p, uaddr, val, g,
sys/kern/sys_futex.c
252
futex_wait(struct proc *p, uint32_t *uaddr, uint32_t val,
sys/kern/sys_futex.c
300
if (cval != val) {
sys/kern/sysv_sem.c
385
if (arg.val > seminfo.semvmx)
sys/kern/sysv_sem.c
387
semaptr->sem_base[semnum].semval = arg.val;
sys/kern/sysv_sem.c
909
sema_reallocate(int val)
sys/kern/sysv_sem.c
913
sema_new = mallocarray(val, sizeof(struct semid_ds_kern *),
sys/kern/sysv_sem.c
917
newseqs = mallocarray(val, sizeof(unsigned short), M_SEM,
sys/kern/sysv_sem.c
925
seminfo.semmni = val;
sys/kern/sysv_sem.c
943
int error, val;
sys/kern/sysv_sem.c
947
val = seminfo.semmni;
sys/kern/sysv_sem.c
949
&val, val, 0xffff);
sys/kern/sysv_sem.c
951
if (error || val == seminfo.semmni)
sys/kern/sysv_sem.c
953
sema_reallocate(val);
sys/kern/sysv_shm.c
575
shm_reallocate(int val)
sys/kern/sysv_shm.c
580
newsegs = mallocarray(val, sizeof(struct shmid_ds *),
sys/kern/sysv_shm.c
587
newseqs = mallocarray(val, sizeof(unsigned short), M_SHM,
sys/kern/sysv_shm.c
593
shminfo.shmmni = val;
sys/kern/sysv_shm.c
603
int error, val;
sys/kern/sysv_shm.c
612
val = shminfo.shmmax;
sys/kern/sysv_shm.c
615
&val, 0, INT_MAX);
sys/kern/sysv_shm.c
616
if (error || val == shminfo.shmmax)
sys/kern/sysv_shm.c
619
shminfo.shmmax = val;
sys/kern/sysv_shm.c
628
val = shminfo.shmmni;
sys/kern/sysv_shm.c
631
&val, val, 0xffff);
sys/kern/sysv_shm.c
633
if (error || val == shminfo.shmmni)
sys/kern/sysv_shm.c
635
shm_reallocate(val);
sys/kern/uipc_syscalls.c
1192
syscallarg(const void *) val;
sys/kern/uipc_syscalls.c
1209
if (SCARG(uap, val)) {
sys/kern/uipc_syscalls.c
1218
error = copyin(SCARG(uap, val), mtod(m, caddr_t),
sys/kern/uipc_syscalls.c
1240
syscallarg(void *) val;
sys/kern/uipc_syscalls.c
1254
if (SCARG(uap, val)) {
sys/kern/uipc_syscalls.c
1264
if (error == 0 && SCARG(uap, val) && valsize && m != NULL) {
sys/kern/uipc_syscalls.c
1267
error = copyout(mtod(m, caddr_t), SCARG(uap, val), valsize);
sys/kern/vfs_subr.c
2305
mp->mnt_stat.f_fsid.val[0], mp->mnt_stat.f_fsid.val[1],
sys/kern/vfs_subr.c
301
if (mp->mnt_stat.f_fsid.val[0] == fsid->val[0] &&
sys/kern/vfs_subr.c
302
mp->mnt_stat.f_fsid.val[1] == fsid->val[1]) {
sys/kern/vfs_subr.c
323
mp->mnt_stat.f_fsid.val[0] = makedev(nblkdev + mtype, 0);
sys/kern/vfs_subr.c
324
mp->mnt_stat.f_fsid.val[1] = mtype;
sys/kern/vfs_subr.c
327
tfsid.val[0] = makedev(nblkdev + mtype, xxxfs_mntid);
sys/kern/vfs_subr.c
328
tfsid.val[1] = mtype;
sys/kern/vfs_subr.c
331
tfsid.val[0]++;
sys/kern/vfs_subr.c
335
mp->mnt_stat.f_fsid.val[0] = tfsid.val[0];
sys/lib/libsa/net.c
122
u_long val;
sys/lib/libsa/net.c
134
val = 0;
sys/lib/libsa/net.c
137
val = (val * 10) + (c - '0');
sys/lib/libsa/net.c
150
if (pp >= parts + 3 || val > 0xff)
sys/lib/libsa/net.c
152
*pp++ = val, cp++;
sys/lib/libsa/net.c
173
if (val > 0xffffff)
sys/lib/libsa/net.c
175
val |= parts[0] << 24;
sys/lib/libsa/net.c
179
if (val > 0xffff)
sys/lib/libsa/net.c
181
val |= (parts[0] << 24) | (parts[1] << 16);
sys/lib/libsa/net.c
185
if (val > 0xff)
sys/lib/libsa/net.c
187
val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
sys/lib/libsa/net.c
191
return (htonl(val));
sys/lib/libsa/netif.c
127
val = netif_match(&cur_if, machdep_hint);
sys/lib/libsa/netif.c
130
printf(" [%d -> %d]", s, val);
sys/lib/libsa/netif.c
132
if (val > best_val) {
sys/lib/libsa/netif.c
133
best_val = val;
sys/lib/libsa/netif.c
93
int val;
sys/lib/libz/crc32.c
507
uLong val;
sys/lib/libz/crc32.c
527
val = *buf++;
sys/lib/libz/crc32.c
528
__asm__ volatile("crc32b %w0, %w0, %w1" : "+r"(crc) : "r"(val));
sys/lib/libz/crc32.c
573
val = x2nmodp((int)last, 6);
sys/lib/libz/crc32.c
574
crc = multmodp(val, crc) ^ crc1;
sys/lib/libz/crc32.c
575
crc = multmodp(val, crc) ^ crc2;
sys/lib/libz/crc32.c
589
val = *buf++;
sys/lib/libz/crc32.c
590
__asm__ volatile("crc32b %w0, %w0, %w1" : "+r"(crc) : "r"(val));
sys/lib/libz/deflate.c
1143
int val;
sys/lib/libz/deflate.c
1154
val = s->gzhead->name[s->gzindex++];
sys/lib/libz/deflate.c
1155
put_byte(s, val);
sys/lib/libz/deflate.c
1156
} while (val != 0);
sys/lib/libz/deflate.c
1165
int val;
sys/lib/libz/deflate.c
1176
val = s->gzhead->comment[s->gzindex++];
sys/lib/libz/deflate.c
1177
put_byte(s, val);
sys/lib/libz/deflate.c
1178
} while (val != 0);
sys/lib/libz/infback.c
358
if (here.val < 16) {
sys/lib/libz/infback.c
360
state->lens[state->have++] = here.val;
sys/lib/libz/infback.c
363
if (here.val == 16) {
sys/lib/libz/infback.c
380
else if (here.val == 17) {
sys/lib/libz/infback.c
480
here = state->lencode[last.val +
sys/lib/libz/infback.c
488
state->length = (unsigned)here.val;
sys/lib/libz/infback.c
492
Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?
sys/lib/libz/infback.c
494
"inflate: literal 0x%02x\n", here.val));
sys/lib/libz/infback.c
538
here = state->distcode[last.val +
sys/lib/libz/infback.c
555
state->offset = (unsigned)here.val;
sys/lib/libz/inffast.c
114
Tracevv((stderr, here->val >= 0x20 && here->val < 0x7f ?
sys/lib/libz/inffast.c
116
"inflate: literal 0x%02x\n", here->val));
sys/lib/libz/inffast.c
117
*out++ = (unsigned char)(here->val);
sys/lib/libz/inffast.c
120
len = (unsigned)(here->val);
sys/lib/libz/inffast.c
145
dist = (unsigned)(here->val);
sys/lib/libz/inffast.c
269
here = dcode + here->val + (hold & ((1U << op) - 1));
sys/lib/libz/inffast.c
283
here = lcode + here->val + (hold & ((1U << op) - 1));
sys/lib/libz/inflate.c
1004
state->length = (unsigned)here.val;
sys/lib/libz/inflate.c
1006
Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?
sys/lib/libz/inflate.c
1008
"inflate: literal 0x%02x\n", here.val));
sys/lib/libz/inflate.c
1050
here = state->distcode[last.val +
sys/lib/libz/inflate.c
1069
state->offset = (unsigned)here.val;
sys/lib/libz/inflate.c
871
if (here.val < 16) {
sys/lib/libz/inflate.c
873
state->lens[state->have++] = here.val;
sys/lib/libz/inflate.c
876
if (here.val == 16) {
sys/lib/libz/inflate.c
893
else if (here.val == 17) {
sys/lib/libz/inflate.c
994
here = state->lencode[last.val +
sys/lib/libz/inftrees.c
127
here.val = (unsigned short)0;
sys/lib/libz/inftrees.c
224
here.val = work[sym];
sys/lib/libz/inftrees.c
228
here.val = base[work[sym] - match];
sys/lib/libz/inftrees.c
232
here.val = 0;
sys/lib/libz/inftrees.c
291
(*table)[low].val = (unsigned short)(next - *table);
sys/lib/libz/inftrees.c
301
here.val = (unsigned short)0;
sys/lib/libz/inftrees.c
404
state.lencode[low].bits, state.lencode[low].val);
sys/lib/libz/inftrees.c
415
state.distcode[low].val);
sys/lib/libz/inftrees.h
27
unsigned short val; /* offset in table or code value */
sys/lib/libz/trees.c
275
int val = (int)value;\
sys/lib/libz/trees.c
276
s->bi_buf |= (ush)val << s->bi_valid;\
sys/lib/libz/trees.c
278
s->bi_buf = (ush)val >> (Buf_size - s->bi_valid);\
sys/miscfs/fuse/fuse_vnops.c
430
vap->va_fsid = fmp->mp->mnt_stat.f_fsid.val[0];
sys/miscfs/fuse/fuse_vnops.c
471
vap->va_fsid = fmp->mp->mnt_stat.f_fsid.val[0];
sys/msdosfs/msdosfs_vfsops.c
521
mp->mnt_stat.f_fsid.val[0] = (long)dev;
sys/msdosfs/msdosfs_vfsops.c
522
mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
sys/net/bridgestp.c
2135
int r = 0, err = 0, val;
sys/net/bridgestp.c
2160
val = ifbp->ifbrp_prio;
sys/net/bridgestp.c
2161
if (val < 0 || val > BSTP_MAX_PRIORITY) {
sys/net/bridgestp.c
2167
val -= val % 4096;
sys/net/bridgestp.c
2168
bs->bs_bridge_priority = val;
sys/net/bridgestp.c
2175
val = ifbp->ifbrp_maxage;
sys/net/bridgestp.c
2178
val *= BSTP_TICK_VAL;
sys/net/bridgestp.c
2180
if (val < BSTP_MIN_MAX_AGE || val > BSTP_MAX_MAX_AGE) {
sys/net/bridgestp.c
2184
bs->bs_bridge_max_age = val;
sys/net/bridgestp.c
2191
val = ifbp->ifbrp_hellotime;
sys/net/bridgestp.c
2194
val *= BSTP_TICK_VAL;
sys/net/bridgestp.c
2201
if (val < BSTP_MIN_HELLO_TIME || val > BSTP_MAX_HELLO_TIME) {
sys/net/bridgestp.c
2205
bs->bs_bridge_htime = val;
sys/net/bridgestp.c
2212
val = ifbp->ifbrp_fwddelay;
sys/net/bridgestp.c
2215
val *= BSTP_TICK_VAL;
sys/net/bridgestp.c
2217
if (val < BSTP_MIN_FORWARD_DELAY ||
sys/net/bridgestp.c
2218
val > BSTP_MAX_FORWARD_DELAY) {
sys/net/bridgestp.c
2222
bs->bs_bridge_fdelay = val;
sys/net/bridgestp.c
2226
val = ifbp->ifbrp_txhc;
sys/net/bridgestp.c
2228
if (val < BSTP_MIN_HOLD_COUNT || val > BSTP_MAX_HOLD_COUNT) {
sys/net/bridgestp.c
2232
bs->bs_txholdcount = val;
sys/net/bridgestp.c
2237
val = ifbr->ifbr_priority;
sys/net/bridgestp.c
2238
if (val < 0 || val > BSTP_MAX_PORT_PRIORITY)
sys/net/bridgestp.c
2242
val -= val % 16;
sys/net/bridgestp.c
2243
bp->bp_priority = val;
sys/net/bridgestp.c
2247
val = ifbr->ifbr_path_cost;
sys/net/bridgestp.c
2248
if (val > BSTP_MAX_PATH_COST) {
sys/net/bridgestp.c
2252
if (val == 0) { /* use auto */
sys/net/bridgestp.c
2256
bp->bp_path_cost = val;
sys/net/bridgestp.c
2262
val = ifbp->ifbrp_proto;
sys/net/bridgestp.c
2265
switch (val) {
sys/net/bridgestp.c
2268
bs->bs_protover = val;
sys/net/ifq.c
875
int val;
sys/net/ifq.c
882
val = ifiq_pressure_return;
sys/net/ifq.c
883
error = sysctl_int(oldp, oldlenp, newp, newlen, &val);
sys/net/ifq.c
886
if (val < 1 || val > ifiq_pressure_drop)
sys/net/ifq.c
888
ifiq_pressure_return = val;
sys/net/ifq.c
891
val = ifiq_pressure_drop;
sys/net/ifq.c
892
error = sysctl_int(oldp, oldlenp, newp, newlen, &val);
sys/net/ifq.c
895
if (ifiq_pressure_return > val)
sys/net/ifq.c
897
ifiq_pressure_drop = val;
sys/net/toeplitz.c
122
unsigned int b, shift, val;
sys/net/toeplitz.c
131
for (val = 0; val < 256; ++val) {
sys/net/toeplitz.c
136
if (val & (1 << shift))
sys/net/toeplitz.c
139
scache->bytes[val] = res;
sys/netinet/ipsec_input.c
138
int val;
sys/netinet/ipsec_input.c
682
if (p->val == oldval) {
sys/netinet/ipsec_input.c
709
if (p->val != oldval)
sys/netinet/ipsec_input.c
710
atomic_store_int(var, p->val);
sys/nfs/nfs_subs.c
1026
vap->va_fsid = vp->v_mount->mnt_stat.f_fsid.val[0];
sys/ntfs/ntfs_vfsops.c
417
mp->mnt_stat.f_fsid.val[0] = dev;
sys/ntfs/ntfs_vfsops.c
418
mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
sys/scsi/scsiconf.h
100
bytes[2] = (val >> 40) & 0xff;
sys/scsi/scsiconf.h
101
bytes[3] = (val >> 32) & 0xff;
sys/scsi/scsiconf.h
102
bytes[4] = (val >> 24) & 0xff;
sys/scsi/scsiconf.h
103
bytes[5] = (val >> 16) & 0xff;
sys/scsi/scsiconf.h
104
bytes[6] = (val >> 8) & 0xff;
sys/scsi/scsiconf.h
105
bytes[7] = val & 0xff;
sys/scsi/scsiconf.h
57
static __inline void _lto2b(u_int32_t val, u_int8_t *bytes);
sys/scsi/scsiconf.h
58
static __inline void _lto3b(u_int32_t val, u_int8_t *bytes);
sys/scsi/scsiconf.h
59
static __inline void _lto4b(u_int32_t val, u_int8_t *bytes);
sys/scsi/scsiconf.h
60
static __inline void _lto8b(u_int64_t val, u_int8_t *bytes);
sys/scsi/scsiconf.h
68
_lto2b(u_int32_t val, u_int8_t *bytes)
sys/scsi/scsiconf.h
71
bytes[0] = (val >> 8) & 0xff;
sys/scsi/scsiconf.h
72
bytes[1] = val & 0xff;
sys/scsi/scsiconf.h
76
_lto3b(u_int32_t val, u_int8_t *bytes)
sys/scsi/scsiconf.h
79
bytes[0] = (val >> 16) & 0xff;
sys/scsi/scsiconf.h
80
bytes[1] = (val >> 8) & 0xff;
sys/scsi/scsiconf.h
81
bytes[2] = val & 0xff;
sys/scsi/scsiconf.h
85
_lto4b(u_int32_t val, u_int8_t *bytes)
sys/scsi/scsiconf.h
88
bytes[0] = (val >> 24) & 0xff;
sys/scsi/scsiconf.h
89
bytes[1] = (val >> 16) & 0xff;
sys/scsi/scsiconf.h
90
bytes[2] = (val >> 8) & 0xff;
sys/scsi/scsiconf.h
91
bytes[3] = val & 0xff;
sys/scsi/scsiconf.h
95
_lto8b(u_int64_t val, u_int8_t *bytes)
sys/scsi/scsiconf.h
98
bytes[0] = (val >> 56) & 0xff;
sys/scsi/scsiconf.h
99
bytes[1] = (val >> 48) & 0xff;
sys/stand/boot/cmd.c
355
long long val[2];
sys/stand/boot/cmd.c
365
val[i-1] = strtoll(cmd.argv[i], &ep, 0);
sys/stand/boot/cmd.c
371
hexdump((void *)(unsigned long)val[0], val[1]);
sys/sys/atomic.h
285
#define WRITE_ONCE(x, val) ({ \
sys/sys/atomic.h
286
typeof(x) __tmp = (val); \
sys/sys/mount.h
45
typedef struct { int32_t val[2]; } fsid_t; /* file system id type */
sys/sys/reboot.h
78
#define B_ADAPTOR(val) (((val) >> B_ADAPTORSHIFT) & B_ADAPTORMASK)
sys/sys/reboot.h
81
#define B_CONTROLLER(val) (((val)>>B_CONTROLLERSHIFT) & B_CONTROLLERMASK)
sys/sys/reboot.h
84
#define B_UNIT(val) (((val) >> B_UNITSHIFT) & B_UNITMASK)
sys/sys/reboot.h
87
#define B_PARTITION(val) (((val) >> B_PARTITIONSHIFT) & B_PARTITIONMASK)
sys/sys/reboot.h
90
#define B_TYPE(val) (((val) >> B_TYPESHIFT) & B_TYPEMASK)
sys/sys/resourcevar.h
103
val = limit->pl_rlimit[which].rlim_cur;
sys/sys/resourcevar.h
105
return (val);
sys/sys/resourcevar.h
98
rlim_t val;
sys/sys/sem.h
80
int val; /* value for SETVAL */
sys/sys/signalvar.h
120
union sigval val);
sys/sys/smr.h
76
#define SMR_PTR_SET_LOCKED(pptr, val) do { \
sys/sys/smr.h
78
WRITE_ONCE(*pptr, val); \
sys/sys/syscallargs.h
402
syscallarg(int) val;
sys/sys/syscallargs.h
529
syscallarg(const void *) val;
sys/sys/syscallargs.h
605
syscallarg(void *) val;
sys/sys/termios.h
84
#define CCEQ(val, c) (c == val ? val != _POSIX_VDISABLE : 0)
sys/sys/tree.h
149
name##_SPLAY_MIN_MAX(struct name *head, int val) \
sys/sys/tree.h
151
name##_SPLAY_MINMAX(head, val); \
sys/sys/tree.h
702
name##_RB_MINMAX(struct name *head, int val) \
sys/sys/tree.h
708
if (val < 0) \
sys/sys/videoio.h
6234
u_int64_t val;
sys/tmpfs/tmpfs_vnops.c
459
vap->va_fsid = vp->v_mount->mnt_stat.f_fsid.val[0];
sys/ufs/ext2fs/ext2fs_vfsops.c
554
mp->mnt_stat.f_fsid.val[0] = (long)dev;
sys/ufs/ext2fs/ext2fs_vfsops.c
555
mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
sys/ufs/ffs/ffs_vfsops.c
760
mp->mnt_stat.f_fsid.val[0] = (long)dev;
sys/ufs/ffs/ffs_vfsops.c
763
mp->mnt_stat.f_fsid.val[1] = fs->fs_id[1];
sys/ufs/ffs/ffs_vfsops.c
765
mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum;
sys/ufs/ufs/ufs_dirhash.c
51
#define WRAPINCR(val, limit) (((val) + 1 == (limit)) ? 0 : ((val) + 1))
sys/ufs/ufs/ufs_dirhash.c
52
#define WRAPDECR(val, limit) (((val) == 0) ? ((limit) - 1) : ((val) - 1))
sys/uvm/uvm_pdaemon.c
175
int val;
sys/uvm/uvm_pdaemon.c
177
val = uvmexp.npages / 30;
sys/uvm/uvm_pdaemon.c
180
val = max(val, (16*1024) >> PAGE_SHIFT);
sys/uvm/uvm_pdaemon.c
183
if (val < uvmexp.reserve_kernel + 1)
sys/uvm/uvm_pdaemon.c
184
val = uvmexp.reserve_kernel + 1;
sys/uvm/uvm_pdaemon.c
185
uvmexp.freemin = val;
sys/uvm/uvm_pdaemon.c
188
val = (uvmexp.freemin * 4) / 3;
sys/uvm/uvm_pdaemon.c
189
if (val <= uvmexp.freemin)
sys/uvm/uvm_pdaemon.c
190
val = uvmexp.freemin + 1;
sys/uvm/uvm_pdaemon.c
191
uvmexp.freetarg = val;
sys/uvm/uvmexp.h
161
void *val;
usr.bin/aucat/aucat.c
693
dev_master(int val)
usr.bin/aucat/aucat.c
700
slotvol = MIDI_TO_ADATA(val);
usr.bin/aucat/aucat.c
704
logx(3, "master volume set to %u", val);
usr.bin/aucat/aucat.c
709
dev_slotvol(int midich, int val)
usr.bin/aucat/aucat.c
717
slotvol = MIDI_TO_ADATA(val);
usr.bin/aucat/aucat.c
720
logx(3, "%s: volume set to %u", s->afile.path, val);
usr.bin/awk/b.c
657
static int set_gototab(fa *f, int state, int ch, int val) /* hide gototab implementation */
usr.bin/awk/b.c
661
f->gototab[state].entries[0].state = val;
usr.bin/awk/b.c
663
return val;
usr.bin/awk/b.c
671
f->gototab[state].entries[f->gototab[state].inuse].state = val;
usr.bin/awk/b.c
673
return val;
usr.bin/awk/b.c
687
item->state = val;
usr.bin/awk/b.c
697
f->gototab[state].entries[tab->inuse].state = val;
usr.bin/awk/b.c
703
return val; /* not used anywhere at the moment */
usr.bin/awk/proto.h
150
#define is_number(s, val) is_valid_number(s, false, NULL, val)
usr.bin/awk/run.c
957
Awkfloat val;
usr.bin/awk/run.c
962
val = getfval(x); /* freebsd: defend against super large field numbers */
usr.bin/awk/run.c
963
if ((Awkfloat)INT_MAX < val)
usr.bin/awk/run.c
965
m = (int) val;
usr.bin/cal/cal.c
479
int display, val;
usr.bin/cal/cal.c
494
val = day / 100;
usr.bin/cal/cal.c
495
if (val) {
usr.bin/cal/cal.c
497
*p++ = val + '0';
usr.bin/cal/cal.c
503
val = day / 10;
usr.bin/cal/cal.c
504
if (val || display)
usr.bin/cal/cal.c
505
*p++ = val + '0';
usr.bin/calendar/io.c
225
int val, var, i;
usr.bin/calendar/io.c
237
val = strtol(p, &p, 10); /* if 0, it's failure */
usr.bin/calendar/io.c
242
return (val);
usr.bin/calendar/io.c
256
if ((val = getmonth(start)) != 0)
usr.bin/calendar/io.c
260
else if ((val = getday(start)) != 0) {
usr.bin/calendar/io.c
266
val += var * 10;
usr.bin/calendar/io.c
278
val = i + 1;
usr.bin/calendar/io.c
283
val = i + 1;
usr.bin/calendar/io.c
298
val += (NUMEV + 1) * var;
usr.bin/calendar/io.c
317
return (val);
usr.bin/cdio/rip.c
119
_parse_val(char *start, char *nxt, int *val)
usr.bin/cdio/rip.c
133
*val = 0;
usr.bin/cdio/rip.c
136
*val += base * (start[n - i - 1] - '0');
usr.bin/cdio/rip.c
58
static int _parse_val(char *start, char *nxt, int *val);
usr.bin/ctfconv/elf.c
251
#define ELF_WRITE_RELOC(buf, val, rsize) \
usr.bin/ctfconv/elf.c
254
uint32_t v32 = val; \
usr.bin/ctfconv/elf.c
257
uint64_t v64 = val; \
usr.bin/ctfconv/parse.c
1013
im = im_new(name, val, 0);
usr.bin/ctfconv/parse.c
1339
uint64_t val = (uint64_t)-1;
usr.bin/ctfconv/parse.c
1345
val = dav->dav_u32;
usr.bin/ctfconv/parse.c
1347
val = dav->dav_u64;
usr.bin/ctfconv/parse.c
1353
dw_loc_parse(&dav->dav_buf, NULL, &val, NULL);
usr.bin/ctfconv/parse.c
1358
val = dav->dav_u8;
usr.bin/ctfconv/parse.c
1362
val = dav->dav_u16;
usr.bin/ctfconv/parse.c
1366
val = dav->dav_u32;
usr.bin/ctfconv/parse.c
1373
val = dav->dav_u64;
usr.bin/ctfconv/parse.c
1376
val = dav->dav_u32;
usr.bin/ctfconv/parse.c
1379
val = 1;
usr.bin/ctfconv/parse.c
1385
return val;
usr.bin/ctfconv/parse.c
987
size_t val = 0;
usr.bin/ctfconv/parse.c
999
val = dav2val(dav, psz);
usr.bin/cvs/config.c
42
char *val, *opt, *ep;
usr.bin/cvs/config.c
45
if ((val = strrchr(opt, '=')) == NULL)
usr.bin/cvs/config.c
48
*(val++) = '\0';
usr.bin/cvs/config.c
52
cvs_tagname = xstrdup(val);
usr.bin/cvs/config.c
54
cvs_umask = strtol(val, &ep, 8);
usr.bin/cvs/config.c
56
if (val == ep || *ep != '\0')
usr.bin/cvs/config.c
58
"invalid", val);
usr.bin/cvs/config.c
61
"invalid", val);
usr.bin/cvs/config.c
64
rl.rlim_cur = (int)strtonum(val, 0, INT_MAX,
usr.bin/cvs/config.c
68
val, errstr);
usr.bin/cvs/cvs.c
539
cvs_var_set(const char *var, const char *val)
usr.bin/cvs/cvs.c
571
vp->cv_val = xstrdup(val);
usr.bin/cvs/modules.c
119
val = p;
usr.bin/cvs/modules.c
120
while (!isspace((unsigned char)*val) && *val != '\0')
usr.bin/cvs/modules.c
121
val++;
usr.bin/cvs/modules.c
122
if (*val == '\0')
usr.bin/cvs/modules.c
125
*(val++) = '\0';
usr.bin/cvs/modules.c
127
p = val;
usr.bin/cvs/modules.c
137
if ((val = strchr(p, ' ' )) == NULL)
usr.bin/cvs/modules.c
140
*(val++) = '\0';
usr.bin/cvs/modules.c
142
p = val;
usr.bin/cvs/modules.c
149
val = p;
usr.bin/cvs/modules.c
152
if (*val == '\0')
usr.bin/cvs/modules.c
165
for (sp = val; *sp != '\0'; sp = dp) {
usr.bin/cvs/modules.c
182
} else if (sp == val) {
usr.bin/cvs/modules.c
57
char *bline, *val, *p, *module, *sp, *dp;
usr.bin/cvs/modules.c
64
p = val = line;
usr.bin/cvs/modules.c
72
module = val;
usr.bin/cvs/modules.c
80
val = p;
usr.bin/cvs/modules.c
84
while (val[0] == '-') {
usr.bin/cvs/modules.c
85
p = val;
usr.bin/cvs/modules.c
94
switch (val[1]) {
usr.bin/cvs/rcsnum.c
220
u_int32_t val;
usr.bin/cvs/rcsnum.c
240
val = (nump->rn_id[nump->rn_len] * 10) + (*sp - '0');
usr.bin/cvs/rcsnum.c
241
if (val > RCSNUM_MAXNUM)
usr.bin/cvs/rcsnum.c
244
nump->rn_id[nump->rn_len] = val;
usr.bin/cvs/trigger.c
102
val = NULL;
usr.bin/cvs/trigger.c
106
val = "%";
usr.bin/cvs/trigger.c
111
val = valbuf;
usr.bin/cvs/trigger.c
116
val = fi->tag_op;
usr.bin/cvs/trigger.c
119
val = current_cvsroot->cr_dir;
usr.bin/cvs/trigger.c
122
val = repo;
usr.bin/cvs/trigger.c
128
val = fi->file_path;
usr.bin/cvs/trigger.c
132
val = fi->tag_new;
usr.bin/cvs/trigger.c
139
val = "NONE";
usr.bin/cvs/trigger.c
141
val = fi->crevstr;
usr.bin/cvs/trigger.c
148
val = "NONE";
usr.bin/cvs/trigger.c
150
val = fi->nrevstr;
usr.bin/cvs/trigger.c
157
if (val != NULL)
usr.bin/cvs/trigger.c
158
buf_puts(buf, val);
usr.bin/cvs/trigger.c
186
const char *val;
usr.bin/cvs/trigger.c
189
if ((val = cvs_var_get(++var)) == NULL) {
usr.bin/cvs/trigger.c
193
buf_puts(buf, val);
usr.bin/cvs/trigger.c
47
const char *val;
usr.bin/dc/bcode.c
844
struct value *val;
usr.bin/dc/bcode.c
848
val = pop();
usr.bin/dc/bcode.c
849
if (val == NULL) {
usr.bin/dc/bcode.c
852
stack_set_tos(&bmachine.reg[idx], val);
usr.bin/diff/diff.c
356
print_status(int val, char *path1, char *path2, char *entry)
usr.bin/diff/diff.c
358
switch (val) {
usr.bin/dig/lib/dns/rcode.c
197
unsigned int val;
usr.bin/dig/lib/dns/rcode.c
205
val = strtoul(buf, &endp, 10);
usr.bin/dig/lib/dns/rcode.c
206
if (*endp == '\0' && val <= 0xffff) {
usr.bin/dig/lib/dns/rcode.c
207
*classp = (dns_rdataclass_t)val;
usr.bin/dig/lib/dns/rdata.c
82
int val;
usr.bin/dig/lib/dns/rdata.c
860
if ((dns_rdatatype_attributes(p->val) &
usr.bin/dig/lib/dns/rdata.c
863
*typep = p->val;
usr.bin/dig/lib/dns/rdata.c
868
int val;
usr.bin/dig/lib/dns/rdata.c
870
val = strtonum(lookup + 4, 0, UINT16_MAX, &errstr);
usr.bin/dig/lib/dns/rdata.c
872
*typep = val;
usr.bin/dig/lib/dns/rdataset.c
249
uint32_t val;
usr.bin/dig/lib/dns/rdataset.c
275
val = rdataset->count;
usr.bin/dig/lib/dns/rdataset.c
276
if (val == UINT32_MAX)
usr.bin/dig/lib/dns/rdataset.c
277
val = arc4random();
usr.bin/dig/lib/dns/rdataset.c
278
j = val % count;
usr.bin/dig/lib/isc/base32.c
119
int val[8];
usr.bin/dig/lib/isc/base32.c
178
if ((ctx->val[1]&0x03) != 0)
usr.bin/dig/lib/isc/base32.c
185
if ((ctx->val[3]&0x0f) != 0)
usr.bin/dig/lib/isc/base32.c
190
if ((ctx->val[4]&0x01) != 0)
usr.bin/dig/lib/isc/base32.c
197
if ((ctx->val[6]&0x07) != 0)
usr.bin/dig/lib/isc/base32.c
206
ctx->val[ctx->digits++] = (last == 32) ? 0 : last;
usr.bin/dig/lib/isc/base32.c
216
buf[0] = (ctx->val[0]<<3)|(ctx->val[1]>>2);
usr.bin/dig/lib/isc/base32.c
217
buf[1] = (ctx->val[1]<<6)|(ctx->val[2]<<1)|(ctx->val[3]>>4);
usr.bin/dig/lib/isc/base32.c
218
buf[2] = (ctx->val[3]<<4)|(ctx->val[4]>>1);
usr.bin/dig/lib/isc/base32.c
219
buf[3] = (ctx->val[4]<<7)|(ctx->val[5]<<2)|(ctx->val[6]>>3);
usr.bin/dig/lib/isc/base32.c
220
buf[4] = (ctx->val[6]<<5)|(ctx->val[7]);
usr.bin/dig/lib/isc/base64.c
115
ctx->val[ctx->digits++] = (int)(s - base64);
usr.bin/dig/lib/isc/base64.c
119
if (ctx->val[0] == 64 || ctx->val[1] == 64)
usr.bin/dig/lib/isc/base64.c
121
if (ctx->val[2] == 64 && ctx->val[3] != 64)
usr.bin/dig/lib/isc/base64.c
126
if (ctx->val[2] == 64 && (ctx->val[1] & 0xf) != 0)
usr.bin/dig/lib/isc/base64.c
132
if (ctx->val[3] == 64 && (ctx->val[2] & 0x3) != 0)
usr.bin/dig/lib/isc/base64.c
134
n = (ctx->val[2] == 64) ? 1 :
usr.bin/dig/lib/isc/base64.c
135
(ctx->val[3] == 64) ? 2 : 3;
usr.bin/dig/lib/isc/base64.c
138
if (ctx->val[2] == 64)
usr.bin/dig/lib/isc/base64.c
139
ctx->val[2] = 0;
usr.bin/dig/lib/isc/base64.c
140
if (ctx->val[3] == 64)
usr.bin/dig/lib/isc/base64.c
141
ctx->val[3] = 0;
usr.bin/dig/lib/isc/base64.c
143
buf[0] = (ctx->val[0]<<2)|(ctx->val[1]>>4);
usr.bin/dig/lib/isc/base64.c
144
buf[1] = (ctx->val[1]<<4)|(ctx->val[2]>>2);
usr.bin/dig/lib/isc/base64.c
145
buf[2] = (ctx->val[2]<<6)|(ctx->val[3]);
usr.bin/dig/lib/isc/base64.c
95
int val[4];
usr.bin/dig/lib/isc/buffer.c
199
isc__buffer_putuint8(isc_buffer_t *b, uint8_t val) {
usr.bin/dig/lib/isc/buffer.c
202
ISC__BUFFER_PUTUINT8(b, val);
usr.bin/dig/lib/isc/buffer.c
226
isc__buffer_putuint16(isc_buffer_t *b, uint16_t val) {
usr.bin/dig/lib/isc/buffer.c
229
ISC__BUFFER_PUTUINT16(b, val);
usr.bin/dig/lib/isc/buffer.c
255
isc__buffer_putuint32(isc_buffer_t *b, uint32_t val) {
usr.bin/dig/lib/isc/buffer.c
258
ISC__BUFFER_PUTUINT32(b, val);
usr.bin/dig/lib/isc/buffer.c
262
isc__buffer_putuint48(isc_buffer_t *b, uint64_t val) {
usr.bin/dig/lib/isc/buffer.c
268
valhi = (uint16_t)(val >> 32);
usr.bin/dig/lib/isc/buffer.c
269
vallo = (uint32_t)(val & 0xFFFFFFFF);
usr.bin/dig/lib/isc/hex.c
73
int val[2];
usr.bin/dig/lib/isc/hex.c
90
ctx->val[ctx->digits++] = (int)(s - hex);
usr.bin/dig/lib/isc/hex.c
94
num = (ctx->val[0] << 4) + (ctx->val[1]);
usr.bin/dig/lib/isc/include/isc/buffer.h
401
isc__buffer_putuint8(isc_buffer_t *b, uint8_t val);
usr.bin/dig/lib/isc/include/isc/buffer.h
436
isc__buffer_putuint16(isc_buffer_t *b, uint16_t val);
usr.bin/dig/lib/isc/include/isc/buffer.h
472
isc__buffer_putuint32(isc_buffer_t *b, uint32_t val);
usr.bin/dig/lib/isc/include/isc/buffer.h
487
isc__buffer_putuint48(isc_buffer_t *b, uint64_t val);
usr.bin/dig/lib/isccfg/parser.c
796
isc_symvalue_t val;
usr.bin/dig/lib/isccfg/parser.c
805
result = isc_symtab_lookup(map->symtab, name, MAP_SYM, &val);
usr.bin/dig/lib/isccfg/parser.c
808
*obj = val.as_pointer;
usr.bin/doas/env.c
170
const char *val;
usr.bin/doas/env.c
202
val = eq + 1;
usr.bin/doas/env.c
203
if (*val == '$') {
usr.bin/doas/env.c
204
if (strcmp(val + 1, "PATH") == 0)
usr.bin/doas/env.c
205
val = formerpath;
usr.bin/doas/env.c
207
val = getenv(val + 1);
usr.bin/doas/env.c
211
val = formerpath;
usr.bin/doas/env.c
213
val = getenv(name);
usr.bin/doas/env.c
216
if (val) {
usr.bin/doas/env.c
217
node = createnode(name, val);
usr.bin/find/function.c
852
static short val;
usr.bin/find/function.c
892
val = sb.f_flags;
usr.bin/find/function.c
897
return (val & plan->mt_data);
usr.bin/ftp/cmds.c
746
int val;
usr.bin/ftp/cmds.c
748
val = strtonum(argv[1], 0, INT_MAX, &errstr);
usr.bin/ftp/cmds.c
755
debug = val;
usr.bin/ftp/cookie.c
144
ck->val = strdup(param);
usr.bin/ftp/cookie.c
145
if (ck->val == NULL)
usr.bin/ftp/cookie.c
157
free(ck->val);
usr.bin/ftp/cookie.c
195
len += strlen(ck->key) + strlen(ck->val) +
usr.bin/ftp/cookie.c
213
(ck == TAILQ_FIRST(&tempjar))? "" : ";", ck->key, ck->val);
usr.bin/ftp/cookie.c
46
char *val;
usr.bin/getconf/getconf.c
407
long val;
usr.bin/getconf/getconf.c
504
if ((val = sysconf(cp->value)) == -1) {
usr.bin/getconf/getconf.c
510
printf("%ld\n", val);
usr.bin/getconf/getconf.c
520
if ((val = pathconf(argv[1], cp->value)) == -1) {
usr.bin/getconf/getconf.c
526
printf("%ld\n", val);
usr.bin/indent/lexi.c
568
addkey(char *key, int val)
usr.bin/indent/lexi.c
602
p->rwcode = val;
usr.bin/infocmp/infocmp.c
343
dump_boolean(int val)
usr.bin/infocmp/infocmp.c
346
switch (val) {
usr.bin/infocmp/infocmp.c
361
dump_numeric(int val, char *buf)
usr.bin/infocmp/infocmp.c
364
switch (val) {
usr.bin/infocmp/infocmp.c
372
_nc_SPRINTF(buf, _nc_SLIMIT(MAX_STRING) "%d", val);
usr.bin/infocmp/infocmp.c
378
dump_string(char *val, char *buf)
usr.bin/infocmp/infocmp.c
381
if (val == ABSENT_STRING)
usr.bin/infocmp/infocmp.c
383
else if (val == CANCELLED_STRING)
usr.bin/infocmp/infocmp.c
387
"'%.*s'", MAX_STRING - 3, TIC_EXPAND(val));
usr.bin/kdump/kdump.c
507
long long val;
usr.bin/kdump/kdump.c
510
val = ((long long)arg2 << 32) | ((long long)arg1 & 0xffffffff);
usr.bin/kdump/kdump.c
512
val = ((long long)arg1 << 32) | ((long long)arg2 & 0xffffffff);
usr.bin/kdump/kdump.c
516
(void)printf("%#llx", val);
usr.bin/kdump/kdump.c
518
(void)printf("%lld", val);
usr.bin/kstat/kstat.c
460
printf("%llu", fr.val);
usr.bin/kstat/kstat.c
56
uint64_t val;
usr.bin/kstat/kstat.c
62
fmt_thing(struct fmt_result *fr, uint64_t val, uint64_t chunk)
usr.bin/kstat/kstat.c
67
while (val > chunk) {
usr.bin/kstat/kstat.c
68
rem = val % chunk;
usr.bin/kstat/kstat.c
69
val /= chunk;
usr.bin/kstat/kstat.c
73
fr->val = val;
usr.bin/less/lesskey.c
560
fputint(FILE *fd, unsigned int val)
usr.bin/less/lesskey.c
564
if (val >= KRADIX*KRADIX) {
usr.bin/less/lesskey.c
566
val, KRADIX*KRADIX);
usr.bin/less/lesskey.c
569
c = val % KRADIX;
usr.bin/less/lesskey.c
571
c = val / KRADIX;
usr.bin/less/option.c
490
flip_triple(int val, int lc)
usr.bin/less/option.c
493
return ((val == OPT_ON) ? OPT_OFF : OPT_ON);
usr.bin/less/option.c
495
return ((val == OPT_ONPLUS) ? OPT_OFF : OPT_ONPLUS);
usr.bin/less/os.c
66
muldiv(off_t val, off_t num, off_t den)
usr.bin/less/os.c
68
double v = (((double)val) * num) / den;
usr.bin/lex/buf.c
176
buf_m4_define(struct Buf * buf, const char *def, const char *val)
usr.bin/lex/buf.c
182
val = val ? val : "";
usr.bin/lex/buf.c
183
strsz = strlen(fmt) + strlen(def) + strlen(val) + 2;
usr.bin/lex/buf.c
188
snprintf(str, strsz, fmt, def, val);
usr.bin/lex/flexdef.h
1075
extern struct Buf *buf_m4_define PROTO((struct Buf *buf, const char* def, const char* val));
usr.bin/lex/flexdef.h
910
extern void out_m4_define (const char* def, const char* val);
usr.bin/lex/misc.c
543
int val = 0;
usr.bin/lex/misc.c
545
(void) sscanf(array, "%d", &val);
usr.bin/lex/misc.c
547
return val;
usr.bin/lex/misc.c
718
out_m4_define(const char *def, const char *val)
usr.bin/lex/misc.c
721
fprintf(stdout, fmt, def, val ? val : "");
usr.bin/lex/scanopt.c
139
#define SAFE_ASSIGN(ptr,val) \
usr.bin/lex/scanopt.c
142
*(ptr) = val; \
usr.bin/make/cond.c
668
char *val;
usr.bin/make/cond.c
677
val = Var_Parse(&condExpr[arglen - 1], NULL,
usr.bin/make/cond.c
679
if (val == var_Error)
usr.bin/make/cond.c
685
for (p = val; ISSPACE(*p); p++)
usr.bin/make/cond.c
690
free(val);
usr.bin/make/stats.c
52
static float average_runs(unsigned long val);
usr.bin/make/stats.c
58
average_runs(unsigned long val)
usr.bin/make/stats.c
60
return (float)val / STAT_INVOCATIONS;
usr.bin/make/var.c
1002
val = get_expanded_value(name.s, name.e, idx, k, ext, ctxt, err,
usr.bin/make/var.c
1005
val = VarModifiers_Apply(val, &name, ctxt, err, freePtr,
usr.bin/make/var.c
1008
if (val == NULL) {
usr.bin/make/var.c
1009
val = err ? var_Error : varNoError;
usr.bin/make/var.c
1025
val = Str_dupi(str, tstr);
usr.bin/make/var.c
1033
return val;
usr.bin/make/var.c
1049
char *val; /* Value to substitute for a variable */
usr.bin/make/var.c
1066
val = Var_Parse(str, ctxt, undefErr, &length, &doFree);
usr.bin/make/var.c
1071
if (val == var_Error || val == varNoError) {
usr.bin/make/var.c
1100
Buf_AddString(&buf, val);
usr.bin/make/var.c
1102
free(val);
usr.bin/make/var.c
1141
char *val = VarModifiers_Apply(NULL, NULL, NULL, false,
usr.bin/make/var.c
1144
free(val);
usr.bin/make/var.c
1214
Buf_Destroy(&(l->me->val));
usr.bin/make/var.c
1223
const char *val) /* Its value */
usr.bin/make/var.c
1227
var_set_value(l->me, val);
usr.bin/make/var.c
1286
newval = VarModifiers_Apply((char *)val,
usr.bin/make/var.c
1296
Buf_AddString(buf, val);
usr.bin/make/var.c
181
BUFFER val; /* the variable value */
usr.bin/make/var.c
358
var_set_initial_value(Var *v, const char *val)
usr.bin/make/var.c
362
len = strlen(val);
usr.bin/make/var.c
363
Buf_Init(&(v->val), len+1);
usr.bin/make/var.c
364
Buf_AddChars(&(v->val), len, val);
usr.bin/make/var.c
372
var_set_value(Var *v, const char *val)
usr.bin/make/var.c
375
Buf_Reset(&(v->val));
usr.bin/make/var.c
376
Buf_AddString(&(v->val), val);
usr.bin/make/var.c
378
var_set_initial_value(v, val);
usr.bin/make/var.c
390
return Buf_Retrieve(&(v->val));
usr.bin/make/var.c
397
var_append_value(Var *v, const char *val)
usr.bin/make/var.c
400
Buf_AddSpace(&(v->val));
usr.bin/make/var.c
401
Buf_AddString(&(v->val), val);
usr.bin/make/var.c
403
var_set_initial_value(v, val);
usr.bin/make/var.c
415
Buf_Destroy(&(v->val));
usr.bin/make/var.c
589
var_set_append(const char *name, const char *ename, const char *val, int ctxt,
usr.bin/make/var.c
610
(append ? var_append_value : var_set_value)(v, val);
usr.bin/make/var.c
617
esetenv(v->name, val);
usr.bin/make/var.c
623
(append ? var_append_value : var_set_value)(v, val);
usr.bin/make/var.c
631
Var_Seti_with_ctxt(const char *name, const char *ename, const char *val,
usr.bin/make/var.c
634
var_set_append(name, ename, val, ctxt, false);
usr.bin/make/var.c
638
Var_Appendi_with_ctxt(const char *name, const char *ename, const char *val,
usr.bin/make/var.c
641
var_set_append(name, ename, val, ctxt, true);
usr.bin/make/var.c
647
char *arg = Buf_Retrieve(&(v->val));
usr.bin/make/var.c
896
char *val;
usr.bin/make/var.c
917
val = var_get_value(v);
usr.bin/make/var.c
918
if (strchr(val, '$') != NULL) {
usr.bin/make/var.c
920
val = Var_Subst(val, ctxt, err);
usr.bin/make/var.c
926
val = ctxt->locals[idx];
usr.bin/make/var.c
928
val = NULL;
usr.bin/make/var.c
929
if (val == NULL)
usr.bin/make/var.c
933
val = Var_GetTail(val);
usr.bin/make/var.c
936
val = Var_GetHead(val);
usr.bin/make/var.c
940
return val;
usr.bin/make/var.c
983
char *val;
usr.bin/mandoc/cgi.c
185
set_query_attr(char **attr, char **val)
usr.bin/mandoc/cgi.c
189
if (**val == '\0') {
usr.bin/mandoc/cgi.c
191
free(*val);
usr.bin/mandoc/cgi.c
193
*attr = *val;
usr.bin/mandoc/cgi.c
194
*val = NULL;
usr.bin/mandoc/cgi.c
204
char *key, *val;
usr.bin/mandoc/cgi.c
214
key = val = NULL;
usr.bin/mandoc/cgi.c
228
val = mandoc_strndup(qs, valsz);
usr.bin/mandoc/cgi.c
233
if ( ! (http_decode(key) && http_decode(val)))
usr.bin/mandoc/cgi.c
239
set_query_attr(&req->q.query, &val);
usr.bin/mandoc/cgi.c
242
req->q.equal = !strcmp(val, "0");
usr.bin/mandoc/cgi.c
246
if ( ! strncmp(val, "OpenBSD ", 8)) {
usr.bin/mandoc/cgi.c
247
val[7] = '-';
usr.bin/mandoc/cgi.c
248
if ('C' == val[8])
usr.bin/mandoc/cgi.c
249
val[8] = 'c';
usr.bin/mandoc/cgi.c
252
set_query_attr(&req->q.manpath, &val);
usr.bin/mandoc/cgi.c
260
if ( ! strcmp(val, "0"))
usr.bin/mandoc/cgi.c
261
*val = '\0';
usr.bin/mandoc/cgi.c
262
set_query_attr(&req->q.sec, &val);
usr.bin/mandoc/cgi.c
266
if ( ! strcmp(val, "default"))
usr.bin/mandoc/cgi.c
267
*val = '\0';
usr.bin/mandoc/cgi.c
268
set_query_attr(&req->q.arch, &val);
usr.bin/mandoc/cgi.c
279
free(val);
usr.bin/mandoc/cgi.c
280
val = NULL;
usr.bin/mandoc/eqn.c
1128
free(p->defs[i].val);
usr.bin/mandoc/eqn.c
290
char *val;
usr.bin/mandoc/eqn.c
451
memcpy(ep->start, def->val, def->valsz);
usr.bin/mandoc/eqn.c
605
free(def->val);
usr.bin/mandoc/eqn.c
606
def->key = def->val = NULL;
usr.bin/mandoc/eqn.c
636
ep->defs[i].key = ep->defs[i].val = NULL;
usr.bin/mandoc/eqn.c
649
free(def->val);
usr.bin/mandoc/eqn.c
650
def->key = def->val = NULL;
usr.bin/mandoc/eqn.c
654
free(def->val);
usr.bin/mandoc/eqn.c
655
def->val = mandoc_strndup(ep->start, ep->toksz);
usr.bin/mandoc/mansearch.c
690
char *key, *val;
usr.bin/mandoc/mansearch.c
732
mandoc_asprintf(&val, "[[:<:]]%s[[:>:]]", argv[*argi]);
usr.bin/mandoc/mansearch.c
734
} else if ((val = strpbrk(argv[*argi], "=~")) == NULL) {
usr.bin/mandoc/mansearch.c
737
val = argv[*argi];
usr.bin/mandoc/mansearch.c
740
if (val == argv[*argi])
usr.bin/mandoc/mansearch.c
742
if (*val == '=') {
usr.bin/mandoc/mansearch.c
744
e->match.str = val + 1;
usr.bin/mandoc/mansearch.c
747
*val++ = '\0';
usr.bin/mandoc/mansearch.c
756
irc = regcomp(e->match.re, val,
usr.bin/mandoc/mansearch.c
760
warnx("regcomp /%s/: %s", val, errbuf);
usr.bin/mandoc/mansearch.c
763
free(val);
usr.bin/mandoc/roff.c
3005
roff_setreg(struct roff *r, const char *name, int val, char sign)
usr.bin/mandoc/roff.c
3007
roff_setregn(r, name, strlen(name), val, sign, INT_MIN);
usr.bin/mandoc/roff.c
3012
int val, char sign, int step)
usr.bin/mandoc/roff.c
3028
reg->val = 0;
usr.bin/mandoc/roff.c
3035
reg->val += val;
usr.bin/mandoc/roff.c
3037
reg->val -= val;
usr.bin/mandoc/roff.c
3039
reg->val = val;
usr.bin/mandoc/roff.c
3086
int val;
usr.bin/mandoc/roff.c
3089
val = roff_getregro(r, name + 1);
usr.bin/mandoc/roff.c
3090
if (-1 != val)
usr.bin/mandoc/roff.c
3091
return val;
usr.bin/mandoc/roff.c
3099
reg->val += reg->step;
usr.bin/mandoc/roff.c
3102
reg->val -= reg->step;
usr.bin/mandoc/roff.c
3107
return reg->val;
usr.bin/mandoc/roff.c
3119
int val;
usr.bin/mandoc/roff.c
3122
val = roff_getregro(r, name + 1);
usr.bin/mandoc/roff.c
3123
if (-1 != val)
usr.bin/mandoc/roff.c
3151
char *key, *val, *step;
usr.bin/mandoc/roff.c
3156
key = val = buf->buf + pos;
usr.bin/mandoc/roff.c
3160
keysz = roff_getname(&val, ln, pos);
usr.bin/mandoc/roff.c
3164
sign = *val;
usr.bin/mandoc/roff.c
3166
val++;
usr.bin/mandoc/roff.c
3169
if (roff_evalnum(ln, val, &len, &iv, 'u', 0) == 0)
usr.bin/mandoc/roff.c
3172
step = val + len;
usr.bin/mandoc/roff.c
4133
n->val.p = NULL;
usr.bin/mandoc/roff.c
4134
n->val.sz = 0;
usr.bin/mandoc/roff.c
4138
free(n->val.p);
usr.bin/mandoc/roff.c
4139
n->val.p = NULL;
usr.bin/mandoc/roff.c
4140
n->val.sz = 0;
usr.bin/mandoc/roff.c
4152
if (NULL == n->val.p) {
usr.bin/mandoc/roff.c
4153
n->val.p = mandoc_malloc(newch);
usr.bin/mandoc/roff.c
4154
*n->val.p = '\0';
usr.bin/mandoc/roff.c
4157
oldch = n->val.sz;
usr.bin/mandoc/roff.c
4158
n->val.p = mandoc_realloc(n->val.p, oldch + newch);
usr.bin/mandoc/roff.c
4162
c = n->val.p + (int)oldch;
usr.bin/mandoc/roff.c
4181
n->val.sz = (int)(c - n->val.p);
usr.bin/mandoc/roff.c
4195
n->key.p[len] != '\0' || n->val.p == NULL)
usr.bin/mandoc/roff.c
4199
return n->val.p;
usr.bin/mandoc/roff.c
4207
n->key.p[len] != '\0' || n->val.p == NULL)
usr.bin/mandoc/roff.c
4211
return n->val.p;
usr.bin/mandoc/roff.c
4285
free(n->val.p);
usr.bin/mandoc/roff.c
4350
ssz + cp->val.sz + 1);
usr.bin/mandoc/roff.c
4351
memcpy(res + ssz, cp->val.p, cp->val.sz);
usr.bin/mandoc/roff.c
4352
ssz += cp->val.sz;
usr.bin/mandoc/roff.c
68
struct roffstr val;
usr.bin/mandoc/roff.c
77
int val;
usr.bin/nc/netcat.c
1626
process_tos_opt(char *s, int *val)
usr.bin/nc/netcat.c
1631
int val;
usr.bin/nc/netcat.c
1666
*val = t->val;
usr.bin/openssl/apps.c
1978
long long val;
usr.bin/openssl/apps.c
2066
val = strtonum(argv[i], 0, INT_MAX, &errstr);
usr.bin/openssl/apps.c
2072
*opt->opt.value = (int)val;
usr.bin/openssl/apps.c
2076
val = strtonum(argv[i], 0, LONG_MAX, &errstr);
usr.bin/openssl/apps.c
2082
*opt->opt.lvalue = (long)val;
usr.bin/openssl/apps.c
2086
val = strtonum(argv[i], 0, LLONG_MAX, &errstr);
usr.bin/openssl/apps.c
2092
*opt->opt.tvalue = val;
usr.bin/openssl/apps.c
934
CONF_VALUE *val;
usr.bin/openssl/apps.c
941
val = sk_CONF_VALUE_value(vals, i);
usr.bin/openssl/apps.c
942
if (!set_table_opts(flags, val->name, in_tbl))
usr.bin/openssl/certhash.c
253
long long val;
usr.bin/openssl/certhash.c
267
val = strtoll(l, &ep, 16);
usr.bin/openssl/certhash.c
270
if (errno == ERANGE && (val == LLONG_MAX || val == LLONG_MIN))
usr.bin/openssl/certhash.c
272
if (val < 0 || val > ULONG_MAX)
usr.bin/openssl/certhash.c
274
hi->hash = (unsigned long)val;
usr.bin/openssl/certhash.c
281
val = strtonum(p, 0, 0xffffffff, &errstr);
usr.bin/openssl/certhash.c
285
hi->index = (unsigned int)val;
usr.bin/pctr/pctr.c
353
pctr_write(int ctr, u_int32_t val)
usr.bin/pctr/pctr.c
360
if (ioctl(fd, PCIOCS0 + ctr, &val) == -1) {
usr.bin/pctr/pctr.c
431
u_int32_t val = func;
usr.bin/pctr/pctr.c
440
val |= P5CTR_C;
usr.bin/pctr/pctr.c
442
val |= P5CTR_K;
usr.bin/pctr/pctr.c
444
val |= P5CTR_U;
usr.bin/pctr/pctr.c
446
val |= P5CTR_K | P5CTR_U;
usr.bin/pctr/pctr.c
459
val |= PCTR_UM_A;
usr.bin/pctr/pctr.c
462
val |= PCTR_UM_M;
usr.bin/pctr/pctr.c
464
val |= PCTR_UM_E;
usr.bin/pctr/pctr.c
466
val |= PCTR_UM_S;
usr.bin/pctr/pctr.c
468
val |= PCTR_UM_I;
usr.bin/pctr/pctr.c
470
val |= PCTR_UM_MESI;
usr.bin/pctr/pctr.c
473
val |= PCTR_E;
usr.bin/pctr/pctr.c
485
val |= PCTR_E;
usr.bin/pctr/pctr.c
487
val |= PCTR_I;
usr.bin/pctr/pctr.c
489
val |= PCTR_K;
usr.bin/pctr/pctr.c
491
val |= PCTR_U;
usr.bin/pctr/pctr.c
493
val |= PCTR_K | PCTR_U;
usr.bin/pctr/pctr.c
494
val |= masku << PCTR_UM_SHIFT;
usr.bin/pctr/pctr.c
495
val |= thold << PCTR_CM_SHIFT;
usr.bin/pctr/pctr.c
497
val |= PCTR_EN;
usr.bin/pctr/pctr.c
501
return (pctr_write(ctr, val));
usr.bin/pkgconf/cli/getopt_long.c
255
long_options[i].val != long_options[match].val)
usr.bin/pkgconf/cli/getopt_long.c
290
pkg_optopt = (int)long_options[match].val;
usr.bin/pkgconf/cli/getopt_long.c
330
pkg_optopt = (int)long_options[match].val;
usr.bin/pkgconf/cli/getopt_long.c
357
*long_options[match].flag |= long_options[match].val;
usr.bin/pkgconf/cli/getopt_long.c
359
*long_options[match].flag = long_options[match].val;
usr.bin/pkgconf/cli/getopt_long.c
363
return ((int)long_options[match].val);
usr.bin/pkgconf/cli/getopt_long.h
57
uint64_t val;
usr.bin/printf/printf.c
426
long val;
usr.bin/printf/printf.c
436
val = strtol(*gargv, &ep, 0);
usr.bin/printf/printf.c
438
return val;
usr.bin/printf/printf.c
444
unsigned long val;
usr.bin/printf/printf.c
454
val = strtoul(*gargv, &ep, 0);
usr.bin/printf/printf.c
456
return val;
usr.bin/printf/printf.c
462
double val;
usr.bin/printf/printf.c
472
val = strtod(*gargv, &ep);
usr.bin/printf/printf.c
474
return val;
usr.bin/radioctl/radioctl.c
386
int val;
usr.bin/radioctl/radioctl.c
392
val = (int)(1000 * atof(str));
usr.bin/radioctl/radioctl.c
394
val = (int)strtol(str, (char **)NULL, 10);
usr.bin/radioctl/radioctl.c
396
return val;
usr.bin/radioctl/radioctl.c
550
show_int_val(int val, const char *nick, char *append, int silent)
usr.bin/radioctl/radioctl.c
553
printf("%u%s\n", val, append);
usr.bin/radioctl/radioctl.c
557
show_float_val(float val, const char *nick, char *append, int silent)
usr.bin/radioctl/radioctl.c
560
printf("%.2f%s\n", val, append);
usr.bin/radioctl/radioctl.c
564
show_char_val(const char *val, const char *nick, int silent)
usr.bin/radioctl/radioctl.c
567
printf("%s\n", val);
usr.bin/rcs/rcsnum.c
243
u_int32_t val;
usr.bin/rcs/rcsnum.c
270
val = (nump->rn_id[nump->rn_len] * 10) + (*sp - '0');
usr.bin/rcs/rcsnum.c
271
if (val > RCSNUM_MAXNUM)
usr.bin/rcs/rcsnum.c
274
nump->rn_id[nump->rn_len] = val;
usr.bin/rdistd/filesys.c
399
int64_t val;
usr.bin/rdistd/filesys.c
421
val = -1;
usr.bin/rdistd/filesys.c
423
val = (statfsbuf.f_bavail * (statfsbuf.f_bsize / 512)) / 2;
usr.bin/rdistd/filesys.c
424
*freespace = val;
usr.bin/rdistd/filesys.c
426
val = -1;
usr.bin/rdistd/filesys.c
428
val = statfsbuf.f_favail;
usr.bin/rdistd/filesys.c
429
*freefiles = val;
usr.bin/rpcgen/rpc_clntout.c
62
def = (definition *) l->val;
usr.bin/rpcgen/rpc_hout.c
498
def = (definition *) l->val;
usr.bin/rpcgen/rpc_main.c
505
print_funcdef(l->val);
usr.bin/rpcgen/rpc_sample.c
237
def = l->val;
usr.bin/rpcgen/rpc_scan.c
313
findstrconst(str, val)
usr.bin/rpcgen/rpc_scan.c
315
char **val;
usr.bin/rpcgen/rpc_scan.c
329
*val = malloc(size + 1);
usr.bin/rpcgen/rpc_scan.c
330
if (val == NULL)
usr.bin/rpcgen/rpc_scan.c
332
(void) strncpy(*val, *str, size);
usr.bin/rpcgen/rpc_scan.c
333
(*val)[size] = 0;
usr.bin/rpcgen/rpc_scan.c
338
findchrconst(str, val)
usr.bin/rpcgen/rpc_scan.c
340
char **val;
usr.bin/rpcgen/rpc_scan.c
357
*val = malloc(size + 1);
usr.bin/rpcgen/rpc_scan.c
358
if (val == NULL)
usr.bin/rpcgen/rpc_scan.c
360
(void) strncpy(*val, *str, size);
usr.bin/rpcgen/rpc_scan.c
361
(*val)[size] = 0;
usr.bin/rpcgen/rpc_scan.c
366
findconst(str, val)
usr.bin/rpcgen/rpc_scan.c
368
char **val;
usr.bin/rpcgen/rpc_scan.c
385
*val = malloc(size + 1);
usr.bin/rpcgen/rpc_scan.c
386
if (val == NULL)
usr.bin/rpcgen/rpc_scan.c
388
(void) strncpy(*val, *str, size);
usr.bin/rpcgen/rpc_scan.c
389
(*val)[size] = 0;
usr.bin/rpcgen/rpc_svcout.c
175
def = (definition *) l->val;
usr.bin/rpcgen/rpc_svcout.c
210
def = (definition *) l->val;
usr.bin/rpcgen/rpc_svcout.c
267
def = (definition *) l->val;
usr.bin/rpcgen/rpc_svcout.c
274
def = (definition *) l->val;
usr.bin/rpcgen/rpc_svcout.c
572
def = (definition *) l->val;
usr.bin/rpcgen/rpc_svcout.c
766
def = (definition *) l->val;
usr.bin/rpcgen/rpc_svcout.c
931
def = (definition *) l->val;
usr.bin/rpcgen/rpc_tblout.c
70
def = (definition *) l->val;
usr.bin/rpcgen/rpc_util.c
100
if ((*cmp) (lst->val, val)) {
usr.bin/rpcgen/rpc_util.c
101
return (lst->val);
usr.bin/rpcgen/rpc_util.c
111
storeval(lstp, val)
usr.bin/rpcgen/rpc_util.c
113
definition *val;
usr.bin/rpcgen/rpc_util.c
125
lst->val = val;
usr.bin/rpcgen/rpc_util.c
93
findval(lst, val, cmp)
usr.bin/rpcgen/rpc_util.c
95
char *val;
usr.bin/rpcgen/rpc_util.h
42
definition *val;
usr.bin/rsync/io.c
390
io_write_ulong(struct sess *sess, int fd, uint64_t val)
usr.bin/rsync/io.c
393
int64_t sval = (int64_t)val;
usr.bin/rsync/io.c
398
if (!io_write_int(sess, fd, (int32_t)val)) {
usr.bin/rsync/io.c
407
nv = htole64(val);
usr.bin/rsync/io.c
420
io_write_long(struct sess *sess, int fd, int64_t val)
usr.bin/rsync/io.c
422
return io_write_ulong(sess, fd, (uint64_t)val);
usr.bin/rsync/io.c
430
io_write_uint(struct sess *sess, int fd, uint32_t val)
usr.bin/rsync/io.c
434
nv = htole32(val);
usr.bin/rsync/io.c
448
io_write_int(struct sess *sess, int fd, int32_t val)
usr.bin/rsync/io.c
450
return io_write_uint(sess, fd, (uint32_t)val);
usr.bin/rsync/io.c
461
io_buffer_buf(void *buf, size_t *bufpos, size_t buflen, const void *val,
usr.bin/rsync/io.c
466
memcpy(buf + *bufpos, val, valsz);
usr.bin/rsync/io.c
477
size_t *bufpos, size_t buflen, const void *val, size_t valsz)
usr.bin/rsync/io.c
485
io_buffer_buf(buf, bufpos, buflen, val, valsz);
usr.bin/rsync/io.c
494
io_buffer_buf(buf, bufpos, buflen, val, valsz);
usr.bin/rsync/io.c
534
size_t *bufpos, size_t buflen, int32_t val)
usr.bin/rsync/io.c
536
int32_t nv = htole32(val);
usr.bin/rsync/io.c
545
io_buffer_int(void *buf, size_t *bufpos, size_t buflen, int32_t val)
usr.bin/rsync/io.c
547
int32_t nv = htole32(val);
usr.bin/rsync/io.c
557
io_read_long(struct sess *sess, int fd, int64_t *val)
usr.bin/rsync/io.c
565
*val = (int64_t)uoval;
usr.bin/rsync/io.c
566
if (*val < 0) {
usr.bin/rsync/io.c
578
io_read_ulong(struct sess *sess, int fd, uint64_t *val)
usr.bin/rsync/io.c
590
*val = sval;
usr.bin/rsync/io.c
601
*val = le64toh(oval);
usr.bin/rsync/io.c
613
io_read_size(struct sess *sess, int fd, size_t *val)
usr.bin/rsync/io.c
625
*val = oval;
usr.bin/rsync/io.c
634
io_read_uint(struct sess *sess, int fd, uint32_t *val)
usr.bin/rsync/io.c
643
*val = le32toh(oval);
usr.bin/rsync/io.c
648
io_read_int(struct sess *sess, int fd, int32_t *val)
usr.bin/rsync/io.c
650
return io_read_uint(sess, fd, (uint32_t *)val);
usr.bin/rsync/io.c
660
io_unbuffer_buf(const void *buf, size_t *bufpos, size_t bufsz, void *val,
usr.bin/rsync/io.c
665
memcpy(val, buf + *bufpos, valsz);
usr.bin/rsync/io.c
673
io_unbuffer_int(const void *buf, size_t *bufpos, size_t bufsz, int32_t *val)
usr.bin/rsync/io.c
678
*val = le32toh(oval);
usr.bin/rsync/io.c
685
io_unbuffer_size(const void *buf, size_t *bufpos, size_t bufsz, size_t *val)
usr.bin/rsync/io.c
694
*val = oval;
usr.bin/rsync/io.c
703
io_read_byte(struct sess *sess, int fd, uint8_t *val)
usr.bin/rsync/io.c
706
if (!io_read_buf(sess, fd, val, sizeof(uint8_t))) {
usr.bin/rsync/io.c
718
io_write_byte(struct sess *sess, int fd, uint8_t val)
usr.bin/rsync/io.c
721
if (!io_write_buf(sess, fd, &val, sizeof(uint8_t))) {
usr.bin/showmount/showmount.c
234
int bool, val, val2;
usr.bin/showmount/showmount.c
261
val = strcmp(mp->ml_host, tp->ml_host);
usr.bin/showmount/showmount.c
265
if (val == 0) {
usr.bin/showmount/showmount.c
270
val = val2;
usr.bin/showmount/showmount.c
278
val = val2;
usr.bin/showmount/showmount.c
281
if (val == 0) {
usr.bin/showmount/showmount.c
287
if (val < 0) {
usr.bin/skeyinit/skeyinit.c
305
if ((skey.val = malloc(16 + 1)) == NULL)
usr.bin/skeyinit/skeyinit.c
307
btoa8(skey.val, key);
usr.bin/skeyinit/skeyinit.c
311
pp->pw_name, skey_get_algorithm(), n, seed, skey.val);
usr.bin/sndioctl/sndioctl.c
545
unsigned int val;
usr.bin/sndioctl/sndioctl.c
548
if (sscanf(p, "%u%n", &val, &n) != 1) {
usr.bin/sndioctl/sndioctl.c
552
if (val >= 255) {
usr.bin/sndioctl/sndioctl.c
553
fprintf(stderr, "%d: too large\n", val);
usr.bin/sndioctl/sndioctl.c
556
*num = val;
usr.bin/sndioctl/sndioctl.c
565
float val;
usr.bin/sndioctl/sndioctl.c
568
if (sscanf(p, "%g%n", &val, &n) != 1) {
usr.bin/sndioctl/sndioctl.c
572
if (val < 0 || val > 1) {
usr.bin/sndioctl/sndioctl.c
573
fprintf(stderr, "%g: expected number between 0 and 1\n", val);
usr.bin/sndioctl/sndioctl.c
576
*num = val;
usr.bin/sndioctl/sndioctl.c
700
float val;
usr.bin/sndioctl/sndioctl.c
747
if (!parse_modeval(&pos, &mode, &val))
usr.bin/sndioctl/sndioctl.c
753
i->newval = ftoi(val * i->desc.maxval);
usr.bin/sndioctl/sndioctl.c
790
if (!parse_val(&pos, &val))
usr.bin/sndioctl/sndioctl.c
793
val = 1.;
usr.bin/sndioctl/sndioctl.c
801
e->newval = ftoi(val * e->desc.maxval);
usr.bin/sndioctl/sndioctl.c
840
int val;
usr.bin/sndioctl/sndioctl.c
843
val = 0xdeadbeef;
usr.bin/sndioctl/sndioctl.c
849
val = i->newval;
usr.bin/sndioctl/sndioctl.c
852
val = i->curval + i->newval;
usr.bin/sndioctl/sndioctl.c
853
if (val > i->desc.maxval)
usr.bin/sndioctl/sndioctl.c
854
val = i->desc.maxval;
usr.bin/sndioctl/sndioctl.c
857
val = i->curval - i->newval;
usr.bin/sndioctl/sndioctl.c
858
if (val < 0)
usr.bin/sndioctl/sndioctl.c
859
val = 0;
usr.bin/sndioctl/sndioctl.c
862
val = i->curval ? 0 : i->desc.maxval;
usr.bin/sndioctl/sndioctl.c
864
sioctl_setval(hdl, i->ctladdr, val);
usr.bin/sndioctl/sndioctl.c
865
i->curval = val;
usr.bin/sndioctl/sndioctl.c
961
onctl(void *arg, unsigned addr, unsigned val)
usr.bin/sndioctl/sndioctl.c
974
if (i->curval == val) {
usr.bin/sndioctl/sndioctl.c
989
i->curval = val;
usr.bin/sndiod/dev.c
1923
ctl_setval(struct ctl *c, int val)
usr.bin/sndiod/dev.c
1925
if (c->curval == val) {
usr.bin/sndiod/dev.c
1929
if (val < 0 || val > c->maxval) {
usr.bin/sndiod/dev.c
1930
logx(3, "ctl%u: %d: out of range", c->addr, val);
usr.bin/sndiod/dev.c
1937
c->curval = val;
usr.bin/sndiod/dev.c
1943
dev_master(c->u.dev_master.dev, val);
usr.bin/sndiod/dev.c
1946
c->curval = val;
usr.bin/sndiod/dev.c
1949
opt_appvol(c->u.app_level.opt, c->u.app_level.app, val);
usr.bin/sndiod/dev.c
1952
c->curval = val;
usr.bin/sndiod/dev.c
1961
opt_setmode(c->u.opt_mode.opt, c->u.opt_mode.idx, val);
usr.bin/sndiod/dev.c
1963
c->curval = val;
usr.bin/sndiod/dev.c
1966
if (midithru_setport(c->u.midi.midithru, c->u.midi.port, val)) {
usr.bin/sndiod/dev.c
1968
c->curval = val;
usr.bin/sndiod/dev.c
1972
if (midithru_setthru(c->u.midi.midithru, val)) {
usr.bin/sndiod/dev.c
1974
c->curval = val;
usr.bin/sndiod/dev.c
1990
char *str1, int unit1, int maxval, int val)
usr.bin/sndiod/dev.c
2044
c->curval = val;
usr.bin/sndiod/dev.c
2126
ctl_onval(int scope, void *arg0, void *arg1, int val)
usr.bin/sndiod/dev.c
2133
c->curval = val;
usr.bin/sndiod/dev.h
349
int ctl_setval(struct ctl *c, int val);
usr.bin/sndiod/dev_sioctl.c
51
dev_sioctl_ondesc(void *arg, struct sioctl_desc *desc, int val)
usr.bin/sndiod/dev_sioctl.c
75
desc->node1.name, desc->node1.unit, desc->maxval, val);
usr.bin/sndiod/dev_sioctl.c
79
dev_sioctl_onval(void *arg, unsigned int addr, unsigned int val)
usr.bin/sndiod/dev_sioctl.c
85
logx(2, "%s: onctl: addr = %u, val = %u", d->path, addr, val);
usr.bin/sndiod/dev_sioctl.c
93
(ctl_fmt(str, sizeof(str), c), str), val);
usr.bin/sndiod/dev_sioctl.c
96
c->curval = val;
usr.bin/sndiod/file.c
110
val = timo_abstime + delta;
usr.bin/sndiod/file.c
112
diff = (*i)->val - val;
usr.bin/sndiod/file.c
118
o->val = val;
usr.bin/sndiod/file.c
168
diff = timo_queue->val - timo_abstime;
usr.bin/sndiod/file.c
383
timo = ((int)timo_queue->val - (int)timo_abstime) / 1000;
usr.bin/sndiod/file.c
97
unsigned int val;
usr.bin/sndiod/file.h
27
unsigned int val; /* time to wait before the callback */
usr.bin/sndiod/midi.c
662
midithru_setport(struct midithru *t, struct port *c, int val)
usr.bin/sndiod/midi.c
664
if (val) {
usr.bin/sndiod/midi.c
677
midithru_setthru(struct midithru *t, int val)
usr.bin/sndiod/midi.c
681
if (t->thru == val)
usr.bin/sndiod/midi.c
690
if (val)
usr.bin/sndiod/midi.c
697
t->thru = val;
usr.bin/sndiod/opt.c
523
opt_setmode(struct opt *o, int idx, int val)
usr.bin/sndiod/opt.c
532
if (val)
usr.bin/sndiod/opt.c
537
logx(2, "%s: %s -> %d", __func__, opt_modes[idx].name, val);
usr.bin/sndiod/sock.c
1066
f->fd, m->u.ctlsub.desc, m->u.ctlsub.val);
usr.bin/sndiod/sock.c
1092
if (m->u.ctlsub.val) {
usr.bin/sndiod/sock.c
1119
if (!ctl_setval(c, ntohs(m->u.ctlset.val))) {
usr.bin/sndiod/sock.c
1404
f->wmsg.u.ctlset.val = htons(c->curval);
usr.bin/spell/spellprog.c
625
int val = 0;
usr.bin/spell/spellprog.c
639
val = 1;
usr.bin/spell/spellprog.c
646
return (val);
usr.bin/ssh/channels.c
440
int val;
usr.bin/ssh/channels.c
468
(val = fcntl(rfd, F_GETFL)) != -1 && !(val & O_NONBLOCK)) {
usr.bin/ssh/channels.c
469
c->restore_flags[0] = val;
usr.bin/ssh/channels.c
474
(val = fcntl(wfd, F_GETFL)) != -1 && !(val & O_NONBLOCK)) {
usr.bin/ssh/channels.c
475
c->restore_flags[1] = val;
usr.bin/ssh/channels.c
480
(val = fcntl(efd, F_GETFL)) != -1 && !(val & O_NONBLOCK)) {
usr.bin/ssh/channels.c
481
c->restore_flags[2] = val;
usr.bin/ssh/clientloop.c
2687
client_send_env(struct ssh *ssh, int id, const char *name, const char *val)
usr.bin/ssh/clientloop.c
2691
debug("channel %d: setting env %s = \"%s\"", id, name, val);
usr.bin/ssh/clientloop.c
2694
(r = sshpkt_put_cstring(ssh, val)) != 0 ||
usr.bin/ssh/clientloop.c
2706
char *type = NULL, *cmdstring = NULL, *name, *val;
usr.bin/ssh/clientloop.c
2745
if ((val = strchr(name, '=')) == NULL) {
usr.bin/ssh/clientloop.c
2749
*val++ = '\0';
usr.bin/ssh/clientloop.c
2763
client_send_env(ssh, id, name, val);
usr.bin/ssh/clientloop.c
2770
if ((val = strchr(name, '=')) == NULL) {
usr.bin/ssh/clientloop.c
2774
*val++ = '\0';
usr.bin/ssh/clientloop.c
2775
client_send_env(ssh, id, name, val);
usr.bin/ssh/gss-genr.c
232
char *val;
usr.bin/ssh/gss-genr.c
234
xasprintf(&val, "host@%s", host);
usr.bin/ssh/gss-genr.c
235
gssbuf.value = val;
usr.bin/ssh/kex.c
409
const u_char *val, size_t len, const char *want_ver, u_int flag)
usr.bin/ssh/kex.c
411
if (memchr(val, '\0', len) != NULL) {
usr.bin/ssh/kex.c
415
debug_f("%s=<%s>", name, val);
usr.bin/ssh/kex.c
416
if (strcmp(val, want_ver) == 0)
usr.bin/ssh/kex.c
486
u_char *val;
usr.bin/ssh/kex.c
506
if ((r = sshpkt_get_string(ssh, &val, &vlen)) != 0) {
usr.bin/ssh/kex.c
513
val, vlen)) != 0)
usr.bin/ssh/kex.c
517
val, vlen)) != 0)
usr.bin/ssh/kex.c
521
free(val);
usr.bin/ssh/libcrux-mlkem-mldsa.c
186
memcpy(sig, res.val.case_Ok.data, MLDSA44_SIGBYTES);
usr.bin/ssh/libcrux-mlkem-mldsa.c
283
memcpy(sig, res.val.case_Ok.data, MLDSA65_SIGBYTES);
usr.bin/ssh/libcrux-mlkem-mldsa.c
381
memcpy(sig, res.val.case_Ok.data, MLDSA87_SIGBYTES);
usr.bin/ssh/libcrux_internal.h
1024
val;
usr.bin/ssh/libcrux_internal.h
1040
return self.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
13716
val;
usr.bin/ssh/libcrux_internal.h
13817
libcrux_secrets_mem_requests_ct_declassify_6a(const Eurydice_arr_8f *val)
usr.bin/ssh/libcrux_internal.h
13941
val;
usr.bin/ssh/libcrux_internal.h
14038
libcrux_secrets_mem_requests_ct_declassify_b2(const Eurydice_arr_dc1 *val)
usr.bin/ssh/libcrux_internal.h
14635
val;
usr.bin/ssh/libcrux_internal.h
147
val.*m = std::move(v); \
usr.bin/ssh/libcrux_internal.h
15416
libcrux_secrets_mem_requests_ct_declassify_f5(const Eurydice_arr_9d *val)
usr.bin/ssh/libcrux_internal.h
17478
KRML_CLITERAL(core_result_Result_8e){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
1758
val;
usr.bin/ssh/libcrux_internal.h
1774
return self.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
17880
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
17924
.val = { .case_Ok = signature }
usr.bin/ssh/libcrux_internal.h
17932
(KRML_CLITERAL(core_result_Result_48){ .tag = core_result_Err, .val = { .case_Err = e } });
usr.bin/ssh/libcrux_internal.h
18031
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
18090
.val = { .case_Ok = signature }
usr.bin/ssh/libcrux_internal.h
18098
(KRML_CLITERAL(core_result_Result_48){ .tag = core_result_Err, .val = { .case_Err = e } });
usr.bin/ssh/libcrux_internal.h
18316
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
18383
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
18934
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
18978
.val = { .case_Ok = signature }
usr.bin/ssh/libcrux_internal.h
18986
(KRML_CLITERAL(core_result_Result_8c){ .tag = core_result_Err, .val = { .case_Err = e } });
usr.bin/ssh/libcrux_internal.h
19067
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
19126
.val = { .case_Ok = signature }
usr.bin/ssh/libcrux_internal.h
19134
(KRML_CLITERAL(core_result_Result_8c){ .tag = core_result_Err, .val = { .case_Err = e } });
usr.bin/ssh/libcrux_internal.h
19357
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
19424
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
19975
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
20019
.val = { .case_Ok = signature }
usr.bin/ssh/libcrux_internal.h
20027
(KRML_CLITERAL(core_result_Result_8b){ .tag = core_result_Err, .val = { .case_Err = e } });
usr.bin/ssh/libcrux_internal.h
20108
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
20167
.val = { .case_Ok = signature }
usr.bin/ssh/libcrux_internal.h
20175
(KRML_CLITERAL(core_result_Result_8b){ .tag = core_result_Err, .val = { .case_Err = e } });
usr.bin/ssh/libcrux_internal.h
20398
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
20465
libcrux_ml_dsa_pre_hash_DomainSeparationContext dsc = uu____0.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
21113
KRML_CLITERAL(core_result_Result_ec){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
2160
libcrux_secrets_mem_requests_ct_declassify_56(const Eurydice_arr_c7 *val)
usr.bin/ssh/libcrux_internal.h
2408
libcrux_secrets_mem_requests_ct_declassify_69(const Eurydice_arr_65 *val)
usr.bin/ssh/libcrux_internal.h
25710
KRML_CLITERAL(core_result_Result_07){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
2670
libcrux_secrets_mem_requests_ct_declassify_4b(const Eurydice_arr_ec *val)
usr.bin/ssh/libcrux_internal.h
26707
KRML_CLITERAL(core_result_Result_07){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
282
? ((t_res){.tag = core_result_Ok, .val = {.case_Ok = arr_ptr}}) \
usr.bin/ssh/libcrux_internal.h
283
: ((t_res){.tag = core_result_Err, .val = {.case_Err = 0}}))
usr.bin/ssh/libcrux_internal.h
2842
static KRML_MUSTINLINE void libcrux_secrets_mem_requests_ct_classify_45(const uint8_t (*val)[])
usr.bin/ssh/libcrux_internal.h
2993
libcrux_secrets_mem_requests_ct_declassify_45(const uint8_t (*val)[])
usr.bin/ssh/libcrux_internal.h
3119
libcrux_secrets_mem_requests_ct_classify_4b(const Eurydice_arr_ec *val)
usr.bin/ssh/libcrux_internal.h
3598
val;
usr.bin/ssh/libcrux_internal.h
3614
return self.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
3710
static KRML_MUSTINLINE void libcrux_secrets_mem_requests_ct_declassify_5f(const bool *val)
usr.bin/ssh/libcrux_internal.h
4226
KRML_CLITERAL(core_result_Result_8e){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
5911
KRML_CLITERAL(core_result_Result_8e){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
6921
KRML_CLITERAL(core_result_Result_8e){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
727
val;
usr.bin/ssh/libcrux_internal.h
7412
KRML_CLITERAL(core_result_Result_8e){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
743
return self.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
7690
KRML_CLITERAL(core_result_Result_8e){ .tag = core_result_Ok, .val = { .case_Ok = arr } }
usr.bin/ssh/libcrux_internal.h
780
val;
usr.bin/ssh/libcrux_internal.h
796
return self.val.case_Ok;
usr.bin/ssh/libcrux_internal.h
9394
val;
usr.bin/ssh/libcrux_internal.h
9416
.val = { .case_Ok = { .context = context, .pre_hash_oid = pre_hash_oid } }
usr.bin/ssh/libcrux_internal.h
9424
.val = { .case_Err = libcrux_ml_dsa_pre_hash_DomainSeparationError_ContextTooLongError }
usr.bin/ssh/log.c
115
return log_facilities[i].val;
usr.bin/ssh/log.c
125
if (log_facilities[i].val == facility)
usr.bin/ssh/log.c
138
return log_levels[i].val;
usr.bin/ssh/log.c
148
if (log_levels[i].val == level)
usr.bin/ssh/log.c
68
SyslogFacility val;
usr.bin/ssh/log.c
86
LogLevel val;
usr.bin/ssh/misc.c
1316
char *ret = NULL, *var, *varend, *val;
usr.bin/ssh/misc.c
1360
if ((val = getenv(var)) == NULL) {
usr.bin/ssh/misc.c
1364
debug3_f("expand ${%s} -> '%s'", var, val);
usr.bin/ssh/misc.c
1365
if ((r = sshbuf_put(buf, val, strlen(val))) !=0)
usr.bin/ssh/misc.c
148
int val;
usr.bin/ssh/misc.c
150
val = fcntl(fd, F_GETFL);
usr.bin/ssh/misc.c
151
if (val == -1) {
usr.bin/ssh/misc.c
155
if (val & O_NONBLOCK) {
usr.bin/ssh/misc.c
160
val |= O_NONBLOCK;
usr.bin/ssh/misc.c
161
if (fcntl(fd, F_SETFL, val) == -1) {
usr.bin/ssh/misc.c
172
int val;
usr.bin/ssh/misc.c
174
val = fcntl(fd, F_GETFL);
usr.bin/ssh/misc.c
175
if (val == -1) {
usr.bin/ssh/misc.c
179
if (!(val & O_NONBLOCK)) {
usr.bin/ssh/misc.c
184
val &= ~O_NONBLOCK;
usr.bin/ssh/misc.c
185
if (fcntl(fd, F_SETFL, val) == -1) {
usr.bin/ssh/misc.c
1890
int val;
usr.bin/ssh/misc.c
1899
val = (int)strtonum(cp, 0, 255, &errstr);
usr.bin/ssh/misc.c
1902
return val;
usr.bin/ssh/misc.c
2435
atoi_err(const char *nptr, int *val)
usr.bin/ssh/misc.c
2441
*val = strtonum(nptr, 0, INT_MAX, &errstr);
usr.bin/ssh/misc.c
617
double val, total_sec = 0.0, multiplier;
usr.bin/ssh/misc.c
630
if ((val = strtod(p, &endp)) < 0 || errno != 0 || p == endp)
usr.bin/ssh/misc.c
677
total_sec += val * multiplier;
usr.bin/ssh/packet.c
2691
sshpkt_put_u8(struct ssh *ssh, u_char val)
usr.bin/ssh/packet.c
2693
return sshbuf_put_u8(ssh->state->outgoing_packet, val);
usr.bin/ssh/packet.c
2697
sshpkt_put_u32(struct ssh *ssh, uint32_t val)
usr.bin/ssh/packet.c
2699
return sshbuf_put_u32(ssh->state->outgoing_packet, val);
usr.bin/ssh/packet.c
2703
sshpkt_put_u64(struct ssh *ssh, uint64_t val)
usr.bin/ssh/packet.c
2705
return sshbuf_put_u64(ssh->state->outgoing_packet, val);
usr.bin/ssh/packet.h
184
int sshpkt_put_u8(struct ssh *ssh, u_char val);
usr.bin/ssh/packet.h
185
int sshpkt_put_u32(struct ssh *ssh, uint32_t val);
usr.bin/ssh/packet.h
186
int sshpkt_put_u64(struct ssh *ssh, uint64_t val);
usr.bin/ssh/readconf.c
3555
fmt_multistate_int(int val, const struct multistate *m)
usr.bin/ssh/readconf.c
3560
if (m[i].value == val)
usr.bin/ssh/readconf.c
3567
fmt_intarg(OpCodes code, int val)
usr.bin/ssh/readconf.c
3569
if (val == -1)
usr.bin/ssh/readconf.c
3573
return fmt_multistate_int(val, multistate_addressfamily);
usr.bin/ssh/readconf.c
3575
return fmt_multistate_int(val, multistate_compression);
usr.bin/ssh/readconf.c
3578
return fmt_multistate_int(val, multistate_yesnoask);
usr.bin/ssh/readconf.c
3580
return fmt_multistate_int(val, multistate_strict_hostkey);
usr.bin/ssh/readconf.c
3582
return fmt_multistate_int(val, multistate_controlmaster);
usr.bin/ssh/readconf.c
3584
return fmt_multistate_int(val, multistate_tunnel);
usr.bin/ssh/readconf.c
3586
return fmt_multistate_int(val, multistate_requesttty);
usr.bin/ssh/readconf.c
3588
return fmt_multistate_int(val, multistate_sessiontype);
usr.bin/ssh/readconf.c
3590
return fmt_multistate_int(val, multistate_canonicalizehostname);
usr.bin/ssh/readconf.c
3592
return fmt_multistate_int(val, multistate_yesnoaskconfirm);
usr.bin/ssh/readconf.c
3594
return fmt_multistate_int(val, multistate_pubkey_auth);
usr.bin/ssh/readconf.c
3596
return ssh_digest_alg_name(val);
usr.bin/ssh/readconf.c
3598
switch (val) {
usr.bin/ssh/readconf.c
3621
dump_cfg_int(OpCodes code, int val)
usr.bin/ssh/readconf.c
3624
if (val == 0) {
usr.bin/ssh/readconf.c
3627
} else if (val == SSH_KEYSTROKE_DEFAULT_INTERVAL_MS) {
usr.bin/ssh/readconf.c
3633
printf("%s %d\n", lookup_opcode_name(code), val);
usr.bin/ssh/readconf.c
3637
dump_cfg_fmtint(OpCodes code, int val)
usr.bin/ssh/readconf.c
3639
printf("%s %s\n", lookup_opcode_name(code), fmt_intarg(code, val));
usr.bin/ssh/readconf.c
3643
dump_cfg_string(OpCodes code, const char *val)
usr.bin/ssh/readconf.c
3645
if (val == NULL)
usr.bin/ssh/readconf.c
3647
printf("%s %s\n", lookup_opcode_name(code), val);
usr.bin/ssh/scp.c
1608
#define TYPE_OVERFLOW(type, val) \
usr.bin/ssh/scp.c
1609
((sizeof(type) == 4 && (val) > INT32_MAX) || \
usr.bin/ssh/scp.c
1610
(sizeof(type) == 8 && (val) > INT64_MAX) || \
usr.bin/ssh/servconf.c
2051
for (i = 0; tunmode_desc[i].val != -1; i++)
usr.bin/ssh/servconf.c
2053
value = tunmode_desc[i].val;
usr.bin/ssh/servconf.c
2605
const char *val;
usr.bin/ssh/servconf.c
2608
if ((val = strprefix(p, "addr=", 0)) != NULL) {
usr.bin/ssh/servconf.c
2609
ci->address = xstrdup(val);
usr.bin/ssh/servconf.c
2610
} else if ((val = strprefix(p, "host=", 0)) != NULL) {
usr.bin/ssh/servconf.c
2611
ci->host = xstrdup(val);
usr.bin/ssh/servconf.c
2612
} else if ((val = strprefix(p, "user=", 0)) != NULL) {
usr.bin/ssh/servconf.c
2613
ci->user = xstrdup(val);
usr.bin/ssh/servconf.c
2614
} else if ((val = strprefix(p, "laddr=", 0)) != NULL) {
usr.bin/ssh/servconf.c
2615
ci->laddress = xstrdup(val);
usr.bin/ssh/servconf.c
2616
} else if ((val = strprefix(p, "rdomain=", 0)) != NULL) {
usr.bin/ssh/servconf.c
2617
ci->rdomain = xstrdup(val);
usr.bin/ssh/servconf.c
2618
} else if ((val = strprefix(p, "lport=", 0)) != NULL) {
usr.bin/ssh/servconf.c
2619
ci->lport = a2port(val);
usr.bin/ssh/servconf.c
3973
fmt_multistate_int(int val, const struct multistate *m)
usr.bin/ssh/servconf.c
3978
if (m[i].value == val)
usr.bin/ssh/servconf.c
3985
fmt_intarg(ServerOpCodes code, int val)
usr.bin/ssh/servconf.c
3987
if (val == -1)
usr.bin/ssh/servconf.c
3991
return fmt_multistate_int(val, multistate_addressfamily);
usr.bin/ssh/servconf.c
3993
return fmt_multistate_int(val, multistate_permitrootlogin);
usr.bin/ssh/servconf.c
3995
return fmt_multistate_int(val, multistate_gatewayports);
usr.bin/ssh/servconf.c
3997
return fmt_multistate_int(val, multistate_compression);
usr.bin/ssh/servconf.c
3999
return fmt_multistate_int(val, multistate_tcpfwd);
usr.bin/ssh/servconf.c
4001
return fmt_multistate_int(val, multistate_tcpfwd);
usr.bin/ssh/servconf.c
4003
return fmt_multistate_int(val, multistate_ignore_rhosts);
usr.bin/ssh/servconf.c
4005
return ssh_digest_alg_name(val);
usr.bin/ssh/servconf.c
4007
switch (val) {
usr.bin/ssh/servconf.c
4019
dump_cfg_int(ServerOpCodes code, int val)
usr.bin/ssh/servconf.c
4021
if (code == sUnusedConnectionTimeout && val == 0) {
usr.bin/ssh/servconf.c
4025
printf("%s %d\n", lookup_opcode_name(code), val);
usr.bin/ssh/servconf.c
4029
dump_cfg_oct(ServerOpCodes code, int val)
usr.bin/ssh/servconf.c
4031
printf("%s 0%o\n", lookup_opcode_name(code), val);
usr.bin/ssh/servconf.c
4035
dump_cfg_fmtint(ServerOpCodes code, int val)
usr.bin/ssh/servconf.c
4037
printf("%s %s\n", lookup_opcode_name(code), fmt_intarg(code, val));
usr.bin/ssh/servconf.c
4041
dump_cfg_string(ServerOpCodes code, const char *val)
usr.bin/ssh/servconf.c
4044
val == NULL ? "none" : val);
usr.bin/ssh/servconf.c
4263
for (i = 0; tunmode_desc[i].val != -1; i++) {
usr.bin/ssh/servconf.c
4264
if (tunmode_desc[i].val == o->permit_tun) {
usr.bin/ssh/servconf.c
520
int val;
usr.bin/ssh/session.c
1724
char *name, *val;
usr.bin/ssh/session.c
1729
(r = sshpkt_get_cstring(ssh, &val, NULL)) != 0 ||
usr.bin/ssh/session.c
1741
debug2("Setting env %d: %s=%s", s->num_env, name, val);
usr.bin/ssh/session.c
1745
s->env[s->num_env].val = val;
usr.bin/ssh/session.c
1754
free(val);
usr.bin/ssh/session.c
2096
free(s->env[i].val);
usr.bin/ssh/session.c
813
child_set_env(&env, &envsize, s->env[i].name, s->env[i].val);
usr.bin/ssh/session.h
62
char *val;
usr.bin/ssh/sftp-server.c
373
int val;
usr.bin/ssh/sftp-server.c
377
val = get_u32(handle);
usr.bin/ssh/sftp-server.c
378
if (handle_is_ok(val, HANDLE_FILE) ||
usr.bin/ssh/sftp-server.c
379
handle_is_ok(val, HANDLE_DIR))
usr.bin/ssh/sftp-server.c
380
return val;
usr.bin/ssh/ssh-keygen.c
129
char *val;
usr.bin/ssh/ssh-keygen.c
1565
cert_ext[ncert_ext].val = value == NULL ? NULL : xstrdup(value);
usr.bin/ssh/ssh-keygen.c
1582
if ((a->val == NULL) != (b->val == NULL))
usr.bin/ssh/ssh-keygen.c
1583
return (a->val == NULL) ? -1 : 1;
usr.bin/ssh/ssh-keygen.c
1584
if (a->val != NULL && (r = strcmp(a->val, b->val)) != 0)
usr.bin/ssh/ssh-keygen.c
1607
if (ext->val == NULL) {
usr.bin/ssh/ssh-keygen.c
1615
debug3_f("%s=%s", ext->key, ext->val);
usr.bin/ssh/ssh-keygen.c
1618
(r = sshbuf_put_cstring(b, ext->val)) != 0 ||
usr.bin/ssh/ssh-keygen.c
1950
char *val, *cp;
usr.bin/ssh/ssh-keygen.c
2000
val = xstrdup(strchr(opt, ':') + 1);
usr.bin/ssh/ssh-keygen.c
2001
if ((cp = strchr(val, '=')) != NULL)
usr.bin/ssh/ssh-keygen.c
2003
cert_ext_add(val, cp, iscrit);
usr.bin/ssh/ssh-keygen.c
2004
free(val);
usr.bin/ssh/ssh-pkcs11.c
1626
#define FILL_ATTR(attr, idx, typ, val, len) \
usr.bin/ssh/ssh-pkcs11.c
1627
{ (attr[idx]).type=(typ); (attr[idx]).pValue=(val); (attr[idx]).ulValueLen=len; idx++; }
usr.bin/ssh/ssh-pkcs11.c
285
CK_ATTRIBUTE_TYPE type, int *val)
usr.bin/ssh/ssh-pkcs11.c
293
*val = 0;
usr.bin/ssh/ssh-pkcs11.c
312
*val = flag != 0;
usr.bin/ssh/ssh-pkcs11.c
314
k11->provider->name, k11->slotidx, obj, type, *val);
usr.bin/ssh/sshbuf-getput-basic.c
185
const u_char *val;
usr.bin/ssh/sshbuf-getput-basic.c
193
if ((r = sshbuf_get_string_direct(buf, &val, &len)) < 0)
usr.bin/ssh/sshbuf-getput-basic.c
201
memcpy(*valp, val, len);
usr.bin/ssh/sshbuf-getput-basic.c
388
sshbuf_put_u64(struct sshbuf *buf, uint64_t val)
usr.bin/ssh/sshbuf-getput-basic.c
395
POKE_U64(p, val);
usr.bin/ssh/sshbuf-getput-basic.c
400
sshbuf_put_u32(struct sshbuf *buf, uint32_t val)
usr.bin/ssh/sshbuf-getput-basic.c
407
POKE_U32(p, val);
usr.bin/ssh/sshbuf-getput-basic.c
412
sshbuf_put_u16(struct sshbuf *buf, uint16_t val)
usr.bin/ssh/sshbuf-getput-basic.c
419
POKE_U16(p, val);
usr.bin/ssh/sshbuf-getput-basic.c
424
sshbuf_put_u8(struct sshbuf *buf, u_char val)
usr.bin/ssh/sshbuf-getput-basic.c
431
p[0] = val;
usr.bin/ssh/sshbuf-getput-basic.c
450
sshbuf_poke_u64(struct sshbuf *buf, size_t offset, uint64_t val)
usr.bin/ssh/sshbuf-getput-basic.c
457
POKE_U64(p, val);
usr.bin/ssh/sshbuf-getput-basic.c
462
sshbuf_poke_u32(struct sshbuf *buf, size_t offset, uint32_t val)
usr.bin/ssh/sshbuf-getput-basic.c
469
POKE_U32(p, val);
usr.bin/ssh/sshbuf-getput-basic.c
474
sshbuf_poke_u16(struct sshbuf *buf, size_t offset, uint16_t val)
usr.bin/ssh/sshbuf-getput-basic.c
481
POKE_U16(p, val);
usr.bin/ssh/sshbuf-getput-basic.c
486
sshbuf_poke_u8(struct sshbuf *buf, size_t offset, u_char val)
usr.bin/ssh/sshbuf-getput-basic.c
493
*p = val;
usr.bin/ssh/sshbuf-getput-basic.c
636
char *val = NULL;
usr.bin/ssh/sshbuf-getput-basic.c
652
if ((val = strdup(sshbuf_ptr(buf))) == NULL)
usr.bin/ssh/sshbuf-getput-basic.c
659
*valp = val;
usr.bin/ssh/sshbuf-getput-basic.c
660
val = NULL;
usr.bin/ssh/sshbuf-getput-basic.c
665
free(val);
usr.bin/ssh/sshbuf.h
186
int sshbuf_put_u64(struct sshbuf *buf, uint64_t val);
usr.bin/ssh/sshbuf.h
187
int sshbuf_put_u32(struct sshbuf *buf, uint32_t val);
usr.bin/ssh/sshbuf.h
188
int sshbuf_put_u16(struct sshbuf *buf, uint16_t val);
usr.bin/ssh/sshbuf.h
189
int sshbuf_put_u8(struct sshbuf *buf, u_char val);
usr.bin/ssh/sshbuf.h
205
int sshbuf_poke_u64(struct sshbuf *buf, size_t offset, uint64_t val);
usr.bin/ssh/sshbuf.h
206
int sshbuf_poke_u32(struct sshbuf *buf, size_t offset, uint32_t val);
usr.bin/ssh/sshbuf.h
207
int sshbuf_poke_u16(struct sshbuf *buf, size_t offset, uint16_t val);
usr.bin/ssh/sshbuf.h
208
int sshbuf_poke_u8(struct sshbuf *buf, size_t offset, u_char val);
usr.bin/systat/cpu.c
165
print_fld_percentage(field_def *fld, double val)
usr.bin/systat/cpu.c
171
tbprintf(val >= 1000 ? "%4.0f%%" : "%4.1f%%", val / 10.);
usr.bin/systat/engine.c
312
int len, i, d, tr, tw, val, pos, cur;
usr.bin/systat/engine.c
334
val = 0;
usr.bin/systat/engine.c
346
val++;
usr.bin/systat/engine.c
354
len = snprintf(buf, sizeof(buf), "%d\\", val);
usr.bin/systat/engine.c
371
int i, tw, val;
usr.bin/systat/engine.c
376
val = 0;
usr.bin/systat/engine.c
385
val++;
usr.bin/systat/engine.c
388
if (val > value)
usr.bin/systat/pf.c
127
print_fld_double(field_def *fld, double val)
usr.bin/systat/pf.c
139
if (tbprintf("%.2f", val) > len)
usr.bin/tcpbench/tcpbench.c
1022
*val = t->val;
usr.bin/tcpbench/tcpbench.c
982
map_tos(char *s, int *val)
usr.bin/tcpbench/tcpbench.c
987
int val;
usr.bin/telnet/commands.c
362
int val = 0;
usr.bin/telnet/commands.c
391
val = cpp - telopts;
usr.bin/telnet/commands.c
393
val = strtonum(name, 0, 255, &errstr);
usr.bin/telnet/commands.c
404
(*func)(val, 1);
usr.bin/telnet/commands.c
445
togbinary(int val)
usr.bin/telnet/commands.c
449
if (val >= 0) {
usr.bin/telnet/commands.c
450
binmode = val;
usr.bin/telnet/commands.c
459
val = binmode ? 0 : 1;
usr.bin/telnet/commands.c
462
if (val == 1) {
usr.bin/telnet/commands.c
483
togrbinary(int val)
usr.bin/telnet/commands.c
487
if (val == -1)
usr.bin/telnet/commands.c
488
val = my_want_state_is_do(TELOPT_BINARY) ? 0 : 1;
usr.bin/telnet/commands.c
490
if (val == 1) {
usr.bin/telnet/commands.c
509
togxbinary(int val)
usr.bin/telnet/commands.c
513
if (val == -1)
usr.bin/telnet/commands.c
514
val = my_want_state_is_will(TELOPT_BINARY) ? 0 : 1;
usr.bin/telnet/commands.c
516
if (val == 1) {
usr.bin/telnet/telnet.c
1030
if (spcp->val == (cc_t)(_POSIX_VDISABLE))
usr.bin/telnet/telnet.c
1035
spcp->val = *spcp->valp;
usr.bin/telnet/telnet.c
1036
slc_add_reply(spcp - spc_data, spcp->flags, spcp->val);
usr.bin/telnet/telnet.c
1072
if ((cp[SLC_VALUE] == (unsigned char)spcp->val) &&
usr.bin/telnet/telnet.c
1088
spcp->val = (cc_t)cp[SLC_VALUE];
usr.bin/telnet/telnet.c
1097
spcp->val = (cc_t)cp[SLC_VALUE];
usr.bin/telnet/telnet.c
1105
slc_add_reply(func, spcp->flags, spcp->val);
usr.bin/telnet/telnet.c
1119
if (spcp->valp && spcp->val != *spcp->valp) {
usr.bin/telnet/telnet.c
1120
spcp->val = *spcp->valp;
usr.bin/telnet/telnet.c
1121
if (spcp->val == (cc_t)(_POSIX_VDISABLE))
usr.bin/telnet/telnet.c
1125
slc_add_reply(spcp - spc_data, spcp->flags, spcp->val);
usr.bin/telnet/telnet.c
1201
if (spcp->valp && (*spcp->valp != spcp->val)) {
usr.bin/telnet/telnet.c
1202
*spcp->valp = spcp->val;
usr.bin/telnet/telnet.c
910
cc_t val;
usr.bin/telnet/telnet.c
928
spcp->val = 0;
usr.bin/telnet/telnet.c
936
spcp->val = *spcp->valp; \
usr.bin/telnet/telnet.c
939
spcp->val = 0; \
usr.bin/tftp/tftp.c
586
char *opt, *val;
usr.bin/tftp/tftp.c
591
val = tp->th_u.tu_stuff;
usr.bin/tftp/tftp.c
600
val = opt;
usr.bin/tftp/tftp.c
608
if (*val != '\0') {
usr.bin/tftp/tftp.c
609
val++;
usr.bin/tftp/tftp.c
613
val++;
usr.bin/tftp/tftp.c
615
printf("%s=%s", opt, val);
usr.bin/tftp/tftp.c
617
if (oack_set(opt, val) == -1)
usr.bin/tftp/tftp.c
619
len = strlen(val) + 1;
usr.bin/tftp/tftp.c
620
val += len;
usr.bin/tftp/tftp.c
621
opt = val;
usr.bin/tic/reset_cmd.c
179
#define DISABLED(val) (((_POSIX_VDISABLE != -1) \
usr.bin/tic/reset_cmd.c
180
&& ((val) == _POSIX_VDISABLE)) \
usr.bin/tic/reset_cmd.c
181
|| ((val) <= 0))
usr.bin/tic/reset_cmd.c
183
#define DISABLED(val) ((int)(val) <= 0)
usr.bin/tic/reset_cmd.c
186
#define CHK(val, dft) (unsigned char) (DISABLED(val) ? dft : val)
usr.bin/top/commands.c
108
val = val * 10 + (ch - '0');
usr.bin/top/commands.c
117
*intp = val;
usr.bin/top/commands.c
94
int val = 0, bad_flag = 0;
usr.bin/top/utils.c
75
itoa(int val)
usr.bin/top/utils.c
83
(void)snprintf(buffer, sizeof(buffer), "%d", val);
usr.bin/tr/str.c
295
int ch, val;
usr.bin/tr/str.c
306
val = 0;
usr.bin/tr/str.c
310
val = val * 8 + s->str[i] - '0';
usr.bin/tr/str.c
313
if (val > UCHAR_MAX)
usr.bin/tr/str.c
314
errx(1, "octal value out of range: %d", val);
usr.bin/tr/str.c
316
return (val);
usr.bin/unifdef/unifdef.c
1058
long val;
usr.bin/unifdef/unifdef.c
1075
rt = ops->inner(ops+1, &val, &cp);
usr.bin/unifdef/unifdef.c
1078
lt = op->fn(valp, lt, *valp, rt, val);
usr.bin/unifdef/unifdef.c
1096
long val = 0;
usr.bin/unifdef/unifdef.c
1100
ret = eval_table(eval_ops, &val, cpp);
usr.bin/unifdef/unifdef.c
1101
debug("eval = %d", val);
usr.bin/unifdef/unifdef.c
1409
const char *sym, *val;
usr.bin/unifdef/unifdef.c
1412
val = skipsym(sym);
usr.bin/unifdef/unifdef.c
1413
if (definethis && *val == '=') {
usr.bin/unifdef/unifdef.c
1414
symval[val - sym] = '\0';
usr.bin/unifdef/unifdef.c
1415
val = val + 1;
usr.bin/unifdef/unifdef.c
1416
} else if (*val == '\0') {
usr.bin/unifdef/unifdef.c
1417
val = definethis ? "1" : NULL;
usr.bin/unifdef/unifdef.c
1421
addsym2(ignorethis, sym, val);
usr.bin/unifdef/unifdef.c
1428
addsym2(bool ignorethis, const char *sym, const char *val)
usr.bin/unifdef/unifdef.c
1441
value[symind] = val;
usr.bin/unifdef/unifdef.c
1481
const char *cp, *kw, *sym, *val, *end;
usr.bin/unifdef/unifdef.c
1502
val = "1";
usr.bin/unifdef/unifdef.c
1505
val = (cp < end) ? xstrdup(cp, end) : "";
usr.bin/unifdef/unifdef.c
1508
addsym2(false, sym, val);
usr.bin/usbhidaction/usbhidaction.c
190
val = hid_get_data(buf, &cmd->item);
usr.bin/usbhidaction/usbhidaction.c
191
if (cmd->value == val || cmd->anyvalue)
usr.bin/usbhidaction/usbhidaction.c
192
docmd(cmd, val, dev, argc, argv);
usr.bin/usbhidaction/usbhidaction.c
85
int fd, ch, sz, n, val, i;
usr.bin/usbhidctl/usbhid.c
455
int val, i;
usr.bin/usbhidctl/usbhid.c
466
val = hid_get_data(buf, item);
usr.bin/usbhidctl/usbhid.c
469
val += item->usage_minimum;
usr.bin/usbhidctl/usbhid.c
470
printf("%s=1", hid_usage_in_page(val));
usr.bin/usbhidctl/usbhid.c
473
val, item->flags & HIO_CONST ? " (const)" : "");
usr.bin/vi/cl/cl_funcs.c
376
cl_keyval(SCR *sp, scr_keyval_t val, CHAR_T *chp, int *dnep)
usr.bin/vi/cl/cl_funcs.c
385
switch (val) {
usr.bin/vi/common/key.c
157
v_keyval(SCR *sp, int val, scr_keyval_t name)
usr.bin/vi/common/key.c
172
kp->value = val;
usr.bin/vi/common/key.c
179
keylist[nkeylist].value = val;
usr.bin/vi/common/options.c
698
o_set(SCR *sp, int opt, u_int flags, char *str, u_long val)
usr.bin/vi/common/options.c
704
&sp->gp->opts[sp->opts[opt].o_cur.val] : &sp->opts[opt];
usr.bin/vi/common/options.c
719
op->o_def.val = val;
usr.bin/vi/common/options.c
726
op->o_cur.val = val;
usr.bin/vi/common/options.h
31
(sp)->gp->opts[(sp)->opts[(o)].o_cur.val].fld : \
usr.bin/vi/common/options.h
35
#define OG_CLR(gp, o) ((gp)->opts[(o)].o_cur.val) = 0
usr.bin/vi/common/options.h
36
#define OG_SET(gp, o) ((gp)->opts[(o)].o_cur.val) = 1
usr.bin/vi/common/options.h
38
#define OG_VAL(gp, o) ((gp)->opts[(o)].o_cur.val)
usr.bin/vi/common/options.h
42
#define OG_D_VAL(gp, o) ((gp)->opts[(o)].o_def.val)
usr.bin/vi/common/options.h
55
u_long val; /* Value or boolean. */
usr.bin/vi/common/options.h
61
#define O_VAL(sp, o) O_V((sp), (o), o_cur.val)
usr.bin/vi/common/options.h
65
u_long val; /* Value or boolean. */
usr.bin/vi/common/options.h
71
#define O_D_VAL(sp, o) O_V((sp), (o), o_def.val)
usr.bin/vi/ex/ex.c
1815
long total, val;
usr.bin/vi/ex/ex.c
1846
if ((nret = nget_slong(&val, ecp->cp, &endp, 10)) != NUM_OK) {
usr.bin/vi/ex/ex.c
1851
if (!NPFITS(MAX_REC_NUMBER, 0, val)) {
usr.bin/vi/ex/ex.c
1856
mp->lno = val;
usr.bin/vi/ex/ex.c
2010
if ((nret = nget_slong(&val,
usr.bin/vi/ex/ex.c
2012
(nret = NADD_SLONG(total, val)) != NUM_OK) {
usr.bin/vi/ex/ex.c
2017
total += isneg ? -val : val;
usr.bin/vi/vi/vs_relative.c
139
#define CHLEN(val) (ch = *(u_char *)p++) == '\t' && \
usr.bin/vi/vi/vs_relative.c
140
!listset ? TAB_OFF(val) : KEY_LEN(sp, ch);
usr.bin/vmstat/vmstat.c
929
#define PRWORD(ovflw, fmt, width, fixed, val) do { \
usr.bin/vmstat/vmstat.c
933
(val)) - (width); \
usr.sbin/acme-client/http.c
448
rc = sscanf(st->val, "%*s %u %*s", &code);
usr.sbin/acme-client/http.c
531
h[hsz++].val = cp;
usr.sbin/acme-client/http.c
545
h[hsz++].val = ccp;
usr.sbin/acme-client/http.h
34
const char *val;
usr.sbin/acme-client/netproc.c
225
host = url2host(st->val, &port, &path);
usr.sbin/acme-client/netproc.c
286
} else if ((nonce = strdup(h->val)) == NULL) {
usr.sbin/acme-client/netproc.c
382
} else if ((nonce = strdup(h->val)) == NULL) {
usr.sbin/acme-client/netproc.c
398
*loc = strdup(h->val);
usr.sbin/acme-client/parse.y
651
char *p, *val;
usr.sbin/acme-client/parse.y
681
val = symget(buf);
usr.sbin/acme-client/parse.y
682
if (val == NULL) {
usr.sbin/acme-client/parse.y
686
p = val + strlen(val) - 1;
usr.sbin/acme-client/parse.y
688
while (p >= val) {
usr.sbin/acme-client/parse.y
86
char *val;
usr.sbin/acme-client/parse.y
883
free(sym->val);
usr.sbin/acme-client/parse.y
905
symset(const char *nam, const char *val, int persist)
usr.sbin/acme-client/parse.y
919
free(sym->val);
usr.sbin/acme-client/parse.y
932
sym->val = strdup(val);
usr.sbin/acme-client/parse.y
933
if (sym->val == NULL) {
usr.sbin/acme-client/parse.y
947
char *sym, *val;
usr.sbin/acme-client/parse.y
950
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/acme-client/parse.y
952
sym = strndup(s, val - s);
usr.sbin/acme-client/parse.y
955
ret = symset(sym, val + 1, 1);
usr.sbin/acme-client/parse.y
969
return sym->val;
usr.sbin/amd/amd/info_file.c
158
*val = dc;
usr.sbin/amd/amd/info_file.c
85
search_or_reload_file(FILE *fp, char *map, char *key, char **val, mnt_map *m,
usr.sbin/amd/amd/info_ndbm.c
51
search_ndbm(DBM *db, char *key, char **val)
usr.sbin/amd/amd/info_ndbm.c
59
*val = strdup(v.dptr);
usr.sbin/amd/amd/info_nis.c
105
char *vp = strnsave(val, vl);
usr.sbin/amd/amd/info_nis.c
167
nis_search(mnt_map *m, char *map, char *key, char **val, time_t *tp)
usr.sbin/amd/amd/info_nis.c
222
res = yp_match(domain, map, key, strlen(key), val, &outlen);
usr.sbin/amd/amd/info_nis.c
96
callback(unsigned long status, char *key, int kl, char *val, int vl, void *arg)
usr.sbin/amd/amd/info_passwd.c
135
snprintf(val, sizeof(val),
usr.sbin/amd/amd/info_passwd.c
141
*pval = strdup(val);
usr.sbin/amd/amd/info_passwd.c
89
char val[PATH_MAX], rhost[HOST_NAME_MAX+1];
usr.sbin/amd/amd/info_union.c
107
char *val;
usr.sbin/amd/amd/info_union.c
117
val = xmalloc(dlen + 5);
usr.sbin/amd/amd/info_union.c
118
snprintf(val, dlen + 5, "fs:=%s", *dir);
usr.sbin/amd/amd/info_union.c
119
(*fn)(m, strdup(dp->d_name), val);
usr.sbin/amd/amd/info_union.c
128
char *val = xmalloc(strlen(dir[-1]) + 5);
usr.sbin/amd/amd/info_union.c
130
snprintf(val, strlen(dir[-1]) + 5, "fs:=%s", dir[-1]);
usr.sbin/amd/amd/info_union.c
131
(*fn)(m, strdup("*"), val);
usr.sbin/amd/amd/mapc.c
120
char *val;
usr.sbin/amd/amd/mapc.c
238
mapc_add_kv(mnt_map *m, char *key, char *val)
usr.sbin/amd/amd/mapc.c
245
dlog("add_kv: %s -> %s", key, val);
usr.sbin/amd/amd/mapc.c
280
n->val = val;
usr.sbin/amd/amd/mapc.c
286
mapc_repl_kv(mnt_map *m, char *key, char *val)
usr.sbin/amd/amd/mapc.c
302
free(k->val);
usr.sbin/amd/amd/mapc.c
303
k->val = val;
usr.sbin/amd/amd/mapc.c
305
mapc_add_kv(m, key, val);
usr.sbin/amd/amd/mapc.c
464
free(k->val);
usr.sbin/amd/amd/mapc.c
596
if (k->val)
usr.sbin/amd/amd/mapc.c
597
*pval = strdup(k->val);
usr.sbin/amd/amd/opts.c
106
char *val;
usr.sbin/amd/amd/opts.c
494
char *val;
usr.sbin/amd/amd/opts.c
509
val = xbuf;
usr.sbin/amd/amd/opts.c
516
val = *op->sel_p;
usr.sbin/amd/amd/opts.c
518
val = *op->optp;
usr.sbin/amd/amd/opts.c
520
if (val) {
usr.sbin/amd/amd/opts.c
529
int vlen = strlen(val);
usr.sbin/amd/amd/opts.c
530
char *vptr = val;
usr.sbin/amd/amd/opts.c
533
vptr = strrchr(val, '/');
usr.sbin/amd/amd/opts.c
535
vlen = vptr - val;
usr.sbin/amd/amd/opts.c
536
vptr = val;
usr.sbin/amd/amd/opts.c
539
vptr = strrchr(val, '/');
usr.sbin/amd/amd/opts.c
544
vptr = val;
usr.sbin/amd/amd/opts.c
547
vptr = strchr(val, '.');
usr.sbin/amd/amd/opts.c
557
vptr = strchr(val, '.');
usr.sbin/amd/amd/opts.c
559
vlen = vptr - val;
usr.sbin/amd/amd/opts.c
560
vptr = val;
usr.sbin/amd/amd/opts.c
658
} else if (p->val) {
usr.sbin/amd/amd/opts.c
664
char *s = *p->opt = expand_key(p->val);
usr.sbin/amd/amd/opts.c
706
oa.opt = &key; oa.val = 0;
usr.sbin/bgpctl/ometric.c
422
ometric_set_int_value(struct ometric *om, uint64_t val, struct olabels *ol)
usr.sbin/bgpctl/ometric.c
429
ov->value.i = val;
usr.sbin/bgpctl/ometric.c
440
ometric_set_int(struct ometric *om, uint64_t val, struct olabels *ol)
usr.sbin/bgpctl/ometric.c
445
ometric_set_int_value(om, val, ol);
usr.sbin/bgpctl/ometric.c
452
ometric_set_float(struct ometric *om, double val, struct olabels *ol)
usr.sbin/bgpctl/ometric.c
462
ov->value.f = val;
usr.sbin/bgpctl/ometric.c
518
int val;
usr.sbin/bgpctl/ometric.c
525
val = 1;
usr.sbin/bgpctl/ometric.c
527
val = 0;
usr.sbin/bgpctl/ometric.c
531
ometric_set_int_value(om, val, extra);
usr.sbin/bgpctl/ometric.c
541
ometric_set_int_with_labels(struct ometric *om, uint64_t val,
usr.sbin/bgpctl/ometric.c
547
ometric_set_int(om, val, extra);
usr.sbin/bgpctl/ometric.c
552
ometric_set_float_with_labels(struct ometric *om, double val,
usr.sbin/bgpctl/ometric.c
558
ometric_set_float(om, val, extra);
usr.sbin/bgpctl/output.c
484
if (get_rel_monotime(t->val) >= 0)
usr.sbin/bgpctl/output.c
487
printf("%s\n", fmt_monotime(t->val));
usr.sbin/bgpctl/output.c
782
uint32_t as, pathid, val;
usr.sbin/bgpctl/output.c
847
if (alen != 4 || ibuf_get_n32(buf, &val) == -1)
usr.sbin/bgpctl/output.c
849
printf("%u", val);
usr.sbin/bgpctl/output_json.c
377
json_do_int("due", -get_rel_monotime(t->val));
usr.sbin/bgpctl/output_json.c
594
uint32_t as, pathid, val;
usr.sbin/bgpctl/output_json.c
668
if (alen != 4 || ibuf_get_n32(buf, &val) == -1)
usr.sbin/bgpctl/output_json.c
670
json_do_uint("metric", val);
usr.sbin/bgpctl/parser.c
1152
getcommunity(char *s, int large, uint32_t *val, uint32_t *flag)
usr.sbin/bgpctl/parser.c
1158
*val = 0;
usr.sbin/bgpctl/parser.c
1171
*val = strtonum(s, 0, max, &errstr);
usr.sbin/bgpctl/parser.c
1505
push_numop(struct parse_result *r, int type, uint8_t op, int and, long long val)
usr.sbin/bgpctl/parser.c
1518
if (val < 0 || val > 0xffffffff) {
usr.sbin/bgpctl/parser.c
1520
} else if (val <= 255) {
usr.sbin/bgpctl/parser.c
1522
u8 = val;
usr.sbin/bgpctl/parser.c
1524
} else if (val <= 0xffff) {
usr.sbin/bgpctl/parser.c
1526
u16 = htons(val);
usr.sbin/bgpctl/parser.c
1531
u32 = htonl(val);
usr.sbin/bgpctl/parser.c
1553
long long val, val2;
usr.sbin/bgpctl/parser.c
1603
val = strtonum(argv[1], LLONG_MIN, LLONG_MAX, &errstr);
usr.sbin/bgpctl/parser.c
1607
push_numop(r, type, op, 0, val);
usr.sbin/bgpctl/parser.c
1611
val = strtonum(argv[0], LLONG_MIN, LLONG_MAX, &errstr);
usr.sbin/bgpctl/parser.c
1624
0, val);
usr.sbin/bgpctl/parser.c
1630
0, val);
usr.sbin/bgpctl/parser.c
1638
push_numop(r, type, FLOWSPEC_OP_NUM_EQ, 0, val);
usr.sbin/bgpd/bgpd.h
578
monotime_t val;
usr.sbin/bgpd/bgpd.h
648
monotime_t val;
usr.sbin/bgpd/chash.c
941
ch_rotate(uint64_t val, int shift)
usr.sbin/bgpd/chash.c
943
return shift == 0 ? val : ((val >> shift) | (val << (64 - shift)));
usr.sbin/bgpd/control.c
351
ct.val = d;
usr.sbin/bgpd/flowspec.c
418
uint64_t val = 0;
usr.sbin/bgpd/flowspec.c
421
val <<= 8;
usr.sbin/bgpd/flowspec.c
422
val |= *comp++;
usr.sbin/bgpd/flowspec.c
424
return val;
usr.sbin/bgpd/flowspec.c
431
uint64_t val, val2 = 0;
usr.sbin/bgpd/flowspec.c
444
val = extract_val(comp + *off + 1, FLOWSPEC_OP_LEN(op));
usr.sbin/bgpd/flowspec.c
467
(unsigned long long)val, (unsigned long long)val2);
usr.sbin/bgpd/flowspec.c
478
(unsigned long long)val);
usr.sbin/bgpd/flowspec.c
483
(unsigned long long)val);
usr.sbin/bgpd/flowspec.c
488
(unsigned long long)val);
usr.sbin/bgpd/flowspec.c
493
(unsigned long long)val);
usr.sbin/bgpd/flowspec.c
498
(unsigned long long)val);
usr.sbin/bgpd/flowspec.c
503
(unsigned long long)val);
usr.sbin/bgpd/flowspec.c
521
fmt_flags(uint64_t val, const char *bits, char *buf, size_t blen)
usr.sbin/bgpd/flowspec.c
525
for (i = 0, bi = 0; i < 64 && val != 0; i++) {
usr.sbin/bgpd/flowspec.c
526
if (val & 1) {
usr.sbin/bgpd/flowspec.c
531
val >>= 1;
usr.sbin/bgpd/flowspec.c
537
snprintf(buf, blen, "%llx", (unsigned long long)val);
usr.sbin/bgpd/flowspec.c
546
uint64_t val, val2 = 0;
usr.sbin/bgpd/flowspec.c
559
val = extract_val(comp + *off + 1, FLOWSPEC_OP_LEN(op));
usr.sbin/bgpd/flowspec.c
580
val2 |= val;
usr.sbin/bgpd/flowspec.c
582
fmt_flags(val, bits, bit, sizeof(bit)),
usr.sbin/bgpd/flowspec.c
588
fmt_flags(val, bits, bit, sizeof(bit)));
usr.sbin/bgpd/flowspec.c
592
fmt_flags(val, bits, mask, sizeof(mask)));
usr.sbin/bgpd/flowspec.c
596
fmt_flags(val, bits, bit, sizeof(bit)),
usr.sbin/bgpd/flowspec.c
597
fmt_flags(val, bits, mask, sizeof(mask)));
usr.sbin/bgpd/parse.y
1461
int val;
usr.sbin/bgpd/parse.y
1464
if (map_tos($1, &val))
usr.sbin/bgpd/parse.y
1465
$$ = val;
usr.sbin/bgpd/parse.y
3845
char *p, *val;
usr.sbin/bgpd/parse.y
3864
val = symget(buf);
usr.sbin/bgpd/parse.y
3865
if (val == NULL) {
usr.sbin/bgpd/parse.y
3869
p = val + strlen(val) - 1;
usr.sbin/bgpd/parse.y
3871
while (p >= val) {
usr.sbin/bgpd/parse.y
4190
free(sym->val);
usr.sbin/bgpd/parse.y
4274
symset(const char *nam, const char *val, int persist)
usr.sbin/bgpd/parse.y
4288
free(sym->val);
usr.sbin/bgpd/parse.y
4301
sym->val = strdup(val);
usr.sbin/bgpd/parse.y
4302
if (sym->val == NULL) {
usr.sbin/bgpd/parse.y
4316
char *sym, *val;
usr.sbin/bgpd/parse.y
4319
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/bgpd/parse.y
4321
sym = strndup(s, val - s);
usr.sbin/bgpd/parse.y
4324
ret = symset(sym, val + 1, 1);
usr.sbin/bgpd/parse.y
4338
return (sym->val);
usr.sbin/bgpd/parse.y
4367
getcommunity(char *s, int large, uint32_t *val, uint32_t *flag)
usr.sbin/bgpd/parse.y
4373
*val = 0;
usr.sbin/bgpd/parse.y
4386
*val = strtonum(s, 0, max, &errstr);
usr.sbin/bgpd/parse.y
5599
map_tos(char *s, int *val)
usr.sbin/bgpd/parse.y
5638
*val = p->k_val;
usr.sbin/bgpd/parse.y
5810
push_binop(uint8_t binop, long long val)
usr.sbin/bgpd/parse.y
5816
if (val < 0 || val > 0xff) {
usr.sbin/bgpd/parse.y
5820
u8 = val;
usr.sbin/bgpd/parse.y
5885
push_numop(enum comp_ops op, int and, long long val)
usr.sbin/bgpd/parse.y
5894
if (val < 0 || val > 0xffffffff) {
usr.sbin/bgpd/parse.y
5897
} else if (val <= 255) {
usr.sbin/bgpd/parse.y
5899
u8 = val;
usr.sbin/bgpd/parse.y
5901
} else if (val <= 0xffff) {
usr.sbin/bgpd/parse.y
5903
u16 = htons(val);
usr.sbin/bgpd/parse.y
5907
u32 = htonl(val);
usr.sbin/bgpd/parse.y
5929
push_unary_numop(enum comp_ops op, long long val)
usr.sbin/bgpd/parse.y
5931
return push_numop(op, 0, val);
usr.sbin/bgpd/parse.y
91
char *val;
usr.sbin/bgpd/rtr_proto.c
1600
ct.val = d;
usr.sbin/bgpd/session_bgp.c
95
capa2role(uint8_t val)
usr.sbin/bgpd/session_bgp.c
97
switch (val) {
usr.sbin/bgpd/timer.c
111
t->val = monotime_clear();
usr.sbin/bgpd/timer.c
44
if (t != NULL && monotime_valid(t->val) &&
usr.sbin/bgpd/timer.c
45
monotime_cmp(t->val, now) <= 0)
usr.sbin/bgpd/timer.c
55
if ((t = TAILQ_FIRST(th)) != NULL && monotime_valid(t->val))
usr.sbin/bgpd/timer.c
56
return t->val;
usr.sbin/bgpd/timer.c
65
if (t != NULL && monotime_valid(t->val)) {
usr.sbin/bgpd/timer.c
67
*due = t->val;
usr.sbin/bgpd/timer.c
88
if (monotime_cmp(t->val, ms) == 0)
usr.sbin/bgpd/timer.c
93
t->val = ms;
usr.sbin/bgpd/timer.c
96
if (!monotime_valid(next->val) ||
usr.sbin/bgpd/timer.c
97
monotime_cmp(next->val, t->val) > 0)
usr.sbin/bgplgd/qs.c
172
parse_value(struct lg_ctx *ctx, unsigned int qs, enum qs_type type, char *val)
usr.sbin/bgplgd/qs.c
175
if (val == NULL) {
usr.sbin/bgplgd/qs.c
182
if (strcmp("1", val) == 0) {
usr.sbin/bgplgd/qs.c
184
} else if (strcmp("0", val) == 0) {
usr.sbin/bgplgd/qs.c
187
lwarnx("%s: bad value %s expected 1", qs2str(qs), val);
usr.sbin/bgplgd/qs.c
193
if (!valid_string(val)) {
usr.sbin/bgplgd/qs.c
197
ctx->qs_args[qs].string = strdup(val);
usr.sbin/bgplgd/qs.c
204
if (!valid_number(val)) {
usr.sbin/bgplgd/qs.c
208
ctx->qs_args[qs].string = strdup(val);
usr.sbin/bgplgd/qs.c
215
if (!valid_prefix(val)) {
usr.sbin/bgplgd/qs.c
219
ctx->qs_args[qs].string = strdup(val);
usr.sbin/bgplgd/qs.c
226
if (strcasecmp("ipv4", val) == 0 ||
usr.sbin/bgplgd/qs.c
227
strcasecmp("ipv6", val) == 0 ||
usr.sbin/bgplgd/qs.c
228
strcasecmp("vpnv4", val) == 0 ||
usr.sbin/bgplgd/qs.c
229
strcasecmp("vpnv6", val) == 0) {
usr.sbin/bgplgd/qs.c
230
ctx->qs_args[qs].string = strdup(val);
usr.sbin/bgplgd/qs.c
236
lwarnx("%s: bad value %s", qs2str(qs), val);
usr.sbin/bgplgd/qs.c
241
if (strcmp("not-found", val) == 0 ||
usr.sbin/bgplgd/qs.c
242
strcmp("valid", val) == 0 ||
usr.sbin/bgplgd/qs.c
243
strcmp("invalid", val) == 0) {
usr.sbin/bgplgd/qs.c
244
ctx->qs_args[qs].string = strdup(val);
usr.sbin/bgplgd/qs.c
250
lwarnx("%s: bad OVS value %s", qs2str(qs), val);
usr.sbin/bgplgd/qs.c
255
if (strcmp("unknown", val) == 0 ||
usr.sbin/bgplgd/qs.c
256
strcmp("valid", val) == 0 ||
usr.sbin/bgplgd/qs.c
257
strcmp("invalid", val) == 0) {
usr.sbin/bgplgd/qs.c
258
ctx->qs_args[qs].string = strdup(val);
usr.sbin/bgplgd/qs.c
264
lwarnx("%s: bad AVS value %s", qs2str(qs), val);
usr.sbin/bgplgd/slowcgi.c
1203
free(env_entry->val);
usr.sbin/bgplgd/slowcgi.c
801
if ((env_entry->val = malloc(val_len + 1)) == NULL) {
usr.sbin/bgplgd/slowcgi.c
812
memcpy(env_entry->val, buf, val_len);
usr.sbin/bgplgd/slowcgi.c
815
env_entry->val[val_len] = '\0';
usr.sbin/bgplgd/slowcgi.c
819
env_entry->val);
usr.sbin/bgplgd/slowcgi.c
82
char *val;
usr.sbin/bgplgd/slowcgi.c
887
return (env->val);
usr.sbin/btrace/bt_parse.y
278
long val;
usr.sbin/btrace/bt_parse.y
281
val = (long)strtonum(vargs[index-1], LONG_MIN, LONG_MAX,
usr.sbin/btrace/bt_parse.y
284
return ba_new(val, B_AT_LONG);
usr.sbin/btrace/bt_parse.y
450
ba_new0(void *val, enum bt_argtype type)
usr.sbin/btrace/bt_parse.y
457
ba->ba_value = val;
usr.sbin/btrace/btrace.c
1049
long val;
usr.sbin/btrace/btrace.c
1065
val = ba2long(map_get(map, hash), NULL);
usr.sbin/btrace/btrace.c
1066
val++;
usr.sbin/btrace/btrace.c
1067
bval = ba_new(val, B_AT_LONG);
usr.sbin/btrace/btrace.c
1070
val = ba2long(map_get(map, hash), NULL);
usr.sbin/btrace/btrace.c
1071
val = MAXIMUM(val, ba2long(bval->ba_value, dtev));
usr.sbin/btrace/btrace.c
1072
bval = ba_new(val, B_AT_LONG);
usr.sbin/btrace/btrace.c
1075
val = ba2long(map_get(map, hash), NULL);
usr.sbin/btrace/btrace.c
1076
val = MINIMUM(val, ba2long(bval->ba_value, dtev));
usr.sbin/btrace/btrace.c
1077
bval = ba_new(val, B_AT_LONG);
usr.sbin/btrace/btrace.c
1080
val = ba2long(map_get(map, hash), NULL);
usr.sbin/btrace/btrace.c
1081
val += ba2long(bval->ba_value, dtev);
usr.sbin/btrace/btrace.c
1082
bval = ba_new(val, B_AT_LONG);
usr.sbin/btrace/btrace.c
1424
long val, bucket;
usr.sbin/btrace/btrace.c
1427
val = ba2long(ba, dtev);
usr.sbin/btrace/btrace.c
1429
bucket = next_pow2(val);
usr.sbin/btrace/btrace.c
1440
if ((val < min) || (val > max))
usr.sbin/btrace/btrace.c
1447
bucket = ((val / step) + 1) * step;
usr.sbin/btrace/btrace.c
1704
long val;
usr.sbin/btrace/btrace.c
1708
val = (*ba2str(ba, dtev) == '\0') ? 0 : 1;
usr.sbin/btrace/btrace.c
1711
val = (long)ba->ba_value;
usr.sbin/btrace/btrace.c
1715
val = (long)ba->ba_value;
usr.sbin/btrace/btrace.c
1722
val = ba2long(map_get((struct map *)bv->bv_value,
usr.sbin/btrace/btrace.c
1726
val = 0L;
usr.sbin/btrace/btrace.c
1729
val = dtev->dtev_pid;
usr.sbin/btrace/btrace.c
1732
val = dtev->dtev_tid;
usr.sbin/btrace/btrace.c
1735
val = dtev->dtev_cpu;
usr.sbin/btrace/btrace.c
1738
val = builtin_nsecs(dtev);
usr.sbin/btrace/btrace.c
1741
val = dtev->dtev_args[ba->ba_type - B_AT_BI_ARG0];
usr.sbin/btrace/btrace.c
1744
val = dtev->dtev_retval[0];
usr.sbin/btrace/btrace.c
1747
val = dtev->dtev_pbn;
usr.sbin/btrace/btrace.c
1750
val = baexpr2long(ba, dtev);
usr.sbin/btrace/btrace.c
1756
return val;
usr.sbin/btrace/btrace.c
1972
long val;
usr.sbin/btrace/btrace.c
1988
val = bacmp(a, b);
usr.sbin/btrace/btrace.c
1989
if (val != 0)
usr.sbin/btrace/btrace.c
1995
val = -1;
usr.sbin/btrace/btrace.c
1997
val = 1;
usr.sbin/btrace/btrace.c
2000
return val;
usr.sbin/btrace/map.c
216
long val;
usr.sbin/btrace/map.c
221
val = (long)ba->ba_value;
usr.sbin/btrace/map.c
222
val++;
usr.sbin/btrace/map.c
223
ba->ba_value = (void *)val;
usr.sbin/btrace/map.c
306
long bmin, bprev, bin, val, max = 0;
usr.sbin/btrace/map.c
314
val = ba2long(mep->mval, NULL);
usr.sbin/btrace/map.c
315
if (val > max)
usr.sbin/btrace/map.c
316
max = val;
usr.sbin/btrace/map.c
339
val = ba2long(mcur->mval, NULL);
usr.sbin/btrace/map.c
340
i = (length * val) / max;
usr.sbin/btrace/map.c
343
20 - l, val,
usr.sbin/btrace/printf.c
443
long val;
usr.sbin/btrace/printf.c
458
val = strtol(str, &ep, 0);
usr.sbin/btrace/printf.c
460
return val;
usr.sbin/btrace/printf.c
467
unsigned long val;
usr.sbin/btrace/printf.c
482
val = strtoul(str, &ep, 0);
usr.sbin/btrace/printf.c
484
return val;
usr.sbin/btrace/printf.c
491
double val;
usr.sbin/btrace/printf.c
506
val = strtod(str, &ep);
usr.sbin/btrace/printf.c
508
return val;
usr.sbin/config/config.h
327
#define ht_insert(ht, nam, val) ht_insrep(ht, nam, val, 0)
usr.sbin/config/config.h
328
#define ht_replace(ht, nam, val) ht_insrep(ht, nam, val, 1)
usr.sbin/config/gram.y
104
%token <val> NUMBER
usr.sbin/config/gram.y
112
%type <val> fflgs fflag oflgs oflag
usr.sbin/config/gram.y
117
%type <val> disable
usr.sbin/config/gram.y
128
%type <val> major_minor signed_number npseudo
usr.sbin/config/gram.y
129
%type <val> flags_opt
usr.sbin/config/gram.y
96
int val;
usr.sbin/config/hash.c
237
ht_insrep(struct hashtab *ht, const char *nam, void *val, int replace)
usr.sbin/config/hash.c
247
hp->h_value = val;
usr.sbin/config/hash.c
252
hp->h_value = val;
usr.sbin/config/main.c
740
const char *val;
usr.sbin/config/main.c
751
if (!sp1->val && !sp2->val)
usr.sbin/config/main.c
753
else if (sp1->val && !sp2->val)
usr.sbin/config/main.c
755
else if (sp2->val && !sp1->val)
usr.sbin/config/main.c
757
else r = strcmp(sp1->val, sp2->val);
usr.sbin/config/main.c
778
newopts[i].val = nv->nv_str;
usr.sbin/config/main.c
785
if (newopts[i].val)
usr.sbin/config/main.c
787
newopts[i].name, newopts[i].val);
usr.sbin/config/main.c
804
if (newopts[i].val)
usr.sbin/config/main.c
806
newopts[i].val);
usr.sbin/config/ukcutil.c
1009
*val = a;
usr.sbin/config/ukcutil.c
1036
int val, max_unit, star_unit;
usr.sbin/config/ukcutil.c
1068
add_read("Clone Device (DevNo, 'q' or '?')", 'a', dev, len, &val);
usr.sbin/config/ukcutil.c
1070
if (val != -1) {
usr.sbin/config/ukcutil.c
1071
cd = get_cfdata(val);
usr.sbin/config/ukcutil.c
1076
'i', dev, len, &val);
usr.sbin/config/ukcutil.c
1079
if (val != -1) {
usr.sbin/config/ukcutil.c
1084
for (i = maxdev; val <= i; i--) {
usr.sbin/config/ukcutil.c
1087
cd = get_cfdata(val);
usr.sbin/config/ukcutil.c
1094
if (*pv != 1 && *pv >= val)
usr.sbin/config/ukcutil.c
1103
if (*pv != 1 && *pv >= val)
usr.sbin/config/ukcutil.c
1186
pdev(val);
usr.sbin/config/ukcutil.c
1200
int val, max_unit;
usr.sbin/config/ukcutil.c
1212
val = newno;
usr.sbin/config/ukcutil.c
1221
for (i = maxdev; val <= i; i--)
usr.sbin/config/ukcutil.c
1223
cd = get_cfdata(val);
usr.sbin/config/ukcutil.c
123
pnum(long val)
usr.sbin/config/ukcutil.c
1230
if (*pv != 1 && *pv >= val)
usr.sbin/config/ukcutil.c
1239
if (*pv != 1 && *pv >= val)
usr.sbin/config/ukcutil.c
125
if (val > -2 && val < 16) {
usr.sbin/config/ukcutil.c
126
printf("%ld", val);
usr.sbin/config/ukcutil.c
1294
pdev(val);
usr.sbin/config/ukcutil.c
132
printf("0%lo", val);
usr.sbin/config/ukcutil.c
135
printf("%ld", val);
usr.sbin/config/ukcutil.c
139
printf("0x%lx", val);
usr.sbin/config/ukcutil.c
248
numberl(const char *c, long *val)
usr.sbin/config/ukcutil.c
253
*val = strtol(c, &ep, 0);
usr.sbin/config/ukcutil.c
255
(errno == ERANGE && (*val == LONG_MAX || *val == LONG_MIN)))
usr.sbin/config/ukcutil.c
261
number(const char *c, int *val)
usr.sbin/config/ukcutil.c
268
*val = (int)v;
usr.sbin/config/ukcutil.c
311
attr(char *cmd, int *val)
usr.sbin/config/ukcutil.c
336
*val = attr;
usr.sbin/config/ukcutil.c
341
modifyl(char *item, long *val)
usr.sbin/config/ukcutil.c
349
pnum(*val);
usr.sbin/config/ukcutil.c
358
*val = a;
usr.sbin/config/ukcutil.c
370
modify(char *item, int *val)
usr.sbin/config/ukcutil.c
372
long a = *val;
usr.sbin/config/ukcutil.c
376
*val = (int)a;
usr.sbin/config/ukcutil.c
752
common_attr_val(short attr, int *val, char routine)
usr.sbin/config/ukcutil.c
769
if (val == NULL) {
usr.sbin/config/ukcutil.c
773
if (*val == *l) {
usr.sbin/config/ukcutil.c
978
add_read(char *prompt, char field, char *dev, int len, int *val)
usr.sbin/config/ukcutil.c
986
*val = -1;
usr.sbin/cron/env.c
162
char name[MAX_ENVSTR], val[MAX_ENVSTR];
usr.sbin/cron/env.c
172
bzero(val, sizeof val);
usr.sbin/cron/env.c
215
str = val;
usr.sbin/cron/env.c
239
c = val + strlen(val);
usr.sbin/cron/env.c
240
while (c > val && isspace((unsigned char)c[-1]))
usr.sbin/cron/env.c
250
if (snprintf(envstr, MAX_ENVSTR, "%s=%s", name, val) >= MAX_ENVSTR)
usr.sbin/dhcpd/confpars.c
1002
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1009
vendor = strdup(val);
usr.sbin/dhcpd/confpars.c
1012
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1015
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1018
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
102
token = next_token(&val, cfile); /* Clear the peek buffer */
usr.sbin/dhcpd/confpars.c
1048
val = vendor;
usr.sbin/dhcpd/confpars.c
1054
(unsigned char *)val, 0);
usr.sbin/dhcpd/confpars.c
1058
if (val == vendor)
usr.sbin/dhcpd/confpars.c
1059
parse_warn("no option named %s", val);
usr.sbin/dhcpd/confpars.c
1062
val, vendor);
usr.sbin/dhcpd/confpars.c
1085
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1089
(&val, cfile);
usr.sbin/dhcpd/confpars.c
1099
convert_num(buf, val, 16, 8);
usr.sbin/dhcpd/confpars.c
1102
token = peek_token(&val,
usr.sbin/dhcpd/confpars.c
1106
next_token(&val,
usr.sbin/dhcpd/confpars.c
1110
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1112
tree_const((unsigned char *)val,
usr.sbin/dhcpd/confpars.c
1113
strlen(val)));
usr.sbin/dhcpd/confpars.c
1123
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1132
tree_const((unsigned char *)val,
usr.sbin/dhcpd/confpars.c
1133
strlen(val)));
usr.sbin/dhcpd/confpars.c
1145
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1153
convert_num(buf, val, 0, 32);
usr.sbin/dhcpd/confpars.c
1158
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1166
convert_num(buf, val, 0, 16);
usr.sbin/dhcpd/confpars.c
1171
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1179
convert_num(buf, val, 0, 8);
usr.sbin/dhcpd/confpars.c
118
char *val;
usr.sbin/dhcpd/confpars.c
1183
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1190
if (!strcasecmp(val, "true")
usr.sbin/dhcpd/confpars.c
1191
|| !strcasecmp(val, "on"))
usr.sbin/dhcpd/confpars.c
1193
else if (!strcasecmp(val, "false")
usr.sbin/dhcpd/confpars.c
1194
|| !strcasecmp(val, "off"))
usr.sbin/dhcpd/confpars.c
1227
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1229
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1236
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1265
char *val;
usr.sbin/dhcpd/confpars.c
1287
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1294
strlcpy(tbuf, val, sizeof tbuf);
usr.sbin/dhcpd/confpars.c
1327
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1329
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1330
lease.uid_len = strlen(val);
usr.sbin/dhcpd/confpars.c
1336
memcpy(lease.uid, val, lease.uid_len);
usr.sbin/dhcpd/confpars.c
1360
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1387
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1401
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1417
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
142
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1445
char *val;
usr.sbin/dhcpd/confpars.c
1447
if ((token = peek_token(&val, cfile)) == TOK_DYNAMIC_BOOTP) {
usr.sbin/dhcpd/confpars.c
1448
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1459
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1470
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1507
char *val, *domain;
usr.sbin/dhcpd/confpars.c
1515
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1517
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
1522
domain = strdup(val);
usr.sbin/dhcpd/confpars.c
196
char *val;
usr.sbin/dhcpd/confpars.c
203
switch (next_token(&val, cfile)) {
usr.sbin/dhcpd/confpars.c
342
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
386
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
459
char *val;
usr.sbin/dhcpd/confpars.c
461
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
493
char *val;
usr.sbin/dhcpd/confpars.c
496
next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
497
if (!strcasecmp (val, "true") || !strcasecmp (val, "on"))
usr.sbin/dhcpd/confpars.c
499
else if (!strcasecmp (val, "false") || !strcasecmp (val, "off"))
usr.sbin/dhcpd/confpars.c
518
char *val;
usr.sbin/dhcpd/confpars.c
520
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
536
char *val;
usr.sbin/dhcpd/confpars.c
560
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
562
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
566
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
600
char *val;
usr.sbin/dhcpd/confpars.c
605
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
612
class = add_class (type, val);
usr.sbin/dhcpd/confpars.c
614
fatalx("No memory for class %s.", val);
usr.sbin/dhcpd/confpars.c
625
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
627
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
630
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
647
char *val;
usr.sbin/dhcpd/confpars.c
665
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
667
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
669
if (val[0] == 0) {
usr.sbin/dhcpd/confpars.c
671
val = "<no-name-given>";
usr.sbin/dhcpd/confpars.c
673
name = strdup(val);
usr.sbin/dhcpd/confpars.c
694
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
696
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
707
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
71
char *val;
usr.sbin/dhcpd/confpars.c
724
char *val;
usr.sbin/dhcpd/confpars.c
749
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
777
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
779
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
782
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
823
char *val;
usr.sbin/dhcpd/confpars.c
836
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
838
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
841
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
860
char *val;
usr.sbin/dhcpd/confpars.c
868
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
870
numval = strtonum(val, 0, 32, &errstr);
usr.sbin/dhcpd/confpars.c
872
numval = strtonum(val, 0, UINT8_MAX, &errstr);
usr.sbin/dhcpd/confpars.c
906
char *val;
usr.sbin/dhcpd/confpars.c
917
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
933
val, token);
usr.sbin/dhcpd/confpars.c
939
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
94
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
941
val, token);
usr.sbin/dhcpd/confpars.c
959
char *val;
usr.sbin/dhcpd/confpars.c
970
token = peek_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
972
token = next_token(&val, cfile);
usr.sbin/dhcpd/confpars.c
991
char *val;
usr.sbin/dhcpd/convert.c
104
putShort(unsigned char *obuf, int val)
usr.sbin/dhcpd/convert.c
106
int16_t tmp = htons(val);
usr.sbin/dhcpd/convert.c
80
putULong(unsigned char *obuf, u_int32_t val)
usr.sbin/dhcpd/convert.c
82
u_int32_t tmp = htonl(val);
usr.sbin/dhcpd/convert.c
88
putLong(unsigned char *obuf, int32_t val)
usr.sbin/dhcpd/convert.c
90
int32_t tmp = htonl(val);
usr.sbin/dhcpd/convert.c
96
putUShort(unsigned char *obuf, unsigned int val)
usr.sbin/dhcpd/convert.c
98
u_int16_t tmp = htons(val);
usr.sbin/dhcpd/parse.c
100
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
109
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
112
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
120
char *val;
usr.sbin/dhcpd/parse.c
122
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
137
char *val, *s;
usr.sbin/dhcpd/parse.c
140
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
146
s = strdup(val);
usr.sbin/dhcpd/parse.c
148
fatalx("no memory for string %s.", val);
usr.sbin/dhcpd/parse.c
163
char *val, *s, *t;
usr.sbin/dhcpd/parse.c
170
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
177
s = strdup(val);
usr.sbin/dhcpd/parse.c
186
token = peek_token(&val, cfile);
usr.sbin/dhcpd/parse.c
188
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
219
char *val;
usr.sbin/dhcpd/parse.c
223
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
240
token = peek_token(&val, cfile);
usr.sbin/dhcpd/parse.c
244
if (ether_hostton(val, (struct ether_addr *)e) == 0) {
usr.sbin/dhcpd/parse.c
245
(void)next_token(&val, cfile); /* consume token */
usr.sbin/dhcpd/parse.c
278
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
292
char *val;
usr.sbin/dhcpd/parse.c
295
next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
297
value = strtonum(val, 0, UINT32_MAX, &errstr);
usr.sbin/dhcpd/parse.c
299
parse_warn("lease time is %s: %s", errstr, val);
usr.sbin/dhcpd/parse.c
321
char *val, *t;
usr.sbin/dhcpd/parse.c
335
token = peek_token(&val, cfile);
usr.sbin/dhcpd/parse.c
340
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
346
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
348
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
364
convert_num(s, val, base, size);
usr.sbin/dhcpd/parse.c
367
t = strdup(val);
usr.sbin/dhcpd/parse.c
398
u_int32_t val = 0;
usr.sbin/dhcpd/parse.c
440
val = val * base + tval;
usr.sbin/dhcpd/parse.c
447
if (val > max) {
usr.sbin/dhcpd/parse.c
451
negative ? "-" : "", val, max);
usr.sbin/dhcpd/parse.c
455
negative ? "-" : "", val, max);
usr.sbin/dhcpd/parse.c
459
negative ? "-" : "", val, max);
usr.sbin/dhcpd/parse.c
467
*buf = -(unsigned long)val;
usr.sbin/dhcpd/parse.c
470
putShort(buf, -(unsigned long)val);
usr.sbin/dhcpd/parse.c
473
putLong(buf, -(unsigned long)val);
usr.sbin/dhcpd/parse.c
482
*buf = (u_int8_t)val;
usr.sbin/dhcpd/parse.c
485
putUShort(buf, (u_int16_t)val);
usr.sbin/dhcpd/parse.c
488
putULong(buf, val);
usr.sbin/dhcpd/parse.c
510
char *val, *p;
usr.sbin/dhcpd/parse.c
525
token = next_token(&val, cfile);
usr.sbin/dhcpd/parse.c
526
n = strlcat(timestr, val, sizeof(timestr));
usr.sbin/dhcpd/parse.c
85
char *val;
usr.sbin/dhcpd/parse.c
89
token = peek_token(&val, cfile);
usr.sbin/dhcpd/parse.c
92
token = next_token(&val, cfile);
usr.sbin/dvmrpd/parse.y
520
char *p, *val;
usr.sbin/dvmrpd/parse.y
550
val = symget(buf);
usr.sbin/dvmrpd/parse.y
551
if (val == NULL) {
usr.sbin/dvmrpd/parse.y
555
parsebuf = val;
usr.sbin/dvmrpd/parse.y
76
char *val;
usr.sbin/dvmrpd/parse.y
779
free(sym->val);
usr.sbin/dvmrpd/parse.y
794
symset(const char *nam, const char *val, int persist)
usr.sbin/dvmrpd/parse.y
808
free(sym->val);
usr.sbin/dvmrpd/parse.y
821
sym->val = strdup(val);
usr.sbin/dvmrpd/parse.y
822
if (sym->val == NULL) {
usr.sbin/dvmrpd/parse.y
836
char *sym, *val;
usr.sbin/dvmrpd/parse.y
839
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/dvmrpd/parse.y
841
sym = strndup(s, val - s);
usr.sbin/dvmrpd/parse.y
844
ret = symset(sym, val + 1, 1);
usr.sbin/dvmrpd/parse.y
858
return (sym->val);
usr.sbin/eigrpd/parse.y
1033
free(sym->val);
usr.sbin/eigrpd/parse.y
1054
symset(const char *nam, const char *val, int persist)
usr.sbin/eigrpd/parse.y
1068
free(sym->val);
usr.sbin/eigrpd/parse.y
1081
sym->val = strdup(val);
usr.sbin/eigrpd/parse.y
1082
if (sym->val == NULL) {
usr.sbin/eigrpd/parse.y
1096
char *sym, *val;
usr.sbin/eigrpd/parse.y
1099
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/eigrpd/parse.y
1101
sym = strndup(s, val - s);
usr.sbin/eigrpd/parse.y
1104
ret = symset(sym, val + 1, 1);
usr.sbin/eigrpd/parse.y
1118
return (sym->val);
usr.sbin/eigrpd/parse.y
62
char *val;
usr.sbin/eigrpd/parse.y
764
char *p, *val;
usr.sbin/eigrpd/parse.y
794
val = symget(buf);
usr.sbin/eigrpd/parse.y
795
if (val == NULL) {
usr.sbin/eigrpd/parse.y
799
p = val + strlen(val) - 1;
usr.sbin/eigrpd/parse.y
801
while (p >= val) {
usr.sbin/hostapd/handle.c
118
int offset, min_rate = 0, val;
usr.sbin/hostapd/handle.c
224
val = ((float)rtap.r_rssi / rtap.r_max_rssi) * 100;
usr.sbin/hostapd/handle.c
226
val, frame->f_rssi))
usr.sbin/hostapd/handle.c
230
val = rtap.r_txrate;
usr.sbin/hostapd/handle.c
232
val, frame->f_txrate))
usr.sbin/hostapd/handle.c
236
val = rtap.r_chan;
usr.sbin/hostapd/handle.c
238
val, frame->f_chan))
usr.sbin/hostapd/parse.y
1166
double val;
usr.sbin/hostapd/parse.y
1169
val = strtod($1, &cp);
usr.sbin/hostapd/parse.y
1171
val < 0 || val > 100) {
usr.sbin/hostapd/parse.y
1177
$$ = val;
usr.sbin/hostapd/parse.y
1183
double val;
usr.sbin/hostapd/parse.y
1186
val = strtod($1, &cp) * 2;
usr.sbin/hostapd/parse.y
1188
val != (int)val) {
usr.sbin/hostapd/parse.y
1194
$$ = val;
usr.sbin/hostapd/parse.y
1200
double val;
usr.sbin/hostapd/parse.y
1203
val = strtod($1, &cp);
usr.sbin/hostapd/parse.y
1206
$$ = val * 1000;
usr.sbin/hostapd/parse.y
1208
$$ = val;
usr.sbin/hostapd/parse.y
1451
char *p, *val;
usr.sbin/hostapd/parse.y
1481
val = symget(buf);
usr.sbin/hostapd/parse.y
1482
if (val == NULL) {
usr.sbin/hostapd/parse.y
1486
p = val + strlen(val) - 1;
usr.sbin/hostapd/parse.y
1488
while (p >= val) {
usr.sbin/hostapd/parse.y
1627
symset(const char *nam, const char *val, int persist)
usr.sbin/hostapd/parse.y
1641
free(sym->val);
usr.sbin/hostapd/parse.y
1654
sym->val = strdup(val);
usr.sbin/hostapd/parse.y
1655
if (sym->val == NULL) {
usr.sbin/hostapd/parse.y
1664
hostapd_log(HOSTAPD_LOG_DEBUG, "%s = \"%s\"", sym->nam, sym->val);
usr.sbin/hostapd/parse.y
1672
char *sym, *val;
usr.sbin/hostapd/parse.y
1676
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/hostapd/parse.y
1679
len = strlen(s) - strlen(val) + 1;
usr.sbin/hostapd/parse.y
1685
ret = symset(sym, val + 1, 1);
usr.sbin/hostapd/parse.y
1700
return (sym->val);
usr.sbin/hostapd/parse.y
1816
free(sym->val);
usr.sbin/hostapd/parse.y
92
char *val;
usr.sbin/httpd/httpd.h
144
in_port_t val[2];
usr.sbin/httpd/parse.y
1511
$$.val[0] = htons($2);
usr.sbin/httpd/parse.y
1515
int val;
usr.sbin/httpd/parse.y
1517
if ((val = getservice($2)) == -1) {
usr.sbin/httpd/parse.y
1524
$$.val[0] = val;
usr.sbin/httpd/parse.y
1800
char *p, *val;
usr.sbin/httpd/parse.y
1830
val = symget(buf);
usr.sbin/httpd/parse.y
1831
if (val == NULL) {
usr.sbin/httpd/parse.y
1835
p = val + strlen(val) - 1;
usr.sbin/httpd/parse.y
1837
while (p >= val) {
usr.sbin/httpd/parse.y
2063
free(sym->val);
usr.sbin/httpd/parse.y
2112
free(sym->val);
usr.sbin/httpd/parse.y
2147
symset(const char *nam, const char *val, int persist)
usr.sbin/httpd/parse.y
2161
free(sym->val);
usr.sbin/httpd/parse.y
2174
sym->val = strdup(val);
usr.sbin/httpd/parse.y
2175
if (sym->val == NULL) {
usr.sbin/httpd/parse.y
2189
char *sym, *val;
usr.sbin/httpd/parse.y
2192
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/httpd/parse.y
2194
sym = strndup(s, val - s);
usr.sbin/httpd/parse.y
2197
ret = symset(sym, val + 1, 1);
usr.sbin/httpd/parse.y
2211
return (sym->val);
usr.sbin/httpd/parse.y
2662
s_conf->port = h->port.val[0];
usr.sbin/httpd/parse.y
95
char *val;
usr.sbin/httpd/server.c
661
int s = -1, val;
usr.sbin/httpd/server.c
678
val = 1;
usr.sbin/httpd/server.c
679
if (setsockopt(s, SOL_SOCKET, SO_REUSEPORT, &val,
usr.sbin/httpd/server.c
684
val = srv_conf->tcpbufsiz;
usr.sbin/httpd/server.c
686
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
688
val = srv_conf->tcpbufsiz;
usr.sbin/httpd/server.c
690
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
698
val = (int)srv_conf->tcpipttl;
usr.sbin/httpd/server.c
702
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
707
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
713
val = (int)srv_conf->tcpipminttl;
usr.sbin/httpd/server.c
717
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
722
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
733
val = 0;
usr.sbin/httpd/server.c
735
val = 1;
usr.sbin/httpd/server.c
737
&val, sizeof(val)) == -1)
usr.sbin/httpd/server.c
742
val = 0;
usr.sbin/httpd/server.c
744
val = 1;
usr.sbin/httpd/server.c
746
&val, sizeof(val)) == -1)
usr.sbin/httpd/server_fcgi.c
442
const char *val, struct client *clt)
usr.sbin/httpd/server_fcgi.c
447
int val_len = strlen(val);
usr.sbin/httpd/server_fcgi.c
455
val, val_len, p->total_len);
usr.sbin/httpd/server_fcgi.c
488
memcpy(param, val, val_len);
usr.sbin/httpd/server_fcgi.c
749
char *val, *name, *p;
usr.sbin/httpd/server_fcgi.c
759
val = hdr->kv_value;
usr.sbin/httpd/server_fcgi.c
788
ret = fcgi_add_param(param, name, val, clt);
usr.sbin/httpd/server_http.c
1169
server_expand_http(struct client *clt, const char *val, char *buf,
usr.sbin/httpd/server_http.c
1179
if (strlcpy(buf, val, len) >= len)
usr.sbin/httpd/server_http.c
1183
for (p = val; clt->clt_srv_match.sm_nmatch &&
usr.sbin/httpd/server_http.c
1206
if (strstr(val, "$DOCUMENT_URI") != NULL) {
usr.sbin/httpd/server_http.c
1214
if (strstr(val, "$QUERY_STRING_ENC") != NULL) {
usr.sbin/httpd/server_http.c
1227
if (strstr(val, "$QUERY_STRING") != NULL) {
usr.sbin/httpd/server_http.c
1237
if (strstr(val, "$HTTP_HOST") != NULL) {
usr.sbin/httpd/server_http.c
1245
if (strstr(val, "$REMOTE_") != NULL) {
usr.sbin/httpd/server_http.c
1246
if (strstr(val, "$REMOTE_ADDR") != NULL) {
usr.sbin/httpd/server_http.c
1254
if (strstr(val, "$REMOTE_PORT") != NULL) {
usr.sbin/httpd/server_http.c
1261
if (strstr(val, "$REMOTE_USER") != NULL) {
usr.sbin/httpd/server_http.c
1275
if (strstr(val, "$REQUEST_URI") != NULL) {
usr.sbin/httpd/server_http.c
1292
if (strstr(val, "$REQUEST_SCHEME") != NULL) {
usr.sbin/httpd/server_http.c
1303
if (strstr(val, "$SERVER_") != NULL) {
usr.sbin/httpd/server_http.c
1304
if (strstr(val, "$SERVER_ADDR") != NULL) {
usr.sbin/httpd/server_http.c
1312
if (strstr(val, "$SERVER_PORT") != NULL) {
usr.sbin/httpd/server_http.c
1319
if (strstr(val, "$SERVER_NAME") != NULL) {
usr.sbin/ifstated/parse.y
514
char *p, *val;
usr.sbin/ifstated/parse.y
544
val = symget(buf);
usr.sbin/ifstated/parse.y
545
if (val == NULL) {
usr.sbin/ifstated/parse.y
549
parsebuf = val;
usr.sbin/ifstated/parse.y
74
char *val;
usr.sbin/ifstated/parse.y
782
free(sym->val);
usr.sbin/ifstated/parse.y
831
symset(const char *nam, const char *val, int persist)
usr.sbin/ifstated/parse.y
845
free(sym->val);
usr.sbin/ifstated/parse.y
858
sym->val = strdup(val);
usr.sbin/ifstated/parse.y
859
if (sym->val == NULL) {
usr.sbin/ifstated/parse.y
873
char *sym, *val;
usr.sbin/ifstated/parse.y
876
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ifstated/parse.y
878
sym = strndup(s, val - s);
usr.sbin/ifstated/parse.y
881
ret = symset(sym, val + 1, 1);
usr.sbin/ifstated/parse.y
895
return (sym->val);
usr.sbin/inetd/inetd.c
305
int val;
usr.sbin/inetd/inetd.c
307
val = strtoul(optarg, &p, 0);
usr.sbin/inetd/inetd.c
308
if (val >= 1 && *p == '\0') {
usr.sbin/inetd/inetd.c
309
toomany = val;
usr.sbin/iscsictl/iscsictl.c
121
val = 1;
usr.sbin/iscsictl/iscsictl.c
125
&val, sizeof(int)) == -1)
usr.sbin/iscsictl/iscsictl.c
80
int ch, poll = 0, val = 0;
usr.sbin/iscsictl/parse.y
499
char *p, *val;
usr.sbin/iscsictl/parse.y
529
val = symget(buf);
usr.sbin/iscsictl/parse.y
530
if (val == NULL) {
usr.sbin/iscsictl/parse.y
534
p = val + strlen(val) - 1;
usr.sbin/iscsictl/parse.y
536
while (p >= val) {
usr.sbin/iscsictl/parse.y
724
free(sym->val);
usr.sbin/iscsictl/parse.y
741
char *sym, *val;
usr.sbin/iscsictl/parse.y
744
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/iscsictl/parse.y
746
sym = strndup(s, val - s);
usr.sbin/iscsictl/parse.y
749
ret = symset(sym, val + 1, 1);
usr.sbin/iscsictl/parse.y
763
return (sym->val);
usr.sbin/iscsictl/parse.y
770
symset(const char *nam, const char *val, int persist)
usr.sbin/iscsictl/parse.y
784
free(sym->val);
usr.sbin/iscsictl/parse.y
797
sym->val = strdup(val);
usr.sbin/iscsictl/parse.y
798
if (sym->val == NULL) {
usr.sbin/iscsictl/parse.y
82
char *val;
usr.sbin/iscsid/pdu.c
194
int val;
usr.sbin/iscsid/pdu.c
197
val = 1;
usr.sbin/iscsid/pdu.c
199
val = 0;
usr.sbin/iscsid/pdu.c
207
return val;
usr.sbin/iscsid/pdu.c
213
int val = 0;
usr.sbin/iscsid/pdu.c
225
val |= DIGEST_NONE;
usr.sbin/iscsid/pdu.c
227
val |= DIGEST_CRC32C;
usr.sbin/iscsid/pdu.c
237
return val;
usr.sbin/ldapctl/ldapctl.c
143
struct btval key, val;
usr.sbin/ldapctl/ldapctl.c
175
bzero(&val, sizeof(val));
usr.sbin/ldapctl/ldapctl.c
192
rc = btree_cursor_get(cursor, &key, &val, BT_NEXT);
usr.sbin/ldapctl/ldapctl.c
195
if ((elm = db2ber(&val, ns->compression_level)) == NULL)
usr.sbin/ldapctl/ldapctl.c
200
btval_reset(&val);
usr.sbin/ldapd/index.c
115
rc = btree_txn_put(NULL, ns->indx_txn, &key, &val,
usr.sbin/ldapd/index.c
163
struct btval key, val;
usr.sbin/ldapd/index.c
166
memset(&val, 0, sizeof(val));
usr.sbin/ldapd/index.c
176
rc = btree_txn_put(NULL, ns->indx_txn, &key, &val, BT_NOOVERWRITE);
usr.sbin/ldapd/index.c
91
struct btval key, val;
usr.sbin/ldapd/index.c
99
memset(&val, 0, sizeof(val));
usr.sbin/ldapd/ldapd.h
403
struct ber_element *root, struct btval *val);
usr.sbin/ldapd/ldapd.h
405
struct btval *val);
usr.sbin/ldapd/ldapd.h
476
int ber2db(struct ber_element *root, struct btval *val,
usr.sbin/ldapd/ldapd.h
478
struct ber_element *db2ber(struct btval *val, int compression_level);
usr.sbin/ldapd/namespace.c
259
static struct btval val;
usr.sbin/ldapd/namespace.c
267
memset(&val, 0, sizeof(val));
usr.sbin/ldapd/namespace.c
272
if (btree_txn_get(ns->data_db, ns->data_txn, &key, &val) != 0) {
usr.sbin/ldapd/namespace.c
284
return &val;
usr.sbin/ldapd/namespace.c
291
struct btval *val;
usr.sbin/ldapd/namespace.c
293
if ((val = namespace_find(ns, dn)) == NULL)
usr.sbin/ldapd/namespace.c
296
elm = namespace_db2ber(ns, val);
usr.sbin/ldapd/namespace.c
297
btval_reset(val);
usr.sbin/ldapd/namespace.c
304
struct btval *val;
usr.sbin/ldapd/namespace.c
306
if ((val = namespace_find(ns, dn)) == NULL)
usr.sbin/ldapd/namespace.c
308
btval_reset(val);
usr.sbin/ldapd/namespace.c
314
struct btval *val)
usr.sbin/ldapd/namespace.c
316
return ber2db(root, val, ns->compression_level);
usr.sbin/ldapd/namespace.c
320
namespace_db2ber(struct namespace *ns, struct btval *val)
usr.sbin/ldapd/namespace.c
322
return db2ber(val, ns->compression_level);
usr.sbin/ldapd/namespace.c
330
struct btval key, val;
usr.sbin/ldapd/namespace.c
340
if (namespace_ber2db(ns, root, &val) != 0)
usr.sbin/ldapd/namespace.c
343
rc = btree_txn_put(NULL, ns->data_txn, &key, &val,
usr.sbin/ldapd/namespace.c
361
btval_reset(&val);
usr.sbin/ldapd/parse.y
602
char *p, *val;
usr.sbin/ldapd/parse.y
632
val = symget(buf);
usr.sbin/ldapd/parse.y
633
if (val == NULL) {
usr.sbin/ldapd/parse.y
637
p = val + strlen(val) - 1;
usr.sbin/ldapd/parse.y
639
while (p >= val) {
usr.sbin/ldapd/parse.y
869
free(sym->val);
usr.sbin/ldapd/parse.y
879
symset(const char *nam, const char *val, int persist)
usr.sbin/ldapd/parse.y
893
free(sym->val);
usr.sbin/ldapd/parse.y
906
sym->val = strdup(val);
usr.sbin/ldapd/parse.y
907
if (sym->val == NULL) {
usr.sbin/ldapd/parse.y
921
char *sym, *val;
usr.sbin/ldapd/parse.y
924
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ldapd/parse.y
926
sym = strndup(s, val - s);
usr.sbin/ldapd/parse.y
929
ret = symset(sym, val + 1, 1);
usr.sbin/ldapd/parse.y
94
char *val;
usr.sbin/ldapd/parse.y
943
return (sym->val);
usr.sbin/ldapd/search.c
218
check_search_entry(struct btval *key, struct btval *val, struct search *search)
usr.sbin/ldapd/search.c
244
if ((elm = namespace_db2ber(search->ns, val)) == NULL) {
usr.sbin/ldapd/search.c
302
struct btval key, ikey, val;
usr.sbin/ldapd/search.c
307
memset(&val, 0, sizeof(val));
usr.sbin/ldapd/search.c
342
rc = btree_cursor_get(search->cursor, &key, &val, op);
usr.sbin/ldapd/search.c
352
btval_reset(&val);
usr.sbin/ldapd/search.c
387
btval_reset(&val);
usr.sbin/ldapd/search.c
415
rc = btree_txn_get(NULL, search->data_txn, &key, &val);
usr.sbin/ldapd/search.c
435
btval_reset(&val);
usr.sbin/ldapd/search.c
446
rc = check_search_entry(&key, &val, search);
usr.sbin/ldapd/search.c
447
btval_reset(&val);
usr.sbin/ldapd/search.c
493
struct ber_element *root, *elm, *key, *val;
usr.sbin/ldapd/search.c
501
val = ober_add_set(key);
usr.sbin/ldapd/search.c
502
ober_add_string(val, "top");
usr.sbin/ldapd/search.c
506
val = ober_add_set(key);
usr.sbin/ldapd/search.c
507
ober_add_string(val, "3");
usr.sbin/ldapd/search.c
511
val = ober_add_set(key);
usr.sbin/ldapd/search.c
513
val = ober_add_string(val, ns->suffix);
usr.sbin/ldapd/search.c
517
val = ober_add_set(key);
usr.sbin/ldapd/search.c
518
ober_add_string(val, "1.3.6.1.4.1.1466.20037"); /* StartTLS */
usr.sbin/ldapd/search.c
522
val = ober_add_set(key);
usr.sbin/ldapd/search.c
524
ober_add_string(val, "1.3.6.1.4.1.4203.1.5.1");
usr.sbin/ldapd/search.c
528
val = ober_add_set(key);
usr.sbin/ldapd/search.c
529
ober_add_string(val, "cn=schema");
usr.sbin/ldapd/search.c
534
val = ober_add_set(key);
usr.sbin/ldapd/search.c
535
ober_add_string(val, "PLAIN");
usr.sbin/ldapd/search.c
549
struct ber_element *root, *elm, *key, *val;
usr.sbin/ldapd/search.c
560
val = ober_add_set(key);
usr.sbin/ldapd/search.c
561
val = ober_add_string(val, "top");
usr.sbin/ldapd/search.c
562
ober_add_string(val, "subschema");
usr.sbin/ldapd/search.c
566
val = ober_add_set(key);
usr.sbin/ldapd/search.c
567
ober_add_string(val, ldap_strftime(stats.started_at));
usr.sbin/ldapd/search.c
571
val = ober_add_set(key);
usr.sbin/ldapd/search.c
572
ober_add_string(val, ldap_strftime(stats.started_at));
usr.sbin/ldapd/search.c
576
val = ober_add_set(key);
usr.sbin/ldapd/search.c
577
ober_add_string(val, "cn=schema");
usr.sbin/ldapd/search.c
582
val = ober_add_set(key);
usr.sbin/ldapd/search.c
589
val = ober_add_string(val, buf);
usr.sbin/ldapd/search.c
596
val = ober_add_set(key);
usr.sbin/ldapd/search.c
603
val = ober_add_string(val, buf);
usr.sbin/ldapd/search.c
610
val = ober_add_set(key);
usr.sbin/ldapd/search.c
618
val = ober_add_string(val, buf);
usr.sbin/ldapd/search.c
960
struct btval key, val;
usr.sbin/ldapd/search.c
963
memset(&val, 0, sizeof(val));
usr.sbin/ldapd/search.c
967
if (btree_txn_get(NULL, search->data_txn, &key, &val) == 0) {
usr.sbin/ldapd/search.c
968
check_search_entry(&key, &val, search);
usr.sbin/ldapd/search.c
969
btval_reset(&val);
usr.sbin/ldapd/util.c
105
ber2db(struct ber_element *root, struct btval *val, int compression_level)
usr.sbin/ldapd/util.c
114
memset(val, 0, sizeof(*val));
usr.sbin/ldapd/util.c
123
val->size = compressBound(len);
usr.sbin/ldapd/util.c
124
val->data = malloc(val->size + sizeof(uint32_t));
usr.sbin/ldapd/util.c
125
if (val->data == NULL) {
usr.sbin/ldapd/util.c
126
log_warn("malloc(%zu)", val->size + sizeof(uint32_t));
usr.sbin/ldapd/util.c
130
dest = (char *)val->data + sizeof(uint32_t);
usr.sbin/ldapd/util.c
131
destlen = val->size - sizeof(uint32_t);
usr.sbin/ldapd/util.c
135
free(val->data);
usr.sbin/ldapd/util.c
142
*(uint32_t *)val->data = len;
usr.sbin/ldapd/util.c
143
val->size = destlen + sizeof(uint32_t);
usr.sbin/ldapd/util.c
144
val->free_data = 1;
usr.sbin/ldapd/util.c
146
val->data = buf;
usr.sbin/ldapd/util.c
147
val->size = len;
usr.sbin/ldapd/util.c
148
val->free_data = 1; /* XXX: take over internal br_wbuf */
usr.sbin/ldapd/util.c
158
db2ber(struct btval *val, int compression_level)
usr.sbin/ldapd/util.c
168
assert(val != NULL);
usr.sbin/ldapd/util.c
173
if (val->size < sizeof(uint32_t))
usr.sbin/ldapd/util.c
176
len = *(uint32_t *)val->data;
usr.sbin/ldapd/util.c
182
src = (char *)val->data + sizeof(uint32_t);
usr.sbin/ldapd/util.c
183
srclen = val->size - sizeof(uint32_t);
usr.sbin/ldapd/util.c
192
val->size, len);
usr.sbin/ldapd/util.c
199
ober_set_readbuf(&ber, val->data, val->size);
usr.sbin/ldapd/validate.c
55
char *val;
usr.sbin/ldapd/validate.c
68
if (ober_get_string(elm, &val) == -1) {
usr.sbin/ldapd/validate.c
80
!at->syntax->is_valid(conf->schema, val, elm->be_len)) {
usr.sbin/ldapd/validate.c
83
log_debug("value: [%.*s]", (int)elm->be_len, val);
usr.sbin/ldomctl/mdesc.c
187
uint64_t val)
usr.sbin/ldomctl/mdesc.c
193
prop->d.val = val;
usr.sbin/ldomctl/mdesc.c
249
uint64_t *val)
usr.sbin/ldomctl/mdesc.c
257
*val = prop->d.val;
usr.sbin/ldomctl/mdesc.c
263
uint64_t val)
usr.sbin/ldomctl/mdesc.c
271
prop->d.val = val;
usr.sbin/ldomctl/mdesc.c
467
md_add_prop_val(md, node, str, betoh64(mde->d.val));
usr.sbin/ldomctl/mdesc.c
490
prop->d.arc.index = betoh64(mde->d.val);
usr.sbin/ldomctl/mdesc.c
565
mde->d.val = htobe64(TAILQ_NEXT(node, link)->index);
usr.sbin/ldomctl/mdesc.c
567
mde->d.val = htobe64(index);
usr.sbin/ldomctl/mdesc.c
576
mde->d.val = htobe64(prop->d.val);
usr.sbin/ldomctl/mdesc.c
586
mde->d.val =
usr.sbin/ldomctl/mdesc.h
53
uint64_t val;
usr.sbin/ldomctl/mdesc.h
75
uint64_t val;
usr.sbin/ldpd/parse.y
1078
char *p, *val;
usr.sbin/ldpd/parse.y
1108
val = symget(buf);
usr.sbin/ldpd/parse.y
1109
if (val == NULL) {
usr.sbin/ldpd/parse.y
1113
p = val + strlen(val) - 1;
usr.sbin/ldpd/parse.y
1115
while (p >= val) {
usr.sbin/ldpd/parse.y
1341
free(sym->val);
usr.sbin/ldpd/parse.y
1368
symset(const char *nam, const char *val, int persist)
usr.sbin/ldpd/parse.y
1382
free(sym->val);
usr.sbin/ldpd/parse.y
1395
sym->val = strdup(val);
usr.sbin/ldpd/parse.y
1396
if (sym->val == NULL) {
usr.sbin/ldpd/parse.y
1410
char *sym, *val;
usr.sbin/ldpd/parse.y
1413
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ldpd/parse.y
1415
sym = strndup(s, val - s);
usr.sbin/ldpd/parse.y
1418
ret = symset(sym, val + 1, 1);
usr.sbin/ldpd/parse.y
1432
return (sym->val);
usr.sbin/ldpd/parse.y
64
char *val;
usr.sbin/lpd/lp_stty.c
491
char **argv, **ap, **ep, *p, *val;
usr.sbin/lpd/lp_stty.c
521
while ((val = strsep(&p, " \t,")) != NULL) {
usr.sbin/lpd/lp_stty.c
522
if ((*ap++ = strdup(val)) == NULL)
usr.sbin/lpd/parse.y
374
char *p, *val;
usr.sbin/lpd/parse.y
404
val = symget(buf);
usr.sbin/lpd/parse.y
405
if (val == NULL) {
usr.sbin/lpd/parse.y
409
parsebuf = val;
usr.sbin/lpd/parse.y
627
free(sym->val);
usr.sbin/lpd/parse.y
642
symset(const char *nam, const char *val, int persist)
usr.sbin/lpd/parse.y
656
free(sym->val);
usr.sbin/lpd/parse.y
669
sym->val = strdup(val);
usr.sbin/lpd/parse.y
670
if (sym->val == NULL) {
usr.sbin/lpd/parse.y
684
char *sym, *val;
usr.sbin/lpd/parse.y
687
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/lpd/parse.y
689
sym = strndup(s, val - s);
usr.sbin/lpd/parse.y
692
ret = symset(sym, val + 1, 1);
usr.sbin/lpd/parse.y
706
return (sym->val);
usr.sbin/lpd/parse.y
77
char *val;
usr.sbin/lpr/lpd/printjob.c
1523
char **argv, **ap, **ep, *p, *val;
usr.sbin/lpr/lpd/printjob.c
1556
while ((val = strsep(&p, " \t,")) != NULL) {
usr.sbin/lpr/lpd/printjob.c
1557
if ((*ap++ = strdup(val)) == NULL) {
usr.sbin/makefs/cd9660.c
289
cd9660_arguments_set_string(const char *val, const char *fieldtitle,
usr.sbin/makefs/cd9660.c
295
if (val == NULL)
usr.sbin/makefs/cd9660.c
297
else if ((len = strlen(val)) <= length) {
usr.sbin/makefs/cd9660.c
299
test = cd9660_valid_d_chars(val);
usr.sbin/makefs/cd9660.c
301
test = cd9660_valid_a_chars(val);
usr.sbin/makefs/cd9660.c
303
memcpy(dest, val, len);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
485
uint8_t val;
usr.sbin/makefs/cd9660/cd9660_eltorito.c
491
val = 0x80; /* Bootable */
usr.sbin/makefs/cd9660/cd9660_eltorito.c
492
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
494
val = 0xff; /* CHS begin */
usr.sbin/makefs/cd9660/cd9660_eltorito.c
495
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
496
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
497
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
499
val = type; /* Part type */
usr.sbin/makefs/cd9660/cd9660_eltorito.c
500
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
502
val = 0xff; /* CHS end */
usr.sbin/makefs/cd9660/cd9660_eltorito.c
503
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
504
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/cd9660/cd9660_eltorito.c
505
fwrite(&val, sizeof(val), 1, fd);
usr.sbin/makefs/ffs/mkfs.c
803
ilog2(int val)
usr.sbin/makefs/ffs/mkfs.c
808
if (1 << n == val)
usr.sbin/makefs/ffs/mkfs.c
810
errx(1, "%s: %d is not a power of 2", __func__, val);
usr.sbin/makefs/makefs.c
221
char *var, *val;
usr.sbin/makefs/makefs.c
227
for (val = var; *val; val++)
usr.sbin/makefs/makefs.c
228
if (*val == '=') {
usr.sbin/makefs/makefs.c
229
*val++ = '\0';
usr.sbin/makefs/makefs.c
232
retval = set_option_var(options, var, val, buf, len);
usr.sbin/makefs/makefs.c
238
set_option_var(const option_t *options, const char *var, const char *val,
usr.sbin/makefs/makefs.c
245
if (!*val) { \
usr.sbin/makefs/makefs.c
249
*(type *)options[i].value = (type)strsuftoll(options[i].name, val, \
usr.sbin/makefs/makefs.c
260
strlcpy((void *)options[i].value, val, (size_t)
usr.sbin/makefs/makefs.c
264
s = estrdup(val);
usr.sbin/makefs/makefs.c
270
strlcpy(buf, val, len);
usr.sbin/makefs/makefs.c
282
val);
usr.sbin/makefs/makefs.c
330
strsuftoll(const char *desc, const char *val, long long min, long long max)
usr.sbin/makefs/makefs.c
334
if (scan_scaled((char *)val, &res) == -1)
usr.sbin/makefs/msdos/mkfs_msdos.c
844
ckgeom(const char *fname, u_int val, const char *msg)
usr.sbin/makefs/msdos/mkfs_msdos.c
846
if (!val) {
usr.sbin/makefs/msdos/mkfs_msdos.c
850
if (val > MAXU16) {
usr.sbin/memconfig/memconfig.c
187
if (((1<<j) & mrd[i].mr_flags) & attrnames[k].val) {
usr.sbin/memconfig/memconfig.c
246
mrd.mr_flags |= attrnames[i].val;
usr.sbin/memconfig/memconfig.c
44
int val;
usr.sbin/mopd/common/nma.c
192
if (current->val == devno)
usr.sbin/mopd/common/nma.c
208
if (current->val == devno)
usr.sbin/mopd/common/nma.c
31
int val;
usr.sbin/mtree/compare.c
227
} else if (crc(fd, &val, &len)) {
usr.sbin/mtree/compare.c
235
if (s->cksum != val) {
usr.sbin/mtree/compare.c
238
tab, s->cksum, val);
usr.sbin/mtree/compare.c
77
u_int32_t len, val;
usr.sbin/mtree/create.c
130
u_int32_t len, val;
usr.sbin/mtree/create.c
196
crc(fd, &val, &len))
usr.sbin/mtree/create.c
199
output(indent, &offset, "cksum=%u", val);
usr.sbin/mtree/misc.c
46
u_int val; /* value */
usr.sbin/mtree/misc.c
89
return (k->val);
usr.sbin/mtree/spec.c
171
char *kw, *val = NULL;
usr.sbin/mtree/spec.c
180
if (value && (val = strtok(NULL, " \t\n")) == NULL)
usr.sbin/mtree/spec.c
184
ip->cksum = strtoul(val, &ep, 10);
usr.sbin/mtree/spec.c
186
error("invalid checksum %s", val);
usr.sbin/mtree/spec.c
189
ip->md5digest = strdup(val);
usr.sbin/mtree/spec.c
194
if (!strcmp(val, "none")) {
usr.sbin/mtree/spec.c
198
if (strtofflags(&val, &fset, &fclr))
usr.sbin/mtree/spec.c
203
ip->st_gid = strtoul(val, &ep, 10);
usr.sbin/mtree/spec.c
205
error("invalid gid %s", val);
usr.sbin/mtree/spec.c
208
if (gid_from_group(val, &ip->st_gid) == -1)
usr.sbin/mtree/spec.c
209
error("unknown group %s", val);
usr.sbin/mtree/spec.c
215
if ((m = setmode(val)) == NULL)
usr.sbin/mtree/spec.c
216
error("invalid file mode %s", val);
usr.sbin/mtree/spec.c
221
ip->st_nlink = strtoul(val, &ep, 10);
usr.sbin/mtree/spec.c
223
error("invalid link count %s", val);
usr.sbin/mtree/spec.c
226
ip->rmd160digest = strdup(val);
usr.sbin/mtree/spec.c
231
ip->sha1digest = strdup(val);
usr.sbin/mtree/spec.c
236
ip->sha256digest = strdup(val);
usr.sbin/mtree/spec.c
241
ip->st_size = strtoll(val, &ep, 10);
usr.sbin/mtree/spec.c
243
error("invalid size %s", val);
usr.sbin/mtree/spec.c
246
len = strlen(val) + 1;
usr.sbin/mtree/spec.c
249
if (strunvis(ip->slink, val) == -1) {
usr.sbin/mtree/spec.c
251
"mtree: filename (%s) encoded incorrectly\n", val);
usr.sbin/mtree/spec.c
252
strlcpy(ip->slink, val, len);
usr.sbin/mtree/spec.c
256
ip->st_mtim.tv_sec = strtoull(val, &ep, 10);
usr.sbin/mtree/spec.c
258
error("invalid time %s", val);
usr.sbin/mtree/spec.c
259
val = ep + 1;
usr.sbin/mtree/spec.c
260
ip->st_mtim.tv_nsec = strtoul(val, &ep, 10);
usr.sbin/mtree/spec.c
262
error("invalid time %s", val);
usr.sbin/mtree/spec.c
265
switch(*val) {
usr.sbin/mtree/spec.c
267
if (!strcmp(val, "block"))
usr.sbin/mtree/spec.c
271
if (!strcmp(val, "char"))
usr.sbin/mtree/spec.c
275
if (!strcmp(val, "dir"))
usr.sbin/mtree/spec.c
279
if (!strcmp(val, "file"))
usr.sbin/mtree/spec.c
281
if (!strcmp(val, "fifo"))
usr.sbin/mtree/spec.c
285
if (!strcmp(val, "link"))
usr.sbin/mtree/spec.c
289
if (!strcmp(val, "socket"))
usr.sbin/mtree/spec.c
293
error("unknown file type %s", val);
usr.sbin/mtree/spec.c
297
ip->st_uid = strtoul(val, &ep, 10);
usr.sbin/mtree/spec.c
299
error("invalid uid %s", val);
usr.sbin/mtree/spec.c
302
if (uid_from_user(val, &ip->st_uid) == -1)
usr.sbin/mtree/spec.c
303
error("unknown user %s", val);
usr.sbin/npppctl/npppctl.c
490
humanize_bytes(double val, char *buf, int lbuf)
usr.sbin/npppctl/npppctl.c
495
if (val >= 1000 * 1024 * 1024)
usr.sbin/npppctl/npppctl.c
497
(double)val / (1024 * 1024 * 1024));
usr.sbin/npppctl/npppctl.c
498
else if (val >= 1000 * 1024)
usr.sbin/npppctl/npppctl.c
499
snprintf(buf, lbuf, " (%.1f MB)", (double)val / (1024 * 1024));
usr.sbin/npppctl/npppctl.c
500
else if (val >= 1000)
usr.sbin/npppctl/npppctl.c
501
snprintf(buf, lbuf, " (%.1f KB)", (double)val / 1024);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1424
const char *val;
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1460
if ((val = L2TP_CTRL_CONF(_this)->hostname) == NULL) {
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1462
val = hbuf;
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1464
len = strlen(val);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1465
memcpy(avp->attr_value, val, len);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1494
if ((val = L2TP_CTRL_CONF(_this)->vendor_name) != NULL) {
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1499
len = strlen(val);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1500
memcpy(avp->attr_value, val, len);
usr.sbin/npppd/l2tp/l2tp_subr.h
68
avp_set_val16(struct l2tp_avp *avp, uint16_t val)
usr.sbin/npppd/l2tp/l2tp_subr.h
70
avp->attr_value[0] = val >> 8;
usr.sbin/npppd/l2tp/l2tp_subr.h
71
avp->attr_value[1] = val & 0xff;
usr.sbin/npppd/l2tp/l2tp_subr.h
75
avp_set_val32(struct l2tp_avp *avp, uint32_t val)
usr.sbin/npppd/l2tp/l2tp_subr.h
77
avp->attr_value[0] = val >> 24;
usr.sbin/npppd/l2tp/l2tp_subr.h
78
avp->attr_value[1] = val >> 16;
usr.sbin/npppd/l2tp/l2tp_subr.h
79
avp->attr_value[2] = val >> 8;
usr.sbin/npppd/l2tp/l2tp_subr.h
80
avp->attr_value[3] = val & 0xff;
usr.sbin/npppd/npppd/chap.c
259
u_char *pktp1, *val, namebuf[MAX_USERNAME_LENGTH];
usr.sbin/npppd/npppd/chap.c
307
val = pktp1;
usr.sbin/npppd/npppd/chap.c
346
chap_authenticate(_this, val, lval);
usr.sbin/npppd/pptp/pptp_ctrl.c
721
const char *val;
usr.sbin/npppd/pptp/pptp_ctrl.c
750
if ((val = PPTP_CTRL_CONF(_this)->hostname) == NULL)
usr.sbin/npppd/pptp/pptp_ctrl.c
751
val = "";
usr.sbin/npppd/pptp/pptp_ctrl.c
752
strlcpy(scc->host_name, val, sizeof(scc->host_name));
usr.sbin/npppd/pptp/pptp_ctrl.c
756
val = PPTPD_DEFAULT_VENDOR_NAME;
usr.sbin/npppd/pptp/pptp_ctrl.c
757
strlcpy(scc->vendor_string, val, sizeof(scc->vendor_string));
usr.sbin/nsd/difffile.c
31
write_64(FILE *out, uint64_t val)
usr.sbin/nsd/difffile.c
33
return write_data(out, &val, sizeof(val));
usr.sbin/nsd/difffile.c
37
write_32(FILE *out, uint32_t val)
usr.sbin/nsd/difffile.c
39
val = htonl(val);
usr.sbin/nsd/difffile.c
40
return write_data(out, &val, sizeof(val));
usr.sbin/nsd/difffile.c
44
write_8(FILE *out, uint8_t val)
usr.sbin/nsd/difffile.c
46
return write_data(out, &val, sizeof(val));
usr.sbin/nsd/dname.c
218
int val = (hexdigit_to_int(s[1]) * 100 +
usr.sbin/nsd/dname.c
221
if (0 <= val && val <= 255) {
usr.sbin/nsd/dname.c
223
*p = val;
usr.sbin/nsd/ixfrcreate.c
21
static int spool_u16(FILE* out, uint16_t val)
usr.sbin/nsd/ixfrcreate.c
23
if(!fwrite(&val, sizeof(val), 1, out)) {
usr.sbin/nsd/ixfrcreate.c
236
static int read_spool_u16(FILE* spool, uint16_t* val)
usr.sbin/nsd/ixfrcreate.c
238
if(fread(val, sizeof(*val), 1, spool) < 1)
usr.sbin/nsd/ixfrcreate.c
244
static int read_spool_u32(FILE* spool, uint32_t* val)
usr.sbin/nsd/ixfrcreate.c
246
if(fread(val, sizeof(*val), 1, spool) < 1)
usr.sbin/nsd/ixfrcreate.c
30
static int spool_u32(FILE* out, uint32_t val)
usr.sbin/nsd/ixfrcreate.c
32
if(!fwrite(&val, sizeof(val), 1, out)) {
usr.sbin/nsd/remote.c
1196
int val = atoi(str);
usr.sbin/nsd/remote.c
1201
if(val == 0 && strcmp(str, "0") != 0) {
usr.sbin/nsd/remote.c
1205
verbosity = val;
usr.sbin/nsd/remote.c
1207
xfrd->last_task, val);
usr.sbin/nsd/simdzone/src/generic/ip6.h
105
uint32_t val;
usr.sbin/nsd/simdzone/src/generic/ip6.h
118
val = 0;
usr.sbin/nsd/simdzone/src/generic/ip6.h
125
val <<= 4;
usr.sbin/nsd/simdzone/src/generic/ip6.h
126
val |= (pch - xdigits);
usr.sbin/nsd/simdzone/src/generic/ip6.h
127
if (val > 0xffff)
usr.sbin/nsd/simdzone/src/generic/ip6.h
142
*tp++ = (uint8_t) (val >> 8) & 0xff;
usr.sbin/nsd/simdzone/src/generic/ip6.h
143
*tp++ = (uint8_t) val & 0xff;
usr.sbin/nsd/simdzone/src/generic/ip6.h
145
val = 0;
usr.sbin/nsd/simdzone/src/generic/ip6.h
160
*tp++ = (uint8_t) (val >> 8) & 0xff;
usr.sbin/nsd/simdzone/src/generic/ip6.h
161
*tp++ = (uint8_t) val & 0xff;
usr.sbin/ntpd/client.c
130
int val;
usr.sbin/ntpd/client.c
184
val = IPTOS_LOWDELAY;
usr.sbin/ntpd/client.c
186
IPPROTO_IP, IP_TOS, &val, sizeof(val)) == -1)
usr.sbin/ntpd/client.c
188
val = 1;
usr.sbin/ntpd/client.c
190
&val, sizeof(val)) == -1)
usr.sbin/ntpd/constraint.c
886
constraint_check(double val)
usr.sbin/ntpd/constraint.c
899
diff = fabs(val - gettime_from_timeval(&tv));
usr.sbin/ocspcheck/http.c
464
rc = sscanf(st->val, "%*s %u %*s", &code);
usr.sbin/ocspcheck/http.c
547
h[hsz++].val = cp;
usr.sbin/ocspcheck/http.c
561
h[hsz++].val = ccp;
usr.sbin/ocspcheck/http.c
772
warnx("head: [%s]=[%s]", httph[i].key, httph[i].val);
usr.sbin/ocspcheck/http.h
43
const char *val;
usr.sbin/ocspcheck/ocspcheck.c
684
dspew(" [%s]=[%s]\n", hget->head[i].key, hget->head[i].val);
usr.sbin/ospf6d/parse.y
1070
free(sym->val);
usr.sbin/ospf6d/parse.y
1091
symset(const char *nam, const char *val, int persist)
usr.sbin/ospf6d/parse.y
1105
free(sym->val);
usr.sbin/ospf6d/parse.y
1118
sym->val = strdup(val);
usr.sbin/ospf6d/parse.y
1119
if (sym->val == NULL) {
usr.sbin/ospf6d/parse.y
1133
char *sym, *val;
usr.sbin/ospf6d/parse.y
1136
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ospf6d/parse.y
1138
sym = strndup(s, val - s);
usr.sbin/ospf6d/parse.y
1141
ret = symset(sym, val + 1, 1);
usr.sbin/ospf6d/parse.y
1155
return (sym->val);
usr.sbin/ospf6d/parse.y
794
char *p, *val;
usr.sbin/ospf6d/parse.y
82
char *val;
usr.sbin/ospf6d/parse.y
824
val = symget(buf);
usr.sbin/ospf6d/parse.y
825
if (val == NULL) {
usr.sbin/ospf6d/parse.y
829
p = val + strlen(val) - 1;
usr.sbin/ospf6d/parse.y
831
while (p >= val) {
usr.sbin/ospfd/parse.y
1013
val = symget(buf);
usr.sbin/ospfd/parse.y
1014
if (val == NULL) {
usr.sbin/ospfd/parse.y
1018
p = val + strlen(val) - 1;
usr.sbin/ospfd/parse.y
1020
while (p >= val) {
usr.sbin/ospfd/parse.y
1261
free(sym->val);
usr.sbin/ospfd/parse.y
1282
symset(const char *nam, const char *val, int persist)
usr.sbin/ospfd/parse.y
1296
free(sym->val);
usr.sbin/ospfd/parse.y
1309
sym->val = strdup(val);
usr.sbin/ospfd/parse.y
1310
if (sym->val == NULL) {
usr.sbin/ospfd/parse.y
1324
char *sym, *val;
usr.sbin/ospfd/parse.y
1327
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ospfd/parse.y
1329
sym = strndup(s, val - s);
usr.sbin/ospfd/parse.y
1332
ret = symset(sym, val + 1, 1);
usr.sbin/ospfd/parse.y
1346
return (sym->val);
usr.sbin/ospfd/parse.y
80
char *val;
usr.sbin/ospfd/parse.y
983
char *p, *val;
usr.sbin/pcidump/pcidump.c
1081
pci_read(int bus, int dev, int func, u_int32_t reg, u_int32_t *val)
usr.sbin/pcidump/pcidump.c
1097
*val = io.pi_data;
usr.sbin/pcidump/pcidump.c
1103
pci_readmask(int bus, int dev, int func, u_int32_t reg, u_int32_t *val)
usr.sbin/pcidump/pcidump.c
1119
*val = io.pi_data;
usr.sbin/pppd/chat/chat.c
1436
unsigned long val = 0;
usr.sbin/pppd/chat/chat.c
1496
val = -i;
usr.sbin/pppd/chat/chat.c
1498
val = i;
usr.sbin/pppd/chat/chat.c
1502
val = va_arg(args, unsigned int);
usr.sbin/pppd/chat/chat.c
1506
val = va_arg(args, unsigned int);
usr.sbin/pppd/chat/chat.c
1510
val = (unsigned long) va_arg(args, void *);
usr.sbin/pppd/chat/chat.c
1582
*--str = hexchars[val % base];
usr.sbin/pppd/chat/chat.c
1583
val = val / base;
usr.sbin/pppd/chat/chat.c
1584
if (--prec <= 0 && val == 0)
usr.sbin/pppd/ipcp.c
350
#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
usr.sbin/pppd/ipcp.c
356
PUTSHORT(val, ucp); \
usr.sbin/pppd/ipcp.c
415
#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
usr.sbin/pppd/ipcp.c
426
if (cishort != val) \
usr.sbin/pppd/ipcp.c
695
#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
usr.sbin/pppd/ipcp.c
704
if (cishort != val) \
usr.sbin/pppd/lcp.c
1008
#define REJCISHORT(opt, neg, val) \
usr.sbin/pppd/lcp.c
1017
if (cishort != val) \
usr.sbin/pppd/lcp.c
1022
#define REJCICHAP(opt, neg, val, digest) \
usr.sbin/pppd/lcp.c
1032
if (cishort != val || cichar != digest) \
usr.sbin/pppd/lcp.c
1038
#define REJCILONG(opt, neg, val) \
usr.sbin/pppd/lcp.c
1047
if (cilong != val) \
usr.sbin/pppd/lcp.c
1052
#define REJCILQR(opt, neg, val) \
usr.sbin/pppd/lcp.c
1062
if (cishort != PPP_LQR || cilong != val) \
usr.sbin/pppd/lcp.c
1067
#define REJCICBCP(opt, neg, val) \
usr.sbin/pppd/lcp.c
1076
if (cichar != val) \
usr.sbin/pppd/lcp.c
492
#define ADDCISHORT(opt, neg, val) \
usr.sbin/pppd/lcp.c
496
PUTSHORT(val, ucp); \
usr.sbin/pppd/lcp.c
498
#define ADDCICHAP(opt, neg, val, digest) \
usr.sbin/pppd/lcp.c
502
PUTSHORT(val, ucp); \
usr.sbin/pppd/lcp.c
505
#define ADDCILONG(opt, neg, val) \
usr.sbin/pppd/lcp.c
509
PUTLONG(val, ucp); \
usr.sbin/pppd/lcp.c
511
#define ADDCILQR(opt, neg, val) \
usr.sbin/pppd/lcp.c
516
PUTLONG(val, ucp); \
usr.sbin/pppd/lcp.c
518
#define ADDCICHAR(opt, neg, val) \
usr.sbin/pppd/lcp.c
522
PUTCHAR(val, ucp); \
usr.sbin/pppd/lcp.c
574
#define ACKCISHORT(opt, neg, val) \
usr.sbin/pppd/lcp.c
584
if (cishort != val) \
usr.sbin/pppd/lcp.c
587
#define ACKCICHAR(opt, neg, val) \
usr.sbin/pppd/lcp.c
597
if (cichar != val) \
usr.sbin/pppd/lcp.c
600
#define ACKCICHAP(opt, neg, val, digest) \
usr.sbin/pppd/lcp.c
610
if (cishort != val) \
usr.sbin/pppd/lcp.c
616
#define ACKCILONG(opt, neg, val) \
usr.sbin/pppd/lcp.c
626
if (cilong != val) \
usr.sbin/pppd/lcp.c
629
#define ACKCILQR(opt, neg, val) \
usr.sbin/pppd/lcp.c
642
if (cilong != val) \
usr.sbin/pppd/main.c
1351
unsigned long val = 0;
usr.sbin/pppd/main.c
1411
val = -i;
usr.sbin/pppd/main.c
1413
val = i;
usr.sbin/pppd/main.c
1417
val = va_arg(args, unsigned int);
usr.sbin/pppd/main.c
1421
val = va_arg(args, unsigned int);
usr.sbin/pppd/main.c
1425
val = (unsigned long) va_arg(args, void *);
usr.sbin/pppd/main.c
1506
*--str = hexchars[val % base];
usr.sbin/pppd/main.c
1507
val = val / base;
usr.sbin/pppd/main.c
1508
if (--prec <= 0 && val == 0)
usr.sbin/pstat/pstat.c
1017
state[j++] = ttystates[i].val;
usr.sbin/pstat/pstat.c
981
char val;
usr.sbin/rad/parse.y
1012
free(sym->val);
usr.sbin/rad/parse.y
1025
sym->val = strdup(val);
usr.sbin/rad/parse.y
1026
if (sym->val == NULL) {
usr.sbin/rad/parse.y
1040
char *sym, *val;
usr.sbin/rad/parse.y
1043
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/rad/parse.y
1045
sym = strndup(s, val - s);
usr.sbin/rad/parse.y
1048
ret = symset(sym, val + 1, 1);
usr.sbin/rad/parse.y
1062
return (sym->val);
usr.sbin/rad/parse.y
673
char *p, *val;
usr.sbin/rad/parse.y
703
val = symget(buf);
usr.sbin/rad/parse.y
704
if (val == NULL) {
usr.sbin/rad/parse.y
708
p = val + strlen(val) - 1;
usr.sbin/rad/parse.y
710
while (p >= val) {
usr.sbin/rad/parse.y
86
char *val;
usr.sbin/rad/parse.y
928
free(sym->val);
usr.sbin/rad/parse.y
998
symset(const char *nam, const char *val, int persist)
usr.sbin/radiusd/radiusd.c
1646
struct radiusd_module_object *val;
usr.sbin/radiusd/radiusd.c
1677
val = (struct radiusd_module_object *)(buf + bufoff);
usr.sbin/radiusd/radiusd.c
1678
val->size = valsiz;
usr.sbin/radiusd/radiusd.c
1679
memcpy(val + 1, argv[i], vallen);
usr.sbin/radiusd/radiusd_ipcp.c
1458
DBT key, val;
usr.sbin/radiusd/radiusd_ipcp.c
1473
if (db->seq(db, &key, &val, R_CURSOR) == 0) {
usr.sbin/radiusd/radiusd_ipcp.c
1482
record = (struct radiusd_ipcp_db_record *)val.data;
usr.sbin/radiusd/radiusd_ipcp.c
1512
} while (db->seq(db, &key, &val, R_NEXT) == 0);
usr.sbin/radiusd/radiusd_ipcp.c
1523
DBT key, val;
usr.sbin/radiusd/radiusd_ipcp.c
1550
val.data = &record;
usr.sbin/radiusd/radiusd_ipcp.c
1551
val.size = sizeof(record);
usr.sbin/radiusd/radiusd_ipcp.c
1555
db->put(db, &key, &val, 0);
usr.sbin/radiusd/radiusd_ipcp.c
1940
radius_tunnel_type_string(unsigned val, const char *label)
usr.sbin/radiusd/radiusd_ipcp.c
1971
if (tunnel_types[i].constval == val)
usr.sbin/radiusd/radiusd_ipcp.c
1979
radius_terminate_cause_string(unsigned val)
usr.sbin/radiusd/radiusd_ipcp.c
2007
if (terminate_causes[i].constval == val)
usr.sbin/radiusd/radiusd_ipcp.c
2015
radius_error_cause_string(unsigned val)
usr.sbin/radiusd/radiusd_ipcp.c
2059
if (error_causes[i].constval == val)
usr.sbin/radiusd/radiusd_module.c
394
struct radiusd_module_object *val;
usr.sbin/radiusd/radiusd_module.c
412
val = (struct radiusd_module_object *)
usr.sbin/radiusd/radiusd_module.c
414
if (datalen - off < val->size)
usr.sbin/radiusd/radiusd_module.c
416
argv[i] = (char *)(val + 1);
usr.sbin/radiusd/radiusd_module.c
417
off += val->size;
usr.sbin/rbootd/rmp_var.h
147
typedef struct _uword { u_int16_t val[2]; } u_word;
usr.sbin/rbootd/rmp_var.h
150
((w.val[_WORD_HIGHPART] == 0) && (w.val[_WORD_LOWPART] == 0))
usr.sbin/rbootd/rmp_var.h
152
(w).val[_WORD_HIGHPART] = (w).val[_WORD_LOWPART] = 0
usr.sbin/rbootd/rmp_var.h
154
{ (w2).val[_WORD_HIGHPART] = (w1).val[_WORD_HIGHPART]; \
usr.sbin/rbootd/rmp_var.h
155
(w2).val[_WORD_LOWPART] = (w1).val[_WORD_LOWPART]; \
usr.sbin/rbootd/rmp_var.h
158
(i) = (((u_int32_t)ntohs((w).val[_WORD_HIGHPART])) << 16) | ntohs((w).val[_WORD_LOWPART])
usr.sbin/rbootd/rmp_var.h
160
{ (w).val[_WORD_HIGHPART] = htons((u_int16_t) ((i >> 16) & 0xffff)); \
usr.sbin/rbootd/rmp_var.h
161
(w).val[_WORD_LOWPART] = htons((u_int16_t) (i & 0xffff)); \
usr.sbin/relayd/agentx_control.c
1007
oidstr, type, buf, val);
usr.sbin/relayd/agentx_control.c
1017
d = (u_int32_t)val;
usr.sbin/relayd/agentx_control.c
1024
d = (u_int32_t)val;
usr.sbin/relayd/agentx_control.c
1031
d = (u_int32_t)val;
usr.sbin/relayd/agentx_control.c
1038
l = (u_int64_t)val;
usr.sbin/relayd/agentx_control.c
1046
d = (u_int32_t)val;
usr.sbin/relayd/agentx_control.c
999
snmp_element(const char *oidstr, enum snmp_type type, void *buf, int64_t val,
usr.sbin/relayd/check_icmp.c
52
int proto = IPPROTO_ICMP, val;
usr.sbin/relayd/check_icmp.c
58
val = ICMP_RCVBUF_SIZE;
usr.sbin/relayd/check_icmp.c
59
if (setsockopt(cie->s, SOL_SOCKET, SO_RCVBUF, &val, sizeof(val)) == -1)
usr.sbin/relayd/parse.y
2046
nr->rl_conf.port = h->port.val[0];
usr.sbin/relayd/parse.y
2131
rlay->rl_conf.dstport = h->port.val[0];
usr.sbin/relayd/parse.y
2758
char *p, *val;
usr.sbin/relayd/parse.y
2788
val = symget(buf);
usr.sbin/relayd/parse.y
2789
if (val == NULL) {
usr.sbin/relayd/parse.y
2793
p = val + strlen(val) - 1;
usr.sbin/relayd/parse.y
2795
while (p >= val) {
usr.sbin/relayd/parse.y
3017
free(sym->val);
usr.sbin/relayd/parse.y
3070
free(sym->val);
usr.sbin/relayd/parse.y
3158
symset(const char *nam, const char *val, int persist)
usr.sbin/relayd/parse.y
3172
free(sym->val);
usr.sbin/relayd/parse.y
3185
sym->val = strdup(val);
usr.sbin/relayd/parse.y
3186
if (sym->val == NULL) {
usr.sbin/relayd/parse.y
319
$$.val[0] = p;
usr.sbin/relayd/parse.y
320
$$.val[1] = 0;
usr.sbin/relayd/parse.y
3200
char *sym, *val;
usr.sbin/relayd/parse.y
3203
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/relayd/parse.y
3205
sym = strndup(s, val - s);
usr.sbin/relayd/parse.y
3208
ret = symset(sym, val + 1, 1);
usr.sbin/relayd/parse.y
3222
return (sym->val);
usr.sbin/relayd/parse.y
344
$$.val[0] = p[0];
usr.sbin/relayd/parse.y
345
$$.val[1] = p[1];
usr.sbin/relayd/parse.y
353
$$.val[0] = htons($2);
usr.sbin/relayd/parse.y
95
char *val;
usr.sbin/relayd/pfe_filter.c
413
rio.rule.dst.port[0] = address->port.val[0];
usr.sbin/relayd/pfe_filter.c
414
rio.rule.dst.port[1] = address->port.val[1];
usr.sbin/relayd/relay.c
544
int s = -1, val;
usr.sbin/relayd/relay.c
561
val = 1;
usr.sbin/relayd/relay.c
562
if (setsockopt(s, SOL_SOCKET, SO_REUSEPORT, &val,
usr.sbin/relayd/relay.c
567
val = proto->tcpbufsiz;
usr.sbin/relayd/relay.c
569
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
571
val = proto->tcpbufsiz;
usr.sbin/relayd/relay.c
573
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
581
val = (int)proto->tcpipttl;
usr.sbin/relayd/relay.c
585
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
590
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
596
val = (int)proto->tcpipminttl;
usr.sbin/relayd/relay.c
600
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
605
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
616
val = 0;
usr.sbin/relayd/relay.c
618
val = 1;
usr.sbin/relayd/relay.c
620
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay.c
625
val = 0;
usr.sbin/relayd/relay.c
627
val = 1;
usr.sbin/relayd/relay.c
629
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay_http.c
1014
free(val);
usr.sbin/relayd/relay_http.c
1023
char *val, *ptr, *tmpkey = NULL, *tmpval = NULL;
usr.sbin/relayd/relay_http.c
1028
if ((val = strdup(desc->http_query)) == NULL) {
usr.sbin/relayd/relay_http.c
1032
ptr = val;
usr.sbin/relayd/relay_http.c
1062
free(val);
usr.sbin/relayd/relay_http.c
1198
relay_expand_http(struct ctl_relay_event *cre, char *val, char *buf,
usr.sbin/relayd/relay_http.c
1207
if (strlcpy(buf, val, len) >= len)
usr.sbin/relayd/relay_http.c
1210
if (strstr(val, "$HOST") != NULL) {
usr.sbin/relayd/relay_http.c
1225
if (strstr(val, "$REMOTE_") != NULL) {
usr.sbin/relayd/relay_http.c
1226
if (strstr(val, "$REMOTE_ADDR") != NULL) {
usr.sbin/relayd/relay_http.c
1233
if (strstr(val, "$REMOTE_PORT") != NULL) {
usr.sbin/relayd/relay_http.c
1240
if (strstr(val, "$SERVER_") != NULL) {
usr.sbin/relayd/relay_http.c
1241
if (strstr(val, "$SERVER_ADDR") != NULL) {
usr.sbin/relayd/relay_http.c
1249
if (strstr(val, "$SERVER_PORT") != NULL) {
usr.sbin/relayd/relay_http.c
1256
if (strstr(val, "$SERVER_NAME") != NULL) {
usr.sbin/relayd/relay_http.c
1262
if (strstr(val, "$TIMEOUT") != NULL) {
usr.sbin/relayd/relay_http.c
845
char *val, *md = NULL;
usr.sbin/relayd/relay_http.c
849
if (asprintf(&val, "%s%s%s%s",
usr.sbin/relayd/relay_http.c
861
val, strlen(val), NULL)) == NULL) {
usr.sbin/relayd/relay_http.c
869
str = val;
usr.sbin/relayd/relay_http.c
884
free(val);
usr.sbin/relayd/relay_http.c
968
char *val, *ptr, *key, *value;
usr.sbin/relayd/relay_http.c
971
if ((val = strdup(str)) == NULL) {
usr.sbin/relayd/relay_http.c
975
for (ptr = val; ptr != NULL && strlen(ptr);) {
usr.sbin/relayd/relay_udp.c
112
int s = -1, val;
usr.sbin/relayd/relay_udp.c
125
val = proto->tcpbufsiz;
usr.sbin/relayd/relay_udp.c
127
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay_udp.c
129
val = proto->tcpbufsiz;
usr.sbin/relayd/relay_udp.c
131
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay_udp.c
139
val = (int)proto->tcpipttl;
usr.sbin/relayd/relay_udp.c
143
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay_udp.c
148
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay_udp.c
154
val = (int)proto->tcpipminttl;
usr.sbin/relayd/relay_udp.c
158
&val, sizeof(val)) == -1)
usr.sbin/relayd/relay_udp.c
163
&val, sizeof(val)) == -1)
usr.sbin/relayd/relayd.c
852
char *val = NULL, *next, *ptr;
usr.sbin/relayd/relayd.c
866
if ((val = strdup(match->kv_value)) == NULL)
usr.sbin/relayd/relayd.c
868
for (next = ptr = val; ptr != NULL;
usr.sbin/relayd/relayd.c
885
free(val);
usr.sbin/relayd/relayd.h
355
in_port_t val[2];
usr.sbin/ripd/parse.y
555
char *p, *val;
usr.sbin/ripd/parse.y
585
val = symget(buf);
usr.sbin/ripd/parse.y
586
if (val == NULL) {
usr.sbin/ripd/parse.y
590
parsebuf = val;
usr.sbin/ripd/parse.y
74
char *val;
usr.sbin/ripd/parse.y
803
free(sym->val);
usr.sbin/ripd/parse.y
821
symset(const char *nam, const char *val, int persist)
usr.sbin/ripd/parse.y
835
free(sym->val);
usr.sbin/ripd/parse.y
848
sym->val = strdup(val);
usr.sbin/ripd/parse.y
849
if (sym->val == NULL) {
usr.sbin/ripd/parse.y
863
char *sym, *val;
usr.sbin/ripd/parse.y
866
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ripd/parse.y
868
sym = strndup(s, val - s);
usr.sbin/ripd/parse.y
871
ret = symset(sym, val + 1, 1);
usr.sbin/ripd/parse.y
885
return (sym->val);
usr.sbin/rpki-client/ccr.c
224
hash_asn1_item(ASN1_OCTET_STRING *astr, const ASN1_ITEM *it, void *val)
usr.sbin/rpki-client/ccr.c
228
if (!ASN1_item_digest(it, EVP_sha256(), val, hash, NULL))
usr.sbin/rpki-client/ccr.c
237
const ASN1_OCTET_STRING *hash, const ASN1_ITEM *it, void *val)
usr.sbin/rpki-client/ccr.c
245
hash_asn1_item(astr, it, val);
usr.sbin/rpki-client/ometric.c
424
ometric_set_int_value(struct ometric *om, uint64_t val, struct olabels *ol)
usr.sbin/rpki-client/ometric.c
431
ov->value.i = val;
usr.sbin/rpki-client/ometric.c
442
ometric_set_int(struct ometric *om, uint64_t val, struct olabels *ol)
usr.sbin/rpki-client/ometric.c
447
ometric_set_int_value(om, val, ol);
usr.sbin/rpki-client/ometric.c
454
ometric_set_float(struct ometric *om, double val, struct olabels *ol)
usr.sbin/rpki-client/ometric.c
464
ov->value.f = val;
usr.sbin/rpki-client/ometric.c
520
int val;
usr.sbin/rpki-client/ometric.c
527
val = 1;
usr.sbin/rpki-client/ometric.c
529
val = 0;
usr.sbin/rpki-client/ometric.c
533
ometric_set_int_value(om, val, extra);
usr.sbin/rpki-client/ometric.c
543
ometric_set_int_with_labels(struct ometric *om, uint64_t val,
usr.sbin/rpki-client/ometric.c
549
ometric_set_int(om, val, extra);
usr.sbin/rpki-client/ometric.c
554
ometric_set_float_with_labels(struct ometric *om, double val,
usr.sbin/rpki-client/ometric.c
560
ometric_set_float(om, val, extra);
usr.sbin/sasyncd/conf.y
331
yylval.val = v;
usr.sbin/sasyncd/conf.y
59
int val;
usr.sbin/sasyncd/conf.y
71
%token <val> VALUE
usr.sbin/sasyncd/conf.y
72
%type <val> af port mode flushmode ctlmode
usr.sbin/sensorsd/sensorsd.c
773
double val;
usr.sbin/sensorsd/sensorsd.c
784
val = strtod(buf, &p);
usr.sbin/sensorsd/sensorsd.c
793
rval = val * 1000 * 1000 + 273150000;
usr.sbin/sensorsd/sensorsd.c
797
rval = (val * 1000 * 1000 + 459670000) / 9 * 5;
usr.sbin/sensorsd/sensorsd.c
804
rval = val;
usr.sbin/sensorsd/sensorsd.c
810
rval = val * 1000 * 1000;
usr.sbin/sensorsd/sensorsd.c
813
rval = val * 1000.0;
usr.sbin/sensorsd/sensorsd.c
819
rval = val;
usr.sbin/sensorsd/sensorsd.c
830
rval = val * 1000 * 1000;
usr.sbin/sensorsd/sensorsd.c
833
rval = val * 1000 * 1000 * 1000;
usr.sbin/sensorsd/sensorsd.c
837
rval = val * 1000.0;
usr.sbin/slowcgi/slowcgi.c
1159
free(env_entry->val);
usr.sbin/slowcgi/slowcgi.c
770
if ((env_entry->val = calloc(sizeof(char), name_len + val_len +
usr.sbin/slowcgi/slowcgi.c
777
bcopy(buf, env_entry->val, name_len);
usr.sbin/slowcgi/slowcgi.c
781
env_entry->val[name_len] = '\0';
usr.sbin/slowcgi/slowcgi.c
782
if (val_len < PATH_MAX && strcmp(env_entry->val,
usr.sbin/slowcgi/slowcgi.c
786
} else if (val_len < PATH_MAX && strcmp(env_entry->val,
usr.sbin/slowcgi/slowcgi.c
791
env_entry->val[name_len] = '=';
usr.sbin/slowcgi/slowcgi.c
793
bcopy(buf, (env_entry->val) + name_len + 1, val_len);
usr.sbin/slowcgi/slowcgi.c
798
ldebug("env[%d], %s", c->env_count, env_entry->val);
usr.sbin/slowcgi/slowcgi.c
87
char *val;
usr.sbin/slowcgi/slowcgi.c
959
env[i++] = env_entry->val;
usr.sbin/smtpd/control.c
119
if (sz != sizeof(val))
usr.sbin/smtpd/control.c
121
memmove(&val, data, sz);
usr.sbin/smtpd/control.c
123
stat_backend->increment(key, val.u.counter);
usr.sbin/smtpd/control.c
124
control_digest_update(key, val.u.counter, 1);
usr.sbin/smtpd/control.c
132
if (sz != sizeof(val))
usr.sbin/smtpd/control.c
134
memmove(&val, data, sz);
usr.sbin/smtpd/control.c
136
stat_backend->decrement(key, val.u.counter);
usr.sbin/smtpd/control.c
137
control_digest_update(key, val.u.counter, 0);
usr.sbin/smtpd/control.c
145
if (sz != sizeof(val))
usr.sbin/smtpd/control.c
147
memmove(&val, data, sz);
usr.sbin/smtpd/control.c
149
stat_backend->set(key, &val);
usr.sbin/smtpd/control.c
419
struct stat_value val;
usr.sbin/smtpd/control.c
458
if (!stat_backend->iter(&kvp->iter, &key, &val))
usr.sbin/smtpd/control.c
462
kvp->val = val;
usr.sbin/smtpd/control.c
75
struct stat_value val;
usr.sbin/smtpd/envelope.c
114
const char *val, *errstr;
usr.sbin/smtpd/envelope.c
124
val = dict_get(&d, "version");
usr.sbin/smtpd/envelope.c
125
if (val == NULL) {
usr.sbin/smtpd/envelope.c
129
version = strtonum(val, 1, 64, &errstr);
usr.sbin/smtpd/envelope.c
131
log_debug("debug: cannot parse envelope version: %s", val);
usr.sbin/smtpd/makemap.c
250
char *key, *val, *line = NULL;
usr.sbin/smtpd/makemap.c
275
&key, &val, &malformed) != -1) {
usr.sbin/smtpd/makemap.c
289
r = add_mapentry(db, dbputs, key, val, lineno);
usr.sbin/smtpd/makemap.c
312
DBT val;
usr.sbin/smtpd/makemap.c
319
if (db->get(db, &key, &val, 0) == 0) {
usr.sbin/smtpd/makemap.c
325
if (!make_plain(&val, valp))
usr.sbin/smtpd/makemap.c
329
if (!make_aliases(&val, valp))
usr.sbin/smtpd/makemap.c
333
if (db->put(db, &key, &val, 0) == -1) {
usr.sbin/smtpd/makemap.c
340
free(val.data);
usr.sbin/smtpd/makemap.c
353
DBT val;
usr.sbin/smtpd/makemap.c
355
val.data = "<set>";
usr.sbin/smtpd/makemap.c
356
val.size = strlen(val.data) + 1;
usr.sbin/smtpd/makemap.c
362
if (db->get(db, &key, &val, 0) == 0) {
usr.sbin/smtpd/makemap.c
367
if (db->put(db, &key, &val, 0) == -1) {
usr.sbin/smtpd/makemap.c
378
make_plain(DBT *val, char *text)
usr.sbin/smtpd/makemap.c
380
val->data = xstrdup(text);
usr.sbin/smtpd/makemap.c
381
val->size = strlen(text) + 1;
usr.sbin/smtpd/makemap.c
383
return (val->size);
usr.sbin/smtpd/makemap.c
387
make_aliases(DBT *val, char *text)
usr.sbin/smtpd/makemap.c
393
val->data = NULL;
usr.sbin/smtpd/makemap.c
394
val->size = 0;
usr.sbin/smtpd/makemap.c
408
val->data = origtext;
usr.sbin/smtpd/makemap.c
409
val->size = strlen(origtext) + 1;
usr.sbin/smtpd/makemap.c
410
return (val->size);
usr.sbin/smtpd/makemap.c
445
DBT key, val;
usr.sbin/smtpd/makemap.c
453
for (r = db->seq(db, &key, &val, R_FIRST); r == 0;
usr.sbin/smtpd/makemap.c
454
r = db->seq(db, &key, &val, R_NEXT)) {
usr.sbin/smtpd/makemap.c
456
valstr = val.data;
usr.sbin/smtpd/makemap.c
459
if (valstr[val.size - 1] == '\0')
usr.sbin/smtpd/makemap.c
460
val.size--;
usr.sbin/smtpd/makemap.c
462
(int)val.size, valstr);
usr.sbin/smtpd/parse.y
2905
char *p, *val;
usr.sbin/smtpd/parse.y
2935
val = symget(buf);
usr.sbin/smtpd/parse.y
2936
if (val == NULL) {
usr.sbin/smtpd/parse.y
2940
p = val + strlen(val) - 1;
usr.sbin/smtpd/parse.y
2942
while (p >= val) {
usr.sbin/smtpd/parse.y
3178
free(sym->val);
usr.sbin/smtpd/parse.y
3198
symset(const char *nam, const char *val, int persist)
usr.sbin/smtpd/parse.y
3212
free(sym->val);
usr.sbin/smtpd/parse.y
3225
sym->val = strdup(val);
usr.sbin/smtpd/parse.y
3226
if (sym->val == NULL) {
usr.sbin/smtpd/parse.y
3240
char *sym, *val;
usr.sbin/smtpd/parse.y
3243
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/smtpd/parse.y
3245
sym = strndup(s, val - s);
usr.sbin/smtpd/parse.y
3248
ret = symset(sym, val + 1, 1);
usr.sbin/smtpd/parse.y
3262
return (sym->val);
usr.sbin/smtpd/parse.y
81
char *val;
usr.sbin/smtpd/rfc5322.c
108
if (buf_cat(&parser->val, parser->currhdr) == -1)
usr.sbin/smtpd/rfc5322.c
135
if (buf_cat(&parser->val, "\n") == -1 ||
usr.sbin/smtpd/rfc5322.c
136
buf_cat(&parser->val, line) == -1)
usr.sbin/smtpd/rfc5322.c
144
parser->val.buflen = 0;
usr.sbin/smtpd/rfc5322.c
146
res->value = parser->val.buf;
usr.sbin/smtpd/rfc5322.c
44
struct buf val;
usr.sbin/smtpd/rfc5322.c
58
parser->val.bufmax = 65536;
usr.sbin/smtpd/rfc5322.c
67
free(parser->val.buf);
usr.sbin/smtpd/rfc5322.c
78
parser->val.buflen = 0;
usr.sbin/smtpd/smtp_session.c
459
const char *val)
usr.sbin/smtpd/smtp_session.c
473
for (line = val; line; line = end) {
usr.sbin/smtpd/smtpctl.c
836
duration = time(NULL) - kv.val.u.counter;
usr.sbin/smtpd/smtpctl.c
842
switch (kv.val.type) {
usr.sbin/smtpd/smtpctl.c
845
kv.key, kv.val.u.counter);
usr.sbin/smtpd/smtpctl.c
849
kv.key, (int64_t)kv.val.u.timestamp);
usr.sbin/smtpd/smtpctl.c
853
kv.key, (long long)kv.val.u.tv.tv_sec,
usr.sbin/smtpd/smtpctl.c
854
(long long)kv.val.u.tv.tv_usec);
usr.sbin/smtpd/smtpctl.c
859
(long long)kv.val.u.ts.tv_sec * 1000000 +
usr.sbin/smtpd/smtpctl.c
860
kv.val.u.ts.tv_nsec / 1000000,
usr.sbin/smtpd/smtpctl.c
861
kv.val.u.ts.tv_nsec % 1000000);
usr.sbin/smtpd/smtpd.h
941
struct stat_value val;
usr.sbin/smtpd/stat_ramstat.c
103
ramstat_set(const char *name, const struct stat_value *val)
usr.sbin/smtpd/stat_ramstat.c
116
np->value = *val;
usr.sbin/smtpd/stat_ramstat.c
120
ramstat_iter(void **iter, char **name, struct stat_value *val)
usr.sbin/smtpd/stat_ramstat.c
138
*val = np->value;
usr.sbin/smtpd/stat_ramstat.c
67
ramstat_increment(const char *name, size_t val)
usr.sbin/smtpd/stat_ramstat.c
80
name, name, np->value.u.counter, np->value.u.counter + val);
usr.sbin/smtpd/stat_ramstat.c
81
np->value.u.counter += val;
usr.sbin/smtpd/stat_ramstat.c
85
ramstat_decrement(const char *name, size_t val)
usr.sbin/smtpd/stat_ramstat.c
98
name, name, np->value.u.counter, np->value.u.counter - val);
usr.sbin/smtpd/stat_ramstat.c
99
np->value.u.counter -= val;
usr.sbin/smtpd/table.c
296
table_add(struct table *t, const char *key, const char *val)
usr.sbin/smtpd/table.c
301
if (t->t_backend->add(t, key, val) == 0)
usr.sbin/smtpd/table_static.c
188
table_static_add(struct table *table, const char *key, const char *val)
usr.sbin/smtpd/table_static.c
198
table->t_type = val ? T_HASH : T_LIST;
usr.sbin/smtpd/table_static.c
199
else if (table->t_type == T_LIST && val)
usr.sbin/smtpd/table_static.c
201
else if (table->t_type == T_HASH && val == NULL)
usr.sbin/smtpd/table_static.c
210
r = table_static_priv_add(priv, key, val);
usr.sbin/smtpd/table_static.c
83
table_static_priv_add(struct table_static_priv *priv, const char *key, const char *val)
usr.sbin/smtpd/table_static.c
93
if (val) {
usr.sbin/smtpd/table_static.c
94
new = strdup(val);
usr.sbin/smtpd/util.c
1104
int *type, char **key, char **val, int *malformed)
usr.sbin/smtpd/util.c
1110
*val = NULL;
usr.sbin/smtpd/util.c
1162
*val = valp;
usr.sbin/snmpd/application_internal.c
274
appl_internal_object_int(struct ber_oid *oid, int32_t val)
usr.sbin/snmpd/application_internal.c
283
obj->intval = val;
usr.sbin/snmpd/application_internal.c
295
appl_internal_object_string(struct ber_oid *oid, char *val)
usr.sbin/snmpd/application_internal.c
304
obj->stringval = val;
usr.sbin/snmpd/parse.y
1468
char *p, *val;
usr.sbin/snmpd/parse.y
1498
val = symget(buf);
usr.sbin/snmpd/parse.y
1499
if (val == NULL) {
usr.sbin/snmpd/parse.y
1503
p = val + strlen(val) - 1;
usr.sbin/snmpd/parse.y
1505
while (p >= val) {
usr.sbin/snmpd/parse.y
1949
free(sym->val);
usr.sbin/snmpd/parse.y
1959
symset(const char *nam, const char *val, int persist)
usr.sbin/snmpd/parse.y
1973
free(sym->val);
usr.sbin/snmpd/parse.y
1986
sym->val = strdup(val);
usr.sbin/snmpd/parse.y
1987
if (sym->val == NULL) {
usr.sbin/snmpd/parse.y
2001
char *sym, *val;
usr.sbin/snmpd/parse.y
2004
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/snmpd/parse.y
2006
sym = strndup(s, val - s);
usr.sbin/snmpd/parse.y
2009
ret = symset(sym, val + 1, 1);
usr.sbin/snmpd/parse.y
2023
return (sym->val);
usr.sbin/snmpd/parse.y
95
char *val;
usr.sbin/snmpd/snmpe.c
155
int val, s;
usr.sbin/snmpd/snmpe.c
167
val = 1;
usr.sbin/snmpd/snmpe.c
169
&val, sizeof(val)) == -1)
usr.sbin/snmpd/snmpe.c
174
val = 1;
usr.sbin/snmpd/snmpe.c
176
&val, sizeof(int)) == -1) {
usr.sbin/snmpd/snmpe.c
183
val = 1;
usr.sbin/snmpd/snmpe.c
185
&val, sizeof(int)) == -1) {
usr.sbin/syslogd/syslogd.c
3233
int val = 1;
usr.sbin/syslogd/syslogd.c
3235
if (setsockopt(fd, SOL_SOCKET, SO_KEEPALIVE, &val, sizeof(val)) == -1)
usr.sbin/syslogd/syslogd.c
3236
log_warn("setsockopt keepalive %d", val);
usr.sbin/tcpdump/pfctl_osfp.c
768
long val = 0;
usr.sbin/tcpdump/pfctl_osfp.c
832
val = val * 10 + field[i] - '0';
usr.sbin/tcpdump/pfctl_osfp.c
833
if (val < 0) {
usr.sbin/tcpdump/pfctl_osfp.c
840
if (val > max) {
usr.sbin/tcpdump/pfctl_osfp.c
842
name, val, max);
usr.sbin/tcpdump/pfctl_osfp.c
845
*var = (int)val;
usr.sbin/tcpdump/print-gtp.c
327
int val, ielen, iecount = 0;
usr.sbin/tcpdump/print-gtp.c
341
val = (u_int)cp[0];
usr.sbin/tcpdump/print-gtp.c
348
if ((val & GTPV0_IE_TYPE_MASK) == 0)
usr.sbin/tcpdump/print-gtp.c
349
ielen = gtp_v0_print_tv(cp, val);
usr.sbin/tcpdump/print-gtp.c
351
ielen = gtp_v0_print_tlv(cp, val);
usr.sbin/tcpdump/print-gtp.c
355
if ((val & GTPV1_IE_TYPE_MASK) == 0)
usr.sbin/tcpdump/print-gtp.c
356
ielen = gtp_v1_print_tv(cp, val);
usr.sbin/tcpdump/print-gtp.c
358
ielen = gtp_v1_print_tlv(cp, val);
usr.sbin/tcpdump/print-ike.c
306
u_int16_t len = buf[2] << 8 | buf[3], val;
usr.sbin/tcpdump/print-ike.c
324
for (val = 0; val < len; val++)
usr.sbin/tcpdump/print-ike.c
325
printf("%02x", *(buf + 4 + val));
usr.sbin/tcpdump/print-ike.c
329
val = len; /* For AF=1, this field is the "VALUE" */
usr.sbin/tcpdump/print-ike.c
334
if (val < sizeof var / sizeof var [0]) \
usr.sbin/tcpdump/print-ike.c
335
printf("%s", var [val]); \
usr.sbin/tcpdump/print-ike.c
337
printf("%d (unknown)", val); \
usr.sbin/tcpdump/print-ike.c
349
printf("%d", val);
usr.sbin/tcpdump/print-ike.c
358
"%d", val));
usr.sbin/tcpdump/print-ike.c
361
printf("%d", val);
usr.sbin/tcpdump/print-ike.c
730
u_int8_t *val = af ? buf + 2 : buf + 4;
usr.sbin/tcpdump/print-ike.c
743
if (len == 0 || (af && !val[0] && !val[1])) {
usr.sbin/tcpdump/print-ike.c
755
memcpy (&in.s_addr, val, sizeof in);
usr.sbin/tcpdump/print-ike.c
764
printf("%s", inet_ntop (AF_INET6, val, ntop_buf,
usr.sbin/tcpdump/print-ike.c
769
memcpy(&in.s_addr, val, sizeof in);
usr.sbin/tcpdump/print-ike.c
771
memcpy(&in.s_addr, val + sizeof in, sizeof in);
usr.sbin/tcpdump/print-ike.c
776
printf("%s/%u", inet_ntop (AF_INET6, val, ntop_buf,
usr.sbin/tcpdump/print-ike.c
777
sizeof ntop_buf), val[16]);
usr.sbin/tcpdump/print-ike.c
782
val[0] << 24 | val[1] << 16 | val[2] << 8 | val[3]);
usr.sbin/tcpdump/print-ike.c
787
printf("%c", isprint(val[p]) ? val[p] : '.');
usr.sbin/tcpdump/print-ike.c
794
type = (val[p] << 8 | val[p + 1]) & 0x7fff;
usr.sbin/tcpdump/print-l2tp.c
619
u_short pad, val;
usr.sbin/tcpdump/print-l2tp.c
631
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
632
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
633
if ((ntohs(val) & L2TP_VERSION_MASK) == L2TP_VERSION_L2TP) {
usr.sbin/tcpdump/print-l2tp.c
635
} else if ((ntohs(val) & L2TP_VERSION_MASK) == L2TP_VERSION_L2F) {
usr.sbin/tcpdump/print-l2tp.c
644
if (ntohs(val) & L2TP_FLAG_TYPE) {
usr.sbin/tcpdump/print-l2tp.c
648
if (ntohs(val) & L2TP_FLAG_LENGTH) {
usr.sbin/tcpdump/print-l2tp.c
652
if (ntohs(val) & L2TP_FLAG_SEQUENCE) {
usr.sbin/tcpdump/print-l2tp.c
656
if (ntohs(val) & L2TP_FLAG_OFFSET) {
usr.sbin/tcpdump/print-l2tp.c
660
if (ntohs(val) & L2TP_FLAG_PRIORITY) {
usr.sbin/tcpdump/print-l2tp.c
670
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
671
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
676
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
677
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
678
printf("(%d/", ntohs(val)); /* Tunnel ID */
usr.sbin/tcpdump/print-l2tp.c
681
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
682
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
683
printf("%d)", ntohs(val)); /* Session ID */
usr.sbin/tcpdump/print-l2tp.c
688
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
689
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
690
printf("Ns=%d,", ntohs(val));
usr.sbin/tcpdump/print-l2tp.c
693
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
694
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
695
printf("Nr=%d", ntohs(val));
usr.sbin/tcpdump/print-l2tp.c
701
TCHECK2(*dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
702
memcpy(&val, dat, sizeof(val));
usr.sbin/tcpdump/print-l2tp.c
703
pad = ntohs(val);
usr.sbin/tcpdump/print-radius.c
42
static void r_print_att(int code, int len, const u_char *val);
usr.sbin/tcpdump/print-radius.c
43
static void r_print_int(int code, int len, const u_char *val);
usr.sbin/tcpdump/print-radius.c
44
static void r_print_address(int code, int len, const u_char *val);
usr.sbin/tcpdump/print-radius.c
45
static void r_print_string(int code, int len, const u_char *val);
usr.sbin/tcpdump/print-radius.c
46
static void r_print_hex(int code, int len, const u_char *val);
usr.sbin/tcpdump/print-vqp.c
101
switch (val) {
usr.sbin/tcpdump/print-vqp.c
115
printf("unknown(%x)", val);
usr.sbin/tcpdump/print-vqp.c
121
vqp_print_rcode(u_int val)
usr.sbin/tcpdump/print-vqp.c
123
switch (val) {
usr.sbin/tcpdump/print-vqp.c
143
printf("unknown(%x)", val);
usr.sbin/tcpdump/print-vqp.c
99
vqp_print_opcode(u_int val)
usr.sbin/tcpdump/smb.h
12
#define SCVAL(buf,pos,val) (CVAL(buf,pos) = (val))
usr.sbin/tcpdump/smb.h
16
#define SSVALX(buf,pos,val) (CVAL(buf,pos)=(val)&0xFF,CVAL(buf,pos+1)=(val)>>8)
usr.sbin/tcpdump/smb.h
17
#define SIVALX(buf,pos,val) (SSVALX(buf,pos,val&0xFFFF),SSVALX(buf,pos+2,val>>16))
usr.sbin/tcpdump/smb.h
20
#define SSVAL(buf,pos,val) SSVALX((buf),(pos),((uint16)(val)))
usr.sbin/tcpdump/smb.h
21
#define SIVAL(buf,pos,val) SIVALX((buf),(pos),((uint32)(val)))
usr.sbin/tcpdump/smb.h
22
#define SSVALS(buf,pos,val) SSVALX((buf),(pos),((int16)(val)))
usr.sbin/tcpdump/smb.h
23
#define SIVALS(buf,pos,val) SIVALX((buf),(pos),((int32)(val)))
usr.sbin/tcpdump/smb.h
31
#define RSSVAL(buf,pos,val) SSVAL(buf,pos,SREV(val))
usr.sbin/tcpdump/smb.h
32
#define RSIVAL(buf,pos,val) SIVAL(buf,pos,IREV(val))
usr.sbin/tcpdump/smbutil.c
252
static void write_bits(unsigned int val,char *fmt)
usr.sbin/tcpdump/smbutil.c
259
if (l && (val & (1<<i)))
usr.sbin/traceroute/worker.c
1007
*val = t->val;
usr.sbin/traceroute/worker.c
967
map_tos(char *s, int *val)
usr.sbin/traceroute/worker.c
972
int val;
usr.sbin/unbound/daemon/remote.c
798
int val = atoi(str);
usr.sbin/unbound/daemon/remote.c
799
if(val == 0 && strcmp(str, "0") != 0) {
usr.sbin/unbound/daemon/remote.c
803
verbosity = val;
usr.sbin/unbound/daemon/remote.c
916
size_t msg, rrset, val, iter, respip;
usr.sbin/unbound/daemon/remote.c
932
val = mod_get_mem(&worker->env, "validator");
usr.sbin/unbound/daemon/remote.c
958
if(!print_longnum(ssl, "mem.mod.validator"SQ, val))
usr.sbin/unbound/daemon/worker.c
125
size_t me, iter, val, anch;
usr.sbin/unbound/daemon/worker.c
142
val = 0;
usr.sbin/unbound/daemon/worker.c
147
val += (*worker->env.mesh->mods.mod[i]->get_mem)
usr.sbin/unbound/daemon/worker.c
173
total = front+back+mesh+msg+rrset+infra+iter+val+ac+superac+me;
usr.sbin/unbound/daemon/worker.c
181
(unsigned)iter, (unsigned)val,
usr.sbin/unbound/daemon/worker.c
190
(unsigned)infra, (unsigned)iter, (unsigned)val, (unsigned)anch,
usr.sbin/unbound/daemon/worker.c
197
size_t val = 0;
usr.sbin/unbound/daemon/worker.c
208
val += (*worker->env.mesh->mods.mod[i]->get_mem)
usr.sbin/unbound/daemon/worker.c
223
(unsigned)val, (unsigned)subnet);
usr.sbin/unbound/daemon/worker.c
229
(unsigned)val);
usr.sbin/unbound/libunbound/libunbound.c
413
ub_ctx_set_option(struct ub_ctx* ctx, const char* opt, const char* val)
usr.sbin/unbound/libunbound/libunbound.c
420
if(!config_set_option(ctx->env->cfg, opt, val)) {
usr.sbin/unbound/libunbound/unbound.h
293
int ub_ctx_set_option(struct ub_ctx* ctx, const char* opt, const char* val);
usr.sbin/unbound/libunbound/unbound.h
668
long long val;
usr.sbin/unbound/services/listen_dnsport.c
512
int val=(v6only==2)?0:1;
usr.sbin/unbound/services/listen_dnsport.c
514
(void*)&val, (socklen_t)sizeof(val)) < 0) {
usr.sbin/unbound/sldns/parseutil.c
323
uint16_t val;
usr.sbin/unbound/sldns/parseutil.c
329
val = (uint16_t)(((*str_p)[0] - '0') * 100 +
usr.sbin/unbound/sldns/parseutil.c
333
if (val > 255) {
usr.sbin/unbound/sldns/parseutil.c
336
*ch_p = (uint8_t)val;
usr.sbin/unbound/sldns/str2wire.c
1174
sldns_str2wire_svcparam_port(const char* val, uint8_t* rd, size_t* rd_len)
usr.sbin/unbound/sldns/str2wire.c
1182
port = strtoul(val, &endptr, 10);
usr.sbin/unbound/sldns/str2wire.c
1184
if (endptr > val /* digits seen */
usr.sbin/unbound/sldns/str2wire.c
1200
sldns_str2wire_svcbparam_ipv4hint(const char* val, uint8_t* rd, size_t* rd_len)
usr.sbin/unbound/sldns/str2wire.c
1207
for (i = 0, count = 1; val[i]; i++) {
usr.sbin/unbound/sldns/str2wire.c
1208
if (val[i] == ',')
usr.sbin/unbound/sldns/str2wire.c
1226
if (!(next_ip_str = strchr(val, ','))) {
usr.sbin/unbound/sldns/str2wire.c
1227
if (inet_pton(AF_INET, val, rd + *rd_len) != 1)
usr.sbin/unbound/sldns/str2wire.c
1233
} else if (next_ip_str - val >= (int)sizeof(ip_str))
usr.sbin/unbound/sldns/str2wire.c
1237
memcpy(ip_str, val, next_ip_str - val);
usr.sbin/unbound/sldns/str2wire.c
1238
ip_str[next_ip_str - val] = 0;
usr.sbin/unbound/sldns/str2wire.c
1244
val = next_ip_str + 1;
usr.sbin/unbound/sldns/str2wire.c
1255
sldns_str2wire_svcbparam_ipv6hint(const char* val, uint8_t* rd, size_t* rd_len)
usr.sbin/unbound/sldns/str2wire.c
1262
for (i = 0, count = 1; val[i]; i++) {
usr.sbin/unbound/sldns/str2wire.c
1263
if (val[i] == ',')
usr.sbin/unbound/sldns/str2wire.c
1281
if (!(next_ip_str = strchr(val, ','))) {
usr.sbin/unbound/sldns/str2wire.c
1282
if (inet_pton(AF_INET6, val, rd + *rd_len) != 1)
usr.sbin/unbound/sldns/str2wire.c
1288
} else if (next_ip_str - val >= (int)sizeof(ip_str))
usr.sbin/unbound/sldns/str2wire.c
1292
memcpy(ip_str, val, next_ip_str - val);
usr.sbin/unbound/sldns/str2wire.c
1293
ip_str[next_ip_str - val] = 0;
usr.sbin/unbound/sldns/str2wire.c
1299
val = next_ip_str + 1;
usr.sbin/unbound/sldns/str2wire.c
1317
sldns_str2wire_svcbparam_mandatory(const char* val, uint8_t* rd, size_t* rd_len)
usr.sbin/unbound/sldns/str2wire.c
1322
val_len = strlen(val);
usr.sbin/unbound/sldns/str2wire.c
1324
for (i = 0, count = 1; val[i]; i++) {
usr.sbin/unbound/sldns/str2wire.c
1325
if (val[i] == ',')
usr.sbin/unbound/sldns/str2wire.c
1341
if (!(next_key = strchr(val, ','))) {
usr.sbin/unbound/sldns/str2wire.c
1342
svcparamkey = sldns_str2wire_svcparam_key_lookup(val, val_len);
usr.sbin/unbound/sldns/str2wire.c
1352
svcparamkey = sldns_str2wire_svcparam_key_lookup(val, next_key - val);
usr.sbin/unbound/sldns/str2wire.c
1363
val_len -= next_key - val + 1;
usr.sbin/unbound/sldns/str2wire.c
1364
val = next_key + 1; /* skip the comma */
usr.sbin/unbound/sldns/str2wire.c
1402
sldns_str2wire_svcbparam_ech_value(const char* val, uint8_t* rd, size_t* rd_len)
usr.sbin/unbound/sldns/str2wire.c
1408
if(strcmp(val, "0") == 0) {
usr.sbin/unbound/sldns/str2wire.c
1417
wire_len = sldns_b64_pton(val, buffer, LDNS_MAX_RDFLEN);
usr.sbin/unbound/sldns/str2wire.c
1434
sldns_str2wire_svcbparam_parse_next_unescaped_comma(const char *val)
usr.sbin/unbound/sldns/str2wire.c
1436
while (*val) {
usr.sbin/unbound/sldns/str2wire.c
1438
if (*val == '\\'){
usr.sbin/unbound/sldns/str2wire.c
1439
++val;
usr.sbin/unbound/sldns/str2wire.c
1440
if (!*val)
usr.sbin/unbound/sldns/str2wire.c
1442
} else if (*val == ',')
usr.sbin/unbound/sldns/str2wire.c
1443
return val;
usr.sbin/unbound/sldns/str2wire.c
1445
val++;
usr.sbin/unbound/sldns/str2wire.c
1476
sldns_str2wire_svcbparam_alpn_value(const char* val,
usr.sbin/unbound/sldns/str2wire.c
1486
val_len = strlen(val);
usr.sbin/unbound/sldns/str2wire.c
1494
str_len = (next_str = sldns_str2wire_svcbparam_parse_next_unescaped_comma(val))
usr.sbin/unbound/sldns/str2wire.c
1495
? (size_t)(next_str - val) : val_len;
usr.sbin/unbound/sldns/str2wire.c
1501
key_len = sldns_str2wire_svcbparam_parse_copy_unescaped(dst + 1, val, str_len);
usr.sbin/unbound/sldns/str2wire.c
1509
val_len -= next_str - val + 1;
usr.sbin/unbound/sldns/str2wire.c
1510
val = next_str + 1;
usr.sbin/unbound/sldns/str2wire.c
1524
sldns_str2wire_svcbparam_dohpath_value(const char* val,
usr.sbin/unbound/sldns/str2wire.c
1536
val_len = strlen(val);
usr.sbin/unbound/sldns/str2wire.c
1544
memcpy(rd + 4, val, val_len);
usr.sbin/unbound/sldns/str2wire.c
1552
const char *val, uint8_t* rd, size_t* rd_len)
usr.sbin/unbound/sldns/str2wire.c
1562
if (val == NULL) {
usr.sbin/unbound/sldns/str2wire.c
1587
return sldns_str2wire_svcparam_port(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1589
return sldns_str2wire_svcbparam_ipv4hint(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1591
return sldns_str2wire_svcbparam_ipv6hint(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1593
return sldns_str2wire_svcbparam_mandatory(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1599
return sldns_str2wire_svcbparam_ech_value(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1601
return sldns_str2wire_svcbparam_alpn_value(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1603
return sldns_str2wire_svcbparam_dohpath_value(val, rd, rd_len);
usr.sbin/unbound/sldns/str2wire.c
1605
str_len = strlen(val);
usr.sbin/unbound/sldns/str2wire.c
1610
memcpy(rd + 4, val, str_len);
usr.sbin/unbound/sldns/str2wire.c
2225
uint32_t meters = 0, cm = 0, val;
usr.sbin/unbound/sldns/str2wire.c
2240
val = meters;
usr.sbin/unbound/sldns/str2wire.c
2243
val = cm;
usr.sbin/unbound/sldns/str2wire.c
2245
while(val >= 10) {
usr.sbin/unbound/sldns/str2wire.c
2247
val /= 10;
usr.sbin/unbound/sldns/str2wire.c
2249
*m = (uint8_t)val;
usr.sbin/unbound/smallapp/unbound-anchor.c
1680
unsigned long val = 0;
usr.sbin/unbound/smallapp/unbound-anchor.c
1684
val = s->data[0];
usr.sbin/unbound/smallapp/unbound-anchor.c
1686
val |= s->data[1] << 8;
usr.sbin/unbound/smallapp/unbound-anchor.c
1690
return val;
usr.sbin/unbound/smallapp/unbound-control.c
295
PR_LL("mem.mod.validator", shm_stat->mem.val);
usr.sbin/unbound/testcode/doqclient.c
1459
unsigned int val = ecn;
usr.sbin/unbound/testcode/doqclient.c
1461
if(setsockopt(fd, IPPROTO_IPV6, IPV6_TCLASS, &val,
usr.sbin/unbound/testcode/doqclient.c
1462
(socklen_t)sizeof(val)) == -1) {
usr.sbin/unbound/testcode/doqclient.c
1468
if(setsockopt(fd, IPPROTO_IP, IP_TOS, &val,
usr.sbin/unbound/testcode/doqclient.c
1469
(socklen_t)sizeof(val)) == -1) {
usr.sbin/unbound/testcode/lock_verify.c
228
static void read_lock(rbtree_type* all, FILE* in, int val)
usr.sbin/unbound/testcode/lock_verify.c
235
prev_id.thr = val;
usr.sbin/unbound/testcode/readhex.c
68
int val;
usr.sbin/unbound/testcode/readhex.c
76
val = sldns_hexdigit_to_int(*p++) << 4;
usr.sbin/unbound/testcode/readhex.c
79
val |= sldns_hexdigit_to_int(*p++);
usr.sbin/unbound/testcode/readhex.c
80
sldns_buffer_write_u8(pkt, (uint8_t)val);
usr.sbin/unbound/testcode/unitlruhash.c
71
static testdata_type* newdata(int val) {
usr.sbin/unbound/testcode/unitlruhash.c
75
d->data = val;
usr.sbin/unbound/testcode/unitslabhash.c
73
static testdata_type* newdata(int val) {
usr.sbin/unbound/testcode/unitslabhash.c
77
d->data = val;
usr.sbin/unbound/util/config_file.c
1478
#define SET_AUTO_SLAB(var, name, val) \
usr.sbin/unbound/util/config_file.c
1481
cfg->var = val; \
usr.sbin/unbound/util/config_file.c
1482
verbose(VERB_QUERY, "setting "name": %lu", (unsigned long)val); \
usr.sbin/unbound/util/config_file.c
2674
cfg_parse_local_zone(struct config_file* cfg, const char* val)
usr.sbin/unbound/util/config_file.c
2680
name = val;
usr.sbin/unbound/util/config_file.c
2684
log_err("syntax error: too short: %s", val);
usr.sbin/unbound/util/config_file.c
2689
log_err("syntax error: expected zone type: %s", val);
usr.sbin/unbound/util/config_file.c
2693
log_err("syntax error: bad zone name: %s", val);
usr.sbin/unbound/util/config_file.c
2703
log_err("syntax error: expected zone type: %s", val);
usr.sbin/unbound/util/config_file.c
474
if(atoi(val) == 0 && strcmp(val, "0") != 0) return 0
usr.sbin/unbound/util/config_file.c
477
if(atoi(val) == 0) return 0
usr.sbin/unbound/util/config_file.c
480
if(atoi(val) == 0 || !is_pow2((size_t)atoi(val))) return 0
usr.sbin/unbound/util/config_file.c
483
if(strcmp(val, "yes") != 0 && strcmp(val, "no") != 0) return 0
usr.sbin/unbound/util/config_file.c
486
{ IS_NUMBER_OR_ZERO; cfg->var = atoi(val); }
usr.sbin/unbound/util/config_file.c
489
{ IS_NONZERO_NUMBER; cfg->var = atoi(val); }
usr.sbin/unbound/util/config_file.c
492
{ IS_NUMBER_OR_ZERO; cfg->var = (unsigned)atoi(val); }
usr.sbin/unbound/util/config_file.c
495
{ IS_NUMBER_OR_ZERO; cfg->var = (size_t)atoi(val); }
usr.sbin/unbound/util/config_file.c
498
{ IS_NONZERO_NUMBER; cfg->var = (size_t)atoi(val); }
usr.sbin/unbound/util/config_file.c
501
{ IS_YES_OR_NO; cfg->var = (strcmp(val, "yes") == 0); }
usr.sbin/unbound/util/config_file.c
504
{ return cfg_parse_memsize(val, &cfg->var); }
usr.sbin/unbound/util/config_file.c
507
{ IS_POW2_NUMBER; cfg->var = (size_t)atoi(val); }
usr.sbin/unbound/util/config_file.c
510
{ free(cfg->var); return (cfg->var = strdup(val)) != NULL; }
usr.sbin/unbound/util/config_file.c
513
{ return cfg_strlist_insert(&cfg->var, strdup(val)); }
usr.sbin/unbound/util/config_file.c
516
{ if(cfg_strlist_find(cfg->var, val)) { return 0;} \
usr.sbin/unbound/util/config_file.c
517
return cfg_strlist_insert(&cfg->var, strdup(val)); }
usr.sbin/unbound/util/config_file.c
520
{ return cfg_strlist_append(&cfg->var, strdup(val)); }
usr.sbin/unbound/util/config_file.c
542
const char* val)
usr.sbin/unbound/util/config_file.c
552
if(strcmp(val, "0") == 0 || strcmp(val, "") == 0)
usr.sbin/unbound/util/config_file.c
554
else if(atoi(val) == 0)
usr.sbin/unbound/util/config_file.c
556
else cfg->stat_interval = atoi(val);
usr.sbin/unbound/util/config_file.c
561
return cfg_mark_ports(val, 1,
usr.sbin/unbound/util/config_file.c
564
return cfg_mark_ports(val, 0,
usr.sbin/unbound/util/config_file.c
567
return cfg_parse_local_zone(cfg, val);
usr.sbin/unbound/util/config_file.c
569
if(strcmp(val, "") == 0 || strcmp(val, "0") == 0) {
usr.sbin/unbound/util/config_file.c
571
} else if(strlen(val) == 14) {
usr.sbin/unbound/util/config_file.c
572
cfg->val_date_override = cfg_convert_timeval(val);
usr.sbin/unbound/util/config_file.c
575
if(atoi(val) == 0) return 0;
usr.sbin/unbound/util/config_file.c
576
cfg->val_date_override = (uint32_t)atoi(val);
usr.sbin/unbound/util/config_file.c
584
return (cfg->logfile = strdup(val)) != NULL;
usr.sbin/unbound/util/config_file.c
587
{ IS_YES_OR_NO; cfg->log_time_ascii = (strcmp(val, "yes") == 0);
usr.sbin/unbound/util/config_file.c
590
{ IS_YES_OR_NO; cfg->log_time_iso = (strcmp(val, "yes") == 0);
usr.sbin/unbound/util/config_file.c
639
if(!cfg_tls_protocols_is_valid(val)) return 0;
usr.sbin/unbound/util/config_file.c
641
return (cfg->tls_protocols = strdup(val)) != NULL;
usr.sbin/unbound/util/config_file.c
679
{ IS_NUMBER_OR_ZERO; cfg->max_ttl = atoi(val); MAX_TTL=(time_t)cfg->max_ttl;}
usr.sbin/unbound/util/config_file.c
681
{ IS_NUMBER_OR_ZERO; cfg->max_negative_ttl = atoi(val); MAX_NEG_TTL=(time_t)cfg->max_negative_ttl;}
usr.sbin/unbound/util/config_file.c
683
{ IS_NUMBER_OR_ZERO; cfg->min_negative_ttl = atoi(val); MIN_NEG_TTL=(time_t)cfg->min_negative_ttl;}
usr.sbin/unbound/util/config_file.c
685
{ IS_NUMBER_OR_ZERO; cfg->min_ttl = atoi(val); MIN_TTL=(time_t)cfg->min_ttl;}
usr.sbin/unbound/util/config_file.c
687
IS_NUMBER_OR_ZERO; cfg->infra_cache_min_rtt = atoi(val);
usr.sbin/unbound/util/config_file.c
691
IS_NUMBER_OR_ZERO; cfg->infra_cache_max_rtt = atoi(val);
usr.sbin/unbound/util/config_file.c
713
if (!(cfg->nsid_cfg_str = strdup(val)))
usr.sbin/unbound/util/config_file.c
716
if (*val == 0) {
usr.sbin/unbound/util/config_file.c
722
cfg->nsid = cfg_parse_nsid(val, &cfg->nsid_len);
usr.sbin/unbound/util/config_file.c
766
{ IS_YES_OR_NO; cfg->serve_expired = (strcmp(val, "yes") == 0);
usr.sbin/unbound/util/config_file.c
769
{ IS_NUMBER_OR_ZERO; cfg->serve_expired_ttl = atoi(val); SERVE_EXPIRED_TTL=(time_t)cfg->serve_expired_ttl;}
usr.sbin/unbound/util/config_file.c
771
{ IS_YES_OR_NO; cfg->serve_expired_ttl_reset = (strcmp(val, "yes") == 0);
usr.sbin/unbound/util/config_file.c
774
{ IS_NUMBER_OR_ZERO; cfg->serve_expired_reply_ttl = atoi(val); SERVE_EXPIRED_REPLY_TTL=(time_t)cfg->serve_expired_reply_ttl;}
usr.sbin/unbound/util/config_file.c
791
{ IS_YES_OR_NO; cfg->permit_small_holddown = (strcmp(val, "yes") == 0);
usr.sbin/unbound/util/config_file.c
868
IS_NUMBER_OR_ZERO; cfg->ip_ratelimit_cookie = atoi(val);
usr.sbin/unbound/util/config_file.c
872
IS_NUMBER_OR_ZERO; cfg->ip_ratelimit = atoi(val);
usr.sbin/unbound/util/config_file.c
876
IS_NUMBER_OR_ZERO; cfg->ratelimit = atoi(val);
usr.sbin/unbound/util/config_file.c
903
{ IS_NUMBER_OR_ZERO; cfg->ipsecmod_max_ttl = atoi(val); }
usr.sbin/unbound/util/config_file.c
913
return config_add_tag(cfg, val);
usr.sbin/unbound/util/config_file.c
917
{ IS_NUMBER_OR_ZERO; cfg->val_sig_skew_min = (int32_t)atoi(val); }
usr.sbin/unbound/util/config_file.c
919
{ IS_NUMBER_OR_ZERO; cfg->val_sig_skew_max = (int32_t)atoi(val); }
usr.sbin/unbound/util/config_file.c
921
{ IS_NUMBER_OR_ZERO; cfg->val_max_restart = (int32_t)atoi(val); }
usr.sbin/unbound/util/config_file.c
923
char* d = strdup(val);
usr.sbin/unbound/util/config_file.h
1326
int cfg_parse_local_zone(struct config_file* cfg, const char* val);
usr.sbin/unbound/util/netevent.c
1215
unsigned int val = ecn;
usr.sbin/unbound/util/netevent.c
1217
if(setsockopt(fd, IPPROTO_IPV6, IPV6_TCLASS, &val,
usr.sbin/unbound/util/netevent.c
1218
(socklen_t)sizeof(val)) == -1) {
usr.sbin/unbound/util/netevent.c
1224
if(setsockopt(fd, IPPROTO_IP, IP_TOS, &val,
usr.sbin/unbound/util/netevent.c
1225
(socklen_t)sizeof(val)) == -1) {
usr.sbin/unbound/util/shm_side/shm_main.c
264
shm_stat->mem.val = (long long)mod_get_mem(&worker->env, "validator");
usr.sbin/vmctl/main.c
351
parse_ifs(struct parse_result *res, char *word, int val)
usr.sbin/vmctl/main.c
356
val = strtonum(word, 1, INT_MAX, &error);
usr.sbin/vmctl/main.c
362
res->nifs = val;
usr.sbin/vmctl/main.c
393
long long val = 0;
usr.sbin/vmctl/main.c
396
if (scan_scaled(word, &val) != 0)
usr.sbin/vmctl/main.c
400
if (val < (1024 * 1024))
usr.sbin/vmctl/main.c
403
if (strcmp("memory", type) == 0 && val > VMM_MAX_VM_MEM_SIZE) {
usr.sbin/vmctl/main.c
411
res->size = (val / (1024 * 1024)) * (1024 * 1024);
usr.sbin/vmctl/main.c
413
if (res->size != (size_t)val) {
usr.sbin/vmctl/vmctl.c
929
int val;
usr.sbin/vmctl/vmctl.c
931
if (imsg_get_data(imsg, &val, sizeof(val)))
usr.sbin/vmctl/vmctl.c
934
return (val);
usr.sbin/vmd/arm64_vm.c
92
intr_toggle_el(struct vmd_vm *vm, int irq, int val)
usr.sbin/vmd/i8259.c
691
pic_set_elcr(uint8_t irq, uint8_t val)
usr.sbin/vmd/i8259.c
693
if (irq > 15 || val > 1)
usr.sbin/vmd/i8259.c
697
val ? "level" : "edge", irq);
usr.sbin/vmd/i8259.c
700
if (val)
usr.sbin/vmd/i8259.c
705
if (val)
usr.sbin/vmd/parse.y
1022
val = symget(buf);
usr.sbin/vmd/parse.y
1023
if (val == NULL) {
usr.sbin/vmd/parse.y
1027
p = val + strlen(val) - 1;
usr.sbin/vmd/parse.y
1029
while (p >= val) {
usr.sbin/vmd/parse.y
1233
free(sym->val);
usr.sbin/vmd/parse.y
1246
symset(const char *nam, const char *val, int persist)
usr.sbin/vmd/parse.y
1260
free(sym->val);
usr.sbin/vmd/parse.y
1273
sym->val = strdup(val);
usr.sbin/vmd/parse.y
1274
if (sym->val == NULL) {
usr.sbin/vmd/parse.y
1288
char *sym, *val;
usr.sbin/vmd/parse.y
1291
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/vmd/parse.y
1293
sym = strndup(s, val - s);
usr.sbin/vmd/parse.y
1296
ret = symset(sym, val + 1, 1);
usr.sbin/vmd/parse.y
1310
return (sym->val);
usr.sbin/vmd/parse.y
1317
parse_size(char *word, int64_t val)
usr.sbin/vmd/parse.y
1328
val = (int64_t)res;
usr.sbin/vmd/parse.y
1331
if (val < (1024 * 1024)) {
usr.sbin/vmd/parse.y
1336
if (val > VMM_MAX_VM_MEM_SIZE) {
usr.sbin/vmd/parse.y
1346
size = (val / (1024 * 1024)) * (1024 * 1024);
usr.sbin/vmd/parse.y
1348
if (size != val) {
usr.sbin/vmd/parse.y
85
char *val;
usr.sbin/vmd/parse.y
992
char *p, *val;
usr.sbin/vmd/proc.c
674
unsigned int val;
usr.sbin/vmd/proc.c
676
if (imsg_get_data(imsg, &val, sizeof(val)))
usr.sbin/vmd/proc.c
679
return (val);
usr.sbin/vmd/proc.c
685
int val;
usr.sbin/vmd/proc.c
687
if (imsg_get_data(imsg, &val, sizeof(val)))
usr.sbin/vmd/proc.c
690
return (val);
usr.sbin/vmd/x86_vm.c
1139
intr_toggle_el(struct vmd_vm *vm, int irq, int val)
usr.sbin/vmd/x86_vm.c
1142
pic_set_elcr(irq, val);
usr.sbin/wsfontload/wsfontload.c
248
return (encodings[i].val);
usr.sbin/wsfontload/wsfontload.c
68
int val;
usr.sbin/wsmoused/mouse_protocols.c
534
if (t->val != -1)
usr.sbin/wsmoused/mouse_protocols.c
549
if (t->val != -1)
usr.sbin/wsmoused/mouse_protocols.c
774
mouse.proto = t->val;
usr.sbin/wsmoused/mouse_protocols.h
186
int val;
usr.sbin/ypldap/parse.y
1001
sym->val = strdup(val);
usr.sbin/ypldap/parse.y
1002
if (sym->val == NULL) {
usr.sbin/ypldap/parse.y
1016
char *sym, *val;
usr.sbin/ypldap/parse.y
1019
if ((val = strrchr(s, '=')) == NULL)
usr.sbin/ypldap/parse.y
1021
sym = strndup(s, val - s);
usr.sbin/ypldap/parse.y
1024
ret = symset(sym, val + 1, 1);
usr.sbin/ypldap/parse.y
1038
return (sym->val);
usr.sbin/ypldap/parse.y
691
char *p, *val;
usr.sbin/ypldap/parse.y
721
val = symget(buf);
usr.sbin/ypldap/parse.y
722
if (val == NULL) {
usr.sbin/ypldap/parse.y
726
p = val + strlen(val) - 1;
usr.sbin/ypldap/parse.y
728
while (p >= val) {
usr.sbin/ypldap/parse.y
89
char *val;
usr.sbin/ypldap/parse.y
960
free(sym->val);
usr.sbin/ypldap/parse.y
974
symset(const char *nam, const char *val, int persist)
usr.sbin/ypldap/parse.y
988
free(sym->val);
usr.sbin/ypldap/yp.c
716
res->val.valdat_len = strlen(buf);
usr.sbin/ypldap/yp.c
717
res->val.valdat_val = buf;
usr.sbin/ypldap/yp.c
743
res->val.valdat_len = strlen(buf);
usr.sbin/ypldap/yp.c
744
res->val.valdat_val = buf;
usr.sbin/ypserv/common/yplib_host.c
148
*outvallen = yprv.val.valdat_len;
usr.sbin/ypserv/common/yplib_host.c
150
memcpy(*outval, yprv.val.valdat_val, *outvallen);
usr.sbin/ypserv/common/yplib_host.c
185
*outvallen = yprkv.val.valdat_len;
usr.sbin/ypserv/common/yplib_host.c
187
memcpy(*outval, yprkv.val.valdat_val, *outvallen);
usr.sbin/ypserv/common/yplib_host.c
224
*outvallen = yprkv.val.valdat_len;
usr.sbin/ypserv/common/yplib_host.c
226
memcpy(*outval, yprkv.val.valdat_val, *outvallen);
usr.sbin/ypserv/common/yplib_host.c
241
char *key, *val;
usr.sbin/ypserv/common/yplib_host.c
255
status = out.ypresp_all_u.val.stat;
usr.sbin/ypserv/common/yplib_host.c
257
size = out.ypresp_all_u.val.key.keydat_len;
usr.sbin/ypserv/common/yplib_host.c
262
(void)memcpy(key, out.ypresp_all_u.val.key.keydat_val,
usr.sbin/ypserv/common/yplib_host.c
266
size = out.ypresp_all_u.val.val.valdat_len;
usr.sbin/ypserv/common/yplib_host.c
267
if ((val = malloc(size + 1)) == NULL) {
usr.sbin/ypserv/common/yplib_host.c
272
(void)memcpy(val, out.ypresp_all_u.val.val.valdat_val,
usr.sbin/ypserv/common/yplib_host.c
274
val[size] = '\0';
usr.sbin/ypserv/common/yplib_host.c
277
out.ypresp_all_u.val.key.keydat_len, val,
usr.sbin/ypserv/common/yplib_host.c
278
out.ypresp_all_u.val.val.valdat_len, ypserv_ypresp_data);
usr.sbin/ypserv/common/yplib_host.c
280
free(val);
usr.sbin/ypserv/makedbm/db.c
46
DBT key, val;
usr.sbin/ypserv/makedbm/db.c
53
status = db->seq(db, &key, &val, R_FIRST);
usr.sbin/ypserv/makedbm/db.c
57
(int)val.size-1, (int)val.size-1, (char *)val.data);
usr.sbin/ypserv/makedbm/db.c
58
status = db->seq(db, &key, &val, R_NEXT);
usr.sbin/ypserv/makedbm/makedbm.c
131
datum key, val;
usr.sbin/ypserv/makedbm/makedbm.c
148
val = ypdb_fetch(db, key);
usr.sbin/ypserv/makedbm/makedbm.c
151
val.dsize, val.dsize, val.dptr);
usr.sbin/ypserv/makedbm/makedbm.c
81
datum key, val;
usr.sbin/ypserv/makedbm/makedbm.c
88
val = ypdb_fetch(db, key);
usr.sbin/ypserv/makedbm/makedbm.c
90
if (val.dptr != NULL)
usr.sbin/ypserv/makedbm/makedbm.c
94
val.dptr = str2;
usr.sbin/ypserv/makedbm/makedbm.c
95
val.dsize = strlen(str2);
usr.sbin/ypserv/makedbm/makedbm.c
96
status = ypdb_store(db, key, val, YPDB_INSERT);
usr.sbin/ypserv/mkalias/mkalias.c
146
datum key, val;
usr.sbin/ypserv/mkalias/mkalias.c
243
val = ypdb_fetch(db, key);
usr.sbin/ypserv/mkalias/mkalias.c
245
if (val.dptr == NULL)
usr.sbin/ypserv/mkalias/mkalias.c
251
if (memchr(val.dptr, ',', val.dsize))
usr.sbin/ypserv/mkalias/mkalias.c
253
if (memchr(val.dptr, '|', val.dsize))
usr.sbin/ypserv/mkalias/mkalias.c
256
if (!(memchr(val.dptr, '@', val.dsize) ||
usr.sbin/ypserv/mkalias/mkalias.c
257
memchr(val.dptr, '!', val.dsize)))
usr.sbin/ypserv/mkalias/mkalias.c
260
split_address(val.dptr, val.dsize, user, host);
usr.sbin/ypserv/mkalias/mkalias.c
262
if (eflag && check_host(val.dptr, val.dsize, host, dflag, uflag, Eflag)) {
usr.sbin/ypserv/mkalias/mkalias.c
265
val.dsize, val.dsize, val.dptr);
usr.sbin/ypserv/mkalias/mkalias.c
273
status = ypdb_store(new_db, val, key, YPDB_INSERT);
usr.sbin/ypserv/mkalias/mkalias.c
276
val.dsize, val.dsize, val.dptr,
usr.sbin/ypserv/mkalias/mkalias.c
283
val.dsize, val.dsize, val.dptr,
usr.sbin/ypserv/mkalias/mkalias.c
294
val.dptr = datestr;
usr.sbin/ypserv/mkalias/mkalias.c
295
val.dsize = strlen(datestr);
usr.sbin/ypserv/mkalias/mkalias.c
296
status = ypdb_store(new_db, key, val, YPDB_INSERT);
usr.sbin/ypserv/mkalias/mkalias.c
300
val.dsize, val.dsize, val.dptr);
usr.sbin/ypserv/mkalias/mkalias.c
308
val.dptr = myname;
usr.sbin/ypserv/mkalias/mkalias.c
309
val.dsize = strlen(myname);
usr.sbin/ypserv/mkalias/mkalias.c
310
status = ypdb_store(new_db, key, val, YPDB_INSERT);
usr.sbin/ypserv/mkalias/mkalias.c
314
val.dsize, val.dsize, val.dptr);
usr.sbin/ypserv/ypserv/ypserv_db.c
367
static char val[BUFSIZ+1]; /* match libc */
usr.sbin/ypserv/ypserv/ypserv_db.c
385
v = val;
usr.sbin/ypserv/ypserv/ypserv_db.c
390
len = strlcat(val, tmpbuf, sizeof(val));
usr.sbin/ypserv/ypserv/ypserv_db.c
391
if (len >= sizeof(val))
usr.sbin/ypserv/ypserv/ypserv_db.c
393
v = val + len;
usr.sbin/ypserv/ypserv/ypserv_db.c
395
result->val.valdat_val = val;
usr.sbin/ypserv/ypserv/ypserv_db.c
396
result->val.valdat_len = v - val;
usr.sbin/ypserv/ypserv/ypserv_db.c
423
len = snprintf(val, sizeof(val), "%s %s", keystr, host->h_name);
usr.sbin/ypserv/ypserv/ypserv_db.c
424
if (len < 0 || len >= sizeof(val))
usr.sbin/ypserv/ypserv/ypserv_db.c
426
v = val + len;
usr.sbin/ypserv/ypserv/ypserv_db.c
428
strlcat(val, " ", sizeof(val));
usr.sbin/ypserv/ypserv/ypserv_db.c
429
len = strlcat(val, ptr, sizeof(val));
usr.sbin/ypserv/ypserv/ypserv_db.c
430
if (len >= sizeof(val))
usr.sbin/ypserv/ypserv/ypserv_db.c
432
v = val + len;
usr.sbin/ypserv/ypserv/ypserv_db.c
435
result->val.valdat_val = val;
usr.sbin/ypserv/ypserv/ypserv_db.c
436
result->val.valdat_len = v - val;
usr.sbin/ypserv/ypserv/ypserv_db.c
480
res.val.valdat_val = v.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
481
res.val.valdat_len = v.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
515
res.val.valdat_val = v.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
516
res.val.valdat_len = v.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
563
res.val.valdat_val = v.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
564
res.val.valdat_len = v.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
643
&resp.ypresp_all_u.val.stat, NULL);
usr.sbin/ypserv/ypserv/ypserv_db.c
644
if (!db || resp.ypresp_all_u.val.stat < 0)
usr.sbin/ypserv/ypserv/ypserv_db.c
659
resp.ypresp_all_u.val.stat = YP_TRUE;
usr.sbin/ypserv/ypserv/ypserv_db.c
660
resp.ypresp_all_u.val.key.keydat_val = k.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
661
resp.ypresp_all_u.val.key.keydat_len = k.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
662
resp.ypresp_all_u.val.val.valdat_val = v.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
663
resp.ypresp_all_u.val.val.valdat_len = v.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
679
resp.ypresp_all_u.val.stat = YP_NOKEY;
usr.sbin/ypserv/ypserv/ypserv_proc.c
333
res.ypresp_all_u.val.stat = YP_YPERR;
usr.sbin/ypserv/ypxfr/ypxfr.c
188
datum key, val;
usr.sbin/ypserv/ypxfr/ypxfr.c
197
val.dptr = datestr;
usr.sbin/ypserv/ypxfr/ypxfr.c
198
val.dsize = strlen(datestr);
usr.sbin/ypserv/ypxfr/ypxfr.c
200
status = ypdb_store(db, key, val, YPDB_INSERT);
usr.sbin/ypserv/ypxfr/ypxfr.c
212
datum key, val;
usr.sbin/ypserv/ypxfr/ypxfr.c
222
val.dptr = master;
usr.sbin/ypserv/ypxfr/ypxfr.c
223
val.dsize = strlen(master);
usr.sbin/ypserv/ypxfr/ypxfr.c
225
status = ypdb_store(db, key, val, YPDB_INSERT);
usr.sbin/ypserv/ypxfr/ypxfr.c
59
datum key, val;
usr.sbin/ypserv/ypxfr/ypxfr.c
70
val.dptr = valstr;
usr.sbin/ypserv/ypxfr/ypxfr.c
71
val.dsize = strlen(valstr);
usr.sbin/ypserv/ypxfr/ypxfr.c
73
ypdb_store(db, key, val, YPDB_INSERT);
usr.sbin/zic/zic.c
1277
convert(int_fast32_t val, unsigned char *buf)
usr.sbin/zic/zic.c
1283
buf[i] = val >> shift;
usr.sbin/zic/zic.c
1287
convert64(zic_t val, unsigned char *buf)
usr.sbin/zic/zic.c
1293
buf[i] = val >> shift;
usr.sbin/zic/zic.c
1297
puttzcode(int_fast32_t val, FILE *fp)
usr.sbin/zic/zic.c
1301
convert(val, buf);
usr.sbin/zic/zic.c
1306
puttzcode64(zic_t val, FILE *fp)
usr.sbin/zic/zic.c
1310
convert64(val, buf);
