#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#include <machine/psl.h>
#include <machine/pte.h>
#define tlbbtop(b) ((b) >> (PAGE_SHIFT - 5))
#define tlbptob(p) ((p) << (PAGE_SHIFT - 5))
#define hptbtop(b) ((b) >> 17)
static __inline register_t ldsid(vaddr_t p) {
register_t ret;
__asm volatile("ldsid (%1),%0" : "=r" (ret) : "r" (p));
return ret;
}
#define mtctl(v,r) __asm volatile("mtctl %0,%1":: "r" (v), "i" (r))
#define mfctl(r,v) __asm volatile("mfctl %1,%0": "=r" (v): "i" (r))
#define mfcpu(r,v) \
__asm volatile(".word %1\n\t" \
"copy %%r22, %0" \
: "=r" (v) : "i" ((0x14001400 | ((r) << 21) | (22))) \
: "r22")
#define mtsp(v,r) __asm volatile("mtsp %0,%1":: "r" (v), "i" (r))
#define mfsp(r,v) __asm volatile("mfsp %1,%0": "=r" (v): "i" (r))
#define ssm(v,r) __asm volatile("ssm %1,%0": "=r" (r): "i" (v))
#define rsm(v,r) __asm volatile("rsm %1,%0": "=r" (r): "i" (v))
static __inline register_t
mtsm(register_t mask) {
register_t ret;
__asm volatile("ssm 0,%0\n\t"
"mtsm %1": "=&r" (ret) : "r" (mask));
return ret;
}
#define fdce(sp,off) __asm volatile("fdce 0(%0,%1)":: "i" (sp), "r" (off))
#define fice(sp,off) __asm volatile("fice 0(%0,%1)":: "i" (sp), "r" (off))
#define sync_caches() __asm volatile(\
"sync\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop":::"memory")
static __inline void
iitlba(u_int pg, pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("iitlba %0,(%%sr1, %1)":: "r" (pg), "r" (va));
}
static __inline void
idtlba(u_int pg, pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("idtlba %0,(%%sr1, %1)":: "r" (pg), "r" (va));
}
static __inline void
iitlbp(u_int prot, pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("iitlbp %0,(%%sr1, %1)":: "r" (prot), "r" (va));
}
static __inline void
idtlbp(u_int prot, pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("idtlbp %0,(%%sr1, %1)":: "r" (prot), "r" (va));
}
static __inline void
pitlb(pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("pitlb %%r0(%%sr1, %0)":: "r" (va));
}
static __inline void
pdtlb(pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("pdtlb %%r0(%%sr1, %0)":: "r" (va));
}
static __inline void
pitlbe(pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("pitlbe %%r0(%%sr1, %0)":: "r" (va));
}
static __inline void
pdtlbe(pa_space_t sp, vaddr_t va)
{
mtsp(sp, 1);
__asm volatile("pdtlbe %%r0(%%sr1, %0)":: "r" (va));
}
#ifdef USELEDS
#define PALED_NETSND 0x01
#define PALED_NETRCV 0x02
#define PALED_DISK 0x04
#define PALED_HEARTBEAT 0x08
#define PALED_LOADMASK 0xf0
#define PALED_DATA 0x01
#define PALED_STROBE 0x02
extern volatile u_int8_t *machine_ledaddr;
extern int machine_ledword, machine_leds;
static __inline void
ledctl(int on, int off, int toggle)
{
if (machine_ledaddr) {
int r;
if (on)
machine_leds |= on;
if (off)
machine_leds &= ~off;
if (toggle)
machine_leds ^= toggle;
r = ~machine_leds;
if (machine_ledword)
*machine_ledaddr = r;
else {
register int b;
for (b = 0x80; b; b >>= 1) {
*machine_ledaddr = (r & b)? PALED_DATA : 0;
DELAY(1);
*machine_ledaddr = ((r & b)? PALED_DATA : 0) |
PALED_STROBE;
}
}
}
}
#endif
#ifdef _KERNEL
extern int (*cpu_hpt_init)(vaddr_t hpt, vsize_t hptsize);
void fpu_save(vaddr_t va);
void fpu_exit(void);
void ficache(pa_space_t sp, vaddr_t va, vsize_t size);
void fdcache(pa_space_t sp, vaddr_t va, vsize_t size);
void pdcache(pa_space_t sp, vaddr_t va, vsize_t size);
void ficacheall(void);
void fdcacheall(void);
void ptlball(void);
int btlb_insert(pa_space_t space, vaddr_t va, paddr_t pa, vsize_t *lenp, u_int prot);
hppa_hpa_t cpu_gethpa(int n);
void eaio_l2(int i);
#endif
#endif