sys/arch/aarch64/aarch64/cpu.c

101

.ci_cpl = IPL_HIGH,

sys/arch/aarch64/aarch64/cpu.c

126

ci->ci_cpl = IPL_HIGH;

sys/arch/acorn32/acorn32/autoconf.c

177

irqmasks[IPL_AUDIO], irqmasks[IPL_CLOCK], irqmasks[IPL_HIGH],

sys/arch/algor/algor/algor_intr.c

81

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/alpha/alpha/prom.c

169

mutex_init(&prom_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/alpha/pci/ttwoga_pci.c

82

mutex_init(&ttwoga_conf_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/amd64/amd64/machdep.c

2092

splraise(IPL_HIGH);

sys/arch/amiga/amiga/machdep.c

857

[IPL_HIGH] = PSL_IPL4|PSL_S,

sys/arch/amiga/amiga/machdep.c

860

[IPL_HIGH] = PSL_IPL7|PSL_S,

sys/arch/arc/arc/c_magnum.c

101

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/arc/arc/c_nec_eisa.c

122

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/arc/arc/c_nec_pci.c

127

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/arc/arc/p_dti_arcstation.c

114

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/arc/arc/p_dti_tyne.c

117

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/arc/arc/p_sni_rm200pci.c

98

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

282

mutex_init(&pcie->lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/acpi/cpu_acpi.c

393

ih = intr_establish_xname(gicc->PerformanceInterrupt, IPL_HIGH,

sys/arch/arm/apple/apple_dart.c

603

NULL, NULL, NULL, 0, VM_SLEEP, IPL_HIGH);

sys/arch/arm/apple/apple_dart.c

685

ih = fdtbus_intr_establish_xname(phandle, 0, IPL_HIGH, FDT_INTR_MPSAFE,

sys/arch/arm/apple/apple_intc.c

359

if (oldipl != IPL_HIGH) {

sys/arch/arm/apple/apple_intc.c

386

if (oldipl != IPL_HIGH) {

sys/arch/arm/apple/apple_intc.c

518

IPL_HIGH, IST_LEVEL | IST_MPSAFE, apple_intc_ipi_handler,

sys/arch/arm/arm/arm_machdep.c

118

.ci_cpl = IPL_HIGH,

sys/arch/arm/arm/efi_runtime.c

99

mutex_init(&efi_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/arm32/cpu.c

126

ci->ci_cpl = IPL_HIGH;

sys/arch/arm/arm32/intr.c

67

spl_masks[IPL_HIGH] = irqmasks[IPL_HIGH];

sys/arch/arm/at91/at91aic.c

167

aic_imask[IPL_HIGH] |= aic_imask[IPL_SCHED];

sys/arch/arm/broadcom/bcm2835_intr.c

903

intr_establish(BCM2836_INT_MAILBOX0_CPUN(cpuid), IPL_HIGH,

sys/arch/arm/broadcom/bcm2838_pcie.c

187

mutex_init(&sc->sc_bcmstb.sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/cortex/gic.c

185

| ((IPL_HIGH - ipl) * GICC_PMR_NS_PRIORITIES / NIPL);

sys/arch/arm/cortex/gic.c

192

return IPL_HIGH

sys/arch/arm/cortex/gic.c

341

if (old_ipl == IPL_HIGH) {

sys/arch/arm/cortex/gic.c

361

KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x",

sys/arch/arm/cortex/gic.c

546

KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl);

sys/arch/arm/cortex/gic.c

684

KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl);

sys/arch/arm/cortex/gic.c

720

intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_HIGH,

sys/arch/arm/cortex/gic.c

722

intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_GENERIC, IPL_HIGH,

sys/arch/arm/cortex/gic.c

729

intr_establish_xname(ARMGIC_SGI_IPIBASE + IPI_DDB, IPL_HIGH,

sys/arch/arm/cortex/gicv3.c

418

ci->ci_hwpl = IPL_HIGH;

sys/arch/arm/cortex/gicv3.c

419

icc_pmr_write(IPL_TO_PMR(sc, IPL_HIGH));

sys/arch/arm/cortex/gicv3.c

740

if (oldhwpl == IPL_HIGH) {

sys/arch/arm/cortex/gicv3.c

912

1, NULL, NULL, NULL, 0, VM_SLEEP, IPL_HIGH);

sys/arch/arm/cortex/gicv3.c

941

intr_establish_xname(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1, "IPI xcall");

sys/arch/arm/cortex/gicv3.c

942

intr_establish_xname(IPI_GENERIC, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1, "IPI generic");

sys/arch/arm/cortex/gicv3.c

946

intr_establish_xname(IPI_DDB, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL, "IPI ddb");

sys/arch/arm/cortex/pl310.c

160

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/ep93xx/ep93xx_intr.c

167

vic1_imask[IPL_HIGH] |= vic1_imask[IPL_SCHED];

sys/arch/arm/ep93xx/ep93xx_intr.c

168

vic2_imask[IPL_HIGH] |= vic2_imask[IPL_SCHED];

sys/arch/arm/fdt/pmu_fdt.c

147

ih[n] = fdtbus_intr_establish_xname(phandle, n, IPL_HIGH,

sys/arch/arm/footbridge/footbridge.c

178

sc->sc_serr_ih = footbridge_intr_claim(IRQ_SERR, IPL_HIGH,

sys/arch/arm/footbridge/footbridge.c

180

sc->sc_sdram_par_ih = footbridge_intr_claim(IRQ_SDRAM_PARITY, IPL_HIGH,

sys/arch/arm/footbridge/footbridge.c

182

sc->sc_data_par_ih = footbridge_intr_claim(IRQ_DATA_PARITY, IPL_HIGH,

sys/arch/arm/footbridge/footbridge.c

184

sc->sc_master_abt_ih = footbridge_intr_claim(IRQ_MASTER_ABORT, IPL_HIGH,

sys/arch/arm/footbridge/footbridge.c

186

sc->sc_target_abt_ih = footbridge_intr_claim(IRQ_TARGET_ABORT, IPL_HIGH,

sys/arch/arm/footbridge/footbridge.c

188

sc->sc_parity_ih = footbridge_intr_claim(IRQ_PARITY, IPL_HIGH,

sys/arch/arm/footbridge/footbridge_clock.c

301

clock_sc->sc_statclockintr = footbridge_intr_claim(IRQ_TIMER_2, IPL_HIGH,

sys/arch/arm/footbridge/footbridge_irqhandler.c

149

footbridge_imask[IPL_HIGH] |= footbridge_imask[IPL_SCHED];

sys/arch/arm/footbridge/isa/isa_machdep.c

207

imask[IPL_HIGH] |= imask[IPL_SCHED];

sys/arch/arm/gemini/gemini_gpio.c

374

IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, &gpio->gpio_pic);

sys/arch/arm/gemini/gemini_timer.c

318

intr_establish(stat_sc->sc_intr, IPL_HIGH, IST_LEVEL_HIGH,

sys/arch/arm/imx/imx51_gpio.c

119

IPL_HIGH, IST_LEVEL, pic_handle_intr, &gpio->gpio_pic);

sys/arch/arm/imx/imx51_gpio.c

122

IPL_HIGH, IST_LEVEL, pic_handle_intr, &gpio->gpio_pic);

sys/arch/arm/imx/imx51_tzic.c

98

#define HW_TO_SW_IPL(ipl) (IPL_HIGH - ((ipl) >> 3))

sys/arch/arm/imx/imx51_tzic.c

99

#define SW_TO_HW_IPL(ipl) ((IPL_HIGH - (ipl)) << 3)

sys/arch/arm/imx/imxuart.c

330

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/include/arm32/psl.h

63

#define splhigh() raisespl(IPL_HIGH)

sys/arch/arm/iomd/vidcvideo.c

580

if (curcpl() == IPL_HIGH) {

sys/arch/arm/ixp12x0/ixp12x0_intr.c

224

imask[IPL_HIGH] |= imask[IPL_SCHED];

sys/arch/arm/ixp12x0/ixp12x0_intr.c

225

pci_imask[IPL_HIGH] |= pci_imask[IPL_SCHED];

sys/arch/arm/marvell/armadaxp.c

597

ih = intr_establish(ARMADAXP_IRQ_ERR_SUMMARY, IPL_HIGH, IST_LEVEL_HIGH,

sys/arch/arm/marvell/dove.c

204

ih = intr_establish(DOVE_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,

sys/arch/arm/marvell/dove.c

424

marvell_intr_establish(mva->mva_irq, IPL_HIGH, dove_pmu_intr, sc);

sys/arch/arm/marvell/kirkwood.c

158

ih = intr_establish(KIRKWOOD_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,

sys/arch/arm/marvell/mvsocgpp.c

183

IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic);

sys/arch/arm/marvell/orion.c

120

ih = intr_establish(ORION_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,

sys/arch/arm/nxp/imx_gpio.c

128

sc->gpio_is = fdtbus_intr_establish_xname(phandle, 0, IPL_HIGH, 0,

sys/arch/arm/nxp/imx_gpio.c

141

sc->gpio_is_high = fdtbus_intr_establish_xname(phandle, 1, IPL_HIGH, 0,

sys/arch/arm/pic/pic.c

565

if (__predict_false(newipl == IPL_HIGH)) {

sys/arch/arm/pic/pic.c

566

KASSERTMSG(ci->ci_cpl == IPL_HIGH, "cpl %d", ci->ci_cpl);

sys/arch/arm/pic/pic.c

628

mutex_init(&pic_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/rockchip/rk3399_pcie.c

448

mutex_init(&sc->sc_conf_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/s3c2xx0/s3c2410_extint.c

154

s3c24x0_intr_establish(S3C2410_INT_4_7, IPL_HIGH, IST_NONE,

sys/arch/arm/s3c2xx0/s3c2410_extint.c

157

s3c24x0_intr_establish(S3C2410_INT_8_23, IPL_HIGH, IST_NONE,

sys/arch/arm/s3c2xx0/s3c2440_extint.c

185

s3c24x0_intr_establish(S3C2440_INT_4_7, IPL_HIGH, IST_NONE,

sys/arch/arm/s3c2xx0/s3c2440_extint.c

188

s3c24x0_intr_establish(S3C2440_INT_8_23, IPL_HIGH, IST_NONE,

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

263

s3c24x0_intr_establish(S3C24X0_INT_TIMER3, IPL_HIGH,

sys/arch/arm/s3c2xx0/s3c2800_clk.c

261

s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_HIGH,

sys/arch/arm/s3c2xx0/s3c2xx0_intr.c

117

s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_CLOCK];

sys/arch/arm/sa11x0/sa11x0_irqhandler.c

104

#if IPL_NONE > IPL_HIGH

sys/arch/arm/samsung/exynos_uart.c

224

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

391

mutex_init(&cpux_axi_cfg_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/sunxi/sun9i_a80_ccu.c

410

mutex_init(&cpux_axi_cfg_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/sunxi/sunxi_nmi.c

405

mutex_init(&sc->sc_intr_lock, MUTEX_SPIN, IPL_HIGH);

sys/arch/arm/sunxi/sunxi_rtc.c

394

mutex_init(&sc->sc_clk_mutex, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/xilinx/zynq_uart.c

393

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/arm/xscale/becc_icu.c

201

becc_imask[IPL_HIGH] |= becc_imask[IPL_SCHED];

sys/arch/arm/xscale/ixp425_intr.c

240

ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_SCHED];

sys/arch/arm/xscale/pxa2x0_intr.c

243

pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED];

sys/arch/atari/atari/intr.c

324

[IPL_HIGH] = PSL_S | PSL_IPL7,

sys/arch/bebox/bebox/machdep.c

170

intr_establish(16 + 26, IST_LEVEL, IPL_HIGH, pic_handle_intr, isa_pic);

sys/arch/cats/cats/autoconf.c

157

footbridge_imask[IPL_HIGH], footbridge_imask[IPL_SERIAL]);

sys/arch/cesfic/include/z8530var.h

22

#define IPL_ZS IPL_HIGH

sys/arch/cobalt/cobalt/interrupt.c

152

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/emips/emips/xilinx_ml40x.c

85

[IPL_HIGH] = NOINTS,

sys/arch/emips/emips/xs_bee3.c

83

[IPL_HIGH] = NOINTS,

sys/arch/evbarm/dev/plcom.c

475

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/evbarm/ifpga/ifpga_clock.c

310

IPL_HIGH, statclockhandler, 0);

sys/arch/evbarm/ifpga/ifpga_intr.c

177

ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_SCHED];

sys/arch/evbarm/iq80310/iq80310_intr.c

223

iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_STATCLOCK];

sys/arch/evbarm/iq80310/iq80310_intr.c

225

iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_CLOCK];

sys/arch/evbarm/iq80310/iq80310_intr.c

232

iq80310_imask[IPL_SERIAL] |= iq80310_imask[IPL_HIGH];

sys/arch/evbarm/lubbock/sacc_obio.c

174

IPL_HIGH, sacc_obio_intr, sc );

sys/arch/evbmips/evbmips/interrupt.c

109

KASSERT(ci->ci_cpl == IPL_HIGH);

sys/arch/evbmips/evbmips/interrupt.c

60

KASSERT(ci->ci_cpl == IPL_HIGH);

sys/arch/evbmips/gdium/gdium_intr.c

163

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/evbmips/ingenic/intr.c

85

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/evbmips/ingenic/machdep.c

236

mutex_init(&ingenic_ipi_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/evbmips/loongson/loongson_intr.c

93

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/evbmips/malta/malta_intr.c

77

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/evbmips/mipssim/mipssim_intr.c

59

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/evbmips/sbmips/sb1250_icu.c

73

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/evbppc/ev64260/gt_mainbus.c

206

intr_establish(IRQ_GPP7_0, IST_LEVEL, IPL_HIGH,

sys/arch/evbppc/ev64260/gt_mainbus.c

208

intr_establish(IRQ_GPP15_8, IST_LEVEL, IPL_HIGH,

sys/arch/evbppc/ev64260/gt_mainbus.c

210

intr_establish(IRQ_GPP23_16, IST_LEVEL, IPL_HIGH,

sys/arch/evbppc/ev64260/gt_mainbus.c

212

intr_establish(IRQ_GPP31_24, IST_LEVEL, IPL_HIGH,

sys/arch/evbppc/nintendo/dev/hwgpio.c

210

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/evbppc/nintendo/dev/resetbtn.c

89

ahb_intr_establish(aaa->aaa_irq, IPL_HIGH, resetbtn_intr, smpsw,

sys/arch/ews4800mips/ews4800mips/tr2_intr.c

68

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

59

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/hpcarm/dev/nbpiic.c

115

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/hpcarm/dev/nbpiic.c

117

ih = pxa2x0_intr_establish(pxa->pxa_intr, IPL_HIGH, nbpiic_intr, sc);

sys/arch/hpcarm/dev/nbppm.c

86

if (pxa2x0_gpio_intr_establish(0, IST_EDGE_RISING, IPL_HIGH,

sys/arch/hpcarm/dev/nbppm.c

93

if (pxa2x0_gpio_intr_establish(1, IST_EDGE_BOTH, IPL_HIGH,

sys/arch/hpcmips/tx/tx39icu.c

97

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/hpcmips/vr/vr.c

144

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/hpcsh/dev/j6x0pwr.c

265

sc->sc_ih = intc_intr_establish(SH7709_INTEVT2_IRQ0, IST_EDGE, IPL_HIGH,

sys/arch/hppa/dev/cpu.c

181

sc->sc_ihipi = hppa_intr_establish(IPL_HIGH, hppa_ipi_intr,

sys/arch/hppa/dev/gftfb.c

282

mutex_init(&sc->sc_hwlock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/hppa/dev/hyperfb.c

390

mutex_init(&sc->sc_hwlock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/i386/i386/machdep.c

1590

splraise(IPL_HIGH);

sys/arch/i386/pci/elan520.c

1291

mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/i386/pci/elan520.c

943

IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) {

sys/arch/ia64/ia64/sapic.c

152

mutex_init(&sa->sa_mtx, MUTEX_SPIN, IPL_HIGH);

sys/arch/ia64/include/intr.h

17

#define splhigh() splraise(IPL_HIGH)

sys/arch/m68k/m68k/m68k_intr.c

110

[IPL_HIGH] = PSL_S | PSL_IPL7,

sys/arch/mac68k/dev/pm_direct.c

262

mutex_init(&pm_mutex, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/mac68k/mac68k/intr.c

112

ipl2psl_table[IPL_HIGH] = PSL_S|PSL_IPL7;

sys/arch/mac68k/mac68k/intr.c

162

if (ipl2psl_table[IPL_SCHED] > ipl2psl_table[IPL_HIGH])

sys/arch/mac68k/mac68k/intr.c

163

ipl2psl_table[IPL_HIGH] = ipl2psl_table[IPL_SCHED];

sys/arch/macppc/dev/gpio.c

163

intr_establish_xname(ca->ca_intr[0], IST_LEVEL, IPL_HIGH, gpio_intr, sc,

sys/arch/macppc/macppc/pic_ohare.c

160

intr_establish_xname(irq, IST_LEVEL, IPL_HIGH, pic_handle_intr, pic,

sys/arch/macppc/macppc/pic_u3_ht.c

280

intr_establish_xname(cirq, IST_EDGE, IPL_HIGH,

sys/arch/mips/adm5120/adm5120_intr.c

99

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/mips/alchemy/au_icu.c

109

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/mips/atheros/ar5312.c

378

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/mips/atheros/ar5315.c

362

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/mips/atheros/ar7100.c

94

[IPL_HIGH] = MIPS_INT_MASK, /* EVERYTHING */

sys/arch/mips/atheros/ar9344.c

380

[IPL_HIGH] = MIPS_INT_MASK, /* EVERYTHING */

sys/arch/mips/cavium/octeon_cpunode.c

230

KASSERT(ci->ci_cpl == IPL_HIGH);

sys/arch/mips/cavium/octeon_intr.c

175

.ih_ipl = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

186

[IPI_NOP] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

187

[IPI_AST] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

189

[IPI_SYNCICACHE] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

190

[IPI_KPREEMPT] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

191

[IPI_SUSPEND] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

192

[IPI_HALT] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

193

[IPI_XCALL] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

194

[IPI_GENERIC] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

195

[IPI_WDOG] = IPL_HIGH,

sys/arch/mips/cavium/octeon_intr.c

270

mutex_init(&octeon_intr_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/mips/cavium/octeon_intr.c

397

case IPL_HIGH:

sys/arch/mips/cavium/octeon_intr.c

454

case IPL_HIGH:

sys/arch/mips/cavium/octeon_intr.c

88

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/mips/include/intr.h

55

#define _IPL_N (IPL_HIGH+1)

sys/arch/mips/mips/cpu_subr.c

94

.ci_cpl = IPL_HIGH,

sys/arch/mips/mips/locore.S

490

#if IPL_SCHED != IPL_HIGH

sys/arch/mips/mips/mips_machdep.c

2425

KASSERT((status ^ sr_map[IPL_HIGH]) == MIPS_INT_MASK);

sys/arch/mips/mips/mips_machdep.c

2426

KASSERT(ci->ci_cpl == IPL_HIGH);

sys/arch/mips/mips/mips_machdep.c

2434

for (int r = IPL_SOFTCLOCK; r <= IPL_HIGH; r++) {

sys/arch/mips/mips/mips_machdep.c

2444

for (int t = r; t <= IPL_HIGH; t++) {

sys/arch/mips/mips/mips_softint.c

103

KASSERTMSG(ci->ci_cpl == IPL_HIGH, "cpl (%d) != HIGH", ci->ci_cpl); \

sys/arch/mips/mips/mips_softint.c

115

KASSERT(ci->ci_cpl == IPL_HIGH);

sys/arch/mips/ralink/ralink_intr.c

64

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/mips/rmi/rmixl_fmnvar.h

195

KASSERT(curcpu()->ci_cpl == IPL_HIGH);

sys/arch/mips/rmi/rmixl_fmnvar.h

216

KASSERT(curcpu()->ci_cpl == IPL_HIGH);

sys/arch/mips/rmi/rmixl_fmnvar.h

279

#define RMIXL_FMN_INTR_IPL IPL_HIGH

sys/arch/mips/rmi/rmixl_gpio.c

226

IPL_HIGH, IST_LEVEL, pic_handle_intr, &gpio->gpio_pic);

sys/arch/mips/rmi/rmixl_intr.c

1057

IPL_HIGH, ipl_eimr_map[IPL_HIGH]);

sys/arch/mips/rmi/rmixl_intr.c

412

mutex_init(&rmixl_ipi_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/mips/rmi/rmixl_intr.c

413

mutex_init(&rmixl_intr_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/mips/rmi/rmixl_obio.c

285

rmixl_intr_establish(16, 1, IPL_HIGH,

sys/arch/mips/rmi/rmixl_pcie.c

292

mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/mips/rmi/rmixl_pcie.c

795

IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,

sys/arch/mips/rmi/rmixl_pcix.c

317

mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/mips/sibyte/dev/sbtimer.c

119

ipl = IPL_HIGH;

sys/arch/mips/sibyte/dev/sbwdog.c

117

cpu_intr_establish(sa->sa_locs.sa_intr[0], IPL_HIGH,

sys/arch/mipsco/mipsco/mips_3x30.c

79

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/netwinder/netwinder/autoconf.c

105

footbridge_imask[IPL_HIGH], footbridge_imask[IPL_SERIAL]);

sys/arch/newsmips/newsmips/news3400.c

78

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/newsmips/newsmips/news4000.c

69

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/newsmips/newsmips/news5000.c

74

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/ofppc/ofppc/mainbus.c

139

ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL);

sys/arch/ofppc/ofppc/mainbus.c

166

ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL);

sys/arch/ofppc/ofppc/mainbus.c

198

ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL);

sys/arch/ofppc/ofppc/mainbus.c

354

intr_establish(16, IST_LEVEL, IPL_HIGH, pic_handle_intr,

sys/arch/or1k/include/intr.h

121

return _splraise(IPL_HIGH);

sys/arch/pmax/pmax/dec_3100.c

118

[IPL_HIGH] = MIPS_SPLHIGH,

sys/arch/pmax/pmax/dec_3max.c

123

[IPL_HIGH] = MIPS_SPLHIGH,

sys/arch/pmax/pmax/dec_3maxplus.c

133

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/pmax/pmax/dec_3min.c

131

[IPL_HIGH] = MIPS_SPLHIGH,

sys/arch/pmax/pmax/dec_5100.c

78

[IPL_HIGH] = MIPS_SPLHIGH,

sys/arch/pmax/pmax/dec_maxine.c

129

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/powerpc/booke/booke_machdep.c

139

.ci_cpl = IPL_HIGH,

sys/arch/powerpc/booke/booke_machdep.c

148

.ci_cpl = IPL_HIGH,

sys/arch/powerpc/booke/booke_machdep.c

233

ci->ci_cpl = IPL_HIGH;

sys/arch/powerpc/booke/e500_intr.c

1052

15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR));

sys/arch/powerpc/booke/e500_intr.c

1058

15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR));

sys/arch/powerpc/booke/e500_intr.c

1072

e500_splset(ci, IPL_HIGH); /* pop to high */

sys/arch/powerpc/booke/e500_intr.c

1163

mutex_init(&e500_intr_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/powerpc/booke/e500_intr.c

537

e500_splset(ci, IPL_HIGH);

sys/arch/powerpc/booke/e500_intr.c

573

e500_splset(ci, IPL_HIGH);

sys/arch/powerpc/booke/e500_intr.c

637

if (ipl < IPL_VM || ipl > IPL_HIGH) {

sys/arch/powerpc/booke/e500_intr.c

74

#define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH)

sys/arch/powerpc/booke/e500_intr.c

743

KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH);

sys/arch/powerpc/booke/e500_intr.c

75

#define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH))

sys/arch/powerpc/booke/e500_intr.c

962

if (old_ipl == IPL_HIGH

sys/arch/powerpc/booke/e500_intr.c

966

__func__, tf, old_ipl, IPL_HIGH,

sys/arch/powerpc/booke/e500_intr.c

967

15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR));

sys/arch/powerpc/booke/e500_intr.c

983

15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR));

sys/arch/powerpc/booke/e500_intr.c

996

15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR));

sys/arch/powerpc/ibm4xx/pic_uic.c

242

intr_establish_xname(UIC1_CASCADE_IRQ, IST_LEVEL, IPL_HIGH,

sys/arch/powerpc/ibm4xx/pic_uic.c

296

intr_establish_xname(UIC2_CASCADE_IRQ, IST_LEVEL, IPL_HIGH,

sys/arch/powerpc/ibm4xx/pic_uic.c

352

intr_establish_xname(UIC3_CASCADE_IRQ, IST_LEVEL, IPL_HIGH,

sys/arch/powerpc/include/booke/intr.h

158

return splraise(IPL_HIGH);

sys/arch/powerpc/mpc5200/psc.c

208

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/powerpc/mpc5200/psc.c

241

sc->sc_ih = intr_establish(sc->sc_irq, ist, IPL_HIGH,

sys/arch/powerpc/oea/cpu_subr.c

555

ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL);

sys/arch/powerpc/pic/intr.c

171

maxipl = IPL_HIGH;

sys/arch/powerpc/pic/intr.c

565

ci->ci_cpl = IPL_HIGH;

sys/arch/powerpc/pic/intr.c

713

(u_int)imask[IPL_HIGH] & 0x7fffffff);

sys/arch/powerpc/powerpc/intr_stubs.c

128

return splraise(IPL_HIGH);

sys/arch/powerpc/powerpc/locore_subr.S

352

#if IPL_SCHED != IPL_HIGH

sys/arch/powerpc/powerpc/softint_machdep.c

61

KASSERTMSG(ci->ci_cpl == IPL_HIGH,

sys/arch/powerpc/powerpc/softint_machdep.c

75

KASSERT(ci->ci_cpl == IPL_HIGH);

sys/arch/prep/prep/machdep.c

357

intr_establish(16, IST_LEVEL, IPL_HIGH, pic_handle_intr,

sys/arch/riscv/fdt/clint_fdt.c

224

int ipl = IPL_HIGH;

sys/arch/riscv/fdt/intc_fdt.c

355

intc_intr_establish(sc, IRQ_SUPERVISOR_SOFTWARE, IPL_HIGH, IST_MPSAFE,

sys/arch/riscv/include/intr.h

55

#define _IPL_N (IPL_HIGH + 1)

sys/arch/riscv/riscv/cpu.c

100

.ci_cpl = IPL_HIGH,

sys/arch/riscv/riscv/cpu.c

199

ci->ci_cpl = IPL_HIGH;

sys/arch/riscv/riscv/cpu_switch.S

139

#if IPL_SCHED != IPL_HIGH

sys/arch/sandpoint/sandpoint/machdep.c

259

intr_establish_xname(16, IST_LEVEL, IPL_HIGH, pic_handle_intr, isa_pic,

sys/arch/sandpoint/sandpoint/satmgr.c

247

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/sbmips/sbmips/sb1250_icu.c

73

[IPL_HIGH] = MIPS_INT_MASK,

sys/arch/sgimips/sgimips/machdep.c

128

[IPL_HIGH] = MIPS_INT_MASK

sys/arch/sh3/dev/shpcic.c

327

if ((level < IPL_NONE) || (level > IPL_HIGH)) {

sys/arch/shark/isa/isa_irqhandler.c

305

irqmasks[IPL_HIGH] &= irqmasks[IPL_CLOCK];

sys/arch/shark/ofw/vlpci.c

215

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/sparc/dev/audioamd.c

239

(void)bus_intr_establish2(sc->sc_bt, pri, IPL_HIGH,

sys/arch/sparc/include/intr.h

62

#define IPL_ZS IPL_HIGH

sys/arch/sparc64/dev/auxio.c

126

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/sparc64/dev/psm.c

176

(void) bus_intr_establish(sc->sc_memt, ea->ea_intr[0], IPL_HIGH,

sys/arch/sparc64/dev/tadpmu.c

444

mutex_init(&data_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/usermode/usermode/machdep.c

278

splraise(IPL_HIGH);

sys/arch/usermode/usermode/pmap.c

484

"pventry", NULL, IPL_HIGH);

sys/arch/vax/boot/boot/autoconf.c

190

mtpr(IPL_HIGH, PR_IPL);

sys/arch/virt68k/virt68k/machdep.c

294

[IPL_HIGH] = PSL_S | PSL_IPL7,

sys/arch/x68k/dev/kbd.c

139

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/x68k/x68k/machdep.c

392

[IPL_HIGH] = PSL_S | PSL_IPL7,

sys/arch/x86/x86/intr.c

1431

fake_ipi_intrhand.ih_level = IPL_HIGH;

sys/arch/x86/x86/pmap.c

3593

KASSERTMSG((ilevel = ci->ci_ilevel) < IPL_HIGH, "ilevel=%d", ilevel);

sys/arch/x86/x86/x86_softintr.c

199

int minlevel = IPL_HIGH;

sys/arch/xen/x86/hypervisor_machdep.c

260

if (ci->ci_ilevel < IPL_HIGH) {

sys/arch/xen/x86/hypervisor_machdep.c

263

ci->ci_ilevel = IPL_HIGH;

sys/arch/xen/x86/xen_ipi.c

143

__FPTRCAST(int (*)(void *), xen_ipi_handler), ci, IPL_HIGH,

sys/arch/xen/xen/evtchn.c

913

KASSERT(mpsafe || level < IPL_HIGH);

sys/arch/xen/xen/xenevt.c

170

int level = IPL_HIGH;

sys/arch/xen/xen/xenevt.c

179

mutex_init(&devevent_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/arch/xen/xen/xenevt.c

210

KASSERT(xenevt_ih->ih_cpu->ci_ilevel >= IPL_HIGH);

sys/arch/xen/xen/xenevt.c

329

mutex_init(&d->lock, MUTEX_DEFAULT, IPL_HIGH);

sys/dev/fdt/fdt_intr.c

76

mutex_init(&fdtbus_interrupt_cookie_mutex, MUTEX_DEFAULT, IPL_HIGH);

sys/dev/ic/com.c

595

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/dev/ic/ssdfb.c

1122

if (s == IPL_HIGH)

sys/dev/marvell/gtmpsc.c

342

mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/dev/pci/cxgb/cxgb_osdep.h

71

#define mtx_init(a, b, c, d) { mutex_init(a, MUTEX_DEFAULT, IPL_HIGH) }

sys/kern/kern_cctr.c

136

mutex_init(&cc_calibration_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/kern/kern_exec.c

2677

mutex_init(&p2->p_stmutex, MUTEX_DEFAULT, IPL_HIGH);

sys/kern/kern_fork.c

377

mutex_init(&p2->p_stmutex, MUTEX_DEFAULT, IPL_HIGH);

sys/kern/kern_pmf.c

1152

"pewpl", NULL, IPL_HIGH);

sys/kern/kern_proc.c

495

mutex_init(&p->p_stmutex, MUTEX_DEFAULT, IPL_HIGH);

sys/kern/kern_tc.c

1520

mutex_init(&timecounter_lock, MUTEX_DEFAULT, IPL_HIGH);

sys/kern/subr_prf.c

151

mutex_init(&kprintf_mtx, MUTEX_DEFAULT, IPL_HIGH);

sys/kern/subr_spldebug.c

102

if (ipl != IPL_HIGH)

sys/kern/subr_spldebug.c

77

if (ipl == IPL_HIGH)

sys/rump/librump/rumpkern/lwproc.c

257

mutex_init(&p->p_stmutex, MUTEX_DEFAULT, IPL_HIGH);

sys/sys/intr.h

87

#define IPL_SERIAL IPL_HIGH

sys/uvm/pmap/pmap.c

2461

mutex_init(lock, MUTEX_DEFAULT, IPL_HIGH);

sys/uvm/pmap/pmap.c

2501

mutex_init(&pmap_pvlist_mutex, MUTEX_DEFAULT, IPL_HIGH);

sys/uvm/pmap/pmap.c

339

mutex_init(&pmap_tlb_miss_lock, MUTEX_SPIN, IPL_HIGH);

sys/uvm/pmap/pmap.c

700

mutex_init(&pmap_segtab_lock, MUTEX_DEFAULT, IPL_HIGH);