sys/arch/arm/altera/cycv_dwcmmc.c

133

sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu);

sys/arch/arm/amlogic/meson8b_clkc.c

112

const u_int old_rate = clk_get_rate(clkp);

sys/arch/arm/amlogic/meson8b_clkc.c

116

const u_int parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk.c

164

return clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk.c

361

aprint_debug("%10u Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/amlogic/meson_clk_div.c

106

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk_div.c

55

rate = clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

48

return clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk_mpll.c

57

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk_pll.c

118

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_clk_pll.c

56

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/amlogic/meson_dwmac.c

143

const u_int div = DIV_ROUND_OFF(clk_get_rate(clkin), 250000000);

sys/arch/arm/amlogic/meson_dwmac.c

293

miiclk_rate = clk_get_rate(clk_gmac);

sys/arch/arm/amlogic/meson_i2c.c

384

u_int rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/amlogic/meson_i2c.c

399

u_int rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/amlogic/meson_pwm.c

352

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/amlogic/meson_sdhc.c

263

sc->sc_bus_freq = clk_get_rate(clk_clkin);

sys/arch/arm/amlogic/meson_sdhc.c

265

aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin));

sys/arch/arm/amlogic/meson_sdio.c

236

sc->sc_bus_freq = clk_get_rate(clk_clkin);

sys/arch/arm/amlogic/meson_sdio.c

238

aprint_normal_dev(self, "core %u Hz, clkin %u Hz\n", clk_get_rate(clk_core), clk_get_rate(clk_clkin));

sys/arch/arm/amlogic/mesong12_clkc.c

1259

uint64_t xtal_clock = clk_get_rate(fdtbus_clock_byname("xtal"));

sys/arch/arm/amlogic/mesong12_clkc.c

1288

freq = clk_get_rate(clkp);

sys/arch/arm/amlogic/mesong12_clkc.c

1293

freq = clk_get_rate(clkp);

sys/arch/arm/amlogic/mesong12_clkc.c

1318

uint64_t xtal_clock = clk_get_rate(fdtbus_clock_byname("xtal"));

sys/arch/arm/amlogic/mesongx_mmc.c

482

const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]);

sys/arch/arm/amlogic/mesongx_wdt.c

154

sc->sc_rate = clk_get_rate(clk);

sys/arch/arm/apple/apple_iic.c

214

clock_speed = clk_get_rate(sc->sc_clk);

sys/arch/arm/broadcom/bcm2835_aux.c

199

return clk_get_rate(sc->sc_pclk);

sys/arch/arm/broadcom/bcm2835_bsc_fdt.c

99

sc->sc_frequency = clk_get_rate(sc->sc_clk);

sys/arch/arm/broadcom/bcm2835_com.c

104

sc->sc_frequency = clk_get_rate(clk);

sys/arch/arm/broadcom/bcm2835_emmc.c

155

sc->sc.sc_clkbase = clk_get_rate(clk) / 1000;

sys/arch/arm/broadcom/bcm2835_pwm.c

143

sc->sc_clockrate = clk_get_rate(sc->sc_clk);

sys/arch/arm/broadcom/bcm2835_sdhost.c

230

sc->sc_rate = clk_get_rate(clk);

sys/arch/arm/fdt/a9ptmr_fdt.c

165

rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/fdt/a9ptmr_fdt.c

98

uint32_t rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/fdt/a9tmr_fdt.c

165

rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/fdt/a9tmr_fdt.c

98

uint32_t rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/fdt/plcom_fdt.c

98

sc->sc_frequency = clk_get_rate(clk);

sys/arch/arm/fdt/plmmc_fdt.c

97

sc->sc_clock_freq = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra124_cpu.c

296

return clk_get_rate(tegra124_clk_pllx) / 1000000;

sys/arch/arm/nvidia/tegra210_car.c

808

printf("%u Hz\n", clk_get_rate(clk));

sys/arch/arm/nvidia/tegra_com.c

115

sc->sc_frequency = clk_get_rate(tsc->tsc_clk);

sys/arch/arm/nvidia/tegra_drm_mode.c

638

const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent);

sys/arch/arm/nvidia/tegra_sdhc.c

217

sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;

sys/arch/arm/nvidia/tegra_xusb.c

313

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

319

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

324

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

330

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

335

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

341

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

346

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

356

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nvidia/tegra_xusb.c

359

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nvidia/tegra_xusb.c

363

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nvidia/tegra_xusb.c

368

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nvidia/tegra_xusb.c

373

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nvidia/tegra_xusb.c

381

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

386

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

446

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

451

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

555

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nvidia/tegra_xusb.c

561

rate = clk_get_rate(psc->sc_clk_ss_src);

sys/arch/arm/nxp/if_enet_imx.c

167

sc->sc_clock = clk_get_rate(sc->sc_clk_ipg);

sys/arch/arm/nxp/imx6_ccm.c

103

parent_str, clk_get_rate(clk));

sys/arch/arm/nxp/imx6_pwm.c

137

sc->sc_freq = clk_get_rate(sc->sc_clk);

sys/arch/arm/nxp/imx6_spi.c

147

sc->sc_freq = clk_get_rate(ifsc->sc_clk);

sys/arch/arm/nxp/imx_ahcisata.c

459

clk_get_rate(sc->sc_clk_ahb) / 1000);

sys/arch/arm/nxp/imx_ccm.c

101

return clk_get_rate(clkp_parent);

sys/arch/arm/nxp/imx_ccm.c

307

aprint_debug("%10d Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/nxp/imx_ccm_composite.c

128

const u_int prate = clk_get_rate(clk_parent);

sys/arch/arm/nxp/imx_ccm_composite.c

80

const u_int prate = clk_get_rate(clkp_parent);

sys/arch/arm/nxp/imx_ccm_div.c

55

const u_int prate = clk_get_rate(clkp_parent);

sys/arch/arm/nxp/imx_ccm_div.c

85

const u_int prate = clk_get_rate(clkp_parent);

sys/arch/arm/nxp/imx_ccm_extclk.c

66

return clk_get_rate(extclk);

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

48

return clk_get_rate(clkp_parent);

sys/arch/arm/nxp/imx_ccm_pll.c

82

const u_int prate = clk_get_rate(clkp_parent);

sys/arch/arm/nxp/imx_com.c

104

aprint_normal(", %u Hz", clk_get_rate(per));

sys/arch/arm/nxp/imx_com.c

106

imxuart_set_frequency(clk_get_rate(per), 2);

sys/arch/arm/nxp/imx_i2c.c

85

clk_get_rate(imxsc->sc_clk), freq);

sys/arch/arm/nxp/imx_sdhc.c

138

sc->sc_sdhc.sc_clkbase = clk_get_rate(sc->sc_clk_per) / 1000;

sys/arch/arm/nxp/imxpcie.c

332

rate = clk_get_rate(sc->sc_clk_pcie_ext);

sys/arch/arm/nxp/imxpcie.c

334

rate = clk_get_rate(sc->sc_clk_pcie_phy);

sys/arch/arm/rockchip/rk3399_cru.c

1132

clk_set_rate(&clk->base, clk_get_rate(&clk->base));

sys/arch/arm/rockchip/rk3399_cru.c

247

const u_int fref = clk_get_rate(clkp_parent);

sys/arch/arm/rockchip/rk3399_pmucru.c

175

const u_int fref = clk_get_rate(clkp_parent);

sys/arch/arm/rockchip/rk_cru.c

152

return clk_get_rate(clkp_parent);

sys/arch/arm/rockchip/rk_cru.c

368

aprint_debug("%10d Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/rockchip/rk_cru_arm.c

53

const u_int fref = clk_get_rate(clkp_parent);

sys/arch/arm/rockchip/rk_cru_composite.c

126

const u_int prate = clk_get_rate(clk_parent);

sys/arch/arm/rockchip/rk_cru_composite.c

179

const u_int prate = clk_get_rate(clk_parent);

sys/arch/arm/rockchip/rk_cru_composite.c

74

const u_int prate = clk_get_rate(clkp_parent);

sys/arch/arm/rockchip/rk_cru_pll.c

101

const u_int fref = clk_get_rate(clkp_parent);

sys/arch/arm/rockchip/rk_emmcphy.c

164

rate = sc->sc_clk ? clk_get_rate(sc->sc_clk) : 0;

sys/arch/arm/rockchip/rk_i2c.c

142

rate = clk_get_rate(sc->sc_sclk);

sys/arch/arm/rockchip/rk_i2s.c

187

const u_int mclk_rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/rockchip/rk_pwm.c

227

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/rockchip/rk_spi.c

222

sc->sc_spi_freq = clk_get_rate(sclk);

sys/arch/arm/samsung/exynos5410_clock.c

514

if (clk_get_rate(clk) == 24 * 1000 * 1000) {

sys/arch/arm/samsung/exynos5410_clock.c

606

type, clk_get_rate(&eclk->base));

sys/arch/arm/samsung/exynos5422_clock.c

731

type, clk_get_rate(&eclk->base));

sys/arch/arm/samsung/exynos_dwcmmc.c

147

sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / (esc->sc_ciu_div + 1);

sys/arch/arm/samsung/exynos_dwcmmc.c

211

sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / ciu_div;

sys/arch/arm/samsung/exynos_pwm.c

230

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/samsung/exynos_uart.c

234

sc->sc_freq = clk_get_rate(clk_uart_baud0);

sys/arch/arm/sunxi/sun4i_spi.c

114

|| clk_set_rate(modclk, clk_get_rate(clk)) != 0

sys/arch/arm/sunxi/sun4i_spi.c

119

sc->sc_modclkrate = clk_get_rate(modclk);

sys/arch/arm/sunxi/sun6i_spi.c

130

sc->sc_modclkrate = clk_get_rate(modclk);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

177

return clk_get_rate(clk_parent) / (div + 1);

sys/arch/arm/sunxi/sun8i_crypto.c

459

aprint_debug_dev(self, ": clock freq %d\n", clk_get_rate(clk));

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

181

rate = clk_get_rate(clk_parent) / (clk_ratio + 1);

sys/arch/arm/sunxi/sunxi_can.c

187

sc->sc_timecaps.cltc_clock_freq = clk_get_rate(clk);

sys/arch/arm/sunxi/sunxi_ccu.c

163

return clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu.c

373

aprint_debug("%10u Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/sunxi/sunxi_ccu_div.c

120

const u_int rate = clk_get_rate(&clk_parent->base);

sys/arch/arm/sunxi/sunxi_ccu_div.c

159

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_div.c

77

rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

48

return clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

121

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

200

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

77

rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

89

rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

120

rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

138

parent_rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

77

rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

48

return clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

55

rate = clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_emac.c

1097

freq = clk_get_rate(sc->clk_ahb);

sys/arch/arm/sunxi/sunxi_gates.c

131

return clk_get_rate(clkp_parent);

sys/arch/arm/sunxi/sunxi_gates.c

201

aprint_debug("%10d Hz\n", clk_get_rate(&gate->base));

sys/arch/arm/sunxi/sunxi_gmacclk.c

181

if (rate == clk_get_rate(sc->sc_parent[GMAC_CLK_PIT_MII])) {

sys/arch/arm/sunxi/sunxi_gmacclk.c

185

} else if (rate == clk_get_rate(sc->sc_parent[GMAC_CLK_PIT_RGMII])) {

sys/arch/arm/sunxi/sunxi_gmacclk.c

202

return clk_get_rate(clk_parent);

sys/arch/arm/sunxi/sunxi_hdmi.c

875

parent_rate = clk_get_rate(clk_pll);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

374

const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0);

sys/arch/arm/sunxi/sunxi_hstimer.c

179

tc->tc_frequency = clk_get_rate(clk);

sys/arch/arm/sunxi/sunxi_pwm.c

212

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/sunxi/sunxi_rtc.c

525

u_int parent_rate = clk_get_rate(sc->sc_parent_clk);

sys/arch/arm/sunxi/sunxi_timer.c

218

const u_int rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/sunxi/sunxi_twi.c

174

sunxi_twi_set_clock(sc, clk_get_rate(clk), 100000);

sys/arch/arm/ti/am18xx_aclk.c

125

return clk_get_rate(sc->sc_parent_clk);

sys/arch/arm/ti/am18xx_pllc.c

205

u_int ref_clk_rate = clk_get_rate(sc->sc_ref_clk);

sys/arch/arm/ti/am18xx_pllc.c

226

return clk_get_rate(sc->sc_ref_clk);

sys/arch/arm/ti/am18xx_psc.c

220

return clk_get_rate(clk->u.clk_parent);

sys/arch/arm/ti/am18xx_usbphyclk.c

349

u_int ref_clk_rate = clk_get_rate(sc->sc_ref_clk);

sys/arch/arm/ti/ti_comp_clock.c

153

return clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_div_clock.c

202

parent_rate = clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_dpll_clock.c

262

parent_rate = clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_dpll_clock.c

287

parent_rate = clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_dpll_clock.c

329

parent_rate = clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_dpll_clock.c

373

parent_rate = clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_dpll_clock.c

394

parent_rate = clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_lcdc.c

170

const u_int rate = clk_get_rate(sc->sc_clk);

sys/arch/arm/ti/ti_mux_clock.c

180

return clk_get_rate(clk_parent);

sys/arch/arm/ti/ti_omaptimer.c

217

rate = clk_get_rate(hwmod);

sys/arch/arm/ti/ti_prcm.c

80

return clk_get_rate(clkp_parent);

sys/arch/arm/ti/ti_prcm.h

116

return (clk_get_rate(&tc_parent->base) * mult) / div;

sys/arch/arm/ti/ti_wdt.c

235

sc->sc_rate = clk_get_rate(clk);

sys/arch/arm/xilinx/zynq7000_clkc.c

424

clk_get_rate(&sc->sc_clk[clkid]));

sys/arch/riscv/sifive/fu540_prci.c

250

sc->sc_hfclk = clk_get_rate(clk);

sys/arch/riscv/sifive/fu540_prci.c

257

sc->sc_rtcclk = clk_get_rate(clk);

sys/arch/riscv/sifive/fu540_prci.c

279

clk_get_rate(&sc->sc_clk[clkid]));

sys/arch/riscv/starfive/jh7100_clkc.c

497

u_int osclk_rate = clk_get_rate(osclk);

sys/arch/riscv/starfive/jh7100_clkc.c

504

u_int oaclk_rate = clk_get_rate(oaclk);

sys/arch/riscv/starfive/jh7100_clkc.c

534

clk->name ? clk->name : "<none>", clk_get_rate(clk));

sys/arch/riscv/starfive/jh7100_gmac.c

68

u_int rate = clk_get_rate(jheth_sc->sc_clk_tx);

sys/arch/riscv/starfive/jh7110_clkc.c

1157

clk->name ? clk->name : "<none>", clk_get_rate(clk));

sys/arch/riscv/starfive/jh71x0_clkc.c

227

u_int rate = clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

253

u_int parent_rate = clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

297

u_int rate = clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

325

u_int parent_rate = clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

416

u_int rate = clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

442

u_int parent_rate = clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

576

return clk_get_rate(clk_parent);

sys/arch/riscv/starfive/jh71x0_clkc.c

74

return clk_get_rate(clk_parent);

sys/dev/clk/clk.c

241

if (clk_get_rate(clk) == rate)

sys/dev/clk/clk.c

98

rate = clk_get_rate(clk);

sys/dev/clk/clk.h

37

u_int clk_get_rate(struct clk *);

sys/dev/fdt/arasan_sdhc_fdt.c

122

return clk_get_rate(sc->sc_clk_xin);

sys/dev/fdt/arasan_sdhc_fdt.c

185

const u_int xin_rate = clk_get_rate(sc->sc_clk_xin);

sys/dev/fdt/arasan_sdhc_fdt.c

303

sc->sc_base.sc_clkbase = clk_get_rate(sc->sc_clk_xin) / 1000;

sys/dev/fdt/cpufreq_dt.c

110

old_rate = clk_get_rate(sc->sc_clk);

sys/dev/fdt/cpufreq_dt.c

175

sc->sc_freq_target = clk_get_rate(sc->sc_clk) / 1000000;

sys/dev/fdt/cpufreq_dt.c

216

sc->sc_freq_target = clk_get_rate(sc->sc_clk) / 1000000;

sys/dev/fdt/cpufreq_dt.c

219

fq = clk_get_rate(sc->sc_clk) / 1000000;

sys/dev/fdt/cpufreq_dt.c

90

ci->ci_data.cpu_cc_freq = clk_get_rate(sc->sc_clk);

sys/dev/fdt/dw_apb_uart.c

127

sc->sc_frequency = clk_get_rate(ssc->ssc_clk);

sys/dev/fdt/dwcmmc_fdt.c

250

sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu);

sys/dev/fdt/dwcwdt_fdt.c

95

sc->sc_clkrate = clk_get_rate(clk);

sys/dev/fdt/fixedfactorclock.c

170

return (clk_get_rate(clkp_parent) * fclk->mult) / fclk->div;

sys/dev/fdt/ns8250_uart.c

135

sc->sc_frequency = clk_get_rate(clk);

sys/dev/fdt/pcfiic_fdt.c

102

frequency = clk_get_rate(clk);

sys/dev/i2c/pca9685.c

549

sc->sc_clk_freq = clk_get_rate(clk);

sys/dev/ic/cdnsiic.c

108

pclk = clk_get_rate(sc->sc_pclk);