sys/arch/arm64/dev/apldart.c

372

HWRITE4(sc, DART_TCR(sc, sid), sc->sc_tcr_bypass);

sys/arch/arm64/dev/apldart.c

404

HWRITE4(sc, DART_TCR(sc, sid), 0);

sys/arch/arm64/dev/apldart.c

409

HWRITE4(sc, DART_TTBR(sc, sid, idx), 0);

sys/arch/arm64/dev/apldart.c

415

HWRITE4(sc, DART_T8110_ERROR, HREAD4(sc, DART_T8110_ERROR));

sys/arch/arm64/dev/apldart.c

416

HWRITE4(sc, DART_T8110_ERROR_MASK, 0);

sys/arch/arm64/dev/apldart.c

420

HWRITE4(sc, DART_T8020_ERROR, HREAD4(sc, DART_T8020_ERROR));

sys/arch/arm64/dev/apldart.c

461

HWRITE4(sc, DART_TCR(sc, sid), sc->sc_tcr_bypass);

sys/arch/arm64/dev/apldart.c

475

HWRITE4(sc, DART_TTBR(sc, sid, idx),

sys/arch/arm64/dev/apldart.c

488

HWRITE4(sc, DART_SID_ENABLE(sc, sid / 32), mask);

sys/arch/arm64/dev/apldart.c

495

HWRITE4(sc, DART_TCR(sc, sid), sc->sc_tcr_translate_enable);

sys/arch/arm64/dev/apldart.c

499

HWRITE4(sc, DART_T8110_ERROR, HREAD4(sc, DART_T8110_ERROR));

sys/arch/arm64/dev/apldart.c

500

HWRITE4(sc, DART_T8110_ERROR_MASK, 0);

sys/arch/arm64/dev/apldart.c

502

HWRITE4(sc, DART_T8020_ERROR, HREAD4(sc, DART_T8020_ERROR));

sys/arch/arm64/dev/apldart.c

669

HWRITE4(sc, DART_TTBR(sc, sid, idx),

sys/arch/arm64/dev/apldart.c

678

HWRITE4(sc, DART_SID_ENABLE(sc, sid / 32), mask);

sys/arch/arm64/dev/apldart.c

681

HWRITE4(sc, DART_TCR(sc, sid), sc->sc_tcr_translate_enable);

sys/arch/arm64/dev/apldart.c

750

HWRITE4(sc, DART_T8020_TLB_SIDMASK, mask);

sys/arch/arm64/dev/apldart.c

751

HWRITE4(sc, DART_T8020_TLB_CMD, DART_T8020_TLB_CMD_FLUSH);

sys/arch/arm64/dev/apldart.c

768

HWRITE4(sc, DART_T8110_TLB_CMD, cmd);

sys/arch/arm64/dev/apldc.c

145

HWRITE4(sc, DC_IRQ_MASK, 0);

sys/arch/arm64/dev/apldc.c

146

HWRITE4(sc, DC_IRQ_STAT, 0xffffffff);

sys/arch/arm64/dev/apldc.c

186

HWRITE4(sc, DC_IRQ_STAT, stat);

sys/arch/arm64/dev/apldc.c

69

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/apldc.c

71

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/apldma.c

234

HWRITE4(sc, DMA_TX_DESC_WRITE(ac->ac_chan), addr);

sys/arch/arm64/dev/apldma.c

235

HWRITE4(sc, DMA_TX_DESC_WRITE(ac->ac_chan), addr >> 32);

sys/arch/arm64/dev/apldma.c

236

HWRITE4(sc, DMA_TX_DESC_WRITE(ac->ac_chan), ac->ac_blksize);

sys/arch/arm64/dev/apldma.c

237

HWRITE4(sc, DMA_TX_DESC_WRITE(ac->ac_chan), DMA_DESC_NOTIFY);

sys/arch/arm64/dev/apldma.c

258

HWRITE4(sc, DMA_TX_INTRSTAT(chan, sc->sc_irq), intrstat);

sys/arch/arm64/dev/apldma.c

385

HWRITE4(sc, DMA_TX_BUS_WIDTH(ac->ac_chan),

sys/arch/arm64/dev/apldma.c

389

HWRITE4(sc, DMA_TX_BUS_WIDTH(ac->ac_chan),

sys/arch/arm64/dev/apldma.c

395

HWRITE4(sc, DMA_TX_BURST_SIZE(ac->ac_chan), DMA_TX_BURST_SIZE_MAGIC);

sys/arch/arm64/dev/apldma.c

398

HWRITE4(sc, DMA_TX_CTL(ac->ac_chan), DMA_TX_CTL_RESET_RINGS);

sys/arch/arm64/dev/apldma.c

399

HWRITE4(sc, DMA_TX_CTL(ac->ac_chan), 0);

sys/arch/arm64/dev/apldma.c

402

HWRITE4(sc, DMA_TX_INTRSTAT(ac->ac_chan, sc->sc_irq),

sys/arch/arm64/dev/apldma.c

404

HWRITE4(sc, DMA_TX_INTRMASK(ac->ac_chan, sc->sc_irq),

sys/arch/arm64/dev/apldma.c

410

HWRITE4(sc, DMA_TX_EN, 1 << (ac->ac_chan / 2));

sys/arch/arm64/dev/apldma.c

421

HWRITE4(sc, DMA_TX_EN_CLR, 1 << (ac->ac_chan / 2));

sys/arch/arm64/dev/apldma.c

424

HWRITE4(sc, DMA_TX_INTRMASK(ac->ac_chan, sc->sc_irq), 0);

sys/arch/arm64/dev/apldog.c

101

HWRITE4(sc, WDT_CHIP_CTL, 0);

sys/arch/arm64/dev/apldog.c

102

HWRITE4(sc, WDT_SYS_CTL, 0);

sys/arch/arm64/dev/apldog.c

138

HWRITE4(sc, WDT_SYS_RST, WDT_SYS_RST_IMMEDIATE);

sys/arch/arm64/dev/apldog.c

139

HWRITE4(sc, WDT_SYS_CTL, WDT_SYS_CTL_ENABLE);

sys/arch/arm64/dev/apldog.c

140

HWRITE4(sc, WDT_SYS_TMR, 0);

sys/arch/arm64/dev/apldog.c

151

HWRITE4(sc, WDT_SYS_TMR, 0);

sys/arch/arm64/dev/apldog.c

154

HWRITE4(sc, WDT_SYS_CTL, 0);

sys/arch/arm64/dev/apldog.c

158

HWRITE4(sc, WDT_SYS_RST, period * sc->sc_clock_freq);

sys/arch/arm64/dev/apldog.c

160

HWRITE4(sc, WDT_SYS_CTL, WDT_SYS_CTL_ENABLE);

sys/arch/arm64/dev/apliic.c

138

HWRITE4(sc, I2C_CTL, sc->sc_clkdiv | I2C_CTL_MTR | I2C_CTL_MRR |

sys/arch/arm64/dev/apliic.c

171

HWRITE4(sc, I2C_SMSTA, reg);

sys/arch/arm64/dev/apliic.c

175

HWRITE4(sc, I2C_SMSTA, I2C_SMSTA_XEN);

sys/arch/arm64/dev/apliic.c

202

HWRITE4(sc, I2C_SMSTA, reg);

sys/arch/arm64/dev/apliic.c

205

HWRITE4(sc, I2C_MTXFIFO, I2C_MTXFIFO_START | addr << 1);

sys/arch/arm64/dev/apliic.c

207

HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)cmd)[i]);

sys/arch/arm64/dev/apliic.c

208

HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)cmd)[cmdlen - 1] |

sys/arch/arm64/dev/apliic.c

216

HWRITE4(sc, I2C_MTXFIFO, I2C_MTXFIFO_START | addr << 1 | 1);

sys/arch/arm64/dev/apliic.c

217

HWRITE4(sc, I2C_MTXFIFO, I2C_MTXFIFO_READ | buflen |

sys/arch/arm64/dev/apliic.c

230

HWRITE4(sc, I2C_MTXFIFO, I2C_MTXFIFO_START | addr << 1);

sys/arch/arm64/dev/apliic.c

232

HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)buf)[i]);

sys/arch/arm64/dev/apliic.c

233

HWRITE4(sc, I2C_MTXFIFO, ((uint8_t *)buf)[buflen - 1] |

sys/arch/arm64/dev/apliic.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/apliic.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplintc.c

132

HWRITE4(sc, AIC_SW_CLR(irq), AIC_SW_BIT(irq));

sys/arch/arm64/dev/aplintc.c

134

HWRITE4(sc, AIC2_SW_CLR(die, irq), AIC_SW_BIT(irq));

sys/arch/arm64/dev/aplintc.c

141

HWRITE4(sc, AIC_SW_SET(irq), AIC_SW_BIT(irq));

sys/arch/arm64/dev/aplintc.c

143

HWRITE4(sc, AIC2_SW_SET(die, irq), AIC_SW_BIT(irq));

sys/arch/arm64/dev/aplintc.c

150

HWRITE4(sc, AIC_MASK_CLR(irq), AIC_MASK_BIT(irq));

sys/arch/arm64/dev/aplintc.c

152

HWRITE4(sc, AIC2_MASK_CLR(die, irq), AIC_MASK_BIT(irq));

sys/arch/arm64/dev/aplintc.c

159

HWRITE4(sc, AIC_MASK_SET(irq), AIC_MASK_BIT(irq));

sys/arch/arm64/dev/aplintc.c

161

HWRITE4(sc, AIC2_MASK_SET(die, irq), AIC_MASK_BIT(irq));

sys/arch/arm64/dev/aplintc.c

603

HWRITE4(sc, AIC_TARGET_CPU(irq), 1);

sys/arch/arm64/dev/aplintc.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplintc.c

90

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplmca.c

101

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplmca.c

103

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplmca.c

279

HWRITE4(sc, MCA_SERDES_CONF(ad->ad_cluster, MCA_SERDES_TXA), conf);

sys/arch/arm64/dev/aplmca.c

282

HWRITE4(sc, MCA_PORT_CLOCK_SEL(port),

sys/arch/arm64/dev/aplmca.c

284

HWRITE4(sc, MCA_PORT_DATA_SEL(port),

sys/arch/arm64/dev/aplmca.c

286

HWRITE4(sc, MCA_PORT_ENABLE(port),

sys/arch/arm64/dev/aplmca.c

297

HWRITE4(sc, MCA_PORT_CLOCK_SEL(port),

sys/arch/arm64/dev/aplmca.c

299

HWRITE4(sc, MCA_PORT_DATA_SEL(port),

sys/arch/arm64/dev/aplmca.c

301

HWRITE4(sc, MCA_PORT_ENABLE(port),

sys/arch/arm64/dev/aplmca.c

402

HWRITE4(sc, MCA_SERDES_CONF(ad->ad_cluster, MCA_SERDES_TXA), conf);

sys/arch/arm64/dev/aplmca.c

484

HWRITE4(sc, MCA_SERDES_CONF(ad->ad_cluster, MCA_SERDES_TXA), conf);

sys/arch/arm64/dev/aplmca.c

485

HWRITE4(sc, MCA_SERDES_CHANMASK0(ad->ad_cluster, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplmca.c

487

HWRITE4(sc, MCA_SERDES_CHANMASK1(ad->ad_cluster, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplmca.c

489

HWRITE4(sc, MCA_SERDES_CHANMASK2(ad->ad_cluster, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplmca.c

491

HWRITE4(sc, MCA_SERDES_CHANMASK3(ad->ad_cluster, MCA_SERDES_TXA),

sys/arch/arm64/dev/aplmca.c

495

HWRITE4(sc, MCA_SYNCGEN_HI_PERIOD(ad->ad_cluster), period - 2);

sys/arch/arm64/dev/aplmca.c

496

HWRITE4(sc, MCA_SYNCGEN_LO_PERIOD(ad->ad_cluster), 0);

sys/arch/arm64/dev/aplmca.c

497

HWRITE4(sc, MCA_MCLK_CONF(ad->ad_cluster),

sys/arch/arm64/dev/aplmca.c

502

HWRITE4(sc, MCA_SYNCGEN_MCLK_SEL(ad->ad_cluster),

sys/arch/arm64/dev/aplnco.c

229

HWRITE4(sc, NCO_CTRL(idx), ctrl & ~NCO_CTRL_ENABLE);

sys/arch/arm64/dev/aplnco.c

230

HWRITE4(sc, NCO_DIV(idx), div);

sys/arch/arm64/dev/aplnco.c

231

HWRITE4(sc, NCO_INC1(idx), inc1);

sys/arch/arm64/dev/aplnco.c

232

HWRITE4(sc, NCO_INC2(idx), inc2);

sys/arch/arm64/dev/aplnco.c

233

HWRITE4(sc, NCO_CTRL(idx), ctrl);

sys/arch/arm64/dev/aplnco.c

47

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplnco.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpcie.c

764

HWRITE4(sc, tag | reg, data);

sys/arch/arm64/dev/aplpinctrl.c

210

HWRITE4(sc, GPIO_PIN(pin), reg);

sys/arch/arm64/dev/aplpinctrl.c

233

HWRITE4(sc, GPIO_PIN(pin), reg);

sys/arch/arm64/dev/aplpinctrl.c

296

HWRITE4(sc, GPIO_IRQ(0, base), status);

sys/arch/arm64/dev/aplpinctrl.c

377

HWRITE4(sc, GPIO_PIN(pin), reg);

sys/arch/arm64/dev/aplpinctrl.c

400

HWRITE4(sc, GPIO_PIN(ih->ih_irq), reg);

sys/arch/arm64/dev/aplpinctrl.c

439

HWRITE4(sc, GPIO_PIN(ih->ih_irq), reg);

sys/arch/arm64/dev/aplpinctrl.c

455

HWRITE4(sc, GPIO_PIN(ih->ih_irq), reg);

sys/arch/arm64/dev/aplpinctrl.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplpinctrl.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpmgr.c

188

HWRITE4(sc, ps->ps_offset, val);

sys/arch/arm64/dev/aplpmgr.c

215

HWRITE4(sc, ps->ps_offset, val | PMGR_DEV_DISABLE);

sys/arch/arm64/dev/aplpmgr.c

218

HWRITE4(sc, ps->ps_offset, val | PMGR_RESET);

sys/arch/arm64/dev/aplpmgr.c

222

HWRITE4(sc, ps->ps_offset, val & ~PMGR_RESET);

sys/arch/arm64/dev/aplpmgr.c

225

HWRITE4(sc, ps->ps_offset, val & ~PMGR_DEV_DISABLE);

sys/arch/arm64/dev/aplpwm.c

152

HWRITE4(sc, PWM_ON_CYCLES, on_cycles);

sys/arch/arm64/dev/aplpwm.c

153

HWRITE4(sc, PWM_OFF_CYCLES, off_cycles);

sys/arch/arm64/dev/aplpwm.c

154

HWRITE4(sc, PWM_CTRL, ctrl);

sys/arch/arm64/dev/aplrtk.c

103

HWRITE4(sc, CPU_CTRL, ctrl | CPU_CTRL_RUN);

sys/arch/arm64/dev/aplsart.c

143

HWRITE4(sc, SART2_ADDR(i), addr >> SART_ADDR_SHIFT);

sys/arch/arm64/dev/aplsart.c

144

HWRITE4(sc, SART2_CONFIG(i),

sys/arch/arm64/dev/aplsart.c

163

HWRITE4(sc, SART3_ADDR(i), addr >> SART_ADDR_SHIFT);

sys/arch/arm64/dev/aplsart.c

164

HWRITE4(sc, SART3_SIZE(i), size >> SART_SIZE_SHIFT);

sys/arch/arm64/dev/aplsart.c

165

HWRITE4(sc, SART3_CONFIG(i), SART3_CONFIG_FLAGS_ALLOW);

sys/arch/arm64/dev/aplsart.c

201

HWRITE4(sc, SART2_ADDR(i), 0);

sys/arch/arm64/dev/aplsart.c

202

HWRITE4(sc, SART2_CONFIG(i), 0);

sys/arch/arm64/dev/aplsart.c

218

HWRITE4(sc, SART3_ADDR(i), 0);

sys/arch/arm64/dev/aplsart.c

219

HWRITE4(sc, SART3_SIZE(i), 0);

sys/arch/arm64/dev/aplsart.c

220

HWRITE4(sc, SART3_CONFIG(i), 0);

sys/arch/arm64/dev/aplspi.c

100

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplspi.c

102

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplspi.c

155

HWRITE4(sc, SPI_PIN, SPI_PIN_CS);

sys/arch/arm64/dev/aplspi.c

185

HWRITE4(sc, SPI_CLKCFG, 0);

sys/arch/arm64/dev/aplspi.c

187

HWRITE4(sc, SPI_CLKDIV, aplspi_clkdiv(sc, conf->sc_freq));

sys/arch/arm64/dev/aplspi.c

188

HWRITE4(sc, SPI_CLKIDLE, 0);

sys/arch/arm64/dev/aplspi.c

190

HWRITE4(sc, SPI_CONFIG, SPI_CONFIG_EN);

sys/arch/arm64/dev/aplspi.c

191

HWRITE4(sc, SPI_CLKCFG, SPI_CLKCFG_EN);

sys/arch/arm64/dev/aplspi.c

217

HWRITE4(sc, SPI_PIN, on ? 0 : SPI_PIN_CS);

sys/arch/arm64/dev/aplspi.c

232

HWRITE4(sc, SPI_TXCNT, len);

sys/arch/arm64/dev/aplspi.c

233

HWRITE4(sc, SPI_RXCNT, len);

sys/arch/arm64/dev/aplspi.c

234

HWRITE4(sc, SPI_CONFIG, SPI_CONFIG_EN | SPI_CONFIG_PIOEN);

sys/arch/arm64/dev/aplspi.c

253

HWRITE4(sc, SPI_TXDATA, data);

sys/arch/arm64/dev/aplspi.c

259

HWRITE4(sc, SPI_CONFIG, SPI_CONFIG_EN);

sys/arch/arm64/dev/aplspi.c

261

HWRITE4(sc, SPI_STATUS, status);

sys/arch/arm64/dev/aplspmi.c

168

HWRITE4(sc, SPMI_CMD, SPMI_CMD_SID(sid) | cmd | SPMI_CMD_ADDR(addr) |

sys/arch/arm64/dev/aplspmi.c

198

HWRITE4(sc, SPMI_CMD, SPMI_CMD_SID(sid) | cmd | SPMI_CMD_ADDR(addr) |

sys/arch/arm64/dev/aplspmi.c

203

HWRITE4(sc, SPMI_CMD, data);

sys/arch/arm64/dev/bcm2712_mip.c

118

HWRITE4(sc, MIP_INT_MASKL_VPU, 0xffffffff);

sys/arch/arm64/dev/bcm2712_mip.c

119

HWRITE4(sc, MIP_INT_MASKH_VPU, 0xffffffff);

sys/arch/arm64/dev/bcm2712_mip.c

120

HWRITE4(sc, MIP_INT_CFGL_HOST, 0xffffffff);

sys/arch/arm64/dev/bcm2712_mip.c

121

HWRITE4(sc, MIP_INT_CFGH_HOST, 0xffffffff);

sys/arch/arm64/dev/bcm2712_mip.c

122

HWRITE4(sc, MIP_INT_MASKL_HOST, 0);

sys/arch/arm64/dev/bcm2712_mip.c

123

HWRITE4(sc, MIP_INT_MASKH_HOST, 0);

sys/arch/arm64/dev/bcm2712_mip.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/bcm2712_mip.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/rpiclock.c

277

HWRITE4(sc, base + PLL_SYS_FBDIV_INT - PLL_SYS_CS, 0);

sys/arch/arm64/dev/rpiclock.c

278

HWRITE4(sc, base + PLL_SYS_FBDIV_FRAC - PLL_SYS_CS, 0);

sys/arch/arm64/dev/rpiclock.c

303

HWRITE4(sc, base + PLL_SYS_FBDIV_INT - PLL_SYS_CS, fbdiv_int);

sys/arch/arm64/dev/rpiclock.c

304

HWRITE4(sc, base + PLL_SYS_FBDIV_FRAC - PLL_SYS_CS, fbdiv_frac);

sys/arch/arm64/dev/rpiclock.c

362

HWRITE4(sc, base + PLL_SYS_PRIM - PLL_SYS_CS, prim);

sys/arch/arm64/dev/rpiclock.c

401

HWRITE4(sc, base + PLL_SYS_SEC - PLL_SYS_CS, sec | PLL_SEC_RST);

sys/arch/arm64/dev/rpiclock.c

403

HWRITE4(sc, base + PLL_SYS_SEC - PLL_SYS_CS, sec);

sys/arch/arm64/dev/rpiclock.c

558

HWRITE4(sc, clk->ctrl_reg, ctrl);

sys/arch/arm64/dev/rpiclock.c

563

HWRITE4(sc, clk->div_int_reg, div);

sys/arch/arm64/dev/rpiclock.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/rpiclock.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/rpipwm.c

141

HWRITE4(sc, CHAN_CTRL(chan),

sys/arch/arm64/dev/rpipwm.c

168

HWRITE4(sc, CHAN_RANGE(chan), range);

sys/arch/arm64/dev/rpipwm.c

171

HWRITE4(sc, CHAN_DUTY(chan), duty);

sys/arch/arm64/dev/rpipwm.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/rpipwm.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exclock.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/exclock.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exgpio.c

250

HWRITE4(sc, GPXCON(bank->addr), reg);

sys/arch/armv7/exynos/exgpio.c

257

HWRITE4(sc, GPXDAT(bank->addr), reg);

sys/arch/armv7/exynos/exgpio.c

262

HWRITE4(sc, GPXPUD(bank->addr), reg);

sys/arch/armv7/exynos/exgpio.c

267

HWRITE4(sc, GPXDRV(bank->addr), reg);

sys/arch/armv7/exynos/exgpio.c

295

HWRITE4(ec->ec_sc, GPXCON(ec->ec_bank->addr), val);

sys/arch/armv7/exynos/exgpio.c

336

HWRITE4(ec->ec_sc, GPXDAT(ec->ec_bank->addr), reg);

sys/arch/armv7/exynos/exiic.c

100

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exiic.c

202

HWRITE4(sc, I2C_CON, sc->frequency);

sys/arch/armv7/exynos/exiic.c

230

HWRITE4(sc, I2C_STAT, 0);

sys/arch/armv7/exynos/exiic.c

231

HWRITE4(sc, I2C_ADD, 0);

sys/arch/armv7/exynos/exiic.c

232

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX

sys/arch/armv7/exynos/exiic.c

270

HWRITE4(sc, I2C_DS, addr);

sys/arch/armv7/exynos/exiic.c

272

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_TX

sys/arch/armv7/exynos/exiic.c

276

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX

sys/arch/armv7/exynos/exiic.c

287

HWRITE4(sc, I2C_DS, ((uint8_t *)cmdbuf)[i]);

sys/arch/armv7/exynos/exiic.c

298

HWRITE4(sc, I2C_DS, addr);

sys/arch/armv7/exynos/exiic.c

301

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX

sys/arch/armv7/exynos/exiic.c

322

HWRITE4(sc, I2C_DS, ((uint8_t *)databuf)[i]);

sys/arch/armv7/exynos/exiic.c

331

HWRITE4(sc, I2C_STAT, I2C_STAT_MODE_SEL_MASTER_RX

sys/arch/armv7/exynos/exiic.c

98

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/expower.c

36

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/expower.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/imx/imxtemp.c

66

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/imx/imxtemp.c

68

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvacc.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvacc.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvagc.c

33

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvagc.c

35

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvodog.c

38

HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) | (bits))

sys/arch/armv7/marvell/mvodog.c

40

HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvortc.c

166

HWRITE4(sc, RTC_STATUS, 0);

sys/arch/armv7/marvell/mvortc.c

167

HWRITE4(sc, RTC_STATUS, 0);

sys/arch/armv7/marvell/mvortc.c

168

HWRITE4(sc, reg, val);

sys/arch/armv7/marvell/mvpcie.c

394

HWRITE4(po, PCIE_STAT, (HREAD4(po, PCIE_STAT) &

sys/arch/armv7/marvell/mvpcie.c

400

HWRITE4(po, PCIE_CMD, HREAD4(po, PCIE_CMD) |

sys/arch/armv7/marvell/mvpcie.c

403

HWRITE4(po, PCIE_MASK, HREAD4(po, PCIE_MASK) |

sys/arch/armv7/marvell/mvpcie.c

454

HWRITE4(po, PCIE_BAR_CTRL(i), 0);

sys/arch/armv7/marvell/mvpcie.c

455

HWRITE4(po, PCIE_BAR_LO(i), 0);

sys/arch/armv7/marvell/mvpcie.c

456

HWRITE4(po, PCIE_BAR_HI(i), 0);

sys/arch/armv7/marvell/mvpcie.c

460

HWRITE4(po, PCIE_WIN04_CTRL(i), 0);

sys/arch/armv7/marvell/mvpcie.c

461

HWRITE4(po, PCIE_WIN04_BASE(i), 0);

sys/arch/armv7/marvell/mvpcie.c

462

HWRITE4(po, PCIE_WIN04_REMAP(i), 0);

sys/arch/armv7/marvell/mvpcie.c

465

HWRITE4(po, PCIE_WIN5_CTRL, 0);

sys/arch/armv7/marvell/mvpcie.c

466

HWRITE4(po, PCIE_WIN5_BASE, 0);

sys/arch/armv7/marvell/mvpcie.c

467

HWRITE4(po, PCIE_WIN5_REMAP, 0);

sys/arch/armv7/marvell/mvpcie.c

473

HWRITE4(po, PCIE_WIN04_BASE(i), PCIE_BASEADDR(win->base));

sys/arch/armv7/marvell/mvpcie.c

474

HWRITE4(po, PCIE_WIN04_REMAP(i), 0);

sys/arch/armv7/marvell/mvpcie.c

475

HWRITE4(po, PCIE_WIN04_CTRL(i),

sys/arch/armv7/marvell/mvpcie.c

487

HWRITE4(po, PCIE_BAR_LO(1), mvmbus_dram_info->cs[0].base);

sys/arch/armv7/marvell/mvpcie.c

488

HWRITE4(po, PCIE_BAR_HI(1), 0);

sys/arch/armv7/marvell/mvpcie.c

489

HWRITE4(po, PCIE_BAR_CTRL(1), PCIE_WINEN | PCIE_SIZE(size));

sys/arch/armv7/marvell/mvpcie.c

702

HWRITE4(po, PCIE_STAT, (HREAD4(po, PCIE_STAT) &

sys/arch/armv7/marvell/mvpcie.c

746

HWRITE4(po, PCIE_CONF_ADDR, PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(dev) |

sys/arch/armv7/marvell/mvpcie.c

767

HWRITE4(po, PCIE_CONF_ADDR, PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(dev) |

sys/arch/armv7/marvell/mvpcie.c

769

HWRITE4(po, PCIE_CONF_DATA, data);

sys/arch/armv7/marvell/mvpcie.c

82

HWRITE4((po), (reg), HREAD4((po), (reg)) | (bits))

sys/arch/armv7/marvell/mvpcie.c

84

HWRITE4((po), (reg), HREAD4((po), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvsysctrl.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvsysctrl.c

40

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvsysctrl.c

94

HWRITE4(sc, RSTOUTN, RSTOUTN_GLOBAL_SOFT_RSTOUT_EN);

sys/arch/armv7/marvell/mvsysctrl.c

95

HWRITE4(sc, SYSSOFTRST, SYSSOFTRST_GLOBAL_SOFT_RST);

sys/arch/armv7/omap/amdisplay.c

198

HWRITE4(sc, LCD_SYSCONFIG, reg);

sys/arch/armv7/omap/amdisplay.c

288

HWRITE4(sc, LCD_CTRL, reg);

sys/arch/armv7/omap/amdisplay.c

296

HWRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arch/armv7/omap/amdisplay.c

317

HWRITE4(sc, LCD_LCDDMA_CTRL, reg);

sys/arch/armv7/omap/amdisplay.c

320

HWRITE4(sc, LCD_LCDDMA_FB0, sc->sc_fb0_dma_segs[0].ds_addr);

sys/arch/armv7/omap/amdisplay.c

321

HWRITE4(sc, LCD_LCDDMA_FB0_CEIL, (sc->sc_fb0_dma_segs[0].ds_addr

sys/arch/armv7/omap/amdisplay.c

323

HWRITE4(sc, LCD_LCDDMA_FB1, sc->sc_fb0_dma_segs[0].ds_addr);

sys/arch/armv7/omap/amdisplay.c

324

HWRITE4(sc, LCD_LCDDMA_FB1_CEIL, (sc->sc_fb0_dma_segs[0].ds_addr

sys/arch/armv7/omap/amdisplay.c

332

HWRITE4(sc, LCD_IRQENABLE_SET, reg);

sys/arch/armv7/omap/amdisplay.c

399

HWRITE4(sc, LCD_IRQSTATUS, reg);

sys/arch/armv7/omap/amdisplay.c

424

HWRITE4(sc, LCD_LCDDMA_FB0, sc->sc_fb0_dma_segs[0].ds_addr);

sys/arch/armv7/omap/amdisplay.c

425

HWRITE4(sc, LCD_LCDDMA_FB0_CEIL, (sc->sc_fb0_dma_segs[0].ds_addr

sys/arch/armv7/omap/amdisplay.c

439

HWRITE4(sc, LCD_IRQSTATUS, 0xFFFFFFFF);

sys/arch/armv7/omap/amdisplay.c

453

HWRITE4(sc, LCD_IRQ_END, 0);

sys/arch/armv7/omap/amdisplay.c

552

HWRITE4(sc, LCD_RASTER_TIMING_0, timing0);

sys/arch/armv7/omap/amdisplay.c

553

HWRITE4(sc, LCD_RASTER_TIMING_1, timing1);

sys/arch/armv7/omap/amdisplay.c

554

HWRITE4(sc, LCD_RASTER_TIMING_2, timing2);

sys/arch/armv7/omap/amdisplay.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/amdisplay.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/omclock.c

150

HWRITE4(sc, base, reg);

sys/arch/armv7/omap/omclock.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/omclock.c

45

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/ommmc.c

1013

HWRITE4(sc, MMCHS_BLK, (blkcount << MMCHS_BLK_NBLK_SHIFT) |

sys/arch/armv7/omap/ommmc.c

1015

HWRITE4(sc, MMCHS_ARG, cmd->c_arg);

sys/arch/armv7/omap/ommmc.c

1016

HWRITE4(sc, MMCHS_CMD, command);

sys/arch/armv7/omap/ommmc.c

1092

HWRITE4(sc, MMCHS_DATA, *((uint32_t *)datap));

sys/arch/armv7/omap/ommmc.c

1103

HWRITE4(sc, MMCHS_DATA, rv);

sys/arch/armv7/omap/ommmc.c

1191

HWRITE4(sc, MMCHS_STAT, status);

sys/arch/armv7/omap/ommmc.c

226

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/ommmc.c

228

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/ommmc.c

531

HWRITE4(sc, MMCHS_IE, 0);

sys/arch/armv7/omap/ommmc.c

532

HWRITE4(sc, MMCHS_ISE, 0);

sys/arch/armv7/omap/ommmc.c

545

HWRITE4(sc, MMCHS_CMD, 0);

sys/arch/armv7/omap/ommmc.c

548

HWRITE4(sc, MMCHS_STAT, MMCHS_STAT_CC);

sys/arch/armv7/omap/ommmc.c

550

HWRITE4(sc, MMCHS_STAT, ~0);

sys/arch/armv7/omap/ommmc.c

565

HWRITE4(sc, MMCHS_IE, imask);

sys/arch/armv7/omap/ommmc.c

566

HWRITE4(sc, MMCHS_ISE, imask);

sys/arch/armv7/omap/ommmc.c

664

HWRITE4(sc, MMCHS_HCTL, reg);

sys/arch/armv7/omap/ommmc.c

749

HWRITE4(sc, MMCHS_SYSCTL, reg);

sys/arch/armv7/omap/ommmc.c

825

HWRITE4(sc, MMCHS_STAT, MMCHS_STAT_CIRQ);

sys/arch/armv7/omap/omrng.c

117

HWRITE4(sc, RNG_CONFIG, 0x21 << RNG_CONFIG_MIN_CYCLES_SHIFT |

sys/arch/armv7/omap/omrng.c

119

HWRITE4(sc, RNG_FRODETUNE, 0);

sys/arch/armv7/omap/omrng.c

120

HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK);

sys/arch/armv7/omap/omrng.c

121

HWRITE4(sc, RNG_ALARMCNT, 0xff << RNG_ALARMCNT_ALARM_TH_SHIFT |

sys/arch/armv7/omap/omrng.c

123

HWRITE4(sc, RNG_CONTROL, 0xff << RNG_CONTROL_START_CYCLES_SHIFT |

sys/arch/armv7/omap/omrng.c

139

HWRITE4(sc, RNG_ALARMMASK, 0);

sys/arch/armv7/omap/omrng.c

140

HWRITE4(sc, RNG_ALARMSTOP, 0);

sys/arch/armv7/omap/omrng.c

147

HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK);

sys/arch/armv7/omap/omrng.c

148

HWRITE4(sc, RNG_INTACK, RNG_INTACK_SHUTDOWN);

sys/arch/armv7/omap/omrng.c

153

HWRITE4(sc, RNG_INTACK, RNG_INTACK_READY);

sys/arch/armv7/omap/omrng.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/omrng.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/vexpress/pciecam.c

310

HWRITE4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3), data);

sys/arch/armv7/vexpress/pciecam.c

54

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/vexpress/pciecam.c

56

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/mpfclock.c

212

HWRITE4(sc, SUBBLK_CLOCK_CR, val);

sys/arch/riscv64/dev/mpfclock.c

216

HWRITE4(sc, SUBBLK_RESET_CR, val);

sys/arch/riscv64/dev/mpfclock.c

220

HWRITE4(sc, SUBBLK_RESET_CR, val);

sys/arch/riscv64/dev/mpfclock.c

224

HWRITE4(sc, SUBBLK_CLOCK_CR, val);

sys/arch/riscv64/dev/mpfclock.c

234

HWRITE4(sc, MSS_RESET_CR, 0xdead);

sys/arch/riscv64/dev/mpfgpio.c

167

HWRITE4(sc, MPFGPIO_CONFIG(pin), val);

sys/arch/riscv64/dev/mpfgpio.c

202

HWRITE4(sc, MPFGPIO_SET_BITS, (1U << (pin % 32)));

sys/arch/riscv64/dev/mpfgpio.c

204

HWRITE4(sc, MPFGPIO_CLEAR_BITS, (1U << (pin % 32)));

sys/arch/riscv64/dev/mpfiic.c

172

HWRITE4(sc, I2C_CTRL, sc->sc_ctrl);

sys/arch/riscv64/dev/mpfiic.c

173

HWRITE4(sc, I2C_CTRL, 0);

sys/arch/riscv64/dev/mpfiic.c

176

HWRITE4(sc, I2C_SLAVE0ADR, 0);

sys/arch/riscv64/dev/mpfiic.c

177

HWRITE4(sc, I2C_SLAVE1ADR, 0);

sys/arch/riscv64/dev/mpfiic.c

180

HWRITE4(sc, I2C_SMBUS, 0);

sys/arch/riscv64/dev/mpfiic.c

235

HWRITE4(sc, I2C_CTRL, sc->sc_ctrl | I2C_CTRL_STA);

sys/arch/riscv64/dev/mpfiic.c

257

HWRITE4(sc, I2C_CTRL, sc->sc_ctrl | I2C_CTRL_STO);

sys/arch/riscv64/dev/mpfiic.c

263

HWRITE4(sc, I2C_CTRL, 0);

sys/arch/riscv64/dev/mpfiic.c

290

HWRITE4(sc, I2C_DATA, (addr << 1) | mode);

sys/arch/riscv64/dev/mpfiic.c

291

HWRITE4(sc, I2C_CTRL, sc->sc_ctrl);

sys/arch/riscv64/dev/mpfiic.c

305

HWRITE4(sc, I2C_CTRL, sc->sc_ctrl | ack);

sys/arch/riscv64/dev/mpfiic.c

329

HWRITE4(sc, I2C_DATA, data);

sys/arch/riscv64/dev/mpfiic.c

330

HWRITE4(sc, I2C_CTRL, sc->sc_ctrl);

sys/arch/riscv64/dev/sfgpio.c

143

HWRITE4(sc, GPIO_RISE_IE, 0);

sys/arch/riscv64/dev/sfgpio.c

144

HWRITE4(sc, GPIO_FALL_IE, 0);

sys/arch/riscv64/dev/sfgpio.c

145

HWRITE4(sc, GPIO_HIGH_IE, 0);

sys/arch/riscv64/dev/sfgpio.c

146

HWRITE4(sc, GPIO_LOW_IE, 0);

sys/arch/riscv64/dev/sfgpio.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/sfgpio.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/sfuart.c

318

HWRITE4(sc, UART_DIV, div - 1);

sys/arch/riscv64/dev/sfuart.c

351

HWRITE4(sc, UART_TXDATA, getc(&tp->t_outq));

sys/arch/riscv64/dev/sfuart.c

401

HWRITE4(sc, UART_TXCTRL, UART_TXCTRL_TXEN |

sys/arch/riscv64/dev/sfuart.c

405

HWRITE4(sc, UART_RXCTRL, UART_RXCTRL_RXEN |

sys/arch/riscv64/dev/sfuart.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/sfuart.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtclock.c

139

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtclock.c

141

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtclock.c

403

HWRITE4(sc, APBC_TWSI8_CLK_RST,

sys/arch/riscv64/dev/smtclock.c

407

HWRITE4(sc, clock->reg, 0);

sys/arch/riscv64/dev/smtclock.c

447

HWRITE4(sc, APBC_TWSI8_CLK_RST,

sys/arch/riscv64/dev/smtclock.c

450

HWRITE4(sc, APBC_TWSI8_CLK_RST,

sys/arch/riscv64/dev/smtclock.c

468

HWRITE4(sc, reset->reg, val);

sys/arch/riscv64/dev/smtcomphy.c

207

HWRITE4(sc, PCIE_PU_PLL_1, val);

sys/arch/riscv64/dev/smtcomphy.c

212

HWRITE4(sc, PCIE_PU_ADDR_CLK_CFG(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

232

HWRITE4(sc, PCIE_PU_ADDR_CLK_CFG(0), val);

sys/arch/riscv64/dev/smtcomphy.c

237

HWRITE4(sc, PCIE_PU_PLL_1, val);

sys/arch/riscv64/dev/smtcomphy.c

252

HWRITE4(sc, PCIE_PU_ADDR_CLK_CFG(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

257

HWRITE4(sc, PCIE_RC_DONE_STATUS, val);

sys/arch/riscv64/dev/smtcomphy.c

262

HWRITE4(sc, PCIE_PU_PLL_1, val);

sys/arch/riscv64/dev/smtcomphy.c

266

HWRITE4(sc, PCIE_PU_PLL_2, val);

sys/arch/riscv64/dev/smtcomphy.c

297

HWRITE4(sc, USB3_TEST_CTRL, 0);

sys/arch/riscv64/dev/smtcomphy.c

315

HWRITE4(sc, PCIE_RX_REG1(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

319

HWRITE4(sc, PCIE_RX_REG2(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

325

HWRITE4(sc, PCIE_TX_REG1(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

331

HWRITE4(sc, PCIE_RC_CAL_REG2(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

333

HWRITE4(sc, PCIE_RC_CAL_REG2(lane), val);

sys/arch/riscv64/dev/smtcomphy.c

339

HWRITE4(sc, PCIE_LTSSM_DIS_ENTRY(lane), val);

sys/arch/riscv64/dev/smtgpio.c

175

HWRITE4(sc, offset + GPIO_PSR, (1U << pin));

sys/arch/riscv64/dev/smtgpio.c

177

HWRITE4(sc, offset + GPIO_PCR, (1U << pin));

sys/arch/riscv64/dev/smtgpio.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtgpio.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtiic.c

142

HWRITE4(sc, ICR, ICR_UR);

sys/arch/riscv64/dev/smtiic.c

144

HWRITE4(sc, ICR, 0);

sys/arch/riscv64/dev/smtiic.c

145

HWRITE4(sc, ISR, ISR_INIT);

sys/arch/riscv64/dev/smtiic.c

231

HWRITE4(sc, IDBR, addr << 1 | 1);

sys/arch/riscv64/dev/smtiic.c

233

HWRITE4(sc, IDBR, addr << 1);

sys/arch/riscv64/dev/smtiic.c

239

HWRITE4(sc, ISR, ISR_ITE);

sys/arch/riscv64/dev/smtiic.c

266

HWRITE4(sc, ISR, ISR_IRF);

sys/arch/riscv64/dev/smtiic.c

279

HWRITE4(sc, IDBR, val);

sys/arch/riscv64/dev/smtiic.c

286

HWRITE4(sc, ISR, ISR_ITE);

sys/arch/riscv64/dev/smtiic.c

81

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtiic.c

83

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfclock.c

1009

HWRITE4(sc, idx * 4, reg);

sys/arch/riscv64/dev/stfclock.c

1056

HWRITE4(sc, idx * 4, reg);

sys/arch/riscv64/dev/stfclock.c

184

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/stfclock.c

186

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfclock.c

596

HWRITE4(sc, idx * 4, reg);

sys/arch/riscv64/dev/stfpcie.c

364

HWRITE4(sc, IMASK_LOCAL, 0);

sys/arch/riscv64/dev/stfpcie.c

365

HWRITE4(sc, ISTATUS_LOCAL, 0xffffffff);

sys/arch/riscv64/dev/stfpcie.c

406

HWRITE4(sc, PCIE_PCI_IOV_DW0, reg);

sys/arch/riscv64/dev/stfpcie.c

418

HWRITE4(sc, GEN_SETTINGS, reg);

sys/arch/riscv64/dev/stfpcie.c

421

HWRITE4(sc, PCI_IDS_DW1,

sys/arch/riscv64/dev/stfpcie.c

428

HWRITE4(sc, PCIE_BAR_WIN, reg);

sys/arch/riscv64/dev/stfpcie.c

433

HWRITE4(sc, PMSG_SUPPORT_RX, reg);

sys/arch/riscv64/dev/stfpcie.c

436

HWRITE4(sc, ATR_AXI4_SLV0_SRCADDR_PARAM(0),

sys/arch/riscv64/dev/stfpcie.c

438

HWRITE4(sc, ATR_AXI4_SLV0_SRC_ADDR(0), cfg_base >> 32);

sys/arch/riscv64/dev/stfpcie.c

439

HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_LSB(0), 0);

sys/arch/riscv64/dev/stfpcie.c

440

HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_UDW(0), 0);

sys/arch/riscv64/dev/stfpcie.c

441

HWRITE4(sc, ATR_AXI4_SLV0_TRSL_PARAM(0), TRSL_ID_PCIE_CONFIG);

sys/arch/riscv64/dev/stfpcie.c

445

HWRITE4(sc, ATR_AXI4_SLV0_SRCADDR_PARAM(i + 1),

sys/arch/riscv64/dev/stfpcie.c

448

HWRITE4(sc, ATR_AXI4_SLV0_SRC_ADDR(i + 1),

sys/arch/riscv64/dev/stfpcie.c

450

HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_LSB(i + 1),

sys/arch/riscv64/dev/stfpcie.c

452

HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_UDW(i + 1),

sys/arch/riscv64/dev/stfpcie.c

454

HWRITE4(sc, ATR_AXI4_SLV0_TRSL_PARAM(i + 1),

sys/arch/riscv64/dev/stfpcie.c

497

HWRITE4(sc, IMASK_LOCAL, IMASK_INT_MSI);

sys/arch/riscv64/dev/stfpcie.c

596

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

614

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

629

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

641

HWRITE4(sc, IMASK_LOCAL, mask);

sys/arch/riscv64/dev/stfpcie.c

725

HWRITE4(sc, ISTATUS_MSI, status);

sys/arch/riscv64/dev/stfpcie.c

763

HWRITE4(sc, ISTATUS_LOCAL, status);

sys/arch/riscv64/dev/stfpciephy.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/stfpciephy.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfpciephy.c

92

HWRITE4(sc, PCIE_KVO_LEVEL, PCIE_KVO_FINE_TUNE_LEVEL);

sys/arch/riscv64/dev/stfpciephy.c

93

HWRITE4(sc, PCIE_KVO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNAL);

sys/arch/riscv64/dev/stfrng.c

109

HWRITE4(sc, RNG_ISTAT, 0xffffffff);

sys/arch/riscv64/dev/stfrng.c

111

HWRITE4(sc, RNG_MODE, RNG_MODE_R256);

sys/arch/riscv64/dev/stfrng.c

112

HWRITE4(sc, RNG_CTRL, RNG_CTRL_RESEED);

sys/arch/riscv64/dev/stfrng.c

128

HWRITE4(sc, RNG_ISTAT, RNG_ISTAT_RAND_RDY);

sys/arch/riscv64/dev/stfrng.c

140

HWRITE4(sc, RNG_CTRL, RNG_CTRL_RESEED);

sys/arch/riscv64/dev/stfrng.c

142

HWRITE4(sc, RNG_CTRL, RNG_CTRL_RANDOMIZE);

sys/arch/riscv64/dev/stftemp.c

105

HWRITE4(sc, TEMP, TEMP_PD);

sys/arch/riscv64/dev/stftemp.c

109

HWRITE4(sc, TEMP, 0);

sys/arch/riscv64/dev/stftemp.c

113

HWRITE4(sc, TEMP, TEMP_RSTN);

sys/arch/riscv64/dev/stftemp.c

117

HWRITE4(sc, TEMP, TEMP_RSTN | TEMP_RUN);

sys/arch/riscv64/dev/sxitimer.c

109

HWRITE4(sc, TMR_IRQ_EN, 0);

sys/arch/riscv64/dev/sxitimer.c

126

HWRITE4(sc, TMR0_INTV_VALUE, 0);

sys/arch/riscv64/dev/sxitimer.c

127

HWRITE4(sc, TMR0_CTRL, TMR0_MODE_SINGLE | TMR0_CLK_PRES_1 |

sys/arch/riscv64/dev/sxitimer.c

129

HWRITE4(sc, TMR_IRQ_STA, TMR0_IRQ_PEND);

sys/arch/riscv64/dev/sxitimer.c

130

HWRITE4(sc, TMR_IRQ_EN, TMR0_IRQ_EN);

sys/arch/riscv64/dev/sxitimer.c

147

HWRITE4(sc, TMR_IRQ_STA, TMR0_IRQ_PEND);

sys/arch/riscv64/dev/sxitimer.c

164

HWRITE4(sc, TMR0_INTV_VALUE, cycles);

sys/arch/riscv64/dev/sxitimer.c

165

HWRITE4(sc, TMR0_CTRL, TMR0_MODE_SINGLE | TMR0_CLK_PRES_1 |

sys/arch/riscv64/dev/sxitimer.c

174

HWRITE4(sc, TMR0_INTV_VALUE, 1);

sys/arch/riscv64/dev/sxitimer.c

175

HWRITE4(sc, TMR0_CTRL, TMR0_MODE_SINGLE | TMR0_CLK_PRES_1 |

sys/dev/acpi/dwgpio.c

266

HWRITE4(sc, GPIO_PORTS_EOI, status);

sys/dev/acpi/dwgpio.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/acpi/dwgpio.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/acpi/qcgpio.c

518

HWRITE4(sc, off + TLMM_GPIO_INTR_CFG(pin), reg);

sys/dev/acpi/qcgpio.c

568

HWRITE4(sc, off + TLMM_GPIO_INTR_STATUS(pin),

sys/dev/acpi/qcgpio.c

64

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/acpi/qcgpio.c

66

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/acpi/qciic.c

248

HWRITE4(sc, GENI_TX_FIFO, word);

sys/dev/acpi/qciic.c

272

HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);

sys/dev/acpi/qciic.c

273

HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen);

sys/dev/acpi/qciic.c

275

HWRITE4(sc, GENI_M_CMD0, m_cmd);

sys/dev/acpi/qciic.c

294

HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);

sys/dev/acpi/qciic.c

295

HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen);

sys/dev/acpi/qciic.c

297

HWRITE4(sc, GENI_M_CMD0, m_cmd);

sys/dev/acpi/qciic.c

308

HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);

sys/dev/acpi/qciic.c

309

HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen);

sys/dev/acpi/qciic.c

311

HWRITE4(sc, GENI_M_CMD0, m_cmd);

sys/dev/fdt/amlclock.c

111

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlclock.c

113

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlclock.c

263

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

275

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

312

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

321

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

333

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

343

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

352

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

364

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

401

HWRITE4(sc, offset, reg);

sys/dev/fdt/amlclock.c

573

HWRITE4(sc, HHI_PCIE_PLL_CNTL0, 0x20090496);

sys/dev/fdt/amlclock.c

574

HWRITE4(sc, HHI_PCIE_PLL_CNTL0, 0x30090496);

sys/dev/fdt/amlclock.c

575

HWRITE4(sc, HHI_PCIE_PLL_CNTL1, 0x00000000);

sys/dev/fdt/amlclock.c

576

HWRITE4(sc, HHI_PCIE_PLL_CNTL2, 0x00001100);

sys/dev/fdt/amlclock.c

577

HWRITE4(sc, HHI_PCIE_PLL_CNTL3, 0x10058e00);

sys/dev/fdt/amlclock.c

578

HWRITE4(sc, HHI_PCIE_PLL_CNTL4, 0x000100c0);

sys/dev/fdt/amlclock.c

579

HWRITE4(sc, HHI_PCIE_PLL_CNTL5, 0x68000048);

sys/dev/fdt/amlclock.c

580

HWRITE4(sc, HHI_PCIE_PLL_CNTL5, 0x68000068);

sys/dev/fdt/amlclock.c

582

HWRITE4(sc, HHI_PCIE_PLL_CNTL4, 0x008100c0);

sys/dev/fdt/amlclock.c

584

HWRITE4(sc, HHI_PCIE_PLL_CNTL0, 0x34090496);

sys/dev/fdt/amlclock.c

585

HWRITE4(sc, HHI_PCIE_PLL_CNTL0, 0x14090496);

sys/dev/fdt/amlclock.c

587

HWRITE4(sc, HHI_PCIE_PLL_CNTL2, 0x00001000);

sys/dev/fdt/amldwusb.c

110

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amldwusb.c

112

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amldwusb.c

178

HWRITE4(sc, USB_R1, reg);

sys/dev/fdt/amldwusb.c

185

HWRITE4(sc, USB_R5, reg);

sys/dev/fdt/amldwusb.c

225

HWRITE4(sc, USB_R3, reg);

sys/dev/fdt/amldwusb.c

232

HWRITE4(sc, USB_R2, reg);

sys/dev/fdt/amldwusb.c

236

HWRITE4(sc, USB_R2, reg);

sys/dev/fdt/amldwusb.c

244

HWRITE4(sc, USB_R1, reg);

sys/dev/fdt/amliic.c

137

HWRITE4(sc, I2C_M_CONTROL, divh << I2C_M_CONTROL_QTR_CLK_EXT_SHIFT |

sys/dev/fdt/amliic.c

204

HWRITE4(sc, I2C_M_SLAVE_ADDRESS, addr << 1);

sys/dev/fdt/amliic.c

227

HWRITE4(sc, I2C_M_TOKEN_LIST0, tokens);

sys/dev/fdt/amliic.c

228

HWRITE4(sc, I2C_M_TOKEN_LIST1, tokens >> 32);

sys/dev/fdt/amliic.c

229

HWRITE4(sc, I2C_M_TOKEN_WDATA0, data);

sys/dev/fdt/amliic.c

230

HWRITE4(sc, I2C_M_TOKEN_WDATA1, data >> 32);

sys/dev/fdt/amliic.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amliic.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlmmc.c

113

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlmmc.c

115

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlmmc.c

275

HWRITE4(sc, SD_EMMC_CFG, cfg);

sys/dev/fdt/amlmmc.c

278

HWRITE4(sc, SD_EMMC_STATUS, SD_EMMC_STATUS_MASK);

sys/dev/fdt/amlmmc.c

279

HWRITE4(sc, SD_EMMC_IRQ_EN, SD_EMMC_IRQ_EN_MASK);

sys/dev/fdt/amlmmc.c

385

HWRITE4(sc, SD_EMMC_STATUS, status);

sys/dev/fdt/amlmmc.c

402

HWRITE4(sc, SD_EMMC_CFG, cfg);

sys/dev/fdt/amlmmc.c

545

HWRITE4(sc, SD_EMMC_CLOCK, clock);

sys/dev/fdt/amlmmc.c

575

HWRITE4(sc, SD_EMMC_CFG, cfg);

sys/dev/fdt/amlmmc.c

636

HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_START |

sys/dev/fdt/amlmmc.c

672

HWRITE4(sc, SD_EMMC_CMD_CFG, cmd_cfg);

sys/dev/fdt/amlmmc.c

673

HWRITE4(sc, SD_EMMC_CMD_DAT, data_addr);

sys/dev/fdt/amlmmc.c

674

HWRITE4(sc, SD_EMMC_CMD_RSP, 0);

sys/dev/fdt/amlmmc.c

677

HWRITE4(sc, SD_EMMC_CMD_ARG, cmd->c_arg);

sys/dev/fdt/amlmmc.c

733

HWRITE4(sc, SD_EMMC_START, SD_EMMC_START_STOP);

sys/dev/fdt/amlmmc.c

794

HWRITE4(sc, SD_EMMC_ADJUST, adjust);

sys/dev/fdt/amlmmc.c

799

HWRITE4(sc, SD_EMMC_ADJUST, adjust);

sys/dev/fdt/amlmmc.c

819

HWRITE4(sc, SD_EMMC_ADJUST, adjust);

sys/dev/fdt/amlpciephy.c

132

HWRITE4(sc, PHY_R0, reg);

sys/dev/fdt/amlpciephy.c

149

HWRITE4(sc, PHY_R0, reg);

sys/dev/fdt/amlpciephy.c

195

HWRITE4(sc, PHY_R4, addr << 2);

sys/dev/fdt/amlpciephy.c

196

HWRITE4(sc, PHY_R4, addr << 2);

sys/dev/fdt/amlpciephy.c

197

HWRITE4(sc, PHY_R4, (addr << 2) | PHY_R4_PHY_CR_CAP_ADDR);

sys/dev/fdt/amlpciephy.c

207

HWRITE4(sc, PHY_R4, addr << 2);

sys/dev/fdt/amlpciephy.c

226

HWRITE4(sc, PHY_R4, 0);

sys/dev/fdt/amlpciephy.c

227

HWRITE4(sc, PHY_R4, PHY_R4_PHY_CR_READ);

sys/dev/fdt/amlpciephy.c

238

HWRITE4(sc, PHY_R4, 0);

sys/dev/fdt/amlpciephy.c

257

HWRITE4(sc, PHY_R4, data << 2);

sys/dev/fdt/amlpciephy.c

258

HWRITE4(sc, PHY_R4, data << 2);

sys/dev/fdt/amlpciephy.c

259

HWRITE4(sc, PHY_R4, data << 2 | PHY_R4_PHY_CR_CAP_DATA);

sys/dev/fdt/amlpciephy.c

269

HWRITE4(sc, PHY_R4, data << 2);

sys/dev/fdt/amlpciephy.c

280

HWRITE4(sc, PHY_R4, data << 2);

sys/dev/fdt/amlpciephy.c

281

HWRITE4(sc, PHY_R4, data << 2 | PHY_R4_PHY_CR_WRITE);

sys/dev/fdt/amlpciephy.c

291

HWRITE4(sc, PHY_R4, data << 2);

sys/dev/fdt/amlpciephy.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpciephy.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpwm.c

218

HWRITE4(sc, PWM_MISC_REG_AB, misc);

sys/dev/fdt/amlpwm.c

219

HWRITE4(sc, (idx == 0) ? PWM_PWM_A : PWM_PWM_B, pwm);

sys/dev/fdt/amlpwm.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpwm.c

57

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpwrc.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpwrc.c

54

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlreset.c

40

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlreset.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amltemp.c

53

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amltemp.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amluart.c

192

HWRITE4(sc, UART_MISC, reg);

sys/dev/fdt/amluart.c

357

HWRITE4(sc, UART_WFIFO, getc(&tp->t_outq));

sys/dev/fdt/amluart.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amluart.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlusbphy.c

168

HWRITE4(sc, PHY_R16, (20 << PHY_R16_MPLL_M_SHIFT) |

sys/dev/fdt/amlusbphy.c

172

HWRITE4(sc, PHY_R17, (0 << PHY_R17_MPLL_FRAC_IN_SHIFT) |

sys/dev/fdt/amlusbphy.c

177

HWRITE4(sc, PHY_R18, (1 << PHY_R18_MPLL_LKW_SEL_SHIFT) |

sys/dev/fdt/amlusbphy.c

188

HWRITE4(sc, PHY_R16, (20 << PHY_R16_MPLL_M_SHIFT) |

sys/dev/fdt/amlusbphy.c

194

HWRITE4(sc, PHY_R20, (4 << PHY_R20_USB2_ITG_VBUS_TRIM_SHIFT) |

sys/dev/fdt/amlusbphy.c

201

HWRITE4(sc, PHY_R4, (0xfff << PHY_R4_CALIB_CODE_SHIFT) |

sys/dev/fdt/amlusbphy.c

206

HWRITE4(sc, PHY_R3, (0 << PHY_R3_SQUELCH_REF_SHIFT) |

sys/dev/fdt/amlusbphy.c

210

HWRITE4(sc, PHY_R14, 0);

sys/dev/fdt/amlusbphy.c

211

HWRITE4(sc, PHY_R13, PHY_R13_UPDATE_PMA_SIGNALS |

sys/dev/fdt/amlusbphy.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlusbphy.c

90

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2711_pcie.c

161

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcm2711_pcie.c

163

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2711_pcie.c

399

HWRITE4(sc, sc->sc_pcie_hard_debug, reg);

sys/dev/fdt/bcm2711_pcie.c

412

HWRITE4(sc, PCIE_MISC_MISC_CTRL, reg);

sys/dev/fdt/bcm2711_pcie.c

418

HWRITE4(sc, PCIE_RC_CFG_PRIV1_ID_VAL3, reg);

sys/dev/fdt/bcm2711_pcie.c

526

HWRITE4(sc, PCIE_RGR1_SW_INIT_1, reg);

sys/dev/fdt/bcm2711_pcie.c

533

HWRITE4(sc, PCIE_MISC_PCIE_CTRL, reg);

sys/dev/fdt/bcm2711_pcie.c

575

HWRITE4(sc, PCIE_MISC_AXI_READ_ERROR_DATA, 0xffffffff);

sys/dev/fdt/bcm2711_pcie.c

593

HWRITE4(sc, PCIE_RC_PL_PHY_CTL_15, reg);

sys/dev/fdt/bcm2711_pcie.c

615

HWRITE4(sc, sc->sc_pcie_hard_debug, reg);

sys/dev/fdt/bcm2711_pcie.c

622

HWRITE4(sc, PCIE_RC_CFG_PRIV1_ROOT_CAP, reg);

sys/dev/fdt/bcm2711_pcie.c

666

HWRITE4(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO,

sys/dev/fdt/bcm2711_pcie.c

668

HWRITE4(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI,

sys/dev/fdt/bcm2711_pcie.c

670

HWRITE4(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,

sys/dev/fdt/bcm2711_pcie.c

673

HWRITE4(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,

sys/dev/fdt/bcm2711_pcie.c

675

HWRITE4(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,

sys/dev/fdt/bcm2711_pcie.c

752

HWRITE4(sc, PCIE_MISC_RC_BAR1_CONFIG_LO + i * 8,

sys/dev/fdt/bcm2711_pcie.c

754

HWRITE4(sc, PCIE_MISC_RC_BAR1_CONFIG_HI + i * 8,

sys/dev/fdt/bcm2711_pcie.c

761

HWRITE4(sc, PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_LO + i * 8,

sys/dev/fdt/bcm2711_pcie.c

763

HWRITE4(sc, PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI + i * 8,

sys/dev/fdt/bcm2711_pcie.c

780

HWRITE4(sc, PCIE_MISC_MISC_CTRL, reg);

sys/dev/fdt/bcm2711_pcie.c

807

HWRITE4(sc, PCIE_RC_DL_MDIO_ADDR, reg);

sys/dev/fdt/bcm2711_pcie.c

836

HWRITE4(sc, PCIE_RC_DL_MDIO_ADDR, reg);

sys/dev/fdt/bcm2711_pcie.c

839

HWRITE4(sc, PCIE_RC_DL_MDIO_WR_DATA, data | PCIE_RC_DL_MDIO_DATA_DONE);

sys/dev/fdt/bcm2711_pcie.c

906

HWRITE4(sc, PCIE_EXT_CFG_INDEX, tag);

sys/dev/fdt/bcm2711_pcie.c

919

HWRITE4(sc, tag | reg, data);

sys/dev/fdt/bcm2711_pcie.c

923

HWRITE4(sc, PCIE_EXT_CFG_INDEX, tag);

sys/dev/fdt/bcm2711_pcie.c

924

HWRITE4(sc, PCIE_EXT_CFG_DATA + reg, data);

sys/dev/fdt/bcm2711_rng.c

92

HWRITE4(sc, RNG_CTRL, RNG_CTRL_RBGEN_EN);

sys/dev/fdt/bcm2835_bsc.c

142

HWRITE4(sc, BSC_DIV, div);

sys/dev/fdt/bcm2835_bsc.c

143

HWRITE4(sc, BSC_DEL, (fedl << BSC_DEL_FEDL_SHIFT) |

sys/dev/fdt/bcm2835_bsc.c

170

HWRITE4(sc, BSC_S, HREAD4(sc, BSC_S));

sys/dev/fdt/bcm2835_bsc.c

171

HWRITE4(sc, BSC_C, BSC_C_I2CEN | BSC_C_CLEAR);

sys/dev/fdt/bcm2835_bsc.c

180

HWRITE4(sc, BSC_C, BSC_C_CLEAR);

sys/dev/fdt/bcm2835_bsc.c

227

HWRITE4(sc, BSC_FIFO, buf[i]);

sys/dev/fdt/bcm2835_bsc.c

244

HWRITE4(sc, BSC_A, addr);

sys/dev/fdt/bcm2835_bsc.c

247

HWRITE4(sc, BSC_DLEN, cmdlen);

sys/dev/fdt/bcm2835_bsc.c

249

HWRITE4(sc, BSC_DLEN, cmdlen + buflen);

sys/dev/fdt/bcm2835_bsc.c

252

HWRITE4(sc, BSC_C, ctrl);

sys/dev/fdt/bcm2835_bsc.c

261

HWRITE4(sc, BSC_DLEN, buflen);

sys/dev/fdt/bcm2835_bsc.c

262

HWRITE4(sc, BSC_C, ctrl | BSC_C_READ);

sys/dev/fdt/bcm2835_bsc.c

268

HWRITE4(sc, BSC_C, ctrl);

sys/dev/fdt/bcm2835_dog.c

126

HWRITE4(sc, PM_RSTC, PM_RSTC_RESET | PM_PASSWORD);

sys/dev/fdt/bcm2835_dog.c

137

HWRITE4(sc, PM_WDOG, wdog);

sys/dev/fdt/bcm2835_dog.c

138

HWRITE4(sc, PM_RSTC, rstc);

sys/dev/fdt/bcm2835_dog.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcm2835_dog.c

51

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2835_gpio.c

157

HWRITE4(sc, GPFSEL(reg), val);

sys/dev/fdt/bcm2835_gpio.c

159

HWRITE4(sc, GPFSEL(reg), val);

sys/dev/fdt/bcm2835_gpio.c

173

HWRITE4(sc, GPPULL(reg), val);

sys/dev/fdt/bcm2835_gpio.c

182

HWRITE4(sc, GPPUD, pull & GPPUD_PUD);

sys/dev/fdt/bcm2835_gpio.c

184

HWRITE4(sc, GPPUDCLK(reg), 1 << shift);

sys/dev/fdt/bcm2835_gpio.c

186

HWRITE4(sc, GPPUDCLK(reg), 0);

sys/dev/fdt/bcm2835_gpio.c

288

HWRITE4(sc, GPSET(pin / 32), (1 << (pin % 32)));

sys/dev/fdt/bcm2835_gpio.c

290

HWRITE4(sc, GPCLR(pin / 32), (1 << (pin % 32)));

sys/dev/fdt/bcm2835_rng.c

91

HWRITE4(sc, RNG_STATUS, 250000);

sys/dev/fdt/bcm2835_rng.c

92

HWRITE4(sc, RNG_CTRL, RNG_CTRL_EN);

sys/dev/fdt/bcmstbgpio.c

136

HWRITE4(sc, GIO_MASK(bank), 0);

sys/dev/fdt/bcmstbgpio.c

252

HWRITE4(sc, GIO_STAT(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

260

HWRITE4(sc, GIO_STAT(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

369

HWRITE4(sc, GIO_EC(bank), ec);

sys/dev/fdt/bcmstbgpio.c

370

HWRITE4(sc, GIO_EI(bank), ei);

sys/dev/fdt/bcmstbgpio.c

371

HWRITE4(sc, GIO_LEVEL(bank), level);

sys/dev/fdt/bcmstbgpio.c

373

HWRITE4(sc, GIO_STAT(bank), 1U << pin);

sys/dev/fdt/bcmstbgpio.c

46

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbgpio.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbintc.c

122

HWRITE4(sc, INTR_MASK_SET, 0xffffffff);

sys/dev/fdt/bcmstbintc.c

220

HWRITE4(sc, INTR_MASK_CLEAR, 1U << ih->ih_irq);

sys/dev/fdt/bcmstbintc.c

231

HWRITE4(sc, INTR_MASK_SET, 1U << ih->ih_irq);

sys/dev/fdt/bcmstbintc.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbintc.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbpinctrl.c

201

HWRITE4(sc, sc->sc_pins[pin].func_reg * 4, val);

sys/dev/fdt/bcmstbpinctrl.c

207

HWRITE4(sc, sc->sc_pins[pin].bias_reg * 4, val);

sys/dev/fdt/bcmstbrescal.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbrescal.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbreset.c

108

HWRITE4(sc, SW_INIT_SET(bank), 1U << bit);

sys/dev/fdt/bcmstbreset.c

110

HWRITE4(sc, SW_INIT_CLR(bank), 1U << bit);

sys/dev/fdt/cdpcie.c

234

HWRITE4(sc, PCIE_LM_RC_BAR_CFG, PCIE_LM_RC_BAR_CFG_IO_ENABLE |

sys/dev/fdt/cdpcie.c

241

HWRITE4(sc, PCIE_LM_ID, PCI_ID_CODE(vendor_id, vendor_id));

sys/dev/fdt/cdpcie.c

246

HWRITE4(sc, PCIE_RP_BASE + PCI_ID_REG, id);

sys/dev/fdt/cdpcie.c

250

HWRITE4(sc, PCIE_RP_BASE + PCI_CLASS_REG,

sys/dev/fdt/cdpcie.c

258

HWRITE4(sc, PPB_REG_BUSINFO, bir);

sys/dev/fdt/cdpcie.c

275

HWRITE4(sc, PCI_COMMAND_STATUS_REG, csr);

sys/dev/fdt/cdpcie.c

328

HWRITE4(sc, PCIE_AT_OB_ADDR1(0), 0);

sys/dev/fdt/cdpcie.c

329

HWRITE4(sc, PCIE_AT_OB_DESC1(0), sc->sc_bus);

sys/dev/fdt/cdpcie.c

359

HWRITE4(sc, PPB_REG_IOSTATUS, blr);

sys/dev/fdt/cdpcie.c

362

HWRITE4(sc, PPB_REG_IO_HI, blr);

sys/dev/fdt/cdpcie.c

376

HWRITE4(sc, PPB_REG_MEM, blr);

sys/dev/fdt/cdpcie.c

390

HWRITE4(sc, PPB_REG_PREFMEM, blr);

sys/dev/fdt/cdpcie.c

391

HWRITE4(sc, PPB_REG_PREFBASE_HI32, pmembase >> 32);

sys/dev/fdt/cdpcie.c

392

HWRITE4(sc, PPB_REG_PREFLIM_HI32, pmemlimit >> 32);

sys/dev/fdt/cdpcie.c

402

HWRITE4(sc, PCIE_AT_OB_ADDR0(region),

sys/dev/fdt/cdpcie.c

404

HWRITE4(sc, PCIE_AT_OB_ADDR1(region),

sys/dev/fdt/cdpcie.c

406

HWRITE4(sc, PCIE_AT_OB_CPU_ADDR0(region),

sys/dev/fdt/cdpcie.c

408

HWRITE4(sc, PCIE_AT_OB_CPU_ADDR1(region),

sys/dev/fdt/cdpcie.c

410

HWRITE4(sc, PCIE_AT_OB_DESC0(region), PCIE_AT_HDR_RID | type);

sys/dev/fdt/cdpcie.c

411

HWRITE4(sc, PCIE_AT_OB_DESC1(region), sc->sc_bus);

sys/dev/fdt/cdpcie.c

416

HWRITE4(sc, PCIE_AT_IB_ADDR0(2), PCIE_AT_OB_ADDR0_NBITS(48));

sys/dev/fdt/cdpcie.c

417

HWRITE4(sc, PCIE_AT_IB_ADDR1(2), 0);

sys/dev/fdt/cdpcie.c

472

HWRITE4(sc, PCIE_AT_OB_ADDR0(0), PCIE_AT_OB_ADDR0_NBITS(12) | tag);

sys/dev/fdt/cdpcie.c

474

HWRITE4(sc, PCIE_AT_OB_DESC0(0),

sys/dev/fdt/cdpcie.c

477

HWRITE4(sc, PCIE_AT_OB_DESC0(0),

sys/dev/fdt/cdpcie.c

492

HWRITE4(sc, reg, data);

sys/dev/fdt/cdpcie.c

496

HWRITE4(sc, PCIE_AT_OB_ADDR0(0), PCIE_AT_OB_ADDR0_NBITS(12) | tag);

sys/dev/fdt/cdpcie.c

498

HWRITE4(sc, PCIE_AT_OB_DESC0(0),

sys/dev/fdt/cdpcie.c

501

HWRITE4(sc, PCIE_AT_OB_DESC0(0),

sys/dev/fdt/cdsdhc.c

167

HWRITE4(sc, HRS06, val);

sys/dev/fdt/dwdog.c

111

HWRITE4(sc, WDT_TORR, 0);

sys/dev/fdt/dwdog.c

115

HWRITE4(sc, WDT_CRR, WDT_CRR_KICK);

sys/dev/fdt/dwdog.c

46

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwdog.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwmmc.c

1148

HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR);

sys/dev/fdt/dwmmc.c

1155

HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap));

sys/dev/fdt/dwmmc.c

1165

HWRITE4(sc, SDMMC_FIFO_BASE, rv);

sys/dev/fdt/dwmmc.c

1167

HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR);

sys/dev/fdt/dwmmc.c

1189

HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_RXDR);

sys/dev/fdt/dwmmc.c

1196

HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap));

sys/dev/fdt/dwmmc.c

1199

HWRITE4(sc, SDMMC_FIFO_BASE + 4, *((uint32_t *)datap));

sys/dev/fdt/dwmmc.c

1211

HWRITE4(sc, SDMMC_FIFO_BASE, rv);

sys/dev/fdt/dwmmc.c

1218

HWRITE4(sc, SDMMC_FIFO_BASE + 4, rv);

sys/dev/fdt/dwmmc.c

1220

HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_TXDR);

sys/dev/fdt/dwmmc.c

161

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwmmc.c

163

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwmmc.c

403

HWRITE4(sc, SDMMC_INTMASK, 0);

sys/dev/fdt/dwmmc.c

404

HWRITE4(sc, SDMMC_RINTSTS, 0xffffffff);

sys/dev/fdt/dwmmc.c

503

HWRITE4(sc, SDMMC_IDSTS32, 0xffffffff);

sys/dev/fdt/dwmmc.c

504

HWRITE4(sc, SDMMC_IDINTEN32,

sys/dev/fdt/dwmmc.c

506

HWRITE4(sc, SDMMC_DBADDR, sc->sc_desc_map->dm_segs[0].ds_addr);

sys/dev/fdt/dwmmc.c

530

HWRITE4(sc, SDMMC_IDSTS64, 0xffffffff);

sys/dev/fdt/dwmmc.c

531

HWRITE4(sc, SDMMC_IDINTEN64,

sys/dev/fdt/dwmmc.c

533

HWRITE4(sc, SDMMC_DBADDRL, sc->sc_desc_map->dm_segs[0].ds_addr);

sys/dev/fdt/dwmmc.c

534

HWRITE4(sc, SDMMC_DBADDRH,

sys/dev/fdt/dwmmc.c

556

HWRITE4(sc, SDMMC_IDSTS(sc), stat);

sys/dev/fdt/dwmmc.c

564

HWRITE4(sc, SDMMC_RINTSTS, SDMMC_RINTSTS_SDIO);

sys/dev/fdt/dwmmc.c

666

HWRITE4(sc, SDMMC_CLKENA, 0);

sys/dev/fdt/dwmmc.c

667

HWRITE4(sc, SDMMC_CLKSRC, 0);

sys/dev/fdt/dwmmc.c

677

HWRITE4(sc, SDMMC_CLKDIV, div);

sys/dev/fdt/dwmmc.c

680

HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD |

sys/dev/fdt/dwmmc.c

696

HWRITE4(sc, SDMMC_CLKENA, clkena);

sys/dev/fdt/dwmmc.c

699

HWRITE4(sc, SDMMC_CMD, SDMMC_CMD_START_CMD |

sys/dev/fdt/dwmmc.c

747

HWRITE4(sc, SDMMC_FIFOTH, 2 << SDMMC_FIFOTH_MSIZE_SHIFT |

sys/dev/fdt/dwmmc.c

887

HWRITE4(sc, SDMMC_FIFOTH,

sys/dev/fdt/dwmmc.c

938

HWRITE4(sc, SDMMC_TMOUT, 0xffffffff);

sys/dev/fdt/dwmmc.c

939

HWRITE4(sc, SDMMC_BYTCNT, cmd->c_datalen);

sys/dev/fdt/dwmmc.c

940

HWRITE4(sc, SDMMC_BLKSIZ, cmd->c_blklen);

sys/dev/fdt/dwmmc.c

944

HWRITE4(sc, SDMMC_CARDTHRCTL,

sys/dev/fdt/dwmmc.c

975

HWRITE4(sc, SDMMC_PLDMND, 1);

sys/dev/fdt/dwmmc.c

986

HWRITE4(sc, SDMMC_RINTSTS, ~SDMMC_RINTSTS_SDIO);

sys/dev/fdt/dwmmc.c

988

HWRITE4(sc, SDMMC_CMDARG, cmd->c_arg);

sys/dev/fdt/dwmmc.c

989

HWRITE4(sc, SDMMC_CMD, cmdval | cmd->c_opcode);

sys/dev/fdt/dwpcie.c

1004

HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);

sys/dev/fdt/dwpcie.c

1006

HWRITE4(sc, PCIE_ARCACHE_TRC, PCIE_ARCACHE_TRC_DEFAULT);

sys/dev/fdt/dwpcie.c

1007

HWRITE4(sc, PCIE_AWCACHE_TRC, PCIE_AWCACHE_TRC_DEFAULT);

sys/dev/fdt/dwpcie.c

1011

HWRITE4(sc, PCIE_ARUSER, reg);

sys/dev/fdt/dwpcie.c

1015

HWRITE4(sc, PCIE_AWUSER, reg);

sys/dev/fdt/dwpcie.c

1020

HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);

sys/dev/fdt/dwpcie.c

1035

HWRITE4(sc, PCIE_GLOBAL_INT_MASK,

sys/dev/fdt/dwpcie.c

1061

HWRITE4(sc, PCIE_GLOBAL_INT_CAUSE, cause);

sys/dev/fdt/dwpcie.c

1296

HWRITE4(sc, 0x100000 + PCIE_RC_LCR, reg);

sys/dev/fdt/dwpcie.c

1303

HWRITE4(sc, PCIE_RC_LCR, reg);

sys/dev/fdt/dwpcie.c

1321

HWRITE4(sc, PCIE_RC_LCR, reg);

sys/dev/fdt/dwpcie.c

1325

HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg);

sys/dev/fdt/dwpcie.c

1342

HWRITE4(sc, PCIE_GLOBAL_INT_MASK,

sys/dev/fdt/dwpcie.c

1365

HWRITE4(sc, PCIE_GLOBAL_INT_CAUSE, cause);

sys/dev/fdt/dwpcie.c

1435

HWRITE4(sc, PCI_ID_REG,

sys/dev/fdt/dwpcie.c

1465

HWRITE4(sc, off + PCI_PCIE_LCAP, val);

sys/dev/fdt/dwpcie.c

1734

HWRITE4(sc, IATU_VIEWPORT, index);

sys/dev/fdt/dwpcie.c

1738

HWRITE4(sc, IATU_OFFSET_VIEWPORT + reg, val);

sys/dev/fdt/dwpcie.c

1750

HWRITE4(sc, IATU_VIEWPORT, index);

sys/dev/fdt/dwpcie.c

1917

HWRITE4(sc, PCITAG_OFFSET(tag) | reg, data);

sys/dev/fdt/dwpcie.c

195

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwpcie.c

197

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwpcie.c

647

HWRITE4(sc, PCI_CLASS_REG,

sys/dev/fdt/dwpcie.c

652

HWRITE4(sc, PCI_MAPREG_START, PCI_MAPREG_MEM_TYPE_64BIT);

sys/dev/fdt/dwpcie.c

653

HWRITE4(sc, PCI_MAPREG_START + 4, 0);

sys/dev/fdt/dwpcie.c

674

HWRITE4(sc, PPB_REG_BUSINFO, bir);

sys/dev/fdt/dwpcie.c

681

HWRITE4(sc, PPB_REG_MEM, blr);

sys/dev/fdt/dwpcie.c

689

HWRITE4(sc, PPB_REG_IOSTATUS, blr);

sys/dev/fdt/dwpcie.c

692

HWRITE4(sc, PPB_REG_IO_HI, blr);

sys/dev/fdt/dwpcie.c

694

HWRITE4(sc, PPB_REG_IOSTATUS, 0x000000ff);

sys/dev/fdt/dwpcie.c

695

HWRITE4(sc, PPB_REG_IO_HI, 0x0000ffff);

sys/dev/fdt/dwpcie.c

704

HWRITE4(sc, PPB_REG_PREFMEM, blr);

sys/dev/fdt/dwpcie.c

705

HWRITE4(sc, PPB_REG_PREFBASE_HI32, pmembase >> 32);

sys/dev/fdt/dwpcie.c

706

HWRITE4(sc, PPB_REG_PREFLIM_HI32, pmemlimit >> 32);

sys/dev/fdt/dwpcie.c

708

HWRITE4(sc, PPB_REG_PREFMEM, 0x0000ffff);

sys/dev/fdt/dwpcie.c

709

HWRITE4(sc, PPB_REG_PREFBASE_HI32, 0);

sys/dev/fdt/dwpcie.c

710

HWRITE4(sc, PPB_REG_PREFLIM_HI32, 0);

sys/dev/fdt/dwpcie.c

716

HWRITE4(sc, PCI_COMMAND_STATUS_REG, csr);

sys/dev/fdt/dwpcie.c

829

HWRITE4(sc, PCIE_PORT_LINK_CTRL, reg);

sys/dev/fdt/dwpcie.c

834

HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg);

sys/dev/fdt/dwpcie.c

838

HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg);

sys/dev/fdt/dwpcie.c

852

HWRITE4(sc, PCIE_MSI_INTR_STATUS(idx), status);

sys/dev/fdt/dwpcie.c

923

HWRITE4(sc, PCIE_MSI_ADDR_LO, addr);

sys/dev/fdt/dwpcie.c

924

HWRITE4(sc, PCIE_MSI_ADDR_HI, addr >> 32);

sys/dev/fdt/dwpcie.c

943

HWRITE4(sc, PCIE_MSI_INTR_ENABLE(idx), 0xffffffff);

sys/dev/fdt/dwpcie.c

944

HWRITE4(sc, PCIE_MSI_INTR_MASK(idx), 0xffffffff);

sys/dev/fdt/dwpcie.c

945

HWRITE4(sc, PCIE_MSI_INTR_STATUS(idx), 0xffffffff);

sys/dev/fdt/dwpcie.c

991

HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);

sys/dev/fdt/dwpcie.c

998

HWRITE4(sc, PCIE_STREAMID, PCIE_STREAMID_8040);

sys/dev/fdt/exrtc.c

137

HWRITE4(sc, RTCSEC, TOBCD(dt.dt_sec));

sys/dev/fdt/exrtc.c

138

HWRITE4(sc, RTCMIN, TOBCD(dt.dt_min));

sys/dev/fdt/exrtc.c

139

HWRITE4(sc, RTCHOUR, TOBCD(dt.dt_hour));

sys/dev/fdt/exrtc.c

140

HWRITE4(sc, RTCDAY, TOBCD(dt.dt_day));

sys/dev/fdt/exrtc.c

141

HWRITE4(sc, RTCMON, TOBCD(dt.dt_mon));

sys/dev/fdt/exrtc.c

142

HWRITE4(sc, RTCYEAR, TOBCD(dt.dt_year - 1900));

sys/dev/fdt/exrtc.c

145

HWRITE4(sc, RTCCTRL, val | RTCCTRL_RTCEN);

sys/dev/fdt/if_cad.c

1122

HWRITE4(sc, GEM_HASHL, hash);

sys/dev/fdt/if_cad.c

1123

HWRITE4(sc, GEM_HASHH, hash >> 32);

sys/dev/fdt/if_cad.c

1126

HWRITE4(sc, GEM_NETCFG, netcfg);

sys/dev/fdt/if_cad.c

1170

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_STARTTX);

sys/dev/fdt/if_cad.c

1187

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_STARTTX);

sys/dev/fdt/if_cad.c

1279

HWRITE4(sc, GEM_ISR, isr);

sys/dev/fdt/if_cad.c

1294

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_DPRAM);

sys/dev/fdt/if_cad.c

1301

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl);

sys/dev/fdt/if_cad.c

1302

HWRITE4(sc, GEM_IDR, ~0U);

sys/dev/fdt/if_cad.c

1553

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl & ~GEM_NETCTL_RXEN);

sys/dev/fdt/if_cad.c

1555

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl);

sys/dev/fdt/if_cad.c

1614

HWRITE4(sc, GEM_PHYMNTNC, oper);

sys/dev/fdt/if_cad.c

1675

HWRITE4(sc, GEM_NETCFG, netcfg);

sys/dev/fdt/if_cad.c

666

HWRITE4(sc, GEM_NETCTL, 0);

sys/dev/fdt/if_cad.c

667

HWRITE4(sc, GEM_IDR, ~0U);

sys/dev/fdt/if_cad.c

668

HWRITE4(sc, GEM_RXSR, 0);

sys/dev/fdt/if_cad.c

669

HWRITE4(sc, GEM_TXSR, 0);

sys/dev/fdt/if_cad.c

671

HWRITE4(sc, GEM_RXQBASEHI, 0);

sys/dev/fdt/if_cad.c

672

HWRITE4(sc, GEM_TXQBASEHI, 0);

sys/dev/fdt/if_cad.c

674

HWRITE4(sc, GEM_RXQBASE, 0);

sys/dev/fdt/if_cad.c

675

HWRITE4(sc, GEM_TXQBASE, 0);

sys/dev/fdt/if_cad.c

680

HWRITE4(sc, GEM_RXQ1BASE(i - 1), 0);

sys/dev/fdt/if_cad.c

682

HWRITE4(sc, GEM_RXQ8BASE(i - 8), 0);

sys/dev/fdt/if_cad.c

683

HWRITE4(sc, GEM_TXQ1BASE(i - 1), 0);

sys/dev/fdt/if_cad.c

689

HWRITE4(sc, GEM_SCR_TYPE1(i), 0);

sys/dev/fdt/if_cad.c

691

HWRITE4(sc, GEM_SCR_TYPE2(i), 0);

sys/dev/fdt/if_cad.c

704

HWRITE4(sc, GEM_NETCFG, netcfg);

sys/dev/fdt/if_cad.c

708

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl);

sys/dev/fdt/if_cad.c

798

HWRITE4(sc, GEM_TXQBASEHI, addr >> 32);

sys/dev/fdt/if_cad.c

799

HWRITE4(sc, GEM_TXQBASE, addr);

sys/dev/fdt/if_cad.c

805

HWRITE4(sc, GEM_TXQ1BASE(i - 1),

sys/dev/fdt/if_cad.c

866

HWRITE4(sc, GEM_RXQBASEHI, addr >> 32);

sys/dev/fdt/if_cad.c

867

HWRITE4(sc, GEM_RXQBASE, addr);

sys/dev/fdt/if_cad.c

874

HWRITE4(sc, GEM_RXQ1BASE(i - 1),

sys/dev/fdt/if_cad.c

877

HWRITE4(sc, GEM_RXQ8BASE(i - 8),

sys/dev/fdt/if_cad.c

889

HWRITE4(sc, GEM_LADDRL(0), sc->sc_ac.ac_enaddr[0] |

sys/dev/fdt/if_cad.c

893

HWRITE4(sc, GEM_LADDRH(0), sc->sc_ac.ac_enaddr[4] |

sys/dev/fdt/if_cad.c

897

HWRITE4(sc, GEM_LADDRL(i), 0);

sys/dev/fdt/if_cad.c

898

HWRITE4(sc, GEM_LADDRH(i), 0);

sys/dev/fdt/if_cad.c

921

HWRITE4(sc, GEM_NETCFG, val);

sys/dev/fdt/if_cad.c

947

HWRITE4(sc, GEM_DMACR, val);

sys/dev/fdt/if_cad.c

950

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl | GEM_NETCTL_STATCLR);

sys/dev/fdt/if_cad.c

954

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl);

sys/dev/fdt/if_cad.c

957

HWRITE4(sc, GEM_IER, GEM_IXR_HRESP | GEM_IXR_RXOVR | GEM_IXR_RXDONE |

sys/dev/fdt/if_cad.c

961

HWRITE4(sc, GEM_IER, GEM_IXR_RXUSED);

sys/dev/fdt/if_cad.c

995

HWRITE4(sc, GEM_NETCTL, sc->sc_netctl);

sys/dev/fdt/if_cad.c

998

HWRITE4(sc, GEM_IDR, ~0U);

sys/dev/fdt/if_fec.c

1014

HWRITE4(sc, ENET_EIR, status);

sys/dev/fdt/if_fec.c

1081

HWRITE4(sc, ENET_TDAR, ENET_TDAR_TDAR);

sys/dev/fdt/if_fec.c

1146

HWRITE4(sc, ENET_RDAR, ENET_RDAR_RDAR);

sys/dev/fdt/if_fec.c

1173

HWRITE4(sc, ENET_EIR, ENET_EIR_MII);

sys/dev/fdt/if_fec.c

1191

HWRITE4(sc, ENET_EIR, ENET_EIR_MII);

sys/dev/fdt/if_fec.c

1221

HWRITE4(sc, ENET_ECR, ecr);

sys/dev/fdt/if_fec.c

1222

HWRITE4(sc, ENET_RCR, rcr);

sys/dev/fdt/if_fec.c

143

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/if_fec.c

145

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/if_fec.c

358

HWRITE4(sc, ENET_EIMR, 0);

sys/dev/fdt/if_fec.c

359

HWRITE4(sc, ENET_EIR, 0xffffffff);

sys/dev/fdt/if_fec.c

441

HWRITE4(sc, ENET_MSCR, (sc->sc_phy_speed << 1) | 0x100);

sys/dev/fdt/if_fec.c

639

HWRITE4(sc, ENET_PALR,

sys/dev/fdt/if_fec.c

644

HWRITE4(sc, ENET_PAUR,

sys/dev/fdt/if_fec.c

649

HWRITE4(sc, ENET_EIR, 0xffffffff);

sys/dev/fdt/if_fec.c

652

HWRITE4(sc, ENET_MRBR, ENET_MAX_PKT_SIZE);

sys/dev/fdt/if_fec.c

668

HWRITE4(sc, ENET_TDSR, ENET_DMA_DVA(sc->sc_txring));

sys/dev/fdt/if_fec.c

669

HWRITE4(sc, ENET_RDSR, ENET_DMA_DVA(sc->sc_rxring));

sys/dev/fdt/if_fec.c

672

HWRITE4(sc, ENET_TCR, ENET_TCR_FDEN);

sys/dev/fdt/if_fec.c

679

HWRITE4(sc, ENET_RCR,

sys/dev/fdt/if_fec.c

683

HWRITE4(sc, ENET_MSCR, (sc->sc_phy_speed << 1) | 0x100);

sys/dev/fdt/if_fec.c

685

HWRITE4(sc, ENET_RACC, ENET_RACC_SHIFT16);

sys/dev/fdt/if_fec.c

686

HWRITE4(sc, ENET_FTRL, ENET_MAX_BUF_SIZE);

sys/dev/fdt/if_fec.c

689

HWRITE4(sc, ENET_RSEM, 0x84);

sys/dev/fdt/if_fec.c

690

HWRITE4(sc, ENET_RSFL, 16);

sys/dev/fdt/if_fec.c

691

HWRITE4(sc, ENET_RAEM, 8);

sys/dev/fdt/if_fec.c

692

HWRITE4(sc, ENET_RAFL, 8);

sys/dev/fdt/if_fec.c

693

HWRITE4(sc, ENET_OPD, 0xFFF0);

sys/dev/fdt/if_fec.c

696

HWRITE4(sc, ENET_TFWR, ENET_TFWR_STRFWD);

sys/dev/fdt/if_fec.c

706

HWRITE4(sc, ENET_ECR, ENET_ECR_ETHEREN | speed | ENET_ECR_DBSWP);

sys/dev/fdt/if_fec.c

713

HWRITE4(sc, ENET_RDAR, ENET_RDAR_RDAR);

sys/dev/fdt/if_fec.c

725

HWRITE4(sc, ENET_EIMR, ENET_EIR_TXF | ENET_EIR_RXF);

sys/dev/fdt/if_fec.c

751

HWRITE4(sc, ENET_MSCR, (sc->sc_phy_speed << 1) | 0x100);

sys/dev/fdt/if_fec.c

805

HWRITE4(sc, ENET_GAUR, (uint32_t)(ghash >> 32));

sys/dev/fdt/if_fec.c

806

HWRITE4(sc, ENET_GALR, (uint32_t)ghash);

sys/dev/fdt/if_fec.c

808

HWRITE4(sc, ENET_IAUR, (uint32_t)(ihash >> 32));

sys/dev/fdt/if_fec.c

809

HWRITE4(sc, ENET_IALR, (uint32_t)ihash);

sys/dev/fdt/if_fec.c

978

HWRITE4(sc, ENET_TDAR, ENET_TDAR_TDAR);

sys/dev/fdt/imxanatop.c

245

HWRITE4(ir->ir_sc, ir->ir_reg_offset, reg);

sys/dev/fdt/imxanatop.c

96

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxanatop.c

98

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxccm.c

1325

HWRITE4(sc, sc->sc_divs[idx].reg, reg);

sys/dev/fdt/imxccm.c

181

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxccm.c

183

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxccm.c

1838

HWRITE4(sc, sc->sc_divs[idx].reg, reg);

sys/dev/fdt/imxccm.c

1874

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1882

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1891

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1900

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1909

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1920

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1928

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1936

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1944

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1952

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1960

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1968

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1983

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

1991

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

2000

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

2009

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxccm.c

2018

HWRITE4(sc, sc->sc_muxs[idx].reg, mux);

sys/dev/fdt/imxesdhc.c

1095

HWRITE4(sc, SDHC_DATA_BUFF_ACC_PORT, *((uint32_t *)datap));

sys/dev/fdt/imxesdhc.c

1106

HWRITE4(sc, SDHC_DATA_BUFF_ACC_PORT, rv);

sys/dev/fdt/imxesdhc.c

1197

HWRITE4(sc, SDHC_INT_STATUS, status);

sys/dev/fdt/imxesdhc.c

225

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxesdhc.c

227

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxesdhc.c

571

HWRITE4(sc, SDHC_INT_STATUS_EN, 0);

sys/dev/fdt/imxesdhc.c

572

HWRITE4(sc, SDHC_INT_SIGNAL_EN, 0);

sys/dev/fdt/imxesdhc.c

596

HWRITE4(sc, SDHC_INT_STATUS_EN, imask);

sys/dev/fdt/imxesdhc.c

597

HWRITE4(sc, SDHC_INT_SIGNAL_EN, imask);

sys/dev/fdt/imxesdhc.c

606

HWRITE4(sc, SDHC_WTMK_LVL,

sys/dev/fdt/imxesdhc.c

750

HWRITE4(sc, SDHC_PROT_CTRL, reg);

sys/dev/fdt/imxesdhc.c

980

HWRITE4(sc, SDHC_ADMA_SYS_ADDR,

sys/dev/fdt/imxesdhc.c

989

HWRITE4(sc, SDHC_BLK_ATT, blkcount << SDHC_BLK_ATT_BLKCNT_SHIFT |

sys/dev/fdt/imxesdhc.c

991

HWRITE4(sc, SDHC_CMD_ARG, cmd->c_arg);

sys/dev/fdt/imxesdhc.c

992

HWRITE4(sc, SDHC_MIX_CTRL,

sys/dev/fdt/imxesdhc.c

994

HWRITE4(sc, SDHC_CMD_XFR_TYP, command);

sys/dev/fdt/imxpwm.c

192

HWRITE4(sc, PWM_CR, PWM_CR_SWR);

sys/dev/fdt/imxpwm.c

204

HWRITE4(sc, PWM_SAR, dcycles);

sys/dev/fdt/imxpwm.c

205

HWRITE4(sc, PWM_PR, pcycles);

sys/dev/fdt/imxpwm.c

209

HWRITE4(sc, PWM_CR, PWM_CR_PRESCALER(prescale) |

sys/dev/fdt/imxpwm.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxpwm.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxrtc.c

146

HWRITE4(sc, LPCR, cr);

sys/dev/fdt/imxrtc.c

153

HWRITE4(sc, LPSRTCMR, srtc >> 32);

sys/dev/fdt/imxrtc.c

154

HWRITE4(sc, LPSRTCLR, srtc & 0xffffffff);

sys/dev/fdt/imxrtc.c

158

HWRITE4(sc, LPCR, cr);

sys/dev/fdt/imxspi.c

126

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxspi.c

128

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxspi.c

196

HWRITE4(sc, SPI_INTREG, 0);

sys/dev/fdt/imxspi.c

197

HWRITE4(sc, SPI_STATREG, SPI_STATREG_TC);

sys/dev/fdt/imxspi.c

219

HWRITE4(sc, SPI_CONREG, 0);

sys/dev/fdt/imxspi.c

261

HWRITE4(sc, SPI_CONREG, conreg);

sys/dev/fdt/imxspi.c

262

HWRITE4(sc, SPI_TESTREG, HREAD4(sc, SPI_TESTREG) &

sys/dev/fdt/imxspi.c

264

HWRITE4(sc, SPI_CONFIGREG, configreg);

sys/dev/fdt/imxspi.c

350

HWRITE4(sc, SPI_TXDATA, out[i]);

sys/dev/fdt/imxspi.c

352

HWRITE4(sc, SPI_TXDATA, 0xff);

sys/dev/fdt/imxspi.c

372

HWRITE4(sc, SPI_STATREG, SPI_STATREG_TC);

sys/dev/fdt/imxspi.c

385

HWRITE4(sc, SPI_CONREG, 0);

sys/dev/fdt/imxspi.c

386

HWRITE4(sc, SPI_STATREG, SPI_STATREG_TC);

sys/dev/fdt/imxsrc.c

192

HWRITE4(sc, sc->sc_resets[idx].reg, reg);

sys/dev/fdt/imxsrc.c

97

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxsrc.c

99

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxtmu.c

140

HWRITE4(sc, TMU_MQ_TIER, 0);

sys/dev/fdt/imxtmu.c

141

HWRITE4(sc, TMU_MQ_TMTMIR, TMU_MQ_TMTMIR_DEFAULT);

sys/dev/fdt/imxtmu.c

142

HWRITE4(sc, TMU_MQ_TMR, 0);

sys/dev/fdt/imxtmu.c

148

HWRITE4(sc, TMU_MQ_TTR0CR, range[0]);

sys/dev/fdt/imxtmu.c

149

HWRITE4(sc, TMU_MQ_TTR1CR, range[1]);

sys/dev/fdt/imxtmu.c

150

HWRITE4(sc, TMU_MQ_TTR2CR, range[2]);

sys/dev/fdt/imxtmu.c

151

HWRITE4(sc, TMU_MQ_TTR3CR, range[3]);

sys/dev/fdt/imxtmu.c

161

HWRITE4(sc, TMU_MQ_TTCFGR, calibration[i + 0]);

sys/dev/fdt/imxtmu.c

162

HWRITE4(sc, TMU_MQ_TSCFGR, calibration[i + 1]);

sys/dev/fdt/imxtmu.c

166

HWRITE4(sc, TMU_MQ_TMR, TMU_MQ_TMR_SENSOR(sc->sc_sensorid) |

sys/dev/fdt/imxtmu.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxtmu.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mtxhci.c

202

HWRITE4(sc, MTXHCI_RESET, val);

sys/dev/fdt/mtxhci.c

205

HWRITE4(sc, MTXHCI_RESET, val);

sys/dev/fdt/mtxhci.c

211

HWRITE4(sc, MTXHCI_CFG_DEV, val);

sys/dev/fdt/mtxhci.c

216

HWRITE4(sc, MTXHCI_CFG_HOST, val);

sys/dev/fdt/mtxhci.c

225

HWRITE4(sc, MTXHCI_CFG_PCIE, val);

sys/dev/fdt/mtxhci.c

233

HWRITE4(sc, MTXHCI_USB3_PORT(i), val);

sys/dev/fdt/mtxhci.c

239

HWRITE4(sc, MTXHCI_USB2_PORT(i), val);

sys/dev/fdt/mvclock.c

36

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvclock.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvclock.c

418

HWRITE4(sc, PERIPH_CLK_DIS, reg);

sys/dev/fdt/mvdog.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvdog.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvgpio.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvgpio.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvicu.c

167

HWRITE4(sc, ICU_INT_CFG(i), 0);

sys/dev/fdt/mvicu.c

234

HWRITE4(sc, ICU_SETSPI_NSR_AL,

sys/dev/fdt/mvicu.c

236

HWRITE4(sc, ICU_SETSPI_NSR_AH,

sys/dev/fdt/mvicu.c

238

HWRITE4(sc, ICU_CLRSPI_NSR_AL,

sys/dev/fdt/mvicu.c

240

HWRITE4(sc, ICU_CLRSPI_NSR_AH,

sys/dev/fdt/mvicu.c

246

HWRITE4(sc, ICU_SET_SEI_AL, addr & 0xffffffff);

sys/dev/fdt/mvicu.c

247

HWRITE4(sc, ICU_SET_SEI_AH, addr >> 32);

sys/dev/fdt/mvicu.c

251

HWRITE4(sc, ICU_INT_CFG(idx), data | ICU_INT_ENABLE |

sys/dev/fdt/mvicu.c

256

HWRITE4(sc, ICU_INT_CFG(ICU_DEVICE_SATA0), data |

sys/dev/fdt/mvicu.c

259

HWRITE4(sc, ICU_INT_CFG(ICU_DEVICE_SATA1), data |

sys/dev/fdt/mviic.c

139

HWRITE4(sc, ICR, ICR_RESET);

sys/dev/fdt/mviic.c

140

HWRITE4(sc, ISR, ISR_INIT);

sys/dev/fdt/mviic.c

144

HWRITE4(sc, ICR, ICR_MSTA | ICR_GCD);

sys/dev/fdt/mviic.c

240

HWRITE4(sc, IDBR, addr << 1 | 1);

sys/dev/fdt/mviic.c

242

HWRITE4(sc, IDBR, addr << 1);

sys/dev/fdt/mviic.c

248

HWRITE4(sc, ISR, ISR_TXE);

sys/dev/fdt/mviic.c

274

HWRITE4(sc, ISR, ISR_RXF);

sys/dev/fdt/mviic.c

287

HWRITE4(sc, IDBR, val);

sys/dev/fdt/mviic.c

294

HWRITE4(sc, ISR, ISR_TXE);

sys/dev/fdt/mviic.c

89

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mviic.c

91

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvkpcie.c

132

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvkpcie.c

134

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvkpcie.c

379

HWRITE4(sc, CTRL_CORE_CONFIG, reg);

sys/dev/fdt/mvkpcie.c

383

HWRITE4(sc, PCIE_ERR_CAPCTL,

sys/dev/fdt/mvkpcie.c

389

HWRITE4(sc, PCIE_DEV_CTRL_STATS,

sys/dev/fdt/mvkpcie.c

393

HWRITE4(sc, PCIE_CORE_CTRL2,

sys/dev/fdt/mvkpcie.c

399

HWRITE4(sc, LMI_DEBUG_CTRL, reg);

sys/dev/fdt/mvkpcie.c

404

HWRITE4(sc, PCIE_CORE_CTRL0, reg);

sys/dev/fdt/mvkpcie.c

409

HWRITE4(sc, PCIE_CORE_CTRL0, reg);

sys/dev/fdt/mvkpcie.c

413

HWRITE4(sc, PCIE_CORE_ISR0_STATUS, PCIE_CORE_ISR0_MASK_ALL);

sys/dev/fdt/mvkpcie.c

414

HWRITE4(sc, PCIE_CORE_ISR1_STATUS, PCIE_CORE_ISR1_MASK_ALL);

sys/dev/fdt/mvkpcie.c

415

HWRITE4(sc, HOST_CTRL_INT_STATUS, HOST_CTRL_INT_MASK_ALL);

sys/dev/fdt/mvkpcie.c

417

HWRITE4(sc, PCIE_CORE_ISR0_MASK, PCIE_CORE_ISR0_MASK_ALL &

sys/dev/fdt/mvkpcie.c

419

HWRITE4(sc, PCIE_CORE_ISR1_MASK, PCIE_CORE_ISR1_MASK_ALL);

sys/dev/fdt/mvkpcie.c

420

HWRITE4(sc, PCIE_CORE_MSI_MASK, 0);

sys/dev/fdt/mvkpcie.c

421

HWRITE4(sc, HOST_CTRL_INT_MASK, HOST_CTRL_INT_MASK_ALL &

sys/dev/fdt/mvkpcie.c

442

HWRITE4(sc, PCIE_LINK_CTRL_STAT,

sys/dev/fdt/mvkpcie.c

449

HWRITE4(sc, PCIE_CORE_MSI_ADDR_LOW,

sys/dev/fdt/mvkpcie.c

451

HWRITE4(sc, PCIE_CORE_MSI_ADDR_HIGH,

sys/dev/fdt/mvkpcie.c

669

HWRITE4(sc, PIO_START, PIO_START_STOP);

sys/dev/fdt/mvkpcie.c

670

HWRITE4(sc, PIO_ISR, PIO_ISR_CLEAR);

sys/dev/fdt/mvkpcie.c

677

HWRITE4(sc, PIO_CTRL, reg);

sys/dev/fdt/mvkpcie.c

678

HWRITE4(sc, PIO_ADDR_LS, tag | off);

sys/dev/fdt/mvkpcie.c

679

HWRITE4(sc, PIO_ADDR_MS, 0);

sys/dev/fdt/mvkpcie.c

680

HWRITE4(sc, PIO_WR_DATA_STRB, PIO_WR_DATA_STRB_VALUE);

sys/dev/fdt/mvkpcie.c

681

HWRITE4(sc, PIO_START, PIO_START_START);

sys/dev/fdt/mvkpcie.c

712

HWRITE4(sc, PIO_START, PIO_START_STOP);

sys/dev/fdt/mvkpcie.c

713

HWRITE4(sc, PIO_ISR, PIO_ISR_CLEAR);

sys/dev/fdt/mvkpcie.c

720

HWRITE4(sc, PIO_CTRL, reg);

sys/dev/fdt/mvkpcie.c

721

HWRITE4(sc, PIO_ADDR_LS, tag | off);

sys/dev/fdt/mvkpcie.c

722

HWRITE4(sc, PIO_ADDR_MS, 0);

sys/dev/fdt/mvkpcie.c

723

HWRITE4(sc, PIO_WR_DATA, data);

sys/dev/fdt/mvkpcie.c

724

HWRITE4(sc, PIO_WR_DATA_STRB, PIO_WR_DATA_STRB_VALUE);

sys/dev/fdt/mvkpcie.c

725

HWRITE4(sc, PIO_START, PIO_START_START);

sys/dev/fdt/mvkpcie.c

885

HWRITE4(sc, PCIE_CORE_MSI_STATUS, (1 << i));

sys/dev/fdt/mvkpcie.c

896

HWRITE4(sc, PCIE_CORE_ISR0_STATUS, PCIE_CORE_ISR0_MASK_MSI_INT);

sys/dev/fdt/mvkpcie.c

910

HWRITE4(sc, PCIE_CORE_ISR1_STATUS, pending);

sys/dev/fdt/mvkpcie.c

912

HWRITE4(sc, HOST_CTRL_INT_STATUS, HOST_CTRL_INT_MASK_CORE_INT);

sys/dev/fdt/mvpinctrl.c

261

HWRITE4(sc, off, (HREAD4(sc, off) & ~(0xf << shift)) |

sys/dev/fdt/mvpinctrl.c

45

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvpinctrl.c

47

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvrng.c

107

HWRITE4(sc, RNG_CONFIG, 0x5 << RNG_CONFIG_MIN_CYCLES_SHIFT |

sys/dev/fdt/mvrng.c

109

HWRITE4(sc, RNG_FRODETUNE, 0);

sys/dev/fdt/mvrng.c

110

HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK);

sys/dev/fdt/mvrng.c

126

HWRITE4(sc, RNG_ALARMMASK, 0);

sys/dev/fdt/mvrng.c

127

HWRITE4(sc, RNG_ALARMSTOP, 0);

sys/dev/fdt/mvrng.c

134

HWRITE4(sc, RNG_FROENABLE, RNG_FROENABLE_MASK);

sys/dev/fdt/mvrng.c

135

HWRITE4(sc, RNG_STATUS, RNG_STATUS_SHUTDOWN);

sys/dev/fdt/mvrng.c

142

HWRITE4(sc, RNG_STATUS, RNG_STATUS_READY);

sys/dev/fdt/mvrng.c

53

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvrng.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvrtc.c

143

HWRITE4(sc, RTC_STATUS, 0);

sys/dev/fdt/mvrtc.c

144

HWRITE4(sc, RTC_STATUS, 0);

sys/dev/fdt/mvrtc.c

145

HWRITE4(sc, RTC_TIME, tv->tv_sec);

sys/dev/fdt/mvspi.c

247

HWRITE4(sc, SPI_DOUT, out[i]);

sys/dev/fdt/mvspi.c

249

HWRITE4(sc, SPI_DOUT, 0x0);

sys/dev/fdt/mvspi.c

86

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvspi.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvuart.c

331

HWRITE4(sc, MVUART_TSH, buf);

sys/dev/fdt/mvuart.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvuart.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/pciecam.c

336

HWRITE4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3), data);

sys/dev/fdt/pciecam.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/pciecam.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/pinctrl.c

177

HWRITE4(sc, reg, val);

sys/dev/fdt/qcaoss.c

129

HWRITE4(sc, AOSS_DESC_UCORE_LINK_STATE_ACK,

sys/dev/fdt/qcaoss.c

132

HWRITE4(sc, AOSS_DESC_MCORE_LINK_STATE, AOSS_STATE_UP);

sys/dev/fdt/qcaoss.c

145

HWRITE4(sc, AOSS_DESC_MCORE_CH_STATE, AOSS_STATE_UP);

sys/dev/fdt/qcaoss.c

158

HWRITE4(sc, AOSS_DESC_UCORE_CH_STATE_ACK, AOSS_STATE_UP);

sys/dev/fdt/qcaoss.c

193

HWRITE4(sc, sc->sc_offset + sizeof(uint32_t) + i, reg);

sys/dev/fdt/qcaoss.c

197

HWRITE4(sc, sc->sc_offset, len);

sys/dev/fdt/qcaoss.c

210

HWRITE4(sc, sc->sc_offset, 0);

sys/dev/fdt/qcgpio_fdt.c

322

HWRITE4(sc, TLMM_GPIO_INTR_CFG(pin), reg);

sys/dev/fdt/qcgpio_fdt.c

397

HWRITE4(sc, TLMM_GPIO_INTR_STATUS(pin),

sys/dev/fdt/qcgpio_fdt.c

57

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcgpio_fdt.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qciic_fdt.c

203

HWRITE4(sc, GENI_TX_FIFO, word);

sys/dev/fdt/qciic_fdt.c

227

HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);

sys/dev/fdt/qciic_fdt.c

228

HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, cmdlen);

sys/dev/fdt/qciic_fdt.c

230

HWRITE4(sc, GENI_M_CMD0, m_cmd);

sys/dev/fdt/qciic_fdt.c

249

HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);

sys/dev/fdt/qciic_fdt.c

250

HWRITE4(sc, GENI_I2C_RX_TRANS_LEN, buflen);

sys/dev/fdt/qciic_fdt.c

252

HWRITE4(sc, GENI_M_CMD0, m_cmd);

sys/dev/fdt/qciic_fdt.c

263

HWRITE4(sc, GENI_M_IRQ_CLEAR, stat);

sys/dev/fdt/qciic_fdt.c

264

HWRITE4(sc, GENI_I2C_TX_TRANS_LEN, buflen);

sys/dev/fdt/qciic_fdt.c

266

HWRITE4(sc, GENI_M_CMD0, m_cmd);

sys/dev/fdt/qcipcc.c

159

HWRITE4(sc, IPCC_RECV_SIGNAL_CLEAR, reg);

sys/dev/fdt/qcipcc.c

219

HWRITE4(sc, IPCC_RECV_SIGNAL_ENABLE,

sys/dev/fdt/qcipcc.c

230

HWRITE4(sc, IPCC_RECV_SIGNAL_DISABLE,

sys/dev/fdt/qcipcc.c

264

HWRITE4(sc, IPCC_SEND_ID,

sys/dev/fdt/qcmtx.c

106

HWRITE4(sc, QCMTX_OFF(idx), QCMTX_APPS_PROC_ID);

sys/dev/fdt/qcmtx.c

113

HWRITE4(sc, QCMTX_OFF(idx), 0);

sys/dev/fdt/qcpdc.c

172

HWRITE4(sc, PDC_INTR_CONFIG(pin), PDC_INTR_CONFIG_EDGE_RISING);

sys/dev/fdt/qcpdc.c

175

HWRITE4(sc, PDC_INTR_CONFIG(pin), PDC_INTR_CONFIG_EDGE_FALLING);

sys/dev/fdt/qcpdc.c

178

HWRITE4(sc, PDC_INTR_CONFIG(pin), PDC_INTR_CONFIG_EDGE_BOTH);

sys/dev/fdt/qcpdc.c

181

HWRITE4(sc, PDC_INTR_CONFIG(pin), PDC_INTR_CONFIG_LEVEL_HIGH);

sys/dev/fdt/qcpdc.c

184

HWRITE4(sc, PDC_INTR_CONFIG(pin), PDC_INTR_CONFIG_LEVEL_LOW);

sys/dev/fdt/qcpdc.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcpdc.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qcspmi.c

106

HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcspmi.c

108

HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qcspmi.c

399

HWRITE4(sc, QCSPMI_REG_OBSRVR,

sys/dev/fdt/qcspmi.c

473

HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +

sys/dev/fdt/qcspmi.c

480

HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +

sys/dev/fdt/qcspmi.c

486

HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) + SPMI_COMMAND,

sys/dev/fdt/qcspmi.c

571

HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, ih->ih_apid) +

sys/dev/fdt/qcspmi.c

601

HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, ih->ih_apid) +

sys/dev/fdt/qcspmi.c

670

HWRITE4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, ih->ih_apid) +

sys/dev/fdt/rkclock.c

1046

HWRITE4(sc, RK3288_CRU_SOFTRST_CON(idx / 16),

sys/dev/fdt/rkclock.c

1250

HWRITE4(sc, RK3308_CRU_CLKSEL_CON(0),

sys/dev/fdt/rkclock.c

1265

HWRITE4(sc, RK3308_CRU_CLKSEL_CON(0),

sys/dev/fdt/rkclock.c

1416

HWRITE4(sc, RK3308_CRU_CRU_MODE,

sys/dev/fdt/rkclock.c

1421

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

1426

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

1438

HWRITE4(sc, RK3308_CRU_CRU_MODE,

sys/dev/fdt/rkclock.c

1485

HWRITE4(sc, RK3308_CRU_CLKSEL_CON(2), 1 << 26 | (mux << 10));

sys/dev/fdt/rkclock.c

1486

HWRITE4(sc, RK3308_CRU_CLKSEL_CON(4), 0xffff0000 | div_con);

sys/dev/fdt/rkclock.c

1583

HWRITE4(sc, RK3308_CRU_SOFTRST_CON(idx / 16),

sys/dev/fdt/rkclock.c

1866

HWRITE4(sc, RK3328_CRU_CLKSEL_CON(0),

sys/dev/fdt/rkclock.c

1869

HWRITE4(sc, RK3328_CRU_CLKSEL_CON(1),

sys/dev/fdt/rkclock.c

1882

HWRITE4(sc, RK3328_CRU_CLKSEL_CON(0),

sys/dev/fdt/rkclock.c

1887

HWRITE4(sc, RK3328_CRU_CLKSEL_CON(1),

sys/dev/fdt/rkclock.c

2001

HWRITE4(sc, RK3328_CRU_CRU_MODE,

sys/dev/fdt/rkclock.c

2006

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

2011

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

2023

HWRITE4(sc, RK3328_CRU_CRU_MODE,

sys/dev/fdt/rkclock.c

2094

HWRITE4(sc, RK3328_CRU_CRU_MODE,

sys/dev/fdt/rkclock.c

2099

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

2104

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

2113

HWRITE4(sc, base + 0x0008, reg);

sys/dev/fdt/rkclock.c

2120

HWRITE4(sc, RK3328_CRU_CRU_MODE,

sys/dev/fdt/rkclock.c

2289

HWRITE4(sc, RK3328_CRU_SOFTRST_CON(idx / 16),

sys/dev/fdt/rkclock.c

2614

HWRITE4(sc, RK3399_CRU_CLKSEL_CON(2),

sys/dev/fdt/rkclock.c

262

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkclock.c

264

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkclock.c

2732

HWRITE4(sc, base + 0x000c,

sys/dev/fdt/rkclock.c

2737

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

2740

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

2753

HWRITE4(sc, base + 0x000c,

sys/dev/fdt/rkclock.c

2816

HWRITE4(sc, clksel,

sys/dev/fdt/rkclock.c

2821

HWRITE4(sc, clksel + 0x0004,

sys/dev/fdt/rkclock.c

2832

HWRITE4(sc, clksel,

sys/dev/fdt/rkclock.c

2837

HWRITE4(sc, clksel + 0x0004,

sys/dev/fdt/rkclock.c

2918

HWRITE4(sc, base, p1 << 16 | q1);

sys/dev/fdt/rkclock.c

3050

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(6), (1 << 5) << 16);

sys/dev/fdt/rkclock.c

3053

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(6), (1 << 6) << 16);

sys/dev/fdt/rkclock.c

3056

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(13), (1 << 4) << 16);

sys/dev/fdt/rkclock.c

3059

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(13), (1 << 5) << 16);

sys/dev/fdt/rkclock.c

3062

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(13), (1 << 6) << 16);

sys/dev/fdt/rkclock.c

3065

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(13), (1 << 7) << 16);

sys/dev/fdt/rkclock.c

3068

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(32), (1 << 0) << 16);

sys/dev/fdt/rkclock.c

3071

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(32), (1 << 2) << 16);

sys/dev/fdt/rkclock.c

3074

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(5), (1 << 5) << 16);

sys/dev/fdt/rkclock.c

3077

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(5), (1 << 8) << 16);

sys/dev/fdt/rkclock.c

3080

HWRITE4(sc, RK3399_CRU_CLKGATE_CON(5), (1 << 9) << 16);

sys/dev/fdt/rkclock.c

3092

HWRITE4(sc, RK3399_CRU_SOFTRST_CON(idx / 16),

sys/dev/fdt/rkclock.c

3399

HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

3778

HWRITE4(sc, RK3568_CRU_MODE_CON,

sys/dev/fdt/rkclock.c

3783

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

3788

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

3800

HWRITE4(sc, RK3568_CRU_MODE_CON,

sys/dev/fdt/rkclock.c

3933

HWRITE4(sc, RK3568_CRU_SOFTRST_CON(idx / 16),

sys/dev/fdt/rkclock.c

4064

HWRITE4(sc, RK3568_PMUCRU_MODE_CON,

sys/dev/fdt/rkclock.c

4069

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

4074

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

4086

HWRITE4(sc, RK3568_PMUCRU_MODE_CON,

sys/dev/fdt/rkclock.c

4464

HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

5010

HWRITE4(sc, RK3588_CRU_MODE_CON,

sys/dev/fdt/rkclock.c

5014

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

5018

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

5020

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

5023

HWRITE4(sc, base + 0x0008,

sys/dev/fdt/rkclock.c

5027

HWRITE4(sc, base + 0x0004, RK3588_CRU_PLL_RESETB << 16);

sys/dev/fdt/rkclock.c

5034

HWRITE4(sc, RK3588_CRU_MODE_CON,

sys/dev/fdt/rkclock.c

5306

HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));

sys/dev/fdt/rkclock.c

665

HWRITE4(sc, clk->reg,

sys/dev/fdt/rkclock.c

696

HWRITE4(sc, clk->reg,

sys/dev/fdt/rkclock.c

725

HWRITE4(sc, clk->reg, clk->sel_mask << 16 | mux << shift);

sys/dev/fdt/rkclock.c

833

HWRITE4(sc, RK3288_CRU_MODE_CON,

sys/dev/fdt/rkclock.c

838

HWRITE4(sc, base + 0x000c,

sys/dev/fdt/rkclock.c

842

HWRITE4(sc, base + 0x0000,

sys/dev/fdt/rkclock.c

847

HWRITE4(sc, base + 0x0004,

sys/dev/fdt/rkclock.c

852

HWRITE4(sc, base + 0x000c,

sys/dev/fdt/rkclock.c

857

HWRITE4(sc, RK3288_CRU_MODE_CON,

sys/dev/fdt/rkclock.c

991

HWRITE4(sc, RK3288_CRU_CLKSEL_CON(0),

sys/dev/fdt/rkcomphy.c

108

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkcomphy.c

110

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkcomphy.c

187

HWRITE4(sc, COMBO_PIPE_PHY_REG(5), reg);

sys/dev/fdt/rkcomphy.c

192

HWRITE4(sc, COMBO_PIPE_PHY_REG(6), reg);

sys/dev/fdt/rkcomphy.c

195

HWRITE4(sc, COMBO_PIPE_PHY_REG(66), 0x570804f0);

sys/dev/fdt/rkcomphy.c

232

HWRITE4(sc, COMBO_PIPE_PHY_REG(6), reg);

sys/dev/fdt/rkcomphy.c

261

HWRITE4(sc, COMBO_PIPE_PHY_REG(32), reg);

sys/dev/fdt/rkcomphy.c

263

HWRITE4(sc, COMBO_PIPE_PHY_REG(11), COMBO_PIPE_PHY_PLL_LPF_ADJ_VALUE);

sys/dev/fdt/rkcomphy.c

268

HWRITE4(sc, COMBO_PIPE_PHY_REG(5), reg);

sys/dev/fdt/rkcomphy.c

270

HWRITE4(sc, COMBO_PIPE_PHY_REG(17), COMBO_PIPE_PHY_PLL_LOOP);

sys/dev/fdt/rkcomphy.c

271

HWRITE4(sc, COMBO_PIPE_PHY_REG(10), COMBO_PIPE_PHY_SU_TRIM_0_7);

sys/dev/fdt/rkcomphy.c

312

HWRITE4(sc, COMBO_PIPE_PHY_REG(31), reg);

sys/dev/fdt/rkcomphy.c

318

HWRITE4(sc, COMBO_PIPE_PHY_REG(14), reg);

sys/dev/fdt/rkcomphy.c

329

HWRITE4(sc, COMBO_PIPE_PHY_REG(6),

sys/dev/fdt/rkcomphy.c

362

HWRITE4(sc, COMBO_PIPE_PHY_REG(14), reg);

sys/dev/fdt/rkcomphy.c

366

HWRITE4(sc, COMBO_PIPE_PHY_REG(15), reg);

sys/dev/fdt/rkcomphy.c

386

HWRITE4(sc, COMBO_PIPE_PHY_REG(31), reg);

sys/dev/fdt/rkcomphy.c

419

HWRITE4(sc, COMBO_PIPE_PHY_REG(32), reg);

sys/dev/fdt/rkcomphy.c

421

HWRITE4(sc, COMBO_PIPE_PHY_REG(11), COMBO_PIPE_PHY_PLL_LPF_ADJ_VALUE);

sys/dev/fdt/rkcomphy.c

423

HWRITE4(sc, COMBO_PIPE_PHY_REG(27), COMBO_PIPE_PHY_RX_TRIM_RK3588);

sys/dev/fdt/rkcomphy.c

424

HWRITE4(sc, COMBO_PIPE_PHY_REG(10), COMBO_PIPE_PHY_SU_TRIM_0_7);

sys/dev/fdt/rkemmcphy.c

166

HWRITE4(sc, GRF_EMMCPHY_CON6, GRF_EMMCPHY_CON6_DR_CLR | impedance);

sys/dev/fdt/rkemmcphy.c

168

HWRITE4(sc, GRF_EMMCPHY_CON0,

sys/dev/fdt/rkemmcphy.c

170

HWRITE4(sc, GRF_EMMCPHY_CON0,

sys/dev/fdt/rkemmcphy.c

173

HWRITE4(sc, GRF_EMMCPHY_CON6,

sys/dev/fdt/rkemmcphy.c

178

HWRITE4(sc, GRF_EMMCPHY_CON6, GRF_EMMCPHY_CON6_PDB_CLR |

sys/dev/fdt/rkemmcphy.c

190

HWRITE4(sc, GRF_EMMCPHY_CON0, GRF_EMMCPHY_CON0_FREQSEL_CLR | freqsel);

sys/dev/fdt/rkemmcphy.c

191

HWRITE4(sc, GRF_EMMCPHY_CON6, GRF_EMMCPHY_CON6_ENDLL_CLR |

sys/dev/fdt/rkgpio.c

184

HWRITE4(sc, GPIO_INT_MASK_L, ~0);

sys/dev/fdt/rkgpio.c

185

HWRITE4(sc, GPIO_INT_MASK_H, ~0);

sys/dev/fdt/rkgpio.c

186

HWRITE4(sc, GPIO_INT_EN_L, ~0);

sys/dev/fdt/rkgpio.c

187

HWRITE4(sc, GPIO_INT_EN_H, ~0);

sys/dev/fdt/rkgpio.c

189

HWRITE4(sc, GPIO_INTMASK, ~0);

sys/dev/fdt/rkgpio.c

190

HWRITE4(sc, GPIO_INTEN, ~0);

sys/dev/fdt/rkgpio.c

219

HWRITE4(sc, GPIO_SWPORT_DDR_L + (pin / 16) * 4, reg);

sys/dev/fdt/rkgpio.c

267

HWRITE4(sc, GPIO_SWPORT_DR_L + (pin / 16) * 4, reg);

sys/dev/fdt/rkgpio.c

304

HWRITE4(sc, GPIO_PORT_EOI_L,

sys/dev/fdt/rkgpio.c

306

HWRITE4(sc, GPIO_PORT_EOI_H,

sys/dev/fdt/rkgpio.c

309

HWRITE4(sc, GPIO_PORTS_EOI, status);

sys/dev/fdt/rkgpio.c

365

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

366

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

369

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

370

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

373

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

374

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask | bit);

sys/dev/fdt/rkgpio.c

377

HWRITE4(sc, GPIO_INT_TYPE_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

378

HWRITE4(sc, GPIO_INT_POLARITY_L + off * 4, mask);

sys/dev/fdt/rkgpio.c

384

HWRITE4(sc, GPIO_SWPORT_DDR_L + off, mask);

sys/dev/fdt/rkgpio.c

385

HWRITE4(sc, GPIO_INT_MASK_L + off, mask);

sys/dev/fdt/rkgpio.c

434

HWRITE4(sc, GPIO_INT_MASK_L + off, mask | bit);

sys/dev/fdt/rkgpio.c

495

HWRITE4(sc, GPIO_INT_MASK_L + off, mask);

sys/dev/fdt/rkgpio.c

513

HWRITE4(sc, GPIO_INT_MASK_L + off, mask | bit);

sys/dev/fdt/rkgpio.c

76

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkgpio.c

78

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiic.c

160

HWRITE4(sc, RKI2C_CLKDIV, clkdivh << 16 | clkdivl);

sys/dev/fdt/rkiic.c

255

HWRITE4(sc, RKI2C_TXDATA0 + i,

sys/dev/fdt/rkiic.c

260

HWRITE4(sc, RKI2C_MTXCNT, len);

sys/dev/fdt/rkiic.c

283

HWRITE4(sc, RKI2C_MRXADDR, (addr << 1) | RKI2C_MRXADDR_ADDLVLD);

sys/dev/fdt/rkiic.c

291

HWRITE4(sc, RKI2C_MRXRADDR, mrxraddr);

sys/dev/fdt/rkiic.c

299

HWRITE4(sc, RKI2C_MRXCNT, MIN(buflen, 32));

sys/dev/fdt/rkiic.c

311

HWRITE4(sc, RKI2C_IPD, RKI2C_IPD_MBRF);

sys/dev/fdt/rkiic.c

328

HWRITE4(sc, RKI2C_CON, con);

sys/dev/fdt/rkiic.c

346

HWRITE4(sc, RKI2C_IPD, RKI2C_IPD_ALL);

sys/dev/fdt/rkiic.c

357

HWRITE4(sc, RKI2C_CON, con);

sys/dev/fdt/rkiic.c

74

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkiic.c

76

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiis.c

136

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkiis.c

138

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiis.c

321

HWRITE4(sc, I2S_TXDR, *pch->ch_cur);

sys/dev/fdt/rkiis.c

381

HWRITE4(sc, I2S_TXCR, txcr);

sys/dev/fdt/rkiis.c

382

HWRITE4(sc, I2S_RXCR, rxcr);

sys/dev/fdt/rkiis.c

406

HWRITE4(sc, I2S_CKR, ckr);

sys/dev/fdt/rkiis.c

462

HWRITE4(sc, I2S_CKR, ckr);

sys/dev/fdt/rkiis.c

493

HWRITE4(sc, I2S_TXCR, txcr);

sys/dev/fdt/rkiis.c

500

HWRITE4(sc, I2S_RXCR, rxcr);

sys/dev/fdt/rkiis.c

537

HWRITE4(sc, I2S_XFER, val);

sys/dev/fdt/rkiis.c

546

HWRITE4(sc, I2S_INTCR, val);

sys/dev/fdt/rkiis.c

576

HWRITE4(sc, I2S_XFER, val);

sys/dev/fdt/rkiis.c

581

HWRITE4(sc, I2S_INTCR, val);

sys/dev/fdt/rkiis.c

585

HWRITE4(sc, I2S_CLR, val);

sys/dev/fdt/rkiis.c

607

HWRITE4(sc, I2S_XFER, val);

sys/dev/fdt/rkiis.c

612

HWRITE4(sc, I2S_INTCR, val);

sys/dev/fdt/rkpcie.c

270

HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_MODE_SELECT_RC

sys/dev/fdt/rkpcie.c

287

HWRITE4(sc, PCIE_RC_LCSR2, status);

sys/dev/fdt/rkpcie.c

291

HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_LINK_TRAIN_EN);

sys/dev/fdt/rkpcie.c

308

HWRITE4(sc, PCIE_RC_LCSR, HREAD4(sc, PCIE_RC_LCSR) |

sys/dev/fdt/rkpcie.c

328

HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP);

sys/dev/fdt/rkpcie.c

329

HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG,

sys/dev/fdt/rkpcie.c

332

HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS);

sys/dev/fdt/rkpcie.c

337

HWRITE4(sc, PCIE_RC_PCIE_LCAP, status);

sys/dev/fdt/rkpcie.c

409

HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1);

sys/dev/fdt/rkpcie.c

410

HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0);

sys/dev/fdt/rkpcie.c

411

HWRITE4(sc, PCIE_ATR_OB_DESC0(0),

sys/dev/fdt/rkpcie.c

413

HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0);

sys/dev/fdt/rkpcie.c

457

HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1);

sys/dev/fdt/rkpcie.c

458

HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0);

sys/dev/fdt/rkpcie.c

459

HWRITE4(sc, PCIE_ATR_OB_DESC0(region),

sys/dev/fdt/rkpcie.c

461

HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0);

sys/dev/fdt/rkpcie.c

472

HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1);

sys/dev/fdt/rkpcie.c

473

HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0);

sys/dev/fdt/rkpcie.c

551

HWRITE4(sc, PCIE_RC_NORMAL_BASE + tag | reg, data);

sys/dev/fdt/rkpcie.c

627

HWRITE4(sc, PCIE_CLIENT_INT_MASK,

sys/dev/fdt/rkpwm.c

168

HWRITE4(sc, PWM_V2_PERIOD, cycles);

sys/dev/fdt/rkpwm.c

169

HWRITE4(sc, PWM_V2_DUTY, act_cycles);

sys/dev/fdt/rkpwm.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkpwm.c

51

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkrng.c

216

HWRITE4(sc, RNG_TRNG_CTRL, RNG_TRNG_CTRL_OSC_ENABLE |

sys/dev/fdt/rkrng.c

218

HWRITE4(sc, RNG_CTRL, (RNG_CTRL_START << 16) | RNG_CTRL_START);

sys/dev/fdt/rkrng.c

230

HWRITE4(sc, RNG_CTRL, (RNG_CTRL_START << 16) | 0);

sys/dev/fdt/rkrng.c

241

HWRITE4(sc, TRNG_SAMPLE_CNT, 100);

sys/dev/fdt/rkrng.c

242

HWRITE4(sc, TRNG_CTL, (ctl_m << 16) | ctl_v);

sys/dev/fdt/rkrng.c

256

HWRITE4(sc, TRNG_CTL, (ctl_m << 16) | 0);

sys/dev/fdt/rkrng.c

277

HWRITE4(sc, TRNG_V1_ISTAT, HREAD4(sc, TRNG_V1_ISTAT));

sys/dev/fdt/rkrng.c

278

HWRITE4(sc, TRNG_V1_AUTO_RQSTS, 1000);

sys/dev/fdt/rkrng.c

286

HWRITE4(sc, TRNG_V1_ISTAT, HREAD4(sc, TRNG_V1_ISTAT));

sys/dev/fdt/rkrng.c

287

HWRITE4(sc, TRNG_V1_MODE, TRNG_V1_MODE_256_BIT);

sys/dev/fdt/rkrng.c

288

HWRITE4(sc, TRNG_V1_CTRL, TRNG_V1_CTRL_RAND);

sys/dev/fdt/rkrng.c

300

HWRITE4(sc, TRNG_V1_ISTAT, HREAD4(sc, TRNG_V1_ISTAT));

sys/dev/fdt/rkrng.c

301

HWRITE4(sc, TRNG_V1_CTRL, TRNG_V1_CTRL_NOP);

sys/dev/fdt/rkspi.c

123

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkspi.c

125

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkspi.c

171

HWRITE4(sc, SPI_ENR, 0);

sys/dev/fdt/rkspi.c

172

HWRITE4(sc, SPI_DMACR, 0);

sys/dev/fdt/rkspi.c

173

HWRITE4(sc, SPI_DMATDLR, 0);

sys/dev/fdt/rkspi.c

174

HWRITE4(sc, SPI_DMARDLR, 0);

sys/dev/fdt/rkspi.c

175

HWRITE4(sc, SPI_IPR, 0);

sys/dev/fdt/rkspi.c

176

HWRITE4(sc, SPI_IMR, 0);

sys/dev/fdt/rkspi.c

177

HWRITE4(sc, SPI_ICR, SPI_ICR_MASK);

sys/dev/fdt/rkspi.c

195

HWRITE4(sc, SPI_ENR, 0);

sys/dev/fdt/rkspi.c

196

HWRITE4(sc, SPI_IMR, 0);

sys/dev/fdt/rkspi.c

245

HWRITE4(sc, SPI_ENR, 0);

sys/dev/fdt/rkspi.c

246

HWRITE4(sc, SPI_SER, 0);

sys/dev/fdt/rkspi.c

247

HWRITE4(sc, SPI_CTRLR0, ctrlr0);

sys/dev/fdt/rkspi.c

248

HWRITE4(sc, SPI_BAUDR, div);

sys/dev/fdt/rkspi.c

281

HWRITE4(sc, SPI_CTRLR1, len - 1);

sys/dev/fdt/rkspi.c

286

HWRITE4(sc, SPI_ENR, 1);

sys/dev/fdt/rkspi.c

293

HWRITE4(sc, SPI_TXDR, out[i]);

sys/dev/fdt/rkspi.c

311

HWRITE4(sc, SPI_ENR, 0);

sys/dev/fdt/rkspi.c

318

HWRITE4(sc, SPI_ENR, 0);

sys/dev/fdt/rktcphy.c

109

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rktcphy.c

111

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rktcphy.c

250

HWRITE4(sc, PMA_CMN_CTRL1, 0x830);

sys/dev/fdt/rktcphy.c

252

HWRITE4(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90);

sys/dev/fdt/rktcphy.c

253

HWRITE4(sc, TX_RCVDET_EN_TMR(i), 0x960);

sys/dev/fdt/rktcphy.c

254

HWRITE4(sc, TX_RCVDET_ST_TMR(i), 0x30);

sys/dev/fdt/rktcphy.c

259

HWRITE4(sc, CMN_DIAG_HSCLK_SEL, reg);

sys/dev/fdt/rktcphy.c

262

HWRITE4(sc, CMN_PLL0_VCOCAL_INIT, 0xf0);

sys/dev/fdt/rktcphy.c

263

HWRITE4(sc, CMN_PLL0_VCOCAL_ITER, 0x18);

sys/dev/fdt/rktcphy.c

264

HWRITE4(sc, CMN_PLL0_INTDIV, 0xd0);

sys/dev/fdt/rktcphy.c

265

HWRITE4(sc, CMN_PLL0_FRACDIV, 0x4a4a);

sys/dev/fdt/rktcphy.c

266

HWRITE4(sc, CMN_PLL0_HIGH_THR, 0x34);

sys/dev/fdt/rktcphy.c

267

HWRITE4(sc, CMN_PLL0_SS_CTRL1, 0x1ee);

sys/dev/fdt/rktcphy.c

268

HWRITE4(sc, CMN_PLL0_SS_CTRL2, 0x7f03);

sys/dev/fdt/rktcphy.c

269

HWRITE4(sc, CMN_PLL0_DSM_DIAG, 0x20);

sys/dev/fdt/rktcphy.c

270

HWRITE4(sc, CMN_DIAG_PLL0_OVRD, 0);

sys/dev/fdt/rktcphy.c

271

HWRITE4(sc, CMN_DIAG_PLL0_FBH_OVRD, 0);

sys/dev/fdt/rktcphy.c

272

HWRITE4(sc, CMN_DIAG_PLL0_FBL_OVRD, 0);

sys/dev/fdt/rktcphy.c

273

HWRITE4(sc, CMN_DIAG_PLL0_V2I_TUNE, 0x7);

sys/dev/fdt/rktcphy.c

274

HWRITE4(sc, CMN_DIAG_PLL0_CP_TUNE, 0x45);

sys/dev/fdt/rktcphy.c

275

HWRITE4(sc, CMN_DIAG_PLL0_LF_PROG, 0x8);

sys/dev/fdt/rktcphy.c

278

HWRITE4(sc, TX_PSC_A0(0), 0x7799);

sys/dev/fdt/rktcphy.c

279

HWRITE4(sc, TX_PSC_A1(0), 0x7798);

sys/dev/fdt/rktcphy.c

280

HWRITE4(sc, TX_PSC_A2(0), 0x5098);

sys/dev/fdt/rktcphy.c

281

HWRITE4(sc, TX_PSC_A3(0), 0x5098);

sys/dev/fdt/rktcphy.c

282

HWRITE4(sc, TX_TXCC_MGNFS_MULT_000(0), 0x0);

sys/dev/fdt/rktcphy.c

283

HWRITE4(sc, XCVR_DIAG_BIDI_CTRL(0), 0xbf);

sys/dev/fdt/rktcphy.c

285

HWRITE4(sc, RX_PSC_A0(1), 0xa6fd);

sys/dev/fdt/rktcphy.c

286

HWRITE4(sc, RX_PSC_A1(1), 0xa6fd);

sys/dev/fdt/rktcphy.c

287

HWRITE4(sc, RX_PSC_A2(1), 0xa410);

sys/dev/fdt/rktcphy.c

288

HWRITE4(sc, RX_PSC_A3(1), 0x2410);

sys/dev/fdt/rktcphy.c

289

HWRITE4(sc, RX_PSC_CAL(1), 0x23ff);

sys/dev/fdt/rktcphy.c

290

HWRITE4(sc, RX_SIGDET_HL_FILT_TMR(1), 0x13);

sys/dev/fdt/rktcphy.c

291

HWRITE4(sc, RX_REE_CTRL_DATA_MASK(1), 0x03e7);

sys/dev/fdt/rktcphy.c

292

HWRITE4(sc, RX_DIAG_SIGDET_TUNE(1), 0x1004);

sys/dev/fdt/rktcphy.c

293

HWRITE4(sc, RX_PSC_RDY(1), 0x2010);

sys/dev/fdt/rktcphy.c

294

HWRITE4(sc, XCVR_DIAG_BIDI_CTRL(1), 0xfb);

sys/dev/fdt/rktcphy.c

296

HWRITE4(sc, PMA_LANE_CFG, PIN_ASSIGN_D_F);

sys/dev/fdt/rktcphy.c

298

HWRITE4(sc, DP_MODE_CTL, DP_MODE_ENTER_A2);

sys/dev/fdt/rktemp.c

425

HWRITE4(sc, TSADC_V3_AUTO_PERIOD, auto_period);

sys/dev/fdt/rktemp.c

426

HWRITE4(sc, TSADC_V3_AUTO_PERIOD_HT, auto_period_ht);

sys/dev/fdt/rktemp.c

427

HWRITE4(sc, TSADC_V3_HIGHT_INT_DEBOUNCE, 4);

sys/dev/fdt/rktemp.c

428

HWRITE4(sc, TSADC_V3_HIGHT_TSHUT_DEBOUNCE, 4);

sys/dev/fdt/rktemp.c

433

HWRITE4(sc, TSADC_AUTO_CON, auto_con);

sys/dev/fdt/rktemp.c

437

HWRITE4(sc, TSADC_V3_COMP_SHUT(i),

sys/dev/fdt/rktemp.c

439

HWRITE4(sc, TSADC_V3_AUTO_SRC,

sys/dev/fdt/rktemp.c

446

HWRITE4(sc, TSADC_V3_HLT_INT_PD,

sys/dev/fdt/rktemp.c

460

HWRITE4(sc, TSADC_V3_GPIO_EN, gpio_en);

sys/dev/fdt/rktemp.c

461

HWRITE4(sc, TSADC_V3_CRU_EN, cru_en);

sys/dev/fdt/rktemp.c

467

HWRITE4(sc, TSADC_USER_CON,

sys/dev/fdt/rktemp.c

469

HWRITE4(sc, TSADC_AUTO_PERIOD, auto_period);

sys/dev/fdt/rktemp.c

470

HWRITE4(sc, TSADC_AUTO_PERIOD_HT, auto_period_ht);

sys/dev/fdt/rktemp.c

471

HWRITE4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4);

sys/dev/fdt/rktemp.c

472

HWRITE4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4);

sys/dev/fdt/rktemp.c

481

HWRITE4(sc, TSADC_AUTO_CON, auto_con);

sys/dev/fdt/rktemp.c

485

HWRITE4(sc, TSADC_COMP_SHUT(i),

sys/dev/fdt/rktemp.c

489

HWRITE4(sc, TSADC_AUTO_CON, auto_con);

sys/dev/fdt/rktemp.c

493

HWRITE4(sc, TSADC_INT_PD, TSADC_INT_PD_TSHUT_O_SRC(i));

sys/dev/fdt/rktemp.c

503

HWRITE4(sc, TSADC_INT_EN, int_en);

sys/dev/fdt/rktemp.c

510

HWRITE4(sc, TSADC_AUTO_CON,

sys/dev/fdt/rktemp.c

514

HWRITE4(sc, TSADC_AUTO_CON, auto_con);

sys/dev/fdt/rktemp.c

555

HWRITE4(sc, TSADC_V3_HT_INT_EN, stat << 16);

sys/dev/fdt/rktemp.c

556

HWRITE4(sc, TSADC_V3_HLT_INT_PD, stat);

sys/dev/fdt/rktemp.c

713

HWRITE4(sc, TSADC_V3_COMP_INT(ch), rktemp_calc_code(sc, temp));

sys/dev/fdt/rktemp.c

716

HWRITE4(sc, TSADC_V3_HLT_INT_PD, TSADC_V3_HT_INT_STATUS(ch));

sys/dev/fdt/rktemp.c

717

HWRITE4(sc, TSADC_V3_HT_INT_EN, TSADC_V3_HT_INT_EN_CH(ch) << 16 |

sys/dev/fdt/rkusbdpphy.c

298

HWRITE4(sc, USBDP_COMBO_PHY_REG(

sys/dev/fdt/rkusbdpphy.c

307

HWRITE4(sc, USBDP_COMBO_PHY_REG(

sys/dev/fdt/rkusbdpphy.c

314

HWRITE4(sc, USBDP_COMBO_PHY_REG(

sys/dev/fdt/rkusbdpphy.c

56

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkusbdpphy.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkvop.c

301

HWRITE4(sc, VOP_WIN0_ACT_INFO, val);

sys/dev/fdt/rkvop.c

305

HWRITE4(sc, VOP_WIN0_DSP_INFO, val);

sys/dev/fdt/rkvop.c

309

HWRITE4(sc, VOP_WIN0_DSP_ST, val);

sys/dev/fdt/rkvop.c

311

HWRITE4(sc, VOP_WIN0_COLOR_KEY, 0);

sys/dev/fdt/rkvop.c

325

HWRITE4(sc, VOP_WIN0_CTRL, val);

sys/dev/fdt/rkvop.c

328

HWRITE4(sc, VOP_WIN0_VIR, val);

sys/dev/fdt/rkvop.c

335

HWRITE4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr);

sys/dev/fdt/rkvop.c

372

HWRITE4(sc, VOP_SYS_CTRL, val);

sys/dev/fdt/rkvop.c

375

HWRITE4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);

sys/dev/fdt/rkvop.c

459

HWRITE4(sc, VOP_SYS_CTRL, val);

sys/dev/fdt/rkvop.c

464

HWRITE4(sc, VOP_DSP_CTRL0, val);

sys/dev/fdt/rkvop.c

468

HWRITE4(sc, VOP_POST_DSP_HACT_INFO, val);

sys/dev/fdt/rkvop.c

472

HWRITE4(sc, VOP_DSP_HACT_ST_END, val);

sys/dev/fdt/rkvop.c

476

HWRITE4(sc, VOP_DSP_HTOTAL_HS_END, val);

sys/dev/fdt/rkvop.c

480

HWRITE4(sc, VOP_POST_DSP_VACT_INFO, val);

sys/dev/fdt/rkvop.c

484

HWRITE4(sc, VOP_DSP_VACT_ST_END, val);

sys/dev/fdt/rkvop.c

488

HWRITE4(sc, VOP_DSP_VTOTAL_VS_END, val);

sys/dev/fdt/rkvop.c

498

HWRITE4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);

sys/dev/fdt/rkvop.c

575

HWRITE4(sc, VOP_SYS_CTRL, val);

sys/dev/fdt/rkvop.c

608

HWRITE4(sc, VOP_DSP_CTRL1, val);

sys/dev/fdt/sxipwm.c

226

HWRITE4(sc, PWM_CTRL_REG, reg);

sys/dev/fdt/sxipwm.c

230

HWRITE4(sc, PWM_CH0_PERIOD, reg);

sys/dev/fdt/sxirintc.c

104

HWRITE4(sc, RINTC_IRQ_PENDING, ~0);

sys/dev/fdt/sxirintc.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sxirintc.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sxirsb.c

186

HWRITE4(sc, RSB_CTRL, RSB_CTRL_SOFT_RESET);

sys/dev/fdt/sxirsb.c

209

HWRITE4(sc, RSB_CCR, (odly << RSB_CCR_CD_ODLY_SHIFT) |

sys/dev/fdt/sxirsb.c

212

HWRITE4(sc, RSB_DMCR, RSB_DMCR_DEVICE_MODE_START |

sys/dev/fdt/sxirsb.c

230

HWRITE4(sc, RSB_CMD, SRTA);

sys/dev/fdt/sxirsb.c

231

HWRITE4(sc, RSB_DAR, (rta << 16 | reg));

sys/dev/fdt/sxirsb.c

291

HWRITE4(sc, RSB_STAT, stat);

sys/dev/fdt/sxirsb.c

304

HWRITE4(sc, RSB_CMD, RD8);

sys/dev/fdt/sxirsb.c

305

HWRITE4(sc, RSB_DAR, rta << 16);

sys/dev/fdt/sxirsb.c

306

HWRITE4(sc, RSB_AR, addr);

sys/dev/fdt/sxirsb.c

322

HWRITE4(sc, RSB_CMD, RD16);

sys/dev/fdt/sxirsb.c

323

HWRITE4(sc, RSB_DAR, rta << 16);

sys/dev/fdt/sxirsb.c

324

HWRITE4(sc, RSB_AR, addr);

sys/dev/fdt/sxirsb.c

340

HWRITE4(sc, RSB_CMD, WR8);

sys/dev/fdt/sxirsb.c

341

HWRITE4(sc, RSB_DAR, rta << 16);

sys/dev/fdt/sxirsb.c

342

HWRITE4(sc, RSB_AR, addr);

sys/dev/fdt/sxirsb.c

343

HWRITE4(sc, RSB_DATA, data);

sys/dev/fdt/sxirsb.c

357

HWRITE4(sc, RSB_CMD, WR16);

sys/dev/fdt/sxirsb.c

358

HWRITE4(sc, RSB_DAR, rta << 16);

sys/dev/fdt/sxirsb.c

359

HWRITE4(sc, RSB_AR, addr);

sys/dev/fdt/sxirsb.c

360

HWRITE4(sc, RSB_DATA, data);

sys/dev/fdt/sxirsb.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sxirsb.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sxisid.c

137

HWRITE4(sc, SID_PRCTL, SID_PRCTL_OFFSET(addr) |

sys/dev/fdt/sxitemp.c

179

HWRITE4(sc, THS_FILTER, THS_FILTER_EN | THS_FILTER_TYPE(1));

sys/dev/fdt/sxitemp.c

180

HWRITE4(sc, THS_INT_CTRL, THS_INT_CTRL_THERMAL_PER(800) | irq);

sys/dev/fdt/sxitemp.c

181

HWRITE4(sc, THS_CTRL0, THS_CTRL0_SENSOR_ACQ(31));

sys/dev/fdt/sxitemp.c

182

HWRITE4(sc, THS_CTRL2, THS_CTRL2_ADC_ACQ(31) | enable);

sys/dev/fdt/sxitemp.c

235

HWRITE4(sc, THS0_1_CDATA, calib[0]);

sys/dev/fdt/sxitemp.c

237

HWRITE4(sc, THS2_CDATA, calib[1]);

sys/dev/fdt/sxitemp.c

248

HWRITE4(sc, THS_STAT, stat);

sys/dev/fdt/sxits.c

117

HWRITE4(sc, TP_CTRL0, TP_CTRL0_ADC_CLK_DIVIDER(2) |

sys/dev/fdt/sxits.c

119

HWRITE4(sc, TP_CTRL1, TP_CTRL1_TP_MODE_EN);

sys/dev/fdt/sxits.c

120

HWRITE4(sc, TP_CTRL3, TP_CTRL3_FILTER_EN | TP_CTRL3_FILTER_TYPE(1));

sys/dev/fdt/sxits.c

121

HWRITE4(sc, TP_TPR, TP_TPR_TEMP_EN | TP_TPR_TEMP_PER(800));

sys/dev/ic/qcuart.c

111

HWRITE4(sc, GENI_M_IRQ_EN, 0);

sys/dev/ic/qcuart.c

112

HWRITE4(sc, GENI_S_IRQ_EN, 0);

sys/dev/ic/qcuart.c

170

HWRITE4(sc, GENI_M_IRQ_CLEAR, m_stat);

sys/dev/ic/qcuart.c

171

HWRITE4(sc, GENI_S_IRQ_CLEAR, s_stat);

sys/dev/ic/qcuart.c

298

HWRITE4(sc, GENI_UART_TX_TRANS_LEN, 1);

sys/dev/ic/qcuart.c

299

HWRITE4(sc, GENI_M_CMD0, GENI_M_CMD0_OPCODE_UART_START_TX);

sys/dev/ic/qcuart.c

300

HWRITE4(sc, GENI_TX_FIFO, getc(&tp->t_outq));

sys/dev/ic/qcuart.c

353

HWRITE4(sc, GENI_S_CMD0, GENI_S_CMD0_OPCODE_UART_START_RX);

sys/dev/ic/qcuart.c

412

HWRITE4(sc, GENI_M_IRQ_EN, 0);

sys/dev/ic/qcuart.c

413

HWRITE4(sc, GENI_S_IRQ_EN, 0);

sys/dev/ic/qcuart.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/ic/qcuart.c

69

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/pci/com_pci.c

115

HWRITE4(sc, LPSS_RESETS, 0);

sys/dev/pci/com_pci.c

116

HWRITE4(sc, LPSS_RESETS, LPSS_RESETS_FUNC | LPSS_RESETS_IDMA);

sys/dev/pci/com_pci.c

117

HWRITE4(sc, LPSS_REMAP_ADDR, sc->sc.sc_iobase);

sys/dev/pci/com_pci.c

185

HWRITE4(sc, i * sizeof(uint32_t), sc->sc_priv[i]);

sys/dev/pci/com_pci.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/pci/com_pci.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/sdmmc/sdhc.c

1062

HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR,

sys/dev/sdmmc/sdhc.c

1080

HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);

sys/dev/sdmmc/sdhc.c

1188

HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap));

sys/dev/sdmmc/sdhc.c

1199

HWRITE4(hp, SDHC_DATA, rv);