bin/csh/csh.c
1016
process(bool catch)
bin/csh/csh.c
113
bool cantell;
bin/csh/csh.c
1151
bool hflg = 0;
bin/csh/csh.c
1186
bool new;
bin/csh/csh.c
142
bool reenter = 0;
bin/csh/csh.c
143
bool nverbose = 0;
bin/csh/csh.c
144
bool nexececho = 0;
bin/csh/csh.c
145
bool quitit = 0;
bin/csh/csh.c
146
bool fast = 0;
bin/csh/csh.c
147
bool batch = 0;
bin/csh/csh.c
148
bool mflag = 0;
bin/csh/csh.c
149
bool prompt = 1;
bin/csh/csh.c
150
bool enterhist = 0;
bin/csh/csh.c
151
bool tellwhat = 0;
bin/csh/csh.c
160
static int srcfile(char *, bool, bool);
bin/csh/csh.c
162
static void srcunit(int, bool, bool);
bin/csh/csh.c
693
srcfile(char *f, bool onlyown, bool flag)
bin/csh/csh.c
712
srcunit(int unit, bool onlyown, bool hflg)
bin/csh/csh.c
721
bool oenterhist = enterhist;
bin/csh/csh.c
723
bool otell = cantell;
bin/csh/csh.c
76
bool chkstop;
bin/csh/csh.c
77
bool didfds;
bin/csh/csh.c
78
bool doneinp;
bin/csh/csh.c
79
bool exiterr;
bin/csh/csh.c
80
bool child;
bin/csh/csh.c
81
bool haderr;
bin/csh/csh.c
82
bool intty;
bin/csh/csh.c
83
bool intact;
bin/csh/csh.c
84
bool justpr;
bin/csh/csh.c
85
bool loginsh;
bin/csh/csh.c
86
bool neednote;
bin/csh/csh.c
87
bool noexec;
bin/csh/csh.c
88
bool pjobs;
bin/csh/csh.c
89
bool setintr;
bin/csh/csh.c
90
bool timflg;
bin/csh/csh.c
91
bool havhash;
bin/csh/csh.c
92
bool needprompt;
bin/csh/csh.c
957
pintr1(bool wantnl)
bin/csh/csh.h
100
extern bool noexec; /* Don't execute, just syntax check */
bin/csh/csh.h
101
extern bool pjobs; /* want to print jobs if interrupted */
bin/csh/csh.h
102
extern bool setintr; /* Set interrupts on/off -> Wait intr... */
bin/csh/csh.h
103
extern bool timflg; /* Time the next waited for command */
bin/csh/csh.h
104
extern bool havhash; /* path hashing is available */
bin/csh/csh.h
106
extern bool filec; /* doing filename expansion */
bin/csh/csh.h
107
extern bool needprompt; /* print prompt, used by filec */
bin/csh/csh.h
238
extern bool cantell; /* Is current source tellable ? */
bin/csh/csh.h
89
extern bool chkstop; /* Warned of stopped jobs... allow exit */
bin/csh/csh.h
90
extern bool didfds; /* Have setup i/o fd's for child */
bin/csh/csh.h
91
extern bool doneinp; /* EOF indicator after reset from readc */
bin/csh/csh.h
92
extern bool exiterr; /* Exit if error or non-zero exit status */
bin/csh/csh.h
93
extern bool child; /* Child shell ... errors cause exit */
bin/csh/csh.h
94
extern bool haderr; /* Reset was because of an error */
bin/csh/csh.h
95
extern bool intty; /* Input is a tty */
bin/csh/csh.h
96
extern bool intact; /* We are interactive... therefore prompt */
bin/csh/csh.h
97
extern bool justpr; /* Just print because of :p hist mod */
bin/csh/csh.h
98
extern bool loginsh; /* We are a loginsh -> .login/.logout */
bin/csh/csh.h
99
extern bool neednote; /* Need to pnotify() */
bin/csh/dir.c
608
bool slash;
bin/csh/dol.c
212
bool dolflg;
bin/csh/dol.c
213
bool sofar = 0, done = 0;
bin/csh/dol.c
392
bool dimen = 0, bitset = 0;
bin/csh/dol.c
821
bool quoted;
bin/csh/exec.c
104
bool slash;
bin/csh/exec.c
490
bool slash = any(short2str(name), '/');
bin/csh/exec.c
545
executable(Char *dir, Char *name, bool dir_ok)
bin/csh/exec.c
620
bool aliased = 0, found;
bin/csh/exec.c
677
bool slash = any(short2str(sp->word), '/');
bin/csh/exec.c
95
static int executable(Char *, Char *, bool);
bin/csh/exp.c
111
exp2_(Char ***vp, bool ignore)
bin/csh/exp.c
126
exp2a(Char ***vp, bool ignore)
bin/csh/exp.c
141
exp2b(Char ***vp, bool ignore)
bin/csh/exp.c
156
exp2c(Char ***vp, bool ignore)
bin/csh/exp.c
196
exp3(Char ***vp, bool ignore)
bin/csh/exp.c
234
exp3a(Char ***vp, bool ignore)
bin/csh/exp.c
256
exp4(Char ***vp, bool ignore)
bin/csh/exp.c
285
exp5(Char ***vp, bool ignore)
bin/csh/exp.c
332
exp6(Char ***vp, bool ignore)
bin/csh/exp.c
60
static int exp1(Char ***, bool);
bin/csh/exp.c
61
static int exp2_(Char ***, bool);
bin/csh/exp.c
62
static int exp2a(Char ***, bool);
bin/csh/exp.c
63
static int exp2b(Char ***, bool);
bin/csh/exp.c
64
static int exp2c(Char ***, bool);
bin/csh/exp.c
65
static Char * exp3(Char ***, bool);
bin/csh/exp.c
66
static Char * exp3a(Char ***, bool);
bin/csh/exp.c
67
static Char * exp4(Char ***, bool);
bin/csh/exp.c
68
static Char * exp5(Char ***, bool);
bin/csh/exp.c
69
static Char * exp6(Char ***, bool);
bin/csh/exp.c
81
exp0(Char ***vp, bool ignore)
bin/csh/exp.c
96
exp1(Char ***vp, bool ignore)
bin/csh/extern.h
146
Char **dobackp(Char *, bool);
bin/csh/extern.h
162
enthist(int, struct wordent *, bool);
bin/csh/extern.h
177
int readc(bool);
bin/csh/extern.h
227
void panystop(bool);
bin/csh/extern.h
45
void pintr1(bool);
bin/csh/extern.h
47
void process(bool);
bin/csh/extern.h
96
int exp0(Char ***, bool);
bin/csh/file.c
125
bool filec = 0;
bin/csh/func.c
410
bool again = whyles != 0 && SEEKEQ(&whyles->w_start, &lineloc) &&
bin/csh/glob.c
576
dobackp(Char *cp, bool literal)
bin/csh/glob.c
614
backeval(Char *cp, bool literal)
bin/csh/glob.c
619
bool hadnl;
bin/csh/glob.c
85
static void backeval(Char *, bool);
bin/csh/hist.c
145
bool print = (*np) > 0;
bin/csh/hist.c
75
enthist(int event, struct wordent *lp, bool docopy)
bin/csh/lex.c
1002
bool first = *al < 0;
bin/csh/lex.c
1088
bool back = 0;
bin/csh/lex.c
119
static bool hadhist = 0;
bin/csh/lex.c
1199
findev(Char *cp, bool anyarg)
bin/csh/lex.c
1263
readc(bool wanteof)
bin/csh/lex.c
226
bool dolflg;
bin/csh/lex.c
405
bool special = 0, toolong;
bin/csh/lex.c
56
*findev(Char *, bool);
bin/csh/lex.c
66
static Char *subword(Char *, int, bool *);
bin/csh/lex.c
68
*dosub(int, struct wordent *, bool);
bin/csh/lex.c
704
bool global;
bin/csh/lex.c
820
dosub(int sc, struct wordent *en, bool global)
bin/csh/lex.c
823
bool didsub = 0, didone = 0;
bin/csh/lex.c
870
subword(Char *cp, int type, bool *adid)
bin/csh/parse.c
143
bool redid;
bin/csh/parse.c
469
bool specp = 0;
bin/csh/proc.c
1130
panystop(bool neednl)
bin/csh/proc.c
1245
bool ignint = 0;
bin/csh/proc.c
50
bool pnoprocesses; /* pchild found nothing to wait for */
bin/csh/proc.c
654
pprint(struct process *pp, bool flag)
bin/csh/proc.c
659
bool hadnl = 1; /* did we just have a newline */
bin/csh/proc.h
92
extern bool pnoprocesses; /* pchild found nothing to wait for */
bin/csh/sem.c
293
bool ignint = 0;
bin/csh/sem.c
55
bool forked = 0;
bin/csh/set.c
204
bool hadsub;
bin/csh/set.c
63
bool hadsub;
bin/ksh/edit.c
153
bool
bin/ksh/edit.c
154
x_mode(bool onoff)
bin/ksh/edit.c
156
static bool x_cur_mode;
bin/ksh/edit.c
157
bool prev;
bin/ksh/edit.c
760
bool saw_slash = false;
bin/ksh/edit.h
46
bool x_mode(bool);
bin/ksh/exec.c
1249
do_selectargs(char **ap, bool print_menu)
bin/ksh/exec.c
276
volatile bool is_first = true;
bin/ksh/exec.c
30
static char *do_selectargs(char **, bool);
bin/ksh/expr.c
124
bool arith; /* true if evaluating an $(())
bin/ksh/expr.c
142
static struct tbl *do_ppmm(Expr_state *, enum token, struct tbl *, bool);
bin/ksh/expr.c
151
evaluate(const char *expr, int64_t *rval, int error_ok, bool arith)
bin/ksh/expr.c
168
bool arith)
bin/ksh/expr.c
534
do_ppmm(Expr_state *es, enum token op, struct tbl *vasn, bool is_prefix)
bin/ksh/io.c
46
warningf(bool show_lineno, const char *fmt, ...)
bin/ksh/sh.h
445
int evaluate(const char *, int64_t *, int, bool);
bin/ksh/sh.h
446
int v_evaluate(struct tbl *, const char *, volatile int, bool);
bin/ksh/sh.h
466
void warningf(bool, const char *, ...)
bin/ksh/sh.h
587
struct tbl * local(const char *, bool);
bin/ksh/sh.h
591
struct tbl *setint_v(struct tbl *, struct tbl *, bool);
bin/ksh/sh.h
593
int getint(struct tbl *, int64_t *, bool);
bin/ksh/var.c
138
array_index_calc(const char *n, bool *arrayp, int *valp)
bin/ksh/var.c
176
bool array;
bin/ksh/var.c
252
local(const char *n, bool copy)
bin/ksh/var.c
257
bool array;
bin/ksh/var.c
423
getint(struct tbl *vp, int64_t *nump, bool arith)
bin/ksh/var.c
492
setint_v(struct tbl *vq, struct tbl *vp, bool arith)
games/bs/bs.c
1005
bool sunk;
games/bs/bs.c
1036
static bool used[4];
games/bs/bs.c
1039
bool closenoshot = FALSE;
games/bs/bs.c
58
bool placed; /* has it been placed on the board? */
games/bs/bs.c
63
static bool checkplace(int, ship_t *, int);
games/bs/bs.c
66
static bool cpushipcanfit(int, int, int, int);
games/bs/bs.c
701
static bool
games/bs/bs.c
924
static bool
games/canfield/canfield/canfield.c
1241
bool
games/canfield/canfield/canfield.c
129
bool visible;
games/canfield/canfield/canfield.c
130
bool paid;
games/canfield/canfield/canfield.c
149
bool errmsg, done;
games/canfield/canfield/canfield.c
150
bool mtfdone, Cflag = FALSE;
games/canfield/canfield/canfield.c
1656
bool
games/canfield/canfield/canfield.c
181
bool startedgame = FALSE, infullgame = FALSE;
games/canfield/canfield/canfield.c
193
bool diffcolor(const struct cardtype *, const struct cardtype *);
games/canfield/canfield/canfield.c
195
bool finish(void);
games/canfield/canfield/canfield.c
207
bool notempty(const struct cardtype *);
games/canfield/canfield/canfield.c
211
void printrank(int, int, const struct cardtype *, bool);
games/canfield/canfield/canfield.c
214
bool rankhigher(const struct cardtype *, int);
games/canfield/canfield/canfield.c
215
bool ranklower(const struct cardtype *, const struct cardtype *);
games/canfield/canfield/canfield.c
224
bool tabok(const struct cardtype *, int);
games/canfield/canfield/canfield.c
557
printrank(int a, int b, const struct cardtype *cp, bool inverse)
games/canfield/canfield/canfield.c
597
bool inverse = (cp->suit == 'd' || cp->suit == 'h');
games/canfield/canfield/canfield.c
632
bool nomore;
games/canfield/canfield/canfield.c
799
bool
games/canfield/canfield/canfield.c
814
bool
games/canfield/canfield/canfield.c
831
bool
games/canfield/canfield/canfield.c
843
bool
games/cribbage/crib.c
171
bool flag;
games/cribbage/crib.c
172
bool compcrib;
games/cribbage/crib.c
272
playhand(bool mycrib)
games/cribbage/crib.c
303
deal(bool mycrib)
games/cribbage/crib.c
325
discard(bool mycrib)
games/cribbage/crib.c
354
cut(bool mycrib, int pos)
games/cribbage/crib.c
357
bool win;
games/cribbage/crib.c
408
prcrib(bool mycrib, bool blank)
games/cribbage/crib.c
438
peg(bool mycrib)
games/cribbage/crib.c
44
bool playing;
games/cribbage/crib.c
444
bool myturn, mego, ugo, last, played;
games/cribbage/crib.c
618
score(bool mycrib)
games/cribbage/cribbage.h
100
int peg(bool);
games/cribbage/cribbage.h
102
int playhand(bool);
games/cribbage/cribbage.h
104
void prcard(WINDOW *, int, int, CARD, bool);
games/cribbage/cribbage.h
105
void prcrib(bool, bool);
games/cribbage/cribbage.h
106
void prhand(CARD [], int, WINDOW *, bool);
games/cribbage/cribbage.h
107
void printcard(WINDOW *, int, CARD, bool);
games/cribbage/cribbage.h
108
void prpeg(int, int, bool);
games/cribbage/cribbage.h
112
int score(bool);
games/cribbage/cribbage.h
113
int scorehand(CARD [], CARD, int, bool, bool);
games/cribbage/cribbage.h
58
extern bool iwon; /* if comp won last */
games/cribbage/cribbage.h
59
extern bool explain; /* player mistakes explained */
games/cribbage/cribbage.h
60
extern bool muggins; /* player mistakes exploited */
games/cribbage/cribbage.h
61
extern bool rflag; /* if all cuts random */
games/cribbage/cribbage.h
62
extern bool quiet; /* if suppress random mess */
games/cribbage/cribbage.h
72
void cdiscard(bool);
games/cribbage/cribbage.h
76
int cut(bool, int);
games/cribbage/cribbage.h
77
int deal(bool);
games/cribbage/cribbage.h
78
void discard(bool);
games/cribbage/cribbage.h
95
int msgcard(CARD, bool);
games/cribbage/cribbage.h
96
int msgcrd(CARD, bool, char *, bool);
games/cribbage/extern.c
37
bool explain = FALSE; /* player mistakes explained */
games/cribbage/extern.c
38
bool iwon = FALSE; /* if comp won last game */
games/cribbage/extern.c
39
bool muggins = FALSE; /* player mistakes exploited */
games/cribbage/extern.c
40
bool quiet = FALSE; /* if suppress random mess */
games/cribbage/extern.c
41
bool rflag = FALSE; /* if all cuts random */
games/cribbage/io.c
104
printcard(WINDOW *win, int cardno, CARD c, bool blank)
games/cribbage/io.c
114
prcard(WINDOW *win, int y, int x, CARD c, bool blank)
games/cribbage/io.c
137
prhand(CARD h[], int n, WINDOW *win, bool blank)
games/cribbage/io.c
212
bool retval;
games/cribbage/io.c
69
msgcard(CARD c, bool brief)
games/cribbage/io.c
82
msgcrd(CARD c, bool brfrank, char *mid, bool brfsuit)
games/cribbage/score.c
103
bool flag;
games/cribbage/score.c
217
bool run;
games/cribbage/score.c
281
bool got[RANKS];
games/cribbage/score.c
99
scorehand(CARD hand[], CARD starter, int n, bool crb, bool do_explain)
games/cribbage/support.c
122
bool win;
games/cribbage/support.c
178
bool myturn;
games/cribbage/support.c
197
prpeg(int score, int peg, bool myturn)
games/cribbage/support.c
233
cdiscard(bool mycrib)
games/fortune/fortune/fortune.c
395
bool was_malloc;
games/fortune/fortune/fortune.c
396
bool isdir;
games/fortune/fortune/fortune.c
78
bool read_tbl;
games/fortune/fortune/fortune.c
85
bool Found_one = false; /* did we find a match? */
games/fortune/fortune/fortune.c
86
bool Find_files = false; /* display a list of fortune files */
games/fortune/fortune/fortune.c
87
bool Wait = false; /* wait desired after fortune */
games/fortune/fortune/fortune.c
88
bool Short_only = false; /* short fortune desired */
games/fortune/fortune/fortune.c
89
bool Long_only = false; /* long fortune desired */
games/fortune/fortune/fortune.c
90
bool Offend = false; /* offensive fortunes only */
games/fortune/fortune/fortune.c
907
static bool did_noprobs = false;
games/fortune/fortune/fortune.c
91
bool All_forts = false; /* any fortune allowed */
games/fortune/fortune/fortune.c
92
bool Equal_probs = false; /* scatter un-allocted prob equally */
games/fortune/fortune/fortune.c
93
bool Match = false; /* dump fortunes matching a pattern */
games/fortune/strfile/strfile.c
129
bool first;
games/fortune/strfile/strfile.c
380
bool n1, n2;
games/fortune/strfile/strfile.c
93
bool Sflag = false; /* silent run flag */
games/fortune/strfile/strfile.c
94
bool Oflag = false; /* ordering flag */
games/fortune/strfile/strfile.c
95
bool Iflag = false; /* ignore case flag */
games/fortune/strfile/strfile.c
96
bool Rflag = false; /* randomize order flag */
games/fortune/strfile/strfile.c
97
bool Xflag = false; /* set rotated bit */
games/hangman/extern.c
36
bool Guessed[26 + 10];
games/hangman/getguess.c
49
bool correct;
games/hangman/hangman.h
63
extern bool Guessed[];
games/mille/comp.c
47
bool foundend, cango, canstop, foundlow;
games/mille/comp.c
52
bool playit[HAND_SZ];
games/mille/extern.c
39
bool Debug, /* set if debugging code on */
games/mille/mille.c
50
bool restore;
games/mille/mille.h
148
bool coups[NUM_SAFE];
games/mille/mille.h
149
bool can_go;
games/mille/mille.h
150
bool new_battle;
games/mille/mille.h
151
bool new_speed;
games/mille/mille.h
192
extern bool Debug, Finished, Next, On_exit, Order, Saved;
games/mille/mille.h
217
int check_ext(bool);
games/mille/mille.h
222
bool error(char *, ...);
games/mille/mille.h
236
void prscore(bool);
games/mille/mille.h
238
bool rest_f(const char *);
games/mille/mille.h
242
bool save(void);
games/mille/mille.h
247
bool varpush(int, ssize_t(int, const struct iovec *, int));
games/mille/misc.c
109
check_ext(bool forcomp)
games/mille/misc.c
44
bool
games/mille/move.c
323
Next = (Next == (bool)-1 ? FALSE : TRUE);
games/mille/move.c
335
static bool last_ex = FALSE; /* set if last command was E */
games/mille/move.c
51
bool goodplay;
games/mille/print.c
110
prscore(bool for_real)
games/mille/save.c
139
bool
games/mille/save.c
54
bool
games/mille/save.c
63
bool rv;
games/mille/varpush.c
50
bool
games/monop/deck.h
43
bool gojf_used; /* set if gojf card out of deck */
games/monop/execute.c
48
static bool new_play; /* set if move on to new player */
games/monop/execute.c
96
bool was_jail;
games/monop/houses.c
117
bool chot;
games/monop/houses.c
205
bool good;
games/monop/houses.c
349
static bool
games/monop/houses.c
48
static bool can_only_buy_hotel(MON *);
games/monop/houses.c
59
bool good, got_morg;
games/monop/initdeck.c
153
bool newline;
games/monop/initdeck.c
176
bool newline;
games/monop/monop.c
131
bool over = 0;
games/monop/monop.h
102
bool morg; /* set if mortgaged */
games/monop/monop.h
103
bool monop; /* set if monopoly */
games/monop/monop.h
180
void printsq(int, bool);
games/monop/print.c
77
printsq(int sqn, bool eoln)
games/monop/prop.c
146
static bool in[MAX_PL];
games/monop/trade.c
169
bool some;
games/phantasia/fight.c
53
volatile bool firsthit = Player.p_blessing; /* set if player gets
games/phantasia/gamesupport.c
64
changestats(bool ingameflag)
games/phantasia/gamesupport.c
691
bool found = FALSE; /* set if we found an entry for this login */
games/phantasia/gamesupport.c
76
bool *bptr; /* pointer to bool item to change */
games/phantasia/interplayer.c
712
userlist(bool ingameflag)
games/phantasia/io.c
317
getanswer(char *choices, bool def)
games/phantasia/main.c
108
bool noheader = FALSE; /* set if don't want header */
games/phantasia/main.c
109
bool headeronly = FALSE; /* set if only want header */
games/phantasia/main.c
110
bool examine = FALSE; /* set if examine a character */
games/phantasia/main.c
520
bool hasmoved = FALSE; /* set if player has moved */
games/phantasia/main.c
748
bool councilfound = FALSE; /* set if we find a member of the
games/phantasia/main.c
750
bool kingfound = FALSE; /* set if we find a king */
games/phantasia/misc.c
129
descrlocation(struct player *playerp, bool shortflag)
games/phantasia/misc.c
235
bool dishonest = FALSE; /* set when merchant is dishonest */
games/phantasia/misc.c
594
descrtype(struct player *playerp, bool shortflag)
games/phantasia/phantglobs.c
16
bool Beyond; /* set if player is beyond point of no return */
games/phantasia/phantglobs.c
17
bool Marsh; /* set if player is in dead marshes */
games/phantasia/phantglobs.c
18
bool Throne; /* set if player is on throne */
games/phantasia/phantglobs.c
19
bool Changed; /* set if important player stats have changed */
games/phantasia/phantglobs.c
20
bool Wizard; /* set if player is the 'wizard' of the game */
games/phantasia/phantglobs.c
21
bool Timeout; /* set if short timeout waiting for input */
games/phantasia/phantglobs.c
22
bool Windows; /* set if we are set up for curses stuff */
games/phantasia/phantglobs.c
23
bool Luckout; /* set if we have tried to luck out in fight */
games/phantasia/phantglobs.c
24
bool Foestrikes; /* set if foe gets a chance to hit in battleplayer() */
games/phantasia/phantglobs.c
25
bool Echo; /* set if echo input to terminal */
games/phantasia/phantglobs.h
100
int getanswer(char *, bool);
games/phantasia/phantglobs.h
132
void userlist(bool);
games/phantasia/phantglobs.h
15
extern bool Beyond; /* set if player is beyond point of no return */
games/phantasia/phantglobs.h
16
extern bool Marsh; /* set if player is in dead marshes */
games/phantasia/phantglobs.h
17
extern bool Throne; /* set if player is on throne */
games/phantasia/phantglobs.h
18
extern bool Changed; /* set if important player stats have changed */
games/phantasia/phantglobs.h
19
extern bool Wizard; /* set if player is the 'wizard' of the game */
games/phantasia/phantglobs.h
20
extern bool Timeout; /* set if short timeout waiting for input */
games/phantasia/phantglobs.h
21
extern bool Windows; /* set if we are set up for curses stuff */
games/phantasia/phantglobs.h
22
extern bool Luckout; /* set if we have tried to luck out in fight */
games/phantasia/phantglobs.h
23
extern bool Foestrikes; /* set if foe gets a chance to hit in battleplayer()*/
games/phantasia/phantglobs.h
24
extern bool Echo; /* set if echo input to terminal */
games/phantasia/phantglobs.h
68
char *descrlocation(struct player *, bool);
games/phantasia/phantglobs.h
70
char *descrtype(struct player *, bool);
games/phantasia/phantglobs.h
82
void changestats(bool);
games/phantasia/phantstruct.h
40
bool ring_inuse; /* ring in use flag */
games/phantasia/phantstruct.h
59
bool p_palantir; /* palantir */
games/phantasia/phantstruct.h
60
bool p_blessing; /* blessing */
games/phantasia/phantstruct.h
61
bool p_virgin; /* virgin */
games/phantasia/phantstruct.h
62
bool p_blindness; /* blindness */
games/phantasia/phantstruct.h
95
bool ev_active; /* active or not */
games/robots/extern.c
36
bool Dead; /* Player is now dead */
games/robots/extern.c
37
bool Full_clear = TRUE; /* Lots of junk for init_field to clear */
games/robots/extern.c
38
bool Jump = FALSE; /* Jump while running, counting, or waiting */
games/robots/extern.c
39
bool Newscore; /* There was a new score added */
games/robots/extern.c
41
bool Pattern_roll = FALSE; /* Auto play for YHBJNLUK pattern */
games/robots/extern.c
43
bool Real_time = FALSE; /* Play in real time? */
games/robots/extern.c
44
bool Running = FALSE; /* Currently in the middle of a run */
games/robots/extern.c
46
bool Stand_still = FALSE; /* Auto play for standing still pattern */
games/robots/extern.c
48
bool Teleport = FALSE; /* Teleport automatically when player must */
games/robots/extern.c
49
bool Waiting; /* Player is waiting for end */
games/robots/extern.c
50
bool Was_bonus = FALSE; /* Was a bonus last level */
games/robots/init_field.c
44
static bool first = TRUE;
games/robots/main.c
187
bool
games/robots/main.c
53
bool show_only;
games/robots/move.c
232
bool
games/robots/move.c
264
bool
games/robots/move.c
299
bool
games/robots/move.c
334
bool
games/robots/robots.h
105
bool another(void);
games/robots/robots.h
107
bool do_move(int, int);
games/robots/robots.h
108
bool eaten(COORD *);
games/robots/robots.h
111
bool jumping(void);
games/robots/robots.h
114
bool must_telep(void);
games/robots/robots.h
82
extern bool Dead, Full_clear, Jump, Newscore, Real_time, Running,
games/robots/robots.h
86
extern bool Pattern_roll, Stand_still;
games/robots/score.c
61
bool done_show = FALSE;
include/stdbool.h
36
#define _Bool bool
include/stdbool.h
37
#define bool bool
lib/libc/arch/arm/quad/fixdfdi.c
61
const bool neg = ux.dbl_sign;
lib/libc/arch/arm/quad/fixsfdi.c
59
const bool neg = ux.sng_sign;
lib/libc/gen/devname.c
77
static bool failure;
lib/libc/gen/getpwent.c
258
bool remap = true;
lib/libc/gen/getpwent.c
741
struct passwd **pwretp, bool shadow, bool reentrant)
lib/libc/gen/getpwent.c
824
struct passwd **pwretp, bool shadow, bool reentrant)
lib/libcbor/src/cbor.c
117
static cbor_item_t *_cbor_copy_int(cbor_item_t *item, bool negative) {
lib/libcbor/src/cbor/arrays.c
26
bool cbor_array_set(cbor_item_t *item, size_t index, cbor_item_t *value) {
lib/libcbor/src/cbor/arrays.c
36
bool cbor_array_replace(cbor_item_t *item, size_t index, cbor_item_t *value) {
lib/libcbor/src/cbor/arrays.c
44
bool cbor_array_push(cbor_item_t *array, cbor_item_t *pushee) {
lib/libcbor/src/cbor/arrays.c
82
bool cbor_array_is_definite(const cbor_item_t *item) {
lib/libcbor/src/cbor/arrays.c
87
bool cbor_array_is_indefinite(const cbor_item_t *item) {
lib/libcbor/src/cbor/arrays.h
122
CBOR_EXPORT bool cbor_array_push(cbor_item_t* array, cbor_item_t* pushee);
lib/libcbor/src/cbor/arrays.h
54
CBOR_EXPORT bool cbor_array_set(cbor_item_t* item, size_t index,
lib/libcbor/src/cbor/arrays.h
67
CBOR_EXPORT bool cbor_array_replace(cbor_item_t* item, size_t index,
lib/libcbor/src/cbor/arrays.h
76
CBOR_EXPORT bool cbor_array_is_definite(const cbor_item_t* item);
lib/libcbor/src/cbor/arrays.h
84
CBOR_EXPORT bool cbor_array_is_indefinite(const cbor_item_t* item);
lib/libcbor/src/cbor/bytestrings.c
22
bool cbor_bytestring_is_definite(const cbor_item_t *item) {
lib/libcbor/src/cbor/bytestrings.c
27
bool cbor_bytestring_is_indefinite(const cbor_item_t *item) {
lib/libcbor/src/cbor/bytestrings.c
92
bool cbor_bytestring_add_chunk(cbor_item_t *item, cbor_item_t *chunk) {
lib/libcbor/src/cbor/bytestrings.h
105
CBOR_EXPORT bool cbor_bytestring_add_chunk(cbor_item_t *item,
lib/libcbor/src/cbor/bytestrings.h
40
CBOR_EXPORT bool cbor_bytestring_is_definite(const cbor_item_t *item);
lib/libcbor/src/cbor/bytestrings.h
48
CBOR_EXPORT bool cbor_bytestring_is_indefinite(const cbor_item_t *item);
lib/libcbor/src/cbor/callbacks.c
73
bool _CBOR_UNUSED(_val)) {}
lib/libcbor/src/cbor/callbacks.h
177
CBOR_EXPORT void cbor_null_boolean_callback(void *, bool);
lib/libcbor/src/cbor/callbacks.h
48
typedef void (*cbor_bool_callback)(void *, bool);
lib/libcbor/src/cbor/common.c
19
bool _cbor_enable_assert = true;
lib/libcbor/src/cbor/common.c
22
bool cbor_isa_uint(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
26
bool cbor_isa_negint(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
30
bool cbor_isa_bytestring(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
34
bool cbor_isa_string(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
38
bool cbor_isa_array(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
42
bool cbor_isa_map(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
46
bool cbor_isa_tag(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
50
bool cbor_isa_float_ctrl(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
56
bool cbor_is_int(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
60
bool cbor_is_bool(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
66
bool cbor_is_null(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
70
bool cbor_is_undef(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.c
74
bool cbor_is_float(const cbor_item_t *item) {
lib/libcbor/src/cbor/common.h
167
CBOR_EXPORT bool cbor_isa_uint(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
174
CBOR_EXPORT bool cbor_isa_negint(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
181
CBOR_EXPORT bool cbor_isa_bytestring(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
188
CBOR_EXPORT bool cbor_isa_string(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
195
CBOR_EXPORT bool cbor_isa_array(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
202
CBOR_EXPORT bool cbor_isa_map(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
209
CBOR_EXPORT bool cbor_isa_tag(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
216
CBOR_EXPORT bool cbor_isa_float_ctrl(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
225
CBOR_EXPORT bool cbor_is_int(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
232
CBOR_EXPORT bool cbor_is_float(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
239
CBOR_EXPORT bool cbor_is_bool(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
252
CBOR_EXPORT bool cbor_is_null(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
265
CBOR_EXPORT bool cbor_is_undef(const cbor_item_t *item);
lib/libcbor/src/cbor/common.h
59
extern bool _cbor_enable_assert;
lib/libcbor/src/cbor/encoding.c
114
size_t cbor_encode_bool(bool value, unsigned char *buffer, size_t buffer_size) {
lib/libcbor/src/cbor/encoding.h
94
_CBOR_NODISCARD CBOR_EXPORT size_t cbor_encode_bool(bool, unsigned char *,
lib/libcbor/src/cbor/floats_ctrls.c
159
cbor_item_t *cbor_build_bool(bool value) {
lib/libcbor/src/cbor/floats_ctrls.c
23
bool cbor_float_ctrl_is_ctrl(const cbor_item_t *item) {
lib/libcbor/src/cbor/floats_ctrls.c
61
bool cbor_get_bool(const cbor_item_t *item) {
lib/libcbor/src/cbor/floats_ctrls.c
90
void cbor_set_bool(cbor_item_t *item, bool value) {
lib/libcbor/src/cbor/floats_ctrls.h
136
_CBOR_NODISCARD CBOR_EXPORT cbor_item_t *cbor_build_bool(bool value);
lib/libcbor/src/cbor/floats_ctrls.h
156
CBOR_EXPORT void cbor_set_bool(cbor_item_t *item, bool value);
lib/libcbor/src/cbor/floats_ctrls.h
29
_CBOR_NODISCARD CBOR_EXPORT bool cbor_float_ctrl_is_ctrl(
lib/libcbor/src/cbor/floats_ctrls.h
85
_CBOR_NODISCARD CBOR_EXPORT bool cbor_get_bool(const cbor_item_t *item);
lib/libcbor/src/cbor/internal/builder_callbacks.c
347
bool _cbor_is_indefinite(cbor_item_t *item) {
lib/libcbor/src/cbor/internal/builder_callbacks.c
419
void cbor_builder_boolean_callback(void *context, bool value) {
lib/libcbor/src/cbor/internal/builder_callbacks.h
22
bool creation_failed;
lib/libcbor/src/cbor/internal/builder_callbacks.h
24
bool syntax_error;
lib/libcbor/src/cbor/internal/builder_callbacks.h
77
void cbor_builder_boolean_callback(void *, bool);
lib/libcbor/src/cbor/internal/memory_utils.c
25
bool _cbor_safe_to_multiply(size_t a, size_t b) {
lib/libcbor/src/cbor/internal/memory_utils.c
30
bool _cbor_safe_to_add(size_t a, size_t b) {
lib/libcbor/src/cbor/internal/memory_utils.h
18
bool _cbor_safe_to_multiply(size_t a, size_t b);
lib/libcbor/src/cbor/internal/memory_utils.h
22
bool _cbor_safe_to_add(size_t a, size_t b);
lib/libcbor/src/cbor/maps.c
106
bool cbor_map_add(cbor_item_t *item, struct cbor_pair pair) {
lib/libcbor/src/cbor/maps.c
112
bool cbor_map_is_definite(const cbor_item_t *item) {
lib/libcbor/src/cbor/maps.c
117
bool cbor_map_is_indefinite(const cbor_item_t *item) {
lib/libcbor/src/cbor/maps.c
52
bool _cbor_map_add_key(cbor_item_t *item, cbor_item_t *key) {
lib/libcbor/src/cbor/maps.c
95
bool _cbor_map_add_value(cbor_item_t *item, cbor_item_t *value) {
lib/libcbor/src/cbor/maps.h
100
_CBOR_NODISCARD CBOR_EXPORT bool cbor_map_is_indefinite(
lib/libcbor/src/cbor/maps.h
61
_CBOR_NODISCARD CBOR_EXPORT bool cbor_map_add(cbor_item_t *item,
lib/libcbor/src/cbor/maps.h
73
_CBOR_NODISCARD CBOR_EXPORT bool _cbor_map_add_key(cbor_item_t *item,
lib/libcbor/src/cbor/maps.h
85
_CBOR_NODISCARD CBOR_EXPORT bool _cbor_map_add_value(cbor_item_t *item,
lib/libcbor/src/cbor/maps.h
93
_CBOR_NODISCARD CBOR_EXPORT bool cbor_map_is_definite(const cbor_item_t *item);
lib/libcbor/src/cbor/streaming.c
11
static bool claim_bytes(size_t required, size_t provided,
lib/libcbor/src/cbor/strings.c
125
bool cbor_string_is_definite(const cbor_item_t *item) {
lib/libcbor/src/cbor/strings.c
130
bool cbor_string_is_indefinite(const cbor_item_t *item) {
lib/libcbor/src/cbor/strings.c
83
bool cbor_string_add_chunk(cbor_item_t *item, cbor_item_t *chunk) {
lib/libcbor/src/cbor/strings.h
120
_CBOR_NODISCARD CBOR_EXPORT bool cbor_string_add_chunk(cbor_item_t *item,
lib/libcbor/src/cbor/strings.h
49
_CBOR_NODISCARD CBOR_EXPORT bool cbor_string_is_definite(
lib/libcbor/src/cbor/strings.h
57
_CBOR_NODISCARD CBOR_EXPORT bool cbor_string_is_indefinite(
lib/libcrypto/bio/bio.h
414
#define BIO_set_no_connect_return(b,bool) BIO_int_ctrl(b,BIO_C_SET_PROXY_PARAM,5,bool)
lib/libcurses/base/keyok.c
101
keyok(int c, bool flag)
lib/libcurses/base/keyok.c
52
NCURSES_SP_NAME(keyok) (NCURSES_SP_DCLx int c, bool flag)
lib/libcurses/base/lib_addch.c
122
static bool
lib/libcurses/base/lib_addch.c
125
bool result = FALSE;
lib/libcurses/base/lib_addch.c
596
bool save_immed = win->_immed;
lib/libcurses/base/lib_bkgd.c
120
_nc_background(WINDOW *win, const ARG_CH_T ch, bool narrow)
lib/libcurses/base/lib_clearok.c
49
clearok(WINDOW *win, bool flag)
lib/libcurses/base/lib_color.c
250
static bool
lib/libcurses/base/lib_color.c
308
static bool
lib/libcurses/base/lib_color.c
314
bool result = FALSE;
lib/libcurses/base/lib_color.c
330
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_color.c
353
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_color.c
504
bool changed = FALSE;
lib/libcurses/base/lib_color.c
579
bool isDefault = FALSE;
lib/libcurses/base/lib_color.c
580
bool wasDefault = FALSE;
lib/libcurses/base/lib_color.c
778
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_color.c
793
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_color.c
800
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_color.c
823
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_delwin.c
50
static bool
lib/libcurses/base/lib_delwin.c
53
bool result = TRUE;
lib/libcurses/base/lib_dft_fgbg.c
85
bool save = SP_PARM->_default_color;
lib/libcurses/base/lib_freeall.c
76
bool deleted = FALSE;
lib/libcurses/base/lib_freeall.c
81
bool found = FALSE;
lib/libcurses/base/lib_getch.c
378
static int kgetch(SCREEN *, bool EVENTLIST_2nd(_nc_eventlist *));
lib/libcurses/base/lib_getch.c
385
bool same_sp;
lib/libcurses/base/lib_getch.c
720
kgetch(SCREEN *sp, bool forever EVENTLIST_2nd(_nc_eventlist * evl))
lib/libcurses/base/lib_immedok.c
49
immedok(WINDOW *win, bool flag)
lib/libcurses/base/lib_instr.c
80
bool done = FALSE;
lib/libcurses/base/lib_isendwin.c
50
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_isendwin.c
59
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_leaveok.c
49
leaveok(WINDOW *win, bool flag)
lib/libcurses/base/lib_mouse.c
1009
static bool
lib/libcurses/base/lib_mouse.c
1012
bool result;
lib/libcurses/base/lib_mouse.c
1099
static bool
lib/libcurses/base/lib_mouse.c
1106
bool result;
lib/libcurses/base/lib_mouse.c
1144
static bool
lib/libcurses/base/lib_mouse.c
1151
bool result;
lib/libcurses/base/lib_mouse.c
1223
static bool
lib/libcurses/base/lib_mouse.c
1306
static bool
lib/libcurses/base/lib_mouse.c
1310
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
1355
static bool
lib/libcurses/base/lib_mouse.c
1359
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
1502
static bool
lib/libcurses/base/lib_mouse.c
1512
bool merge;
lib/libcurses/base/lib_mouse.c
1513
bool endLoop;
lib/libcurses/base/lib_mouse.c
1579
bool changed = TRUE;
lib/libcurses/base/lib_mouse.c
188
static bool _nc_mouse_parse(SCREEN *, int);
lib/libcurses/base/lib_mouse.c
1952
mouse_activate(SP_PARM, (bool) (result != 0));
lib/libcurses/base/lib_mouse.c
1985
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_mouse.c
1989
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
2032
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_mouse.c
2038
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_mouse.c
2045
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_mouse.c
2052
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_mouse.c
2053
wmouse_trafo(const WINDOW *win, int *pY, int *pX, bool to_screen)
lib/libcurses/base/lib_mouse.c
2055
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
471
static bool
lib/libcurses/base/lib_mouse.c
474
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
554
static bool
lib/libcurses/base/lib_mouse.c
555
enable_gpm_mouse(SCREEN *sp, bool enable)
lib/libcurses/base/lib_mouse.c
557
bool result;
lib/libcurses/base/lib_mouse.c
775
static bool
lib/libcurses/base/lib_mouse.c
779
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
808
static bool
lib/libcurses/base/lib_mouse.c
812
bool result = FALSE;
lib/libcurses/base/lib_mouse.c
959
static bool
lib/libcurses/base/lib_mouse.c
962
bool result = TRUE;
lib/libcurses/base/lib_newwin.c
260
static bool
lib/libcurses/base/lib_newwin.c
278
bool is_padwin = (flags & _ISPAD);
lib/libcurses/base/lib_overlay.c
172
bool copied = FALSE;
lib/libcurses/base/lib_overlay.c
179
bool touched;
lib/libcurses/base/lib_pad.c
142
bool wide;
lib/libcurses/base/lib_refresh.c
89
bool wide;
lib/libcurses/base/lib_screen.c
215
bool found = FALSE;
lib/libcurses/base/lib_screen.c
413
*(bool *) data = TRUE;
lib/libcurses/base/lib_screen.c
506
bool old_format = FALSE;
lib/libcurses/base/lib_screen.c
605
bool success = TRUE;
lib/libcurses/base/lib_screen.c
672
bool first = TRUE;
lib/libcurses/base/lib_screen.c
840
if (!(*(const bool *) data)) {
lib/libcurses/base/lib_scrollok.c
49
scrollok(WINDOW *win, bool flag)
lib/libcurses/base/lib_set_term.c
122
static bool
lib/libcurses/base/lib_set_term.c
127
bool result = FALSE;
lib/libcurses/base/lib_set_term.c
155
bool is_current = (sp == CURRENT_SCREEN);
lib/libcurses/base/lib_set_term.c
259
static bool
lib/libcurses/base/lib_set_term.c
265
static bool
lib/libcurses/base/lib_set_term.c
271
static bool
lib/libcurses/base/lib_set_term.c
330
bool support_cookies = USE_XMC_SUPPORT;
lib/libcurses/base/lib_set_term.c
353
if ((sp->_screen_acs_map = typeCalloc(bool, ACS_LEN)) == NULL) {
lib/libcurses/base/lib_set_term.c
368
|| ((SP->_screen_acs_map = typeCalloc(bool, ACS_LEN)) == 0)) {
lib/libcurses/base/lib_touch.c
53
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_touch.c
66
NCURSES_EXPORT(bool)
lib/libcurses/base/lib_window.c
84
syncok(WINDOW *win, bool bf)
lib/libcurses/base/new_pair.c
201
bool used;
lib/libcurses/base/new_pair.c
277
bool found = FALSE;
lib/libcurses/base/resizeterm.c
104
NCURSES_EXPORT(bool)
lib/libcurses/base/resizeterm.c
115
NCURSES_EXPORT(bool)
lib/libcurses/base/resizeterm.c
284
bool found;
lib/libcurses/base/resizeterm.c
319
bool found;
lib/libcurses/base/resizeterm.c
488
bool slk_visible = (SP_PARM != 0
lib/libcurses/base/wresize.c
181
bool valid = (col <= size_x);
lib/libcurses/curses.h
1011
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(can_change_color) (SCREEN*); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1027
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(has_colors) (SCREEN*); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1028
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(has_ic) (SCREEN*); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1029
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(has_il) (SCREEN*); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1032
extern NCURSES_EXPORT(int) NCURSES_SP_NAME(intrflush) (SCREEN*, WINDOW*, bool); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1033
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(isendwin) (SCREEN*); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1078
extern NCURSES_EXPORT(void) NCURSES_SP_NAME(use_env) (SCREEN*, bool); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1079
extern NCURSES_EXPORT(void) NCURSES_SP_NAME(use_tioctl) (SCREEN*, bool); /* implemented:SP_FUNC */
lib/libcurses/curses.h
1098
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(is_term_resized) (SCREEN*, int, int); /* implemented:EXT_SP_FUNC */
lib/libcurses/curses.h
1101
extern NCURSES_EXPORT(int) NCURSES_SP_NAME(keyok) (SCREEN*, int, bool); /* implemented:EXT_SP_FUNC */
lib/libcurses/curses.h
2031
extern NCURSES_EXPORT(bool) has_mouse(void);
lib/libcurses/curses.h
2035
extern NCURSES_EXPORT(bool) wenclose (const WINDOW *, int, int);
lib/libcurses/curses.h
2037
extern NCURSES_EXPORT(bool) wmouse_trafo (const WINDOW*, int*, int*, bool);
lib/libcurses/curses.h
2038
extern NCURSES_EXPORT(bool) mouse_trafo (int*, int*, bool); /* generated */
lib/libcurses/curses.h
2041
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(has_mouse) (SCREEN*);
lib/libcurses/curses.h
279
#define NCURSES_BOOL bool
lib/libcurses/curses.h
286
#define NCURSES_BOOL bool
lib/libcurses/curses.h
508
bool _notimeout; /* no time out on function-key entry? */
lib/libcurses/curses.h
509
bool _clear; /* consider all data in the window invalid? */
lib/libcurses/curses.h
510
bool _leaveok; /* OK to not reset cursor on exit? */
lib/libcurses/curses.h
511
bool _scroll; /* OK to scroll this window? */
lib/libcurses/curses.h
512
bool _idlok; /* OK to use insert/delete line? */
lib/libcurses/curses.h
513
bool _idcok; /* OK to use insert/delete char? */
lib/libcurses/curses.h
514
bool _immed; /* window in immed mode? (not yet used) */
lib/libcurses/curses.h
515
bool _sync; /* window in sync mode? */
lib/libcurses/curses.h
516
bool _use_keypad; /* process function keys into KEY_ symbols? */
lib/libcurses/curses.h
626
extern NCURSES_EXPORT(bool) can_change_color (void); /* implemented */
lib/libcurses/curses.h
630
extern NCURSES_EXPORT(int) clearok (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
662
extern NCURSES_EXPORT(bool) has_colors (void); /* implemented */
lib/libcurses/curses.h
663
extern NCURSES_EXPORT(bool) has_ic (void); /* implemented */
lib/libcurses/curses.h
664
extern NCURSES_EXPORT(bool) has_il (void); /* implemented */
lib/libcurses/curses.h
666
extern NCURSES_EXPORT(void) idcok (WINDOW *, bool); /* implemented */
lib/libcurses/curses.h
667
extern NCURSES_EXPORT(int) idlok (WINDOW *, bool); /* implemented */
lib/libcurses/curses.h
668
extern NCURSES_EXPORT(void) immedok (WINDOW *, bool); /* implemented */
lib/libcurses/curses.h
682
extern NCURSES_EXPORT(int) intrflush (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
683
extern NCURSES_EXPORT(bool) isendwin (void); /* implemented */
lib/libcurses/curses.h
684
extern NCURSES_EXPORT(bool) is_linetouched (WINDOW *,int); /* implemented */
lib/libcurses/curses.h
685
extern NCURSES_EXPORT(bool) is_wintouched (WINDOW *); /* implemented */
lib/libcurses/curses.h
687
extern NCURSES_EXPORT(int) keypad (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
689
extern NCURSES_EXPORT(int) leaveok (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
691
extern NCURSES_EXPORT(int) meta (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
750
extern NCURSES_EXPORT(int) nodelay (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
755
extern NCURSES_EXPORT(int) notimeout (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
781
extern NCURSES_EXPORT(int) scrollok (WINDOW *,bool); /* implemented */
lib/libcurses/curses.h
807
extern NCURSES_EXPORT(int) syncok (WINDOW *, bool); /* implemented */
lib/libcurses/curses.h
816
extern NCURSES_EXPORT(void) use_env (bool); /* implemented */
lib/libcurses/curses.h
817
extern NCURSES_EXPORT(void) use_tioctl (bool); /* implemented */
lib/libcurses/curses.h
948
extern NCURSES_EXPORT(bool) is_term_resized (int, int);
lib/libcurses/curses.h
951
extern NCURSES_EXPORT(int) keyok (int, bool);
lib/libcurses/curses.h
967
extern NCURSES_EXPORT(int) use_extended_names (bool);
lib/libcurses/curses.h
975
extern NCURSES_EXPORT(bool) is_cleared (const WINDOW *); /* generated */
lib/libcurses/curses.h
976
extern NCURSES_EXPORT(bool) is_idcok (const WINDOW *); /* generated */
lib/libcurses/curses.h
977
extern NCURSES_EXPORT(bool) is_idlok (const WINDOW *); /* generated */
lib/libcurses/curses.h
978
extern NCURSES_EXPORT(bool) is_immedok (const WINDOW *); /* generated */
lib/libcurses/curses.h
979
extern NCURSES_EXPORT(bool) is_keypad (const WINDOW *); /* generated */
lib/libcurses/curses.h
980
extern NCURSES_EXPORT(bool) is_leaveok (const WINDOW *); /* generated */
lib/libcurses/curses.h
981
extern NCURSES_EXPORT(bool) is_nodelay (const WINDOW *); /* generated */
lib/libcurses/curses.h
982
extern NCURSES_EXPORT(bool) is_notimeout (const WINDOW *); /* generated */
lib/libcurses/curses.h
983
extern NCURSES_EXPORT(bool) is_pad (const WINDOW *); /* generated */
lib/libcurses/curses.h
984
extern NCURSES_EXPORT(bool) is_scrollok (const WINDOW *); /* generated */
lib/libcurses/curses.h
985
extern NCURSES_EXPORT(bool) is_subwin (const WINDOW *); /* generated */
lib/libcurses/curses.h
986
extern NCURSES_EXPORT(bool) is_syncok (const WINDOW *); /* generated */
lib/libcurses/curses.priv.h
1012
bool _notty; /* true if we cannot switch non-tty */
lib/libcurses/curses.priv.h
1067
bool * _screen_acs_map;
lib/libcurses/curses.priv.h
1071
bool _use_rmso; /* true if we may use 'rmso' */
lib/libcurses/curses.priv.h
1072
bool _use_rmul; /* true if we may use 'rmul' */
lib/libcurses/curses.priv.h
1081
bool _nc_sp_idlok;
lib/libcurses/curses.priv.h
1082
bool _nc_sp_idcok;
lib/libcurses/curses.priv.h
1087
bool _mouse_initialized;
lib/libcurses/curses.priv.h
1090
bool (*_mouse_event) (SCREEN *);
lib/libcurses/curses.priv.h
1091
bool (*_mouse_inline)(SCREEN *);
lib/libcurses/curses.priv.h
1092
bool (*_mouse_parse) (SCREEN *, int);
lib/libcurses/curses.priv.h
1096
bool _mouse_active; /* true if initialized */
lib/libcurses/curses.priv.h
1111
bool _sig_winch;
lib/libcurses/curses.priv.h
1130
bool _no_padding; /* flag to set if padding disabled */
lib/libcurses/curses.priv.h
1140
bool _use_ritm; /* true if we may use 'ritm' */
lib/libcurses/curses.priv.h
1145
bool _extended_key; /* true if an extended key */
lib/libcurses/curses.priv.h
1150
bool _assumed_color; /* use assumed colors */
lib/libcurses/curses.priv.h
1151
bool _default_color; /* use default colors */
lib/libcurses/curses.priv.h
1152
bool _has_sgr_39_49; /* has ECMA default color support */
lib/libcurses/curses.priv.h
1160
bool _mouse_gpm_loaded;
lib/libcurses/curses.priv.h
1161
bool _mouse_gpm_found;
lib/libcurses/curses.priv.h
1218
bool use_tioctl;
lib/libcurses/curses.priv.h
1228
bool _screen_acs_fix;
lib/libcurses/curses.priv.h
1229
bool _screen_unicode;
lib/libcurses/curses.priv.h
1684
#define returnBool(code) TRACE_RETURN(code,bool)
lib/libcurses/curses.priv.h
1940
extern NCURSES_EXPORT(bool) _nc_is_charable(wchar_t);
lib/libcurses/curses.priv.h
1998
extern NCURSES_EXPORT(bool) _nc_reset_colors(void);
lib/libcurses/curses.priv.h
2028
extern NCURSES_EXPORT(bool) _nc_has_mouse (SCREEN *);
lib/libcurses/curses.priv.h
2100
extern NCURSES_EXPORT(bool) _nc_safe_strcat (string_desc *, const char *);
lib/libcurses/curses.priv.h
2101
extern NCURSES_EXPORT(bool) _nc_safe_strcpy (string_desc *, const char *);
lib/libcurses/curses.priv.h
2365
bool caninit;
lib/libcurses/curses.priv.h
2367
bool hascolor;
lib/libcurses/curses.priv.h
2368
bool initcolor;
lib/libcurses/curses.priv.h
2369
bool canchange;
lib/libcurses/curses.priv.h
2386
bool isTerminfo;
lib/libcurses/curses.priv.h
2388
bool (*td_CanHandle)(struct DriverTCB*, const char*, int*);
lib/libcurses/curses.priv.h
2396
bool (*td_rescol)(struct DriverTCB*);
lib/libcurses/curses.priv.h
2397
bool (*td_rescolors)(struct DriverTCB*);
lib/libcurses/curses.priv.h
2421
bool (*td_kyExist)(struct DriverTCB*, int);
lib/libcurses/curses.priv.h
2574
extern NCURSES_EXPORT(bool) NCURSES_SP_NAME(_nc_reset_colors)(SCREEN*);
lib/libcurses/curses.priv.h
711
extern NCURSES_EXPORT(void) _nc_set_read_thread(bool);
lib/libcurses/curses.priv.h
841
bool dirty; /* all labels have changed */
lib/libcurses/curses.priv.h
842
bool hidden; /* soft labels are hidden */
lib/libcurses/curses.priv.h
973
bool _filtered; /* filter() was called */
lib/libcurses/curses.priv.h
974
bool _prescreen; /* is in prescreen phase */
lib/libcurses/curses.priv.h
975
bool _use_env; /* LINES & COLS from environment? */
lib/libcurses/curses.priv.h
995
bool _tried; /* keypad mode was initialized */
lib/libcurses/curses.priv.h
996
bool _keypad_on; /* keypad mode is currently on */
lib/libcurses/curses.priv.h
998
bool _called_wgetch; /* check for recursion in wgetch() */
lib/libcurses/hashed_db.h
63
extern NCURSES_EXPORT(DB *) _nc_db_open(const char * /* path */, bool /* modify */);
lib/libcurses/hashed_db.h
64
extern NCURSES_EXPORT(bool) _nc_db_have_data(DBT * /* key */, DBT * /* data */, char ** /* buffer */, int * /* size */);
lib/libcurses/hashed_db.h
65
extern NCURSES_EXPORT(bool) _nc_db_have_index(DBT * /* key */, DBT * /* data */, char ** /* buffer */, int * /* size */);
lib/libcurses/term.priv.h
139
bool last_used;
lib/libcurses/term.priv.h
161
bool init_signals;
lib/libcurses/term.priv.h
162
bool init_screen;
lib/libcurses/term.priv.h
167
bool have_tic_directory;
lib/libcurses/term.priv.h
168
bool keep_tic_directory;
lib/libcurses/term.priv.h
240
bool trace_opened;
lib/libcurses/term.priv.h
269
bool leak_checking;
lib/libcurses/term.priv.h
295
bool use_env;
lib/libcurses/term.priv.h
296
bool filter_mode;
lib/libcurses/term.priv.h
300
bool use_tioctl;
lib/libcurses/term.priv.h
307
bool _no_padding; /* flag to set if padding disabled */
lib/libcurses/term.priv.h
74
bool num_type;
lib/libcurses/term_entry.h
144
#define NULLHOOK (bool(*)(ENTRY *))0
lib/libcurses/term_entry.h
176
extern NCURSES_EXPORT(void) _nc_wrap_entry (ENTRY *const, bool);
lib/libcurses/term_entry.h
191
extern NCURSES_EXPORT_VAR(bool) _nc_user_definable;
lib/libcurses/term_entry.h
192
extern NCURSES_EXPORT_VAR(bool) _nc_disable_period;
lib/libcurses/term_entry.h
194
extern NCURSES_EXPORT(int) _nc_parse_entry (ENTRY *, int, bool);
lib/libcurses/term_entry.h
203
extern NCURSES_EXPORT(void) _nc_read_entry_source (FILE*, char*, int, bool, bool (*)(ENTRY*));
lib/libcurses/term_entry.h
204
extern NCURSES_EXPORT(bool) _nc_entry_match (char *, char *);
lib/libcurses/term_entry.h
205
extern NCURSES_EXPORT(int) _nc_resolve_uses (bool); /* obs 20040705 */
lib/libcurses/term_entry.h
206
extern NCURSES_EXPORT(int) _nc_resolve_uses2 (bool, bool);
lib/libcurses/term_entry.h
209
extern NCURSES_IMPEXP void (NCURSES_API *_nc_check_termtype2)(TERMTYPE2 *, bool);
lib/libcurses/tic.h
272
extern NCURSES_EXPORT(bool) _nc_is_abs_path (const char *);
lib/libcurses/tic.h
273
extern NCURSES_EXPORT(bool) _nc_is_dir_path (const char *);
lib/libcurses/tic.h
274
extern NCURSES_EXPORT(bool) _nc_is_file_path (const char *);
lib/libcurses/tic.h
279
extern NCURSES_EXPORT(const struct name_table_entry *) _nc_get_table (bool);
lib/libcurses/tic.h
280
extern NCURSES_EXPORT(const HashData *) _nc_get_hash_info (bool);
lib/libcurses/tic.h
281
extern NCURSES_EXPORT(const struct alias *) _nc_get_alias_table (bool);
lib/libcurses/tic.h
285
(const char *, int, bool);
lib/libcurses/tic.h
290
extern NCURSES_EXPORT(int) _nc_get_token (bool);
lib/libcurses/tic.h
312
extern NCURSES_EXPORT_VAR(bool) _nc_suppress_warnings;
lib/libcurses/tic.h
353
extern NCURSES_EXPORT(char *) _nc_tic_expand (const char *, bool, int);
lib/libcurses/tic.h
358
extern NCURSES_EXPORT(const HashValue *) _nc_get_hash_table (bool);
lib/libcurses/tinfo/access.c
163
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/access.c
166
bool result = FALSE;
lib/libcurses/tinfo/access.c
176
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/access.c
179
bool result = FALSE;
lib/libcurses/tinfo/access.c
95
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/alloc_entry.c
141
_nc_wrap_entry(ENTRY * const ep, bool copy_strings)
lib/libcurses/tinfo/alloc_ttype.c
275
static bool
lib/libcurses/tinfo/alloc_ttype.c
440
bool used_ext_Names = FALSE;
lib/libcurses/tinfo/alloc_ttype.c
447
bool same;
lib/libcurses/tinfo/alloc_ttype.c
83
static bool
lib/libcurses/tinfo/captoinfo.c
632
bool syntax_error = FALSE;
lib/libcurses/tinfo/captoinfo.c
786
bool will_fix = TRUE;
lib/libcurses/tinfo/comp_error.c
49
NCURSES_EXPORT_VAR(bool) _nc_suppress_warnings = FALSE;
lib/libcurses/tinfo/comp_expand.c
63
_nc_tic_expand(const char *srcp, bool tic_format, int numbers)
lib/libcurses/tinfo/comp_hash.c
60
bool termcap = (hash_table != _nc_get_hash_table(FALSE));
lib/libcurses/tinfo/comp_hash.c
97
bool termcap)
lib/libcurses/tinfo/comp_parse.c
111
static bool
lib/libcurses/tinfo/comp_parse.c
167
static bool
lib/libcurses/tinfo/comp_parse.c
172
bool removed = FALSE;
lib/libcurses/tinfo/comp_parse.c
204
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/comp_parse.c
218
int literal, bool silent,
lib/libcurses/tinfo/comp_parse.c
219
bool(*hook) (ENTRY *))
lib/libcurses/tinfo/comp_parse.c
223
bool oldsuppress = _nc_suppress_warnings;
lib/libcurses/tinfo/comp_parse.c
403
_nc_resolve_uses2(bool fullresolve, bool literal)
lib/libcurses/tinfo/comp_parse.c
407
bool keepgoing;
lib/libcurses/tinfo/comp_parse.c
451
bool foundit;
lib/libcurses/tinfo/comp_parse.c
55
static void sanity_check2(TERMTYPE2 *, bool);
lib/libcurses/tinfo/comp_parse.c
56
NCURSES_IMPEXP void (NCURSES_API *_nc_check_termtype2) (TERMTYPE2 *, bool) = sanity_check2;
lib/libcurses/tinfo/comp_parse.c
692
sanity_check2(TERMTYPE2 *tp, bool literal)
lib/libcurses/tinfo/comp_parse.c
696
bool terminal_entry = !strchr(tp->term_names, '+');
lib/libcurses/tinfo/comp_scan.c
319
static bool
lib/libcurses/tinfo/comp_scan.c
386
_nc_get_token(bool silent)
lib/libcurses/tinfo/comp_scan.c
540
bool capability = FALSE;
lib/libcurses/tinfo/comp_scan.c
84
static bool first_column; /* See 'next_char()' below */
lib/libcurses/tinfo/comp_scan.c
845
bool ignored = FALSE;
lib/libcurses/tinfo/comp_scan.c
846
bool long_warning = FALSE;
lib/libcurses/tinfo/comp_scan.c
85
static bool had_newline;
lib/libcurses/tinfo/comp_scan.c
875
bool strict_bsd = ((_nc_syntax == SYN_TERMCAP) && _nc_strict_bsd);
lib/libcurses/tinfo/comp_scan.c
91
NCURSES_EXPORT_VAR (bool) _nc_disable_period = FALSE; /* used by tic -a option */
lib/libcurses/tinfo/db_iterator.c
122
static bool
lib/libcurses/tinfo/db_iterator.c
125
bool result = FALSE;
lib/libcurses/tinfo/db_iterator.c
130
bool same_value;
lib/libcurses/tinfo/db_iterator.c
179
static bool
lib/libcurses/tinfo/db_iterator.c
182
bool result = FALSE;
lib/libcurses/tinfo/db_iterator.c
289
bool cache_has_expired = FALSE;
lib/libcurses/tinfo/db_iterator.c
413
bool found = check_existence(my_list[j], &my_stat[j]);
lib/libcurses/tinfo/db_iterator.c
73
static bool
lib/libcurses/tinfo/db_iterator.c
76
bool result = FALSE;
lib/libcurses/tinfo/free_ttype.c
51
really_free_termtype(TERMTYPE2 *ptr, bool freeStrings)
lib/libcurses/tinfo/free_ttype.c
95
NCURSES_EXPORT_VAR(bool) _nc_user_definable = TRUE;
lib/libcurses/tinfo/free_ttype.c
98
use_extended_names(bool flag)
lib/libcurses/tinfo/hashed_db.c
100
make_connection(DB * db, const char *path, bool modify)
lib/libcurses/tinfo/hashed_db.c
121
_nc_db_open(const char *path, bool modify)
lib/libcurses/tinfo/hashed_db.c
288
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/hashed_db.c
291
bool result = FALSE;
lib/libcurses/tinfo/hashed_db.c
311
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/hashed_db.c
314
bool result = FALSE;
lib/libcurses/tinfo/hashed_db.c
52
bool modify;
lib/libcurses/tinfo/hashed_db.c
66
find_connection(const char *path, bool modify)
lib/libcurses/tinfo/lib_data.c
310
static bool initialized = FALSE;
lib/libcurses/tinfo/lib_has_cap.c
54
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_has_cap.c
57
bool code = FALSE;
lib/libcurses/tinfo/lib_has_cap.c
71
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_has_cap.c
78
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_has_cap.c
81
bool code = FALSE;
lib/libcurses/tinfo/lib_has_cap.c
92
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_options.c
110
nodelay(WINDOW *win, bool flag)
lib/libcurses/tinfo/lib_options.c
125
notimeout(WINDOW *win, bool f)
lib/libcurses/tinfo/lib_options.c
148
keypad(WINDOW *win, bool flag)
lib/libcurses/tinfo/lib_options.c
160
meta(WINDOW *win GCC_UNUSED, bool flag)
lib/libcurses/tinfo/lib_options.c
55
idlok(WINDOW *win, bool flag)
lib/libcurses/tinfo/lib_options.c
77
idcok(WINDOW *win, bool flag)
lib/libcurses/tinfo/lib_raw.c
362
NCURSES_SP_NAME(intrflush) (NCURSES_SP_DCLx WINDOW *win GCC_UNUSED, bool flag)
lib/libcurses/tinfo/lib_raw.c
395
intrflush(WINDOW *win GCC_UNUSED, bool flag)
lib/libcurses/tinfo/lib_setup.c
228
NCURSES_SP_NAME(use_env) (NCURSES_SP_DCLx bool f)
lib/libcurses/tinfo/lib_setup.c
243
NCURSES_SP_NAME(use_tioctl) (NCURSES_SP_DCLx bool f)
lib/libcurses/tinfo/lib_setup.c
259
use_env(bool f)
lib/libcurses/tinfo/lib_setup.c
268
use_tioctl(bool f)
lib/libcurses/tinfo/lib_setup.c
307
bool useEnv = _nc_prescreen.use_env;
lib/libcurses/tinfo/lib_setup.c
308
bool useTioctl = _nc_prescreen.use_tioctl;
lib/libcurses/tinfo/lib_termcap.c
127
bool same_result = (MyCache[n].last_used && MyCache[n].last_bufp == bufp);
lib/libcurses/tinfo/lib_termcap.c
218
static bool
lib/libcurses/tinfo/lib_termcap.c
221
bool code = SameCap(a, b);
lib/libcurses/tinfo/lib_termcap.c
98
bool found_cache = FALSE;
lib/libcurses/tinfo/lib_tgoto.c
44
static bool
lib/libcurses/tinfo/lib_tgoto.c
47
bool result = TRUE;
lib/libcurses/tinfo/lib_tgoto.c
82
bool need_BC = FALSE;
lib/libcurses/tinfo/lib_ti.c
45
static bool
lib/libcurses/tinfo/lib_tparm.c
1103
static bool
lib/libcurses/tinfo/lib_tparm.c
1106
bool result = FALSE;
lib/libcurses/tinfo/lib_tparm.c
367
bool done = FALSE;
lib/libcurses/tinfo/lib_tparm.c
368
bool allowminus = FALSE;
lib/libcurses/tinfo/lib_tparm.c
369
bool dot = FALSE;
lib/libcurses/tinfo/lib_tparm.c
370
bool err = FALSE;
lib/libcurses/tinfo/lib_tparm.c
716
static bool
lib/libcurses/tinfo/lib_tparm.c
719
bool termcap_hack = FALSE;
lib/libcurses/tinfo/lib_tparm.c
783
bool incremented_two = FALSE;
lib/libcurses/tinfo/lib_tparm.c
784
bool termcap_hack = tparm_tc_compat(tps, data);
lib/libcurses/tinfo/lib_tparm.c
798
bool dynamic_used = FALSE;
lib/libcurses/tinfo/lib_tputs.c
282
bool always_delay = FALSE;
lib/libcurses/tinfo/lib_tputs.c
283
bool normal_delay = FALSE;
lib/libcurses/tinfo/lib_tputs.c
375
bool mandatory;
lib/libcurses/tinfo/lib_tputs.c
68
bool no_padding = (getenv("NCURSES_NO_PADDING") != 0);
lib/libcurses/tinfo/lib_win32con.c
100
static bool console_initialized = FALSE;
lib/libcurses/tinfo/lib_win32con.c
1118
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_win32con.c
1119
_nc_console_checkinit(bool initFlag, bool assumeTermInfo)
lib/libcurses/tinfo/lib_win32con.c
1121
bool res = FALSE;
lib/libcurses/tinfo/lib_win32con.c
356
_nc_console_MapColor(bool fore, int color)
lib/libcurses/tinfo/lib_win32con.c
377
static bool
lib/libcurses/tinfo/lib_win32con.c
380
bool result = FALSE;
lib/libcurses/tinfo/lib_win32con.c
408
static bool
lib/libcurses/tinfo/lib_win32con.c
412
bool result = FALSE;
lib/libcurses/tinfo/lib_win32con.c
444
static bool
lib/libcurses/tinfo/lib_win32con.c
447
bool result = FALSE;
lib/libcurses/tinfo/lib_win32con.c
489
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_win32con.c
492
bool rc = FALSE;
lib/libcurses/tinfo/lib_win32con.c
530
_nc_console_set_scrollback(bool normal, CONSOLE_SCREEN_BUFFER_INFO * info)
lib/libcurses/tinfo/lib_win32con.c
534
bool changed = FALSE;
lib/libcurses/tinfo/lib_win32con.c
61
static bool read_screen_data(void);
lib/libcurses/tinfo/lib_win32con.c
673
static bool
lib/libcurses/tinfo/lib_win32con.c
677
bool result = FALSE;
lib/libcurses/tinfo/lib_win32con.c
806
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/lib_win32con.c
811
bool found = FALSE;
lib/libcurses/tinfo/lib_win32con.c
845
bool isNoDelay = (milliseconds == 0);
lib/libcurses/tinfo/make_hash.c
259
bool is_user;
lib/libcurses/tinfo/make_keys.c
70
bool found = FALSE;
lib/libcurses/tinfo/obsolete.c
260
static bool
lib/libcurses/tinfo/obsolete.c
263
static bool initialized = FALSE;
lib/libcurses/tinfo/obsolete.c
264
static bool triggered = FALSE;
lib/libcurses/tinfo/obsolete.c
265
bool result = FALSE;
lib/libcurses/tinfo/parse_entry.c
204
static bool
lib/libcurses/tinfo/parse_entry.c
205
expected_type(const char *name, int token_type, bool silent)
lib/libcurses/tinfo/parse_entry.c
208
bool result = TRUE;
lib/libcurses/tinfo/parse_entry.c
241
static bool
lib/libcurses/tinfo/parse_entry.c
244
bool result = TRUE;
lib/libcurses/tinfo/parse_entry.c
245
bool first = TRUE;
lib/libcurses/tinfo/parse_entry.c
287
_nc_parse_entry(ENTRY * entryp, int literal, bool silent)
lib/libcurses/tinfo/parse_entry.c
293
bool bad_tc_usage = FALSE;
lib/libcurses/tinfo/parse_entry.c
371
bool is_use = (strcmp(_nc_curr_token.tk_name, "use") == 0);
lib/libcurses/tinfo/parse_entry.c
372
bool is_tc = !is_use && (strcmp(_nc_curr_token.tk_name, "tc") == 0);
lib/libcurses/tinfo/parse_entry.c
618
bool has_base_entry = FALSE;
lib/libcurses/tinfo/parse_entry.c
62
static void postprocess_termcap(TERMTYPE2 *, bool);
lib/libcurses/tinfo/parse_entry.c
653
bool ok_s = VALID_STRING(s);
lib/libcurses/tinfo/parse_entry.c
654
bool ok_t = VALID_STRING(t);
lib/libcurses/tinfo/parse_entry.c
77
bool found;
lib/libcurses/tinfo/parse_entry.c
773
postprocess_termcap(TERMTYPE2 *tp, bool has_base)
lib/libcurses/tinfo/parse_entry.c
930
bool foundim;
lib/libcurses/tinfo/read_entry.c
143
static bool
lib/libcurses/tinfo/read_entry.c
145
char *table, bool always)
lib/libcurses/tinfo/read_entry.c
149
bool success = TRUE;
lib/libcurses/tinfo/read_entry.c
263
static bool
lib/libcurses/tinfo/read_entry.c
266
bool result = FALSE;
lib/libcurses/tinfo/read_entry.c
622
static bool
lib/libcurses/tinfo/read_entry.c
630
bool result = FALSE;
lib/libcurses/tinfo/read_entry.c
647
static bool
lib/libcurses/tinfo/read_entry.c
653
bool result = FALSE;
lib/libcurses/tinfo/read_termcap.c
1037
bool use_buffer = FALSE;
lib/libcurses/tinfo/read_termcap.c
1038
bool normal = TRUE;
lib/libcurses/tinfo/read_termcap.c
1089
bool omit = FALSE;
lib/libcurses/tinfo/read_termcap.c
723
bool found = FALSE;
lib/libcurses/tinfo/read_termcap.c
881
bool ignore = FALSE;
lib/libcurses/tinfo/setbuf.c
103
_nc_set_buffer(FILE *ofp, bool buffered)
lib/libcurses/tinfo/strings.c
109
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/strings.c
130
NCURSES_EXPORT(bool)
lib/libcurses/tinfo/tinfo_driver.c
1163
bool support_cookies = USE_XMC_SUPPORT;
lib/libcurses/tinfo/tinfo_driver.c
1441
static bool
lib/libcurses/tinfo/tinfo_driver.c
1444
bool res = FALSE;
lib/libcurses/tinfo/tinfo_driver.c
155
static bool
lib/libcurses/tinfo/tinfo_driver.c
158
bool result = FALSE;
lib/libcurses/tinfo/tinfo_driver.c
335
bool save = sp->_default_color;
lib/libcurses/tinfo/tinfo_driver.c
385
static bool
lib/libcurses/tinfo/tinfo_driver.c
388
bool result = FALSE;
lib/libcurses/tinfo/tinfo_driver.c
401
static bool
lib/libcurses/tinfo/tinfo_driver.c
421
bool useEnv = TRUE;
lib/libcurses/tinfo/tinfo_driver.c
422
bool useTioctl = TRUE;
lib/libcurses/tinfo/trim_sgr0.c
107
static bool
lib/libcurses/tinfo/trim_sgr0.c
130
static bool
lib/libcurses/tinfo/trim_sgr0.c
133
bool result = FALSE;
lib/libcurses/tinfo/trim_sgr0.c
246
bool found = FALSE;
lib/libcurses/tinfo/write_entry.c
128
static bool verified[sizeof(dirnames)];
lib/libcurses/tinfo/write_entry.c
227
bool specific = (dir != NULL);
lib/libcurses/tinfo/write_entry.c
237
bool success = FALSE;
lib/libcurses/tinfo/write_entry.c
705
static bool
lib/libcurses/tinfo/write_entry.c
708
bool result = FALSE;
lib/libcurses/tinfo/write_entry.c
733
bool need_ints = FALSE;
lib/libcurses/trace/lib_trace.c
231
bool before = FALSE;
lib/libcurses/trace/lib_trace.c
232
bool after = FALSE;
lib/libcurses/trace/lib_trace.c
392
bool leading = TRUE;
lib/libcurses/trace/lib_trace.c
431
bool result = FALSE;
lib/libcurses/tty/hashmap.c
176
static NCURSES_INLINE bool
lib/libcurses/tty/lib_mvcur.c
178
static bool profiling = FALSE;
lib/libcurses/tty/lib_tstp.c
290
_nc_set_read_thread(bool enable)
lib/libcurses/tty/lib_tstp.c
394
static bool ignore_tstp = FALSE;
lib/libcurses/tty/lib_vidattr.c
118
bool reverse = FALSE;
lib/libcurses/tty/lib_vidattr.c
119
bool can_color = (SP_PARM == 0 || SP_PARM->_coloron);
lib/libcurses/tty/lib_vidattr.c
121
bool fix_pair0 = (SP_PARM != 0 && SP_PARM->_coloron && !SP_PARM->_default_color);
lib/libcurses/tty/tty_display.h
102
bool _sig_winch;
lib/libcurses/tty/tty_display.h
37
extern NCURSES_EXPORT(bool) _nc_tty_beep (void);
lib/libcurses/tty/tty_display.h
38
extern NCURSES_EXPORT(bool) _nc_tty_check_resize (void);
lib/libcurses/tty/tty_display.h
39
extern NCURSES_EXPORT(bool) _nc_tty_cursor (int);
lib/libcurses/tty/tty_display.h
40
extern NCURSES_EXPORT(bool) _nc_tty_flash (void);
lib/libcurses/tty/tty_display.h
41
extern NCURSES_EXPORT(bool) _nc_tty_init_color (int,int,int,int);
lib/libcurses/tty/tty_display.h
42
extern NCURSES_EXPORT(bool) _nc_tty_init_pair (int,int,int);
lib/libcurses/tty/tty_display.h
43
extern NCURSES_EXPORT(bool) _nc_tty_slk_hide (bool);
lib/libcurses/tty/tty_display.h
44
extern NCURSES_EXPORT(bool) _nc_tty_slk_update (int,const char *);
lib/libcurses/tty/tty_display.h
45
extern NCURSES_EXPORT(bool) _nc_tty_start_color (void);
lib/libcurses/tty/tty_input.h
38
extern NCURSES_EXPORT(bool) _nc_tty_mouse_mask (mmask_t);
lib/libcurses/tty/tty_input.h
39
extern NCURSES_EXPORT(bool) _nc_tty_pending (void);
lib/libcurses/tty/tty_input.h
54
bool (*_mouse_event) (SCREEN *);
lib/libcurses/tty/tty_input.h
55
bool (*_mouse_inline)(SCREEN *);
lib/libcurses/tty/tty_input.h
56
bool (*_mouse_parse) (int);
lib/libcurses/tty/tty_update.c
1246
bool ok;
lib/libcurses/tty/tty_update.c
1312
bool attrchanged = FALSE;
lib/libcurses/tty/tty_update.c
1645
bool fast_clear = (clear_screen || clr_eos || clr_eol);
lib/libcurses/tty/tty_update.c
2017
bool cursor_saved = FALSE;
lib/libcurses/tty/tty_update.c
368
static bool
lib/libcurses/tty/tty_update.c
372
bool have_pending = FALSE;
lib/libcurses/tty/tty_update.c
530
static NCURSES_INLINE bool
lib/libcurses/tty/tty_update.c
637
bool wrap_possible = (SP_PARM->_curscol + runcount >=
lib/libcurses/tty/tty_update.c
849
bool failed = FALSE;
lib/libcurses/tty/tty_update.c
893
bool end_onscreen = FALSE;
lib/libcurses/widechar/charable.c
40
NCURSES_EXPORT(bool) _nc_is_charable(wchar_t ch)
lib/libcurses/widechar/charable.c
42
bool result;
lib/libcurses/widechar/lib_add_wch.c
119
static bool
lib/libcurses/widechar/lib_add_wch.c
122
bool result = FALSE;
lib/libcurses/widechar/lib_add_wch.c
444
bool save_immed = win->_immed;
lib/libcurses/widechar/lib_inwstr.c
58
bool done = FALSE;
lib/libcurses/widechar/lib_vid_attr.c
91
bool reverse = FALSE;
lib/libcurses/widechar/lib_vid_attr.c
92
bool can_color = (SP_PARM == 0 || SP_PARM->_coloron);
lib/libcurses/widechar/lib_vid_attr.c
94
bool fix_pair0 = (SP_PARM != 0 && SP_PARM->_coloron && !SP_PARM->_default_color);
lib/libexpat/examples/element_declarations.c
143
static bool
lib/libexpat/examples/element_declarations.c
182
const bool success = dumpContentModel(name, model);
lib/libexpat/lib/xmlparse.c
1277
const bool enough
lib/libexpat/lib/xmlparse.c
6665
bool checkEntityDecl;
lib/libexpat/lib/xmlparse.c
7469
const bool prefixNameUsed = prefix && prefix->name == prefixName;
lib/libexpat/lib/xmlparse.c
814
static bool
lib/libexpat/lib/xmlparse.c
821
bool tolerable = true;
lib/libexpat/lib/xmlparse.c
964
const bool isIncrease = (size > prevSize);
lib/libexpat/lib/xmltok.c
369
bool input_incomplete = false;
lib/libexpat/lib/xmltok.c
370
bool output_exhausted = false;
lib/libexpat/tests/alloc_tests.c
2105
bool values[] = {true, false};
lib/libexpat/tests/alloc_tests.c
2107
const bool useMemSuite = values[i];
lib/libexpat/tests/basic_tests.c
1225
bool usesParameterEntities;
lib/libexpat/tests/basic_tests.c
1260
const bool usesParameterEntities = cases[i].usesParameterEntities;
lib/libexpat/tests/basic_tests.c
1265
const bool rejection_expected = true;
lib/libexpat/tests/basic_tests.c
1267
const bool rejection_expected = ! usesParameterEntities;
lib/libexpat/tests/basic_tests.c
1269
const bool rejection_expected = false;
lib/libexpat/tests/basic_tests.c
347
bool success = true;
lib/libexpat/tests/basic_tests.c
4886
bool goodName;
lib/libexpat/tests/basic_tests.c
4887
bool goodNameStart;
lib/libexpat/tests/basic_tests.c
4938
const bool atNameStart[] = {true, false};
lib/libexpat/tests/basic_tests.c
4953
const bool expectedSuccess
lib/libexpat/tests/basic_tests.c
4962
bool success = true;
lib/libfido2/src/assert.c
622
fido_assert_set_options(fido_assert_t *assert, bool up, bool uv)
lib/libfido2/src/config.c
142
config_pin_minlen_tx(fido_dev_t *dev, size_t len, bool force,
lib/libfido2/src/config.c
182
config_pin_minlen(fido_dev_t *dev, size_t len, bool force,
lib/libfido2/src/cred.c
877
fido_cred_set_options(fido_cred_t *cred, bool rk, bool uv)
lib/libfido2/src/dev.c
13
static TLS bool disable_u2f_fallback;
lib/libfido2/src/dev.c
41
const bool *val = fido_cbor_info_options_value_ptr(info);
lib/libfido2/src/dev.c
507
bool
lib/libfido2/src/dev.c
513
bool
lib/libfido2/src/dev.c
519
bool
lib/libfido2/src/dev.c
525
bool
lib/libfido2/src/dev.c
531
bool
lib/libfido2/src/dev.c
537
bool
lib/libfido2/src/dev.c
543
bool
lib/libfido2/src/dev.c
549
bool
lib/libfido2/src/dev.c
555
bool
lib/libfido2/src/extern.h
121
bool fido_is_nfc(const char *);
lib/libfido2/src/extern.h
132
bool fido_is_pcsc(const char *);
lib/libfido2/src/fido.h
116
int fido_assert_set_options(fido_assert_t *, bool, bool);
lib/libfido2/src/fido.h
134
int fido_cred_set_options(fido_cred_t *, bool, bool);
lib/libfido2/src/fido.h
218
bool fido_dev_has_pin(const fido_dev_t *);
lib/libfido2/src/fido.h
219
bool fido_dev_has_uv(const fido_dev_t *);
lib/libfido2/src/fido.h
220
bool fido_dev_is_fido2(const fido_dev_t *);
lib/libfido2/src/fido.h
221
bool fido_dev_is_winhello(const fido_dev_t *);
lib/libfido2/src/fido.h
222
bool fido_dev_supports_credman(const fido_dev_t *);
lib/libfido2/src/fido.h
223
bool fido_dev_supports_cred_prot(const fido_dev_t *);
lib/libfido2/src/fido.h
224
bool fido_dev_supports_permissions(const fido_dev_t *);
lib/libfido2/src/fido.h
225
bool fido_dev_supports_pin(const fido_dev_t *);
lib/libfido2/src/fido.h
226
bool fido_dev_supports_uv(const fido_dev_t *);
lib/libfido2/src/fido.h
74
const bool *fido_cbor_info_options_value_ptr(const fido_cbor_info_t *);
lib/libfido2/src/fido/types.h
198
bool *value;
lib/libfido2/src/fido/types.h
267
bool io_own; /* device has own io/transport */
lib/libfido2/src/info.c
104
o->value = calloc(cbor_map_size(item), sizeof(bool));
lib/libfido2/src/info.c
430
const bool *
lib/libfido2/src/nfc.c
293
bool
lib/libform/fld_def.c
214
FORM_EXPORT(bool)
lib/libform/fld_ftchoice.c
53
bool (*const next_choice) (FIELD *, const void *),
lib/libform/fld_ftchoice.c
54
bool (*const prev_choice) (FIELD *, const void *))
lib/libform/fld_max.c
58
bool single_line_field = Single_Line_Field(field);
lib/libform/fld_newftyp.c
76
new_fieldtype(bool (*const field_check) (FIELD *, const void *),
lib/libform/fld_newftyp.c
77
bool (*const char_check) (int, const void *))
lib/libform/fld_page.c
50
set_new_page(FIELD *field, bool new_page_flag)
lib/libform/fld_page.c
76
FORM_EXPORT(bool)
lib/libform/fld_stat.c
49
set_field_status(FIELD *field, bool status)
lib/libform/fld_stat.c
73
FORM_EXPORT(bool)
lib/libform/form.h
185
bool (*ofcheck)(FIELD *,const void *); /* field validation */
lib/libform/form.h
186
bool (*gfcheck)(FORM*,FIELD *,const void*); /* generic field validation */
lib/libform/form.h
189
bool (*occheck)(int,const void *); /* character validation */
lib/libform/form.h
190
bool (*gccheck)(int,FORM*,
lib/libform/form.h
194
bool (*onext)(FIELD *,const void *); /* enumerate next value */
lib/libform/form.h
195
bool (*gnext)(FORM*,FIELD*,const void*); /* generic enumerate next */
lib/libform/form.h
198
bool (*oprev)(FIELD *,const void *); /* enumerate prev value */
lib/libform/form.h
199
bool (*gprev)(FORM*,FIELD*,const void*); /* generic enumerate prev */
lib/libform/form.h
203
bool (*fcheck)(FIELD *,const void *); /* field validation */
lib/libform/form.h
204
bool (*ccheck)(int,const void *); /* character validation */
lib/libform/form.h
206
bool (*next)(FIELD *,const void *); /* enumerate next value */
lib/libform/form.h
207
bool (*prev)(FIELD *,const void *); /* enumerate prev value */
lib/libform/form.h
341
bool (* const field_check)(FIELD *,const void *),
lib/libform/form.h
342
bool (* const char_check)(int,const void *));
lib/libform/form.h
352
bool (* const next_choice)(FIELD *,const void *),
lib/libform/form.h
353
bool (* const prev_choice)(FIELD *,const void *));
lib/libform/form.h
368
extern FORM_EXPORT(int) set_new_page (FIELD *,bool);
lib/libform/form.h
376
extern FORM_EXPORT(int) set_field_status (FIELD *,bool);
lib/libform/form.h
385
extern FORM_EXPORT(bool) new_page (const FIELD *);
lib/libform/form.h
386
extern FORM_EXPORT(bool) field_status (const FIELD *);
lib/libform/form.h
449
extern FORM_EXPORT(bool) data_ahead (const FORM *);
lib/libform/form.h
450
extern FORM_EXPORT(bool) data_behind (const FORM *);
lib/libform/form.priv.h
183
extern FORM_EXPORT(bool) _nc_Copy_Type (FIELD*, FIELD const *);
lib/libform/form.priv.h
191
extern FORM_EXPORT(bool) _nc_Internal_Validation (FORM*);
lib/libform/form.priv.h
206
_nc_generic_fieldtype(bool (*const field_check) (FORM*,
lib/libform/form.priv.h
209
bool (*const char_check) (int,
lib/libform/form.priv.h
213
bool (*const next)(FORM*,FIELD*,const void*),
lib/libform/form.priv.h
214
bool (*const prev)(FORM*,FIELD*,const void*),
lib/libform/form.priv.h
264
bool blank = FALSE; \
lib/libform/frm_data.c
136
FORM_EXPORT(bool)
lib/libform/frm_data.c
139
bool result = FALSE;
lib/libform/frm_data.c
146
bool cursor_moved = FALSE;
lib/libform/frm_data.c
49
FORM_EXPORT(bool)
lib/libform/frm_data.c
52
bool result = FALSE;
lib/libform/frm_data.c
85
NCURSES_INLINE static bool
lib/libform/frm_data.c
88
bool result = TRUE;
lib/libform/frm_driver.c
1091
static bool
lib/libform/frm_driver.c
1140
Display_Or_Erase_Field(FIELD *field, bool bEraseFlag)
lib/libform/frm_driver.c
1394
bool single_line_field = Single_Line_Field(field);
lib/libform/frm_driver.c
1752
bool again = FALSE;
lib/libform/frm_driver.c
2365
NCURSES_INLINE static bool
lib/libform/frm_driver.c
2387
NCURSES_INLINE static bool
lib/libform/frm_driver.c
2503
bool Last_Row = ((field->drows - 1) == form->currow);
lib/libform/frm_driver.c
2638
bool Last_Row = ((field->drows - 1) == form->currow);
lib/libform/frm_driver.c
2686
bool May_Do_It = !Last_Row && Is_There_Room_For_A_Line(form);
lib/libform/frm_driver.c
2727
bool There_Is_Room = Is_There_Room_For_A_Char_In_Line(form);
lib/libform/frm_driver.c
2763
bool Maybe_Done = (form->currow != (field->drows - 1)) &&
lib/libform/frm_driver.c
3042
static bool
lib/libform/frm_driver.c
3083
static bool
lib/libform/frm_driver.c
3181
static bool
lib/libform/frm_driver.c
3234
FORM_EXPORT(bool)
lib/libform/frm_driver.c
4101
bool There_Is_Room = Is_There_Room_For_A_Char_In_Line(form);
lib/libform/frm_driver.c
4115
bool End_Of_Field = (((field->drows - 1) == form->currow) &&
lib/libform/frm_driver.c
4182
bool There_Is_Room = Is_There_Room_For_A_Char_In_Line(form);
lib/libform/frm_driver.c
4196
bool End_Of_Field = (((field->drows - 1) == form->currow) &&
lib/libform/frm_driver.c
4956
bool found = FALSE;
lib/libform/frm_driver.c
652
static bool
lib/libform/frm_driver.c
655
bool result = FALSE;
lib/libform/frm_driver.c
659
bool single_line_field = Single_Line_Field(field);
lib/libform/frm_driver.c
669
bool need_visual_update = ((form != (FORM *)0) &&
lib/libform/frm_driver.c
872
static bool move_after_insert = TRUE;
lib/libform/frm_driver.c
878
bool is_public;
lib/libform/fty_alnum.c
140
static bool
lib/libform/fty_alnum.c
161
static bool
lib/libform/fty_alnum.c
166
bool result = (width < 0);
lib/libform/fty_alpha.c
140
static bool
lib/libform/fty_alpha.c
161
static bool
lib/libform/fty_alpha.c
166
bool result = (width < 0);
lib/libform/fty_enum.c
238
bool ccase)
lib/libform/fty_enum.c
289
static bool
lib/libform/fty_enum.c
293
bool ccase = ((const enumARG *)argp)->checkcase;
lib/libform/fty_enum.c
294
bool unique = ((const enumARG *)argp)->checkunique;
lib/libform/fty_enum.c
346
static bool
lib/libform/fty_enum.c
351
bool ccase = args->checkcase;
lib/libform/fty_enum.c
384
static bool
lib/libform/fty_enum.c
390
bool ccase = args->checkcase;
lib/libform/fty_enum.c
45
bool checkcase;
lib/libform/fty_enum.c
46
bool checkunique;
lib/libform/fty_generic.c
104
_nc_generic_fieldtype(bool (*const field_check) (FORM *, FIELD *, const void *),
lib/libform/fty_generic.c
105
bool (*const char_check) (int, FORM *, FIELD *, const
lib/libform/fty_generic.c
107
bool (*const next) (FORM *, FIELD *, const void *),
lib/libform/fty_generic.c
108
bool (*const prev) (FORM *, FIELD *, const void *),
lib/libform/fty_int.c
165
static bool
lib/libform/fty_int.c
174
bool result = FALSE;
lib/libform/fty_int.c
190
bool blank = FALSE;
lib/libform/fty_int.c
261
static bool
lib/libform/fty_ipv4.c
52
static bool
lib/libform/fty_ipv4.c
84
static bool
lib/libform/fty_num.c
183
static bool
lib/libform/fty_num.c
193
bool result = FALSE;
lib/libform/fty_num.c
209
bool blank = FALSE;
lib/libform/fty_num.c
299
static bool
lib/libform/fty_regex.c
333
static bool
lib/libform/fty_regex.c
337
bool match = FALSE;
lib/libkeynote/keynote.y
25
int bool;
lib/libkeynote/keynote.y
27
%type <bool> stringexp numexp expr floatexp
lib/libmenu/m_driver.c
124
bool found = FALSE, passed = FALSE;
lib/libmenu/m_driver.c
164
if (Is_Sub_String((bool)((menu->opt & O_IGNORECASE) != 0),
lib/libmenu/m_driver.c
68
static bool
lib/libmenu/m_driver.c
70
bool IgnoreCaseFlag,
lib/libmenu/m_global.c
176
MENU_EXPORT(bool)
lib/libmenu/m_global.c
295
calculate_actual_width(MENU *menu, bool name)
lib/libmenu/m_global.c
389
bool cycle = (menu->opt & O_NONCYCLIC) ? FALSE : TRUE;
lib/libmenu/m_global.c
556
bool mterm_called = FALSE;
lib/libmenu/m_global.c
557
bool iterm_called = FALSE;
lib/libmenu/m_item_new.c
62
static bool
lib/libmenu/m_item_val.c
59
set_item_value(ITEM *item, bool value)
lib/libmenu/m_item_val.c
98
MENU_EXPORT(bool)
lib/libmenu/m_item_vis.c
55
MENU_EXPORT(bool)
lib/libmenu/m_pad.c
67
bool do_refresh = (menu != (MENU *)0);
lib/libmenu/m_post.c
61
bool isfore = FALSE, isback = FALSE, isgrey = FALSE;
lib/libmenu/menu.h
100
bool value; /* Selection value */
lib/libmenu/menu.h
247
extern MENU_EXPORT(int) set_item_value(ITEM *, bool);
lib/libmenu/menu.h
269
extern MENU_EXPORT(bool) item_value(const ITEM *);
lib/libmenu/menu.h
270
extern MENU_EXPORT(bool) item_visible(const ITEM *);
lib/libmenu/menu.priv.h
130
extern MENU_EXPORT(bool) _nc_Connect_Items (MENU *, ITEM **);
lib/libradius/radius.h
443
bool radius_has_attr(const RADIUS_PACKET *, uint8_t);
lib/libradius/radius.h
444
bool radius_has_vs_attr(const RADIUS_PACKET *, uint32_t, uint8_t);
lib/libradius/radius_attr.c
351
bool
lib/libradius/radius_attr.c
361
bool
lib/libutil/ber.c
233
ober_add_boolean(struct ber_element *prev, int bool)
lib/libutil/ber.c
240
elm->be_numeric = bool ? 0xff : 0;
libexec/tradcpp/directive.c
129
ifstate_create(struct ifstate *prev, struct place *p, bool startstate)
libexec/tradcpp/directive.c
155
ifstate_push(struct place *p, bool startstate)
libexec/tradcpp/directive.c
182
bool doprint;
libexec/tradcpp/directive.c
184
bool val;
libexec/tradcpp/directive.c
215
bool doprint;
libexec/tradcpp/directive.c
233
bool doprint;
libexec/tradcpp/directive.c
251
bool doprint;
libexec/tradcpp/directive.c
288
bool doprint;
libexec/tradcpp/directive.c
413
bool
libexec/tradcpp/directive.c
49
bool curtrue;
libexec/tradcpp/directive.c
50
bool evertrue;
libexec/tradcpp/directive.c
51
bool seenelse;
libexec/tradcpp/directive.c
578
bool ifskip;
libexec/tradcpp/directive.c
64
bool incomment = false;
libexec/tradcpp/directive.c
645
bool incomment;
libexec/tradcpp/directive.c
65
bool inesc = false;
libexec/tradcpp/directive.c
66
bool inquote = false;
libexec/tradcpp/eval.c
208
bool
libexec/tradcpp/eval.c
224
bool
libexec/tradcpp/eval.c
244
bool
libexec/tradcpp/eval.c
281
bool
libexec/tradcpp/eval.c
650
bool
libexec/tradcpp/eval.c
671
bool
libexec/tradcpp/eval.c
687
bool
libexec/tradcpp/eval.c
738
bool
libexec/tradcpp/eval.c
743
bool result;
libexec/tradcpp/eval.h
32
bool eval(struct place *p, char *expr);
libexec/tradcpp/files.c
107
files_addbracketpath(const char *dir, bool issystem)
libexec/tradcpp/files.c
128
bool inquote = false;
libexec/tradcpp/files.c
177
file_read(const struct placefile *pf, int fd, const char *name, bool toplevel)
libexec/tradcpp/files.c
183
bool ateof = false;
libexec/tradcpp/files.c
323
bool needslash = false;
libexec/tradcpp/files.c
46
bool issystem;
libexec/tradcpp/files.c
59
incdir_create(const char *name, bool issystem)
libexec/tradcpp/files.c
98
files_addquotepath(const char *dir, bool issystem)
libexec/tradcpp/files.h
35
void files_addquotepath(const char *dir, bool issystem);
libexec/tradcpp/files.h
36
void files_addbracketpath(const char *dir, bool issystem);
libexec/tradcpp/macro.c
1159
bool inquote = false;
libexec/tradcpp/macro.c
1244
macroexpand(struct place *p, const char *buf, size_t len, bool honordefined)
libexec/tradcpp/macro.c
155
bool
libexec/tradcpp/macro.c
212
bool
libexec/tradcpp/macro.c
343
macrotable_findlen(const char *name, size_t len, bool remove_it)
libexec/tradcpp/macro.c
380
macrotable_find(const char *name, bool remove_it)
libexec/tradcpp/macro.c
484
bool ok;
libexec/tradcpp/macro.c
549
bool
libexec/tradcpp/macro.c
63
bool hasparams;
libexec/tradcpp/macro.c
66
bool inuse;
libexec/tradcpp/macro.c
660
bool
libexec/tradcpp/macro.c
673
bool honordefined;
libexec/tradcpp/macro.c
679
bool tobuf;
libexec/tradcpp/macro.c
691
expstate_init(struct expstate *es, bool tobuf, bool honordefined)
libexec/tradcpp/macro.c
925
expand_missingargs(struct expstate *es, struct place *p, bool needspace)
libexec/tradcpp/macro.h
45
bool macro_isdefined(const char *macro);
libexec/tradcpp/macro.h
48
bool honordefined);
libexec/tradcpp/main.c
261
bool suppress_output;
libexec/tradcpp/main.c
294
commandline_addfile(const struct place *p, char *name, bool suppress_output)
libexec/tradcpp/main.c
325
bool save = false;
libexec/tradcpp/main.c
755
bool *flag;
libexec/tradcpp/main.c
756
bool setto;
libexec/tradcpp/main.c
849
bool
libexec/tradcpp/main.c
868
bool
libexec/tradcpp/main.c
888
bool
libexec/tradcpp/main.c
908
bool
libexec/tradcpp/main.c
929
bool
libexec/tradcpp/mode.h
33
bool werror;
libexec/tradcpp/mode.h
34
bool input_allow_dollars;
libexec/tradcpp/mode.h
36
bool do_stdinc;
libexec/tradcpp/mode.h
37
bool do_stddef;
libexec/tradcpp/mode.h
38
bool do_output;
libexec/tradcpp/mode.h
39
bool output_linenumbers;
libexec/tradcpp/mode.h
40
bool output_cheaplinenumbers;
libexec/tradcpp/mode.h
41
bool output_retain_comments;
libexec/tradcpp/mode.h
43
bool do_depend;
libexec/tradcpp/mode.h
44
bool depend_report_system;
libexec/tradcpp/mode.h
45
bool depend_assume_generated;
libexec/tradcpp/mode.h
46
bool depend_issue_fakerules;
libexec/tradcpp/mode.h
47
bool depend_quote_target;
libexec/tradcpp/mode.h
50
bool do_macrolist;
libexec/tradcpp/mode.h
51
bool macrolist_include_stddef;
libexec/tradcpp/mode.h
52
bool macrolist_include_expansions;
libexec/tradcpp/mode.h
53
bool do_trace;
libexec/tradcpp/mode.h
54
bool trace_namesonly;
libexec/tradcpp/mode.h
55
bool trace_indented;
libexec/tradcpp/mode.h
59
bool endiflabels;
libexec/tradcpp/mode.h
60
bool nestcomment;
libexec/tradcpp/mode.h
61
bool undef;
libexec/tradcpp/mode.h
62
bool unused;
libexec/tradcpp/output.c
106
bool inesc = false;
libexec/tradcpp/output.c
107
bool inquote = false;
libexec/tradcpp/output.c
42
static bool incomment = false;
libexec/tradcpp/place.c
144
place_addfile(const struct place *place, const char *file, bool issystem)
libexec/tradcpp/place.c
237
bool
libexec/tradcpp/place.c
249
bool
libexec/tradcpp/place.c
311
bool
libexec/tradcpp/place.c
46
bool fromsystemdir;
libexec/tradcpp/place.c
52
static bool overall_failure;
libexec/tradcpp/place.c
64
bool fromsystemdir)
libexec/tradcpp/place.h
61
bool place_eq(const struct place *, const struct place *);
libexec/tradcpp/place.h
62
bool place_samefile(const struct place *, const struct place *);
libexec/tradcpp/place.h
67
const char *name, bool fromsystemdir);
libexec/tradcpp/utils.c
231
bool
libexec/tradcpp/utils.h
62
bool is_identifier(const char *str);
libexec/tradcpp/utils.h
68
bool complain_failed(void);
regress/lib/libc/qsort/qsort_test.c
57
static bool dump_table, timing, verbose;
regress/lib/libc/sys/t_dup.c
51
static void check_mode(bool, bool, bool);
regress/lib/libc/sys/t_dup.c
54
check_mode(bool _dup, bool _dup2, bool _dup3)
regress/lib/libc/sys/t_getitimer.c
44
static bool fail;
regress/lib/libc/sys/t_msgget.c
203
bool fail = false;
regress/lib/libc/sys/t_sigaction.c
44
static bool handler_called = false;
regress/lib/libc/sys/t_sigaltstack.c
39
static bool handler_called;
regress/lib/libc/sys/t_sigaltstack.c
40
static bool handler_use_altstack;
regress/lib/libc/sys/t_write.c
48
static bool fail = false;
regress/lib/libm/msun/test-utils.h
109
fpequal_cs(long double x, long double y, bool checksign)
regress/lib/libm/msun/test-utils.h
162
bool eq = fpequal_tol(_x, _y, tol, flags); \
regress/lib/libm/msun/test-utils.h
191
bool equal_cs = \
regress/lib/libm/msun/test-utils.h
201
bool equal_tol = (fpequal_tol(creal(_x), creal(_y), tol, flags) && \
sys/arch/amd64/amd64/ghcb.c
283
_ghcb_mem_rw(vaddr_t addr, int valsz, void *val, bool read)
sys/arch/amd64/amd64/ghcb.c
373
_ghcb_io_rw(uint16_t port, int valsz, uint32_t *val, bool read)
sys/arch/amd64/include/ghcb.h
138
void _ghcb_mem_rw(vaddr_t, int, void *, bool);
sys/arch/amd64/include/ghcb.h
139
void _ghcb_io_rw(uint16_t, int, uint32_t *, bool);
sys/arch/arm64/arm64/disasm.c
622
static bool
sys/arch/arm64/arm64/disasm.c
663
static bool
sys/arch/arm64/arm64/disasm.c
702
static bool
sys/arch/armv7/omap/if_cpsw.c
1149
bool handled = false;
sys/arch/armv7/omap/if_cpsw.c
156
volatile bool sc_txrun;
sys/arch/armv7/omap/if_cpsw.c
157
volatile bool sc_rxrun;
sys/arch/armv7/omap/if_cpsw.c
158
volatile bool sc_txeoq;
sys/arch/armv7/omap/if_cpsw.c
159
volatile bool sc_rxeoq;
sys/arch/armv7/omap/if_cpsw.c
514
bool pad;
sys/arch/luna88k/dev/siotty.c
88
bool sc_rx_ready;
sys/arch/luna88k/dev/siotty.c
89
bool sc_tx_busy;
sys/arch/luna88k/dev/siotty.c
90
bool sc_tx_done;
sys/arch/luna88k/dev/xp.c
57
bool sc_isopen;
sys/arch/luna88k/dev/xp.c
81
static bool xp_matched;
sys/ddb/db_dwarf.c
103
static bool
sys/ddb/db_dwarf.c
104
read_leb128(struct dwbuf *d, uint64_t *v, bool signextend)
sys/ddb/db_dwarf.c
122
static bool
sys/ddb/db_dwarf.c
128
static bool
sys/ddb/db_dwarf.c
135
static bool
sys/ddb/db_dwarf.c
148
static bool
sys/ddb/db_dwarf.c
160
static bool
sys/ddb/db_dwarf.c
170
static bool
sys/ddb/db_dwarf.c
218
bool
sys/ddb/db_dwarf.c
264
bool basic_block = false, end_sequence = false;
sys/ddb/db_dwarf.c
265
bool prologue_end = false, epilogue_begin = false;
sys/ddb/db_dwarf.c
268
bool have_last = false;
sys/ddb/db_dwarf.c
274
bool emit = false, reset_basic_block = false;
sys/ddb/db_dwarf.c
431
bool showdir = true;
sys/ddb/db_dwarf.c
61
static inline bool
sys/ddb/db_dwarf.c
72
static bool
sys/ddb/db_dwarf.c
78
static bool
sys/ddb/db_dwarf.c
84
static bool
sys/ddb/db_dwarf.c
90
static bool
sys/ddb/db_dwarf.c
96
static bool
sys/ddb/db_sym.h
92
bool db_dwarf_line_at_pc(const char *, size_t, uintptr_t,
sys/dev/acpi/acpidmar.h
262
static inline bool
sys/dev/acpi/acpidmar.h
380
static inline bool
sys/dev/fdt/rkvop.c
165
bool rkvop_mode_fixup(struct drm_crtc *, const struct drm_display_mode *,
sys/dev/fdt/rkvop.c
378
bool
sys/dev/fdt/rkvop.c
390
bool enabled = state->plane_mask & drm_plane_mask(crtc->primary);
sys/dev/i2c/ietp.c
103
int32_t ietp_res2dpmm(uint8_t, bool);
sys/dev/i2c/ietp.c
107
int ietp_iic_set_absolute_mode(struct ietp_softc *, bool);
sys/dev/i2c/ietp.c
139
ietp_res2dpmm(uint8_t res, bool hi_precision)
sys/dev/i2c/ietp.c
341
ietp_iic_set_absolute_mode(struct ietp_softc *sc, bool enable)
sys/dev/i2c/ietp.c
352
bool require_wakeup;
sys/dev/i2c/ietp.h
58
bool hi_precision;
sys/dev/i2c/ietp.h
59
bool is_clickpad;
sys/dev/ic/anxdp.c
194
static inline const bool
sys/dev/ic/anxdp.c
201
anxdp_connector_detect(struct drm_connector *connector, bool force)
sys/dev/ic/anxdp.c
722
bool
sys/dev/ic/bcm2835_vcprop.h
406
static inline bool
sys/dev/ic/bcm2835_vcprop.h
412
static inline bool
sys/dev/ic/dwhdmi.c
558
dwhdmi_connector_detect(struct drm_connector *connector, bool force)
sys/dev/ic/qwx.c
12878
bool intersect = false;
sys/dev/ic/qwxreg.h
12970
bool is_valid_peer_id;
sys/dev/ic/qwxreg.h
2887
bool passive;
sys/dev/ic/qwxreg.h
2888
bool allow_ibss;
sys/dev/ic/qwxreg.h
2889
bool allow_ht;
sys/dev/ic/qwxreg.h
2890
bool allow_vht;
sys/dev/ic/qwxreg.h
2891
bool ht40plus;
sys/dev/ic/qwxreg.h
2892
bool chan_radar;
sys/dev/ic/qwxreg.h
2893
bool freq2_radar;
sys/dev/ic/qwxreg.h
2894
bool allow_he;
sys/dev/ic/qwxreg.h
2911
bool disable_hw_ack;
sys/dev/ic/qwxreg.h
2912
bool hidden_ssid;
sys/dev/ic/qwxreg.h
2913
bool pmf_enabled;
sys/dev/ic/qwxreg.h
3763
bool is_pmf_enabled;
sys/dev/ic/qwxreg.h
3764
bool is_wme_set;
sys/dev/ic/qwxreg.h
3765
bool qos_flag;
sys/dev/ic/qwxreg.h
3766
bool apsd_flag;
sys/dev/ic/qwxreg.h
3767
bool ht_flag;
sys/dev/ic/qwxreg.h
3768
bool bw_40;
sys/dev/ic/qwxreg.h
3769
bool bw_80;
sys/dev/ic/qwxreg.h
3770
bool bw_160;
sys/dev/ic/qwxreg.h
3771
bool stbc_flag;
sys/dev/ic/qwxreg.h
3772
bool ldpc_flag;
sys/dev/ic/qwxreg.h
3773
bool static_mimops_flag;
sys/dev/ic/qwxreg.h
3774
bool dynamic_mimops_flag;
sys/dev/ic/qwxreg.h
3775
bool spatial_mux_flag;
sys/dev/ic/qwxreg.h
3776
bool vht_flag;
sys/dev/ic/qwxreg.h
3777
bool vht_ng_flag;
sys/dev/ic/qwxreg.h
3778
bool need_ptk_4_way;
sys/dev/ic/qwxreg.h
3779
bool need_gtk_2_way;
sys/dev/ic/qwxreg.h
3780
bool auth_flag;
sys/dev/ic/qwxreg.h
3781
bool safe_mode_enabled;
sys/dev/ic/qwxreg.h
3782
bool amsdu_disable;
sys/dev/ic/qwxreg.h
3786
bool he_flag;
sys/dev/ic/qwxreg.h
3795
bool twt_responder;
sys/dev/ic/qwxreg.h
3796
bool twt_requester;
sys/dev/ic/qwxreg.h
3797
bool is_assoc;
sys/dev/ic/qwxreg.h
4460
bool psd_flag;
sys/dev/ic/qwxreg.h
4481
bool is_ext_reg_event;
sys/dev/ic/qwxreg.h
4483
bool rnr_tpe_usable;
sys/dev/ic/qwxreg.h
4484
bool unspecified_ap_usable;
sys/dev/ic/qwxreg.h
6159
bool do_passive_scan;
sys/dev/ic/qwxvar.h
1271
bool dma_ring_cap_done;
sys/dev/ic/qwxvar.h
1284
bool buf_entry_done;
sys/dev/ic/qwxvar.h
1285
bool meta_data_done;
sys/dev/ic/qwxvar.h
1293
bool chain_rssi_done;
sys/dev/ic/qwxvar.h
1299
bool frame_buf_done;
sys/dev/ic/qwxvar.h
1348
bool tx_credit_flow_enabled;
sys/dev/ic/qwxvar.h
135
bool enable_mesh;
sys/dev/ic/qwxvar.h
1606
bool hold_mon_dst_ring;
sys/dev/ic/qwxvar.h
1677
bool hidden_ssid;
sys/dev/ic/qwxvar.h
1684
bool is_started;
sys/dev/ic/qwxvar.h
1685
bool is_up;
sys/dev/ic/qwxvar.h
1686
bool ftm_responder;
sys/dev/ic/qwxvar.h
1687
bool spectral_enabled;
sys/dev/ic/qwxvar.h
1688
bool ps;
sys/dev/ic/qwxvar.h
1698
bool rsnie_present;
sys/dev/ic/qwxvar.h
1699
bool wpaie_present;
sys/dev/ic/qwxvar.h
1700
bool bcca_zero_sent;
sys/dev/ic/qwxvar.h
1701
bool do_not_send_tmpl;
sys/dev/ic/qwxvar.h
1732
bool napi_enabled;
sys/dev/ic/qwxvar.h
178
bool internal_sleep_clock;
sys/dev/ic/qwxvar.h
1810
bool is_authorized;
sys/dev/ic/qwxvar.h
1811
bool dp_setup_done;
sys/dev/ic/qwxvar.h
189
bool single_pdev_only;
sys/dev/ic/qwxvar.h
191
bool rxdma1_enable;
sys/dev/ic/qwxvar.h
193
bool rx_mac_buf_ring;
sys/dev/ic/qwxvar.h
194
bool vdev_start_delay;
sys/dev/ic/qwxvar.h
195
bool htt_peer_map_v2;
sys/dev/ic/qwxvar.h
203
bool fragment_160mhz;
sys/dev/ic/qwxvar.h
207
bool supports_monitor;
sys/dev/ic/qwxvar.h
208
bool full_monitor_mode;
sys/dev/ic/qwxvar.h
210
bool supports_shadow_regs;
sys/dev/ic/qwxvar.h
211
bool idle_ps;
sys/dev/ic/qwxvar.h
212
bool supports_sta_ps;
sys/dev/ic/qwxvar.h
213
bool cold_boot_calib;
sys/dev/ic/qwxvar.h
214
bool cbcal_restart_fw;
sys/dev/ic/qwxvar.h
218
bool supports_suspend;
sys/dev/ic/qwxvar.h
220
bool supports_regdb;
sys/dev/ic/qwxvar.h
221
bool fix_l1ss;
sys/dev/ic/qwxvar.h
222
bool credit_flow;
sys/dev/ic/qwxvar.h
226
bool supports_dynamic_smps_6ghz;
sys/dev/ic/qwxvar.h
227
bool alloc_cacheable_memory;
sys/dev/ic/qwxvar.h
228
bool supports_rssi_stats;
sys/dev/ic/qwxvar.h
230
bool fw_wmi_diag_event;
sys/dev/ic/qwxvar.h
231
bool current_cc_support;
sys/dev/ic/qwxvar.h
232
bool dbr_debug_support;
sys/dev/ic/qwxvar.h
233
bool global_reset;
sys/dev/ic/qwxvar.h
237
bool m3_fw_support;
sys/dev/ic/qwxvar.h
238
bool fixed_bdf_addr;
sys/dev/ic/qwxvar.h
239
bool fixed_mem_region;
sys/dev/ic/qwxvar.h
240
bool static_window_map;
sys/dev/ic/qwxvar.h
241
bool hybrid_bus_type;
sys/dev/ic/qwxvar.h
242
bool fixed_fw_mem;
sys/dev/ic/qwxvar.h
244
bool support_off_channel_tx;
sys/dev/ic/qwxvar.h
245
bool supports_multi_bssid;
sys/dev/ic/qwxvar.h
252
bool tcl_ring_retry;
sys/dev/ic/qwxvar.h
255
bool smp2p_wow_exit;
sys/dev/ic/qwxvar.h
270
bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
sys/dev/ic/qwxvar.h
279
bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);
sys/dev/ic/qwxvar.h
280
bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
sys/dev/ic/qwxvar.h
281
bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
sys/dev/ic/qwxvar.h
309
bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
sys/dev/ic/qwxvar.h
697
bool err_detected;
sys/dev/ic/qwxvar.h
707
bool err_detected;
sys/dev/ic/qwxvar.h
709
bool cache_controller_flush_status_hit;
sys/dev/ic/qwxvar.h
722
bool err_detected;
sys/dev/ic/qwxvar.h
727
bool err_detected;
sys/dev/ic/qwxvar.h
728
bool list_empty;
sys/dev/ic/qwz.c
10571
bool intersect = false;
sys/dev/ic/qwz.c
1286
static bool qwz_dp_srng_is_comp_ring_wcn7850(int ring_num)
sys/dev/ic/qwz.c
15187
bool
sys/dev/ic/qwzreg.h
13500
bool is_valid_peer_id;
sys/dev/ic/qwzreg.h
2427
bool is_reg_cc_ext_event_supported;
sys/dev/ic/qwzreg.h
2956
bool passive;
sys/dev/ic/qwzreg.h
2957
bool allow_ibss;
sys/dev/ic/qwzreg.h
2958
bool allow_ht;
sys/dev/ic/qwzreg.h
2959
bool allow_vht;
sys/dev/ic/qwzreg.h
2960
bool ht40plus;
sys/dev/ic/qwzreg.h
2961
bool chan_radar;
sys/dev/ic/qwzreg.h
2962
bool freq2_radar;
sys/dev/ic/qwzreg.h
2963
bool allow_he;
sys/dev/ic/qwzreg.h
2980
bool disable_hw_ack;
sys/dev/ic/qwzreg.h
2981
bool hidden_ssid;
sys/dev/ic/qwzreg.h
2982
bool pmf_enabled;
sys/dev/ic/qwzreg.h
3823
bool is_pmf_enabled;
sys/dev/ic/qwzreg.h
3824
bool is_wme_set;
sys/dev/ic/qwzreg.h
3825
bool qos_flag;
sys/dev/ic/qwzreg.h
3826
bool apsd_flag;
sys/dev/ic/qwzreg.h
3827
bool ht_flag;
sys/dev/ic/qwzreg.h
3828
bool bw_40;
sys/dev/ic/qwzreg.h
3829
bool bw_80;
sys/dev/ic/qwzreg.h
3830
bool bw_160;
sys/dev/ic/qwzreg.h
3831
bool stbc_flag;
sys/dev/ic/qwzreg.h
3832
bool ldpc_flag;
sys/dev/ic/qwzreg.h
3833
bool static_mimops_flag;
sys/dev/ic/qwzreg.h
3834
bool dynamic_mimops_flag;
sys/dev/ic/qwzreg.h
3835
bool spatial_mux_flag;
sys/dev/ic/qwzreg.h
3836
bool vht_flag;
sys/dev/ic/qwzreg.h
3837
bool vht_ng_flag;
sys/dev/ic/qwzreg.h
3838
bool need_ptk_4_way;
sys/dev/ic/qwzreg.h
3839
bool need_gtk_2_way;
sys/dev/ic/qwzreg.h
3840
bool auth_flag;
sys/dev/ic/qwzreg.h
3841
bool safe_mode_enabled;
sys/dev/ic/qwzreg.h
3842
bool amsdu_disable;
sys/dev/ic/qwzreg.h
3846
bool he_flag;
sys/dev/ic/qwzreg.h
3855
bool twt_responder;
sys/dev/ic/qwzreg.h
3856
bool twt_requester;
sys/dev/ic/qwzreg.h
3857
bool is_assoc;
sys/dev/ic/qwzreg.h
4515
bool psd_flag;
sys/dev/ic/qwzreg.h
4536
bool is_ext_reg_event;
sys/dev/ic/qwzreg.h
4538
bool rnr_tpe_usable;
sys/dev/ic/qwzreg.h
4539
bool unspecified_ap_usable;
sys/dev/ic/qwzreg.h
6213
bool do_passive_scan;
sys/dev/ic/qwzvar.h
142
bool enable_mesh;
sys/dev/ic/qwzvar.h
1430
bool dma_ring_cap_done;
sys/dev/ic/qwzvar.h
1443
bool buf_entry_done;
sys/dev/ic/qwzvar.h
1444
bool meta_data_done;
sys/dev/ic/qwzvar.h
1452
bool chain_rssi_done;
sys/dev/ic/qwzvar.h
1458
bool frame_buf_done;
sys/dev/ic/qwzvar.h
1507
bool tx_credit_flow_enabled;
sys/dev/ic/qwzvar.h
1752
bool hold_mon_dst_ring;
sys/dev/ic/qwzvar.h
1815
bool hidden_ssid;
sys/dev/ic/qwzvar.h
1822
bool is_started;
sys/dev/ic/qwzvar.h
1823
bool is_up;
sys/dev/ic/qwzvar.h
1824
bool ftm_responder;
sys/dev/ic/qwzvar.h
1825
bool spectral_enabled;
sys/dev/ic/qwzvar.h
1826
bool ps;
sys/dev/ic/qwzvar.h
1836
bool rsnie_present;
sys/dev/ic/qwzvar.h
1837
bool wpaie_present;
sys/dev/ic/qwzvar.h
1838
bool bcca_zero_sent;
sys/dev/ic/qwzvar.h
1839
bool do_not_send_tmpl;
sys/dev/ic/qwzvar.h
1870
bool napi_enabled;
sys/dev/ic/qwzvar.h
193
bool internal_sleep_clock;
sys/dev/ic/qwzvar.h
204
bool single_pdev_only;
sys/dev/ic/qwzvar.h
206
bool rxdma1_enable;
sys/dev/ic/qwzvar.h
209
bool rx_mac_buf_ring;
sys/dev/ic/qwzvar.h
210
bool vdev_start_delay;
sys/dev/ic/qwzvar.h
211
bool htt_peer_map_v2;
sys/dev/ic/qwzvar.h
2126
bool is_authorized;
sys/dev/ic/qwzvar.h
2127
bool dp_setup_done;
sys/dev/ic/qwzvar.h
219
bool fragment_160mhz;
sys/dev/ic/qwzvar.h
223
bool supports_monitor;
sys/dev/ic/qwzvar.h
224
bool full_monitor_mode;
sys/dev/ic/qwzvar.h
226
bool reoq_lut_support;
sys/dev/ic/qwzvar.h
227
bool supports_shadow_regs;
sys/dev/ic/qwzvar.h
228
bool idle_ps;
sys/dev/ic/qwzvar.h
229
bool supports_sta_ps;
sys/dev/ic/qwzvar.h
230
bool supports_suspend;
sys/dev/ic/qwzvar.h
232
bool fix_l1ss;
sys/dev/ic/qwzvar.h
241
bool supports_dynamic_smps_6ghz;
sys/dev/ic/qwzvar.h
242
bool alloc_cacheable_memory;
sys/dev/ic/qwzvar.h
243
bool supports_rssi_stats;
sys/dev/ic/qwzvar.h
245
bool current_cc_support;
sys/dev/ic/qwzvar.h
246
bool dbr_debug_support;
sys/dev/ic/qwzvar.h
249
bool support_off_channel_tx;
sys/dev/ic/qwzvar.h
250
bool supports_multi_bssid;
sys/dev/ic/qwzvar.h
257
bool tcl_ring_retry;
sys/dev/ic/qwzvar.h
260
bool smp2p_wow_exit;
sys/dev/ic/qwzvar.h
267
bool (*dp_srng_is_tx_comp_ring)(int ring_num);
sys/dev/ic/qwzvar.h
273
bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
282
bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
283
bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
306
bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
318
bool (*dp_rx_h_msdu_done)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
320
bool (*dp_rx_h_l4_cksum_fail)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
321
bool (*dp_rx_h_ip_cksum_fail)(struct hal_rx_desc *desc);
sys/dev/ic/qwzvar.h
708
bool err_detected;
sys/dev/ic/qwzvar.h
718
bool err_detected;
sys/dev/ic/qwzvar.h
720
bool cache_controller_flush_status_hit;
sys/dev/ic/qwzvar.h
733
bool err_detected;
sys/dev/ic/qwzvar.h
738
bool err_detected;
sys/dev/ic/qwzvar.h
739
bool list_empty;
sys/dev/pci/drm/amd/amdgpu/aldebaran.c
34
static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1000
bool shutdown;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1001
bool need_swiotlb;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1002
bool accel_working;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1014
bool have_disp_power_ref;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1015
bool have_atomics_support;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1018
bool is_atom_fw;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1102
bool enable_virtual_display;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1120
bool ib_pool_ready;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1174
bool enable_umsch_mm;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1200
bool enable_mes;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1201
bool enable_mes_kiq;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1202
bool enable_uni_mes;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1246
bool has_hw_reset;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1250
bool in_suspend;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1251
bool in_s3;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1252
bool in_s4;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1253
bool in_s0ix;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1275
bool in_runpm;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1276
bool has_pr3;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1278
bool ucode_sysfs_en;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1285
bool ras_default_ecc_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1287
bool no_hw_access;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1294
bool barrier_has_auto_waitcnt;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1299
bool ram_is_direct_mapped;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1309
bool scpm_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1314
bool dc_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1319
bool debug_vm;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1320
bool debug_largebar;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1321
bool debug_disable_soft_recovery;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1322
bool debug_use_vram_fw_buf;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1323
bool debug_enable_ras_aca;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1324
bool debug_exp_resets;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1325
bool debug_disable_gpu_ring_reset;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1326
bool debug_vm_userptr;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1327
bool debug_disable_ce_logs;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1328
bool debug_enable_ce_cs;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1345
bool apu_prefer_gtt;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1349
bool userq_halt_for_enforce_isolation;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1389
static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1402
void *buf, size_t size, bool write);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1404
void *buf, size_t size, bool write);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1407
void *buf, size_t size, bool write);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1445
bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1447
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1597
bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1598
bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
160
bool timeout_fatal_disable;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1604
bool amdgpu_device_need_post(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1605
bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1606
bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1617
bool amdgpu_device_supports_atpx(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1618
bool amdgpu_device_supports_px(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1619
bool amdgpu_device_supports_boco(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1620
bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1623
bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1644
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1652
bool amdgpu_has_atpx_dgpu_power_cntl(void);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1653
bool amdgpu_is_atpx_hybrid(void);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1654
bool amdgpu_has_atpx(void);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1658
static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1659
static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1660
static inline bool amdgpu_has_atpx(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1679
int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1680
int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1723
bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1724
bool amdgpu_acpi_is_power_shift_control_supported(void);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1726
u8 perf_req, bool advertise);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1728
u8 dev_state, bool drv_state);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1738
bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1755
static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1758
static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1760
u8 dev_state, bool drv_state) { return 0; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1770
bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1771
bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1773
static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1774
static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1790
bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1791
bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1793
bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1800
static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1811
static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
224
extern bool amdgpu_ignore_bad_page_threshold;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
241
extern bool debug_evictions;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
242
extern bool no_system_mem_limit;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
247
static const bool __maybe_unused debug_evictions; /* = false */
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
248
static const bool __maybe_unused no_system_mem_limit;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
252
extern bool pcie_p2p;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
381
bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
390
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
391
bool sw;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
392
bool hw;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
393
bool late_initialized;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
394
bool hang;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
425
bool amdgpu_get_bios(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
426
bool amdgpu_read_bios(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
427
bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
495
bool async;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
598
bool grbm_indexed;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
663
bool (*read_disabled_bios)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
664
bool (*read_bios_from_rom)(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
668
void (*set_vga_state)(struct amdgpu_device *adev, bool state);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
687
bool (*need_full_reset)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
694
bool (*need_reset_on_init)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
702
int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
704
int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
895
bool use_doorbell;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
900
bool allow_tunneling;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
901
bool hqd_active;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
906
bool tmz_queue;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
907
bool kernel_queue;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
917
bool in_link_reset;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
918
bool occurs_dpc;
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
919
bool audio_suspended;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
134
static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
212
static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
252
bool found = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
390
static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
393
bool ret = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
591
static bool aca_handle_is_valid(struct aca_handle *handle)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
773
bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c
873
int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en)
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h
187
bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type,
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h
194
int (*set_debug_mode)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h
204
bool is_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h
217
bool amdgpu_aca_is_enabled(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h
228
int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
582
static bool acp_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c
597
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
100
bool temperature_change;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
101
bool query_backlight_transfer_characteristics;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
102
bool ready_to_undock;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
103
bool external_gpu_information;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
117
bool get_ext_state;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
118
bool pcie_perf_req;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
119
bool pcie_dev_rdy;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
120
bool pcie_bus_width;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
121
bool power_shift_control;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1322
static bool amdgpu_atif_pci_probe_handle(struct pci_dev *pdev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1357
static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1394
bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1523
bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
1536
bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
648
bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
665
bool amdgpu_acpi_is_power_shift_control_supported(void)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
708
u8 perf_req, bool advertise)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
784
u8 dev_state, bool drv_state)
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
84
bool enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
89
bool thermal_state;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
90
bool forced_power_state;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
91
bool system_power_state;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
92
bool brightness_change;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
93
bool dgpu_display_event;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
94
bool gpu_package_power_limit;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
98
bool system_params;
sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c
99
bool sbios_requests;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
256
void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
266
int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
326
void **cpu_ptr, bool cp_mqd_gfx9)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
45
static bool kfd_initialized;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
590
int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
705
void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
727
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
735
bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
745
bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
77
bool vf = amdgpu_sriov_vf(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
896
bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c
906
bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
107
bool init_complete;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
153
bool block_mmu_notifications;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
159
void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
160
int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
174
void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
175
bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
177
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
198
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
208
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
241
void **cpu_ptr, bool mqd_gfx9);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
261
int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
269
bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
270
bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
281
bool valid = false; \
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
311
uint64_t *offset, uint32_t flags, bool criu_resume);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
321
struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
348
bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
349
bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
414
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
415
bool kgd2kfd_device_init(struct kfd_dev *kfd,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
418
void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
419
int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
434
bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
435
bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
436
bool retry_fault);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
449
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
455
bool kgd2kfd_device_init(struct kfd_dev *kfd,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
465
static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
469
static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
538
static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
543
static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
544
bool retry_fault)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
63
bool is_mapped;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
90
bool aql_queue;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
91
bool is_imported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
41
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
55
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h
23
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
223
bool kgd_arcturus_hqd_sdma_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
285
static int suspend_resume_compute_scheduler(struct amdgpu_device *adev, bool suspend)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
314
static void set_barrier_auto_waitcnt(struct amdgpu_device *adev, bool enable_waitcnt)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
349
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
374
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h
28
bool kgd_arcturus_hqd_sdma_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
119
static bool amdkfd_fence_enable_signaling(struct dma_fence *f)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
171
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
165
static bool kgd_gfx_v9_4_3_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
364
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
518
bool is_active = !!REG_GET_FIELD(status, SDMA_RLC0_CONTEXT_STATUS, SELECTED);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
473
static bool kgd_hqd_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
478
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
495
static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
665
static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
736
static void kgd_gfx_v10_set_wave_launch_stall(struct amdgpu_device *adev, uint32_t vmid, bool stall)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
754
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
791
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
864
bool is_mode_set = !!wave_launch_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
24
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
27
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
459
static bool hqd_is_occupied_v10_3(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
464
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
481
static bool hqd_sdma_is_occupied_v10_3(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
613
static bool get_atc_vmid_pasid_mapping_info_v10_3(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
449
static bool hqd_is_occupied_v11(struct amdgpu_device *adev, uint64_t queue_address,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
453
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
470
static bool hqd_sdma_is_occupied_v11(struct amdgpu_device *adev, void *mqd)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
621
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
635
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
189
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
203
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
303
bool is_stall_mode = wave_launch_mode == 4;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
167
bool valid_wptr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
320
static bool kgd_hqd_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
325
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
342
static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
520
static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
162
bool valid_wptr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
352
static bool kgd_hqd_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
357
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
374
static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
531
static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
484
bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
489
bool retval = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
506
static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
615
bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
673
bool stall)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
702
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
725
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
798
bool is_mode_set = !!wave_launch_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
41
bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
51
bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
68
bool stall);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
70
bool restore_dbg_registers,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
73
bool keep_trap_enabled,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
102
static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1023
bool userptr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1055
bool criu_resume)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1243
bool wait, bool intr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1306
bool no_update_pte)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1694
uint64_t *offset, uint32_t flags, bool criu_resume)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1889
bool use_release_notifier = (mem->bo->kfd_bo == mem);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1894
bool is_imported = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2009
bool is_invalid_userptr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2190
struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
2745
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
3217
bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
418
bool wait)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
656
bool mmio;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
77
static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
872
struct amdgpu_vm *vm, bool is_aql)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
880
bool same_hive = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1018
bool strobe_mode,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1116
bool strobe_mode,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1344
bool
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1545
bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1558
void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1598
bool hung)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1622
bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1641
void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
284
bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
311
bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
899
bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
141
bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
143
bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
151
bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
158
bool strobe_mode,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
164
bool strobe_mode,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
170
bool
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
193
bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
195
void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
197
bool hung);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
200
bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
202
void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
206
bool strobe_mode,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
44
bool enable_post_div;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h
45
bool enable_dithen;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
548
bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
555
bool mem_ecc_enabled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
621
bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
637
bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
656
bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
79
bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
897
bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c
953
int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
30
bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
37
bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
38
bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
39
bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t *i2c_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
40
bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
41
bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h
43
int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset);
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
108
static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
145
static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
186
bool amdgpu_read_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
214
bool amdgpu_read_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
253
static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
294
static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
328
static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
405
static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
413
bool found = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
476
static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
482
static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
489
static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
546
static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
552
static bool amdgpu_get_bios_apu(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
56
static bool check_atom_bios(struct amdgpu_device *adev, size_t size)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
581
static bool amdgpu_prefer_rom_resource(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
592
static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
650
bool amdgpu_get_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
652
bool found;
sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c
666
bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.h
42
bool user_invalidated;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1012
amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1020
bool dret = false, broken_edid = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1373
static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1377
bool found = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1388
bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1402
amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1617
bool shared_ddc = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1618
bool is_dp_bridge = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
1619
bool has_aux = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
221
bool connected;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
456
bool new_coherent_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
704
amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
853
amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
858
bool dret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c
945
static bool
sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.h
30
bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
120
bool bp_threshold,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
121
bool poison,
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
190
bool poison;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
446
static bool amdgpu_cper_is_hdr(struct amdgpu_ring *ring, u64 pos)
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h
54
bool enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c
891
bool userpage_invalidated = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c
48
bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c
639
bool set, u32 *stable_pstate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h
53
bool preamble_presented;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h
84
bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
1880
bool preempted = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
72
static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
78
bool pm_pg_lock, use_bank, use_ring;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c
31
void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c
32
bool vram_lost, struct amdgpu_job *job)
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c
329
void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c
330
bool vram_lost, struct amdgpu_job *job)
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.h
38
bool skip_vram_check;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.h
39
bool reset_vram_lost;
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.h
44
void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,
sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.h
45
bool vram_lost, struct amdgpu_job *job);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1446
bool optional;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1786
bool amdgpu_device_need_post(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
184
static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1850
bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1882
static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1901
static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1965
bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1996
bool state)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2061
bool is_os_64 = (sizeof(void *) == 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2290
static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2446
bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2806
bool total, skip_bios;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
2945
bool optional =
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3177
bool init_badpage;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
3383
static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4233
bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4292
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
433
bool amdgpu_device_supports_px(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4437
static bool amdgpu_device_check_iommu_remap(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
4479
bool px = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
448
bool amdgpu_device_supports_boco(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5157
bool px;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5362
int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5453
int amdgpu_device_resume(struct drm_device *dev, bool notify_clients)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5567
static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5570
bool asic_hang = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
558
bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5631
static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
578
void *buf, size_t size, bool write)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5811
bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5835
bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
5971
bool need_full_reset =
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6052
bool full_reset, vram_lost = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6192
bool need_full_reset, skip_hw_reset;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
622
void *buf, size_t size, bool write)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6449
bool need_emergency_restart)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6566
bool job_signaled)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6620
bool need_emergency_restart)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6663
bool job_signaled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
6666
bool need_emergency_restart = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
671
void *buf, size_t size, bool write)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
691
bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7069
bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7073
bool p2p_access =
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7080
bool is_large_bar = adev->gmc.visible_vram_size &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7082
bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7446
bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7478
bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7754
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
28
bool hash_64k;
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
29
bool hash_2m;
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
30
bool hash_1g;
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
38
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
42
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
46
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h
56
bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1069
bool reg_base_64)
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1843
int *range_cnt, bool refresh)
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
277
bool sz_valid = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
354
static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
360
static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.h
36
int *range_cnt, bool refresh);
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
101
static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1148
bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1164
uint64_t *tiling_flags, bool *tmz_surface,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1165
bool *gfx12_dcc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1427
static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1439
bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1558
bool in_vbl = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1673
bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1674
bool in_vblank_irq, int *vpos,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1685
static bool
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
317
bool active = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
488
bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
489
bool use_aux)
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
765
bool has_xor = swizzle >= 16;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
866
bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
867
bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
872
bool dcc_constant_encode =
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
978
static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
979
bool pipe_aligned)
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
286
bool reads = (direction == DMA_BIDIRECTIONAL ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.c
586
bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_dma_buf.h
32
bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
2338
bool supports_atomic = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
3270
bool amdgpu_msi_ok(struct amdgpu_device *);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
3368
bool supports_atomic = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
617
module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
827
bool hws_gws_support;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
828
module_param_unsafe(hws_gws_support, bool, 0444);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
843
bool debug_evictions;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
844
module_param(debug_evictions, bool, 0644);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
851
bool no_system_mem_limit;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
852
module_param(no_system_mem_limit, bool, 0644);
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
876
bool pcie_p2p = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
877
module_param(pcie_p2p, bool, 0444);
sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c
182
u8 *eeprom_buf, u32 buf_size, bool read)
sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c
93
u8 *eeprom_buf, u32 buf_size, bool read)
sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c
205
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
sys/dev/pci/drm/amd/amdgpu/amdgpu_eviction_fence.c
130
static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
234
bool amdgpu_fence_process(struct amdgpu_ring *ring)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
539
static bool amdgpu_fence_need_ring_interrupt_restore(struct amdgpu_ring *ring)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
542
bool is_gfx_power_domain = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
602
void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
888
static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
903
static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c
36
static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c
1328
bool tiled)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1351
bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
146
static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
151
static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
170
bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1793
bool xcp_switch_supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1820
bool xcp_switch_supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
192
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1986
bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
208
bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2094
bool wait = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2147
bool sched_work = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
2187
bool sched_work = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
244
bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
71
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
779
static void amdgpu_gfx_do_off_ctrl(struct amdgpu_device *adev, bool enable,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
780
bool no_delay)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
846
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
849
bool no_delay = adev->in_s0ix ? true : false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
866
void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
871
int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
92
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
144
bool all_hub);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
278
bool ta_cntl2_truncate_coord_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
349
void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
352
bool skip_check);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
417
bool rs64_enable; /* firmware format */
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
448
bool mec_fw_write_wait;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
449
bool me_fw_write_wait;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
450
bool cp_fw_write_wait;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
478
bool gfx_off_state; /* true: enabled, false: disabled */
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
493
bool is_poweron;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
498
bool cp_gfx_shadow; /* for gfx11 */
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
503
bool mcbp; /* mid command buffer preemption */
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
518
bool enable_cleaner_shader;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
523
bool userq_sch_inactive[MAX_XCP];
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
529
bool workload_profile_active;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
532
bool disable_kq;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
533
bool disable_uq;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
594
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
596
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
598
bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
600
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
602
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
603
void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
609
int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
625
bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfxhub.h
34
void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1296
bool nps_switch_support;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1334
bool refresh;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1424
static inline bool amdgpu_gmc_need_nps_switch_req(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1471
bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1522
static bool amdgpu_gmc_validate_partition_info(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1526
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1557
static bool amdgpu_gmc_is_node_present(int *node_ids, int num_ids, int nid)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
1682
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
417
bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
43
bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
723
uint32_t flush_type, bool all_hub,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
940
bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
956
bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
133
bool sdma_invalidation_workaround;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
147
uint32_t flush_type, bool all_hub,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
156
void (*set_prt)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
180
bool (*need_reset_on_init)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
277
bool prt_warning;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
286
bool translate_further;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
296
bool tmz_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
297
bool is_app_apu;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
352
bool flush_tlb_needs_extra_type_0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
353
bool flush_tlb_needs_extra_type_2;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
354
bool flush_pasid_uses_kiq;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
380
static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
400
bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
419
bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
431
uint32_t flush_type, bool all_hub,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
443
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h
461
bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c
215
static bool amdgpu_gtt_mgr_intersects(struct ttm_resource_manager *man,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c
233
static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man,
sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c
96
bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *res)
sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.h
35
void (*update_clock_gating)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
103
static bool amdgpu_hmm_invalidate_hsa(struct mmu_interval_notifier *mni,
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
169
uint64_t start, uint64_t npages, bool readonly,
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
238
bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range)
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
240
bool r;
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.c
66
static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni,
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.h
35
uint64_t start, uint64_t npages, bool readonly,
sys/dev/pci/drm/amd/amdgpu/amdgpu_hmm.h
38
bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
132
bool need_ctx_switch;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
137
bool secure, init_shadow;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c
140
bool need_pipe_sync = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
170
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
178
static bool amdgpu_vmid_gds_switch_needed(struct amdgpu_vmid *id,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
190
static bool amdgpu_vmid_compatible(struct amdgpu_vmid *id,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
289
bool needs_flush = vm->use_cpu_for_update;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
361
bool needs_flush = vm->use_cpu_for_update;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c
481
bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h
70
bool reserved_vmid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h
79
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h
81
bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c
45
unsigned ring_size, bool use_bus_addr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h
106
unsigned ring_size, bool use_bus_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h
55
bool use_doorbell;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h
56
bool use_bus_addr;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h
69
bool enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h
76
bool overflow;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
239
bool amdgpu_msi_ok(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
452
bool handled = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
672
bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h
102
bool retry_cam_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h
142
bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h
82
bool installed;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h
89
bool msi_enabled; /* msi enabled */
sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c
129
static bool isp_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h
71
bool vm_needs_flush;
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h
72
bool gds_switch_needed;
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h
73
bool spm_update_needed;
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h
90
bool init_shadow;
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h
96
bool enforce_isolation;
sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h
97
bool run_cleaner_shader;
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
547
static inline bool amdgpu_jpeg_reg_valid(u32 reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
146
bool indirect_sram;
sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h
36
void (*update_memory_power_gating)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
267
int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
30
static bool amdgpu_mca_is_deferred_error(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
334
static bool amdgpu_mca_bank_should_update(struct amdgpu_device *adev, enum amdgpu_mca_error_type type)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
337
bool ret = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
354
static bool amdgpu_mca_bank_should_dump(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c
357
bool ret;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h
131
int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h
162
int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
358
bool use_mmio)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
394
bool detect_only,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
536
bool trap_en)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
613
bool need_retry = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
691
bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
703
uint32_t node_id, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
198
bool paging;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
266
bool suspend_all_gangs;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
273
bool resume_all_gangs;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
280
bool use_mmio;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
287
bool legacy_gfx;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
288
bool is_kq;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
293
bool detect_only;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
418
bool use_mmio);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
423
bool detect_only,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
438
bool trap_en);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
509
bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
81
bool enable_legacy_queue_map;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h
57
bool value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h
65
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
143
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
149
bool hw_capable;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
151
bool mm_i2c;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
230
bool has_aux;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
235
bool enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
237
bool last_buffer_filled_status;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
252
bool connected;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
257
bool enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
273
bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
279
int crtc_id, u64 crtc_base, bool async);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
303
bool tmz_surface;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
304
bool gfx12_dcc;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
313
bool mode_config_initialized;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
341
bool gpu_vm_support; /* supports display from GTT */
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
461
bool enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
462
bool can_tile;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
489
bool ss_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
512
bool wb_pending;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
513
bool wb_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
518
bool linkb;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
520
bool coherent_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
550
bool is_ext_encoder;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
561
bool edp_on;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
565
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
583
bool ddc_valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
588
bool cd_valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
614
bool oem;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
625
bool shared_ddc;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
626
bool use_digital;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
631
bool dac_load_detect;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
632
bool detected_by_load; /* if the connection status was determined by load */
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
633
bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
651
bool is_mst_connector;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
671
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
677
bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
678
bool use_aux);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
691
bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
698
bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
699
bool in_vblank_irq, int *vpos,
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c
57
bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
104
bool (*is_nps_switch_requested)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
122
bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
68
void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
71
bool use_doorbell, int doorbell_index, int doorbell_size);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
73
bool use_doorbell, int doorbell_index, int doorbell_size);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
74
void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
78
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
80
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
82
bool use_doorbell, int doorbell_index);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
84
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
86
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
88
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h
95
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1275
bool evict,
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1417
bool shared)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1449
bool intr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1471
int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
252
bool free = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
558
static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
588
bool amdgpu_bo_support_uswc(u64 bo_flags)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
867
bool is_iomem;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
93
bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
188
static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
236
static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
247
static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
252
bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
299
bool evict,
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
304
bool shared);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
307
bool intr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
308
int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
356
bool amdgpu_bo_support_uswc(u64 bo_flags);
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
56
bool no_wait_gpu;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
90
bool cleared;
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h
92
bool is_xgmi;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1435
int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1518
static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1581
bool get_extended_data)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1636
bool requires_reflection =
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1643
bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 :
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1855
union ta_ras_cmd_input *info, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2450
bool amdgpu_psp_get_ras_capability(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2460
bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3000
static bool fw_load_skip_check(struct psp_context *psp,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
365
static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
372
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3779
static bool is_ta_fw_applicable(struct psp_context *psp,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
4034
uint32_t xcp_id, bool core_override_enable,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
4035
bool reg_override_enable, bool perfmon_override_enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
581
bool check_changed = flags & PSP_WAITREG_CHANGED;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
582
bool verbose = !(flags & PSP_WAITREG_NOVERBOSE);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
678
static bool psp_err_warn(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
700
bool ras_intr = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
701
bool skip_unsupport = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
894
static bool psp_skip_tmr(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
159
bool (*smu_reload_quirk)(struct psp_context *psp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
170
bool (*get_ras_capability)(struct psp_context *psp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
171
bool (*is_aux_sos_load_required)(struct psp_context *psp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
172
bool (*is_reload_needed)(struct psp_context *psp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
213
bool initialized;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
230
bool supports_extended_data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
282
bool enable_mem_training;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
414
bool autoload_supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
416
bool boot_time_tmr;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
418
bool pmfw_centralized_cstate_management;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
441
bool sup_pd_fw_up;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
442
bool sup_ifwi_up;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
446
bool vbflash_done;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
453
bool (*check_fw_loading_status)(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
557
int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
565
bool get_extended_data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
572
union ta_ras_cmd_input *info, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
616
bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
619
bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
620
bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c
56
static bool is_ta_type_valid(enum ta_type_id ta_type)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1129
bool is_ue,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1130
bool is_de)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1211
static inline bool err_data_has_source_info(struct ras_err_data *data)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
159
void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
165
static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2107
static bool amdgpu_ras_aca_is_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2109
bool ret;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
222
bool hit = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2284
bool poison_stat = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2695
struct amdgpu_hive_info *hive, bool status)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
2707
bool amdgpu_ras_in_recovery(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3049
struct eeprom_table_record *bps, int pages, bool from_rom)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3393
static bool amdgpu_ras_schedule_retirement_dwork(struct amdgpu_ras *con,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3677
int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3769
bool ret;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3807
static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3913
bool df_poison, umc_poison;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4280
bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4561
bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4572
void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4606
bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4715
bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
48
static bool notifier_registered;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4924
int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4938
int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4955
bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
4971
bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5032
bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5056
bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5393
static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5461
bool amdgpu_ras_is_rma(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5529
bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
5533
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
869
struct ras_common_if *head, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
926
struct ras_common_if *head, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
977
bool bypass)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
999
bool bypass)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
1004
bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
1010
bool amdgpu_ras_in_recovery(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
1016
bool amdgpu_ras_is_rma(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
532
bool reboot;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
535
bool error_query_ready;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
541
bool disable_ras_err_cnt_harvest;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
544
bool poison_supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
555
bool update_channel_flag;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
557
bool is_aca_debug_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
558
bool is_rma;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
753
bool (*query_poison_status)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
754
bool (*handle_poison_consumption)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
772
int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
784
struct eeprom_table_record *bps, int pages, bool from_rom);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
870
struct ras_common_if *head, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
873
struct ras_common_if *head, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
908
static inline bool amdgpu_ras_intr_triggered(void)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
920
void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
922
bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
930
bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
940
int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
941
int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
942
bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
943
bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
950
bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
954
bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
990
void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
991
bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
995
bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
154
static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
172
static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c
555
bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h
118
bool is_eeprom_valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h
150
bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_res_cursor.h
176
static inline bool amdgpu_res_cleared(struct amdgpu_res_cursor *cur)
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.c
351
bool amdgpu_reset_in_recovery(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h
123
static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h
134
static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h
140
static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain)
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h
162
bool amdgpu_reset_in_recovery(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h
165
bool status)
sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h
171
static inline bool amdgpu_reset_in_dpc(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
456
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
461
bool ret;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
703
bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
705
bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
780
bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c
826
bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
122
bool initialized;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
173
bool amdgpu_fence_process(struct amdgpu_ring *ring);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
180
void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
211
bool support_64bit_ptrs;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
212
bool no_user_fence;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
213
bool secure_submission_supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
272
u64 gds_va, bool init_shadow, int vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
281
void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
282
bool secure);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
287
void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
381
bool use_doorbell;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
382
bool use_pollmem;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
411
bool has_compute_vm_bug;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
412
bool no_scheduler;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
413
bool no_user_submission;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
418
bool is_sw_ring;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
473
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
477
bool cond_exec)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
572
bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
579
bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c
566
bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h
115
bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h
76
bool s_resubmit;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h
81
bool pending_trailing_fence_signaled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h
235
bool (*is_rlc_enabled)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h
261
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h
294
bool in_safe_mode[AMDGPU_MAX_RLC_INSTANCES];
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h
336
bool is_rlc_v2_1;
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h
348
bool rlcg_reg_access_supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
189
bool duplicate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
204
u32 instance, bool duplicate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
522
bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_ring *ring)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c
557
bool caller_handles_kernel_queues)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
128
bool has_page_queue;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
134
bool no_user_submission;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
135
bool disable_uq;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
176
bool caller_handles_kernel_queues);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
194
bool duplicate);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
196
bool duplicate);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
201
bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_ring *ring);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
67
bool burst_nop;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
75
bool gfx_guilty;
sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h
76
bool page_guilty;
sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h
41
void (*update_rom_clock_gating)(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h
46
bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
133
static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
187
static bool amdgpu_sync_test_fence(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
471
int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c
65
static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.h
62
int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
367
uint32_t incr, uint64_t flags, bool immediate),
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
375
__field(bool, immediate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
392
TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool immediate),
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
398
__field(bool, immediate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1339
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1363
bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1376
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1450
static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1498
void *buf, size_t size, bool write)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
1797
bool mem_train_support = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
183
bool tmz, uint64_t *size, uint64_t *addr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2257
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2314
bool direct_submit,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2317
bool vm_needs_flush,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2319
bool delayed, u64 k_job_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2349
struct dma_fence **fence, bool direct_submit,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2350
bool vm_needs_flush, uint32_t copy_flags)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2405
bool vm_needs_flush, bool delayed,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2509
bool delayed,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
292
uint64_t size, bool tmz,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
381
bool evict,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
443
bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
474
static bool amdgpu_res_copyable(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
493
static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
697
bool bound;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
719
bool readonly;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
776
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
140
bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
162
bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
168
bool enable);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
172
struct dma_fence **fence, bool direct_submit,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
173
bool vm_needs_flush, uint32_t copy_flags);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
177
uint64_t size, bool tmz,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
187
bool delayed,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
199
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
211
static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
223
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
225
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
227
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
229
bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
230
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
57
bool initialized;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
64
bool buffer_funcs_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h
80
bool keep_stolen_vga_memory;
sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c
1402
bool amdgpu_is_kicker_fw(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c
524
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h
625
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h
640
bool amdgpu_is_kicker_fw(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c
548
struct ta_ras_query_address_output *addr_out, bool dump_addr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h
104
bool (*check_ecc_err_status)(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h
112
bool dump_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h
191
struct ta_ras_query_address_output *addr_out, bool dump_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h
99
bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
486
bool skip_map_queue;
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c
695
bool amdgpu_userq_enabled(struct drm_device *dev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h
138
bool amdgpu_userq_enabled(struct drm_device *dev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c
334
static bool amdgpu_userq_fence_signaled(struct dma_fence *f)
sys/dev/pci/drm/amd/amdgpu/amdgpu_utils.h
76
static inline bool NAME##_cap_is_ro(const struct NAME##_caps *c, enum NAME##_cap_id id) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_utils.h
78
static inline bool NAME##_cap_is_wo(const struct NAME##_caps *c, enum NAME##_cap_id id) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_utils.h
80
static inline bool NAME##_cap_is_rw(const struct NAME##_caps *c, enum NAME##_cap_id id) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
105
bool has_msg_cmd;
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1126
bool direct, struct dma_fence **fence)
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1230
bool direct, struct dma_fence **fence)
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1295
bool set_clocks;
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h
60
bool address_64_bit;
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h
61
bool use_ctx_buf;
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h
83
bool direct, struct dma_fence **fence);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
366
bool set_clocks;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
531
bool direct, struct dma_fence **fence)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
88
bool direct, struct dma_fence **fence);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1584
bool is_powered;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1613
bool is_powered;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
297
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
299
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
353
bool in_ras_intr = amdgpu_ras_intr_triggered();
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
431
bool pg = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
760
uint32_t ib_pack_in_dw, bool enc)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
104
bool video_range, video1_range, aon_range, aon1_range; \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
165
bool video_range, video1_range, aon_range, aon1_range; \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
328
bool indirect_sram;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
336
bool using_unified_queue;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
362
bool per_inst_fw;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
365
bool workload_profile_active;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
525
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1020
bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1022
bool write, u32 *rlcg_flag)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1024
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
108
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1189
bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1191
bool xnack_mode = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1200
bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1327
static int amdgpu_virt_req_ras_err_count_internal(struct amdgpu_device *adev, bool force_update)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1452
int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1483
bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1512
bool *hit)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
1539
int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
241
bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
401
static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
47
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
783
static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
785
bool is_sriov = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
83
int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
848
bool is_sriov = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
857
static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
862
static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
922
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
284
bool chained_ib_support;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
301
bool tdr_debug;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
303
bool ras_init_done;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
312
bool is_mm_bw_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
330
bool is_xgmi_node_migrate_enabled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
395
static inline bool is_virtual_machine(void)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
424
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
426
int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
427
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
434
bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
441
bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
455
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
459
bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
460
bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
462
bool write, u32 *rlcg_flag);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
464
bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
467
int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
469
bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
472
int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
87
int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
88
int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h
97
bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1024
struct amdgpu_vm *vm, bool immediate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1028
bool flush_tlb_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1165
bool immediate, bool unlocked, bool flush_tlb,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1166
bool allow_override, struct amdgpu_sync *sync,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1233
bool contiguous = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1319
bool clear)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1328
bool flush_tlb = clear;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1331
bool uncached;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1474
bool enable;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1674
bool clear, unlock;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
1752
bool all_hub = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2018
bool valid = true;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2290
bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2325
void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2360
bool evicted)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
2842
bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3027
bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3029
bool write_fault)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3031
bool is_compute_context = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
3280
bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
367
bool shared;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
724
bool amdgpu_vm_ready(struct amdgpu_vm *vm)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
726
bool ret;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
757
bool has_compute_vm_bug;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
793
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
828
bool need_pipe_sync)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
835
bool spm_update_needed = job->spm_update_needed;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
836
bool gds_switch_needed = ring->funcs->emit_gds_switch &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
838
bool vm_flush_needed = job->vm_needs_flush;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
839
bool cleaner_shader_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
840
bool pasid_mapping_needed = false;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
211
bool shared;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
214
bool moved;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
267
bool immediate;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
272
bool unlocked;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
294
bool needs_flush;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
300
bool allow_override;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
349
bool evicting;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
424
bool use_cpu_for_update;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
451
bool is_compute_context;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
464
bool concurrent_flush;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
521
bool amdgpu_vm_ready(struct amdgpu_vm *vm);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
527
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
529
struct amdgpu_vm *vm, bool immediate);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
543
bool immediate, bool unlocked, bool flush_tlb,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
544
bool allow_override, struct amdgpu_sync *sync,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
551
bool clear);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
552
bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
553
void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
558
bool evicted);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
588
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
600
bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
602
bool write_fault);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
612
struct amdgpu_bo_vm *vmbo, bool immediate);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
614
int level, bool immediate, struct amdgpu_bo_vm **vmbo,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
633
bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h
675
static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
177
static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
206
static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
240
static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
309
static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
361
struct amdgpu_bo_vm *vmbo, bool immediate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
441
int level, bool immediate, struct amdgpu_bo_vm **vmbo,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
498
bool immediate)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c
564
bool unlocked = params->unlocked;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
325
static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h
78
bool context_started;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h
81
bool collaborate_mode;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
61
static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
829
static bool amdgpu_vram_mgr_intersects(struct ttm_resource_manager *man,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c
862
static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h
70
static inline bool amdgpu_vram_mgr_is_cleared(struct drm_buddy_block *block)
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c
241
static bool __amdgpu_xcp_is_cached_mode_valid(struct amdgpu_xcp_mgr *xcp_mgr)
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h
105
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h
97
bool valid;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1373
bool is_xgmi_pcs,
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1374
bool check_mask)
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1716
bool reset_scheduled;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
1782
bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
792
bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
793
bool init_low;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
898
bool peer_mode = bw_mode == AMDGPU_XGMI_BW_MODE_PER_PEER;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
942
bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c
966
bool set_extended_data)
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h
108
bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h
112
bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h
90
bool supported;
sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h
92
bool connected_to_cpu;
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
277
bool res_lt_xcp;
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
337
static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr,
sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c
344
bool comp_mode;
sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c
33
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c
49
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c
35
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c
55
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c
34
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c
51
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c
72
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c
89
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c
58
bool enable)
sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c
75
bool enable)
sys/dev/pci/drm/amd/amdgpu/atom.c
1618
bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
sys/dev/pci/drm/amd/amdgpu/atom.c
1639
bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
sys/dev/pci/drm/amd/amdgpu/atom.c
70
bool abort;
sys/dev/pci/drm/amd/amdgpu/atom.h
164
bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
sys/dev/pci/drm/amd/amdgpu/atom.h
166
bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index,
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
318
bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
563
static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c
586
bool ss_enabled,
sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h
53
bool ss_enabled,
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
456
bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
494
bool tp3_supported;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
601
bool clock_recovery;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.c
670
bool channel_eq;
sys/dev/pci/drm/amd/amdgpu/atombios_dp.h
36
bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1142
bool
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1666
static bool
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
1815
bool connected)
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
2041
bool bad_record = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
263
bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder)
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
278
bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder,
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c
760
bool is_dp = false;
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h
41
bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder);
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h
42
bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder,
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h
52
bool
sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h
72
bool connected);
sys/dev/pci/drm/amd/amdgpu/cik.c
1012
static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/cik.c
1123
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/cik.c
1225
bool indexed = cik_allowed_read_registers[i].grbm_indexed;
sys/dev/pci/drm/amd/amdgpu/cik.c
130
static int cik_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/cik.c
1392
bool baco_reset;
sys/dev/pci/drm/amd/amdgpu/cik.c
1692
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1693
bool disable_clkreq = false;
sys/dev/pci/drm/amd/amdgpu/cik.c
1732
bool clk_req_support;
sys/dev/pci/drm/amd/amdgpu/cik.c
1879
static bool cik_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/cik.c
1931
static bool cik_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/cik.c
2151
static bool cik_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/cik.c
955
static void cik_vga_set_state(struct amdgpu_device *adev, bool state)
sys/dev/pci/drm/amd/amdgpu/cik.c
967
static bool cik_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/cik.c
974
bool r;
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
348
static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1022
static bool cik_sdma_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1187
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
281
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
341
static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
398
static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
874
bool enable)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
895
bool enable)
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
344
static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1415
bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1742
static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1813
static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1827
static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1855
bool bypass_lut = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2274
static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
235
int crtc_id, u64 crtc_base, bool async)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2624
static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
280
static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
283
bool connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2967
static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2972
static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
307
bool connected = dce_v10_0_hpd_sense(adev, hpd);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
413
static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
444
bool render)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
703
bool interlaced; /* mode is interlaced */
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
951
static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
971
static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
989
static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1393
bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1636
static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1649
static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1686
static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1784
static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1857
static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1868
static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1892
bool bypass_lut = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
202
int crtc_id, u64 crtc_base, bool async)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2247
static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
244
static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
247
bool connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2591
static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
271
bool connected = dce_v6_0_hpd_sense(adev, hpd);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2912
static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3360
static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
381
static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
411
bool render)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
556
bool interlaced; /* mode is interlaced */
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
804
static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
824
static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
842
static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1387
bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1689
static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1760
static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1774
static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
1802
bool bypass_lut = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
186
int crtc_id, u64 crtc_base, bool async)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2195
static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
228
static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
231
bool connected = false;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
255
bool connected = dce_v8_0_hpd_sense(adev, hpd);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2550
static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2884
static bool dce_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
365
static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
395
bool render)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
656
bool interlaced; /* mode is interlaced */
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
904
static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
924
static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
942
static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
115
bool enable)
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
44
bool enable)
sys/dev/pci/drm/amd/amdgpu/df_v1_7.c
80
bool enable)
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
265
bool enable)
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
307
bool enable)
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
348
static bool df_v3_6_pmc_has_counter(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
411
bool is_enable)
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
464
bool is_deferred)
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
480
static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/df_v3_6.c
642
static bool df_v3_6_query_ras_poison_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/df_v4_3.c
29
static bool df_v4_3_query_ras_poison_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/df_v4_6_2.c
26
static bool df_v4_6_2_query_ras_poison_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3693
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3694
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3695
static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3701
bool all_hub, uint8_t dst_sel);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3816
bool all_hub)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4001
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4176
static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4178
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4554
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5419
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5485
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6072
static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6602
static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6748
bool priority = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6845
static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7170
static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7275
static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7281
static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7580
static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7854
static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7927
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8001
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8060
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8119
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8249
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8330
static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8352
static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8357
static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8393
static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8435
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8716
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8717
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8758
bool all_hub, uint8_t dst_sel)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8912
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8942
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8978
static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8979
bool secure)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9039
bool fw_version_ok = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1063
bool skip_check)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2206
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2264
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3113
static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
334
static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
335
static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
341
bool all_hub, uint8_t dst_sel);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
345
bool enable);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3813
static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4072
bool priority = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4183
static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4515
static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4645
static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4654
bool value;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
466
bool all_hub)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4841
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4935
static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4965
bool req)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
511
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5127
static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5290
static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5324
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5343
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5362
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5381
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5416
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5544
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5616
static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5644
static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5657
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5931
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5932
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5973
bool all_hub, uint8_t dst_sel)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6068
u64 gds_va, bool init_shadow,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6207
static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6243
static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6244
bool secure)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6758
static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6826
bool use_mmio = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.h
30
bool req);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1871
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1929
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2326
static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2772
static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
286
bool all_hub, uint8_t dst_sel);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
290
bool enable);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3061
static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3393
static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3509
static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3518
bool value;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3698
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3793
static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3903
static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3939
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4001
static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4006
static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4016
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4034
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
405
bool all_hub)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4151
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4185
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4206
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4225
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4459
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4460
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4499
bool all_hub, uint8_t dst_sel)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5232
static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5300
bool use_mmio = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
919
bool skip_check)
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.h
30
bool req);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1828
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1829
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1936
static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2226
static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2237
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2410
static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2487
static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2547
static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2586
static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2658
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2663
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2667
static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2680
static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2752
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2777
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2791
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2819
static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3169
static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3382
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3404
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2124
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2125
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2126
bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2171
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2172
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2372
static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2638
static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3042
static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3063
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3253
static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3328
static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3490
static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3533
static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3619
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3634
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3648
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3661
static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3674
static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3696
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3767
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3781
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3846
static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4480
static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4820
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4843
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3844
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3879
bool new_entry = true;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4004
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4010
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4015
static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4084
static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4280
static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4738
static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4798
static bool gfx_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4809
static bool gfx_v8_0_rlc_is_idle(void *handle)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4890
static bool gfx_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5276
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5288
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5294
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5300
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5306
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5316
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5332
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5489
static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5582
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5682
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5770
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6112
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6113
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6114
bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6209
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6210
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6635
bool from_wq)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6767
uint32_t pipe, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6797
static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1033
bool all_hub)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1161
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1383
static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1400
static bool is_raven_kicker(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1408
static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1538
static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1807
static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2751
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2926
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2994
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3008
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3022
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3036
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3049
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3066
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3079
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3241
static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3457
static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3878
static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4011
static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4110
static bool gfx_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4883
static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4921
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4939
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4958
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5029
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5080
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5128
bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5183
static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5205
static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5232
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5546
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5547
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5548
bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5549
bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5671
static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5761
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5800
static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5801
bool secure)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5909
bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7103
uint32_t pipe, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7133
static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
915
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
454
uint32_t pattern, uint32_t num_wave, bool wait)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1397
static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1506
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1696
static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1723
static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1731
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2157
static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2402
static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2558
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2580
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2602
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2667
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2714
bool enable, int xcc_id)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
281
bool all_hub)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2887
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2888
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2889
bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3413
uint32_t pipe, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3443
static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3496
static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
376
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4910
bool is_symmetric_cus;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
890
static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
413
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
418
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
377
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
318
static inline bool
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
487
bool value,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
536
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
646
bool value;
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
393
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
418
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
410
bool value)
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
403
bool value)
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
106
bool retry_fault = !!(entry->src_data[1] & 0x80);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
107
bool write_fault = !!(entry->src_data[1] & 0x20);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
1070
static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
213
static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
220
static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
253
bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
349
bool all_hub, uint32_t inst)
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
355
bool valid;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
377
bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
942
bool value;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
1020
static bool gmc_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
106
bool retry_fault = !!(entry->src_data[1] & 0x80);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
107
bool write_fault = !!(entry->src_data[1] & 0x20);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
209
static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
216
static bool gmc_v11_0_get_vmid_pasid_mapping_info(
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
238
bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
341
bool all_hub, uint32_t inst)
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
347
bool valid;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
369
bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
919
bool value;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
1007
static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
202
static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
209
static bool gmc_v12_0_get_vmid_pasid_mapping_info(
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
228
bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
361
bool all_hub, uint32_t inst)
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
383
bool valid;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
405
bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
908
bool value;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
94
bool retry_fault = !!(entry->src_data[1] & 0x80);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
95
bool write_fault = !!(entry->src_data[1] & 0x20);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
1102
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
395
bool value)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
421
static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
669
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
686
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
703
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
726
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
742
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
960
static bool gmc_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1147
static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
1318
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
436
bool all_hub, uint32_t inst)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
523
bool value)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
549
static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
827
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
844
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
861
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
884
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
900
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1270
static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1304
static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1504
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
1584
bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
627
bool all_hub, uint32_t inst)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
738
bool value)
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
766
static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1116
bool is_vram = bo->tbo.resource &&
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1118
bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1120
bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1121
bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1124
bool snoop = false;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1125
bool is_local;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1385
static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
2187
bool value;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
2324
static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
547
bool retry_fault = !!(entry->src_data[1] & 0x80);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
548
bool write_fault = !!(entry->src_data[1] & 0x20);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
797
static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
811
static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
843
bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
958
bool all_hub, uint32_t inst)
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
964
bool valid;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
987
bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
84
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
137
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
168
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
43
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
140
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
196
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c
55
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c
34
bool enable)
sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c
31
bool enable)
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
338
static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
129
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
198
static int ih_v6_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
579
bool use_bus_addr;
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
658
static bool ih_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
677
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
710
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
766
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
94
u32 threshold, u32 timeout, bool enabled)
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
129
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
170
static int ih_v6_1_toggle_interrupts(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
554
bool use_bus_addr;
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
633
static bool ih_v6_1_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
652
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
687
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
743
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
94
u32 threshold, u32 timeout, bool enabled)
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
129
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
170
static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
544
bool use_bus_addr;
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
623
static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
642
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
677
bool enable)
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
733
bool enable = (state == AMD_PG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
94
u32 threshold, u32 timeout, bool enabled)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
286
u32 data, bool high)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
607
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
685
static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
709
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
521
static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
561
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
837
static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
476
static bool jpeg_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
501
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
636
static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
661
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
846
static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1009
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1364
static bool jpeg_v4_0_3_query_ras_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
1418
static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
970
static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
973
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
98
static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
421
static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
652
static bool jpeg_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
689
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
341
static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
562
static bool jpeg_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
587
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
1033
static bool jpeg_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
657
static bool jpeg_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
660
bool ret = false;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
700
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
980
static bool jpeg_v5_0_1_query_ras_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
105
bool enable)
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
105
bool enable)
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1008
enum amdgpu_mes_pipe pipe, bool prime_icache)
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
943
static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1083
static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1178
enum amdgpu_mes_pipe pipe, bool prime_icache)
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
381
bool req)
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
860
struct amdgpu_mes *mes, bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
351
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
425
static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
499
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
562
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
409
static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
482
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
536
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
536
static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
815
static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
476
static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
567
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
624
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
407
bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
494
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
528
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
430
static void mmhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
544
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
605
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
425
bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
526
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
542
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
422
static void mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
532
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
538
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
567
bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
674
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
690
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
424
mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
539
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
584
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
481
static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
591
bool enable)
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
648
bool enable)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
210
bool init)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
219
bool init)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
42
static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
464
static bool xgpu_ai_rcvd_ras_intr(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
266
bool init)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
275
bool init)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
41
static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
535
static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
343
static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
470
bool init)
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
479
bool init)
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
106
u32 threshold, u32 timeout, bool enabled)
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
154
bool enable)
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
196
static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
557
bool use_bus_addr;
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
628
static bool navi10_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
647
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
106
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
156
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
164
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
186
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
244
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
250
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
51
static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
67
int instance, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
109
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
134
static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
156
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
163
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
187
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
229
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
258
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
348
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
93
static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
102
static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
152
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
159
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
182
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
239
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
268
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
49
static void nbio_v4_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
515
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
520
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
525
static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
65
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
107
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
113
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
133
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
164
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
192
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
73
static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
89
bool use_doorbell, int doorbell_index, int doorbell_size)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
105
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
111
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
117
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
148
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
187
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
53
static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
68
bool use_doorbell, int doorbell_index, int doorbell_size)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
84
static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
113
bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
137
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
150
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
175
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
289
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
318
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
49
static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
65
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
88
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
108
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
130
static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
151
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
163
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
189
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
234
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
260
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
78
static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
124
static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
139
bool use_doorbell, int doorbell_index, int doorbell_size)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
179
static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
209
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
215
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
234
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
249
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
255
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
644
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
108
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
120
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
146
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
258
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
287
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
49
static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
65
bool use_doorbell, int doorbell_index,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
87
static void nbio_v7_7_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
172
static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
233
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
242
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
264
bool use_doorbell, int doorbell_index)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
308
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
313
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
387
bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
404
static bool nbio_v7_9_is_nps_switch_requested(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
59
static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
74
bool use_doorbell, int doorbell_index, int doorbell_size)
sys/dev/pci/drm/amd/amdgpu/nv.c
1038
static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/nv.c
210
static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/nv.c
329
static bool nv_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/nv.c
375
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/nv.c
537
static bool nv_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/nv.c
542
static bool nv_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/nv.c
601
bool enter)
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
190
static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
139
static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
860
static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
886
static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
900
static bool psp_v13_0_is_reload_needed(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
59
static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
94
static bool psp_v14_0_is_sos_alive(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
298
static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
310
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
373
static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
914
static bool sdma_v2_4_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1203
static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1232
static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1425
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1464
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
486
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
549
static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
610
static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1044
static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1252
sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1737
static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2018
static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2237
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2276
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
889
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
922
static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
981
static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1333
static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1609
static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1650
static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1942
struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1971
struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2561
static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
457
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
576
bool enable, uint32_t inst_mask)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
630
static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
686
static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
792
static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
967
uint32_t inst_mask, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1496
static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1762
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1799
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
526
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
598
static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
656
static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
688
static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1409
static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1699
static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1724
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1761
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
376
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
448
static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
505
static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
537
static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1431
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1489
static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
358
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
429
static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
452
static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
482
static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
671
bool use_broadcast;
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
795
static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1387
bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1445
static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
362
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
433
static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
445
static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
475
static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
788
static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/si.c
1003
static int si_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/si.c
1179
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/si.c
1260
bool indexed = si_allowed_read_registers[i].grbm_indexed;
sys/dev/pci/drm/amd/amdgpu/si.c
1272
static bool si_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/si.c
1279
bool r;
sys/dev/pci/drm/amd/amdgpu/si.c
1320
static bool si_read_bios_from_rom(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/si.c
1468
static void si_vga_set_state(struct amdgpu_device *adev, bool state)
sys/dev/pci/drm/amd/amdgpu/si.c
1519
static bool si_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/si.c
1525
static bool si_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/si.c
2430
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/amd/amdgpu/si.c
2431
bool disable_clkreq = false;
sys/dev/pci/drm/amd/amdgpu/si.c
2465
bool clk_req_support;
sys/dev/pci/drm/amd/amdgpu/si.c
2662
static bool si_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/si_dma.c
111
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
sys/dev/pci/drm/amd/amdgpu/si_dma.c
560
static bool si_dma_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/si_dma.c
653
bool enable;
sys/dev/pci/drm/amd/amdgpu/si_ih.c
214
static bool si_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/sienna_cichlid.c
34
static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
458
static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
47
static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
556
static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
568
static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
76
static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
767
bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
sys/dev/pci/drm/amd/amdgpu/smu_v13_0_10.c
32
static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c
38
static void smuio_v11_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c
38
static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
115
static bool smuio_v13_0_is_host_gpu_xgmi_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
40
static void smuio_v13_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c
38
static void smuio_v9_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/soc15.c
1368
static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/soc15.c
1373
static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/soc15.c
1402
static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/soc15.c
190
static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/soc15.c
375
static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc15.c
422
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/soc15.c
530
bool connected_to_cpu = false;
sys/dev/pci/drm/amd/amdgpu/soc15.c
605
static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc15.c
750
static bool soc15_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc15.c
852
static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc15.h
75
bool grbm_indexed;
sys/dev/pci/drm/amd/amdgpu/soc21.c
144
static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/soc21.c
250
static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc21.c
296
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/soc21.c
458
static bool soc21_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc21.c
469
static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc21.c
527
bool enter)
sys/dev/pci/drm/amd/amdgpu/soc21.c
922
static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc21.c
955
static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/soc24.c
155
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/soc24.c
260
static bool soc24_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc24.c
270
static bool soc24_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/soc24.c
335
bool enter)
sys/dev/pci/drm/amd/amdgpu/soc24.c
534
static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/soc24.c
73
static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
356
static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
383
static bool tonga_ih_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
103
bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
239
bool dump_addr)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
418
static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
443
static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
73
bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
92
bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
101
typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
97
bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
98
bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.h
99
bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
505
static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
326
static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
207
bool sw_mode)
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
596
bool enable)
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
782
static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
146
bool enable);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
50
bool sw_mode);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
610
bool enable)
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
636
bool sw_mode)
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
662
static bool uvd_v4_2_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
48
bool enable);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
583
static bool uvd_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
633
static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
768
bool enable)
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
797
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1148
static bool uvd_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1168
static bool uvd_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1255
bool int_handled = true;
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1283
static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1430
bool enable)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1459
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
54
bool enable);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
63
static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
642
bool enable)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
204
static bool vce_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
316
static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
351
static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
389
static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
390
bool sw_cg)
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
584
bool gate = false;
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
585
bool sw_cg = false;
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
163
static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
169
bool gated)
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
600
static bool vce_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
629
static bool vce_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
767
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1424
static bool vcn_v1_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1447
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1918
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1929
void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2010
bool is_powered;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
310
bool idle_work_unexecuted;
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.h
28
void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1379
static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1401
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
439
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
853
static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1005
static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1950
static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1986
bool enable = (state == AMD_CG_STATE_GATE);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
2183
static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
651
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
977
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1028
static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2194
static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2231
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
573
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
2039
static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
2091
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
2282
static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
510
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
965
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
996
static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
101
static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1685
static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1731
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1982
static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2036
static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2107
int inst_idx, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
529
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
844
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
99
int inst_idx, bool indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1542
static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1594
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
461
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
911
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1263
static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1315
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
425
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
695
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1386
static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1431
bool enable = state == AMD_CG_STATE_GATE;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1609
static bool vcn_v5_0_1_query_poison_status(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1661
static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
485
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
667
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
141
static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
558
static bool vega10_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
578
bool enable)
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
98
bool enable)
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
106
bool enable)
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
177
static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
572
bool use_bus_addr = true;
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
658
static bool vega20_ih_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
678
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
1123
bool bL1SS = false;
sys/dev/pci/drm/amd/amdgpu/vi.c
1124
bool bClkReqSupport = true;
sys/dev/pci/drm/amd/amdgpu/vi.c
1279
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
1331
static bool vi_need_full_reset(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vi.c
1410
static bool vi_need_reset_on_init(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vi.c
1738
static bool vi_common_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/amdgpu/vi.c
1744
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
1764
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
1780
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
1796
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
1813
bool enable)
sys/dev/pci/drm/amd/amdgpu/vi.c
256
static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode,
sys/dev/pci/drm/amd/amdgpu/vi.c
589
static bool vi_read_disabled_bios(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/amdgpu/vi.c
596
bool r;
sys/dev/pci/drm/amd/amdgpu/vi.c
634
static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/amdgpu/vi.c
745
bool indexed, u32 se_num,
sys/dev/pci/drm/amd/amdgpu/vi.c
847
bool indexed = vi_allowed_read_registers[i].grbm_indexed;
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
100
static void vpe_v6_1_set_collaborate_mode(struct amdgpu_vpe *vpe, bool enable)
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
73
static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)
sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c
29
static bool cik_event_interrupt_isr(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c
32
bool *patched_flag)
sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c
39
bool ret;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
1011
bool kfd_dev_is_large_bar(struct kfd_node *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
130
bool is_32bit_user_mode;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
1366
bool flush_tlb;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2301
const bool criu_resume = true;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2759
bool enable_ttmp_setup)
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2830
bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
2938
bool create_process;
sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
3252
bool ptrace_attached = false;
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
1426
bool cache_line_size_missing,
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
1582
bool cache_line_size_missing = false;
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2024
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2133
bool ext_cpu = KFD_GC_VERSION(kdev) != IP_VERSION(9, 4, 3);
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2187
bool use_ta_info = kdev->kfd->num_nodes == 1;
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2213
bool is_single_hop = kdev->kfd == peer_kdev->kfd;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
114
bool kfd_dbg_ev_raise(uint64_t event_mask,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
116
unsigned int source_id, bool use_worker,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
124
bool is_subscribed = true;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
199
bool kfd_set_dbg_ev_from_interrupt(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
208
bool signaled_to_debugger_or_runtime = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
299
static int kfd_dbg_set_queue_workaround(struct queue *q, bool enable)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
323
static int kfd_dbg_set_workaround(struct kfd_process *target, bool enable)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
349
int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
417
static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
419
bool owns_watch_id = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
589
void kfd_dbg_trap_deactivate(struct kfd_process *target, bool unwind, int unwind_count)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
931
bool clear_exception,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.c
935
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
100
static inline bool kfd_dbg_is_rlc_restore_supported(struct kfd_node *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
106
static inline bool kfd_dbg_has_cwsr_workaround(struct kfd_node *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
112
static inline bool kfd_dbg_has_gws_support(struct kfd_node *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
131
int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
133
static inline bool kfd_dbg_has_ttmps_always_setup(struct kfd_node *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
28
void kfd_dbg_trap_deactivate(struct kfd_process *target, bool unwind, int unwind_count);
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
35
bool kfd_set_dbg_ev_from_interrupt(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
41
bool kfd_dbg_ev_raise(uint64_t event_mask,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
43
unsigned int source_id, bool use_worker,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
69
bool clear_exception,
sys/dev/pci/drm/amd/amdkfd/kfd_debug.h
77
static inline bool kfd_dbg_is_per_vmid_supported(struct kfd_node *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1017
bool kfd_is_locked(struct kfd_dev *kfd)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1043
void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1060
int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1124
bool is_patched = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1450
static bool kfd_compute_active(struct kfd_node *node)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1624
bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1679
bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
1680
bool retry_fault)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
201
bool vf, uint32_t gfx_target_version)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
265
struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
sys/dev/pci/drm/amd/amdkfd/kfd_device.c
714
bool kgd2kfd_device_init(struct kfd_dev *kfd,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1064
bool is_new;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
1641
bool free_bit_found = false, is_xgmi = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2256
static bool sdma_has_hang(struct device_queue_manager *dqm)
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2275
static bool set_sdma_queue_as_reset(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2343
static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma)
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2375
bool reset)
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2603
static bool set_cache_memory_policy(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2611
bool retval = true;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2648
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
2781
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3443
bool is_mes = dqm->dev->kfd->shared_resources.enable_mes;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3613
bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
3618
bool r = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
60
bool reset);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
73
static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma);
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
743
bool set;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
83
static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c
950
bool prev_active = false;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
171
bool (*set_cache_memory_policy)(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
208
bool (*set_cache_memory_policy)(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
266
bool active_runlist;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
271
bool is_hws_hang;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
272
bool is_resetting;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
274
bool sched_running;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
275
bool sched_halt;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h
327
bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
38
static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
87
static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
98
bool retval = true;
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
34
static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
60
static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c
33
static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c
59
static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c
33
static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c
59
static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
33
static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
59
static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
38
static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
88
static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c
99
bool retval = true;
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
1126
bool send_signal = true;
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
315
static bool event_can_be_gpu_signaled(const struct kfd_event *ev)
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
321
static bool event_can_be_cpu_signaled(const struct kfd_event *ev)
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
403
uint32_t event_type, bool auto_reset, uint32_t node_id,
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
43
bool activated; /* Becomes true when event is signaled */
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
44
bool event_age_enabled; /* set to true when last_event_age is non-zero */
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
57
bool need_to_free_pages;
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
855
static uint32_t test_event_condition(bool all, uint32_t num_events,
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
938
bool undo_auto_reset)
sys/dev/pci/drm/amd/amdkfd/kfd_events.c
958
bool all, uint32_t *user_timeout_ms,
sys/dev/pci/drm/amd/amdkfd/kfd_events.h
58
bool signaled;
sys/dev/pci/drm/amd/amdkfd/kfd_events.h
59
bool auto_reset;
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
132
static bool event_interrupt_isr_v10(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c
135
bool *patched_flag)
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
258
static bool event_interrupt_isr_v11(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c
261
bool *patched_flag)
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
240
static bool context_id_expected(struct kfd_dev *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
259
static bool event_interrupt_isr_v9(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
262
bool *patched_flag)
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
573
static bool event_interrupt_isr_v9_4_3(struct kfd_node *node,
sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c
576
bool *patched_flag)
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
108
bool enqueue_ih_ring_entry(struct kfd_node *node, const void *ih_ring_entry)
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
123
static bool dequeue_ih_ring_entry(struct kfd_node *node, u32 **ih_ring_entry)
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
157
bool interrupt_is_wanted(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c
159
uint32_t *patched_ihre, bool *flag)
sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c
42
static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c
105
bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c
235
bool kfd_is_occupied_cp(struct mqd_manager *mm, void *mqd,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c
264
bool kfd_is_occupied_sdma(struct mqd_manager *mm, void *mqd,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c
296
bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h
122
bool (*check_preemption_failed)(struct mqd_manager *mm, void *mqd);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h
179
bool kfd_is_occupied_cp(struct mqd_manager *mm, void *mqd,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h
191
bool kfd_is_occupied_sdma(struct mqd_manager *mm, void *mqd,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h
201
bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h
95
bool (*is_occupied)(struct mqd_manager *mm, void *mqd,
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
209
static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
229
static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
282
static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
49
bool has_wa_flag = minfo && (minfo->update_flag & (UPDATE_FLAG_DBG_WA_ENABLE |
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
245
static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
326
static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
645
static bool check_preemption_failed_v9_4_3(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
651
bool ret = false;
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
240
static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c
152
bool xnack_conflict = 0;
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c
494
uint32_t filter_param, bool reset)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
149
uint64_t ib, size_t ib_size_in_dwords, bool chain)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
221
static inline bool pm_use_ext_eng(struct kfd_dev *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
228
struct queue *q, bool is_static)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
396
uint32_t filter_param, bool reset)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
144
struct queue *q, bool is_static)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
147
bool use_static = is_static;
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
203
uint32_t filter_param, bool reset)
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
77
uint64_t ib, size_t ib_size_in_dwords, bool chain)
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1002
bool xnack_enabled;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1012
bool queues_paused;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1016
bool is_runtime_retry;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1020
bool gpu_page_fault;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1046
bool kfd_dev_is_large_bar(struct kfd_node *dev);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1089
bool kfd_process_xnack_mode(struct kfd_process *p, bool supported);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1155
static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id,
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1188
bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1189
bool interrupt_is_wanted(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1191
uint32_t *patched_ihre, bool *flag);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1202
bool enabled);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1426
bool allocated;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1429
bool is_over_subscription;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1439
uint64_t ib, size_t ib_size_in_dwords, bool chain);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1443
struct queue *q, bool is_static);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1446
uint32_t filter_param, bool reset);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1478
uint32_t filter_param, bool reset);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1505
bool all, uint32_t *user_timeout_ms,
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1515
uint32_t event_type, bool auto_reset, uint32_t node_id,
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1541
static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1551
bool kfd_is_locked(struct kfd_dev *kfd);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
1577
static inline bool kfd_is_first_node(struct kfd_node *node)
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
192
extern bool hws_gws_support;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
203
extern bool debug_evictions;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
223
bool (*interrupt_isr)(struct kfd_node *dev,
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
225
bool *patched_flag);
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
239
bool supports_cwsr;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
240
bool needs_pci_atomics;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
291
bool interrupts_active;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
347
bool init_complete;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
355
bool cwsr_enabled;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
362
bool pci_atomic_requested;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
517
bool is_interop;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
518
bool is_evicted;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
519
bool is_suspended;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
520
bool is_being_destroyed;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
521
bool is_active;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
522
bool is_gws;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
524
bool is_dbg_wa;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
525
bool is_user_cu_masked;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
673
bool is_debug;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
679
bool reset_wavefronts;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
687
bool mapped_gws_queue;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
784
bool already_dequeued;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
785
bool runtime_inuse;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
864
bool has_reset_queue;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
936
bool is_32bit_user_mode;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
947
bool signal_event_limit_reached;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
968
bool debug_trap_enabled;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
989
bool has_cwsr;
sys/dev/pci/drm/amd/amdkfd/kfd_priv.h
997
bool irq_drain_is_open;
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1447
bool kfd_process_xnack_mode(struct kfd_process *p, bool supported)
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1502
bool enabled)
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
69
bool ref);
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
945
bool ref)
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
163
static bool kfd_smi_ev_enabled(pid_t pid, struct kfd_smi_client *client,
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
218
void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset,
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
264
unsigned long address, bool write_fault,
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
273
unsigned long address, bool migration)
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
347
void kfd_smi_event_process(struct kfd_process_device *pdd, bool start)
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c
44
bool suser;
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h
33
void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset,
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h
36
unsigned long address, bool write_fault,
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h
39
unsigned long address, bool migration);
sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h
56
void kfd_smi_event_process(struct kfd_process_device *pdd, bool start);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1150
bool huge_page_mapping = last_align_down > start_align;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1174
bool huge_page_mapping = last_align_down > start_align;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1203
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1219
bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1220
bool coherent = flags & (KFD_IOCTL_SVM_FLAG_COHERENT | KFD_IOCTL_SVM_FLAG_EXT_COHERENT);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1221
bool ext_coherent = flags & KFD_IOCTL_SVM_FLAG_EXT_COHERENT;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1402
unsigned long offset, unsigned long npages, bool readonly,
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1404
struct dma_fence **fence, bool flush_tlb)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1479
unsigned long npages, bool readonly,
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1480
unsigned long *bitmap, bool wait, bool flush_tlb)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
152
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1537
bool intr;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1542
static int svm_range_reserve_bos(struct svm_validate_context *ctx, bool intr)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1636
bool intr, bool wait, bool flush_tlb)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1727
bool readonly;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1975
bool mapped = prange->mapped_to_gpu;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2506
bool unmap_parent;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2607
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2763
bool *is_heap_stack)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
280
static void svm_range_free(struct svm_range *prange, bool do_unmap)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2874
bool is_heap_stack;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2928
static bool svm_range_skip_recover(struct svm_range *prange)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2981
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2982
svm_fault_allowed(struct vm_area_struct *vma, bool write_fault)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2997
uint64_t addr, uint64_t ts, bool write_fault)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3008
bool write_locked = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3010
bool migration = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3224
svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
326
uint64_t last, bool update_mem_usage)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3545
bool *migrated)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3670
bool update_mapping = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3671
bool flush_tlb;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
372
static bool svm_bo_ref_unless_zero(struct svm_range_bo *svm_bo)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3731
bool migrated;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3798
bool get_preferred_loc = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3799
bool get_prefetch_loc = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3800
bool get_granularity = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3801
bool get_accessible = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3802
bool get_flags = false;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
467
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
555
bool clear)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
73
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
766
bool *update_mapping)
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
815
static bool
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
139
bool mapped_to_gpu;
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
174
bool clear);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
178
bool write_fault);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
210
int svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled);
sys/dev/pci/drm/amd/amdkfd/kfd_svm.h
228
uint64_t addr, uint64_t ts, bool write_fault)
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1096
bool is_unique;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1289
bool support_rec_eng = !amdgpu_sriov_vf(adev) && to_dev->gpu &&
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1696
bool found = false;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1933
bool firmware_supported = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10199
bool mode_set_reset_required = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10202
bool set_backlight_level = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10575
bool enable_encryption = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10658
bool wait_for_vblank = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10686
bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11105
bool fs_vid_mode = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1114
int pipe, bool *enabled,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11150
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11200
bool enable,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11201
bool *lock_and_validation_needed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11470
static bool should_reset_plane(struct drm_atomic_state *state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11638
bool linear;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11701
bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11728
static bool dm_should_update_native_cursor(struct drm_atomic_state *state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11731
bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11762
bool enable,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11763
bool *lock_and_validation_needed,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11764
bool *is_top_most_overlay)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11772
bool needs_reset, update_native_cursor;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12090
bool consider_mode_change = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12091
bool entire_crtc_covered = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12092
bool cursor_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12208
static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12271
bool lock_and_validation_needed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12272
bool is_top_most_overlay = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12363
bool modified = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1264
bool has_hw_support;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12770
static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12777
bool res;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12828
static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12836
bool res;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12869
static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12885
static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12890
bool ret;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12985
bool valid_vsdb_found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13033
bool freesync_capable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13275
static bool execute_fused_io(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13290
const bool result = dm_execute_dmub_cmd_list(ctx, count, commands, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13316
bool amdgpu_dm_execute_fused_io(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13327
const bool result = execute_fused_io(dev, link->ctx, commands, count, timeout_us);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13340
bool is_cmd_complete;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13362
bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
13367
bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1445
bool init;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1706
static bool dm_should_disable_stutter(struct pci_dev *pdev)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
174
static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
177
create_i2c(struct ddc_service *ddc_service, bool oem);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
249
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2832
static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
2852
static void s3_handle_mst(struct drm_device *dev, bool suspend)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3031
struct dc_state *state, bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
320
static bool dm_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
332
static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3536
bool ret;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3584
bool init = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
364
static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3881
static bool are_sinks_equal(const struct dc_sink *sink1, const struct dc_sink *sink2)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3922
bool fake_reconnect = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3923
bool reallow_idle = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3924
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3980
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3981
bool debounce_required = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
408
static inline bool update_planes_and_stream_adapter(struct dc *dc,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4102
bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4103
bool result = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4107
bool link_loss = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4108
bool has_left_work = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4139
bool skip = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4160
bool skip = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
4198
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
446
bool vrr_active;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5080
bool rc, reallow_idle = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5370
bool psr_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5371
bool replay_feature_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5584
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5977
static bool modereset_required(struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5997
bool full_range;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6042
bool tmz_surface)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
616
bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
617
bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
618
bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6213
int *i, bool ffu)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6265
bool is_psr_su,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6266
bool *dirty_regions_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6272
bool bb_changed;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6273
bool fb_changed;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6428
bool is_y420, int requested_bpc)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6572
static bool adjust_colour_depth_from_display_info(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6796
bool scale_enabled)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6926
bool use_probed_modes)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6980
static bool is_freesync_video_mode(const struct drm_display_mode *mode,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7184
bool native_mode_found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7185
bool recalculate_timing = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7186
bool scale = dm_state->scaling != RMX_OFF;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
723
bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
724
bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
725
bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7354
amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7356
bool connected;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
7545
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8237
bool is_y420 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8501
bool mode_existed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8594
static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8919
create_i2c(struct ddc_service *ddc_service, bool oem)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9198
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9216
static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
927
static bool register_dmub_notify_callback(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
930
bool dmub_int_thread_offload)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9377
bool pack_sdp_v1_3 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9522
bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9523
bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9651
bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9699
bool wait_for_vblank)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9714
bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9715
bool cursor_update = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9716
bool pflip_present = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9717
bool dirty_rects_changed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9718
bool updated_planes_and_streams = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9764
bool plane_needs_flip;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1003
bool underscan_enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1004
bool freesync_capable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1005
bool update_hdcp;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1061
bool check_only);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1074
bool amdgpu_dm_execute_fused_io(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1109
bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
143
bool enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
156
bool enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
157
bool running;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
217
bool caps_valid;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
221
bool aux_support;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
276
bool is_handling_link_loss;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
281
bool is_handling_mst_msg_rdy_event;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
375
bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
468
bool audio_registered;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
612
bool force_timing_sync;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
613
bool disable_hpd_irq;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
614
bool dmcub_trace_event_en;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
643
bool aux_hpd_discon_quirk;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
650
bool edp0_on_dp1_quirk;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
696
bool dsc_force_disable_passthrough;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
724
bool freesync_supported;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
739
bool replay_mode;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
804
bool fake_enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
805
bool force_yuv420_output;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
806
bool force_yuv422_output;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
813
bool disallow_edp_enter_psr;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
819
bool timing_changed;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
823
bool pack_sdp_v1_3;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
834
uint8_t flags, bool set)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
956
bool cm_has_degamma;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
957
bool cm_is_degamma_srgb;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
959
bool mpo_requested;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
966
bool freesync_vrr_info_changed;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
968
bool mode_changed_independent_from_dsc;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
969
bool dsc_force_changed;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
970
bool vrr_supported;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1140
bool has_degamma_lut;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
1251
bool has_crtc_cm_degamma;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
357
static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
387
struct dc_gamma *gamma, bool is_legacy)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
485
bool has_rom)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
489
bool res;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
523
bool has_rom)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
527
bool res;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
571
uint32_t regamma_size, bool has_rom,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
620
bool res;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
682
bool use_tetrahedral_9,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
751
bool has_rom,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
777
bool has_rom,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
823
bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
908
bool check_only)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
912
bool has_rom = adev->asic_type <= CHIP_RAVEN;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
916
bool has_regamma, has_degamma;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
918
bool is_legacy;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
152
bool swap = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
216
static bool get_phy_id(struct amdgpu_display_manager *dm,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
220
bool found = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
301
bool was_activated;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
467
bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
471
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
503
bool enable = amdgpu_dm_is_valid_crc_source(source);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
556
bool enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
557
bool enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
61
static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
67
static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
73
static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
778
bool reset_crc_frame_count[MAX_CRC_WINDOW_NUM] = {false};
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
783
bool forward_roi_change = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
784
bool notify_ta = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
785
bool all_crc_ready = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
109
bool support_mul_roi;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
111
bool phy_mapping_updated;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
117
static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
143
bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
55
bool assigned;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
56
bool is_mst;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
68
bool crc_ready;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
83
bool enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
85
bool update_win;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
129
bool vblank_enabled, bool allow_sr_entry)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
132
bool is_sr_active = (link->replay_settings.replay_allow_active ||
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
134
bool is_crc_window_active = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
135
bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
168
bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
173
bool is_headless = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
290
static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
314
bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
61
bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
645
static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
68
bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
728
bool is_dcn;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
77
int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
96
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
32
bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
36
int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
38
bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
40
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1007
bool sink_support_replay = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1008
bool driver_support_replay = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1031
(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1244
bool hdcp_cap, hdcp2_cap;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1369
bool try_again = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1370
bool is_fec_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1371
bool is_dsc_supported = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1447
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
270
bool valid_input = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2885
bool enable;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3074
connector->force_yuv420_output = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3117
bool is_start = (val != 0);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3334
adev->dm.dmcub_trace_event_en = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
343
static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3443
bool valid_input = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
345
bool is_end_device = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3957
adev->dm.force_timing_sync = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
3989
adev->dm.disable_hpd_irq = (bool)val;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
401
bool valid_input = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4018
bool mall_supported = dc->caps.mall_size_total;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
4019
bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
617
bool use_prefer_link_setting;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
761
bool disable_hpd = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
762
bool valid_test_pattern = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
182
static void link_lock(struct hdcp_workqueue *work, bool lock)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
198
bool enable_encryption)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
41
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
494
static bool enable_assr(void *handle, struct dc_link *link)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
52
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
536
bool link_is_hdcp14 = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
65
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
73
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
81
static bool lp_atomic_write_poll_read_i2c(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
95
static bool lp_atomic_write_poll_read_aux(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
82
bool enable_encryption);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1172
bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1175
bool ret;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1211
bool dm_helpers_dp_handle_test_pattern_request(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1354
void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1372
static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1374
bool ret_val = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1408
bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1414
bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
177
bool enable,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
266
bool dm_helpers_dp_mst_write_payload_allocation_table(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
270
bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
511
bool dm_helpers_dp_mst_start_top_mgr(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
514
bool boot)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
545
bool dm_helpers_dp_mst_stop_top_mgr(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
567
bool dm_helpers_dp_read_dpcd(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
584
bool dm_helpers_dp_write_dpcd(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
600
bool dm_helpers_submit_i2c(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
609
bool result;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
635
bool dm_helpers_execute_fused_io(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
648
static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
649
bool is_write_cmd,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
655
bool success = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
792
bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
826
bool dm_helpers_dp_write_dsc_enable(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
829
bool enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
909
bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
915
bool dm_helpers_is_dp_sink_present(struct dc_link *link)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
917
bool dp_sink_present;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
140
bool handler_removed = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
240
static bool
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
264
static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
571
bool work_queued = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
696
bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
709
bool st;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
784
bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
810
bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
37
bool allow_sr_entry;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
45
bool crc_window_activated;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1101
bool tried[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1199
bool debugfs_overwrite = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1350
static bool is_dsc_need_re_compute(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1356
bool is_dsc_need_re_compute = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1488
bool computed_streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1558
bool computed_streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1621
static bool is_link_to_dschub(struct dc_link *dc_link)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1636
static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1641
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1780
static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1784
bool is_dsc_possible;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1799
static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
242
bool needs_dsc_aux_workaround(struct dc_link *link)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
253
static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
268
static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
314
static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
333
static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
512
struct drm_modeset_acquire_ctx *ctx, bool force)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
720
bool new_irq_handled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
877
bool compression_possible;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
998
bool bpp_increased[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
78
bool dsc_enabled;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
87
bool needs_dsc_aux_workaround(struct dc_link *link);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
101
bool *per_pixel_alpha, bool *pre_multiplied_alpha,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
102
bool *global_alpha, int *global_alpha_value)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1269
struct drm_atomic_state *state, bool flip)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1525
static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
167
static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1677
bool replaced = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1906
bool amdgpu_dm_plane_is_video_format(uint32_t format)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
328
bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
329
bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
464
bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
847
bool tmz_surface)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
54
bool tmz_surface);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
64
bool *per_pixel_alpha, bool *pre_multiplied_alpha,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
65
bool *global_alpha, int *global_alpha_value);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
67
bool amdgpu_dm_plane_is_video_format(uint32_t format);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
294
bool dm_pp_get_clock_levels_by_type(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
361
bool dm_pp_get_clock_levels_by_type_with_latency(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
37
bool dm_pp_apply_display_requirements(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
381
bool dm_pp_get_clock_levels_by_type_with_voltage(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
401
bool dm_pp_notify_wm_clock_changes(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
420
bool dm_pp_apply_power_level_change_request(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
428
bool dm_pp_apply_clock_for_voltage_request(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
449
bool dm_pp_get_static_clocks(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
646
struct pp_smu *pp, bool pstate_handshake_supported)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
104
bool ret = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
151
bool psr_enable = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
199
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
201
bool psr_enable = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
214
bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
227
bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
230
bool allow_active = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
257
bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
33
static bool link_supports_psrsu(struct dc_link *link)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
98
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
37
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
38
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
39
bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
40
bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
41
bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c
33
bool aux_hpd_discon;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c
34
bool support_edp0_on_dp1;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
121
bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
153
bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
155
bool replay_active = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
180
bool amdgpu_dm_replay_disable(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
182
bool replay_active = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
205
bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
42
bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
79
bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
42
bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
43
bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
44
bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
45
bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
46
bool amdgpu_dm_replay_disable(struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
47
bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
60
void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
116
__field(bool, self_refresh_aware)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
170
__field(bool, enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
171
__field(bool, active)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
172
__field(bool, planes_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
173
__field(bool, mode_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
174
__field(bool, active_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
175
__field(bool, connectors_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
176
__field(bool, zpos_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
177
__field(bool, color_mgmt_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
178
__field(bool, no_vblank)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
179
__field(bool, async_flip)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
180
__field(bool, vrr_enabled)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
181
__field(bool, self_refresh_active)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
254
__field(bool, visible)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
323
__field(bool, allow_modeset)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
324
__field(bool, legacy_cursor_update)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
325
__field(bool, async_update)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
326
__field(bool, duplicated)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
368
__field(bool, async_update)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
369
__field(bool, allow_modeset)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
564
__field(bool, cpuc_state_change_enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
565
__field(bool, cpup_state_change_enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
566
__field(bool, stutter_mode_enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
567
__field(bool, nbp_state_change_enable)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
568
__field(bool, all_displays_in_sync)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
644
TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
648
__field(bool, begin)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
668
TP_PROTO(const struct optc *optc_state, int instance, bool lock, const char *function, const int line),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
674
__field(bool, lock)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
731
TP_PROTO(void *function, u32 user_brightness, u32 converted_brightness, bool aux, bool ac),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
737
__field(bool, aux)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
738
__field(bool, ac)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
49
bool found = false;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
143
bool arg1_negative = arg1.value < 0;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
144
bool arg2_negative = arg2.value < 0;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
61
bool arg1_negative = numerator < 0;
sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c
62
bool arg2_negative = denominator < 0;
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
100
static bool setup_custom_float(const struct custom_float_format *format,
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
101
bool negative,
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
158
bool convert_to_custom_float_format(struct fixed31_32 value,
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
164
bool negative;
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
29
static bool build_custom_float(struct fixed31_32 value,
sys/dev/pci/drm/amd/display/dc/basics/custom_float.c
31
bool *negative,
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
30
bool is_rgb_cspace(enum dc_color_space output_color_space)
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
53
bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
62
bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/basics/dc_common.c
71
bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/basics/dc_common.h
31
bool is_rgb_cspace(enum dc_color_space output_color_space);
sys/dev/pci/drm/amd/display/dc/basics/dc_common.h
33
bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/basics/dc_common.h
35
bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/basics/dc_common.h
37
bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
101
bool d0_underlay_enable;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
102
bool d1_underlay_enable;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
103
bool fbc_enabled;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
104
bool lpt_enabled;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2766
static bool is_display_configuration_supported(
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3009
static bool all_displays_in_sync(const struct pipe_ctx pipe[],
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3041
bool bw_calcs(struct dc_context *ctx,
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
125
bool arg1_negative = arg1.value < 0;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
126
bool arg2_negative = arg2.value < 0;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
73
bool arg1_negative = numerator < 0;
sys/dev/pci/drm/amd/display/dc/basics/fixpt31_32.c
74
bool arg2_negative = denominator < 0;
sys/dev/pci/drm/amd/display/dc/basics/vector.c
162
bool dal_vector_remove_at_index(
sys/dev/pci/drm/amd/display/dc/basics/vector.c
202
bool dal_vector_insert_at(
sys/dev/pci/drm/amd/display/dc/basics/vector.c
234
bool dal_vector_append(
sys/dev/pci/drm/amd/display/dc/basics/vector.c
284
bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
sys/dev/pci/drm/amd/display/dc/basics/vector.c
29
bool dal_vector_construct(
sys/dev/pci/drm/amd/display/dc/basics/vector.c
53
static bool dal_vector_presized_costruct(struct vector *vector,
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1923
static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1925
bool rc = true;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
1946
static bool dal_graphics_object_id_is_equal(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2228
bool state)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
2861
static bool bios_parser_construct(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
79
static bool bios_parser_construct(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
790
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
831
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c
855
static bool bios_parser_is_device_id_supported(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1584
static bool bios_parser_is_device_id_supported(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1676
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1714
static bool bios_parser_is_accelerated_mode(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
1729
bool state)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
3694
static bool bios_parser2_construct(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c
466
bool find_valid = false;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c
57
bool bios_is_accelerated_mode(
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c
76
bool state)
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.h
34
bool bios_is_accelerated_mode(struct dc_bios *bios);
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.h
36
void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal.h
65
bool remap_device_tags;
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal2.h
68
bool remap_device_tags;
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1286
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1290
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1294
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1322
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1366
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1418
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1622
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1627
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1653
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1671
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1692
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1720
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1723
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1746
struct bios_parser *bp, bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1763
struct bios_parser *bp, bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1988
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2007
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2009
bool result = BP_RESULT_FAILURE;
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2040
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2057
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2059
bool result = BP_RESULT_BADINPUT;
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
2218
bool is_input_signal_dp = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
561
bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
51
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
57
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
62
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
67
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
70
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
77
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table.h
81
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table2.c
382
bool is_phy_transition_interlock_allowed = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table2.c
707
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table2.c
724
bool enable)
sys/dev/pci/drm/amd/display/dc/bios/command_table2.c
726
bool result = BP_RESULT_FAILURE;
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
51
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
57
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
62
bool enable,
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
67
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
70
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
77
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table2.h
81
bool enable);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
148
bool enable_dp_audio)
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
212
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
34
bool dal_bios_parser_init_cmd_tbl_helper(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
356
bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
358
bool result = false;
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c
75
bool dal_cmd_table_helper_controller_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h
37
bool dal_bios_parser_init_cmd_tbl_helper(const struct command_table_helper **h,
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h
40
bool dal_cmd_table_helper_controller_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h
46
bool enable_dp_audio);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h
53
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h
68
bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
172
bool enable_dp_audio)
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
197
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
35
bool dal_bios_parser_init_cmd_tbl_helper2(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c
98
bool dal_cmd_table_helper_controller_id_to_atom2(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h
37
bool dal_bios_parser_init_cmd_tbl_helper2(const struct command_table_helper **h,
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h
40
bool dal_cmd_table_helper_controller_id_to_atom2(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h
46
bool enable_dp_audio);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h
48
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h
35
bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h
39
bool enable_dp_audio);
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h
40
bool (*engine_bp_to_atom)(enum engine_id engine_id,
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h
46
bool (*clock_source_id_to_atom)(enum clock_source_id id,
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h
48
bool (*clock_source_id_to_ref_clk_src)(
sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h
61
bool (*dc_clock_type_to_atom)(enum bp_dce_clock_type id,
sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
105
static bool clock_source_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
109
bool result = true;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
104
static bool clock_source_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
108
bool result = true;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
203
static bool dc_clock_type_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
207
bool retCode = true;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
102
static bool clock_source_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
106
bool result = true;
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
201
static bool dc_clock_type_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
205
bool retCode = true;
sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
61
static bool clock_source_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
65
bool result = true;
sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c
61
static bool clock_source_id_to_atom(
sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c
65
bool result = true;
sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c
109
bool allow_active = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
402
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
257
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
193
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
86
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
111
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
189
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
196
bool send_request_to_increase = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
197
bool send_request_to_lower = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
200
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
41
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
42
bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
44
bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
89
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
93
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
105
struct dc_state *context, bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
218
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
225
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
226
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
227
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
228
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
230
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
231
bool p_state_change_support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
345
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
469
static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
31
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
35
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
37
struct dc_state *context, bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
86
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
91
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
92
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
93
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
94
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
95
bool p_state_change_support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
107
struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
133
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
139
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
140
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
141
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
528
static bool rn_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
58
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
234
void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
38
void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
195
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
201
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
202
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
203
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
204
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
205
bool update_pstate_unsupported_clk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
207
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
208
bool update_uclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
209
bool p_state_change_support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
356
static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
430
static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
436
static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
112
bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
126
bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
142
bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
161
bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
312
void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
324
void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
77
static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
33
bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
34
bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
35
bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
36
bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
47
void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
48
void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
76
static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
230
void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
157
void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
103
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
104
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
105
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
465
static bool vg_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
67
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
97
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
114
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
136
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
143
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
144
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
145
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
310
bool dcn31_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
81
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
42
bool dcn31_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
47
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
255
void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
350
void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h
261
void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h
269
void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
178
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
212
bool safe_to_lower, bool disable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
237
bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
275
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
282
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
283
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
284
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
446
bool dcn314_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
716
static inline bool is_valid_clock_value(uint32_t clock_value)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
50
bool dcn314_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
53
bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
59
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
274
void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
389
void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h
100
void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h
108
void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
100
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
127
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
134
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
135
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
136
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
62
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
90
static bool should_disable_otg(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
92
bool ret = true;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
268
void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
357
void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h
120
void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h
129
void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
103
bool safe_to_lower, bool disable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
137
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
144
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
145
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
146
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
74
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
243
void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
309
void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
128
void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
135
void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1069
static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
1100
static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
315
struct dc_state *context, bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
490
static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
492
bool is_native_scaling = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
569
bool is_scaled_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
623
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
629
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
630
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
631
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
632
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
634
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
635
bool update_uclk = false, update_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
636
bool p_state_change_support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
637
bool fclk_p_state_change_support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
994
static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
36
struct dc_state *context, bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
129
static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
161
void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
194
static bool dcn32_get_hard_min_status_supported(struct clk_mgr_internal *clk_mgr)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
210
static unsigned int dcn32_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
226
static bool dcn32_smu_wait_get_hard_min_status(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
231
bool no_timeout, hard_min_done;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
284
bool hard_min_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
303
void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
72
static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
39
void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
44
void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1215
static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1231
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
1529
bool ips_support = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
162
bool tmds_present = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
190
bool safe_to_lower, bool disable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
208
bool stream_changed_otg_dig_on = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
209
bool has_active_hpo = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
281
struct dc_state *context, bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
284
bool dppclk_active[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
342
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
379
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
386
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
387
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
388
bool dpp_clock_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
573
bool dcn35_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
706
static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
993
static inline bool is_valid_clock_value(uint32_t clock_value)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h
49
bool dcn35_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h
54
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
294
void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
445
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
457
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
203
void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
211
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
212
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1081
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1088
bool force_reset = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1089
bool update_dispclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1090
bool update_dppclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1091
bool dppclk_lowered = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
120
static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
122
bool ppclk_idle_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1220
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1327
static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1428
static bool dcn401_are_clock_states_equal(struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
144
static bool dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal *clk_mgr)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
1459
static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
146
bool is_df_throttle_opt_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
314
bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
395
static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
397
bool is_native_scaling = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
471
bool is_scaled_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
531
bool use_hpo_encoder;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
557
struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
75
static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
768
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
77
bool ppclk_dpm_enabled = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
774
bool enter_display_off = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
775
bool update_active_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
776
bool update_active_uclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
777
bool update_idle_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
778
bool update_idle_uclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
779
bool update_subvp_prefetch_dramclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
780
bool update_subvp_prefetch_fclk = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
781
bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
785
bool is_df_throttle_opt_enabled = is_idle_dpm_enabled &&
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
798
bool fclk_p_state_change_support, uclk_p_state_change_support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
108
bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
40
bool support;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
48
bool enable;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
52
bool mod_drr_for_pstate;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
58
bool safe_to_lower;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
112
static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
146
bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
162
bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
181
bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
199
void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
207
void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
255
static unsigned int dcn401_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
271
static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
277
bool hardmin_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
282
bool no_timeout;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
304
bool hard_min_done = false;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
321
void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
328
void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
336
bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
341
bool success;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
358
bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
363
bool success;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
380
bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
385
bool success;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
55
static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
13
bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
14
bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
15
bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
16
void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
17
void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
24
void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
25
void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
26
bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
29
bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
32
bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
sys/dev/pci/drm/amd/display/dc/core/dc.c
1040
static bool dc_construct(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
1204
bool lock)
sys/dev/pci/drm/amd/display/dc/core/dc.c
1326
bool should_disable = true;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1327
bool pipe_split_change = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1359
bool is_phantom = dc_state_get_stream_subvp_type(dc->current_state, old_stream) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1671
bool is_blanked;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1718
bool is_blanked;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1749
static bool streams_changed(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
1768
bool dc_validate_boot_timing(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
193
static bool create_links(
sys/dev/pci/drm/amd/display/dc/core/dc.c
1986
static inline bool should_update_pipe_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc.c
1994
static inline bool should_update_pipe_for_plane(
sys/dev/pci/drm/amd/display/dc/core/dc.c
2118
bool subvp_prev_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2324
static bool commit_minimal_transition_state(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
2346
bool handle_exit_odm2to1 = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2465
bool dc_acquire_release_mpc_3dlut(
sys/dev/pci/drm/amd/display/dc/core/dc.c
2466
struct dc *dc, bool acquire,
sys/dev/pci/drm/amd/display/dc/core/dc.c
2472
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2473
bool found_pipe_idx = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2501
static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/core/dc.c
2582
bool dc_set_generic_gpio_for_stereo(bool enable,
sys/dev/pci/drm/amd/display/dc/core/dc.c
2631
static bool is_surface_in_context(
sys/dev/pci/drm/amd/display/dc/core/dc.c
2909
bool has_flip_immediate_plane = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
332
static bool create_link_encoders(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
334
bool res = true;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3451
static bool update_planes_and_stream_state(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
3717
bool should_program_abm = true;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3737
static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc.c
3862
static bool check_address_only_update(union surface_update_flags update_flags)
sys/dev/pci/drm/amd/display/dc/core/dc.c
3952
bool should_offload_fams2_flip = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
3953
bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4070
bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
sys/dev/pci/drm/amd/display/dc/core/dc.c
4071
bool subvp_prev_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4072
bool subvp_curr_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
414
static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust)
sys/dev/pci/drm/amd/display/dc/core/dc.c
452
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4523
static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4527
bool *is_plane_addition)
sys/dev/pci/drm/amd/display/dc/core/dc.c
4531
bool force_minimal_pipe_splitting = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4532
bool subvp_active = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4597
bool dynamic_odm_policy;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4598
bool subvp_policy;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4689
static bool is_pipe_topology_transition_seamless_with_intermediate_step(
sys/dev/pci/drm/amd/display/dc/core/dc.c
4744
static bool commit_minimal_transition_based_on_new_context(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4750
bool success = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4777
static bool commit_minimal_transition_based_on_current_context(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4780
bool success = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4851
static bool commit_minimal_transition_state_in_dc_update(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4857
bool success = commit_minimal_transition_based_on_new_context(
sys/dev/pci/drm/amd/display/dc/core/dc.c
4886
static bool commit_minimal_transition_state(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
4894
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4895
bool odm_in_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
4997
static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5018
bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5038
static bool full_update_required(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5116
static bool fast_update_only(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5127
static bool update_planes_and_stream_v2(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5140
bool force_minimal_pipe_splitting = 0;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5141
bool is_plane_addition = 0;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5142
bool is_fast_update_only;
sys/dev/pci/drm/amd/display/dc/core/dc.c
515
bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
519
bool status = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5281
static bool update_planes_and_stream_v3(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5331
bool dc_update_planes_and_stream(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5336
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5373
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5416
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
sys/dev/pci/drm/amd/display/dc/core/dc.c
548
struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5489
bool dc_is_dmcu_initialized(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5511
bool dc_set_psr_allow_active(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5514
bool allow_active;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5541
bool dc_set_replay_allow_active(struct dc *dc, bool active)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5544
bool allow_active;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5573
bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5582
void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5640
bool dc_dmub_is_ips_idle_state(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5677
static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
sys/dev/pci/drm/amd/display/dc/core/dc.c
572
struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5733
void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5736
bool p_state_change_support;
sys/dev/pci/drm/amd/display/dc/core/dc.c
5772
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
580
bool
sys/dev/pci/drm/amd/display/dc/core/dc.c
5810
bool dc_is_dmub_outbox_supported(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
582
struct rect *rect, uint8_t phy_id, bool is_stop)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5851
bool dc_enable_dmub_notifications(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
5880
bool dc_process_dmub_aux_transfer_async(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5971
bool dc_process_dmub_set_config_async(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc.c
5977
bool is_cmd_complete = true;
sys/dev/pci/drm/amd/display/dc/core/dc.c
6125
void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6177
bool dc_abm_save_restore(
sys/dev/pci/drm/amd/display/dc/core/dc.c
621
struct crc_window *window, struct otg_phy_mux *mux_mapping, bool stop)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6257
bool powerOn)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6321
bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6340
bool dc_is_cursor_limit_pending(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6352
bool dc_can_clear_cursor_limit(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc.c
647
bool
sys/dev/pci/drm/amd/display/dc/core/dc.c
649
struct crc_window *window, uint8_t phy_id, bool stop)
sys/dev/pci/drm/amd/display/dc/core/dc.c
698
bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc.c
699
struct crc_params *crc_window, bool enable, bool continuous,
sys/dev/pci/drm/amd/display/dc/core/dc.c
700
uint8_t idx, bool reset)
sys/dev/pci/drm/amd/display/dc/core/dc.c
771
bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/core/dc.c
861
bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc.c
864
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
880
bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc.c
883
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc.c
989
static bool dc_construct_ctx(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1074
bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
116
static bool is_rgb_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
119
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
132
static bool is_rgb_limited_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
135
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
143
static bool is_ycbcr601_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
146
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
154
static bool is_ycbcr601_limited_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
157
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
164
static bool is_ycbcr709_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
167
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
175
static bool is_ycbcr2020_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
178
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
185
static bool is_ycbcr709_limited_type(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
188
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
288
bool hwss_wait_for_blank_complete(
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
387
bool is_sdr = false;
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
636
bool enable_subvp;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
187
static bool is_avail_link_enc(struct dc_state *state, enum engine_id eng_id, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
189
bool is_avail = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
212
static bool are_ep_ids_equal(struct display_endpoint_id *lhs, struct display_endpoint_id *rhs)
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
214
bool are_equal = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
32
static bool is_dig_link_enc_stream(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
34
bool is_dig_stream = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
448
bool link_enc_cfg_is_transmitter_mappable(
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
452
bool is_mappable = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
598
bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
600
bool is_avail = true;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
619
bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
621
bool is_valid = false;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
622
bool valid_entries = true;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
623
bool valid_stream_ptrs = true;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
624
bool valid_uniqueness = true;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
625
bool valid_avail = true;
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
626
bool valid_streams = true;
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
102
bool dc_link_is_hdcp14(struct dc_link *link, enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
107
bool dc_link_is_hdcp22(struct dc_link *link, enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
117
bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
147
bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
160
bool dc_is_oem_i2c_device_present(
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
173
bool dc_submit_i2c(
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
188
bool dc_submit_i2c_oem(
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
208
bool dc_link_dp_set_test_pattern(
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
242
bool skip_immediate_retrain)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
248
bool dc_dp_trace_is_initialized(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
254
bool in_detection,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
255
bool is_logged)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
260
bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
266
bool in_detection)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
272
bool in_detection)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
311
bool dc_link_decide_edp_link_settings(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
318
bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
353
bool dc_link_is_dp_sink_present(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
358
bool dc_link_is_fec_supported(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
369
bool dc_link_should_enable_fec(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
380
bool dc_link_check_link_loss_status(
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
387
bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
404
bool dc_link_handle_hpd_rx_irq(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
405
union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
406
bool defer_handling, bool *has_left_work)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
412
void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
423
void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
433
bool dc_link_get_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
442
bool dc_link_set_backlight_level(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
449
bool dc_link_set_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
450
bool isHDR,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
463
bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
468
bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
469
bool wait, bool force_static, const unsigned int *power_opts)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
475
bool dc_link_setup_psr(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
482
bool dc_link_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
483
bool wait, bool force_static, const unsigned int *power_opts)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
489
bool dc_link_get_replay_state(const struct dc_link *link, uint64_t *state)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
494
bool dc_link_wait_for_t12(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
499
bool dc_link_get_hpd_state(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
514
void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
525
bool *auxless_support,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
526
bool *auxwake_support)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
66
bool dc_get_edp_link_panel_inst(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
85
bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c
90
bool dc_link_detect_connection_type(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1194
bool flip_scan_dir,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1266
bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1443
bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1449
bool res = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1641
bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1934
bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2135
bool is_last_segment)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2141
bool two_pixel_alignment_required = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2175
bool is_last_odm_slice = pipe_ctx->next_odm_pipe == NULL;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2216
bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2262
bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2306
bool is_primary)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2359
bool is_primary;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2481
static bool update_pipe_params_after_odm_slice_count_change(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2488
bool result = true;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2504
static bool update_pipe_params_after_mpc_slice_count_change(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2511
bool result = true;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2560
bool acquired)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2574
bool acquired)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2635
static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2730
static bool is_dio_enc_acquired_by_other_link(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2769
static bool add_dio_link_enc_to_ctx(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2921
static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2970
static bool acquire_secondary_dpp_pipes_and_add_plane(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3018
bool resource_append_dpp_pipes_for_plane_composition(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3025
bool success;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3112
static bool acquire_pipes_and_add_odm_slice(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3192
static bool release_pipes_and_remove_odm_slice(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3251
static bool acquire_dpp_pipe_and_add_mpc_slice(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3314
static bool release_dpp_pipe_and_remove_mpc_slice(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3339
bool resource_update_pipes_for_stream_with_slice_count(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3350
bool result = true;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3374
bool resource_update_pipes_for_plane_with_slice_count(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3385
bool result = true;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3409
bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3425
static bool are_stream_backends_same(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3454
bool dc_is_stream_unchanged(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3476
bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3503
bool acquired)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3780
static bool acquire_otg_master_pipe_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3870
bool acquired = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3871
bool is_dio_encoder = true;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3986
bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3994
static bool planes_changed_for_existing_stream(struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
400
bool resource_construct(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4031
static bool add_all_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4088
bool found = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4879
bool pipe_need_reprogram(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4925
bool need_reprogram = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5231
bool get_temp_dp_link_res(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5401
bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5403
bool divisible = false;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5433
bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5438
bool odm)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5535
static bool resource_allocate_mcache(struct dc_state *context, const struct dc_mcache_params *mcache_params)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
558
bool resource_are_vblanks_synchronizable(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5609
bool resource_is_hpo_acquired(struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
601
bool resource_are_streams_timing_synchronizable(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
643
static bool is_dp_and_hdmi_sharable(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
658
static bool is_sharable_clk_src(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
756
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
757
bool *orthogonal_rotation,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
758
bool *flip_vert_scan_dir,
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
759
bool *flip_horz_scan_dir)
sys/dev/pci/drm/amd/display/dc/core/dc_sink.c
34
static bool dc_sink_construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1001
bool dc_state_get_stream_subvp_cursor_limit(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1004
bool limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1019
bool limit)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1030
bool dc_state_get_stream_cursor_subvp_limit(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1033
bool limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1046
bool dc_state_can_clear_stream_cursor_subvp_limit(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1049
bool can_clear_limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
1067
bool dc_state_is_subvp_in_use(struct dc_state *state)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
107
static bool dc_state_untrack_phantom_plane(struct dc_state *state, struct dc_plane_state *phantom_plane)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
109
bool res = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
133
static bool dc_state_is_phantom_plane_tracked(struct dc_state *state, struct dc_plane_state *phantom_plane)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
463
bool dc_state_add_plane(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
47
static bool dc_state_track_phantom_stream(struct dc_state *state,
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
472
bool added = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
531
bool dc_state_remove_plane(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
58
static bool dc_state_untrack_phantom_stream(struct dc_state *state, struct dc_stream_state *phantom_stream)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
592
bool dc_state_rem_all_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
60
bool res = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
624
bool dc_state_add_all_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
632
bool result = true;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
84
static bool dc_state_is_phantom_stream_tracked(struct dc_state *state, struct dc_stream_state *phantom_stream)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
844
bool dc_state_add_phantom_plane(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
850
bool res = dc_state_add_plane(dc, phantom_stream, phantom_plane, state);
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
861
bool dc_state_remove_phantom_plane(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
870
bool dc_state_rem_all_phantom_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
874
bool should_release_planes)
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
906
bool dc_state_add_all_phantom_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
916
bool dc_state_remove_phantom_streams_and_planes(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
921
bool removed_phantom = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
96
static bool dc_state_track_phantom_plane(struct dc_state *state,
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
973
bool dc_state_is_fams2_in_use(
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
977
bool is_fams2_in_use = false;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
990
bool limit)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1016
bool is_gaming,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1017
bool search_for_max_increase)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1076
static int dc_stream_get_max_delta_lumin_millinits(struct dc_stream_state *stream, int hz1, int hz2, bool isGaming)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1112
static unsigned int dc_stream_get_max_flickerless_instant_vtotal_delta(struct dc_stream_state *stream, bool is_gaming, bool increase)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1137
int dc_stream_calculate_max_flickerless_refresh_rate(struct dc_stream_state *stream, int starting_refresh_hz, bool is_gaming)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1155
int dc_stream_calculate_min_flickerless_refresh_rate(struct dc_stream_state *stream, int starting_refresh_hz, bool is_gaming)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1172
bool dc_stream_is_refresh_rate_range_flickerless(struct dc_stream_state *stream, int hz1, int hz2, bool is_gaming)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1195
bool is_gaming)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1208
bool is_gaming)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1216
bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1218
bool is_limit_pending = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1226
bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
1228
bool can_clear_limit = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
270
bool dc_stream_check_cursor_attributes(
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
313
bool dc_stream_set_cursor_attributes(
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
317
bool result = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
330
bool dc_stream_program_cursor_attributes(
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
335
bool reset_idle_optimizations = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
399
bool dc_stream_set_cursor_position(
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
419
bool dc_stream_program_cursor_position(
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
424
bool reset_idle_optimizations = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
475
bool dc_stream_add_writeback(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
479
bool isDrc = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
549
bool dc_stream_fc_disable_writeback(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
586
bool dc_stream_remove_writeback(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
65
bool dc_stream_construct(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
663
bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
700
bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
707
bool ret = false;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
738
bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
760
bool dc_stream_set_dynamic_metadata(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
882
bool allocate_one)
sys/dev/pci/drm/amd/display/dc/core/dc_surface.c
276
bool clear_tiling)
sys/dev/pci/drm/amd/display/dc/dc.h
1001
bool disable_pplib_clock_request;
sys/dev/pci/drm/amd/display/dc/dc.h
1002
bool disable_clock_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
1003
bool disable_mem_low_power;
sys/dev/pci/drm/amd/display/dc/dc.h
1004
bool pstate_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1005
bool disable_dmcu;
sys/dev/pci/drm/amd/display/dc/dc.h
1006
bool force_abm_enable;
sys/dev/pci/drm/amd/display/dc/dc.h
1007
bool disable_stereo_support;
sys/dev/pci/drm/amd/display/dc/dc.h
1008
bool vsr_support;
sys/dev/pci/drm/amd/display/dc/dc.h
1009
bool performance_trace;
sys/dev/pci/drm/amd/display/dc/dc.h
1010
bool az_endpoint_mute_only;
sys/dev/pci/drm/amd/display/dc/dc.h
1011
bool always_use_regamma;
sys/dev/pci/drm/amd/display/dc/dc.h
1012
bool recovery_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1013
bool avoid_vbios_exec_table;
sys/dev/pci/drm/amd/display/dc/dc.h
1014
bool scl_reset_length10;
sys/dev/pci/drm/amd/display/dc/dc.h
1015
bool hdmi20_disable;
sys/dev/pci/drm/amd/display/dc/dc.h
1016
bool skip_detection_link_training;
sys/dev/pci/drm/amd/display/dc/dc.h
1023
bool disable_z9_mpc;
sys/dev/pci/drm/amd/display/dc/dc.h
1025
bool enable_tri_buf;
sys/dev/pci/drm/amd/display/dc/dc.h
1026
bool ips_disallow_entry;
sys/dev/pci/drm/amd/display/dc/dc.h
1027
bool dmub_offload_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1028
bool dmcub_emulation;
sys/dev/pci/drm/amd/display/dc/dc.h
1029
bool disable_idle_power_optimizations;
sys/dev/pci/drm/amd/display/dc/dc.h
1032
bool mall_error_as_fatal;
sys/dev/pci/drm/amd/display/dc/dc.h
1033
bool dmub_command_table; /* for testing only */
sys/dev/pci/drm/amd/display/dc/dc.h
1035
bool disable_fec;
sys/dev/pci/drm/amd/display/dc/dc.h
1036
bool disable_48mhz_pwrdwn;
sys/dev/pci/drm/amd/display/dc/dc.h
1042
bool disable_timing_sync;
sys/dev/pci/drm/amd/display/dc/dc.h
1043
bool cm_in_bypass;
sys/dev/pci/drm/amd/display/dc/dc.h
1046
bool disable_dram_clock_change_vactive_support;
sys/dev/pci/drm/amd/display/dc/dc.h
1047
bool validate_dml_output;
sys/dev/pci/drm/amd/display/dc/dc.h
1048
bool enable_dmcub_surface_flip;
sys/dev/pci/drm/amd/display/dc/dc.h
1049
bool usbc_combo_phy_reset_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
1050
bool enable_dram_clock_change_one_display_vactive;
sys/dev/pci/drm/amd/display/dc/dc.h
1052
bool legacy_dp2_lt;
sys/dev/pci/drm/amd/display/dc/dc.h
1053
bool set_mst_en_for_sst;
sys/dev/pci/drm/amd/display/dc/dc.h
1054
bool disable_uhbr;
sys/dev/pci/drm/amd/display/dc/dc.h
1055
bool force_dp2_lt_fallback_method;
sys/dev/pci/drm/amd/display/dc/dc.h
1056
bool ignore_cable_id;
sys/dev/pci/drm/amd/display/dc/dc.h
1060
bool hpo_optimization;
sys/dev/pci/drm/amd/display/dc/dc.h
1061
bool force_vblank_alignment;
sys/dev/pci/drm/amd/display/dc/dc.h
1064
bool enable_dmub_aux_for_legacy_ddc;
sys/dev/pci/drm/amd/display/dc/dc.h
1065
bool disable_fams;
sys/dev/pci/drm/amd/display/dc/dc.h
1069
bool enable_driver_sequence_debug;
sys/dev/pci/drm/amd/display/dc/dc.h
1072
bool disable_z10;
sys/dev/pci/drm/amd/display/dc/dc.h
1073
bool enable_z9_disable_interface;
sys/dev/pci/drm/amd/display/dc/dc.h
1074
bool psr_skip_crtc_disable;
sys/dev/pci/drm/amd/display/dc/dc.h
1077
bool disable_fixed_vs_aux_timeout_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
1079
bool force_disable_subvp;
sys/dev/pci/drm/amd/display/dc/dc.h
1080
bool force_subvp_mclk_switch;
sys/dev/pci/drm/amd/display/dc/dc.h
1081
bool allow_sw_cursor_fallback;
sys/dev/pci/drm/amd/display/dc/dc.h
1084
bool alloc_extra_way_for_cursor;
sys/dev/pci/drm/amd/display/dc/dc.h
1086
bool disable_force_pstate_allow_on_hw_release;
sys/dev/pci/drm/amd/display/dc/dc.h
1087
bool force_usr_allow;
sys/dev/pci/drm/amd/display/dc/dc.h
1089
bool disable_dtb_ref_clk_switch;
sys/dev/pci/drm/amd/display/dc/dc.h
1090
bool extended_blank_optimization;
sys/dev/pci/drm/amd/display/dc/dc.h
1095
bool dml_disallow_alternate_prefetch_modes;
sys/dev/pci/drm/amd/display/dc/dc.h
1096
bool use_legacy_soc_bb_mechanism;
sys/dev/pci/drm/amd/display/dc/dc.h
1097
bool exit_idle_opt_for_cursor_updates;
sys/dev/pci/drm/amd/display/dc/dc.h
1098
bool using_dml2;
sys/dev/pci/drm/amd/display/dc/dc.h
1099
bool enable_single_display_2to1_odm_policy;
sys/dev/pci/drm/amd/display/dc/dc.h
1100
bool enable_double_buffered_dsc_pg_support;
sys/dev/pci/drm/amd/display/dc/dc.h
1101
bool enable_dp_dig_pixel_rate_div_policy;
sys/dev/pci/drm/amd/display/dc/dc.h
1102
bool using_dml21;
sys/dev/pci/drm/amd/display/dc/dc.h
1106
bool disable_unbounded_requesting;
sys/dev/pci/drm/amd/display/dc/dc.h
1107
bool dig_fifo_off_in_blank;
sys/dev/pci/drm/amd/display/dc/dc.h
1108
bool override_dispclk_programming;
sys/dev/pci/drm/amd/display/dc/dc.h
1109
bool otg_crc_db;
sys/dev/pci/drm/amd/display/dc/dc.h
1110
bool disallow_dispclk_dppclk_ds;
sys/dev/pci/drm/amd/display/dc/dc.h
1111
bool disable_fpo_optimizations;
sys/dev/pci/drm/amd/display/dc/dc.h
1112
bool support_eDP1_5;
sys/dev/pci/drm/amd/display/dc/dc.h
1114
bool disable_fpo_vactive;
sys/dev/pci/drm/amd/display/dc/dc.h
1115
bool disable_boot_optimizations;
sys/dev/pci/drm/amd/display/dc/dc.h
1116
bool override_odm_optimization;
sys/dev/pci/drm/amd/display/dc/dc.h
1117
bool minimize_dispclk_using_odm;
sys/dev/pci/drm/amd/display/dc/dc.h
1118
bool disable_subvp_high_refresh;
sys/dev/pci/drm/amd/display/dc/dc.h
1119
bool disable_dp_plus_plus_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
1122
bool enable_hpo_pg_support;
sys/dev/pci/drm/amd/display/dc/dc.h
1123
bool enable_legacy_fast_update;
sys/dev/pci/drm/amd/display/dc/dc.h
1124
bool disable_dc_mode_overwrite;
sys/dev/pci/drm/amd/display/dc/dc.h
1125
bool replay_skip_crtc_disabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1126
bool ignore_pg;/*do nothing, let pmfw control it*/
sys/dev/pci/drm/amd/display/dc/dc.h
1127
bool psp_disabled_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
1130
bool optimize_ips_handshake;
sys/dev/pci/drm/amd/display/dc/dc.h
1131
bool disable_dmub_reallow_idle;
sys/dev/pci/drm/amd/display/dc/dc.h
1132
bool disable_timeout;
sys/dev/pci/drm/amd/display/dc/dc.h
1133
bool disable_extblankadj;
sys/dev/pci/drm/amd/display/dc/dc.h
1134
bool enable_idle_reg_checks;
sys/dev/pci/drm/amd/display/dc/dc.h
1137
bool force_chroma_subsampling_1tap;
sys/dev/pci/drm/amd/display/dc/dc.h
1139
bool disable_422_left_edge_pixel;
sys/dev/pci/drm/amd/display/dc/dc.h
1140
bool dml21_force_pstate_method;
sys/dev/pci/drm/amd/display/dc/dc.h
1151
bool notify_dpia_hr_bw;
sys/dev/pci/drm/amd/display/dc/dc.h
1152
bool enable_ips_visual_confirm;
sys/dev/pci/drm/amd/display/dc/dc.h
1155
bool skip_full_updated_if_possible;
sys/dev/pci/drm/amd/display/dc/dc.h
1157
bool enable_hblank_borrow;
sys/dev/pci/drm/amd/display/dc/dc.h
1158
bool force_subvp_df_throttle;
sys/dev/pci/drm/amd/display/dc/dc.h
1160
bool enable_pg_cntl_debug_logs;
sys/dev/pci/drm/amd/display/dc/dc.h
1166
bool disable_stutter_for_wm_program;
sys/dev/pci/drm/amd/display/dc/dc.h
1188
bool dchub_initialzied;
sys/dev/pci/drm/amd/display/dc/dc.h
1189
bool dchub_info_valid;
sys/dev/pci/drm/amd/display/dc/dc.h
1215
bool force_smu_not_present;
sys/dev/pci/drm/amd/display/dc/dc.h
1354
bool isInUse;
sys/dev/pci/drm/amd/display/dc/dc.h
1373
bool is_flip_pending;
sys/dev/pci/drm/amd/display/dc/dc.h
1374
bool is_right_eye;
sys/dev/pci/drm/amd/display/dc/dc.h
1421
bool triplebuffer_flips;
sys/dev/pci/drm/amd/display/dc/dc.h
1454
bool is_tiling_rotated;
sys/dev/pci/drm/amd/display/dc/dc.h
1455
bool per_pixel_alpha;
sys/dev/pci/drm/amd/display/dc/dc.h
1456
bool pre_multiplied_alpha;
sys/dev/pci/drm/amd/display/dc/dc.h
1457
bool global_alpha;
sys/dev/pci/drm/amd/display/dc/dc.h
1459
bool visible;
sys/dev/pci/drm/amd/display/dc/dc.h
1460
bool flip_immediate;
sys/dev/pci/drm/amd/display/dc/dc.h
1461
bool horizontal_mirror;
sys/dev/pci/drm/amd/display/dc/dc.h
1465
bool flip_int_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1466
bool skip_manual_trigger;
sys/dev/pci/drm/amd/display/dc/dc.h
1473
bool force_full_update;
sys/dev/pci/drm/amd/display/dc/dc.h
1475
bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
sys/dev/pci/drm/amd/display/dc/dc.h
1482
bool is_statically_allocated;
sys/dev/pci/drm/amd/display/dc/dc.h
1485
bool mcm_lut1d_enable;
sys/dev/pci/drm/amd/display/dc/dc.h
1487
bool lut_bank_a;
sys/dev/pci/drm/amd/display/dc/dc.h
1490
bool adaptive_sharpness_en;
sys/dev/pci/drm/amd/display/dc/dc.h
1507
bool horizontal_mirror;
sys/dev/pci/drm/amd/display/dc/dc.h
1508
bool visible;
sys/dev/pci/drm/amd/display/dc/dc.h
1509
bool per_pixel_alpha;
sys/dev/pci/drm/amd/display/dc/dc.h
1510
bool pre_multiplied_alpha;
sys/dev/pci/drm/amd/display/dc/dc.h
1511
bool global_alpha;
sys/dev/pci/drm/amd/display/dc/dc.h
1513
bool input_csc_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1548
bool is_hpd_filter_disabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1549
bool dp_ss_off;
sys/dev/pci/drm/amd/display/dc/dc.h
1558
bool link_state_valid;
sys/dev/pci/drm/amd/display/dc/dc.h
1559
bool aux_access_disabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1560
bool sync_lt_in_progress;
sys/dev/pci/drm/amd/display/dc/dc.h
1561
bool skip_stream_reenable;
sys/dev/pci/drm/amd/display/dc/dc.h
1562
bool is_internal_display;
sys/dev/pci/drm/amd/display/dc/dc.h
1564
bool is_dig_mapping_flexible;
sys/dev/pci/drm/amd/display/dc/dc.h
1565
bool hpd_status; /* HPD status of link without physical HPD pin. */
sys/dev/pci/drm/amd/display/dc/dc.h
1566
bool is_hpd_pending; /* Indicates a new received hpd */
sys/dev/pci/drm/amd/display/dc/dc.h
1573
bool skip_fallback_on_link_loss;
sys/dev/pci/drm/amd/display/dc/dc.h
1575
bool edp_sink_present;
sys/dev/pci/drm/amd/display/dc/dc.h
1606
bool test_pattern_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
1627
bool aux_mode;
sys/dev/pci/drm/amd/display/dc/dc.h
1661
bool apply_vendor_specific_lttpr_link_rate_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
1665
bool dp_keep_receiver_powered;
sys/dev/pci/drm/amd/display/dc/dc.h
1666
bool dp_skip_DID2;
sys/dev/pci/drm/amd/display/dc/dc.h
1667
bool dp_skip_reset_segment;
sys/dev/pci/drm/amd/display/dc/dc.h
1668
bool dp_skip_fs_144hz;
sys/dev/pci/drm/amd/display/dc/dc.h
1669
bool dp_mot_reset_segment;
sys/dev/pci/drm/amd/display/dc/dc.h
1671
bool dpia_mst_dsc_always_on;
sys/dev/pci/drm/amd/display/dc/dc.h
1673
bool dpia_forced_tbt3_mode;
sys/dev/pci/drm/amd/display/dc/dc.h
1674
bool dongle_mode_timing_override;
sys/dev/pci/drm/amd/display/dc/dc.h
1675
bool blank_stream_on_ocs_change;
sys/dev/pci/drm/amd/display/dc/dc.h
1676
bool read_dpcd204h_on_irq_hpd;
sys/dev/pci/drm/amd/display/dc/dc.h
1677
bool force_dp_ffe_preset;
sys/dev/pci/drm/amd/display/dc/dc.h
1678
bool skip_phy_ssc_reduction;
sys/dev/pci/drm/amd/display/dc/dc.h
1688
bool is_dds;
sys/dev/pci/drm/amd/display/dc/dc.h
1689
bool is_display_mux_present;
sys/dev/pci/drm/amd/display/dc/dc.h
1690
bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
sys/dev/pci/drm/amd/display/dc/dc.h
1697
bool skip_implict_edp_power_control;
sys/dev/pci/drm/amd/display/dc/dc.h
1737
bool optimized_required;
sys/dev/pci/drm/amd/display/dc/dc.h
1738
bool idle_optimizations_allowed;
sys/dev/pci/drm/amd/display/dc/dc.h
1739
bool enable_c20_dtm_b0;
sys/dev/pci/drm/amd/display/dc/dc.h
1744
bool is_switch_in_progress_orig;
sys/dev/pci/drm/amd/display/dc/dc.h
1745
bool is_switch_in_progress_dest;
sys/dev/pci/drm/amd/display/dc/dc.h
1773
bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
sys/dev/pci/drm/amd/display/dc/dc.h
1887
bool dc_validate_boot_timing(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc.h
1899
bool dc_set_generic_gpio_for_stereo(bool enable,
sys/dev/pci/drm/amd/display/dc/dc.h
1907
bool dc_acquire_release_mpc_3dlut(
sys/dev/pci/drm/amd/display/dc/dc.h
1908
struct dc *dc, bool acquire,
sys/dev/pci/drm/amd/display/dc/dc.h
1913
bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
1917
bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);
sys/dev/pci/drm/amd/display/dc/dc.h
1940
void dc_set_disable_128b_132b_stream_overhead(bool disable);
sys/dev/pci/drm/amd/display/dc/dc.h
1958
bool dc_get_edp_link_panel_inst(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc.h
1968
bool powerOn);
sys/dev/pci/drm/amd/display/dc/dc.h
1990
bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
sys/dev/pci/drm/amd/display/dc/dc.h
2034
bool dc_link_detect_connection_type(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2041
bool dc_link_get_hpd_state(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2060
void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/dc.h
2067
bool dc_submit_i2c(
sys/dev/pci/drm/amd/display/dc/dc.h
2077
bool dc_submit_i2c_oem(
sys/dev/pci/drm/amd/display/dc/dc.h
2094
bool dc_is_oem_i2c_device_present(
sys/dev/pci/drm/amd/display/dc/dc.h
2100
bool dc_link_is_hdcp14(struct dc_link *link, enum amd_signal_type signal);
sys/dev/pci/drm/amd/display/dc/dc.h
2101
bool dc_link_is_hdcp22(struct dc_link *link, enum amd_signal_type signal);
sys/dev/pci/drm/amd/display/dc/dc.h
2115
bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
sys/dev/pci/drm/amd/display/dc/dc.h
2116
union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
sys/dev/pci/drm/amd/display/dc/dc.h
2117
bool defer_handling, bool *has_left_work);
sys/dev/pci/drm/amd/display/dc/dc.h
2130
bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2137
bool dc_link_check_link_loss_status(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2163
bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2228
bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/dc.h
2241
bool dc_link_decide_edp_link_settings(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2248
bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2283
bool dc_link_is_dp_sink_present(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2310
bool dc_link_dp_set_test_pattern(
sys/dev/pci/drm/amd/display/dc/dc.h
2343
bool skip_immediate_retrain);
sys/dev/pci/drm/amd/display/dc/dc.h
2346
bool dc_link_is_fec_supported(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2352
bool dc_link_should_enable_fec(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2368
void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
sys/dev/pci/drm/amd/display/dc/dc.h
2379
bool wait_for_hpd);
sys/dev/pci/drm/amd/display/dc/dc.h
2385
bool dc_link_set_backlight_level(const struct dc_link *dc_link,
sys/dev/pci/drm/amd/display/dc/dc.h
2389
bool dc_link_set_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2390
bool isHDR,
sys/dev/pci/drm/amd/display/dc/dc.h
2394
bool dc_link_get_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2402
bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
sys/dev/pci/drm/amd/display/dc/dc.h
2403
bool wait, bool force_static, const unsigned int *power_opts);
sys/dev/pci/drm/amd/display/dc/dc.h
2405
bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
sys/dev/pci/drm/amd/display/dc/dc.h
2407
bool dc_link_setup_psr(struct dc_link *dc_link,
sys/dev/pci/drm/amd/display/dc/dc.h
2422
bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
sys/dev/pci/drm/amd/display/dc/dc.h
2423
bool wait, bool force_static, const unsigned int *power_opts);
sys/dev/pci/drm/amd/display/dc/dc.h
2425
bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
sys/dev/pci/drm/amd/display/dc/dc.h
2431
bool dc_link_wait_for_t12(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2437
bool dc_dp_trace_is_initialized(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dc.h
2442
bool dc_dp_trace_is_logged(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dc.h
2443
bool in_detection);
sys/dev/pci/drm/amd/display/dc/dc.h
2450
bool in_detection,
sys/dev/pci/drm/amd/display/dc/dc.h
2451
bool is_logged);
sys/dev/pci/drm/amd/display/dc/dc.h
2460
bool in_detection);
sys/dev/pci/drm/amd/display/dc/dc.h
2468
bool in_detection);
sys/dev/pci/drm/amd/display/dc/dc.h
2511
void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support,
sys/dev/pci/drm/amd/display/dc/dc.h
2512
bool *auxwake_support);
sys/dev/pci/drm/amd/display/dc/dc.h
2531
bool is_virtual_dpcd_dsc;
sys/dev/pci/drm/amd/display/dc/dc.h
2534
bool is_dsc_passthrough_supported;
sys/dev/pci/drm/amd/display/dc/dc.h
2541
bool is_virtual_dpcd_hblank_expansion;
sys/dev/pci/drm/amd/display/dc/dc.h
2546
bool is_rx_fec_supported;
sys/dev/pci/drm/amd/display/dc/dc.h
2547
bool is_topology_fec_supported;
sys/dev/pci/drm/amd/display/dc/dc.h
255
bool preblend;
sys/dev/pci/drm/amd/display/dc/dc.h
2566
bool converter_disable_audio;
sys/dev/pci/drm/amd/display/dc/dc.h
2573
bool is_vsc_sdp_colorimetry_supported;
sys/dev/pci/drm/amd/display/dc/dc.h
2595
bool converter_disable_audio;
sys/dev/pci/drm/amd/display/dc/dc.h
2612
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
sys/dev/pci/drm/amd/display/dc/dc.h
2617
void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
sys/dev/pci/drm/amd/display/dc/dc.h
2635
bool dc_is_dmcu_initialized(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
2640
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc.h
2649
void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
sys/dev/pci/drm/amd/display/dc/dc.h
2651
bool dc_dmub_is_ips_idle_state(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
2660
void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/dc.h
2668
bool dc_set_psr_allow_active(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/dc.h
2670
bool dc_set_replay_allow_active(struct dc *dc, bool active);
sys/dev/pci/drm/amd/display/dc/dc.h
2672
bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
sys/dev/pci/drm/amd/display/dc/dc.h
2677
bool dc_is_dmub_outbox_supported(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
2678
bool dc_enable_dmub_notifications(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
2680
bool dc_abm_save_restore(
sys/dev/pci/drm/amd/display/dc/dc.h
2687
bool dc_process_dmub_aux_transfer_async(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc.h
269
bool psr;
sys/dev/pci/drm/amd/display/dc/dc.h
2695
bool dc_process_dmub_set_config_async(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc.h
270
bool mclk_sw;
sys/dev/pci/drm/amd/display/dc/dc.h
271
bool subvp_psr;
sys/dev/pci/drm/amd/display/dc/dc.h
272
bool gecc_enable;
sys/dev/pci/drm/amd/display/dc/dc.h
2722
bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index);
sys/dev/pci/drm/amd/display/dc/dc.h
2735
bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
sys/dev/pci/drm/amd/display/dc/dc.h
2738
bool dc_is_cursor_limit_pending(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
2739
bool dc_can_clear_cursor_limit(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/dc.h
274
bool aux_backlight_support;
sys/dev/pci/drm/amd/display/dc/dc.h
278
bool sharpener_support;
sys/dev/pci/drm/amd/display/dc/dc.h
303
bool dcc_const_color;
sys/dev/pci/drm/amd/display/dc/dc.h
304
bool dynamic_audio;
sys/dev/pci/drm/amd/display/dc/dc.h
305
bool is_apu;
sys/dev/pci/drm/amd/display/dc/dc.h
306
bool dual_link_dvi;
sys/dev/pci/drm/amd/display/dc/dc.h
307
bool post_blend_color_processing;
sys/dev/pci/drm/amd/display/dc/dc.h
308
bool force_dp_tps4_for_cp2520;
sys/dev/pci/drm/amd/display/dc/dc.h
309
bool disable_dp_clk_share;
sys/dev/pci/drm/amd/display/dc/dc.h
310
bool psp_setup_panel_mode;
sys/dev/pci/drm/amd/display/dc/dc.h
311
bool extended_aux_timeout_support;
sys/dev/pci/drm/amd/display/dc/dc.h
312
bool dmcub_support;
sys/dev/pci/drm/amd/display/dc/dc.h
313
bool zstate_support;
sys/dev/pci/drm/amd/display/dc/dc.h
314
bool ips_support;
sys/dev/pci/drm/amd/display/dc/dc.h
315
bool ips_v2_support;
sys/dev/pci/drm/amd/display/dc/dc.h
324
bool dp_hpo;
sys/dev/pci/drm/amd/display/dc/dc.h
325
bool dp_hdmi21_pcon_support;
sys/dev/pci/drm/amd/display/dc/dc.h
326
bool edp_dsc_support;
sys/dev/pci/drm/amd/display/dc/dc.h
327
bool vbios_lttpr_aware;
sys/dev/pci/drm/amd/display/dc/dc.h
328
bool vbios_lttpr_enable;
sys/dev/pci/drm/amd/display/dc/dc.h
329
bool fused_io_supported;
sys/dev/pci/drm/amd/display/dc/dc.h
340
bool seamless_odm;
sys/dev/pci/drm/amd/display/dc/dc.h
342
bool vtotal_limited_by_fp2;
sys/dev/pci/drm/amd/display/dc/dc.h
345
bool cursor_not_scaled;
sys/dev/pci/drm/amd/display/dc/dc.h
346
bool dcmode_power_limits_present;
sys/dev/pci/drm/amd/display/dc/dc.h
347
bool sequential_ono;
sys/dev/pci/drm/amd/display/dc/dc.h
358
bool no_connect_phy_config;
sys/dev/pci/drm/amd/display/dc/dc.h
359
bool dedcn20_305_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
360
bool skip_clock_update;
sys/dev/pci/drm/amd/display/dc/dc.h
361
bool lt_early_cr_pattern;
sys/dev/pci/drm/amd/display/dc/dc.h
368
bool skip_psr_ips_crtc_disable;
sys/dev/pci/drm/amd/display/dc/dc.h
386
bool independent_64b_blks;
sys/dev/pci/drm/amd/display/dc/dc.h
411
bool capable;
sys/dev/pci/drm/amd/display/dc/dc.h
412
bool const_color_support;
sys/dev/pci/drm/amd/display/dc/dc.h
417
bool force_trigger;
sys/dev/pci/drm/amd/display/dc/dc.h
418
bool cursor_update;
sys/dev/pci/drm/amd/display/dc/dc.h
419
bool surface_update;
sys/dev/pci/drm/amd/display/dc/dc.h
420
bool overlay_update;
sys/dev/pci/drm/amd/display/dc/dc.h
464
bool (*get_dcc_compression_cap)(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc.h
467
bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/dc.h
474
bool DP1_4A : 1;
sys/dev/pci/drm/amd/display/dc/dc.h
475
bool DP2_0 : 1;
sys/dev/pci/drm/amd/display/dc/dc.h
482
bool gpu_vm_support;
sys/dev/pci/drm/amd/display/dc/dc.h
483
bool disable_disp_pll_sharing;
sys/dev/pci/drm/amd/display/dc/dc.h
484
bool fbc_support;
sys/dev/pci/drm/amd/display/dc/dc.h
485
bool disable_fractional_pwm;
sys/dev/pci/drm/amd/display/dc/dc.h
486
bool allow_seamless_boot_optimization;
sys/dev/pci/drm/amd/display/dc/dc.h
487
bool seamless_boot_edp_requested;
sys/dev/pci/drm/amd/display/dc/dc.h
488
bool edp_not_connected;
sys/dev/pci/drm/amd/display/dc/dc.h
489
bool edp_no_power_sequencing;
sys/dev/pci/drm/amd/display/dc/dc.h
490
bool force_enum_edp;
sys/dev/pci/drm/amd/display/dc/dc.h
491
bool forced_clocks;
sys/dev/pci/drm/amd/display/dc/dc.h
493
bool multi_mon_pp_mclk_switch;
sys/dev/pci/drm/amd/display/dc/dc.h
494
bool disable_dmcu;
sys/dev/pci/drm/amd/display/dc/dc.h
495
bool enable_4to1MPC;
sys/dev/pci/drm/amd/display/dc/dc.h
496
bool enable_windowed_mpo_odm;
sys/dev/pci/drm/amd/display/dc/dc.h
497
bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
sys/dev/pci/drm/amd/display/dc/dc.h
499
bool skip_riommu_prefetch_wa;
sys/dev/pci/drm/amd/display/dc/dc.h
500
bool clamp_min_dcfclk;
sys/dev/pci/drm/amd/display/dc/dc.h
503
bool is_asymmetric_memory;
sys/dev/pci/drm/amd/display/dc/dc.h
504
bool is_single_rank_dimm;
sys/dev/pci/drm/amd/display/dc/dc.h
505
bool is_vmin_only_asic;
sys/dev/pci/drm/amd/display/dc/dc.h
506
bool use_spl;
sys/dev/pci/drm/amd/display/dc/dc.h
507
bool prefer_easf;
sys/dev/pci/drm/amd/display/dc/dc.h
508
bool use_pipe_ctx_sync_logic;
sys/dev/pci/drm/amd/display/dc/dc.h
510
bool ignore_dpref_ss;
sys/dev/pci/drm/amd/display/dc/dc.h
511
bool enable_mipi_converter_optimization;
sys/dev/pci/drm/amd/display/dc/dc.h
512
bool use_default_clock_table;
sys/dev/pci/drm/amd/display/dc/dc.h
513
bool force_bios_enable_lttpr;
sys/dev/pci/drm/amd/display/dc/dc.h
516
bool dc_mode_clk_limit_support;
sys/dev/pci/drm/amd/display/dc/dc.h
517
bool EnableMinDispClkODM;
sys/dev/pci/drm/amd/display/dc/dc.h
518
bool enable_auto_dpm_test_logs;
sys/dev/pci/drm/amd/display/dc/dc.h
522
bool disable_ips_in_dpms_off;
sys/dev/pci/drm/amd/display/dc/dc.h
523
bool usb4_bw_alloc_support;
sys/dev/pci/drm/amd/display/dc/dc.h
524
bool allow_0_dtb_clk;
sys/dev/pci/drm/amd/display/dc/dc.h
525
bool use_assr_psp_message;
sys/dev/pci/drm/amd/display/dc/dc.h
526
bool support_edp0_on_dp1;
sys/dev/pci/drm/amd/display/dc/dc.h
528
bool disable_hbr_audio_dp2;
sys/dev/pci/drm/amd/display/dc/dc.h
529
bool consolidated_dpia_dp_lt;
sys/dev/pci/drm/amd/display/dc/dc.h
530
bool set_pipe_unlock_order;
sys/dev/pci/drm/amd/display/dc/dc.h
531
bool enable_dpia_pre_training;
sys/dev/pci/drm/amd/display/dc/dc.h
532
bool unify_link_enc_assignment;
sys/dev/pci/drm/amd/display/dc/dc.h
662
bool p_state_change_support;
sys/dev/pci/drm/amd/display/dc/dc.h
664
bool dtbclk_en;
sys/dev/pci/drm/amd/display/dc/dc.h
666
bool fclk_p_state_change_support;
sys/dev/pci/drm/amd/display/dc/dc.h
672
bool prev_p_state_change_support;
sys/dev/pci/drm/amd/display/dc/dc.h
673
bool fclk_prev_p_state_change_support;
sys/dev/pci/drm/amd/display/dc/dc.h
686
bool fw_based_mclk_switching;
sys/dev/pci/drm/amd/display/dc/dc.h
687
bool fw_based_mclk_switching_shut_down;
sys/dev/pci/drm/amd/display/dc/dc.h
710
bool enable;
sys/dev/pci/drm/amd/display/dc/dc.h
762
bool vga: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
763
bool i2c: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
764
bool dmcu: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
765
bool dscl: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
766
bool cm: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
767
bool mpc: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
768
bool optc: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
769
bool vpg: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
770
bool afmt: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
777
bool dpp: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
778
bool dsc: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
779
bool hdmistream: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
780
bool hdmichar: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
781
bool dpstream: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
782
bool symclk32_se: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
783
bool symclk32_le: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
784
bool symclk_fe: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
785
bool physymclk: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
786
bool dpiasymclk: 1;
sys/dev/pci/drm/amd/display/dc/dc.h
794
bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
sys/dev/pci/drm/amd/display/dc/dc.h
795
bool dchub : 1; /* Display controller hub */
sys/dev/pci/drm/amd/display/dc/dc.h
796
bool dchubbub : 1;
sys/dev/pci/drm/amd/display/dc/dc.h
797
bool dpp : 1; /* Display pipes and planes */
sys/dev/pci/drm/amd/display/dc/dc.h
798
bool opp : 1; /* Output pixel processing */
sys/dev/pci/drm/amd/display/dc/dc.h
799
bool optc : 1; /* Output pipe timing combiner */
sys/dev/pci/drm/amd/display/dc/dc.h
800
bool dio : 1; /* Display output */
sys/dev/pci/drm/amd/display/dc/dc.h
801
bool dwb : 1; /* Display writeback */
sys/dev/pci/drm/amd/display/dc/dc.h
802
bool mmhubbub : 1; /* Multimedia hub */
sys/dev/pci/drm/amd/display/dc/dc.h
803
bool dmu : 1; /* Display core management unit */
sys/dev/pci/drm/amd/display/dc/dc.h
804
bool az : 1; /* Azalia */
sys/dev/pci/drm/amd/display/dc/dc.h
805
bool dchvm : 1;
sys/dev/pci/drm/amd/display/dc/dc.h
806
bool dsc : 1; /* Display stream compression */
sys/dev/pci/drm/amd/display/dc/dc.h
839
bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc.h
840
bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
sys/dev/pci/drm/amd/display/dc/dc.h
896
bool base_addr_is_mc_addr;
sys/dev/pci/drm/amd/display/dc/dc.h
899
bool valid;
sys/dev/pci/drm/amd/display/dc/dc.h
900
bool is_hvm_enabled;
sys/dev/pci/drm/amd/display/dc/dc.h
943
bool native422_support;
sys/dev/pci/drm/amd/display/dc/dc.h
944
bool disable_dsc;
sys/dev/pci/drm/amd/display/dc/dc.h
948
bool sanity_checks;
sys/dev/pci/drm/amd/display/dc/dc.h
949
bool max_disp_clk;
sys/dev/pci/drm/amd/display/dc/dc.h
950
bool surface_trace;
sys/dev/pci/drm/amd/display/dc/dc.h
951
bool clock_trace;
sys/dev/pci/drm/amd/display/dc/dc.h
952
bool validation_trace;
sys/dev/pci/drm/amd/display/dc/dc.h
953
bool bandwidth_calcs_trace;
sys/dev/pci/drm/amd/display/dc/dc.h
957
bool disable_stutter;
sys/dev/pci/drm/amd/display/dc/dc.h
958
bool use_max_lb;
sys/dev/pci/drm/amd/display/dc/dc.h
966
bool force_single_disp_pipe_split;
sys/dev/pci/drm/amd/display/dc/dc.h
967
bool voltage_align_fclk;
sys/dev/pci/drm/amd/display/dc/dc.h
968
bool disable_min_fclk;
sys/dev/pci/drm/amd/display/dc/dc.h
970
bool hdcp_lc_force_fw_enable;
sys/dev/pci/drm/amd/display/dc/dc.h
971
bool hdcp_lc_enable_sw_fallback;
sys/dev/pci/drm/amd/display/dc/dc.h
973
bool disable_dfs_bypass;
sys/dev/pci/drm/amd/display/dc/dc.h
974
bool disable_dpp_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
975
bool disable_hubp_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
976
bool disable_dsc_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
977
bool disable_optc_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
978
bool disable_hpo_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
979
bool disable_io_clk_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
980
bool disable_mem_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
981
bool disable_dio_power_gate;
sys/dev/pci/drm/amd/display/dc/dc.h
984
bool disable_pplib_wm_range;
sys/dev/pci/drm/amd/display/dc/dc.h
999
bool optimized_watermark;
sys/dev/pci/drm/amd/display/dc/dc_bios_types.h
103
bool enable);
sys/dev/pci/drm/amd/display/dc/dc_bios_types.h
116
bool enable);
sys/dev/pci/drm/amd/display/dc/dc_bios_types.h
184
bool fw_info_valid;
sys/dev/pci/drm/amd/display/dc/dc_bios_types.h
84
bool (*is_accelerated_mode)(
sys/dev/pci/drm/amd/display/dc/dc_bios_types.h
88
bool state);
sys/dev/pci/drm/amd/display/dc/dc_bios_types.h
89
bool (*is_device_id_supported)(
sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h
107
bool write;
sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h
133
bool hw_supported;
sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h
83
bool i2c_over_aux;
sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h
86
bool write;
sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h
87
bool mot;
sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h
88
bool write_status_update;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1007
static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1141
bool dc_dmub_check_min_version(struct dmub_srv *srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1177
bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1222
static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
138
static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1522
bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1525
bool reallow_idle = false, should_detect = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1552
void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1602
bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1608
bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1612
bool result = false, reallow_idle = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1641
static bool dc_dmub_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1668
bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1672
bool result = false, reallow_idle = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1693
bool enable)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1759
bool enable)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
180
static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1806
bool enable)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1820
bool program_manual_trigger)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1940
bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1960
bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst, struct dmub_ips_residency_info *driver_info,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1988
bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
1994
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2013
bool dmub_lsdma_send_linear_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2024
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2046
bool dmub_lsdma_send_linear_sub_window_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2055
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2090
bool dmub_lsdma_send_tiled_to_tiled_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2099
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2141
bool dmub_lsdma_send_pio_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2153
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2176
bool dmub_lsdma_send_pio_constfill_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2187
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2209
bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
2215
bool result;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
239
bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
243
bool res = false;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
259
bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
298
bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
303
bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
311
bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
333
bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
343
bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
365
bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
371
void dc_dmub_trace_event_control(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
438
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
74
bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
872
bool enable)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
944
bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
103
bool dc_dmub_check_min_version(struct dmub_srv *srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
108
bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
110
void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
144
bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
158
bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
181
bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
193
bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
198
bool enable);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
205
bool program_manual_trigger);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
213
bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
214
bool dmub_lsdma_send_linear_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
249
bool dmub_lsdma_send_linear_sub_window_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
253
bool dmub_lsdma_send_pio_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
259
bool dmub_lsdma_send_pio_constfill_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
296
bool dmub_lsdma_send_tiled_to_tiled_copy_command(
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
299
bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
322
bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
324
bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
41
bool gather_in_progress;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
43
bool should_burst_write;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
57
bool idle_allowed;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
58
bool needs_idle_wake;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
61
bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
63
bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
65
bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
69
bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
73
bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
75
bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
77
bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
80
bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
82
bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
84
void dc_dmub_trace_event_control(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
89
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
97
bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h
99
void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1157
bool cable_id_written;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1197
bool supported;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1211
bool extendedCapValid;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1214
bool is_dp_hdmi_s3d_converter;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1215
bool is_dp_hdmi_ycbcr422_pass_through;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1216
bool is_dp_hdmi_ycbcr420_pass_through;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1217
bool is_dp_hdmi_ycbcr422_converter;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1218
bool is_dp_hdmi_ycbcr420_converter;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1238
bool is_dongle_type_one;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1240
bool is_branch_dev;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1243
bool is_mst_capable;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1259
bool allow_invalid_MSA_timing_param;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1260
bool panel_mode_edp;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1261
bool dpcd_display_control_capable;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1262
bool ext_receiver_cap_field_present;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1263
bool set_power_state_capable_edp;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1264
bool dynamic_backlight_capable_edp;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1276
bool panel_luminance_control;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1425
bool is_logged;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
1432
bool is_initialized;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
158
bool use_link_rate_set;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
163
bool should_enable_dp_tunneling;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
164
bool should_use_dp_bw_allocation;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
202
bool *alternate_scrambler_reset;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
203
bool *enhanced_framing;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
204
bool *mst_enable;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
205
bool *fec_enable;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
586
bool is_valid;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
906
bool psr_exit_link_training_required;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
909
bool su_granularity_required;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
910
bool y_coordinate_required;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
912
bool alpm_cap;
sys/dev/pci/drm/amd/display/dc/dc_dp_types.h
913
bool standby_support;
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
114
void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
116
void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable);
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
49
bool use_min_slices_h;
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
54
bool enable_dsc_when_not_needed;
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
62
bool force_dsc_when_not_needed;
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
65
bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
70
bool dc_dsc_compute_bandwidth_range(
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
80
bool dc_dsc_compute_config(
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
90
uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
sys/dev/pci/drm/amd/display/dc/dc_dsc.h
95
const bool is_dp);
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c
29
bool dc_edid_parser_send_cea(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c
50
bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset)
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.c
63
bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.h
31
bool dc_edid_parser_send_cea(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.h
37
bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset);
sys/dev/pci/drm/amd/display/dc/dc_edid_parser.h
39
bool dc_edid_parser_recv_amd_vsdb(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
10
static bool op_i2c_convert(
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
105
const bool over_aux = false;
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
109
const bool converted = op_i2c_convert(&commands[0], write, FUSED_REQUEST_WRITE, ddc_line, over_aux)
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
116
const bool result = atomic_write_poll_read(link, commands, poll_timeout_us, poll_mask_msb);
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
122
bool dm_atomic_write_poll_read_aux(
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
136
const bool converted = op_aux_convert(&commands[0], write, FUSED_REQUEST_WRITE, ddc_line)
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
143
const bool result = atomic_write_poll_read(link, commands, poll_timeout_us, poll_mask_msb);
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
15
bool over_aux
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
36
static bool op_aux_convert(
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
59
static bool atomic_write_poll_read(
sys/dev/pci/drm/amd/display/dc/dc_fused_io.c
93
bool dm_atomic_write_poll_read_i2c(
sys/dev/pci/drm/amd/display/dc/dc_fused_io.h
12
bool dm_atomic_write_poll_read_i2c(
sys/dev/pci/drm/amd/display/dc/dc_fused_io.h
21
bool dm_atomic_write_poll_read_aux(
sys/dev/pci/drm/amd/display/dc/dc_helper.c
143
static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,
sys/dev/pci/drm/amd/display/dc/dc_helper.c
759
bool dc_supports_vrr(const enum dce_version v)
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
1009
bool enabled;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
154
bool enable;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
157
bool independent_64b_blks;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
161
bool independent_64b_blks_c;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
252
bool flip_immediate;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
254
bool triplebuffer_flips;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
428
bool shaderEnable;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
430
bool meta_linear;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
431
bool rb_aligned;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
432
bool pipe_aligned;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
487
bool enable;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
493
bool translate_by_source;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
504
bool mirror;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
527
bool enable_adjustment;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
553
bool is_identity;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
716
bool integer_scaling;
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
864
bool block_pred_enable; /* DSC block prediction enable */
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
867
bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
869
bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
sys/dev/pci/drm/amd/display/dc/dc_hw_types.h
870
bool is_dp; /* indicate if DSC is applied based on DP's capability */
sys/dev/pci/drm/amd/display/dc/dc_plane.h
46
bool clear_tiling);
sys/dev/pci/drm/amd/display/dc/dc_state.h
50
bool dc_state_add_plane(
sys/dev/pci/drm/amd/display/dc/dc_state.h
56
bool dc_state_remove_plane(
sys/dev/pci/drm/amd/display/dc/dc_state.h
62
bool dc_state_rem_all_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/dc_state.h
67
bool dc_state_add_all_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
104
bool dc_state_is_fams2_in_use(
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
111
bool limit);
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
113
bool dc_state_get_stream_subvp_cursor_limit(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
118
bool limit);
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
120
bool dc_state_get_stream_cursor_subvp_limit(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
123
bool dc_state_can_clear_stream_cursor_subvp_limit(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
126
bool dc_state_is_subvp_in_use(struct dc_state *state);
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
71
bool dc_state_add_phantom_plane(
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
77
bool dc_state_remove_phantom_plane(
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
83
bool dc_state_rem_all_phantom_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
87
bool should_release_planes);
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
89
bool dc_state_add_all_phantom_planes_for_stream(
sys/dev/pci/drm/amd/display/dc/dc_state_priv.h
96
bool dc_state_remove_phantom_streams_and_planes(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
130
bool is_increase; // is bandwidth reduced or increased
sys/dev/pci/drm/amd/display/dc/dc_stream.h
177
bool is_valid;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
215
bool use_dynamic_meta;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
227
bool use_vsc_sdp_for_colorimetry;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
228
bool ignore_msa_timing_param;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
235
bool allow_freesync;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
242
bool vrr_active_variable;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
243
bool freesync_on_desktop;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
244
bool vrr_active_fixed;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
246
bool converter_disable_audio;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
268
bool dpms_off;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
274
bool hw_cursor_req;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
289
bool mode_changed : 1;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
302
bool apply_edp_fast_boot_optimization;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
303
bool apply_seamless_boot_optimization;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
311
bool has_non_synchronizable_pclk;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
312
bool vblank_synchronized;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
313
bool is_phantom;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
316
bool scaler_sharpener_update;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
317
bool sharpening_required;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
341
bool *dpms_off;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
342
bool integer_scaling_update;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
343
bool *allow_freesync;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
344
bool *vrr_active_variable;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
345
bool *vrr_active_fixed;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
364
bool *hw_cursor_req;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
365
bool *scaler_sharpener_update;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
366
bool *sharpening_required;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
369
bool dc_is_stream_unchanged(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
371
bool dc_is_stream_scaling_unchanged(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
38
bool master;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
388
bool dc_update_planes_and_stream(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
425
bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
433
bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
439
bool dc_stream_add_writeback(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
443
bool dc_stream_fc_disable_writeback(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
447
bool dc_stream_remove_writeback(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
455
bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
457
bool dc_stream_set_dynamic_metadata(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
47
bool subvp_limit_cursor_size; /* stream has/is using subvp limiting hw cursor support */
sys/dev/pci/drm/amd/display/dc/dc_stream.h
48
bool cursor_size_limit_subvp; /* stream is using hw cursor config preventing subvp */
sys/dev/pci/drm/amd/display/dc/dc_stream.h
511
bool dc_stream_check_cursor_attributes(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
516
bool dc_stream_set_cursor_attributes(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
520
bool dc_stream_program_cursor_attributes(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
524
bool dc_stream_set_cursor_position(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
528
bool dc_stream_program_cursor_position(
sys/dev/pci/drm/amd/display/dc/dc_stream.h
533
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
537
bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
542
bool dc_stream_forward_crc_window(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
545
bool is_stop);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
547
bool dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
550
bool stop);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
553
bool dc_stream_configure_crc(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
556
bool enable,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
557
bool continuous,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
559
bool reset);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
561
bool dc_stream_get_crc(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
579
bool dc_stream_set_gamut_remap(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
582
bool dc_stream_program_csc_matrix(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dc_stream.h
588
bool allocate_one);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
604
bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
605
bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/dc_stream.h
62
bool is_abm_supported;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
64
bool fpo_in_use;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
78
bool dmdata_repeat;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
82
bool dmdata_updated;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
86
bool dmdata_qos_mode;
sys/dev/pci/drm/amd/display/dc/dc_stream.h
98
bool wb_enabled;
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
31
bool dc_stream_construct(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
43
bool is_gaming);
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
51
bool is_gaming);
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
56
bool dc_stream_is_refresh_rate_range_flickerless(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
59
bool is_gaming);
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
66
bool is_gaming);
sys/dev/pci/drm/amd/display/dc/dc_stream_priv.h
73
bool is_gaming);
sys/dev/pci/drm/amd/display/dc/dc_types.h
1039
bool psr_feature_enabled; // PSR is supported by sink
sys/dev/pci/drm/amd/display/dc/dc_types.h
1040
bool psr_allow_active; // PSR is currently active
sys/dev/pci/drm/amd/display/dc/dc_types.h
1042
bool psr_vtotal_control_support; // Vtotal control is supported by sink
sys/dev/pci/drm/amd/display/dc/dc_types.h
1050
bool psr_frame_capture_indication_req;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1125
bool replay_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1127
bool replay_cap_support;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1131
bool replay_smu_opt_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1137
bool replay_timing_sync_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1139
bool force_disable_desync_error_check;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1141
bool received_desync_error_hpd;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1143
bool replay_support_fast_resync_in_ultra_sleep_mode;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1149
bool low_rr_activated;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1151
bool low_rr_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1153
bool replay_video_conferencing_optimization_enabled;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1157
bool os_request_force_ffu;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1165
bool replay_feature_enabled;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1167
bool replay_allow_active;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1169
bool replay_allow_long_vblank;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1173
bool replay_smu_opt_enable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1214
bool disable_psr;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1215
bool disallow_psrsu;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1216
bool disallow_replay;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1217
bool rc_disable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1218
bool rc_allow_static_screen;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1219
bool rc_allow_fullscreen_VPB;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1220
bool read_psrcap_again;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1231
bool disable_dsc_edp;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1236
bool optimize_edp_link_rate; /* eDP ILR */
sys/dev/pci/drm/amd/display/dc/dc_types.h
1253
bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM
sys/dev/pci/drm/amd/display/dc/dc_types.h
1319
bool lut1d_enable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1333
bool rmcm_3dlut_shaper_select;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1334
bool mpc_3dlut_enable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1335
bool rmcm_3dlut_enable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
1336
bool mpc_mcm_post_blend;
sys/dev/pci/drm/amd/display/dc/dc_types.h
183
bool oled_optimize_display_on;
sys/dev/pci/drm/amd/display/dc/dc_types.h
210
bool lte_340mcsc_scramble;
sys/dev/pci/drm/amd/display/dc/dc_types.h
212
bool edid_hdmi;
sys/dev/pci/drm/amd/display/dc/dc_types.h
213
bool hdr_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
214
bool rr_capable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
292
bool supported ;
sys/dev/pci/drm/amd/display/dc/dc_types.h
293
bool allTimings ;
sys/dev/pci/drm/amd/display/dc/dc_types.h
294
bool cloneMode ;
sys/dev/pci/drm/amd/display/dc/dc_types.h
295
bool scaling ;
sys/dev/pci/drm/amd/display/dc/dc_types.h
296
bool singleFrameSWPacked;
sys/dev/pci/drm/amd/display/dc/dc_types.h
398
bool stereo_enabled; /* false: normal mode, true: 3D stereo */
sys/dev/pci/drm/amd/display/dc/dc_types.h
400
bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
sys/dev/pci/drm/amd/display/dc/dc_types.h
408
bool crop_en; /* window cropping enable in cnv */
sys/dev/pci/drm/amd/display/dc/dc_types.h
549
bool valid;
sys/dev/pci/drm/amd/display/dc/dc_types.h
558
bool valid;
sys/dev/pci/drm/amd/display/dc/dc_types.h
619
bool psr_exit_link_training_required;
sys/dev/pci/drm/amd/display/dc/dc_types.h
620
bool psr_frame_capture_indication_req;
sys/dev/pci/drm/amd/display/dc/dc_types.h
622
bool allow_smu_optimizations;
sys/dev/pci/drm/amd/display/dc/dc_types.h
623
bool allow_multi_disp_optimizations;
sys/dev/pci/drm/amd/display/dc/dc_types.h
625
bool su_granularity_required;
sys/dev/pci/drm/amd/display/dc/dc_types.h
631
bool os_request_force_ffu;
sys/dev/pci/drm/amd/display/dc/dc_types.h
696
bool psrSupportedDisplayConfig;
sys/dev/pci/drm/amd/display/dc/dc_types.h
698
bool psrExitLinkTrainingRequired;
sys/dev/pci/drm/amd/display/dc/dc_types.h
705
bool psrFrameCaptureIndicationReq;
sys/dev/pci/drm/amd/display/dc/dc_types.h
720
bool rfb_update_auto_en;
sys/dev/pci/drm/amd/display/dc/dc_types.h
735
bool allow_smu_optimizations;
sys/dev/pci/drm/amd/display/dc/dc_types.h
736
bool allow_multi_disp_optimizations;
sys/dev/pci/drm/amd/display/dc/dc_types.h
738
bool su_granularity_required;
sys/dev/pci/drm/amd/display/dc/dc_types.h
744
bool os_request_force_ffu;
sys/dev/pci/drm/amd/display/dc/dc_types.h
749
bool enable_remap;
sys/dev/pci/drm/amd/display/dc/dc_types.h
811
bool created_bios;
sys/dev/pci/drm/amd/display/dc/dc_types.h
873
bool is_dsc_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
879
bool is_block_pred_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
892
bool is_dp; /* Decoded format */
sys/dev/pci/drm/amd/display/dc/dc_types.h
896
bool expansion_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
897
bool reduction_supported;
sys/dev/pci/drm/amd/display/dc/dc_types.h
898
bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/
sys/dev/pci/drm/amd/display/dc/dc_types.h
899
bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/
sys/dev/pci/drm/amd/display/dc/dc_types.h
969
bool enable;
sys/dev/pci/drm/amd/display/dc/dc_types.h
984
bool link_active;
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
100
bool en)
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
447
bool en);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
330
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
446
bool force_enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
191
bool enable);
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
197
bool force_enable);
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
332
bool clock_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
137
static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1493
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1535
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1575
bool force_enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1663
bool clock_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
170
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1794
void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
209
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2127
bool power_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2184
bool power_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2227
bool power_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2244
bool force_enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2256
bool power_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2270
bool power_on)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
236
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
273
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
320
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
366
static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
393
static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
426
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
463
bool enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
243
void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
271
bool force_enable)
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
596
bool enable = false;
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
247
bool force_enable);
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
199
static bool dce_abm_set_level(struct abm *abm, uint32_t level)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
220
static bool dce_abm_immediate_disable(struct abm *abm, uint32_t panel_inst)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
230
static bool dce_abm_set_backlight_level_pwm(
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
58
static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1244
static bool dce_aud_endpoint_valid(struct audio *audio)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
131
bool limit_freq_to_48_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
132
bool limit_freq_to_88_2_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
133
bool limit_freq_to_96_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
134
bool limit_freq_to_174_4_khz = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
306
bool is_mst)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
327
bool is_mst)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
554
bool capable)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
678
bool is_ac3_supported = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
86
static bool is_audio_format_supported(
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
93
bool found = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
107
static bool acquire_engine(
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
191
bool is_write =
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
398
static bool acquire(
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
514
bool is_ext_aux_timeout_configurable)
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
695
bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
700
bool payload_reply = true;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
702
bool retry_on_defer = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
94
static bool is_engine_available(
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h
249
bool acquire_reset;
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h
295
bool is_ext_aux_timeout_configurable);
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h
299
bool dce110_aux_engine_acquire(
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h
310
bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
674
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
701
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
728
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
755
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1067
static bool dcn401_program_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1169
static bool dce110_clock_source_power_down(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1192
static bool get_pixel_clk_frequency_100hz(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1281
static bool dcn20_program_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1304
static bool dcn20_override_dp_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1327
static bool dcn3_program_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
136
static bool calculate_fb_and_fractional_fb_divider(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1591
static bool calc_pll_max_vco_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1668
bool dce110_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1768
bool dce112_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1796
bool dcn20_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1805
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1812
bool dcn3_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1821
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1828
bool dcn31_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1837
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1844
bool dcn401_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1853
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1859
bool dcn301_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1868
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
195
static bool calc_fb_divider_checking_tolerance(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
251
static bool calc_pll_dividers_in_range(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
396
static bool pll_adjust_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
633
static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
649
static bool calculate_ss(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
714
static bool enable_spread_spectrum(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
802
bool enable_ycbcr420)
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
844
static bool dce110_program_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
918
static bool dce112_program_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
965
static bool dcn31_program_pix_clk(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
256
bool dce110_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
265
bool dce112_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
274
bool dcn20_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
283
bool dcn3_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
292
bool dcn301_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
301
bool dcn31_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
310
bool dcn401_clk_src_construct(
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
129
static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
168
static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
280
static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
379
static bool dcn10_dmcu_init(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
383
bool status = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
462
static bool dcn21_dmcu_init(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
474
static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
546
static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
599
static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
72
static bool dce_dmcu_init(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
758
static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
768
static bool dcn20_lock_phy(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
78
static bool dce_dmcu_load_iram(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
791
static bool dcn20_unlock_phy(struct dmcu *dmcu)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
814
static bool dcn10_send_edid_cea(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
855
static bool dcn10_get_scp_results(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
878
static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
906
static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
28
bool dce_i2c_oem_device_present(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.c
54
bool dce_i2c_submit_command(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.h
33
bool dce_i2c_oem_device_present(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c.h
39
bool dce_i2c_submit_command(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
128
static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
144
static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
158
static bool process_transaction(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
165
bool last_transaction = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
295
static bool acquire_engine(struct dce_i2c_hw *dce_i2c_hw)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
318
static bool setup_engine(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
408
bool safe_to_reset;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
560
static bool dce_i2c_hw_engine_submit_payload(struct dce_i2c_hw *dce_i2c_hw,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
562
bool middle_of_transaction,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
572
bool result = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
628
bool dce_i2c_submit_command_hw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
635
bool result;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
642
bool mot = (index_of_payload != cmd->number_of_payloads - 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h
345
bool dce_i2c_submit_command_hw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
102
bool ack;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
152
static bool read_byte_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
157
bool more)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
212
static bool stop_sync_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
249
static bool i2c_write_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
271
static bool i2c_read_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
296
static bool start_sync_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
354
static bool dce_i2c_sw_engine_acquire_engine(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
371
bool dce_i2c_engine_acquire_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
376
bool result;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
39
static inline bool read_bit_from_ddc(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
404
bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
41
bool data_nor_clock)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
439
static bool dce_i2c_sw_engine_submit_payload(struct dce_i2c_sw *engine,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
441
bool middle_of_transaction)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
466
bool dce_i2c_submit_command_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
473
bool result;
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
480
bool mot = (index_of_payload != cmd->number_of_payloads - 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
55
bool data_nor_clock,
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
56
bool bit)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
74
static bool wait_for_scl_high_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c
95
static bool write_byte_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.h
46
bool dce_i2c_submit_command_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.h
52
bool dce_i2c_engine_acquire_sw(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
136
bool enable)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
147
bool disable)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
1623
bool connect)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
226
bool complete)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
647
bool exit_link_training_required)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
680
bool dce110_is_dig_enabled(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
711
bool dce110_link_encoder_validate_dvi_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
762
static bool dce110_link_encoder_validate_hdmi_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
797
bool dce110_link_encoder_validate_dp_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
915
bool dce110_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
920
bool is_valid;
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
212
bool dce110_link_encoder_validate_dvi_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
218
bool dce110_link_encoder_validate_rgb_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
222
bool dce110_link_encoder_validate_dp_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
226
bool dce110_link_encoder_validate_wireless_output(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
230
bool dce110_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
297
bool connect);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
310
bool exit_link_training_required);
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h
315
bool dce110_is_dig_enabled(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
122
static bool is_vert_scan(enum dc_rotation_angle rotation)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
657
bool horizontal_mirror)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
677
bool horizontal_mirror)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
843
static bool dce_mi_is_flip_pending(struct mem_input *mem_input)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
856
static bool dce_mi_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
859
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
147
static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
161
static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1014
bool enable)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1377
bool enable)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1438
bool mute)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1488
int tg_inst, bool enable)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
271
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
536
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
652
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
713
struct stream_encoder *enc, bool mute);
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1146
static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chroma)
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
116
static bool setup_scaling_configuration(
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1168
bool dce_transform_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1275
static bool configure_graphics_mode(
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
150
static bool dce60_setup_scaling_configuration(
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
1577
bool power_on)
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
416
bool is_scaling_required;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
417
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
498
bool is_scaling_required;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
733
bool dither_enable,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
736
bool frame_random_enable,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
737
bool rgb_random_enable,
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
738
bool highpass_random_enable)
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
800
bool spatial_dither_enable;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
860
bool spatial_dither_enable;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h
655
bool prescaler_on;
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h
674
bool dce_transform_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h
690
bool power_on);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
100
static bool dmub_abm_init_config_ex(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
115
static bool dmub_abm_set_pause_ex(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst)
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
117
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
137
static bool dmub_abm_save_restore_ex(
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
142
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
154
static bool dmub_abm_set_pipe_ex(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
160
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
171
static bool dmub_abm_set_backlight_level_pwm_ex(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
177
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
81
static bool dmub_abm_set_level_ex(struct abm *abm, uint32_t level)
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c
83
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
141
bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask)
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
189
bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst)
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
219
bool dmub_abm_save_restore(
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
254
bool dmub_abm_set_pipe(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
279
bool dmub_abm_set_backlight_level(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
301
bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned int scaling_strength_map,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h
34
bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h
42
bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h
43
bool dmub_abm_save_restore(
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h
47
bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst);
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h
48
bool dmub_abm_set_backlight_level(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h
52
bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned int scaling_strength_map,
sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
32
bool lock,
sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
64
bool should_use_dmub_lock(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
33
bool lock,
sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
40
bool should_use_dmub_lock(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
140
static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
179
static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
292
static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.h
40
bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.h
42
void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait,
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
115
static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
238
uint32_t *residency, const bool is_start, enum pr_residency_mode mode)
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
47
static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst)
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h
21
void (*replay_enable)(struct dmub_replay *dmub, bool enable, bool wait,
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h
23
bool (*replay_copy_settings)(struct dmub_replay *dmub, struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h
32
uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
112
bool enabled)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
265
bool dce110_compressor_is_fbc_enabled_in_hw(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.h
65
bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.h
76
bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
41
bool immediate)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
471
static bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
486
static bool dce_mem_input_v_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
489
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
528
bool chroma)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
643
bool horizotal_mirror)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
115
bool use_set_a = (get_reg_field_value(cntl_value,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
358
static bool configure_graphics_mode_v(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c
537
bool use_set_a;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
35
bool power_on, bool inputgamma, bool regamma)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
519
bool power_on)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1113
bool dce110_timing_generator_validate_timing(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
123
bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1395
bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1411
bool enable,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1473
bool lock)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1774
bool dce110_timing_generator_did_triggered_reset_occur(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1782
bool force = get_reg_field_value(value,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1785
bool vert_sync = get_reg_field_value(value1,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1960
bool use_vbios)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1968
bool dce110_tg_is_blanked(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
1986
bool enable_blanking)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2013
bool dce110_tg_validate_timing(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2031
bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2066
bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2102
static bool dce110_is_tg_enabled(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2116
bool dce110_configure_crc(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2254
bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
232
bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
280
bool dce110_timing_generator_program_timing_generator(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
91
static bool dce110_timing_generator_is_in_vertical_blank(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
127
bool dce110_timing_generator_validate_timing(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
135
bool dce110_timing_generator_program_timing_generator(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
140
bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
141
bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
158
bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
193
bool dce110_timing_generator_did_triggered_reset_occur(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
246
bool enable,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
250
bool lock);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
266
bool use_vbios);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
268
bool dce110_tg_is_blanked(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
271
bool enable_blanking);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
273
bool dce110_tg_validate_timing(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
283
bool dce110_arm_vert_intr(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
286
bool dce110_configure_crc(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
289
bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
292
bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
139
static bool dce110_timing_generator_v_is_in_vertical_blank(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
152
static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
385
bool enable,
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
427
bool enable_blanking)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
443
bool use_vbios)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
53
static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
613
static bool dce110_timing_generator_v_did_triggered_reset_occur(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
80
static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
157
static bool setup_scaling_configuration(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
161
bool is_scaling_needed = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
503
static bool dce110_xfmv_power_up_line_buffer(struct transform *xfm)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
526
bool is_scaling_required = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
527
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c
698
bool dce110_transform_v_construct(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.h
33
bool dce110_transform_v_construct(
sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.h
52
bool power_on);
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
268
static bool is_source_bigger_than_epanel_size(
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
292
bool enabled)
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
439
bool dce112_compressor_is_fbc_enabled_in_hw(
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
467
bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h
65
bool dce112_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h
76
bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
101
static bool dce120_timing_generator_validate_timing(
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1055
static bool dce120_arm_vert_intr(
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1081
static bool dce120_is_tg_enabled(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1094
static bool dce120_configure_crc(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1174
static bool dce120_get_crc(struct timing_generator *tg, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
128
static bool dce120_tg_validate_timing(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
136
static bool dce120_timing_generator_enable_crtc(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
370
static bool dce120_timing_generator_did_triggered_reset_occur(
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
623
bool enable,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
702
bool use_vbios)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
710
static bool dce120_tg_is_blanked(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
732
bool enable_blanking)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
747
bool dce120_tg_validate_timing(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
85
static bool dce120_timing_generator_is_in_vertical_blank(
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
116
bool use_vbios)
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
126
bool enable,
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
179
static bool dce60_is_tg_enabled(struct timing_generator *tg)
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
193
static bool dce60_configure_crc(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c
116
bool use_vbios)
sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c
126
bool enable,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
148
bool cm_helper_convert_to_custom_float(
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
152
bool fixpoint)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
334
bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
336
struct pwl_params *lut_params, bool fixpoint)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
540
bool cm_helper_translate_curve_to_degamma_hw_format(
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
102
bool cm_helper_convert_to_custom_float(
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
106
bool fixpoint);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
108
bool cm_helper_translate_curve_to_hw_format(
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
111
struct pwl_params *lut_params, bool fixpoint);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
113
bool cm_helper_translate_curve_to_degamma_hw_format(
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
45
static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
64
static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
81
static bool dwb1_disable(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
110
static unsigned int dcn10_get_hubp_states(struct dc *dc, char *pBuf, unsigned int bufSize, bool invarOnly)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
135
bool dwb2_disable(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
158
static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
198
bool dwb2_is_enabled(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
227
bool is_new_content)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
306
bool coef_ram_current = get_reg_field_value_ex(
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
50
static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
99
static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
402
bool dwb2_disable(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
404
bool dwb2_is_enabled(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
410
bool is_new_content);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
417
bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
423
bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
722
bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
800
bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
68
static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
45
bool enable,
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
46
bool rate_2x_mode,
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h
63
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
169
static bool update_cfg_data(
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
205
static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
148
bool mute)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h
117
bool mute);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h
155
bool mute);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
111
bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
113
struct pwl_params *lut_params, bool fixpoint)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
304
bool cm3_helper_convert_to_custom_float(
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
308
bool fixpoint)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
462
bool is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
465
bool ret = true;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c
50
bool immediate_update)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h
147
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
158
static bool dcn301_is_panel_backlight_on(struct panel_cntl *panel_cntl)
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
168
static bool dcn301_is_panel_powered_on(struct panel_cntl *panel_cntl)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
124
static bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
134
static bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
41
static bool dcn31_query_backlight_info(struct panel_cntl *panel_cntl, union dmub_rb_cmd *cmd)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
107
bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
118
bool disable)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1347
bool connect)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
197
bool complete)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
499
bool exit_link_training_required)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
532
bool dcn10_is_dig_enabled(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
563
bool dcn10_link_encoder_validate_dvi_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
614
static bool dcn10_link_encoder_validate_hdmi_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
655
bool dcn10_link_encoder_validate_dp_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
781
bool dcn10_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
786
bool is_valid;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
542
bool dcn10_link_encoder_validate_dvi_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
548
bool dcn10_link_encoder_validate_rgb_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
552
bool dcn10_link_encoder_validate_dp_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
556
bool dcn10_link_encoder_validate_wireless_output(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
560
bool dcn10_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
632
bool connect);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
643
bool exit_link_training_required);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
648
bool dcn10_is_dig_enabled(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1033
bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1367
bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1429
bool mute)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1482
int tg_inst, bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1509
bool enc1_stream_encoder_dp_get_pixel_format(
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
249
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
484
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
603
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
646
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
653
bool enable_audio);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
658
bool is_dual_link);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
687
int tg_inst, bool enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
691
bool enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
695
bool mute);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
730
bool enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
744
bool enc1_stream_encoder_dp_get_pixel_format(
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
173
void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
181
void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
188
bool enc2_fec_is_active(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
211
static bool update_cfg_data(
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
285
bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
289
bool is_usb_c_alt_mode = false;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
256
bool mpllb_word_div2_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
257
bool mpllb_ssc_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
258
bool mpllb_div5_clk_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
259
bool mpllb_div_clk_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
260
bool mpllb_fracn_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
261
bool mpllb_pmix_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
276
bool hdmimode_enable;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
277
bool sup_pre_hp;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
278
bool dp_tx0_vergdrv_byp;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
279
bool dp_tx1_vergdrv_byp;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
280
bool dp_tx2_vergdrv_byp;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
281
bool dp_tx3_vergdrv_byp;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
288
bool program_fuse;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
289
bool bypass_sram;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
290
bool lane_en[4];
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
291
bool use_calibration_setting;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
293
bool load_sram_fw;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
296
bool hdmimode_enable;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
297
bool silver2;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
298
bool ext_refclk_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
324
bool data_swap_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
325
bool data_order_invert_en;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
328
bool rdpcs_reg_fifo_error_mask;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
329
bool rdpcs_tx_fifo_error_mask;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
330
bool rdpcs_dpalt_disable_mask;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
331
bool rdpcs_dpalt_4lane_mask;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
340
void enc2_fec_set_enable(struct link_encoder *enc, bool enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
341
void enc2_fec_set_ready(struct link_encoder *enc, bool ready);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
342
bool enc2_fec_is_active(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h
352
bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
215
bool immediate_update)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
297
bool enable,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
299
bool immediate_update)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
378
bool enable_dme,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
459
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
461
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
555
bool odm_combine)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
566
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h
103
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h
112
bool enable_dme,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
51
bool dcn30_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h
82
bool dcn30_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
320
bool enable,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
322
bool immediate_update)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
520
bool odm_combine)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
531
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
578
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
712
bool mute)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
305
bool mute);
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
323
bool enable,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
325
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
103
static bool has_query_dp_alt(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
116
static bool query_dp_alt_from_dmub(struct link_encoder *enc,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
423
static bool link_dpia_control(struct dc_context *dc_ctx,
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
592
bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h
282
bool dcn31_link_encoder_is_in_alt_mode(
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
108
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
149
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
277
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
279
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
52
void enc314_reset_fifo(struct stream_encoder *enc, bool reset)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
86
static bool enc314_is_fifo_enabled(struct stream_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
97
bool odm_combine)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
293
bool mute);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
311
bool enable,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
313
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
318
bool is_dual_link);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
324
bool enable_audio);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
335
void enc314_reset_fifo(struct stream_encoder *enc, bool reset);
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
347
bool odm_combine);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
153
static bool query_dp_alt_from_dmub(struct link_encoder *enc,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
171
bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.h
48
bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
107
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
235
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
237
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
394
static void enc32_reset_fifo(struct stream_encoder *enc, bool reset)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
55
bool two_pixel_per_cyle)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
66
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
126
void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
273
static bool link_dpia_control(struct dc_context *dc_ctx,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
56
bool dcn35_is_dig_enabled(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
141
void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enabled);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h
142
bool dcn35_is_dig_enabled(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
235
bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
267
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
269
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
379
static void enc35_reset_fifo(struct stream_encoder *enc, bool reset)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
394
static bool enc35_is_fifo_enabled(struct stream_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
54
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
94
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
303
bool mute);
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
321
bool enable,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
323
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
157
bool dcn401_is_dig_enabled(struct link_encoder *enc)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h
131
bool dcn401_is_dig_enabled(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
107
bool enable_audio)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
254
static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
256
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
400
bool enable)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
441
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
58
bool odm_combine)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
66
bool is_dual_link)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
796
bool enable_dme,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
205
bool enable_dme,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
215
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
220
bool is_dual_link);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
228
bool enable);
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
239
bool enable_audio);
sys/dev/pci/drm/amd/display/dc/dm_cp_psp.h
47
bool dpms_off;
sys/dev/pci/drm/amd/display/dc/dm_cp_psp.h
51
bool (*enable_assr)(void *handle, struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
118
bool dm_helpers_dp_mst_start_top_mgr(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
121
bool boot);
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
123
bool dm_helpers_dp_mst_stop_top_mgr(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
134
bool dm_helpers_dp_read_dpcd(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
144
bool dm_helpers_dp_write_dpcd(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
151
bool dm_helpers_submit_i2c(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
156
bool dm_helpers_execute_fused_io(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
164
bool dm_helpers_dp_write_dsc_enable(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
167
bool enable
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
170
bool dm_helpers_dp_write_hblank_reduction(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
174
bool dm_helpers_is_dp_sink_present(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
184
bool dm_helpers_dp_handle_test_pattern_request(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
194
void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
198
bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
226
bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
227
bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
78
bool dm_helpers_dp_mst_write_payload_allocation_table(
sys/dev/pci/drm/amd/display/dc/dm_helpers.h
82
bool enable);
sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h
242
bool pstate_handshake_supported);
sys/dev/pci/drm/amd/display/dc/dm_services.h
190
bool dm_pp_get_clock_levels_by_type(
sys/dev/pci/drm/amd/display/dc/dm_services.h
195
bool dm_pp_get_clock_levels_by_type_with_latency(
sys/dev/pci/drm/amd/display/dc/dm_services.h
200
bool dm_pp_get_clock_levels_by_type_with_voltage(
sys/dev/pci/drm/amd/display/dc/dm_services.h
205
bool dm_pp_notify_wm_clock_changes(
sys/dev/pci/drm/amd/display/dc/dm_services.h
223
bool dm_pp_apply_display_requirements(
sys/dev/pci/drm/amd/display/dc/dm_services.h
227
bool dm_pp_apply_power_level_change_request(
sys/dev/pci/drm/amd/display/dc/dm_services.h
231
bool dm_pp_apply_clock_for_voltage_request(
sys/dev/pci/drm/amd/display/dc/dm_services.h
235
bool dm_pp_get_static_clocks(
sys/dev/pci/drm/amd/display/dc/dm_services.h
242
bool save_per_link;
sys/dev/pci/drm/amd/display/dc/dm_services.h
243
bool save_per_edid;
sys/dev/pci/drm/amd/display/dc/dm_services.h
246
bool dm_query_extended_brightness_caps
sys/dev/pci/drm/amd/display/dc/dm_services.h
250
bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
sys/dev/pci/drm/amd/display/dc/dm_services.h
281
void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx);
sys/dev/pci/drm/amd/display/dc/dm_services.h
291
bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);
sys/dev/pci/drm/amd/display/dc/dm_services.h
292
bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);
sys/dev/pci/drm/amd/display/dc/dm_services.h
315
bool dc_supports_vrr(const enum dce_version v);
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
185
bool nb_pstate_switch_disable;/* controls NB PState switch */
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
186
bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
187
bool cpu_pstate_disable;
sys/dev/pci/drm/amd/display/dc/dm_services_types.h
201
bool all_displays_in_sync;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
638
static bool dcn_bw_apply_registry_override(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
640
bool updated = false;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
739
static unsigned int get_highest_allowed_voltage_level(bool is_vmin_only_asic)
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
748
bool dcn_validate_bandwidth(
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
763
bool bw_limit_pass;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1045
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1085
bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1086
bool is_pwrseq0 = (link && link->link_index == 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1087
bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1089
bool is_replay = link && link->replay_settings.replay_feature_enabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1225
bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1320
bool synchronized_vblank = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1957
bool duplicate = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2028
static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2031
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2078
bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2081
bool voltage_supported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2082
bool full_pstate_supported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2083
bool dummy_pstate_supported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2144
bool is_validating_bw)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2319
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2322
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
64
bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
73
bool is_validating_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
79
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
102
bool XFCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
104
bool InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
105
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
126
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
127
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1329
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
134
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
144
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
153
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
180
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
183
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
201
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2050
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2051
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2052
bool prefetch_vm_bw_valid = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2053
bool prefetch_row_bw_valid = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
212
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
219
bool *ImmediateFlipSupportedForPipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
248
bool DCCEnabledAnyPlane,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2687
bool FirstMainPlane = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2731
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3036
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3039
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3085
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3096
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3103
bool *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3190
bool DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
439
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
447
bool ScalerEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
46
bool DCCEnabledAnyPlane,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
462
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
463
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
466
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
485
bool XFCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
487
bool InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
488
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
504
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
56
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
64
bool ScalerEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
79
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
80
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
813
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
814
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
83
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
858
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
868
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
877
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
104
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
105
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
108
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
127
bool XFCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
129
bool InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
130
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1389
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
150
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
151
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
158
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
168
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
177
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
204
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
207
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2086
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2087
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2088
bool prefetch_vm_bw_valid = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2089
bool prefetch_row_bw_valid = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
225
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
236
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
243
bool *ImmediateFlipSupportedForPipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
272
bool DCCEnabledAnyPlane,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2760
bool FirstMainPlane = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2804
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3109
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3112
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3158
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3169
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3176
bool *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3264
bool DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
463
static bool CalculateDelayAfterScaler(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
47
bool DCCEnabledAnyPlane,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
476
bool ScalerEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
492
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
493
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
541
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
554
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
555
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
558
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
56
static bool CalculateDelayAfterScaler(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
577
bool XFCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
579
bool InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
580
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
595
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
69
bool ScalerEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
85
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
86
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
873
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
874
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
91
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
918
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
928
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
937
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
108
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
110
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
121
bool odm_combine,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1535
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1536
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1537
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1538
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1539
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
243
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
244
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
245
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
246
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
345
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
346
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
413
bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
54
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
55
const bool pstate_en);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
682
bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
784
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
785
const bool pstate_en)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
79
static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
809
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
819
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
833
bool scl_enable;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
67
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
68
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
69
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
70
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
71
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
108
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
110
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
121
bool odm_combine,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1536
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1537
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1538
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1539
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1540
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
243
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
244
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
245
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
246
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
345
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
346
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
413
bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
54
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
55
const bool pstate_en);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
682
bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
784
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
785
const bool pstate_en)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
79
static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
809
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
819
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
833
bool scl_enable;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
67
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
68
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
69
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
70
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
71
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
101
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
104
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1075
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1076
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1212
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1213
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
123
bool XFCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
125
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1257
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1267
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1268
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1278
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
147
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
148
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
164
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
165
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1682
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
172
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
182
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
183
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1848
bool PTEBufferSizeNotExceededY;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1849
bool PTEBufferSizeNotExceededC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
193
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2098
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2099
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
232
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
235
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
254
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
257
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
267
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
275
bool *ImmediateFlipSupportedForPipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2829
bool MainPlaneDoesODMCombine = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
298
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
311
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3123
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3126
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3167
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3170
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3180
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3188
bool *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3270
bool DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
329
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
416
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
428
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
47
bool ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
477
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
478
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5252
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5265
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5283
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5834
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5846
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
60
bool Enable;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6109
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6110
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
634
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
652
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
654
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
657
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
676
bool XFCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
678
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
698
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
81
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
99
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1644
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1645
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1646
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1647
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1648
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
225
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
226
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
227
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
228
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
333
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
334
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
404
bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
54
static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
691
bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
83
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
830
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
831
const bool pstate_en)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
85
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
855
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
865
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
879
bool scl_enable;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
97
bool odm_combine,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
67
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
68
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
69
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
70
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
71
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
312
bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1052
bool Case1OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1053
bool Case2OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1054
bool Case3OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
118
bool *NotEnoughTimeForDynamicMetadata);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
122
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
123
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1254
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1255
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
148
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
149
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1559
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
156
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1560
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1604
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1613
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1614
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1624
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
165
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
166
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
176
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1797
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1798
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
196
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
200
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2117
bool PTEBufferSizeNotExceededY = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2118
bool PTEBufferSizeNotExceededC = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
219
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
221
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
233
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
241
bool *ImmediateFlipSupportedForPipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
262
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
278
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
291
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2975
bool dummy7[DC__NUM_DPP__MAX] = { 0 };
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2976
bool dummysinglestring = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
313
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3188
int DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3213
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3217
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3258
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3260
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3272
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3280
bool *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3362
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3453
bool EnoughWritebackUnits = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3454
bool WritebackModeSupport = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3455
bool ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3458
bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX] = { 0 };
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
366
bool *NotEnoughUrgentLatencyHiding);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
411
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
419
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
462
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
468
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
489
bool SynchronizedVBlank,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
50
bool ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5080
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5093
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
511
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5115
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
512
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
522
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5370
bool *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5542
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5550
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
558
bool ViewportSizeSupportPerPlane[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
559
bool *ViewportSizeSupport);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
561
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5715
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5721
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5831
bool SynchronizedVBlank,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5853
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5854
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5978
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
599
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
600
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6014
bool ViewportSizeSupportPerPlane[],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6015
bool *ViewportSizeSupport)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
61
bool ODMCombineEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
614
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
615
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6169
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
627
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6284
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6285
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6320
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6321
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6364
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
784
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
82
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
820
bool *NotEnoughTimeForDynamicMetadata)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
824
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1183
bool visited[DC__NUM_PIPES__MAX] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
169
bool req128_l = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
170
bool req128_c = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
171
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
172
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1734
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1735
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1736
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1737
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1738
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
295
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
296
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
34
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
342
const bool dual_plane_en = is_dual_plane((enum source_format_class)(source_format));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
36
bool ret_val = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
658
bool is_chroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
659
bool is_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
895
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
896
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
897
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
898
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
899
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
923
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
933
bool dual_plane = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
947
bool scl_enable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
63
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
64
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
65
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
66
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.h
67
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
101
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
117
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
118
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1192
bool Case1OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1193
bool Case2OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1194
bool Case3OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
121
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
122
bool DynamicMetadataVMEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1471
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1472
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
154
bool *NotEnoughTimeForDynamicMetadata,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
166
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
167
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1737
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1738
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1791
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1800
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1801
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1811
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
192
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
193
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1992
bool NoChromaPlanes = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
200
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
209
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
210
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
220
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2301
bool PTEBufferSizeNotExceededY;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2302
bool PTEBufferSizeNotExceededC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
236
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
240
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2585
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2586
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
283
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
310
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3130
bool isInterlaceTiming;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3283
bool dummy7[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3284
bool dummysinglestring;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3413
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3447
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3451
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
358
bool *NotEnoughUrgentLatencyHiding);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3588
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3793
bool NoChroma = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3794
bool EnoughWritebackUnits = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3795
bool P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3796
bool DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3797
bool DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3799
bool ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3800
bool FMTBufferExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
402
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
410
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
453
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
459
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4728
bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
476
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
489
bool SynchronizedVBlank,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
492
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
493
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5106
bool UnboundedRequestEnabledThisState = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
518
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
519
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
533
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
535
bool DETSharedByAllDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5561
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
570
bool ViewportSizeSupportPerPlane[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
571
bool *ViewportSizeSupport);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
573
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5832
bool *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6023
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6031
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
612
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
613
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6196
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6202
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
627
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
628
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6297
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6310
bool SynchronizedVBlank,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6313
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6314
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6339
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6340
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
640
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6485
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
650
bool NoChromaPlanes,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
654
bool *UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
657
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6612
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6614
bool DETSharedByAllDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6649
bool ViewportSizeSupportPerPlane[],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6650
bool *ViewportSizeSupport)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6796
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
68
bool ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6927
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6928
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6973
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6974
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7011
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7191
bool NoChromaPlanes,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7195
bool *UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7218
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7220
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
81
bool ODMCombineIsEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
813
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
829
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
830
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
833
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
834
bool DynamicMetadataVMEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
85
bool ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
866
bool *NotEnoughTimeForDynamicMetadata,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
876
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1056
bool visited[DC__NUM_PIPES__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1550
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1551
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1552
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1553
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1554
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
174
bool req128_l = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
175
bool req128_c = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
176
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
177
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
316
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
317
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
32
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
34
bool ret_val = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
361
const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
651
bool is_chroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
652
bool is_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
856
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
857
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
858
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
859
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
860
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
881
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
885
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
63
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
64
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
65
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
66
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
67
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
272
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
314
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
110
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1210
bool Case1OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1211
bool Case2OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1212
bool Case3OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
126
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
127
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
130
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
131
bool DynamicMetadataVMEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1488
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1489
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
163
bool *NotEnoughTimeForDynamicMetadata,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
175
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1754
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1755
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
176
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1808
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1817
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1818
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1828
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2009
bool NoChromaPlanes = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
201
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
202
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
209
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
218
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
219
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
229
bool *PTEBufferSizeNotExceeded,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2320
bool PTEBufferSizeNotExceededY;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2321
bool PTEBufferSizeNotExceededC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
245
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
249
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2603
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2604
bool VRatioPrefetchMoreThan4 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
292
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3149
bool isInterlaceTiming;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
319
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3302
bool dummy7[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3303
bool dummysinglestring;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3363
static bool CalculateBytePerPixelAnd256BBlockSizes(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3519
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3553
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3557
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
367
bool *NotEnoughUrgentLatencyHiding);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3694
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3886
bool NoChroma = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3887
bool EnoughWritebackUnits = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3888
bool P2IWith420 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3889
bool DSCOnlyIfNecessaryWithBPP = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3890
bool DSC422NativeNotSupported = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3892
bool ViewportExceedsSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3893
bool FMTBufferExceeded = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
411
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
419
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
462
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
468
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4814
bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
485
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
498
bool SynchronizedVBlank,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
501
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
502
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5192
bool UnboundedRequestEnabledThisState = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
527
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
528
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
542
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5655
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
578
bool ViewportSizeSupportPerPlane[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
579
bool *ViewportSizeSupport);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
581
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5926
bool *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6118
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6126
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
620
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
621
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6291
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6297
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
635
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
636
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6392
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6405
bool SynchronizedVBlank,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6408
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6409
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6434
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6435
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
648
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
658
bool NoChromaPlanes,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6580
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
66
bool ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
662
bool *UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
665
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6707
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
672
bool ProgressiveTointerlaceUnitinOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
673
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6743
bool ViewportSizeSupportPerPlane[],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6744
bool *ViewportSizeSupport)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6887
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7017
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7018
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7063
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7064
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7099
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7279
bool NoChromaPlanes,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7283
bool *UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7306
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7308
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7322
bool ProgressiveTointerlaceUnitinOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7323
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
79
bool ODMCombineIsEnabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
83
bool ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
831
static bool CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
847
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
848
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
851
bool DynamicMetadataEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
852
bool DynamicMetadataVMEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
884
bool *NotEnoughTimeForDynamicMetadata,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
89
static bool CalculateBytePerPixelAnd256BBlockSizes(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
894
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1143
bool visited[DC__NUM_PIPES__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
120
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
122
bool ret_val = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1638
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1639
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1640
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1641
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1642
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
262
bool req128_l = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
263
bool req128_c = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
264
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
265
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
32
static bool CalculateBytePerPixelAnd256BBlockSizes(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
404
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
405
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
449
const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
739
bool is_chroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
740
bool is_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
941
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
942
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
943
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
944
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
945
const bool immediate_flip_support)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
966
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
970
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
64
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
65
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
66
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
67
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.h
68
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1037
static bool subvp_validate_static_schedulability(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1041
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1198
static bool update_pipe_slice_table_with_split_flags(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1204
bool merge[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1226
bool odm;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1228
bool updated = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1285
static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1287
bool merge[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1290
bool updated;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1300
static bool should_apply_odm_power_optimization(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1302
bool *merge)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1398
bool *merge,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1415
memset(merge, 0, MAX_PIPES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1424
static bool is_test_pattern_enabled(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1437
static bool dcn32_full_validate_bw_helper(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1442
bool *merge,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1444
bool *repopulate_pipes)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1449
bool found_supported_config = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1478
memset(merge, 0, MAX_PIPES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1600
static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1650
bool usr_retraining_support = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1651
bool unbounded_req_enabled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
183
static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
184
bool *repopulate_pipes, int *split, bool *merge);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1851
static bool dcn32_split_stream_for_mpc_or_odm(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1856
bool odm)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1937
static bool dcn32_apply_merge_split_flags_helper(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1940
bool *repopulate_pipes,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1942
bool *merge)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1945
bool newly_split[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2036
bool odm;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2138
bool dcn32_internal_validate_bw(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2145
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2146
bool repopulate_pipes = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2148
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2272
bool flags_valid = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2312
bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2317
bool subvp_in_use = dcn32_subvp_in_use(dc, context);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2319
bool need_fclk_lat_as_dummy = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2320
bool is_subvp_p_drr = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2802
static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3391
bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3393
bool allow = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3433
bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3435
bool allow = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3560
bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3564
bool vactive_found = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
599
static bool dcn32_assign_subvp_pipe(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
605
bool valid_assignment_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
680
static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
684
bool subvp_possible = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
726
static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
797
static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
799
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
814
bool subvp_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
815
bool drr_found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
898
static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
902
bool found = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
903
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
985
static bool subvp_subvp_admissable(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
988
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
47
bool dcn32_internal_validate_bw(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
74
bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1418
bool isInterlaceTiming;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1732
bool CompBufReservedSpaceNeedAdjustment;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1733
bool CompBufReservedSpaceNeedAdjustmentSingleDPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
63
bool ImmediateFlipRequirementFinal;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
68
bool DestinationLineTimesForPrefetchLessThan2 = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
69
bool VRatioPrefetchMoreThanMax = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1189
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1199
bool *TotalAvailablePipesSupport,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1325
double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1341
bool IsMainSurfaceUsingTheIndicatedTiming,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1354
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1359
bool *RequiresDSC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1366
bool LinkDSCEnable;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1580
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1688
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1717
unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1774
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1775
bool ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1803
bool *ExceededMALLSize)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
187
bool IsVertical(enum dm_rotation_angle Scan)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
189
bool is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1922
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1923
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1930
bool PTEBufferSizeNotExceeded[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1931
bool DCCMetaBufferSizeNotExceeded[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1969
bool use_one_row_for_frame[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1970
bool use_one_row_for_frame_flip[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1971
bool UsesMALLForStaticScreen[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1972
bool PTE_BUFFER_MODE[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1990
bool one_row_per_frame_fits_in_buffer[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2263
bool ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2264
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2276
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2277
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2537
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2538
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2541
bool ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2613
bool one_row_per_frame_fits_in_buffer[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2616
bool UsesMALLForStaticScreen[])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2620
bool CanAddAnotherSurfaceToMALL;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2667
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2671
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2710
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2746
bool *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2925
bool DRRDisplay[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2926
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2937
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2939
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2943
bool DynamicMetadataVMEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2944
bool ImmediateFlipRequirement,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2945
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2952
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2973
bool DynamicMetadataEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3157
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3158
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3204
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3251
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3252
bool DRRDisplay,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3285
const bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3359
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3360
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3399
bool dml32_CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3428
bool ExtendPrefetchIfPossible,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3440
bool *NotEnoughTimeForDynamicMetadata,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3451
bool MyError = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3802
bool Case1OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3803
bool Case2OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3804
bool Case3OK;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
405
bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4121
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4123
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4135
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4140
bool use_one_row_for_frame_flip,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4146
bool *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
415
bool ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4278
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4287
bool *USRRetrainingSupport,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4295
bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4305
bool SynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4317
bool SameTimingForFCLKChange;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
453
bool *UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
456
bool *CompBufReservedSpaceNeedAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
457
bool ViewportSizeSupportPerSurface[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
458
bool *ViewportSizeSupport)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
470
bool NoChromaSurfaces = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4872
bool use_one_row_for_frame[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4874
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4882
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5147
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5153
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5300
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5301
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5590
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5603
bool SynchronizeTimingsFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5607
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5608
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5633
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5634
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5648
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5651
bool FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5661
bool SameTiming = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5672
bool doublePlaneCriticalSurface = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5673
bool doublePipeCriticalSurface = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5862
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6076
bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6084
bool det_buff_size_override_en = nomDETInKByteOverrideEnable;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6109
bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6111
bool NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6123
bool NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6124
bool CalculateVActiveBandwithSupport_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6150
bool NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6174
bool *PrefetchBandwidthSupport)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6178
bool NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6260
bool *ImmediateFlipBandwidthSupport)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6279
bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurfaces,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6306
bool NotEnoughDETSwathFillLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
682
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
686
bool ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
877
bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
879
bool NoChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
882
bool CompBufReservedSpaceNeedAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
883
bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
885
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
910
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
912
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
930
bool DETPieceAssignedToThisSurfaceAlready[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
931
bool NextPotentialSurfaceToAssignDETPieceFound;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1009
bool SynchronizeTimingsFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1013
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1014
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1039
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
104
bool ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1040
bool WritebackEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1054
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1060
bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1068
bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1070
bool NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1083
bool NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1107
bool *PrefetchBandwidthSupport);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1149
bool *ImmediateFlipBandwidthSupport);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
1151
bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurfaces,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
142
bool *UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
145
bool *CompBufReservedSpaceNeedAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
146
bool ViewportSizeSupportPerSurface[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
147
bool *ViewportSizeSupport);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
150
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
154
bool ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
187
bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
189
bool NoChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
192
bool CompBufReservedSpaceNeedAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
193
bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
198
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
200
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
224
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
234
bool *TotalAvailablePipesSupport,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
247
double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
254
bool IsMainSurfaceUsingTheIndicatedTiming,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
267
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
272
bool *RequiresDSC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
297
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
310
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
320
unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
338
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
339
bool ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
367
bool *ExceededMALLSize);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
381
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
382
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
389
bool PTEBufferSizeNotExceeded[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
390
bool DCCMetaBufferSizeNotExceeded[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
428
bool use_one_row_for_frame[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
429
bool use_one_row_for_frame_flip[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
430
bool UsesMALLForStaticScreen[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
431
bool PTE_BUFFER_MODE[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
435
bool ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
436
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
448
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
449
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
45
bool IsVertical(enum dm_rotation_angle Scan);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
482
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
483
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
486
bool ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
501
bool one_row_per_frame_fits_in_buffer[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
504
bool UsesMALLForStaticScreen[]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
507
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
511
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
529
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
555
bool *NotEnoughUrgentLatencyHiding);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
591
bool DRRDisplay[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
592
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
603
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
605
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
609
bool DynamicMetadataVMEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
610
bool ImmediateFlipRequirement,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
611
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
618
bool Interlace[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
639
bool DynamicMetadataEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
651
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
652
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
671
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
683
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
684
bool DRRDisplay,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
692
const bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
712
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
713
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
721
bool dml32_CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
750
bool ExtendPrefetchIfPossible,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
762
bool *NotEnoughTimeForDynamicMetadata,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
777
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
779
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
791
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
796
bool use_one_row_for_frame_flip,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
802
bool *ImmediateFlipSupportedForPipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
823
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
832
bool *USRRetrainingSupport,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
891
bool use_one_row_for_frame[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
893
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
901
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
94
bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
946
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
952
bool DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
969
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
970
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
996
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
232
bool interlaced = dst->interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
237
bool dual_plane = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
303
bool visited[DC__NUM_PIPES__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
32
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
34
bool ret_val = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
50
bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
53
bool is_phantom_pipe;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
344
static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
401
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
445
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
595
bool is_pwrseq0 = link && link->link_index == 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
596
bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
598
bool is_replay = link && link->replay_settings.replay_feature_enabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
601
bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
604
bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
434
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
478
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
626
bool is_pwrseq0 = link && link->link_index == 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
627
bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
629
bool is_replay = link && link->replay_settings.replay_feature_enabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
632
bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h
58
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h
59
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h
60
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h
61
const bool ignore_viewport_pos,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h
62
const bool immediate_flip_support);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_lib.h
93
bool validate_max_state;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
100
bool ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
117
bool DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
123
bool ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
132
bool ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
137
bool FORCE_ONE_ROW_FOR_FRAME;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
205
bool dram_clock_change_requirement_final;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
244
bool do_urgent_latency_adjustment;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
247
bool disable_dram_clock_change_vactive_support;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
248
bool allow_dram_clock_one_display_vactive;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
262
bool use_min_dcfclk;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
263
bool clamp_min_dcfclk;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
264
bool gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
265
bool hostvm_enable;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
266
bool dsc422_native_support;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
335
bool odm_combine_4to1_supported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
336
bool dynamic_metadata_vm_enabled;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
391
bool unbounded_req_mode;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
392
bool gpuvm; // gpuvm enabled
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
393
bool hostvm; // hostvm enabled
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
394
bool gpuvm_levels_force_en;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
396
bool hostvm_levels_force_en;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
417
bool viewport_stationary;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
422
bool force_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
423
bool pte_buffer_mode;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
484
bool dp_multistream_en;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
536
bool synchronize_timings;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_structs.h
538
bool drr_display;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1018
bool CalculateMinAndMaxPrefetchMode(
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
292
bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
522
bool PlaneVisited[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
523
bool visited[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
57
bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1016
bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1024
bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1037
bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1048
bool DoUrgentLatencyAdjustment;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1054
bool FirstMainPlane;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1055
bool NotEnoughDETSwathFillLatencyHiding;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1063
bool ModeIsSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1064
bool ODMCombine4To1Supported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1072
bool DSCEnable[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1079
bool MPCCombineEnable[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1081
bool DynamicMetadataVMEnabled;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1090
bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1091
bool NumberOfHDMIFRLSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1097
bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1101
bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1102
bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1108
bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1109
bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1116
bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1141
bool dummystring[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1144
bool UseMinimumRequiredDCFCLK;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1145
bool ClampMinDCFCLK;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1146
bool AllowDramClockChangeOneDisplayVactive;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1167
bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1168
bool LinkCapacitySupport[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1169
bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1180
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1181
bool DSC422NativeSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1182
bool NoEnoughUrgentLatencyHiding;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1183
bool NoEnoughUrgentLatencyHidingPre;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1200
bool ExceededMALLSize;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1201
bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1205
bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1207
bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1208
bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1210
bool UnboundedRequestEnabledThisState;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1211
bool DRAMClockChangeRequirementFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1212
bool FCLKChangeRequirementFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1213
bool USRRetrainingRequiredFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1217
bool MPCCombineMethodIncompatible;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1219
bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1222
bool OutputMultistreamEn[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1223
bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1226
bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1227
bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1228
bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1229
bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1230
bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1238
bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1239
bool NotEnoughDETSwathFillLatencyHidingPerState[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
1243
bool CalculateMinAndMaxPrefetchMode(
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
170
bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
191
bool dummy_boolean_array[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
192
bool dummy_boolean;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
193
bool dummy_boolean2;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
196
bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
206
bool dummy_USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
221
bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
235
bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
236
bool MPCCombineMethodAsPossible;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
237
bool FullFrameMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
238
bool SubViewportMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
239
bool PhantomPipeMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
240
bool NoChroma;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
241
bool TotalAvailablePipesSupportNoDSC;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
242
bool TotalAvailablePipesSupportDSC;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
250
bool dummy_boolean[2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
264
bool UseMaximumVStartup;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
276
bool DCCEnabledAnyPlane;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
299
bool DummyPStateCheck;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
300
bool DRAMClockChangeSupportsVActive;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
301
bool PrefetchModeSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
302
bool PrefetchAndImmediateFlipSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
308
bool ImmediateFlipSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
311
bool PrefetchERROR;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
364
bool UseUrgentBurstBandwidth;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
377
bool GPUVMEnable;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
378
bool HostVMEnable;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
387
bool ODMCapability;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
401
bool XFCSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
414
bool ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
442
bool ViewportStationary[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
446
bool SynchronizeTimingsFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
447
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
448
bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
452
bool DRRDisplay[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
453
bool PteBufferMode[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
478
bool DCCEnable[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
479
bool FECEnable[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
484
bool WritebackEnable[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
498
bool Interlace[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
501
bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
508
bool DSCEnabled[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
512
bool skip_dio_check[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
514
bool SynchronizedVBlank;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
518
bool XFCEnabled[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
519
bool ScalerEnabled[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
521
bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
524
bool ImmediateFlipSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
540
bool AnyLinesForVMOrRowTooLarge;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
542
bool IgnoreViewportPositioning;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
543
bool ErrorResult[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
564
bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
568
bool CompBufReservedSpaceNeedAdjustment;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
576
bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
578
bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
579
bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
593
bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
597
bool WritebackLumaAndChromaScalingSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
598
bool Cursor64BppSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
613
bool ScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
614
bool SourceFormatPixelAndScanSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
616
bool DCCEnabledInAnyPlane;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
617
bool WritebackLatencySupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
618
bool WritebackModeSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
619
bool Writeback10bpc420Supported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
620
bool BandwidthSupport[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
624
bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
625
bool prefetch_vm_bw_valid;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
626
bool prefetch_row_bw_valid;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
627
bool NumberOfOTGSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
628
bool NonsupportedDSCInputBPC;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
629
bool WritebackScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
630
bool CursorSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
631
bool PitchSupport;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
635
bool P2IWith420;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
636
bool DSCOnlyIfNecessaryWithBPP;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
637
bool DSC422NativeNotSupported;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
638
bool LinkRateDoesNotMatchDPVersion;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
639
bool LinkRateForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
640
bool BPPForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
641
bool MultistreamWithHDMIOreDP;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
642
bool MSOOrODMSplitWithNonDPLink;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
643
bool NotEnoughLanesForMSO;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
644
bool ViewportExceedsSurface;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
646
bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
647
bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
648
bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
649
bool InvalidCombinationOfMALLUseForPState;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
659
bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
660
bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
661
bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
662
bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
670
bool ImmediateFlipRequiredFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
671
bool DCCProgrammingAssumesScanDirectionUnknownFinal;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
672
bool EnoughWritebackUnits;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
673
bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
674
bool NumberOfDP2p0Support;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
754
bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
755
bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
756
bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
757
bool PrefetchSupported[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
758
bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
760
bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
761
bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
764
bool ModeSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
766
bool DIOSupport[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
767
bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
768
bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
769
bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
771
bool ROBSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
773
bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
774
bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
775
bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
794
bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
799
bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
826
bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
840
bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
856
bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
884
bool dummysinglestring;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
885
bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
889
bool LinkDSCEnable;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
890
bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
893
bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
918
bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.h
919
bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1003
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1004
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1005
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1006
const bool iflip_en)
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1013
bool interlaced = e2e_pipe_param->pipe.dest.interlaced;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1028
bool dcc_en;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1029
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1030
bool mode_422;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
282
bool req128_l = 0;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
283
bool req128_c = 0;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
284
bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
285
bool surf_vert = (pipe_src_param->source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
394
bool surf_linear = (tiling == dm_sw_linear);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
395
bool surf_vert = (source_scan == dm_vert);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
40
static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
560
bool is_chroma)
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
567
bool surf_linear;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
568
bool surf_vert;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
67
static bool is_dual_plane(enum source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
69
bool ret_val = 0;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h
61
const bool cstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h
62
const bool pstate_en,
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h
63
const bool vm_en,
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h
64
const bool iflip_en);
sys/dev/pci/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c
169
bool is_navite_422_or_420,
sys/dev/pci/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h
85
bool is_navite_422_or_420,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10126
bool call_standalone)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
73
bool call_standalone);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
703
bool UseOnlyMaxPrefetchModes;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_lib_defines.h
77
typedef bool dml_bool_t;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
17
bool disable_fams2 = !in_dc->debug.fams2_config.bits.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
644
static bool dml21_wrapper_get_plane_id(const struct dc_state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
727
bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
900
bool sub_vp_enabled)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h
21
bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h
26
void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
186
bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
196
static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
236
bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
327
bool phantoms_added = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
36
bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
513
bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h
20
bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h
29
bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h
49
bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
15
static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
204
static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
206
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
266
static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
268
bool is_supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
297
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
300
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
454
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
70
bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
100
bool plane0_plane1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
31
bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
35
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
61
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
75
bool valid;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
81
bool requires_dedicated_mall_mcache;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
98
bool mall_comb_mcache_p0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
99
bool mall_comb_mcache_p1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top.h
22
bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top.h
28
bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top.h
35
bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top.h
44
bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
157
bool cursor_stereo_en;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
158
bool cursor_2x_magnify;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
182
bool enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
202
bool mirrored;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
204
bool rect_out_height_spans_vactive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
207
bool stationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
224
bool enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
225
bool upsp_enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
264
bool interlaced;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
267
bool enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
271
bool disallowed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
272
bool drr_active_variable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
273
bool drr_active_fixed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
285
bool output_disabled; // The stream does not go to a backend for output to a physical
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
287
bool validate_output; // Do not validate the link configuration for this display stream.
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
355
bool enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
369
bool setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
372
bool tdlut_mpc_width_flag;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
375
bool immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
396
bool force_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
398
bool enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
399
bool value;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
413
bool disable_dynamic_odm;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
414
bool disable_subvp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
416
bool minimize_active_latency_hiding;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
429
bool gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
430
bool ffbm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
431
bool hostvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
435
bool minimize_det_reallocation;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
451
bool enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
452
bool value;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
456
bool enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
457
bool value;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
459
bool mode_support_check_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
460
bool mcache_admissibility_check_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
461
bool surface_viewport_size_check_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
465
bool optimize_tdlut_scheduling; // TBD: for DV, will set this to 1, to ensure tdlut schedule is calculated based on address/width mode
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
469
bool uclk_pstate_change_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
470
bool fclk_pstate_change_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
471
bool g6_temp_read_pstate_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
472
bool g7_ppt_pstate_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
475
bool enhanced_prefetch_schedule_acceleration;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
476
bool dcc_programming_assumes_scan_direction_unknown;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
477
bool synchronize_timings;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
478
bool synchronize_ddr_displays_for_uclk_pstate_change;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
479
bool max_outstanding_when_urgent_expected_disable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
480
bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
482
bool all_streams_blanked;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
497
bool plane1_enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
498
bool imall_enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
161
bool no_dfs;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
162
bool do_urgent_latency_adjustment;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
106
bool is_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
110
bool valid;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
116
bool requires_dedicated_mall_mcache;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
185
bool mall_comb_mcache_p0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
186
bool mall_comb_mcache_p1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
187
bool plane0_plane1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
243
bool valid;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
278
bool enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
295
bool ModeIsSupported; //<brief Is the mode support any voltage and combine setting
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
296
bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
298
bool WritebackLatencySupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
299
bool ScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
300
bool SourceFormatPixelAndScanSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
301
bool P2IWith420;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
302
bool DSCOnlyIfNecessaryWithBPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
303
bool DSC422NativeNotSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
304
bool LinkRateDoesNotMatchDPVersion;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
305
bool LinkRateForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
306
bool BPPForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
307
bool MultistreamWithHDMIOreDP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
308
bool MSOOrODMSplitWithNonDPLink;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
309
bool NotEnoughLanesForMSO;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
310
bool NumberOfOTGSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
311
bool NumberOfHDMIFRLSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
312
bool NumberOfDP2p0Support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
313
bool WritebackScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
314
bool CursorSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
315
bool PitchSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
316
bool ViewportExceedsSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
317
bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
318
bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
319
bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
320
bool InvalidCombinationOfMALLUseForPState;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
321
bool ExceededMALLSize;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
322
bool EnoughWritebackUnits;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
323
bool ExceededMultistreamSlots;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
324
bool NotEnoughDSCUnits;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
325
bool NotEnoughDSCSlices;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
326
bool PixelsPerLinePerDSCUnitSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
327
bool DSCCLKRequiredMoreThanSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
328
bool DTBCLKRequiredMoreThanSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
329
bool LinkCapacitySupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
330
bool ROBSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
331
bool OutstandingRequestsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
332
bool OutstandingRequestsUrgencyAvoidance;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
333
bool PTEBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
334
bool DCCMetaBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
335
bool TotalVerticalActiveBandwidthSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
336
bool VActiveBandwidthSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
338
bool USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
339
bool PrefetchSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
340
bool DynamicMetadataSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
341
bool VRatioInPrefetchSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
342
bool DISPCLK_DPPCLK_Support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
343
bool TotalAvailablePipesSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
344
bool ViewportSizeSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
345
bool ImmediateFlipSupportedForState;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
347
bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
350
bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
351
bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
358
bool g6_temp_read_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
359
bool temp_read_or_ppt_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
411
bool uclk_pstate_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
412
bool fclk_pstate_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
415
bool fams2_required;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
419
bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
425
bool meets_eco; // Stutter cycles will meet Z8 ECO criteria
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
426
bool supported_in_blank; // Changing to configurations where this is false requires Z8 to be disabled during the transition
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
578
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
612
bool vready_at_or_after_vsync[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
614
bool cstate_max_cap_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
615
bool hw_debug5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
62
bool disable_vblank;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
621
bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
622
bool UsesMALLForStaticScreen[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
63
bool disable_svp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
64
bool disable_drr_var;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
65
bool disable_drr_clamped;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
66
bool disable_drr_var_when_var_active;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
668
bool PTE_BUFFER_MODE[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
67
bool disable_drr_clamped_when_var_active;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
672
bool ROBUrgencyAvoidance;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
68
bool disable_fams2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
684
bool failed_prefetch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
685
bool failed_uclk_pstate;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
686
bool failed_mcache_validation;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
687
bool failed_dpmm;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
688
bool failed_mode_programming;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
689
bool failed_mode_programming_dcfclk;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
69
bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
690
bool failed_mode_programming_prefetch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
691
bool failed_mode_programming_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
692
bool failed_map_watermarks;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
70
bool disable_dyn_odm;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
71
bool disable_dyn_odm_for_multi_stream;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
72
bool disable_dyn_odm_for_stream_with_svp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
124
bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
409
bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
414
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
540
bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
545
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
632
bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
645
bool core_dcn4_calculate_mcache_allocation(struct dml2_calculate_mcache_allocation_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h
10
bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h
11
bool core_dcn4_calculate_mcache_allocation(struct dml2_calculate_mcache_allocation_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h
7
bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h
8
bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h
9
bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10063
bool SameTiming = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10064
bool FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1008
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1010
bool UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10183
bool isInterlaceTiming = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !p->ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10249
memset(l->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1028
bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1029
bool NextPotentialSurfaceToAssignDETPieceFound;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1030
bool MinimizeReallocationSuccess = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10343
static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex *in_out_params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10365
bool must_support_iflip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11048
bool cursor_not_enough_urgent_latency_hiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11837
bool isInterlaceTiming;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12017
bool dml2_core_calcs_mode_programming_ex(struct dml2_core_calcs_mode_programming_ex *in_out_params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12020
bool result = dml_core_mode_programming(in_out_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12030
bool is_plane1,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12049
bool surf_linear_128_l = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12050
bool surf_linear_128_c = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12148
static bool is_dual_plane(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12150
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12221
bool dual_plane = is_dual_plane((enum dml2_source_format_class)(source_format));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12237
bool is_phantom_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1242
bool isTMDS420)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1272
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1563
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1564
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1827
bool Interlace,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1828
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1831
bool mirrored,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1832
bool ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
188
static unsigned int dml_round_to_multiple(unsigned int num, unsigned int multiple, bool up)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1900
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1901
bool use_one_row_for_frame,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1905
bool DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1912
bool mrq_present,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1946
bool one_row_per_frame_fits_in_buffer[],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1949
bool is_using_mall_for_ss[])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1953
bool CanAddAnotherSurfaceToMALL;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1993
bool DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1994
bool DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
233
static bool dml_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
235
bool is_phantom = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
245
static bool dml_get_is_phantom_pipe(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int pipe_idx)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
249
bool is_phantom = dml_is_phantom_pipe(&display_cfg->plane_descriptors[plane_idx]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2659
bool is_avg_bw,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2660
bool is_hvm_en,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2661
bool is_hvm_only,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2753
bool HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3184
bool DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3390
bool *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3437
bool *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3659
bool ptoi_supported,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3701
bool NoChromaOrLinear = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
385
dml_get_var_func(unbounded_request_enabled, bool, mode_lib->mp.UnboundedRequestEnabled);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
387
dml_get_var_func(cstate_max_cap_mode, bool, mode_lib->mp.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
389
dml_get_var_func(hw_debug5, bool, mode_lib->mp.hw_debug5);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3952
bool UseDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
399
bool is_mrq_present,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4043
static bool ValidateODMMode(enum dml2_odm_mode ODMMode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4047
bool UseDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4057
bool are_odm_segments_symmetrical = (ODMMode == dml2_odm_mode_combine_3to1) ? UseDSC : true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4058
bool is_max_dsc_slice_required = (ODMMode == dml2_odm_mode_combine_3to1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4110
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4117
bool *TotalAvailablePipesSupport,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4131
bool success;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4132
bool UseDSC = DSCEnable && (NumberOfDSCSlices > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4134
bool isTMDS420 = (OutFormat == dml2_420 && Output == dml2_hdmi);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4224
bool *RequiresDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4225
bool *RequiresFEC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4231
bool LinkDSCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
428
static void PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
442
static bool dml_is_420(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
444
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4463
bool DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4486
bool DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4553
bool *ExceededMALLSize)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4809
bool ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4860
bool inc_flip_bw, // including flip bw
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4861
bool use_qual_row_bw,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4912
bool is_phantom = dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4913
bool exclude_this_plane = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5011
bool max_outstanding_when_urgent_expected,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5087
static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch, struct dml2_core_calcs_CalculatePrefetchSchedule_params *p)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5090
bool dcc_mrq_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
537
static bool dml_is_vertical_rotation(enum dml2_rotation_angle Scan)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
539
bool is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
55
static void dml2_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5521
bool min_Lsw_equ_ok = *p->Tpre_rounded >= s->Tvm_trips_rounded + 2.0*s->Tr0_trips_rounded + s->min_Lsw_equ*s->LineTime;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5522
bool tpre_gt_req_latency = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5610
bool Case1OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5611
bool Case2OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5612
bool Case3OK = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
593
bool *surf_linear128_l,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
594
bool *surf_linear128_c)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5978
static noinline_for_stack bool CheckGlobalPrefetchAdmissibility(struct dml2_core_internal_scratch *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6314
bool *vactive_bandwidth_support_ok, // vactive ok
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6315
bool *bandwidth_support_ok,// max of vm, prefetch, vactive all ok
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6416
bool *flip_bandwidth_support_ok,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6463
bool iflip_enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6464
bool use_lb_flip_bw,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6470
bool GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6482
bool use_one_row_for_frame_flip,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6489
bool dcc_mrq_enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6495
bool *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6683
bool FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7114
bool clk_entry_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7152
bool gpuvm_enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7153
bool hostvm_enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7928
static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
817
bool ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
826
bool surf_linear128_l[],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
827
bool surf_linear128_c[],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8598
memset(s->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8777
memset(s->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9081
bool cursor_not_enough_urgent_latency_hiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9174
bool isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
987
static bool UnboundedRequest(bool unb_req_force_en, bool unb_req_force_val, unsigned int TotalNumberOfActiveDPP, bool NoChromaOrLinear)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
989
bool unb_req_ok = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
990
bool unb_req_en = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9926
bool mrq_present,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9947
bool dcc_mrq_enable = display_cfg->plane_descriptors[k].surface.dcc.enable && mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.h
20
bool dml2_core_calcs_mode_programming_ex(struct dml2_core_calcs_mode_programming_ex *in_out_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.h
34
void dml2_core_calcs_get_dpte_row_height(unsigned int *dpte_row_height, struct dml2_core_internal_display_mode_lib *mode_lib, bool is_plane1, enum dml2_source_format_class SourcePixelFormat, enum dml2_swizzle_mode SurfaceTiling, enum dml2_rotation_angle ScanDirection, unsigned int pitch, unsigned int GPUVMMinPageSizeKBytes);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
11
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
9
bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance *out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.h
11
bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance *out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1008
bool mall_comb_mcache_l[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1009
bool mall_comb_mcache_c[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1010
bool lc_comb_mcache[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
104
bool ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1048
bool dummy_boolean[3];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
105
bool UPSPEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1052
bool dummy_boolean_array[2][DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1068
bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1069
bool MPCCombineMethodAsPossible;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
107
bool mirrored;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1070
bool TotalAvailablePipesSupportNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1074
bool TotalAvailablePipesSupportDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1088
bool ImmediateFlipRequired;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1089
bool FullFrameMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1090
bool SubViewportMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1091
bool PhantomPipeMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1092
bool SubViewportMALLRefreshGreaterThan120Hz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1128
bool stream_visited[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1136
bool recalc_prefetch_schedule;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1137
bool recalc_prefetch_done;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1162
bool dummy_boolean_array[2][DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1163
bool dummy_boolean[2];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1176
bool immediate_flip_required; // any pipes need immediate flip
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1177
bool DestinationLineTimesForPrefetchLessThan2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1178
bool VRatioPrefetchMoreThanMax;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1228
bool recalc_prefetch_schedule;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
123
bool DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1235
bool dsc_enable[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
129
bool ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1290
bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1308
bool mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1312
bool *PTEBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1313
bool *DCCMetaBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1350
bool *use_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1351
bool *use_one_row_for_frame_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1352
bool *is_using_mall_for_ss;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1353
bool *PTE_BUFFER_MODE;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
136
bool ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1375
bool NoTimeToPrefetch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
141
bool FORCE_ONE_ROW_FOR_FRAME;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1424
bool ForceSingleDPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1426
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1439
bool TryToAllocateForWriteLatency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1448
bool ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1449
bool DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1461
bool GPUVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1468
bool is_phantom;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1470
bool mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1570
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1578
bool dual_plane;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1585
bool interlaced;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1651
bool *use_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1668
bool mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1704
bool USRRetrainingRequired;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1711
bool SynchronizeTimings;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1712
bool SynchronizeDRRDisplaysForUCLKPStateChange;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1729
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1731
bool max_outstanding_when_urgent_expected;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1740
bool *global_dram_clock_change_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1744
bool *global_fclk_change_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1746
bool *USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1749
bool *g6_temp_read_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1750
bool *temp_read_or_ppt_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1761
bool ForceSingleDPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1774
bool *surf_linear128_l;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1775
bool *surf_linear128_c;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1782
bool mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1805
bool *UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1808
bool *ViewportSizeSupportPerSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1809
bool *ViewportSizeSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1810
bool *hw_debug5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1825
bool SinglePlaneCriticalSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1826
bool SinglePipeCriticalSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1842
bool stream_visited[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1848
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1859
bool hw_debug5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1863
bool SynchronizeTimings;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1867
bool ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1886
bool rob_alloc_compressed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1899
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1917
bool DynamicMetadataEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1918
bool DynamicMetadataVMEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1939
bool setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1950
bool dcc_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1951
bool mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1970
bool *NotEnoughTimeForDynamicMetadata;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2017
bool *recalc_prefetch_schedule;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2026
bool prefetch_global_check_passed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2042
bool surf_vert;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2045
bool imall_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2075
bool is_dual_plane;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2102
bool dcc_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2111
bool surf_vert;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2114
bool imall_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2155
bool *mall_comb_mcache_l;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2156
bool *mall_comb_mcache_c;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2157
bool *lc_comb_mcache;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
216
bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2163
bool setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2167
bool gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2169
bool is_gfx11;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2170
bool tdlut_mpc_width_flag;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
219
bool WritebackLatencySupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2193
bool inc_flip_bw;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
220
bool ScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
221
bool SourceFormatPixelAndScanSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
222
bool P2IWith420;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
2226
bool mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
223
bool DSCSlicesODMModeSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
224
bool DSCOnlyIfNecessaryWithBPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
225
bool DSC422NativeNotSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
226
bool LinkRateDoesNotMatchDPVersion;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
227
bool LinkRateForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
228
bool BPPForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
229
bool MultistreamWithHDMIOreDP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
230
bool MSOOrODMSplitWithNonDPLink;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
231
bool NotEnoughLanesForMSO;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
232
bool NumberOfOTGSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
233
bool NumberOfHDMIFRLSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
234
bool NumberOfDP2p0Support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
235
bool WritebackScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
236
bool CursorSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
237
bool PitchSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
238
bool ViewportExceedsSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
240
bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
241
bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
242
bool InvalidCombinationOfMALLUseForPState;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
243
bool ExceededMALLSize;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
244
bool EnoughWritebackUnits;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
246
bool ExceededMultistreamSlots;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
247
bool NotEnoughDSCUnits;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
248
bool NotEnoughDSCSlices;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
249
bool PixelsPerLinePerDSCUnitSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
250
bool DSCCLKRequiredMoreThanSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
251
bool DTBCLKRequiredMoreThanSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
252
bool LinkCapacitySupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
254
bool ROBSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
255
bool OutstandingRequestsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
256
bool OutstandingRequestsUrgencyAvoidance;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
258
bool PTEBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
259
bool DCCMetaBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
262
bool global_dram_clock_change_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
263
bool global_fclk_change_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
264
bool USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
265
bool AvgBandwidthSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
266
bool UrgVactiveBandwidthSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
267
bool EnoughUrgentLatencyHidingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
268
bool PrefetchScheduleSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
269
bool PrefetchSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
270
bool PrefetchBandwidthSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
271
bool DynamicMetadataSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
272
bool VRatioInPrefetchSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
273
bool DISPCLK_DPPCLK_Support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
274
bool TotalAvailablePipesSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
275
bool ODMSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
276
bool ModeSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
277
bool ViewportSizeSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
279
bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
282
bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
283
bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
324
bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
331
bool incorrect_imall_usage;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
333
bool g6_temp_read_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
334
bool temp_read_or_ppt_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
337
bool dcfclk_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
338
bool qos_bandwidth_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
372
bool NoTimeForPrefetch[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
373
bool NoTimeForDynamicMetadata[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
400
bool DCCEnabledInAnySurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
405
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
407
bool hw_debug5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
427
bool use_one_row_for_frame[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
428
bool use_one_row_for_frame_flip[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
449
bool surf_linear128_l[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
450
bool surf_linear128_c[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
485
bool is_using_mall_for_ss[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
488
bool PTE_BUFFER_MODE[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
52
bool dsc422_native_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
520
bool RequiresDSC[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
521
bool RequiresFEC[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
528
bool TotalAvailablePipesSupportNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
529
bool TotalAvailablePipesSupportDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
53
bool cursor_64bpp_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
569
bool MPCCombine[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
572
bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
573
bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
574
bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
575
bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
576
bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
577
bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
601
bool mall_comb_mcache_l[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
602
bool mall_comb_mcache_c[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
603
bool lc_comb_mcache[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
63
bool dynamic_metadata_vm_enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
68
bool dcc_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
69
bool ptoi_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
707
bool surf_linear128_l[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
708
bool surf_linear128_c[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
778
bool UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
781
bool hw_debug5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
785
bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
786
bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
79
bool imall_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
790
bool PrefetchAndImmediateFlipSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
793
bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
795
bool use_one_row_for_frame[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
796
bool use_one_row_for_frame_flip[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
806
bool dsc_enable[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
827
bool immediate_flip_required; // any pipes need immediate flip
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
839
bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
842
bool UrgVactiveBandwidthSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
843
bool PrefetchScheduleSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
844
bool UrgentBandwidthSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
845
bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
846
bool ImmediateFlipSupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
847
bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
848
bool dcfclk_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
860
bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
87
bool dcn_mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
893
bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
941
bool PTE_BUFFER_MODE[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
945
bool is_using_mall_for_ss[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
957
bool USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
958
bool g6_temp_read_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
959
bool temp_read_or_ppt_support;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
962
bool global_dram_clock_change_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
963
bool global_fclk_change_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
154
bool dml2_core_utils_is_422_packed(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
156
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
217
void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
28
bool dml2_core_utils_is_420(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
30
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
368
unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
415
bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
417
bool is_phantom = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
460
bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
465
bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
471
bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
473
bool is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
536
bool clk_entry_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
556
bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
558
bool ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
672
bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
686
bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
702
bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
717
bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
732
bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
739
bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
755
bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
771
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
91
bool dml2_core_utils_is_422_planar(enum dml2_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
93
bool val = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
13
bool dml2_core_utils_is_420(enum dml2_source_format_class source_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
14
bool dml2_core_utils_is_422_planar(enum dml2_source_format_class source_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
15
bool dml2_core_utils_is_422_packed(enum dml2_source_format_class source_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
16
void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
19
unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
22
bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
24
bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
25
bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
26
bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
30
bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
34
bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
35
bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
36
bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
37
bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
38
bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
39
bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
40
bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
41
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
186
static bool add_margin_and_round_to_dfs_grainularity(double clock_khz, double margin, unsigned long vco_freq_khz, unsigned long *rounded_khz, uint32_t *divider_id)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
238
static bool round_to_non_dfs_granularity(unsigned long dispclk_khz, unsigned long dpprefclk_khz, unsigned long dtbrefclk_khz,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
258
static bool round_up_and_copy_to_next_dpm(unsigned long min_value, unsigned long *rounded_value, const struct dml2_clk_table *clock_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
260
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
278
static bool round_up_to_next_dpm(unsigned long *clock_value, const struct dml2_clk_table *clock_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
283
static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
285
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
321
static bool map_soc_min_clocks_to_dpm_coarse_grained(struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
323
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
362
static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mode_support_result, struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
364
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
365
bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_identical = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
415
static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
418
bool identical = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
419
bool contains_drr = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
482
static bool determine_power_management_features_with_vblank_only(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
527
static bool determine_power_management_features_with_vactive_and_vblank(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
559
static bool determine_power_management_features_with_fams(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
589
static bool map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
592
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
664
bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
666
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
688
bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
690
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
742
bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h
10
bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h
11
bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h
12
bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
14
static bool dummy_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
19
bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance *out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
21
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
9
static bool dummy_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.h
11
bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance *out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
10
bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
133
static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
147
static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
149
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
150
bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_equal = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
39
static bool build_min_clk_table_fine_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
41
bool dcfclk_fine_grained = false, fclk_fine_grained = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
8
static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h
10
bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h
11
bool mcg_dcn4_unit_test(void);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
14
bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
16
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
9
static bool dummy_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.h
11
bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
120
static bool iterate_to_next_candidiate(struct dml2_pmo_instance *pmo, int size)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
123
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
145
static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
147
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
197
static bool are_timings_trivially_synchronizable(struct display_configuation_with_meta *display_config, int mask)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
200
bool identical = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
201
bool contains_drr = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
235
bool pmo_dcn3_initialize(struct dml2_pmo_initialize_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
250
static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
265
static bool is_dp_encoder(enum dml2_output_encoder_class encoder_type)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
280
bool pmo_dcn3_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
332
bool pmo_dcn3_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
334
bool is_vmin = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
366
bool pmo_dcn3_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
375
bool optimizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
455
bool pmo_dcn3_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
460
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
525
bool pmo_dcn3_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
650
bool pmo_dcn3_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
66
static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
668
bool pmo_dcn3_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
672
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
673
bool reached_end;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
76
static bool optimize_dcc_mcache_no_odm(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
82
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
10
bool pmo_dcn3_initialize(struct dml2_pmo_initialize_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
12
bool pmo_dcn3_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
14
bool pmo_dcn3_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
15
bool pmo_dcn3_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
16
bool pmo_dcn3_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
18
bool pmo_dcn3_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
19
bool pmo_dcn3_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h
20
bool pmo_dcn3_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1007
static bool all_timings_support_vblank(const struct dml2_pmo_instance *pmo,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1013
bool synchronizable = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1038
static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1076
static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1219
static bool all_planes_match_method(const struct display_configuation_with_meta *display_cfg, int plane_mask, enum dml2_pstate_method method)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1286
static bool is_timing_group_schedulable(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1346
static bool is_config_schedulable(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1352
bool schedulable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1391
bool swapped = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1450
bool swapped = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1515
static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1521
bool strategy_matches_drr_requirements = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1566
static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_instance *pmo,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1583
bool strategy_matches_forced_requirements = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1584
bool strategy_matches_drr_requirements = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
182
static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1833
bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
184
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
1845
bool build_override_strategy = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2107
static bool setup_display_config(struct display_configuation_with_meta *display_config, struct dml2_pmo_instance *pmo, int strategy_index)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2111
bool fams2_required = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2112
bool success = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2169
bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2171
bool p_state_supported = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
221
static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2229
bool pmo_dcn4_fams2_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2231
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2262
bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2264
bool success = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2266
bool stutter_period_meets_z8_eco = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2267
bool z8_stutter_optimization_too_expensive = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2268
bool stutter_optimization_too_expensive = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2325
bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2327
bool success = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2349
bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
2351
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
244
static bool optimize_dcc_mcache_no_odm(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
250
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
288
bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
293
bool result;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
440
bool skip_to_next_stream;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
441
bool expanded_strategy_added;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
442
bool skip_iteration;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
513
static bool is_variant_method_valid(const struct dml2_pmo_pstate_strategy *base_strategy,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
519
bool valid = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
539
const bool should_permute,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
543
bool variant_found;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
640
bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
711
static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
726
static bool is_dp_encoder(enum dml2_output_encoder_class encoder_type)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
741
bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
797
bool pmo_dcn4_fams2_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
799
bool is_vmin = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
831
bool pmo_dcn4_fams2_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
840
bool optimizable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
925
static bool is_bit_set_in_bitfield(unsigned int bit_field, unsigned int bit_offset)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
989
static bool all_timings_support_vactive(const struct dml2_pmo_instance *pmo,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
994
bool valid = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
10
bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
12
bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
14
bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
15
bool pmo_dcn4_fams2_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
16
bool pmo_dcn4_fams2_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
18
bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
19
bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
20
bool pmo_dcn4_fams2_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
22
bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
23
bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h
24
bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
10
static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
15
static bool dummy_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
20
static bool dummy_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
25
bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
27
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.h
11
bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
14
bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
27
bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
35
bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c
43
bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.h
8
bool dml2_top_legacy_initialize_instance(struct dml2_initialize_instance_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1018
bool dml2_top_soc15_build_mcache_programming(struct dml2_build_mcache_programming_in_out *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1020
bool success = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1109
bool dml2_top_soc15_initialize_instance(struct dml2_initialize_instance_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
1116
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
112
static bool dml2_top_optimization_init_function_vmin(const struct optimization_init_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
121
static bool dml2_top_optimization_test_function_vmin(const struct optimization_test_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
131
static bool dml2_top_optimization_optimize_function_vmin(const struct optimization_optimize_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
144
static bool dml2_top_optimization_init_function_uclk_pstate(const struct optimization_init_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
154
static bool dml2_top_optimization_test_function_uclk_pstate(const struct optimization_test_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
164
static bool dml2_top_optimization_optimize_function_uclk_pstate(const struct optimization_optimize_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
176
static bool dml2_top_optimization_init_function_stutter(const struct optimization_init_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
186
static bool dml2_top_optimization_test_function_stutter(const struct optimization_test_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
195
static bool dml2_top_optimization_optimize_function_stutter(const struct optimization_optimize_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
206
static bool dml2_top_optimization_perform_optimization_phase(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
208
bool test_passed = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
209
bool optimize_succeeded = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
210
bool candidate_validation_passed = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
282
static bool dml2_top_optimization_perform_optimization_phase_1(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
285
bool supported = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
29
static bool dml2_top_optimization_init_function_min_clk_for_latency(const struct optimization_init_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
331
static bool calculate_first_second_splitting(const int *mcache_boundaries, int num_boundaries, int shift,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
339
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
38
static bool dml2_top_optimization_test_function_min_clk_for_latency(const struct optimization_test_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
395
static bool find_shift_for_valid_cache_id_assignment(int *mcache_boundaries, unsigned int num_boundaries,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
401
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
45
static bool dml2_top_optimization_optimize_function_min_clk_for_latency(const struct optimization_optimize_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
47
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
472
static bool calculate_h_split_for_scaling_transform(int full_vp_width, int h_active, int num_pipes,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
477
bool success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
508
bool dml2_top_mcache_validate_admissability(struct top_mcache_validate_admissability_in_out *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
527
bool p0pass = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
528
bool p1pass = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
529
bool all_pass = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
58
static bool dml2_top_optimization_test_function_mcache(const struct optimization_test_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
61
bool mcache_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
62
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
728
bool dml2_top_mcache_calc_mcache_count_and_offsets(struct top_mcache_calc_mcache_count_and_offsets_in_out *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
735
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
775
static bool dml2_top_soc15_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
781
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
782
bool mcache_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
824
static bool dml2_top_soc15_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
829
bool result = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
830
bool mcache_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
831
bool uclk_pstate_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
832
bool vmin_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
833
bool stutter_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
85
memcpy(params->display_config->stage2.per_plane_mcache_support, l->test_mcache.validate_admissibility_params.per_plane_status, sizeof(bool) * DML2_MAX_PLANES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
91
static bool dml2_top_optimization_optimize_function_mcache(const struct optimization_optimize_function_params *params)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c
94
bool optimize_success = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h
10
bool dml2_top_mcache_calc_mcache_count_and_offsets(struct top_mcache_calc_mcache_count_and_offsets_in_out *params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h
12
bool dml2_top_mcache_validate_admissability(struct top_mcache_validate_admissability_in_out *params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h
13
bool dml2_top_soc15_build_mcache_programming(struct dml2_build_mcache_programming_in_out *params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h
8
bool dml2_top_soc15_initialize_instance(struct dml2_initialize_instance_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
116
bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
117
bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
170
bool dsc_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
174
bool is_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
230
bool performed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
231
bool success;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
237
bool performed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
238
bool success;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
243
bool per_plane_mcache_support[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
252
bool valid;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
269
bool valid;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
309
bool performed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
310
bool success;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
321
bool fams2_required;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
328
bool performed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
329
bool success;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
330
bool unoptimizable_streams[DML2_MAX_DCN_PIPES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
334
bool performed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
335
bool success;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
337
bool optimal_reserved_time_in_vblank_us;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
338
bool vblank_includes_z8_optimization;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
364
bool allow_state_increase;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
420
bool mode_is_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
481
bool (*initialize)(struct dml2_core_initialize_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
482
bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
483
bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
484
bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
485
bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
513
bool *dcc_mcache_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
574
bool last_candidate_failed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
604
bool last_candidate_failed;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
63
bool perform_pseudo_build;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
656
bool z8_vblank_optimizable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
661
bool group_is_drr_enabled[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
662
bool group_is_drr_active[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
718
bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
719
bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
72
bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
721
bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
722
bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
723
bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
725
bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
726
bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
727
bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
729
bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
730
bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
731
bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
748
bool per_plane_status[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
88
bool perform_pseudo_map;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
885
bool last_candidate_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
895
bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
896
bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
897
bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
900
bool all_or_nothing;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
954
bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
955
bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
956
bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1012
static bool map_dc_pipes_with_callbacks(struct dml2_context *ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1019
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
1035
bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
179
static bool validate_pipe_assignment(const struct dml2_context *ctx, const struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, const struct dml2_dml_to_dc_pipe_mapping *mapping)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
227
static bool is_plane_using_pipe(const struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
235
static bool is_pipe_free(const struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
326
static bool is_pipe_in_candidate_array(const unsigned int pipe_idx,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
340
static bool find_more_pipes_for_stream(struct dml2_context *ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
39
bool pipe_used[MAX_ODM_FACTOR][MAX_MPCC_FACTOR];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
406
static bool find_more_free_pipes(struct dml2_context *ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
474
bool sorted, swapped;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
58
static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
62
bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
681
static bool is_pipe_used(const struct dc_plane_pipe_pool *pool, unsigned int pipe_idx)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
704
bool is_plane_duplicate = ctx->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
954
static bool unmap_dc_pipes_for_stream(struct dml2_context *ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
963
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
983
static bool map_dc_pipes_for_stream(struct dml2_context *ctx,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
992
bool result = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h
50
bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
102
bool enable_flexible_pipe_mapping;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
103
bool plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
73
bool disp_cfg_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
75
bool disp_cfg_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
77
bool dml_pipe_idx_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
79
bool dml_pipe_idx_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
81
bool dml_pipe_idx_to_plane_index_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
146
static bool all_pipes_have_stream_and_plane(struct dml2_context *ctx, const struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
162
static bool mpo_in_use(const struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
228
static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context, unsigned int *index)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
232
bool valid_assignment_found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
234
bool current_assignment_freesync = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
309
static bool enough_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *state)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
313
bool subvp_possible = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
357
static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
431
bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
433
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
507
static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
511
bool found = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
512
bool schedulable = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
601
bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc_state *context, enum dml_dram_clock_change_support pstate_change_type)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
603
bool schedulable = true; // true by default for single display case
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
810
static bool remove_all_phantom_planes_for_stream(struct dml2_context *ctx, struct dc_stream_state *stream, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
840
bool dml2_svp_remove_all_phantom_pipes(struct dml2_context *ctx, struct dc_state *state)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
843
bool removed_pipe = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c
874
bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_state *state, struct dml_mode_support_info_st *mode_support_info)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h
44
bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_state *state, struct dml_mode_support_info_st *mode_support_info);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h
46
bool dml2_svp_remove_all_phantom_pipes(struct dml2_context *ctx, struct dc_state *state);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h
48
bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc_state *context, enum dml_dram_clock_change_support pstate_change_type);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h
50
bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1146
static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1150
bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h
39
bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
133
unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, enum dml_output_encoder_class encoder, bool dsc_enabled)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
156
bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
169
bool is_dtbclk_required(const struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
216
static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
220
bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
511
bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc_state *display_state, struct dml2_helper_det_policy_scratch *det_scratch)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
515
bool need_recalculation = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
545
bool dml2_is_stereo_timing(const struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
547
bool is_stereo = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h
141
bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc_state *display_state, struct dml2_helper_det_policy_scratch *det_scratch);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h
40
unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, enum dml_output_encoder_class encoder, bool dsc_enabled);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h
45
bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h
46
bool dml2_is_stereo_timing(const struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h
84
bool dml2_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
115
static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrapper_optimize_configuration_params *p)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
121
bool optimization_done = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
235
static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
252
static bool does_configuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
255
bool pass = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
265
static bool dml_mode_support_wrapper(struct dml2_context *dml2,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
356
static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode validate_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
398
static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
405
bool need_recalculation = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
508
static bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
548
bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
551
bool out = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
626
bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c
677
bool dml2_create_copy(struct dml2_context **dst_dml2,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
110
bool is_gaming);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
111
bool (*allocate_mcache)(struct dc_state *context, const struct dc_mcache_params *mcache_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
116
bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
127
bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
128
bool (*remove_phantom_plane)(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
145
bool (*remove_phantom_streams_and_planes)(
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
211
bool use_native_pstate_optimization;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
212
bool enable_windowed_mpo_odm;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
213
bool use_native_soc_bb_construction;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
214
bool skip_hw_state_mapping;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
215
bool optimize_odm_4to1;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
216
bool minimize_dispclk_using_odm;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
217
bool override_det_buffer_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
220
bool force_disable_subvp;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
221
bool force_enable_subvp;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
235
bool force_pstate_method_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
238
bool map_dc_pipes_with_callbacks;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
240
bool use_clock_dc_limits;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
241
bool gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
242
bool force_tdlut_enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
258
bool dml2_create(const struct dc *in_dc,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
265
bool dml2_create_copy(struct dml2_context **dst_dml2,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
295
bool dml2_validate(const struct dc *in_dc,
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
67
bool p_state_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
74
bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
76
bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
77
bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
78
bool (*update_pipes_for_stream_with_slice_count)(
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
84
bool (*update_pipes_for_plane_with_slice_count)(
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
124
bool dpp1_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
264
bool is_float)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
290
bool is_float;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
292
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
507
bool dppclk_div,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
508
bool enable)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1371
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1397
bool dpp1_dscl_is_lb_conf_valid(
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1410
bool use_ram_a);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1424
bool is_ram_a);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1428
bool power_on);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1466
bool power_on);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1470
bool is_ram_a);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1507
bool dppclk_div,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1508
bool enable);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
1514
bool dpp1_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
387
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
421
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
644
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
691
bool use_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
702
static bool dpp1_degamma_ram_inuse(
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
704
bool *ram_a_inuse)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
706
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
727
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
756
bool is_ram_a = true;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
795
static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
796
bool *ram_a_inuse)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
798
bool in_use = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
832
bool rama_occupied = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
105
static bool dpp1_dscl_is_video_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
114
static bool dpp1_dscl_is_420_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
126
bool dbg_always_scale)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
159
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
281
bool chroma_coef_mode)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
283
bool h_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
284
bool v_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
285
bool h_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
286
bool v_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
289
bool coef_ram_current;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
314
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
450
bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
620
bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
110
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
406
bool dpp2_construct(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
437
bool alpha_en,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
79
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
691
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
692
bool dispclk_r_gate_disable;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
730
bool dpp20_program_blnd_lut(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
733
bool dpp20_program_shaper(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
737
bool dpp20_program_3dlut(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
752
bool alpha_en,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
775
bool dpp2_construct(struct dcn20_dpp *dpp2,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
784
bool power_on);
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1016
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1017
bool is_lut_size17x17x17)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1037
bool is_color_channel_12bits)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1115
bool dpp20_program_3dlut(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1120
bool is_17x17x17;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
1121
bool is_12bits_color_channel;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
120
bool is_ram_a = true;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
367
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
378
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
522
bool dpp20_program_blnd_lut(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
617
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
64
static bool dpp2_degamma_ram_inuse(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
66
bool *ram_a_inuse)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
68
bool ret = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
89
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
931
bool dpp20_program_shaper(
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
969
bool *is_17x17x17,
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
970
bool *is_12bits_color_channel)
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
190
static bool dpp201_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
297
bool dpp201_construct(
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
57
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h
71
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h
76
bool dpp201_construct(struct dcn201_dpp *dpp2,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1193
static bool dpp3_program_shaper(struct dpp *dpp_base,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1235
bool *is_17x17x17,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1236
bool *is_12bits_color_channel)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1283
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1284
bool is_lut_size17x17x17)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1304
bool is_color_channel_12bits)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1382
static bool dpp3_program_3dlut(struct dpp *dpp_base,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1386
bool is_17x17x17;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1387
bool is_12bits_color_channel;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1503
bool dpp3_construct(
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
1524
bool dpp3_should_bypass_post_csc_for_colorspace(enum dc_color_space dc_color_space)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
217
bool force_disable_cursor = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
418
bool dpp3_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
569
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
586
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
603
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
620
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
781
static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
879
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
574
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
575
bool dispclk_r_gate_disable;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
580
bool dpp3_construct(struct dcn3_dpp *dpp3,
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
587
bool dpp3_program_gamcor_lut(
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
597
bool dpp3_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
646
bool dpp3_should_bypass_post_csc_for_colorspace(
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
128
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
203
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
215
bool dpp3_program_gamcor_lut(
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
81
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c
146
bool dpp32_construct(
sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c
167
bool alpha_en,
sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h
31
bool dpp32_construct(struct dcn3_dpp *dpp3,
sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h
39
bool alpha_en,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
128
bool dpp35_construct(
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
134
bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
146
void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
42
bool dppclk_div,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
43
bool enable)
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
54
bool dppclk_div,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
55
bool enable);
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
57
bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx,
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
62
void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
261
bool dpp401_construct(
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
358
bool alpha_en,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
671
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
686
bool dpp401_construct(struct dcn401_dpp *dpp401,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
727
bool alpha_en,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
106
static bool dpp401_dscl_is_420_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1066
bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1068
bool program_isharp_1dlut = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
1069
bool bs_coeffs_updated = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
118
bool dbg_always_scale)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
151
bool power_on)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
273
bool chroma_coef_mode,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
274
bool force_coeffs_update)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
276
bool h_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
277
bool v_2tap_hardcode_coef_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
278
bool h_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
279
bool v_2tap_sharp_en = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
282
bool coef_ram_current;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
327
bool filter_updated = false;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
456
static bool dpp401_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
952
bool program_isharp_1dlut,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
953
bool *bs_coeffs_updated)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
97
static bool dpp401_dscl_is_video_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1045
static bool setup_dsc_config(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1063
bool is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1093
is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.RGB;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1098
is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_444;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1103
is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1107
is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1113
is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_420;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1131
is_dsc_possible = (bool)dsc_common_caps.color_depth.bits.COLOR_DEPTH_8_BPC;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1134
is_dsc_possible = (bool)dsc_common_caps.color_depth.bits.COLOR_DEPTH_10_BPC;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1137
is_dsc_possible = (bool)dsc_common_caps.color_depth.bits.COLOR_DEPTH_12_BPC;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1293
bool dc_dsc_compute_config(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1302
bool is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1321
uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1339
const bool is_dp)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1437
void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1442
void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
1447
void dc_set_disable_128b_132b_stream_overhead(bool disable)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
160
static bool decide_dsc_bandwidth_range(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
174
const bool is_dp);
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
181
static bool intersect_dsc_caps(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
187
static bool setup_dsc_config(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
197
static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
223
static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *line_buff_bit_depth)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
238
static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
299
static bool dsc_bpp_increment_div_from_dpcd(uint8_t bpp_increment_dpcd, uint32_t *bpp_increment_div)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
331
bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
45
static bool dsc_policy_enable_dsc_when_not_needed;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
458
bool dc_dsc_compute_bandwidth_range(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
468
bool is_dsc_possible = false;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
47
static bool dsc_policy_disable_dsc_stream_overhead;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
49
static bool disable_128b_132b_stream_overhead;
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
691
static bool intersect_dsc_caps(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
773
const bool is_dp)
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
797
static bool decide_dsc_bandwidth_range(
sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c
853
static bool decide_dsc_target_bpp_x16(
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
159
bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
185
bool is_config_ok;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
198
bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
200
bool is_config_ok;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
362
bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
454
enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
581
bool dsc_prepare_config(const struct dsc_config *dsc_cfg,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
586
bool is_ycbcr422_simple);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
604
bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
609
bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
109
void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h
57
void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
112
bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
126
bool is_config_ok;
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
390
void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
335
void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable);
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
338
bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
sys/dev/pci/drm/amd/display/dc/dsc/dsc.h
102
bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
sys/dev/pci/drm/amd/display/dc/dsc/dsc.h
105
bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
sys/dev/pci/drm/amd/display/dc/dsc/dsc.h
42
bool is_odm;
sys/dev/pci/drm/amd/display/dc/dsc/dsc.h
51
bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */
sys/dev/pci/drm/amd/display/dc/dsc/dsc.h
89
bool is_block_pred_supported;
sys/dev/pci/drm/amd/display/dc/dsc/dsc.h
96
bool is_dp;
sys/dev/pci/drm/amd/display/dc/dsc/rc_calc.c
45
bool is_navite_422_or_420;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
62
bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
64
struct pwl_params *lut_params, bool fixpoint);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
66
bool cm3_helper_convert_to_custom_float(
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
70
bool fixpoint);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
72
bool is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
119
bool dwb3_disable(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
155
bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
193
bool dwb3_is_enabled(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
221
bool is_new_content)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
46
static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
91
bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
884
bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
886
bool dwb3_disable(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
888
bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
890
bool dwb3_is_enabled(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
898
bool is_new_content);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
913
bool dwb3_ogam_set_input_transfer_func(
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
177
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
234
static bool dwb3_program_ogam_lut(
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
272
bool dwb3_ogam_set_input_transfer_func(
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
277
bool result = false;
sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c
54
void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable)
sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h
59
void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable);
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
181
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
186
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c
39
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
203
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
208
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
61
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
210
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
215
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
63
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
210
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
215
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c
63
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
203
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
208
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
61
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
192
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
197
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
65
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
188
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
193
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
64
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
199
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
204
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
72
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
189
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
194
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
65
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
170
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
175
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
63
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
154
static bool id_to_offset(
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
159
bool result = true;
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
38
static bool offset_to_id(
sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c
237
static bool is_pin_busy(
sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.c
57
bool dal_hw_factory_init(
sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h
72
bool dal_hw_factory_init(
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
60
bool dal_hw_gpio_open(
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h
105
bool mux_supported;
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h
118
bool dal_hw_gpio_open(
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h
44
bool opened;
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h
51
bool (*open)(
sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.c
61
bool dal_hw_translate_init(
sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h
30
bool (*offset_to_id)(
sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h
35
bool (*id_to_offset)(
sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h
45
bool dal_hw_translate_init(
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
112
bool supported;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
113
bool (*process_transaction)(
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
122
static bool hdmi_14_process_transaction(
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
127
bool result;
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
229
static bool dpcd_access_helper(
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
234
bool is_read)
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
315
static bool dp_11_process_transaction(
sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c
40
static const bool hdcp_cmd_is_read[HDCP_MESSAGE_ID_MAX] = {
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
439
static bool dcn31_hpo_dp_link_enc_is_in_alt_mode(
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
188
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
189
bool compressed_format,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
190
bool double_buffer_en)
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
550
bool enable,
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
552
bool immediate_update)
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
44
bool dcn32_hpo_dp_link_enc_is_in_alt_mode(
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h
57
bool dcn32_hpo_dp_link_enc_is_in_alt_mode(struct hpo_dp_link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h
65
bool dcn32_hpo_dp_link_enc_is_in_alt_mode(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
104
bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
116
bool hubbub1_verify_allow_pstate_change_high(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
131
static bool forced_pstate_allow; /* help with revert wa */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
243
bool hubbub1_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
247
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
251
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
357
bool hubbub1_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
361
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
365
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
502
bool hubbub1_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
506
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
510
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
583
bool hubbub1_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
587
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
590
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
682
void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
692
static bool hubbub1_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
698
bool standard_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
699
bool display_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
751
static bool hubbub1_dcc_support_pixel_format(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
802
bool *req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
803
bool *req128_vert_wc)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
825
static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
836
bool req128_horz_wc, req128_vert_wc;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
91
void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
477
bool hubbub1_verify_allow_pstate_change_high(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
482
bool hubbub1_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
486
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
488
void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
490
bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
495
void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
502
bool hubbub1_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
506
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
507
bool hubbub1_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
511
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
512
bool hubbub1_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
516
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
138
bool hubbub2_dcc_support_pixel_format(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
196
bool *req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
197
bool *req128_vert_wc)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
217
bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
226
bool req128_horz_wc, req128_vert_wc;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
56
bool hubbub2_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
592
static bool hubbub2_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
596
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
599
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
62
bool standard_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
63
bool display_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
64
bool render_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
108
bool hubbub2_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
114
bool hubbub2_dcc_support_pixel_format(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
118
bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
122
bool hubbub2_initialize_vmids(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
99
bool allow_sdpif_rate_limit_when_cstate_req;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
53
static bool hubbub201_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
57
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
60
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
141
bool hubbub21_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
145
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
149
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
335
bool hubbub21_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
339
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
343
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
488
bool hubbub21_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
492
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
497
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
574
bool hubbub21_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
578
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
581
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
128
bool hubbub21_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
132
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
133
bool hubbub21_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
137
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
138
bool hubbub21_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
142
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
143
bool hubbub21_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h
147
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
100
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
103
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
138
bool hubbub3_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
144
bool standard_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
145
bool display_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
146
bool render_swizzle = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
255
bool *req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
256
bool *req128_vert_wc)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
276
bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
285
bool req128_horz_wc, req128_vert_wc;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
392
bool force, bool allow)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
96
bool hubbub3_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
113
bool hubbub3_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
121
bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
125
bool hubbub3_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
129
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
132
bool force, bool allow);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
134
static void dcn31_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
173
static bool hubbub31_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
177
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
181
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
363
static bool hubbub31_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
367
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
371
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
636
static bool hubbub31_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
640
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
645
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
718
static bool hubbub31_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
722
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
724
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
783
bool *req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
784
bool *req128_vert_wc)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
804
static bool hubbub31_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
812
bool req128_horz_wc, req128_vert_wc;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
979
static bool hubbub31_verify_allow_pstate_change_high(struct hubbub *hubbub)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
991
static bool forced_pstate_allow; /* help with revert wa */
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
140
void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
177
bool hubbub32_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
181
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
185
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
367
bool hubbub32_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
371
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
375
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
513
bool hubbub32_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
517
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
522
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
666
bool hubbub32_program_usr_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
670
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
675
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
746
void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
76
static void hubbub32_set_sdp_control(struct hubbub *hubbub, bool dc_control)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
760
static bool hubbub32_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
764
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
767
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
119
bool hubbub32_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
123
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
125
bool hubbub32_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
129
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
131
bool hubbub32_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
135
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
137
bool hubbub32_program_usr_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
141
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
143
void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h
164
void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
112
static bool hubbub35_program_stutter_z8_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
116
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
120
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
298
bool hubbub35_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
302
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
304
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
512
static void hubbub35_set_fgcg(struct dcn20_hubbub *hubbub2, bool enable)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
74
void dcn35_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
161
bool hubbub35_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
165
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h
168
unsigned int compbuf_size_kb, bool safe_to_increase);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1150
static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1195
static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
1199
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
185
bool hubbub401_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
189
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
192
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
284
bool hubbub401_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
288
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
291
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
411
bool hubbub401_program_usr_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
415
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
418
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
450
static bool hubbub401_program_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
454
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
456
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
601
bool hubbub401_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
608
bool swizzle_supported = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
650
bool hubbub401_dcc_support_pixel_format(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
67
bool hubbub401_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
71
bool safe_to_lower)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
733
bool *p0_req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
734
bool *p0_req128_vert_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
735
bool *p1_req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
736
bool *p1_req128_vert_wc)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
74
bool wm_pending = false;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
827
bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
838
bool req128_horz_wc, req128_vert_wc;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
840
bool p1_req128_horz_wc, p1_req128_vert_wc, is_dual_plane;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
138
bool hubbub401_program_urgent_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
142
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
144
bool hubbub401_program_stutter_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
148
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
150
bool hubbub401_program_pstate_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
154
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
156
bool hubbub401_program_usr_watermarks(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
160
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
162
bool hubbub401_dcc_support_swizzle(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
169
bool hubbub401_dcc_support_pixel_format(
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
188
bool *p0_req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
189
bool *p0_req128_vert_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
190
bool *p1_req128_horz_wc,
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
191
bool *p1_req128_vert_wc);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h
192
bool hubbub401_get_dcc_compression_cap(
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
110
static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1298
void hubp1_clk_cntl(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1313
bool hubp1_in_blank(struct hubp *hubp)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1322
void hubp1_soft_reset(struct hubp *hubp, bool reset)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
206
bool horizontal_mirror)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
349
bool hubp1_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
352
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
41
void hubp1_set_blank(struct hubp *hubp, bool blank)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
535
void hubp1_dcc_control(struct hubp *hubp, bool enable,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
562
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
751
bool hubp1_is_flip_pending(struct hubp *hubp)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
81
static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
737
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
762
bool horizontal_mirror);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
770
bool enable,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
775
bool hubp1_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
778
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
780
bool hubp1_is_flip_pending(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
791
void hubp1_set_blank(struct hubp *hubp, bool blank);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
797
void hubp1_clk_cntl(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
818
bool hubp1_in_blank(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
819
void hubp1_soft_reset(struct hubp *hubp, bool reset);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1109
void hubp2_clk_cntl(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1700
bool hubp2_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
336
bool use_pitch_c = false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
379
bool horizontal_mirror)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
423
void hubp2_dcc_control(struct hubp *hubp, bool enable,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
557
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
717
bool hubp2_dmdata_status_done(struct hubp *hubp)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
726
bool hubp2_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
729
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
891
bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
895
bool tri_buffer_en;
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
905
bool hubp2_is_triplebuffer_enabled(
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
913
return (bool)triple_buffer_en;
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
916
void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
923
bool hubp2_is_flip_pending(struct hubp *hubp)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
951
void hubp2_set_blank(struct hubp *hubp, bool blank)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
961
void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
307
bool hubp2_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
343
bool hubp2_dmdata_status_done(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
347
bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
349
bool hubp2_is_triplebuffer_enabled(
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
352
void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
359
bool hubp2_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
362
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
364
void hubp2_dcc_control(struct hubp *hubp, bool enable,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
376
bool horizontal_mirror);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
389
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
392
bool hubp2_is_flip_pending(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
394
void hubp2_set_blank(struct hubp *hubp, bool blank);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
395
void hubp2_set_blank_regs(struct hubp *hubp, bool blank);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
402
void hubp2_clk_cntl(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
138
bool dcn201_hubp_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
49
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h
124
bool dcn201_hubp_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
698
static bool hubp21_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
701
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
846
bool hubp21_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h
114
bool hubp21_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
353
void hubp3_dcc_control(struct hubp *hubp, bool enable,
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
418
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
565
bool hubp3_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
68
bool hubp3_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
71
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
249
bool hubp3_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
260
bool hubp3_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
263
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
272
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
287
void hubp3_dcc_control(struct hubp *hubp, bool enable,
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
118
bool hubp31_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
42
void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
50
void hubp31_soft_reset(struct hubp *hubp, bool reset)
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
236
bool hubp31_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
244
void hubp31_soft_reset(struct hubp *hubp, bool reset);
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
246
void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
214
bool hubp32_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
42
void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
50
void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow)
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
59
void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
68
void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
47
void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
49
void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
51
void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
53
void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h
62
bool hubp32_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
179
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
226
bool hubp35_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
41
void hubp35_set_fgcg(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
51
bool hubp35_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
59
void hubp35_set_fgcg(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h
72
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1014
void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
1079
bool hubp401_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
167
void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
197
bool is_vready_at_or_after_vsync = false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
409
bool hubp401_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
412
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
59
void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
603
bool use_pitch_c = false;
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
636
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
720
bool hubp401_in_blank(struct hubp *hubp)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
259
void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
271
bool hubp401_program_surface_flip_and_addr(
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
274
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
297
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
308
bool hubp401_in_blank(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
317
bool hubp401_construct(
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
329
void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
344
void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
164
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
210
bool dce_use_lut(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
41
unsigned int fe_inst, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
49
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
91
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
1280
unsigned int inst, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
1284
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
1292
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
1296
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
1302
bool dce_use_lut(enum surface_pixel_format format);
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
156
bool clear_tiling)
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
72
bool dce100_enable_display_power_gating(
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
45
bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
51
bool clear_tiling);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1267
void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1921
bool can_apply_edp_fast_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1922
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1923
bool keep_edp_vdd_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
202
bool clock_gating)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
207
static bool dce110_enable_display_power_gating(
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2199
static bool should_enable_fbc(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2459
bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2460
bool is_hpo_acquired = resource_is_hpo_acquired(context);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2596
bool blank_target = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2682
static bool wait_for_reset_trigger_to_occur(
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2687
bool rc = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
283
static bool
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
290
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3184
bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3194
bool fw_set_brightness = true;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
330
static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
434
static bool
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
606
static bool
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
633
bool is_hdmi_tmds;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
634
bool is_dp;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
711
bool power_up)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
716
bool edp_hpd_high = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
784
bool power_up)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
951
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
968
bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h
61
void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h
80
bool power_up);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h
84
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h
88
bool power_up);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h
90
bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
113
static bool dce112_enable_display_power_gating(
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
151
static bool dce120_enable_display_power_gating(
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
251
bool dce121_xgmi_enabled(struct dce_hwseq *hws)
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h
34
bool dce121_xgmi_enabled(struct dce_hwseq *hws);
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
184
bool blank_target = false;
sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
50
static bool dce60_should_enable_fbc(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
101
void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1088
bool allow_self_fresh_force_enable = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1129
bool underflow;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1349
static bool dcn10_hw_wa_force_recovery(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1418
static bool should_log_hw_state; /* prevent hw state log by default */
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1574
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1575
bool tg_enabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1769
bool is_optimized_init_done = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1978
static bool patch_address_for_sbs_tb_stereo(
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1982
bool sec_split = pipe_ctx->top_pipe &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2008
bool addr_patched = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2031
bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2036
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2109
bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2150
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
221
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2238
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2264
static bool wait_for_reset_trigger_to_occur(
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2268
bool rc = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2305
bool checkUint32Bounary)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2308
bool ret = checkUint32Bounary == false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2353
static bool is_low_refresh_rate(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2363
bool account_low_refresh_rate)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2794
static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2891
bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2967
bool per_pixel_alpha =
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2988
bool should_divided_by_2 = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3142
bool blank)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3209
bool blank = !is_pipe_tree_visible(pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3480
bool non_stereo_timing = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3588
bool dcn10_dummy_display_power_gating(
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3601
bool flip_pending;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3658
bool pipe_split_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3659
bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
4129
bool clear_tiling)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
454
bool is_gamut_remap_available = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
813
bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
832
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
834
bool force_on = true; /* disable power gating */
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
897
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
958
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
100
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
103
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
147
bool dcn10_dummy_display_power_gating(
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
160
void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
174
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
179
bool power_up);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
182
bool power_up);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
196
bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
201
bool dcn10_disconnect_pipes(
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
219
bool clear_tiling);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
56
bool is_surface_update_only);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
63
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
64
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
68
bool blank);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
76
bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
78
bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
89
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
96
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1029
bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1069
bool dcn20_set_blend_lut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1073
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1089
bool dcn20_set_shaper_3dlut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1093
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1115
bool dcn20_set_input_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1122
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1123
bool use_degamma_ram = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1217
bool blank)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1394
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1397
bool flip_immediate = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1496
bool old_is_phantom = dc_state_get_pipe_subvp_type(old_state, old_pipe) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1497
bool new_is_phantom = dc_state_get_pipe_subvp_type(new_state, new_pipe) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1689
bool viewport_changed = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
220
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2224
bool is_dsc_ungated = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2484
bool dcn20_update_bandwidth(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2506
bool blank = !is_pipe_tree_visible(pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2579
bool dcn20_wait_for_blank_complete(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2602
bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2701
static bool patch_address_for_sbs_tb_stereo(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2705
bool sec_split = pipe_ctx->top_pipe &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2731
bool addr_patched = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2765
bool is_two_pixels_per_container =
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2937
bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
299
bool flip_immediate)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
309
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3109
bool enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
311
bool force_on = true; /* disable power gating */
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
395
bool enable_triple_buffer)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
477
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
554
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
636
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
752
bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
772
void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
778
int opp_cnt, bool is_two_pixels_per_container)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
780
bool hblank_halved = is_two_pixels_per_container;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
79
bool is_gamut_remap_available = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
842
bool interlace = stream->timing.flags.INTERLACE;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
846
bool is_two_pixels_per_container =
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
848
bool rate_control_2x_pclk = (interlace || is_two_pixels_per_container);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
101
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
105
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
109
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
113
bool enable_triple_buffer);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
122
bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
132
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
136
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
138
bool dcn20_wait_for_blank_complete(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
156
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
33
bool dcn20_set_blend_lut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
35
bool dcn20_set_shaper_3dlut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
45
bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
47
bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
61
bool blank);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
65
bool blank);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
69
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
76
bool dcn20_update_bandwidth(
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
135
bool addr_patched = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
386
bool mpcc_removed = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
426
bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
528
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
56
static bool patch_address_for_sbs_tb_stereo(
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
60
bool sec_split = pipe_ctx->top_pipe &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
85
static bool gpu_addr_to_uma(struct dce_hwseq *hwseq,
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
88
bool is_in_uma;
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h
42
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
140
bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
244
bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
288
bool dcn21_is_abm_supported(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
88
bool dcn21_s0i3_golden_init_wa(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h
37
bool dcn21_s0i3_golden_init_wa(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h
50
bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h
54
bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h
56
bool dcn21_is_abm_supported(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1103
bool dcn30_does_plane_fit_in_mall(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1143
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1209
bool pending_updates = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
231
bool dcn30_set_blend_lut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
235
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
253
static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
260
bool result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
313
bool dcn30_set_input_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
320
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
391
bool dcn30_set_output_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
398
bool ret = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
467
bool dcn30_mmhubbub_warmup(
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
77
bool is_gamut_remap_available = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
830
void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
853
bool is_hdmi_tmds;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
854
bool is_dp;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
887
bool enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
909
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
914
bool cursor_cache_enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
51
bool dcn30_mmhubbub_warmup(
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
59
bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
62
bool dcn30_set_input_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
68
bool dcn30_set_output_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
71
void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
75
bool dcn30_does_plane_fit_in_mall(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
81
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
95
bool blank_enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
102
void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
159
void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
45
void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h
31
void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h
32
void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h
33
void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c
46
void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c
51
void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c
56
void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c
61
void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h
32
void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h
33
void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h
34
void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h
35
void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
284
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
347
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
349
bool force_on = true; /* disable power gating */
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
380
bool is_hdmi_tmds;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
381
bool is_dp;
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
448
void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
660
void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
707
bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
38
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
42
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
49
void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
54
bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
56
bool dcn31_is_abm_supported(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h
59
void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
227
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
295
void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
297
bool force_on = true; /* disable power gating */
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
331
bool two_pix_per_container = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
384
static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
402
bool otg_disabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
455
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
545
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
72
static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
36
void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
38
void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
46
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h
50
void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1013
void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1030
bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1187
bool two_pix_per_container = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1247
bool otg_disabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1343
bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
135
bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
137
bool force_on = true; /* disable power gating */
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1481
bool dcn32_dsc_pg_status(
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1515
bool safe_to_disable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1522
bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
163
void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1717
static bool is_subvp_phantom_topology_transition_seamless(
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1735
bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1741
bool is_seamless = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1791
bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1819
struct dc_state *context, bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
197
static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
252
bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
258
bool mall_ss_unsupported = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
348
bool enable_subvp = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
373
bool lock,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
374
bool should_lock_all_pipes,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
376
bool subvp_prev_use)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
379
bool subvp_immediate_flip = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
380
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
424
bool lock = params->subvp_pipe_control_lock_fast_params.lock;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
425
bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
439
bool dcn32_set_mpc_shaper_3dlut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
446
bool result = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
476
bool dcn32_set_mcm_luts(
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
482
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
522
bool dcn32_set_input_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
531
bool result = true;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
562
bool dcn32_set_output_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
569
bool ret = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
671
bool cache_cursor = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
72
bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
106
bool dcn32_dsc_pg_status(
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
112
bool safe_to_disable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
122
bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
130
struct dc_state *context, bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
36
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
40
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
42
void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
44
bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
46
void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
50
bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
53
bool dcn32_set_input_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
57
bool dcn32_set_mpc_shaper_3dlut(
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
60
bool dcn32_set_output_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
74
void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
82
bool lock,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
83
bool should_lock_all_pipes,
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
85
bool subvp_prev_use);
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
92
bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1029
bool hpo_frl_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1030
bool hpo_dp_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
124
void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1300
struct pg_block_update *update_state, bool power_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
133
void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1490
static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1545
bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
327
static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
480
void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
491
void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
502
void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
563
bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
575
bool is_psr = link && !link->panel_config.psr.disable_psr &&
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
578
bool is_replay = link && link->replay_settings.replay_feature_enabled;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
626
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
627
bool tg_enabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
901
bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
925
bool hpo_frl_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
926
bool hpo_dp_stream_enc_acquired = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
100
bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
36
void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
38
void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
40
void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
42
void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
44
void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
46
void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
56
bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
75
struct pg_block_update *update_state, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
85
void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
89
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1005
void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1090
bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1094
bool mpc_combine_on = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1225
static bool dcn401_check_no_memory_request_for_cab(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1271
bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1276
bool mall_ss_unsupported = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1348
bool is_wait_needed = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1374
bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1480
bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1498
bool lock = params->fams2_global_control_lock_fast_params.lock;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1511
void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1513
bool fams2_required;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1698
struct dc_state *context, bool lock)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2399
bool dcn401_update_bandwidth(
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2421
bool blank = !is_pipe_tree_visible(pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2457
bool old_is_phantom = dc_state_get_pipe_subvp_type(old_state, old_pipe) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
2458
bool new_is_phantom = dc_state_get_pipe_subvp_type(new_state, new_pipe) == SUBVP_PHANTOM;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
378
bool lut1d_enable = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
408
bool lut_bank_a)
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
426
bool rval;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
611
bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
618
bool result;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
620
bool rval;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
664
bool dcn401_set_output_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
671
bool ret = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
725
bool *manual_mode,
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
770
bool manual_mode = false;
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
103
bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
38
bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
40
bool dcn401_set_output_transfer_func(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
55
bool lut_bank_a);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
56
void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
64
bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
78
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
79
void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
87
void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
123
bool power_on;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
153
bool is_required;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
154
bool lock;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
213
void (*edp_power_control)(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
214
void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
225
void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
244
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
246
struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
248
void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
249
void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
253
struct pipe_ctx *pipe, bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
255
struct dc_state *context, bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
257
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
258
void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
295
bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
299
void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
307
bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
369
bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
398
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
400
bool (*does_plane_fit_in_mall)(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
410
bool lock,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
411
bool should_lock_all_pipes,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
413
bool subvp_prev_use);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
418
bool (*is_abm_supported)(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
449
struct pg_block_update *update_state, bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
450
bool (*is_pipe_topology_transition_seamless)(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
457
bool lock);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
460
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
465
void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
489
bool hwss_wait_for_blank_complete(
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
54
bool lock;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
55
bool subvp_immediate_flip;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
61
bool lock;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
66
bool flip_immediate;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
72
bool enableTripleBuffer;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
105
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
108
bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
117
bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
121
bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
125
bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
129
bool clock_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
132
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
135
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
138
bool power_on);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
139
bool (*dsc_pg_status)(struct dce_hwseq *hws,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
146
bool (*s0i3_golden_init_wa)(struct dc *dc);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
152
bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
154
bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
156
bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
158
bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
162
void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
178
bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
185
bool lut_bank_a);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
187
void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
38
bool blnd_crtc_trigger;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
39
bool DEGVIDCN10_253;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
40
bool false_optc_underflow;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
41
bool DEGVIDCN10_254;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
42
bool DEGVIDCN21;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
43
bool disallow_self_refresh_during_multi_plane_transition;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
44
bool dp_hpo_and_otg_sequence;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
45
bool wait_hubpret_read_start_during_mpo_transition;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
49
bool DEGVIDCN10_253_applied;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
50
bool disallow_self_refresh_during_multi_plane_transition_applied;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
52
bool skip_blank_stream;
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
84
bool (*set_input_transfer_func)(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
87
bool (*set_output_transfer_func)(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
92
bool clock_gating);
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
93
bool (*enable_display_power_gating)(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h
99
bool blank);
sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h
138
static inline bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2)
sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h
143
static inline bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2)
sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h
148
static inline bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2)
sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h
153
static inline bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2)
sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h
158
static inline bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2)
sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h
163
static inline bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2)
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
118
bool use_external_clk;
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
162
bool (*cs_power_down)(
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
164
bool (*program_pix_clk)(
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
173
bool (*get_pixel_clk_frequency_100hz)(
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
177
bool (*override_dp_pix_clk)(
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
188
bool dp_clk_src;
sys/dev/pci/drm/amd/display/dc/inc/clock_source.h
69
bool hw_dso_n_dp_ref_clk;
sys/dev/pci/drm/amd/display/dc/inc/compressor.h
115
bool dynamic_fbc_buffer_alloc;
sys/dev/pci/drm/amd/display/dc/inc/compressor.h
75
bool (*is_fbc_enabled_in_hw)(struct compressor *cp,
sys/dev/pci/drm/amd/display/dc/inc/compressor.h
82
bool is_enabled;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
191
bool (*acquire_post_bldn_3dlut)(
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
198
bool (*release_post_bldn_3dlut)(
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
226
bool (*program_mcache_pipe_config)(struct dc_state *context,
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
236
bool dp_audio;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
237
bool hdmi_audio_on_dongle;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
238
bool hdmi_audio_native;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
258
bool i2c_hw_buffer_in_use;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
488
bool unbounded_req;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
499
bool has_vactive_margin;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
507
bool wait_is_required;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
523
bool is_stream_enc_acquired[MAX_PIPES * 2];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
524
bool is_audio_acquired[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
527
bool is_dsc_acquired[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
531
bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
534
bool is_mpc_3dlut_acquired[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
540
bool cpuc_state_change_enable;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
541
bool cpup_state_change_enable;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
542
bool stutter_mode_enable;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
543
bool nbp_state_change_enable;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
544
bool all_displays_in_sync;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
569
bool legacy_svp_drr_stream_index_valid;
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
692
bool os_request_force_ffu;
sys/dev/pci/drm/amd/display/dc/inc/custom_float.h
34
bool convert_to_custom_float_format(
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
138
bool large_cursor;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
140
bool dmif_pipe_en_fbc_chunk_tracker;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
147
bool display_write_back_supported;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
148
bool argb_compression_support;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
162
bool pre_downscaler_enabled;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
163
bool underlay_downscale_prefetch_enabled;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
166
bool graphics_lb_nodownscaling_multi_line_prefetching;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
179
bool limit_excessive_outstanding_dmif_requests;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
221
bool scatter_gather_enable;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
238
bool display_synchronization_enabled;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
247
bool d1_display_write_back_dwb_enable;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
250
bool increase_voltage_to_support_mclk_switch;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
251
bool cpup_state_change_enable;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
252
bool cpuc_state_change_enable;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
253
bool nbp_state_change_enable;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
254
bool stutter_mode_enable;
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
363
bool fbc_en[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
364
bool lpt_en[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
365
bool displays_match_flag[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
366
bool use_alpha[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
367
bool orthogonal_rotation[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
368
bool enable[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
369
bool access_one_channel_only[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
370
bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
371
bool interlace_mode[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
372
bool display_pstate_change_enable[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
373
bool line_buffer_prefetch[maximum_number_of_surfaces];
sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h
480
bool bw_calcs(
sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h
622
bool dcn_validate_bandwidth(
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
35
bool dmcu_is_running;
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
40
bool (*set_abm_level)(struct abm *abm, unsigned int abm_level);
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
41
bool (*set_abm_immediate_disable)(struct abm *abm, unsigned int panel_inst);
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
42
bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst);
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
47
bool (*set_backlight_level_pwm)(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
55
bool (*init_abm_config)(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
59
bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
60
bool (*save_restore)(
sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h
64
bool (*set_pipe_ex)(struct abm *abm,
sys/dev/pci/drm/amd/display/dc/inc/hw/audio.h
35
bool (*endpoint_valid)(struct audio *audio);
sys/dev/pci/drm/amd/display/dc/inc/hw/audio.h
63
bool enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
118
bool transaction_complete;
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
119
bool operation_succeeded;
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
123
bool mot;
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
143
bool transaction_complete;
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
144
bool operation_succeeded;
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
149
bool (*configure_timeout)(
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
154
bool (*acquire_engine)(
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
174
bool (*is_engine_available)(struct aux_engine *engine);
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
175
bool (*acquire)(
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
178
bool (*submit_request)(
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
181
bool middle_of_transaction);
sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h
98
bool acquire_reset;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
154
bool valid;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
158
bool valid;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
177
bool enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
287
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
294
bool (*is_ips_supported)(struct clk_mgr *clk_mgr);
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
307
bool (*are_clock_states_equal) (struct dc_clocks *a,
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
318
void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
334
bool (*is_smu_present)(struct clk_mgr *clk_mgr);
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
338
bool (*is_dc_mode_present)(struct clk_mgr *clk_mgr);
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
349
bool psr_allow_active_cache;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
350
bool force_smu_not_present;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h
351
bool dc_mode_softmax_enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
366
bool dfs_bypass_enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
368
bool dfs_bypass_active;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
382
bool ss_on_dprefclk;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
390
bool xgmi_enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
412
bool periodic_retraining_disabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
416
bool smu_present;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
420
bool dpm_present;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
421
bool pme_trigger_pending;
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
437
static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
442
static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
103
bool en);
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
112
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
141
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
147
bool force_enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
152
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
196
bool clock_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
79
bool dpp_clock_gated[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
92
bool is_hdmi;
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
166
bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
170
bool (*dcc_support_swizzle)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
176
bool (*dcc_support_swizzle_addr3)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
183
bool (*dcc_support_pixel_format_plane0_plane1)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
187
bool (*dcc_support_pixel_format)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
198
bool (*program_watermarks)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
202
bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
204
bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
205
void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
207
bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
215
void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
235
void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
237
void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
242
void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
244
bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower);
sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h
261
bool riommu_active;
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
56
bool auto_load_dmcu;
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
60
bool (*dmcu_init)(struct dmcu *dmcu);
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
61
bool (*load_iram)(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
65
void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
66
bool (*setup_psr)(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
74
bool (*is_dmcu_initialized)(struct dmcu *dmcu);
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
75
bool (*lock_phy)(struct dmcu *dmcu);
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
76
bool (*unlock_phy)(struct dmcu *dmcu);
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
77
bool (*send_edid_cea)(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
82
bool (*recv_amd_vsdb)(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h
86
bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset);
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
213
bool (*dpp_program_gamcor_lut)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
238
bool (*dpp_get_optimal_number_of_taps)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
257
bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
266
bool is_ram_a);
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
328
bool dppclk_div,
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
329
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
333
bool (*dpp_program_blnd_lut)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
336
bool (*dpp_program_shaper_lut)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
339
bool (*dpp_program_3dlut)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
60
bool disable_blnd_lut:1;
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
61
bool disable_3dlut:1;
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
62
bool disable_shaper:1;
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
63
bool disable_gamcor:1;
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
64
bool disable_dscl:1;
sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h
86
bool cm_bypass_mode;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
131
bool warmup_en; /* false: normal mode, true: enable pattern generator */
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
132
bool warmup_mode; /* false: 420, true: 444 */
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
133
bool warmup_depth; /* false: 8bit, true: 10bit */
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
161
bool status;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
163
bool dwb_output_black;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
166
bool dwb_is_efc_transition;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
167
bool dwb_is_drc;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
171
bool mvc_cfg;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
176
bool (*get_caps)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
180
bool (*enable)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
184
bool (*disable)(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
186
bool (*update)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
190
bool (*is_enabled)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
207
bool is_new_content);
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
214
bool (*dwb_get_mcifbuf_line)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
224
bool (*dwb_ogam_set_output_transfer_func)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
229
bool (*dwb_ogam_set_input_transfer_func)(
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
236
bool (*get_dwb_status)(
sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h
84
bool (*offset_to_id)(
sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h
89
bool (*id_to_offset)(
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
103
bool enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
129
bool power_gated;
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
150
bool tmz_surface;
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
151
bool immediate;
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
153
bool grph_stereo;
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
179
void (*dcc_control)(struct hubp *hubp, bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
189
bool (*hubp_program_surface_flip_and_addr)(
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
192
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
215
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
218
bool (*hubp_is_flip_pending)(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
220
void (*set_blank)(struct hubp *hubp, bool blank);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
221
void (*set_blank_regs)(struct hubp *hubp, bool blank);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
223
void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
236
void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
240
void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
252
bool (*dmdata_status_done)(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
255
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
257
bool (*hubp_is_triplebuffer_enabled)(
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
262
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
272
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
273
bool (*hubp_in_blank)(struct hubp *hubp);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
274
void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
278
void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
279
void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
280
void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
281
void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
283
bool lock);
sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h
298
void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
124
bool use_tetrahedral_9;
sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
125
bool use_12bits;
sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
196
bool force_hw_default;
sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
232
bool bias_and_scale_valid;
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
110
bool (*validate_output_with_stream)(
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
140
bool exit_link_training_required);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
145
bool connect);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
148
bool (*is_dig_enabled)(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
153
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
156
bool ready);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
158
bool (*fec_is_active)(struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
159
bool (*is_in_alt_mode) (struct link_encoder *enc);
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
189
bool valid;
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
273
bool (*is_in_alt_mode) (
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
73
bool hdmi_ycbcr420_supported;
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
74
bool dp_ycbcr420_supported;
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
75
bool fec_supported;
sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h
89
bool usbc_combo_phy;
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
112
void (*dcc_control)(struct mem_input *mem_input, bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
113
bool independent_64b_blks);
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
145
bool (*mem_input_program_surface_flip_and_addr)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
148
bool flip_immediate);
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
171
bool horizontal_mirror);
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
173
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
178
void (*set_blank)(struct mem_input *mi, bool blank);
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
179
void (*set_hubp_blank_en)(struct mem_input *mi, bool blank);
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
77
bool enhanced;
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
78
bool quad_dmif_buffer;
sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h
79
bool watermark_nb_pstate;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1035
bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1052
void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1071
bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1082
bool (*is_config_supported)(uint32_t width);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1084
bool lut_bank_a, bool enabled, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1087
bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1097
void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1100
bool lut_bank_a, bool enabled, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1102
bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1106
bool (*is_config_supported)(uint32_t width);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1108
void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
1110
bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
119
bool enabled;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
121
bool select_lut_bank_a;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
152
bool pre_multiplied_alpha;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
167
bool overlap_only;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
240
bool enable;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
244
bool frame_alt;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
246
bool field_alt;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
304
bool shared_bottom;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
330
bool cm_bypass_mode;
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
495
bool lock);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
752
bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
805
bool (*is_dwb_idle)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
828
bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
829
bool rate_2x_mode,
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
863
bool (*program_1dlut)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
882
bool (*program_shaper)(
sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h
915
bool (*program_3dlut)(
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
148
bool sign;
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
155
bool negative;
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
240
bool mpcc_disconnect_pending[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
330
bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
335
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
352
bool (*dpg_is_blanked)(
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
355
bool (*dpg_is_pending)(struct output_pixel_processor *opp);
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
365
bool is_primary);
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
370
bool is_primary);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
108
bool optc1_disable_crtc(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
110
bool optc1_is_counter_moving(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
130
bool enable_blanking);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
132
bool optc1_is_blanked(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
137
bool optc1_did_triggered_reset_occur(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
147
void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
162
bool optc1_is_stereo_left_eye(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
168
bool optc1_is_tg_enabled(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
170
bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
172
void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
174
void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
176
bool optc1_get_otg_active_size(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
184
bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
186
bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
193
bool program_fp2);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
195
bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
76
bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing);
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
78
bool optc1_validate_timing(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
89
bool use_vbios);
sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h
49
bool (*is_panel_backlight_on)(struct panel_cntl *panel_cntl);
sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h
50
bool (*is_panel_powered_on)(struct panel_cntl *panel_cntl);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
35
bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
36
bool pg_res_enable[PG_HW_RESOURCES_NUM_ELEMENT];
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
40
void (*dsc_pg_control)(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
41
void (*hubp_dpp_pg_control)(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
42
void (*hpo_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
43
void (*io_clk_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
44
void (*plane_otg_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
45
void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
46
void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
47
void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
48
void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
49
void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
50
void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
138
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
145
bool enable_audio);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
150
bool is_dual_link);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
193
struct stream_encoder *enc, bool mute);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
218
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
221
struct stream_encoder *enc, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
230
bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
238
bool (*dp_get_pixel_format)(
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
252
bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
254
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
257
bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
266
bool odm_combine);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
275
bool (*is_fifo_enabled)(struct stream_encoder *enc);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
319
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
320
bool compressed_format,
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
321
bool double_buffer_en);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
336
bool enable,
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
338
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h
76
bool adaptive_sync_line_num_valid;
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
142
bool continuous_mode;
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
143
bool enable;
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
146
bool reset;
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
199
bool (*validate_timing)(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
209
bool use_vbios
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
222
bool (*enable_crtc)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
223
bool (*disable_crtc)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
226
bool (*immediate_disable_crtc)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
227
bool (*is_counter_moving)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
238
bool (*get_otg_active_size)(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
241
bool (*is_matching_timing)(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
248
bool enable_blanking);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
249
bool (*is_blanked)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
257
bool (*did_triggered_reset_occur)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
274
bool enable, const struct dc_crtc_timing *timing);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
286
bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
294
void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
297
bool (*is_stereo_left_eye)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
299
void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
302
bool (*is_tg_enabled)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
303
bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
313
bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
319
bool (*configure_crc)(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
326
bool (*get_crc)(struct timing_generator *tg, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
331
bool (*get_hw_timing)(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
335
const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
352
void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
368
bool (*validate_vmin_vmax)(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
370
bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
378
bool (*get_optc_double_buffer_pending)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
379
bool (*get_otg_double_buffer_pending)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
380
bool (*get_pipe_update_pending)(struct timing_generator *tg);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
381
void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
382
bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
64
bool immediate_flip;
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
139
bool alpha_en;
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
140
bool pixel_expan_mode;
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
141
bool interleave_en;
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
180
bool (*transform_get_optimal_number_of_taps)(
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
199
bool power_on);
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
208
bool is_ram_a);
sys/dev/pci/drm/amd/display/dc/inc/hw/vpg.h
38
bool immediate_update);
sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h
108
bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h
111
bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
sys/dev/pci/drm/amd/display/dc/inc/link_enc_cfg.h
77
bool link_enc_cfg_is_transmitter_mappable(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
107
bool (*detect_link)(struct dc_link *link, enum dc_detect_reason reason);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
108
bool (*detect_connection_type)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
116
bool (*get_hpd_state)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
122
void (*enable_hpd_filter)(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
123
bool (*reset_cur_dp_mst_topology)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
125
bool (*is_hdcp1x_supported)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
127
bool (*is_hdcp2x_supported)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
162
void (*blank_dp_stream)(struct dc_link *link, bool hw_init);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
167
void (*set_dsc_on_stream)(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
168
bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
169
bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
176
bool (*query_ddc_data)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
186
bool (*configure_fixed_vs_pe_retimer)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
190
bool (*aux_transfer_with_retries_no_mutex)(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
192
bool (*is_in_aux_transaction_mode)(struct ddc_service *ddc);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
197
bool (*dp_is_sink_present)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
198
bool (*dp_is_fec_supported)(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
199
bool (*dp_is_128b_132b_signal)(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
200
bool (*dp_get_max_link_enc_cap)(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
206
bool (*dp_should_enable_fec)(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
207
bool (*dp_decide_link_settings)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
215
bool (*edp_decide_link_settings)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
218
bool (*dp_overwrite_extended_receiver_cap)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
223
bool *auxless_support,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
224
bool *auxwake_support);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
233
void (*dpcd_write_rx_power_ctrl)(struct dc_link *link, bool on);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
237
bool (*dp_parse_link_loss_status)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
240
bool (*dp_should_allow_hpd_rx_irq)(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
245
bool (*dp_handle_hpd_rx_irq)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
247
bool *out_link_loss,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
248
bool defer_handling, bool *has_left_work);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
253
struct dc_link *link, bool wait_for_hpd);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
255
bool (*edp_get_backlight_level_nits)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
258
bool (*edp_set_backlight_level)(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
260
bool (*edp_set_backlight_level_nits)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
261
bool isHDR,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
265
bool (*edp_get_psr_state)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
267
bool (*edp_set_psr_allow_active)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
269
const bool *allow_active,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
270
bool wait,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
271
bool force_static,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
273
bool (*edp_setup_psr)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
277
bool (*edp_set_sink_vtotal_in_psr_active)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
284
bool (*edp_get_replay_state)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
286
bool (*edp_set_replay_allow_active)(struct dc_link *dc_link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
287
const bool *enable, bool wait, bool force_static,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
289
bool (*edp_setup_replay)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
291
bool (*edp_send_replay_cmd)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
294
bool (*edp_set_coasting_vtotal)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
296
bool (*edp_replay_residency)(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
297
unsigned int *residency, const bool is_start,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
299
bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
302
bool (*edp_wait_for_t12)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
303
bool (*edp_is_ilr_optimization_required)(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
305
bool (*edp_backlight_enable_aux)(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
307
bool (*edp_receiver_ready_T9)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
308
bool (*edp_receiver_ready_T7)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
309
bool (*edp_power_alpm_dpcd_enable)(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
310
void (*edp_set_panel_power)(struct dc_link *link, bool powerOn);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
315
bool (*dp_set_test_pattern)(
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
329
bool skip_immediate_retrain);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
333
bool (*dp_trace_is_initialized)(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
335
bool in_detection,
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
336
bool is_logged);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
337
bool (*dp_trace_is_logged)(struct dc_link *link, bool in_detection);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
339
struct dc_link *link, bool in_detection);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
341
struct dc_link *link, bool in_detection);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
344
bool power_up);
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
89
bool is_dpia_link;
sys/dev/pci/drm/amd/display/dc/inc/link_service.h
96
bool is_dpia_link;
sys/dev/pci/drm/amd/display/dc/inc/resource.h
117
bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
140
bool resource_are_streams_timing_synchronizable(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
144
bool resource_are_vblanks_synchronizable(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
156
bool resource_attach_surfaces_to_context(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
163
bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
286
bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
310
bool resource_append_dpp_pipes_for_plane_composition(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
342
bool resource_update_pipes_for_stream_with_slice_count(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
366
bool resource_update_pipes_for_plane_with_slice_count(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
463
bool is_last_segment);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
466
bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
sys/dev/pci/drm/amd/display/dc/inc/resource.h
476
bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,
sys/dev/pci/drm/amd/display/dc/inc/resource.h
570
bool resource_validate_attach_surfaces(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
587
bool pipe_need_reprogram(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
598
bool acquired);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
602
bool get_temp_dp_link_res(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/inc/resource.h
622
bool is_h_timing_divisible_by_2(struct dc_stream_state *stream);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
624
bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
sys/dev/pci/drm/amd/display/dc/inc/resource.h
629
bool odm);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
656
bool resource_is_hpo_acquired(struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
96
bool resource_construct(
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
182
bool dal_irq_service_dummy_set(struct irq_service *irq_service,
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
184
bool enable)
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
192
bool dal_irq_service_dummy_ack(struct irq_service *irq_service,
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
202
bool dce110_vblank_set(struct irq_service *irq_service,
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
204
bool enable)
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
42
static bool hpd_ack(struct irq_service *irq_service,
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
39
bool dal_irq_service_dummy_set(
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
42
bool enable);
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
44
bool dal_irq_service_dummy_ack(
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
48
bool dce110_vblank_set(
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
51
bool enable);
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
108
bool dal_irq_service_set(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
111
bool enable)
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
152
bool dal_irq_service_ack(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
191
bool hpd0_ack(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
218
bool hpd1_ack(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.c
98
bool enable)
sys/dev/pci/drm/amd/display/dc/irq/irq_service.h
37
bool (*set)(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.h
40
bool enable);
sys/dev/pci/drm/amd/display/dc/irq/irq_service.h
41
bool (*ack)(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.h
83
bool enable);
sys/dev/pci/drm/amd/display/dc/irq/irq_service.h
85
bool hpd0_ack(
sys/dev/pci/drm/amd/display/dc/irq/irq_service.h
89
bool hpd1_ack(
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
188
static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
646
bool dp_set_test_pattern(
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
67
bool skip_video_pattern)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
72
bool dpms_off = false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
73
bool needs_divider_update = false;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
74
bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
75
bool is_hpo_acquired;
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
998
bool skip_immediate_retrain)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.h
29
bool dp_set_test_pattern(
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.h
43
bool skip_immediate_retrain);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
107
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
116
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
125
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
134
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
148
bool power_up)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
39
bool dp_trace_is_initialized(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
61
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
70
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
79
bool in_detection,
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
80
bool is_logged)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
88
bool dp_trace_is_logged(struct dc_link *link, bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.c
98
bool in_detection)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
31
bool dp_trace_is_initialized(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
37
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
39
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
41
bool in_detection,
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
42
bool is_logged);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
43
bool dp_trace_is_logged(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
44
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
47
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
49
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
51
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
53
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
55
bool in_detection);
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_trace.h
58
bool power_up);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c
327
bool can_use_dio_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h
33
bool can_use_dio_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
191
bool requires_fixed_vs_pe_retimer_dio_link_hwss(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
74
static bool set_dio_fixed_vs_pe_retimer_dp_link_test_pattern_override(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h
34
bool requires_fixed_vs_pe_retimer_dio_link_hwss(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
164
bool can_use_dpia_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dpia.h
34
bool can_use_dpia_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
218
bool can_use_hpo_dp_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h
58
bool can_use_hpo_dp_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
122
static bool dp_hpo_fixed_vs_pe_retimer_set_override_test_pattern(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
225
bool requires_fixed_vs_pe_retimer_hpo_link_hwss(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h
30
bool requires_fixed_vs_pe_retimer_hpo_link_hwss(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1245
bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1293
bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1295
bool is_local_sink_detect_success;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1296
bool is_delegated_to_mst_top_mgr = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1326
bool link_is_hdcp14(struct dc_link *link, enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1328
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1350
bool link_is_hdcp22(struct dc_link *link, enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1352
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
1379
static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
284
static bool i2c_read(
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
325
bool is_valid_hdmi_signature;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
328
bool is_type2_dongle = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
586
static bool detect_dp(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
623
static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
635
static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
644
bool is_in_alt_mode;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
720
static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
741
bool link_reset_cur_dp_mst_topology(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
752
static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
756
bool can_apply_seamless_boot = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
783
bool should_prepare_phy_clocks =
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
818
static bool should_verify_link_capability_destructively(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
821
bool destrictive = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
823
bool is_link_enc_unavailable = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
870
static bool detect_link_and_local_sink(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
876
bool converter_disable_audio = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
878
bool same_edid = false;
sys/dev/pci/drm/amd/display/dc/link/link_detection.h
29
bool link_detect(struct dc_link *link, enum dc_detect_reason reason);
sys/dev/pci/drm/amd/display/dc/link/link_detection.h
30
bool link_detect_connection_type(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_detection.h
38
bool link_reset_cur_dp_mst_topology(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/link_detection.h
40
bool link_is_hdcp14(struct dc_link *link, enum amd_signal_type signal);
sys/dev/pci/drm/amd/display/dc/link/link_detection.h
41
bool link_is_hdcp22(struct dc_link *link, enum amd_signal_type signal);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1010
bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1013
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1034
bool link_update_dsc_config(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1199
static bool poll_for_allocation_change_trigger(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
120
void link_blank_dp_stream(struct dc_link *link, bool hw_init)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1337
bool mst_mode = (link->type == dc_connection_mst_branch);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1548
static bool write_128b_132b_sst_payload_allocation_table(
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1552
bool allocate)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1556
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
157
bool dpms_off = true;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1657
bool allocate)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
195
static bool is_master_pipe_for_link(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1970
bool is_over_340mhz = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
1971
bool is_vga_mode = (stream->timing.h_addressable == 640)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2041
bool skip_video_pattern;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2045
bool fec_enable;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2047
bool apply_seamless_boot_optimization = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2051
bool do_fallback = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
225
static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2278
static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
229
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2325
static bool allocate_usb4_bandwidth(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2327
bool ret;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2337
static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2339
bool ret;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
2467
bool apply_edp_fast_boot_optimization =
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
322
static bool write_i2c(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
350
bool is_vga_mode,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
351
bool is_over_340mhz,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
360
bool i2c_success = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
512
bool is_vga_mode,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
513
bool is_over_340mhz)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
517
bool i2c_success = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
635
bool is_over_340mhz)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
639
bool i2c_success = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
662
static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
727
static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
737
static void enable_mst_on_sink(struct dc_link *link, bool enable)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
772
static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
776
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
785
static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
789
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
802
void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
822
bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
946
bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
37
void link_blank_dp_stream(struct dc_link *link, bool hw_init);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
45
bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx,
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
46
bool enable, bool immediate_update);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
50
void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
51
bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
52
bool link_update_dsc_config(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
454
static bool construct_phy(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
760
static bool construct_dpia(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_factory.c
829
static bool link_construct(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c
53
bool can_use_hpo_frl_link_hwss(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
274
static bool dp_validate_mode_timing(
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
306
bool is_max_uncompressed_pixel_rate_exceeded = link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid &&
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
426
bool is_new_slot = false;
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
491
bool is_mst)
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
512
bool is_mst)
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
56
static bool dp_active_dongle_validate_timing(
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
562
const bool is_mst = (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
192
bool link_is_in_aux_transaction_mode(struct ddc_service *ddc)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
275
static bool submit_aux_command(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
279
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
289
bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
313
bool link_query_ddc_data(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
321
bool success = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
459
bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
477
bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
495
bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
502
bool try_to_configure_aux_timeout(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
505
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
54
static bool i2c_payloads_create(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
542
bool lte_340_scramble)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
544
bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c
91
bool write)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
51
bool link_is_in_aux_transaction_mode(struct ddc_service *ddc);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
53
bool try_to_configure_aux_timeout(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
56
bool link_query_ddc_data(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
72
bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
75
bool link_configure_fixed_vs_pe_retimer(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
80
bool link_query_fixed_vs_pe_retimer(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h
92
bool lte_340_scramble);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
107
bool is_dp_active_dongle(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
113
bool is_dp_branch_device(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1322
bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1481
static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1516
bool read_is_mst_supported(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1518
bool mst = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1549
static bool dpcd_read_sink_ext_caps(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1578
bool is_lttpr_present;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1583
bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1679
static bool retrieve_link_cap(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1698
bool is_fec_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1699
bool is_dsc_basic_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
1700
bool is_dsc_passthrough_supported = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2081
bool detect_dp_sink_caps(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2207
bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2250
bool is_uhbr13_5_supported = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2337
static bool dp_verify_link_cap(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2344
bool success = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2345
bool skip_video_pattern;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2404
bool dp_verify_link_cap_with_retries(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2410
bool success = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2458
bool dp_is_sink_present(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2468
bool present =
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2526
bool *auxless_support,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2527
bool *auxwake_support)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
2529
bool lttpr_present = dp_is_lttpr_present(link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
338
bool dp_is_fec_supported(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
356
bool dp_should_enable_fec(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
358
bool force_disable = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
376
bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
385
bool dp_is_lttpr_present(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
389
bool is_lttpr_present = (lttpr_count > 0 &&
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
471
static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
476
static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
588
static bool decide_fallback_link_setting_max_bw_policy(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
595
bool found = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
646
bool decide_fallback_link_setting(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
720
static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
762
bool edp_decide_link_settings(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
812
bool decide_edp_link_settings_with_dsc(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
941
static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c
947
bool link_decide_link_settings(struct dc_stream_state *stream,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
102
bool dp_verify_link_cap_with_retries(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
109
bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
114
bool *auxless_support,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
115
bool *auxwake_support);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
31
bool detect_dp_sink_caps(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
37
bool dp_get_max_link_enc_cap(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
54
bool dp_is_sink_present(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
56
bool dp_is_lttpr_present(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
58
bool dp_is_fec_supported(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
60
bool is_dp_active_dongle(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
62
bool is_dp_branch_device(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
66
bool dp_should_enable_fec(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
68
bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
77
bool link_decide_link_settings(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
81
bool edp_decide_link_settings(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
84
bool decide_edp_link_settings_with_dsc(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
94
bool read_is_mst_supported(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h
96
bool decide_fallback_link_setting(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c
114
bool dpia_query_hpd_status(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.h
40
bool dpia_query_hpd_status(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
223
bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
225
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
362
bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
370
bool is_success = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
49
static bool link_dp_is_bw_alloc_available(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h
109
bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h
42
bool is_valid;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h
58
bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
122
static bool handle_hpd_irq_psr_sink(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
156
bool allow_active;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
193
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
228
bool allow_active;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
395
bool dp_should_allow_hpd_rx_irq(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
410
bool dp_handle_hpd_rx_irq(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
411
union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
412
bool defer_handling, bool *has_left_work)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
417
bool status = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
46
bool dp_parse_link_loss_status(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
54
bool sink_status_changed;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
55
bool return_code;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h
30
bool dp_parse_link_loss_status(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h
33
bool dp_should_allow_hpd_rx_irq(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h
38
bool dp_handle_hpd_rx_irq(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h
39
union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h
40
bool defer_handling, bool *has_left_work);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
138
enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
180
void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
44
void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c
91
static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.h
53
const struct link_resource *link_res, bool ready);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.h
56
const struct link_resource *link_res, bool enable);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.h
58
void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1235
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1384
bool dp_set_hw_training_pattern(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1420
static bool perform_post_lt_adj_req_sequence(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1430
bool req_drv_setting_changed;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1558
bool skip_video_pattern)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1618
bool perform_link_training_with_retries(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1620
bool skip_video_pattern,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1624
bool do_fallback)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1636
bool is_link_bw_low = false; /* link bandwidth < stream bandwidth */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
1637
bool is_link_bw_min = /* RBR x 1 */
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
457
bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
462
bool dp_is_max_vs_reached(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
477
bool dp_is_cr_done(enum dc_lane_count ln_count,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
480
bool done = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
491
bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
494
bool done = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
502
bool dp_is_symbol_locked(enum dc_lane_count ln_count,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
505
bool locked = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
513
bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
518
bool dp_check_interlane_aligned(union lane_align_status_updated align_status,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
547
bool dp_check_dpcd_reqeust_status(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
140
bool dp_is_cr_done(enum dc_lane_count ln_count,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
143
bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
145
bool dp_is_symbol_locked(enum dc_lane_count ln_count,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
147
bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
149
bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
151
bool dp_is_max_vs_reached(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
188
bool dp_check_interlane_aligned(union lane_align_status_updated align_status,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
198
bool dp_check_dpcd_reqeust_status(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
31
bool perform_link_training_with_retries(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
33
bool skip_video_pattern,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
37
bool do_fallback);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
43
bool skip_video_pattern);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h
45
bool dp_set_hw_training_pattern(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
157
bool is_lttpr_present = dp_is_lttpr_present(link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
158
bool vbios_lttpr_force_non_transparent = link->dc->caps.vbios_lttpr_enable;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
159
bool vbios_lttpr_aware = link->dc->caps.vbios_lttpr_aware;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c
33
bool dp_perform_link_training_skip_aux(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.h
31
bool dp_perform_link_training_skip_aux(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
104
bool fec_enable;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
992
bool skip_video_pattern)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h
42
bool skip_video_pattern);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
109
bool apply_toggle_rate_wa = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c
103
static inline bool do_addresses_intersect_with_range(
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1088
bool edp_send_replay_cmd(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1113
bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1133
bool edp_replay_residency(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1134
unsigned int *residency, const bool is_start, const enum pr_residency_mode mode)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1154
bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1205
bool fw_set_brightness = true;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1228
bool is_smartmux_suported(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1239
struct link_resource *link_res, bool enable)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1242
bool use_hpo_dp_link_enc = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1276
enum dp_panel_mode *panel_mode, bool enable)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1292
bool result;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
155
bool edp_set_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
156
bool isHDR,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
237
bool edp_get_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
269
bool edp_backlight_enable_aux(struct dc_link *link, bool enable)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
288
static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
312
bool set_default_brightness_aux(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
329
bool edp_is_ilr_optimization_enabled(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
349
bool edp_is_ilr_optimization_required(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
398
void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
410
void edp_set_panel_power(struct dc_link *link, bool powerOn)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
438
bool edp_wait_for_t12(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
455
bool edp_receiver_ready_T9(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
480
bool edp_receiver_ready_T7(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
515
bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
517
bool ret = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
549
bool edp_set_backlight_level(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
56
bool panel_mode_edp = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
584
bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
585
bool wait, bool force_static, const unsigned int *power_opts)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
633
bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
688
bool edp_setup_psr(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
923
bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
936
bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
937
bool wait, bool force_static, const unsigned int *power_opts)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
970
bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
987
bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
32
bool set_default_brightness_aux(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
33
bool is_smartmux_suported(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
34
void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
36
bool edp_get_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
39
bool edp_set_backlight_level(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
41
bool edp_set_backlight_level_nits(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
42
bool isHDR,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
46
bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
47
bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
48
bool wait, bool force_static, const unsigned int *power_opts);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
49
bool edp_setup_psr(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
52
bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
55
bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
56
bool wait, bool force_static, const unsigned int *power_opts);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
57
bool edp_setup_replay(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
59
bool edp_send_replay_cmd(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
62
bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
63
bool edp_replay_residency(const struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
64
unsigned int *residency, const bool is_start, const enum pr_residency_mode mode);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
65
bool edp_get_replay_state(const struct dc_link *link, uint64_t *state);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
66
bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
68
bool edp_wait_for_t12(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
69
bool edp_is_ilr_optimization_required(struct dc_link *link,
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
71
bool edp_is_ilr_optimization_enabled(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
73
bool edp_backlight_enable_aux(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
75
bool edp_receiver_ready_T9(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
76
bool edp_receiver_ready_T7(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
77
bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
78
void edp_set_panel_power(struct dc_link *link, bool powerOn);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
80
enum dp_panel_mode *panel_mode, bool enable);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
120
bool query_hpd_status(struct dc_link *link, uint32_t *is_hpd_high)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
176
bool program_hpd_filter(const struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
178
bool result = false;
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
36
bool link_get_hpd_state(struct dc_link *link)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c
63
void link_enable_hpd_filter(struct dc_link *link, bool enable)
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h
41
bool program_hpd_filter(const struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h
45
bool dpia_query_hpd_status(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h
46
bool query_hpd_status(struct dc_link *link, uint32_t *is_hpd_high);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h
47
bool link_get_hpd_state(struct dc_link *link);
sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h
53
void link_enable_hpd_filter(struct dc_link *link, bool enable);
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c
56
void dcn35_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled)
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
73
void dcn35_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled);
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
277
bool found = false;
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
460
void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
197
void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
274
bool power_on)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
285
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
311
void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
116
bool enable,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
117
bool rate_2x_mode,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1218
bool mpc3_program_3dlut(
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1224
bool is_17x17x17;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1225
bool is_12bits_color_channel;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
170
bool power_on)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
190
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
475
bool is_ram_a,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
77
bool mpc3_is_dwb_idle(
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
823
bool power_on)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
863
bool mpc3_program_shaper(
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
907
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
908
bool is_lut_size17x17x17,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
928
bool *is_17x17x17,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
929
bool *is_12bits_color_channel,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
974
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1017
bool mpc3_program_shaper(
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1022
bool mpc3_program_3dlut(
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1084
bool mpc3_is_dwb_idle(
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1091
bool enable,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1092
bool rate_2x_mode,
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
1097
bool power_on);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
127
bool is_ram_a)
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
261
bool mpc32_program_post1dlut(
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
330
bool is_ram_a,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
685
bool power_on)
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
70
bool power_on)
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
712
bool mpc32_program_shaper(
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
755
bool *is_17x17x17,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
756
bool *is_12bits_color_channel,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
802
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
883
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
884
bool is_lut_size17x17x17,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
907
bool mpc32_program_3dlut(
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
913
bool is_17x17x17;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
914
bool is_12bits_color_channel;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
312
bool mpc32_program_3dlut(
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
316
bool mpc32_program_post1dlut(
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
320
bool mpc32_program_shaper(
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
336
bool power_on);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
353
bool is_ram_a);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
369
bool is_ram_a,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
374
bool power_on);
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
392
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
398
bool is_color_channel_12bits,
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
399
bool is_lut_size17x17x17,
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
111
void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id)
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
116
bool is_17x17x17;
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
117
bool is_12bits_color_channel;
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
229
bool lut_bank_a,
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
272
void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id)
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
68
bool *is_17x17x17,
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
69
bool *is_12bits_color_channel,
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
209
bool lut_bank_a, int mpcc_id);
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
215
bool lut_bank_a,
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
221
bool lut_bank_a,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
164
bool force_chroma_subsampling_1tap =
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
325
bool enable,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
367
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
157
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
184
bool enable,
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h
187
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
324
bool opp2_dpg_is_blanked(struct output_pixel_processor *opp)
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
341
bool opp2_dpg_is_pending(struct output_pixel_processor *opp)
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
357
bool is_primary)
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
370
enum dc_pixel_encoding pixel_encoding, bool is_primary)
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
136
bool is_write_to_ram_a_safe;
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
160
bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
162
bool opp2_dpg_is_pending(struct output_pixel_processor *opp);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
170
enum dc_pixel_encoding pixel_encoding, bool is_primary);
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
173
enum dc_pixel_encoding pixel_encoding, bool is_primary);
sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c
50
void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable)
sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.h
65
void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1291
bool optc1_is_stereo_left_eye(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1293
bool ret = false;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1307
bool optc1_get_hw_timing(struct timing_generator *tg,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1398
bool optc1_get_otg_active_size(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1443
bool optc1_is_tg_enabled(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1454
bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1466
bool optc1_configure_crc(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1560
bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1612
bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1614
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
165
bool use_vbios)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
346
const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
390
void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
411
void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
461
bool enable_blanking)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
469
bool optc1_is_blanked(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
482
void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
523
static bool optc1_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
555
bool optc1_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
590
bool optc1_validate_timing(
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
710
bool optc1_is_counter_moving(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
724
bool optc1_did_triggered_reset_occur(
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
48
bool optc2_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
485
bool optc2_configure_crc(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
126
bool optc2_configure_crc(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
92
bool optc2_enable_crtc(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
68
static bool optc201_validate_timing(
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
275
bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
288
bool optc3_get_otg_update_pending(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
301
bool optc3_get_pipe_update_pending(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
327
static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
356
void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
365
bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
366
bool optc3_get_otg_update_pending(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
367
bool optc3_get_pipe_update_pending(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
121
static bool optc31_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
155
bool optc31_immediate_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
95
static bool optc31_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
268
bool optc31_immediate_disable_crtc(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
105
static bool optc314_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
131
static bool optc314_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
186
static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
131
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
145
static bool optc32_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
171
static bool optc32_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
189
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
112
static bool optc35_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
138
static bool optc35_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
183
static bool optc35_configure_crc(struct timing_generator *optc,
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
534
void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
79
void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
165
void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
180
bool optc401_enable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
206
bool optc401_disable_crtc(struct timing_generator *optc)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
321
bool program_manual_trigger = false;
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
438
void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
450
bool optc401_wait_update_lock_status(struct timing_generator *tg, bool locked)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
59
bool first_preferred_memory_for_opp[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
60
bool second_preferred_memory_for_opp[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
183
bool optc401_enable_crtc(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
184
bool optc401_disable_crtc(struct timing_generator *optc);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
191
void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
193
bool optc401_wait_update_lock_status(struct timing_generator *tg, bool locked);
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
194
void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
145
static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
175
void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
181
bool block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
182
bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
238
static bool pg_cntl35_hpo_pg_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
249
void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
256
bool block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
286
static bool pg_cntl35_io_clk_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
297
void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
304
bool block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
336
static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
348
unsigned int mpcc_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
358
unsigned int opp_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
368
unsigned int optc_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
377
void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
384
bool block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
385
bool all_mpcc_disabled = true, all_opp_disabled = true;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
386
bool all_optc_disabled = true, all_stream_disabled = true;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
442
void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
450
static bool pg_cntl35_mem_status(struct pg_cntl *pg_cntl)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
464
bool block_enabled;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
47
static bool pg_cntl35_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
498
bool block_enabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
561
memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
562
memset(base->pg_res_enable, 0, PG_HW_RESOURCES_NUM_ELEMENT * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
76
void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
82
bool block_enabled = false;
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
83
bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
172
void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
174
unsigned int hubp_dpp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
175
void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
176
void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
177
void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
179
unsigned int mpcc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
181
unsigned int opp_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
183
unsigned int optc_inst, bool power_on);
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h
184
void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
732
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
846
bool at_least_one_pipe = false;
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
881
static bool dce100_validate_surface_sets(
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
999
static bool dce100_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1047
static bool dce110_validate_surface_sets(
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1245
static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
1349
static bool dce110_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
776
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
929
static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
968
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
1223
static bool dce112_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
752
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
891
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
993
static bool dce112_validate_surface_sets(
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1059
static bool dce120_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
1070
bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
538
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
564
static bool dce120_hw_sequencer_create(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1085
static bool dce61_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
1283
static bool dce64_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
758
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
887
static bool dce60_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1095
static bool dce81_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
1295
static bool dce83_construct(
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
764
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
893
static bool dce80_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1110
static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1134
bool voltage_supported;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1156
bool video_down_scaled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1157
bool video_large = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1158
bool desktop_large = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1159
bool dcc_disabled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1160
bool mpo_enabled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1297
static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1312
static bool dcn10_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
1323
bool res;
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
782
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1478
bool dcn20_split_stream_for_odm(
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1643
bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1820
bool *merge)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1824
bool force_split = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1825
bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1899
bool split4mpc = context->stream_count == 1 && plane_count == 1
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2003
bool dcn20_fast_validate_bw(
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2012
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2014
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2130
bool voltage_supported;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2172
bool dcn20_get_dcc_compression_cap(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2237
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2260
bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2337
static bool init_soc_bounding_box(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2352
bool clock_limits_available = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2353
bool uclk_states_available = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2391
static bool dcn20_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
962
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
114
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
115
bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
131
bool *merge);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
135
bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
141
bool dcn20_split_stream_for_odm(
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
154
bool dcn20_fast_validate_bw(
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
76
bool dcn20_get_dcc_compression_cap(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1029
static bool dcn201_get_dcc_compression_cap(const struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
1086
static bool dcn201_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
821
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
1384
static bool dcn21_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
766
bool dcn21_fast_validate_bw(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
774
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
776
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
929
bool voltage_supported;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
958
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h
47
bool dcn21_fast_validate_bw(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1215
static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1240
static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1300
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1428
bool dcn30_acquire_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1436
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1464
bool dcn30_release_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1471
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1486
static bool is_soc_bounding_box_valid(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1496
static bool init_soc_bounding_box(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1520
static bool dcn30_split_stream_for_mpc_or_odm(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1525
bool odm)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1624
noinline bool dcn30_internal_validate_bw(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1631
bool allow_self_refresh_only)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1633
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1634
bool repopulate_pipes = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1636
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1637
bool newly_split[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1770
bool odm;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1942
static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1959
bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2042
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
2268
static bool dcn30_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
103
bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
61
bool dcn30_internal_validate_bw(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
68
bool allow_self_refresh_only);
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
83
bool dcn30_acquire_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
90
bool dcn30_release_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1175
static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1200
static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1255
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1279
static bool is_soc_bounding_box_valid(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1289
static bool init_soc_bounding_box(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1407
static bool dcn301_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1198
static bool dcn302_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
443
enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
708
static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
743
static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
944
static bool is_soc_bounding_box_valid(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
954
static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1139
static bool dcn303_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
427
enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
669
static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
704
static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
889
static bool is_soc_bounding_box_valid(struct dc *dc)
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
899
static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1513
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1538
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1592
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1611
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1649
bool upscaled = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1765
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1863
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1882
static bool dcn31_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1571
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1596
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1650
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1703
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1794
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1813
static bool dcn314_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1513
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1538
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1592
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1611
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1634
static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1674
bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1708
bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1758
bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1852
static bool dcn315_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1506
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1531
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1585
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1605
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1728
static bool dcn316_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1504
static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1533
static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1596
bool dcn32_acquire_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1603
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1618
bool dcn32_release_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1625
bool ret = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1746
static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1748
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1874
bool subvp_in_use = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1878
bool single_display_subvp = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2085
bool limit_cur_to_buf;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2131
static bool dcn32_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
814
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
119
bool ignore_cursor_buf);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
128
bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
131
bool dcn32_subvp_in_use(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
134
bool dcn32_mpo_in_use(struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
136
bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
137
bool dcn32_is_center_timing(struct pipe_ctx *pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
138
bool dcn32_is_psr_capable(struct pipe_ctx *pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
171
bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
173
bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
179
bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
181
bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
183
bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
82
bool dcn32_acquire_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
89
bool dcn32_release_post_bldn_3dlut(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
153
bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
170
bool dcn32_subvp_in_use(struct dc *dc,
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
184
bool dcn32_mpo_in_use(struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
196
bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
212
bool dcn32_is_center_timing(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
214
bool is_center_timing = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
233
bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
235
bool psr_capable = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
34
static bool is_dual_plane(enum surface_pixel_format format)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
387
bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
42
bool ignore_cursor_buf)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
462
static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
520
bool is_fpo_vactive = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
591
bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
593
bool is_native_scaling = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
618
static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
620
bool disallow = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
644
bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
646
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
650
bool drr_pipe_found = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
651
bool drr_psr_capable = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
653
bool subvp_disallow = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
704
bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
706
bool result = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
710
bool drr_pipe_found = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
712
bool vblank_psr_capable = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
714
bool subvp_disallow = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1484
static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1513
static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1634
static bool dcn321_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
808
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1598
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1637
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1706
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1739
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1808
static bool dcn35_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
811
bool success = (dpp != NULL);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1578
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1617
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1686
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1719
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1781
static bool dcn351_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
791
bool success = (dpp != NULL);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1579
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1618
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1687
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1720
bool out = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1781
static bool dcn36_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
792
bool success = (dpp != NULL);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1507
static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1538
static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1817
static bool dcn401_resource_construct(
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
807
bool dp_clk_src)
sys/dev/pci/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
32
bool use_clock_dc_limits)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1167
bool ycbcr = spl_is_video_format(format);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1225
struct spl_out *spl_out, bool enable_easf_v, bool enable_easf_h, bool enable_isharp)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1233
bool enable_easf = enable_easf_v || enable_easf_h;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
13
static bool spl_is_yuv420(enum spl_pixel_format format)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1300
static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1301
bool enable_easf_h, enum linear_light_scaling lls_pref,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1666
struct adaptive_sharpness adp_sharpness, bool enable_isharp,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1802
static bool spl_calculate_number_of_taps(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1803
bool *enable_easf_v, bool *enable_easf_h, bool *enable_isharp)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1805
bool res = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1830
bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1832
bool res = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1833
bool enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1834
bool enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1840
bool enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
189
bool use_recout_width_aligned =
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1895
bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out))
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1897
bool res = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1898
bool enable_easf_v = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1899
bool enable_easf_h = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
1900
bool enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
22
static bool spl_is_rgb8(enum spl_pixel_format format)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
243
bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
30
static bool spl_is_video_format(enum spl_pixel_format format)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
39
static bool spl_is_subsampled_format(enum spl_pixel_format format)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
512
bool horizontal_mirror,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
513
bool *orthogonal_rotation,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
514
bool *flip_vert_scan_dir,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
515
bool *flip_horz_scan_dir)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
539
static void spl_calculate_init_and_vp(bool flip_scan_dir,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
613
bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
758
bool enable_isharp, bool enable_easf)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
801
static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
805
bool skip_easf = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
836
static bool spl_is_video_fullscreen(struct spl_in *spl_in)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
843
static bool spl_get_isharp_en(struct spl_in *spl_in,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
846
bool enable_isharp = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
850
bool fullscreen = spl_is_video_fullscreen(spl_in);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
894
bool is_subsampled)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
896
bool check_max_downscale = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
967
static bool spl_get_optimal_number_of_taps(
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
969
const struct spl_taps *in_taps, bool *enable_easf_v, bool *enable_easf_h,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
970
bool *enable_isharp)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
976
bool skip_easf = false;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
977
bool is_subsampled = spl_is_subsampled_format(spl_in->basic_in.format);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.h
23
bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out));
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.h
25
bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out));
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c
2346
const struct spl_scaler_data *data, bool enable_easf_v,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c
2347
bool enable_easf_h)
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h
17
const struct spl_scaler_data *data, bool enable_easf_v,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h
18
bool enable_easf_h);
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
42
bool integer_scaling;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
446
bool horizontal_mirror; // Horizontal mirror
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
448
bool use_recout_width_aligned;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
462
bool film_grain_applied; // Film Grain Applied // TODO: To check from where to get this?
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
475
bool always_scale; // Is always scale enabled? Required for getting SCL_MODE
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
477
bool alpha_en;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
478
bool use_two_pixels_per_container;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
501
bool enable;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
523
(bool alpha_en,
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
546
bool prefer_easf;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
547
bool disable_easf;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
549
bool is_fullscreen;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h
550
bool is_hdr_on;
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
10
bool *negative,
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
137
bool spl_convert_to_custom_float_format(struct spl_fixed31_32 value,
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
143
bool negative;
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
79
static bool spl_setup_custom_float(const struct spl_custom_float_format *format,
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
8
static bool spl_build_custom_float(struct spl_fixed31_32 value,
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c
80
bool negative,
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h
14
bool sign;
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h
21
bool negative;
sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h
24
bool spl_convert_to_custom_float_format(
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
103
bool arg1_negative = arg1.value < 0;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
104
bool arg2_negative = arg2.value < 0;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
51
bool arg1_negative = numerator < 0;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.c
52
bool arg2_negative = denominator < 0;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.h
117
static inline bool spl_fixpt_lt(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.h
126
static inline bool spl_fixpt_le(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.h
135
static inline bool spl_fixpt_eq(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.h
208
bool negative = arg.value < 0;
sys/dev/pci/drm/amd/display/dc/sspl/spl_fixpt31_32.h
501
bool negative = arg.value < 0;
sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c
113
bool virtual_link_encoder_construct(
sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c
31
static bool virtual_link_encoder_validate_output_with_stream(
sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c
78
bool connect) {}
sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.h
31
bool virtual_link_encoder_construct(
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
104
bool enable,
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
106
bool immediate_update)
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
141
bool virtual_stream_encoder_construct(
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
33
bool use_vsc_sdp_for_colorimetry,
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
40
bool enable_audio) {}
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
45
bool is_dual_link) {}
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
61
bool enable) {}
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
80
bool mute) {}
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
88
bool odm_combine)
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c
99
bool enable)
sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.h
34
bool virtual_stream_encoder_construct(
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
301
bool load_inst_const;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
302
bool skip_panel_power_sequence;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
303
bool disable_z10;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
304
bool power_optimization;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
305
bool dpia_supported;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
306
bool disable_dpia;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
307
bool usb4_cm_version;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
308
bool fw_in_system_memory;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
309
bool dpia_hpd_int_enable_supported;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
310
bool disable_clock_gate;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
311
bool disallow_dispclk_dppclk_ds;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
312
bool ips_sequential_ono;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
315
bool disallow_phy_access;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
316
bool disable_sldo_opt;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
317
bool enable_non_transparent_setconfig;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
318
bool lower_hbr3_phy_ssc;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
319
bool override_hbr3_pll_vco;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
328
bool timeout_occured;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
373
bool is_pending;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
374
bool is_multi_pending;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
456
bool (*is_supported)(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
458
bool (*is_psrsu_supported)(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
460
bool (*is_hw_init)(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
461
bool (*is_hw_powered_up)(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
466
void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
475
bool (*is_gpint_acked)(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
490
bool (*should_detect)(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
502
void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
509
void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
527
bool is_virtual;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
544
bool is_virtual;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
569
bool sw_init;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
570
bool hw_init;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
571
bool dpia_supported;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
604
bool pending_notification;
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
688
bool *is_supported);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
697
enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
774
bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
930
bool skip);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
932
bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
934
bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
936
bool dmub_srv_should_detect(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
4827
bool sign_bit;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
5930
bool enable;
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6469
static inline bool dmub_rb_empty(struct dmub_rb *rb)
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6520
static inline bool dmub_rb_full(struct dmub_rb *rb)
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6541
static inline bool dmub_rb_push_front(struct dmub_rb *rb,
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6574
static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6604
static inline bool dmub_rb_front(struct dmub_rb *rb,
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6646
static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6668
static inline bool dmub_rb_out_front(struct dmub_rb *rb,
sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h
6692
static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
349
bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
358
bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
373
bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
404
void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
87
bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
226
bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
228
bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
233
bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
240
void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
244
bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
246
bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
291
bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
302
bool dmub_dcn31_is_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
311
bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
322
bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
387
void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
489
bool dmub_dcn31_should_detect(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
492
bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
221
bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
223
bool dmub_dcn31_is_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
225
bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
230
bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
239
void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
256
bool dmub_dcn31_should_detect(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.c
64
bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.h
33
bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
321
bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
332
bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
347
bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
395
void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
234
bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
236
bool dmub_dcn32_is_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
241
bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
250
void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
327
bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
338
bool dmub_dcn35_is_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
353
bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
425
void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
536
bool dmub_dcn35_should_detect(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
539
bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
558
bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
241
bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
243
bool dmub_dcn35_is_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
248
bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
257
void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
282
bool dmub_dcn35_should_detect(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
284
bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
307
bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
318
bool dmub_dcn401_is_supported(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
333
bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
383
void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
627
void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
656
void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
238
bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
240
bool dmub_dcn401_is_supported(struct dmub_srv *dmub);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
245
bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
254
void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
281
void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
287
void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1110
bool skip)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1121
static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1144
bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1151
bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1159
bool dmub_srv_should_detect(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
162
static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
616
bool *is_supported)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
629
enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
880
bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
913
bool hw_on = true;
sys/dev/pci/drm/amd/display/include/audio_types.h
43
bool is_mst;
sys/dev/pci/drm/amd/display/include/audio_types.h
58
bool interlaced;
sys/dev/pci/drm/amd/display/include/audio_types.h
83
bool ss_enabled;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
118
bool enable_dp_audio;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
129
bool coherent;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
143
bool enable_dp_audio;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
164
bool coherent;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
165
bool multi_path;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
166
bool single_pll_mode;
sys/dev/pci/drm/amd/display/include/bios_parser_types.h
214
bool ss_enable;
sys/dev/pci/drm/amd/display/include/ddc_service_types.h
104
bool ss_supported;
sys/dev/pci/drm/amd/display/include/ddc_service_types.h
112
bool is_dp_hdmi_s3d_converter;
sys/dev/pci/drm/amd/display/include/ddc_service_types.h
115
bool is_edp_sink_cap_valid;
sys/dev/pci/drm/amd/display/include/ddc_service_types.h
76
bool is_dongle_type_one;
sys/dev/pci/drm/amd/display/include/ddc_service_types.h
85
bool downstrm_sink_count_valid;
sys/dev/pci/drm/amd/display/include/fixed31_32.h
135
static inline bool dc_fixpt_lt(struct fixed31_32 arg1, struct fixed31_32 arg2)
sys/dev/pci/drm/amd/display/include/fixed31_32.h
144
static inline bool dc_fixpt_le(struct fixed31_32 arg1, struct fixed31_32 arg2)
sys/dev/pci/drm/amd/display/include/fixed31_32.h
153
static inline bool dc_fixpt_eq(struct fixed31_32 arg1, struct fixed31_32 arg2)
sys/dev/pci/drm/amd/display/include/fixed31_32.h
226
bool negative = arg.value < 0;
sys/dev/pci/drm/amd/display/include/fixed31_32.h
519
bool negative = arg.value < 0;
sys/dev/pci/drm/amd/display/include/gpio_types.h
292
bool data_en_bit_present;
sys/dev/pci/drm/amd/display/include/gpio_types.h
293
bool clock_en_bit_present;
sys/dev/pci/drm/amd/display/include/gpio_types.h
304
bool enable_output_from_mux;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
155
bool realtek_eDPToLVDS;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
181
bool oem_i2c_present;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
199
bool CENTER_MODE:1;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
200
bool EXTERNAL:1;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
201
bool STEP_AND_DELAY_INFO:1;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
231
bool gpio_tv_active_state;
sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h
92
bool i2c_hw_assist;
sys/dev/pci/drm/amd/display/include/grph_object_id.h
303
static inline bool dal_graphics_object_id_equal(
sys/dev/pci/drm/amd/display/include/irq_service_interface.h
37
bool dal_irq_service_set(
sys/dev/pci/drm/amd/display/include/irq_service_interface.h
40
bool enable);
sys/dev/pci/drm/amd/display/include/irq_service_interface.h
42
bool dal_irq_service_ack(
sys/dev/pci/drm/amd/display/include/link_service_types.h
75
bool should_set_fec_ready;
sys/dev/pci/drm/amd/display/include/link_service_types.h
89
bool enhanced_framing;
sys/dev/pci/drm/amd/display/include/link_service_types.h
92
bool lttpr_early_tps2;
sys/dev/pci/drm/amd/display/include/link_service_types.h
95
bool disallow_per_lane_settings;
sys/dev/pci/drm/amd/display/include/link_service_types.h
98
bool always_match_dpcd_with_hw_lane_settings;
sys/dev/pci/drm/amd/display/include/logger_interface.h
61
static bool print_not_impl = true; \
sys/dev/pci/drm/amd/display/include/signal_types.h
104
static inline bool dc_is_lvds_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
109
static inline bool dc_is_dvi_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
121
static inline bool dc_is_tmds_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
134
static inline bool dc_is_dvi_single_link_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
139
static inline bool dc_is_dual_link_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
144
static inline bool dc_is_audio_capable_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
151
static inline bool dc_is_virtual_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
76
static inline bool dc_is_hdmi_tmds_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
81
static inline bool dc_is_hdmi_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
86
static inline bool dc_is_dp_sst_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
92
static inline bool dc_is_dp_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/signal_types.h
99
static inline bool dc_is_embedded_signal(enum amd_signal_type signal)
sys/dev/pci/drm/amd/display/include/vector.h
104
bool dal_vector_reserve(struct vector *vector, uint32_t capacity);
sys/dev/pci/drm/amd/display/include/vector.h
113
static bool vector_type##_vector_insert_at( \
sys/dev/pci/drm/amd/display/include/vector.h
122
static bool vector_type##_vector_append( \
sys/dev/pci/drm/amd/display/include/vector.h
37
bool dal_vector_construct(
sys/dev/pci/drm/amd/display/include/vector.h
72
bool dal_vector_insert_at(
sys/dev/pci/drm/amd/display/include/vector.h
77
bool dal_vector_append(
sys/dev/pci/drm/amd/display/include/vector.h
98
bool dal_vector_remove_at_index(
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1046
static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1063
bool use_eetf = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1064
bool is_clipped = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1180
static bool build_degamma(struct pwl_float_data_ex *curve,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1187
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1559
static bool calculate_interpolated_hardware_curve(
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1622
static bool map_regamma_hw_to_x_user(
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1631
bool map_user_ramp,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1632
bool do_clamping)
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1670
bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1672
const struct dc_gamma *ramp, bool map_user_ramp)
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1682
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1828
static bool calculate_curve(enum dc_transfer_func_predefined trans,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1836
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1908
bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1910
bool map_user_ramp,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1911
bool can_rom_be_used,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1923
bool do_clamping = true;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
1924
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
397
static bool build_coefficients(struct gamma_coefficients *coefficients,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
403
bool ret = true;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
523
static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg, bool use_eetf, struct calculate_buffer *cal_buffer)
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
611
static bool find_software_points(
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
690
static bool build_custom_gamma_mapping_coefficients_worker(
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
923
static bool build_regamma(struct pwl_float_data_ex *rgb_regamma,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
930
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_gamma.h
109
bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.h
110
const struct dc_gamma *ramp, bool mapUserRamp, bool canRomBeUsed,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.h
114
bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
sys/dev/pci/drm/amd/display/modules/color/color_gamma.h
116
const struct dc_gamma *ramp, bool mapUserRamp);
sys/dev/pci/drm/amd/display/modules/color/color_table.c
30
static bool pq_initialized;
sys/dev/pci/drm/amd/display/modules/color/color_table.c
31
static bool de_pg_initialized;
sys/dev/pci/drm/amd/display/modules/color/color_table.c
33
bool mod_color_is_table_init(enum table_type type)
sys/dev/pci/drm/amd/display/modules/color/color_table.c
35
bool ret = false;
sys/dev/pci/drm/amd/display/modules/color/color_table.c
57
void mod_color_set_table_init_state(enum table_type type, bool state)
sys/dev/pci/drm/amd/display/modules/color/color_table.h
41
bool mod_color_is_table_init(enum table_type type);
sys/dev/pci/drm/amd/display/modules/color/color_table.h
45
void mod_color_set_table_init_state(enum table_type type, bool state);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1291
bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
229
bool ramp_direction_is_up = current_duration_in_us >
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
450
bool update = false;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
542
static bool vrr_settings_require_update(struct core_freesync *core_freesync,
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
565
bool freesync_on_desktop)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
619
bool freesync_on_desktop)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
875
bool freesync_on_desktop)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
891
bool freesync_on_desktop)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
909
bool freesync_on_desktop)
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
947
bool pack_sdp_v1_3)
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_execution.c
500
const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c
188
const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp2_transition.c
514
const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_aux
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c
157
bool success = true;
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c
228
bool success = true;
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c
692
static bool write_stall_read_lc_fw_aux(struct mod_hdcp *hdcp)
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c
720
static bool write_poll_read_lc_fw_i2c(struct mod_hdcp *hdcp)
sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c
759
const bool success = (is_dp_hdcp(hdcp) ? write_stall_read_lc_fw_aux : write_poll_read_lc_fw_i2c)(hdcp);
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
119
bool pack_sdp_v1_3);
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
144
bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr);
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
38
bool supported;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
53
bool vsif_supported;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
54
bool ramping;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
55
bool btr;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
63
bool btr_enabled;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
64
bool btr_active;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
73
bool fixed_active;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
74
bool ramping_active;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
75
bool ramping_done;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
81
bool flip_interval_workaround_active;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
82
bool program_flip_interval_workaround;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
83
bool do_flip_interval_workaround_cleanup;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
91
bool supported;
sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h
92
bool send_info_frame;
sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h
152
bool (*read_i2c)(void *handle,
sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h
157
bool (*write_i2c)(void *handle,
sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h
161
bool (*read_dpcd)(void *handle,
sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h
165
bool (*write_dpcd)(void *handle,
sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h
169
bool (*atomic_write_poll_read_i2c)(
sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h
177
bool (*atomic_write_poll_read_aux)(
sys/dev/pci/drm/amd/display/modules/inc/mod_info_packet.h
61
bool support;
sys/dev/pci/drm/amd/display/modules/inc/mod_info_packet.h
66
bool supportMode;
sys/dev/pci/drm/amd/display/modules/inc/mod_stats.h
36
bool dummy;
sys/dev/pci/drm/amd/display/modules/inc/mod_stats.h
49
bool mod_stats_init(struct mod_stats *mod_stats);
sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c
142
bool stereo3dSupport = false;
sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c
455
bool hdmi_vic_mode = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
1021
bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps)
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
278
struct iram_table_v_2_2 *table, bool big_endian)
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
631
static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian)
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
692
bool dmub_init_abm_config(struct resource_pool *res_pool,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
699
bool result = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
766
bool dmcu_load_iram(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
770
bool result = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
818
bool is_psr_su_specific_panel(struct dc_link *link)
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
820
bool isPSRSUSupported = false;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
938
bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
943
bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
43
bool backlight_ramping_override;
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
50
bool dmcu_load_iram(struct dmcu *dmcu,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
52
bool dmub_init_abm_config(struct resource_pool *res_pool,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
69
bool is_psr_su_specific_panel(struct dc_link *link);
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
73
bool mod_power_only_edp(const struct dc_state *context,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
75
bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
79
bool fill_custom_backlight_caps(unsigned int config_no,
sys/dev/pci/drm/amd/include/amd_pcie_helpers.h
28
static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
sys/dev/pci/drm/amd/include/amd_pcie_helpers.h
36
static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
sys/dev/pci/drm/amd/include/amd_shared.h
466
bool (*is_idle)(struct amdgpu_ip_block *ip_block);
sys/dev/pci/drm/amd/include/amd_shared.h
468
bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
sys/dev/pci/drm/amd/include/cgs_common.h
78
bool is_kicker;
sys/dev/pci/drm/amd/include/dm_pp_interface.h
100
bool invalid_vblank_time;
sys/dev/pci/drm/amd/include/dm_pp_interface.h
74
bool nb_pstate_switch_disable;/* controls NB PState switch */
sys/dev/pci/drm/amd/include/dm_pp_interface.h
75
bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
sys/dev/pci/drm/amd/include/dm_pp_interface.h
76
bool cpu_pstate_disable;
sys/dev/pci/drm/amd/include/dm_pp_interface.h
94
bool multi_monitor_in_sync;
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
146
bool enable_mes;
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
257
bool (*hqd_is_occupied)(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
266
bool (*hqd_sdma_is_occupied)(struct amdgpu_device *adev, void *mqd);
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
274
bool (*get_atc_vmid_pasid_mapping_info)(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
290
bool restore_dbg_registers,
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
293
bool keep_trap_enabled,
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
54
bool prot_valid;
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
55
bool prot_read;
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
56
bool prot_write;
sys/dev/pci/drm/amd/include/kgd_kfd_interface.h
57
bool prot_exec;
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
414
bool (*vblank_too_short)(void *handle);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
415
void (*enable_bapm)(void *handle, bool enable);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
419
bool *equal);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
444
int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
445
int (*pause_power_profile)(void *handle, bool pause);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
454
bool gate,
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
467
int (*smu_i2c_bus_access)(void *handle, bool acquire);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
470
u32 (*get_sclk)(void *handle, bool low);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
471
u32 (*get_mclk)(void *handle, bool low);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
510
bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
516
bool disable_memory_clock_switch);
sys/dev/pci/drm/amd/include/kgd_pp_interface.h
526
int (*notify_rlc_state)(void *handle, bool en);
sys/dev/pci/drm/amd/include/mes_v11_api_def.h
518
bool mes_healthy; /* 0 - not healthy, 1 - healthy */
sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h
437
bool umsch_mm_healthy; /* 0 - not healthy, 1 - healthy */
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1620
bool cclk_dpm_supported = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
1965
bool disable_memory_clock_switch)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
2075
bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
2079
bool support_temp_metrics = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
288
bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
291
bool support_mode1_reset = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
316
bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
319
bool support_link_reset = false;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
346
bool en)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
365
bool pause)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
41
int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
480
bool acquire)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
57
int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
591
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
615
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
625
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
650
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
660
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
694
int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
75
bool gate,
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
761
bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
764
bool ret;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
806
bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
809
bool ret;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
81
bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN;
sys/dev/pci/drm/amd/pm/amdgpu_dpm.c
894
int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
110
static int amdgpu_pm_dev_state_check(struct amdgpu_device *adev, bool runpm)
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
112
bool runpm_check = runpm ? adev->in_runpm : false;
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4491
static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
4511
static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
239
bool ucode_fan_control;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
276
bool power_control;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
278
bool thermal_active;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
279
bool uvd_active;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
280
bool vce_active;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
340
bool bus_locked;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
345
bool no_fan;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
350
bool dpm_enabled;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
351
bool sysfs_initialized;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
360
bool ac_power;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
377
bool pp_force_state_enabled;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
397
uint32_t block_type, bool gate, int inst);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
399
extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
401
extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
408
bool en);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
410
bool pause);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
420
bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
421
bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
442
bool acquire);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
447
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
448
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
449
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
450
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
451
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
453
int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
469
int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
597
bool disable_memory_clock_switch);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
610
bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
612
bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
613
bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
69
bool vce_active;
sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h
99
bool high_to_low;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
118
static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1199
static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1236
static void kv_dpm_enable_bapm(void *handle, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1249
static bool kv_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1475
static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1481
static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1487
static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1493
static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1499
static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1585
static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1637
static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1668
static void kv_dpm_powergate_uvd(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1695
static void kv_dpm_powergate_vce(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1720
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1740
static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
1849
bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2205
bool force_high;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2313
u32 index, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2342
bool force_high;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2920
static u32 kv_dpm_get_sclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2932
static u32 kv_dpm_get_mclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3112
static bool kv_dpm_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3169
bool queue_thermal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3207
static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3219
bool *equal)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
3295
bool gate,
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
449
static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
49
bool enable);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
491
static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
551
static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
68
static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
69
static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
708
u32 index, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
751
static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
110
bool need_dfs_bypass;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
137
bool enable_nb_ps_policy;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
138
bool disable_nb_ps3_in_battery;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
139
bool video_start;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
140
bool battery_state;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
144
bool cac_enabled;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
145
bool bapm_enable;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
179
bool uvd_power_gated;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
180
bool vce_power_gated;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
181
bool acp_power_gated;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
182
bool samu_power_gated;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
183
bool nb_dpm_enabled;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
185
bool enable_didt;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
186
bool enable_dpm;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
187
bool enable_auto_thermal_throttling;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
188
bool enable_nb_dpm;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
190
bool caps_cac;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
191
bool caps_power_containment;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
192
bool caps_sq_ramping;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
193
bool caps_db_ramping;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
194
bool caps_td_ramping;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
195
bool caps_tcp_ramping;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
196
bool caps_sclk_throttle_low_notification;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
197
bool caps_fps;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
198
bool caps_uvd_dpm;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
199
bool caps_uvd_pg;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
200
bool caps_vce_pg;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
201
bool caps_samu_pg;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
202
bool caps_acp_pg;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
203
bool caps_stable_p_state;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
204
bool caps_enable_dfs_bypass;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
205
bool caps_sclk_ds;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
223
int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h
224
int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
105
int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c
113
int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
776
bool single_display = adev->pm.pm_display_cfg.num_display < 2;
sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c
900
bool equal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1995
bool update_dte_from_pl2 = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2226
bool adjust_polarity,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2373
static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2408
bool disable_uvd_power_tune;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2492
bool enable_sq_ramping = ni_pi->enable_sq_ramping;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2547
bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2911
bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3077
static bool si_dpm_vblank_too_short(void *handle)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3395
static bool r600_is_uvd_state(u32 class, u32 class2)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3450
bool disable_mclk_switching = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3451
bool disable_sclk_switching = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3723
static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3725
bool ret = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3727
bool is_memory_gddr5, is_special;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3800
bool want_thermal_protection;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3834
bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3861
static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3893
static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4109
bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4151
bool has_display)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4242
static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4353
static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4378
bool strobe_mode = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4405
static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4665
bool voltage_found = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5421
bool strobe_mode,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5422
bool dll_state_on)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5529
bool dll_state_on;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5683
static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5950
static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5952
bool result = true;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6232
static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6333
bool ds_status_on, u32 count_write)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
6465
bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7650
bool queue_thermal = false;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7907
static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7951
static u32 si_dpm_get_sclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7963
static u32 si_dpm_get_mclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
8007
static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
8020
bool *equal)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
1016
bool fan_ctrl_is_in_default_mode;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
1019
bool fan_is_controlled_by_smc;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
330
bool supported;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
533
bool mem_gddr5;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
534
bool pcie_gen2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
535
bool dynamic_pcie_gen2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
536
bool acpi_pcie_gen2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
537
bool boot_in_gen2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
538
bool voltage_control; /* vddc */
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
539
bool mvdd_control;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
540
bool sclk_ss;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
541
bool mclk_ss;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
542
bool dynamic_ss;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
543
bool gfx_clock_gating;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
544
bool mg_clock_gating;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
545
bool mgcgtssm;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
546
bool power_gating;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
547
bool thermal_protection;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
548
bool display_gap;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
549
bool dcodt;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
550
bool ulps;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
618
bool dc_compatible;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
623
bool dc_compatible;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
656
bool vddci_control;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
657
bool dynamic_ac_timing;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
658
bool abm;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
659
bool mcls;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
660
bool light_sleep;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
661
bool memory_transition;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
662
bool pcie_performance_request;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
663
bool pcie_performance_request_registered;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
664
bool sclk_deep_sleep;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
665
bool dll_default_on;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
666
bool ls_clock_gating;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
667
bool smu_uvd_hs;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
668
bool uvd_enabled;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
832
bool use_power_boost_limit;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
833
bool support_cac_long_term_average;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
834
bool cac_enabled;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
835
bool cac_configuration_required;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
836
bool driver_calculate_cac_leakage;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
837
bool pc_enabled;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
838
bool enable_power_containment;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
839
bool enable_cac;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
840
bool enable_sq_ramping;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
879
bool enable_powertune_by_default;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
891
bool disable_uvd_powertune;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
909
bool enable_dte_by_default;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
957
bool supported;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
962
bool one_pcie_lane_in_ulv;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
982
bool enable_dte;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
983
bool enable_ppm;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
984
bool vddc_phase_shed_control;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
985
bool pspp_notify_required;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
986
bool sclk_deep_sleep_above_low;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
987
bool voltage_control_svi2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
988
bool vddci_control_svi2;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
147
void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c
159
bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h
399
void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);
sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h
400
bool amdgpu_si_is_smc_running(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1189
static int pp_dpm_powergate_gfx(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1204
static void pp_dpm_powergate_acp(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1219
static void pp_dpm_powergate_sdma(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1236
bool gate,
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1456
static int pp_smu_i2c_bus_access(void *handle, bool acquire)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
247
static bool pp_is_idle(struct amdgpu_ip_block *ip_block)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
399
static uint32_t pp_dpm_get_sclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
413
static uint32_t pp_dpm_get_mclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
427
static void pp_dpm_powergate_vce(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
441
static void pp_dpm_powergate_uvd(void *handle, bool gate)
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
917
enum PP_SMC_POWER_PROFILE type, bool en)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
101
bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
27
static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
44
static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
49
bool ret = true;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
82
bool baco_program_registers(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h
57
extern bool baco_program_registers(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h
60
extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
265
bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
284
bool *equal)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_psm.c
251
bool equal;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_psm.c
271
int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_settings,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_psm.h
37
bool skip_display_settings,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
297
bool strobe_mode)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
554
bool atomctrl_is_voltage_controlled_by_gpio_v3(
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
561
bool ret;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
616
static bool atomctrl_lookup_gpio_pin(
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
669
bool atomctrl_get_pp_assign_pin(
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
674
bool bRet = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
824
bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
293
extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
298
bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
305
extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
308
extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
42
bool enable_post_divider;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
62
bool enable_post_divider;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
63
bool enable_dithen;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
76
bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
82
bool ret;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
223
bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
40
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c
441
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1174
bool latency_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1302
bool has_gfx_busy;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1395
static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1403
static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
1484
static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
335
static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
417
static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
852
static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
868
static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
951
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
135
bool need_dfs_bypass;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
164
bool display_phy_access_initialized;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
219
bool disp_clk_bypass;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
220
bool disp_clk_bypass_pending;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
223
bool video_start;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
224
bool battery_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
230
bool in_vpu_recovery;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
231
bool pg_acp_init;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
236
bool cac_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
237
bool disable_uvd_power_tune_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
238
bool enable_bapm_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
239
bool enable_tdc_limit_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
262
bool acp_power_up_no_dsp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
269
bool cc6_disable;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
270
bool pstate_disable;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
271
bool cc6_setting_changed;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
275
bool isp_tileA_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
276
bool isp_tileB_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
290
bool vcn_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
291
bool vcn_dpg_mode;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
293
bool gfx_off_controled_by_driver;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
294
bool water_marks_exist;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
300
bool need_min_deep_sleep_dcefclk;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
304
bool fine_grain_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
114
void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
142
void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
28
static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
36
static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
424
int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
44
static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
51
static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h
29
void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h
30
void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h
31
int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h
35
int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1379
bool protection;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
1693
static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
264
static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3321
bool disable_mclk_switching;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3322
bool disable_mclk_switching_for_frame_lock;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3323
bool disable_mclk_switching_for_display;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3332
bool latency_allowed = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3487
static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3509
static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4303
bool force_trim = (low_limit == high_limit);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4680
static bool
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4684
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4706
static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
4717
const struct pp_hw_power_state *pstate2, bool *equal)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5342
bool valid_entry;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5454
static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
229
bool is_memory_gddr5;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
231
bool pspp_notify_required;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
248
bool is_uvd_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
251
bool pcie_performance_request;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
252
bool battery_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
253
bool mclk_ignore_signal;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
254
bool is_tlu_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
255
bool disable_handshake;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
256
bool smc_voltage_control_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
257
bool vbi_time_out_support;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
275
bool dll_default_on;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
276
bool performance_request_registered;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
279
bool ulv_supported;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
283
bool cac_configuration_required;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
284
bool driver_calculate_cac_leakage;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
285
bool cac_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
289
bool enable_dte_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
290
bool enable_tdc_limit_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
291
bool enable_pkg_pwr_tracking_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
292
bool disable_uvd_power_tune_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
316
bool use_pcie_performance_levels;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
317
bool use_pcie_power_saving_levels;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
321
bool uvd_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
324
bool uvd_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
325
bool vce_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
326
bool need_long_memory_training;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
329
bool update_up_hyst;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
330
bool update_down_hyst;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
334
bool apply_optimized_settings;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
337
bool apply_avfs_cks_off_voltage;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
348
bool disable_edc_leakage_controller;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
83
bool dc_compatible;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
89
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
850
static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1081
bool force_high;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1343
static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1350
static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1499
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1880
static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1905
static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1936
static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1963
static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1978
static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
2013
static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
797
static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
868
bool disable_switch;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
869
bool enable_low_mem_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
151
bool need_dfs_bypass;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
175
bool cc6_setting_changed;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
176
bool nb_pstate_switch_disable;/* controls NB PState switch */
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
177
bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
178
bool cpu_pstate_disable;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
224
bool disp_clk_bypass;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
225
bool disp_clk_bypass_pending;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
237
bool video_start;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
238
bool battery_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
246
bool pgacpinit;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
252
bool cac_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
253
bool disable_uvd_power_tune_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
254
bool enable_ba_pm_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
255
bool enable_tdc_limit_feature;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
300
bool uvd_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
301
bool vce_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
302
bool samu_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
303
bool acp_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
304
bool acp_power_up_no_dsp;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
95
bool display_phy_access_initialized;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
193
bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
198
bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c
208
bool found = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
71
extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
72
extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
73
extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
1027
bool found = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
2444
static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3009
static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3285
bool disable_mclk_switching;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3286
bool disable_mclk_switching_for_frame_lock;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3287
bool disable_mclk_switching_for_vr;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3288
bool force_mclk_high;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3796
int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3884
static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
3906
static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4029
bool has_disp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
4990
static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5005
static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5013
static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5021
static inline bool vega10_are_power_levels_equal(
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5032
const struct pp_hw_power_state *pstate2, bool *equal)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5075
static bool
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5079
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5360
static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5418
static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
5704
static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
110
bool dc_compatible;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
116
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
182
bool bsoc_vddc_lock;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
336
bool cac_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
337
bool battery_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
338
bool is_tlu_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
372
bool uvd_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
373
bool vce_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
374
bool need_long_memory_training;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
439
extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
441
int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
442
int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
443
int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
444
int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
78
bool supported;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
79
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
800
static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
314
bool is_acg_enabled = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
321
(bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
37
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1322
int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1339
static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1362
static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1387
bool bypass_cache)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1560
bool has_disp)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
1843
bool max)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2362
bool vblank_too_short = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2363
bool disable_mclk_switching;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2583
static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2600
static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2611
static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2622
static bool
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2626
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
2826
static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
62
bool max);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
923
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
949
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
159
bool bsoc_vddc_lock;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
303
bool force_fan_pwm;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
337
bool cac_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
338
bool battery_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
339
bool is_tlu_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
340
bool avfs_exist;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
374
bool uvd_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
375
bool vce_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
376
bool samu_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
377
bool need_long_memory_training;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
380
bool apply_optimized_settings;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
397
bool gfxoff_controlled_by_driver;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
455
int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
81
bool supported;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
82
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
83
bool allowed;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
89
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c
34
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2011
static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2040
bool max)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2063
static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2089
static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
2117
bool bypass_cache)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3282
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3680
static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3706
static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3728
static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3743
bool vblank_too_short = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3744
bool disable_mclk_switching;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3745
bool disable_fclk_switching;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3916
static bool
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
3920
bool is_update_required = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
4258
static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
503
bool use_baco = (amdgpu_in_reset(adev) &&
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
974
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
127
bool dc_compatible;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
133
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
366
bool force_fan_pwm;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
458
bool cac_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
459
bool battery_state;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
460
bool is_tlu_enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
461
bool avfs_exist;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
497
bool uvd_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
498
bool vce_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
499
bool samu_power_gated;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
500
bool need_long_memory_training;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
503
bool apply_optimized_settings;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
508
bool gfxclk_overdrive;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
509
bool memclk_overdrive;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
523
bool gfxoff_allowed;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
530
bool pcie_parameters_override;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
534
bool is_custom_profile_set;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
94
bool supported;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
95
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
96
bool allowed;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
119
bool od_supported = false;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c
36
static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
295
static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
362
bool TDPAdjustmentPolarity;
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
368
bool VidAdjustmentPolarity;
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
386
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
40
bool supports_percent_read;
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
41
bool supports_percent_write;
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
419
extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
42
bool supports_rpm_read;
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
424
bool *equal);
sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h
43
bool supports_rpm_write;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
227
bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
228
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
230
int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
260
void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
261
void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
262
void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
263
uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
264
uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
286
bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
290
bool *equal);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
293
bool cc6_disable, bool pstate_disable,
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
294
bool pstate_switch_disable);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
317
int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
323
int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
347
int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
360
int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool acquire);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
364
bool disable);
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
56
bool enabled;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
661
bool bNoFan;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
747
bool not_vf;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
748
bool pm_en;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
749
bool pp_one_vf;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
758
bool need_pp_table_upload;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
773
bool is_kicker;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
783
bool fan_ctrl_is_in_default_mode;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
785
bool fan_ctrl_enabled;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
795
bool avfs_supported;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
797
bool en_umd_pstate;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
802
bool od_enabled;
sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h
808
bool gfxoff_state_changed_by_workload;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
100
bool disableFrameModulation;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
101
bool limitRefreshrate;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
105
bool enableVariBright;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
109
bool dllOff;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
115
bool disableLoadBalancing;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
116
bool enableSleepForTimestamps;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
138
bool singleDisplayOnly;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
139
bool disallowOnDC;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
86
bool temporary_state;
sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h
87
bool to_be_deleted;
sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h
108
extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h
110
extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h
114
extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1027
bool strobe_mode,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1028
bool dllStateOn
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1120
bool strobe_mode)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1182
bool dll_state_on;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
186
static bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2375
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2448
static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2450
bool result = true;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2729
static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
769
bool vol_found = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2452
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
2541
static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
317
static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1048
bool strobe_mode,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1049
bool dllStateOn
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1170
bool strobe_mode)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1235
bool dll_state_on;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2285
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2375
static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2377
bool result = true;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2656
static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
535
bool vol_found = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2498
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
2579
static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
323
static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
295
static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
124
bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h
59
bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
329
uint8_t type, bool is_last)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
366
bool is_last)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
870
static bool smu8_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
888
static bool smu8_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
39
bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.h
26
bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c
217
bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c
225
bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c
241
int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2764
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2837
static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2839
bool result = true;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3140
static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
791
bool strobe_mode,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
792
bool dllStateOn
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
921
bool strobe_mode)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
974
bool dll_state_on;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
112
bool enable, uint32_t feature_mask)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
149
static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
374
uint16_t table_id, bool rw)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.h
46
bool enable, uint32_t feature_mask);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
126
bool enable, uint64_t feature_mask)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
182
static bool vega12_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
388
uint16_t table_id, bool rw)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.h
52
bool enable, uint64_t feature_mask);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
318
bool enable, uint64_t feature_mask)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
49
bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
606
static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
619
uint16_t table_id, bool rw)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h
51
bool enable, uint64_t feature_mask);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h
60
bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1547
static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
231
bool error = false;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
296
static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
106
int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
1328
bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
194
static u32 smu_get_mclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
1991
bool use_baco = !smu->is_apu &&
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
208
static u32 smu_get_sclk(void *handle, bool low)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
235
static bool is_vcn_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2412
bool skip_display_settings)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
250
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2504
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2540
bool pause)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
277
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
2858
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
300
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
320
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3269
bool custom = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
340
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3479
bool disable_memory_clock_switch)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3549
bool smu_mode1_reset_is_support(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3551
bool ret = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3562
bool smu_link_reset_is_support(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3743
int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
391
bool gate,
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3914
static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3917
bool ret = false;
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
4155
bool smu_reset_sdma_is_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
4170
bool smu_reset_vcn_is_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
589
bool is_support_sw_smu(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
602
bool is_support_cclk_dpm(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
73
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1046
int (*powergate_sdma)(struct smu_context *smu, bool gate);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1052
int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1080
int (*system_features_control)(struct smu_context *smu, bool en);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1204
int (*gfx_off_control)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1227
u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1285
bool (*mode1_reset_is_support)(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
130
bool temporary_state;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
131
bool to_be_deleted;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1322
bool automatic);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1371
int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1376
int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1398
int (*gpo_control)(struct smu_context *smu, bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1414
int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
144
bool disable_frame_modulation;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
145
bool limit_refreshrate;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1479
int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1485
int (*dpm_set_isp_enable)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
149
bool enable_vari_bright;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1491
int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1501
int (*notify_rlc_state)(struct smu_context *smu, bool en);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1506
bool (*is_asic_wbrf_supported)(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1511
int (*enable_uclk_shadow)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
153
bool dll_off;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
159
bool disable_load_balancing;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
160
bool enable_sleep_for_timestamps;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1687
static inline bool smu_table_cache_is_valid(struct smu_table *table)
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1737
bool smu_mode1_reset_is_support(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1738
bool smu_link_reset_is_support(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1744
bool is_support_sw_smu(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1745
bool is_support_cclk_dpm(struct amdgpu_device *adev);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1765
int smu_set_residency_gfxoff(struct smu_context *smu, bool value);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1769
int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
178
bool single_display_only;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1780
bool smu_reset_sdma_is_supported(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1782
bool smu_reset_vcn_is_supported(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
179
bool disallow_on_dc;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
1791
bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
416
bool uvd_gated;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
417
bool vce_gated;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
473
bool platform_support;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
474
bool maco_support;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
513
bool enabled;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
571
bool od_enabled;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
582
bool support_power_containment;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
583
bool disable_watermark;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
589
bool disable_uclk_switch;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
593
bool pause_workload;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
599
bool pm_enabled;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
600
bool is_apu;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
608
bool uploading_custom_pp_table;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
609
bool dc_controlled_by_gpio;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
648
bool wbrf_supported;
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
673
bool (*temp_metrics_is_supported)(struct smu_context *smu, enum smu_temp_metric_type type);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
802
int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
808
int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
870
bool (*is_dpm_running)(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
919
int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
179
bool en);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
231
int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
258
uint32_t min, uint32_t max, bool automatic);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
293
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
296
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
300
int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
84
bool enabled;
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h
92
bool is_fine_grained;
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
40
int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
42
int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
44
int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
46
int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
50
int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h
59
uint32_t min, uint32_t max, bool automatic);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
165
bool en);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
202
int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
220
uint32_t min, uint32_t max, bool automatic);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
245
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
251
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
255
bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
262
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
265
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
291
int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
77
bool enabled;
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
85
bool is_fine_grained;
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
157
bool en);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
170
int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
190
uint32_t min, uint32_t max, bool automatic);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
208
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
214
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
218
bool enable);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
225
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
228
bool enablement);
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
72
bool enabled;
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h
80
bool is_fine_grained;
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1591
static bool arcturus_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1604
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
810
bool freq_match;
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
948
bool max,
sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h
34
bool enabled;
sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
359
static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1139
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1162
static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1242
static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
1874
static bool navi10_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2363
bool disable_memory_clock_switch)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
262
static bool is_asic_secure(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
265
bool is_secure = true;
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2812
static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1156
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1174
static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1246
static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1576
static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2115
bool disable_memory_clock_switch)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2508
static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2689
bool use_metrics_v2 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2690
bool use_metrics_v3 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2900
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2954
bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
596
bool use_metrics_v3,
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
597
bool use_metrics_v2)
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
620
static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
741
bool use_metrics_v2 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
742
bool use_metrics_v3 = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1107
int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1146
smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1705
int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1778
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1875
bool auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2108
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2119
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
776
bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1087
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
1273
static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2205
static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2448
static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
473
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
492
static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
509
static bool vangogh_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
578
bool cur_value_match_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
679
bool cur_value_match_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
860
static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
1354
static bool renoir_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
500
bool cur_value_match_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
644
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
667
static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
688
static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
110
int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
121
int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
158
int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
214
uint32_t min, uint32_t max, bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1309
static int aldebaran_system_features_control(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1363
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1519
static bool aldebaran_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
1997
static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
2005
static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
552
static bool aldebaran_is_primary(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
839
bool freq_match;
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
985
bool max,
sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h
34
bool enabled;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1068
smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1543
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1611
bool auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
1875
bool *is_fine_grained_dpm)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2000
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2017
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2036
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2051
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2124
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2455
int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
782
int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
812
bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1058
static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2699
static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
3069
static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
709
static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
722
bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
355
bool smu_v13_0_12_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
568
static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
211
static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
224
static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
721
static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
185
static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
197
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
213
static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
229
static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
698
static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
819
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
117
bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1581
static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
1993
static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2005
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2099
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2354
static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2640
bool per_inst;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2757
bool per_inst;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
286
bool smu_v13_0_6_cap_supported(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3131
static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3136
static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3187
static bool smu_v13_0_6_reset_sdma_is_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3189
bool ret = true;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3217
static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3249
static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3464
static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3529
static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3548
static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3661
static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
3714
static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
751
bool bypass_cache)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
53
bool Init;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
79
bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
82
bool bypass_cache);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
84
bool smu_v13_0_12_is_dpm_running(struct smu_context *smu);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
1047
static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2650
static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
2670
static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
707
static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
212
static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
224
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
240
static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
256
static bool yellow_carp_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
832
static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
953
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1166
bool automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1273
bool auto_level = false;
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1488
bool *is_fine_grained_dpm)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1571
bool enable,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1599
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1642
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1657
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
1730
bool enablement)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
767
int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
794
bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1212
bool __always_unused automatic)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1545
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1553
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1561
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
246
static int smu_v14_0_0_system_features_control(struct smu_context *smu, bool en)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
469
static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
741
static bool smu_v14_0_0_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
1969
static bool smu_v14_0_2_is_mode1_reset_supported(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
639
static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
969
static bool smu_v14_0_2_is_od_feature_supported(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1029
bool bypass_cache)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1096
bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
1102
bool snd_driver_loaded;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
255
enum smu_message_type msg, bool *poll)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
259
bool fed_status, pri;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
428
bool poll = true;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
649
bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
745
bool enabled)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
778
bool enable)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
962
bool drv2smu)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
134
bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
146
bool enabled);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
150
bool enable);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
169
bool drv2smu);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
177
bool bypass_cache);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h
197
bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev);
sys/dev/pci/drm/apple/afk.c
538
static bool afk_recv(struct apple_dcp_afkep *ep)
sys/dev/pci/drm/apple/afk.h
147
bool ready;
sys/dev/pci/drm/apple/afk.h
32
bool done;
sys/dev/pci/drm/apple/afk.h
33
bool free_on_ack;
sys/dev/pci/drm/apple/afk.h
47
bool enabled;
sys/dev/pci/drm/apple/apple_drv.c
183
apple_connector_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/apple/apple_drv.c
317
int num, bool dcp_ext)
sys/dev/pci/drm/apple/apple_drv.c
419
bool dcp_ext;
sys/dev/pci/drm/apple/dcp-internal.h
124
bool crashed;
sys/dev/pci/drm/apple/dcp-internal.h
175
bool during_modeset;
sys/dev/pci/drm/apple/dcp-internal.h
176
bool valid_mode;
sys/dev/pci/drm/apple/dcp-internal.h
183
bool active;
sys/dev/pci/drm/apple/dcp-internal.h
186
bool main_display;
sys/dev/pci/drm/apple/dcp-internal.h
189
bool surfaces_cleared;
sys/dev/pci/drm/apple/dcp-internal.h
247
bool dcp_has_panel(struct apple_dcp *dcp);
sys/dev/pci/drm/apple/dcp-internal.h
89
bool update;
sys/dev/pci/drm/apple/dcp-internal.h
99
bool has_mini_led;
sys/dev/pci/drm/apple/dcp.c
1068
bool connected = gpiod_get_value_cansleep(dcp->hdmi_hpd);
sys/dev/pci/drm/apple/dcp.c
221
bool needs_modeset;
sys/dev/pci/drm/apple/dcp.c
323
bool connected = gpiod_get_value_cansleep(dcp->hdmi_hpd);
sys/dev/pci/drm/apple/dcp.c
372
bool connected;
sys/dev/pci/drm/apple/dcp.c
45
static bool show_notch;
sys/dev/pci/drm/apple/dcp.c
452
bool connected = gpiod_get_value_cansleep(dcp->hdmi_hpd);
sys/dev/pci/drm/apple/dcp.c
46
module_param(show_notch, bool, 0644);
sys/dev/pci/drm/apple/dcp.c
490
bool connected = gpiod_get_value_cansleep(dcp->hdmi_hpd);
sys/dev/pci/drm/apple/dcp.c
94
bool dcp_has_panel(struct apple_dcp *dcp)
sys/dev/pci/drm/apple/dcp.h
17
bool vsync_disabled;
sys/dev/pci/drm/apple/dcp.h
29
bool connected;
sys/dev/pci/drm/apple/dcp.h
54
bool dcp_is_initialized(struct platform_device *pdev);
sys/dev/pci/drm/apple/dcp.h
62
bool dcp_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/apple/dptxep.c
140
int dptxport_set_hpd(struct apple_epic_service *service, bool hpd)
sys/dev/pci/drm/apple/dptxep.c
352
bool phy_set_rate = false;
sys/dev/pci/drm/apple/dptxep.h
50
bool enabled, connected;
sys/dev/pci/drm/apple/dptxep.h
69
int dptxport_set_hpd(struct apple_epic_service *service, bool hpd);
sys/dev/pci/drm/apple/iomfb.c
156
void dcp_push(struct apple_dcp *dcp, bool oob, const struct dcp_method_entry *call,
sys/dev/pci/drm/apple/iomfb.c
432
bool modeset;
sys/dev/pci/drm/apple/iomfb.c
464
bool dcp_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/apple/iomfb.c
522
bool dcp_is_initialized(struct platform_device *pdev)
sys/dev/pci/drm/apple/iomfb.c
87
static bool dcp_channel_busy(struct dcp_channel *ch)
sys/dev/pci/drm/apple/iomfb.c
98
static enum dcp_context_id dcp_call_context(struct apple_dcp *dcp, bool oob)
sys/dev/pci/drm/apple/iomfb.h
210
typedef bool (*iomfb_cb_handler)(struct apple_dcp *, int, void *, void *);
sys/dev/pci/drm/apple/iomfb_internal.h
103
void dcp_push(struct apple_dcp *dcp, bool oob, const struct dcp_method_entry *call,
sys/dev/pci/drm/apple/iomfb_internal.h
15
static void func(struct apple_dcp *dcp, bool oob, dcp_callback_t cb, \
sys/dev/pci/drm/apple/iomfb_internal.h
22
static void func(struct apple_dcp *dcp, bool oob, dcp_callback_t cb, \
sys/dev/pci/drm/apple/iomfb_internal.h
29
static void func(struct apple_dcp *dcp, bool oob, T *data, \
sys/dev/pci/drm/apple/iomfb_internal.h
36
static void func(struct apple_dcp *dcp, bool oob, T_in *data, \
sys/dev/pci/drm/apple/iomfb_internal.h
44
static void iomfb_ ## name(struct apple_dcp *dcp, bool oob, \
sys/dev/pci/drm/apple/iomfb_internal.h
60
static bool __maybe_unused func(struct apple_dcp *dcp, int tag, void *out, void *in) \
sys/dev/pci/drm/apple/iomfb_internal.h
70
static bool __maybe_unused func(struct apple_dcp *dcp, int tag, void *out, void *in) \
sys/dev/pci/drm/apple/iomfb_internal.h
82
static bool __maybe_unused func(struct apple_dcp *dcp, int tag, void *out, void *in) \
sys/dev/pci/drm/apple/iomfb_internal.h
93
static bool __maybe_unused func(struct apple_dcp *dcp, int tag, void *out, void *in) \
sys/dev/pci/drm/apple/iomfb_template.c
1294
bool is_premultiplied = false;
sys/dev/pci/drm/apple/iomfb_template.c
136
static bool iomfbep_cb_match_pmu_service(struct apple_dcp *dcp, int tag, void *out, void *in)
sys/dev/pci/drm/apple/iomfb_template.c
158
static bool iomfbep_cb_match_pmu_service_2(struct apple_dcp *dcp, int tag, void *out, void *in)
sys/dev/pci/drm/apple/iomfb_template.c
180
static bool iomfbep_cb_match_backlight_service(struct apple_dcp *dcp, int tag, void *out, void *in)
sys/dev/pci/drm/apple/iomfb_template.c
403
static bool is_disp_register(struct apple_dcp *dcp, u64 start, u64 end)
sys/dev/pci/drm/apple/iomfb_template.c
539
static bool dcpep_process_chunks(struct apple_dcp *dcp,
sys/dev/pci/drm/apple/iomfb_template.c
644
static bool dcpep_cb_boot_1(struct apple_dcp *dcp, int tag, void *out, void *in)
sys/dev/pci/drm/apple/parser.c
1008
bool type_match = false;
sys/dev/pci/drm/apple/parser.c
133
static bool consume_string(struct dcp_parse_ctx *ctx, const char *specimen)
sys/dev/pci/drm/apple/parser.c
193
static int parse_bool(struct dcp_parse_ctx *handle, bool *b)
sys/dev/pci/drm/apple/parser.c
230
bool dict)
sys/dev/pci/drm/apple/parser.c
30
bool last : 1;
sys/dev/pci/drm/apple/parser.c
355
bool is_virtual = true;
sys/dev/pci/drm/apple/parser.c
436
bool is_virtual = false;
sys/dev/pci/drm/apple/parser.c
640
bool parsed_unit = false;
sys/dev/pci/drm/apple/parser.c
641
bool parsed_name = false;
sys/dev/pci/drm/apple/parser.c
642
bool parsed_class = false;
sys/dev/pci/drm/apple/systemep.c
10
static bool enable_verbose_logging;
sys/dev/pci/drm/apple/systemep.c
11
module_param(enable_verbose_logging, bool, 0644);
sys/dev/pci/drm/apple/trace.h
324
TP_PROTO(s64 id, struct dimension *horiz, struct dimension *vert, s64 best_color_mode, bool is_virtual, s64 score),
sys/dev/pci/drm/apple/trace.h
331
__field(bool, is_virtual)
sys/dev/pci/drm/apple/trace.h
347
TP_PROTO(s64 id, struct dimension *horiz, struct dimension *vert, s64 best_color_mode, bool is_virtual, s64 score),
sys/dev/pci/drm/apple/trace.h
351
TP_PROTO(s64 id, struct dimension *horiz, struct dimension *vert, s64 best_color_mode, bool is_virtual, s64 score),
sys/dev/pci/drm/clients/drm_fbdev_client.c
65
static int drm_fbdev_client_suspend(struct drm_client_dev *client, bool holds_console_lock)
sys/dev/pci/drm/clients/drm_fbdev_client.c
77
static int drm_fbdev_client_resume(struct drm_client_dev *client, bool holds_console_lock)
sys/dev/pci/drm/clients/drm_log.c
322
static int drm_log_client_suspend(struct drm_client_dev *client, bool _console_lock)
sys/dev/pci/drm/clients/drm_log.c
331
static int drm_log_client_resume(struct drm_client_dev *client, bool _console_lock)
sys/dev/pci/drm/clients/drm_log.c
58
bool probed;
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
161
static bool is_hdmi_adaptor(const char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN])
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
170
static bool is_type1_adaptor(uint8_t adaptor_id)
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
175
static bool is_type2_adaptor(uint8_t adaptor_id)
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
181
static bool is_lspcon_adaptor(const char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN],
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
324
bool *enabled)
sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c
362
struct i2c_adapter *adapter, bool enable)
sys/dev/pci/drm/display/drm_dp_helper.c
1042
static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid)
sys/dev/pci/drm/display/drm_dp_helper.c
1065
bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
1082
bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
111
bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
1117
bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
sys/dev/pci/drm/display/drm_dp_helper.c
1500
bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
1531
bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
1562
bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
1667
bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
sys/dev/pci/drm/display/drm_dp_helper.c
167
bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
1675
bool branch_device = drm_dp_is_branch(dpcd);
sys/dev/pci/drm/display/drm_dp_helper.c
1831
bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
sys/dev/pci/drm/display/drm_dp_helper.c
187
bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/display/drm_dp_helper.c
203
bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
sys/dev/pci/drm/display/drm_dp_helper.c
212
bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
sys/dev/pci/drm/display/drm_dp_helper.c
221
bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
sys/dev/pci/drm/display/drm_dp_helper.c
2525
bool is_branch;
sys/dev/pci/drm/display/drm_dp_helper.c
2565
drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
sys/dev/pci/drm/display/drm_dp_helper.c
2627
bool is_branch)
sys/dev/pci/drm/display/drm_dp_helper.c
2717
bool is_edp)
sys/dev/pci/drm/display/drm_dp_helper.c
288
enum drm_dp_phy dp_phy, bool uhbr, bool cr)
sys/dev/pci/drm/display/drm_dp_helper.c
2961
int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable)
sys/dev/pci/drm/display/drm_dp_helper.c
3036
bool
sys/dev/pci/drm/display/drm_dp_helper.c
3052
bool
sys/dev/pci/drm/display/drm_dp_helper.c
3337
bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
sys/dev/pci/drm/display/drm_dp_helper.c
3362
bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
sys/dev/pci/drm/display/drm_dp_helper.c
343
enum drm_dp_phy dp_phy, bool uhbr)
sys/dev/pci/drm/display/drm_dp_helper.c
3498
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
sys/dev/pci/drm/display/drm_dp_helper.c
350
enum drm_dp_phy dp_phy, bool uhbr)
sys/dev/pci/drm/display/drm_dp_helper.c
3516
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
sys/dev/pci/drm/display/drm_dp_helper.c
3661
bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
sys/dev/pci/drm/display/drm_dp_helper.c
3750
bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
sys/dev/pci/drm/display/drm_dp_helper.c
4006
bool enable)
sys/dev/pci/drm/display/drm_dp_helper.c
4312
u32 *current_level, u8 *current_mode, bool need_luminance)
sys/dev/pci/drm/display/drm_dp_helper.c
4476
bool is_mst)
sys/dev/pci/drm/display/drm_dp_helper.c
4497
int bpp_x16, int symbol_size, bool is_mst)
sys/dev/pci/drm/display/drm_dp_helper.c
4545
bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
sys/dev/pci/drm/display/drm_dp_helper.c
4614
int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
sys/dev/pci/drm/display/drm_dp_helper.c
474
void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode)
sys/dev/pci/drm/display/drm_dp_helper.c
63
bool enabled;
sys/dev/pci/drm/display/drm_dp_helper.c
684
void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered)
sys/dev/pci/drm/display/drm_dp_helper.c
700
void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable)
sys/dev/pci/drm/display/drm_dp_helper.c
706
static bool dpcd_access_needs_probe(struct drm_dp_aux *aux)
sys/dev/pci/drm/display/drm_dp_helper.c
91
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1035
static bool drm_dp_sideband_parse_reply(const struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1081
static bool
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1111
static bool drm_dp_sideband_parse_resource_status_notify(const struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1135
static bool drm_dp_sideband_parse_req(const struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1217
int port_num, bool power_up)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
1250
static bool check_txmsg_state(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2052
static bool drm_dp_mst_is_end_device(u8 pdt, bool mcs)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2070
bool new_mcs)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2366
bool new_mcs = 0;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2367
bool created = false, send_link_addr = false, changed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2491
bool new_mcs;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2492
bool dowork = false, create_connector = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2640
bool changed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2671
bool clear_payload_id_table;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2717
static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2741
bool up, u8 *msg, int len)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2802
bool up)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
2934
bool changed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
302
static bool drm_dp_decode_sideband_msg_hdr(const struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3189
struct drm_dp_mst_port *port, bool power_up)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3386
bool send_remove = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3571
int req_type, bool broadcast)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3654
int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3807
bool sync)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3873
static bool
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3874
drm_dp_get_one_sb_msg(struct drm_dp_mst_topology_mgr *mgr, bool up,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3956
static bool verify_rx_request_type(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4045
static bool primary_mstb_probing_is_done(struct drm_dp_mst_topology_mgr *mgr)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4047
bool probing_done = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4061
static inline bool
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4068
bool hotplug = false, dowork = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4112
bool send_hotplug = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4243
u8 *ack, bool *handled)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4285
bool kick = true;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4543
bool update_payload = true;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4885
static bool dump_dp_payload_table(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5048
bool wake_tx = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5080
bool send_hotplug = false, go_again;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5197
static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5212
static bool
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5249
bool
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5254
bool ret;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5277
bool found = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
543
bool failed = false;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5490
int pbn, bool enable)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5803
static bool remote_i2c_read_ok(const struct i2c_msg msgs[], int num)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5820
static bool remote_i2c_write_ok(const struct i2c_msg msgs[], int num)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
6027
static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
66
static bool dump_dp_payload_table(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
787
static bool drm_dp_sideband_append_payload(struct drm_dp_sideband_msg_rx *msg,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
809
static bool drm_dp_sideband_parse_link_address(const struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
863
static bool drm_dp_sideband_parse_remote_dpcd_read(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
88
static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
884
static bool drm_dp_sideband_parse_remote_dpcd_write(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
899
static bool drm_dp_sideband_parse_remote_i2c_read_ack(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
918
static bool drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
942
static bool drm_dp_sideband_parse_allocate_payload_ack(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
95
static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
965
static bool drm_dp_sideband_parse_query_payload_ack(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
984
static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_msg_rx *raw,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
999
static bool
sys/dev/pci/drm/display/drm_dp_tunnel.c
1033
bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1049
static int bw_req_complete(struct drm_dp_aux *aux, bool *status_changed)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1108
bool status_changed;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1245
bool changed = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
148
bool bw_alloc_supported:1;
sys/dev/pci/drm/display/drm_dp_tunnel.c
149
bool bw_alloc_enabled:1;
sys/dev/pci/drm/display/drm_dp_tunnel.c
150
bool has_io_error:1;
sys/dev/pci/drm/display/drm_dp_tunnel.c
151
bool destroyed:1;
sys/dev/pci/drm/display/drm_dp_tunnel.c
1582
static bool init_group(struct drm_dp_tunnel_mgr *mgr, struct drm_dp_tunnel_group *group)
sys/dev/pci/drm/display/drm_dp_tunnel.c
185
bool active:1;
sys/dev/pci/drm/display/drm_dp_tunnel.c
275
static bool tunnel_reg_bw_alloc_supported(const struct drm_dp_tunnel_regs *regs)
sys/dev/pci/drm/display/drm_dp_tunnel.c
286
static bool tunnel_reg_bw_alloc_enabled(const struct drm_dp_tunnel_regs *regs)
sys/dev/pci/drm/display/drm_dp_tunnel.c
455
static bool add_tunnel_to_group(struct drm_dp_tunnel_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_tunnel.c
550
static bool tunnel_regs_are_valid(struct drm_dp_tunnel_mgr *mgr,
sys/dev/pci/drm/display/drm_dp_tunnel.c
555
bool check_dprx = !(flags & SKIP_DPRX_CAPS_CHECK);
sys/dev/pci/drm/display/drm_dp_tunnel.c
556
bool ret = true;
sys/dev/pci/drm/display/drm_dp_tunnel.c
621
static bool tunnel_info_changes_are_valid(struct drm_dp_tunnel *tunnel,
sys/dev/pci/drm/display/drm_dp_tunnel.c
626
bool ret = true;
sys/dev/pci/drm/display/drm_dp_tunnel.c
702
static bool update_dprx_caps(struct drm_dp_tunnel *tunnel, const struct drm_dp_tunnel_regs *regs)
sys/dev/pci/drm/display/drm_dp_tunnel.c
704
bool changed = false;
sys/dev/pci/drm/display/drm_dp_tunnel.c
873
bool changed;
sys/dev/pci/drm/display/drm_dp_tunnel.c
912
static int set_bw_alloc_mode(struct drm_dp_tunnel *tunnel, bool enable)
sys/dev/pci/drm/display/drm_hdcp_helper.c
8
bool hdcp_content_type)
sys/dev/pci/drm/display/drm_hdmi_audio_helper.c
116
bool plugged)
sys/dev/pci/drm/display/drm_hdmi_audio_helper.c
161
bool spdif_playback,
sys/dev/pci/drm/display/drm_hdmi_audio_helper.c
50
bool enable, int direction)
sys/dev/pci/drm/display/drm_hdmi_cec_helper.c
21
static int drm_connector_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
sys/dev/pci/drm/display/drm_hdmi_helper.c
13
static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
351
static bool hdmi_is_limited_range(const struct drm_connector *connector,
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
378
static bool
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
574
static bool
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
683
bool is_limited_range = conn_state->hdmi.is_limited_range;
sys/dev/pci/drm/display/drm_scdc_helper.c
154
bool drm_scdc_get_scrambling_status(struct drm_connector *connector)
sys/dev/pci/drm/display/drm_scdc_helper.c
183
bool drm_scdc_set_scrambling(struct drm_connector *connector,
sys/dev/pci/drm/display/drm_scdc_helper.c
184
bool enable)
sys/dev/pci/drm/display/drm_scdc_helper.c
243
bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector,
sys/dev/pci/drm/display/drm_scdc_helper.c
244
bool set)
sys/dev/pci/drm/dma-resv.c
445
bool restart;
sys/dev/pci/drm/dma-resv.c
691
bool intr, unsigned long timeout)
sys/dev/pci/drm/dma-resv.c
750
bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage)
sys/dev/pci/drm/drm_atomic.c
1852
bool take_locks)
sys/dev/pci/drm/drm_atomic.c
571
static bool
sys/dev/pci/drm/drm_atomic_helper.c
107
bool disable_conflicting_encoders)
sys/dev/pci/drm/drm_atomic_helper.c
1140
static bool
sys/dev/pci/drm/drm_atomic_helper.c
1841
bool pre_swap)
sys/dev/pci/drm/drm_atomic_helper.c
2250
bool nonblock)
sys/dev/pci/drm/drm_atomic_helper.c
2378
static int stall_checks(struct drm_crtc *crtc, bool nonblock)
sys/dev/pci/drm/drm_atomic_helper.c
2381
bool completed = true;
sys/dev/pci/drm/drm_atomic_helper.c
2515
bool nonblock)
sys/dev/pci/drm/drm_atomic_helper.c
2930
static bool plane_crtc_active(const struct drm_plane_state *state)
sys/dev/pci/drm/drm_atomic_helper.c
296
bool added_by_user)
sys/dev/pci/drm/drm_atomic_helper.c
2985
bool active_only = flags & DRM_PLANE_COMMIT_ACTIVE_ONLY;
sys/dev/pci/drm/drm_atomic_helper.c
2986
bool no_disable = flags & DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET;
sys/dev/pci/drm/drm_atomic_helper.c
3004
bool disabling;
sys/dev/pci/drm/drm_atomic_helper.c
3119
bool disabling;
sys/dev/pci/drm/drm_atomic_helper.c
3166
bool atomic)
sys/dev/pci/drm/drm_atomic_helper.c
3257
bool stall)
sys/dev/pci/drm/drm_atomic_helper.c
662
bool has_connectors =
sys/dev/pci/drm/drm_atomic_helper.c
902
bool can_position,
sys/dev/pci/drm/drm_atomic_helper.c
903
bool can_update_disabled)
sys/dev/pci/drm/drm_atomic_uapi.c
1016
bool async_flip)
sys/dev/pci/drm/drm_atomic_uapi.c
1347
bool install_fds)
sys/dev/pci/drm/drm_atomic_uapi.c
1419
bool async_flip = false;
sys/dev/pci/drm/drm_atomic_uapi.c
374
bool replaced = false;
sys/dev/pci/drm/drm_atomic_uapi.c
479
bool replaced = false;
sys/dev/pci/drm/drm_atomic_uapi.c
677
bool replaced = false;
sys/dev/pci/drm/drm_atomic_uapi.c
953
bool active = false;
sys/dev/pci/drm/drm_auth.c
157
bool new_master)
sys/dev/pci/drm/drm_auth.c
439
bool drm_master_internal_acquire(struct drm_device *dev)
sys/dev/pci/drm/drm_auth.c
64
static bool drm_is_current_master_locked(struct drm_file *fpriv)
sys/dev/pci/drm/drm_auth.c
86
bool drm_is_current_master(struct drm_file *fpriv)
sys/dev/pci/drm/drm_auth.c
88
bool ret;
sys/dev/pci/drm/drm_bridge.c
393
static bool drm_bridge_is_atomic(struct drm_bridge *bridge)
sys/dev/pci/drm/drm_buddy.c
165
static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
sys/dev/pci/drm/drm_buddy.c
170
static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)
sys/dev/pci/drm/drm_buddy.c
192
bool force_merge)
sys/dev/pci/drm/drm_buddy.c
497
void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear)
sys/dev/pci/drm/drm_buddy.c
557
bool mark_clear,
sys/dev/pci/drm/drm_buddy.c
558
bool mark_dirty)
sys/dev/pci/drm/drm_buddy.c
597
bool mark_clear = flags & DRM_BUDDY_CLEARED;
sys/dev/pci/drm/drm_buddy.c
603
static bool block_incompatible(struct drm_buddy_block *block, unsigned int flags)
sys/dev/pci/drm/drm_buddy.c
605
bool needs_clear = flags & DRM_BUDDY_CLEAR_ALLOCATION;
sys/dev/pci/drm/drm_buddy.c
615
bool fallback)
sys/dev/pci/drm/drm_buddy.c
709
bool fallback = false;
sys/dev/pci/drm/drm_buddy.c
84
static bool rbtree_is_empty(struct rb_root *root)
sys/dev/pci/drm/drm_buddy.c
89
static bool drm_buddy_block_offset_less(const struct drm_buddy_block *block,
sys/dev/pci/drm/drm_buddy.c
95
static bool rbtree_block_offset_less(struct rb_node *block,
sys/dev/pci/drm/drm_cache.c
180
bool drm_need_swiotlb(int dma_bits)
sys/dev/pci/drm/drm_client_event.c
125
static int drm_client_suspend(struct drm_client_dev *client, bool holds_console_lock)
sys/dev/pci/drm/drm_client_event.c
142
void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock)
sys/dev/pci/drm/drm_client_event.c
155
static int drm_client_resume(struct drm_client_dev *client, bool holds_console_lock)
sys/dev/pci/drm/drm_client_event.c
175
void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock)
sys/dev/pci/drm/drm_client_modeset.c
1044
static int drm_client_modeset_commit_atomic(struct drm_client_dev *client, bool active, bool check)
sys/dev/pci/drm/drm_client_modeset.c
177
bool prefer_non_interlace;
sys/dev/pci/drm/drm_client_modeset.c
230
static bool drm_connector_enabled(struct drm_connector *connector, bool strict)
sys/dev/pci/drm/drm_client_modeset.c
232
bool enable;
sys/dev/pci/drm/drm_client_modeset.c
247
bool enabled[])
sys/dev/pci/drm/drm_client_modeset.c
249
bool any_enabled = false;
sys/dev/pci/drm/drm_client_modeset.c
290
static bool drm_client_target_cloned(struct drm_device *dev,
sys/dev/pci/drm/drm_client_modeset.c
295
bool enabled[], int width, int height)
sys/dev/pci/drm/drm_client_modeset.c
298
bool can_clone = false;
sys/dev/pci/drm/drm_client_modeset.c
416
static bool drm_client_target_preferred(struct drm_device *dev,
sys/dev/pci/drm/drm_client_modeset.c
421
bool enabled[], int width, int height)
sys/dev/pci/drm/drm_client_modeset.c
531
static bool connector_has_possible_crtc(struct drm_connector *connector,
sys/dev/pci/drm/drm_client_modeset.c
619
static bool drm_client_firmware_config(struct drm_client_dev *client,
sys/dev/pci/drm/drm_client_modeset.c
625
bool enabled[], int width, int height)
sys/dev/pci/drm/drm_client_modeset.c
631
bool *save_enabled;
sys/dev/pci/drm/drm_client_modeset.c
632
bool fallback = true, ret = true;
sys/dev/pci/drm/drm_client_modeset.c
644
save_enabled = kcalloc(count, sizeof(bool), GFP_KERNEL);
sys/dev/pci/drm/drm_client_modeset.c
828
bool *enabled;
sys/dev/pci/drm/drm_client_modeset.c
869
enabled = kcalloc(connector_count, sizeof(bool), GFP_KERNEL);
sys/dev/pci/drm/drm_client_modeset.c
970
bool drm_client_rotation(struct drm_mode_set *modeset, unsigned int *rotation)
sys/dev/pci/drm/drm_color_mgmt.c
139
bool negative = !!(user_input & BIT_ULL(63));
sys/dev/pci/drm/drm_color_mgmt.c
168
bool has_ctm,
sys/dev/pci/drm/drm_color_mgmt.c
244
static bool drm_crtc_supports_legacy_gamma(struct drm_crtc *crtc)
sys/dev/pci/drm/drm_color_mgmt.c
289
bool use_gamma_lut;
sys/dev/pci/drm/drm_color_mgmt.c
291
bool replaced;
sys/dev/pci/drm/drm_connector.c
2946
bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state,
sys/dev/pci/drm/drm_connector.c
2972
struct drm_connector *connector, bool capable)
sys/dev/pci/drm/drm_connector.c
3159
struct drm_connector *connector, bool set_sw_state)
sys/dev/pci/drm/drm_connector.c
3295
static bool
sys/dev/pci/drm/drm_connector.c
3343
bool is_current_master;
sys/dev/pci/drm/drm_connector.c
702
bool drm_connector_has_possible_encoder(struct drm_connector *connector,
sys/dev/pci/drm/drm_crtc.c
954
bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/drm_crtc_helper.c
107
bool drm_helper_encoder_in_use(struct drm_encoder *encoder)
sys/dev/pci/drm/drm_crtc_helper.c
148
bool drm_helper_crtc_in_use(struct drm_crtc *crtc)
sys/dev/pci/drm/drm_crtc_helper.c
283
bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
sys/dev/pci/drm/drm_crtc_helper.c
293
bool saved_enabled;
sys/dev/pci/drm/drm_crtc_helper.c
295
bool ret = true;
sys/dev/pci/drm/drm_crtc_helper.c
558
bool mode_changed = false; /* if true do a full mode set */
sys/dev/pci/drm/drm_crtc_helper.c
559
bool fb_changed = false; /* if true and !mode_changed just do a flip */
sys/dev/pci/drm/drm_crtc_helper.c
988
bool ret;
sys/dev/pci/drm/drm_crtc_internal.h
136
bool drm_property_change_valid_get(struct drm_property *property,
sys/dev/pci/drm/drm_crtc_internal.h
154
uint32_t obj_type, bool register_obj,
sys/dev/pci/drm/drm_crtc_internal.h
165
int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomic,
sys/dev/pci/drm/drm_crtc_internal.h
263
u64 prop_value, bool async_flip);
sys/dev/pci/drm/drm_crtc_internal.h
320
bool drm_panic_is_enabled(struct drm_device *dev);
sys/dev/pci/drm/drm_crtc_internal.h
326
static inline bool drm_panic_is_enabled(struct drm_device *dev) { return false; }
sys/dev/pci/drm/drm_damage_helper.c
271
bool
sys/dev/pci/drm/drm_damage_helper.c
275
bool ret = false;
sys/dev/pci/drm/drm_damage_helper.c
312
bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state,
sys/dev/pci/drm/drm_damage_helper.c
318
bool valid = false;
sys/dev/pci/drm/drm_debugfs.c
98
bool is_current_master = drm_is_current_master(priv);
sys/dev/pci/drm/drm_debugfs_crc.c
394
int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool has_frame,
sys/dev/pci/drm/drm_debugfs_crc.c
414
bool was_overflow = crc->overflow;
sys/dev/pci/drm/drm_displayid.c
158
bool base_section = !iter->section;
sys/dev/pci/drm/drm_displayid.c
54
validate_displayid(const u8 *displayid, int length, int idx, bool ignore_checksum)
sys/dev/pci/drm/drm_displayid.c
86
bool ignore_checksum = iter->quirks & BIT(QUIRK_IGNORE_CHECKSUM);
sys/dev/pci/drm/drm_draw_internal.h
16
static inline bool drm_draw_is_pixel_fg(const u8 *sbuf8, unsigned int spitch, int x, int y)
sys/dev/pci/drm/drm_drv.c
522
bool drm_dev_enter(struct drm_device *dev, int *idx)
sys/dev/pci/drm/drm_drv.c
89
static bool drm_core_init_complete;
sys/dev/pci/drm/drm_edid.c
106
bool preferred;
sys/dev/pci/drm/drm_edid.c
112
bool matched;
sys/dev/pci/drm/drm_edid.c
1829
static bool edid_block_is_zero(const void *edid)
sys/dev/pci/drm/drm_edid.c
1834
static bool drm_edid_eq(const struct drm_edid *drm_edid,
sys/dev/pci/drm/drm_edid.c
1837
bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size;
sys/dev/pci/drm/drm_edid.c
1838
bool edid2_present = raw_edid && raw_edid_size;
sys/dev/pci/drm/drm_edid.c
1867
bool is_base_block)
sys/dev/pci/drm/drm_edid.c
1903
static bool edid_block_status_valid(enum edid_block_status status, int tag)
sys/dev/pci/drm/drm_edid.c
1910
static bool edid_block_valid(const void *block, bool base)
sys/dev/pci/drm/drm_edid.c
1984
static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid,
sys/dev/pci/drm/drm_edid.c
1985
bool *edid_corrupt)
sys/dev/pci/drm/drm_edid.c
1989
bool is_base_block = block_num == 0;
sys/dev/pci/drm/drm_edid.c
1990
bool valid;
sys/dev/pci/drm/drm_edid.c
2039
bool drm_edid_is_valid(struct edid *edid)
sys/dev/pci/drm/drm_edid.c
2066
bool drm_edid_valid(const struct drm_edid *drm_edid)
sys/dev/pci/drm/drm_edid.c
2345
bool is_base_block = block_num == 0;
sys/dev/pci/drm/drm_edid.c
2608
bool
sys/dev/pci/drm/drm_edid.c
2787
const struct drm_edid_product_id *id, bool raw)
sys/dev/pci/drm/drm_edid.c
2999
static bool drm_edid_has_internal_quirk(struct drm_connector *connector,
sys/dev/pci/drm/drm_edid.c
3005
bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk)
sys/dev/pci/drm/drm_edid.c
3058
static bool
sys/dev/pci/drm/drm_edid.c
3081
bool rb)
sys/dev/pci/drm/drm_edid.c
3104
static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
sys/dev/pci/drm/drm_edid.c
3115
static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
sys/dev/pci/drm/drm_edid.c
3184
bool *res = data;
sys/dev/pci/drm/drm_edid.c
3198
static bool
sys/dev/pci/drm/drm_edid.c
3202
bool ret = false;
sys/dev/pci/drm/drm_edid.c
3638
static bool
sys/dev/pci/drm/drm_edid.c
3655
static bool
sys/dev/pci/drm/drm_edid.c
3687
static bool mode_in_range(const struct drm_display_mode *mode,
sys/dev/pci/drm/drm_edid.c
3717
static bool valid_inferred_mode(const struct drm_connector *connector,
sys/dev/pci/drm/drm_edid.c
3721
bool ok = false;
sys/dev/pci/drm/drm_edid.c
3835
bool rb = drm_monitor_supports_rb(drm_edid);
sys/dev/pci/drm/drm_edid.c
4236
static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
sys/dev/pci/drm/drm_edid.c
4242
bool found = false;
sys/dev/pci/drm/drm_edid.c
4319
static bool
sys/dev/pci/drm/drm_edid.c
4433
static bool drm_valid_cea_vic(u8 vic)
sys/dev/pci/drm/drm_edid.c
4529
static bool drm_valid_hdmi_vic(u8 vic)
sys/dev/pci/drm/drm_edid.c
4732
static bool
sys/dev/pci/drm/drm_edid.c
4832
static bool hdmi_vsdb_latency_present(const u8 *db)
sys/dev/pci/drm/drm_edid.c
4837
static bool hdmi_vsdb_i_latency_present(const u8 *db)
sys/dev/pci/drm/drm_edid.c
4940
bool detail_present;
sys/dev/pci/drm/drm_edid.c
5050
static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
sys/dev/pci/drm/drm_edid.c
5057
static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
sys/dev/pci/drm/drm_edid.c
5217
static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5223
static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5229
static bool cea_db_is_hdmi_forum_eeodb(const void *db)
sys/dev/pci/drm/drm_edid.c
5235
static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5241
static bool cea_db_is_vcdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5247
static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5253
static bool cea_db_is_y420cmdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5258
static bool cea_db_is_y420vdb(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5263
static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
sys/dev/pci/drm/drm_edid.c
5583
bool drm_edid_match(const struct drm_edid *drm_edid,
sys/dev/pci/drm/drm_edid.c
5923
static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
sys/dev/pci/drm/drm_edid.c
5927
bool hdmi = false;
sys/dev/pci/drm/drm_edid.c
5956
bool drm_detect_hdmi_monitor(const struct edid *edid)
sys/dev/pci/drm/drm_edid.c
5964
static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
sys/dev/pci/drm/drm_edid.c
5970
bool has_audio = false;
sys/dev/pci/drm/drm_edid.c
6018
bool drm_detect_monitor_audio(const struct edid *edid)
sys/dev/pci/drm/drm_edid.c
6104
static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
sys/dev/pci/drm/drm_edid.c
6276
bool dsc_support = false;
sys/dev/pci/drm/drm_edid.c
6434
bool desktop_usage = db[5] & BIT(6);
sys/dev/pci/drm/drm_edid.c
6831
bool type_7)
sys/dev/pci/drm/drm_edid.c
6845
bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
sys/dev/pci/drm/drm_edid.c
6846
bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
sys/dev/pci/drm/drm_edid.c
6884
bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
sys/dev/pci/drm/drm_edid.c
6905
bool type_10)
sys/dev/pci/drm/drm_edid.c
6939
bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING;
sys/dev/pci/drm/drm_edid.c
7263
static bool is_hdmi2_sink(const struct drm_connector *connector)
sys/dev/pci/drm/drm_edid.c
7279
bool has_hdmi_infoframe = connector ?
sys/dev/pci/drm/drm_edid.c
7508
bool has_hdmi_infoframe = connector ?
sys/dev/pci/drm/drm_edid.c
7593
static bool displayid_is_tiled_block(const struct displayid_iter *iter,
sys/dev/pci/drm/drm_edid.c
7629
bool drm_edid_is_digital(const struct drm_edid *drm_edid)
sys/dev/pci/drm/drm_encoder.c
308
bool uses_atomic = false;
sys/dev/pci/drm/drm_exec.c
123
bool drm_exec_cleanup(struct drm_exec *exec)
sys/dev/pci/drm/drm_fb_helper.c
1142
static bool drm_fb_pixel_format_equal(const struct fb_var_screeninfo *var_1,
sys/dev/pci/drm/drm_fb_helper.c
1358
bool force;
sys/dev/pci/drm/drm_fb_helper.c
1594
bool lastv = true, lasth = true;
sys/dev/pci/drm/drm_fb_helper.c
1710
bool is_color_indexed)
sys/dev/pci/drm/drm_fb_helper.c
218
bool force)
sys/dev/pci/drm/drm_fb_helper.c
220
bool do_delayed;
sys/dev/pci/drm/drm_fb_helper.c
48
static bool drm_fbdev_emulation = true;
sys/dev/pci/drm/drm_fb_helper.c
49
module_param_named(fbdev_emulation, drm_fbdev_emulation, bool, 0600);
sys/dev/pci/drm/drm_fb_helper.c
72
static bool drm_leak_fbdev_smem;
sys/dev/pci/drm/drm_fb_helper.c
74
module_param_unsafe(drm_leak_fbdev_smem, bool, 0600);
sys/dev/pci/drm/drm_fb_helper.c
772
void drm_fb_helper_set_suspend(struct drm_fb_helper *fb_helper, bool suspend)
sys/dev/pci/drm/drm_fb_helper.c
801
bool suspend)
sys/dev/pci/drm/drm_fb_helper.c
960
bool replaced;
sys/dev/pci/drm/drm_file.c
57
bool drm_dev_needs_global_mutex(struct drm_device *dev)
sys/dev/pci/drm/drm_format_helper.c
149
const struct drm_rect *clip, bool vaddr_cached_hint,
sys/dev/pci/drm/drm_format_helper.c
191
const struct drm_rect *clip, bool vaddr_cached_hint,
sys/dev/pci/drm/drm_format_helper.c
236
const struct drm_rect *clip, bool vaddr_cached_hint,
sys/dev/pci/drm/drm_format_helper.c
502
const struct drm_rect *clip, bool cached,
sys/dev/pci/drm/drm_framebuffer.c
1013
bool disable_crtcs = false;
sys/dev/pci/drm/drm_framebuffer.c
403
bool found = false;
sys/dev/pci/drm/drm_framebuffer.c
868
bool exists;
sys/dev/pci/drm/drm_gem.c
1048
bool wait_all, unsigned long timeout)
sys/dev/pci/drm/drm_gem.c
1838
bool (*shrink)(struct drm_gem_object *obj, struct ww_acquire_ctx *ticket),
sys/dev/pci/drm/drm_gem.c
422
bool drm_gem_object_handle_get_if_exists_unlocked(struct drm_gem_object *obj)
sys/dev/pci/drm/drm_gem.c
481
bool final = false;
sys/dev/pci/drm/drm_gem.c
890
bool dirty, bool accessed)
sys/dev/pci/drm/drm_gpusvm.c
1189
static bool drm_gpusvm_pages_valid(struct drm_gpusvm *gpusvm,
sys/dev/pci/drm/drm_gpusvm.c
1211
bool drm_gpusvm_range_pages_valid(struct drm_gpusvm *gpusvm,
sys/dev/pci/drm/drm_gpusvm.c
1228
static bool drm_gpusvm_pages_valid_unlocked(struct drm_gpusvm *gpusvm,
sys/dev/pci/drm/drm_gpusvm.c
1231
bool pages_valid;
sys/dev/pci/drm/drm_gpusvm.c
1596
bool drm_gpusvm_has_mapping(struct drm_gpusvm *gpusvm, unsigned long start,
sys/dev/pci/drm/drm_gpusvm.c
331
static bool
sys/dev/pci/drm/drm_gpusvm.c
625
bool migrate_devmem)
sys/dev/pci/drm/drm_gpusvm.c
691
static bool drm_gpusvm_check_pages(struct drm_gpusvm *gpusvm,
sys/dev/pci/drm/drm_gpusvm.c
903
bool notifier_alloc = false;
sys/dev/pci/drm/drm_gpusvm.c
906
bool migrate_devmem;
sys/dev/pci/drm/drm_gpuvm.c
1001
bool
sys/dev/pci/drm/drm_gpuvm.c
1576
bool lock = !drm_gpuvm_resv_protected(gpuvm);
sys/dev/pci/drm/drm_gpuvm.c
1612
bool
sys/dev/pci/drm/drm_gpuvm.c
1745
bool lock = !drm_gpuvm_resv_protected(gpuvm);
sys/dev/pci/drm/drm_gpuvm.c
1764
drm_gpuvm_bo_evict(struct drm_gpuvm_bo *vm_bo, bool evict)
sys/dev/pci/drm/drm_gpuvm.c
1768
bool lock = !drm_gpuvm_resv_protected(gpuvm);
sys/dev/pci/drm/drm_gpuvm.c
2051
bool
sys/dev/pci/drm/drm_gpuvm.c
2161
struct drm_gpuva *va, bool merge, bool madvise)
sys/dev/pci/drm/drm_gpuvm.c
2179
bool madvise)
sys/dev/pci/drm/drm_gpuvm.c
2199
bool merge = !!va->gem.obj;
sys/dev/pci/drm/drm_gpuvm.c
2368
bool prev_split = false, next_split = false;
sys/dev/pci/drm/drm_gpuvm.c
2712
bool madvise)
sys/dev/pci/drm/drm_gpuvm.c
856
cond_spin_lock(spinlock_t *lock, bool cond)
sys/dev/pci/drm/drm_gpuvm.c
863
cond_spin_unlock(spinlock_t *lock, bool cond)
sys/dev/pci/drm/drm_gpuvm.c
896
struct list_head *entry, bool init)
sys/dev/pci/drm/drm_gpuvm.c
954
static bool
sys/dev/pci/drm/drm_gpuvm.c
962
static bool
sys/dev/pci/drm/drm_gpuvm.c
969
static bool
sys/dev/pci/drm/drm_gpuvm.c
979
static bool
sys/dev/pci/drm/drm_internal.h
148
bool drm_master_internal_acquire(struct drm_device *dev);
sys/dev/pci/drm/drm_internal.h
196
bool drm_gem_object_handle_get_if_exists_unlocked(struct drm_gem_object *obj);
sys/dev/pci/drm/drm_internal.h
61
bool drm_dev_needs_global_mutex(struct drm_device *dev);
sys/dev/pci/drm/drm_internal.h
98
static inline bool drm_vblank_passed(u64 seq, u64 ref)
sys/dev/pci/drm/drm_ioctl.c
1001
bool drm_ioctl_flags(unsigned int nr, unsigned int *flags)
sys/dev/pci/drm/drm_ioctl.c
898
bool is_driver_ioctl;
sys/dev/pci/drm/drm_linux.c
1855
bool
sys/dev/pci/drm/drm_linux.c
1869
bool
sys/dev/pci/drm/drm_linux.c
1918
dma_fence_wait_timeout(struct dma_fence *fence, bool intr, long timeout)
sys/dev/pci/drm/drm_linux.c
1930
dma_fence_wait(struct dma_fence *fence, bool intr)
sys/dev/pci/drm/drm_linux.c
1981
bool was_set;
sys/dev/pci/drm/drm_linux.c
2014
bool
sys/dev/pci/drm/drm_linux.c
2017
bool ret;
sys/dev/pci/drm/drm_linux.c
2052
dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
sys/dev/pci/drm/drm_linux.c
2058
bool was_set;
sys/dev/pci/drm/drm_linux.c
2109
static bool
sys/dev/pci/drm/drm_linux.c
2128
bool intr, long timeout, uint32_t *idx)
sys/dev/pci/drm/drm_linux.c
2263
static bool
sys/dev/pci/drm/drm_linux.c
228
bool
sys/dev/pci/drm/drm_linux.c
2284
static bool
sys/dev/pci/drm/drm_linux.c
2307
unsigned seqno, bool signal_on_any)
sys/dev/pci/drm/drm_linux.c
239
bool
sys/dev/pci/drm/drm_linux.c
242
bool ret = false;
sys/dev/pci/drm/drm_linux.c
2439
static bool dma_fence_chain_enable_signaling(struct dma_fence *);
sys/dev/pci/drm/drm_linux.c
2461
static bool
sys/dev/pci/drm/drm_linux.c
2487
static bool
sys/dev/pci/drm/drm_linux.c
2568
bool
sys/dev/pci/drm/drm_linux.c
2831
bool
sys/dev/pci/drm/drm_linux.c
332
bool
sys/dev/pci/drm/drm_linux.c
339
bool
sys/dev/pci/drm/drm_linux.c
448
bool
sys/dev/pci/drm/drm_linux.c
500
static bool
sys/dev/pci/drm/drm_linux.c
724
bool
sys/dev/pci/drm/drm_linux.c
755
int rowsize, int groupsize, const void *buf, size_t len, bool ascii)
sys/dev/pci/drm/drm_mipi_dsi.c
1598
bool enable,
sys/dev/pci/drm/drm_mipi_dsi.c
1627
bool enable)
sys/dev/pci/drm/drm_mipi_dsi.c
481
bool mipi_dsi_packet_format_is_short(u8 type)
sys/dev/pci/drm/drm_mipi_dsi.c
519
bool mipi_dsi_packet_format_is_long(u8 type)
sys/dev/pci/drm/drm_mipi_dsi.c
677
int mipi_dsi_compression_mode_ext(struct mipi_dsi_device *dsi, bool enable,
sys/dev/pci/drm/drm_mipi_dsi.c
713
int mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
sys/dev/pci/drm/drm_mm.c
197
bool leftmost;
sys/dev/pci/drm/drm_mm.c
270
bool first = true;
sys/dev/pci/drm/drm_mm.c
501
bool once;
sys/dev/pci/drm/drm_mm.c
592
static inline bool drm_mm_node_scanned_block(const struct drm_mm_node *node)
sys/dev/pci/drm/drm_mm.c
758
bool drm_mm_scan_add_block(struct drm_mm_scan *scan,
sys/dev/pci/drm/drm_mm.c
849
bool drm_mm_scan_remove_block(struct drm_mm_scan *scan,
sys/dev/pci/drm/drm_mode_object.c
126
bool drm_mode_object_lease_required(uint32_t type)
sys/dev/pci/drm/drm_mode_object.c
408
int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomic,
sys/dev/pci/drm/drm_mode_object.c
41
uint32_t obj_type, bool register_obj,
sys/dev/pci/drm/drm_modes.c
1055
bool interlaced, int margins)
sys/dev/pci/drm/drm_modes.c
1272
bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
sys/dev/pci/drm/drm_modes.c
1472
static bool drm_mode_match_timings(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1487
static bool drm_mode_match_clock(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1500
static bool drm_mode_match_flags(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1507
static bool drm_mode_match_3d_flags(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1514
static bool drm_mode_match_aspect_ratio(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1531
bool drm_mode_match(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1575
bool drm_mode_equal(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1598
bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1619
bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
sys/dev/pci/drm/drm_modes.c
1807
struct list_head *mode_list, bool verbose)
sys/dev/pci/drm/drm_modes.c
1895
bool found_it = false;
sys/dev/pci/drm/drm_modes.c
1979
bool freestanding,
sys/dev/pci/drm/drm_modes.c
2030
bool extras,
sys/dev/pci/drm/drm_modes.c
2035
bool rb = false, cvt = false;
sys/dev/pci/drm/drm_modes.c
2168
bool freestanding,
sys/dev/pci/drm/drm_modes.c
2369
bool drm_mode_parse_command_line_for_connector(const char *mode_option,
sys/dev/pci/drm/drm_modes.c
2375
bool freestanding = false, parse_extras = false;
sys/dev/pci/drm/drm_modes.c
2723
bool drm_mode_is_420_only(const struct drm_display_info *display,
sys/dev/pci/drm/drm_modes.c
2743
bool drm_mode_is_420_also(const struct drm_display_info *display,
sys/dev/pci/drm/drm_modes.c
2762
bool drm_mode_is_420(const struct drm_display_info *display,
sys/dev/pci/drm/drm_modes.c
331
bool interlace)
sys/dev/pci/drm/drm_modes.c
344
bool bt601 = false;
sys/dev/pci/drm/drm_modes.c
550
bool interlace)
sys/dev/pci/drm/drm_modes.c
625
bool reduced, bool interlaced, bool margins)
sys/dev/pci/drm/drm_modes.c
850
int vrefresh, bool interlaced, int margins,
sys/dev/pci/drm/drm_modeset_lock.c
298
bool interruptible, bool slow)
sys/dev/pci/drm/drm_panel.c
572
bool drm_is_panel_follower(struct device *dev)
sys/dev/pci/drm/drm_panic.c
431
bool centered,
sys/dev/pci/drm/drm_panic.c
832
static bool drm_panic_is_format_supported(const struct drm_format_info *format)
sys/dev/pci/drm/drm_panic.c
929
bool run;
sys/dev/pci/drm/drm_panic.c
963
bool drm_panic_is_enabled(struct drm_device *dev)
sys/dev/pci/drm/drm_plane.c
199
bool (*format_mod_supported)
sys/dev/pci/drm/drm_plane.c
916
bool drm_plane_has_format(struct drm_plane *plane,
sys/dev/pci/drm/drm_plane.c
996
bool drm_any_plane_has_format(struct drm_device *dev,
sys/dev/pci/drm/drm_plane_helper.c
103
bool can_position,
sys/dev/pci/drm/drm_plane_helper.c
104
bool can_update_disabled,
sys/dev/pci/drm/drm_plane_helper.c
105
bool *visible)
sys/dev/pci/drm/drm_plane_helper.c
195
bool visible;
sys/dev/pci/drm/drm_prime.c
984
bool drm_gem_is_prime_exported_dma_buf(struct drm_device *dev,
sys/dev/pci/drm/drm_print.c
321
bool first = true;
sys/dev/pci/drm/drm_privacy_screen_x86.c
17
bool (*detect)(void);
sys/dev/pci/drm/drm_privacy_screen_x86.c
28
static bool __init detect_thinkpad_privacy_screen(void)
sys/dev/pci/drm/drm_privacy_screen_x86.c
54
static bool __init detect_chromeos_privacy_screen(void)
sys/dev/pci/drm/drm_probe_helper.c
1038
bool drm_connector_helper_hpd_irq_event(struct drm_connector *connector)
sys/dev/pci/drm/drm_probe_helper.c
1041
bool changed;
sys/dev/pci/drm/drm_probe_helper.c
1085
bool drm_helper_hpd_irq_event(struct drm_device *dev)
sys/dev/pci/drm/drm_probe_helper.c
1323
bool force)
sys/dev/pci/drm/drm_probe_helper.c
243
static bool drm_kms_helper_enable_hpd(struct drm_device *dev)
sys/dev/pci/drm/drm_probe_helper.c
245
bool poll = false;
sys/dev/pci/drm/drm_probe_helper.c
344
bool force)
sys/dev/pci/drm/drm_probe_helper.c
357
drm_helper_probe_detect_ctx(struct drm_connector *connector, bool force)
sys/dev/pci/drm/drm_probe_helper.c
399
bool force)
sys/dev/pci/drm/drm_probe_helper.c
67
static bool drm_kms_helper_poll = true;
sys/dev/pci/drm/drm_probe_helper.c
68
module_param_named(poll, drm_kms_helper_poll, bool, 0600);
sys/dev/pci/drm/drm_probe_helper.c
763
bool repoll = false, changed;
sys/dev/pci/drm/drm_probe_helper.c
866
bool drm_kms_helper_is_poll_worker(void)
sys/dev/pci/drm/drm_probe_helper.c
978
static bool check_connector_changed(struct drm_connector *connector)
sys/dev/pci/drm/drm_property.c
59
static bool drm_property_flags_valid(u32 flags)
sys/dev/pci/drm/drm_property.c
739
bool drm_property_replace_blob(struct drm_property_blob **blob,
sys/dev/pci/drm/drm_property.c
776
bool *replaced)
sys/dev/pci/drm/drm_property.c
883
bool found = false;
sys/dev/pci/drm/drm_property.c
933
bool drm_property_change_valid_get(struct drm_property *property,
sys/dev/pci/drm/drm_rect.c
227
void drm_rect_debug_print(const char *prefix, const struct drm_rect *r, bool fixed_point)
sys/dev/pci/drm/drm_rect.c
44
bool drm_rect_intersect(struct drm_rect *r1, const struct drm_rect *r2)
sys/dev/pci/drm/drm_rect.c
91
bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst,
sys/dev/pci/drm/drm_self_refresh_helper.c
155
bool new_self_refresh_active = new_self_refresh_mask & BIT(i);
sys/dev/pci/drm/drm_suballoc.c
164
static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager,
sys/dev/pci/drm/drm_suballoc.c
188
static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager,
sys/dev/pci/drm/drm_suballoc.c
215
static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager,
sys/dev/pci/drm/drm_suballoc.c
218
bool ret;
sys/dev/pci/drm/drm_suballoc.c
226
static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager,
sys/dev/pci/drm/drm_suballoc.c
316
gfp_t gfp, bool intr, size_t align)
sys/dev/pci/drm/drm_syncobj.c
1322
struct drm_syncobj **syncobjs, bool timeline,
sys/dev/pci/drm/drm_vblank.c
156
static bool
sys/dev/pci/drm/drm_vblank.c
158
ktime_t *tvblank, bool in_vblank_irq);
sys/dev/pci/drm/drm_vblank.c
1701
static bool drm_wait_vblank_is_query(union drm_wait_vblank *vblwait)
sys/dev/pci/drm/drm_vblank.c
1745
static bool drm_wait_vblank_supported(struct drm_device *dev)
sys/dev/pci/drm/drm_vblank.c
1895
bool high_prec = false;
sys/dev/pci/drm/drm_vblank.c
1934
bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe)
sys/dev/pci/drm/drm_vblank.c
1938
bool disable_irq;
sys/dev/pci/drm/drm_vblank.c
2008
bool drm_crtc_handle_vblank(struct drm_crtc *crtc)
sys/dev/pci/drm/drm_vblank.c
2030
bool vblank_enabled;
sys/dev/pci/drm/drm_vblank.c
242
bool rc;
sys/dev/pci/drm/drm_vblank.c
287
bool in_vblank_irq)
sys/dev/pci/drm/drm_vblank.c
291
bool rc;
sys/dev/pci/drm/drm_vblank.c
583
bool drm_dev_has_vblank(const struct drm_device *dev)
sys/dev/pci/drm/drm_vblank.c
696
bool
sys/dev/pci/drm/drm_vblank.c
699
bool in_vblank_irq,
sys/dev/pci/drm/drm_vblank.c
707
bool vbl_status;
sys/dev/pci/drm/drm_vblank.c
840
bool drm_crtc_vblank_helper_get_vblank_timestamp(struct drm_crtc *crtc,
sys/dev/pci/drm/drm_vblank.c
843
bool in_vblank_irq)
sys/dev/pci/drm/drm_vblank.c
871
static bool
sys/dev/pci/drm/drm_vblank.c
873
bool in_vblank_irq)
sys/dev/pci/drm/drm_vblank.c
875
bool ret = false;
sys/dev/pci/drm/drm_vblank.c
895
static bool
sys/dev/pci/drm/drm_vblank.c
897
ktime_t *tvblank, bool in_vblank_irq)
sys/dev/pci/drm/drm_vblank_work.c
114
u64 count, bool nextonmiss)
sys/dev/pci/drm/drm_vblank_work.c
120
bool passed, inmodeset, rescheduling = false, wake = false;
sys/dev/pci/drm/drm_vblank_work.c
189
bool drm_vblank_work_cancel_sync(struct drm_vblank_work *work)
sys/dev/pci/drm/drm_vblank_work.c
193
bool ret = false;
sys/dev/pci/drm/drm_vblank_work.c
54
bool wake = false;
sys/dev/pci/drm/drm_vma_manager.c
245
struct drm_file *tag, bool ref_counted)
sys/dev/pci/drm/drm_vma_manager.c
399
bool drm_vma_node_is_allowed(struct drm_vma_offset_node *node,
sys/dev/pci/drm/i915/display/dvo_ch7017.c
169
static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable);
sys/dev/pci/drm/i915/display/dvo_ch7017.c
171
static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)
sys/dev/pci/drm/i915/display/dvo_ch7017.c
190
static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
sys/dev/pci/drm/i915/display/dvo_ch7017.c
203
static bool ch7017_init(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/dvo_ch7017.c
337
static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/pci/drm/i915/display/dvo_ch7017.c
365
static bool ch7017_get_hw_state(struct intel_dvo_device *dvo)
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
121
bool quiet;
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
149
static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
187
static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
213
static bool ch7xxx_init(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
335
static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/pci/drm/i915/display/dvo_ch7xxx.c
343
static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo)
sys/dev/pci/drm/i915/display/dvo_ivch.c
178
bool quiet;
sys/dev/pci/drm/i915/display/dvo_ivch.c
194
static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data)
sys/dev/pci/drm/i915/display/dvo_ivch.c
237
static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data)
sys/dev/pci/drm/i915/display/dvo_ivch.c
265
static bool ivch_init(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/dvo_ivch.c
345
static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/pci/drm/i915/display/dvo_ivch.c
383
static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
sys/dev/pci/drm/i915/display/dvo_ns2501.c
381
bool quiet;
sys/dev/pci/drm/i915/display/dvo_ns2501.c
393
static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
sys/dev/pci/drm/i915/display/dvo_ns2501.c
438
static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
sys/dev/pci/drm/i915/display/dvo_ns2501.c
472
static bool ns2501_init(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/dvo_ns2501.c
645
static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
sys/dev/pci/drm/i915/display/dvo_ns2501.c
656
static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/pci/drm/i915/display/dvo_sil164.c
112
static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
sys/dev/pci/drm/i915/display/dvo_sil164.c
139
static bool sil164_init(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/dvo_sil164.c
224
static void sil164_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/pci/drm/i915/display/dvo_sil164.c
241
static bool sil164_get_hw_state(struct intel_dvo_device *dvo)
sys/dev/pci/drm/i915/display/dvo_sil164.c
70
bool quiet;
sys/dev/pci/drm/i915/display/dvo_sil164.c
75
static bool sil164_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
sys/dev/pci/drm/i915/display/dvo_tfp410.c
133
static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
sys/dev/pci/drm/i915/display/dvo_tfp410.c
171
static bool tfp410_init(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/dvo_tfp410.c
240
static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable)
sys/dev/pci/drm/i915/display/dvo_tfp410.c
255
static bool tfp410_get_hw_state(struct intel_dvo_device *dvo)
sys/dev/pci/drm/i915/display/dvo_tfp410.c
93
bool quiet;
sys/dev/pci/drm/i915/display/dvo_tfp410.c
96
static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
sys/dev/pci/drm/i915/display/g4x_dp.c
1188
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/g4x_dp.c
1196
static bool g4x_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/g4x_dp.c
1219
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/g4x_dp.c
1284
bool g4x_dp_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_dp.c
171
static void assert_dp_port(struct intel_dp *intel_dp, bool state)
sys/dev/pci/drm/i915/display/g4x_dp.c
175
bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
sys/dev/pci/drm/i915/display/g4x_dp.c
184
static void assert_edp_pll(struct intel_display *display, bool state)
sys/dev/pci/drm/i915/display/g4x_dp.c
186
bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;
sys/dev/pci/drm/i915/display/g4x_dp.c
253
static bool cpt_dp_port_selected(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_dp.c
276
bool g4x_dp_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_dp.c
280
bool ret;
sys/dev/pci/drm/i915/display/g4x_dp.c
300
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/g4x_dp.c
306
bool ret;
sys/dev/pci/drm/i915/display/g4x_dp.c
916
bool uniq_trans_scale = false;
sys/dev/pci/drm/i915/display/g4x_dp.h
22
bool g4x_dp_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_dp.h
25
bool g4x_dp_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_dp.h
32
static inline bool g4x_dp_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_dp.h
38
static inline bool g4x_dp_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
655
static bool is_hdmi_port_valid(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
66
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
663
static bool assert_hdmi_port_valid(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
669
bool g4x_hdmi_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
72
bool ret;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
86
static bool connector_is_hdmi(struct drm_connector *connector)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
94
static bool g4x_compute_has_hdmi_sink(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/g4x_hdmi.h
19
bool g4x_hdmi_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/g4x_hdmi.h
24
static inline bool g4x_hdmi_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/hsw_ips.c
124
bool hsw_ips_pre_update(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/hsw_ips.c
136
static bool hsw_ips_need_enable(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/hsw_ips.c
185
bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/hsw_ips.c
192
static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
65
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
68
bool need_vblank_wait = false;
sys/dev/pci/drm/i915/display/hsw_ips.c
95
static bool hsw_ips_need_disable(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/hsw_ips.h
16
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.h
17
bool hsw_ips_pre_update(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/hsw_ips.h
21
bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
sys/dev/pci/drm/i915/display/hsw_ips.h
28
static inline bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.h
32
static inline bool hsw_ips_pre_update(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/hsw_ips.h
41
static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/i9xx_plane.c
116
static bool i9xx_plane_has_fbc(struct intel_display *display,
sys/dev/pci/drm/i915/display/i9xx_plane.c
1252
bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/i9xx_plane.c
142
static bool i9xx_plane_has_windowing(struct intel_plane *plane)
sys/dev/pci/drm/i915/display/i9xx_plane.c
606
bool async_flip)
sys/dev/pci/drm/i915/display/i9xx_plane.c
624
bool async_flip)
sys/dev/pci/drm/i915/display/i9xx_plane.c
716
static bool i9xx_plane_can_async_flip(u64 modifier)
sys/dev/pci/drm/i915/display/i9xx_plane.c
721
static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
sys/dev/pci/drm/i915/display/i9xx_plane.c
728
bool ret;
sys/dev/pci/drm/i915/display/i9xx_plane.c
73
static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/i9xx_plane.c
91
static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/i9xx_plane.h
34
bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/i9xx_plane.h
56
static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1023
static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1027
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1039
static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1043
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1062
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1068
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1135
static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1143
static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
115
static void chv_set_memory_dvfs(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1182
static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
141
static void chv_set_memory_pm5(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1547
static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
sys/dev/pci/drm/i915/display/i9xx_wm.c
160
static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/i9xx_wm.c
162
bool was_enabled;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1665
static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1669
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1681
static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1688
bool dirty = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1722
static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1733
static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2138
bool cxsr_enabled;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2449
u32 mem_value, bool is_lp)
sys/dev/pci/drm/i915/display/i9xx_wm.c
249
bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/i9xx_wm.c
251
bool ret;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2555
int level, bool is_sprite)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2593
bool is_sprite)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2664
static bool ilk_validate_wm_level(struct intel_display *display,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2669
bool ret;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2806
static bool ilk_increase_wm_latency(struct intel_display *display, u16 wm[5], u16 min)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2822
bool changed;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2898
static bool ilk_validate_pipe_wm(struct intel_display *display,
sys/dev/pci/drm/i915/display/i9xx_wm.c
3323
static bool _ilk_disable_lp_wm(struct intel_display *display,
sys/dev/pci/drm/i915/display/i9xx_wm.c
3327
bool changed = false;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3412
bool ilk_disable_cxsr(struct intel_display *display)
sys/dev/pci/drm/i915/display/i9xx_wm.c
37
bool sprites_enabled;
sys/dev/pci/drm/i915/display/i9xx_wm.c
38
bool sprites_scaled;
sys/dev/pci/drm/i915/display/i9xx_wm.c
42
bool is_desktop : 1;
sys/dev/pci/drm/i915/display/i9xx_wm.c
43
bool is_ddr3 : 1;
sys/dev/pci/drm/i915/display/i9xx_wm.c
609
static bool is_disabling(int old, int new, int threshold)
sys/dev/pci/drm/i915/display/i9xx_wm.c
614
static bool is_enabling(int old, int new, int threshold)
sys/dev/pci/drm/i915/display/i9xx_wm.c
619
static bool intel_crtc_active(struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/i9xx_wm.c
718
static bool i9xx_wm_need_update(const struct intel_plane_state *old_plane_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
743
bool turn_off, turn_on, visible, was_visible, mode_changed;
sys/dev/pci/drm/i915/display/i9xx_wm.c
93
bool is_ddr3 = dram_info->type == INTEL_DRAM_DDR3;
sys/dev/pci/drm/i915/display/i9xx_wm.c
98
bool is_desktop = !display->platform.mobile;
sys/dev/pci/drm/i915/display/i9xx_wm.h
16
bool ilk_disable_cxsr(struct intel_display *display);
sys/dev/pci/drm/i915/display/i9xx_wm.h
18
bool intel_set_memory_cxsr(struct intel_display *display, bool enable);
sys/dev/pci/drm/i915/display/i9xx_wm.h
21
static inline bool ilk_disable_cxsr(struct intel_display *display)
sys/dev/pci/drm/i915/display/i9xx_wm.h
28
static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/icl_dsi.c
1106
bool enable)
sys/dev/pci/drm/i915/display/icl_dsi.c
1247
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/icl_dsi.c
1541
static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
sys/dev/pci/drm/i915/display/icl_dsi.c
1620
bool use_dsc;
sys/dev/pci/drm/i915/display/icl_dsi.c
1722
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/icl_dsi.c
1730
bool ret = false;
sys/dev/pci/drm/i915/display/icl_dsi.c
1768
static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/icl_dsi.c
1826
bool enable_lpdt = false;
sys/dev/pci/drm/i915/display/icl_dsi.c
192
bool enable_lpdt)
sys/dev/pci/drm/i915/display/icl_dsi.c
654
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/icl_dsi.c
658
bool clock_enabled = false;
sys/dev/pci/drm/i915/display/icl_dsi.c
74
static bool wait_for_header_credits(struct intel_display *display,
sys/dev/pci/drm/i915/display/icl_dsi.c
90
static bool wait_for_payload_credits(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_alpm.c
167
static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_alpm.c
219
bool intel_alpm_compute_params(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_alpm.c
27
bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_alpm.c
32
bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_alpm.c
37
bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_alpm.c
586
bool intel_alpm_get_error(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_alpm.h
19
bool intel_alpm_compute_params(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_alpm.h
35
bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_alpm.h
36
bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_alpm.h
37
bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_alpm.h
40
bool intel_alpm_get_error(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_atomic.c
178
bool
sys/dev/pci/drm/i915/display/intel_atomic.c
199
bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/intel_atomic.h
35
bool intel_connector_needs_modeset(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_atomic.h
37
bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state);
sys/dev/pci/drm/i915/display/intel_audio.c
1088
bool enable)
sys/dev/pci/drm/i915/display/intel_audio.c
1217
int cpu_transcoder, bool *enabled,
sys/dev/pci/drm/i915/display/intel_audio.c
191
static bool needs_wa_14020863754(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_audio.c
401
bool enable)
sys/dev/pci/drm/i915/display/intel_audio.c
701
bool intel_audio_compute_config(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_audio.c
940
bool enable)
sys/dev/pci/drm/i915/display/intel_audio.c
960
bool enable)
sys/dev/pci/drm/i915/display/intel_audio.h
17
bool intel_audio_compute_config(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_backlight.c
1253
bool alt, cpu_mode;
sys/dev/pci/drm/i915/display/intel_backlight.c
1498
static bool cnp_backlight_controller_is_valid(struct intel_display *display, int controller)
sys/dev/pci/drm/i915/display/intel_backlight.c
904
bool enable = bd->props.power == BACKLIGHT_POWER_ON &&
sys/dev/pci/drm/i915/display/intel_bios.c
1061
bool scale;
sys/dev/pci/drm/i915/display/intel_bios.c
1159
bool alternate)
sys/dev/pci/drm/i915/display/intel_bios.c
224
static bool validate_lfp_data_ptrs(const void *bdb,
sys/dev/pci/drm/i915/display/intel_bios.c
2519
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2536
bool is_hdmi;
sys/dev/pci/drm/i915/display/intel_bios.c
2575
static bool
sys/dev/pci/drm/i915/display/intel_bios.c
2581
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2587
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2594
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2600
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2607
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2613
bool
sys/dev/pci/drm/i915/display/intel_bios.c
2653
static bool is_port_valid(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_bios.c
2670
bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt;
sys/dev/pci/drm/i915/display/intel_bios.c
2757
static bool has_ddi_port_info(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_bios.c
2800
static bool child_device_size_valid(struct intel_display *display, int size)
sys/dev/pci/drm/i915/display/intel_bios.c
3013
bool intel_bios_is_valid_vbt(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_bios.c
318
static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block)
sys/dev/pci/drm/i915/display/intel_bios.c
3241
bool use_fallback)
sys/dev/pci/drm/i915/display/intel_bios.c
3331
bool intel_bios_is_tv_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_bios.c
3373
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
sys/dev/pci/drm/i915/display/intel_bios.c
3420
bool intel_bios_is_port_present(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_bios.c
3440
bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata)
sys/dev/pci/drm/i915/display/intel_bios.c
3469
bool intel_bios_is_dsi_present(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_bios.c
3564
bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_bios.c
3676
bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata)
sys/dev/pci/drm/i915/display/intel_bios.c
3721
bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
sys/dev/pci/drm/i915/display/intel_bios.c
3726
bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
sys/dev/pci/drm/i915/display/intel_bios.c
3731
bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
sys/dev/pci/drm/i915/display/intel_bios.c
3736
bool intel_bios_encoder_hpd_invert(const struct intel_bios_encoder_data *devdata)
sys/dev/pci/drm/i915/display/intel_bios.c
629
const struct drm_edid *drm_edid, bool use_fallback)
sys/dev/pci/drm/i915/display/intel_bios.c
636
const struct drm_edid *drm_edid, bool use_fallback)
sys/dev/pci/drm/i915/display/intel_bios.c
662
const struct drm_edid *drm_edid, bool use_fallback)
sys/dev/pci/drm/i915/display/intel_bios.c
712
const struct drm_edid *drm_edid, bool use_fallback)
sys/dev/pci/drm/i915/display/intel_bios.c
726
const struct drm_edid *drm_edid, bool use_fallback)
sys/dev/pci/drm/i915/display/intel_bios.c
732
const struct drm_edid *drm_edid, bool use_fallback);
sys/dev/pci/drm/i915/display/intel_bios.c
788
static bool panel_bool(unsigned int value, int panel_type)
sys/dev/pci/drm/i915/display/intel_bios.h
63
bool intel_bios_is_valid_vbt(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_bios.h
65
bool intel_bios_is_tv_present(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_bios.h
66
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);
sys/dev/pci/drm/i915/display/intel_bios.h
67
bool intel_bios_is_port_present(struct intel_display *display, enum port port);
sys/dev/pci/drm/i915/display/intel_bios.h
68
bool intel_bios_is_dsi_present(struct intel_display *display, enum port *port);
sys/dev/pci/drm/i915/display/intel_bios.h
69
bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_bios.h
76
bool intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
77
bool intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
78
bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
79
bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
80
bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
81
bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
82
bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
83
bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
84
bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
85
bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
86
bool intel_bios_encoder_hpd_invert(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bios.h
88
bool intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata,
sys/dev/pci/drm/i915/display/intel_bios.h
94
bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata);
sys/dev/pci/drm/i915/display/intel_bo.c
12
bool intel_bo_is_tiled(struct drm_gem_object *obj)
sys/dev/pci/drm/i915/display/intel_bo.c
17
bool intel_bo_is_userptr(struct drm_gem_object *obj)
sys/dev/pci/drm/i915/display/intel_bo.c
22
bool intel_bo_is_shmem(struct drm_gem_object *obj)
sys/dev/pci/drm/i915/display/intel_bo.c
27
bool intel_bo_is_protected(struct drm_gem_object *obj)
sys/dev/pci/drm/i915/display/intel_bo.h
15
bool intel_bo_is_tiled(struct drm_gem_object *obj);
sys/dev/pci/drm/i915/display/intel_bo.h
16
bool intel_bo_is_userptr(struct drm_gem_object *obj);
sys/dev/pci/drm/i915/display/intel_bo.h
17
bool intel_bo_is_shmem(struct drm_gem_object *obj);
sys/dev/pci/drm/i915/display/intel_bo.h
18
bool intel_bo_is_protected(struct drm_gem_object *obj);
sys/dev/pci/drm/i915/display/intel_bw.c
1265
static bool intel_dbuf_bw_changed(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_bw.c
1280
static bool intel_bw_state_changed(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_bw.c
1402
bool *need_cdclk_calc)
sys/dev/pci/drm/i915/display/intel_bw.c
1482
static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
sys/dev/pci/drm/i915/display/intel_bw.c
1602
int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)
sys/dev/pci/drm/i915/display/intel_bw.c
1605
bool changed = false;
sys/dev/pci/drm/i915/display/intel_bw.c
1759
bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/intel_bw.c
1773
bool intel_bw_can_enable_sagv(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_bw.c
185
static bool is_sagv_enabled(struct intel_display *display, u16 points_mask)
sys/dev/pci/drm/i915/display/intel_bw.c
259
bool is_y_tile)
sys/dev/pci/drm/i915/display/intel_bw.c
468
bool is_y_tile = true; /* assume y tile may be used */
sys/dev/pci/drm/i915/display/intel_bw.c
539
bool is_y_tile = true; /* assume y tile may be used */
sys/dev/pci/drm/i915/display/intel_bw.h
31
int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms);
sys/dev/pci/drm/i915/display/intel_bw.h
33
bool *need_cdclk_calc);
sys/dev/pci/drm/i915/display/intel_bw.h
39
bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
sys/dev/pci/drm/i915/display/intel_bw.h
40
bool intel_bw_can_enable_sagv(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
1082
bool changed = display->cdclk.skl_preferred_vco_freq != vco;
sys/dev/pci/drm/i915/display/intel_cdclk.c
152
bool disable_pipes;
sys/dev/pci/drm/i915/display/intel_cdclk.c
1979
static bool cdclk_pll_is_unknown(unsigned int vco)
sys/dev/pci/drm/i915/display/intel_cdclk.c
1989
static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2020
static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2093
static bool pll_enable_wa_needed(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2372
static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2394
static bool intel_cdclk_can_crawl(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2416
static bool intel_cdclk_can_squash(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2444
bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2463
static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2494
static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2515
bool cdclk_update_valid,
sys/dev/pci/drm/i915/display/intel_cdclk.c
2516
bool pipe_count_update_valid)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2611
bool change_cdclk, update_pipe_count;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2656
bool update_cdclk, update_pipe_count;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2685
bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2786
static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
sys/dev/pci/drm/i915/display/intel_cdclk.c
3187
bool *need_cdclk_calc)
sys/dev/pci/drm/i915/display/intel_cdclk.c
3221
int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus)
sys/dev/pci/drm/i915/display/intel_cdclk.c
3249
static bool intel_cdclk_need_serialize(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cdclk.c
3253
bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
sys/dev/pci/drm/i915/display/intel_cdclk.c
3255
bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
sys/dev/pci/drm/i915/display/intel_cdclk.c
3905
bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/intel_cdclk.h
22
bool joined_mbus;
sys/dev/pci/drm/i915/display/intel_cdclk.h
31
bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
sys/dev/pci/drm/i915/display/intel_cdclk.h
35
bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
sys/dev/pci/drm/i915/display/intel_cdclk.h
45
bool *need_cdclk_calc);
sys/dev/pci/drm/i915/display/intel_cdclk.h
46
int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus);
sys/dev/pci/drm/i915/display/intel_cdclk.h
68
bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
sys/dev/pci/drm/i915/display/intel_cmtg.c
119
static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_cmtg.c
54
bool cmtg_a_enable;
sys/dev/pci/drm/i915/display/intel_cmtg.c
58
bool cmtg_b_enable;
sys/dev/pci/drm/i915/display/intel_cmtg.c
59
bool trans_a_secondary;
sys/dev/pci/drm/i915/display/intel_cmtg.c
60
bool trans_b_secondary;
sys/dev/pci/drm/i915/display/intel_cmtg.c
63
static bool intel_cmtg_has_cmtg_b(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_cmtg.c
68
static bool intel_cmtg_has_clock_sel(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_cmtg.c
84
static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_color.c
1211
bool limited_color_range)
sys/dev/pci/drm/i915/display/intel_color.c
183
static bool lut_is_legacy(const struct drm_property_blob *lut)
sys/dev/pci/drm/i915/display/intel_color.c
1968
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1973
bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1980
bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2041
static bool intel_can_preload_luts(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_color.c
2055
static bool vlv_can_preload_luts(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_color.c
2065
static bool chv_can_preload_luts(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_color.c
2118
bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
2121
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2136
static bool need_plane_update(struct intel_plane *plane,
sys/dev/pci/drm/i915/display/intel_color.c
2503
static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2510
static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2642
bool limited_color_range = ilk_csc_limited_range(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2755
static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3000
static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3009
static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3081
static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3089
static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3120
static bool err_check(const struct drm_color_lut *lut1,
sys/dev/pci/drm/i915/display/intel_color.c
3128
static bool intel_lut_entries_equal(const struct drm_color_lut *lut1,
sys/dev/pci/drm/i915/display/intel_color.c
3142
static bool intel_lut_equal(const struct drm_property_blob *blob1,
sys/dev/pci/drm/i915/display/intel_color.c
3179
static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3182
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3198
static bool i965_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3201
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3211
static bool chv_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3214
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3224
static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3227
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3237
static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3240
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3250
static bool glk_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3253
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3263
static bool icl_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3266
bool is_pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
3969
bool has_ctm;
sys/dev/pci/drm/i915/display/intel_color.c
407
static bool ilk_limited_range(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
422
static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
439
static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
459
bool limited_color_range)
sys/dev/pci/drm/i915/display/intel_color.c
520
bool limited_color_range = ilk_csc_limited_range(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
77
bool (*lut_equal)(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
80
bool is_pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_color.h
26
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
27
bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
28
bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
38
bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.h
41
bool is_pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
112
static bool icl_verify_procmon_ref_values(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_combo_phy.c
116
bool ret;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
130
static bool has_phy_misc(struct intel_display *display, enum phy phy)
sys/dev/pci/drm/i915/display/intel_combo_phy.c
151
static bool icl_combo_phy_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_combo_phy.c
163
static bool ehl_vbt_ddi_d_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_combo_phy.c
165
bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
166
bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
167
bool dsi_present = intel_bios_is_dsi_present(display, NULL);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
190
static bool phy_is_master(struct intel_display *display, enum phy phy)
sys/dev/pci/drm/i915/display/intel_combo_phy.c
218
static bool icl_combo_phy_verify_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_combo_phy.c
221
bool ret = true;
sys/dev/pci/drm/i915/display/intel_combo_phy.c
261
enum phy phy, bool is_dsi,
sys/dev/pci/drm/i915/display/intel_combo_phy.c
262
int lane_count, bool lane_reversal)
sys/dev/pci/drm/i915/display/intel_combo_phy.c
94
static bool check_phy_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_combo_phy.h
17
enum phy phy, bool is_dsi,
sys/dev/pci/drm/i915/display/intel_combo_phy.h
18
int lane_count, bool lane_reversal);
sys/dev/pci/drm/i915/display/intel_connector.c
199
bool intel_connector_get_hw_state(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_connector.h
24
bool intel_connector_get_hw_state(struct intel_connector *connector);
sys/dev/pci/drm/i915/display/intel_crt.c
107
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_crt.c
113
bool ret;
sys/dev/pci/drm/i915/display/intel_crt.c
477
static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
sys/dev/pci/drm/i915/display/intel_crt.c
482
bool ret;
sys/dev/pci/drm/i915/display/intel_crt.c
486
bool turn_off_dac = HAS_PCH_SPLIT(display);
sys/dev/pci/drm/i915/display/intel_crt.c
526
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
sys/dev/pci/drm/i915/display/intel_crt.c
531
bool ret;
sys/dev/pci/drm/i915/display/intel_crt.c
578
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
sys/dev/pci/drm/i915/display/intel_crt.c
582
bool ret = false;
sys/dev/pci/drm/i915/display/intel_crt.c
662
static bool intel_crt_detect_ddc(struct drm_connector *connector)
sys/dev/pci/drm/i915/display/intel_crt.c
666
bool ret = false;
sys/dev/pci/drm/i915/display/intel_crt.c
747
bool restore_vblank = false;
sys/dev/pci/drm/i915/display/intel_crt.c
77
bool force_hotplug_required;
sys/dev/pci/drm/i915/display/intel_crt.c
844
bool force)
sys/dev/pci/drm/i915/display/intel_crt.c
91
bool intel_crt_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_crt.h
16
bool intel_crt_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_crt.h
21
static inline bool intel_crt_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_crtc.c
418
static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
215
static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
322
static bool i845_cursor_get_hw_state(struct intel_plane *plane,
sys/dev/pci/drm/i915/display/intel_cursor.c
328
bool ret;
sys/dev/pci/drm/i915/display/intel_cursor.c
43
bool early_tpt)
sys/dev/pci/drm/i915/display/intel_cursor.c
433
static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
725
static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
sys/dev/pci/drm/i915/display/intel_cursor.c
73
static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
731
bool ret;
sys/dev/pci/drm/i915/display/intel_cursor.c
779
static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2030
struct intel_cx0pll_state *pll_state, bool is_dp)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2059
bool is_dp, int port_clock,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2163
bool fracen;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2212
static bool is_arrowlake_s_by_host_bridge(void)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2383
static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2437
bool cntx;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2589
static bool is_dp2(u32 clock)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2598
static bool is_hdmi_frl(u32 clock)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2612
static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2621
static int intel_get_c20_custom_width(u32 clock, bool dp)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2634
bool is_dp, int port_clock)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2637
bool cntx;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2764
bool is_dp, int port_clock,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2765
bool lane_reversal)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
283
int lane, u16 addr, u8 data, bool committed)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2894
bool lane_reversal)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2954
bool lane_reversal)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2958
bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3021
bool is_dp, int port_clock, int lane_count)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3026
bool lane_reversal = dig_port->lane_reversal;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3346
static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
342
int lane, u16 addr, u8 data, bool committed)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3472
static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3487
static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3507
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3540
bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3541
bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
363
u8 lane_mask, u16 addr, u8 data, bool committed)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
37
bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
404
int lane, u16 addr, u8 clear, u8 set, bool committed)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
416
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
82
bool enabled;
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
22
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
40
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
sys/dev/pci/drm/i915/display/intel_ddi.c
116
static bool has_buf_trans_select(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_ddi.c
121
static bool has_iboost(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_ddi.c
1578
static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1620
static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
1664
static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
1717
static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
1774
static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
1822
static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
1874
static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
1978
static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
2033
bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
2096
bool ddi_clk_needed;
sys/dev/pci/drm/i915/display/intel_ddi.c
2107
bool is_mst;
sys/dev/pci/drm/i915/display/intel_ddi.c
2311
bool enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2327
bool enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2345
static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
sys/dev/pci/drm/i915/display/intel_ddi.c
2370
bool enabled)
sys/dev/pci/drm/i915/display/intel_ddi.c
2624
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
2625
bool transparent_mode;
sys/dev/pci/drm/i915/display/intel_ddi.c
2744
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
2892
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
3130
bool is_mst = intel_crtc_has_type(old_crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3229
bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_ddi.c
3515
bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_ddi.c
3690
bool is_tc_port = intel_encoder_is_tc(encoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
3872
static bool intel_ddi_is_audio_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_ddi.c
4228
bool pll_active;
sys/dev/pci/drm/i915/display/intel_ddi.c
4293
static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
sys/dev/pci/drm/i915/display/intel_ddi.c
4331
bool pll_active;
sys/dev/pci/drm/i915/display/intel_ddi.c
4396
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_ddi.c
4400
bool fastset = true;
sys/dev/pci/drm/i915/display/intel_ddi.c
4473
static bool mode_equal(const struct drm_display_mode *mode1,
sys/dev/pci/drm/i915/display/intel_ddi.c
4483
static bool m_n_equal(const struct intel_link_m_n *m_n_1,
sys/dev/pci/drm/i915/display/intel_ddi.c
4493
static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
sys/dev/pci/drm/i915/display/intel_ddi.c
4763
bool is_tc = intel_encoder_is_tc(encoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
4813
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
4821
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
4829
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
4861
static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_ddi.c
487
bool enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
4977
static bool intel_ddi_is_tc(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_ddi.c
5024
static bool port_strap_detected(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_ddi.c
5047
static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
sys/dev/pci/drm/i915/display/intel_ddi.c
5052
static bool assert_has_icl_dsi(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_ddi.c
5059
static bool port_in_use(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_ddi.c
5111
bool init_hdmi, init_dp;
sys/dev/pci/drm/i915/display/intel_ddi.c
5347
bool is_legacy =
sys/dev/pci/drm/i915/display/intel_ddi.c
725
bool enable, u32 hdcp_mask)
sys/dev/pci/drm/i915/display/intel_ddi.c
742
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
sys/dev/pci/drm/i915/display/intel_ddi.c
752
bool ret;
sys/dev/pci/drm/i915/display/intel_ddi.c
801
u8 *pipe_mask, bool *is_dp_mst)
sys/dev/pci/drm/i915/display/intel_ddi.c
934
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_ddi.c
938
bool is_mst;
sys/dev/pci/drm/i915/display/intel_ddi.h
47
bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_ddi.h
59
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
sys/dev/pci/drm/i915/display/intel_ddi.h
70
bool enabled);
sys/dev/pci/drm/i915/display/intel_ddi.h
73
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
sys/dev/pci/drm/i915/display/intel_ddi.h
75
bool state);
sys/dev/pci/drm/i915/display/intel_ddi.h
79
bool enable, u32 hdcp_mask);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1118
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1123
static bool use_edp_hobl(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1131
static bool use_edp_low_vswing(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h
68
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table);
sys/dev/pci/drm/i915/display/intel_display.c
1004
bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_display.c
1021
static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
1032
static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
1156
bool need_vbl_wait = false;
sys/dev/pci/drm/i915/display/intel_display.c
1593
static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
1600
static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
sys/dev/pci/drm/i915/display/intel_display.c
1819
bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
sys/dev/pci/drm/i915/display/intel_display.c
1841
bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
sys/dev/pci/drm/i915/display/intel_display.c
1861
bool intel_phy_is_snps(struct intel_display *display, enum phy phy)
sys/dev/pci/drm/i915/display/intel_display.c
1907
bool intel_encoder_is_combo(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display.c
1914
bool intel_encoder_is_snps(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display.c
1921
bool intel_encoder_is_tc(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display.c
203
static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
211
skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_display.c
2179
static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/intel_display.c
221
bool enable)
sys/dev/pci/drm/i915/display/intel_display.c
231
bool enable)
sys/dev/pci/drm/i915/display/intel_display.c
238
static bool
sys/dev/pci/drm/i915/display/intel_display.c
244
bool
sys/dev/pci/drm/i915/display/intel_display.c
250
bool
sys/dev/pci/drm/i915/display/intel_display.c
2550
bool bios_lvds_use_ssc = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_display.c
2586
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display.c
2630
static bool
sys/dev/pci/drm/i915/display/intel_display.c
266
static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2821
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
287
bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
297
bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3018
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_display.c
3025
bool ret = false;
sys/dev/pci/drm/i915/display/intel_display.c
322
bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
335
bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3360
static bool ilk_get_pipe_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_display.c
3367
bool ret = false;
sys/dev/pci/drm/i915/display/intel_display.c
3452
static bool transcoder_ddi_func_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display.c
356
bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
372
bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3796
static bool has_edp_transcoders(u8 enabled_transcoders)
sys/dev/pci/drm/i915/display/intel_display.c
380
bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3801
static bool has_dsi_transcoders(u8 enabled_transcoders)
sys/dev/pci/drm/i915/display/intel_display.c
3807
static bool has_pipe_transcoders(u8 enabled_transcoders)
sys/dev/pci/drm/i915/display/intel_display.c
3829
static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_display.c
3868
static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_display.c
3928
static bool hsw_get_pipe_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_display.c
3932
bool active;
sys/dev/pci/drm/i915/display/intel_display.c
4019
bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
4120
static bool encoders_cloneable(const struct intel_encoder *a,
sys/dev/pci/drm/i915/display/intel_display.c
4128
static bool check_single_encoder_cloning(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_display.c
429
enum transcoder cpu_transcoder, bool state)
sys/dev/pci/drm/i915/display/intel_display.c
431
bool cur_state;
sys/dev/pci/drm/i915/display/intel_display.c
4379
static bool check_digital_port_conflicts(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/intel_display.c
4386
bool ret = true;
sys/dev/pci/drm/i915/display/intel_display.c
457
static void assert_plane(struct intel_plane *plane, bool state)
sys/dev/pci/drm/i915/display/intel_display.c
461
bool cur_state;
sys/dev/pci/drm/i915/display/intel_display.c
4788
bool intel_fuzzy_clock_check(int clock1, int clock2)
sys/dev/pci/drm/i915/display/intel_display.c
4806
static bool
sys/dev/pci/drm/i915/display/intel_display.c
4817
static bool
sys/dev/pci/drm/i915/display/intel_display.c
4824
static bool
sys/dev/pci/drm/i915/display/intel_display.c
4835
static bool
sys/dev/pci/drm/i915/display/intel_display.c
4846
static bool
sys/dev/pci/drm/i915/display/intel_display.c
4853
pipe_config_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4875
pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4902
pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4917
pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4946
pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4961
pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4978
pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
sys/dev/pci/drm/i915/display/intel_display.c
4995
static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
5008
bool
sys/dev/pci/drm/i915/display/intel_display.c
5011
bool fastset)
sys/dev/pci/drm/i915/display/intel_display.c
5017
bool ret = true;
sys/dev/pci/drm/i915/display/intel_display.c
5026
BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
sys/dev/pci/drm/i915/display/intel_display.c
5038
BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
sys/dev/pci/drm/i915/display/intel_display.c
5050
BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
sys/dev/pci/drm/i915/display/intel_display.c
5072
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
sys/dev/pci/drm/i915/display/intel_display.c
5725
static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode,
sys/dev/pci/drm/i915/display/intel_display.c
5788
static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_display.c
5805
static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_display.c
635
bool visible)
sys/dev/pci/drm/i915/display/intel_display.c
6357
bool any_ms = false;
sys/dev/pci/drm/i915/display/intel_display.c
6639
bool modeset = intel_crtc_needs_modeset(new_crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
6669
bool modeset = intel_crtc_needs_modeset(new_crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
6727
bool modeset = intel_crtc_needs_modeset(new_crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
7424
bool modeset = intel_crtc_needs_modeset(new_crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
7587
static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
sys/dev/pci/drm/i915/display/intel_display.c
7620
bool nonblock)
sys/dev/pci/drm/i915/display/intel_display.c
767
bool intel_has_pending_fb_unpin(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display.c
770
bool cleanup_done;
sys/dev/pci/drm/i915/display/intel_display.c
7716
static bool ilk_has_edp_a(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display.c
7730
static bool intel_ddi_crt_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display.c
7752
bool assert_port_valid(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_display.c
7761
bool dpd_is_edp = false;
sys/dev/pci/drm/i915/display/intel_display.c
7813
bool has_edp, has_port;
sys/dev/pci/drm/i915/display/intel_display.c
7864
bool found = false;
sys/dev/pci/drm/i915/display/intel_display.c
834
static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
8340
bool intel_scanout_needs_vtd_wa(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display.c
848
static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
859
static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
873
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_display.c
891
static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
950
static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
959
static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
968
static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
980
static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
987
static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_display.h
413
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
sys/dev/pci/drm/i915/display/intel_display.h
414
bool is_trans_port_sync_master(const struct intel_crtc_state *state);
sys/dev/pci/drm/i915/display/intel_display.h
416
bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
417
bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
418
bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
419
bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
420
bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
421
bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
422
bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
427
bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
428
bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
sys/dev/pci/drm/i915/display/intel_display.h
430
bool fastset);
sys/dev/pci/drm/i915/display/intel_display.h
443
bool intel_has_pending_fb_unpin(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display.h
449
bool intel_phy_is_combo(struct intel_display *display, enum phy phy);
sys/dev/pci/drm/i915/display/intel_display.h
450
bool intel_phy_is_tc(struct intel_display *display, enum phy phy);
sys/dev/pci/drm/i915/display/intel_display.h
451
bool intel_phy_is_snps(struct intel_display *display, enum phy phy);
sys/dev/pci/drm/i915/display/intel_display.h
455
bool intel_encoder_is_combo(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_display.h
456
bool intel_encoder_is_snps(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_display.h
457
bool intel_encoder_is_tc(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_display.h
462
bool intel_fuzzy_clock_check(int clock1, int clock2);
sys/dev/pci/drm/i915/display/intel_display.h
473
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display.h
504
bool visible);
sys/dev/pci/drm/i915/display/intel_display.h
507
bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_display.h
535
bool nonblock);
sys/dev/pci/drm/i915/display/intel_display.h
539
enum transcoder cpu_transcoder, bool state);
sys/dev/pci/drm/i915/display/intel_display.h
543
bool assert_port_valid(struct intel_display *display, enum port port);
sys/dev/pci/drm/i915/display/intel_display.h
560
bool intel_scanout_needs_vtd_wa(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display.h
73
static inline bool transcoder_is_dsi(enum transcoder transcoder)
sys/dev/pci/drm/i915/display/intel_display_core.h
104
bool component_registered;
sys/dev/pci/drm/i915/display/intel_display_core.h
178
bool poll_enabled;
sys/dev/pci/drm/i915/display/intel_display_core.h
184
bool detection_work_enabled;
sys/dev/pci/drm/i915/display/intel_display_core.h
211
bool ignore_long_hpd;
sys/dev/pci/drm/i915/display/intel_display_core.h
228
bool override_afc_startup;
sys/dev/pci/drm/i915/display/intel_display_core.h
281
bool ipc_enabled;
sys/dev/pci/drm/i915/display/intel_display_core.h
322
bool any_task_allowed;
sys/dev/pci/drm/i915/display/intel_display_core.h
424
bool comp_added;
sys/dev/pci/drm/i915/display/intel_display_core.h
455
bool false_color;
sys/dev/pci/drm/i915/display/intel_display_core.h
469
bool vlv_display_irqs_enabled;
sys/dev/pci/drm/i915/display/intel_display_core.h
485
bool disable[I915_MAX_PIPES];
sys/dev/pci/drm/i915/display/intel_display_core.h
504
bool chv_phy_assert[2];
sys/dev/pci/drm/i915/display/intel_display_core.h
66
bool (*get_pipe_config)(struct intel_crtc *,
sys/dev/pci/drm/i915/display/intel_display_core.h
70
bool (*fixup_initial_plane_config)(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1174
bool dsc_fractional_bpp_enable = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
231
bool has_audio = connector->base.display_info.has_audio;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
239
bool has_audio = connector->base.display_info.has_audio;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
684
static bool
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
688
bool is_enabled;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
700
bool lpsp_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
757
bool reset;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
850
bool lpsp_capable = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
893
bool try_again = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
91
bool sr_enabled = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
963
bool dsc_enable = false;
sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c
145
bool * : debugfs_create_bool, \
sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c
41
bool b;
sys/dev/pci/drm/i915/display/intel_display_debugfs_params.c
94
bool b;
sys/dev/pci/drm/i915/display/intel_display_device.c
1432
static bool has_no_display(struct pci_dev *pdev)
sys/dev/pci/drm/i915/display/intel_display_device.c
1982
bool intel_display_device_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_device.c
1996
bool intel_display_device_enabled(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_device.h
273
bool has_hdcp;
sys/dev/pci/drm/i915/display/intel_display_device.h
274
bool has_dmc;
sys/dev/pci/drm/i915/display/intel_display_device.h
275
bool has_dsc;
sys/dev/pci/drm/i915/display/intel_display_device.h
276
bool edp_typec_support;
sys/dev/pci/drm/i915/display/intel_display_device.h
277
bool has_dbuf_overlap_detection;
sys/dev/pci/drm/i915/display/intel_display_device.h
311
bool intel_display_device_present(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display_device.h
312
bool intel_display_device_enabled(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display_driver.c
326
bool any_task_allowed,
sys/dev/pci/drm/i915/display/intel_display_driver.c
440
bool intel_display_driver_check_access(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_driver.c
66
bool intel_display_driver_probe_defer(struct pci_dev *pdev)
sys/dev/pci/drm/i915/display/intel_display_driver.h
16
bool intel_display_driver_probe_defer(struct pci_dev *pdev);
sys/dev/pci/drm/i915/display/intel_display_driver.h
39
bool intel_display_driver_check_access(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1078
static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id)
sys/dev/pci/drm/i915/display/intel_display_irq.c
1089
static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id)
sys/dev/pci/drm/i915/display/intel_display_irq.c
1100
static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id)
sys/dev/pci/drm/i915/display/intel_display_irq.c
1188
bool found = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1373
bool found = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
1568
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/intel_display_irq.c
1682
static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
sys/dev/pci/drm/i915/display/intel_display_irq.c
1683
bool enable)
sys/dev/pci/drm/i915/display/intel_display_irq.c
370
static bool i915_has_legacy_blc_interrupt(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_irq.c
583
bool blc_event = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
607
bool blc_event = false;
sys/dev/pci/drm/i915/display/intel_display_irq.c
75
bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id);
sys/dev/pci/drm/i915/display/intel_display_irq.c
80
static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id)
sys/dev/pci/drm/i915/display/intel_display_irq.h
87
void i915gm_irq_cstate_wa(struct intel_display *display, bool enable);
sys/dev/pci/drm/i915/display/intel_display_params.c
102
intel_display_param_named(disable_display, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
105
intel_display_param_named(verbose_state_checks, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
108
intel_display_param_named_unsafe(nuclear_pageflip, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
111
intel_display_param_named_unsafe(enable_dp_mst, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
126
intel_display_param_named(psr_safest_params, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
132
intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
144
const char *name, bool val)
sys/dev/pci/drm/i915/display/intel_display_params.c
179
bool : _param_print_bool, \
sys/dev/pci/drm/i915/display/intel_display_params.c
59
intel_display_param_named_unsafe(enable_dpt, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
62
intel_display_param_named_unsafe(enable_dsb, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
65
intel_display_param_named_unsafe(enable_flipq, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
68
intel_display_param_named_unsafe(enable_sagv, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
75
intel_display_param_named_unsafe(enable_ips, bool, 0400, "Enable IPS (default: true)");
sys/dev/pci/drm/i915/display/intel_display_params.c
94
intel_display_param_named_unsafe(load_detect_test, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.c
98
intel_display_param_named_unsafe(force_reset_modeset_test, bool, 0400,
sys/dev/pci/drm/i915/display/intel_display_params.h
32
param(bool, enable_dpt, true, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
33
param(bool, enable_dsb, true, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
34
param(bool, enable_flipq, false, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
35
param(bool, enable_sagv, true, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
37
param(bool, enable_ips, true, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
41
param(bool, load_detect_test, false, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
42
param(bool, force_reset_modeset_test, false, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
43
param(bool, disable_display, false, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
44
param(bool, verbose_state_checks, true, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
45
param(bool, nuclear_pageflip, false, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
46
param(bool, enable_dp_mst, true, 0600) \
sys/dev/pci/drm/i915/display/intel_display_params.h
50
param(bool, psr_safest_params, false, 0400) \
sys/dev/pci/drm/i915/display/intel_display_params.h
51
param(bool, enable_psr2_sel_fetch, true, 0400) \
sys/dev/pci/drm/i915/display/intel_display_power.c
1071
enum dbuf_slice slice, bool enable)
sys/dev/pci/drm/i915/display/intel_display_power.c
1074
bool state;
sys/dev/pci/drm/i915/display/intel_display_power.c
1282
bool switch_to_fclk, bool allow_power_down)
sys/dev/pci/drm/i915/display/intel_display_power.c
1436
bool enable)
sys/dev/pci/drm/i915/display/intel_display_power.c
1456
bool resume)
sys/dev/pci/drm/i915/display/intel_display_power.c
1522
static void bxt_display_core_init(struct intel_display *display, bool resume)
sys/dev/pci/drm/i915/display/intel_display_power.c
1662
bool resume)
sys/dev/pci/drm/i915/display/intel_display_power.c
1895
static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)
sys/dev/pci/drm/i915/display/intel_display_power.c
1897
bool ret;
sys/dev/pci/drm/i915/display/intel_display_power.c
1946
void intel_power_domains_init_hw(struct intel_display *display, bool resume)
sys/dev/pci/drm/i915/display/intel_display_power.c
207
static bool __intel_display_power_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power.c
2107
void intel_power_domains_suspend(struct intel_display *display, bool s2idle)
sys/dev/pci/drm/i915/display/intel_display_power.c
211
bool is_enabled;
sys/dev/pci/drm/i915/display/intel_display_power.c
2208
bool dump_domain_info;
sys/dev/pci/drm/i915/display/intel_display_power.c
2218
bool enabled;
sys/dev/pci/drm/i915/display/intel_display_power.c
2245
static bool dumped;
sys/dev/pci/drm/i915/display/intel_display_power.c
2264
void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)
sys/dev/pci/drm/i915/display/intel_display_power.c
248
bool intel_display_power_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power.c
252
bool ret;
sys/dev/pci/drm/i915/display/intel_display_power.c
300
bool dc_off_enabled;
sys/dev/pci/drm/i915/display/intel_display_power.c
371
static bool
sys/dev/pci/drm/i915/display/intel_display_power.c
384
static bool
sys/dev/pci/drm/i915/display/intel_display_power.c
392
bool err = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
479
cancel_async_put_work(struct i915_power_domains *power_domains, bool sync)
sys/dev/pci/drm/i915/display/intel_display_power.c
489
static bool
sys/dev/pci/drm/i915/display/intel_display_power.c
495
bool ret = false;
sys/dev/pci/drm/i915/display/intel_display_power.c
579
bool is_enabled;
sys/dev/pci/drm/i915/display/intel_display_power.c
898
bool
sys/dev/pci/drm/i915/display/intel_display_power.h
137
bool initializing;
sys/dev/pci/drm/i915/display/intel_display_power.h
138
bool display_core_suspended;
sys/dev/pci/drm/i915/display/intel_display_power.h
172
void intel_power_domains_init_hw(struct intel_display *display, bool resume);
sys/dev/pci/drm/i915/display/intel_display_power.h
176
void intel_power_domains_suspend(struct intel_display *display, bool s2idle);
sys/dev/pci/drm/i915/display/intel_display_power.h
180
void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
sys/dev/pci/drm/i915/display/intel_display_power.h
188
bool intel_display_power_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power.h
255
bool
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1084
static bool i9xx_always_on_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1106
static bool i830_pipes_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1123
struct i915_power_well *power_well, bool enable)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1172
static bool vlv_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1176
bool enabled = false;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1558
enum dpio_channel ch, bool override, unsigned int mask)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
156
bool intel_power_well_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
162
bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1621
bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1622
enum dpio_channel ch, bool override)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1625
bool was_override;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1655
bool override, unsigned int mask)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
167
bool intel_display_power_well_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1686
static bool chv_pipe_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1690
bool enabled;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1718
bool enable)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
177
bool intel_power_well_is_always_on(struct i915_power_well *power_well)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1776
tgl_tc_cold_request(struct intel_display *display, bool block)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1840
static bool
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1885
static bool xelpdp_aux_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1921
static bool xe2lpd_pica_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
204
u8 irq_pipe_mask, bool has_vga)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
277
bool timeout_expected)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
420
static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch)
sys/dev/pci/drm/i915/display/intel_display_power_well.c
529
bool is_tbt = power_well->desc->is_tc_tbt;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
530
bool timeout_expected;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
602
static bool hsw_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
774
bool dc6_was_enabled, enable_dc6;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
82
bool (*is_enabled)(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
957
static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.c
984
static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.h
124
bool hw_enabled;
sys/dev/pci/drm/i915/display/intel_display_power_well.h
142
bool intel_power_well_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.h
144
bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
sys/dev/pci/drm/i915/display/intel_display_power_well.h
145
bool intel_display_power_well_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_power_well.h
147
bool intel_power_well_is_always_on(struct i915_power_well *power_well);
sys/dev/pci/drm/i915/display/intel_display_power_well.h
153
bool override, unsigned int mask);
sys/dev/pci/drm/i915/display/intel_display_power_well.h
154
bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy,
sys/dev/pci/drm/i915/display/intel_display_power_well.h
155
enum dpio_channel ch, bool override);
sys/dev/pci/drm/i915/display/intel_display_reset.c
18
bool intel_display_reset_test(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_reset.c
24
bool intel_display_reset_prepare(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_reset.c
79
void intel_display_reset_finish(struct intel_display *display, bool test_only)
sys/dev/pci/drm/i915/display/intel_display_reset.h
15
bool intel_display_reset_test(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display_reset.h
16
bool intel_display_reset_prepare(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_display_reset.h
18
void intel_display_reset_finish(struct intel_display *display, bool test_only);
sys/dev/pci/drm/i915/display/intel_display_rpm.c
51
bool intel_display_rpm_suspended(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_rpm.h
23
bool intel_display_rpm_suspended(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display_rps.c
78
bool interactive)
sys/dev/pci/drm/i915/display/intel_display_rps.h
21
bool interactive);
sys/dev/pci/drm/i915/display/intel_display_rps.h
32
bool interactive)
sys/dev/pci/drm/i915/display/intel_display_types.h
1004
bool update_pipe; /* can a fast modeset be performed? */
sys/dev/pci/drm/i915/display/intel_display_types.h
1005
bool update_m_n; /* update M/N seamlessly during fastset? */
sys/dev/pci/drm/i915/display/intel_display_types.h
1006
bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */
sys/dev/pci/drm/i915/display/intel_display_types.h
1007
bool disable_cxsr;
sys/dev/pci/drm/i915/display/intel_display_types.h
1008
bool update_wm_pre, update_wm_post; /* watermarks are updated */
sys/dev/pci/drm/i915/display/intel_display_types.h
1009
bool fifo_changed; /* FIFO split is changed */
sys/dev/pci/drm/i915/display/intel_display_types.h
1010
bool preload_luts;
sys/dev/pci/drm/i915/display/intel_display_types.h
1011
bool inherited; /* state inherited from BIOS? */
sys/dev/pci/drm/i915/display/intel_display_types.h
1014
bool do_async_flip;
sys/dev/pci/drm/i915/display/intel_display_types.h
1029
bool has_pch_encoder;
sys/dev/pci/drm/i915/display/intel_display_types.h
1032
bool has_infoframe;
sys/dev/pci/drm/i915/display/intel_display_types.h
1043
bool limited_color_range;
sys/dev/pci/drm/i915/display/intel_display_types.h
1051
bool has_hdmi_sink;
sys/dev/pci/drm/i915/display/intel_display_types.h
1055
bool has_audio;
sys/dev/pci/drm/i915/display/intel_display_types.h
1061
bool dither;
sys/dev/pci/drm/i915/display/intel_display_types.h
1069
bool dither_force_disable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1072
bool clock_set;
sys/dev/pci/drm/i915/display/intel_display_types.h
1076
bool sdvo_tv_clock;
sys/dev/pci/drm/i915/display/intel_display_types.h
1083
bool bw_constrained;
sys/dev/pci/drm/i915/display/intel_display_types.h
1116
bool has_drrs;
sys/dev/pci/drm/i915/display/intel_display_types.h
1119
bool has_psr;
sys/dev/pci/drm/i915/display/intel_display_types.h
1120
bool has_sel_update;
sys/dev/pci/drm/i915/display/intel_display_types.h
1121
bool enable_psr2_sel_fetch;
sys/dev/pci/drm/i915/display/intel_display_types.h
1122
bool enable_psr2_su_region_et;
sys/dev/pci/drm/i915/display/intel_display_types.h
1123
bool req_psr2_sdp_prior_scanline;
sys/dev/pci/drm/i915/display/intel_display_types.h
1124
bool has_panel_replay;
sys/dev/pci/drm/i915/display/intel_display_types.h
1125
bool wm_level_disabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1126
bool pkg_c_latency_used;
sys/dev/pci/drm/i915/display/intel_display_types.h
1166
bool enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1167
bool force_thru;
sys/dev/pci/drm/i915/display/intel_display_types.h
1174
bool ips_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1176
bool crc_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1178
bool double_wide;
sys/dev/pci/drm/i915/display/intel_display_types.h
1241
bool hdmi_scrambling;
sys/dev/pci/drm/i915/display/intel_display_types.h
1244
bool hdmi_high_tmds_clock_ratio;
sys/dev/pci/drm/i915/display/intel_display_types.h
1259
bool gamma_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1262
bool csc_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1265
bool wgc_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1272
bool compression_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1287
bool enhanced_framing;
sys/dev/pci/drm/i915/display/intel_display_types.h
1295
bool fec_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1297
bool sdp_split_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1310
bool use_dsb;
sys/dev/pci/drm/i915/display/intel_display_types.h
1311
bool use_flipq;
sys/dev/pci/drm/i915/display/intel_display_types.h
1321
bool enable, in_range;
sys/dev/pci/drm/i915/display/intel_display_types.h
1329
bool enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1335
bool enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1344
bool has_lobf;
sys/dev/pci/drm/i915/display/intel_display_types.h
1401
bool active;
sys/dev/pci/drm/i915/display/intel_display_types.h
1423
bool cpu_fifo_underrun_disabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1424
bool pch_fifo_underrun_disabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1476
bool vblank_psr_notify;
sys/dev/pci/drm/i915/display/intel_display_types.h
1488
bool need_async_flip_toggle_wa;
sys/dev/pci/drm/i915/display/intel_display_types.h
1519
bool (*can_async_flip)(u64 modifier);
sys/dev/pci/drm/i915/display/intel_display_types.h
1537
bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
sys/dev/pci/drm/i915/display/intel_display_types.h
1547
bool async_flip);
sys/dev/pci/drm/i915/display/intel_display_types.h
1590
bool test_active;
sys/dev/pci/drm/i915/display/intel_display_types.h
1596
bool is_trained;
sys/dev/pci/drm/i915/display/intel_display_types.h
1607
bool want_panel_vdd;
sys/dev/pci/drm/i915/display/intel_display_types.h
1608
bool initializing;
sys/dev/pci/drm/i915/display/intel_display_types.h
1637
bool bxt_pps_reset;
sys/dev/pci/drm/i915/display/intel_display_types.h
1657
bool sink_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1658
bool source_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1659
bool enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1663
bool active;
sys/dev/pci/drm/i915/display/intel_display_types.h
1666
bool sink_psr2_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1667
bool link_standby;
sys/dev/pci/drm/i915/display/intel_display_types.h
1668
bool sel_update_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1669
bool psr2_sel_fetch_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1670
bool psr2_sel_fetch_cff_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1671
bool su_region_et_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1672
bool req_psr2_sdp_prior_scanline;
sys/dev/pci/drm/i915/display/intel_display_types.h
1676
bool sink_not_reliable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1677
bool irq_aux_error;
sys/dev/pci/drm/i915/display/intel_display_types.h
1680
bool source_panel_replay_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1681
bool sink_panel_replay_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1682
bool sink_panel_replay_su_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1683
bool panel_replay_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1689
bool link_ok;
sys/dev/pci/drm/i915/display/intel_display_types.h
1690
bool pkg_c_latency_used;
sys/dev/pci/drm/i915/display/intel_display_types.h
1701
bool needs_modeset_retry;
sys/dev/pci/drm/i915/display/intel_display_types.h
1702
bool use_max_params;
sys/dev/pci/drm/i915/display/intel_display_types.h
1719
bool use_rate_select;
sys/dev/pci/drm/i915/display/intel_display_types.h
1727
bool active;
sys/dev/pci/drm/i915/display/intel_display_types.h
1759
bool retrain_disabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
1763
bool force_retrain;
sys/dev/pci/drm/i915/display/intel_display_types.h
1765
bool reset_link_params;
sys/dev/pci/drm/i915/display/intel_display_types.h
1776
bool is_mst;
sys/dev/pci/drm/i915/display/intel_display_types.h
1781
bool as_sdp_supported;
sys/dev/pci/drm/i915/display/intel_display_types.h
1784
bool tunnel_suspended:1;
sys/dev/pci/drm/i915/display/intel_display_types.h
1825
bool ycbcr_444_to_420;
sys/dev/pci/drm/i915/display/intel_display_types.h
1826
bool ycbcr420_passthrough;
sys/dev/pci/drm/i915/display/intel_display_types.h
1827
bool rgb_to_ycbcr;
sys/dev/pci/drm/i915/display/intel_display_types.h
1834
bool force_dsc_en;
sys/dev/pci/drm/i915/display/intel_display_types.h
1836
bool force_dsc_fractional_bpp_en;
sys/dev/pci/drm/i915/display/intel_display_types.h
1839
bool hobl_failed;
sys/dev/pci/drm/i915/display/intel_display_types.h
1840
bool hobl_active;
sys/dev/pci/drm/i915/display/intel_display_types.h
1848
bool oui_valid;
sys/dev/pci/drm/i915/display/intel_display_types.h
1850
bool colorimetry_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
1863
bool lobf_disable_debug;
sys/dev/pci/drm/i915/display/intel_display_types.h
1864
bool sink_alpm_error;
sys/dev/pci/drm/i915/display/intel_display_types.h
1880
bool active;
sys/dev/pci/drm/i915/display/intel_display_types.h
1881
bool hdr_supported;
sys/dev/pci/drm/i915/display/intel_display_types.h
1891
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
sys/dev/pci/drm/i915/display/intel_display_types.h
1893
bool lane_reversal;
sys/dev/pci/drm/i915/display/intel_display_types.h
1894
bool ddi_a_4_lanes;
sys/dev/pci/drm/i915/display/intel_display_types.h
1895
bool release_cl2_override;
sys/dev/pci/drm/i915/display/intel_display_types.h
1911
bool auth_status;
sys/dev/pci/drm/i915/display/intel_display_types.h
1915
bool mst_type1_capable;
sys/dev/pci/drm/i915/display/intel_display_types.h
1927
bool enable,
sys/dev/pci/drm/i915/display/intel_display_types.h
1932
bool (*connected)(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_display_types.h
1951
static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display_types.h
1964
static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display_types.h
2021
static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display_types.h
2035
static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_display_types.h
2124
static inline bool
sys/dev/pci/drm/i915/display/intel_display_types.h
2131
static inline bool
sys/dev/pci/drm/i915/display/intel_display_types.h
2140
static inline bool
sys/dev/pci/drm/i915/display/intel_display_types.h
2146
static inline bool
sys/dev/pci/drm/i915/display/intel_display_types.h
2152
static inline bool
sys/dev/pci/drm/i915/display/intel_display_types.h
222
bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
sys/dev/pci/drm/i915/display/intel_display_types.h
241
bool (*initial_fastset_check)(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_display_types.h
282
bool (*is_clock_enabled)(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_display_types.h
336
bool vrr;
sys/dev/pci/drm/i915/display/intel_display_types.h
350
bool low_vswing;
sys/dev/pci/drm/i915/display/intel_display_types.h
351
bool hobl;
sys/dev/pci/drm/i915/display/intel_display_types.h
352
bool dsc_disable;
sys/dev/pci/drm/i915/display/intel_display_types.h
356
bool enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
357
bool full_link;
sys/dev/pci/drm/i915/display/intel_display_types.h
358
bool require_aux_wakeup;
sys/dev/pci/drm/i915/display/intel_display_types.h
369
bool present;
sys/dev/pci/drm/i915/display/intel_display_types.h
370
bool active_low_pwm;
sys/dev/pci/drm/i915/display/intel_display_types.h
403
bool present;
sys/dev/pci/drm/i915/display/intel_display_types.h
407
bool enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
408
bool combination_mode; /* gen 2/4 only */
sys/dev/pci/drm/i915/display/intel_display_types.h
409
bool active_low_pwm;
sys/dev/pci/drm/i915/display/intel_display_types.h
410
bool alternate_pwm_increment; /* lpt+ */
sys/dev/pci/drm/i915/display/intel_display_types.h
415
bool pwm_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
416
bool util_pin_active_low; /* bxt+ */
sys/dev/pci/drm/i915/display/intel_display_types.h
425
bool luminance_control_support;
sys/dev/pci/drm/i915/display/intel_display_types.h
428
bool sdr_uses_aux;
sys/dev/pci/drm/i915/display/intel_display_types.h
429
bool supports_2084_decode;
sys/dev/pci/drm/i915/display/intel_display_types.h
430
bool supports_2020_gamut;
sys/dev/pci/drm/i915/display/intel_display_types.h
431
bool supports_segmented_backlight;
sys/dev/pci/drm/i915/display/intel_display_types.h
432
bool supports_sdp_colorimetry;
sys/dev/pci/drm/i915/display/intel_display_types.h
433
bool supports_tone_mapping;
sys/dev/pci/drm/i915/display/intel_display_types.h
441
void (*power)(struct intel_connector *, bool enable);
sys/dev/pci/drm/i915/display/intel_display_types.h
458
bool hdcp_encrypted;
sys/dev/pci/drm/i915/display/intel_display_types.h
462
bool hdcp2_supported;
sys/dev/pci/drm/i915/display/intel_display_types.h
465
bool hdcp2_encrypted;
sys/dev/pci/drm/i915/display/intel_display_types.h
474
bool is_paired;
sys/dev/pci/drm/i915/display/intel_display_types.h
475
bool is_repeater;
sys/dev/pci/drm/i915/display/intel_display_types.h
509
bool force_hdcp14;
sys/dev/pci/drm/i915/display/intel_display_types.h
524
bool (*get_hw_state)(struct intel_connector *);
sys/dev/pci/drm/i915/display/intel_display_types.h
603
bool internal;
sys/dev/pci/drm/i915/display/intel_display_types.h
605
bool dpll_set, modeset;
sys/dev/pci/drm/i915/display/intel_display_types.h
615
bool skip_intermediate_wm;
sys/dev/pci/drm/i915/display/intel_display_types.h
617
bool rps_interactive;
sys/dev/pci/drm/i915/display/intel_display_types.h
653
bool decrypt;
sys/dev/pci/drm/i915/display/intel_display_types.h
656
bool force_black;
sys/dev/pci/drm/i915/display/intel_display_types.h
659
bool is_y_plane;
sys/dev/pci/drm/i915/display/intel_display_types.h
728
bool in_use;
sys/dev/pci/drm/i915/display/intel_display_types.h
780
bool enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
789
bool fbc_wm_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
790
bool pipe_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
791
bool sprites_enabled;
sys/dev/pci/drm/i915/display/intel_display_types.h
792
bool sprites_scaled;
sys/dev/pci/drm/i915/display/intel_display_types.h
799
bool enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
800
bool ignore_lines;
sys/dev/pci/drm/i915/display/intel_display_types.h
801
bool auto_min_alloc_wm_enable;
sys/dev/pci/drm/i915/display/intel_display_types.h
802
bool can_sagv;
sys/dev/pci/drm/i915/display/intel_display_types.h
813
bool is_planar;
sys/dev/pci/drm/i915/display/intel_display_types.h
818
bool use_sagv_wm;
sys/dev/pci/drm/i915/display/intel_display_types.h
832
bool cxsr;
sys/dev/pci/drm/i915/display/intel_display_types.h
850
bool cxsr;
sys/dev/pci/drm/i915/display/intel_display_types.h
851
bool hpll_en;
sys/dev/pci/drm/i915/display/intel_display_types.h
852
bool fbc_en;
sys/dev/pci/drm/i915/display/intel_display_types.h
925
bool need_postvbl_update;
sys/dev/pci/drm/i915/display/intel_display_types.h
980
bool active, enable;
sys/dev/pci/drm/i915/display/intel_display_wa.c
50
static bool intel_display_needs_wa_16025573575(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_wa.c
61
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
sys/dev/pci/drm/i915/display/intel_display_wa.h
16
static inline bool intel_display_needs_wa_16023588340(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_display_wa.h
21
bool intel_display_needs_wa_16023588340(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_display_wa.h
30
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
sys/dev/pci/drm/i915/display/intel_dmc.c
1509
bool initialized;
sys/dev/pci/drm/i915/display/intel_dmc.c
1510
bool loaded;
sys/dev/pci/drm/i915/display/intel_dmc.c
1548
bool start_tracking)
sys/dev/pci/drm/i915/display/intel_dmc.c
1564
static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
sys/dev/pci/drm/i915/display/intel_dmc.c
1568
bool dc6_enabled;
sys/dev/pci/drm/i915/display/intel_dmc.c
398
static bool is_valid_dmc_id(enum intel_dmc_id dmc_id)
sys/dev/pci/drm/i915/display/intel_dmc.c
403
static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id)
sys/dev/pci/drm/i915/display/intel_dmc.c
410
bool intel_dmc_has_payload(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dmc.c
463
static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/intel_dmc.c
496
static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/intel_dmc.c
524
static bool is_dmc_evt_ctl_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dmc.c
534
static bool is_dmc_evt_htp_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dmc.c
544
static bool is_event_handler(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dmc.c
553
static bool fixup_dmc_evt(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dmc.c
583
static bool disable_dmc_evt(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dmc.c
690
static bool need_pipedmc_load_program(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dmc.c
696
static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
sys/dev/pci/drm/i915/display/intel_dmc.c
742
static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dmc.c
818
bool enable)
sys/dev/pci/drm/i915/display/intel_dmc.c
82
bool present;
sys/dev/pci/drm/i915/display/intel_dmc.c
850
bool block)
sys/dev/pci/drm/i915/display/intel_dmc.c
868
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_dmc.c
936
static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
sys/dev/pci/drm/i915/display/intel_dmc.c
989
static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
sys/dev/pci/drm/i915/display/intel_dmc.c
99
static bool dmc_firmware_param_disabled(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dmc.h
26
bool block);
sys/dev/pci/drm/i915/display/intel_dmc.h
28
enum pipe pipe, bool enable);
sys/dev/pci/drm/i915/display/intel_dmc.h
32
bool intel_dmc_has_payload(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_dmc.h
37
void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
228
static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
243
static bool intel_dmc_wl_check_range(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
281
static bool __intel_dmc_wl_supported(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dmc_wl.h
19
bool enabled;
sys/dev/pci/drm/i915/display/intel_dmc_wl.h
20
bool taken;
sys/dev/pci/drm/i915/display/intel_dp.c
1084
static bool source_can_output(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
1111
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
1128
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
1141
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
1240
static bool intel_dp_hdisplay_bad(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dp.c
1276
bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_dp.c
1352
bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
136
bool intel_dp_is_edp(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
1391
bool intel_dp_has_dsc(const struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_dp.c
1426
bool dsc = false;
sys/dev/pci/drm/i915/display/intel_dp.c
146
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
1525
bool intel_dp_source_supports_tps3(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dp.c
1531
bool intel_dp_source_supports_tps4(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dp.c
1628
bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
1635
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
1651
bool intel_dp_supports_fec(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
1659
bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
1675
int bpc, bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_dp.c
1707
bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_dp.c
1745
static bool has_seamless_m_n(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_dp.c
1932
static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
sys/dev/pci/drm/i915/display/intel_dp.c
1958
static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,
sys/dev/pci/drm/i915/display/intel_dp.c
2132
bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16)
sys/dev/pci/drm/i915/display/intel_dp.c
2222
bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits,
sys/dev/pci/drm/i915/display/intel_dp.c
2375
bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp.c
2467
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
2471
bool dsc,
sys/dev/pci/drm/i915/display/intel_dp.c
2526
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
2552
bool
sys/dev/pci/drm/i915/display/intel_dp.c
2556
bool respect_downstream_limits,
sys/dev/pci/drm/i915/display/intel_dp.c
2557
bool dsc,
sys/dev/pci/drm/i915/display/intel_dp.c
2561
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp.c
2641
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dp.c
2658
bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_dp.c
2668
bool dsc_needed, joiner_needs_dsc;
sys/dev/pci/drm/i915/display/intel_dp.c
2745
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2778
static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_dp.c
2952
bool
sys/dev/pci/drm/i915/display/intel_dp.c
2989
static bool can_enable_drrs(struct intel_connector *connector,
sys/dev/pci/drm/i915/display/intel_dp.c
3061
static bool intel_dp_has_audio(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_dp.c
3083
bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_dp.c
3090
bool ycbcr_420_only;
sys/dev/pci/drm/i915/display/intel_dp.c
3179
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp.c
3425
static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
3441
write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
sys/dev/pci/drm/i915/display/intel_dp.c
3460
bool enable)
sys/dev/pci/drm/i915/display/intel_dp.c
3473
bool enable)
sys/dev/pci/drm/i915/display/intel_dp.c
3491
bool for_get_ref)
sys/dev/pci/drm/i915/display/intel_dp.c
3530
static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_dp.c
3533
bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
sys/dev/pci/drm/i915/display/intel_dp.c
3540
static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_dp.c
3711
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
3726
bool dpcd_updated = false;
sys/dev/pci/drm/i915/display/intel_dp.c
3746
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_dp.c
3751
bool fastset = true;
sys/dev/pci/drm/i915/display/intel_dp.c
3867
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
3886
bool is_active;
sys/dev/pci/drm/i915/display/intel_dp.c
3947
static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
4041
bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;
sys/dev/pci/drm/i915/display/intel_dp.c
4064
bool hdmi_is_dsc_1_2;
sys/dev/pci/drm/i915/display/intel_dp.c
4112
bool ycbcr444_to_420 = false;
sys/dev/pci/drm/i915/display/intel_dp.c
4113
bool rgb_to_ycbcr = false;
sys/dev/pci/drm/i915/display/intel_dp.c
4174
static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
4415
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
4473
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
4491
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
4626
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
4649
static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
sys/dev/pci/drm/i915/display/intel_dp.c
4662
bool
sys/dev/pci/drm/i915/display/intel_dp.c
483
bool intel_dp_has_joiner(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
4833
bool enable,
sys/dev/pci/drm/i915/display/intel_dp.c
5115
static bool intel_dp_link_ok(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
5120
bool uhbr = intel_dp->link_rate >= 1000000;
sys/dev/pci/drm/i915/display/intel_dp.c
5121
bool ok;
sys/dev/pci/drm/i915/display/intel_dp.c
5144
bool handled = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5154
static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
5186
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
5192
bool link_ok = true;
sys/dev/pci/drm/i915/display/intel_dp.c
5193
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5244
bool is_active;
sys/dev/pci/drm/i915/display/intel_dp.c
5265
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
5314
bool intel_dp_has_connector(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
5405
static bool intel_dp_is_connected(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
5509
static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp.c
5512
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5550
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
5554
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5555
bool ret;
sys/dev/pci/drm/i915/display/intel_dp.c
5685
bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_dp.c
5689
bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
sys/dev/pci/drm/i915/display/intel_dp.c
5690
bool is_connected = false;
sys/dev/pci/drm/i915/display/intel_dp.c
5702
bool intel_digital_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_dp.c
5704
bool ret;
sys/dev/pci/drm/i915/display/intel_dp.c
5771
static bool
sys/dev/pci/drm/i915/display/intel_dp.c
5824
bool vrr_capable;
sys/dev/pci/drm/i915/display/intel_dp.c
5877
static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
sys/dev/pci/drm/i915/display/intel_dp.c
5893
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external)
sys/dev/pci/drm/i915/display/intel_dp.c
5902
bool force)
sys/dev/pci/drm/i915/display/intel_dp.c
6358
bool hpd_high = hpd_state == connector_status_connected;
sys/dev/pci/drm/i915/display/intel_dp.c
6360
bool need_work = false;
sys/dev/pci/drm/i915/display/intel_dp.c
6398
intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
sys/dev/pci/drm/i915/display/intel_dp.c
6456
static bool _intel_dp_is_port_edp(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dp.c
6473
bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_dp.c
6481
bool
sys/dev/pci/drm/i915/display/intel_dp.c
6565
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.c
6571
bool has_dpcd;
sys/dev/pci/drm/i915/display/intel_dp.c
6731
bool
sys/dev/pci/drm/i915/display/intel_dp.c
797
bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
sys/dev/pci/drm/i915/display/intel_dp.c
822
int intel_dp_bw_fec_overhead(bool fec_enabled)
sys/dev/pci/drm/i915/display/intel_dp.h
114
bool intel_dp_source_supports_tps3(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_dp.h
115
bool intel_dp_source_supports_tps4(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_dp.h
122
bool intel_dp_joiner_needs_dsc(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dp.h
124
bool intel_dp_has_joiner(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp.h
125
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
127
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
sys/dev/pci/drm/i915/display/intel_dp.h
135
bool intel_digital_port_connected(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_dp.h
136
bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_dp.h
150
bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16);
sys/dev/pci/drm/i915/display/intel_dp.h
163
bool intel_dp_supports_fec(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.h
167
int intel_dp_bw_fec_overhead(bool fec_enabled);
sys/dev/pci/drm/i915/display/intel_dp.h
169
bool intel_dp_supports_fec(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.h
173
bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.h
182
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_dp.h
195
bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.h
198
bool respect_downstream_limits,
sys/dev/pci/drm/i915/display/intel_dp.h
199
bool dsc,
sys/dev/pci/drm/i915/display/intel_dp.h
203
bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_dp.h
205
bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
sys/dev/pci/drm/i915/display/intel_dp.h
207
bool intel_dp_has_connector(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp.h
216
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
sys/dev/pci/drm/i915/display/intel_dp.h
217
bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
sys/dev/pci/drm/i915/display/intel_dp.h
40
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
48
bool intel_dp_init_connector(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_dp.h
83
bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp.h
84
bool intel_dp_is_edp(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp.h
85
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
86
bool intel_dp_has_dsc(const struct intel_connector *connector);
sys/dev/pci/drm/i915/display/intel_dp.h
89
bool intel_dp_is_port_edp(struct intel_display *display, enum port port);
sys/dev/pci/drm/i915/display/intel_dp.h
91
bool long_hpd);
sys/dev/pci/drm/i915/display/intel_dp_aux.c
253
bool vdd;
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
106
static bool is_intel_tcon_cap(const u8 tcon_cap[4])
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
112
static bool
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
367
static const char *dpcd_vs_pwm_str(bool aux)
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
601
static bool
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
648
bool try_intel_interface = false, try_vesa_interface = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
150
bool *repeater_present)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
184
bool *ksv_ready)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
250
bool enable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
257
bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
277
bool *hdcp_capable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
299
bool msg_detectable;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
365
u8 msg_id, bool *msg_ready)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
407
bool msg_ready = false;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
528
bool msg_expired;
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
600
bool is_repeater, u8 content_type)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
649
bool *capable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
681
bool *capable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
698
bool *hdcp_capable,
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
699
bool *hdcp2_capable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
748
bool enable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
766
bool enable)
sys/dev/pci/drm/i915/display/intel_dp_hdcp.c
798
bool enable)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1023
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1031
bool channel_eq = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1093
static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1164
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1169
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1188
static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
120
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1205
static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
121
intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1270
static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1293
static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
132
bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1339
static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1365
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1370
bool ret = true;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1395
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1403
bool timeout = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1527
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1545
bool timeout = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1583
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1588
bool passed = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1644
bool passed;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
321
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
379
static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
482
bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
488
bool changed = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
528
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
630
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
641
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
660
static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
676
static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
692
static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
712
void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
744
bool enhanced_framing)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
780
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
839
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
889
static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
929
static bool
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
937
bool max_vswing_reached = false;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
95
static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
18
bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
21
int link_rate, bool is_vrr);
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
24
bool enhanced_framing);
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
26
bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1053
bool last_mst_stream;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1163
static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
118
static bool intel_dp_mst_dec_active_streams(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1204
bool first_mst_stream;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1297
bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
131
static bool intel_dp_mst_inc_active_streams(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1354
static bool mst_stream_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1372
static bool mst_stream_initial_fastset_check(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
143
bool dsc)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1462
bool dsc = false;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1576
struct drm_modeset_acquire_ctx *ctx, bool force)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1617
static bool mst_connector_get_hw_state(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1671
static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
178
bool ssc, int dsc_slice_count, int bpp_x16)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1849
static bool
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1893
bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1912
bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1917
bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2017
bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
2114
bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
260
int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
269
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
526
static bool
sys/dev/pci/drm/i915/display/intel_dp_mst.c
533
bool is_uhbr_sink = connector->mst.dp &&
sys/dev/pci/drm/i915/display/intel_dp_mst.c
552
static bool
sys/dev/pci/drm/i915/display/intel_dp_mst.c
557
bool dsc)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
612
static bool
sys/dev/pci/drm/i915/display/intel_dp_mst.c
616
bool dsc,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
647
bool dsc_needed, joiner_needs_dsc;
sys/dev/pci/drm/i915/display/intel_dp_mst.h
22
bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.h
23
bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.h
24
bool intel_dp_mst_source_support(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_mst.h
29
bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_dp_mst.h
32
bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_mst.h
37
int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc);
sys/dev/pci/drm/i915/display/intel_dp_test.c
491
bool intel_dp_test_phy(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_test.c
523
bool intel_dp_test_short_pulse(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_test.c
526
bool reprobe_needed = false;
sys/dev/pci/drm/i915/display/intel_dp_test.h
19
bool intel_dp_test_phy(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_test.h
20
bool intel_dp_test_short_pulse(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
256
bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
297
bool dpcd_updated)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
58
bool *below_dprx_bw)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
74
bool old_bw_below_dprx;
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
75
bool new_bw_below_dprx;
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
31
bool dpcd_updated);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
34
bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
71
bool dpcd_updated) {}
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
74
static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
137
bool dual_channel;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
355
bool bxt_dpio_phy_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
492
bool was_enabled;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
513
static bool __printf(6, 7)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
540
bool bxt_dpio_phy_verify_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
545
bool ok;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
718
bool uniq_trans_scale)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
813
bool reset)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
858
bool reset)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
133
bool uniq_trans_scale)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
138
bool reset)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
36
bool bxt_dpio_phy_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
38
bool bxt_dpio_phy_verify_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
53
bool uniq_trans_scale);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
56
bool reset);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
92
static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
97
static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll.c
1250
static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
sys/dev/pci/drm/i915/display/intel_dpll.c
1814
static bool i9xx_has_pps(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_dpll.c
2308
enum pipe pipe, bool state)
sys/dev/pci/drm/i915/display/intel_dpll.c
2310
bool cur_state;
sys/dev/pci/drm/i915/display/intel_dpll.c
581
static bool intel_pll_is_valid(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll.c
653
static bool
sys/dev/pci/drm/i915/display/intel_dpll.c
711
static bool
sys/dev/pci/drm/i915/display/intel_dpll.c
767
static bool
sys/dev/pci/drm/i915/display/intel_dpll.c
777
bool found = false;
sys/dev/pci/drm/i915/display/intel_dpll.c
821
static bool vlv_PLL_is_optimal(struct intel_display *display, int target_freq,
sys/dev/pci/drm/i915/display/intel_dpll.c
861
static bool
sys/dev/pci/drm/i915/display/intel_dpll.c
873
bool found = false;
sys/dev/pci/drm/i915/display/intel_dpll.c
918
static bool
sys/dev/pci/drm/i915/display/intel_dpll.c
976
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.h
41
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
119
bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1263
static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1298
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1427
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1435
bool ret;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1465
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1474
bool ret;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
180
bool state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
182
bool cur_state;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1996
static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2170
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2180
bool ret;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2479
static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2612
static bool
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2925
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2928
bool is_dkl)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3018
bool use_ssc = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3019
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3020
bool is_dkl = DISPLAY_VER(display) >= 12;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3548
static bool mg_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3556
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3615
static bool dkl_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3623
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3687
static bool icl_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3695
bool ret = false;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3748
static bool combo_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3757
static bool tbt_pll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4117
static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4509
bool intel_dpll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4617
bool intel_dpll_compare_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4639
bool active;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4686
static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
528
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
555
bool enabled;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
661
static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
749
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
771
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
89
bool (*get_hw_state)(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
272
bool ssc_enabled;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
273
bool use_c10;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
274
bool tbt_mode;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
342
bool always_on;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
350
bool is_alt_port_dpll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
378
bool on;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
403
bool state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
425
bool intel_dpll_get_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
439
bool intel_dpll_compare_hw_state(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
443
bool intel_dpll_is_combophy(enum intel_dpll_id id);
sys/dev/pci/drm/i915/display/intel_drrs.c
104
bool intel_drrs_is_active(struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/intel_drrs.c
226
bool invalidate)
sys/dev/pci/drm/i915/display/intel_drrs.c
69
bool intel_cpu_transcoder_has_drrs(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_drrs.h
19
bool intel_cpu_transcoder_has_drrs(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_drrs.h
22
bool intel_drrs_is_active(struct intel_crtc *crtc);
sys/dev/pci/drm/i915/display/intel_dsb.c
102
static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_dsb.c
201
static bool assert_dsb_has_room(struct intel_dsb *dsb)
sys/dev/pci/drm/i915/display/intel_dsb.c
212
static bool assert_dsb_tail_is_aligned(struct intel_dsb *dsb)
sys/dev/pci/drm/i915/display/intel_dsb.c
239
static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
sys/dev/pci/drm/i915/display/intel_dsb.c
288
static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
sys/dev/pci/drm/i915/display/intel_dsb.c
307
static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dsb.c
812
bool wait_for_vblank)
sys/dev/pci/drm/i915/display/intel_dsb.c
875
bool is_busy;
sys/dev/pci/drm/i915/display/intel_dsb.h
69
bool wait_for_vblank);
sys/dev/pci/drm/i915/display/intel_dsb_buffer.c
35
bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
sys/dev/pci/drm/i915/display/intel_dsb_buffer.h
24
bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf,
sys/dev/pci/drm/i915/display/intel_dsi.h
147
static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
sys/dev/pci/drm/i915/display/intel_dsi.h
152
static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
sys/dev/pci/drm/i915/display/intel_dsi.h
90
bool bgr_enabled;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
198
const char *con_id, u8 idx, bool value)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
226
const char *con_id, u8 idx, bool value)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
250
u8 gpio_source, u8 gpio_index, bool value)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
272
u8 gpio_source, u8 gpio_index, bool value)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
315
u8 gpio_index, bool value)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
334
int gpio, bool value)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
404
bool value;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
406
bool native = DISPLAY_VER(display) >= 11;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
770
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
909
void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
918
bool want_backlight_gpio = false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
919
bool want_panel_gpio = false;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.h
14
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
sys/dev/pci/drm/i915/display/intel_dsi_vbt.h
15
void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);
sys/dev/pci/drm/i915/display/intel_dvo.c
131
static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_dvo.c
147
static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_dvo.c
320
intel_dvo_detect(struct drm_connector *_connector, bool force)
sys/dev/pci/drm/i915/display/intel_dvo.c
417
static bool intel_dvo_init_dev(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dvo.c
425
bool ret;
sys/dev/pci/drm/i915/display/intel_dvo.c
476
static bool intel_dvo_probe(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_dvo_dev.h
53
bool (*init)(struct intel_dvo_device *dvo,
sys/dev/pci/drm/i915/display/intel_dvo_dev.h
62
void (*dpms)(struct intel_dvo_device *dvo, bool enable);
sys/dev/pci/drm/i915/display/intel_dvo_dev.h
96
bool (*get_hw_state)(struct intel_dvo_device *dev);
sys/dev/pci/drm/i915/display/intel_fb.c
1242
static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fb.c
1282
bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
sys/dev/pci/drm/i915/display/intel_fb.c
1290
bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fb.c
1310
static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fb.c
1650
bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
sys/dev/pci/drm/i915/display/intel_fb.c
445
static bool plane_caps_contain_any(u8 caps, u8 mask)
sys/dev/pci/drm/i915/display/intel_fb.c
450
static bool plane_caps_contain_all(u8 caps, u8 mask)
sys/dev/pci/drm/i915/display/intel_fb.c
462
bool intel_fb_is_tiled_modifier(u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
476
bool intel_fb_is_ccs_modifier(u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
489
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
502
bool intel_fb_is_mc_ccs_modifier(u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
515
bool intel_fb_needs_64k_phys(u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
533
bool intel_fb_is_tile4_modifier(u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
539
static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
sys/dev/pci/drm/i915/display/intel_fb.c
546
static bool plane_has_modifier(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fb.c
620
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
631
static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
sys/dev/pci/drm/i915/display/intel_fb.c
651
bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
sys/dev/pci/drm/i915/display/intel_fb.c
674
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
sys/dev/pci/drm/i915/display/intel_fb.c
689
static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
sys/dev/pci/drm/i915/display/intel_fb.c
717
static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)
sys/dev/pci/drm/i915/display/intel_fb.c
722
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
sys/dev/pci/drm/i915/display/intel_fb.c
902
bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
907
bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
sys/dev/pci/drm/i915/display/intel_fb.h
120
bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
121
bool intel_fb_uses_dpt(const struct drm_framebuffer *fb);
sys/dev/pci/drm/i915/display/intel_fb.h
35
bool intel_fb_is_tiled_modifier(u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
36
bool intel_fb_is_ccs_modifier(u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
37
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
38
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
39
bool intel_fb_needs_64k_phys(u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
40
bool intel_fb_is_tile4_modifier(u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
42
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
sys/dev/pci/drm/i915/display/intel_fb.h
47
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
sys/dev/pci/drm/i915/display/intel_fb.h
52
bool
sys/dev/pci/drm/i915/display/intel_fb.h
56
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
sys/dev/pci/drm/i915/display/intel_fb.h
81
bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb);
sys/dev/pci/drm/i915/display/intel_fb.h
82
bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
sys/dev/pci/drm/i915/display/intel_fb.h
83
bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb);
sys/dev/pci/drm/i915/display/intel_fb_pin.c
115
bool uses_fence,
sys/dev/pci/drm/i915/display/intel_fb_pin.h
23
bool uses_fence,
sys/dev/pci/drm/i915/display/intel_fbc.c
1010
static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1015
static bool stride_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1031
static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1051
static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1070
static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1086
static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1098
static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1103
static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1108
static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
111
bool false_color;
sys/dev/pci/drm/i915/display/intel_fbc.c
1120
static bool rotation_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
113
bool active;
sys/dev/pci/drm/i915/display/intel_fbc.c
114
bool activated;
sys/dev/pci/drm/i915/display/intel_fbc.c
115
bool flip_pending;
sys/dev/pci/drm/i915/display/intel_fbc.c
1159
static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
117
bool underrun_detected;
sys/dev/pci/drm/i915/display/intel_fbc.c
1192
static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1205
static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1212
static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1217
static bool tiling_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1330
static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1351
static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1361
static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1583
static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_fbc.c
1628
static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_fbc.c
1634
bool need_vblank_wait = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
1665
bool intel_fbc_pre_update(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_fbc.c
1669
bool need_vblank_wait = false;
sys/dev/pci/drm/i915/display/intel_fbc.c
264
static bool intel_fbc_has_fences(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_fbc.c
355
static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
360
static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
485
static bool g4x_fbc_is_active(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
490
static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
525
bool disable)
sys/dev/pci/drm/i915/display/intel_fbc.c
554
static bool ilk_fbc_is_active(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
559
static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
696
static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
702
bool enable)
sys/dev/pci/drm/i915/display/intel_fbc.c
718
static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
742
static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
sys/dev/pci/drm/i915/display/intel_fbc.c
79
bool (*is_active)(struct intel_fbc *fbc);
sys/dev/pci/drm/i915/display/intel_fbc.c
80
bool (*is_compressing)(struct intel_fbc *fbc);
sys/dev/pci/drm/i915/display/intel_fbc.c
83
void (*set_false_color)(struct intel_fbc *fbc, bool enable);
sys/dev/pci/drm/i915/display/intel_fbc.c
974
static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
983
static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
992
static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
997
static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_fbc.h
31
bool intel_fbc_pre_update(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_fbdev.c
196
static void intelfb_set_suspend(struct drm_fb_helper *fb_helper, bool suspend)
sys/dev/pci/drm/i915/display/intel_fbdev.c
257
bool prealloc = false;
sys/dev/pci/drm/i915/display/intel_fbdev.c
396
static bool intel_fbdev_init_bios(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fdi.c
101
enum pipe pipe, bool state)
sys/dev/pci/drm/i915/display/intel_fdi.c
103
bool cur_state;
sys/dev/pci/drm/i915/display/intel_fdi.c
30
enum pipe pipe, bool state)
sys/dev/pci/drm/i915/display/intel_fdi.c
32
bool cur_state;
sys/dev/pci/drm/i915/display/intel_fdi.c
389
static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/intel_fdi.c
63
enum pipe pipe, bool state)
sys/dev/pci/drm/i915/display/intel_fdi.c
65
bool cur_state;
sys/dev/pci/drm/i915/display/intel_fdi.c
85
bool cur_state;
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
115
bool enable, bool old)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
135
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
165
enum pipe pipe, bool enable,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
166
bool old)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
189
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
199
bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
232
bool enable, bool old)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
254
static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
255
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
258
bool old;
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
293
bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
294
enum pipe pipe, bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
297
bool ret;
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
320
bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
322
bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
326
bool old;
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
462
bool enable)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
60
static bool ivb_can_enable_err_int(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
77
static bool cpt_can_enable_serr_int(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.h
16
struct intel_crtc *crtc, bool enable);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.h
17
bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.h
18
enum pipe pipe, bool enable);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.h
19
bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.h
21
bool enable);
sys/dev/pci/drm/i915/display/intel_fixed.h
20
static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
sys/dev/pci/drm/i915/display/intel_flipq.c
113
bool intel_flipq_supported(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_flipq.c
158
static void intel_flipq_preempt(struct intel_crtc *crtc, bool preempt)
sys/dev/pci/drm/i915/display/intel_flipq.c
328
static bool assert_flipq_has_room(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_flipq.c
451
static bool need_dmc_halt_wa(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_flipq.h
19
bool intel_flipq_supported(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_frontbuffer.h
98
static inline bool intel_frontbuffer_invalidate(struct intel_frontbuffer *front,
sys/dev/pci/drm/i915/display/intel_global_state.c
147
static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx *ctx,
sys/dev/pci/drm/i915/display/intel_global_state.c
340
bool
sys/dev/pci/drm/i915/display/intel_global_state.h
35
bool changed, serialized;
sys/dev/pci/drm/i915/display/intel_global_state.h
63
bool intel_atomic_global_state_is_serialized(struct intel_atomic_state *state);
sys/dev/pci/drm/i915/display/intel_gmbus.c
1106
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
sys/dev/pci/drm/i915/display/intel_gmbus.c
1122
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
sys/dev/pci/drm/i915/display/intel_gmbus.c
199
bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
sys/dev/pci/drm/i915/display/intel_gmbus.c
222
bool enable)
sys/dev/pci/drm/i915/display/intel_gmbus.c
231
bool enable)
sys/dev/pci/drm/i915/display/intel_gmbus.c
239
bool enable)
sys/dev/pci/drm/i915/display/intel_gmbus.c
323
ptl_handle_mask_bits(struct intel_gmbus *bus, bool set)
sys/dev/pci/drm/i915/display/intel_gmbus.c
499
static bool has_gmbus_irq(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_gmbus.c
579
bool burst_read = len > gmbus_max_xfer_size(display);
sys/dev/pci/drm/i915/display/intel_gmbus.c
580
bool extra_byte_added = false;
sys/dev/pci/drm/i915/display/intel_gmbus.c
725
static bool
sys/dev/pci/drm/i915/display/intel_gmbus.h
39
bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);
sys/dev/pci/drm/i915/display/intel_gmbus.h
44
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
sys/dev/pci/drm/i915/display/intel_gmbus.h
45
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
sys/dev/pci/drm/i915/display/intel_hdcp.c
1091
u64 value, bool update_property)
sys/dev/pci/drm/i915/display/intel_hdcp.c
120
bool enforce_type0 = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
1215
bool is_hdcp_supported(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_hdcp.c
1251
bool *paired,
sys/dev/pci/drm/i915/display/intel_hdcp.c
185
bool intel_hdcp_is_ksv_valid(u8 *ksv)
sys/dev/pci/drm/i915/display/intel_hdcp.c
2110
_intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery)
sys/dev/pci/drm/i915/display/intel_hdcp.c
221
static bool intel_hdcp_get_capability(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_hdcp.c
225
bool capable = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2349
static bool is_hdcp2_supported(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_hdcp.c
250
static bool intel_hdcp2_prerequisite(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_hdcp.c
2573
bool content_protection_type_changed, desired_and_not_enabled = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2756
bool remote_req)
sys/dev/pci/drm/i915/display/intel_hdcp.c
2758
bool hdcp_cap = false, hdcp2_cap = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
277
static bool intel_hdcp2_get_capability(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_hdcp.c
280
bool capable = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2828
bool force_hdcp14 = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
292
bool *hdcp_capable,
sys/dev/pci/drm/i915/display/intel_hdcp.c
293
bool *hdcp2_capable)
sys/dev/pci/drm/i915/display/intel_hdcp.c
307
static bool intel_hdcp_in_use(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_hdcp.c
315
static bool intel_hdcp2_in_use(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_hdcp.c
327
bool ksv_ready;
sys/dev/pci/drm/i915/display/intel_hdcp.c
341
static bool hdcp_key_loadable(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_hdcp.c
344
bool enabled = false;
sys/dev/pci/drm/i915/display/intel_hdcp.c
47
bool enable)
sys/dev/pci/drm/i915/display/intel_hdcp.c
831
bool repeater_present, hdcp_capable;
sys/dev/pci/drm/i915/display/intel_hdcp.h
41
bool is_hdcp_supported(struct intel_display *display, enum port port);
sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c
22
bool intel_hdcp_gsc_check_status(struct drm_device *drm)
sys/dev/pci/drm/i915/display/intel_hdcp_gsc.h
17
bool intel_hdcp_gsc_check_status(struct drm_device *drm);
sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c
78
bool *km_stored,
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
106
bool *capable);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
122
bool is_repeater, u8 type);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
126
bool enable);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
134
bool *hdcp_capable, bool *hdcp2_capable);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
67
bool *repeater_present);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
74
bool *ksv_ready);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
87
bool enable);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
91
bool enable);
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
94
bool (*check_link)(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_hdcp_shim.h
99
bool *hdcp_capable);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1051
bool enable,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1110
bool enable,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1159
bool enable,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1241
bool enable,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1284
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1414
bool *repeater_present)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1447
bool *ksv_ready)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1537
bool enable)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1568
bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1599
bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1634
static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1655
u8 msg_id, bool *msg_ready,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1683
u8 msg_id, bool paired)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1686
bool msg_ready = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1778
bool *capable)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1834
static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1843
static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1849
bool respect_downstream_limits,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1850
bool has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1875
int clock, bool respect_downstream_limits,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1876
bool has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1926
static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1941
static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1942
int bpc, bool has_hdmi_sink,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1976
bool has_hdmi_sink,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2021
bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2022
bool ycbcr_420_only;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2078
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2079
int bpc, bool has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2098
static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2119
int clock, bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2154
bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2186
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2214
static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2234
bool ycbcr_420_output)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2254
bool respect_downstream_limits)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2260
bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2289
static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2295
static bool source_supports_scrambling(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2314
bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2500
static bool
sys/dev/pci/drm/i915/display/intel_hdmi.c
2509
bool connected = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2543
intel_hdmi_detect(struct drm_connector *_connector, bool force)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2701
bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2703
bool high_tmds_clock_ratio,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2704
bool scrambling)
sys/dev/pci/drm/i915/display/intel_hdmi.c
3044
bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_hdmi.c
3270
int output_format, bool hdmi_all_bpp,
sys/dev/pci/drm/i915/display/intel_hdmi.c
3275
bool bpp_found = false;
sys/dev/pci/drm/i915/display/intel_hdmi.c
712
static bool
sys/dev/pci/drm/i915/display/intel_hdmi.c
769
static bool
sys/dev/pci/drm/i915/display/intel_hdmi.c
801
static bool
sys/dev/pci/drm/i915/display/intel_hdmi.c
831
static bool
sys/dev/pci/drm/i915/display/intel_hdmi.c
867
bool enable,
sys/dev/pci/drm/i915/display/intel_hdmi.c
946
static bool gcp_default_phase_possible(int pipe_bpp,
sys/dev/pci/drm/i915/display/intel_hdmi.c
979
static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_hdmi.h
24
bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_hdmi.h
26
bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_hdmi.h
33
bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_hdmi.h
35
bool high_tmds_clock_ratio,
sys/dev/pci/drm/i915/display/intel_hdmi.h
36
bool scrambling);
sys/dev/pci/drm/i915/display/intel_hdmi.h
37
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
sys/dev/pci/drm/i915/display/intel_hdmi.h
51
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
53
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
54
int bpc, bool has_hdmi_sink);
sys/dev/pci/drm/i915/display/intel_hdmi.h
57
int num_slices, int output_format, bool hdmi_all_bpp,
sys/dev/pci/drm/i915/display/intel_hotplug.c
1025
static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)
sys/dev/pci/drm/i915/display/intel_hotplug.c
1036
static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin)
sys/dev/pci/drm/i915/display/intel_hotplug.c
1078
bool do_flush = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
1164
bool intel_hpd_schedule_detection(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_hotplug.c
1167
bool ret;
sys/dev/pci/drm/i915/display/intel_hotplug.c
1289
bool new_state;
sys/dev/pci/drm/i915/display/intel_hotplug.c
152
static bool intel_hpd_irq_storm_detect(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_hotplug.c
153
enum hpd_pin pin, bool long_hpd)
sys/dev/pci/drm/i915/display/intel_hotplug.c
160
bool storm = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
187
static bool detection_work_enabled(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_hotplug.c
194
static bool
sys/dev/pci/drm/i915/display/intel_hotplug.c
205
static bool
sys/dev/pci/drm/i915/display/intel_hotplug.c
216
static bool
sys/dev/pci/drm/i915/display/intel_hotplug.c
232
bool hpd_disabled = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
316
bool ret = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
349
static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_hotplug.c
355
static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin pin)
sys/dev/pci/drm/i915/display/intel_hotplug.c
370
static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin pin)
sys/dev/pci/drm/i915/display/intel_hotplug.c
413
bool long_hpd, short_hpd;
sys/dev/pci/drm/i915/display/intel_hotplug.c
591
bool storm_detected = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
592
bool queue_dig = false, queue_hp = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
609
bool long_hpd;
sys/dev/pci/drm/i915/display/intel_hotplug.c
639
bool long_hpd;
sys/dev/pci/drm/i915/display/intel_hotplug.c
789
bool enabled;
sys/dev/pci/drm/i915/display/intel_hotplug.c
954
static bool cancel_all_detection_work(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_hotplug.c
956
bool was_pending = false;
sys/dev/pci/drm/i915/display/intel_hotplug.c
995
bool queue_hp_work = false;
sys/dev/pci/drm/i915/display/intel_hotplug.h
36
bool intel_hpd_schedule_detection(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
1089
static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
1095
enum hpd_pin hpd_pin, bool enable)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
19
typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
216
static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
231
static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
245
static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
258
static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
273
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
283
static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
299
static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
309
static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
323
static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
sys/dev/pci/drm/i915/display/intel_hotplug_irq.c
348
bool long_pulse_detect(enum hpd_pin pin, u32 val))
sys/dev/pci/drm/i915/display/intel_hti.c
24
bool intel_hti_uses_phy(struct intel_display *display, enum phy phy)
sys/dev/pci/drm/i915/display/intel_hti.h
15
bool intel_hti_uses_phy(struct intel_display *display, enum phy phy);
sys/dev/pci/drm/i915/display/intel_link_bw.c
103
bool reduce_forced_bpp)
sys/dev/pci/drm/i915/display/intel_link_bw.c
180
bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_link_bw.c
213
bool
sys/dev/pci/drm/i915/display/intel_link_bw.c
260
static bool
sys/dev/pci/drm/i915/display/intel_link_bw.c
265
bool bpps_changed = false;
sys/dev/pci/drm/i915/display/intel_link_bw.c
420
static bool connector_supports_dsc(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_link_bw.h
30
bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_link_bw.h
31
bool intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_lpe_audio.c
194
static bool lpe_audio_detect(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_lpe_audio.c
352
const void *eld, int ls_clock, bool dp_output)
sys/dev/pci/drm/i915/display/intel_lpe_audio.h
21
const void *eld, int ls_clock, bool dp_output);
sys/dev/pci/drm/i915/display/intel_lpe_audio.h
35
const void *eld, int ls_clock, bool dp_output)
sys/dev/pci/drm/i915/display/intel_lspcon.c
132
bool intel_lspcon_detect_hdr_capability(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_lspcon.c
243
static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
sys/dev/pci/drm/i915/display/intel_lspcon.c
261
static bool lspcon_probe(struct intel_lspcon *lspcon)
sys/dev/pci/drm/i915/display/intel_lspcon.c
330
static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
sys/dev/pci/drm/i915/display/intel_lspcon.c
356
static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
sys/dev/pci/drm/i915/display/intel_lspcon.c
403
static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
sys/dev/pci/drm/i915/display/intel_lspcon.c
435
static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
sys/dev/pci/drm/i915/display/intel_lspcon.c
501
bool ret = true;
sys/dev/pci/drm/i915/display/intel_lspcon.c
539
bool enable,
sys/dev/pci/drm/i915/display/intel_lspcon.c
612
static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
sys/dev/pci/drm/i915/display/intel_lspcon.c
627
static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
sys/dev/pci/drm/i915/display/intel_lspcon.c
648
bool infoframes_enabled;
sys/dev/pci/drm/i915/display/intel_lspcon.c
679
bool intel_lspcon_init(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_lspcon.c
710
bool intel_lspcon_active(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_lspcon.c
89
static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
sys/dev/pci/drm/i915/display/intel_lspcon.h
16
bool intel_lspcon_init(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_lspcon.h
17
bool intel_lspcon_active(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_lspcon.h
18
bool intel_lspcon_detect_hdr_capability(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_lspcon.h
34
bool enable,
sys/dev/pci/drm/i915/display/intel_lvds.c
103
static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_lvds.c
109
bool ret;
sys/dev/pci/drm/i915/display/intel_lvds.c
66
bool powerdown_on_reset;
sys/dev/pci/drm/i915/display/intel_lvds.c
72
bool is_dual_link;
sys/dev/pci/drm/i915/display/intel_lvds.c
788
bool intel_is_dual_link_lvds(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_lvds.c
795
static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
sys/dev/pci/drm/i915/display/intel_lvds.c
87
bool intel_lvds_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_lvds.h
17
bool intel_lvds_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_lvds.h
21
bool intel_is_dual_link_lvds(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_lvds.h
23
static inline bool intel_lvds_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_lvds.h
35
static inline bool intel_is_dual_link_lvds(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_modeset_lock.c
23
bool _intel_modeset_lock_loop(int *ret)
sys/dev/pci/drm/i915/display/intel_modeset_lock.h
18
bool _intel_modeset_lock_loop(int *ret);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
398
static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
409
static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
466
static bool intel_sanitize_crtc(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
471
bool needs_link_reset;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
554
static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
589
bool has_active_crtc = crtc_state &&
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
667
bool visible;
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
121
bool enabled = false, found = false;
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
152
bool active;
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
201
bool active;
sys/dev/pci/drm/i915/display/intel_opregion.c
1172
bool intel_opregion_vbt_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_opregion.c
1195
bool intel_opregion_headless_sku(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_opregion.c
392
bool enable)
sys/dev/pci/drm/i915/display/intel_opregion.c
666
bool intel_opregion_asle_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_opregion.c
806
bool requested_callbacks = false;
sys/dev/pci/drm/i915/display/intel_opregion.h
101
intel_opregion_notify_encoder(struct intel_encoder *encoder, bool enable)
sys/dev/pci/drm/i915/display/intel_opregion.h
123
static inline bool intel_opregion_vbt_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_opregion.h
134
static inline bool intel_opregion_headless_sku(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_opregion.h
47
bool intel_opregion_asle_present(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_opregion.h
50
bool enable);
sys/dev/pci/drm/i915/display/intel_opregion.h
56
bool intel_opregion_vbt_present(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_opregion.h
59
bool intel_opregion_headless_sku(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_opregion.h
91
static inline bool intel_opregion_asle_present(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_overlay.c
1240
static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
sys/dev/pci/drm/i915/display/intel_overlay.c
1255
static bool check_gamma5_errata(u32 gamma5)
sys/dev/pci/drm/i915/display/intel_overlay.c
1360
static int get_registers(struct intel_overlay *overlay, bool use_phys)
sys/dev/pci/drm/i915/display/intel_overlay.c
1446
bool intel_overlay_available(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_overlay.c
196
bool active;
sys/dev/pci/drm/i915/display/intel_overlay.c
197
bool pfit_active;
sys/dev/pci/drm/i915/display/intel_overlay.c
213
bool enable)
sys/dev/pci/drm/i915/display/intel_overlay.c
322
bool load_polyphase_filter)
sys/dev/pci/drm/i915/display/intel_overlay.c
624
static bool update_scaling_factors(struct intel_overlay *overlay,
sys/dev/pci/drm/i915/display/intel_overlay.c
632
bool scale_changed = false;
sys/dev/pci/drm/i915/display/intel_overlay.c
805
bool scale_changed = false;
sys/dev/pci/drm/i915/display/intel_overlay.h
21
bool intel_overlay_available(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_overlay.h
33
static inline bool intel_overlay_available(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_panel.c
103
static bool is_alt_drrs_mode(const struct drm_display_mode *mode,
sys/dev/pci/drm/i915/display/intel_panel.c
113
static bool is_alt_fixed_mode(const struct drm_display_mode *mode,
sys/dev/pci/drm/i915/display/intel_panel.c
179
static bool has_drrs_modes(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_panel.c
206
bool is_vrr;
sys/dev/pci/drm/i915/display/intel_panel.c
317
bool use_alt_fixed_modes)
sys/dev/pci/drm/i915/display/intel_panel.c
384
intel_panel_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/i915/display/intel_panel.c
47
bool intel_panel_use_ssc(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_panel.c
62
static bool is_best_fixed_mode(struct intel_connector *connector,
sys/dev/pci/drm/i915/display/intel_panel.h
29
intel_panel_detect(struct drm_connector *connector, bool force);
sys/dev/pci/drm/i915/display/intel_panel.h
30
bool intel_panel_use_ssc(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_panel.h
50
bool use_alt_fixed_modes);
sys/dev/pci/drm/i915/display/intel_pch.c
217
static bool intel_is_virt_pch(unsigned short id,
sys/dev/pci/drm/i915/display/intel_pch_display.c
109
bool enabled;
sys/dev/pci/drm/i915/display/intel_pch_display.c
25
bool intel_has_pch_trancoder(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_pch_display.c
47
bool state;
sys/dev/pci/drm/i915/display/intel_pch_display.c
503
bool pll_active;
sys/dev/pci/drm/i915/display/intel_pch_display.c
66
bool state;
sys/dev/pci/drm/i915/display/intel_pch_display.h
19
bool intel_has_pch_trancoder(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_pch_display.h
46
static inline bool intel_has_pch_trancoder(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
281
bool with_spread, bool with_fdi)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
405
static bool spll_uses_pch_ssc(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
424
static bool wrpll_uses_pch_ssc(struct intel_display *display, enum intel_dpll_id id)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
446
bool has_fdi = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
507
bool has_lvds = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
508
bool has_cpu_edp = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
509
bool has_panel = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
510
bool has_ck505 = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
511
bool can_ssc = false;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
512
bool using_ssc_source = false;
sys/dev/pci/drm/i915/display/intel_pfit.c
696
static bool i9xx_has_pfit(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
133
bool need_stable_symbols = false;
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
282
intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
sys/dev/pci/drm/i915/display/intel_pipe_crc.c
593
bool enable;
sys/dev/pci/drm/i915/display/intel_plane.c
1058
bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
sys/dev/pci/drm/i915/display/intel_plane.c
1624
static bool active_planes_affects_min_cdclk(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_plane.c
173
bool intel_plane_needs_physical(struct intel_plane *plane)
sys/dev/pci/drm/i915/display/intel_plane.c
181
bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
sys/dev/pci/drm/i915/display/intel_plane.c
191
bool intel_plane_format_mod_supported_async(struct drm_plane *plane,
sys/dev/pci/drm/i915/display/intel_plane.c
297
bool *need_cdclk_calc)
sys/dev/pci/drm/i915/display/intel_plane.c
448
static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_plane.c
458
static bool intel_plane_do_async_flip(struct intel_plane *plane,
sys/dev/pci/drm/i915/display/intel_plane.c
486
static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
491
bool old_visible = old_plane_state->uapi.visible;
sys/dev/pci/drm/i915/display/intel_plane.c
492
bool new_visible = new_plane_state->uapi.visible;
sys/dev/pci/drm/i915/display/intel_plane.c
495
bool modeset, turn_on, turn_off;
sys/dev/pci/drm/i915/display/intel_plane.c
527
static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
532
bool old_visible = old_plane_state->uapi.visible;
sys/dev/pci/drm/i915/display/intel_plane.c
533
bool new_visible = new_plane_state->uapi.visible;
sys/dev/pci/drm/i915/display/intel_plane.c
534
bool modeset, turn_on;
sys/dev/pci/drm/i915/display/intel_plane.c
590
bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
sys/dev/pci/drm/i915/display/intel_plane.c
591
bool was_crtc_enabled = old_crtc_state->hw.active;
sys/dev/pci/drm/i915/display/intel_plane.c
592
bool is_crtc_enabled = new_crtc_state->hw.active;
sys/dev/pci/drm/i915/display/intel_plane.c
593
bool turn_off, turn_on, visible, was_visible;
sys/dev/pci/drm/i915/display/intel_plane.c
858
bool async_flip)
sys/dev/pci/drm/i915/display/intel_plane.c
999
bool can_position)
sys/dev/pci/drm/i915/display/intel_plane.h
24
bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
sys/dev/pci/drm/i915/display/intel_plane.h
44
bool async_flip);
sys/dev/pci/drm/i915/display/intel_plane.h
74
bool *need_cdclk_calc);
sys/dev/pci/drm/i915/display/intel_plane.h
78
bool can_position);
sys/dev/pci/drm/i915/display/intel_plane.h
83
bool intel_plane_needs_physical(struct intel_plane *plane);
sys/dev/pci/drm/i915/display/intel_plane.h
90
bool intel_plane_format_mod_supported_async(struct drm_plane *plane,
sys/dev/pci/drm/i915/display/intel_plane_initial.c
23
static bool
sys/dev/pci/drm/i915/display/intel_plane_initial.c
258
static bool
sys/dev/pci/drm/i915/display/intel_plane_initial.c
69
static bool
sys/dev/pci/drm/i915/display/intel_plane_initial.c
77
bool is_present, is_local;
sys/dev/pci/drm/i915/display/intel_pmdemand.c
148
bool set_bit)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
205
bool set_bit,
sys/dev/pci/drm/i915/display/intel_pmdemand.c
258
static bool
sys/dev/pci/drm/i915/display/intel_pmdemand.c
265
static bool
sys/dev/pci/drm/i915/display/intel_pmdemand.c
295
static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
390
static bool intel_pmdemand_check_prev_transaction(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
452
static bool intel_pmdemand_req_complete(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
519
u32 *reg1, u32 *reg2, bool serialized)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
575
bool serialized)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
577
bool changed = false;
sys/dev/pci/drm/i915/display/intel_pmdemand.c
624
static bool
sys/dev/pci/drm/i915/display/intel_pmdemand.h
32
bool clear_bit);
sys/dev/pci/drm/i915/display/intel_pps.c
100
bool pll_enabled, release_cl_override = false;
sys/dev/pci/drm/i915/display/intel_pps.c
1147
void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
sys/dev/pci/drm/i915/display/intel_pps.c
1152
bool is_enabled;
sys/dev/pci/drm/i915/display/intel_pps.c
1362
bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_pps.c
1365
bool have_power = false;
sys/dev/pci/drm/i915/display/intel_pps.c
1458
static bool pps_delays_valid(struct intel_pps_delays *delays)
sys/dev/pci/drm/i915/display/intel_pps.c
1597
static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
sys/dev/pci/drm/i915/display/intel_pps.c
1716
bool intel_pps_init(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_pps.c
1719
bool ret;
sys/dev/pci/drm/i915/display/intel_pps.c
1845
bool locked = true;
sys/dev/pci/drm/i915/display/intel_pps.c
279
typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
sys/dev/pci/drm/i915/display/intel_pps.c
281
static bool pps_has_pp_on(struct intel_display *display, int pps_idx)
sys/dev/pci/drm/i915/display/intel_pps.c
286
static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)
sys/dev/pci/drm/i915/display/intel_pps.c
291
static bool pps_any(struct intel_display *display, int pps_idx)
sys/dev/pci/drm/i915/display/intel_pps.c
31
static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
sys/dev/pci/drm/i915/display/intel_pps.c
375
static bool intel_pps_is_valid(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_pps.c
400
static bool
sys/dev/pci/drm/i915/display/intel_pps.c
547
static bool edp_have_panel_power(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_pps.c
560
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_pps.c
745
bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_pps.c
751
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
sys/dev/pci/drm/i915/display/intel_pps.c
814
bool vdd;
sys/dev/pci/drm/i915/display/intel_pps.c
929
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
sys/dev/pci/drm/i915/display/intel_pps.h
28
void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
sys/dev/pci/drm/i915/display/intel_pps.h
30
bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_pps.h
31
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
sys/dev/pci/drm/i915/display/intel_pps.h
41
bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_pps.h
44
bool intel_pps_init(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_psr.c
1118
static bool
sys/dev/pci/drm/i915/display/intel_psr.c
1192
static bool
sys/dev/pci/drm/i915/display/intel_psr.c
1253
static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1268
static bool psr2_granularity_check(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1311
static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1368
static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1370
bool aux_less)
sys/dev/pci/drm/i915/display/intel_psr.c
1394
static bool alpm_config_valid(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1396
bool aux_less)
sys/dev/pci/drm/i915/display/intel_psr.c
1415
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1515
static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1569
static bool _psr_compute_config(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1598
static bool
sys/dev/pci/drm/i915/display/intel_psr.c
1655
static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1832
bool activate = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1975
static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
208
bool intel_encoder_can_psr(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_psr.c
217
bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_psr.c
2318
bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
236
static bool psr_global_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
2503
bool full_update)
sys/dev/pci/drm/i915/display/intel_psr.c
251
static bool sel_update_global_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
2537
bool full_update)
sys/dev/pci/drm/i915/display/intel_psr.c
2570
static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2575
bool su_area_changed = false;
sys/dev/pci/drm/i915/display/intel_psr.c
2605
bool *cursor_in_su_area)
sys/dev/pci/drm/i915/display/intel_psr.c
262
static bool panel_replay_global_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
2646
static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2664
static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2728
bool full_update = false, su_area_changed;
sys/dev/pci/drm/i915/display/intel_psr.c
2836
bool cursor_in_su_area;
sys/dev/pci/drm/i915/display/intel_psr.c
3011
bool keep_disabled = false;
sys/dev/pci/drm/i915/display/intel_psr.c
3148
static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
3719
bool intel_psr_enabled(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
3721
bool ret;
sys/dev/pci/drm/i915/display/intel_psr.c
3745
bool intel_psr_link_ok(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.c
3747
bool ret;
sys/dev/pci/drm/i915/display/intel_psr.c
3812
bool dc5_dc6_blocked;
sys/dev/pci/drm/i915/display/intel_psr.c
3889
struct intel_crtc *crtc, bool enable)
sys/dev/pci/drm/i915/display/intel_psr.c
393
u32 val, bool sel_update_enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3941
bool enable)
sys/dev/pci/drm/i915/display/intel_psr.c
4078
bool enabled;
sys/dev/pci/drm/i915/display/intel_psr.c
4352
bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
4362
bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
663
bool y_req = intel_dp->psr_dpcd[1] &
sys/dev/pci/drm/i915/display/intel_psr.c
732
static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
sys/dev/pci/drm/i915/display/intel_psr.c
897
static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_psr.h
28
bool intel_encoder_can_psr(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_psr.h
29
bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_psr.h
57
bool intel_psr_enabled(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_psr.h
66
bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
68
struct intel_crtc *crtc, bool enable);
sys/dev/pci/drm/i915/display/intel_psr.h
72
bool enable);
sys/dev/pci/drm/i915/display/intel_psr.h
73
bool intel_psr_link_ok(struct intel_dp *intel_dp);
sys/dev/pci/drm/i915/display/intel_psr.h
83
bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
84
bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
sys/dev/pci/drm/i915/display/intel_qp_tables.c
457
u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420)
sys/dev/pci/drm/i915/display/intel_qp_tables.c
467
u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420)
sys/dev/pci/drm/i915/display/intel_qp_tables.h
11
u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420);
sys/dev/pci/drm/i915/display/intel_qp_tables.h
12
u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420);
sys/dev/pci/drm/i915/display/intel_quirks.c
301
bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk)
sys/dev/pci/drm/i915/display/intel_quirks.c
306
bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)
sys/dev/pci/drm/i915/display/intel_quirks.h
29
bool intel_has_quirk(struct intel_display *display, enum intel_quirk_id quirk);
sys/dev/pci/drm/i915/display/intel_quirks.h
30
bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk);
sys/dev/pci/drm/i915/display/intel_sbi.c
18
u32 *val, bool is_read)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1007
static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1098
static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1134
static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1217
static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1233
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
1255
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
1315
static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1325
static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1337
static bool intel_sdvo_has_audio(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1655
static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_sdvo.c
166
bool is_hdmi;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1667
bool intel_sdvo_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1685
static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1691
bool ret;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1710
bool ret;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1906
bool input1, input2;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1908
bool success;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1944
bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1979
static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
sys/dev/pci/drm/i915/display/intel_sdvo.c
199
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
201
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
205
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2123
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2127
bool monitor_is_digital = drm_edid_is_digital(drm_edid);
sys/dev/pci/drm/i915/display/intel_sdvo.c
2128
bool connector_is_digital = !!IS_DIGITAL(sdvo);
sys/dev/pci/drm/i915/display/intel_sdvo.c
2137
intel_sdvo_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/i915/display/intel_sdvo.c
253
static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
sys/dev/pci/drm/i915/display/intel_sdvo.c
2677
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2795
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2848
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2888
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2920
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
2996
static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)
sys/dev/pci/drm/i915/display/intel_sdvo.c
3010
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
3067
static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
3130
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
3242
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
3258
static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
3369
static bool is_sdvo_port_valid(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_sdvo.c
3377
static bool assert_sdvo_port_valid(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_sdvo.c
3383
bool intel_sdvo_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_sdvo.c
463
static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
sys/dev/pci/drm/i915/display/intel_sdvo.c
465
bool unlocked)
sys/dev/pci/drm/i915/display/intel_sdvo.c
533
static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
sys/dev/pci/drm/i915/display/intel_sdvo.c
539
static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
630
static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
639
static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
sys/dev/pci/drm/i915/display/intel_sdvo.c
647
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
656
static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
sys/dev/pci/drm/i915/display/intel_sdvo.c
670
static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
sys/dev/pci/drm/i915/display/intel_sdvo.c
684
static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
692
static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
700
static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
724
static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
742
static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
750
static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
sys/dev/pci/drm/i915/display/intel_sdvo.c
757
static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
sys/dev/pci/drm/i915/display/intel_sdvo.c
764
static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
771
static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
778
static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
785
static bool
sys/dev/pci/drm/i915/display/intel_sdvo.c
812
static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
823
static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
sys/dev/pci/drm/i915/display/intel_sdvo.c
927
static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
sys/dev/pci/drm/i915/display/intel_sdvo.c
937
static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
943
static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
949
static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
956
static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.c
963
static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
sys/dev/pci/drm/i915/display/intel_sdvo.h
18
bool intel_sdvo_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_sdvo.h
20
bool intel_sdvo_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_sdvo.h
23
static inline bool intel_sdvo_port_enabled(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_sdvo.h
28
static inline bool intel_sdvo_init(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1923
bool frac_en;
sys/dev/pci/drm/i915/display/intel_snps_phy.c
52
bool enable)
sys/dev/pci/drm/i915/display/intel_snps_phy.h
21
bool enable);
sys/dev/pci/drm/i915/display/intel_sprite.c
1232
static bool
sys/dev/pci/drm/i915/display/intel_sprite.c
1239
bool ret;
sys/dev/pci/drm/i915/display/intel_sprite.c
1255
static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
sys/dev/pci/drm/i915/display/intel_sprite.c
1488
static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/intel_sprite.c
1509
static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/intel_sprite.c
1535
static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/intel_sprite.c
458
static bool
sys/dev/pci/drm/i915/display/intel_sprite.c
466
bool ret;
sys/dev/pci/drm/i915/display/intel_sprite.c
653
static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)
sys/dev/pci/drm/i915/display/intel_sprite.c
890
static bool
sys/dev/pci/drm/i915/display/intel_sprite.c
897
bool ret;
sys/dev/pci/drm/i915/display/intel_sprite_uapi.c
11
static bool has_dst_key_in_primary_plane(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_tc.c
1039
static bool
sys/dev/pci/drm/i915/display/intel_tc.c
1051
static bool
sys/dev/pci/drm/i915/display/intel_tc.c
1052
xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled)
sys/dev/pci/drm/i915/display/intel_tc.c
1055
bool is_enabled;
sys/dev/pci/drm/i915/display/intel_tc.c
106
bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1076
static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)
sys/dev/pci/drm/i915/display/intel_tc.c
1100
static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
sys/dev/pci/drm/i915/display/intel_tc.c
111
bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1120
static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
sys/dev/pci/drm/i915/display/intel_tc.c
1147
static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
sys/dev/pci/drm/i915/display/intel_tc.c
116
bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1164
static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1203
static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
sys/dev/pci/drm/i915/display/intel_tc.c
121
bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1285
static bool tc_phy_is_ready(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1290
static bool tc_phy_is_owned(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1301
static bool tc_phy_owned_by_display(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
1302
bool phy_is_ready, bool phy_is_owned)
sys/dev/pci/drm/i915/display/intel_tc.c
1315
static bool tc_phy_is_connected(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
1319
bool phy_is_ready = tc_phy_is_ready(tc);
sys/dev/pci/drm/i915/display/intel_tc.c
1320
bool phy_is_owned = tc_phy_is_owned(tc);
sys/dev/pci/drm/i915/display/intel_tc.c
1321
bool is_connected;
sys/dev/pci/drm/i915/display/intel_tc.c
1339
static bool tc_phy_wait_for_ready(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1342
bool is_ready;
sys/dev/pci/drm/i915/display/intel_tc.c
1421
bool phy_is_ready;
sys/dev/pci/drm/i915/display/intel_tc.c
1422
bool phy_is_owned;
sys/dev/pci/drm/i915/display/intel_tc.c
1485
bool connected;
sys/dev/pci/drm/i915/display/intel_tc.c
1516
int required_lanes, bool force_disconnect)
sys/dev/pci/drm/i915/display/intel_tc.c
1545
static bool intel_tc_port_needs_reset(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1551
int required_lanes, bool force_disconnect)
sys/dev/pci/drm/i915/display/intel_tc.c
1568
static bool tc_port_is_enabled(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1590
bool update_mode = false;
sys/dev/pci/drm/i915/display/intel_tc.c
1635
static bool tc_port_has_active_streams(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
1716
bool intel_tc_port_connected(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/intel_tc.c
1731
static bool __intel_tc_port_link_needs_reset(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
1733
bool ret;
sys/dev/pci/drm/i915/display/intel_tc.c
1746
bool intel_tc_port_link_needs_reset(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
176
bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1836
bool intel_tc_port_link_reset(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1928
bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
sys/dev/pci/drm/i915/display/intel_tc.c
1963
int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
sys/dev/pci/drm/i915/display/intel_tc.c
242
bool enabled;
sys/dev/pci/drm/i915/display/intel_tc.c
40
bool (*is_ready)(struct intel_tc_port *tc);
sys/dev/pci/drm/i915/display/intel_tc.c
41
bool (*is_owned)(struct intel_tc_port *tc);
sys/dev/pci/drm/i915/display/intel_tc.c
429
bool lane_reversal = dig_port->lane_reversal;
sys/dev/pci/drm/i915/display/intel_tc.c
43
bool (*connect)(struct intel_tc_port *tc, int required_lanes);
sys/dev/pci/drm/i915/display/intel_tc.c
492
static void tc_phy_load_fia_params(struct intel_tc_port *tc, bool modular_fia)
sys/dev/pci/drm/i915/display/intel_tc.c
566
static bool icl_tc_phy_is_ready(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
584
static bool icl_tc_phy_take_ownership(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
585
bool take)
sys/dev/pci/drm/i915/display/intel_tc.c
61
bool legacy_port:1;
sys/dev/pci/drm/i915/display/intel_tc.c
610
static bool icl_tc_phy_is_owned(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
656
static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
692
static bool icl_tc_phy_connect(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
74
static bool tc_phy_is_ready(struct intel_tc_port *tc);
sys/dev/pci/drm/i915/display/intel_tc.c
75
static bool tc_phy_wait_for_ready(struct intel_tc_port *tc);
sys/dev/pci/drm/i915/display/intel_tc.c
850
static bool adlp_tc_phy_is_ready(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
869
static bool adlp_tc_phy_take_ownership(struct intel_tc_port *tc,
sys/dev/pci/drm/i915/display/intel_tc.c
870
bool take)
sys/dev/pci/drm/i915/display/intel_tc.c
883
static bool adlp_tc_phy_is_owned(struct intel_tc_port *tc)
sys/dev/pci/drm/i915/display/intel_tc.c
914
static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
sys/dev/pci/drm/i915/display/intel_tc.c
98
static bool intel_tc_port_in_mode(struct intel_digital_port *dig_port,
sys/dev/pci/drm/i915/display/intel_tc.h
106
bool intel_tc_port_ref_held(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
107
bool intel_tc_port_link_needs_reset(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
108
bool intel_tc_port_link_reset(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
111
int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
sys/dev/pci/drm/i915/display/intel_tc.h
114
bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
84
bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
85
bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
86
bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
87
bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port);
sys/dev/pci/drm/i915/display/intel_tc.h
89
bool intel_tc_port_connected(struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_tv.c
1173
static bool intel_tv_source_too_wide(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_tv.c
1179
static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
sys/dev/pci/drm/i915/display/intel_tv.c
1359
bool burst_ena)
sys/dev/pci/drm/i915/display/intel_tv.c
1448
bool burst_ena;
sys/dev/pci/drm/i915/display/intel_tv.c
1710
bool force)
sys/dev/pci/drm/i915/display/intel_tv.c
1766
static bool
sys/dev/pci/drm/i915/display/intel_tv.c
324
bool progressive : 1, trilevel_sync : 1, component_only : 1;
sys/dev/pci/drm/i915/display/intel_tv.c
326
bool veq_ena : 1;
sys/dev/pci/drm/i915/display/intel_tv.c
330
bool burst_ena : 1;
sys/dev/pci/drm/i915/display/intel_tv.c
347
bool pal_burst : 1;
sys/dev/pci/drm/i915/display/intel_tv.c
886
bool bypass_vfilter;
sys/dev/pci/drm/i915/display/intel_tv.c
915
static bool
sys/dev/pci/drm/i915/display/intel_vblank.c
328
static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
sys/dev/pci/drm/i915/display/intel_vblank.c
329
bool in_vblank_irq,
sys/dev/pci/drm/i915/display/intel_vblank.c
340
bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
sys/dev/pci/drm/i915/display/intel_vblank.c
456
bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
sys/dev/pci/drm/i915/display/intel_vblank.c
457
ktime_t *vblank_time, bool in_vblank_irq)
sys/dev/pci/drm/i915/display/intel_vblank.c
481
static bool pipe_scanline_is_moving(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_vblank.c
494
static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
sys/dev/pci/drm/i915/display/intel_vblank.c
498
bool is_moving;
sys/dev/pci/drm/i915/display/intel_vblank.c
524
bool vrr_enable)
sys/dev/pci/drm/i915/display/intel_vblank.c
539
bool vrr_enable)
sys/dev/pci/drm/i915/display/intel_vblank.h
21
bool need_vlv_dsi_wa;
sys/dev/pci/drm/i915/display/intel_vblank.h
38
bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
sys/dev/pci/drm/i915/display/intel_vblank.h
39
ktime_t *vblank_time, bool in_vblank_irq);
sys/dev/pci/drm/i915/display/intel_vblank.h
44
bool vrr_enable);
sys/dev/pci/drm/i915/display/intel_vdsc.c
24
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
263
static bool is_dsi_dsc_1_1(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
38
static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
sys/dev/pci/drm/i915/display/intel_vdsc.c
422
bool pipe_dsc;
sys/dev/pci/drm/i915/display/intel_vdsc.c
860
bool *all_equal)
sys/dev/pci/drm/i915/display/intel_vdsc.c
892
bool all_equal;
sys/dev/pci/drm/i915/display/intel_vdsc.h
19
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vga.c
31
static bool has_vga_pipe_sel(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_vrr.c
182
static bool
sys/dev/pci/drm/i915/display/intel_vrr.c
19
bool intel_vrr_is_capable(struct intel_connector *connector)
sys/dev/pci/drm/i915/display/intel_vrr.c
207
cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
sys/dev/pci/drm/i915/display/intel_vrr.c
353
bool is_edp = intel_dp_is_edp(intel_dp);
sys/dev/pci/drm/i915/display/intel_vrr.c
53
bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
sys/dev/pci/drm/i915/display/intel_vrr.c
572
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
583
bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_vrr.c
62
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
711
bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
723
bool vrr_enable;
sys/dev/pci/drm/i915/display/intel_vrr.h
18
bool intel_vrr_is_capable(struct intel_connector *connector);
sys/dev/pci/drm/i915/display/intel_vrr.h
19
bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
sys/dev/pci/drm/i915/display/intel_vrr.h
20
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
31
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
39
bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
43
bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
sys/dev/pci/drm/i915/display/intel_wm.c
119
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_wm.c
66
bool intel_initial_watermarks(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_wm.h
20
bool intel_initial_watermarks(struct intel_atomic_state *state,
sys/dev/pci/drm/i915/display/intel_wm.h
29
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_wm_types.h
22
bool enable_fbc_wm;
sys/dev/pci/drm/i915/display/intel_wm_types.h
46
bool cxsr;
sys/dev/pci/drm/i915/display/intel_wm_types.h
53
bool cxsr;
sys/dev/pci/drm/i915/display/intel_wm_types.h
54
bool hpll_en;
sys/dev/pci/drm/i915/display/intel_wm_types.h
55
bool fbc_en;
sys/dev/pci/drm/i915/display/intel_wm_types.h
67
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
sys/dev/pci/drm/i915/display/skl_scaler.c
154
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
sys/dev/pci/drm/i915/display/skl_scaler.c
158
u64 modifier, bool need_scaler)
sys/dev/pci/drm/i915/display/skl_scaler.c
303
bool force_detach = !fb || !plane_state->uapi.visible;
sys/dev/pci/drm/i915/display/skl_scaler.c
304
bool need_scaler = false;
sys/dev/pci/drm/i915/display/skl_scaler.c
342
bool is_yuv_semiplanar,
sys/dev/pci/drm/i915/display/skl_scaler.c
58
static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1672
bool async_flip)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1695
static bool intel_format_is_p01x(u32 format)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
171
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1909
static bool
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2228
static bool skl_fb_scalable(const struct drm_framebuffer *fb)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2412
static bool skl_plane_has_fbc(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2435
static bool skl_plane_has_planar(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
246
bool icl_is_nv12_y_plane(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2493
static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2547
static bool icl_plane_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
258
bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2601
static bool tgl_plane_format_mod_supported(struct drm_plane *_plane,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2705
static bool skl_plane_has_rc_ccs(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2725
static bool glk_plane_has_rc_ccs(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2753
static bool tgl_plane_has_mc_ccs(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3178
bool skl_fixup_initial_plane_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
515
static bool tgl_plane_can_async_flip(u64 modifier)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
540
static bool icl_plane_can_async_flip(u64 modifier)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
561
static bool skl_plane_can_async_flip(u64 modifier)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
920
static bool
sys/dev/pci/drm/i915/display/skl_universal_plane.c
928
bool ret;
sys/dev/pci/drm/i915/display/skl_universal_plane.h
27
bool skl_fixup_initial_plane_config(struct intel_crtc *crtc,
sys/dev/pci/drm/i915/display/skl_universal_plane.h
30
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
sys/dev/pci/drm/i915/display/skl_universal_plane.h
38
bool icl_is_nv12_y_plane(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_universal_plane.h
41
bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id);
sys/dev/pci/drm/i915/display/skl_watermark.c
1165
static bool check_mbus_joined(u8 active_pipes,
sys/dev/pci/drm/i915/display/skl_watermark.c
1177
static bool adlp_check_mbus_joined(u8 active_pipes)
sys/dev/pci/drm/i915/display/skl_watermark.c
1182
static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,
sys/dev/pci/drm/i915/display/skl_watermark.c
1200
static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
sys/dev/pci/drm/i915/display/skl_watermark.c
1218
static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
sys/dev/pci/drm/i915/display/skl_watermark.c
1224
static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
sys/dev/pci/drm/i915/display/skl_watermark.c
1230
static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
sys/dev/pci/drm/i915/display/skl_watermark.c
1236
static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus)
sys/dev/pci/drm/i915/display/skl_watermark.c
1256
static bool
sys/dev/pci/drm/i915/display/skl_watermark.c
1360
static bool skl_need_wm_copy_wa(struct intel_display *display, int level,
sys/dev/pci/drm/i915/display/skl_watermark.c
1774
static bool skl_wm_has_lines(struct intel_display *display, int level)
sys/dev/pci/drm/i915/display/skl_watermark.c
1791
static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level)
sys/dev/pci/drm/i915/display/skl_watermark.c
2244
static bool
sys/dev/pci/drm/i915/display/skl_watermark.c
2392
static bool skl_wm_level_equals(const struct skl_wm_level *l1,
sys/dev/pci/drm/i915/display/skl_watermark.c
2402
static bool skl_plane_wm_equals(struct intel_display *display,
sys/dev/pci/drm/i915/display/skl_watermark.c
2423
static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
sys/dev/pci/drm/i915/display/skl_watermark.c
2441
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
sys/dev/pci/drm/i915/display/skl_watermark.c
2619
static char enast(bool enable)
sys/dev/pci/drm/i915/display/skl_watermark.c
2766
static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
sys/dev/pci/drm/i915/display/skl_watermark.c
302
static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
3135
bool skl_watermark_ipc_enabled(struct intel_display *display)
sys/dev/pci/drm/i915/display/skl_watermark.c
3149
static bool skl_watermark_ipc_can_enable(struct intel_display *display)
sys/dev/pci/drm/i915/display/skl_watermark.c
3342
static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
sys/dev/pci/drm/i915/display/skl_watermark.c
3452
int ratio, bool joined_mbus)
sys/dev/pci/drm/i915/display/skl_watermark.c
355
static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
3666
bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state)
sys/dev/pci/drm/i915/display/skl_watermark.c
3711
static bool skl_dbuf_is_misconfigured(struct intel_display *display)
sys/dev/pci/drm/i915/display/skl_watermark.c
374
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
3992
bool enable;
sys/dev/pci/drm/i915/display/skl_watermark.c
45
bool joined_mbus;
sys/dev/pci/drm/i915/display/skl_watermark.c
60
bool x_tiled, y_tiled;
sys/dev/pci/drm/i915/display/skl_watermark.c
61
bool rc_surface;
sys/dev/pci/drm/i915/display/skl_watermark.c
62
bool is_planar;
sys/dev/pci/drm/i915/display/skl_watermark.c
733
bool join_mbus;
sys/dev/pci/drm/i915/display/skl_watermark.c
91
static bool skl_needs_memory_bw_wa(struct intel_display *display)
sys/dev/pci/drm/i915/display/skl_watermark.c
96
bool
sys/dev/pci/drm/i915/display/skl_watermark.h
27
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.h
28
bool intel_has_sagv(struct intel_display *display);
sys/dev/pci/drm/i915/display/skl_watermark.h
33
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
sys/dev/pci/drm/i915/display/skl_watermark.h
46
bool skl_watermark_ipc_enabled(struct intel_display *display);
sys/dev/pci/drm/i915/display/skl_watermark.h
75
int ratio, bool joined_mbus);
sys/dev/pci/drm/i915/display/skl_watermark.h
80
bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
sys/dev/pci/drm/i915/display/vlv_dsi.c
226
static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
sys/dev/pci/drm/i915/display/vlv_dsi.c
328
static bool glk_dsi_enable_io(struct intel_encoder *encoder)
sys/dev/pci/drm/i915/display/vlv_dsi.c
333
bool cold_boot = false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
733
bool glk_cold_boot = false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
934
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/vlv_dsi.c
941
bool active = false;
sys/dev/pci/drm/i915/display/vlv_dsi.c
962
bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
266
static bool has_dsic_clock(struct intel_display *display)
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
271
bool bxt_dsi_pll_is_enabled(struct intel_display *display)
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
273
bool enabled;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
602
static void assert_dsi_pll(struct intel_display *display, bool state)
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
604
bool cur_state;
sys/dev/pci/drm/i915/display/vlv_dsi_pll.h
35
bool bxt_dsi_pll_is_enabled(struct intel_display *display);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.h
39
static inline bool bxt_dsi_pll_is_enabled(struct intel_display *display)
sys/dev/pci/drm/i915/gem/i915_gem_clflush.c
70
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_clflush.h
14
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_context.c
1344
static bool __cancel_engine(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
1381
bool found;
sys/dev/pci/drm/i915/gem/i915_gem_context.c
1402
kill_engines(struct i915_gem_engines *engines, bool exit, bool persistent)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
1582
static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
221
bool persist)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
2319
static bool client_is_banned(struct drm_i915_file_private *file_priv)
sys/dev/pci/drm/i915/gem/i915_gem_context.c
262
bool protected)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
110
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_context.h
162
static inline bool i915_gem_context_has_full_ppgtt(struct i915_gem_context *ctx)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
21
static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
32
static inline bool i915_gem_context_no_error_capture(const struct i915_gem_context *ctx)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
47
static inline bool i915_gem_context_is_bannable(const struct i915_gem_context *ctx)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
62
static inline bool i915_gem_context_is_recoverable(const struct i915_gem_context *ctx)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
77
static inline bool i915_gem_context_is_persistent(const struct i915_gem_context *ctx)
sys/dev/pci/drm/i915/gem/i915_gem_context.h
92
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_context_types.h
212
bool single_timeline;
sys/dev/pci/drm/i915/gem/i915_gem_context_types.h
215
bool uses_protected_content;
sys/dev/pci/drm/i915/gem/i915_gem_context_types.h
361
bool uses_protected_content;
sys/dev/pci/drm/i915/gem/i915_gem_dmabuf.c
122
bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE);
sys/dev/pci/drm/i915/gem/i915_gem_dmabuf.c
20
I915_SELFTEST_DECLARE(static bool force_different_devices;)
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
129
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
19
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
191
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
37
bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_domain.c
493
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1067
static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1383
bool wide = eb->reloc_cache.use_64bit_reloc;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1768
bool have_copy = false;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1892
bool throttle = true;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2499
bool throttle)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2523
bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2525
bool nonblock = eb->file->filp->f_flag & FNONBLOCK;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2553
static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
290
bool use_64bit_reloc : 1;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
291
bool has_llc : 1;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
292
bool has_fence : 1;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
293
bool needs_unfenced : 1;
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
3094
int err, bool last_parallel)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
320
static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle);
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
324
static bool eb_use_cmdparser(const struct i915_execbuffer *eb)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
3566
static bool check_buffer_count(size_t count)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
377
static bool
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
551
static bool
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
695
static bool eb_unbind(struct i915_execbuffer *eb, bool force)
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
700
bool unpinned = false;
sys/dev/pci/drm/i915/gem/i915_gem_lmem.c
42
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_lmem.h
20
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_mman.c
28
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_mman.c
382
bool write = area->vm_flags & VM_WRITE;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
1005
bool i915_gem_object_has_unknown_state(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
214
bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
547
static bool object_has_mappable_iomem(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
59
bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.c
601
bool i915_gem_object_evictable(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
632
bool i915_gem_object_migratable(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
651
bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
670
bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
697
bool i915_gem_object_can_migrate(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.c
832
bool i915_gem_object_placement_possible(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.c
867
bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_object.c
869
bool lmem_placement = false;
sys/dev/pci/drm/i915/gem/i915_gem_object.c
981
bool intr)
sys/dev/pci/drm/i915/gem/i915_gem_object.h
165
bool intr)
sys/dev/pci/drm/i915/gem/i915_gem_object.h
202
static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.h
225
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
231
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
237
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
249
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
25
static inline bool i915_gem_object_size_2big(u64 size)
sys/dev/pci/drm/i915/gem/i915_gem_object.h
267
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
273
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
280
bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
282
bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
284
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
290
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
296
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
302
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
308
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
320
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
37
bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.h
658
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
672
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
69
bool needs_clflush);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
698
struct drm_gem_object *_obj, bool panic_tiling);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
764
bool intr);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
765
bool i915_gem_object_has_unknown_state(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
771
bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
774
bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
777
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
779
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
781
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
815
bool i915_gem_object_is_shmem(const struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
823
bool i915_gem_object_evictable(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
825
bool i915_gem_object_migratable(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
835
bool i915_gem_object_can_migrate(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.h
841
bool i915_gem_object_placement_possible(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_object.h
844
bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
852
bool dirty, bool backup);
sys/dev/pci/drm/i915/gem/i915_gem_object.h
860
bool dirty, bool backup,
sys/dev/pci/drm/i915/gem/i915_gem_object.h
866
static inline bool
sys/dev/pci/drm/i915/gem/i915_gem_object.h
876
static inline bool i915_gem_object_is_userptr(struct drm_i915_gem_object *obj) { return false; }
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
623
bool ttm_shrinkable;
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
641
bool unknown_state;
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
693
bool dirty:1;
sys/dev/pci/drm/i915/gem/i915_gem_object_types.h
702
bool created:1;
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
26
bool shrinkable;
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
451
struct drm_gem_object *_obj, bool panic_tiling)
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
492
bool pinned;
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
651
const bool dma = iter == &obj->mm.get_dma_page ||
sys/dev/pci/drm/i915/gem/i915_gem_pm.c
147
bool flush = false;
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
36
bool dirty, bool backup,
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
421
bool needs_clflush)
sys/dev/pci/drm/i915/gem/i915_gem_shmem.c
864
bool i915_gem_object_is_shmem(const struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
126
bool trylock_vm = !ww && intel_vm_no_concurrent_access_wa(i915);
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
20
static bool swap_available(void)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
25
static bool can_release_pages(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
39
static bool drop_pages(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/gem/i915_gem_shrinker.c
40
unsigned long shrink, bool trylock_vm)
sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
1062
bool i915_gem_object_is_stolen(const struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
1067
bool i915_gem_stolen_initialized(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
1088
bool i915_gem_stolen_node_allocated(const struct drm_mm_node *node)
sys/dev/pci/drm/i915/gem/i915_gem_stolen.c
79
static bool valid_stolen_size(struct drm_i915_private *i915, struct resource *dsm)
sys/dev/pci/drm/i915/gem/i915_gem_stolen.h
37
bool i915_gem_object_is_stolen(const struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_stolen.h
41
bool i915_gem_stolen_initialized(const struct drm_i915_private *i915);
sys/dev/pci/drm/i915/gem/i915_gem_stolen.h
48
bool i915_gem_stolen_node_allocated(const struct drm_mm_node *node);
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
117
static bool
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
160
static bool i915_vma_fence_prepare(struct i915_vma *vma,
sys/dev/pci/drm/i915/gem/i915_gem_tiling.c
221
bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/i915_gem_tiling.h
14
bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
249
bool backup = ttm->page_flags & TTM_TT_FLAG_SWAPPED;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
364
static bool i915_ttm_eviction_valuable(struct ttm_buffer_object *bo,
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
54
bool is_shmem;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
668
bool i915_ttm_resource_mappable(struct ttm_resource *res)
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
681
bool unknown_state;
sys/dev/pci/drm/i915/gem/i915_gem_ttm.c
957
bool shrinkable =
sys/dev/pci/drm/i915/gem/i915_gem_ttm.h
105
bool i915_ttm_resource_mappable(struct ttm_resource *res);
sys/dev/pci/drm/i915/gem/i915_gem_ttm.h
37
static inline bool i915_ttm_is_ghost_object(struct ttm_buffer_object *bo)
sys/dev/pci/drm/i915/gem/i915_gem_ttm.h
88
static inline bool i915_ttm_gtt_binds_lmem(struct ttm_resource *mem)
sys/dev/pci/drm/i915/gem/i915_gem_ttm.h
99
static inline bool i915_ttm_cpu_maps_iomem(struct ttm_resource *mem)
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
188
bool clear,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
272
bool clear;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
303
bool memcpy_allowed;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
313
struct ttm_buffer_object *bo, bool clear,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
34
static bool fail_gpu_migration;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
35
static bool fail_work_allocation;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
356
bool cookie;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
36
static bool ban_memcpy;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
38
void i915_ttm_migrate_set_failure_modes(bool gpu_migration,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
39
bool work_allocation)
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
45
void i915_ttm_migrate_set_ban_memcpy(bool ban)
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
457
static bool i915_ttm_memcpy_allowed(struct ttm_buffer_object *bo,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
472
const struct ttm_operation_ctx *ctx, bool clear,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
474
struct i915_refct_sgt *dst_rsgt, bool allow_accel,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
477
const bool memcpy_allowed = i915_ttm_memcpy_allowed(bo, dst_mem);
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
573
int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
584
bool clear, prealloc_bo;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c
709
bool allow_accel, bool intr)
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.h
23
I915_SELFTEST_DECLARE(void i915_ttm_migrate_set_failure_modes(bool gpu_migration,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.h
24
bool work_allocation));
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.h
25
I915_SELFTEST_DECLARE(void i915_ttm_migrate_set_ban_memcpy(bool ban));
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.h
29
bool allow_accel, bool intr);
sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.h
33
int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.c
38
bool allow_gpu : 1;
sys/dev/pci/drm/i915/gem/i915_gem_ttm_pm.c
39
bool backup_pinned : 1;
sys/dev/pci/drm/i915/gem/i915_gem_userptr.c
58
static bool i915_gem_userptr_invalidate(struct mmu_interval_notifier *mni,
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1317
static inline bool igt_can_allocate_thp(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1843
bool should_swap;
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
328
fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
716
bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
722
bool single = false;
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
860
bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
111
static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
128
static bool fast_blit_ok(const struct blit_buffer *buf)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
147
bool use_64b_reloc = ver >= 8;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
271
__create_vma(struct tiled_blits *t, size_t size, bool lmem)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
291
static struct i915_vma *create_vma(struct tiled_blits *t, bool lmem)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
683
static bool has_bit17_swizzle(int sw)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
689
static bool bad_swizzling(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
252
static bool always_valid(struct context *ctx)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
257
static bool needs_fence_registers(struct context *ctx)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
267
static bool needs_mi_store_dword(struct context *ctx)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
279
bool (*valid)(struct context *ctx);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
479
const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
114
bool silent_migrate)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
17
bool fill)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
187
bool borked_migrate)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
321
bool wedged;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c
476
bool wedged;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1097
bool unfaultable)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1268
bool wedged;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1415
static bool can_access(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1417
bool access;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
1835
bool unuse_mm = false;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
612
static bool assert_mmap_offset(struct drm_i915_private *i915,
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
871
static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
874
bool no_map;
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
265
intel_gmch_gtt_read_entry(unsigned int pg, bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/gen6_ppgtt.c
179
bool flush = false;
sys/dev/pci/drm/i915/gt/gen6_ppgtt.h
23
bool scan_for_unused_pt;
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
15
bool vf_flush_wa = false, dc_flush_wa = false;
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
163
static u32 preparser_disable(bool state)
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
188
static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
163
static bool gen8_pd_contains(u64 start, u64 end, int lvl)
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
88
static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
112
__maybe_unused static bool
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
131
static bool
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
21
static bool irq_enable(struct intel_breadcrumbs *b)
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
217
bool release;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
412
bool i915_request_enable_breadcrumb(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
441
bool release;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
465
bool release = false;
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c
97
static bool remove_signaling_context(struct intel_breadcrumbs *b,
sys/dev/pci/drm/i915/gt/intel_breadcrumbs.h
45
bool i915_request_enable_breadcrumb(struct i915_request *request);
sys/dev/pci/drm/i915/gt/intel_breadcrumbs_types.h
52
bool (*irq_enable)(struct intel_breadcrumbs *b);
sys/dev/pci/drm/i915/gt/intel_context.c
230
bool handoff = false;
sys/dev/pci/drm/i915/gt/intel_context.c
642
bool intel_context_ban(struct intel_context *ce, struct i915_request *rq)
sys/dev/pci/drm/i915/gt/intel_context.c
644
bool ret = intel_context_set_banned(ce);
sys/dev/pci/drm/i915/gt/intel_context.c
655
bool intel_context_revoke(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.c
657
bool ret = intel_context_set_exiting(ce);
sys/dev/pci/drm/i915/gt/intel_context.h
121
static inline bool
sys/dev/pci/drm/i915/gt/intel_context.h
150
static inline bool intel_context_pin_if_active(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
280
static inline bool intel_context_is_barrier(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
293
static inline bool intel_context_is_closed(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
298
static inline bool intel_context_has_inflight(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
303
static inline bool intel_context_use_semaphores(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
318
static inline bool intel_context_is_banned(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
323
static inline bool intel_context_set_banned(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
328
bool intel_context_ban(struct intel_context *ce, struct i915_request *rq);
sys/dev/pci/drm/i915/gt/intel_context.h
330
static inline bool intel_context_is_schedulable(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
336
static inline bool intel_context_is_exiting(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
341
static inline bool intel_context_set_exiting(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
346
bool intel_context_revoke(struct intel_context *ce);
sys/dev/pci/drm/i915/gt/intel_context.h
348
static inline bool
sys/dev/pci/drm/i915/gt/intel_context.h
360
static inline bool
sys/dev/pci/drm/i915/gt/intel_context.h
379
static inline bool intel_context_has_own_state(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
384
static inline bool intel_context_set_own_state(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
389
static inline bool intel_context_has_own_state(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
394
static inline bool intel_context_set_own_state(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
52
static inline bool intel_context_is_child(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
57
static inline bool intel_context_is_parent(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context.h
62
static inline bool intel_context_is_pinned(struct intel_context *ce);
sys/dev/pci/drm/i915/gt/intel_context.h
83
static inline bool intel_context_is_parallel(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_context_types.h
313
bool drop_schedule_enable;
sys/dev/pci/drm/i915/gt/intel_context_types.h
319
bool drop_schedule_disable;
sys/dev/pci/drm/i915/gt/intel_context_types.h
324
bool drop_deregister;
sys/dev/pci/drm/i915/gt/intel_engine.h
240
bool intel_engine_irq_enable(struct intel_engine_cs *engine);
sys/dev/pci/drm/i915/gt/intel_engine.h
244
bool stalled)
sys/dev/pci/drm/i915/gt/intel_engine.h
251
bool intel_engines_are_idle(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_engine.h
252
bool intel_engine_is_idle(struct intel_engine_cs *engine);
sys/dev/pci/drm/i915/gt/intel_engine.h
254
void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);
sys/dev/pci/drm/i915/gt/intel_engine.h
262
bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
sys/dev/pci/drm/i915/gt/intel_engine.h
295
static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine.h
300
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine.h
323
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine.h
337
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1845
static bool ring_is_idle(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1847
bool idle = true;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1870
void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1898
bool intel_engine_is_idle(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1919
bool intel_engines_are_idle(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1943
bool intel_engine_irq_enable(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1981
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2047
bool skip = false;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
728
bool gen11_vdbox_has_sfc(struct intel_gt *gt,
sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c
23
static bool next_heartbeat(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_pm.c
151
static bool switch_to_kernel_context(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_pm.c
155
bool result = true;
sys/dev/pci/drm/i915/gt/intel_engine_pm.h
16
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_pm.h
32
static inline bool intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
330
bool running;
sys/dev/pci/drm/i915/gt/intel_engine_types.h
359
bool mcr;
sys/dev/pci/drm/i915/gt/intel_engine_types.h
434
bool bind_context_ready;
sys/dev/pci/drm/i915/gt/intel_engine_types.h
520
void (*rewind)(struct intel_engine_cs *engine, bool stalled);
sys/dev/pci/drm/i915/gt/intel_engine_types.h
658
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
664
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
670
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
676
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
682
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
688
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
697
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
703
static inline bool
sys/dev/pci/drm/i915/gt/intel_engine_types.h
712
static inline bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1133
static bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1152
static bool needs_timeslice(const struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1187
static bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1263
static bool completed(const struct i915_request *rq)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1280
bool submit = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1494
bool merge = true;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1703
static inline bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1704
__gen12_csb_parse(bool ctx_to_valid, bool ctx_away_valid, bool new_queue,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1728
static bool xehp_csb_parse(const u64 csb)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1736
static bool gen12_csb_parse(const u64 csb)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1744
static bool gen8_csb_parse(const u64 csb)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1880
bool promote;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2097
static bool execlists_hold(struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2126
static bool hold_request(const struct i915_request *rq)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2129
bool result = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2411
static bool preempt_timeout(const struct intel_engine_cs *const engine)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2489
bool tasklet = false;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2560
static bool submit_queue(struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2572
static bool ancestor_on_hold(const struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
301
static bool need_preempt(const struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3027
execlists_reset_active(struct intel_engine_cs *engine, bool stalled)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3104
static void execlists_reset_csb(struct intel_engine_cs *engine, bool stalled)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3120
static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3316
static bool can_preempt(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
353
__maybe_unused static bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3836
bool first;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
467
static bool bad_request(const struct i915_request *rq)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
770
static bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
776
static __maybe_unused noinline bool
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
806
bool ok = true;
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
942
static bool ctx_single_port_submission(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
948
static bool can_merge_ctx(const struct intel_context *prev,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
965
static bool can_merge_rq(const struct i915_request *prev,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
994
static bool virtual_matches(const struct virtual_engine *ve,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.h
39
bool
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1120
bool trylock;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
145
void i915_ggtt_suspend_vm(struct i915_address_space *vm, bool evict_all)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1565
static dma_addr_t gen6_pte_decode(u64 pte, bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1757
bool i915_ggtt_resume_vm(struct i915_address_space *vm, bool all_evicted)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1760
bool write_domain_objs = false;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
1803
bool flush;
sys/dev/pci/drm/i915/gt/intel_ggtt.c
231
static bool needs_wc_ggtt_mapping(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
322
static dma_addr_t gen8_ggtt_pte_decode(u64 pte, bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
330
static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
369
static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
sys/dev/pci/drm/i915/gt/intel_ggtt.c
497
u64 offset, bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
560
static bool __gen8_ggtt_insert_entries_bind(struct i915_address_space *vm,
sys/dev/pci/drm/i915/gt/intel_ggtt.c
663
bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/intel_ggtt.c
837
u64 offset, bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
121
bool is_y_tiled = tiling == I915_TILING_Y;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
195
static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
324
static bool fence_is_active(const struct i915_fence_reg *fence)
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.h
37
bool dirty;
sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c
31
u64 offset, bool *is_present, bool *is_local)
sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c
69
static bool needs_idle_maps(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_gsc.c
95
bool use_polling;
sys/dev/pci/drm/i915/gt/intel_gsc.c
96
bool slow_firmware;
sys/dev/pci/drm/i915/gt/intel_gt.c
1101
bool always_coherent)
sys/dev/pci/drm/i915/gt/intel_gt.c
1115
bool intel_gt_needs_wa_16018031267(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.c
1121
bool intel_gt_needs_wa_22016122933(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.c
1126
static void __intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready)
sys/dev/pci/drm/i915/gt/intel_gt.c
1165
bool intel_gt_is_bind_context_ready(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.h
161
static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.h
167
static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.h
205
bool always_coherent);
sys/dev/pci/drm/i915/gt/intel_gt.h
209
bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_gt.h
85
static inline bool gt_is_root(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.h
90
bool intel_gt_needs_wa_16018031267(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_gt.h
91
bool intel_gt_needs_wa_22016122933(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c
38
static bool pool_free_older_than(struct intel_gt_buffer_pool *pool, long keep)
sys/dev/pci/drm/i915/gt/intel_gt_buffer_pool.c
41
bool active = false;
sys/dev/pci/drm/i915/gt/intel_gt_debugfs.h
42
bool (*eval)(void *data);
sys/dev/pci/drm/i915/gt/intel_gt_irq.c
183
bool gen11_gt_reset_one_iir(struct intel_gt *gt,
sys/dev/pci/drm/i915/gt/intel_gt_irq.h
27
bool gen11_gt_reset_one_iir(struct intel_gt *gt,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
562
static bool reg_needs_read_steering(struct intel_gt *gt,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
745
bool dump_table)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
770
bool dump_table)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
38
bool dump_table);
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
177
static bool reset_engines(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
185
static void gt_sanitize(struct intel_gt *gt, bool force)
sys/dev/pci/drm/i915/gt/intel_gt_pm.c
30
static void user_forcewake(struct intel_gt *gt, bool suspend)
sys/dev/pci/drm/i915/gt/intel_gt_pm.h
110
static inline bool is_mock_gt(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt_pm.h
14
static inline bool intel_gt_pm_is_awake(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
418
const bool edram = GRAPHICS_VER(i915) > 8;
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
457
static bool llc_eval(void *data)
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
538
static bool rps_eval(void *data)
sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c
578
static bool perf_limit_reasons_eval(void *data)
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
17
static bool retire_requests(struct intel_timeline *tl)
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
29
static bool engine_active(const struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
34
static bool flush_submission(struct intel_gt *gt, long timeout)
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
38
bool active = false;
sys/dev/pci/drm/i915/gt/intel_gt_requests.c
88
static bool add_retire(struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/intel_gt_sysfs.c
23
bool is_object_gt(struct kobject *kobj)
sys/dev/pci/drm/i915/gt/intel_gt_sysfs.h
17
bool is_object_gt(struct kobject *kobj);
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
523
bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask);
sys/dev/pci/drm/i915/gt/intel_gt_types.h
182
bool active;
sys/dev/pci/drm/i915/gt/intel_gtt.c
24
bool i915_ggtt_require_binder(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_gtt.c
31
static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_gtt.c
36
bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_gtt.c
481
bool can_use_gtt_cache = true;
sys/dev/pci/drm/i915/gt/intel_gtt.h
183
bool is_compact;
sys/dev/pci/drm/i915/gt/intel_gtt.h
286
bool is_ggtt:1;
sys/dev/pci/drm/i915/gt/intel_gtt.h
289
bool is_dpt:1;
sys/dev/pci/drm/i915/gt/intel_gtt.h
292
bool has_read_only:1;
sys/dev/pci/drm/i915/gt/intel_gtt.h
295
bool skip_pte_rewrite:1;
sys/dev/pci/drm/i915/gt/intel_gtt.h
315
dma_addr_t (*pte_decode)(u64 pte, bool *is_present, bool *is_local);
sys/dev/pci/drm/i915/gt/intel_gtt.h
345
u64 offset, bool *is_present, bool *is_local);
sys/dev/pci/drm/i915/gt/intel_gtt.h
358
I915_SELFTEST_DECLARE(bool scrub_64K);
sys/dev/pci/drm/i915/gt/intel_gtt.h
385
bool do_idle_maps;
sys/dev/pci/drm/i915/gt/intel_gtt.h
424
bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/gt/intel_gtt.h
429
static inline bool
sys/dev/pci/drm/i915/gt/intel_gtt.h
435
static inline bool
sys/dev/pci/drm/i915/gt/intel_gtt.h
460
static inline bool
sys/dev/pci/drm/i915/gt/intel_gtt.h
599
u64 offset, bool *is_present, bool *is_local);
sys/dev/pci/drm/i915/gt/intel_gtt.h
609
static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
sys/dev/pci/drm/i915/gt/intel_gtt.h
619
void i915_ggtt_suspend_vm(struct i915_address_space *vm, bool evict_all);
sys/dev/pci/drm/i915/gt/intel_gtt.h
620
bool i915_ggtt_resume_vm(struct i915_address_space *vm, bool all_evicted);
sys/dev/pci/drm/i915/gt/intel_gtt.h
664
bool
sys/dev/pci/drm/i915/gt/intel_gtt.h
707
bool i915_ggtt_require_binder(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/gt/intel_llc.c
55
static bool get_ia_constants(struct intel_llc *llc,
sys/dev/pci/drm/i915/gt/intel_lrc.c
1000
static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)
sys/dev/pci/drm/i915/gt/intel_lrc.c
1018
bool inhibit = true;
sys/dev/pci/drm/i915/gt/intel_lrc.c
1590
bool valid = true;
sys/dev/pci/drm/i915/gt/intel_lrc.c
50
bool close)
sys/dev/pci/drm/i915/gt/intel_lrc.c
816
static bool ctx_needs_runalone(const struct intel_context *ce)
sys/dev/pci/drm/i915/gt/intel_lrc.c
819
bool ctx_is_protected = false;
sys/dev/pci/drm/i915/gt/intel_lrc.c
842
bool inhibit)
sys/dev/pci/drm/i915/gt/intel_lrc.c
925
bool inhibit)
sys/dev/pci/drm/i915/gt/intel_lrc.c
953
bool inhibit)
sys/dev/pci/drm/i915/gt/intel_lrc.h
60
bool clear);
sys/dev/pci/drm/i915/gt/intel_migrate.c
1083
bool src_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
1086
bool dst_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
1122
bool is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
23
static bool engine_supports_migration(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_migrate.c
365
bool is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
369
bool has_64K_pages = HAS_64K_PAGES(rq->i915);
sys/dev/pci/drm/i915/gt/intel_migrate.c
478
static bool wa_1209644611_applies(int ver, u32 size)
sys/dev/pci/drm/i915/gt/intel_migrate.c
641
calculate_chunk_sz(struct drm_i915_private *i915, bool src_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
682
bool src_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
685
bool dst_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.c
696
bool ccs_is_src, overwrite_ccs;
sys/dev/pci/drm/i915/gt/intel_migrate.c
918
u32 value, bool is_lmem)
sys/dev/pci/drm/i915/gt/intel_migrate.c
988
bool is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.h
29
bool src_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.h
32
bool dst_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.h
39
bool src_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.h
42
bool dst_is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.h
51
bool is_lmem,
sys/dev/pci/drm/i915/gt/intel_migrate.h
59
bool is_lmem,
sys/dev/pci/drm/i915/gt/intel_mocs.c
437
static bool has_l3cc(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_mocs.c
442
static bool has_global_mocs(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_mocs.c
447
static bool has_mocs(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
124
bool
sys/dev/pci/drm/i915/gt/intel_ppgtt.c
130
bool free = false;
sys/dev/pci/drm/i915/gt/intel_rc6.c
411
bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
sys/dev/pci/drm/i915/gt/intel_rc6.c
426
static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
sys/dev/pci/drm/i915/gt/intel_rc6.c
431
bool enable_rc6 = true;
sys/dev/pci/drm/i915/gt/intel_rc6.c
489
static bool rc6_supported(struct intel_rc6 *rc6)
sys/dev/pci/drm/i915/gt/intel_rc6.c
539
static bool pctx_corrupted(struct intel_rc6 *rc6)
sys/dev/pci/drm/i915/gt/intel_rc6.h
30
bool intel_check_bios_c6_setup(struct intel_rc6 *rc6);
sys/dev/pci/drm/i915/gt/intel_rc6_types.h
36
bool supported : 1;
sys/dev/pci/drm/i915/gt/intel_rc6_types.h
37
bool enabled : 1;
sys/dev/pci/drm/i915/gt/intel_rc6_types.h
38
bool manual : 1;
sys/dev/pci/drm/i915/gt/intel_rc6_types.h
39
bool wakeref : 1;
sys/dev/pci/drm/i915/gt/intel_rc6_types.h
40
bool bios_state_captured : 1;
sys/dev/pci/drm/i915/gt/intel_region_lmem.c
207
static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
sys/dev/pci/drm/i915/gt/intel_reset.c
1065
static bool __intel_gt_unset_wedged(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_reset.c
1069
bool ok;
sys/dev/pci/drm/i915/gt/intel_reset.c
1148
bool intel_gt_unset_wedged(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_reset.c
1150
bool result;
sys/dev/pci/drm/i915/gt/intel_reset.c
1189
bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_reset.c
125
void __i915_request_reset(struct i915_request *rq, bool guilty)
sys/dev/pci/drm/i915/gt/intel_reset.c
127
bool banned = false;
sys/dev/pci/drm/i915/gt/intel_reset.c
1438
bool need_display_reset;
sys/dev/pci/drm/i915/gt/intel_reset.c
1439
bool reset_display;
sys/dev/pci/drm/i915/gt/intel_reset.c
147
static bool i915_in_reset(struct pci_dev *pdev)
sys/dev/pci/drm/i915/gt/intel_reset.c
1583
static int _intel_gt_reset_lock(struct intel_gt *gt, int *srcu, bool retry)
sys/dev/pci/drm/i915/gt/intel_reset.c
1722
bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_reset.c
176
static bool g4x_reset_complete(struct pci_dev *pdev)
sys/dev/pci/drm/i915/gt/intel_reset.c
36
static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
sys/dev/pci/drm/i915/gt/intel_reset.c
415
bool lock_obtained, lock_to_other = false;
sys/dev/pci/drm/i915/gt/intel_reset.c
613
const bool reset_non_ready = retry >= 1;
sys/dev/pci/drm/i915/gt/intel_reset.c
63
static bool mark_guilty(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/intel_reset.c
67
bool banned;
sys/dev/pci/drm/i915/gt/intel_reset.c
704
static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
sys/dev/pci/drm/i915/gt/intel_reset.c
716
wa_14015076503_start(struct intel_gt *gt, intel_engine_mask_t engine_mask, bool first)
sys/dev/pci/drm/i915/gt/intel_reset.c
795
bool intel_has_gpu_reset(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_reset.c
803
bool intel_has_reset_engine(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_reset.h
31
bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_reset.h
41
void __i915_request_reset(struct i915_request *rq, bool guilty);
sys/dev/pci/drm/i915/gt/intel_reset.h
48
bool intel_gt_unset_wedged(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_reset.h
81
bool intel_has_gpu_reset(const struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_reset.h
82
bool intel_has_reset_engine(const struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_reset.h
84
bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_ring.h
67
static inline bool
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
177
static bool stop_ring(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
388
static void reset_rewind(struct intel_engine_cs *engine, bool stalled)
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
740
bool force_restore = false;
sys/dev/pci/drm/i915/gt/intel_rps.c
1222
static bool rps_reset(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1240
static bool gen9_rps_enable(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1257
static bool gen8_rps_enable(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1271
static bool gen6_rps_enable(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1346
static bool chv_rps_enable(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1450
static bool vlv_rps_enable(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1534
static bool has_busy_stats(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
1551
bool enabled = false;
sys/dev/pci/drm/i915/gt/intel_rps.c
1828
bool client_boost = false;
sys/dev/pci/drm/i915/gt/intel_rps.c
2119
static u32 __read_cagf(struct intel_rps *rps, bool take_fw)
sys/dev/pci/drm/i915/gt/intel_rps.c
2657
static void intel_rps_set_manual(struct intel_rps *rps, bool enable)
sys/dev/pci/drm/i915/gt/intel_rps.c
2728
bool rps_read_mask_mmio(struct intel_rps *rps,
sys/dev/pci/drm/i915/gt/intel_rps.c
2830
bool i915_gpu_raise(void)
sys/dev/pci/drm/i915/gt/intel_rps.c
2857
bool i915_gpu_lower(void)
sys/dev/pci/drm/i915/gt/intel_rps.c
2883
bool i915_gpu_busy(void)
sys/dev/pci/drm/i915/gt/intel_rps.c
2886
bool ret;
sys/dev/pci/drm/i915/gt/intel_rps.c
2905
bool i915_gpu_turbo_disable(void)
sys/dev/pci/drm/i915/gt/intel_rps.c
2909
bool ret;
sys/dev/pci/drm/i915/gt/intel_rps.c
559
static bool gen5_rps_enable(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
63
static bool rps_uses_slpc(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.c
787
void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive)
sys/dev/pci/drm/i915/gt/intel_rps.c
842
static int rps_set(struct intel_rps *rps, u8 val, bool update)
sys/dev/pci/drm/i915/gt/intel_rps.c
972
bool boost = false;
sys/dev/pci/drm/i915/gt/intel_rps.h
101
static inline bool intel_rps_has_interrupts(const struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.h
116
static inline bool intel_rps_uses_timer(const struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.h
36
void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive);
sys/dev/pci/drm/i915/gt/intel_rps.h
63
bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
sys/dev/pci/drm/i915/gt/intel_rps.h
71
static inline bool intel_rps_is_enabled(const struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.h
86
static inline bool intel_rps_is_active(const struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_rps.h
96
static inline bool intel_rps_clear_active(struct intel_rps *rps)
sys/dev/pci/drm/i915/gt/intel_sseu.c
657
bool subslice_pg = sseu->has_subslice_pg;
sys/dev/pci/drm/i915/gt/intel_sseu.h
121
static inline bool
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
194
bool is_available_info,
sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c
195
bool has_pooled_eu,
sys/dev/pci/drm/i915/gt/intel_timeline.h
58
static inline bool __intel_timeline_sync_is_later(struct intel_timeline *tl,
sys/dev/pci/drm/i915/gt/intel_timeline.h
64
static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl,
sys/dev/pci/drm/i915/gt/intel_timeline.h
95
static inline bool
sys/dev/pci/drm/i915/gt/intel_timeline_types.h
51
bool has_initial_breadcrumb;
sys/dev/pci/drm/i915/gt/intel_tlb.c
113
static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno)
sys/dev/pci/drm/i915/gt/intel_wopcm.c
104
static bool gen9_check_dword_gap(struct drm_i915_private *i915,
sys/dev/pci/drm/i915/gt/intel_wopcm.c
127
static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
sys/dev/pci/drm/i915/gt/intel_wopcm.c
146
static bool check_hw_restrictions(struct drm_i915_private *i915,
sys/dev/pci/drm/i915/gt/intel_wopcm.c
161
static bool __check_layout(struct intel_gt *gt, u32 wopcm_size,
sys/dev/pci/drm/i915/gt/intel_wopcm.c
200
static bool __wopcm_regs_locked(struct intel_uncore *uncore,
sys/dev/pci/drm/i915/gt/intel_wopcm.c
215
static bool __wopcm_regs_writable(struct intel_uncore *uncore)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1741
static bool
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1810
static bool wa_list_verify(struct intel_gt *gt,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1819
bool ok = true;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1840
bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1846
static bool is_nonpriv_flags_valid(u32 flags)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
217
u32 clear, u32 set, u32 read_mask, bool masked_reg)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
231
u32 clear, u32 set, u32 read_mask, bool masked_reg)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
2961
static bool mcr_range(struct drm_i915_private *i915, u32 offset)
sys/dev/pci/drm/i915/gt/intel_workarounds.h
29
bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from);
sys/dev/pci/drm/i915/gt/mock_engine.c
288
static void mock_reset_rewind(struct intel_engine_cs *engine, bool stalled)
sys/dev/pci/drm/i915/gt/selftest_execlists.c
28
static bool is_active(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3841
bool (*filter)(const struct intel_engine_cs *))
sys/dev/pci/drm/i915/gt/selftest_execlists.c
51
bool done = time_after(jiffies, timeout);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
1657
bool using_guc = intel_engine_uses_guc(engine);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
274
static bool wait_until_running(struct hang *h, struct i915_request *rq)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
343
static bool wait_for_idle(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
684
static int __igt_reset_engine(struct intel_gt *gt, bool active)
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
706
bool using_guc = intel_engine_uses_guc(engine);
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
859
bool stop;
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
996
bool using_guc = intel_engine_uses_guc(engine);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1265
static bool is_moving(u32 a, u32 b)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1504
static bool skip_isolation(const struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1592
u32 *cs, bool per_ctx)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1620
wabb_ctx_setup(struct intel_context *ce, bool per_ctx)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1632
static bool check_ring_start(struct intel_context *ce, bool per_ctx)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1648
static int wabb_ctx_check(struct intel_context *ce, bool per_ctx)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1662
static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1718
static int lrc_wabb_ctx(void *arg, bool per_ctx)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
39
static bool is_active(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
617
bool preempt)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
62
bool done = time_after(jiffies, timeout);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
793
static bool timestamp_advanced(u32 start, u32 end)
sys/dev/pci/drm/i915/gt/selftest_lrc.c
798
static int __lrc_timestamp(const struct lrc_timestamp *arg, bool preempt)
sys/dev/pci/drm/i915/gt/selftest_migrate.c
141
bool write_to_ccs,
sys/dev/pci/drm/i915/gt/selftest_migrate.c
227
bool write_to_ccs,
sys/dev/pci/drm/i915/gt/selftest_migrate.c
268
bool ccs_cap = false;
sys/dev/pci/drm/i915/gt/selftest_migrate.c
811
create_init_lmem_internal(struct intel_gt *gt, size_t sz, bool try_lmem)
sys/dev/pci/drm/i915/gt/selftest_migrate.c
846
bool is_lmem,
sys/dev/pci/drm/i915/gt/selftest_migrate.c
922
bool src_is_lmem,
sys/dev/pci/drm/i915/gt/selftest_migrate.c
925
bool dst_is_lmem,
sys/dev/pci/drm/i915/gt/selftest_mocs.c
182
static bool mcr_range(struct drm_i915_private *i915, u32 offset)
sys/dev/pci/drm/i915/gt/selftest_mocs.c
321
bool using_guc)
sys/dev/pci/drm/i915/gt/selftest_mocs.c
352
struct intel_context *ce, bool using_guc)
sys/dev/pci/drm/i915/gt/selftest_mocs.c
404
bool using_guc = intel_engine_uses_guc(engine);
sys/dev/pci/drm/i915/gt/selftest_rc6.c
45
bool has_power;
sys/dev/pci/drm/i915/gt/selftest_rps.c
59
bool srm,
sys/dev/pci/drm/i915/gt/selftest_rps.c
599
static bool scaled_within(u64 x, u64 y, u32 f_n, u32 f_d)
sys/dev/pci/drm/i915/gt/selftest_timeline.c
200
bool expected;
sys/dev/pci/drm/i915/gt/selftest_timeline.c
201
bool set;
sys/dev/pci/drm/i915/gt/selftest_timeline.c
818
static bool cmp_lt(u32 a, u32 b)
sys/dev/pci/drm/i915/gt/selftest_timeline.c
823
static bool cmp_gte(u32 a, u32 b)
sys/dev/pci/drm/i915/gt/selftest_timeline.c
897
bool (*op)(u32 hwsp, u32 seqno))
sys/dev/pci/drm/i915/gt/selftest_timeline.c
943
static bool retire_requests(struct intel_timeline *tl)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1006
static bool result_neq(struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1022
bool (*fn)(struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1165
static bool
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1171
bool ok = true;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1202
bool ok;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1262
bool using_guc = intel_engine_uses_guc(engine);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1263
bool ok;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
418
static bool wo_register(struct intel_engine_cs *engine, u32 reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
436
static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
450
static bool ro_register(u32 reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
527
bool ro_reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
956
static bool find_reg(struct drm_i915_private *i915,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
973
static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
984
static bool result_eq(struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
996
static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/shmem_utils.c
220
bool write)
sys/dev/pci/drm/i915/gt/shmem_utils.c
98
bool write)
sys/dev/pci/drm/i915/gt/sysfs_engines.c
85
unsigned long caps, char *buf, bool show_unknown)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
159
bool is_valid;
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
46
bool is_partial;
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
17
static bool gsc_is_in_reset(struct intel_uncore *uncore)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
237
bool too_old = false;
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
25
static u32 gsc_uc_get_fw_status(struct intel_uncore *uncore, bool needs_wakeref)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
40
bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc, bool needs_wakeref)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
62
bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.h
17
bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.h
18
bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc, bool needs_wakeref);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c
98
static bool gsc_engine_supported(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h
52
bool component_added;
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h
69
static inline bool intel_gsc_uc_is_supported(struct intel_gsc_uc *gsc)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h
74
static inline bool intel_gsc_uc_is_wanted(struct intel_gsc_uc *gsc)
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.h
79
static inline bool intel_gsc_uc_is_used(struct intel_gsc_uc *gsc)
sys/dev/pci/drm/i915/gt/uc/intel_guc.c
126
static bool __gen11_reset_guc_interrupts(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
177
bool submission_supported;
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
179
bool submission_selected;
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
181
bool submission_initialized;
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
188
bool rc_supported;
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
190
bool rc_selected;
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
318
bool busy;
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
361
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
365
bool not_atomic = !in_atomic() && !irqs_disabled();
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
447
static inline bool intel_guc_is_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
452
static inline bool intel_guc_is_wanted(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
457
static inline bool intel_guc_is_used(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
463
static inline bool intel_guc_is_fw_running(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
468
static inline bool intel_guc_is_ready(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
548
bool intel_guc_tlb_invalidation_is_available(struct intel_guc *guc);
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
96
bool enabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
722
bool ads_is_mapped;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1107
bool is_partial = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1301
bool new_overflow;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1532
bool intel_guc_capture_is_matching_engine(struct intel_gt *gt,
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
300
bool has_xehpg_extregs;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
474
size_t *size, bool is_purpose_est)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
804
static bool
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.h
24
bool intel_guc_capture_is_matching_engine(struct intel_gt *gt, struct intel_context *ce,
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1004
static bool ct_check_lost_and_found(struct intel_guc_ct *ct, u32 fence)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1008
bool found = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1034
static bool ct_check_lost_and_found(struct intel_guc_ct *ct, u32 fence)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1049
bool found = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1173
static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1177
bool done;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
1206
bool done;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
206
static int ct_control_enable(struct intel_guc_ct *ct, bool enable)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
219
static int ct_register_buffer(struct intel_guc_ct *ct, bool send,
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
543
bool ct_enabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
570
static inline bool ct_deadlocked(struct intel_guc_ct *ct)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
573
bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
598
static inline bool g2h_has_room(struct intel_guc_ct *ct, u32 g2h_len_dw)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
624
static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
652
bool h2g = h2g_has_room(ct, h2g_dw);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
653
bool g2h = g2h_has_room(ct, g2h_dw);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c
723
bool send_again;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h
102
bool dead_ct_reported;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h
120
static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h
54
bool broken;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.h
64
bool enabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c
69
static bool intel_eval_slpc_support(void *data)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
107
static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool *success)
sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c
169
bool success;
sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c
98
static bool has_table(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
204
static int guc_action_control_log(struct intel_guc *guc, bool enable,
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
205
bool default_logging, u32 verbosity)
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
330
bool intel_guc_check_log_buf_overflow(struct intel_guc_log *log,
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
335
bool overflow = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
394
bool new_overflow;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
727
bool intel_guc_log_relay_created(const struct intel_guc_log *log)
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.c
905
bool dump_load_err)
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h
109
bool dump_load_err);
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h
60
bool sizes_initialised;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h
68
bool buf_in_use;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h
69
bool started;
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h
85
bool intel_guc_check_log_buf_overflow(struct intel_guc_log *log, enum guc_log_buffer_type type,
sys/dev/pci/drm/i915/gt/uc/intel_guc_log.h
94
bool intel_guc_log_relay_created(const struct intel_guc_log *log);
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c
13
static bool __guc_rc_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c
20
static bool __guc_rc_selected(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c
34
static int guc_action_control_gucrc(struct intel_guc *guc, bool enable)
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.c
50
static int __guc_rc_control(struct intel_guc *guc, bool enable)
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.h
13
static inline bool intel_guc_rc_is_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.h
18
static inline bool intel_guc_rc_is_wanted(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_rc.h
23
static inline bool intel_guc_rc_is_used(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
172
static bool slpc_is_running(struct intel_guc_slpc *slpc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
482
int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
64
static bool __detect_slpc_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
686
static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c
71
static bool __guc_slpc_selected(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
17
static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
22
static inline bool intel_guc_slpc_is_wanted(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
27
static inline bool intel_guc_slpc_is_used(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.h
47
int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h
19
bool supported;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h
20
bool selected;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h
23
bool min_is_rpmax;
sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc_types.h
34
bool ignore_eff_freq;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1052
bool loop;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1081
bool pending_disable, pending_enable, deregister, destroyed, banned;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1090
bool do_put = kref_get_unless_zero(&ce->ref);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1330
bool in_reset;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1670
static inline bool
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1777
static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1817
static void guc_rewind_nop(struct intel_engine_cs *engine, bool stalled)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1859
bool guilty;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
198
static bool sched_state_is_init(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
203
static inline bool
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2097
bool intel_guc_tlb_invalidation_is_available(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2238
static bool need_tasklet(struct intel_guc *guc, struct i915_request *rq)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
226
static inline bool
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
246
static inline bool context_pending_disable(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2461
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2484
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2527
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2541
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2567
register_context_v69(struct intel_guc *guc, struct intel_context *ce, bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2583
register_context_v70(struct intel_guc *guc, struct intel_context *ce, bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2595
static int register_context(struct intel_context *ce, bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
263
static inline bool context_banned(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2707
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2714
static int guc_context_policy_init_v70(struct intel_context *ce, bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
280
static inline bool context_enabled(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2926
static int try_context_registration(struct intel_context *ce, bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2933
bool context_registered;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2952
bool disabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
297
static inline bool context_pending_enable(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3128
bool enabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
314
static inline bool context_registered(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3167
static bool context_cant_unblock(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3183
bool enable;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
331
static inline bool context_policy_required(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3326
static bool bypass_sched_disable(struct intel_guc *guc,
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3358
static bool guc_id_pressure(struct intel_guc *guc, struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3414
bool disabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3455
bool pending_destroyed;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
348
static inline bool context_close_done(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3585
bool destroy;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3716
static inline bool new_guc_prio_higher(u8 old_guc_prio, u8 new_guc_prio)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
3851
static bool context_needs_register(struct intel_context *ce, bool new_guc_id)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
389
static inline bool context_guc_id_invalid(struct intel_context *ce)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4277
static bool
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4282
bool result = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4442
static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4767
static void guc_route_semaphores(struct intel_guc *guc, bool to_guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4820
static bool __guc_submission_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4827
static bool __guc_submission_selected(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
4956
static bool intel_gt_is_enabled(const struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5144
bool banned;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5196
bool match = intel_guc_capture_is_matching_engine(gt, ce, e);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5232
bool capture = intel_context_is_schedulable(ce);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5404
bool found;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
561
static inline bool guc_submission_initialized(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
574
static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5773
static inline bool skip_handshake(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
6002
bool intel_guc_virtual_engine_has_heartbeat(const struct intel_engine_cs *ve)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
621
bool loop)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
644
bool interruptible,
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
693
static int guc_context_policy_init_v70(struct intel_context *ce, bool loop);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
694
static int try_context_registration(struct intel_context *ce, bool loop);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
703
bool enabled;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
802
static bool is_multi_lrc_rq(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
807
static bool can_merge_rq(struct i915_request *rq,
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
911
static bool multi_lrc_submit(struct i915_request *rq)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
931
bool submit = false;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h
34
bool intel_guc_virtual_engine_has_heartbeat(const struct intel_engine_cs *ve);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h
38
bool interruptible,
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h
43
static inline bool intel_guc_submission_is_supported(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h
48
static inline bool intel_guc_submission_is_wanted(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h
53
static inline bool intel_guc_submission_is_used(struct intel_guc *guc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
270
static bool vcs_supported(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
344
bool gsc_enabled = huc->fw.has_gsc_headers;
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
447
bool partial = huc->fw.has_gsc_headers && type == INTEL_HUC_AUTH_BY_GUC;
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
590
bool intel_huc_is_authenticated(struct intel_huc *huc,
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
603
static bool huc_is_fully_authenticated(struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
659
static bool huc_has_delayed_load(struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
53
bool loaded_via_gsc;
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
64
bool intel_huc_is_authenticated(struct intel_huc *huc,
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
72
static inline bool intel_huc_is_supported(struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
77
static inline bool intel_huc_is_wanted(struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
82
static inline bool intel_huc_is_used(struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
88
static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
93
static inline bool intel_huc_wait_required(struct intel_huc *huc)
sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c
109
static bool css_valid(const void *data, size_t size)
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
416
static bool uc_is_wopcm_locked(struct intel_uc *uc)
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
460
bool pl1en = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc.c
709
static int __uc_resume(struct intel_uc *uc, bool enable_communication)
sys/dev/pci/drm/i915/gt/uc/intel_uc.h
39
bool reset_in_progress;
sys/dev/pci/drm/i915/gt/uc/intel_uc.h
40
bool fw_table_invalid;
sys/dev/pci/drm/i915/gt/uc/intel_uc.h
79
static inline bool intel_uc_##state##_##func(struct intel_uc *uc) \
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1187
static inline bool uc_fw_need_rsa_in_memory(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1409
bool got_wanted;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
204
bool legacy;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
208
bool has_gsc_headers;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
291
bool found;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
344
static bool validate_fw_table_type(struct drm_i915_private *i915, enum intel_uc_fw_type type)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
512
bool needs_ggtt_mapping)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
548
bool user = e == -EINVAL;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
735
static bool is_ver_8bit(struct intel_uc_fw_ver *ver)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
819
bool new_huc, new_guc;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
847
int intel_uc_check_file_version(struct intel_uc_fw *uc_fw, bool *old_ver)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
902
bool old_ver = false;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
107
bool needs_ggtt_mapping;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
124
bool has_gsc_headers;
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
231
static inline bool intel_uc_fw_is_supported(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
236
static inline bool intel_uc_fw_is_enabled(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
241
static inline bool intel_uc_fw_is_available(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
246
static inline bool intel_uc_fw_is_loadable(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
251
static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
256
static inline bool intel_uc_fw_is_running(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
261
static inline bool intel_uc_fw_is_in_error(struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
266
static inline bool intel_uc_fw_is_overridden(const struct intel_uc_fw *uc_fw)
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
300
int intel_uc_check_file_version(struct intel_uc_fw *uc_fw, bool *old_ver);
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
303
bool needs_ggtt_mapping);
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.h
98
bool user_overridden;
sys/dev/pci/drm/i915/gt/uc/selftest_guc.c
318
bool spinning = false;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
42
static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
sys/dev/pci/drm/i915/gvt/cfg_space.c
133
static void map_aperture(struct intel_vgpu *vgpu, bool map)
sys/dev/pci/drm/i915/gvt/cfg_space.c
139
static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
sys/dev/pci/drm/i915/gvt/cfg_space.c
185
bool lo = IS_ALIGNED(offset, 8);
sys/dev/pci/drm/i915/gvt/cfg_space.c
187
bool mmio_enabled =
sys/dev/pci/drm/i915/gvt/cfg_space.c
320
bool primary)
sys/dev/pci/drm/i915/gvt/cfg_space.c
386
bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1093
unsigned long guest_gma, int op_size, bool index_mode);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1186
bool index_mode = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1278
bool async_flip;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1518
static bool is_wait_for_flip_pending(u32 cmd)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1562
unsigned long guest_gma, int op_size, bool index_mode)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1718
bool index_mode = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1821
bool bb_end = false;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
2001
bool second_level;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
2783
static inline bool gma_out_of_range(unsigned long gma,
sys/dev/pci/drm/i915/gvt/cmd_parser.c
513
bool is_ctx_wa;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
514
bool is_init_ctx;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
728
static inline bool is_init_ctx(struct parser_exec_state *s)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
847
static inline bool is_mocs_mmio(unsigned int offset)
sys/dev/pci/drm/i915/gvt/display.c
605
void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
sys/dev/pci/drm/i915/gvt/display.c
686
void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
sys/dev/pci/drm/i915/gvt/display.h
161
void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
sys/dev/pci/drm/i915/gvt/display.h
84
bool data_valid;
sys/dev/pci/drm/i915/gvt/dmabuf.c
246
static bool validate_hotspot(struct intel_vgpu_cursor_plane_format *c)
sys/dev/pci/drm/i915/gvt/dmabuf.h
59
bool initref;
sys/dev/pci/drm/i915/gvt/edid.h
108
bool i2c_over_aux_ch;
sys/dev/pci/drm/i915/gvt/edid.h
109
bool aux_ch_mot;
sys/dev/pci/drm/i915/gvt/edid.h
125
bool target_selected;
sys/dev/pci/drm/i915/gvt/edid.h
126
bool edid_available;
sys/dev/pci/drm/i915/gvt/edid.h
46
bool data_valid;
sys/dev/pci/drm/i915/gvt/execlist.c
126
bool trigger_interrupt_later)
sys/dev/pci/drm/i915/gvt/execlist.c
400
bool lite_restore = false;
sys/dev/pci/drm/i915/gvt/execlist.c
433
bool emulate_schedule_in)
sys/dev/pci/drm/i915/gvt/fb_decoder.c
121
static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
sys/dev/pci/drm/i915/gvt/gtt.c
1011
bool ips = false;
sys/dev/pci/drm/i915/gvt/gtt.c
1570
static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
sys/dev/pci/drm/i915/gvt/gtt.c
1977
struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
sys/dev/pci/drm/i915/gvt/gtt.c
2156
bool partial_update = false;
sys/dev/pci/drm/i915/gvt/gtt.c
2176
bool found = false;
sys/dev/pci/drm/i915/gvt/gtt.c
239
unsigned long index, bool hypervisor_access, unsigned long gpa,
sys/dev/pci/drm/i915/gvt/gtt.c
264
unsigned long index, bool hypervisor_access, unsigned long gpa,
sys/dev/pci/drm/i915/gvt/gtt.c
2722
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
sys/dev/pci/drm/i915/gvt/gtt.c
333
static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
sys/dev/pci/drm/i915/gvt/gtt.c
356
static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
sys/dev/pci/drm/i915/gvt/gtt.c
372
static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
sys/dev/pci/drm/i915/gvt/gtt.c
396
static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
sys/dev/pci/drm/i915/gvt/gtt.c
464
struct intel_gvt_gtt_entry *entry, bool ips)
sys/dev/pci/drm/i915/gvt/gtt.c
488
bool guest)
sys/dev/pci/drm/i915/gvt/gtt.c
50
static bool enable_out_of_sync = false;
sys/dev/pci/drm/i915/gvt/gtt.c
515
bool guest)
sys/dev/pci/drm/i915/gvt/gtt.c
57
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
sys/dev/pci/drm/i915/gvt/gtt.c
589
bool guest)
sys/dev/pci/drm/i915/gvt/gtt.c
618
bool guest)
sys/dev/pci/drm/i915/gvt/gtt.c
811
unsigned long gfn, bool guest_pde_ips)
sys/dev/pci/drm/i915/gvt/gtt.c
988
static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
sys/dev/pci/drm/i915/gvt/gtt.h
166
bool shadowed;
sys/dev/pci/drm/i915/gvt/gtt.h
220
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
sys/dev/pci/drm/i915/gvt/gtt.h
247
bool pde_ips; /* for 64KB PTEs */
sys/dev/pci/drm/i915/gvt/gtt.h
255
bool pde_ips; /* for 64KB PTEs */
sys/dev/pci/drm/i915/gvt/gtt.h
61
bool hypervisor_access,
sys/dev/pci/drm/i915/gvt/gtt.h
67
bool hypervisor_access,
sys/dev/pci/drm/i915/gvt/gtt.h
70
bool (*test_present)(struct intel_gvt_gtt_entry *e);
sys/dev/pci/drm/i915/gvt/gtt.h
73
bool (*test_pse)(struct intel_gvt_gtt_entry *e);
sys/dev/pci/drm/i915/gvt/gtt.h
75
bool (*test_ips)(struct intel_gvt_gtt_entry *e);
sys/dev/pci/drm/i915/gvt/gtt.h
77
bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
sys/dev/pci/drm/i915/gvt/gvt.h
103
bool tracked;
sys/dev/pci/drm/i915/gvt/gvt.h
115
bool irq_warn_once[INTEL_GVT_EVENT_MAX];
sys/dev/pci/drm/i915/gvt/gvt.h
166
bool active;
sys/dev/pci/drm/i915/gvt/gvt.h
169
bool valid;
sys/dev/pci/drm/i915/gvt/gvt.h
188
bool pv_notified;
sys/dev/pci/drm/i915/gvt/gvt.h
189
bool failsafe;
sys/dev/pci/drm/i915/gvt/gvt.h
211
bool d3_entered;
sys/dev/pci/drm/i915/gvt/gvt.h
297
bool firmware_loaded;
sys/dev/pci/drm/i915/gvt/gvt.h
364
bool is_reg_whitelist_updated;
sys/dev/pci/drm/i915/gvt/gvt.h
473
u32 offset, u32 val, bool low)
sys/dev/pci/drm/i915/gvt/gvt.h
501
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
sys/dev/pci/drm/i915/gvt/gvt.h
535
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
sys/dev/pci/drm/i915/gvt/gvt.h
538
bool primary);
sys/dev/pci/drm/i915/gvt/gvt.h
547
void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
sys/dev/pci/drm/i915/gvt/gvt.h
604
static inline bool intel_gvt_mmio_is_cmd_accessible(
sys/dev/pci/drm/i915/gvt/gvt.h
629
static inline bool intel_gvt_mmio_is_unalign(
sys/dev/pci/drm/i915/gvt/gvt.h
644
static inline bool intel_gvt_mmio_has_mode_mask(
sys/dev/pci/drm/i915/gvt/gvt.h
660
static inline bool intel_gvt_mmio_is_sr_in_ctx(
sys/dev/pci/drm/i915/gvt/gvt.h
704
static inline bool intel_gvt_mmio_is_cmd_write_patch(
sys/dev/pci/drm/i915/gvt/handlers.c
1118
unsigned int reg, int len, bool data_valid)
sys/dev/pci/drm/i915/gvt/handlers.c
1364
bool vga_disable;
sys/dev/pci/drm/i915/gvt/handlers.c
1461
bool invalid_read = false;
sys/dev/pci/drm/i915/gvt/handlers.c
1538
bool invalid_write = false;
sys/dev/pci/drm/i915/gvt/handlers.c
2041
bool enable_execlist;
sys/dev/pci/drm/i915/gvt/handlers.c
3139
void *pdata, unsigned int bytes, bool is_read)
sys/dev/pci/drm/i915/gvt/handlers.c
767
static inline bool in_whitelist(u32 reg)
sys/dev/pci/drm/i915/gvt/handlers.c
94
static bool intel_gvt_match_device(struct intel_gvt *gvt,
sys/dev/pci/drm/i915/gvt/interrupt.c
46
bool has_upstream_irq;
sys/dev/pci/drm/i915/gvt/kvmgt.c
365
static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn)
sys/dev/pci/drm/i915/gvt/kvmgt.c
400
size_t count, loff_t *ppos, bool iswrite)
sys/dev/pci/drm/i915/gvt/kvmgt.c
428
static bool edid_valid(const void *edid, size_t size)
sys/dev/pci/drm/i915/gvt/kvmgt.c
431
bool is_valid;
sys/dev/pci/drm/i915/gvt/kvmgt.c
442
size_t count, u16 offset, bool is_write)
sys/dev/pci/drm/i915/gvt/kvmgt.c
494
size_t count, u16 offset, bool is_write)
sys/dev/pci/drm/i915/gvt/kvmgt.c
508
size_t count, loff_t *ppos, bool iswrite)
sys/dev/pci/drm/i915/gvt/kvmgt.c
641
static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu)
sys/dev/pci/drm/i915/gvt/kvmgt.c
645
bool ret = false;
sys/dev/pci/drm/i915/gvt/kvmgt.c
72
size_t count, loff_t *ppos, bool iswrite);
sys/dev/pci/drm/i915/gvt/kvmgt.c
752
void *buf, unsigned int count, bool is_write)
sys/dev/pci/drm/i915/gvt/kvmgt.c
766
static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off)
sys/dev/pci/drm/i915/gvt/kvmgt.c
773
void *buf, unsigned long count, bool is_write)
sys/dev/pci/drm/i915/gvt/kvmgt.c
800
size_t count, loff_t *ppos, bool is_write)
sys/dev/pci/drm/i915/gvt/kvmgt.c
847
static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos)
sys/dev/pci/drm/i915/gvt/mmio.c
247
void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
sys/dev/pci/drm/i915/gvt/mmio.c
68
void *p_data, unsigned int bytes, bool read)
sys/dev/pci/drm/i915/gvt/mmio.h
100
void *pdata, unsigned int bytes, bool is_read);
sys/dev/pci/drm/i915/gvt/mmio.h
84
void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
sys/dev/pci/drm/i915/gvt/mmio_context.c
163
bool initialized;
sys/dev/pci/drm/i915/gvt/mmio_context.c
472
bool is_inhibit_context(struct intel_context *ce)
sys/dev/pci/drm/i915/gvt/mmio_context.c
54
bool in_context;
sys/dev/pci/drm/i915/gvt/mmio_context.h
55
bool is_inhibit_context(struct intel_context *ce);
sys/dev/pci/drm/i915/gvt/opregion.c
388
static bool querying_capabilities(u32 scic)
sys/dev/pci/drm/i915/gvt/page_track.h
40
bool tracked;
sys/dev/pci/drm/i915/gvt/sched_policy.c
37
static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
sys/dev/pci/drm/i915/gvt/sched_policy.c
56
bool active;
sys/dev/pci/drm/i915/gvt/sched_policy.c
57
bool pri_sched;
sys/dev/pci/drm/i915/gvt/scheduler.c
1154
const bool need_force_wake = GRAPHICS_VER(engine->i915) >= 9;
sys/dev/pci/drm/i915/gvt/scheduler.c
140
bool skip = false;
sys/dev/pci/drm/i915/gvt/scheduler.c
262
static inline bool is_gvt_request(struct i915_request *rq)
sys/dev/pci/drm/i915/gvt/scheduler.c
85
u32 *reg_state, bool save)
sys/dev/pci/drm/i915/gvt/scheduler.c
919
static __maybe_unused bool
sys/dev/pci/drm/i915/gvt/scheduler.h
110
bool emulate_schedule_in;
sys/dev/pci/drm/i915/gvt/scheduler.h
131
bool ppgtt;
sys/dev/pci/drm/i915/gvt/scheduler.h
48
bool need_reschedule;
sys/dev/pci/drm/i915/gvt/scheduler.h
90
bool dispatched;
sys/dev/pci/drm/i915/gvt/scheduler.h
91
bool shadow; /* if workload has done shadow of guest request */
sys/dev/pci/drm/i915/gvt/trace.h
277
unsigned int old_val, bool changed),
sys/dev/pci/drm/i915/gvt/trace.h
287
__field(bool, changed)
sys/dev/pci/drm/i915/gvt/vgpu.c
435
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
sys/dev/pci/drm/i915/i915_active.c
213
static inline bool
sys/dev/pci/drm/i915/i915_active.c
376
static bool ____active_del_barrier(struct i915_active *ref,
sys/dev/pci/drm/i915/i915_active.c
418
static bool
sys/dev/pci/drm/i915/i915_active.c
424
static bool
sys/dev/pci/drm/i915/i915_active.c
43
static inline bool is_barrier(const struct i915_active_fence *active)
sys/dev/pci/drm/i915/i915_active.c
500
bool i915_active_acquire_if_busy(struct i915_active *ref)
sys/dev/pci/drm/i915/i915_active.c
766
static inline bool is_idle_barrier(struct active_node *node, u64 idx)
sys/dev/pci/drm/i915/i915_active.h
120
static inline bool
sys/dev/pci/drm/i915/i915_active.h
189
bool i915_active_acquire_if_busy(struct i915_active *ref);
sys/dev/pci/drm/i915/i915_active.h
199
static inline bool
sys/dev/pci/drm/i915/i915_cmd_parser.c
1160
bool *needs_clflush_after)
sys/dev/pci/drm/i915/i915_cmd_parser.c
1241
static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,
sys/dev/pci/drm/i915/i915_cmd_parser.c
1247
static bool check_cmd(const struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/i915_cmd_parser.c
1450
bool trampoline)
sys/dev/pci/drm/i915/i915_cmd_parser.c
1455
bool needs_clflush_after = false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1597
bool active = false;
sys/dev/pci/drm/i915/i915_cmd_parser.c
802
static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/i915_cmd_parser.c
807
bool ret = true;
sys/dev/pci/drm/i915/i915_cmd_parser.c
838
static bool check_sorted(const struct intel_engine_cs *engine,
sys/dev/pci/drm/i915/i915_cmd_parser.c
844
bool ret = true;
sys/dev/pci/drm/i915/i915_cmd_parser.c
864
static bool validate_regs_sorted(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/i915_cmd_parser.h
23
bool trampoline);
sys/dev/pci/drm/i915/i915_debugfs_params.c
119
bool b;
sys/dev/pci/drm/i915/i915_debugfs_params.c
241
bool *: debugfs_create_bool, \
sys/dev/pci/drm/i915/i915_debugfs_params.c
64
bool b;
sys/dev/pci/drm/i915/i915_driver.c
1043
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/i915_driver.c
1124
static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
sys/dev/pci/drm/i915/i915_driver.c
1132
bool s2idle = !hibernation && suspend_to_idle(dev_priv);
sys/dev/pci/drm/i915/i915_driver.c
178
bool pre = false;
sys/dev/pci/drm/i915/i915_drv.h
177
bool active;
sys/dev/pci/drm/i915/i915_drv.h
206
bool do_release;
sys/dev/pci/drm/i915/i915_drv.h
268
bool mchbar_need_disable;
sys/dev/pci/drm/i915/i915_drv.h
289
bool irqs_enabled;
sys/dev/pci/drm/i915/i915_drv.h
307
bool preserve_bios_swizzle;
sys/dev/pci/drm/i915/i915_drv.h
487
static __always_inline bool
sys/dev/pci/drm/i915/i915_drv.h
501
static __always_inline bool
sys/dev/pci/drm/i915/i915_gem.c
118
bool vm_trylock = !!(flags & I915_GEM_OBJECT_UNBIND_VM_TRYLOCK);
sys/dev/pci/drm/i915/i915_gem.c
207
bool needs_clflush)
sys/dev/pci/drm/i915/i915_gem.c
277
static inline bool
sys/dev/pci/drm/i915/i915_gem.c
303
bool write)
sys/dev/pci/drm/i915/i915_gem.c
512
static inline bool
sys/dev/pci/drm/i915/i915_gem.c
643
bool needs_clflush_before,
sys/dev/pci/drm/i915/i915_gem.c
644
bool needs_clflush_after)
sys/dev/pci/drm/i915/i915_gem_evict.c
112
static bool defer_evict(struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_gem_evict.c
38
bool fail_if_busy:1;
sys/dev/pci/drm/i915/i915_gem_evict.c
41
static bool dying_vma(struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_gem_evict.c
67
static bool grab_vma(struct i915_vma *vma, struct i915_gem_ww_ctx *ww)
sys/dev/pci/drm/i915/i915_gem_evict.c
95
static bool
sys/dev/pci/drm/i915/i915_gem_ww.c
9
void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr)
sys/dev/pci/drm/i915/i915_gem_ww.h
14
bool intr;
sys/dev/pci/drm/i915/i915_gem_ww.h
17
void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
sys/dev/pci/drm/i915/i915_gpu_error.c
1507
static bool record_context(struct i915_gem_context_coredump *e,
sys/dev/pci/drm/i915/i915_gpu_error.c
1512
bool simulated;
sys/dev/pci/drm/i915/i915_gpu_error.c
1551
bool lockdep_cookie;
sys/dev/pci/drm/i915/i915_gpu_error.c
1631
bool lockdep_cookie;
sys/dev/pci/drm/i915/i915_gpu_error.c
278
static bool compress_init(struct i915_vma_compress *c)
sys/dev/pci/drm/i915/i915_gpu_error.c
300
static bool compress_start(struct i915_vma_compress *c)
sys/dev/pci/drm/i915/i915_gpu_error.c
329
bool wc)
sys/dev/pci/drm/i915/i915_gpu_error.c
413
static bool compress_init(struct i915_vma_compress *c)
sys/dev/pci/drm/i915/i915_gpu_error.c
418
static bool compress_start(struct i915_vma_compress *c)
sys/dev/pci/drm/i915/i915_gpu_error.c
426
bool wc)
sys/dev/pci/drm/i915/i915_gpu_error.c
78
static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
sys/dev/pci/drm/i915/i915_gpu_error.c
980
bool print_guc_capture = false;
sys/dev/pci/drm/i915/i915_gpu_error.h
141
bool awake;
sys/dev/pci/drm/i915/i915_gpu_error.h
142
bool simulated;
sys/dev/pci/drm/i915/i915_gpu_error.h
183
bool is_guc_capture;
sys/dev/pci/drm/i915/i915_gpu_error.h
202
bool simulated;
sys/dev/pci/drm/i915/i915_gpu_error.h
203
bool wakelock;
sys/dev/pci/drm/i915/i915_gpu_error.h
204
bool suspended;
sys/dev/pci/drm/i915/i915_gpu_error.h
62
bool hung;
sys/dev/pci/drm/i915/i915_gpu_error.h
63
bool simulated;
sys/dev/pci/drm/i915/i915_hwmon.c
544
void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old)
sys/dev/pci/drm/i915/i915_hwmon.c
562
void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old)
sys/dev/pci/drm/i915/i915_hwmon.c
63
bool reset_in_progress;
sys/dev/pci/drm/i915/i915_hwmon.h
18
void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old);
sys/dev/pci/drm/i915/i915_hwmon.h
19
void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old);
sys/dev/pci/drm/i915/i915_hwmon.h
23
static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { };
sys/dev/pci/drm/i915/i915_hwmon.h
24
static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { };
sys/dev/pci/drm/i915/i915_irq.c
1301
bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/i915_irq.h
39
bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
sys/dev/pci/drm/i915/i915_memcpy.c
121
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len)
sys/dev/pci/drm/i915/i915_memcpy.c
43
static bool has_movntdqa = false;
sys/dev/pci/drm/i915/i915_memcpy.h
15
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
sys/dev/pci/drm/i915/i915_mitigations.c
104
bool enable;
sys/dev/pci/drm/i915/i915_mitigations.c
25
bool i915_mitigate_clear_residuals(void)
sys/dev/pci/drm/i915/i915_mitigations.c
36
bool first = true;
sys/dev/pci/drm/i915/i915_mitigations.c
46
bool enable = true;
sys/dev/pci/drm/i915/i915_mitigations.h
11
bool i915_mitigate_clear_residuals(void);
sys/dev/pci/drm/i915/i915_module.c
24
bool use_kms = true;
sys/dev/pci/drm/i915/i915_params.c
119
i915_param_named(enable_gvt, bool, 0400,
sys/dev/pci/drm/i915/i915_params.c
134
i915_param_named(enable_debug_only_api, bool, 0400,
sys/dev/pci/drm/i915/i915_params.c
139
bool val)
sys/dev/pci/drm/i915/i915_params.c
170
bool: _param_print_bool, \
sys/dev/pci/drm/i915/i915_params.c
73
i915_param_named(error_capture, bool, 0400,
sys/dev/pci/drm/i915/i915_params.c
79
i915_param_named_unsafe(enable_hangcheck, bool, 0400,
sys/dev/pci/drm/i915/i915_params.c
88
i915_param_named(memtest, bool, 0400,
sys/dev/pci/drm/i915/i915_params.h
55
param(bool, memtest, false, 0400) \
sys/dev/pci/drm/i915/i915_params.h
64
param(bool, enable_hangcheck, true, 0600) \
sys/dev/pci/drm/i915/i915_params.h
65
param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
sys/dev/pci/drm/i915/i915_params.h
66
param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \
sys/dev/pci/drm/i915/i915_params.h
67
param(bool, enable_debug_only_api, false, IS_ENABLED(CONFIG_DRM_I915_REPLAY_GPU_HANGS_API) ? 0400 : 0)
sys/dev/pci/drm/i915/i915_pci.c
890
static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
sys/dev/pci/drm/i915/i915_pci.c
893
bool ret;
sys/dev/pci/drm/i915/i915_pci.c
928
static bool id_forced(u16 device_id)
sys/dev/pci/drm/i915/i915_pci.c
933
static bool id_blocked(u16 device_id)
sys/dev/pci/drm/i915/i915_pci.c
938
bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
sys/dev/pci/drm/i915/i915_pci.c
952
static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
sys/dev/pci/drm/i915/i915_pci.h
16
bool i915_pci_resource_valid(struct pci_dev *pdev, int bar);
sys/dev/pci/drm/i915/i915_perf.c
1456
static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
sys/dev/pci/drm/i915/i915_perf.c
1460
bool found = false;
sys/dev/pci/drm/i915/i915_perf.c
1522
static bool engine_supports_mi_query(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/i915_perf.c
1668
static bool engine_supports_oa(const struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/i915_perf.c
1673
static bool engine_supports_oa_format(struct intel_engine_cs *engine, int type)
sys/dev/pci/drm/i915/i915_perf.c
1934
bool save, i915_reg_t reg, u32 offset,
sys/dev/pci/drm/i915/i915_perf.c
2882
bool periodic = stream->periodic;
sys/dev/pci/drm/i915/i915_perf.c
2997
bool periodic = stream->periodic;
sys/dev/pci/drm/i915/i915_perf.c
375
bool oa_periodic;
sys/dev/pci/drm/i915/i915_perf.c
380
bool has_sseu;
sys/dev/pci/drm/i915/i915_perf.c
3840
bool privileged_op = true;
sys/dev/pci/drm/i915/i915_perf.c
3979
static __always_inline bool
sys/dev/pci/drm/i915/i915_perf.c
4014
bool config_instance = false;
sys/dev/pci/drm/i915/i915_perf.c
4015
bool config_class = false;
sys/dev/pci/drm/i915/i915_perf.c
4016
bool config_sseu = false;
sys/dev/pci/drm/i915/i915_perf.c
4346
static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4366
static bool reg_in_range_table(u32 addr, const struct i915_range *table)
sys/dev/pci/drm/i915/i915_perf.c
4465
static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4470
static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4476
static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4483
static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4489
static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4495
static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4500
static bool mtl_is_valid_oam_b_counter_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4509
static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4516
static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
sys/dev/pci/drm/i915/i915_perf.c
4548
bool (*is_valid)(struct i915_perf *perf, u32 addr),
sys/dev/pci/drm/i915/i915_perf.c
489
static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report)
sys/dev/pci/drm/i915/i915_perf.c
550
static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
sys/dev/pci/drm/i915/i915_perf.c
556
bool pollin;
sys/dev/pci/drm/i915/i915_perf_types.h
215
bool enabled;
sys/dev/pci/drm/i915/i915_perf_types.h
223
bool hold_preemption;
sys/dev/pci/drm/i915/i915_perf_types.h
273
bool pollin;
sys/dev/pci/drm/i915/i915_perf_types.h
278
bool periodic;
sys/dev/pci/drm/i915/i915_perf_types.h
355
bool (*is_valid_b_counter_reg)(struct i915_perf *perf, u32 addr);
sys/dev/pci/drm/i915/i915_perf_types.h
361
bool (*is_valid_mux_reg)(struct i915_perf *perf, u32 addr);
sys/dev/pci/drm/i915/i915_perf_types.h
367
bool (*is_valid_flex_reg)(struct i915_perf *perf, u32 addr);
sys/dev/pci/drm/i915/i915_pmu.c
127
static bool is_engine_event(struct perf_event *event)
sys/dev/pci/drm/i915/i915_pmu.c
149
static bool pmu_needs_timer(struct i915_pmu *pmu)
sys/dev/pci/drm/i915/i915_pmu.c
346
static bool exclusive_mmio_access(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/i915_pmu.c
359
bool busy;
sys/dev/pci/drm/i915/i915_pmu.c
449
static bool
sys/dev/pci/drm/i915/i915_pmu.c
61
static bool is_engine_config(const u64 config)
sys/dev/pci/drm/i915/i915_pmu.c
986
bool global;
sys/dev/pci/drm/i915/i915_pmu.h
114
bool timer_enabled;
sys/dev/pci/drm/i915/i915_pmu.h
66
bool registered;
sys/dev/pci/drm/i915/i915_query.c
227
bool use_uuid)
sys/dev/pci/drm/i915/i915_request.c
1277
static bool
sys/dev/pci/drm/i915/i915_request.c
1332
static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
sys/dev/pci/drm/i915/i915_request.c
1467
static inline bool is_parallel_rq(struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.c
1477
static bool is_same_parallel_context(struct i915_request *to,
sys/dev/pci/drm/i915/i915_request.c
1688
bool write)
sys/dev/pci/drm/i915/i915_request.c
1765
bool uses_guc = intel_engine_uses_guc(rq->engine);
sys/dev/pci/drm/i915/i915_request.c
1766
bool pow2 = is_power_of_2(READ_ONCE(prev->engine)->mask |
sys/dev/pci/drm/i915/i915_request.c
1768
bool same_context = prev->context == rq->context;
sys/dev/pci/drm/i915/i915_request.c
1975
static bool busywait_stop(unsigned long timeout, unsigned int cpu)
sys/dev/pci/drm/i915/i915_request.c
1985
static bool __i915_spin_request(struct i915_request * const rq, int state)
sys/dev/pci/drm/i915/i915_request.c
206
__notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk))
sys/dev/pci/drm/i915/i915_request.c
224
static bool irq_work_imm(struct irq_work *wrk)
sys/dev/pci/drm/i915/i915_request.c
2329
static bool engine_match_ring(struct intel_engine_cs *engine, struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.c
2336
static bool match_ring(struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.c
2339
bool found;
sys/dev/pci/drm/i915/i915_request.c
262
bool
sys/dev/pci/drm/i915/i915_request.c
267
bool ret = false;
sys/dev/pci/drm/i915/i915_request.c
403
bool i915_request_retire(struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.c
485
static bool __request_in_flight(const struct i915_request *signal)
sys/dev/pci/drm/i915/i915_request.c
488
bool inflight = false;
sys/dev/pci/drm/i915/i915_request.c
592
static bool fatal_error(int error)
sys/dev/pci/drm/i915/i915_request.c
622
bool i915_request_set_error_once(struct i915_request *rq, int error)
sys/dev/pci/drm/i915/i915_request.c
656
bool __i915_request_submit(struct i915_request *request)
sys/dev/pci/drm/i915/i915_request.c
659
bool result = false;
sys/dev/pci/drm/i915/i915_request.c
88
static bool i915_fence_signaled(struct dma_fence *fence)
sys/dev/pci/drm/i915/i915_request.c
93
static bool i915_fence_enable_signaling(struct dma_fence *fence)
sys/dev/pci/drm/i915/i915_request.c
99
bool interruptible,
sys/dev/pci/drm/i915/i915_request.h
367
static inline bool dma_fence_is_i915(const struct dma_fence *fence)
sys/dev/pci/drm/i915/i915_request.h
384
bool i915_request_set_error_once(struct i915_request *rq, int error);
sys/dev/pci/drm/i915/i915_request.h
392
bool i915_request_retire(struct i915_request *rq);
sys/dev/pci/drm/i915/i915_request.h
424
bool write);
sys/dev/pci/drm/i915/i915_request.h
433
bool __i915_request_submit(struct i915_request *request);
sys/dev/pci/drm/i915/i915_request.h
459
static inline bool i915_request_signaled(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
465
static inline bool i915_request_is_active(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
470
static inline bool i915_request_in_priority_queue(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
475
static inline bool
sys/dev/pci/drm/i915/i915_request.h
484
static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
sys/dev/pci/drm/i915/i915_request.h
520
static inline bool __i915_request_has_started(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
551
static inline bool i915_request_started(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
553
bool result;
sys/dev/pci/drm/i915/i915_request.h
576
static inline bool i915_request_is_running(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
578
bool result;
sys/dev/pci/drm/i915/i915_request.h
606
static inline bool i915_request_is_ready(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
611
static inline bool __i915_request_is_complete(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
616
static inline bool i915_request_completed(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
618
bool result;
sys/dev/pci/drm/i915/i915_request.h
638
static inline bool i915_request_has_waitboost(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
643
static inline bool i915_request_has_nopreempt(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
649
static inline bool i915_request_has_sentinel(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
654
static inline bool i915_request_on_hold(const struct i915_request *rq)
sys/dev/pci/drm/i915/i915_request.h
718
bool
sys/dev/pci/drm/i915/i915_scatterlist.c
15
bool i915_sg_trim(struct sg_table *orig_st)
sys/dev/pci/drm/i915/i915_scatterlist.h
170
bool i915_sg_trim(struct sg_table *orig_st);
sys/dev/pci/drm/i915/i915_scatterlist.h
31
} __sgt_iter(struct scatterlist *sgl, bool dma) {
sys/dev/pci/drm/i915/i915_scheduler.c
24
static inline bool node_started(const struct i915_sched_node *node)
sys/dev/pci/drm/i915/i915_scheduler.c
29
static inline bool node_signaled(const struct i915_sched_node *node)
sys/dev/pci/drm/i915/i915_scheduler.c
344
bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
sys/dev/pci/drm/i915/i915_scheduler.c
349
bool ret = false;
sys/dev/pci/drm/i915/i915_scheduler.c
462
static bool default_disabled(struct i915_sched_engine *sched_engine)
sys/dev/pci/drm/i915/i915_scheduler.c
64
bool first = true;
sys/dev/pci/drm/i915/i915_scheduler.h
100
static inline bool
sys/dev/pci/drm/i915/i915_scheduler.h
28
bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
sys/dev/pci/drm/i915/i915_scheduler.h
68
static inline bool
sys/dev/pci/drm/i915/i915_scheduler_types.h
159
bool no_priolist;
sys/dev/pci/drm/i915/i915_scheduler_types.h
174
bool (*disabled)(struct i915_sched_engine *sched_engine);
sys/dev/pci/drm/i915/i915_selftest.h
135
bool __igt_timeout(unsigned long timeout, const char *fmt, ...);
sys/dev/pci/drm/i915/i915_sw_fence.c
222
bool i915_sw_fence_await(struct i915_sw_fence *fence)
sys/dev/pci/drm/i915/i915_sw_fence.c
282
static bool __i915_sw_fence_check_if_after(struct i915_sw_fence *fence,
sys/dev/pci/drm/i915/i915_sw_fence.c
319
static bool i915_sw_fence_check_if_after(struct i915_sw_fence *fence,
sys/dev/pci/drm/i915/i915_sw_fence.c
323
bool err;
sys/dev/pci/drm/i915/i915_sw_fence.c
333
static bool i915_sw_fence_check_if_after(struct i915_sw_fence *fence,
sys/dev/pci/drm/i915/i915_sw_fence.c
585
bool write,
sys/dev/pci/drm/i915/i915_sw_fence.h
101
static inline bool i915_sw_fence_signaled(const struct i915_sw_fence *fence)
sys/dev/pci/drm/i915/i915_sw_fence.h
106
static inline bool i915_sw_fence_done(const struct i915_sw_fence *fence)
sys/dev/pci/drm/i915/i915_sw_fence.h
94
bool write,
sys/dev/pci/drm/i915/i915_sw_fence.h
98
bool i915_sw_fence_await(struct i915_sw_fence *fence);
sys/dev/pci/drm/i915/i915_switcheroo.c
47
static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
sys/dev/pci/drm/i915/i915_syncmap.c
132
static inline bool seqno_later(u32 a, u32 b)
sys/dev/pci/drm/i915/i915_syncmap.c
151
bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno)
sys/dev/pci/drm/i915/i915_syncmap.h
35
bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno);
sys/dev/pci/drm/i915/i915_tasklet.h
17
static inline bool tasklet_is_locked(const struct tasklet_struct *t)
sys/dev/pci/drm/i915/i915_tasklet.h
28
static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
sys/dev/pci/drm/i915/i915_tasklet.h
33
static inline bool __tasklet_enable(struct tasklet_struct *t)
sys/dev/pci/drm/i915/i915_tasklet.h
38
static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
sys/dev/pci/drm/i915/i915_timer_util.h
13
static inline bool timer_active(const struct timeout *t)
sys/dev/pci/drm/i915/i915_timer_util.h
22
static inline bool timer_expired(const struct timeout *t)
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c
152
static bool i915_ttm_buddy_man_intersects(struct ttm_resource_manager *man,
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c
190
static bool i915_ttm_buddy_man_compatible(struct ttm_resource_manager *man,
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c
284
unsigned int type, bool use_tt,
sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h
53
unsigned type, bool use_tt,
sys/dev/pci/drm/i915/i915_utils.c
45
bool i915_error_injected(void)
sys/dev/pci/drm/i915/i915_utils.c
52
bool i915_vtd_active(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/i915_utils.c
64
bool i915_direct_stolen_access(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/i915_utils.h
152
static inline bool i915_run_as_guest(void)
sys/dev/pci/drm/i915/i915_utils.h
162
bool i915_vtd_active(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/i915_utils.h
164
bool i915_direct_stolen_access(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/i915_utils.h
50
bool i915_error_injected(void);
sys/dev/pci/drm/i915/i915_utils.h
98
static inline bool is_power_of_2_u64(u64 n)
sys/dev/pci/drm/i915/i915_vgpu.c
119
bool intel_vgpu_active(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/i915_vgpu.c
124
bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/i915_vgpu.c
129
bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/i915_vgpu.c
134
bool intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/i915_vgpu.h
33
bool intel_vgpu_active(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/i915_vgpu.h
35
bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/i915_vgpu.h
36
bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/i915_vgpu.h
37
bool intel_vgpu_has_huge_gtt(struct drm_i915_private *i915);
sys/dev/pci/drm/i915/i915_vma.c
1801
bool vm_ddestroy)
sys/dev/pci/drm/i915/i915_vma.c
1864
bool vm_ddestroy;
sys/dev/pci/drm/i915/i915_vma.c
2063
struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
sys/dev/pci/drm/i915/i915_vma.c
2247
int i915_vma_unbind_async(struct i915_vma *vma, bool trylock_vm)
sys/dev/pci/drm/i915/i915_vma.c
697
bool i915_vma_misplaced(const struct i915_vma *vma,
sys/dev/pci/drm/i915/i915_vma.c
733
bool mappable, fenceable;
sys/dev/pci/drm/i915/i915_vma.c
750
bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
sys/dev/pci/drm/i915/i915_vma.c
950
static bool try_qad_pin(struct i915_vma *vma, unsigned int flags)
sys/dev/pci/drm/i915/i915_vma.h
106
static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
111
static inline bool i915_vma_set_userfault(struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
122
static inline bool i915_vma_has_userfault(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
127
static inline bool i915_vma_is_closed(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
262
bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color);
sys/dev/pci/drm/i915/i915_vma.h
263
bool i915_vma_misplaced(const struct i915_vma *vma,
sys/dev/pci/drm/i915/i915_vma.h
268
struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
sys/dev/pci/drm/i915/i915_vma.h
271
int __must_check i915_vma_unbind_async(struct i915_vma *vma, bool trylock_vm);
sys/dev/pci/drm/i915/i915_vma.h
307
static inline bool i915_vma_is_pinned(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
330
static inline bool i915_vma_is_bound(const struct i915_vma *vma,
sys/dev/pci/drm/i915/i915_vma.h
336
static inline bool i915_node_color_differs(const struct drm_mm_node *node,
sys/dev/pci/drm/i915/i915_vma.h
418
static inline bool i915_vma_is_scanout(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
51
static inline bool i915_vma_is_active(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
77
static inline bool i915_vma_is_ggtt(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
82
static inline bool i915_vma_is_dpt(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
87
static inline bool i915_vma_has_ggtt_write(const struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma.h
98
static inline bool i915_vma_unset_ggtt_write(struct i915_vma *vma)
sys/dev/pci/drm/i915/i915_vma_resource.c
206
bool lockdep_cookie)
sys/dev/pci/drm/i915/i915_vma_resource.c
232
bool i915_vma_resource_hold(struct i915_vma_resource *vma_res,
sys/dev/pci/drm/i915/i915_vma_resource.c
233
bool *lockdep_cookie)
sys/dev/pci/drm/i915/i915_vma_resource.c
235
bool held = refcount_inc_not_zero(&vma_res->hold_count);
sys/dev/pci/drm/i915/i915_vma_resource.c
248
bool lockdep_cookie;
sys/dev/pci/drm/i915/i915_vma_resource.c
368
bool intr)
sys/dev/pci/drm/i915/i915_vma_resource.c
453
bool intr,
sys/dev/pci/drm/i915/i915_vma_resource.h
133
bool allocated:1;
sys/dev/pci/drm/i915/i915_vma_resource.h
134
bool immediate_unbind:1;
sys/dev/pci/drm/i915/i915_vma_resource.h
135
bool needs_wakeref:1;
sys/dev/pci/drm/i915/i915_vma_resource.h
136
bool skip_pte_rewrite:1;
sys/dev/pci/drm/i915/i915_vma_resource.h
141
bool i915_vma_resource_hold(struct i915_vma_resource *vma_res,
sys/dev/pci/drm/i915/i915_vma_resource.h
142
bool *lockdep_cookie);
sys/dev/pci/drm/i915/i915_vma_resource.h
145
bool lockdep_cookie);
sys/dev/pci/drm/i915/i915_vma_resource.h
206
bool readonly,
sys/dev/pci/drm/i915/i915_vma_resource.h
207
bool lmem,
sys/dev/pci/drm/i915/i915_vma_resource.h
246
bool intr);
sys/dev/pci/drm/i915/i915_vma_resource.h
252
bool intr,
sys/dev/pci/drm/i915/i915_vma_resource.h
53
bool readonly:1;
sys/dev/pci/drm/i915/i915_vma_resource.h
54
bool lmem:1;
sys/dev/pci/drm/i915/i915_vma_types.h
232
bool vm_ddestroy;
sys/dev/pci/drm/i915/i915_wait_util.h
27
const bool expired__ = ktime_after(ktime_get_raw(), end__); \
sys/dev/pci/drm/i915/intel_cpu_info.c
36
bool intel_match_g8_cpu(void)
sys/dev/pci/drm/i915/intel_cpu_info.c
42
bool intel_match_g8_cpu(void) { return false; }
sys/dev/pci/drm/i915/intel_cpu_info.h
11
bool intel_match_g8_cpu(void);
sys/dev/pci/drm/i915/intel_device_info.c
219
static bool find_devid(u16 id, const u16 *p, unsigned int num)
sys/dev/pci/drm/i915/intel_device_info.h
221
bool has_pooled_eu;
sys/dev/pci/drm/i915/intel_device_info.h
251
bool has_logical_contexts:1;
sys/dev/pci/drm/i915/intel_gvt.c
52
static bool is_supported_device(struct drm_i915_private *dev_priv)
sys/dev/pci/drm/i915/intel_memory_region.c
103
bool test_all,
sys/dev/pci/drm/i915/intel_memory_region.c
178
bool intel_memory_type_is_local(enum intel_memory_type mem_type)
sys/dev/pci/drm/i915/intel_memory_region.h
76
bool private; /* not for userspace */
sys/dev/pci/drm/i915/intel_memory_region.h
83
bool is_range_manager;
sys/dev/pci/drm/i915/intel_memory_region.h
88
bool intel_memory_type_is_local(enum intel_memory_type mem_type);
sys/dev/pci/drm/i915/intel_pcode.c
131
static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
sys/dev/pci/drm/i915/intel_pcode.c
59
bool is_read)
sys/dev/pci/drm/i915/intel_runtime_pm.c
141
intel_runtime_pm_acquire(struct intel_runtime_pm *rpm, bool wakelock)
sys/dev/pci/drm/i915/intel_runtime_pm.c
166
bool wakelock)
sys/dev/pci/drm/i915/intel_runtime_pm.c
242
bool ignore_usecount)
sys/dev/pci/drm/i915/intel_runtime_pm.c
300
bool wakelock)
sys/dev/pci/drm/i915/intel_runtime_pm.h
44
bool available;
sys/dev/pci/drm/i915/intel_runtime_pm.h
45
bool no_wakeref_tracking;
sys/dev/pci/drm/i915/intel_runtime_pm.h
99
static inline bool
sys/dev/pci/drm/i915/intel_uncore.c
1202
static bool is_shadowed(struct intel_uncore *uncore, u32 offset)
sys/dev/pci/drm/i915/intel_uncore.c
1798
const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1812
const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1821
static inline bool __must_check
sys/dev/pci/drm/i915/intel_uncore.c
1823
const i915_reg_t reg, const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1839
const i915_reg_t reg, const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1850
vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1870
gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1878
gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1903
bool unclaimed_reg_debug; \
sys/dev/pci/drm/i915/intel_uncore.c
1945
fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
sys/dev/pci/drm/i915/intel_uncore.c
1978
gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1986
gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2009
bool unclaimed_reg_debug; \
sys/dev/pci/drm/i915/intel_uncore.c
2022
gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2035
fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2061
vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
222
bool ack_detected;
sys/dev/pci/drm/i915/intel_uncore.c
2856
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
sys/dev/pci/drm/i915/intel_uncore.c
2858
bool ret;
sys/dev/pci/drm/i915/intel_uncore.c
2870
bool
sys/dev/pci/drm/i915/intel_uncore.c
2873
bool ret = false;
sys/dev/pci/drm/i915/intel_uncore.c
551
static bool
sys/dev/pci/drm/i915/intel_uncore.c
581
static bool
sys/dev/pci/drm/i915/intel_uncore.c
595
static bool
sys/dev/pci/drm/i915/intel_uncore.c
610
static bool
sys/dev/pci/drm/i915/intel_uncore.c
613
bool ret = false;
sys/dev/pci/drm/i915/intel_uncore.c
797
bool delayed)
sys/dev/pci/drm/i915/intel_uncore.c
81
static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
sys/dev/pci/drm/i915/intel_uncore.h
103
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
105
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
107
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
109
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
112
i915_reg_t r, u8 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
114
i915_reg_t r, u16 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
116
i915_reg_t r, u32 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
184
bool active;
sys/dev/pci/drm/i915/intel_uncore.h
203
static inline bool
sys/dev/pci/drm/i915/intel_uncore.h
209
static inline bool
sys/dev/pci/drm/i915/intel_uncore.h
215
static inline bool
sys/dev/pci/drm/i915/intel_uncore.h
221
static inline bool
sys/dev/pci/drm/i915/intel_uncore.h
227
static inline bool
sys/dev/pci/drm/i915/intel_uncore.h
233
static inline bool
sys/dev/pci/drm/i915/intel_uncore.h
246
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
sys/dev/pci/drm/i915/intel_uncore.h
247
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
sys/dev/pci/drm/i915/intel_wakeref.h
125
static inline bool
sys/dev/pci/drm/i915/intel_wakeref.h
238
static inline bool
sys/dev/pci/drm/i915/pxp/intel_pxp.c
200
bool is_full_feature = false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
283
static bool pxp_component_bound(struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
285
bool bound = false;
sys/dev/pci/drm/i915/pxp/intel_pxp.c
372
static bool pxp_required_fw_failed(struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
383
static bool pxp_fw_dependencies_completed(struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
463
int intel_pxp_key_check(struct drm_gem_object *_obj, bool assign)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
50
bool intel_pxp_is_supported(const struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
55
bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
60
bool intel_pxp_is_active(const struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp.c
65
static void kcr_pxp_set_status(const struct intel_pxp *pxp, bool enable)
sys/dev/pci/drm/i915/pxp/intel_pxp.h
16
bool intel_pxp_is_supported(const struct intel_pxp *pxp);
sys/dev/pci/drm/i915/pxp/intel_pxp.h
17
bool intel_pxp_is_enabled(const struct intel_pxp *pxp);
sys/dev/pci/drm/i915/pxp/intel_pxp.h
18
bool intel_pxp_is_active(const struct intel_pxp *pxp);
sys/dev/pci/drm/i915/pxp/intel_pxp.h
34
int intel_pxp_key_check(struct drm_gem_object *obj, bool assign);
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
191
bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c
20
static bool
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
26
bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp);
sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.h
38
static inline bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp)
sys/dev/pci/drm/i915/pxp/intel_pxp_pm.c
37
static void _pxp_resume(struct intel_pxp *pxp, bool take_wakeref)
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
121
void intel_pxp_terminate(struct intel_pxp *pxp, bool post_invalidation_needs_restart)
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
18
static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
sys/dev/pci/drm/i915/pxp/intel_pxp_session.c
31
static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)
sys/dev/pci/drm/i915/pxp/intel_pxp_session.h
15
void intel_pxp_terminate(struct intel_pxp *pxp, bool post_invalidation_needs_restart);
sys/dev/pci/drm/i915/pxp/intel_pxp_session.h
21
static inline void intel_pxp_terminate(struct intel_pxp *pxp, bool post_invalidation_needs_restart)
sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c
26
static bool
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
110
bool hw_state_invalidated;
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
113
bool irq_enabled;
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
36
bool platform_cfg_is_bad;
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
73
bool pxp_component_added;
sys/dev/pci/drm/i915/pxp/intel_pxp_types.h
86
bool arb_is_valid;
sys/dev/pci/drm/i915/selftests/i915_active.c
21
bool retired;
sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c
1089
bool is_stolen = mr->type == INTEL_MEMORY_STOLEN_SYSTEM ||
sys/dev/pci/drm/i915/selftests/i915_request.c
1530
static bool wake_all(struct drm_i915_private *i915)
sys/dev/pci/drm/i915/selftests/i915_request.c
2558
bool seen;
sys/dev/pci/drm/i915/selftests/i915_request.c
2971
bool busy;
sys/dev/pci/drm/i915/selftests/i915_request.c
3046
bool busy;
sys/dev/pci/drm/i915/selftests/i915_request.c
305
bool stop;
sys/dev/pci/drm/i915/selftests/i915_request.c
3123
bool busy;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
102
module_param_named(id, mock_selftests[mock_##n].enabled, bool, 0400);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
109
module_param_named(id, live_selftests[live_##n].enabled, bool, 0400);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
116
module_param_named(id, perf_selftests[perf_##n].enabled, bool, 0400);
sys/dev/pci/drm/i915/selftests/i915_selftest.c
134
static bool
sys/dev/pci/drm/i915/selftests/i915_selftest.c
143
bool need_to_wait = (IS_ENABLED(CONFIG_INTEL_MEI_GSC_PROXY) &&
sys/dev/pci/drm/i915/selftests/i915_selftest.c
164
bool need_to_wait = (IS_ENABLED(CONFIG_INTEL_MEI_PXP) &&
sys/dev/pci/drm/i915/selftests/i915_selftest.c
321
static bool apply_subtest_filter(const char *caller, const char *name)
sys/dev/pci/drm/i915/selftests/i915_selftest.c
324
bool result = true;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
328
bool allow = true;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
458
bool __igt_timeout(unsigned long timeout, const char *fmt, ...)
sys/dev/pci/drm/i915/selftests/i915_selftest.c
481
bool skip = false;
sys/dev/pci/drm/i915/selftests/i915_selftest.c
72
bool enabled;
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
576
bool expect;
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
88
static bool
sys/dev/pci/drm/i915/selftests/i915_vma.c
222
bool (*assert)(const struct i915_vma *,
sys/dev/pci/drm/i915/selftests/i915_vma.c
228
static bool assert_pin_valid(const struct i915_vma *vma,
sys/dev/pci/drm/i915/selftests/i915_vma.c
242
static bool assert_pin_enospc(const struct i915_vma *vma,
sys/dev/pci/drm/i915/selftests/i915_vma.c
250
static bool assert_pin_einval(const struct i915_vma *vma,
sys/dev/pci/drm/i915/selftests/i915_vma.c
37
static bool assert_vma(struct i915_vma *vma,
sys/dev/pci/drm/i915/selftests/i915_vma.c
41
bool ok = true;
sys/dev/pci/drm/i915/selftests/i915_vma.c
69
bool ok = true;
sys/dev/pci/drm/i915/selftests/i915_vma.c
717
static bool assert_partial(struct drm_i915_gem_object *obj,
sys/dev/pci/drm/i915/selftests/i915_vma.c
747
static bool assert_pin(struct i915_vma *vma,
sys/dev/pci/drm/i915/selftests/i915_vma.c
752
bool ok = true;
sys/dev/pci/drm/i915/selftests/igt_reset.c
45
bool igt_force_reset(struct intel_gt *gt)
sys/dev/pci/drm/i915/selftests/igt_reset.h
16
bool igt_force_reset(struct intel_gt *gt);
sys/dev/pci/drm/i915/selftests/igt_spinner.c
254
bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq)
sys/dev/pci/drm/i915/selftests/igt_spinner.h
41
bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1214
bool skip;
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
141
static bool is_contiguous(struct drm_i915_gem_object *obj)
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
348
bool should_fail = target > min;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
114
bool is_watertight;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
31
bool is_watertight)
sys/dev/pci/drm/i915/selftests/librapl.c
11
bool librapl_supported(const struct drm_i915_private *i915)
sys/dev/pci/drm/i915/selftests/librapl.h
13
bool librapl_supported(const struct drm_i915_private *i915);
sys/dev/pci/drm/i915/selftests/mock_request.c
44
bool mock_cancel_request(struct i915_request *request)
sys/dev/pci/drm/i915/selftests/mock_request.c
48
bool was_queued;
sys/dev/pci/drm/i915/selftests/mock_request.h
35
bool mock_cancel_request(struct i915_request *request);
sys/dev/pci/drm/i915/selftests/mock_uncore.c
29
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
sys/dev/pci/drm/i915/selftests/mock_uncore.c
36
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
sys/dev/pci/drm/i915/selftests/scatterlist.c
207
static inline bool page_contiguous(struct vm_page *first,
sys/dev/pci/drm/i915/soc/intel_dram.c
29
bool is_16gb_dimm;
sys/dev/pci/drm/i915/soc/intel_dram.c
334
static bool
sys/dev/pci/drm/i915/soc/intel_dram.c
393
static bool
sys/dev/pci/drm/i915/soc/intel_dram.h
33
bool symmetric_memory;
sys/dev/pci/drm/i915/soc/intel_dram.h
34
bool has_16gb_dimms;
sys/dev/pci/drm/i915/soc/intel_gmch.c
117
bool enabled;
sys/dev/pci/drm/i915/soc/intel_gmch.c
182
int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
sys/dev/pci/drm/i915/soc/intel_gmch.c
209
unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode)
sys/dev/pci/drm/i915/soc/intel_gmch.h
17
int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode);
sys/dev/pci/drm/i915/soc/intel_gmch.h
18
unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode);
sys/dev/pci/drm/i915/vlv_iosf_sb.c
171
static u32 unit_to_opcode(enum vlv_iosf_sb_unit unit, bool write)
sys/dev/pci/drm/i915/vlv_iosf_sb.c
91
const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
sys/dev/pci/drm/i915/vlv_suspend.c
305
static int vlv_force_gfx_clock(struct drm_i915_private *i915, bool force_on)
sys/dev/pci/drm/i915/vlv_suspend.c
329
static int vlv_allow_gt_wake(struct drm_i915_private *i915, bool allow)
sys/dev/pci/drm/i915/vlv_suspend.c
351
bool wait_for_on)
sys/dev/pci/drm/i915/vlv_suspend.c
428
int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume)
sys/dev/pci/drm/i915/vlv_suspend.h
16
int vlv_resume_prepare(struct drm_i915_private *i915, bool rpm_resume);
sys/dev/pci/drm/include/acpi/video.h
23
static inline bool
sys/dev/pci/drm/include/asm/cpufeature.h
15
static inline bool
sys/dev/pci/drm/include/asm/cpufeature.h
38
static inline bool
sys/dev/pci/drm/include/asm/hypervisor.h
11
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_dual_mode_helper.h
112
struct i2c_adapter *adapter, bool *enabled);
sys/dev/pci/drm/include/drm/display/drm_dp_dual_mode_helper.h
114
struct i2c_adapter *adapter, bool enable);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
126
bool target_rr_divider;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
134
bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
135
bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
151
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
158
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
165
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
172
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
179
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
193
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
202
bool is_edp);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
207
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
237
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
244
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
250
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
256
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
262
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
270
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
288
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
302
static inline bool drm_dp_is_uhbr_rate(int link_rate)
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
36
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
38
bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
48
enum drm_dp_phy dp_phy, bool uhbr);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
50
enum drm_dp_phy dp_phy, bool uhbr);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
515
bool is_remote;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
520
bool powered_down;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
525
bool no_zero_sized;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
530
bool dpcd_probe_disabled;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
534
void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
535
void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
61
bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
63
bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
65
bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
66
bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
67
bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
676
bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
682
bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
684
bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
698
bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
700
bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
720
bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
734
int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
737
bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
738
bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
739
void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
768
bool is_branch);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
832
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
856
bool lsb_reg_used : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
857
bool aux_enable : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
858
bool aux_set : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
859
bool luminance_set : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
866
u32 *current_level, u8 *current_mode, bool need_luminance);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
942
bool enhanced_frame_cap;
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
951
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
952
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
960
bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
964
bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
971
bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
984
int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
sys/dev/pci/drm/include/drm/display/drm_dp_helper.h
989
int bpp_x16, int symbol_size, bool is_mst);
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
1001
static inline bool
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
116
bool input;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
117
bool mcs;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
118
bool ddps;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
120
bool ldps;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
154
bool fec_capable;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
162
bool broadcast;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
163
bool path_msg;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
165
bool somt;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
166
bool eomt;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
167
bool seqno;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
177
bool have_somt;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
178
bool have_eomt;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
251
bool link_address_sent;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
268
bool input_port;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
271
bool mcs;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
272
bool ddps;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
273
bool legacy_device_plug_status;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
318
bool reply_signed;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
321
bool unauthorizable_device_present;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
322
bool legacy_device_present;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
323
bool query_capable_device_present;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
326
bool hdcp_1x_device_present;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
327
bool hdcp_2x_device_present;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
330
bool auth_completed;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
333
bool encryption_enabled;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
336
bool repeater_present;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
360
bool legacy_device_plug_status;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
361
bool displayport_device_plug_status;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
362
bool message_capability_status;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
363
bool input_port;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
406
bool valid_stream_event;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
418
bool fec_capable;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
507
bool path_msg;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
577
bool delete : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
579
bool dsc_enabled : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
701
bool mst_state : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
707
bool payload_id_table_cleared : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
714
bool reset_rx_state : 1;
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
856
int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state);
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
861
bool *handled);
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
906
bool sync);
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
930
bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
939
int pbn, bool enable);
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
950
struct drm_dp_mst_port *port, bool power_up);
sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h
966
bool drm_dp_mst_port_is_logical(struct drm_dp_mst_port *port)
sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h
138
static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h
55
bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel);
sys/dev/pci/drm/include/drm/display/drm_dsc.h
103
bool simple_422;
sys/dev/pci/drm/include/drm/display/drm_dsc.h
159
bool block_pred_enable;
sys/dev/pci/drm/include/drm/display/drm_dsc.h
223
bool vbr_enable;
sys/dev/pci/drm/include/drm/display/drm_dsc.h
249
bool native_422;
sys/dev/pci/drm/include/drm/display/drm_dsc.h
253
bool native_420;
sys/dev/pci/drm/include/drm/display/drm_dsc.h
87
bool convert_rgb;
sys/dev/pci/drm/include/drm/display/drm_hdcp_helper.h
19
bool hdcp_content_type);
sys/dev/pci/drm/include/drm/display/drm_hdmi_audio_helper.h
18
bool spdif_playback,
sys/dev/pci/drm/include/drm/display/drm_hdmi_audio_helper.h
21
bool plugged);
sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h
27
int (*enable)(struct drm_connector *connector, bool enable);
sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h
75
bool drm_scdc_get_scrambling_status(struct drm_connector *connector);
sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h
77
bool drm_scdc_set_scrambling(struct drm_connector *connector, bool enable);
sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h
78
bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector, bool set);
sys/dev/pci/drm/include/drm/drm_atomic.h
1156
static inline bool
sys/dev/pci/drm/include/drm/drm_atomic.h
1172
static inline bool
sys/dev/pci/drm/include/drm/drm_atomic.h
157
bool abort_completion;
sys/dev/pci/drm/include/drm/drm_atomic.h
432
bool allow_modeset : 1;
sys/dev/pci/drm/include/drm/drm_atomic.h
444
bool legacy_cursor_update : 1;
sys/dev/pci/drm/include/drm/drm_atomic.h
449
bool async_update : 1;
sys/dev/pci/drm/include/drm/drm_atomic.h
459
bool duplicated : 1;
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
135
bool atomic);
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
138
bool stall);
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
142
bool nonblock);
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
249
static inline bool drm_atomic_plane_enabling(struct drm_plane_state *old_plane_state,
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
275
static inline bool
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
58
bool can_position,
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
59
bool can_update_disabled);
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
75
bool nonblock);
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
83
bool pre_swap);
sys/dev/pci/drm/include/drm/drm_audio_component.h
39
void (*codec_wake_override)(struct device *, bool enable);
sys/dev/pci/drm/include/drm/drm_audio_component.h
63
int (*get_eld)(struct device *, int port, int pipe, bool *enabled,
sys/dev/pci/drm/include/drm/drm_auth.h
135
bool drm_is_current_master(struct drm_file *fpriv);
sys/dev/pci/drm/include/drm/drm_blend.h
38
static inline bool drm_rotation_90_or_270(unsigned int rotation)
sys/dev/pci/drm/include/drm/drm_bridge.h
1043
bool interlace_allowed;
sys/dev/pci/drm/include/drm/drm_bridge.h
1048
bool ycbcr_420_allowed;
sys/dev/pci/drm/include/drm/drm_bridge.h
1056
bool pre_enable_prev_first;
sys/dev/pci/drm/include/drm/drm_bridge.h
1060
bool support_hdcp;
sys/dev/pci/drm/include/drm/drm_bridge.h
1209
static inline bool drm_bridge_is_last(struct drm_bridge *bridge)
sys/dev/pci/drm/include/drm/drm_bridge.h
1375
bool drm_bridge_is_panel(const struct drm_bridge *bridge);
sys/dev/pci/drm/include/drm/drm_bridge.h
1391
static inline bool drm_bridge_is_panel(const struct drm_bridge *bridge)
sys/dev/pci/drm/include/drm/drm_bridge.h
173
bool (*mode_fixup)(struct drm_bridge *bridge,
sys/dev/pci/drm/include/drm/drm_bridge.h
751
bool enable, int direction);
sys/dev/pci/drm/include/drm/drm_bridge.h
780
int (*hdmi_cec_enable)(struct drm_bridge *bridge, bool enable);
sys/dev/pci/drm/include/drm/drm_bridge.h
868
bool enable, int direction);
sys/dev/pci/drm/include/drm/drm_bridge.h
911
bool dual_link;
sys/dev/pci/drm/include/drm/drm_buddy.h
110
static inline bool
sys/dev/pci/drm/include/drm/drm_buddy.h
116
static inline bool
sys/dev/pci/drm/include/drm/drm_buddy.h
122
static inline bool
sys/dev/pci/drm/include/drm/drm_buddy.h
128
static inline bool
sys/dev/pci/drm/include/drm/drm_buddy.h
159
void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear);
sys/dev/pci/drm/include/drm/drm_cache.h
43
bool drm_need_swiotlb(int dma_bits);
sys/dev/pci/drm/include/drm/drm_cache.h
46
static inline bool drm_arch_can_wc_memory(void)
sys/dev/pci/drm/include/drm/drm_client.h
143
bool suspended;
sys/dev/pci/drm/include/drm/drm_client.h
151
bool hotplug_pending;
sys/dev/pci/drm/include/drm/drm_client.h
159
bool hotplug_failed;
sys/dev/pci/drm/include/drm/drm_client.h
218
bool drm_client_rotation(struct drm_mode_set *modeset, unsigned int *rotation);
sys/dev/pci/drm/include/drm/drm_client.h
79
int (*suspend)(struct drm_client_dev *client, bool holds_console_lock);
sys/dev/pci/drm/include/drm/drm_client.h
93
int (*resume)(struct drm_client_dev *client, bool holds_console_lock);
sys/dev/pci/drm/include/drm/drm_client_event.h
14
void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock);
sys/dev/pci/drm/include/drm/drm_client_event.h
15
void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock);
sys/dev/pci/drm/include/drm/drm_client_event.h
23
static inline void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock)
sys/dev/pci/drm/include/drm/drm_client_event.h
25
static inline void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock)
sys/dev/pci/drm/include/drm/drm_color_mgmt.h
57
bool has_ctm,
sys/dev/pci/drm/include/drm/drm_connector.h
1066
bool self_refresh_aware;
sys/dev/pci/drm/include/drm/drm_connector.h
1198
bool enable, int direction);
sys/dev/pci/drm/include/drm/drm_connector.h
1368
bool force);
sys/dev/pci/drm/include/drm/drm_connector.h
1635
bool specified;
sys/dev/pci/drm/include/drm/drm_connector.h
1642
bool refresh_specified;
sys/dev/pci/drm/include/drm/drm_connector.h
1649
bool bpp_specified;
sys/dev/pci/drm/include/drm/drm_connector.h
1691
bool rb;
sys/dev/pci/drm/include/drm/drm_connector.h
1698
bool interlace;
sys/dev/pci/drm/include/drm/drm_connector.h
1706
bool cvt;
sys/dev/pci/drm/include/drm/drm_connector.h
1714
bool margins;
sys/dev/pci/drm/include/drm/drm_connector.h
1757
bool tv_mode_specified;
sys/dev/pci/drm/include/drm/drm_connector.h
1797
void (*plugged_cb)(struct device *dev, bool plugged);
sys/dev/pci/drm/include/drm/drm_connector.h
1812
bool last_state;
sys/dev/pci/drm/include/drm/drm_connector.h
1962
bool interlace_allowed;
sys/dev/pci/drm/include/drm/drm_connector.h
1968
bool doublescan_allowed;
sys/dev/pci/drm/include/drm/drm_connector.h
1974
bool stereo_allowed;
sys/dev/pci/drm/include/drm/drm_connector.h
1982
bool ycbcr_420_allowed;
sys/dev/pci/drm/include/drm/drm_connector.h
2189
bool latency_present[2];
sys/dev/pci/drm/include/drm/drm_connector.h
2226
bool edid_corrupt;
sys/dev/pci/drm/include/drm/drm_connector.h
2271
bool has_tile;
sys/dev/pci/drm/include/drm/drm_connector.h
2275
bool tile_is_single_monitor;
sys/dev/pci/drm/include/drm/drm_connector.h
229
bool supported;
sys/dev/pci/drm/include/drm/drm_connector.h
233
bool low_rates;
sys/dev/pci/drm/include/drm/drm_connector.h
2418
static inline bool
sys/dev/pci/drm/include/drm/drm_connector.h
246
bool supported;
sys/dev/pci/drm/include/drm/drm_connector.h
2461
bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state,
sys/dev/pci/drm/include/drm/drm_connector.h
2479
struct drm_connector *connector, bool capable);
sys/dev/pci/drm/include/drm/drm_connector.h
250
bool read_request;
sys/dev/pci/drm/include/drm/drm_connector.h
2548
bool drm_connector_has_possible_encoder(struct drm_connector *connector,
sys/dev/pci/drm/include/drm/drm_connector.h
266
bool v_1p2;
sys/dev/pci/drm/include/drm/drm_connector.h
269
bool native_420;
sys/dev/pci/drm/include/drm/drm_connector.h
275
bool all_bpp;
sys/dev/pci/drm/include/drm/drm_connector.h
751
bool dvi_dual;
sys/dev/pci/drm/include/drm/drm_connector.h
759
bool is_hdmi;
sys/dev/pci/drm/include/drm/drm_connector.h
767
bool has_audio;
sys/dev/pci/drm/include/drm/drm_connector.h
772
bool has_hdmi_infoframe;
sys/dev/pci/drm/include/drm/drm_connector.h
778
bool rgb_quant_range_selectable;
sys/dev/pci/drm/include/drm/drm_connector.h
810
bool non_desktop;
sys/dev/pci/drm/include/drm/drm_connector.h
938
bool set;
sys/dev/pci/drm/include/drm/drm_connector.h
984
bool is_limited_range;
sys/dev/pci/drm/include/drm/drm_crtc.h
1013
bool enabled;
sys/dev/pci/drm/include/drm/drm_crtc.h
105
bool active;
sys/dev/pci/drm/include/drm/drm_crtc.h
111
bool planes_changed : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
123
bool mode_changed : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
130
bool active_changed : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
1326
bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state);
sys/dev/pci/drm/include/drm/drm_crtc.h
141
bool connectors_changed : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
147
bool zpos_changed : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
153
bool color_mgmt_changed : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
189
bool no_vblank : 1;
sys/dev/pci/drm/include/drm/drm_crtc.h
291
bool async_flip;
sys/dev/pci/drm/include/drm/drm_crtc.h
300
bool vrr_enabled;
sys/dev/pci/drm/include/drm/drm_crtc.h
311
bool self_refresh_active;
sys/dev/pci/drm/include/drm/drm_crtc.h
90
bool enable;
sys/dev/pci/drm/include/drm/drm_crtc.h
920
bool (*get_vblank_timestamp)(struct drm_crtc *crtc,
sys/dev/pci/drm/include/drm/drm_crtc.h
923
bool in_vblank_irq);
sys/dev/pci/drm/include/drm/drm_crtc_helper.h
51
bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
sys/dev/pci/drm/include/drm/drm_crtc_helper.h
57
bool drm_helper_crtc_in_use(struct drm_crtc *crtc);
sys/dev/pci/drm/include/drm/drm_crtc_helper.h
58
bool drm_helper_encoder_in_use(struct drm_encoder *encoder);
sys/dev/pci/drm/include/drm/drm_damage_helper.h
64
bool full_update;
sys/dev/pci/drm/include/drm/drm_damage_helper.h
77
bool
sys/dev/pci/drm/include/drm/drm_damage_helper.h
80
bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state,
sys/dev/pci/drm/include/drm/drm_debugfs_crc.h
40
bool has_frame_counter;
sys/dev/pci/drm/include/drm/drm_debugfs_crc.h
62
bool opened, overflow;
sys/dev/pci/drm/include/drm/drm_debugfs_crc.h
70
int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool has_frame,
sys/dev/pci/drm/include/drm/drm_debugfs_crc.h
73
static inline int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool has_frame,
sys/dev/pci/drm/include/drm/drm_device.h
204
bool registered;
sys/dev/pci/drm/include/drm/drm_device.h
230
bool unplugged;
sys/dev/pci/drm/include/drm/drm_device.h
302
bool vblank_disable_immediate;
sys/dev/pci/drm/include/drm/drm_drv.h
271
bool from_open);
sys/dev/pci/drm/include/drm/drm_drv.h
500
bool drm_dev_enter(struct drm_device *dev, int *idx);
sys/dev/pci/drm/include/drm/drm_drv.h
519
static inline bool drm_dev_is_unplugged(struct drm_device *dev)
sys/dev/pci/drm/include/drm/drm_drv.h
542
static inline bool drm_core_check_all_features(const struct drm_device *dev,
sys/dev/pci/drm/include/drm/drm_drv.h
560
static inline bool drm_core_check_feature(const struct drm_device *dev,
sys/dev/pci/drm/include/drm/drm_drv.h
574
static inline bool drm_drv_uses_atomic_modeset(struct drm_device *dev)
sys/dev/pci/drm/include/drm/drm_drv.h
582
static inline bool drm_firmware_drivers_only(void)
sys/dev/pci/drm/include/drm/drm_edid.h
438
bool drm_probe_ddc(struct i2c_adapter *adapter);
sys/dev/pci/drm/include/drm/drm_edid.h
448
bool drm_detect_hdmi_monitor(const struct edid *edid);
sys/dev/pci/drm/include/drm/drm_edid.h
449
bool drm_detect_monitor_audio(const struct edid *edid);
sys/dev/pci/drm/include/drm/drm_edid.h
456
bool drm_edid_is_valid(struct edid *edid);
sys/dev/pci/drm/include/drm/drm_edid.h
461
bool rb);
sys/dev/pci/drm/include/drm/drm_edid.h
470
bool drm_edid_valid(const struct drm_edid *drm_edid);
sys/dev/pci/drm/include/drm/drm_edid.h
484
bool drm_edid_is_digital(const struct drm_edid *drm_edid);
sys/dev/pci/drm/include/drm/drm_edid.h
488
const struct drm_edid_product_id *id, bool raw);
sys/dev/pci/drm/include/drm/drm_edid.h
490
bool drm_edid_match(const struct drm_edid *drm_edid,
sys/dev/pci/drm/include/drm/drm_edid.h
492
bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk);
sys/dev/pci/drm/include/drm/drm_encoder.h
296
static inline bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
sys/dev/pci/drm/include/drm/drm_exec.h
133
static inline bool drm_exec_is_contended(struct drm_exec *exec)
sys/dev/pci/drm/include/drm/drm_exec.h
140
bool drm_exec_cleanup(struct drm_exec *exec);
sys/dev/pci/drm/include/drm/drm_fb_helper.h
111
void (*fb_set_suspend)(struct drm_fb_helper *helper, bool suspend);
sys/dev/pci/drm/include/drm/drm_fb_helper.h
183
bool delayed_hotplug;
sys/dev/pci/drm/include/drm/drm_fb_helper.h
195
bool deferred_setup;
sys/dev/pci/drm/include/drm/drm_fb_helper.h
278
void drm_fb_helper_set_suspend(struct drm_fb_helper *fb_helper, bool suspend);
sys/dev/pci/drm/include/drm/drm_fb_helper.h
280
bool suspend);
sys/dev/pci/drm/include/drm/drm_fb_helper.h
389
bool suspend)
sys/dev/pci/drm/include/drm/drm_fb_helper.h
394
drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, bool suspend)
sys/dev/pci/drm/include/drm/drm_file.h
177
bool authenticated;
sys/dev/pci/drm/include/drm/drm_file.h
184
bool stereo_allowed;
sys/dev/pci/drm/include/drm/drm_file.h
192
bool universal_planes;
sys/dev/pci/drm/include/drm/drm_file.h
195
bool atomic;
sys/dev/pci/drm/include/drm/drm_file.h
203
bool aspect_ratio_allowed;
sys/dev/pci/drm/include/drm/drm_file.h
210
bool writeback_connectors;
sys/dev/pci/drm/include/drm/drm_file.h
221
bool was_master;
sys/dev/pci/drm/include/drm/drm_file.h
232
bool is_master;
sys/dev/pci/drm/include/drm/drm_file.h
244
bool supports_virtualized_cursor_plane;
sys/dev/pci/drm/include/drm/drm_file.h
435
static inline bool drm_is_primary_client(const struct drm_file *file_priv)
sys/dev/pci/drm/include/drm/drm_file.h
449
static inline bool drm_is_render_client(const struct drm_file *file_priv)
sys/dev/pci/drm/include/drm/drm_file.h
464
static inline bool drm_is_accel_client(const struct drm_file *file_priv)
sys/dev/pci/drm/include/drm/drm_fixed.h
159
bool a_neg = a < 0;
sys/dev/pci/drm/include/drm/drm_fixed.h
160
bool b_neg = b < 0;
sys/dev/pci/drm/include/drm/drm_format_helper.h
32
bool preallocated;
sys/dev/pci/drm/include/drm/drm_format_helper.h
78
const struct drm_rect *clip, bool cached,
sys/dev/pci/drm/include/drm/drm_fourcc.h
137
bool has_alpha;
sys/dev/pci/drm/include/drm/drm_fourcc.h
140
bool is_yuv;
sys/dev/pci/drm/include/drm/drm_fourcc.h
143
bool is_color_indexed;
sys/dev/pci/drm/include/drm/drm_fourcc.h
154
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
168
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
182
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
197
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
212
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
227
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
242
static inline bool
sys/dev/pci/drm/include/drm/drm_fourcc.h
257
static inline bool
sys/dev/pci/drm/include/drm/drm_gem.h
579
bool dirty, bool accessed);
sys/dev/pci/drm/include/drm/drm_gem.h
591
bool wait_all, unsigned long timeout);
sys/dev/pci/drm/include/drm/drm_gem.h
607
bool (*shrink)(struct drm_gem_object *obj, struct ww_acquire_ctx *ticket),
sys/dev/pci/drm/include/drm/drm_gem.h
620
static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_object *obj)
sys/dev/pci/drm/include/drm/drm_gem.h
632
static inline bool drm_gem_is_imported(const struct drm_gem_object *obj)
sys/dev/pci/drm/include/drm/drm_gem_dma_helper.h
34
bool map_noncoherent;
sys/dev/pci/drm/include/drm/drm_gpusvm.h
286
bool drm_gpusvm_range_pages_valid(struct drm_gpusvm *gpusvm,
sys/dev/pci/drm/include/drm/drm_gpusvm.h
297
bool drm_gpusvm_has_mapping(struct drm_gpusvm *gpusvm, unsigned long start,
sys/dev/pci/drm/include/drm/drm_gpuvm.h
169
static inline void drm_gpuva_invalidate(struct drm_gpuva *va, bool invalidate)
sys/dev/pci/drm/include/drm/drm_gpuvm.h
184
static inline bool drm_gpuva_invalidated(struct drm_gpuva *va)
sys/dev/pci/drm/include/drm/drm_gpuvm.h
363
bool drm_gpuvm_range_valid(struct drm_gpuvm *gpuvm, u64 addr, u64 range);
sys/dev/pci/drm/include/drm/drm_gpuvm.h
364
bool drm_gpuvm_interval_empty(struct drm_gpuvm *gpuvm, u64 addr, u64 range);
sys/dev/pci/drm/include/drm/drm_gpuvm.h
376
static inline bool
sys/dev/pci/drm/include/drm/drm_gpuvm.h
389
static inline bool
sys/dev/pci/drm/include/drm/drm_gpuvm.h
434
static inline bool
sys/dev/pci/drm/include/drm/drm_gpuvm.h
676
bool evicted;
sys/dev/pci/drm/include/drm/drm_gpuvm.h
747
bool drm_gpuvm_bo_put(struct drm_gpuvm_bo *vm_bo);
sys/dev/pci/drm/include/drm/drm_gpuvm.h
753
void drm_gpuvm_bo_evict(struct drm_gpuvm_bo *vm_bo, bool evict);
sys/dev/pci/drm/include/drm/drm_gpuvm.h
764
drm_gpuvm_bo_gem_evict(struct drm_gem_object *obj, bool evict)
sys/dev/pci/drm/include/drm/drm_gpuvm.h
898
bool keep;
sys/dev/pci/drm/include/drm/drm_ioctl.h
172
bool drm_ioctl_flags(unsigned int nr, unsigned int *flags);
sys/dev/pci/drm/include/drm/drm_mipi_dsi.h
30
bool attached;
sys/dev/pci/drm/include/drm/drm_mipi_dsi.h
82
bool mipi_dsi_packet_format_is_long(u8);
sys/dev/pci/drm/include/drm/drm_mipi_dsi.h
83
int mipi_dsi_compression_mode(struct mipi_dsi_device *, bool);
sys/dev/pci/drm/include/drm/drm_mm.h
257
static inline bool drm_mm_node_allocated(const struct drm_mm_node *node)
sys/dev/pci/drm/include/drm/drm_mm.h
275
static inline bool drm_mm_initialized(const struct drm_mm *mm)
sys/dev/pci/drm/include/drm/drm_mm.h
292
static inline bool drm_mm_hole_follows(const struct drm_mm_node *node)
sys/dev/pci/drm/include/drm/drm_mm.h
476
static inline bool drm_mm_clean(const struct drm_mm *mm)
sys/dev/pci/drm/include/drm/drm_mm.h
543
bool drm_mm_scan_add_block(struct drm_mm_scan *scan,
sys/dev/pci/drm/include/drm/drm_mm.h
545
bool drm_mm_scan_remove_block(struct drm_mm_scan *scan,
sys/dev/pci/drm/include/drm/drm_mode_config.h
270
bool nonblock);
sys/dev/pci/drm/include/drm/drm_mode_config.h
541
bool poll_enabled;
sys/dev/pci/drm/include/drm/drm_mode_config.h
542
bool poll_running;
sys/dev/pci/drm/include/drm/drm_mode_config.h
543
bool delayed_event;
sys/dev/pci/drm/include/drm/drm_mode_config.h
894
bool quirk_addfb_prefer_xbgr_30bpp;
sys/dev/pci/drm/include/drm/drm_mode_config.h
908
bool quirk_addfb_prefer_host_byte_order;
sys/dev/pci/drm/include/drm/drm_mode_config.h
914
bool async_page_flip;
sys/dev/pci/drm/include/drm/drm_mode_config.h
924
bool fb_modifiers_not_supported;
sys/dev/pci/drm/include/drm/drm_mode_config.h
932
bool normalize_zpos;
sys/dev/pci/drm/include/drm/drm_mode_object.h
141
bool drm_mode_object_lease_required(uint32_t type);
sys/dev/pci/drm/include/drm/drm_modes.h
389
bool expose_to_userspace;
sys/dev/pci/drm/include/drm/drm_modes.h
447
static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
sys/dev/pci/drm/include/drm/drm_modes.h
464
bool drm_mode_is_420_only(const struct drm_display_info *display,
sys/dev/pci/drm/include/drm/drm_modes.h
466
bool drm_mode_is_420_also(const struct drm_display_info *display,
sys/dev/pci/drm/include/drm/drm_modes.h
468
bool drm_mode_is_420(const struct drm_display_info *display,
sys/dev/pci/drm/include/drm/drm_modes.h
478
bool interlace);
sys/dev/pci/drm/include/drm/drm_modes.h
492
bool reduced, bool interlaced,
sys/dev/pci/drm/include/drm/drm_modes.h
493
bool margins);
sys/dev/pci/drm/include/drm/drm_modes.h
496
bool interlaced, int margins);
sys/dev/pci/drm/include/drm/drm_modes.h
499
int vrefresh, bool interlaced,
sys/dev/pci/drm/include/drm/drm_modes.h
543
bool drm_mode_match(const struct drm_display_mode *mode1,
sys/dev/pci/drm/include/drm/drm_modes.h
546
bool drm_mode_equal(const struct drm_display_mode *mode1,
sys/dev/pci/drm/include/drm/drm_modes.h
548
bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
sys/dev/pci/drm/include/drm/drm_modes.h
550
bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
sys/dev/pci/drm/include/drm/drm_modes.h
562
struct list_head *mode_list, bool verbose);
sys/dev/pci/drm/include/drm/drm_modes.h
567
bool
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
1414
struct drm_atomic_state *state, bool flip);
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
192
bool (*mode_fixup)(struct drm_crtc *crtc,
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
489
bool (*get_scanout_position)(struct drm_crtc *crtc,
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
490
bool in_vblank_irq, int *vpos, int *hpos,
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
605
bool (*mode_fixup)(struct drm_encoder *encoder,
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
933
bool force);
sys/dev/pci/drm/include/drm/drm_modeset_lock.h
121
static inline bool drm_modeset_is_locked(struct drm_modeset_lock *lock)
sys/dev/pci/drm/include/drm/drm_modeset_lock.h
71
bool trylock_only;
sys/dev/pci/drm/include/drm/drm_modeset_lock.h
74
bool interruptible;
sys/dev/pci/drm/include/drm/drm_panel.h
269
bool prepare_prev_first;
sys/dev/pci/drm/include/drm/drm_panel.h
276
bool prepared;
sys/dev/pci/drm/include/drm/drm_panel.h
283
bool enabled;
sys/dev/pci/drm/include/drm/drm_panel.h
359
bool drm_is_panel_follower(struct device *dev);
sys/dev/pci/drm/include/drm/drm_panel.h
366
static inline bool drm_is_panel_follower(struct device *dev)
sys/dev/pci/drm/include/drm/drm_panic.h
172
static inline bool drm_panic_trylock(struct drm_device *dev, unsigned long flags)
sys/dev/pci/drm/include/drm/drm_plane.h
207
bool ignore_damage_clips;
sys/dev/pci/drm/include/drm/drm_plane.h
237
bool visible;
sys/dev/pci/drm/include/drm/drm_plane.h
262
bool color_mgmt_changed : 1;
sys/dev/pci/drm/include/drm/drm_plane.h
550
bool (*format_mod_supported)(struct drm_plane *plane, uint32_t format,
sys/dev/pci/drm/include/drm/drm_plane.h
566
bool (*format_mod_supported_async)(struct drm_plane *plane,
sys/dev/pci/drm/include/drm/drm_plane.h
676
bool format_default;
sys/dev/pci/drm/include/drm/drm_plane.h
992
bool drm_plane_has_format(struct drm_plane *plane,
sys/dev/pci/drm/include/drm/drm_plane.h
994
bool drm_any_plane_has_format(struct drm_device *dev,
sys/dev/pci/drm/include/drm/drm_prime.h
107
bool drm_gem_is_prime_exported_dma_buf(struct drm_device *dev,
sys/dev/pci/drm/include/drm/drm_print.h
144
static inline bool drm_debug_enabled_raw(enum drm_debug_category category)
sys/dev/pci/drm/include/drm/drm_print.h
357
static inline bool drm_coredump_printer_is_full(struct drm_printer *p)
sys/dev/pci/drm/include/drm/drm_print.h
554
static bool __print_once __read_mostly; \
sys/dev/pci/drm/include/drm/drm_probe_helper.h
18
bool force);
sys/dev/pci/drm/include/drm/drm_probe_helper.h
23
bool drm_helper_hpd_irq_event(struct drm_device *dev);
sys/dev/pci/drm/include/drm/drm_probe_helper.h
24
bool drm_connector_helper_hpd_irq_event(struct drm_connector *connector);
sys/dev/pci/drm/include/drm/drm_probe_helper.h
31
bool drm_kms_helper_is_poll_worker(void);
sys/dev/pci/drm/include/drm/drm_probe_helper.h
44
bool force);
sys/dev/pci/drm/include/drm/drm_property.h
241
static inline bool drm_property_type_is(struct drm_property *property,
sys/dev/pci/drm/include/drm/drm_property.h
287
bool *replaced);
sys/dev/pci/drm/include/drm/drm_property.h
294
bool drm_property_replace_blob(struct drm_property_blob **blob,
sys/dev/pci/drm/include/drm/drm_rect.h
208
static inline bool drm_rect_visible(const struct drm_rect *r)
sys/dev/pci/drm/include/drm/drm_rect.h
221
static inline bool drm_rect_equals(const struct drm_rect *r1,
sys/dev/pci/drm/include/drm/drm_rect.h
249
static inline bool drm_rect_overlap(const struct drm_rect *a,
sys/dev/pci/drm/include/drm/drm_rect.h
256
bool drm_rect_intersect(struct drm_rect *r, const struct drm_rect *clip);
sys/dev/pci/drm/include/drm/drm_rect.h
257
bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst,
sys/dev/pci/drm/include/drm/drm_rect.h
266
const struct drm_rect *r, bool fixed_point);
sys/dev/pci/drm/include/drm/drm_suballoc.h
58
gfp_t gfp, bool intr, size_t align);
sys/dev/pci/drm/include/drm/drm_util.h
62
static inline bool drm_can_sleep(void)
sys/dev/pci/drm/include/drm/drm_vblank.h
103
bool disable_immediate;
sys/dev/pci/drm/include/drm/drm_vblank.h
238
bool enabled;
sys/dev/pci/drm/include/drm/drm_vblank.h
261
bool drm_dev_has_vblank(const struct drm_device *dev);
sys/dev/pci/drm/include/drm/drm_vblank.h
273
bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe);
sys/dev/pci/drm/include/drm/drm_vblank.h
274
bool drm_crtc_handle_vblank(struct drm_crtc *crtc);
sys/dev/pci/drm/include/drm/drm_vblank.h
297
typedef bool (*drm_vblank_get_scanout_position_func)(struct drm_crtc *crtc,
sys/dev/pci/drm/include/drm/drm_vblank.h
298
bool in_vblank_irq,
sys/dev/pci/drm/include/drm/drm_vblank.h
304
bool
sys/dev/pci/drm/include/drm/drm_vblank.h
308
bool in_vblank_irq,
sys/dev/pci/drm/include/drm/drm_vblank.h
310
bool drm_crtc_vblank_helper_get_vblank_timestamp(struct drm_crtc *crtc,
sys/dev/pci/drm/include/drm/drm_vblank.h
313
bool in_vblank_irq);
sys/dev/pci/drm/include/drm/drm_vblank_work.h
66
u64 count, bool nextonmiss);
sys/dev/pci/drm/include/drm/drm_vblank_work.h
69
bool drm_vblank_work_cancel_sync(struct drm_vblank_work *work);
sys/dev/pci/drm/include/drm/drm_vma_manager.h
80
bool drm_vma_node_is_allowed(struct drm_vma_offset_node *node,
sys/dev/pci/drm/include/drm/gpu_scheduler.h
216
bool stopped;
sys/dev/pci/drm/include/drm/gpu_scheduler.h
597
bool ready;
sys/dev/pci/drm/include/drm/gpu_scheduler.h
598
bool free_guilty;
sys/dev/pci/drm/include/drm/gpu_scheduler.h
599
bool pause_submit;
sys/dev/pci/drm/include/drm/gpu_scheduler.h
600
bool own_submit_wq;
sys/dev/pci/drm/include/drm/gpu_scheduler.h
645
bool drm_sched_wqueue_ready(struct drm_gpu_scheduler *sched);
sys/dev/pci/drm/include/drm/gpu_scheduler.h
676
bool write);
sys/dev/pci/drm/include/drm/gpu_scheduler.h
677
bool drm_sched_job_has_dependency(struct drm_sched_job *job,
sys/dev/pci/drm/include/drm/gpu_scheduler.h
682
static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
sys/dev/pci/drm/include/drm/intel/i915_drm.h
33
bool i915_gpu_raise(void);
sys/dev/pci/drm/include/drm/intel/i915_drm.h
34
bool i915_gpu_lower(void);
sys/dev/pci/drm/include/drm/intel/i915_drm.h
35
bool i915_gpu_busy(void);
sys/dev/pci/drm/include/drm/intel/i915_drm.h
36
bool i915_gpu_turbo_disable(void);
sys/dev/pci/drm/include/drm/intel/i915_hdcp_interface.h
24
struct hdcp_port_data *, struct hdcp2_ake_send_cert *, bool *,
sys/dev/pci/drm/include/drm/intel/intel-gtt.h
21
dma_addr_t intel_gmch_gtt_read_entry(unsigned int, bool *, bool *);
sys/dev/pci/drm/include/drm/intel/intel_lpe_audio.h
39
bool dp_output;
sys/dev/pci/drm/include/drm/spsc_queue.h
65
static inline bool spsc_queue_push(struct spsc_queue *queue, struct spsc_node *node)
sys/dev/pci/drm/include/drm/ttm/ttm_backup.h
35
static inline bool ttm_backup_page_ptr_is_handle(const struct vm_page *page)
sys/dev/pci/drm/include/drm/ttm/ttm_backup.h
59
pgoff_t handle, bool intr);
sys/dev/pci/drm/include/drm/ttm/ttm_backup.h
63
bool writeback, pgoff_t idx, gfp_t page_gfp,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
124
bool deleted;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
185
bool interruptible;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
186
bool no_wait_gpu;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
187
bool gfp_retry_mayfail;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
188
bool allow_res_evict;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
220
bool trylock_only;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
253
bool ttm_bo_shrink_suitable(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx);
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
255
bool ttm_bo_shrink_avoid_wait(void);
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
280
bool interruptible, bool no_wait,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
286
bool success;
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
315
bool interruptible,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
385
bool *is_iomem)
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
399
bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
408
uint32_t alignment, bool interruptible,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
467
void ttm_move_memcpy(bool clear, u32 num_pages,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
475
struct dma_fence *fence, bool evict,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
476
bool pipeline,
sys/dev/pci/drm/include/drm/ttm/ttm_bo.h
506
bool needs_unlock;
sys/dev/pci/drm/include/drm/ttm/ttm_device.h
119
bool (*eviction_valuable)(struct ttm_buffer_object *bo,
sys/dev/pci/drm/include/drm/ttm/ttm_device.h
149
int (*move)(struct ttm_buffer_object *bo, bool evict,
sys/dev/pci/drm/include/drm/ttm/ttm_device.h
303
bool use_dma_alloc, bool use_dma32);
sys/dev/pci/drm/include/drm/ttm/ttm_execbuf_util.h
100
struct list_head *list, bool intr,
sys/dev/pci/drm/include/drm/ttm/ttm_kmap_iter.h
43
bool maps_tt;
sys/dev/pci/drm/include/drm/ttm/ttm_pool.h
82
bool use_dma_alloc;
sys/dev/pci/drm/include/drm/ttm/ttm_pool.h
83
bool use_dma32;
sys/dev/pci/drm/include/drm/ttm/ttm_pool.h
95
int nid, bool use_dma_alloc, bool use_dma32);
sys/dev/pci/drm/include/drm/ttm/ttm_range_manager.h
38
unsigned type, bool use_tt,
sys/dev/pci/drm/include/drm/ttm/ttm_range_manager.h
43
unsigned int type, bool use_tt,
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
140
bool (*intersects)(struct ttm_resource_manager *man,
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
156
bool (*compatible)(struct ttm_resource_manager *man,
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
193
bool use_type;
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
194
bool use_tt;
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
235
bool is_iomem;
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
379
bool needs_unmap;
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
392
ttm_resource_manager_set_used(struct ttm_resource_manager *man, bool used)
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
410
static inline bool ttm_resource_manager_used(struct ttm_resource_manager *man)
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
451
bool ttm_resource_intersects(struct ttm_device *bdev,
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
455
bool ttm_resource_compatible(struct ttm_resource *res,
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
457
bool evicting);
sys/dev/pci/drm/include/drm/ttm/ttm_resource.h
85
static inline bool ttm_lru_item_is_res(const struct ttm_lru_item *item)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
149
static inline bool ttm_tt_is_populated(struct ttm_tt *tt)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
160
static inline bool ttm_tt_is_swapped(const struct ttm_tt *tt)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
171
static inline bool ttm_tt_is_backed_up(const struct ttm_tt *tt)
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
197
int ttm_tt_create(struct ttm_buffer_object *bo, bool zero_alloc);
sys/dev/pci/drm/include/drm/ttm/ttm_tt.h
330
bool ttm_agp_is_bound(struct ttm_tt *ttm);
sys/dev/pci/drm/include/linux/apple-gmux.h
6
static inline bool
sys/dev/pci/drm/include/linux/atomic.h
78
static inline bool
sys/dev/pci/drm/include/linux/bitmap.h
100
static inline bool
sys/dev/pci/drm/include/linux/bitops.h
128
__assign_bit(u_int b, volatile void *p, bool set)
sys/dev/pci/drm/include/linux/capability.h
14
static inline bool
sys/dev/pci/drm/include/linux/capability.h
26
static inline bool
sys/dev/pci/drm/include/linux/cc_platform.h
10
static inline bool
sys/dev/pci/drm/include/linux/cgroup_dmem.h
19
static inline bool
sys/dev/pci/drm/include/linux/cgroup_dmem.h
21
struct dmem_cgroup_pool_state *t, bool a, bool *b)
sys/dev/pci/drm/include/linux/completion.h
151
static inline bool
sys/dev/pci/drm/include/linux/console.h
24
static inline bool
sys/dev/pci/drm/include/linux/dma-buf.h
46
bool allow_peer2peer;
sys/dev/pci/drm/include/linux/dma-buf.h
82
static inline bool
sys/dev/pci/drm/include/linux/dma-fence-array.h
34
static inline bool
sys/dev/pci/drm/include/linux/dma-fence-array.h
41
u64, unsigned, bool);
sys/dev/pci/drm/include/linux/dma-fence-chain.h
26
static inline bool
sys/dev/pci/drm/include/linux/dma-fence.h
102
static inline bool
sys/dev/pci/drm/include/linux/dma-fence.h
116
static inline bool
sys/dev/pci/drm/include/linux/dma-fence.h
124
static inline bool
sys/dev/pci/drm/include/linux/dma-fence.h
138
static inline bool
sys/dev/pci/drm/include/linux/dma-fence.h
145
dma_fence_end_signalling(bool x)
sys/dev/pci/drm/include/linux/dma-fence.h
41
bool (*enable_signaling)(struct dma_fence *);
sys/dev/pci/drm/include/linux/dma-fence.h
42
bool (*signaled)(struct dma_fence *);
sys/dev/pci/drm/include/linux/dma-fence.h
43
long (*wait)(struct dma_fence *, bool, long);
sys/dev/pci/drm/include/linux/dma-fence.h
66
bool dma_fence_is_signaled(struct dma_fence *);
sys/dev/pci/drm/include/linux/dma-fence.h
67
bool dma_fence_is_signaled_locked(struct dma_fence *);
sys/dev/pci/drm/include/linux/dma-fence.h
69
long dma_fence_default_wait(struct dma_fence *, bool, long);
sys/dev/pci/drm/include/linux/dma-fence.h
70
long dma_fence_wait_any_timeout(struct dma_fence **, uint32_t, bool, long,
sys/dev/pci/drm/include/linux/dma-fence.h
72
long dma_fence_wait_timeout(struct dma_fence *, bool, long);
sys/dev/pci/drm/include/linux/dma-fence.h
73
long dma_fence_wait(struct dma_fence *, bool);
sys/dev/pci/drm/include/linux/dma-fence.h
83
bool dma_fence_remove_callback(struct dma_fence *, struct dma_fence_cb *);
sys/dev/pci/drm/include/linux/dma-fence.h
84
bool dma_fence_is_container(struct dma_fence *);
sys/dev/pci/drm/include/linux/dma-mapping.h
42
static inline bool
sys/dev/pci/drm/include/linux/dma-resv.h
127
static inline enum dma_resv_usage dma_resv_usage_rw(bool write)
sys/dev/pci/drm/include/linux/dma-resv.h
217
bool is_restarted;
sys/dev/pci/drm/include/linux/dma-resv.h
270
static inline bool dma_resv_iter_is_restarted(struct dma_resv_iter *cursor)
sys/dev/pci/drm/include/linux/dma-resv.h
423
static inline bool __must_check dma_resv_trylock(struct dma_resv *obj)
sys/dev/pci/drm/include/linux/dma-resv.h
434
static inline bool dma_resv_is_locked(struct dma_resv *obj)
sys/dev/pci/drm/include/linux/dma-resv.h
482
bool intr, unsigned long timeout);
sys/dev/pci/drm/include/linux/dma-resv.h
485
bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage);
sys/dev/pci/drm/include/linux/dmi.h
10
bool dmi_match(int, const char *);
sys/dev/pci/drm/include/linux/err.h
23
static inline bool
sys/dev/pci/drm/include/linux/err.h
29
static inline bool
sys/dev/pci/drm/include/linux/fb.h
48
bool skip_vt_switch;
sys/dev/pci/drm/include/linux/fb.h
49
bool skip_panic;
sys/dev/pci/drm/include/linux/gfp.h
34
static inline bool
sys/dev/pci/drm/include/linux/hashtable.h
35
static inline bool
sys/dev/pci/drm/include/linux/hdmi.h
182
bool itc;
sys/dev/pci/drm/include/linux/hdmi.h
339
bool downmix_inhibit;
sys/dev/pci/drm/include/linux/idr.h
68
static inline bool
sys/dev/pci/drm/include/linux/interrupt.h
54
bool use_callback;
sys/dev/pci/drm/include/linux/iosys-map.h
14
bool is_iomem;
sys/dev/pci/drm/include/linux/iosys-map.h
47
static inline bool
sys/dev/pci/drm/include/linux/iosys-map.h
56
static inline bool
sys/dev/pci/drm/include/linux/irq_work.h
50
static inline bool
sys/dev/pci/drm/include/linux/kthread.h
32
bool kthread_queue_work(struct kthread_worker *, struct kthread_work *);
sys/dev/pci/drm/include/linux/kthread.h
33
bool kthread_cancel_work_sync(struct kthread_work *);
sys/dev/pci/drm/include/linux/ktime.h
135
static inline bool
sys/dev/pci/drm/include/linux/ktime.h
141
static inline bool
sys/dev/pci/drm/include/linux/llist.h
39
static inline bool
sys/dev/pci/drm/include/linux/llist.h
51
static inline bool
sys/dev/pci/drm/include/linux/llist.h
70
static inline bool
sys/dev/pci/drm/include/linux/mm.h
34
bool is_vmalloc_addr(const void *);
sys/dev/pci/drm/include/linux/mm.h
98
static inline bool
sys/dev/pci/drm/include/linux/module.h
22
static inline bool
sys/dev/pci/drm/include/linux/pci.h
251
bool pcie_aspm_enabled(struct pci_dev *);
sys/dev/pci/drm/include/linux/pci.h
253
static inline bool
sys/dev/pci/drm/include/linux/pci.h
259
static inline bool
sys/dev/pci/drm/include/linux/pci.h
274
static inline bool
sys/dev/pci/drm/include/linux/pci.h
470
static inline bool
sys/dev/pci/drm/include/linux/pci.h
555
static inline bool
sys/dev/pci/drm/include/linux/pci.h
561
static inline bool
sys/dev/pci/drm/include/linux/pci.h
567
static inline bool
sys/dev/pci/drm/include/linux/pm_qos.h
26
static inline bool
sys/dev/pci/drm/include/linux/preempt.h
29
static inline bool
sys/dev/pci/drm/include/linux/preempt.h
35
static inline bool
sys/dev/pci/drm/include/linux/preempt.h
41
static inline bool
sys/dev/pci/drm/include/linux/preempt.h
47
static inline bool
sys/dev/pci/drm/include/linux/printk.h
67
const void *, size_t, bool);
sys/dev/pci/drm/include/linux/radix-tree.h
80
bool radix_tree_iter_find(struct radix_tree_root *, struct radix_tree_iter *, void ***);
sys/dev/pci/drm/include/linux/rbtree.h
158
bool (*less)(struct rb_node *, const struct rb_node *))
sys/dev/pci/drm/include/linux/rbtree.h
178
bool (*less)(struct rb_node *, const struct rb_node *))
sys/dev/pci/drm/include/linux/reboot.h
23
orderly_poweroff(bool force)
sys/dev/pci/drm/include/linux/refcount.h
11
static inline bool
sys/dev/pci/drm/include/linux/refcount.h
17
static inline bool
sys/dev/pci/drm/include/linux/refcount.h
29
static inline bool
sys/dev/pci/drm/include/linux/scatterlist.h
33
bool end;
sys/dev/pci/drm/include/linux/scatterlist.h
77
static inline bool
sys/dev/pci/drm/include/linux/seq_buf.h
12
bool overflowed;
sys/dev/pci/drm/include/linux/seq_buf.h
32
static inline bool
sys/dev/pci/drm/include/linux/string.h
17
static inline bool
sys/dev/pci/drm/include/linux/string_choices.h
17
str_on_off(bool x)
sys/dev/pci/drm/include/linux/string_choices.h
25
str_enabled_disabled(bool x)
sys/dev/pci/drm/include/linux/string_choices.h
33
str_enable_disable(bool x)
sys/dev/pci/drm/include/linux/string_choices.h
41
str_read_write(bool x)
sys/dev/pci/drm/include/linux/string_choices.h
9
str_yes_no(bool x)
sys/dev/pci/drm/include/linux/suspend.h
35
static inline bool
sys/dev/pci/drm/include/linux/tracepoint.h
12
static inline bool trace_##name##_enabled(void) { return false; }
sys/dev/pci/drm/include/linux/tracepoint.h
19
static inline bool trace_##name##_enabled(void) { return false; }
sys/dev/pci/drm/include/linux/uuid.h
33
static inline bool
sys/dev/pci/drm/include/linux/uuid.h
39
static inline bool
sys/dev/pci/drm/include/linux/vga_switcheroo.h
18
const struct vga_switcheroo_client_ops *ops, bool x)
sys/dev/pci/drm/include/linux/vga_switcheroo.h
66
static inline bool
sys/dev/pci/drm/include/linux/vgaarb.h
16
vga_client_register(struct pci_dev *a, unsigned int (*f)(struct pci_dev *, bool))
sys/dev/pci/drm/include/linux/workqueue.h
108
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
161
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
168
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
175
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
183
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
191
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
201
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
211
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
220
bool flush_work(struct work_struct *);
sys/dev/pci/drm/include/linux/workqueue.h
221
bool flush_delayed_work(struct delayed_work *);
sys/dev/pci/drm/include/linux/workqueue.h
258
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
88
static inline bool
sys/dev/pci/drm/include/linux/workqueue.h
95
static inline bool
sys/dev/pci/drm/include/linux/ww_mutex.h
133
__ww_mutex_lock(struct ww_mutex *lock, struct ww_acquire_ctx *ctx, bool slow, bool intr) {
sys/dev/pci/drm/include/linux/ww_mutex.h
95
static inline bool
sys/dev/pci/drm/include/linux/ww_mutex.h
97
bool res = false;
sys/dev/pci/drm/include/linux/xarray.h
122
static inline bool
sys/dev/pci/drm/include/linux/xarray.h
188
static inline bool
sys/dev/pci/drm/include/linux/xarray.h
93
static inline bool
sys/dev/pci/drm/include/video/nomodeset.h
6
static inline bool
sys/dev/pci/drm/include/xen/xen.h
6
static inline bool
sys/dev/pci/drm/linux_radix.c
75
bool
sys/dev/pci/drm/radeon/atom.c
1380
bool atom_parse_data_header(struct atom_context *ctx, int index,
sys/dev/pci/drm/radeon/atom.c
1401
bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
sys/dev/pci/drm/radeon/atom.c
68
bool abort;
sys/dev/pci/drm/radeon/atom.h
152
bool atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
sys/dev/pci/drm/radeon/atom.h
154
bool atom_parse_cmd_header(struct atom_context *ctx, int index,
sys/dev/pci/drm/radeon/atombios_crtc.c
1150
bool bypass_lut = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
1470
bool bypass_lut = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2027
bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
sys/dev/pci/drm/radeon/atombios_crtc.c
2050
bool is_tvcv = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
2084
static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/radeon/atombios_crtc.c
571
bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
sys/dev/pci/drm/radeon/atombios_crtc.c
826
bool ss_enabled,
sys/dev/pci/drm/radeon/atombios_crtc.c
94
bool is_tv = false, is_cv = false;
sys/dev/pci/drm/radeon/atombios_crtc.c
955
static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
sys/dev/pci/drm/radeon/atombios_dp.c
382
bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
sys/dev/pci/drm/radeon/atombios_dp.c
499
bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
sys/dev/pci/drm/radeon/atombios_dp.c
539
bool tp3_supported;
sys/dev/pci/drm/radeon/atombios_dp.c
544
bool use_dpencoder;
sys/dev/pci/drm/radeon/atombios_dp.c
57
void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
sys/dev/pci/drm/radeon/atombios_dp.c
663
bool clock_recovery;
sys/dev/pci/drm/radeon/atombios_dp.c
730
bool channel_eq;
sys/dev/pci/drm/radeon/atombios_encoders.c
1011
bool is_dp = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
1373
bool
sys/dev/pci/drm/radeon/atombios_encoders.c
1526
atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/radeon/atombios_encoders.c
1660
bool travis_quirk = false;
sys/dev/pci/drm/radeon/atombios_encoders.c
2271
static bool
sys/dev/pci/drm/radeon/atombios_encoders.c
296
static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/btc_dpm.c
1304
bool enable)
sys/dev/pci/drm/radeon/btc_dpm.c
1346
bool enable)
sys/dev/pci/drm/radeon/btc_dpm.c
1445
bool enable)
sys/dev/pci/drm/radeon/btc_dpm.c
1500
bool enable)
sys/dev/pci/drm/radeon/btc_dpm.c
1555
bool enable)
sys/dev/pci/drm/radeon/btc_dpm.c
1589
bool btc_dpm_enabled(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/btc_dpm.c
1761
static bool btc_is_state_ulv_compatible(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/btc_dpm.c
1825
static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
sys/dev/pci/drm/radeon/btc_dpm.c
1827
bool result = true;
sys/dev/pci/drm/radeon/btc_dpm.c
2052
bool btc_dpm_vblank_too_short(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/btc_dpm.c
2070
bool disable_mclk_switching;
sys/dev/pci/drm/radeon/btc_dpm.c
2777
u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/btc_dpm.c
2788
u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/btc_dpm.h
57
bool btc_dpm_enabled(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/ci_dpm.c
1353
bool want_thermal_protection;
sys/dev/pci/drm/radeon/ci_dpm.c
1389
bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
1438
static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
1577
static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
158
static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/ci_dpm.c
1590
bool ac_power)
sys/dev/pci/drm/radeon/ci_dpm.c
1863
bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
1913
bool has_display)
sys/dev/pci/drm/radeon/ci_dpm.c
1921
bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
1977
static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
2289
bool voltage_found = false;
sys/dev/pci/drm/radeon/ci_dpm.c
2456
bool patch;
sys/dev/pci/drm/radeon/ci_dpm.c
2747
bool strobe_mode,
sys/dev/pci/drm/radeon/ci_dpm.c
2748
bool dll_state_on)
sys/dev/pci/drm/radeon/ci_dpm.c
2837
bool dll_state_on;
sys/dev/pci/drm/radeon/ci_dpm.c
3061
static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
3881
static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
3930
static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
3963
static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
3994
static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
4027
static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/ci_dpm.c
4095
static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/ci_dpm.c
4100
static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/ci_dpm.c
4357
static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
sys/dev/pci/drm/radeon/ci_dpm.c
4359
bool result = true;
sys/dev/pci/drm/radeon/ci_dpm.c
4489
bool patch;
sys/dev/pci/drm/radeon/ci_dpm.c
496
static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
586
static int ci_enable_didt(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
5943
u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/ci_dpm.c
5954
u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/ci_dpm.c
611
static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
669
static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
694
bool enable)
sys/dev/pci/drm/radeon/ci_dpm.c
720
bool adjust_polarity = false; /* ??? */
sys/dev/pci/drm/radeon/ci_dpm.c
734
void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/ci_dpm.c
746
bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/ci_dpm.c
771
bool disable_mclk_switching;
sys/dev/pci/drm/radeon/ci_dpm.c
877
bool enable)
sys/dev/pci/drm/radeon/ci_dpm.h
234
bool vddc_phase_shed_control;
sys/dev/pci/drm/radeon/ci_dpm.h
252
bool caps_power_containment;
sys/dev/pci/drm/radeon/ci_dpm.h
253
bool caps_cac;
sys/dev/pci/drm/radeon/ci_dpm.h
254
bool caps_sq_ramping;
sys/dev/pci/drm/radeon/ci_dpm.h
255
bool caps_db_ramping;
sys/dev/pci/drm/radeon/ci_dpm.h
256
bool caps_td_ramping;
sys/dev/pci/drm/radeon/ci_dpm.h
257
bool caps_tcp_ramping;
sys/dev/pci/drm/radeon/ci_dpm.h
258
bool caps_fps;
sys/dev/pci/drm/radeon/ci_dpm.h
259
bool caps_sclk_ds;
sys/dev/pci/drm/radeon/ci_dpm.h
260
bool caps_sclk_ss_support;
sys/dev/pci/drm/radeon/ci_dpm.h
261
bool caps_mclk_ss_support;
sys/dev/pci/drm/radeon/ci_dpm.h
262
bool caps_uvd_dpm;
sys/dev/pci/drm/radeon/ci_dpm.h
263
bool caps_vce_dpm;
sys/dev/pci/drm/radeon/ci_dpm.h
264
bool caps_samu_dpm;
sys/dev/pci/drm/radeon/ci_dpm.h
265
bool caps_acp_dpm;
sys/dev/pci/drm/radeon/ci_dpm.h
266
bool caps_automatic_dc_transition;
sys/dev/pci/drm/radeon/ci_dpm.h
267
bool caps_sclk_throttle_low_notification;
sys/dev/pci/drm/radeon/ci_dpm.h
268
bool caps_dynamic_ac_timing;
sys/dev/pci/drm/radeon/ci_dpm.h
269
bool caps_od_fuzzy_fan_control_support;
sys/dev/pci/drm/radeon/ci_dpm.h
271
bool thermal_protection;
sys/dev/pci/drm/radeon/ci_dpm.h
272
bool pcie_performance_request;
sys/dev/pci/drm/radeon/ci_dpm.h
273
bool dynamic_ss;
sys/dev/pci/drm/radeon/ci_dpm.h
274
bool dll_default_on;
sys/dev/pci/drm/radeon/ci_dpm.h
275
bool cac_enabled;
sys/dev/pci/drm/radeon/ci_dpm.h
276
bool uvd_enabled;
sys/dev/pci/drm/radeon/ci_dpm.h
277
bool battery_state;
sys/dev/pci/drm/radeon/ci_dpm.h
278
bool pspp_notify_required;
sys/dev/pci/drm/radeon/ci_dpm.h
279
bool mem_gddr5;
sys/dev/pci/drm/radeon/ci_dpm.h
280
bool enable_bapm_feature;
sys/dev/pci/drm/radeon/ci_dpm.h
281
bool enable_tdc_limit_feature;
sys/dev/pci/drm/radeon/ci_dpm.h
282
bool enable_pkg_pwr_tracking_feature;
sys/dev/pci/drm/radeon/ci_dpm.h
283
bool use_pcie_performance_levels;
sys/dev/pci/drm/radeon/ci_dpm.h
284
bool use_pcie_powersaving_levels;
sys/dev/pci/drm/radeon/ci_dpm.h
285
bool uvd_power_gated;
sys/dev/pci/drm/radeon/ci_dpm.h
292
bool fan_ctrl_is_in_default_mode;
sys/dev/pci/drm/radeon/ci_dpm.h
293
bool fan_is_controlled_by_smc;
sys/dev/pci/drm/radeon/ci_dpm.h
331
bool ci_is_smc_running(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/ci_dpm.h
48
bool dc_compatible;
sys/dev/pci/drm/radeon/ci_dpm.h
54
bool enabled;
sys/dev/pci/drm/radeon/ci_dpm.h
91
bool supported;
sys/dev/pci/drm/radeon/ci_smc.c
155
bool ci_is_smc_running(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/cik.c
141
bool enable);
sys/dev/pci/drm/radeon/cik.c
1977
bool new_smc = false;
sys/dev/pci/drm/radeon/cik.c
3611
bool cik_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/cik.c
3614
bool emit_wait)
sys/dev/pci/drm/radeon/cik.c
3863
static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
4217
static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
4512
bool use_doorbell = true;
sys/dev/pci/drm/radeon/cik.c
4745
static void cik_cp_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
5209
int cik_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/cik.c
5249
bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/cik.c
5758
bool enable)
sys/dev/pci/drm/radeon/cik.c
5769
static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
5990
static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
6026
static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
6120
bool enable)
sys/dev/pci/drm/radeon/cik.c
6137
bool enable)
sys/dev/pci/drm/radeon/cik.c
6154
bool enable)
sys/dev/pci/drm/radeon/cik.c
6175
bool enable)
sys/dev/pci/drm/radeon/cik.c
6203
bool enable)
sys/dev/pci/drm/radeon/cik.c
6229
bool enable)
sys/dev/pci/drm/radeon/cik.c
6247
bool enable)
sys/dev/pci/drm/radeon/cik.c
6263
bool enable)
sys/dev/pci/drm/radeon/cik.c
6279
u32 block, bool enable)
sys/dev/pci/drm/radeon/cik.c
6353
bool enable)
sys/dev/pci/drm/radeon/cik.c
6367
bool enable)
sys/dev/pci/drm/radeon/cik.c
6380
static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
6393
static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
6495
bool enable)
sys/dev/pci/drm/radeon/cik.c
6581
bool enable)
sys/dev/pci/drm/radeon/cik.c
6595
bool enable)
sys/dev/pci/drm/radeon/cik.c
6660
static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik.c
7547
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/cik.c
7548
bool queue_dp = false;
sys/dev/pci/drm/radeon/cik.c
7549
bool queue_reset = false;
sys/dev/pci/drm/radeon/cik.c
7551
bool queue_thermal = false;
sys/dev/pci/drm/radeon/cik.c
8926
bool interlaced; /* mode is interlaced */
sys/dev/pci/drm/radeon/cik.c
9174
static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
sys/dev/pci/drm/radeon/cik.c
9194
static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
sys/dev/pci/drm/radeon/cik.c
9212
static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
sys/dev/pci/drm/radeon/cik.c
9665
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/radeon/cik.c
9666
bool disable_clkreq = false;
sys/dev/pci/drm/radeon/cik.c
9707
bool clk_req_support;
sys/dev/pci/drm/radeon/cik.h
31
void cik_update_cg(struct radeon_device *rdev, u32 block, bool enable);
sys/dev/pci/drm/radeon/cik.h
38
void cik_sdma_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/cik_sdma.c
227
bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/cik_sdma.c
230
bool emit_wait)
sys/dev/pci/drm/radeon/cik_sdma.c
303
static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik_sdma.c
330
void cik_sdma_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/cik_sdma.c
774
bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/cypress_dpm.c
119
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.c
171
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.c
2156
bool cypress_dpm_vblank_too_short(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/cypress_dpm.c
220
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.c
244
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.c
253
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.c
262
bool has_display)
sys/dev/pci/drm/radeon/cypress_dpm.c
300
u8 perf_req, bool advertise)
sys/dev/pci/drm/radeon/cypress_dpm.c
426
bool strobe_mode = false;
sys/dev/pci/drm/radeon/cypress_dpm.c
475
bool strobe_mode, bool dll_state_on)
sys/dev/pci/drm/radeon/cypress_dpm.c
49
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.c
614
u32 memory_clock, bool strobe_mode)
sys/dev/pci/drm/radeon/cypress_dpm.c
686
bool dll_state_on;
sys/dev/pci/drm/radeon/cypress_dpm.c
86
bool enable)
sys/dev/pci/drm/radeon/cypress_dpm.h
141
bool enable);
sys/dev/pci/drm/radeon/cypress_dpm.h
148
bool has_display);
sys/dev/pci/drm/radeon/cypress_dpm.h
150
bool enable);
sys/dev/pci/drm/radeon/cypress_dpm.h
152
bool enable);
sys/dev/pci/drm/radeon/cypress_dpm.h
157
u32 memory_clock, bool strobe_mode);
sys/dev/pci/drm/radeon/cypress_dpm.h
43
bool supported;
sys/dev/pci/drm/radeon/cypress_dpm.h
65
bool vddci_control;
sys/dev/pci/drm/radeon/cypress_dpm.h
66
bool dynamic_ac_timing;
sys/dev/pci/drm/radeon/cypress_dpm.h
67
bool abm;
sys/dev/pci/drm/radeon/cypress_dpm.h
68
bool mcls;
sys/dev/pci/drm/radeon/cypress_dpm.h
69
bool light_sleep;
sys/dev/pci/drm/radeon/cypress_dpm.h
70
bool memory_transition;
sys/dev/pci/drm/radeon/cypress_dpm.h
71
bool pcie_performance_request;
sys/dev/pci/drm/radeon/cypress_dpm.h
72
bool pcie_performance_request_registered;
sys/dev/pci/drm/radeon/cypress_dpm.h
73
bool sclk_deep_sleep;
sys/dev/pci/drm/radeon/cypress_dpm.h
74
bool dll_default_on;
sys/dev/pci/drm/radeon/cypress_dpm.h
75
bool ls_clock_gating;
sys/dev/pci/drm/radeon/cypress_dpm.h
76
bool smu_uvd_hs;
sys/dev/pci/drm/radeon/cypress_dpm.h
77
bool uvd_enabled;
sys/dev/pci/drm/radeon/dce3_1_afmt.c
224
void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
sys/dev/pci/drm/radeon/evergreen.c
1348
static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
sys/dev/pci/drm/radeon/evergreen.c
1356
static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
sys/dev/pci/drm/radeon/evergreen.c
1417
bool async)
sys/dev/pci/drm/radeon/evergreen.c
1445
bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc_id)
sys/dev/pci/drm/radeon/evergreen.c
1726
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
sys/dev/pci/drm/radeon/evergreen.c
1745
bool connected = evergreen_hpd_sense(rdev, hpd);
sys/dev/pci/drm/radeon/evergreen.c
1942
bool interlaced; /* mode is interlaced */
sys/dev/pci/drm/radeon/evergreen.c
2111
static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
sys/dev/pci/drm/radeon/evergreen.c
2120
static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
sys/dev/pci/drm/radeon/evergreen.c
2129
static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
sys/dev/pci/drm/radeon/evergreen.c
2563
static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/evergreen.c
2574
bool is_enabled = false;
sys/dev/pci/drm/radeon/evergreen.c
2575
bool found_crtc = false;
sys/dev/pci/drm/radeon/evergreen.c
3796
bool evergreen_is_display_hung(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/evergreen.c
4050
int evergreen_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/evergreen.c
4090
bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/evergreen.c
4710
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/evergreen.c
4711
bool queue_hdmi = false;
sys/dev/pci/drm/radeon/evergreen.c
4712
bool queue_dp = false;
sys/dev/pci/drm/radeon/evergreen.c
4713
bool queue_thermal = false;
sys/dev/pci/drm/radeon/evergreen.c
5394
bool disable_l0s, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/radeon/evergreen.c
5400
bool fusion_platform = false;
sys/dev/pci/drm/radeon/evergreen.h
33
bool evergreen_is_display_hung(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/evergreen_cs.c
1757
static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg)
sys/dev/pci/drm/radeon/evergreen_cs.c
3317
static bool evergreen_vm_reg_valid(u32 reg)
sys/dev/pci/drm/radeon/evergreen_cs.c
83
bool sx_misc_kill_all_prims;
sys/dev/pci/drm/radeon/evergreen_cs.c
84
bool cb_dirty;
sys/dev/pci/drm/radeon/evergreen_cs.c
85
bool db_dirty;
sys/dev/pci/drm/radeon/evergreen_cs.c
86
bool streamout_dirty;
sys/dev/pci/drm/radeon/evergreen_dma.c
170
bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/evergreen_hdmi.c
391
void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
sys/dev/pci/drm/radeon/evergreen_hdmi.c
402
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/radeon/evergreen_hdmi.c
442
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/radeon/evergreen_hdmi.h
47
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
sys/dev/pci/drm/radeon/evergreen_hdmi.h
48
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);
sys/dev/pci/drm/radeon/evergreen_hdmi.h
67
void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
sys/dev/pci/drm/radeon/kv_dpm.c
1002
void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1014
static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1219
static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1225
static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1231
static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1237
static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1243
static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1336
static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1400
static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1431
void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1459
static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1482
static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1502
static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
sys/dev/pci/drm/radeon/kv_dpm.c
1611
bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
1943
bool force_high;
sys/dev/pci/drm/radeon/kv_dpm.c
2051
u32 index, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
206
static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
2080
bool force_high;
sys/dev/pci/drm/radeon/kv_dpm.c
248
static int kv_enable_didt(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
2679
u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/kv_dpm.c
2690
u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/kv_dpm.c
275
static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
38
bool enable);
sys/dev/pci/drm/radeon/kv_dpm.c
478
u32 index, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.c
519
static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
sys/dev/pci/drm/radeon/kv_dpm.c
57
void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/kv_dpm.c
58
static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/kv_dpm.c
59
static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/kv_dpm.c
60
static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/kv_dpm.c
65
u32 block, bool enable);
sys/dev/pci/drm/radeon/kv_dpm.c
967
static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_dpm.h
111
bool enable_nb_ps_policy;
sys/dev/pci/drm/radeon/kv_dpm.h
112
bool disable_nb_ps3_in_battery;
sys/dev/pci/drm/radeon/kv_dpm.h
113
bool video_start;
sys/dev/pci/drm/radeon/kv_dpm.h
114
bool battery_state;
sys/dev/pci/drm/radeon/kv_dpm.h
118
bool cac_enabled;
sys/dev/pci/drm/radeon/kv_dpm.h
119
bool bapm_enable;
sys/dev/pci/drm/radeon/kv_dpm.h
153
bool uvd_power_gated;
sys/dev/pci/drm/radeon/kv_dpm.h
154
bool vce_power_gated;
sys/dev/pci/drm/radeon/kv_dpm.h
155
bool acp_power_gated;
sys/dev/pci/drm/radeon/kv_dpm.h
156
bool samu_power_gated;
sys/dev/pci/drm/radeon/kv_dpm.h
157
bool nb_dpm_enabled;
sys/dev/pci/drm/radeon/kv_dpm.h
159
bool enable_didt;
sys/dev/pci/drm/radeon/kv_dpm.h
160
bool enable_dpm;
sys/dev/pci/drm/radeon/kv_dpm.h
161
bool enable_auto_thermal_throttling;
sys/dev/pci/drm/radeon/kv_dpm.h
162
bool enable_nb_dpm;
sys/dev/pci/drm/radeon/kv_dpm.h
164
bool caps_cac;
sys/dev/pci/drm/radeon/kv_dpm.h
165
bool caps_power_containment;
sys/dev/pci/drm/radeon/kv_dpm.h
166
bool caps_sq_ramping;
sys/dev/pci/drm/radeon/kv_dpm.h
167
bool caps_db_ramping;
sys/dev/pci/drm/radeon/kv_dpm.h
168
bool caps_td_ramping;
sys/dev/pci/drm/radeon/kv_dpm.h
169
bool caps_tcp_ramping;
sys/dev/pci/drm/radeon/kv_dpm.h
170
bool caps_sclk_throttle_low_notification;
sys/dev/pci/drm/radeon/kv_dpm.h
171
bool caps_fps;
sys/dev/pci/drm/radeon/kv_dpm.h
172
bool caps_uvd_dpm;
sys/dev/pci/drm/radeon/kv_dpm.h
173
bool caps_uvd_pg;
sys/dev/pci/drm/radeon/kv_dpm.h
174
bool caps_vce_pg;
sys/dev/pci/drm/radeon/kv_dpm.h
175
bool caps_samu_pg;
sys/dev/pci/drm/radeon/kv_dpm.h
176
bool caps_acp_pg;
sys/dev/pci/drm/radeon/kv_dpm.h
177
bool caps_stable_p_state;
sys/dev/pci/drm/radeon/kv_dpm.h
178
bool caps_enable_dfs_bypass;
sys/dev/pci/drm/radeon/kv_dpm.h
179
bool caps_sclk_ds;
sys/dev/pci/drm/radeon/kv_dpm.h
194
int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/kv_dpm.h
195
int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/kv_dpm.h
84
bool need_dfs_bypass;
sys/dev/pci/drm/radeon/kv_smc.c
101
int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/kv_smc.c
109
int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ni.c
1435
static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/ni.c
1930
int cayman_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/ni.c
1965
bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/ni_dma.c
286
bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/ni_dpm.c
1026
bool ac_power)
sys/dev/pci/drm/radeon/ni_dpm.c
1433
bool adjust_polarity,
sys/dev/pci/drm/radeon/ni_dpm.c
2164
bool strobe_mode,
sys/dev/pci/drm/radeon/ni_dpm.c
2165
bool dll_state_on)
sys/dev/pci/drm/radeon/ni_dpm.c
2321
bool dll_state_on;
sys/dev/pci/drm/radeon/ni_dpm.c
2548
bool enable_sq_ramping = ni_pi->enable_sq_ramping;
sys/dev/pci/drm/radeon/ni_dpm.c
2600
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.c
2771
static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
sys/dev/pci/drm/radeon/ni_dpm.c
2773
bool result = true;
sys/dev/pci/drm/radeon/ni_dpm.c
3379
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.c
3419
u8 perf_req, bool advertise)
sys/dev/pci/drm/radeon/ni_dpm.c
3459
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.c
3498
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.c
4361
u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/ni_dpm.c
4372
u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/ni_dpm.c
771
bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/ni_dpm.c
790
bool disable_mclk_switching;
sys/dev/pci/drm/radeon/ni_dpm.c
916
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.c
944
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.c
972
bool enable)
sys/dev/pci/drm/radeon/ni_dpm.h
165
bool enable_power_containment_by_default;
sys/dev/pci/drm/radeon/ni_dpm.h
170
bool dc_compatible;
sys/dev/pci/drm/radeon/ni_dpm.h
181
bool use_power_boost_limit;
sys/dev/pci/drm/radeon/ni_dpm.h
182
bool support_cac_long_term_average;
sys/dev/pci/drm/radeon/ni_dpm.h
183
bool cac_enabled;
sys/dev/pci/drm/radeon/ni_dpm.h
184
bool cac_configuration_required;
sys/dev/pci/drm/radeon/ni_dpm.h
185
bool driver_calculate_cac_leakage;
sys/dev/pci/drm/radeon/ni_dpm.h
186
bool pc_enabled;
sys/dev/pci/drm/radeon/ni_dpm.h
187
bool enable_power_containment;
sys/dev/pci/drm/radeon/ni_dpm.h
188
bool enable_cac;
sys/dev/pci/drm/radeon/ni_dpm.h
189
bool enable_sq_ramping;
sys/dev/pci/drm/radeon/ni_dpm.h
244
bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/r100.c
164
void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
sys/dev/pci/drm/radeon/r100.c
206
bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
sys/dev/pci/drm/radeon/r100.c
2548
bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/r100.c
2586
int r100_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/r100.c
2644
bool force_dac2 = false;
sys/dev/pci/drm/radeon/r100.c
2842
void r100_vga_set_state(struct radeon_device *rdev, bool state)
sys/dev/pci/drm/radeon/r100.c
523
bool r100_gui_idle(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/r100.c
541
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
sys/dev/pci/drm/radeon/r100.c
543
bool connected = false;
sys/dev/pci/drm/radeon/r100.c
572
bool connected = r100_hpd_sense(rdev, hpd);
sys/dev/pci/drm/radeon/r100.c
78
static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
sys/dev/pci/drm/radeon/r100.c
784
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/r100.c
891
bool r100_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/r100.c
894
bool emit_wait)
sys/dev/pci/drm/radeon/r100.c
93
static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
sys/dev/pci/drm/radeon/r100_track.h
50
bool use_pitch;
sys/dev/pci/drm/radeon/r100_track.h
51
bool enabled;
sys/dev/pci/drm/radeon/r100_track.h
52
bool lookup_disable;
sys/dev/pci/drm/radeon/r100_track.h
53
bool roundup_w;
sys/dev/pci/drm/radeon/r100_track.h
54
bool roundup_h;
sys/dev/pci/drm/radeon/r100_track.h
74
bool z_enabled;
sys/dev/pci/drm/radeon/r100_track.h
75
bool separate_cube;
sys/dev/pci/drm/radeon/r100_track.h
76
bool zb_cb_clear;
sys/dev/pci/drm/radeon/r100_track.h
77
bool blend_read_enable;
sys/dev/pci/drm/radeon/r100_track.h
78
bool cb_dirty;
sys/dev/pci/drm/radeon/r100_track.h
79
bool zb_dirty;
sys/dev/pci/drm/radeon/r100_track.h
80
bool tex_dirty;
sys/dev/pci/drm/radeon/r100_track.h
81
bool aa_dirty;
sys/dev/pci/drm/radeon/r100_track.h
82
bool aaresolve;
sys/dev/pci/drm/radeon/r300.c
415
int r300_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/r300.c
890
bool enabled;
sys/dev/pci/drm/radeon/r600.c
1554
void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
sys/dev/pci/drm/radeon/r600.c
1586
static bool r600_is_display_hung(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/r600.c
1881
int r600_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/r600.c
1921
bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/r600.c
2926
bool r600_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/r600.c
2929
bool emit_wait)
sys/dev/pci/drm/radeon/r600.c
3190
void r600_vga_set_state(struct radeon_device *rdev, bool state)
sys/dev/pci/drm/radeon/r600.c
4098
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/r600.c
4099
bool queue_hdmi = false;
sys/dev/pci/drm/radeon/r600.c
4100
bool queue_thermal = false;
sys/dev/pci/drm/radeon/r600.c
795
bool r600_gui_idle(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/r600.c
804
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
sys/dev/pci/drm/radeon/r600.c
806
bool connected = false;
sys/dev/pci/drm/radeon/r600.c
863
bool connected = r600_hpd_sense(rdev, hpd);
sys/dev/pci/drm/radeon/r600.h
45
void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
sys/dev/pci/drm/radeon/r600.h
53
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
sys/dev/pci/drm/radeon/r600_cs.c
1489
bool is_array;
sys/dev/pci/drm/radeon/r600_cs.c
1615
static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
sys/dev/pci/drm/radeon/r600_cs.c
177
bool r600_fmt_is_valid_color(u32 format)
sys/dev/pci/drm/radeon/r600_cs.c
188
bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
sys/dev/pci/drm/radeon/r600_cs.c
61
bool is_resolve;
sys/dev/pci/drm/radeon/r600_cs.c
77
bool sx_misc_kill_all_prims;
sys/dev/pci/drm/radeon/r600_cs.c
78
bool cb_dirty;
sys/dev/pci/drm/radeon/r600_cs.c
79
bool db_dirty;
sys/dev/pci/drm/radeon/r600_cs.c
80
bool streamout_dirty;
sys/dev/pci/drm/radeon/r600_dma.c
207
bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/r600_dma.c
312
bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/r600_dma.c
315
bool emit_wait)
sys/dev/pci/drm/radeon/r600_dpm.c
240
void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
264
void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
272
void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
285
void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
293
bool r600_dynamicpm_enabled(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/r600_dpm.c
301
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
309
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
317
void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
444
u32 index, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
455
u32 index, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
466
u32 index, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
560
enum r600_power_level index, bool enable)
sys/dev/pci/drm/radeon/r600_dpm.c
612
enum r600_power_level index, bool compatible)
sys/dev/pci/drm/radeon/r600_dpm.c
722
bool r600_is_uvd_state(u32 class, u32 class2)
sys/dev/pci/drm/radeon/r600_dpm.c
762
bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
sys/dev/pci/drm/radeon/r600_dpm.h
138
bool r600_is_uvd_state(u32 class, u32 class2);
sys/dev/pci/drm/radeon/r600_dpm.h
142
void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
143
void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
144
void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
146
void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
147
bool r600_dynamicpm_enabled(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/r600_dpm.h
148
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
149
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
150
void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
174
u32 index, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
176
u32 index, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
178
u32 index, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
197
enum r600_power_level index, bool enable);
sys/dev/pci/drm/radeon/r600_dpm.h
208
enum r600_power_level index, bool compatible);
sys/dev/pci/drm/radeon/r600_dpm.h
220
bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
sys/dev/pci/drm/radeon/r600_hdmi.c
122
bool changed = false;
sys/dev/pci/drm/radeon/r600_hdmi.c
263
static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
sys/dev/pci/drm/radeon/r600_hdmi.c
372
void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
sys/dev/pci/drm/radeon/r600_hdmi.c
448
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
sys/dev/pci/drm/radeon/radeon.h
1000
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
sys/dev/pci/drm/radeon/radeon.h
1141
bool enabled;
sys/dev/pci/drm/radeon/radeon.h
1142
bool use_event;
sys/dev/pci/drm/radeon/radeon.h
1273
bool active_high; /* voltage drop is active when bit is high */
sys/dev/pci/drm/radeon/radeon.h
1277
bool vddci_enabled;
sys/dev/pci/drm/radeon/radeon.h
1353
bool vce_active;
sys/dev/pci/drm/radeon/radeon.h
1367
bool high_to_low;
sys/dev/pci/drm/radeon/radeon.h
1515
bool ucode_fan_control;
sys/dev/pci/drm/radeon/radeon.h
1568
bool single_display;
sys/dev/pci/drm/radeon/radeon.h
1579
bool power_control;
sys/dev/pci/drm/radeon/radeon.h
1580
bool ac_power;
sys/dev/pci/drm/radeon/radeon.h
1582
bool thermal_active;
sys/dev/pci/drm/radeon/radeon.h
1583
bool uvd_active;
sys/dev/pci/drm/radeon/radeon.h
1584
bool vce_active;
sys/dev/pci/drm/radeon/radeon.h
1594
void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/radeon.h
1595
void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/radeon.h
1604
bool vblank_sync;
sys/dev/pci/drm/radeon/radeon.h
1641
bool dynpm_can_upclock;
sys/dev/pci/drm/radeon/radeon.h
1642
bool dynpm_can_downclock;
sys/dev/pci/drm/radeon/radeon.h
1651
bool no_fan;
sys/dev/pci/drm/radeon/radeon.h
1656
bool dpm_enabled;
sys/dev/pci/drm/radeon/radeon.h
1657
bool sysfs_initialized;
sys/dev/pci/drm/radeon/radeon.h
1678
bool fw_header_present;
sys/dev/pci/drm/radeon/radeon.h
1744
bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon.h
1747
bool emit_wait);
sys/dev/pci/drm/radeon/radeon.h
1761
bool connected;
sys/dev/pci/drm/radeon/radeon.h
1766
bool enabled;
sys/dev/pci/drm/radeon/radeon.h
1773
bool component_registered;
sys/dev/pci/drm/radeon/radeon.h
1829
bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
sys/dev/pci/drm/radeon/radeon.h
1830
struct radeon_semaphore *semaphore, bool emit_wait);
sys/dev/pci/drm/radeon/radeon.h
1837
bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon.h
1851
void (*vga_set_state)(struct radeon_device *rdev, bool state);
sys/dev/pci/drm/radeon/radeon.h
1852
int (*asic_reset)(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon.h
1856
bool (*gui_idle)(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
1911
void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
sys/dev/pci/drm/radeon/radeon.h
1948
bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
sys/dev/pci/drm/radeon/radeon.h
1981
u32 (*get_sclk)(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon.h
1982
u32 (*get_mclk)(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon.h
1986
bool (*vblank_too_short)(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
1987
void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/radeon.h
1988
void (*enable_bapm)(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/radeon.h
1999
void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
sys/dev/pci/drm/radeon/radeon.h
2000
bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
sys/dev/pci/drm/radeon/radeon.h
2258
bool enabled;
sys/dev/pci/drm/radeon/radeon.h
2263
bool display_switch;
sys/dev/pci/drm/radeon/radeon.h
2264
bool expansion_mode_change;
sys/dev/pci/drm/radeon/radeon.h
2265
bool thermal_state;
sys/dev/pci/drm/radeon/radeon.h
2266
bool forced_power_state;
sys/dev/pci/drm/radeon/radeon.h
2267
bool system_power_state;
sys/dev/pci/drm/radeon/radeon.h
2268
bool display_conf_change;
sys/dev/pci/drm/radeon/radeon.h
2269
bool px_gfx_switch;
sys/dev/pci/drm/radeon/radeon.h
2270
bool brightness_change;
sys/dev/pci/drm/radeon/radeon.h
2271
bool dgpu_display_event;
sys/dev/pci/drm/radeon/radeon.h
2275
bool system_params;
sys/dev/pci/drm/radeon/radeon.h
2276
bool sbios_requests;
sys/dev/pci/drm/radeon/radeon.h
2277
bool select_active_disp;
sys/dev/pci/drm/radeon/radeon.h
2278
bool lid_state;
sys/dev/pci/drm/radeon/radeon.h
2279
bool get_tv_standard;
sys/dev/pci/drm/radeon/radeon.h
2280
bool set_tv_standard;
sys/dev/pci/drm/radeon/radeon.h
2281
bool get_panel_expansion_mode;
sys/dev/pci/drm/radeon/radeon.h
2282
bool set_panel_expansion_mode;
sys/dev/pci/drm/radeon/radeon.h
2283
bool temperature_change;
sys/dev/pci/drm/radeon/radeon.h
2284
bool graphics_device_types;
sys/dev/pci/drm/radeon/radeon.h
2295
bool get_ext_state;
sys/dev/pci/drm/radeon/radeon.h
2296
bool pcie_perf_req;
sys/dev/pci/drm/radeon/radeon.h
2297
bool pcie_dev_rdy;
sys/dev/pci/drm/radeon/radeon.h
2298
bool pcie_bus_width;
sys/dev/pci/drm/radeon/radeon.h
2361
bool is_atom_bios;
sys/dev/pci/drm/radeon/radeon.h
2415
bool ib_pool_ready;
sys/dev/pci/drm/radeon/radeon.h
2426
bool shutdown;
sys/dev/pci/drm/radeon/radeon.h
2427
bool need_swiotlb;
sys/dev/pci/drm/radeon/radeon.h
2428
bool accel_working;
sys/dev/pci/drm/radeon/radeon.h
2429
bool fastfb_working; /* IGP feature*/
sys/dev/pci/drm/radeon/radeon.h
2430
bool needs_reset, in_reset;
sys/dev/pci/drm/radeon/radeon.h
2443
bool new_fw;
sys/dev/pci/drm/radeon/radeon.h
2454
bool has_uvd;
sys/dev/pci/drm/radeon/radeon.h
2455
bool has_vce;
sys/dev/pci/drm/radeon/radeon.h
2479
bool have_disp_power_ref;
sys/dev/pci/drm/radeon/radeon.h
2487
bool radeon_is_px(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon.h
2500
bool always_indirect)
sys/dev/pci/drm/radeon/radeon.h
2509
bool always_indirect)
sys/dev/pci/drm/radeon/radeon.h
260
bool radeon_get_bios(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
2833
extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
sys/dev/pci/drm/radeon/radeon.h
2837
extern bool radeon_card_posted(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
2840
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
2850
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
sys/dev/pci/drm/radeon/radeon.h
2854
extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
sys/dev/pci/drm/radeon/radeon.h
2855
extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
sys/dev/pci/drm/radeon/radeon.h
2856
bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
sys/dev/pci/drm/radeon/radeon.h
2859
extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
sys/dev/pci/drm/radeon/radeon.h
2860
extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
sys/dev/pci/drm/radeon/radeon.h
2861
bool fbcon, bool freeze);
sys/dev/pci/drm/radeon/radeon.h
2937
bool r600_fmt_is_valid_color(u32 format);
sys/dev/pci/drm/radeon/radeon.h
2938
bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
sys/dev/pci/drm/radeon/radeon.h
2977
extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
2979
u8 perf_req, bool advertise);
sys/dev/pci/drm/radeon/radeon.h
2989
bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
sys/dev/pci/drm/radeon/radeon.h
3002
bool enable, const char *name,
sys/dev/pci/drm/radeon/radeon.h
307
bool strobe_mode,
sys/dev/pci/drm/radeon/radeon.h
311
bool strobe_mode,
sys/dev/pci/drm/radeon/radeon.h
346
bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon.h
361
bool gddr5, u8 module_index,
sys/dev/pci/drm/radeon/radeon.h
381
bool initialized, delayed_irq;
sys/dev/pci/drm/radeon/radeon.h
392
bool is_vm_update;
sys/dev/pci/drm/radeon/radeon.h
403
bool radeon_fence_signaled(struct radeon_fence *fence);
sys/dev/pci/drm/radeon/radeon.h
404
long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
sys/dev/pci/drm/radeon/radeon.h
405
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
sys/dev/pci/drm/radeon/radeon.h
411
bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
sys/dev/pci/drm/radeon/radeon.h
433
static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
sys/dev/pci/drm/radeon/radeon.h
463
bool initialized;
sys/dev/pci/drm/radeon/radeon.h
469
bool shared;
sys/dev/pci/drm/radeon/radeon.h
541
int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);
sys/dev/pci/drm/radeon/radeon.h
547
u32 flags, bool kernel,
sys/dev/pci/drm/radeon/radeon.h
568
bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
sys/dev/pci/drm/radeon/radeon.h
570
bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
sys/dev/pci/drm/radeon/radeon.h
591
bool shared);
sys/dev/pci/drm/radeon/radeon.h
624
bool ready;
sys/dev/pci/drm/radeon/radeon.h
661
bool vram_is_ddr;
sys/dev/pci/drm/radeon/radeon.h
662
bool igp_sideport_enabled;
sys/dev/pci/drm/radeon/radeon.h
667
bool radeon_combios_sideport_present(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
668
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon.h
676
bool free[32];
sys/dev/pci/drm/radeon/radeon.h
715
bool async;
sys/dev/pci/drm/radeon/radeon.h
763
bool installed;
sys/dev/pci/drm/radeon/radeon.h
766
bool crtc_vblank_int[RADEON_MAX_CRTCS];
sys/dev/pci/drm/radeon/radeon.h
769
bool hpd[RADEON_MAX_HPD_PINS];
sys/dev/pci/drm/radeon/radeon.h
770
bool afmt[RADEON_MAX_AFMT_BLOCKS];
sys/dev/pci/drm/radeon/radeon.h
772
bool dpm_thermal;
sys/dev/pci/drm/radeon/radeon.h
778
bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
sys/dev/pci/drm/radeon/radeon.h
799
bool is_const_ib;
sys/dev/pci/drm/radeon/radeon.h
821
bool ready;
sys/dev/pci/drm/radeon/radeon.h
925
bool enabled;
sys/dev/pci/drm/radeon/radeon.h
948
bool enabled;
sys/dev/pci/drm/radeon/radeon.h
981
struct radeon_ib *const_ib, bool hdp_flush);
sys/dev/pci/drm/radeon/radeon.h
986
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon.h
992
bool hdp_flush);
sys/dev/pci/drm/radeon/radeon.h
994
bool hdp_flush);
sys/dev/pci/drm/radeon/radeon_acpi.c
42
bool radeon_atpx_dgpu_req_power_for_displays(void);
sys/dev/pci/drm/radeon/radeon_acpi.c
44
static inline bool radeon_atpx_dgpu_req_power_for_displays(void) { return false; }
sys/dev/pci/drm/radeon/radeon_acpi.c
546
bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_acpi.c
600
u8 perf_req, bool advertise)
sys/dev/pci/drm/radeon/radeon_acpi.h
459
bool radeon_has_atpx_dgpu_power_cntl(void);
sys/dev/pci/drm/radeon/radeon_acpi.h
460
bool radeon_is_atpx_hybrid(void);
sys/dev/pci/drm/radeon/radeon_acpi.h
461
bool radeon_has_atpx(void);
sys/dev/pci/drm/radeon/radeon_acpi.h
462
bool radeon_atpx_dgpu_req_power_for_displays(void);
sys/dev/pci/drm/radeon/radeon_agp.c
248
bool is_v3;
sys/dev/pci/drm/radeon/radeon_asic.h
134
extern bool r100_gui_idle(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
141
u64 crtc_base, bool async);
sys/dev/pci/drm/radeon/radeon_asic.h
142
extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
sys/dev/pci/drm/radeon/radeon_asic.h
171
extern int r300_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
228
extern int rs600_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
246
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
sys/dev/pci/drm/radeon/radeon_asic.h
253
u64 crtc_base, bool async);
sys/dev/pci/drm/radeon/radeon_asic.h
254
extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
sys/dev/pci/drm/radeon/radeon_asic.h
280
bool crtc_enabled[2];
sys/dev/pci/drm/radeon/radeon_asic.h
314
void r600_vga_set_state(struct radeon_device *rdev, bool state);
sys/dev/pci/drm/radeon/radeon_asic.h
324
bool r600_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
327
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
330
bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
333
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
335
bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
sys/dev/pci/drm/radeon/radeon_asic.h
336
bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
337
int r600_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
357
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
sys/dev/pci/drm/radeon/radeon_asic.h
361
extern bool r600_gui_idle(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
370
bool r600_card_posted(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
428
u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
429
u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
446
u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
447
u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
466
bool async);
sys/dev/pci/drm/radeon/radeon_asic.h
467
bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
sys/dev/pci/drm/radeon/radeon_asic.h
487
u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
488
u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
495
bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
505
bool crtc_enabled[RADEON_MAX_CRTCS];
sys/dev/pci/drm/radeon/radeon_asic.h
513
bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
514
bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
515
int evergreen_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
520
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
sys/dev/pci/drm/radeon/radeon_asic.h
536
u64 crtc_base, bool async);
sys/dev/pci/drm/radeon/radeon_asic.h
537
extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
sys/dev/pci/drm/radeon/radeon_asic.h
561
bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
570
u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
571
u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
572
bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
587
u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
588
u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
609
int cayman_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
620
bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
sys/dev/pci/drm/radeon/radeon_asic.h
621
bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
sys/dev/pci/drm/radeon/radeon_asic.h
65
void r100_vga_set_state(struct radeon_device *rdev, bool state);
sys/dev/pci/drm/radeon/radeon_asic.h
66
bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
665
u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
666
u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
67
int r100_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
673
bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
686
u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
687
u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
694
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/radeon_asic.h
713
bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
714
bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
715
int si_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
78
bool r100_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
790
bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
793
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
805
bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
sys/dev/pci/drm/radeon/radeon_asic.h
81
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
810
bool cik_semaphore_ring_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
813
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
819
bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
sys/dev/pci/drm/radeon/radeon_asic.h
820
int cik_asic_reset(struct radeon_device *rdev, bool hard);
sys/dev/pci/drm/radeon/radeon_asic.h
883
u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
884
u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
891
bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_asic.h
892
void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/radeon_asic.h
913
u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
914
u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
sys/dev/pci/drm/radeon/radeon_asic.h
921
void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
sys/dev/pci/drm/radeon/radeon_asic.h
922
void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/radeon_asic.h
944
bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
947
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
954
bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
957
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
960
bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_asic.h
963
bool emit_wait);
sys/dev/pci/drm/radeon/radeon_asic.h
99
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
sys/dev/pci/drm/radeon/radeon_atombios.c
1129
bool radeon_atom_get_clock_info(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_atombios.c
1299
bool radeon_atombios_sideport_present(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_atombios.c
1332
bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_atombios.c
1381
bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_atombios.c
1509
bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_atombios.c
1697
bool bad_record = false;
sys/dev/pci/drm/radeon/radeon_atombios.c
1793
bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
sys/dev/pci/drm/radeon/radeon_atombios.c
2483
static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_atombios.c
2588
bool valid;
sys/dev/pci/drm/radeon/radeon_atombios.c
2681
bool valid;
sys/dev/pci/drm/radeon/radeon_atombios.c
281
static bool radeon_atom_apply_quirks(struct drm_device *dev,
sys/dev/pci/drm/radeon/radeon_atombios.c
2846
bool strobe_mode,
sys/dev/pci/drm/radeon/radeon_atombios.c
2962
bool strobe_mode,
sys/dev/pci/drm/radeon/radeon_atombios.c
3449
bool
sys/dev/pci/drm/radeon/radeon_atombios.c
3919
bool gddr5, u8 module_index,
sys/dev/pci/drm/radeon/radeon_atombios.c
4143
void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
sys/dev/pci/drm/radeon/radeon_atombios.c
4172
bool connected)
sys/dev/pci/drm/radeon/radeon_atombios.c
4411
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
sys/dev/pci/drm/radeon/radeon_atombios.c
521
bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_atombios.c
880
bool valid;
sys/dev/pci/drm/radeon/radeon_atombios.c
888
bool radeon_get_atom_connector_info_from_supported_devices_table(struct
sys/dev/pci/drm/radeon/radeon_atombios.h
37
bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
sys/dev/pci/drm/radeon/radeon_audio.c
622
static void radeon_audio_set_mute(struct drm_encoder *encoder, bool mute)
sys/dev/pci/drm/radeon/radeon_audio.c
750
int pipe, bool *enabled,
sys/dev/pci/drm/radeon/radeon_audio.h
63
void (*set_mute)(struct drm_encoder *encoder, u32 offset, bool mute);
sys/dev/pci/drm/radeon/radeon_audio.h
66
void (*dpms)(struct drm_encoder *encoder, bool mode);
sys/dev/pci/drm/radeon/radeon_audio.h
95
void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
sys/dev/pci/drm/radeon/radeon_bios.c
120
static bool radeon_read_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
149
static bool radeon_read_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
189
static bool radeon_read_platform_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
220
static bool radeon_read_platform_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
314
static bool radeon_atrm_get_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
322
bool found = false;
sys/dev/pci/drm/radeon/radeon_bios.c
384
static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
390
static bool ni_read_disabled_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
397
bool r;
sys/dev/pci/drm/radeon/radeon_bios.c
433
static bool r700_read_disabled_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
443
bool r;
sys/dev/pci/drm/radeon/radeon_bios.c
502
static bool r600_read_disabled_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
516
bool r;
sys/dev/pci/drm/radeon/radeon_bios.c
589
static bool avivo_read_disabled_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
59
static bool igp_read_bios_from_vram(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
600
bool r;
sys/dev/pci/drm/radeon/radeon_bios.c
650
static bool legacy_read_disabled_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
659
bool r;
sys/dev/pci/drm/radeon/radeon_bios.c
733
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
750
static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
756
bool r = false;
sys/dev/pci/drm/radeon/radeon_bios.c
808
static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
814
bool radeon_get_bios(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_bios.c
816
bool r;
sys/dev/pci/drm/radeon/radeon_bios.c
90
static bool igp_read_bios_from_vram(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_clocks.c
110
static bool radeon_read_clocks_OF(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_clocks.c
180
static bool radeon_read_clocks_OF(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_clocks.c
193
static bool radeon_read_clocks_OF(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_clocks.c
256
static bool radeon_read_clocks_OF(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_combios.c
1308
bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_combios.c
1324
bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_combios.c
1377
bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_combios.c
1401
bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_combios.c
1445
bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_combios.c
2211
static bool radeon_apply_legacy_quirks(struct drm_device *dev,
sys/dev/pci/drm/radeon/radeon_combios.c
2240
static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_combios.c
2300
bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_combios.c
2881
bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
sys/dev/pci/drm/radeon/radeon_combios.c
3438
void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
sys/dev/pci/drm/radeon/radeon_combios.c
3457
bool connected)
sys/dev/pci/drm/radeon/radeon_combios.c
3593
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
sys/dev/pci/drm/radeon/radeon_combios.c
372
bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_combios.c
723
bool radeon_combios_get_clock_info(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_combios.c
806
bool radeon_combios_sideport_present(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_connectors.c
1127
radeon_tv_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/radeon/radeon_connectors.c
1180
static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector)
sys/dev/pci/drm/radeon/radeon_connectors.c
1213
radeon_dvi_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/radeon/radeon_connectors.c
1222
bool dret = false, broken_edid = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1593
static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
sys/dev/pci/drm/radeon/radeon_connectors.c
1597
bool found = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1608
bool radeon_connector_is_dp12_capable(struct drm_connector *connector)
sys/dev/pci/drm/radeon/radeon_connectors.c
1623
radeon_dp_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/radeon/radeon_connectors.c
1851
bool shared_ddc = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1852
bool is_dp_bridge = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
1853
bool has_aux = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
229
bool connected;
sys/dev/pci/drm/radeon/radeon_connectors.c
381
bool priority)
sys/dev/pci/drm/radeon/radeon_connectors.c
525
bool new_coherent_mode;
sys/dev/pci/drm/radeon/radeon_connectors.c
653
bool ret = false;
sys/dev/pci/drm/radeon/radeon_connectors.c
839
radeon_lvds_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/radeon/radeon_connectors.c
985
radeon_vga_detect(struct drm_connector *connector, bool force)
sys/dev/pci/drm/radeon/radeon_connectors.c
992
bool dret = false;
sys/dev/pci/drm/radeon/radeon_cs.c
809
bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
sys/dev/pci/drm/radeon/radeon_cs.c
86
bool need_mmap_lock = false;
sys/dev/pci/drm/radeon/radeon_cursor.c
32
static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
sys/dev/pci/drm/radeon/radeon_device.c
1087
static unsigned int radeon_vga_set_decode(struct pci_dev *pdev, bool state)
sys/dev/pci/drm/radeon/radeon_device.c
117
bool radeon_has_atpx_dgpu_power_cntl(void);
sys/dev/pci/drm/radeon/radeon_device.c
118
bool radeon_is_atpx_hybrid(void);
sys/dev/pci/drm/radeon/radeon_device.c
120
static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
sys/dev/pci/drm/radeon/radeon_device.c
121
static inline bool radeon_is_atpx_hybrid(void) { return false; }
sys/dev/pci/drm/radeon/radeon_device.c
1262
static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
sys/dev/pci/drm/radeon/radeon_device.c
1300
bool runtime = false;
sys/dev/pci/drm/radeon/radeon_device.c
1576
int radeon_suspend_kms(struct drm_device *dev, bool suspend,
sys/dev/pci/drm/radeon/radeon_device.c
1577
bool notify_clients, bool freeze)
sys/dev/pci/drm/radeon/radeon_device.c
158
bool radeon_is_px(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_device.c
1691
int radeon_resume_kms(struct drm_device *dev, bool resume, bool notify_clients)
sys/dev/pci/drm/radeon/radeon_device.c
1807
bool saved = false;
sys/dev/pci/drm/radeon/radeon_device.c
649
bool radeon_device_is_virtual(void)
sys/dev/pci/drm/radeon/radeon_device.c
667
bool radeon_card_posted(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_device.c
766
bool radeon_boot_test_post_card(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_device.h
30
bool radeon_device_is_virtual(void);
sys/dev/pci/drm/radeon/radeon_display.c
1669
static bool is_hdtv_mode(const struct drm_display_mode *mode)
sys/dev/pci/drm/radeon/radeon_display.c
1681
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/radeon/radeon_display.c
1691
bool first = true;
sys/dev/pci/drm/radeon/radeon_display.c
1816
bool in_vbl = true;
sys/dev/pci/drm/radeon/radeon_display.c
1983
bool
sys/dev/pci/drm/radeon/radeon_display.c
1985
bool in_vblank_irq, int *vpos, int *hpos,
sys/dev/pci/drm/radeon/radeon_display.c
627
bool active = false;
sys/dev/pci/drm/radeon/radeon_display.c
844
static bool radeon_setup_enc_conn(struct drm_device *dev)
sys/dev/pci/drm/radeon/radeon_display.c
847
bool ret = false;
sys/dev/pci/drm/radeon/radeon_dp_auxch.c
69
bool is_write = false;
sys/dev/pci/drm/radeon/radeon_drv.c
648
bool radeon_has_atpx(void);
sys/dev/pci/drm/radeon/radeon_drv.c
650
static inline bool radeon_has_atpx(void) { return false; }
sys/dev/pci/drm/radeon/radeon_drv.c
681
bool radeon_msi_ok(struct radeon_device *);
sys/dev/pci/drm/radeon/radeon_drv.h
129
bool radeon_has_atpx_dgpu_power_cntl(void);
sys/dev/pci/drm/radeon/radeon_drv.h
130
bool radeon_is_atpx_hybrid(void);
sys/dev/pci/drm/radeon/radeon_drv.h
134
static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
sys/dev/pci/drm/radeon/radeon_drv.h
135
static inline bool radeon_is_atpx_hybrid(void) { return false; }
sys/dev/pci/drm/radeon/radeon_encoders.c
168
bool use_bl = false;
sys/dev/pci/drm/radeon/radeon_encoders.c
367
bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_encoders.c
428
bool radeon_encoder_is_digital(struct drm_encoder *encoder)
sys/dev/pci/drm/radeon/radeon_fbdev.c
325
bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
sys/dev/pci/drm/radeon/radeon_fbdev.c
63
bool fb_tiled = false; /* useful for testing */
sys/dev/pci/drm/radeon/radeon_fence.c
1003
static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
sys/dev/pci/drm/radeon/radeon_fence.c
197
static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
sys/dev/pci/drm/radeon/radeon_fence.c
201
bool wake = false;
sys/dev/pci/drm/radeon/radeon_fence.c
339
static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_fence.c
353
static bool radeon_fence_is_signaled(struct dma_fence *f)
sys/dev/pci/drm/radeon/radeon_fence.c
374
static bool radeon_fence_enable_signaling(struct dma_fence *f)
sys/dev/pci/drm/radeon/radeon_fence.c
419
bool radeon_fence_signaled(struct radeon_fence *fence)
sys/dev/pci/drm/radeon/radeon_fence.c
442
static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
sys/dev/pci/drm/radeon/radeon_fence.c
471
u64 *target_seq, bool intr,
sys/dev/pci/drm/radeon/radeon_fence.c
526
long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
sys/dev/pci/drm/radeon/radeon_fence.c
560
int radeon_fence_wait(struct radeon_fence *fence, bool intr)
sys/dev/pci/drm/radeon/radeon_fence.c
698
bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
sys/dev/pci/drm/radeon/radeon_fence.c
984
static inline bool radeon_test_signaled(struct radeon_fence *fence)
sys/dev/pci/drm/radeon/radeon_gem.c
166
u32 flags, bool kernel,
sys/dev/pci/drm/radeon/radeon_gem.c
903
int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled)
sys/dev/pci/drm/radeon/radeon_i2c.c
40
bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
sys/dev/pci/drm/radeon/radeon_ib.c
128
struct radeon_ib *const_ib, bool hdp_flush)
sys/dev/pci/drm/radeon/radeon_irq_kms.c
247
bool radeon_msi_ok(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_irq_kms.c
420
bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring)
sys/dev/pci/drm/radeon/radeon_irq_kms.c
609
bool enable, const char *name, unsigned n)
sys/dev/pci/drm/radeon/radeon_kms.c
45
bool radeon_has_atpx(void);
sys/dev/pci/drm/radeon/radeon_kms.c
47
static inline bool radeon_has_atpx(void) { return false; }
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
1026
static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
57
bool hscale = true, vscale = true;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
573
static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
588
bool is_tv = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
745
bool use_bios_divs = false;
sys/dev/pci/drm/radeon/radeon_legacy_crtc.c
750
bool is_tv = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1038
bool is_tv;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1156
bool is_tv = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1299
static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1306
bool found = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1370
static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1377
bool found = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1434
static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1444
bool found = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1535
bool color = true;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1551
bool tv_detect;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1696
bool ret;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
1719
bool ret;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
256
static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
63
bool is_mac = false;
sys/dev/pci/drm/radeon/radeon_legacy_encoders.c
642
bool color = true;
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
423
static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
sys/dev/pci/drm/radeon/radeon_legacy_tv.c
431
bool h_changed;
sys/dev/pci/drm/radeon/radeon_mn.c
49
static bool radeon_mn_invalidate(struct mmu_interval_notifier *mn,
sys/dev/pci/drm/radeon/radeon_mode.h
117
bool valid;
sys/dev/pci/drm/radeon/radeon_mode.h
123
bool hw_capable;
sys/dev/pci/drm/radeon/radeon_mode.h
125
bool mm_i2c;
sys/dev/pci/drm/radeon/radeon_mode.h
209
bool has_aux;
sys/dev/pci/drm/radeon/radeon_mode.h
238
bool enabled;
sys/dev/pci/drm/radeon/radeon_mode.h
240
bool last_buffer_filled_status;
sys/dev/pci/drm/radeon/radeon_mode.h
248
bool mode_config_initialized;
sys/dev/pci/drm/radeon/radeon_mode.h
325
bool enabled;
sys/dev/pci/drm/radeon/radeon_mode.h
326
bool can_tile;
sys/dev/pci/drm/radeon/radeon_mode.h
327
bool cursor_out_of_bounds;
sys/dev/pci/drm/radeon/radeon_mode.h
353
bool ss_enabled;
sys/dev/pci/drm/radeon/radeon_mode.h
384
bool use_bios_dividers;
sys/dev/pci/drm/radeon/radeon_mode.h
403
bool tv_on;
sys/dev/pci/drm/radeon/radeon_mode.h
422
bool linkb;
sys/dev/pci/drm/radeon/radeon_mode.h
424
bool coherent_mode;
sys/dev/pci/drm/radeon/radeon_mode.h
459
bool is_ext_encoder;
sys/dev/pci/drm/radeon/radeon_mode.h
463
bool can_mst;
sys/dev/pci/drm/radeon/radeon_mode.h
474
bool edp_on;
sys/dev/pci/drm/radeon/radeon_mode.h
478
bool valid;
sys/dev/pci/drm/radeon/radeon_mode.h
496
bool ddc_valid;
sys/dev/pci/drm/radeon/radeon_mode.h
501
bool cd_valid;
sys/dev/pci/drm/radeon/radeon_mode.h
524
bool shared_ddc;
sys/dev/pci/drm/radeon/radeon_mode.h
525
bool use_digital;
sys/dev/pci/drm/radeon/radeon_mode.h
530
bool dac_load_detect;
sys/dev/pci/drm/radeon/radeon_mode.h
531
bool detected_by_load; /* if the connection status was determined by load */
sys/dev/pci/drm/radeon/radeon_mode.h
532
bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
sys/dev/pci/drm/radeon/radeon_mode.h
562
bool enable_post_div;
sys/dev/pci/drm/radeon/radeon_mode.h
563
bool enable_dithen;
sys/dev/pci/drm/radeon/radeon_mode.h
690
bool connected);
sys/dev/pci/drm/radeon/radeon_mode.h
694
bool connected);
sys/dev/pci/drm/radeon/radeon_mode.h
700
extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_mode.h
705
extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
sys/dev/pci/drm/radeon/radeon_mode.h
715
extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
sys/dev/pci/drm/radeon/radeon_mode.h
717
extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
sys/dev/pci/drm/radeon/radeon_mode.h
738
void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
sys/dev/pci/drm/radeon/radeon_mode.h
763
extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
sys/dev/pci/drm/radeon/radeon_mode.h
765
extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_mode.h
768
extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_mode.h
800
extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
sys/dev/pci/drm/radeon/radeon_mode.h
802
extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
sys/dev/pci/drm/radeon/radeon_mode.h
843
extern bool
sys/dev/pci/drm/radeon/radeon_mode.h
844
radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
sys/dev/pci/drm/radeon/radeon_mode.h
849
extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_mode.h
852
extern bool radeon_atom_get_clock_info(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon_mode.h
853
extern bool radeon_combios_get_clock_info(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon_mode.h
856
extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_mode.h
858
extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_mode.h
860
extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_mode.h
862
extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_mode.h
864
extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
sys/dev/pci/drm/radeon/radeon_mode.h
876
extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
sys/dev/pci/drm/radeon/radeon_mode.h
878
extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
sys/dev/pci/drm/radeon/radeon_mode.h
880
extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
sys/dev/pci/drm/radeon/radeon_mode.h
887
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
sys/dev/pci/drm/radeon/radeon_mode.h
891
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
sys/dev/pci/drm/radeon/radeon_mode.h
899
bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon_mode.h
900
bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon_mode.h
908
extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon_mode.h
909
extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
sys/dev/pci/drm/radeon/radeon_mode.h
914
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
sys/dev/pci/drm/radeon/radeon_mode.h
947
bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
sys/dev/pci/drm/radeon/radeon_mode.h
951
static inline bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
sys/dev/pci/drm/radeon/radeon_object.c
129
unsigned long size, int byte_align, bool kernel,
sys/dev/pci/drm/radeon/radeon_object.c
220
bool is_iomem;
sys/dev/pci/drm/radeon/radeon_object.c
69
bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
sys/dev/pci/drm/radeon/radeon_object.c
695
int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
sys/dev/pci/drm/radeon/radeon_object.c
696
bool force_drop)
sys/dev/pci/drm/radeon/radeon_object.c
799
bool shared)
sys/dev/pci/drm/radeon/radeon_object.h
138
bool kernel, u32 domain, u32 flags,
sys/dev/pci/drm/radeon/radeon_object.h
161
extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
sys/dev/pci/drm/radeon/radeon_object.h
162
bool force_drop);
sys/dev/pci/drm/radeon/radeon_object.h
167
bool shared);
sys/dev/pci/drm/radeon/radeon_object.h
64
static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
sys/dev/pci/drm/radeon/radeon_pm.c
1078
bool single_display = radeon_dpm_single_display(rdev);
sys/dev/pci/drm/radeon/radeon_pm.c
1202
void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/radeon_pm.c
1244
void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/radeon_pm.c
1516
bool disable_dpm = false;
sys/dev/pci/drm/radeon/radeon_pm.c
176
bool misc_after = false;
sys/dev/pci/drm/radeon/radeon_pm.c
1840
static bool radeon_pm_in_vbl(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_pm.c
1843
bool in_vbl = true;
sys/dev/pci/drm/radeon/radeon_pm.c
1864
static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
sys/dev/pci/drm/radeon/radeon_pm.c
1867
bool in_vbl = radeon_pm_in_vbl(rdev);
sys/dev/pci/drm/radeon/radeon_pm.c
52
static bool radeon_pm_in_vbl(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/radeon_pm.c
53
static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
sys/dev/pci/drm/radeon/radeon_pm.c
926
static bool radeon_dpm_single_display(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/radeon_pm.c
928
bool single_display = rdev->pm.dpm.new_active_crtc_count < 2;
sys/dev/pci/drm/radeon/radeon_pm.c
951
bool single_display = radeon_dpm_single_display(rdev);
sys/dev/pci/drm/radeon/radeon_ring.c
170
bool hdp_flush)
sys/dev/pci/drm/radeon/radeon_ring.c
201
bool hdp_flush)
sys/dev/pci/drm/radeon/radeon_ring.c
254
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/radeon_ring.c
62
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_semaphore.c
58
bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ridx,
sys/dev/pci/drm/radeon/radeon_semaphore.c
75
bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ridx,
sys/dev/pci/drm/radeon/radeon_sync.c
92
bool shared)
sys/dev/pci/drm/radeon/radeon_test.c
413
bool sigA, sigB;
sys/dev/pci/drm/radeon/radeon_test.c
516
static bool radeon_test_sync_possible(struct radeon_ring *ringA,
sys/dev/pci/drm/radeon/radeon_ttm.c
142
bool evict,
sys/dev/pci/drm/radeon/radeon_ttm.c
196
static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
sys/dev/pci/drm/radeon/radeon_ttm.c
327
bool bound;
sys/dev/pci/drm/radeon/radeon_ttm.c
428
static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
sys/dev/pci/drm/radeon/radeon_ttm.c
548
bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
sys/dev/pci/drm/radeon/radeon_ttm.c
572
bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
sys/dev/pci/drm/radeon/radeon_ttm.c
607
bool radeon_ttm_tt_is_bound(struct ttm_device *bdev,
sys/dev/pci/drm/radeon/radeon_ttm.c
664
bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_ttm.c
675
bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_uvd.c
563
unsigned buf_sizes[], bool *has_msg_cmd)
sys/dev/pci/drm/radeon/radeon_uvd.c
641
bool *has_msg_cmd)
sys/dev/pci/drm/radeon/radeon_uvd.c
679
bool has_msg_cmd = false;
sys/dev/pci/drm/radeon/radeon_uvd.c
880
bool streams_changed = false;
sys/dev/pci/drm/radeon/radeon_uvd.c
881
bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
sys/dev/pci/drm/radeon/radeon_vce.c
318
bool streams_changed = false;
sys/dev/pci/drm/radeon/radeon_vce.c
319
bool set_clocks = !cancel_delayed_work_sync(&rdev->vce.idle_work);
sys/dev/pci/drm/radeon/radeon_vce.c
549
uint32_t handle, bool *allocated)
sys/dev/pci/drm/radeon/radeon_vce.c
589
bool destroyed = false, created = false, allocated = false;
sys/dev/pci/drm/radeon/radeon_vce.c
724
bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/radeon_vce.c
727
bool emit_wait)
sys/dev/pci/drm/radeon/rs600.c
119
void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
sys/dev/pci/drm/radeon/rs600.c
155
bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
sys/dev/pci/drm/radeon/rs600.c
359
bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
sys/dev/pci/drm/radeon/rs600.c
362
bool connected = false;
sys/dev/pci/drm/radeon/rs600.c
385
bool connected = rs600_hpd_sense(rdev, hpd);
sys/dev/pci/drm/radeon/rs600.c
462
int rs600_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/rs600.c
62
static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
sys/dev/pci/drm/radeon/rs600.c
70
static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
sys/dev/pci/drm/radeon/rs600.c
781
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/rs600.c
782
bool queue_hdmi = false;
sys/dev/pci/drm/radeon/rs690.c
275
bool low)
sys/dev/pci/drm/radeon/rs780_dpm.c
303
static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/rs780_dpm.c
313
static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/rs780_dpm.c
73
static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/rs780_dpm.c
964
u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/rs780_dpm.c
974
u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/rs780_dpm.h
34
bool invert_pwm_required;
sys/dev/pci/drm/radeon/rs780_dpm.h
35
bool pwm_voltage_control;
sys/dev/pci/drm/radeon/rs780_dpm.h
36
bool voltage_control;
sys/dev/pci/drm/radeon/rs780_dpm.h
37
bool gfx_clock_gating;
sys/dev/pci/drm/radeon/rv515.c
926
bool low)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1170
static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1255
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1264
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1354
bool want_thermal_protection;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1390
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1409
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1472
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
1495
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
195
bool increasing_vco, u32 step_size)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
209
static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2110
u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
2120
u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
230
static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/rv6xx_dpm.c
233
bool increasing_vco)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
245
bool increasing_vco;
sys/dev/pci/drm/radeon/rv6xx_dpm.c
329
u32 index, bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
352
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
361
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
370
u32 index, bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
88
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
967
bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.c
980
static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/rv6xx_dpm.h
40
bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
sys/dev/pci/drm/radeon/rv6xx_dpm.h
41
bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
sys/dev/pci/drm/radeon/rv6xx_dpm.h
57
bool voltage_control;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
58
bool sclk_ss;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
59
bool mclk_ss;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
60
bool dynamic_ss;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
61
bool dynamic_pcie_gen2;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
62
bool thermal_protection;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
63
bool display_gap;
sys/dev/pci/drm/radeon/rv6xx_dpm.h
64
bool gfx_clock_gating;
sys/dev/pci/drm/radeon/rv730_dpm.c
473
void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt)
sys/dev/pci/drm/radeon/rv740_dpm.c
400
bool enable)
sys/dev/pci/drm/radeon/rv740_dpm.c
93
u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock)
sys/dev/pci/drm/radeon/rv770.c
800
void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
sys/dev/pci/drm/radeon/rv770.c
843
bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id)
sys/dev/pci/drm/radeon/rv770_dpm.c
132
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
1335
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
1362
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
145
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
170
bool dpm_en = false, cg_en = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1752
bool current_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1753
bool new_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1781
bool current_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1782
bool new_use_dc = false;
sys/dev/pci/drm/radeon/rv770_dpm.c
1817
bool want_thermal_protection;
sys/dev/pci/drm/radeon/rv770_dpm.c
1853
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
206
bool rv770_dpm_enabled(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/rv770_dpm.c
215
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
2552
u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/rv770_dpm.c
2562
u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/rv770_dpm.c
2572
bool rv770_dpm_vblank_too_short(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/rv770_dpm.c
321
bool gddr5,
sys/dev/pci/drm/radeon/rv770_dpm.c
71
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
773
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.c
782
bool enable)
sys/dev/pci/drm/radeon/rv770_dpm.h
155
bool dc_compatible;
sys/dev/pci/drm/radeon/rv770_dpm.h
195
bool enable);
sys/dev/pci/drm/radeon/rv770_dpm.h
198
void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
sys/dev/pci/drm/radeon/rv770_dpm.h
211
bool enable);
sys/dev/pci/drm/radeon/rv770_dpm.h
213
u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
sys/dev/pci/drm/radeon/rv770_dpm.h
243
bool rv770_dpm_enabled(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/rv770_dpm.h
245
bool enable);
sys/dev/pci/drm/radeon/rv770_dpm.h
247
bool enable);
sys/dev/pci/drm/radeon/rv770_dpm.h
249
bool enable);
sys/dev/pci/drm/radeon/rv770_dpm.h
252
bool enable);
sys/dev/pci/drm/radeon/rv770_dpm.h
77
bool mem_gddr5;
sys/dev/pci/drm/radeon/rv770_dpm.h
78
bool pcie_gen2;
sys/dev/pci/drm/radeon/rv770_dpm.h
79
bool dynamic_pcie_gen2;
sys/dev/pci/drm/radeon/rv770_dpm.h
80
bool acpi_pcie_gen2;
sys/dev/pci/drm/radeon/rv770_dpm.h
81
bool boot_in_gen2;
sys/dev/pci/drm/radeon/rv770_dpm.h
82
bool voltage_control; /* vddc */
sys/dev/pci/drm/radeon/rv770_dpm.h
83
bool mvdd_control;
sys/dev/pci/drm/radeon/rv770_dpm.h
84
bool sclk_ss;
sys/dev/pci/drm/radeon/rv770_dpm.h
85
bool mclk_ss;
sys/dev/pci/drm/radeon/rv770_dpm.h
86
bool dynamic_ss;
sys/dev/pci/drm/radeon/rv770_dpm.h
87
bool gfx_clock_gating;
sys/dev/pci/drm/radeon/rv770_dpm.h
88
bool mg_clock_gating;
sys/dev/pci/drm/radeon/rv770_dpm.h
89
bool mgcgtssm;
sys/dev/pci/drm/radeon/rv770_dpm.h
90
bool power_gating;
sys/dev/pci/drm/radeon/rv770_dpm.h
91
bool thermal_protection;
sys/dev/pci/drm/radeon/rv770_dpm.h
92
bool display_gap;
sys/dev/pci/drm/radeon/rv770_dpm.h
93
bool dcodt;
sys/dev/pci/drm/radeon/rv770_dpm.h
94
bool ulps;
sys/dev/pci/drm/radeon/rv770_smc.c
400
bool rv770_is_smc_running(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/rv770_smc.h
188
bool rv770_is_smc_running(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/si.c
134
bool enable);
sys/dev/pci/drm/radeon/si.c
1658
bool new_smc = false;
sys/dev/pci/drm/radeon/si.c
1659
bool si58_fw = false;
sys/dev/pci/drm/radeon/si.c
1660
bool banks2_fw = false;
sys/dev/pci/drm/radeon/si.c
2041
bool interlaced; /* mode is interlaced */
sys/dev/pci/drm/radeon/si.c
2230
static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
sys/dev/pci/drm/radeon/si.c
2239
static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
sys/dev/pci/drm/radeon/si.c
2248
static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
sys/dev/pci/drm/radeon/si.c
3440
static void si_cp_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/si.c
4067
int si_asic_reset(struct radeon_device *rdev, bool hard)
sys/dev/pci/drm/radeon/si.c
4107
bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/si.c
4391
static bool si_vm_reg_valid(u32 reg)
sys/dev/pci/drm/radeon/si.c
5126
bool enable)
sys/dev/pci/drm/radeon/si.c
5152
bool sw_mode)
sys/dev/pci/drm/radeon/si.c
5174
bool hw_mode = true;
sys/dev/pci/drm/radeon/si.c
5210
static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/si.c
5235
bool enable)
sys/dev/pci/drm/radeon/si.c
5336
bool enable)
sys/dev/pci/drm/radeon/si.c
5376
bool enable)
sys/dev/pci/drm/radeon/si.c
5432
bool enable)
sys/dev/pci/drm/radeon/si.c
5477
bool enable)
sys/dev/pci/drm/radeon/si.c
5494
bool enable)
sys/dev/pci/drm/radeon/si.c
5511
bool enable)
sys/dev/pci/drm/radeon/si.c
5548
bool enable)
sys/dev/pci/drm/radeon/si.c
5566
bool enable)
sys/dev/pci/drm/radeon/si.c
5582
bool enable)
sys/dev/pci/drm/radeon/si.c
5598
u32 block, bool enable)
sys/dev/pci/drm/radeon/si.c
5817
static bool si_lbpw_supported(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/si.c
5828
static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/si.c
6234
bool queue_hotplug = false;
sys/dev/pci/drm/radeon/si.c
6235
bool queue_dp = false;
sys/dev/pci/drm/radeon/si.c
6236
bool queue_thermal = false;
sys/dev/pci/drm/radeon/si.c
7229
bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
sys/dev/pci/drm/radeon/si.c
7230
bool disable_clkreq = false;
sys/dev/pci/drm/radeon/si.c
7267
bool clk_req_support;
sys/dev/pci/drm/radeon/si_dma.c
40
bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
sys/dev/pci/drm/radeon/si_dpm.c
1806
bool update_dte_from_pl2 = false;
sys/dev/pci/drm/radeon/si_dpm.c
2059
bool adjust_polarity,
sys/dev/pci/drm/radeon/si_dpm.c
2210
static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/si_dpm.c
2238
bool disable_uvd_power_tune;
sys/dev/pci/drm/radeon/si_dpm.c
2323
bool enable_sq_ramping = ni_pi->enable_sq_ramping;
sys/dev/pci/drm/radeon/si_dpm.c
2375
bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
2736
bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
2907
bool disable_mclk_switching = false;
sys/dev/pci/drm/radeon/si_dpm.c
2908
bool disable_sclk_switching = false;
sys/dev/pci/drm/radeon/si_dpm.c
3148
static bool si_is_special_1gb_platform(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/si_dpm.c
3150
bool ret = false;
sys/dev/pci/drm/radeon/si_dpm.c
3152
bool is_memory_gddr5, is_special;
sys/dev/pci/drm/radeon/si_dpm.c
3225
bool want_thermal_protection;
sys/dev/pci/drm/radeon/si_dpm.c
3259
bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
3286
static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
3318
static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
sys/dev/pci/drm/radeon/si_dpm.c
3533
bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
3575
bool has_display)
sys/dev/pci/drm/radeon/si_dpm.c
3669
static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
3780
u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
sys/dev/pci/drm/radeon/si_dpm.c
3805
bool strobe_mode = false;
sys/dev/pci/drm/radeon/si_dpm.c
3835
static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/si_dpm.c
4095
bool voltage_found = false;
sys/dev/pci/drm/radeon/si_dpm.c
4821
bool strobe_mode,
sys/dev/pci/drm/radeon/si_dpm.c
4822
bool dll_state_on)
sys/dev/pci/drm/radeon/si_dpm.c
4929
bool dll_state_on;
sys/dev/pci/drm/radeon/si_dpm.c
4931
bool gmc_pg = false;
sys/dev/pci/drm/radeon/si_dpm.c
5091
static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/si_dpm.c
5369
static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
sys/dev/pci/drm/radeon/si_dpm.c
5371
bool result = true;
sys/dev/pci/drm/radeon/si_dpm.c
5654
static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/si_dpm.c
5755
bool ds_status_on, u32 count_write)
sys/dev/pci/drm/radeon/si_dpm.c
5902
bool enable)
sys/dev/pci/drm/radeon/si_dpm.h
136
bool supported;
sys/dev/pci/drm/radeon/si_dpm.h
141
bool one_pcie_lane_in_ulv;
sys/dev/pci/drm/radeon/si_dpm.h
161
bool enable_dte;
sys/dev/pci/drm/radeon/si_dpm.h
162
bool enable_ppm;
sys/dev/pci/drm/radeon/si_dpm.h
163
bool vddc_phase_shed_control;
sys/dev/pci/drm/radeon/si_dpm.h
164
bool pspp_notify_required;
sys/dev/pci/drm/radeon/si_dpm.h
165
bool sclk_deep_sleep_above_low;
sys/dev/pci/drm/radeon/si_dpm.h
166
bool voltage_control_svi2;
sys/dev/pci/drm/radeon/si_dpm.h
167
bool vddci_control_svi2;
sys/dev/pci/drm/radeon/si_dpm.h
195
bool fan_ctrl_is_in_default_mode;
sys/dev/pci/drm/radeon/si_dpm.h
198
bool fan_is_controlled_by_smc;
sys/dev/pci/drm/radeon/si_dpm.h
231
u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
sys/dev/pci/drm/radeon/si_dpm.h
53
bool enable_powertune_by_default;
sys/dev/pci/drm/radeon/si_dpm.h
64
bool disable_uvd_powertune;
sys/dev/pci/drm/radeon/si_dpm.h
81
bool enable_dte_by_default;
sys/dev/pci/drm/radeon/si_smc.c
161
bool si_is_smc_running(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/sislands_smc.h
405
bool si_is_smc_running(struct radeon_device *rdev);
sys/dev/pci/drm/radeon/sumo_dpm.c
101
static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
1903
u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/sumo_dpm.c
1914
u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/sumo_dpm.c
272
static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
578
static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
597
static bool sumo_dpm_enabled(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/sumo_dpm.c
615
static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
713
bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
86
static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
867
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
886
static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.c
950
static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_dpm.h
101
bool enable_boost;
sys/dev/pci/drm/radeon/sumo_dpm.h
120
bool disable_gfx_power_gating_in_uvd;
sys/dev/pci/drm/radeon/sumo_dpm.h
121
bool driver_nbps_policy_disable;
sys/dev/pci/drm/radeon/sumo_dpm.h
122
bool enable_alt_vddnb;
sys/dev/pci/drm/radeon/sumo_dpm.h
123
bool enable_dynamic_m3_arbiter;
sys/dev/pci/drm/radeon/sumo_dpm.h
124
bool enable_gfx_clock_gating;
sys/dev/pci/drm/radeon/sumo_dpm.h
125
bool enable_gfx_power_gating;
sys/dev/pci/drm/radeon/sumo_dpm.h
126
bool enable_mg_clock_gating;
sys/dev/pci/drm/radeon/sumo_dpm.h
127
bool enable_sclk_ds;
sys/dev/pci/drm/radeon/sumo_dpm.h
128
bool enable_auto_thermal_throttling;
sys/dev/pci/drm/radeon/sumo_dpm.h
129
bool enable_dynamic_patch_ps;
sys/dev/pci/drm/radeon/sumo_dpm.h
130
bool enable_dpm;
sys/dev/pci/drm/radeon/sumo_dpm.h
131
bool enable_boost;
sys/dev/pci/drm/radeon/sumo_dpm.h
196
void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/sumo_dpm.h
217
bool powersaving, bool force_nbps1);
sys/dev/pci/drm/radeon/sumo_dpm.h
218
void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/sumo_smc.c
107
bool powersaving, bool force_nbps1)
sys/dev/pci/drm/radeon/sumo_smc.c
205
void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/sumo_smc.c
90
static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/sumo_smc.c
93
bool return_code = false;
sys/dev/pci/drm/radeon/trinity_dpm.c
1041
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
1498
bool force_high;
sys/dev/pci/drm/radeon/trinity_dpm.c
2044
u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/trinity_dpm.c
2055
u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low)
sys/dev/pci/drm/radeon/trinity_dpm.c
355
bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
395
bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
438
bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
455
bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
469
bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
686
u32 index, bool enable)
sys/dev/pci/drm/radeon/trinity_dpm.c
698
static bool trinity_dpm_enabled(struct radeon_device *rdev)
sys/dev/pci/drm/radeon/trinity_dpm.c
848
static bool trinity_uvd_clocks_zero(struct radeon_ps *rps)
sys/dev/pci/drm/radeon/trinity_dpm.c
856
static bool trinity_uvd_clocks_equal(struct radeon_ps *rps1,
sys/dev/pci/drm/radeon/trinity_dpm.h
100
bool enable_nbps_policy;
sys/dev/pci/drm/radeon/trinity_dpm.h
101
bool voltage_drop_in_dce;
sys/dev/pci/drm/radeon/trinity_dpm.h
102
bool override_dynamic_mgpg;
sys/dev/pci/drm/radeon/trinity_dpm.h
103
bool enable_gfx_clock_gating;
sys/dev/pci/drm/radeon/trinity_dpm.h
104
bool enable_gfx_power_gating;
sys/dev/pci/drm/radeon/trinity_dpm.h
105
bool enable_mg_clock_gating;
sys/dev/pci/drm/radeon/trinity_dpm.h
106
bool enable_gfx_dynamic_mgpg;
sys/dev/pci/drm/radeon/trinity_dpm.h
107
bool enable_auto_thermal_throttling;
sys/dev/pci/drm/radeon/trinity_dpm.h
108
bool enable_dpm;
sys/dev/pci/drm/radeon/trinity_dpm.h
109
bool enable_sclk_ds;
sys/dev/pci/drm/radeon/trinity_dpm.h
110
bool enable_bapm;
sys/dev/pci/drm/radeon/trinity_dpm.h
111
bool uvd_dpm;
sys/dev/pci/drm/radeon/trinity_dpm.h
121
int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/trinity_dpm.h
122
int trinity_dpm_config(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/trinity_dpm.h
128
bool enable);
sys/dev/pci/drm/radeon/trinity_smc.c
55
int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/trinity_smc.c
63
int trinity_dpm_config(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/trinity_smc.c
98
bool enable)
sys/dev/pci/drm/radeon/uvd_v1_0.c
465
bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/uvd_v1_0.c
468
bool emit_wait)
sys/dev/pci/drm/radeon/uvd_v2_2.c
72
bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/uvd_v2_2.c
75
bool emit_wait)
sys/dev/pci/drm/radeon/uvd_v3_1.c
39
bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
sys/dev/pci/drm/radeon/uvd_v3_1.c
42
bool emit_wait)
sys/dev/pci/drm/radeon/vce.h
32
void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/vce.h
33
void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
sys/dev/pci/drm/radeon/vce_v1_0.c
103
void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/vce_v2_0.c
112
void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
sys/dev/pci/drm/radeon/vce_v2_0.c
114
bool sw_cg = false;
sys/dev/pci/drm/radeon/vce_v2_0.c
39
static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
sys/dev/pci/drm/radeon/vce_v2_0.c
74
static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
sys/dev/pci/drm/scheduler/sched_entity.c
147
static bool drm_sched_entity_is_idle(struct drm_sched_entity *entity)
sys/dev/pci/drm/scheduler/sched_entity.c
419
static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity,
sys/dev/pci/drm/scheduler/sched_entity.c
599
bool first;
sys/dev/pci/drm/scheduler/sched_internal.h
79
static inline bool
sys/dev/pci/drm/scheduler/sched_main.c
1005
bool write)
sys/dev/pci/drm/scheduler/sched_main.c
1020
bool drm_sched_job_has_dependency(struct drm_sched_job *job,
sys/dev/pci/drm/scheduler/sched_main.c
1133
drm_sched_get_finished_job(struct drm_gpu_scheduler *sched, bool *have_more)
sys/dev/pci/drm/scheduler/sched_main.c
117
static bool drm_sched_can_queue(struct drm_gpu_scheduler *sched,
sys/dev/pci/drm/scheduler/sched_main.c
1218
bool have_more;
sys/dev/pci/drm/scheduler/sched_main.c
138
static __always_inline bool drm_sched_entity_compare_before(struct rb_node *a,
sys/dev/pci/drm/scheduler/sched_main.c
1528
bool drm_sched_wqueue_ready(struct drm_gpu_scheduler *sched)
sys/dev/pci/drm/scheduler/sched_main.c
745
bool found_guilty = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
113
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
114
bool no_wait = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
143
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
144
bool no_wait = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
189
bool interruptible = true;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
190
bool no_wait = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
29
bool interruptible;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
30
bool no_wait;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
76
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
77
bool no_wait = true;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
95
bool interruptible = false;
sys/dev/pci/drm/ttm/tests/ttm_bo_test.c
96
bool no_wait = true;
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
24
bool with_ttm;
sys/dev/pci/drm/ttm/tests/ttm_bo_validate_test.c
25
bool no_gpu_wait;
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
13
bool use_dma_alloc;
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
14
bool use_dma32;
sys/dev/pci/drm/ttm/tests/ttm_device_test.c
15
bool pools_init_expected;
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
120
bool use_dma_alloc,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
121
bool use_dma32,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
146
bool use_dma_alloc,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
147
bool use_dma32)
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
165
bool use_dma_alloc,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
166
bool use_dma32)
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.c
63
static int mock_move(struct ttm_buffer_object *bo, bool evict,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.h
31
bool use_dma_alloc,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.h
32
bool use_dma32);
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.h
35
bool use_dma_alloc,
sys/dev/pci/drm/ttm/tests/ttm_kunit_helpers.h
36
bool use_dma32);
sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c
172
static bool ttm_bad_manager_compatible(struct ttm_resource_manager *man,
sys/dev/pci/drm/ttm/tests/ttm_pool_test.c
15
bool use_dma_alloc;
sys/dev/pci/drm/ttm/ttm_agp_backend.c
110
bool ttm_agp_is_bound(struct ttm_tt *ttm)
sys/dev/pci/drm/ttm/ttm_backup.c
106
bool writeback, pgoff_t idx, gfp_t page_gfp,
sys/dev/pci/drm/ttm/ttm_backup.c
57
pgoff_t handle, bool intr)
sys/dev/pci/drm/ttm/ttm_bo.c
1023
uint32_t alignment, bool interruptible,
sys/dev/pci/drm/ttm/ttm_bo.c
1128
bool hit_low, evict_low;
sys/dev/pci/drm/ttm/ttm_bo.c
119
struct ttm_resource *mem, bool evict,
sys/dev/pci/drm/ttm/ttm_bo.c
124
bool old_use_tt, new_use_tt;
sys/dev/pci/drm/ttm/ttm_bo.c
1288
bool swapped;
sys/dev/pci/drm/ttm/ttm_bo.c
421
bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
sys/dev/pci/drm/ttm/ttm_bo.c
510
bool try_low;
sys/dev/pci/drm/ttm/ttm_bo.c
512
bool hit_low;
sys/dev/pci/drm/ttm/ttm_bo.c
666
bool no_wait_gpu)
sys/dev/pci/drm/ttm/ttm_bo.c
713
bool force_space,
sys/dev/pci/drm/ttm/ttm_bo.c
729
bool may_evict;
sys/dev/pci/drm/ttm/ttm_bo.c
790
bool force_space = false;
sys/dev/pci/drm/ttm/ttm_bo.c
824
bool force_space;
sys/dev/pci/drm/ttm/ttm_bo_util.c
1156
bool ttm_bo_shrink_suitable(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx)
sys/dev/pci/drm/ttm/ttm_bo_util.c
1174
bool ttm_bo_shrink_avoid_wait(void)
sys/dev/pci/drm/ttm/ttm_bo_util.c
162
bool clear;
sys/dev/pci/drm/ttm/ttm_bo_util.c
613
bool dst_use_tt)
sys/dev/pci/drm/ttm/ttm_bo_util.c
632
bool dst_use_tt)
sys/dev/pci/drm/ttm/ttm_bo_util.c
708
bool evict,
sys/dev/pci/drm/ttm/ttm_bo_util.c
709
bool pipeline,
sys/dev/pci/drm/ttm/ttm_bo_util.c
827
static bool ttm_lru_walk_trylock(struct ttm_bo_lru_cursor *curs,
sys/dev/pci/drm/ttm/ttm_bo_util.c
88
void ttm_move_memcpy(bool clear,
sys/dev/pci/drm/ttm/ttm_bo_util.c
988
bool first = !curs->bo;
sys/dev/pci/drm/ttm/ttm_bo_util.c
995
bool bo_locked = false;
sys/dev/pci/drm/ttm/ttm_bo_vm.c
661
bool is_iomem;
sys/dev/pci/drm/ttm/ttm_device.c
210
bool use_dma_alloc, bool use_dma32)
sys/dev/pci/drm/ttm/ttm_execbuf_util.c
77
struct list_head *list, bool intr,
sys/dev/pci/drm/ttm/ttm_pool.c
1236
int nid, bool use_dma_alloc, bool use_dma32)
sys/dev/pci/drm/ttm/ttm_pool.c
589
static bool ttm_pool_restore_valid(const struct ttm_pool_tt_restore *restore)
sys/dev/pci/drm/ttm/ttm_pool.c
765
bool caching_consistent;
sys/dev/pci/drm/ttm/ttm_pool.c
865
bool allow_pools;
sys/dev/pci/drm/ttm/ttm_range_manager.c
118
static bool ttm_range_man_intersects(struct ttm_resource_manager *man,
sys/dev/pci/drm/ttm/ttm_range_manager.c
134
static bool ttm_range_man_compatible(struct ttm_resource_manager *man,
sys/dev/pci/drm/ttm/ttm_range_manager.c
181
unsigned type, bool use_tt,
sys/dev/pci/drm/ttm/ttm_resource.c
258
static bool ttm_resource_is_swapped(struct ttm_resource *res, struct ttm_buffer_object *bo)
sys/dev/pci/drm/ttm/ttm_resource.c
273
static bool ttm_resource_unevictable(struct ttm_resource *res, struct ttm_buffer_object *bo)
sys/dev/pci/drm/ttm/ttm_resource.c
441
bool ttm_resource_intersects(struct ttm_device *bdev,
sys/dev/pci/drm/ttm/ttm_resource.c
467
bool ttm_resource_compatible(struct ttm_resource *res,
sys/dev/pci/drm/ttm/ttm_resource.c
469
bool evicting)
sys/dev/pci/drm/ttm/ttm_tt.c
66
int ttm_tt_create(struct ttm_buffer_object *bo, bool zero_alloc)
sys/dev/pci/if_bnxt.c
3110
bnxt_hwrm_func_drv_unrgtr(struct bnxt_softc *softc, bool shutdown)
sys/dev/pci/if_bnxt.c
431
int bnxt_hwrm_func_drv_unrgtr(struct bnxt_softc *softc, bool shutdown);
sys/dev/pci/if_em_hw.c
1423
em_disable_ulp_lpt_lp(struct em_hw *hw, bool force)
sys/dev/pci/if_em_hw.c
88
static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force);
sys/dev/pci/if_ice.c
11054
ice_control_rx_queue(struct ice_vsi *vsi, uint16_t qidx, bool enable)
sys/dev/pci/if_ice.c
11108
ice_control_all_rx_queues(struct ice_vsi *vsi, bool enable)
sys/dev/pci/if_ice.c
11291
bool is_tx_fltr, is_rx_lb_fltr;
sys/dev/pci/if_ice.c
11410
bool
sys/dev/pci/if_ice.c
11478
bool is_rx_lb_fltr = false;
sys/dev/pci/if_ice.c
11479
bool is_tx_fltr = false;
sys/dev/pci/if_ice.c
11636
bool remove_rule = false;
sys/dev/pci/if_ice.c
11834
bool promisc_enable = ifp->if_flags & IFF_PROMISC;
sys/dev/pci/if_ice.c
11835
bool multi_enable = ifp->if_flags & IFF_ALLMULTI;
sys/dev/pci/if_ice.c
1219
bool
sys/dev/pci/if_ice.c
12265
bool apply_speed_filter = false;
sys/dev/pci/if_ice.c
12589
bool ice_fw_supports_fec_dis_auto(struct ice_hw *hw)
sys/dev/pci/if_ice.c
12969
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
sys/dev/pci/if_ice.c
13007
ice_set_link(struct ice_softc *sc, bool enabled)
sys/dev/pci/if_ice.c
14533
bool
sys/dev/pci/if_ice.c
14777
struct ice_sq_cd *cd, uint8_t *flags, bool set)
sys/dev/pci/if_ice.c
15100
bool
sys/dev/pci/if_ice.c
15182
bool
sys/dev/pci/if_ice.c
15378
bool
sys/dev/pci/if_ice.c
15468
bool
sys/dev/pci/if_ice.c
15472
bool retval = false;
sys/dev/pci/if_ice.c
15490
bool
sys/dev/pci/if_ice.c
15494
bool result = false;
sys/dev/pci/if_ice.c
15515
bool
sys/dev/pci/if_ice.c
15519
bool match = false;
sys/dev/pci/if_ice.c
15591
bool
sys/dev/pci/if_ice.c
16189
bool
sys/dev/pci/if_ice.c
16203
bool
sys/dev/pci/if_ice.c
16207
bool last = ((idx + 1) == count);
sys/dev/pci/if_ice.c
16235
uint16_t buf_size, bool last_buf, uint32_t *error_offset,
sys/dev/pci/if_ice.c
16283
uint32_t start, uint32_t count, bool indicate_last)
sys/dev/pci/if_ice.c
16303
bool last = false;
sys/dev/pci/if_ice.c
16424
bool save_bad_pac, bool pad_short_pac, bool double_vlan,
sys/dev/pci/if_ice.c
16528
ice_pkg_get_supported_vlan_mode(struct ice_hw *hw, bool *dvm)
sys/dev/pci/if_ice.c
16579
bool
sys/dev/pci/if_ice.c
16583
bool pkg_supports_dvm;
sys/dev/pci/if_ice.c
16622
bool
sys/dev/pci/if_ice.c
16652
bool
sys/dev/pci/if_ice.c
16829
bool
sys/dev/pci/if_ice.c
1690
bool
sys/dev/pci/if_ice.c
16968
ice_get_ddp_pkg_state(struct ice_hw *hw, bool already_loaded)
sys/dev/pci/if_ice.c
17576
bool flag = false;
sys/dev/pci/if_ice.c
17642
bool already_loaded = false;
sys/dev/pci/if_ice.c
17972
bool safe_mode, recovery_mode, have_rss;
sys/dev/pci/if_ice.c
18246
enum ice_vsi_type type, int idx, bool dynamic)
sys/dev/pci/if_ice.c
1840
void *desc, void *buf, uint16_t buf_len, bool response)
sys/dev/pci/if_ice.c
18479
bool
sys/dev/pci/if_ice.c
18654
bool
sys/dev/pci/if_ice.c
18679
ice_alloc_hw_res(struct ice_hw *hw, uint16_t type, uint16_t num, bool btm,
sys/dev/pci/if_ice.c
1887
bool
sys/dev/pci/if_ice.c
18941
ice_alloc_tcam_ent(struct ice_hw *hw, enum ice_block blk, bool btm,
sys/dev/pci/if_ice.c
18964
ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,
sys/dev/pci/if_ice.c
19055
bool used;
sys/dev/pci/if_ice.c
1916
bool cmd_completed = false;
sys/dev/pci/if_ice.c
19220
bool
sys/dev/pci/if_ice.c
19275
uint64_t hdl, bool rev, struct ice_chs_chg_head *chg)
sys/dev/pci/if_ice.c
19814
uint16_t buf_size, bool last_buf, uint32_t *error_offset,
sys/dev/pci/if_ice.c
19862
bool last = ((i + 1) == count);
sys/dev/pci/if_ice.c
20035
bool
sys/dev/pci/if_ice.c
20127
bool last_profile;
sys/dev/pci/if_ice.c
20128
bool only_vsi;
sys/dev/pci/if_ice.c
20365
bool
sys/dev/pci/if_ice.c
20639
bool keep_alloc = false;
sys/dev/pci/if_ice.c
20696
bool
sys/dev/pci/if_ice.c
20847
bool keep_vsi_alloc, struct ice_sq_cd *cd)
sys/dev/pci/if_ice.c
20930
struct ice_vsi_ctx *vsi_ctx, bool keep_vsi_alloc, struct ice_sq_cd *cd)
sys/dev/pci/if_ice.c
2127
bool is_cmd_for_retry;
sys/dev/pci/if_ice.c
21710
uint32_t *node_teids, bool suspend)
sys/dev/pci/if_ice.c
22315
uint16_t maxqs, uint8_t owner, bool enable)
sys/dev/pci/if_ice.c
22383
static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, uint8_t tc)
sys/dev/pci/if_ice.c
22607
bool
sys/dev/pci/if_ice.c
23204
bool
sys/dev/pci/if_ice.c
23259
ice_lldp_fltr_add_remove(struct ice_hw *hw, uint16_t vsi_num, bool add)
sys/dev/pci/if_ice.c
23448
ice_get_link_status(struct ice_port_info *pi, bool *link_up)
sys/dev/pci/if_ice.c
24107
ice_update_link_status(struct ice_softc *sc, bool update_media)
sys/dev/pci/if_ice.c
24168
struct ice_aqc_get_set_rss_keys *key, bool set)
sys/dev/pci/if_ice.c
24355
static inline bool ice_is_pow2(uint64_t n) {
sys/dev/pci/if_ice.c
2478
ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
sys/dev/pci/if_ice.c
25465
bool
sys/dev/pci/if_ice.c
25572
bool only_vsi;
sys/dev/pci/if_ice.c
25792
bool range)
sys/dev/pci/if_ice.c
26233
struct ice_aq_get_set_rss_lut_params *params, bool set)
sys/dev/pci/if_ice.c
26735
bool mdd_detected = false, request_reinit = false;
sys/dev/pci/if_ice.c
2705
bool
sys/dev/pci/if_ice.c
27930
bool
sys/dev/pci/if_ice.c
27934
bool needs_reconfig = false;
sys/dev/pci/if_ice.c
28000
ice_do_dcb_reconfig(struct ice_softc *sc, bool pending_mib)
sys/dev/pci/if_ice.c
28084
bool needs_reconfig, mib_is_pending;
sys/dev/pci/if_ice.c
28616
ice_stat_update40(struct ice_hw *hw, uint32_t reg, bool prev_stat_loaded,
sys/dev/pci/if_ice.c
28655
ice_stat_update32(struct ice_hw *hw, uint32_t reg, bool prev_stat_loaded,
sys/dev/pci/if_ice.c
28711
bool prev_stat_loaded, struct ice_eth_stats *cur_stats)
sys/dev/pci/if_ice.c
28918
bool reschedule = false;
sys/dev/pci/if_ice.c
2905
bool unloading)
sys/dev/pci/if_ice.c
29074
bool isvf;
sys/dev/pci/if_ice.c
2938
ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading)
sys/dev/pci/if_ice.c
29974
ice_aq_start_stop_dcbx(struct ice_hw *hw, bool start_dcbx_agent,
sys/dev/pci/if_ice.c
29975
bool *dcbx_agent_status, struct ice_sq_cd *cd)
sys/dev/pci/if_ice.c
30031
bool dcbx_agent_status;
sys/dev/pci/if_ice.c
30062
ice_aq_cfg_lldp_mib_change(struct ice_hw *hw, bool ena_update,
sys/dev/pci/if_ice.c
30089
ice_init_dcb(struct ice_hw *hw, bool enable_mib_change)
sys/dev/pci/if_ice.c
3211
bool
sys/dev/pci/if_ice.c
3221
bool
sys/dev/pci/if_ice.c
3263
bool
sys/dev/pci/if_ice.c
3326
ice_aq_fwlog_register(struct ice_hw *hw, bool reg)
sys/dev/pci/if_ice.c
338
bool link_up;
sys/dev/pci/if_ice.c
3436
bool second_bank_active;
sys/dev/pci/if_ice.c
3507
uint16_t length, void *data, bool last_command, bool read_shadow_ram,
sys/dev/pci/if_ice.c
3553
uint8_t *data, bool read_shadow_ram)
sys/dev/pci/if_ice.c
3558
bool last_cmd;
sys/dev/pci/if_ice.c
362
bool
sys/dev/pci/if_ice.c
377
ice_usec_delay(uint32_t time, bool sleep)
sys/dev/pci/if_ice.c
394
ice_msec_delay(uint32_t time, bool sleep)
sys/dev/pci/if_ice.c
4546
char const *prefix, bool dbg)
sys/dev/pci/if_ice.c
4580
char const *prefix, bool dbg)
sys/dev/pci/if_ice.c
4618
bool
sys/dev/pci/if_ice.c
4626
bool found = true;
sys/dev/pci/if_ice.c
4973
bool found;
sys/dev/pci/if_ice.c
5092
bool
sys/dev/pci/if_ice.c
5145
bool found;
sys/dev/pci/if_ice.c
5429
uint8_t type, uint16_t swid, uint16_t pf_vf_num, bool is_vf)
sys/dev/pci/if_ice.c
5480
bool is_vf = false;
sys/dev/pci/if_ice.c
6418
bool
sys/dev/pci/if_ice.c
6445
bool
sys/dev/pci/if_ice.c
6467
bool
sys/dev/pci/if_ice.c
6481
bool
sys/dev/pci/if_ice.c
6614
bool
sys/dev/pci/if_ice.c
6698
ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods,
sys/dev/pci/if_ice.c
6795
ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
sys/dev/pci/if_ice.c
6802
bool tx_pause, rx_pause;
sys/dev/pci/if_ice.c
7172
bool
sys/dev/pci/if_ice.c
7228
ice_aq_set_mac_cfg(struct ice_hw *hw, uint16_t max_frame_size, bool auto_drop,
sys/dev/pci/if_ice.c
8511
uint16_t num_vsi, uint16_t vsi_list_id, bool remove,
sys/dev/pci/if_ice.c
9309
bool
sys/dev/pci/if_ice.c
9996
bool found = false;
sys/dev/pci/if_icevar.h
1079
bool sec_rev_disabled;
sys/dev/pci/if_icevar.h
1080
bool update_disabled;
sys/dev/pci/if_icevar.h
1081
bool nvm_unified_update;
sys/dev/pci/if_icevar.h
1082
bool netlist_auth;
sys/dev/pci/if_icevar.h
1088
bool pcie_reset_avoidance; /* false: not supported, true: supported */
sys/dev/pci/if_icevar.h
1090
bool reset_restrict_support; /* false: not supported, true: supported */
sys/dev/pci/if_icevar.h
1100
bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
sys/dev/pci/if_icevar.h
1102
bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
sys/dev/pci/if_icevar.h
1104
bool ext_topo_dev_img_ver_schema[ICE_EXT_TOPO_DEV_IMG_COUNT];
sys/dev/pci/if_icevar.h
1106
bool tx_sched_topo_comp_mode_en;
sys/dev/pci/if_icevar.h
1107
bool dyn_flattening_en;
sys/dev/pci/if_icevar.h
1109
bool orom_recovery_update;
sys/dev/pci/if_icevar.h
142
static inline bool ice_is_bit_set_internal(uint16_t nr, const ice_bitmap_t *bitmap)
sys/dev/pci/if_icevar.h
170
static inline bool ice_test_and_clear_bit_internal(uint16_t nr,
sys/dev/pci/if_icevar.h
180
static inline bool ice_test_and_set_bit_internal(uint16_t nr, ice_bitmap_t *bitmap)
sys/dev/pci/if_icevar.h
197
static inline bool ice_is_bit_set(const ice_bitmap_t *bitmap, uint16_t nr)
sys/dev/pci/if_icevar.h
237
static inline bool
sys/dev/pci/if_icevar.h
252
static inline bool
sys/dev/pci/if_icevar.h
2903
bool symm; /* symmetric or asymmetric hash */
sys/dev/pci/if_icevar.h
2985
bool symm; /* Symmetric Hash for RSS */
sys/dev/pci/if_icevar.h
3938
bool fwlog_support_ena; /* does hardware support FW logging? */
sys/dev/pci/if_icevar.h
4015
bool subscribable_recipes_supported;
sys/dev/pci/if_icevar.h
4400
bool contig_only;
sys/dev/pci/if_icevar.h
4457
bool offsets_loaded;
sys/dev/pci/if_icevar.h
4516
bool offsets_loaded;
sys/dev/pci/if_icevar.h
4640
bool dynamic; /* if true, dynamically allocated */
sys/dev/pci/if_icevar.h
475
static inline bool ice_is_any_bit_set(ice_bitmap_t *bitmap, uint16_t size)
sys/dev/pci/if_icevar.h
545
static inline bool
sys/dev/pci/if_ix.c
2049
bool negotiate;
sys/dev/pci/if_ix.c
3663
bool negotiate;
sys/dev/pci/if_ix.h
204
bool lro_enabled;
sys/dev/pci/if_ix.h
205
bool hw_rsc;
sys/dev/pci/if_ix.h
206
bool discard;
sys/dev/pci/if_ix.h
248
bool link_up;
sys/dev/pci/if_ix.h
249
bool link_enabled;
sys/dev/pci/if_mwx.c
4390
bool cck;
sys/dev/pci/if_qwx_pci.c
1499
bool wakeup_required;
sys/dev/pci/if_qwx_pci.c
1525
bool wakeup_required;
sys/dev/pci/if_qwx_pci.c
2102
qwx_pci_sw_reset(struct qwx_softc *sc, bool power_on)
sys/dev/pci/if_qwx_pci.c
2121
qwx_pci_msi_config(struct qwx_softc *sc, bool enable)
sys/dev/pci/if_qwz_pci.c
1339
bool wakeup_required;
sys/dev/pci/if_qwz_pci.c
1365
bool wakeup_required;
sys/dev/pci/if_qwz_pci.c
1698
static inline bool
sys/dev/pci/if_qwz_pci.c
1969
qwz_pci_sw_reset(struct qwz_softc *sc, bool power_on)
sys/dev/pci/if_qwz_pci.c
1988
qwz_pci_msi_config(struct qwz_softc *sc, bool enable)
sys/dev/pci/igc_api.c
147
igc_setup_init_funcs(struct igc_hw *hw, bool init_device)
sys/dev/pci/igc_api.h
19
int igc_setup_init_funcs(struct igc_hw *, bool);
sys/dev/pci/igc_hw.h
242
int (*set_d0_lplu_state)(struct igc_hw *, bool);
sys/dev/pci/igc_hw.h
243
int (*set_d3_lplu_state)(struct igc_hw *, bool);
sys/dev/pci/igc_hw.h
287
bool asf_firmware_present;
sys/dev/pci/igc_hw.h
288
bool autoneg;
sys/dev/pci/igc_hw.h
289
bool get_link_status;
sys/dev/pci/igc_hw.h
311
bool polarity_correction;
sys/dev/pci/igc_hw.h
312
bool speed_downgraded;
sys/dev/pci/igc_hw.h
313
bool autoneg_wait_to_complete;
sys/dev/pci/igc_hw.h
341
bool send_xon;
sys/dev/pci/igc_hw.h
342
bool strict_ieee;
sys/dev/pci/igc_hw.h
348
bool eee_disable;
sys/dev/pci/igc_hw.h
349
bool clear_semaphore_once;
sys/dev/pci/igc_i225.c
1111
igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
sys/dev/pci/igc_i225.c
1112
bool adv100M)
sys/dev/pci/igc_i225.c
676
bool
sys/dev/pci/igc_i225.c
680
bool ret_val = false;
sys/dev/pci/igc_i225.c
892
igc_set_ltr_i225(struct igc_hw *hw, bool link)
sys/dev/pci/igc_i225.c
996
bool link = false;
sys/dev/pci/igc_i225.h
15
bool igc_get_flash_presence_i225(struct igc_hw *);
sys/dev/pci/igc_i225.h
27
int igc_set_ltr_i225(struct igc_hw *, bool);
sys/dev/pci/igc_i225.h
30
int igc_set_eee_i225(struct igc_hw *, bool, bool, bool);
sys/dev/pci/igc_phy.c
529
bool link;
sys/dev/pci/igc_phy.c
645
uint32_t usec_interval, bool *success)
sys/dev/pci/igc_phy.c
86
igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, bool IGC_UNUSEDARG active)
sys/dev/pci/igc_phy.c
863
uint16_t *data, bool read)
sys/dev/pci/igc_phy.h
16
int igc_null_lplu_state(struct igc_hw *, bool);
sys/dev/pci/igc_phy.h
24
int igc_phy_has_link_generic(struct igc_hw *, uint32_t, uint32_t, bool *);
sys/dev/pci/ixgbe.c
198
bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
sys/dev/pci/ixgbe.c
200
bool supported = FALSE;
sys/dev/pci/ixgbe.c
202
bool link_up;
sys/dev/pci/ixgbe.c
2182
bool clear)
sys/dev/pci/ixgbe.c
2563
bool link_up;
sys/dev/pci/ixgbe.c
277
bool locked = FALSE;
sys/dev/pci/ixgbe.c
2849
int32_t prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked,
sys/dev/pci/ixgbe.c
2867
bool locked)
sys/dev/pci/ixgbe.c
2920
bool link_up = 0;
sys/dev/pci/ixgbe.c
2924
bool locked = FALSE;
sys/dev/pci/ixgbe.c
2972
bool locked = FALSE;
sys/dev/pci/ixgbe.c
3227
int32_t ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, uint32_t vlan, bool vlvf_bypass)
sys/dev/pci/ixgbe.c
3278
bool vlan_on, bool vlvf_bypass)
sys/dev/pci/ixgbe.c
3345
bool vlan_on, uint32_t *vfta_delta, uint32_t vfta,
sys/dev/pci/ixgbe.c
3346
bool vlvf_bypass)
sys/dev/pci/ixgbe.c
3451
bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
sys/dev/pci/ixgbe.c
3480
bool *link_up, bool link_up_wait_to_complete)
sys/dev/pci/ixgbe.c
3708
uint32_t length, uint32_t timeout, bool return_data)
sys/dev/pci/ixgbe.c
3890
bool ixgbe_mng_present(struct ixgbe_hw *hw)
sys/dev/pci/ixgbe.c
3908
bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
sys/dev/pci/ixgbe.c
3939
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe.c
3946
bool autoneg, link_up = FALSE;
sys/dev/pci/ixgbe.c
4362
bool *link_up, bool link_up_wait_to_complete)
sys/dev/pci/ixgbe.c
65
bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
sys/dev/pci/ixgbe.c
67
int32_t prot_autoc_read_generic(struct ixgbe_hw *, bool *, uint32_t *);
sys/dev/pci/ixgbe.c
68
int32_t prot_autoc_write_generic(struct ixgbe_hw *, uint32_t, bool);
sys/dev/pci/ixgbe.h
197
ixgbe_mc_addr_itr func, bool clear);
sys/dev/pci/ixgbe.h
213
int32_t prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, uint32_t *reg_val);
sys/dev/pci/ixgbe.h
214
int32_t prot_autoc_write_generic(struct ixgbe_hw *hw, uint32_t reg_val, bool locked);
sys/dev/pci/ixgbe.h
224
uint32_t vind, bool vlan_on, bool);
sys/dev/pci/ixgbe.h
226
bool vlan_on, uint32_t*, uint32_t, bool);
sys/dev/pci/ixgbe.h
231
bool *link_up,
sys/dev/pci/ixgbe.h
232
bool link_up_wait_to_complete);
sys/dev/pci/ixgbe.h
238
bool return_data);
sys/dev/pci/ixgbe.h
242
bool ixgbe_mng_present(struct ixgbe_hw *hw);
sys/dev/pci/ixgbe.h
243
bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
sys/dev/pci/ixgbe.h
249
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe.h
272
bool *link_up, bool link_up_wait_to_complete);
sys/dev/pci/ixgbe.h
289
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr);
sys/dev/pci/ixgbe.h
305
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe.h
308
bool *autoneg);
sys/dev/pci/ixgbe.h
314
bool *link_up);
sys/dev/pci/ixgbe.h
322
bool ixgbe_is_sfp(struct ixgbe_hw *hw);
sys/dev/pci/ixgbe.h
323
int32_t ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
sys/dev/pci/ixgbe.h
346
uint16_t *val, bool lock);
sys/dev/pci/ixgbe.h
352
uint16_t val, bool lock);
sys/dev/pci/ixgbe.h
368
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe.h
370
bool *link_up, bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe.h
376
bool clear);
sys/dev/pci/ixgbe.h
378
int32_t ixgbe_get_link_state_vf(struct ixgbe_hw *hw, bool *link_state);
sys/dev/pci/ixgbe.h
380
bool vlan_on, bool vlvf_bypass);
sys/dev/pci/ixgbe_82598.c
1011
bool vlan_on, bool vlvf_bypass)
sys/dev/pci/ixgbe_82598.c
306
bool *autoneg)
sys/dev/pci/ixgbe_82598.c
425
bool link_up;
sys/dev/pci/ixgbe_82598.c
51
bool *autoneg);
sys/dev/pci/ixgbe_82598.c
55
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82598.c
566
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82598.c
58
ixgbe_link_speed *speed, bool *link_up,
sys/dev/pci/ixgbe_82598.c
59
bool link_up_wait_to_complete);
sys/dev/pci/ixgbe_82598.c
62
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82598.c
65
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82598.c
651
ixgbe_link_speed *speed, bool *link_up,
sys/dev/pci/ixgbe_82598.c
652
bool link_up_wait_to_complete)
sys/dev/pci/ixgbe_82598.c
72
uint32_t vind, bool vlan_on, bool vlvf_bypass);
sys/dev/pci/ixgbe_82598.c
741
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82598.c
743
bool autoneg = FALSE;
sys/dev/pci/ixgbe_82598.c
795
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82599.c
1031
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82599.c
1061
bool link_up = FALSE;
sys/dev/pci/ixgbe_82599.c
1510
bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
sys/dev/pci/ixgbe_82599.c
1512
bool lesm_enabled = FALSE;
sys/dev/pci/ixgbe_82599.c
286
int32_t prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,
sys/dev/pci/ixgbe_82599.c
316
int32_t prot_autoc_write_82599(struct ixgbe_hw *hw, uint32_t autoc, bool locked)
sys/dev/pci/ixgbe_82599.c
435
bool *autoneg)
sys/dev/pci/ixgbe_82599.c
51
bool *autoneg);
sys/dev/pci/ixgbe_82599.c
60
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82599.c
62
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82599.c
630
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82599.c
636
bool got_lock = FALSE;
sys/dev/pci/ixgbe_82599.c
65
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82599.c
78
int32_t prot_autoc_read_82599(struct ixgbe_hw *, bool *locked, uint32_t *reg_val);
sys/dev/pci/ixgbe_82599.c
79
int32_t prot_autoc_write_82599(struct ixgbe_hw *, uint32_t reg_val, bool locked);
sys/dev/pci/ixgbe_82599.c
797
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82599.c
802
bool link_up = FALSE;
sys/dev/pci/ixgbe_82599.c
85
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_82599.c
88
bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
sys/dev/pci/ixgbe_82599.c
909
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_82599.c
911
bool autoneg = FALSE;
sys/dev/pci/ixgbe_phy.c
1035
bool *autoneg)
sys/dev/pci/ixgbe_phy.c
1059
bool *link_up)
sys/dev/pci/ixgbe_phy.c
1110
bool autoneg = FALSE;
sys/dev/pci/ixgbe_phy.c
115
bool lock)
sys/dev/pci/ixgbe_phy.c
1223
bool end_data = FALSE;
sys/dev/pci/ixgbe_phy.c
1332
bool
sys/dev/pci/ixgbe_phy.c
1722
bool active_cable = FALSE;
sys/dev/pci/ixgbe_phy.c
2028
bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, uint8_t offset, uint8_t addr)
sys/dev/pci/ixgbe_phy.c
2049
uint8_t dev_addr, uint8_t *data, bool lock)
sys/dev/pci/ixgbe_phy.c
2055
bool nack = 1;
sys/dev/pci/ixgbe_phy.c
2175
uint8_t dev_addr, uint8_t data, bool lock)
sys/dev/pci/ixgbe_phy.c
224
uint16_t reg, uint16_t val, bool lock)
sys/dev/pci/ixgbe_phy.c
2350
bool bit = 0;
sys/dev/pci/ixgbe_phy.c
2375
bool bit;
sys/dev/pci/ixgbe_phy.c
2410
bool ack = 1;
sys/dev/pci/ixgbe_phy.c
2456
int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
sys/dev/pci/ixgbe_phy.c
2492
int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
sys/dev/pci/ixgbe_phy.c
2588
int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data)
sys/dev/pci/ixgbe_phy.c
2635
bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl)
sys/dev/pci/ixgbe_phy.c
2637
bool data;
sys/dev/pci/ixgbe_phy.c
2728
int32_t ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
sys/dev/pci/ixgbe_phy.c
359
static bool ixgbe_probe_phy(struct ixgbe_hw *hw, uint16_t phy_addr)
sys/dev/pci/ixgbe_phy.c
46
int32_t ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
sys/dev/pci/ixgbe_phy.c
47
int32_t ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
sys/dev/pci/ixgbe_phy.c
473
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr)
sys/dev/pci/ixgbe_phy.c
476
bool valid = FALSE;
sys/dev/pci/ixgbe_phy.c
50
int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data);
sys/dev/pci/ixgbe_phy.c
51
bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl);
sys/dev/pci/ixgbe_phy.c
863
bool autoneg = FALSE;
sys/dev/pci/ixgbe_phy.c
952
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_type.h
2505
(bool)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
sys/dev/pci/ixgbe_type.h
317
bool oem_valid;
sys/dev/pci/ixgbe_type.h
322
bool or_valid;
sys/dev/pci/ixgbe_type.h
3781
bool user_set_promisc;
sys/dev/pci/ixgbe_type.h
3800
bool send_xon; /* Flow control send XON */
sys/dev/pci/ixgbe_type.h
3801
bool strict_ieee; /* Strict IEEE mode */
sys/dev/pci/ixgbe_type.h
3802
bool disable_fc_autoneg; /* Do not autonegotiate FC */
sys/dev/pci/ixgbe_type.h
3803
bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
sys/dev/pci/ixgbe_type.h
3927
int32_t (*prot_autoc_read)(struct ixgbe_hw *, bool *, uint32_t *);
sys/dev/pci/ixgbe_type.h
3928
int32_t (*prot_autoc_write)(struct ixgbe_hw *, uint32_t, bool);
sys/dev/pci/ixgbe_type.h
3934
int32_t (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
sys/dev/pci/ixgbe_type.h
3935
int32_t (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
sys/dev/pci/ixgbe_type.h
3936
int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
sys/dev/pci/ixgbe_type.h
3938
bool *);
sys/dev/pci/ixgbe_type.h
3956
ixgbe_mc_addr_itr, bool clear);
sys/dev/pci/ixgbe_type.h
3958
int32_t (*get_link_state)(struct ixgbe_hw *hw, bool *link_state);
sys/dev/pci/ixgbe_type.h
3962
int32_t (*set_vfta)(struct ixgbe_hw *, uint32_t, uint32_t, bool, bool);
sys/dev/pci/ixgbe_type.h
3963
int32_t (*set_vlvf)(struct ixgbe_hw *, uint32_t, uint32_t, bool, uint32_t *, uint32_t,
sys/dev/pci/ixgbe_type.h
3964
bool);
sys/dev/pci/ixgbe_type.h
3967
void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
sys/dev/pci/ixgbe_type.h
3968
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
sys/dev/pci/ixgbe_type.h
3979
void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
sys/dev/pci/ixgbe_type.h
3984
int32_t (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);
sys/dev/pci/ixgbe_type.h
4000
int32_t (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
sys/dev/pci/ixgbe_type.h
4001
int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
sys/dev/pci/ixgbe_type.h
4017
int32_t (*set_phy_power)(struct ixgbe_hw *, bool on);
sys/dev/pci/ixgbe_type.h
4067
bool get_link_status;
sys/dev/pci/ixgbe_type.h
4070
bool arc_subsystem_valid;
sys/dev/pci/ixgbe_type.h
4071
bool orig_link_settings_stored;
sys/dev/pci/ixgbe_type.h
4072
bool autotry_restart;
sys/dev/pci/ixgbe_type.h
4075
bool set_lben;
sys/dev/pci/ixgbe_type.h
4085
bool sfp_setup_needed;
sys/dev/pci/ixgbe_type.h
4089
bool reset_disable;
sys/dev/pci/ixgbe_type.h
4095
bool smart_speed_active;
sys/dev/pci/ixgbe_type.h
4096
bool multispeed_fiber;
sys/dev/pci/ixgbe_type.h
4097
bool reset_if_overtemp;
sys/dev/pci/ixgbe_type.h
4098
bool qsfp_shared_i2c_bus;
sys/dev/pci/ixgbe_type.h
4324
bool adapter_stopped;
sys/dev/pci/ixgbe_type.h
4326
bool force_full_reset;
sys/dev/pci/ixgbe_type.h
4327
bool allow_unsupported_sfp;
sys/dev/pci/ixgbe_type.h
4328
bool wol_enabled;
sys/dev/pci/ixgbe_type.h
4329
bool need_crosstalk_fix;
sys/dev/pci/ixgbe_vf.c
375
bool clear)
sys/dev/pci/ixgbe_vf.c
454
int32_t ixgbe_get_link_state_vf(struct ixgbe_hw *hw, bool *link_state)
sys/dev/pci/ixgbe_vf.c
486
bool vlan_on, bool vlvf_bypass)
sys/dev/pci/ixgbe_vf.c
579
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_vf.c
594
bool *link_up, bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_x540.c
174
bool *autoneg)
sys/dev/pci/ixgbe_x540.c
200
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_x540.c
54
ixgbe_link_speed *speed, bool *autoneg);
sys/dev/pci/ixgbe_x540.c
57
bool link_up_wait_to_complete);
sys/dev/pci/ixgbe_x540.c
933
bool link_up;
sys/dev/pci/ixgbe_x550.c
1037
void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
sys/dev/pci/ixgbe_x550.c
107
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_x550.c
119
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_x550.c
121
bool *link_up, bool link_up_wait_to_complete);
sys/dev/pci/ixgbe_x550.c
1370
int32_t ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
sys/dev/pci/ixgbe_x550.c
1410
bool linear;
sys/dev/pci/ixgbe_x550.c
1432
bool linear;
sys/dev/pci/ixgbe_x550.c
1502
bool autoneg_wait)
sys/dev/pci/ixgbe_x550.c
1571
bool autoneg_wait)
sys/dev/pci/ixgbe_x550.c
1703
bool *autoneg)
sys/dev/pci/ixgbe_x550.c
1778
int32_t ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
sys/dev/pci/ixgbe_x550.c
1869
bool lsc;
sys/dev/pci/ixgbe_x550.c
2251
bool link_up = FALSE;
sys/dev/pci/ixgbe_x550.c
2443
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_x550.c
2447
bool setup_linear = FALSE;
sys/dev/pci/ixgbe_x550.c
2536
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_x550.c
2540
bool setup_linear = FALSE;
sys/dev/pci/ixgbe_x550.c
2765
int32_t ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
sys/dev/pci/ixgbe_x550.c
2805
bool link_up;
sys/dev/pci/ixgbe_x550.c
3542
bool link_up;
sys/dev/pci/ixgbe_x550.c
3774
bool link_up;
sys/dev/pci/ixgbe_x550.c
3863
bool link_up;
sys/dev/pci/ixgbe_x550.c
4196
bool lsc;
sys/dev/pci/ixgbe_x550.c
4223
bool autoneg_wait_to_complete)
sys/dev/pci/ixgbe_x550.c
4261
bool *link_up, bool link_up_wait_to_complete)
sys/dev/pci/ixgbe_x550.c
50
bool autoneg_wait_to_complete);
sys/dev/pci/ixgbe_x550.c
74
void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
sys/dev/pci/ixgbe_x550.c
768
int32_t ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
sys/dev/pci/ixgbe_x550.c
90
bool *autoneg);
sys/dev/usb/dwc2/dwc2.c
1195
bool qh_allocated = false;
sys/dev/usb/dwc2/dwc2_core.c
1015
STATIC int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
sys/dev/usb/dwc2/dwc2_core.c
1085
STATIC int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
sys/dev/usb/dwc2/dwc2_core.c
1160
STATIC int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
sys/dev/usb/dwc2/dwc2_core.c
145
bool restore)
sys/dev/usb/dwc2/dwc2_core.c
324
bool host_mode)
sys/dev/usb/dwc2/dwc2_core.c
363
static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.c
430
int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
sys/dev/usb/dwc2/dwc2_core.c
433
bool wait_for_host_mode = false;
sys/dev/usb/dwc2/dwc2_core.c
539
void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
sys/dev/usb/dwc2/dwc2_core.c
870
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.c
916
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.c
926
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.c
935
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.h
1114
bool bus_suspended;
sys/dev/usb/dwc2/dwc2_core.h
1147
bool needs_byte_swap;
sys/dev/usb/dwc2/dwc2_core.h
1198
bool new_connection;
sys/dev/usb/dwc2/dwc2_core.h
1325
static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.h
1330
static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.h
1335
static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
sys/dev/usb/dwc2/dwc2_core.h
1344
int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
sys/dev/usb/dwc2/dwc2_core.h
1347
bool restore);
sys/dev/usb/dwc2/dwc2_core.h
1352
int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
sys/dev/usb/dwc2/dwc2_core.h
1354
void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
sys/dev/usb/dwc2/dwc2_core.h
1357
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
sys/dev/usb/dwc2/dwc2_core.h
1410
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
sys/dev/usb/dwc2/dwc2_core.h
1411
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
sys/dev/usb/dwc2/dwc2_core.h
1412
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
sys/dev/usb/dwc2/dwc2_core.h
1447
bool reset);
sys/dev/usb/dwc2/dwc2_core.h
1461
bool restore);
sys/dev/usb/dwc2/dwc2_core.h
1482
bool reset) {}
sys/dev/usb/dwc2/dwc2_core.h
1504
bool restore)
sys/dev/usb/dwc2/dwc2_core.h
1524
void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
sys/dev/usb/dwc2/dwc2_core.h
1526
int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
sys/dev/usb/dwc2/dwc2_core.h
1536
int rem_wakeup, bool restore);
sys/dev/usb/dwc2/dwc2_core.h
1539
bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
sys/dev/usb/dwc2/dwc2_core.h
1551
static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
sys/dev/usb/dwc2/dwc2_core.h
1554
static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
sys/dev/usb/dwc2/dwc2_core.h
1574
int rem_wakeup, bool restore)
sys/dev/usb/dwc2/dwc2_core.h
1579
static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
sys/dev/usb/dwc2/dwc2_core.h
196
bool frame_overrun;
sys/dev/usb/dwc2/dwc2_core.h
265
bool hnp_support;
sys/dev/usb/dwc2/dwc2_core.h
266
bool srp_support;
sys/dev/usb/dwc2/dwc2_core.h
267
bool adp_support;
sys/dev/usb/dwc2/dwc2_core.h
507
bool phy_ulpi_ddr;
sys/dev/usb/dwc2/dwc2_core.h
508
bool phy_ulpi_ext_vbus;
sys/dev/usb/dwc2/dwc2_core.h
509
bool enable_dynamic_fifo;
sys/dev/usb/dwc2/dwc2_core.h
510
bool en_multiple_tx_fifo;
sys/dev/usb/dwc2/dwc2_core.h
511
bool i2c_enable;
sys/dev/usb/dwc2/dwc2_core.h
512
bool acg_enable;
sys/dev/usb/dwc2/dwc2_core.h
513
bool ulpi_fs_ls;
sys/dev/usb/dwc2/dwc2_core.h
514
bool ts_dline;
sys/dev/usb/dwc2/dwc2_core.h
515
bool reload_ctl;
sys/dev/usb/dwc2/dwc2_core.h
516
bool uframe_sched;
sys/dev/usb/dwc2/dwc2_core.h
517
bool external_id_pin_ctl;
sys/dev/usb/dwc2/dwc2_core.h
523
bool no_clock_gating;
sys/dev/usb/dwc2/dwc2_core.h
525
bool lpm;
sys/dev/usb/dwc2/dwc2_core.h
526
bool lpm_clock_gating;
sys/dev/usb/dwc2/dwc2_core.h
527
bool besl;
sys/dev/usb/dwc2/dwc2_core.h
528
bool hird_threshold_en;
sys/dev/usb/dwc2/dwc2_core.h
529
bool service_interval;
sys/dev/usb/dwc2/dwc2_core.h
531
bool activate_stm_fs_transceiver;
sys/dev/usb/dwc2/dwc2_core.h
532
bool activate_stm_id_vb_detection;
sys/dev/usb/dwc2/dwc2_core.h
533
bool activate_ingenic_overcurrent_detection;
sys/dev/usb/dwc2/dwc2_core.h
534
bool ipg_isoc_en;
sys/dev/usb/dwc2/dwc2_core.h
544
bool host_dma;
sys/dev/usb/dwc2/dwc2_core.h
545
bool dma_desc_enable;
sys/dev/usb/dwc2/dwc2_core.h
546
bool dma_desc_fs_enable;
sys/dev/usb/dwc2/dwc2_core.h
547
bool host_support_fs_ls_low_power;
sys/dev/usb/dwc2/dwc2_core.h
548
bool host_ls_low_power_phy_clk;
sys/dev/usb/dwc2/dwc2_core.h
549
bool oc_disable;
sys/dev/usb/dwc2/dwc2_core.h
557
bool g_dma;
sys/dev/usb/dwc2/dwc2_core.h
558
bool g_dma_desc;
sys/dev/usb/dwc2/dwc2_core.h
563
bool change_speed_quirk;
sys/dev/usb/dwc2/dwc2_core.h
754
bool valid;
sys/dev/usb/dwc2/dwc2_core.h
787
bool valid;
sys/dev/usb/dwc2/dwc2_core.h
808
bool valid;
sys/dev/usb/dwc2/dwc2_hcd.c
1810
void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
sys/dev/usb/dwc2/dwc2_hcd.c
2117
int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
sys/dev/usb/dwc2/dwc2_hcd.c
2932
bool no_queue_space = false;
sys/dev/usb/dwc2/dwc2_hcd.c
2933
bool no_fifo_space = false;
sys/dev/usb/dwc2/dwc2_hcd.c
4787
bool qh_allocated = false;
sys/dev/usb/dwc2/dwc2_hcd.c
5742
bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
sys/dev/usb/dwc2/dwc2_hcd.c
5849
int rem_wakeup, bool restore)
sys/dev/usb/dwc2/dwc2_hcd.h
618
static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
sys/dev/usb/dwc2/dwc2_hcd.h
619
static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
sys/dev/usb/dwc2/dwc2_hcd.h
620
static inline bool dbg_urb(struct urb *urb) { return true; }
sys/dev/usb/dwc2/dwc2_hcd.h
621
static inline bool dbg_perio(void) { return true; }
sys/dev/usb/dwc2/dwc2_hcd.h
623
static inline bool dbg_hc(struct dwc2_host_chan *hc)
sys/dev/usb/dwc2/dwc2_hcd.h
629
static inline bool dbg_qh(struct dwc2_qh *qh)
sys/dev/usb/dwc2/dwc2_hcd.h
636
static inline bool dbg_urb(struct urb *urb)
sys/dev/usb/dwc2/dwc2_hcd.h
643
static inline bool dbg_perio(void) { return false; }
sys/dev/usb/dwc2/dwc2_hcd.h
651
static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
sys/dev/usb/dwc2/dwc2_hcdintr.c
1449
bool past_end;
sys/dev/usb/dwc2/dwc2_hcdintr.c
1794
STATIC bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
sys/dev/usb/dwc2/dwc2_hcdintr.c
2055
STATIC bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1517
bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1518
bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1519
bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
sys/dev/usb/dwc2/dwc2_hcdqueue.c
1522
bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
sys/dev/usb/dwc2/dwc2_hcdqueue.c
243
int interval, int start, bool only_one_period)
sys/dev/usb/dwc2/dwc2_hcdqueue.c
465
bool printed = false;
sys/dev/usb/dwc2/dwc2_hcdqueue.c
668
bool only_one_period, int index)
sys/dev/usb/dwc2/dwc2_params.c
495
bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
sys/dev/usb/dwc2/dwc2_params.c
791
bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
sys/dev/usb/dwc2/dwc2var.h
89
bool sc_hcdenabled;
sys/dev/usb/ukspan.c
156
void ukspan_cmsg_init(bool, struct ukspan_cmsg *);
sys/dev/usb/ukspan.c
406
ukspan_cmsg_init(bool opening, struct ukspan_cmsg *omsg)
sys/net/pf.c
2811
pf_patch_8(struct pf_pdesc *pd, u_int8_t *f, u_int8_t v, bool hi)
sys/net/pf.c
2843
pf_patch_16_unaligned(struct pf_pdesc *pd, void *f, u_int16_t v, bool hi)
sys/net/pf.c
2883
pf_patch_32_unaligned(struct pf_pdesc *pd, void *f, u_int32_t v, bool hi)
sys/net/pfvar.h
1799
int pf_patch_8(struct pf_pdesc *, u_int8_t *, u_int8_t, bool);
sys/net/pfvar.h
1801
int pf_patch_16_unaligned(struct pf_pdesc *, void *, u_int16_t, bool);
sys/net/pfvar.h
1803
int pf_patch_32_unaligned(struct pf_pdesc *, void *, u_int32_t, bool);
sys/ufs/ext2fs/ext2fs_vfsops.c
340
bool huge = fs->e2fs.e2fs_features_rocompat & EXT2F_ROCOMPAT_HUGE_FILE;
usr.bin/awk/awk.h
276
bool anchor;
usr.bin/awk/awk.h
63
extern bool safe; /* false => unsafe, true => safe */
usr.bin/awk/awk.h
64
extern bool do_posix; /* true if POSIXLY_CORRECT set */
usr.bin/awk/awk.h
85
extern bool CSV; /* true for csv input */
usr.bin/awk/awk.h
90
extern bool donefld; /* true if record broken into fields */
usr.bin/awk/awk.h
91
extern bool donerec; /* true if record is valid (no fld has changed */
usr.bin/awk/awkgram.y
36
bool infunc = false; /* = true if in arglist or body of func */
usr.bin/awk/b.c
1266
bool commafound, digitfound;
usr.bin/awk/b.c
190
fa *makedfa(const char *s, bool anchor) /* returns dfa for reg expr s */
usr.bin/awk/b.c
228
fa *mkdfa(const char *s, bool anchor) /* does the real work of making a dfa */
usr.bin/awk/b.c
263
int makeinit(fa *f, bool anchor)
usr.bin/awk/b.c
864
bool fnematch(fa *pfa, FILE *f, char **pbuf, int *pbufsize, int quantum)
usr.bin/awk/lex.c
178
bool sc = false; /* true => return a } right now */
usr.bin/awk/lex.c
179
bool reg = false; /* true => return a REGEXPR now */
usr.bin/awk/lex.c
34
extern bool infunc;
usr.bin/awk/lib.c
137
static bool firsttime = true;
usr.bin/awk/lib.c
139
int getrec(char **pbuf, int *pbufsize, bool isrecord) /* get next input record */
usr.bin/awk/lib.c
221
extern int readcsvrec(char **pbuf, int *pbufsize, FILE *inf, bool newflag);
usr.bin/awk/lib.c
223
int readrec(char **pbuf, int *pbufsize, FILE *inf, bool newflag) /* read one record into buf */
usr.bin/awk/lib.c
234
bool found;
usr.bin/awk/lib.c
294
int readcsvrec(char **pbuf, int *pbufsize, FILE *inf, bool newflag) /* csv can have \n's */
usr.bin/awk/lib.c
299
bool in_quote = false;
usr.bin/awk/lib.c
40
bool innew; /* true = infile has not been read by readrec */
usr.bin/awk/lib.c
54
bool donefld; /* true = implies rec broken into fields */
usr.bin/awk/lib.c
55
bool donerec; /* true = record is valid (no flds have changed) */
usr.bin/awk/lib.c
874
bool is_valid_number(const char *s, bool trailing_stuff_ok,
usr.bin/awk/lib.c
875
bool *no_trailing, double *result)
usr.bin/awk/lib.c
879
bool retval = false;
usr.bin/awk/lib.c
880
bool is_nan = false;
usr.bin/awk/lib.c
881
bool is_inf = false;
usr.bin/awk/main.c
55
bool CSV = false; /* true for csv input */
usr.bin/awk/main.c
56
bool safe = false; /* true => "safe" mode */
usr.bin/awk/main.c
57
bool do_posix = false; /* true => POSIX mode */
usr.bin/awk/proto.h
122
extern int getrec(char **, int *, bool);
usr.bin/awk/proto.h
124
extern int readrec(char **buf, int *bufsize, FILE *inf, bool isnew);
usr.bin/awk/proto.h
148
extern bool is_valid_number(const char *s, bool trailing_stuff_ok,
usr.bin/awk/proto.h
149
bool *no_trailing, double *result);
usr.bin/awk/proto.h
194
extern FILE *openfile(int, const char *, bool *);
usr.bin/awk/proto.h
39
extern fa *makedfa(const char *, bool);
usr.bin/awk/proto.h
40
extern fa *mkdfa(const char *, bool);
usr.bin/awk/proto.h
41
extern int makeinit(fa *, bool);
usr.bin/awk/proto.h
54
extern bool fnematch(fa *, FILE *, char **, int *, int);
usr.bin/awk/run.c
1088
static bool first = true;
usr.bin/awk/run.c
1089
static bool have_a_format = false;
usr.bin/awk/run.c
2364
FILE *openfile(int a, const char *us, bool *pnewflag)
usr.bin/awk/run.c
2446
bool stat;
usr.bin/awk/run.c
2486
bool stat = false;
usr.bin/awk/run.c
412
bool newflag;
usr.bin/awk/run.c
889
bool x_is_nan, y_is_nan;
usr.bin/awk/tran.c
401
bool no_trailing;
usr.bin/bc/bc.y
101
static bool st_has_continue;
usr.bin/bc/bc.y
103
static bool do_fork = true;
usr.bin/bc/extern.h
43
extern bool interactive;
usr.bin/chpass/getpwent.c
192
struct passwd **pwretp, bool shadow, bool reentrant)
usr.bin/chpass/getpwent.c
266
struct passwd **pwretp, bool shadow, bool reentrant)
usr.bin/chpass/getpwent.c
77
bool remap = true;
usr.bin/compress/main.c
974
const bool gzip = (__progname[0] == 'g');
usr.bin/ctags/ctags.c
49
bool _wht[256], _itk[256], _btk[256];
usr.bin/ctags/ctags.h
58
bool been_warned; /* set if noticed dup */
usr.bin/ctags/ctags.h
59
bool dynfile; /* set if file will need freed */
usr.bin/ctags/ctags.h
72
extern bool _wht[], _itk[], _btk[];
usr.bin/ctags/ctags.h
76
extern bool in_preload;
usr.bin/ctags/fortran.c
47
bool pfcnt; /* pascal/fortran functions found */
usr.bin/ctags/tree.c
42
bool in_preload = NO;
usr.bin/ctags/yacc.c
49
bool in_rule;
usr.bin/dc/bcode.c
108
static bool compare_numbers(enum bcode_compare, struct number *,
usr.bin/dc/bcode.c
1160
bool neg;
usr.bin/dc/bcode.c
1408
static bool
usr.bin/dc/bcode.c
1448
bool ok;
usr.bin/dc/bcode.c
226
init_bmachine(bool extended_registers)
usr.bin/dc/bcode.c
43
bool extended_regs;
usr.bin/dc/bcode.h
86
void init_bmachine(bool);
usr.bin/dc/dc.c
44
bool extended_regs = false;
usr.bin/dc/inout.c
182
bool sign = false;
usr.bin/dc/inout.c
183
bool dot = false;
usr.bin/dc/inout.c
234
bool escape;
usr.bin/dc/stack.c
25
static __inline bool stack_empty(const struct stack *);
usr.bin/dc/stack.c
42
static __inline bool
usr.bin/dc/stack.c
45
bool empty = stack->sp == -1;
usr.bin/ftp/cmds.c
457
onoff(int bool)
usr.bin/ftp/cmds.c
460
return (bool ? "on" : "off");
usr.bin/gprof/arcs.c
450
bool ret;
usr.bin/gprof/arcs.c
451
bool done;
usr.bin/gprof/arcs.c
522
bool ret;
usr.bin/gprof/dfn.c
127
bool
usr.bin/gprof/dfn.c
137
bool
usr.bin/gprof/elf.c
141
static bool
usr.bin/gprof/elf.c
42
static bool wantsym(const Elf_Sym *, const char *);
usr.bin/gprof/gprof.c
64
bool aflag; /* suppress static functions */
usr.bin/gprof/gprof.c
65
bool bflag; /* blurbs, too */
usr.bin/gprof/gprof.c
66
bool cflag; /* discovered call graph, too */
usr.bin/gprof/gprof.c
67
bool Cflag; /* find cut-set to eliminate cycles */
usr.bin/gprof/gprof.c
68
bool dflag; /* debugging options */
usr.bin/gprof/gprof.c
69
bool eflag; /* specific functions excluded */
usr.bin/gprof/gprof.c
70
bool Eflag; /* functions excluded with time */
usr.bin/gprof/gprof.c
71
bool fflag; /* specific functions requested */
usr.bin/gprof/gprof.c
72
bool Fflag; /* functions requested with time */
usr.bin/gprof/gprof.c
73
bool kflag; /* arcs to be deleted */
usr.bin/gprof/gprof.c
74
bool sflag; /* sum multiple gmon.out files */
usr.bin/gprof/gprof.c
75
bool zflag; /* zero time/called functions, too */
usr.bin/gprof/gprof.h
202
extern bool aflag; /* suppress static functions */
usr.bin/gprof/gprof.h
203
extern bool bflag; /* blurbs, too */
usr.bin/gprof/gprof.h
204
extern bool cflag; /* discovered call graph, too */
usr.bin/gprof/gprof.h
205
extern bool Cflag; /* find cut-set to eliminate cycles */
usr.bin/gprof/gprof.h
206
extern bool dflag; /* debugging options */
usr.bin/gprof/gprof.h
207
extern bool eflag; /* specific functions excluded */
usr.bin/gprof/gprof.h
208
extern bool Eflag; /* functions excluded with time */
usr.bin/gprof/gprof.h
209
extern bool fflag; /* specific functions requested */
usr.bin/gprof/gprof.h
210
extern bool Fflag; /* functions requested with time */
usr.bin/gprof/gprof.h
211
extern bool kflag; /* arcs to be deleted */
usr.bin/gprof/gprof.h
212
extern bool sflag; /* sum multiple gmon.out files */
usr.bin/gprof/gprof.h
213
extern bool zflag; /* zero time/called functions, too */
usr.bin/gprof/gprof.h
246
bool dfn_busy(nltype *);
usr.bin/gprof/gprof.h
249
bool dfn_numbered(nltype *);
usr.bin/gprof/gprof.h
270
bool onlist(struct stringlist *, const char *);
usr.bin/gprof/printlist.c
69
bool
usr.bin/grep/util.c
54
static bool grep_cmp(const char *, const char *, size_t);
usr.bin/grep/util.c
627
static bool
usr.bin/infocmp/infocmp.c
144
static bool
usr.bin/infocmp/infocmp.c
147
bool result = (value == ABSENT_BOOLEAN);
usr.bin/infocmp/infocmp.c
153
static bool
usr.bin/infocmp/infocmp.c
1540
bool formatted = FALSE;
usr.bin/infocmp/infocmp.c
1541
bool filecompare = FALSE;
usr.bin/infocmp/infocmp.c
1543
bool init_analyze = FALSE;
usr.bin/infocmp/infocmp.c
1544
bool suppress_untranslatable = FALSE;
usr.bin/infocmp/infocmp.c
1546
bool wrap_strings = FALSE;
usr.bin/infocmp/infocmp.c
156
bool result = (value == ABSENT_NUMERIC);
usr.bin/infocmp/infocmp.c
162
static bool
usr.bin/infocmp/infocmp.c
165
bool result = (value == ABSENT_STRING);
usr.bin/infocmp/infocmp.c
275
static bool
usr.bin/infocmp/infocmp.c
286
bool foundmatch = FALSE;
usr.bin/infocmp/infocmp.c
302
static bool
usr.bin/infocmp/infocmp.c
460
bool found;
usr.bin/infocmp/infocmp.c
66
static bool limited = TRUE; /* "-r" option is not set */
usr.bin/infocmp/infocmp.c
67
static bool quiet = FALSE;
usr.bin/infocmp/infocmp.c
68
static bool literal = FALSE;
usr.bin/infocmp/infocmp.c
773
static bool
usr.bin/infocmp/infocmp.c
776
bool result = FALSE;
usr.bin/infocmp/infocmp.c
793
bool found = FALSE;
usr.bin/infocmp/infocmp.c
87
static bool ignorepads; /* ignore pad prefixes when diffing */
usr.bin/jot/jot.c
253
bool use_unif = 0;
usr.bin/jot/jot.c
306
putdata(double x, bool last)
usr.bin/jot/jot.c
65
static bool boring;
usr.bin/jot/jot.c
66
static bool chardata;
usr.bin/jot/jot.c
67
static bool finalnl = true;
usr.bin/jot/jot.c
68
static bool infinity;
usr.bin/jot/jot.c
69
static bool intdata;
usr.bin/jot/jot.c
70
static bool longdata;
usr.bin/jot/jot.c
71
static bool nosign;
usr.bin/jot/jot.c
72
static bool randomize;
usr.bin/jot/jot.c
73
static bool word;
usr.bin/jot/jot.c
77
static int putdata(double, bool);
usr.bin/lex/ccl.c
286
bool
usr.bin/lex/ccl.c
311
bool
usr.bin/lex/ccl.c
39
static bool
usr.bin/lex/filter.c
128
bool
usr.bin/lex/filter.c
238
bool write_header;
usr.bin/lex/filter.c
346
bool in_gen = true; /* in generated code */
usr.bin/lex/filter.c
347
bool last_was_blank = false;
usr.bin/lex/flexdef.h
1114
bool has_case(int c);
usr.bin/lex/flexdef.h
1120
bool range_covers_case (int c1, int c2);
usr.bin/lex/flexdef.h
1144
extern bool filter_apply_chain PROTO((struct filter * chain));
usr.bin/lex/flexdef.h
1155
bool flex_init_regex(void);
usr.bin/lex/flexdef.h
1161
bool regmatch_empty (regmatch_t * m);
usr.bin/lex/flexdef.h
370
extern bool ansi_func_defs, ansi_func_protos;
usr.bin/lex/flexdef.h
477
extern bool *rule_has_nl, *ccl_has_nl;
usr.bin/lex/flexdef.h
651
(bool *) allocate_array( size, sizeof( bool ) )
usr.bin/lex/flexdef.h
654
(bool *) reallocate_array( (void *) array, size, sizeof( bool ) )
usr.bin/lex/main.c
106
bool *rule_has_nl, *ccl_has_nl;
usr.bin/lex/main.c
108
bool ansi_func_defs, ansi_func_protos;
usr.bin/lex/main.c
110
bool tablesext, tablesverify, gentables;
usr.bin/lex/misc.c
57
bool dc; /**< do_copy */
usr.bin/lex/misc.c
62
sko_push(bool dc)
usr.bin/lex/misc.c
798
bool do_copy = true;
usr.bin/lex/misc.c
80
sko_peek(bool * dc)
usr.bin/lex/misc.c
88
sko_pop(bool * dc)
usr.bin/lex/regex.c
169
bool regmatch_empty (regmatch_t * m)
usr.bin/lex/regex.c
39
bool flex_init_regex(void)
usr.bin/lex/tables.h
64
extern bool tablesext, tablesverify,gentables;
usr.bin/make/arch.c
146
static struct timespec ArchMTimeMember(const char *, const char *, bool);
usr.bin/make/arch.c
153
static bool parse_archive(Buffer, const char **, Lst, SymTable *);
usr.bin/make/arch.c
191
bool
usr.bin/make/arch.c
194
bool result;
usr.bin/make/arch.c
212
static bool
usr.bin/make/arch.c
220
bool subst_lib;
usr.bin/make/arch.c
251
bool subst_member = false;
usr.bin/make/arch.c
519
bool hash) /* true if archive should be hashed if not
usr.bin/make/arch.h
45
extern bool Arch_ParseArchive(const char **, Lst, SymTable *);
usr.bin/make/cmd_exec.c
83
run_command(const char *cmd, bool errCheck)
usr.bin/make/cmd_exec.h
38
extern __dead void run_command(const char *, bool);
usr.bin/make/compat.c
260
Compat_Run(Lst targs, bool *has_errors, bool *out_of_date)
usr.bin/make/compat.c
77
bool cmdsOk;
usr.bin/make/compat.h
41
extern void Compat_Run(Lst, bool *, bool *);
usr.bin/make/cond.c
102
static bool CondGetArg(const char **, struct Name *,
usr.bin/make/cond.c
103
const char *, bool);
usr.bin/make/cond.c
104
static bool CondDoDefined(struct Name *);
usr.bin/make/cond.c
105
static bool CondDoMake(struct Name *);
usr.bin/make/cond.c
106
static bool CondDoExists(struct Name *);
usr.bin/make/cond.c
107
static bool CondDoTarget(struct Name *);
usr.bin/make/cond.c
108
static bool CondDoTargetWithCommands(struct Name *);
usr.bin/make/cond.c
109
static bool CondCvtArg(const char *, double *);
usr.bin/make/cond.c
110
static Token CondToken(bool);
usr.bin/make/cond.c
111
static Token CondT(bool);
usr.bin/make/cond.c
112
static Token CondF(bool);
usr.bin/make/cond.c
113
static Token CondE(bool);
usr.bin/make/cond.c
114
static Token CondHandleVarSpec(bool);
usr.bin/make/cond.c
115
static Token CondHandleDefault(bool);
usr.bin/make/cond.c
116
static Token CondHandleComparison(char *, bool, bool);
usr.bin/make/cond.c
117
static Token CondHandleString(bool);
usr.bin/make/cond.c
118
static Token CondHandleNumber(bool);
usr.bin/make/cond.c
123
bool isElse; /* true for else forms */
usr.bin/make/cond.c
124
bool doNot; /* true for embedded negation */
usr.bin/make/cond.c
125
bool (*defProc)(struct Name *); /* function to apply */
usr.bin/make/cond.c
152
static bool condInvert; /* Invert the default function */
usr.bin/make/cond.c
153
static bool (*condDefProc)(struct Name *);
usr.bin/make/cond.c
161
bool value;
usr.bin/make/cond.c
167
static bool skipLine = false; /* Whether the parse module is skipping lines */
usr.bin/make/cond.c
193
static bool
usr.bin/make/cond.c
195
bool parens) /* true if arg should be bounded by parens */
usr.bin/make/cond.c
250
static bool
usr.bin/make/cond.c
267
static bool
usr.bin/make/cond.c
290
static bool
usr.bin/make/cond.c
293
bool result;
usr.bin/make/cond.c
318
static bool
usr.bin/make/cond.c
339
static bool
usr.bin/make/cond.c
368
static bool
usr.bin/make/cond.c
396
CondHandleNumber(bool doEval)
usr.bin/make/cond.c
410
CondHandleVarSpec(bool doEval)
usr.bin/make/cond.c
414
bool doFree;
usr.bin/make/cond.c
448
CondHandleString(bool doEval)
usr.bin/make/cond.c
470
CondHandleComparison(char *lhs, bool doFree, bool doEval)
usr.bin/make/cond.c
575
bool freeIt;
usr.bin/make/cond.c
643
bool (*proc)(struct Name *);
usr.bin/make/cond.c
654
CondHandleDefault(bool doEval)
usr.bin/make/cond.c
656
bool t;
usr.bin/make/cond.c
657
bool (*evalProc)(struct Name *);
usr.bin/make/cond.c
658
bool invert = false;
usr.bin/make/cond.c
667
bool doFree;
usr.bin/make/cond.c
745
CondToken(bool doEval)
usr.bin/make/cond.c
810
CondT(bool doEval)
usr.bin/make/cond.c
850
CondF(bool doEval)
usr.bin/make/cond.c
890
CondE(bool doEval)
usr.bin/make/cond.c
935
bool value = false;
usr.bin/make/dir.c
231
static bool read_directory(struct PathEntry *);
usr.bin/make/dir.c
295
static bool
usr.bin/make/dir.c
413
bool checkCurdirFirst)
usr.bin/make/dir.c
422
bool hasSlash;
usr.bin/make/dir.c
530
bool checkedDot = false;
usr.bin/make/dir.h
103
extern char *Dir_FindFileComplexi(const char *, const char *, Lst, bool);
usr.bin/make/direxpand.c
188
bool dowild; /* Wildcard left after curlies ? */
usr.bin/make/direxpand.c
305
bool
usr.bin/make/direxpand.c
309
bool wild = false;
usr.bin/make/direxpand.h
43
extern bool Dir_HasWildcardsi(const char *, const char *);
usr.bin/make/dump.c
103
TargPrintNode(GNode *gn, bool full)
usr.bin/make/dump.c
167
bool first = true;
usr.bin/make/dump.c
182
targ_dump(bool full)
usr.bin/make/dump.c
203
static bool dumped_once = false;
usr.bin/make/dump.c
46
static void targ_dump(bool);
usr.bin/make/engine.c
104
static bool
usr.bin/make/engine.c
118
bool
usr.bin/make/engine.c
166
bool first = true;
usr.bin/make/engine.c
337
bool do_oodate;
usr.bin/make/engine.c
420
bool
usr.bin/make/engine.c
423
bool oodate;
usr.bin/make/engine.c
522
bool silent;
usr.bin/make/engine.c
613
static bool
usr.bin/make/engine.c
616
bool silent; /* Don't print command */
usr.bin/make/engine.c
617
bool doExecute; /* Execute the command */
usr.bin/make/engine.c
618
bool errCheck; /* Check errors */
usr.bin/make/engine.c
699
bool
usr.bin/make/engine.c
702
bool started;
usr.bin/make/engine.h
133
extern bool job_run_next(Job *);
usr.bin/make/engine.h
45
extern bool node_find_valid_commands(GNode *);
usr.bin/make/engine.h
72
extern bool Make_OODate(GNode *);
usr.bin/make/enginechoice.c
32
void (*run_list)(Lst, bool *, bool *);
usr.bin/make/enginechoice.c
41
choose_engine(bool compat)
usr.bin/make/enginechoice.c
48
engine_run_list(Lst l, bool *has_errors, bool *out_of_date)
usr.bin/make/enginechoice.h
29
extern void engine_run_list(Lst, bool *, bool *);
usr.bin/make/enginechoice.h
31
extern void choose_engine(bool);
usr.bin/make/error.c
148
static bool first = true;
usr.bin/make/extern.h
43
extern bool ignoreErrors; /* True if should ignore all errors */
usr.bin/make/extern.h
44
extern bool beSilent; /* True if should print no commands */
usr.bin/make/extern.h
45
extern bool noExecute; /* True if should execute nothing */
usr.bin/make/extern.h
46
extern bool allPrecious; /* True if every target is precious */
usr.bin/make/extern.h
47
extern bool keepgoing; /* True if should continue on unaffected
usr.bin/make/extern.h
50
extern bool touchFlag; /* true if targets should just be 'touched'
usr.bin/make/extern.h
52
extern bool queryFlag; /* true if we aren't supposed to really make
usr.bin/make/for.c
101
bool freeold;
usr.bin/make/for.c
210
bool
usr.bin/make/for.h
47
extern bool For_Accumulate(For *, const char *);
usr.bin/make/gnode.h
108
bool must_make; /* true if this target needs building */
usr.bin/make/gnode.h
109
bool child_rebuilt; /* true if at least one child was rebuilt,
usr.bin/make/gnode.h
155
bool in_cycle; /* cycle detection */
usr.bin/make/job.c
115
static bool no_new_jobs; /* Mark recursive shit so we shouldn't start
usr.bin/make/job.c
118
bool sequential;
usr.bin/make/job.c
139
static bool reap_jobs(void);
usr.bin/make/job.c
142
static bool expensive_job(Job *);
usr.bin/make/job.c
143
static bool expensive_command(const char *);
usr.bin/make/job.c
211
static bool first = true;
usr.bin/make/job.c
221
quick_error(Job *j, int signo, bool first)
usr.bin/make/job.c
236
static bool first = true;
usr.bin/make/job.c
280
bool first = true;
usr.bin/make/job.c
410
bool first = true;
usr.bin/make/job.c
588
static bool
usr.bin/make/job.c
598
static bool
usr.bin/make/job.c
602
bool include = false;
usr.bin/make/job.c
603
bool expensive = false;
usr.bin/make/job.c
658
bool finished = job_run_next(job);
usr.bin/make/job.c
748
static bool
usr.bin/make/job.c
753
bool reaped = false;
usr.bin/make/job.c
846
bool
usr.bin/make/job.c
855
bool
usr.bin/make/job.h
100
extern bool sequential; /* True if we are running one single-job */
usr.bin/make/job.h
64
extern bool can_start_job(void);
usr.bin/make/job.h
69
extern bool Job_Empty(void);
usr.bin/make/lowparse.c
125
static bool
usr.bin/make/lowparse.c
220
bool
usr.bin/make/lowparse.h
86
extern bool Parse_NextFile(void);
usr.bin/make/lst.h
137
extern bool Lst_AddNew(Lst, void *);
usr.bin/make/lst.h
62
typedef bool (*FindProc)(void *, void *);
usr.bin/make/lst.h
63
typedef bool (*FindProcConst)(void *, const void *);
usr.bin/make/lst.lib/lst.h
132
extern bool Lst_AddNew(Lst, void *);
usr.bin/make/lst.lib/lstAddNew.c
38
bool
usr.bin/make/main.c
112
static void read_all_make_rules(bool, bool, Lst, struct dirs *);
usr.bin/make/main.c
114
static bool ReadMakefile(void *, void *);
usr.bin/make/main.c
601
read_all_make_rules(bool noBuiltins, bool read_depend,
usr.bin/make/main.c
632
run_node(GNode *gn, bool *has_errors, bool *out_of_date)
usr.bin/make/main.c
648
bool outOfDate = false; /* false if all targets up to date */
usr.bin/make/main.c
649
bool errored = false; /* true if errors occurred */
usr.bin/make/main.c
656
bool read_depend = true;/* false if we don't want to read .depend */
usr.bin/make/main.c
72
bool allPrecious; /* .PRECIOUS given on line by itself */
usr.bin/make/main.c
74
static bool noBuiltins; /* -r flag */
usr.bin/make/main.c
78
static bool compatMake; /* -B argument */
usr.bin/make/main.c
79
static bool forceJobs = false;
usr.bin/make/main.c
81
bool noExecute; /* -n flag */
usr.bin/make/main.c
82
bool keepgoing; /* -k flag */
usr.bin/make/main.c
83
bool queryFlag; /* -q flag */
usr.bin/make/main.c
84
bool touchFlag; /* -t flag */
usr.bin/make/main.c
85
bool ignoreErrors; /* -i flag */
usr.bin/make/main.c
86
bool beSilent; /* -s flag */
usr.bin/make/main.c
87
bool dumpData; /* -p flag */
usr.bin/make/main.c
882
static bool
usr.bin/make/make.c
101
static bool MakeStartJobs(void);
usr.bin/make/make.c
105
static bool targets_contain_cycles(void);
usr.bin/make/make.c
110
static bool try_to_make_node(GNode *);
usr.bin/make/make.c
113
static bool has_predecessor_left_to_build(GNode *);
usr.bin/make/make.c
117
static bool randomize_queue;
usr.bin/make/make.c
120
bool
usr.bin/make/make.c
159
static bool
usr.bin/make/make.c
305
static bool
usr.bin/make/make.c
411
static bool
usr.bin/make/make.c
534
Make_Run(Lst targs, bool *has_errors, bool *out_of_date)
usr.bin/make/make.c
592
static bool
usr.bin/make/make.c
597
bool cycle = false;
usr.bin/make/make.c
598
bool first = true;
usr.bin/make/make.h
44
extern void Make_Run(Lst, bool *, bool *);
usr.bin/make/make.h
47
extern bool nothing_left_to_build(void);
usr.bin/make/parse.c
103
static bool htargets_setup = false;
usr.bin/make/parse.c
1089
resolve_include_filename(const char *file, const char *efile, bool isSystem)
usr.bin/make/parse.c
1144
handle_include_file(const char *file, const char *efile, bool isSystem,
usr.bin/make/parse.c
1145
bool errIfNotFound)
usr.bin/make/parse.c
1166
static bool
usr.bin/make/parse.c
1172
bool isSystem;
usr.bin/make/parse.c
1210
bool errIfMissing)
usr.bin/make/parse.c
1215
bool okay = false;
usr.bin/make/parse.c
1268
static bool
usr.bin/make/parse.c
1273
bool not = false;
usr.bin/make/parse.c
1274
bool paren_to_match = false;
usr.bin/make/parse.c
1336
static bool
usr.bin/make/parse.c
1343
bool ok;
usr.bin/make/parse.c
1360
static bool
usr.bin/make/parse.c
1374
static bool
usr.bin/make/parse.c
1413
static bool
usr.bin/make/parse.c
1437
bool seen_target = false;
usr.bin/make/parse.c
146
static bool handle_poison(const char *);
usr.bin/make/parse.c
147
static bool handle_for_loop(Buffer, const char *);
usr.bin/make/parse.c
148
static bool handle_undef(const char *);
usr.bin/make/parse.c
150
static bool handle_bsd_command(Buffer, Buffer, const char *);
usr.bin/make/parse.c
151
static bool register_target(GNode *, struct ohash *);
usr.bin/make/parse.c
153
static char *resolve_include_filename(const char *, const char *, bool);
usr.bin/make/parse.c
154
static void handle_include_file(const char *, const char *, bool, bool);
usr.bin/make/parse.c
155
static bool lookup_bsd_include(const char *);
usr.bin/make/parse.c
1552
static bool
usr.bin/make/parse.c
156
static void lookup_sysv_style_include(const char *, const char *, bool);
usr.bin/make/parse.c
1581
const char *stripped, bool *pcommands_seen)
usr.bin/make/parse.c
159
static bool parse_as_special_line(Buffer, Buffer, const char *);
usr.bin/make/parse.c
1630
bool expectingCommands = false;
usr.bin/make/parse.c
1631
bool commands_seen = false;
usr.bin/make/parse.c
164
const char *, bool *);
usr.bin/make/parse.c
169
static bool found_delimiter(const char *);
usr.bin/make/parse.c
584
static bool
usr.bin/make/parsevar.c
181
bool saved = errorIsOkay;
usr.bin/make/parsevar.c
208
bool
usr.bin/make/parsevar.c
214
bool
usr.bin/make/parsevar.c
217
bool result;
usr.bin/make/parsevar.c
218
bool saved = errorIsOkay;
usr.bin/make/parsevar.c
41
static bool parse_variable_assignment(const char *, int);
usr.bin/make/parsevar.c
57
static bool
usr.bin/make/parsevar.h
36
extern bool Parse_As_Var_Assignment(const char *);
usr.bin/make/parsevar.h
40
extern bool Parse_CmdlineVar(const char *);
usr.bin/make/stats.c
55
static bool mmapped = false;
usr.bin/make/str.c
237
static bool
usr.bin/make/str.c
266
static bool
usr.bin/make/str.c
316
bool
usr.bin/make/str.c
46
static bool range_match(char, const char **, const char *);
usr.bin/make/str.c
47
static bool star_match(const char *, const char *, const char *, const char *);
usr.bin/make/str.h
64
extern bool Str_Matchi(const char *, const char *, const char *, const char *);
usr.bin/make/suff.c
147
static bool parse_transformi(const char *, const char *, Suff **, Suff **);
usr.bin/make/suff.c
1521
bool first = true;
usr.bin/make/suff.c
1546
bool reprint;
usr.bin/make/suff.c
160
static bool SuffRemoveSrc(Lst);
usr.bin/make/suff.c
164
static bool SuffApplyTransform(GNode *, GNode *, Suff *, Suff *);
usr.bin/make/suff.c
349
static bool
usr.bin/make/suff.c
707
static bool
usr.bin/make/suff.c
901
static bool
usr.bin/make/targ.c
247
bool
usr.bin/make/targ.c
256
bool
usr.bin/make/targ.c
265
bool
usr.bin/make/targ.c
274
bool
usr.bin/make/targ.h
54
extern bool Targ_Ignore(GNode *);
usr.bin/make/targ.h
55
extern bool Targ_Silent(GNode *);
usr.bin/make/targ.h
56
extern bool Targ_Precious(GNode *);
usr.bin/make/targ.h
59
extern bool node_is_real(GNode *);
usr.bin/make/targequiv.c
288
bool r;
usr.bin/make/targequiv.c
289
bool free_a, free_b;
usr.bin/make/targequiv.c
320
bool r;
usr.bin/make/targequiv.c
321
bool free_a, free_b;
usr.bin/make/targequiv.c
432
static bool equiv_was_built = false;
usr.bin/make/targequiv.c
445
bool
usr.bin/make/targequiv.h
32
extern bool is_sibling(GNode *, GNode *);
usr.bin/make/var.c
103
bool errorIsOkay;
usr.bin/make/var.c
104
static bool checkEnvFirst; /* true if environment should be searched for
usr.bin/make/var.c
1040
bool undefErr) /* true if undefineds are an error */
usr.bin/make/var.c
1043
static bool errorReported;
usr.bin/make/var.c
1051
bool doFree; /* Set true if val should be freed */
usr.bin/make/var.c
107
static bool varname_list_changed = true;
usr.bin/make/var.c
110
Var_setCheckEnvFirst(bool yes)
usr.bin/make/var.c
1111
bool
usr.bin/make/var.c
1114
bool seen_target = false;
usr.bin/make/var.c
1120
bool has_modifier;
usr.bin/make/var.c
1140
bool doFree = false;
usr.bin/make/var.c
1160
Var_Substi(const char *str, const char *estr, SymTable *ctxt, bool undefErr)
usr.bin/make/var.c
1275
bool doFree; /* should val be freed ? */
usr.bin/make/var.c
1379
bool first = true;
usr.bin/make/var.c
157
static bool xtlist[] = {
usr.bin/make/var.c
169
static bool *tlist = xtlist+1;
usr.bin/make/var.c
224
static void var_set_append(const char *, const char *, const char *, int, bool);
usr.bin/make/var.c
238
SymTable *, bool, bool *);
usr.bin/make/var.c
239
static bool parse_base_variable_name(const char **, struct Name *, SymTable *);
usr.bin/make/var.c
590
bool append)
usr.bin/make/var.c
663
bool first = true;
usr.bin/make/var.c
712
bool
usr.bin/make/var.c
778
static bool
usr.bin/make/var.c
783
bool has_modifier = false;
usr.bin/make/var.c
808
bool
usr.bin/make/var.c
813
bool result;
usr.bin/make/var.c
814
bool has_modifier;
usr.bin/make/var.c
825
bool freePtr = false;
usr.bin/make/var.c
840
bool
usr.bin/make/var.c
841
Var_ParseBuffer(Buffer buf, const char *str, SymTable *ctxt, bool err,
usr.bin/make/var.c
845
bool freeIt;
usr.bin/make/var.c
894
char ext, SymTable *ctxt, bool err, bool *freePtr)
usr.bin/make/var.c
977
bool err, /* true if undefined variables are an error */
usr.bin/make/var.c
979
bool *freePtr) /* OUT: true if caller should free result */
usr.bin/make/var.c
986
bool has_modifier;
usr.bin/make/var.h
102
extern bool Var_ParseBuffer(Buffer, const char *, SymTable *,
usr.bin/make/var.h
103
bool, size_t *);
usr.bin/make/var.h
111
extern char *Var_Subst(const char *, SymTable *, bool);
usr.bin/make/var.h
114
extern char *Var_Substi(const char *, const char *, SymTable *, bool);
usr.bin/make/var.h
121
extern bool Var_Check_for_target(const char *);
usr.bin/make/var.h
150
extern bool errorIsOkay;
usr.bin/make/var.h
31
extern void Var_setCheckEnvFirst(bool);
usr.bin/make/var.h
41
extern bool Var_Definedi(const char *, const char *);
usr.bin/make/var.h
88
extern char *Var_Parse(const char *, SymTable *, bool, size_t *,
usr.bin/make/var.h
89
bool *);
usr.bin/make/var.h
97
extern bool Var_ParseSkip(const char **, SymTable *);
usr.bin/make/varmodifiers.c
1074
bool err, bool *freePtr, const char **pscan, int paren)
usr.bin/make/varmodifiers.c
111
static bool VarHead(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
112
static bool VarTail(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
113
static bool VarSuffix(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
114
static bool VarRoot(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
115
static bool VarMatch(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
116
static bool VarSYSVMatch(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
117
static bool VarNoMatch(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
121
static bool VarRESubstitute(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
132
static bool VarSubstitute(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
136
static char *VarModify(char *, bool (*)(struct Name *, bool, Buffer, void *), void *);
usr.bin/make/varmodifiers.c
138
static void *check_empty(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
139
static void *check_quote(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
142
static void *check_shcmd(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
144
static void *get_stringarg(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
146
static void *get_patternarg(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
147
static void *get_spatternarg(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
148
static void *common_get_patternarg(const char **, SymTable *, bool, int, bool);
usr.bin/make/varmodifiers.c
150
static void *get_sysvpattern(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
156
void * (*getarg)(const char **, SymTable *, bool, int);
usr.bin/make/varmodifiers.c
158
bool (*word_apply)(struct Name *, bool, Buffer, void *);
usr.bin/make/varmodifiers.c
204
static bool
usr.bin/make/varmodifiers.c
205
VarHead(struct Name *word, bool addSpace, Buffer buf, void *dummy UNUSED)
usr.bin/make/varmodifiers.c
231
static bool
usr.bin/make/varmodifiers.c
232
VarTail(struct Name *word, bool addSpace, Buffer buf, void *dummy UNUSED)
usr.bin/make/varmodifiers.c
252
static bool
usr.bin/make/varmodifiers.c
253
VarSuffix(struct Name *word, bool addSpace, Buffer buf, void *dummy UNUSED)
usr.bin/make/varmodifiers.c
274
static bool
usr.bin/make/varmodifiers.c
275
VarRoot(struct Name *word, bool addSpace, Buffer buf, void *dummy UNUSED)
usr.bin/make/varmodifiers.c
295
static bool
usr.bin/make/varmodifiers.c
296
VarMatch(struct Name *word, bool addSpace, Buffer buf, void *pattern)
usr.bin/make/varmodifiers.c
315
static bool
usr.bin/make/varmodifiers.c
316
VarNoMatch(struct Name *word, bool addSpace, Buffer buf, void *pattern)
usr.bin/make/varmodifiers.c
336
static bool
usr.bin/make/varmodifiers.c
337
VarSYSVMatch(struct Name *word, bool addSpace, Buffer buf, void *patp)
usr.bin/make/varmodifiers.c
356
get_sysvpattern(const char **p, SymTable *ctxt UNUSED, bool err, int endc)
usr.bin/make/varmodifiers.c
445
static bool
usr.bin/make/varmodifiers.c
446
VarSubstitute(struct Name *word, bool addSpace, Buffer buf,
usr.bin/make/varmodifiers.c
527
bool done;
usr.bin/make/varmodifiers.c
594
static bool
usr.bin/make/varmodifiers.c
595
VarRESubstitute(struct Name *word, bool addSpace, Buffer buf, void *patternp)
usr.bin/make/varmodifiers.c
724
bool (*modProc)(struct Name *, bool, Buffer, void *),
usr.bin/make/varmodifiers.c
728
bool addSpace; /* true if need to add a space to the
usr.bin/make/varmodifiers.c
859
check_empty(const char **p, SymTable *ctxt UNUSED, bool b UNUSED, int endc)
usr.bin/make/varmodifiers.c
870
check_quote(const char **p, SymTable *ctxt UNUSED, bool b UNUSED, int endc)
usr.bin/make/varmodifiers.c
888
check_shcmd(const char **p, SymTable *ctxt UNUSED, bool b UNUSED, int endc)
usr.bin/make/varmodifiers.c
911
get_stringarg(const char **p, SymTable *ctxt UNUSED, bool b UNUSED, int endc)
usr.bin/make/varmodifiers.c
963
get_patternarg(const char **p, SymTable *ctxt, bool err, int endc)
usr.bin/make/varmodifiers.c
970
get_spatternarg(const char **p, SymTable *ctxt, bool err, int endc)
usr.bin/make/varmodifiers.c
976
common_get_patternarg(const char **p, SymTable *ctxt, bool err, int endc,
usr.bin/make/varmodifiers.c
977
bool dosubst)
usr.bin/make/varmodifiers.h
52
bool, bool *, const char **, int);
usr.bin/make/varname.c
34
VarName_Get(const char *start, struct Name *name, SymTable *ctxt, bool err,
usr.bin/make/varname.h
38
bool tofree; /* Needs freeing after use ? */
usr.bin/make/varname.h
52
bool, const char *(*)(const char *));
usr.bin/netstat/mbuf.c
82
bool seen[MT_NTYPES]; /* "have we seen this type yet?" */
usr.bin/patch/common.h
65
extern bool using_plan_a; /* try to keep everything in memory */
usr.bin/patch/common.h
66
extern bool out_of_mem; /* ran out of memory in plan a */
usr.bin/patch/common.h
71
extern bool ok_to_create_file;
usr.bin/patch/common.h
79
extern bool toutkeep;
usr.bin/patch/common.h
80
extern bool trejkeep;
usr.bin/patch/common.h
86
extern bool force;
usr.bin/patch/common.h
87
extern bool batch;
usr.bin/patch/common.h
88
extern bool verbose;
usr.bin/patch/common.h
89
extern bool reverse;
usr.bin/patch/common.h
90
extern bool noreverse;
usr.bin/patch/common.h
91
extern bool skip_rest_of_patch;
usr.bin/patch/common.h
93
extern bool canonicalize;
usr.bin/patch/common.h
95
extern bool check_only;
usr.bin/patch/common.h
96
extern bool warn_on_invalid_line;
usr.bin/patch/common.h
97
extern bool last_line_missing_eol;
usr.bin/patch/inp.c
106
static bool
usr.bin/patch/inp.c
129
static bool
usr.bin/patch/inp.c
282
bool found_revision = (revision == NULL);
usr.bin/patch/inp.c
411
static bool
usr.bin/patch/inp.c
60
static bool rev_in_string(const char *);
usr.bin/patch/inp.c
61
static bool reallocate_lines(size_t *);
usr.bin/patch/inp.c
64
static bool plan_a(const char *);
usr.bin/patch/patch.c
101
static void dump_line(LINENUM, bool);
usr.bin/patch/patch.c
102
static bool patch_match(LINENUM, LINENUM, LINENUM);
usr.bin/patch/patch.c
1027
copy_till(LINENUM lastline, bool endoffile)
usr.bin/patch/patch.c
103
static bool similar(const char *, const char *, ssize_t);
usr.bin/patch/patch.c
1059
dump_line(LINENUM line, bool write_newline)
usr.bin/patch/patch.c
107
static bool remove_empty_files = false;
usr.bin/patch/patch.c
1076
static bool
usr.bin/patch/patch.c
110
static bool reverse_flag_specified = false;
usr.bin/patch/patch.c
1119
static bool
usr.bin/patch/patch.c
112
static bool Vflag = false;
usr.bin/patch/patch.c
133
static bool do_defines = false;
usr.bin/patch/patch.c
150
bool patch_seen;
usr.bin/patch/patch.c
54
bool using_plan_a = true; /* try to keep everything in memory */
usr.bin/patch/patch.c
55
bool out_of_mem = false; /* ran out of memory in plan a */
usr.bin/patch/patch.c
60
bool ok_to_create_file = false;
usr.bin/patch/patch.c
67
bool toutkeep = false;
usr.bin/patch/patch.c
68
bool trejkeep = false;
usr.bin/patch/patch.c
69
bool warn_on_invalid_line;
usr.bin/patch/patch.c
70
bool last_line_missing_eol;
usr.bin/patch/patch.c
732
bool check_after = (offset <= max_pos_offset);
usr.bin/patch/patch.c
733
bool check_before = (offset <= max_neg_offset);
usr.bin/patch/patch.c
76
bool force = false;
usr.bin/patch/patch.c
77
bool batch = false;
usr.bin/patch/patch.c
78
bool verbose = true;
usr.bin/patch/patch.c
79
bool reverse = false;
usr.bin/patch/patch.c
80
bool noreverse = false;
usr.bin/patch/patch.c
81
bool skip_rest_of_patch = false;
usr.bin/patch/patch.c
83
bool canonicalize = false;
usr.bin/patch/patch.c
84
bool check_only = false;
usr.bin/patch/patch.c
99
static void copy_till(LINENUM, bool);
usr.bin/patch/pch.c
1191
bool
usr.bin/patch/pch.c
1199
bool blankline = false;
usr.bin/patch/pch.c
1391
posix_name(const struct file_name *names, bool assume_exists)
usr.bin/patch/pch.c
1421
compare_names(const struct file_name *names, bool assume_exists)
usr.bin/patch/pch.c
1468
best_name(const struct file_name *names, bool assume_exists)
usr.bin/patch/pch.c
180
bool
usr.bin/patch/pch.c
183
bool exists = false;
usr.bin/patch/pch.c
251
bool last_line_was_command = false, this_is_a_command = false;
usr.bin/patch/pch.c
252
bool stars_last_line = false, stars_this_line = false;
usr.bin/patch/pch.c
468
static bool
usr.bin/patch/pch.c
490
bool
usr.bin/patch/pch.c
498
bool ptrn_spaces_eaten; /* ptrn was slightly malformed */
usr.bin/patch/pch.c
499
bool repl_could_be_missing; /* no + or ! lines in this hunk */
usr.bin/patch/pch.c
500
bool repl_missing; /* we are now backtracking */
usr.bin/patch/pch.c
75
static char *best_name(const struct file_name *, bool);
usr.bin/patch/pch.c
76
static char *posix_name(const struct file_name *, bool);
usr.bin/patch/pch.h
36
bool exists;
usr.bin/patch/pch.h
45
bool there_is_another_patch(void);
usr.bin/patch/pch.h
47
bool another_hunk(void);
usr.bin/patch/pch.h
49
bool pch_swap(void);
usr.bin/patch/util.c
317
makedirs(const char *filename, bool striplast)
usr.bin/patch/util.c
341
fetchname(const char *at, bool *exists, int strip_leading)
usr.bin/patch/util.h
29
char *fetchname(const char *, bool *, int);
usr.bin/patch/util.h
45
void makedirs(const char *, bool);
usr.bin/pkgconf/cli/main.c
101
static bool
usr.bin/pkgconf/cli/main.c
1051
bool opened_error_msgout = false;
usr.bin/pkgconf/cli/main.c
114
static bool
usr.bin/pkgconf/cli/main.c
127
static bool
usr.bin/pkgconf/cli/main.c
148
static bool
usr.bin/pkgconf/cli/main.c
238
static bool
usr.bin/pkgconf/cli/main.c
301
static bool
usr.bin/pkgconf/cli/main.c
341
static bool
usr.bin/pkgconf/cli/main.c
352
static bool
usr.bin/pkgconf/cli/main.c
392
static bool
usr.bin/pkgconf/cli/main.c
411
static bool
usr.bin/pkgconf/cli/main.c
432
static bool
usr.bin/pkgconf/cli/main.c
455
static bool
usr.bin/pkgconf/cli/main.c
458
bool (*filter_fn)(const pkgconf_client_t *client, const pkgconf_fragment_t *frag, void *data),
usr.bin/pkgconf/cli/main.c
577
static bool
usr.bin/pkgconf/cli/main.c
602
static bool
usr.bin/pkgconf/cli/main.c
632
static bool
usr.bin/pkgconf/cli/main.c
661
static bool
usr.bin/pkgconf/cli/main.c
680
static bool
usr.bin/pkgconf/cli/main.c
708
static bool
usr.bin/pkgconf/cli/main.c
753
static bool
usr.bin/pkgconf/cli/main.c
788
static bool
usr.bin/pkgconf/cli/main.c
823
static bool
usr.bin/pkgconf/cli/main.c
92
static bool
usr.bin/pkgconf/libpkgconf/argvsplit.c
68
bool escaped = false;
usr.bin/pkgconf/libpkgconf/client.c
318
bool
usr.bin/pkgconf/libpkgconf/client.c
343
bool
usr.bin/pkgconf/libpkgconf/client.c
371
bool
usr.bin/pkgconf/libpkgconf/client.c
405
bool
usr.bin/pkgconf/libpkgconf/fileio.c
19
bool
usr.bin/pkgconf/libpkgconf/fileio.c
22
bool quoted = false;
usr.bin/pkgconf/libpkgconf/fragment.c
102
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
116
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
171
pkgconf_fragment_insert(const pkgconf_client_t *client, pkgconf_list_t *list, char type, const char *data, bool tail)
usr.bin/pkgconf/libpkgconf/fragment.c
271
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
272
pkgconf_fragment_can_merge_back(const pkgconf_fragment_t *base, unsigned int flags, bool is_private)
usr.bin/pkgconf/libpkgconf/fragment.c
294
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
295
pkgconf_fragment_can_merge(const pkgconf_fragment_t *base, unsigned int flags, bool is_private)
usr.bin/pkgconf/libpkgconf/fragment.c
309
pkgconf_fragment_exists(pkgconf_list_t *list, const pkgconf_fragment_t *base, unsigned int flags, bool is_private)
usr.bin/pkgconf/libpkgconf/fragment.c
320
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
35
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
358
bool
usr.bin/pkgconf/libpkgconf/fragment.c
393
pkgconf_fragment_copy(const pkgconf_client_t *client, pkgconf_list_t *list, const pkgconf_fragment_t *base, bool is_private)
usr.bin/pkgconf/libpkgconf/fragment.c
541
fragment_render_len(const pkgconf_list_t *list, bool escape)
usr.bin/pkgconf/libpkgconf/fragment.c
594
fragment_render_buf(const pkgconf_list_t *list, char *buf, size_t buflen, bool escape)
usr.bin/pkgconf/libpkgconf/fragment.c
635
pkgconf_fragment_render_len(const pkgconf_list_t *list, bool escape, const pkgconf_fragment_render_ops_t *ops)
usr.bin/pkgconf/libpkgconf/fragment.c
658
pkgconf_fragment_render_buf(const pkgconf_list_t *list, char *buf, size_t buflen, bool escape, const pkgconf_fragment_render_ops_t *ops)
usr.bin/pkgconf/libpkgconf/fragment.c
680
pkgconf_fragment_render(const pkgconf_list_t *list, bool escape, const pkgconf_fragment_render_ops_t *ops)
usr.bin/pkgconf/libpkgconf/fragment.c
72
static inline bool
usr.bin/pkgconf/libpkgconf/fragment.c
751
bool
usr.bin/pkgconf/libpkgconf/fragment.c
84
static inline bool
usr.bin/pkgconf/libpkgconf/libpkgconf.h
190
typedef bool (*pkgconf_pkg_iteration_func_t)(const pkgconf_pkg_t *pkg, void *data);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
192
typedef bool (*pkgconf_queue_apply_func_t)(pkgconf_client_t *client, pkgconf_pkg_t *world, void *data, int maxdepth);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
193
typedef bool (*pkgconf_error_handler_func_t)(const char *msg, const pkgconf_client_t *client, void *data);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
220
bool already_sent_notice;
usr.bin/pkgconf/libpkgconf/libpkgconf.h
239
bool want_default_static;
usr.bin/pkgconf/libpkgconf/libpkgconf.h
240
bool want_default_pure;
usr.bin/pkgconf/libpkgconf/libpkgconf.h
318
PKGCONF_API bool pkgconf_error(const pkgconf_client_t *client, const char *format, ...) PRINTFLIKE(2, 3);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
319
PKGCONF_API bool pkgconf_warn(const pkgconf_client_t *client, const char *format, ...) PRINTFLIKE(2, 3);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
320
PKGCONF_API bool pkgconf_trace(const pkgconf_client_t *client, const char *filename, size_t lineno, const char *funcname, const char *format, ...) PRINTFLIKE(5, 6);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
321
PKGCONF_API bool pkgconf_default_error_handler(const char *msg, const pkgconf_client_t *client, void *data);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
371
size_t (*render_len)(const pkgconf_list_t *list, bool escape);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
372
void (*render_buf)(const pkgconf_list_t *list, char *buf, size_t len, bool escape);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
375
typedef bool (*pkgconf_fragment_filter_func_t)(const pkgconf_client_t *client, const pkgconf_fragment_t *frag, void *data);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
376
PKGCONF_API bool pkgconf_fragment_parse(const pkgconf_client_t *client, pkgconf_list_t *list, pkgconf_list_t *vars, const char *value, unsigned int flags);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
377
PKGCONF_API void pkgconf_fragment_insert(const pkgconf_client_t *client, pkgconf_list_t *list, char type, const char *data, bool tail);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
379
PKGCONF_API void pkgconf_fragment_copy(const pkgconf_client_t *client, pkgconf_list_t *list, const pkgconf_fragment_t *base, bool is_private);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
384
PKGCONF_API size_t pkgconf_fragment_render_len(const pkgconf_list_t *list, bool escape, const pkgconf_fragment_render_ops_t *ops);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
385
PKGCONF_API void pkgconf_fragment_render_buf(const pkgconf_list_t *list, char *buf, size_t len, bool escape, const pkgconf_fragment_render_ops_t *ops);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
386
PKGCONF_API char *pkgconf_fragment_render(const pkgconf_list_t *list, bool escape, const pkgconf_fragment_render_ops_t *ops);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
387
PKGCONF_API bool pkgconf_fragment_has_system_dir(const pkgconf_client_t *client, const pkgconf_fragment_t *frag);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
390
PKGCONF_API pkgconf_tuple_t *pkgconf_tuple_add(const pkgconf_client_t *client, pkgconf_list_t *parent, const char *key, const char *value, bool parse, unsigned int flags);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
402
PKGCONF_API bool pkgconf_queue_compile(pkgconf_client_t *client, pkgconf_pkg_t *world, pkgconf_list_t *list);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
403
PKGCONF_API bool pkgconf_queue_solve(pkgconf_client_t *client, pkgconf_list_t *list, pkgconf_pkg_t *world, int maxdepth);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
405
PKGCONF_API bool pkgconf_queue_apply(pkgconf_client_t *client, pkgconf_list_t *list, pkgconf_queue_apply_func_t func, int maxdepth, void *data);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
406
PKGCONF_API bool pkgconf_queue_validate(pkgconf_client_t *client, pkgconf_list_t *list, int maxdepth);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
421
PKGCONF_API void pkgconf_path_add(const char *text, pkgconf_list_t *dirlist, bool filter);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
422
PKGCONF_API void pkgconf_path_prepend(const char *text, pkgconf_list_t *dirlist, bool filter);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
423
PKGCONF_API size_t pkgconf_path_split(const char *text, pkgconf_list_t *dirlist, bool filter);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
424
PKGCONF_API size_t pkgconf_path_build_from_environ(const char *envvarname, const char *fallback, pkgconf_list_t *dirlist, bool filter);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
425
PKGCONF_API bool pkgconf_path_match_list(const char *path, const pkgconf_list_t *dirlist);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
427
PKGCONF_API bool pkgconf_path_relocate(char *buf, size_t buflen);
usr.bin/pkgconf/libpkgconf/libpkgconf.h
463
PKGCONF_API bool pkgconf_fgetline(pkgconf_buffer_t *buffer, FILE *stream);
usr.bin/pkgconf/libpkgconf/parser.c
38
bool continue_reading = true;
usr.bin/pkgconf/libpkgconf/parser.c
43
bool warned_key_whitespace = false, warned_value_whitespace = false;
usr.bin/pkgconf/libpkgconf/path.c
119
pkgconf_path_add(const char *text, pkgconf_list_t *dirlist, bool filter)
usr.bin/pkgconf/libpkgconf/path.c
141
pkgconf_path_prepend(const char *text, pkgconf_list_t *dirlist, bool filter)
usr.bin/pkgconf/libpkgconf/path.c
164
pkgconf_path_split(const char *text, pkgconf_list_t *dirlist, bool filter)
usr.bin/pkgconf/libpkgconf/path.c
200
pkgconf_path_build_from_environ(const char *envvarname, const char *fallback, pkgconf_list_t *dirlist, bool filter)
usr.bin/pkgconf/libpkgconf/path.c
227
bool
usr.bin/pkgconf/libpkgconf/path.c
25
static bool
usr.bin/pkgconf/libpkgconf/path.c
346
bool
usr.bin/pkgconf/libpkgconf/path.c
62
prepare_path_node(const char *text, pkgconf_list_t *dirlist, bool filter)
usr.bin/pkgconf/libpkgconf/personality.c
150
static bool
usr.bin/pkgconf/libpkgconf/personality.c
175
bool *dest = (bool *)((char *) p + offset);
usr.bin/pkgconf/libpkgconf/personality.c
249
load_personality_with_path(const char *path, const char *triplet, bool datadir)
usr.bin/pkgconf/libpkgconf/pkg.c
1138
typedef bool (*pkgconf_vercmp_res_func_t)(const char *a, const char *b);
usr.bin/pkgconf/libpkgconf/pkg.c
1161
static bool pkgconf_pkg_comparator_lt(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1166
static bool pkgconf_pkg_comparator_gt(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1171
static bool pkgconf_pkg_comparator_lte(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1176
static bool pkgconf_pkg_comparator_gte(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1181
static bool pkgconf_pkg_comparator_eq(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1186
static bool pkgconf_pkg_comparator_ne(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1191
static bool pkgconf_pkg_comparator_any(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1199
static bool pkgconf_pkg_comparator_none(const char *a, const char *b)
usr.bin/pkgconf/libpkgconf/pkg.c
1374
static bool
usr.bin/pkgconf/libpkgconf/pkg.c
1395
static bool
usr.bin/pkgconf/libpkgconf/pkg.c
202
bool ret = pkgconf_fragment_parse(client, dest, &pkg->vars, value, pkg->flags);
usr.bin/pkgconf/libpkgconf/pkg.c
374
static bool
usr.bin/pkgconf/libpkgconf/pkg.c
458
static bool
usr.bin/pkgconf/libpkgconf/pkg.c
462
bool valid = true;
usr.bin/pkgconf/libpkgconf/pkg.c
57
static inline bool
usr.bin/pkgconf/libpkgconf/pkg.c
924
bool isnum;
usr.bin/pkgconf/libpkgconf/queue.c
313
bool
usr.bin/pkgconf/libpkgconf/queue.c
347
bool
usr.bin/pkgconf/libpkgconf/queue.c
350
bool ret = false;
usr.bin/pkgconf/libpkgconf/queue.c
388
bool
usr.bin/pkgconf/libpkgconf/queue.c
391
bool retval = true;
usr.bin/pkgconf/libpkgconf/queue.c
65
bool
usr.bin/pkgconf/libpkgconf/tuple.c
193
static bool
usr.bin/pkgconf/libpkgconf/tuple.c
236
pkgconf_tuple_add(const pkgconf_client_t *client, pkgconf_list_t *list, const char *key, const char *value, bool parse, unsigned int flags)
usr.bin/showmount/showmount.c
234
int bool, val, val2;
usr.bin/showmount/showmount.c
238
if (!xdr_bool(xdrsp, &bool))
usr.bin/showmount/showmount.c
240
while (bool) {
usr.bin/showmount/showmount.c
298
if (!xdr_bool(xdrsp, &bool))
usr.bin/showmount/showmount.c
312
int bool, grpbool;
usr.bin/showmount/showmount.c
316
if (!xdr_bool(xdrsp, &bool))
usr.bin/showmount/showmount.c
318
while (bool) {
usr.bin/showmount/showmount.c
342
if (!xdr_bool(xdrsp, &bool))
usr.bin/sort/bwstring.c
411
bwsfwrite(struct bwstring *bws, FILE *f, bool zero_ended)
usr.bin/sort/bwstring.c
465
bwsfgetln(FILE *f, size_t *len, bool zero_ended, struct reader_buffer *rb)
usr.bin/sort/bwstring.c
778
bwstod(struct bwstring *s0, bool *empty)
usr.bin/sort/bwstring.h
72
double bwstod(struct bwstring *s0, bool *empty);
usr.bin/sort/bwstring.h
93
size_t bwsfwrite(struct bwstring *bws, FILE *f, bool zero_ended);
usr.bin/sort/bwstring.h
94
struct bwstring *bwsfgetln(FILE *file, size_t *len, bool zero_ended, struct reader_buffer *rb);
usr.bin/sort/coll.c
1023
static inline bool
usr.bin/sort/coll.c
1036
static inline bool
usr.bin/sort/coll.c
1049
static bool
usr.bin/sort/coll.c
1079
bool empty1, empty2, key1_read, key2_read;
usr.bin/sort/coll.c
1234
bool key1_read, key2_read;
usr.bin/sort/coll.c
211
bool skip_blanks, bool *empty_key)
usr.bin/sort/coll.c
235
skip_fields_to_start(const struct bwstring *s, size_t fields, bool *empty_field)
usr.bin/sort/coll.c
243
bool pb = true;
usr.bin/sort/coll.c
246
bool isblank;
usr.bin/sort/coll.c
283
size_t *field_start, size_t *key_start, bool *empty_field, bool *empty_key)
usr.bin/sort/coll.c
300
bool empty_field, empty_key;
usr.bin/sort/coll.c
345
bool empty_field, empty_key;
usr.bin/sort/coll.c
776
size_t offset __unused, bool use_suffix)
usr.bin/sort/coll.c
784
bool e1, e2, key1_read, key2_read;
usr.bin/sort/coll.c
831
bool neg1, neg2;
usr.bin/sort/coll.h
106
bool pos1b;
usr.bin/sort/coll.h
107
bool pos2b;
usr.bin/sort/coll.h
42
bool empty;
usr.bin/sort/coll.h
43
bool neg;
usr.bin/sort/coll.h
51
bool nan;
usr.bin/sort/coll.h
52
bool notnum;
usr.bin/sort/file.c
146
static bool
usr.bin/sort/file.c
180
file_list_init(struct file_list *fl, bool tmp)
usr.bin/sort/file.c
192
file_list_add(struct file_list *fl, char *fn, bool allocate)
usr.bin/sort/file.c
207
file_list_populate(struct file_list *fl, int argc, char **argv, bool allocate)
usr.bin/sort/file.c
51
bool use_mmap;
usr.bin/sort/file.h
105
void file_list_init(struct file_list *fl, bool tmp);
usr.bin/sort/file.h
106
void file_list_add(struct file_list *fl, char *fn, bool allocate);
usr.bin/sort/file.h
107
void file_list_populate(struct file_list *fl, int argc, char **argv, bool allocate);
usr.bin/sort/file.h
68
bool tmp;
usr.bin/sort/file.h
78
extern bool use_mmap;
usr.bin/sort/radixsort.c
49
static bool reverse_sort;
usr.bin/sort/sort.c
144
static bool
usr.bin/sort/sort.c
373
check_mutually_exclusive_flags(char c, bool *mef_flags)
usr.bin/sort/sort.c
376
bool found_others, found_this;
usr.bin/sort/sort.c
422
static bool
usr.bin/sort/sort.c
478
parse_pos(const char *s, struct key_specs *ks, bool *mef_flags, bool second)
usr.bin/sort/sort.c
590
bool mef_flags[NUMBER_OF_MUTUALLY_EXCLUSIVE_FLAGS] =
usr.bin/sort/sort.c
62
static bool need_random;
usr.bin/sort/sort.c
69
bool debug_sort;
usr.bin/sort/sort.c
70
bool need_hint;
usr.bin/sort/sort.c
799
bool mef_flags[NUMBER_OF_MUTUALLY_EXCLUSIVE_FLAGS] =
usr.bin/sort/sort.h
102
extern bool need_hint;
usr.bin/sort/sort.h
46
extern bool debug_sort;
usr.bin/sort/sort.h
63
bool cflag;
usr.bin/sort/sort.h
64
bool csilentflag;
usr.bin/sort/sort.h
65
bool kflag;
usr.bin/sort/sort.h
66
bool mflag;
usr.bin/sort/sort.h
67
bool sflag;
usr.bin/sort/sort.h
68
bool uflag;
usr.bin/sort/sort.h
69
bool zflag;
usr.bin/sort/sort.h
70
bool tflag;
usr.bin/sort/sort.h
71
bool complex_sort;
usr.bin/sort/sort.h
89
bool bflag;
usr.bin/sort/sort.h
90
bool dflag;
usr.bin/sort/sort.h
91
bool fflag;
usr.bin/sort/sort.h
92
bool gflag;
usr.bin/sort/sort.h
93
bool iflag;
usr.bin/sort/sort.h
94
bool Mflag;
usr.bin/sort/sort.h
95
bool nflag;
usr.bin/sort/sort.h
96
bool rflag;
usr.bin/sort/sort.h
97
bool Rflag;
usr.bin/sort/sort.h
98
bool Vflag;
usr.bin/sort/sort.h
99
bool hflag;
usr.bin/sort/vsort.c
39
static inline bool
usr.bin/sort/vsort.c
45
static inline bool
usr.bin/sort/vsort.c
51
static inline bool
usr.bin/sort/vsort.c
67
bool expect_alpha, sfx;
usr.bin/ssh/libcrux_mlkem768_sha3.h
10532
static KRML_MUSTINLINE bool libcrux_ml_kem_ind_cca_validate_private_key_only_d6(
usr.bin/ssh/libcrux_mlkem768_sha3.h
10543
return Eurydice_array_eq_slice((size_t)32U, t, &expected, uint8_t, bool);
usr.bin/ssh/libcrux_mlkem768_sha3.h
10561
static KRML_MUSTINLINE bool libcrux_ml_kem_ind_cca_validate_private_key_37(
usr.bin/ssh/libcrux_mlkem768_sha3.h
10578
static KRML_MUSTINLINE bool
usr.bin/ssh/libcrux_mlkem768_sha3.h
10591
static inline bool libcrux_ml_kem_mlkem768_portable_validate_private_key(
usr.bin/ssh/libcrux_mlkem768_sha3.h
10608
static KRML_MUSTINLINE bool
usr.bin/ssh/libcrux_mlkem768_sha3.h
10619
static inline bool libcrux_ml_kem_mlkem768_portable_validate_private_key_only(
usr.bin/ssh/libcrux_mlkem768_sha3.h
10690
static KRML_MUSTINLINE bool libcrux_ml_kem_ind_cca_validate_public_key_89(
usr.bin/ssh/libcrux_mlkem768_sha3.h
10722
static KRML_MUSTINLINE bool
usr.bin/ssh/libcrux_mlkem768_sha3.h
10733
static inline bool libcrux_ml_kem_mlkem768_portable_validate_public_key(
usr.bin/ssh/libcrux_mlkem768_sha3.h
4781
bool sponge;
usr.bin/ssh/libcrux_mlkem768_sha3.h
5088
bool sponge;
usr.bin/ssh/libcrux_mlkem768_sha3.h
8333
static KRML_MUSTINLINE bool
usr.bin/ssh/libcrux_mlkem768_sha3.h
8355
bool done = true;
usr.bin/ssh/libcrux_mlkem768_sha3.h
8455
static KRML_MUSTINLINE bool
usr.bin/ssh/libcrux_mlkem768_sha3.h
8477
bool done = true;
usr.bin/ssh/libcrux_mlkem768_sha3.h
8570
bool done = libcrux_ml_kem_sampling_sample_from_uniform_distribution_next_89(
usr.bin/ssh/libcrux_mlkem768_sha3.h
8607
uint8_t *seed, bool transpose) {
usr.bin/ssh/sk-usbhid.c
319
const bool *value;
usr.bin/talk/display.c
47
bool smooth_scroll;
usr.bin/talk/talk.h
46
extern bool smooth_scroll;
usr.bin/tic/clear_cmd.c
50
clear_cmd(bool legacy)
usr.bin/tic/clear_cmd.h
43
extern int clear_cmd(bool);
usr.bin/tic/dump_entry.c
1212
bool box_ok = TRUE;
usr.bin/tic/dump_entry.c
1275
bool trimmed = FALSE;
usr.bin/tic/dump_entry.c
1315
static bool
usr.bin/tic/dump_entry.c
1405
static bool
usr.bin/tic/dump_entry.c
1408
bool result = TRUE;
usr.bin/tic/dump_entry.c
1432
static bool
usr.bin/tic/dump_entry.c
1435
bool result = FALSE;
usr.bin/tic/dump_entry.c
1489
bool infodump;
usr.bin/tic/dump_entry.c
1573
bool changed = FALSE;
usr.bin/tic/dump_entry.c
1657
dump_uses(const char *value, bool infodump)
usr.bin/tic/dump_entry.c
1686
bool infodump = !TcOutput();
usr.bin/tic/dump_entry.c
1716
bool quiet)
usr.bin/tic/dump_entry.c
1791
bool fix_needed = FALSE;
usr.bin/tic/dump_entry.c
198
bool wrap_strings,
usr.bin/tic/dump_entry.c
202
bool formatted,
usr.bin/tic/dump_entry.c
203
bool check,
usr.bin/tic/dump_entry.c
343
static bool
usr.bin/tic/dump_entry.c
404
return is_termcap(bool);
usr.bin/tic/dump_entry.c
67
static bool pretty; /* true if we format if-then-else strings */
usr.bin/tic/dump_entry.c
68
static bool wrapped; /* true if we wrap too-long strings */
usr.bin/tic/dump_entry.c
69
static bool did_wrap; /* true if last wrap_concat did wrapping */
usr.bin/tic/dump_entry.c
70
static bool checking; /* true if we are checking for tic */
usr.bin/tic/dump_entry.c
729
static bool
usr.bin/tic/dump_entry.c
732
bool result = FALSE;
usr.bin/tic/dump_entry.c
752
bool
usr.bin/tic/dump_entry.c
753
has_params(const char *src, bool formatting)
usr.bin/tic/dump_entry.c
755
bool result = FALSE;
usr.bin/tic/dump_entry.c
758
bool ifthen = FALSE;
usr.bin/tic/dump_entry.c
759
bool params = FALSE;
usr.bin/tic/dump_entry.c
783
bool percent = FALSE;
usr.bin/tic/dump_entry.c
784
bool params = has_params(src, TRUE);
usr.bin/tic/dump_entry.c
924
bool outcount = 0;
usr.bin/tic/dump_entry.h
81
extern bool has_params(const char *, bool);
usr.bin/tic/dump_entry.h
84
extern void compare_entry(PredHook, TERMTYPE2 *, bool);
usr.bin/tic/dump_entry.h
86
extern void dump_init(const char *, int, int, bool, int, int, unsigned, bool,
usr.bin/tic/dump_entry.h
87
bool, int);
usr.bin/tic/dump_entry.h
88
extern void dump_uses(const char *, bool);
usr.bin/tic/reset_cmd.c
102
bool sent = FALSE;
usr.bin/tic/reset_cmd.c
434
static bool
usr.bin/tic/reset_cmd.c
437
bool sent = FALSE;
usr.bin/tic/reset_cmd.c
445
static bool
usr.bin/tic/reset_cmd.c
463
static bool
usr.bin/tic/reset_cmd.c
489
bool
usr.bin/tic/reset_cmd.c
493
bool need_flush = FALSE;
usr.bin/tic/reset_cmd.c
614
reset_start(FILE *fp, bool is_reset, bool is_init)
usr.bin/tic/reset_cmd.c
80
static bool use_reset = FALSE; /* invoked as reset */
usr.bin/tic/reset_cmd.c
81
static bool use_init = FALSE; /* invoked as init */
usr.bin/tic/reset_cmd.c
96
static bool
usr.bin/tic/reset_cmd.h
50
extern bool send_init_strings(int /* fd */, TTY * /* old_settings */);
usr.bin/tic/reset_cmd.h
53
extern void reset_start(FILE * /* fp */, bool /* is_reset */, bool /* is_init */ );
usr.bin/tic/tic.c
1075
bool in_comment = FALSE;
usr.bin/tic/tic.c
1076
bool trailing_comment = FALSE;
usr.bin/tic/tic.c
1214
static bool
usr.bin/tic/tic.c
1217
bool result = FALSE;
usr.bin/tic/tic.c
1355
bool skip[4];
usr.bin/tic/tic.c
1356
bool repeated = FALSE;
usr.bin/tic/tic.c
1713
static bool
usr.bin/tic/tic.c
1730
bool have_kmouse = FALSE;
usr.bin/tic/tic.c
1731
bool use_sgr_39_49 = FALSE;
usr.bin/tic/tic.c
1734
bool is_screen = !strncmp(name, "screen", 6);
usr.bin/tic/tic.c
1735
bool screen_base = (is_screen
usr.bin/tic/tic.c
1941
static bool
usr.bin/tic/tic.c
1944
bool result = FALSE;
usr.bin/tic/tic.c
1996
bool params[1 + NUM_PARM];
usr.bin/tic/tic.c
2165
bool mixed = FALSE;
usr.bin/tic/tic.c
2394
static bool
usr.bin/tic/tic.c
2395
same_ti_tc(const char *ti, const char *tc, bool * embedded)
usr.bin/tic/tic.c
2397
bool same = TRUE;
usr.bin/tic/tic.c
2457
bool embedded;
usr.bin/tic/tic.c
2469
bool first = TRUE;
usr.bin/tic/tic.c
254
static bool
usr.bin/tic/tic.c
2577
static bool
usr.bin/tic/tic.c
2759
bool conflict = FALSE;
usr.bin/tic/tic.c
2766
bool first = TRUE;
usr.bin/tic/tic.c
2883
static bool
usr.bin/tic/tic.c
2886
bool result = FALSE;
usr.bin/tic/tic.c
3013
static bool
usr.bin/tic/tic.c
3016
bool result = FALSE;
usr.bin/tic/tic.c
3025
bool numbers = TRUE;
usr.bin/tic/tic.c
308
static bool in_name = FALSE;
usr.bin/tic/tic.c
3087
static bool
usr.bin/tic/tic.c
3090
bool result = FALSE;
usr.bin/tic/tic.c
3098
static bool
usr.bin/tic/tic.c
3101
bool result = FALSE;
usr.bin/tic/tic.c
3195
check_termtype(TERMTYPE2 *tp, bool literal)
usr.bin/tic/tic.c
554
static bool
usr.bin/tic/tic.c
558
bool code = FALSE;
usr.bin/tic/tic.c
62
static bool capdump = FALSE; /* running as infotocap? */
usr.bin/tic/tic.c
63
static bool infodump = FALSE; /* running as captoinfo? */
usr.bin/tic/tic.c
64
static bool showsummary = FALSE;
usr.bin/tic/tic.c
644
bool specific = (outdir != 0) || getenv("TERMINFO") != 0;
usr.bin/tic/tic.c
699
bool formatted = FALSE; /* reformat complex strings? */
usr.bin/tic/tic.c
70
static bool using_extensions = FALSE;
usr.bin/tic/tic.c
700
bool literal = FALSE; /* suppress post-processing? */
usr.bin/tic/tic.c
702
bool forceresolve = FALSE; /* force resolution */
usr.bin/tic/tic.c
703
bool limited = TRUE;
usr.bin/tic/tic.c
707
bool check_only = FALSE;
usr.bin/tic/tic.c
708
bool suppress_untranslatable = FALSE;
usr.bin/tic/tic.c
710
bool quiet = FALSE;
usr.bin/tic/tic.c
711
bool wrap_strings = FALSE;
usr.bin/tic/tic.c
73
static void (*save_check_termtype) (TERMTYPE2 *, bool);
usr.bin/tic/tic.c
74
static void check_termtype(TERMTYPE2 *tt, bool);
usr.bin/tic/transform.c
47
bool trim = FALSE;
usr.bin/tic/transform.c
70
bool
usr.bin/tic/transform.h
6
extern bool same_program(const char *, const char *);
usr.bin/tic/tty_settings.c
43
static bool can_restore = FALSE;
usr.bin/tic/tty_settings.c
57
static bool
usr.bin/tic/tty_settings.c
60
bool success = TRUE;
usr.bin/tic/tty_settings.c
73
save_tty_settings(TTY * tty_settings, bool need_tty)
usr.bin/tic/tty_settings.h
45
extern int save_tty_settings(TTY * /* tty_settings */, bool /* need_tty */ );
usr.bin/timeout/timeout.c
174
bool timedout = false;
usr.bin/timeout/timeout.c
175
bool do_second_kill = false;
usr.bin/tput/tput.c
118
check_aliases(char *name, bool program)
usr.bin/tput/tput.c
163
bool termcap = FALSE;
usr.bin/tput/tput.c
379
bool cmdline = TRUE;
usr.bin/tput/tput.c
387
bool is_alias;
usr.bin/tput/tput.c
388
bool need_tty;
usr.bin/tput/tput.c
58
static bool opt_v = FALSE; /* quiet, do not show warnings */
usr.bin/tput/tput.c
59
static bool opt_x = FALSE; /* clear scrollback if possible */
usr.bin/tput/tput.c
61
static bool is_init = FALSE;
usr.bin/tput/tput.c
62
static bool is_reset = FALSE;
usr.bin/tput/tput.c
63
static bool is_clear = FALSE;
usr.bin/tset/tset.c
780
bool opt_c = FALSE; /* set control-chars */
usr.bin/tset/tset.c
781
bool opt_w = FALSE; /* set window-size */
usr.bin/unexpand/unexpand.c
45
void tabify(bool);
usr.bin/unexpand/unexpand.c
50
bool all = false;
usr.bin/unexpand/unexpand.c
88
tabify(bool all)
usr.bin/unifdef/unifdef.c
1407
addsym1(bool ignorethis, bool definethis, char *symval)
usr.bin/unifdef/unifdef.c
1428
addsym2(bool ignorethis, const char *sym, const char *val)
usr.bin/unifdef/unifdef.c
1478
static bool
usr.bin/unifdef/unifdef.c
161
static bool compblank; /* -B: compress blank lines */
usr.bin/unifdef/unifdef.c
162
static bool lnblank; /* -b: blank deleted lines */
usr.bin/unifdef/unifdef.c
163
static bool complement; /* -c: do the complement */
usr.bin/unifdef/unifdef.c
164
static bool debugging; /* -d: debugging reports */
usr.bin/unifdef/unifdef.c
165
static bool inplace; /* -m: modify in place */
usr.bin/unifdef/unifdef.c
166
static bool iocccok; /* -e: fewer IOCCC errors */
usr.bin/unifdef/unifdef.c
167
static bool strictlogic; /* -K: keep ambiguous #ifs */
usr.bin/unifdef/unifdef.c
168
static bool killconsts; /* -k: eval constant #ifs */
usr.bin/unifdef/unifdef.c
169
static bool lnnum; /* -n: add #line directives */
usr.bin/unifdef/unifdef.c
170
static bool symlist; /* -s: output symbol list */
usr.bin/unifdef/unifdef.c
171
static bool symdepth; /* -S: output symbol depth */
usr.bin/unifdef/unifdef.c
172
static bool text; /* -t: this is a text file */
usr.bin/unifdef/unifdef.c
176
static bool ignore[MAXSYMS]; /* -iDsym or -iUsym */
usr.bin/unifdef/unifdef.c
207
static bool ignoring[MAXDEPTH]; /* ignore comments state */
usr.bin/unifdef/unifdef.c
213
static bool constexpr; /* constant #if expression */
usr.bin/unifdef/unifdef.c
214
static bool zerosyms; /* to format symdepth output */
usr.bin/unifdef/unifdef.c
215
static bool firstsym; /* ditto */
usr.bin/unifdef/unifdef.c
220
static void addsym1(bool, bool, char *);
usr.bin/unifdef/unifdef.c
221
static void addsym2(bool, const char *, const char *);
usr.bin/unifdef/unifdef.c
227
static bool defundef(void);
usr.bin/unifdef/unifdef.c
232
static void flushline(bool);
usr.bin/unifdef/unifdef.c
698
flushline(bool keep)
usr.bin/unifdef/unifdef.c
703
bool blankline = tline[strspn(tline, " \t\r\n")] == '\0';
usr.bin/unifdef/unifdef.c
970
bool defparen;
usr.sbin/btrace/btrace.c
1249
bool
usr.sbin/btrace/btrace.c
95
bool stmt_test(struct bt_stmt *, struct dt_evt *);
usr.sbin/ldomctl/config.c
88
bool have_cwqs;
usr.sbin/ldomctl/config.c
89
bool have_rngs;
usr.sbin/ldomctl/mdesc.c
247
bool
usr.sbin/ldomctl/mdesc.c
261
bool
usr.sbin/ldomctl/mdesc.c
275
bool
usr.sbin/ldomctl/mdesc.c
289
bool
usr.sbin/ldomctl/mdesc.c
304
bool
usr.sbin/ldomctl/mdesc.h
120
bool md_get_prop_val(struct md *, struct md_node *, const char *, uint64_t *);
usr.sbin/ldomctl/mdesc.h
121
bool md_set_prop_val(struct md *, struct md_node *, const char *, uint64_t);
usr.sbin/ldomctl/mdesc.h
122
bool md_get_prop_str(struct md *, struct md_node *, const char *,
usr.sbin/ldomctl/mdesc.h
124
bool md_set_prop_data(struct md *, struct md_node *, const char *,
usr.sbin/ldomctl/mdesc.h
126
bool md_get_prop_data(struct md *, struct md_node *, const char *,
usr.sbin/ldomctl/mdstore.h
26
bool booted_set;
usr.sbin/ldomctl/mdstore.h
27
bool boot_set;
usr.sbin/mrouted/defs.h
245
extern void k_hdr_include(int bool);
usr.sbin/mrouted/kern.c
24
void k_hdr_include(int bool)
usr.sbin/mrouted/kern.c
28
(char *)&bool, sizeof(bool)) == -1)
usr.sbin/mrouted/kern.c
29
logit(LOG_ERR, errno, "setsockopt IP_HDRINCL %u", bool);
usr.sbin/npppctl/npppctl.c
385
static bool
usr.sbin/npppctl/npppctl.c
60
static bool filter_match(struct parse_result *, struct npppd_who *);
usr.sbin/npppd/l2tp/l2tp_conf.h
46
bool data_use_seq;
usr.sbin/npppd/l2tp/l2tp_conf.h
47
bool require_ipsec;
usr.sbin/npppd/l2tp/l2tp_conf.h
48
bool accept_dialin;
usr.sbin/npppd/l2tp/l2tp_conf.h
49
bool lcp_renegotiation;
usr.sbin/npppd/l2tp/l2tp_conf.h
50
bool force_lcp_renegotiation;
usr.sbin/npppd/l2tp/l2tp_conf.h
51
bool ctrl_in_pktdump;
usr.sbin/npppd/l2tp/l2tp_conf.h
52
bool ctrl_out_pktdump;
usr.sbin/npppd/l2tp/l2tp_conf.h
53
bool data_in_pktdump;
usr.sbin/npppd/l2tp/l2tp_conf.h
54
bool data_out_pktdump;
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1046
static bool
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1052
static bool
usr.sbin/npppd/l2tp/l2tp_ctrl.c
1064
static bool
usr.sbin/npppd/l2tp/l2tp_ctrl.c
517
l2tp_ctrl_resend_una_packets(l2tp_ctrl *_this, bool resend)
usr.sbin/npppd/l2tp/l2tp_ctrl.c
72
static int l2tp_ctrl_resend_una_packets(l2tp_ctrl *, bool);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
77
static bool l2tp_ctrl_txwin_is_full(l2tp_ctrl *);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
78
static bool l2tp_ctrl_in_peer_window(l2tp_ctrl *, uint16_t);
usr.sbin/npppd/l2tp/l2tp_ctrl.c
79
static bool l2tp_ctrl_in_our_window(l2tp_ctrl *, uint16_t);
usr.sbin/npppd/npppd/npppd.h
110
bool lcp_keepalive;
usr.sbin/npppd/npppd/npppd.h
127
bool mppe_yesno;
usr.sbin/npppd/npppd/npppd.h
128
bool mppe_required;
usr.sbin/npppd/npppd/npppd.h
133
bool tcp_mss_adjust;
usr.sbin/npppd/npppd/npppd.h
134
bool ingress_filter;
usr.sbin/npppd/npppd/npppd.h
137
bool pipex;
usr.sbin/npppd/npppd/npppd.h
161
bool eap_capable;
usr.sbin/npppd/npppd/npppd.h
162
bool strip_nt_domain;
usr.sbin/npppd/npppd/npppd.h
163
bool strip_atmark_realm;
usr.sbin/npppd/npppd/npppd.h
196
bool dns_use_resolver;
usr.sbin/npppd/npppd/npppd.h
197
bool dns_configured;
usr.sbin/npppd/npppd/npppd.h
199
bool nbns_configured;
usr.sbin/npppd/npppd/npppd.h
201
bool allow_user_select;
usr.sbin/npppd/npppd/npppd.h
212
bool is_pppx;
usr.sbin/npppd/npppd/npppd_ctl.c
110
npppd_ctl_who0(struct npppd_ctl *_this, bool is_monitoring)
usr.sbin/npppd/npppd/npppd_ctl.c
57
bool is_monitoring;
usr.sbin/npppd/npppd/npppd_ctl.c
58
bool responding;
usr.sbin/npppd/npppd/npppd_ctl.c
62
static int npppd_ctl_who0 (struct npppd_ctl *, bool);
usr.sbin/npppd/npppd/parse.y
98
bool yesno;
usr.sbin/npppd/pppoe/pppoe_conf.h
39
bool accept_any_service;
usr.sbin/npppd/pppoe/pppoe_conf.h
40
bool desc_in_pktdump;
usr.sbin/npppd/pppoe/pppoe_conf.h
41
bool desc_out_pktdump;
usr.sbin/npppd/pppoe/pppoe_conf.h
42
bool session_in_pktdump;
usr.sbin/npppd/pppoe/pppoe_conf.h
43
bool session_out_pktdump;
usr.sbin/npppd/pptp/pptp_conf.h
46
bool ctrl_in_pktdump;
usr.sbin/npppd/pptp/pptp_conf.h
47
bool ctrl_out_pktdump;
usr.sbin/npppd/pptp/pptp_conf.h
48
bool data_in_pktdump;
usr.sbin/npppd/pptp/pptp_conf.h
49
bool data_out_pktdump;
usr.sbin/nsd/simdzone/include/zone.h
347
bool grouped;
usr.sbin/nsd/simdzone/include/zone.h
349
bool start_of_line;
usr.sbin/nsd/simdzone/include/zone.h
439
bool secondary;
usr.sbin/nsd/simdzone/include/zone.h
442
bool no_includes;
usr.sbin/nsd/simdzone/include/zone.h
446
bool pretty_ttls;
usr.sbin/nsd/simdzone/src/generic/eui.h
13
static really_inline bool
usr.sbin/nsd/simdzone/src/generic/eui.h
14
eui_base16_dec_loop_generic_32_inner(const uint8_t *s, uint8_t *o, bool last)
usr.sbin/nsd/simdzone/src/generic/parser.h
115
bool is_obsolete;
usr.sbin/nsd/simdzone/src/generic/parser.h
116
bool is_experimental;
usr.sbin/nsd/simdzone/src/generic/parser.h
382
static really_inline bool is_contiguous(const token_t *token)
usr.sbin/nsd/simdzone/src/generic/parser.h
389
static really_inline bool is_quoted(const token_t *token)
usr.sbin/nsd/simdzone/src/generic/parser.h
396
static really_inline bool is_contiguous_or_quoted(const token_t *token)
usr.sbin/nsd/simdzone/src/generic/parser.h
403
static really_inline bool is_delimiter(const token_t *token)
usr.sbin/nsd/simdzone/src/generic/parser.h
410
static really_inline bool is_line_feed(const token_t *token)
usr.sbin/nsd/simdzone/src/generic/parser.h
417
static really_inline bool is_end_of_file(const token_t *token)
usr.sbin/nsd/simdzone/src/generic/svcb.h
679
bool out_of_order = false;
usr.sbin/nsd/simdzone/src/generic/svcb.h
770
bool missing_keys = false;
usr.sbin/nsd/simdzone/src/generic/svcb.h
864
bool out_of_order = false;
usr.sbin/nsd/simdzone/src/generic/ttl.h
34
const char *data, size_t length, bool allow_units, uint32_t *ttl)
usr.sbin/nsd/simdzone/src/haswell/base32.h
26
bool valid = true;
usr.sbin/nsd/simdzone/src/haswell/bits.h
16
static inline bool add_overflow(uint64_t value1, uint64_t value2, uint64_t *result) {
usr.sbin/nsd/simdzone/src/isadetection.h
222
bool have_avx = false, have_xgetbv = false;
usr.sbin/nsd/simdzone/src/westmere/base32.h
25
bool valid = true;
usr.sbin/nsd/simdzone/src/westmere/bits.h
16
static inline bool add_overflow(uint64_t value1, uint64_t value2, uint64_t *result) {
usr.sbin/nsd/simdzone/src/westmere/time.h
101
bool is_leap_yr = (bool)is_leap_year((uint32_t)yr);
usr.sbin/nsd/simdzone/src/westmere/time.h
32
static bool sse_parse_time(const char *date_string, uint32_t *time_in_second) {
usr.sbin/nsd/simdzone/src/zone.c
155
const bool is_string = file->name == not_a_file || file->path == not_a_file;
usr.sbin/nsd/simdzone/src/zone.c
161
const bool is_stdin = file->name &&
usr.sbin/radiusctl/radiusctl.c
485
radius_dump(FILE *out, RADIUS_PACKET *pkt, bool resp, const char *secret)
usr.sbin/radiusctl/radiusctl.c
55
static void radius_dump(FILE *, RADIUS_PACKET *, bool,
usr.sbin/radiusd/radiusd.c
1031
bool islast)
usr.sbin/radiusd/radiusd.c
125
bool noaction = false;
usr.sbin/radiusd/radiusd.c
75
struct radius_query *, bool);
usr.sbin/radiusd/radiusd.h
81
bool has_pass;
usr.sbin/radiusd/radiusd.h
88
bool final;
usr.sbin/radiusd/radiusd_bsdauth.c
135
bool authok = false;
usr.sbin/radiusd/radiusd_bsdauth.c
176
bool group_ok = false;
usr.sbin/radiusd/radiusd_eap2mschap.c
469
bool reset_username = false;
usr.sbin/radiusd/radiusd_eap2mschap.c
621
bool accept = false;
usr.sbin/radiusd/radiusd_ipcp.c
1035
bool is_eap, is_mschap, is_mschap2;
usr.sbin/radiusd/radiusd_ipcp.c
141
bool no_session_timeout;
usr.sbin/radiusd/radiusd_ipcp.c
745
bool found = false;
usr.sbin/radiusd/radiusd_local.h
100
bool isfilter;
usr.sbin/radiusd/radiusd_local.h
134
bool hasnext;
usr.sbin/radiusd/radiusd_local.h
65
bool msgauth_required;
usr.sbin/radiusd/radiusd_local.h
79
bool writeready;
usr.sbin/radiusd/radiusd_local.h
80
bool stopped;
usr.sbin/radiusd/radiusd_module.c
62
bool priv_dropped;
usr.sbin/radiusd/radiusd_module.c
74
bool writeready;
usr.sbin/radiusd/radiusd_module.c
75
bool stopped;
usr.sbin/radiusd/radiusd_module.c
76
bool ev_onhandler;
usr.sbin/radiusd/radiusd_standard.c
48
bool strip_atmark_realm;
usr.sbin/radiusd/radiusd_standard.c
49
bool strip_nt_domain;
