arch/arm/mm/cache-l2x0-pmu.c

127

mask = GENMASK_ULL(31, 0);

arch/arm64/include/asm/cache.h

105

if (FIELD_GET(GENMASK_ULL(63, 40), id))

arch/arm64/include/asm/cache.h

108

return (aff3 << 24) | FIELD_GET(GENMASK_ULL(23, 0), id);

arch/arm64/include/asm/cpufeature.h

994

oval &= GENMASK_ULL(feat + width - 1, feat);

arch/arm64/include/asm/esr.h

176

#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))

arch/arm64/include/asm/esr.h

83

#define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))

arch/arm64/include/asm/kvm_arm.h

297

#define __HCRX_EL2_nMASK (GENMASK_ULL(24, 14) | \

arch/arm64/include/asm/kvm_arm.h

298

GENMASK_ULL(11, 7) | \

arch/arm64/include/asm/kvm_arm.h

299

GENMASK_ULL(5, 0))

arch/arm64/include/asm/kvm_arm.h

317

(((par) & GENMASK_ULL(52 - 1, 12)) >> 8)

arch/arm64/include/asm/kvm_arm.h

319

#define FAR_TO_FIPA_OFFSET(far) ((far) & GENMASK_ULL(11, 0))

arch/arm64/include/asm/kvm_nested.h

64

return ttbr0 & ~GENMASK_ULL(63, 48);

arch/arm64/include/asm/pgtable-hwdef.h

188

#define PHYS_TO_PTE_ADDR_MASK GENMASK_ULL(49, 8)

arch/arm64/include/asm/pgtable-hwdef.h

213

#define PTE_PO_IDX_MASK GENMASK_ULL(62, 60)

arch/arm64/include/asm/pgtable-hwdef.h

284

#define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2)

arch/arm64/include/asm/pointer_auth.h

17

#define ptrauth_user_pac_mask() GENMASK_ULL(54, vabits_actual)

arch/arm64/include/asm/pointer_auth.h

18

#define ptrauth_kernel_pac_mask() GENMASK_ULL(63, vabits_actual)

arch/arm64/include/asm/sysreg.h

1058

#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)

arch/arm64/include/asm/sysreg.h

1059

#define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1061

#define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1064

#define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1065

#define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1068

#define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1070

#define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1074

#define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1075

#define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1079

#define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1080

#define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1084

#define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1085

#define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1088

#define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35)

arch/arm64/include/asm/sysreg.h

1089

#define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1090

#define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1093

#define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1094

#define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1099

#define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1100

#define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

1105

#define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29)

arch/arm64/include/asm/sysreg.h

1106

#define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0)

arch/arm64/include/asm/sysreg.h

334

#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)

arch/arm64/include/asm/sysreg.h

335

#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))

arch/arm64/include/asm/sysreg.h

338

#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)

arch/arm64/include/asm/sysreg.h

342

#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)

arch/arm64/include/asm/sysreg.h

343

#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)

arch/arm64/include/asm/sysreg.h

344

#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))

arch/arm64/include/asm/tlbflush.h

129

#define TLBI_TTL_MASK GENMASK_ULL(47, 44)

arch/arm64/include/asm/tlbflush.h

215

#define TLBIR_ASID_MASK GENMASK_ULL(63, 48)

arch/arm64/include/asm/tlbflush.h

216

#define TLBIR_TG_MASK GENMASK_ULL(47, 46)

arch/arm64/include/asm/tlbflush.h

217

#define TLBIR_SCALE_MASK GENMASK_ULL(45, 44)

arch/arm64/include/asm/tlbflush.h

218

#define TLBIR_NUM_MASK GENMASK_ULL(43, 39)

arch/arm64/include/asm/tlbflush.h

219

#define TLBIR_TTL_MASK GENMASK_ULL(38, 37)

arch/arm64/include/asm/tlbflush.h

220

#define TLBIR_BADDR_MASK GENMASK_ULL(36, 0)

arch/arm64/include/asm/tlbflush.h

53

__ta &= GENMASK_ULL(43, 0); \

arch/arm64/kernel/pi/idreg-override.c

304

u64 mask = GENMASK_ULL(shift + width - 1, shift);

arch/arm64/kernel/ptrace.c

2461

(GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \

arch/arm64/kernel/ptrace.c

2462

GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5))

arch/arm64/kernel/ptrace.c

2464

(GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20))

arch/arm64/kernel/topology.c

464

*val &= GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,

arch/arm64/kvm/at.c

1644

ipa = (par & GENMASK_ULL(47, 12)) | (vaddr & GENMASK_ULL(11, 0));

arch/arm64/kvm/at.c

25

return wi->max_oa_bits < 52 && (ipa & GENMASK_ULL(51, wi->max_oa_bits));

arch/arm64/kvm/at.c

26

return wi->max_oa_bits < 48 && (ipa & GENMASK_ULL(47, wi->max_oa_bits));

arch/arm64/kvm/at.c

402

wi->baddr |= FIELD_GET(GENMASK_ULL(5, 2), ttbr) << 48;

arch/arm64/kvm/at.c

409

wi->baddr &= GENMASK_ULL(wi->max_oa_bits - 1, x);

arch/arm64/kvm/at.c

481

index = (va & GENMASK_ULL(va_top, va_bottom)) >> (va_bottom - 3);

arch/arm64/kvm/at.c

57

return desc & GENMASK_ULL(47, wi->pgshift);

arch/arm64/kvm/at.c

612

wr->pa |= va & GENMASK_ULL(va_bottom - 1, 0);

arch/arm64/kvm/at.c

62

addr = desc & GENMASK_ULL(49, wi->pgshift);

arch/arm64/kvm/at.c

67

addr = desc & GENMASK_ULL(47, wi->pgshift);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

208

u64 mask = GENMASK_ULL(width + shift - 1, shift);

arch/arm64/kvm/inject_fault.c

307

esr &= ~GENMASK_ULL(5, 0);

arch/arm64/kvm/nested.c

1717

GENMASK_ULL(47, 44) |

arch/arm64/kvm/nested.c

1921

resx.res0 = ZCR_ELx_RES0 | GENMASK_ULL(8, 4);

arch/arm64/kvm/nested.c

203

if (output_size != 48 && (output & GENMASK_ULL(47, output_size)))

arch/arm64/kvm/nested.c

288

base_addr = wi->baddr & GENMASK_ULL(47, base_lower_bound);

arch/arm64/kvm/nested.c

302

index = (ipa & GENMASK_ULL(addr_top, addr_bottom))

arch/arm64/kvm/nested.c

340

base_addr = desc & GENMASK_ULL(47, wi->pgshift);

arch/arm64/kvm/nested.c

383

paddr = (desc & GENMASK_ULL(47, addr_bottom)) |

arch/arm64/kvm/nested.c

384

(ipa & GENMASK_ULL(addr_bottom - 1, 0));

arch/arm64/kvm/nested.c

675

u64 addr = (val & GENMASK_ULL(35, 0)) << 12;

arch/arm64/kvm/stacktrace.c

149

unsigned long va_mask = GENMASK_ULL(__hyp_va_bits - 1, 0);

arch/arm64/kvm/sys_regs.c

3232

IMPLEMENTATION_ID(MIDR_EL1, GENMASK_ULL(31, 0)),

arch/arm64/kvm/sys_regs.c

3234

IMPLEMENTATION_ID(REVIDR_EL1, GENMASK_ULL(63, 0)),

arch/arm64/kvm/sys_regs.c

3518

IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)),

arch/arm64/kvm/sys_regs.c

4098

base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12;

arch/arm64/kvm/sys_regs.c

537

*mask = GENMASK_ULL(31, 0);

arch/arm64/kvm/sys_regs.c

541

*mask = GENMASK_ULL(63, 32);

arch/arm64/kvm/sys_regs.c

545

*mask = GENMASK_ULL(63, 0);

arch/arm64/kvm/va_layout.c

100

tag_val |= get_random_long() & GENMASK_ULL(hyp_va_bits - 2, tag_lsb);

arch/arm64/kvm/va_layout.c

229

addr |= ((u64)origptr & GENMASK_ULL(10, 7));

arch/arm64/kvm/va_layout.c

95

va_mask = GENMASK_ULL(tag_lsb - 1, 0);

arch/arm64/kvm/vgic/vgic-its.c

1494

reg &= ~GENMASK_ULL(15, 12);

arch/arm64/kvm/vgic/vgic-its.c

1654

#define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))

arch/arm64/kvm/vgic/vgic-its.c

936

indirect_ptr &= GENMASK_ULL(51, 16);

arch/arm64/kvm/vgic/vgic-mmio-v3.c

25

return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);

arch/arm64/kvm/vgic/vgic-mmio-v3.c

35

reg &= ~GENMASK_ULL(upper, lower);

arch/arm64/kvm/vgic/vgic-mmio-v3.c

36

val &= GENMASK_ULL(len * 8 - 1, 0);

arch/arm64/kvm/vgic/vgic-mmio-v3.c

441

(GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))

arch/arm64/kvm/vgic/vgic-mmio-v3.c

443

(BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \

arch/arm64/kvm/vgic/vgic-mmio-v3.c

444

GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))

arch/arm64/kvm/vgic/vgic-v2.c

163

cpuid = FIELD_GET(GENMASK_ULL(12, 10), val);

arch/arm64/kvm/vgic/vgic-v2.c

164

val &= ~GENMASK_ULL(12, 10);

arch/arm64/kvm/vgic/vgic-v3.c

208

cpuid = FIELD_GET(GENMASK_ULL(12, 10), val);

arch/arm64/kvm/vgic/vgic-v3.c

209

val &= ~GENMASK_ULL(12, 10);

arch/arm64/kvm/vgic/vgic.h

100

#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)

arch/arm64/kvm/vgic/vgic.h

102

#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)

arch/arm64/kvm/vgic/vgic.h

103

#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)

arch/arm64/kvm/vgic/vgic.h

106

#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)

arch/arm64/kvm/vgic/vgic.h

108

#define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)

arch/arm64/kvm/vgic/vgic.h

109

#define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)

arch/arm64/kvm/vgic/vgic.h

111

#define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)

arch/arm64/kvm/vgic/vgic.h

112

#define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52)

arch/arm64/kvm/vgic/vgic.h

92

#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)

arch/arm64/kvm/vgic/vgic.h

95

#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)

arch/arm64/kvm/vgic/vgic.h

96

#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)

arch/arm64/mm/trans_pgd.c

233

level_mask = GENMASK_ULL(level_msb, level_lsb);

arch/loongarch/include/asm/kasan.h

21

#define XRANGE_SHADOW_MASK GENMASK_ULL(XRANGE_SHADOW_SHIFT - 1, 0)

arch/loongarch/include/asm/kvm_para.h

34

#define KVM_STEAL_PHYS_MASK GENMASK_ULL(63, 6)

arch/loongarch/kernel/time.c

152

unsigned long max_delta = GENMASK_ULL(boot_cpu_data.timerbits, 0);

arch/loongarch/mm/mmap.c

153

return !(((pfn << PAGE_SHIFT) + size) & ~(GENMASK_ULL(cpu_pabits, 0)));

arch/loongarch/pci/acpi.c

78

entry->offset = ci->root->mcfg_addr & GENMASK_ULL(63, 40);

arch/mips/include/asm/mips-cm.h

167

#define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)

arch/mips/include/asm/mips-cm.h

174

#define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)

arch/mips/include/asm/mips-cm.h

210

#define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)

arch/mips/include/asm/mips-cm.h

333

#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)

arch/mips/include/asm/mips-cm.h

334

#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)

arch/mips/include/asm/mips-cm.h

371

#define CM_GCR_Cx_RESET64_BASE_BEVEXCBASE GENMASK_ULL(47, 12)

arch/mips/include/asm/mipsregs.h

934

#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)

arch/powerpc/platforms/pseries/plpks.c

33

GENMASK_ULL(63 - (be_bit_hi), 63 - (be_bit_lo))

arch/riscv/include/asm/sbi.h

173

#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)

arch/riscv/include/asm/sbi.h

174

#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)

arch/riscv/include/asm/sbi.h

176

#define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0)

arch/riscv/kvm/aia.c

596

hgctrl->free_bitmap = (hgctrl->nr_hgei) ? GENMASK_ULL(hgctrl->nr_hgei, 1) : 0;

arch/riscv/kvm/aia_device.c

201

mask = GENMASK_ULL(h, 0);

arch/riscv/kvm/aia_device.c

206

mask |= GENMASK_ULL(h, l);

arch/riscv/kvm/aia_device.c

218

GENMASK_ULL(aia->nr_hart_bits - 1, 0);

arch/riscv/kvm/aia_device.c

221

GENMASK_ULL(aia->nr_group_bits - 1, 0);

arch/x86/boot/startup/sev-shared.c

255

if (xfeatures_found != (xfeatures_en & GENMASK_ULL(63, 2)))

arch/x86/coco/sev/core.c

2043

tsc_freq_mhz &= GENMASK_ULL(17, 0);

arch/x86/coco/sev/vc-shared.c

420

ret = ghcb->save.sw_exit_info_1 & GENMASK_ULL(31, 0);

arch/x86/events/amd/core.c

1335

.cntr_mask64 = GENMASK_ULL(AMD64_NUM_COUNTERS - 1, 0),

arch/x86/events/amd/core.c

1434

x86_pmu.cntr_mask64 = GENMASK_ULL(AMD64_NUM_COUNTERS_CORE - 1, 0);

arch/x86/events/amd/core.c

1444

x86_pmu.cntr_mask64 = GENMASK_ULL(ebx.split.num_core_pmc - 1, 0);

arch/x86/events/amd/iommu.c

322

count &= GENMASK_ULL(47, 0);

arch/x86/events/intel/core.c

5959

*cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);

arch/x86/events/intel/core.c

5967

*fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);

arch/x86/events/intel/core.c

6079

u64 gp_mask = GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);

arch/x86/events/intel/core.c

7908

x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);

arch/x86/events/intel/core.c

7927

GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);

arch/x86/events/intel/core.c

8779

x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);

arch/x86/events/intel/ds.c

2626

return header->cont || !(header->format & GENMASK_ULL(63, 16));

arch/x86/events/intel/p4.c

1357

.cntr_mask64 = GENMASK_ULL(ARCH_P4_MAX_CCCR - 1, 0),

arch/x86/events/zhaoxin/core.c

534

x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);

arch/x86/events/zhaoxin/core.c

540

x86_pmu.fixed_cntr_mask64 = GENMASK_ULL(edx.split.num_counters_fixed - 1, 0);

arch/x86/hyperv/ivm.c

138

if (ghcb->save.sw_exit_info_1 & GENMASK_ULL(31, 0))

arch/x86/include/asm/intel_ds.h

20

#define MAX_PEBS_EVENTS_MASK GENMASK_ULL(MAX_PEBS_EVENTS - 1, 0)

arch/x86/include/asm/kvm_host.h

2556

#define KVM_EXIT_HYPERCALL_MBZ GENMASK_ULL(31, 1)

arch/x86/include/asm/mce.h

45

#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)

arch/x86/include/asm/mce.h

97

#define MCI_ADDR_PHYSADDR GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)

arch/x86/include/asm/msr-index.h

285

#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9)

arch/x86/include/asm/msr-index.h

303

#define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)

arch/x86/include/asm/msr-index.h

304

#define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)

arch/x86/include/asm/msr-index.h

748

#define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19)

arch/x86/include/asm/msr-index.h

752

#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)

arch/x86/include/asm/msr-index.h

763

#define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8)

arch/x86/include/asm/msr-index.h

780

#define AMD_CPPC_FLOOR_PERF_CNT_MASK GENMASK_ULL(39, 32)

arch/x86/include/asm/perf_event.h

117

GENMASK_ULL(37, 36))

arch/x86/include/asm/perf_event.h

121

GENMASK_ULL(27, 24))

arch/x86/include/asm/perf_event.h

128

#define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC GENMASK_ULL(7, 0)

arch/x86/include/asm/perf_event.h

129

#define AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC GENMASK_ULL(9, 8)

arch/x86/include/asm/perf_event.h

155

#define PEBS_DATACFG_CNTR_MASK GENMASK_ULL(15, 0)

arch/x86/include/asm/perf_event.h

157

#define PEBS_DATACFG_FIX_MASK GENMASK_ULL(7, 0)

arch/x86/include/asm/sev-common.h

100

((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \

arch/x86/include/asm/sev-common.h

104

#define GHCB_MSR_PSC_REQ_TO_GFN(msr) (((msr) & GENMASK_ULL(51, 12)) >> 12)

arch/x86/include/asm/sev-common.h

105

#define GHCB_MSR_PSC_REQ_TO_OP(msr) (((msr) & GENMASK_ULL(55, 52)) >> 52)

arch/x86/include/asm/sev-common.h

110

(((u64)(val) & GENMASK_ULL(63, 32)) >> 32)

arch/x86/include/asm/sev-common.h

119

((((u64)(v) & GENMASK_ULL(7, 0)) << 32) | \

arch/x86/include/asm/sev-common.h

126

(((u64)(v) & GENMASK_ULL(63, 32)) >> 32)

arch/x86/include/asm/sev-common.h

132

#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0)

arch/x86/include/asm/sev-common.h

135

(((u64)(v) & GENMASK_ULL(63, 12)) >> 12)

arch/x86/include/asm/sev-common.h

60

#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0)

arch/x86/include/asm/sev-common.h

65

#define GHCB_MSR_GPA_VALUE_MASK GENMASK_ULL(51, 0)

arch/x86/include/asm/sev-common.h

74

(((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \

arch/x86/include/asm/sev-common.h

81

(((u64)(v) & GENMASK_ULL(63, 12)) >> 12)

arch/x86/include/asm/sgx.h

109

#define SGX_MISC_RESERVED_MASK GENMASK_ULL(63, 1)

arch/x86/include/asm/sgx.h

146

GENMASK_ULL(63, 11))

arch/x86/include/asm/sgx.h

206

#define SGX_TCS_RESERVED_MASK GENMASK_ULL(63, 1)

arch/x86/include/asm/sgx.h

305

#define SGX_SECINFO_PERMISSION_MASK GENMASK_ULL(2, 0)

arch/x86/include/asm/svm.h

269

#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)

arch/x86/include/asm/svm.h

270

#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12)

arch/x86/include/asm/svm.h

275

#define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)

arch/x86/include/asm/svm.h

289

#define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(11, 0)

arch/x86/include/asm/tdx.h

24

#define TDX_SW_ERROR (TDX_ERROR | GENMASK_ULL(47, 40))

arch/x86/include/asm/vmx.h

154

return vmx_basic & GENMASK_ULL(30, 0);

arch/x86/include/asm/vmx.h

159

return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;

arch/x86/include/asm/vmx.h

164

return (vmx_basic & GENMASK_ULL(53, 50)) >> 50;

arch/x86/include/asm/vmx.h

185

return vmx_misc & GENMASK_ULL(4, 0);

arch/x86/include/asm/vmx.h

190

return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;

arch/x86/include/asm/vmx.h

195

return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;

arch/x86/include/asm/vmx.h

200

return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;

arch/x86/kernel/acpi/cppc.c

54

u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,

arch/x86/kernel/acpi/cppc.c

70

u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1,

arch/x86/kernel/cpu/mce/internal.h

291

m->addr &= GENMASK_ULL(56, lsb);

arch/x86/kernel/cpu/mce/internal.h

298

m->addr &= GENMASK_ULL(55, lsb);

arch/x86/kernel/cpu/mce/threshold.c

151

if (history & GENMASK_ULL(STORM_END_POLL_THRESHOLD, 0))

arch/x86/kernel/cpu/resctrl/intel_aet.c

341

#define DATA_BITS GENMASK_ULL(62, 0)

arch/x86/kernel/cpu/sgx/encl.h

23

#define SGX_ENCL_PAGE_VA_OFFSET_MASK GENMASK_ULL(11, 3)

arch/x86/kernel/cpu/sgx/main.c

751

return (low & GENMASK_ULL(31, 12)) +

arch/x86/kernel/cpu/sgx/main.c

752

((high & GENMASK_ULL(19, 0)) << 32);

arch/x86/kvm/hyperv.c

1327

#define KVM_HV_WIN2016_GUEST_ID_MASK (~GENMASK_ULL(23, 16)) /* mask out the service version */

arch/x86/kvm/hyperv.c

1856

sbank = hweight64(valid_bank_mask & GENMASK_ULL(valid_bit_nr - 1, 0));

arch/x86/kvm/lapic.c

2616

#define X2APIC_ICR_RESERVED_BITS (GENMASK_ULL(31, 20) | GENMASK_ULL(17, 16) | BIT(13))

arch/x86/kvm/mmu/mmu_internal.h

18

#define __PT_BASE_ADDR_MASK GENMASK_ULL(51, 12)

arch/x86/kvm/mmu/spte.c

573

GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);

arch/x86/kvm/mmu/spte.h

121

#define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \

arch/x86/kvm/mmu/spte.h

123

#define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \

arch/x86/kvm/mmu/spte.h

138

#define SPTE_MMIO_ALLOWED_MASK (BIT_ULL(63) | GENMASK_ULL(51, 12) | \

arch/x86/kvm/mmu/spte.h

139

BIT_ULL(10) | GENMASK_ULL(2, 0))

arch/x86/kvm/mmu/spte.h

152

#define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0)

arch/x86/kvm/pmu.c

1005

pmu->global_ctrl = GENMASK_ULL(pmu->nr_arch_gp_counters - 1, 0);

arch/x86/kvm/vmx/nested.c

1361

const u64 reserved_bits = GENMASK_ULL(63, 57) |

arch/x86/kvm/vmx/nested.c

1362

GENMASK_ULL(47, 45) |

arch/x86/kvm/vmx/nested.c

1436

if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))

arch/x86/kvm/vmx/nested.c

1440

if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))

arch/x86/kvm/vmx/nested.c

1461

const u64 reserved_bits = BIT_ULL(31) | GENMASK_ULL(13, 9);

arch/x86/kvm/vmx/nested.c

392

#define EPTP_PA_MASK GENMASK_ULL(51, 12)

arch/x86/kvm/vmx/sgx.c

487

bitmap &= ~GENMASK_ULL(ETRACK, ECREATE);

arch/x86/kvm/vmx/sgx.c

493

bitmap &= ~GENMASK_ULL(EMODT, EAUG);

arch/x86/kvm/vmx/tdx.h

151

GENMASK_ULL(bits - 1, 0)); \

arch/x86/kvm/vmx/tdx_arch.h

12

#define TDX_FIELD_MASK GENMASK_ULL(31, 0)

arch/x86/kvm/vmx/tdx_arch.h

132

#define TDX_SEPT_LEVEL_MASK GENMASK_ULL(2, 0)

arch/x86/kvm/vmx/tdx_arch.h

133

#define TDX_SEPT_STATE_MASK GENMASK_ULL(15, 8)

arch/x86/kvm/vmx/vmx.c

2419

if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))

arch/x86/kvm/x86.h

684

#define CET_US_IBT_MASK_BITS (GENMASK_ULL(5, 2) | GENMASK_ULL(63, 10))

arch/x86/virt/svm/sev.c

104

#define RST_ENTRY_MAPPED_SIZE(x) ((x) & GENMASK_ULL(19, 0))

arch/x86/virt/svm/sev.c

105

#define RST_ENTRY_SEGMENT_BASE(x) ((x) & GENMASK_ULL(51, 20))

arch/x86/virt/svm/sev.c

123

#define PFN_PMD_MASK GENMASK_ULL(63, PMD_SHIFT - PAGE_SHIFT)

arch/x86/virt/svm/sev.c

605

#define RMP_ADDR_MASK GENMASK_ULL(51, 13)

drivers/accel/amdxdna/aie2_pci.h

203

#define AIE2_ALL_FEATURES GENMASK_ULL(AIE2_FEATURE_MAX - 1, AIE2_NPU_COMMAND)

drivers/accel/habanalabs/gaudi/gaudiP.h

207

#define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39)

drivers/accel/habanalabs/gaudi/gaudiP.h

210

(addr) &= ~GENMASK_ULL(49, 39); \

drivers/accel/habanalabs/gaudi/gaudiP.h

215

(addr) &= ~GENMASK_ULL(49, 39); \

drivers/accel/habanalabs/gaudi2/gaudi2.c

165

#define HW_UNSCRAMBLED_BITS_MASK GENMASK_ULL(63, 26)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

186

#define HW_CAP_DMMU_MASK GENMASK_ULL(24, 9)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

189

#define HW_CAP_EDMA_MASK GENMASK_ULL(34, 27)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

191

#define HW_CAP_MME_MASK GENMASK_ULL(38, 35)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

193

#define HW_CAP_ROT_MASK GENMASK_ULL(40, 39)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

225

#define HW_CAP_DEC_MASK GENMASK_ULL(9, 0)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

229

#define HW_CAP_TPC_MASK GENMASK_ULL(24, 0)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

233

#define HW_CAP_NIC_MASK GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)

drivers/accel/habanalabs/gaudi2/gaudi2P.h

235

#define GAUDI2_ARC_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 28)) >> 28)

drivers/accel/ivpu/ivpu_mmu.c

139

#define IVPU_MMU_EVT_OP_MASK GENMASK_ULL(7, 0)

drivers/accel/ivpu/ivpu_mmu.c

140

#define IVPU_MMU_EVT_SSID_MASK GENMASK_ULL(31, 12)

drivers/accel/ivpu/ivpu_mmu.c

143

#define IVPU_MMU_Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)

drivers/accel/ivpu/ivpu_mmu.c

145

#define IVPU_MMU_STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)

drivers/accel/ivpu/ivpu_mmu.c

163

#define IVPU_MMU_CMDQ_OP GENMASK_ULL(7, 0)

drivers/accel/ivpu/ivpu_mmu.c

165

#define IVPU_MMU_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)

drivers/accel/ivpu/ivpu_mmu.c

166

#define IVPU_MMU_CD_0_TCR_TG0 GENMASK_ULL(7, 6)

drivers/accel/ivpu/ivpu_mmu.c

167

#define IVPU_MMU_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)

drivers/accel/ivpu/ivpu_mmu.c

168

#define IVPU_MMU_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)

drivers/accel/ivpu/ivpu_mmu.c

169

#define IVPU_MMU_CD_0_TCR_SH0 GENMASK_ULL(13, 12)

drivers/accel/ivpu/ivpu_mmu.c

174

#define IVPU_MMU_CD_0_TCR_IPS GENMASK_ULL(34, 32)

drivers/accel/ivpu/ivpu_mmu.c

181

#define IVPU_MMU_CD_0_ASID GENMASK_ULL(63, 48)

drivers/accel/ivpu/ivpu_mmu.c

193

#define IVPU_MMU_CD_1_TTB0_MASK GENMASK_ULL(51, 4)

drivers/accel/ivpu/ivpu_mmu.c

195

#define IVPU_MMU_STE_0_S1CDMAX GENMASK_ULL(63, 59)

drivers/accel/ivpu/ivpu_mmu.c

196

#define IVPU_MMU_STE_0_S1FMT GENMASK_ULL(5, 4)

drivers/accel/ivpu/ivpu_mmu.c

200

#define IVPU_MMU_STE_0_CFG GENMASK_ULL(3, 1)

drivers/accel/ivpu/ivpu_mmu.c

201

#define IVPU_MMU_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)

drivers/accel/ivpu/ivpu_mmu.c

205

#define IVPU_MMU_STE_1_CONT GENMASK_ULL(16, 13)

drivers/accel/ivpu/ivpu_mmu.c

206

#define IVPU_MMU_STE_1_STRW GENMASK_ULL(31, 30)

drivers/accel/ivpu/ivpu_mmu.c

207

#define IVPU_MMU_STE_1_PRIVCFG GENMASK_ULL(49, 48)

drivers/accel/ivpu/ivpu_mmu.c

209

#define IVPU_MMU_STE_1_INSTCFG GENMASK_ULL(51, 50)

drivers/accel/ivpu/ivpu_mmu.c

217

#define IVPU_MMU_STE_1_S1CIR GENMASK_ULL(3, 2)

drivers/accel/ivpu/ivpu_mmu.c

218

#define IVPU_MMU_STE_1_S1COR GENMASK_ULL(5, 4)

drivers/accel/ivpu/ivpu_mmu.c

219

#define IVPU_MMU_STE_1_S1CSH GENMASK_ULL(7, 6)

drivers/accel/ivpu/ivpu_mmu.c

220

#define IVPU_MMU_STE_1_S1DSS GENMASK_ULL(1, 0)

drivers/accel/qaic/qaic_data.c

33

#define SEM_VAL_MASK GENMASK_ULL(11, 0)

drivers/accel/qaic/qaic_data.c

34

#define SEM_INDEX_MASK GENMASK_ULL(4, 0)

drivers/acpi/acpi_extlog.c

24

#define EXT_ELOG_ENTRY_MASK GENMASK_ULL(51, 0) /* elog entry address mask */

drivers/acpi/acpi_lpit.c

44

u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset +

drivers/acpi/apei/einj-core.c

863

if (type & GENMASK_ULL(63, 32))

drivers/acpi/apei/einj-cxl.c

83

return einj_cxl_rch_error_inject(type, 0x2, rcrb, GENMASK_ULL(63, 0),

drivers/acpi/riscv/cppc.c

21

#define FFH_CPPC_TYPE(r) (((r) & GENMASK_ULL(63, 60)) >> 60)

drivers/acpi/riscv/cpuidle.c

17

#define RISCV_FFH_LPI_TYPE_MASK GENMASK_ULL(63, 60)

drivers/acpi/riscv/cpuidle.c

18

#define RISCV_FFH_LPI_RSVD_MASK GENMASK_ULL(59, 32)

drivers/ata/libahci.c

2300

devslp &= ~GENMASK_ULL(24, 2);

drivers/base/cacheinfo.c

239

if (FIELD_GET(GENMASK_ULL(63, 32), id)) {

drivers/cache/sifive_ccache.c

42

#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)

drivers/cache/sifive_ccache.c

43

#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)

drivers/cache/sifive_ccache.c

44

#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)

drivers/cache/sifive_ccache.c

45

#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)

drivers/clk/clk-stm32f4.c

1010

GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);

drivers/clk/clk-versaclock7.c

92

#define VC7_REG_FOD_FRAC_MASK GENMASK_ULL(59, VC7_REG_FOD_FRAC_SHIFT)

drivers/clk/qcom/gdsc.c

22

#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)

drivers/clk/qcom/gdsc.c

23

#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)

drivers/clk/qcom/gdsc.c

24

#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)

drivers/clocksource/timer-ep93xx.c

79

return lo_hi_readq(tcu->base + EP93XX_TIMER4_VALUE_LOW) & GENMASK_ULL(39, 0);

drivers/clocksource/timer-microchip-pit64b.c

43

#define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0)

drivers/cpufreq/intel_pstate.c

1314

value &= ~GENMASK_ULL(31, 24);

drivers/cpufreq/intel_pstate.c

1338

value &= ~GENMASK_ULL(31, 24);

drivers/cpufreq/intel_pstate.c

1356

value &= ~GENMASK_ULL(31, 0);

drivers/cpufreq/intel_pstate.c

2413

hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;

drivers/cpufreq/intel_pstate.c

731

value &= ~GENMASK_ULL(31, 24);

drivers/crypto/hisilicon/sec2/sec_main.c

130

#define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \

drivers/crypto/hisilicon/sec2/sec_main.c

132

#define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \

drivers/crypto/hisilicon/sec2/sec_main.c

133

GENMASK_ULL(42, 25))

drivers/crypto/hisilicon/sec2/sec_main.c

134

#define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \

drivers/crypto/hisilicon/sec2/sec_main.c

135

GENMASK_ULL(45, 43))

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

29

(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

36

((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6)

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

338

if (rp_mask & GENMASK_ULL(rp_index + 3, rp_index)) {

drivers/crypto/intel/qat/qat_common/qat_uclo.c

2126

uwrd = uwrd & GENMASK_ULL(43, 0);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

222

#define INFLIGHT GENMASK_ULL(8, 0)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

223

#define GRB_CNT GENMASK_ULL(39, 32)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

224

#define GWB_CNT GENMASK_ULL(47, 40)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

225

#define XQ_XOR GENMASK_ULL(63, 63)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

226

#define DQPTR GENMASK_ULL(19, 0)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

227

#define NQPTR GENMASK_ULL(51, 32)

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

36

GENMASK_ULL(ena_bits, 0));

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

43

GENMASK_ULL(ena_bits, 0));

drivers/cxl/core/hdm.c

724

*tgt |= FIELD_PREP(GENMASK_ULL(39, 32), t[4]->port_id);

drivers/cxl/core/hdm.c

726

*tgt |= FIELD_PREP(GENMASK_ULL(47, 40), t[5]->port_id);

drivers/cxl/core/hdm.c

728

*tgt |= FIELD_PREP(GENMASK_ULL(55, 48), t[6]->port_id);

drivers/cxl/core/hdm.c

730

*tgt |= FIELD_PREP(GENMASK_ULL(63, 56), t[7]->port_id);

drivers/cxl/core/region.c

3142

bits_lower = hpa_offset & GENMASK_ULL(eig + 7, 0);

drivers/cxl/core/region.c

3144

temp = hpa_offset &= ~GENMASK_ULL(eig + eiw + 8 - 1, 0);

drivers/cxl/core/region.c

3212

mask_upper = GENMASK_ULL(51, eig + 8);

drivers/cxl/core/region.c

3224

hpa_offset |= dpa_offset & GENMASK_ULL(eig + 7, 0);

drivers/cxl/core/trace.h

327

#define CXL_DPA_MASK GENMASK_ULL(63, 6)

drivers/cxl/cxl.h

179

#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)

drivers/cxl/cxl.h

180

#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)

drivers/cxl/cxl.h

214

#define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)

drivers/cxl/cxl.h

215

#define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)

drivers/cxl/cxl.h

218

#define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)

drivers/cxl/cxl.h

220

#define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)

drivers/cxl/cxl.h

221

#define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16)

drivers/cxl/cxl.h

222

#define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32)

drivers/cxl/cxl.h

223

#define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)

drivers/cxl/cxlmem.h

703

#define CXL_POISON_START_MASK GENMASK_ULL(63, 6)

drivers/dma/amd/qdma/qdma.c

68

mask = GENMASK_ULL(hi_bit, low_bit);

drivers/dma/amd/qdma/qdma.h

235

#define QDMA_INTR_MASK_PIDX GENMASK_ULL(15, 0)

drivers/dma/amd/qdma/qdma.h

236

#define QDMA_INTR_MASK_CIDX GENMASK_ULL(31, 16)

drivers/dma/amd/qdma/qdma.h

237

#define QDMA_INTR_MASK_DESC_COLOR GENMASK_ULL(32, 32)

drivers/dma/amd/qdma/qdma.h

238

#define QDMA_INTR_MASK_STATE GENMASK_ULL(34, 33)

drivers/dma/amd/qdma/qdma.h

239

#define QDMA_INTR_MASK_ERROR GENMASK_ULL(36, 35)

drivers/dma/amd/qdma/qdma.h

240

#define QDMA_INTR_MASK_TYPE GENMASK_ULL(38, 38)

drivers/dma/amd/qdma/qdma.h

241

#define QDMA_INTR_MASK_QID GENMASK_ULL(62, 39)

drivers/dma/amd/qdma/qdma.h

242

#define QDMA_INTR_MASK_COLOR GENMASK_ULL(63, 63)

drivers/dma/loongson/loongson2-apb-dma.c

34

#define LDMA_CONFIG_MASK GENMASK_ULL(4, 0) /* DMA controller config bits mask */

drivers/dpll/zl3073x/core.c

299

if (val > GENMASK_ULL(47, 0) && val < GENMASK_ULL(63, 47)) {

drivers/edac/amd64_edac.c

1671

addr = m->addr & GENMASK_ULL(end_bit, start_bit);

drivers/edac/amd64_edac.c

1681

if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)

drivers/edac/amd64_edac.c

1689

cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3;

drivers/edac/amd64_edac.c

1698

return cc6_base | (addr & GENMASK_ULL(23, 0));

drivers/edac/amd64_edac.c

1703

tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);

drivers/edac/amd64_edac.c

1706

tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;

drivers/edac/amd64_edac.c

1709

tmp_addr |= addr & GENMASK_ULL(11, 0);

drivers/edac/amd64_edac.c

1774

pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);

drivers/edac/amd64_edac.c

1779

pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);

drivers/edac/amd64_edac.c

2182

return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));

drivers/edac/amd64_edac.c

383

base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);

drivers/edac/amd64_edac.c

384

mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);

drivers/edac/amd64_edac.c

396

*base = (csbase & GENMASK_ULL(15, 5)) << 6;

drivers/edac/amd64_edac.c

397

*base |= (csbase & GENMASK_ULL(30, 19)) << 8;

drivers/edac/amd64_edac.c

401

*mask &= ~((GENMASK_ULL(15, 5) << 6) |

drivers/edac/amd64_edac.c

402

(GENMASK_ULL(30, 19) << 8));

drivers/edac/amd64_edac.c

404

*mask |= (csmask & GENMASK_ULL(15, 5)) << 6;

drivers/edac/amd64_edac.c

405

*mask |= (csmask & GENMASK_ULL(30, 19)) << 8;

drivers/edac/amd64_edac.c

415

GENMASK_ULL(30,19) | GENMASK_ULL(13,5);

drivers/edac/amd64_edac.c

418

GENMASK_ULL(28,19) | GENMASK_ULL(13,5);

drivers/edac/amd64_edac.c

889

dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;

drivers/edac/amd64_edac.c

925

input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +

drivers/edac/bluefield_edac.c

76

#define MLXBF_DIMM_INFO__SIZE_GB GENMASK_ULL(15, 0)

drivers/edac/bluefield_edac.c

80

#define MLXBF_DIMM_INFO__RANKS GENMASK_ULL(23, 21)

drivers/edac/bluefield_edac.c

81

#define MLXBF_DIMM_INFO__PACKAGE_X GENMASK_ULL(31, 24)

drivers/edac/ie31200_edac.c

668

.reg_mchbar_mask = GENMASK_ULL(38, 15),

drivers/edac/ie31200_edac.c

674

.reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27),

drivers/edac/ie31200_edac.c

675

.reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16),

drivers/edac/ie31200_edac.c

690

.reg_mchbar_mask = GENMASK_ULL(38, 15),

drivers/edac/ie31200_edac.c

696

.reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27),

drivers/edac/ie31200_edac.c

697

.reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16),

drivers/edac/ie31200_edac.c

713

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/ie31200_edac.c

721

.reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27),

drivers/edac/ie31200_edac.c

722

.reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16),

drivers/edac/igen6_edac.c

43

#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))

drivers/edac/igen6_edac.c

645

.reg_mchbar_mask = GENMASK_ULL(38, 16),

drivers/edac/igen6_edac.c

646

.reg_tom_mask = GENMASK_ULL(38, 20),

drivers/edac/igen6_edac.c

647

.reg_touud_mask = GENMASK_ULL(38, 20),

drivers/edac/igen6_edac.c

648

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

659

.reg_mchbar_mask = GENMASK_ULL(38, 16),

drivers/edac/igen6_edac.c

660

.reg_tom_mask = GENMASK_ULL(38, 20),

drivers/edac/igen6_edac.c

661

.reg_touud_mask = GENMASK_ULL(38, 20),

drivers/edac/igen6_edac.c

662

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

674

.reg_mchbar_mask = GENMASK_ULL(38, 17),

drivers/edac/igen6_edac.c

675

.reg_tom_mask = GENMASK_ULL(38, 20),

drivers/edac/igen6_edac.c

676

.reg_touud_mask = GENMASK_ULL(38, 20),

drivers/edac/igen6_edac.c

677

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

692

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

693

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

694

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

695

.reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5),

drivers/edac/igen6_edac.c

707

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

708

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

709

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

710

.reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5),

drivers/edac/igen6_edac.c

722

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

723

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

724

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

725

.reg_eccerrlog_addr_mask = GENMASK_ULL(45, 5),

drivers/edac/igen6_edac.c

738

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

739

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

740

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

741

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

755

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

756

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

757

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

758

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

770

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

771

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

772

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

773

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

800

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

801

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

802

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

803

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/igen6_edac.c

815

.reg_mchbar_mask = GENMASK_ULL(41, 17),

drivers/edac/igen6_edac.c

816

.reg_tom_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

817

.reg_touud_mask = GENMASK_ULL(41, 20),

drivers/edac/igen6_edac.c

818

.reg_eccerrlog_addr_mask = GENMASK_ULL(38, 5),

drivers/edac/pnd2_edac.c

125

#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))

drivers/edac/pnd2_edac.c

331

if (mask != GENMASK_ULL(PND_MAX_PHYS_BIT, __ffs(mask))) {

drivers/edac/pnd2_edac.c

340

rp->limit = (base | ~mask) & GENMASK_ULL(PND_MAX_PHYS_BIT, 0);

drivers/edac/pnd2_edac.c

431

GENMASK_ULL(APL_ASYMSHIFT - 1, 0));

drivers/edac/pnd2_edac.c

441

GENMASK_ULL(DNV_ASYMSHIFT - 1, 0));

drivers/edac/pnd2_edac.c

525

GENMASK_ULL(APL_ASYMSHIFT - 1, 0));

drivers/edac/sb_edac.c

2337

rank_addr |= ch_addr & GENMASK_ULL(shiftup - 1, 0);

drivers/edac/sb_edac.c

53

(((v) & GENMASK_ULL(hi, lo)) >> (lo))

drivers/edac/skx_base.c

497

rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);

drivers/edac/skx_common.h

30

(((v) & GENMASK_ULL((hi), (lo))) >> (lo))

drivers/firmware/arm_scmi/powercap.c

622

(FIELD_PREP(GENMASK_ULL(31, 0), power_thresh_low) |

drivers/firmware/arm_scmi/powercap.c

623

FIELD_PREP(GENMASK_ULL(63, 32), power_thresh_high));

drivers/firmware/efi/cper-x86.c

13

#define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2)

drivers/firmware/efi/cper-x86.c

14

#define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8)

drivers/firmware/efi/cper-x86.c

48

#define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0)))

drivers/firmware/efi/cper-x86.c

49

#define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16)

drivers/firmware/efi/cper-x86.c

50

#define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18)

drivers/firmware/efi/cper-x86.c

51

#define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22)

drivers/firmware/efi/cper-x86.c

58

#define CHECK_BUS_PART_TYPE(check) (((check) & GENMASK_ULL(31, 30)) >> 30)

drivers/firmware/efi/cper-x86.c

60

#define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33)

drivers/firmware/efi/cper-x86.c

69

#define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16)

drivers/firmware/stratix10-rsu.c

20

#define RSU_ERASE_SIZE_MASK GENMASK_ULL(63, 32)

drivers/firmware/stratix10-rsu.c

21

#define RSU_DCMF0_MASK GENMASK_ULL(31, 0)

drivers/firmware/stratix10-rsu.c

22

#define RSU_DCMF1_MASK GENMASK_ULL(63, 32)

drivers/firmware/stratix10-rsu.c

23

#define RSU_DCMF2_MASK GENMASK_ULL(31, 0)

drivers/firmware/stratix10-rsu.c

24

#define RSU_DCMF3_MASK GENMASK_ULL(63, 32)

drivers/firmware/stratix10-rsu.c

25

#define RSU_DCMF0_STATUS_MASK GENMASK_ULL(15, 0)

drivers/firmware/stratix10-rsu.c

26

#define RSU_DCMF1_STATUS_MASK GENMASK_ULL(31, 16)

drivers/firmware/stratix10-rsu.c

27

#define RSU_DCMF2_STATUS_MASK GENMASK_ULL(47, 32)

drivers/firmware/stratix10-rsu.c

28

#define RSU_DCMF3_STATUS_MASK GENMASK_ULL(63, 48)

drivers/firmware/ti_sci.h

1475

#define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)

drivers/firmware/ti_sci.h

1476

#define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)

drivers/firmware/ti_sci.h

174

#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)

drivers/fpga/dfl-afu-error.c

28

#define ERROR_MASK GENMASK_ULL(63, 0)

drivers/fpga/dfl-fme-error.c

118

writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

234

writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);

drivers/fpga/dfl-fme-error.c

38

#define INJECT_ERROR_MASK GENMASK_ULL(2, 0)

drivers/fpga/dfl-fme-error.c

40

#define ERROR_MASK GENMASK_ULL(63, 0)

drivers/fpga/dfl-fme-error.c

73

writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);

drivers/fpga/dfl-fme-main.c

194

#define TEMP_THRESHOLD1 GENMASK_ULL(6, 0)

drivers/fpga/dfl-fme-main.c

196

#define TEMP_THRESHOLD2 GENMASK_ULL(14, 8)

drivers/fpga/dfl-fme-main.c

198

#define TRIP_THRESHOLD GENMASK_ULL(30, 24)

drivers/fpga/dfl-fme-main.c

205

#define FPGA_TEMPERATURE GENMASK_ULL(6, 0)

drivers/fpga/dfl-fme-main.c

367

#define PWR_CONSUMED GENMASK_ULL(17, 0)

drivers/fpga/dfl-fme-main.c

370

#define PWR_THRESHOLD1 GENMASK_ULL(6, 0) /* in Watts */

drivers/fpga/dfl-fme-main.c

371

#define PWR_THRESHOLD2 GENMASK_ULL(14, 8) /* in Watts */

drivers/fpga/dfl-fme-main.c

377

#define XEON_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */

drivers/fpga/dfl-fme-main.c

380

#define FPGA_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */

drivers/fpga/dfl-fme-mgr.c

39

#define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */

drivers/fpga/dfl-fme-mgr.c

45

#define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0)

drivers/fpga/dfl-fme-mgr.c

48

#define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */

drivers/fpga/dfl-fme-mgr.c

49

#define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */

drivers/fpga/dfl-fme-mgr.c

53

#define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)

drivers/fpga/dfl-fme-perf.c

105

#define VTD_CNTR_EVNT_CNTR GENMASK_ULL(47, 0)

drivers/fpga/dfl-fme-perf.c

106

#define VTD_CNTR_EVNT GENMASK_ULL(63, 60)

drivers/fpga/dfl-fme-perf.c

111

#define VTD_SIP_CTRL_EVNT GENMASK_ULL(19, 16)

drivers/fpga/dfl-fme-perf.c

126

#define VTD_SIP_CNTR_EVNT_CNTR GENMASK_ULL(47, 0)

drivers/fpga/dfl-fme-perf.c

127

#define VTD_SIP_CNTR_EVNT GENMASK_ULL(63, 60)

drivers/fpga/dfl-fme-perf.c

199

#define FME_EVENT_MASK GENMASK_ULL(11, 0)

drivers/fpga/dfl-fme-perf.c

201

#define FME_EVTYPE_MASK GENMASK_ULL(15, 12)

drivers/fpga/dfl-fme-perf.c

209

#define FME_PORTID_MASK GENMASK_ULL(23, 16)

drivers/fpga/dfl-fme-perf.c

31

#define CACHE_CTRL_EVNT GENMASK_ULL(19, 16)

drivers/fpga/dfl-fme-perf.c

49

#define CACHE_CNTR_EVNT_CNTR GENMASK_ULL(47, 0)

drivers/fpga/dfl-fme-perf.c

50

#define CACHE_CNTR_EVNT GENMASK_ULL(63, 60)

drivers/fpga/dfl-fme-perf.c

60

#define FAB_CTRL_EVNT GENMASK_ULL(19, 16)

drivers/fpga/dfl-fme-perf.c

70

#define FAB_PORT_ID GENMASK_ULL(21, 20)

drivers/fpga/dfl-fme-perf.c

75

#define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0)

drivers/fpga/dfl-fme-perf.c

76

#define FAB_CNTR_EVNT GENMASK_ULL(63, 60)

drivers/fpga/dfl-fme-perf.c

95

#define VTD_CTRL_EVNT GENMASK_ULL(19, 16)

drivers/fpga/dfl-n3000-nios.c

34

#define N3000_NS_PARAM_DATA_WIDTH GENMASK_ULL(7, 2)

drivers/fpga/dfl-n3000-nios.c

35

#define N3000_NS_PARAM_NUM_CS GENMASK_ULL(13, 8)

drivers/fpga/dfl-n3000-nios.c

38

#define N3000_NS_PARAM_PERIPHERAL_ID GENMASK_ULL(47, 32)

drivers/fpga/dfl-n3000-nios.c

41

#define N3000_NS_CTRL_WR_DATA GENMASK_ULL(31, 0)

drivers/fpga/dfl-n3000-nios.c

42

#define N3000_NS_CTRL_ADDR GENMASK_ULL(44, 32)

drivers/fpga/dfl-n3000-nios.c

43

#define N3000_NS_CTRL_CMD_MSK GENMASK_ULL(63, 62)

drivers/fpga/dfl-n3000-nios.c

49

#define N3000_NS_STAT_RD_DATA GENMASK_ULL(31, 0)

drivers/fpga/dfl.h

100

#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */

drivers/fpga/dfl.h

103

#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */

drivers/fpga/dfl.h

104

#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */

drivers/fpga/dfl.h

106

#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */

drivers/fpga/dfl.h

109

#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */

drivers/fpga/dfl.h

110

#define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */

drivers/fpga/dfl.h

111

#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */

drivers/fpga/dfl.h

116

#define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32)

drivers/fpga/dfl.h

117

#define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0)

drivers/fpga/dfl.h

120

#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */

drivers/fpga/dfl.h

134

#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */

drivers/fpga/dfl.h

140

#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */

drivers/fpga/dfl.h

141

#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */

drivers/fpga/dfl.h

142

#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */

drivers/fpga/dfl.h

143

#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */

drivers/fpga/dfl.h

147

#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)

drivers/fpga/dfl.h

149

#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)

drivers/fpga/dfl.h

161

#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */

drivers/fpga/dfl.h

177

#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */

drivers/fpga/dfl.h

178

#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */

drivers/fpga/dfl.h

179

#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */

drivers/fpga/dfl.h

190

#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */

drivers/fpga/dfl.h

201

#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */

drivers/fpga/dfl.h

207

#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */

drivers/fpga/dfl.h

208

#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */

drivers/fpga/dfl.h

72

#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */

drivers/fpga/dfl.h

75

#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */

drivers/fpga/dfl.h

76

#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */

drivers/fpga/dfl.h

78

#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */

drivers/fpga/dfl.h

79

#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1332

#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))

drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h

34

#define ACA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

106

me = (*pos & GENMASK_ULL(33, 24)) >> 24;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

107

pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

108

queue = (*pos & GENMASK_ULL(53, 44)) >> 44;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

109

vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1160

offset = (*pos & GENMASK_ULL(6, 0));

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1161

se = (*pos & GENMASK_ULL(14, 7)) >> 7;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1162

sh = (*pos & GENMASK_ULL(22, 15)) >> 15;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1163

cu = (*pos & GENMASK_ULL(30, 23)) >> 23;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1164

wave = (*pos & GENMASK_ULL(36, 31)) >> 31;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1165

simd = (*pos & GENMASK_ULL(44, 37)) >> 37;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1251

offset = (*pos & GENMASK_ULL(11, 0)) >> 2;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1252

se = (*pos & GENMASK_ULL(19, 12)) >> 12;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1253

sh = (*pos & GENMASK_ULL(27, 20)) >> 20;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1254

cu = (*pos & GENMASK_ULL(35, 28)) >> 28;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1255

wave = (*pos & GENMASK_ULL(43, 36)) >> 36;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1256

simd = (*pos & GENMASK_ULL(51, 44)) >> 44;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1257

thread = (*pos & GENMASK_ULL(59, 52)) >> 52;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

1258

bank = (*pos & GENMASK_ULL(61, 60)) >> 60;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

93

se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

94

sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

95

instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h

28

#define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

883

adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

884

con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

205

adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

206

con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

101

instlo &= GENMASK_ULL(31, 1);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

126

instlo &= GENMASK_ULL(31, 1);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

161

instlo &= GENMASK_ULL(31, 1);

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

62

((instidlo & GENMASK_ULL(31, 1)) == mmSMNAID_XCD0_MCA_SMU) ? 0 : 1;

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h

29

#define ACA__REG__FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)

drivers/gpu/drm/arm/malidp_crtc.c

227

GENMASK_ULL(14, 0);

drivers/gpu/drm/display/drm_dp_tunnel.c

91

GENMASK_ULL((__start) + (__size) - 1, (__start))

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

3499

args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

464

return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);

drivers/gpu/drm/i915/gt/intel_gtt.h

100

#define GEN12_GGTT_PTE_ADDR_MASK GENMASK_ULL(45, 12)

drivers/gpu/drm/i915/gt/intel_gtt.h

101

#define MTL_GGTT_PTE_PAT_MASK GENMASK_ULL(53, 52)

drivers/gpu/drm/i915/gvt/dmabuf.c

45

#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))

drivers/gpu/drm/i915/gvt/gtt.c

292

#define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)

drivers/gpu/drm/i915/gvt/gtt.c

293

#define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)

drivers/gpu/drm/i915/gvt/gtt.c

294

#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)

drivers/gpu/drm/i915/gvt/gtt.c

295

#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)

drivers/gpu/drm/i915/gvt/gtt.c

297

#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)

drivers/gpu/drm/imagination/pvr_device.h

495

((((u64)(b) & GENMASK_ULL(15, 0)) << 48) | \

drivers/gpu/drm/imagination/pvr_device.h

496

(((u64)(v) & GENMASK_ULL(15, 0)) << 32) | \

drivers/gpu/drm/imagination/pvr_device.h

497

(((u64)(n) & GENMASK_ULL(15, 0)) << 16) | \

drivers/gpu/drm/imagination/pvr_device.h

498

(((u64)(c) & GENMASK_ULL(15, 0)) << 0))

drivers/gpu/drm/imagination/pvr_device.h

528

gpu_id->b = (bvnc & GENMASK_ULL(63, 48)) >> 48;

drivers/gpu/drm/imagination/pvr_device.h

529

gpu_id->v = (bvnc & GENMASK_ULL(47, 32)) >> 32;

drivers/gpu/drm/imagination/pvr_device.h

530

gpu_id->n = (bvnc & GENMASK_ULL(31, 16)) >> 16;

drivers/gpu/drm/imagination/pvr_device.h

531

gpu_id->c = bvnc & GENMASK_ULL(15, 0);

drivers/gpu/drm/msm/adreno/adreno_gpu.c

220

vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", start & GENMASK_ULL(48, 0),

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

45

(((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))

drivers/gpu/drm/msm/msm_iommu.c

689

iova |= GENMASK_ULL(63, 49);

drivers/gpu/drm/msm/msm_iommu.c

703

iova |= GENMASK_ULL(63, 49);

drivers/gpu/drm/panfrost/panfrost_mmu.c

128

region_start &= GENMASK_ULL(63, region_width);

drivers/gpu/drm/panthor/panthor_heap.c

178

hdr->next = (prev_gpuva & GENMASK_ULL(63, 12)) |

drivers/gpu/drm/panthor/panthor_heap.c

390

chunk_gpu_va &= GENMASK_ULL(63, 12);

drivers/gpu/drm/panthor/panthor_heap.c

483

*new_chunk_gpu_va = (panthor_kernel_bo_gpuva(chunk->bo) & GENMASK_ULL(63, 12)) |

drivers/gpu/drm/panthor/panthor_mmu.c

578

*region_start &= GENMASK_ULL(63, region_width);

drivers/gpu/drm/vc4/vc4_kms.c

133

if ((in & GENMASK_ULL(62, 32)) > 0) {

drivers/gpu/drm/xe/regs/xe_gtt_defs.h

16

#define XE_PAGE_ADDR_MASK(shift) GENMASK_ULL(51, (shift))

drivers/gpu/drm/xe/regs/xe_gtt_defs.h

17

#define GGTT_PTE_VFID GENMASK_ULL(11, 2)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

22

#define PKG_TDP GENMASK_ULL(14, 0)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

23

#define PKG_MIN_PWR GENMASK_ULL(30, 16)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

24

#define PKG_MAX_PWR GENMASK_ULL(46, 32)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

25

#define PKG_MAX_WIN GENMASK_ULL(54, 48)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

26

#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)

drivers/gpu/drm/xe/regs/xe_mchbar_regs.h

27

#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)

drivers/gpu/drm/xe/xe_device.c

1333

return address & GENMASK_ULL(xe->info.va_bits - 1, 0);

drivers/gpu/drm/xe/xe_execlist.c

35

GENMASK_ULL(SW_CTX_ID_WIDTH + SW_CTX_ID_SHIFT - 1, \

drivers/gpu/drm/xe/xe_execlist.c

39

GENMASK_ULL(XEHP_SW_CTX_ID_WIDTH + XEHP_SW_CTX_ID_SHIFT - 1, \

drivers/gpu/drm/xe/xe_gsc_submit.c

34

#define HOST_SESSION_CLIENT_MASK GENMASK_ULL(63, 56)

drivers/gpu/drm/xe/xe_hw_engine.c

775

GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)) <= 1)

drivers/gpu/drm/xe/xe_lmtt_ml.c

61

#define LMTT_ML_PDE_LMTT_PTR GENMASK_ULL(LMTT_ML_HAW - 13, 4)

drivers/gpu/drm/xe/xe_lrc.c

41

#define LRC_ADDRESSING_MODE GENMASK_ULL(4, 3)

drivers/gpu/drm/xe/xe_lrc.c

44

#define LRC_ENGINE_CLASS GENMASK_ULL(63, 61)

drivers/gpu/drm/xe/xe_lrc.c

45

#define LRC_ENGINE_INSTANCE GENMASK_ULL(53, 48)

drivers/gpu/drm/xe/xe_lrc.c

51

#define LRC_PRIORITY GENMASK_ULL(10, 9)

drivers/gpu/drm/xe/xe_page_reclaim.h

34

#define XE_PAGE_RECLAIM_SIZE GENMASK_ULL(6, 1)

drivers/gpu/drm/xe/xe_page_reclaim.h

35

#define XE_PAGE_RECLAIM_RSVD_0 GENMASK_ULL(11, 7)

drivers/gpu/drm/xe/xe_page_reclaim.h

37

#define XE_PAGE_RECLAIM_ADDR_LO GENMASK_ULL(31, 12)

drivers/gpu/drm/xe/xe_page_reclaim.h

39

#define XE_PAGE_RECLAIM_ADDR_HI GENMASK_ULL(51, 32)

drivers/gpu/drm/xe/xe_page_reclaim.h

40

#define XE_PAGE_RECLAIM_RSVD_1 GENMASK_ULL(63, 52)

drivers/gpu/drm/xe/xe_pmu.c

54

#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)

drivers/gpu/drm/xe/xe_pmu.c

55

#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)

drivers/gpu/drm/xe/xe_pmu.c

56

#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)

drivers/gpu/drm/xe/xe_pmu.c

57

#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)

drivers/gpu/drm/xe/xe_pmu.c

58

#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)

drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c

153

& ~GENMASK_ULL(5, 0);

drivers/i2c/busses/i2c-rk3x.c

60

#define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)

drivers/i3c/master.c

2694

if ((boardinfo->pid & GENMASK_ULL(63, 48)) ||

drivers/iio/accel/adxl372.c

88

#define ADXL372_POWER_CTL_MODE_MSK GENMASK_ULL(1, 0)

drivers/iio/accel/adxl372.c

92

#define ADXL372_MEASURE_LINKLOOP_MSK GENMASK_ULL(5, 4)

drivers/iio/accel/adxl372.c

94

#define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK_ULL(2, 0)

drivers/iio/accel/adxl372.c

98

#define ADXL372_TIMING_ODR_MSK GENMASK_ULL(7, 5)

drivers/iio/adc/xilinx-ams.c

102

#define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22)

drivers/iio/adc/xilinx-ams.c

125

#define AMS_ALARM_MASK GENMASK_ULL(63, 0)

drivers/iio/adc/xilinx-ams.c

132

#define AMS_ISR1_INTR_MASK GENMASK_ULL(63, 32)

drivers/iio/adc/xilinx-ams.c

99

#define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22)

drivers/iio/gyro/mpu3050-core.c

845

FIELD_GET(GENMASK_ULL(12, 0), otp),

drivers/iio/gyro/mpu3050-core.c

847

FIELD_GET(GENMASK_ULL(17, 13), otp),

drivers/iio/gyro/mpu3050-core.c

849

FIELD_GET(GENMASK_ULL(33, 18), otp),

drivers/iio/gyro/mpu3050-core.c

851

FIELD_GET(GENMASK_ULL(45, 34), otp),

drivers/iio/gyro/mpu3050-core.c

853

FIELD_GET(GENMASK_ULL(49, 47), otp),

drivers/iio/gyro/mpu3050-core.c

855

FIELD_GET(GENMASK_ULL(55, 50), otp));

drivers/iio/light/rohm-bu27034.c

619

if (val < GENMASK_ULL(51, 0)) {

drivers/iio/magnetometer/yamaha-yas530.c

806

c->a2 = FIELD_GET(GENMASK_ULL(63, 58), val) - 32;

drivers/iio/magnetometer/yamaha-yas530.c

807

c->a3 = FIELD_GET(GENMASK_ULL(57, 54), val) - 8;

drivers/iio/magnetometer/yamaha-yas530.c

808

c->a4 = FIELD_GET(GENMASK_ULL(53, 48), val) - 32;

drivers/iio/magnetometer/yamaha-yas530.c

809

c->a5 = FIELD_GET(GENMASK_ULL(47, 42), val) + 38;

drivers/iio/magnetometer/yamaha-yas530.c

810

c->a6 = FIELD_GET(GENMASK_ULL(41, 36), val) - 32;

drivers/iio/magnetometer/yamaha-yas530.c

811

c->a7 = FIELD_GET(GENMASK_ULL(35, 29), val) - 64;

drivers/iio/magnetometer/yamaha-yas530.c

812

c->a8 = FIELD_GET(GENMASK_ULL(28, 23), val) - 32;

drivers/iio/magnetometer/yamaha-yas530.c

813

c->a9 = FIELD_GET(GENMASK_ULL(22, 15), val);

drivers/iio/magnetometer/yamaha-yas530.c

814

c->k = FIELD_GET(GENMASK_ULL(14, 10), val) + 10;

drivers/iio/magnetometer/yamaha-yas530.c

815

c->dck = FIELD_GET(GENMASK_ULL(9, 7), val);

drivers/iio/temperature/ltc2983.c

198

(GENMASK_ULL(LTC2983_SENSOR_THERMOCOUPLE_CUSTOM, LTC2983_SENSOR_THERMOCOUPLE) | \

drivers/iio/temperature/ltc2983.c

199

GENMASK_ULL(LTC2983_SENSOR_RTD_CUSTOM, LTC2983_SENSOR_RTD) | \

drivers/iio/temperature/ltc2983.c

200

GENMASK_ULL(LTC2983_SENSOR_THERMISTOR_CUSTOM, LTC2983_SENSOR_THERMISTOR) | \

drivers/iio/temperature/ltc2983.c

207

(GENMASK_ULL(LTC2983_SENSOR_RTD_CUSTOM - 1, LTC2983_SENSOR_RTD) | \

drivers/iio/temperature/ltc2983.c

208

GENMASK_ULL(LTC2983_SENSOR_THERMISTOR_CUSTOM - 1, LTC2983_SENSOR_THERMISTOR) | \

drivers/infiniband/hw/erdma/erdma_hw.h

102

#define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)

drivers/infiniband/hw/erdma/erdma_hw.h

103

#define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)

drivers/infiniband/hw/erdma/erdma_hw.h

106

#define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)

drivers/infiniband/hw/erdma/erdma_hw.h

107

#define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

110

#define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

172

#define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)

drivers/infiniband/hw/erdma/erdma_hw.h

173

#define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32)

drivers/infiniband/hw/erdma/erdma_hw.h

174

#define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)

drivers/infiniband/hw/erdma/erdma_hw.h

175

#define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

176

#define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

237

#define ERDMA_CMD_ALLOC_DB_RESP_RDB_MASK GENMASK_ULL(63, 48)

drivers/infiniband/hw/erdma/erdma_hw.h

238

#define ERDMA_CMD_ALLOC_DB_RESP_CDB_MASK GENMASK_ULL(47, 32)

drivers/infiniband/hw/erdma/erdma_hw.h

239

#define ERDMA_CMD_ALLOC_DB_RESP_SDB_MASK GENMASK_ULL(15, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

367

#define ERDMA_CMD_QUERY_QP_RESP_SQ_PSN_MASK GENMASK_ULL(23, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

368

#define ERDMA_CMD_QUERY_QP_RESP_RQ_PSN_MASK GENMASK_ULL(47, 24)

drivers/infiniband/hw/erdma/erdma_hw.h

369

#define ERDMA_CMD_QUERY_QP_RESP_QP_STATE_MASK GENMASK_ULL(55, 48)

drivers/infiniband/hw/erdma/erdma_hw.h

370

#define ERDMA_CMD_QUERY_QP_RESP_SQ_DRAINING_MASK GENMASK_ULL(56, 56)

drivers/infiniband/hw/erdma/erdma_hw.h

407

#define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

501

#define ERDMA_CMD_DEV_CAP_MAX_GID_MASK GENMASK_ULL(51, 48)

drivers/infiniband/hw/erdma/erdma_hw.h

502

#define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40)

drivers/infiniband/hw/erdma/erdma_hw.h

503

#define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24)

drivers/infiniband/hw/erdma/erdma_hw.h

504

#define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

505

#define ERDMA_CMD_DEV_CAP_MAX_AH_MASK GENMASK_ULL(15, 8)

drivers/infiniband/hw/erdma/erdma_hw.h

506

#define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

509

#define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK GENMASK_ULL(63, 32)

drivers/infiniband/hw/erdma/erdma_hw.h

510

#define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28)

drivers/infiniband/hw/erdma/erdma_hw.h

511

#define ERDMA_CMD_DEV_CAP_QBLOCK_MASK GENMASK_ULL(27, 16)

drivers/infiniband/hw/erdma/erdma_hw.h

512

#define ERDMA_CMD_DEV_CAP_MAX_MW_MASK GENMASK_ULL(7, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

522

#define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

578

#define ERDMA_SQE_HDR_SGL_LEN_MASK GENMASK_ULL(63, 56)

drivers/infiniband/hw/erdma/erdma_hw.h

579

#define ERDMA_SQE_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)

drivers/infiniband/hw/erdma/erdma_hw.h

580

#define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32)

drivers/infiniband/hw/erdma/erdma_hw.h

581

#define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27)

drivers/infiniband/hw/erdma/erdma_hw.h

587

#define ERDMA_SQE_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)

drivers/infiniband/hw/erdma/erdma_hw.h

664

#define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32)

drivers/infiniband/hw/erdma/erdma_hw.h

666

#define ERDMA_CEQE_HDR_CQN_MASK GENMASK_ULL(19, 0)

drivers/infiniband/hw/irdma/defs.h

322

#define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)

drivers/infiniband/hw/irdma/defs.h

323

#define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)

drivers/infiniband/hw/irdma/defs.h

324

#define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)

drivers/infiniband/hw/irdma/defs.h

325

#define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)

drivers/infiniband/hw/irdma/defs.h

326

#define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

327

#define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

328

#define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

329

#define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

330

#define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

332

#define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

333

#define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)

drivers/infiniband/hw/irdma/defs.h

336

#define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)

drivers/infiniband/hw/irdma/defs.h

341

#define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

342

#define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)

drivers/infiniband/hw/irdma/defs.h

343

#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

345

#define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52)

drivers/infiniband/hw/irdma/defs.h

346

#define IRDMA_SD_MAX GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

347

#define IRDMA_MEM_MAX GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

348

#define IRDMA_QP_MEM_LOC GENMASK_ULL(47, 44)

drivers/infiniband/hw/irdma/defs.h

349

#define IRDMA_MR_MEM_LOC GENMASK_ULL(27, 24)

drivers/infiniband/hw/irdma/defs.h

353

#define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)

drivers/infiniband/hw/irdma/defs.h

354

#define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)

drivers/infiniband/hw/irdma/defs.h

355

#define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)

drivers/infiniband/hw/irdma/defs.h

356

#define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)

drivers/infiniband/hw/irdma/defs.h

357

#define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

358

#define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(29, 16)

drivers/infiniband/hw/irdma/defs.h

359

#define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(13, 0)

drivers/infiniband/hw/irdma/defs.h

360

#define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

361

#define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)

drivers/infiniband/hw/irdma/defs.h

366

#define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

367

#define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

368

#define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

370

#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

371

#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

372

#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

373

#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)

drivers/infiniband/hw/irdma/defs.h

374

#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

375

#define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)

drivers/infiniband/hw/irdma/defs.h

378

#define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)

drivers/infiniband/hw/irdma/defs.h

379

#define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)

drivers/infiniband/hw/irdma/defs.h

380

#define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)

drivers/infiniband/hw/irdma/defs.h

381

#define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

382

#define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

383

#define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

384

#define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)

drivers/infiniband/hw/irdma/defs.h

385

#define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)

drivers/infiniband/hw/irdma/defs.h

387

#define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

388

#define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

393

#define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)

drivers/infiniband/hw/irdma/defs.h

394

#define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)

drivers/infiniband/hw/irdma/defs.h

396

#define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

398

#define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)

drivers/infiniband/hw/irdma/defs.h

399

#define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)

drivers/infiniband/hw/irdma/defs.h

400

#define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)

drivers/infiniband/hw/irdma/defs.h

403

#define IRDMA_CQPHC_TS_SHIFT GENMASK_ULL(12, 8)

drivers/infiniband/hw/irdma/defs.h

406

#define IRDMA_CQPHC_OOISC_BLKSIZE GENMASK_ULL(63, 60)

drivers/infiniband/hw/irdma/defs.h

407

#define IRDMA_CQPHC_RRSP_BLKSIZE GENMASK_ULL(59, 56)

drivers/infiniband/hw/irdma/defs.h

408

#define IRDMA_CQPHC_Q1_BLKSIZE GENMASK_ULL(55, 52)

drivers/infiniband/hw/irdma/defs.h

409

#define IRDMA_CQPHC_XMIT_BLKSIZE GENMASK_ULL(51, 48)

drivers/infiniband/hw/irdma/defs.h

412

#define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)

drivers/infiniband/hw/irdma/defs.h

413

#define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)

drivers/infiniband/hw/irdma/defs.h

414

#define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)

drivers/infiniband/hw/irdma/defs.h

415

#define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)

drivers/infiniband/hw/irdma/defs.h

418

#define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)

drivers/infiniband/hw/irdma/defs.h

423

#define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

425

#define IRDMA_CCQ_DEFINFO GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

427

#define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

428

#define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)

drivers/infiniband/hw/irdma/defs.h

429

#define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)

drivers/infiniband/hw/irdma/defs.h

440

#define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)

drivers/infiniband/hw/irdma/defs.h

441

#define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

443

#define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

444

#define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

445

#define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

446

#define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

447

#define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

448

#define IRDMACQ_QPID GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

450

#define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

455

#define IRDMACQ_OP GENMASK_ULL(61, 56)

drivers/infiniband/hw/irdma/defs.h

457

#define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)

drivers/infiniband/hw/irdma/defs.h

462

#define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)

drivers/infiniband/hw/irdma/defs.h

464

#define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)

drivers/infiniband/hw/irdma/defs.h

466

#define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)

drivers/infiniband/hw/irdma/defs.h

467

#define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)

drivers/infiniband/hw/irdma/defs.h

468

#define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)

drivers/infiniband/hw/irdma/defs.h

469

#define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)

drivers/infiniband/hw/irdma/defs.h

470

#define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)

drivers/infiniband/hw/irdma/defs.h

473

#define IRDMA_AEQE_Q2DATA_GEN_3 GENMASK_ULL(5, 4)

drivers/infiniband/hw/irdma/defs.h

474

#define IRDMA_AEQE_TCPSTATE_GEN_3 GENMASK_ULL(3, 0)

drivers/infiniband/hw/irdma/defs.h

475

#define IRDMA_AEQE_QPCQID_GEN_3 GENMASK_ULL(24, 0)

drivers/infiniband/hw/irdma/defs.h

476

#define IRDMA_AEQE_AECODE_GEN_3 GENMASK_ULL(61, 50)

drivers/infiniband/hw/irdma/defs.h

478

#define IRDMA_AEQE_WQDESCIDX_GEN_3 GENMASK_ULL(49, 32)

drivers/infiniband/hw/irdma/defs.h

479

#define IRDMA_AEQE_IWSTATE_GEN_3 GENMASK_ULL(31, 29)

drivers/infiniband/hw/irdma/defs.h

480

#define IRDMA_AEQE_AESRC_GEN_3 GENMASK_ULL(28, 25)

drivers/infiniband/hw/irdma/defs.h

482

#define IRDMA_AEQE_CMPL_CTXT GENMASK_ULL(63, 6)

drivers/infiniband/hw/irdma/defs.h

484

#define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)

drivers/infiniband/hw/irdma/defs.h

485

#define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

486

#define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)

drivers/infiniband/hw/irdma/defs.h

487

#define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)

drivers/infiniband/hw/irdma/defs.h

488

#define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)

drivers/infiniband/hw/irdma/defs.h

491

#define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)

drivers/infiniband/hw/irdma/defs.h

492

#define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)

drivers/infiniband/hw/irdma/defs.h

493

#define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)

drivers/infiniband/hw/irdma/defs.h

494

#define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)

drivers/infiniband/hw/irdma/defs.h

495

#define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)

drivers/infiniband/hw/irdma/defs.h

496

#define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)

drivers/infiniband/hw/irdma/defs.h

498

#define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)

drivers/infiniband/hw/irdma/defs.h

499

#define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)

drivers/infiniband/hw/irdma/defs.h

501

#define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

502

#define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

504

#define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

506

#define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(23, 8)

drivers/infiniband/hw/irdma/defs.h

511

#define IRDMA_CQPSQ_PASID GENMASK_ULL(51, 32)

drivers/infiniband/hw/irdma/defs.h

516

#define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)

drivers/infiniband/hw/irdma/defs.h

517

#define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)

drivers/infiniband/hw/irdma/defs.h

532

#define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)

drivers/infiniband/hw/irdma/defs.h

538

#define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)

drivers/infiniband/hw/irdma/defs.h

541

#define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)

drivers/infiniband/hw/irdma/defs.h

545

#define IRDMA_CQPSQ_SRQ_RQSIZE GENMASK_ULL(3, 0)

drivers/infiniband/hw/irdma/defs.h

546

#define IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE GENMASK_ULL(5, 4)

drivers/infiniband/hw/irdma/defs.h

547

#define IRDMA_CQPSQ_SRQ_SRQ_LIMIT GENMASK_ULL(43, 32)

drivers/infiniband/hw/irdma/defs.h

548

#define IRDMA_CQPSQ_SRQ_SRQCTX GENMASK_ULL(63, 6)

drivers/infiniband/hw/irdma/defs.h

549

#define IRDMA_CQPSQ_SRQ_PD_ID GENMASK_ULL(39, 16)

drivers/infiniband/hw/irdma/defs.h

550

#define IRDMA_CQPSQ_SRQ_SRQ_ID GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

551

#define IRDMA_CQPSQ_SRQ_OP GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

552

#define IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE GENMASK_ULL(45, 44)

drivers/infiniband/hw/irdma/defs.h

556

#define IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX GENMASK_ULL(27, 0)

drivers/infiniband/hw/irdma/defs.h

557

#define IRDMA_CQPSQ_SRQ_TPH_VALUE GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

559

#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR GENMASK_ULL(63, 8)

drivers/infiniband/hw/irdma/defs.h

561

#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR GENMASK_ULL(63, 6)

drivers/infiniband/hw/irdma/defs.h

563

#define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)

drivers/infiniband/hw/irdma/defs.h

564

#define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)

drivers/infiniband/hw/irdma/defs.h

567

#define IRDMA_CQPSQ_CQ_CQID_HIGH GENMASK_ULL(52, 50)

drivers/infiniband/hw/irdma/defs.h

568

#define IRDMA_CQPSQ_CQ_CEQID_HIGH GENMASK_ULL(59, 54)

drivers/infiniband/hw/irdma/defs.h

569

#define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

571

#define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)

drivers/infiniband/hw/irdma/defs.h

577

#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)

drivers/infiniband/hw/irdma/defs.h

581

#define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)

drivers/infiniband/hw/irdma/defs.h

582

#define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

583

#define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)

drivers/infiniband/hw/irdma/defs.h

585

#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

589

#define IRDMA_CQPSQ_STAG_PDID_HI GENMASK_ULL(59, 54)

drivers/infiniband/hw/irdma/defs.h

592

#define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)

drivers/infiniband/hw/irdma/defs.h

593

#define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)

drivers/infiniband/hw/irdma/defs.h

600

#define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

603

#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)

drivers/infiniband/hw/irdma/defs.h

605

#define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)

drivers/infiniband/hw/irdma/defs.h

608

#define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

609

#define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)

drivers/infiniband/hw/irdma/defs.h

610

#define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)

drivers/infiniband/hw/irdma/defs.h

611

#define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)

drivers/infiniband/hw/irdma/defs.h

612

#define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)

drivers/infiniband/hw/irdma/defs.h

613

#define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)

drivers/infiniband/hw/irdma/defs.h

614

#define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

615

#define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)

drivers/infiniband/hw/irdma/defs.h

616

#define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)

drivers/infiniband/hw/irdma/defs.h

620

#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)

drivers/infiniband/hw/irdma/defs.h

621

#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)

drivers/infiniband/hw/irdma/defs.h

622

#define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)

drivers/infiniband/hw/irdma/defs.h

624

#define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)

drivers/infiniband/hw/irdma/defs.h

629

#define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

630

#define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)

drivers/infiniband/hw/irdma/defs.h

635

#define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

636

#define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)

drivers/infiniband/hw/irdma/defs.h

641

#define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

644

#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)

drivers/infiniband/hw/irdma/defs.h

645

#define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

646

#define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)

drivers/infiniband/hw/irdma/defs.h

647

#define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)

drivers/infiniband/hw/irdma/defs.h

649

#define IRDMA_CQPSQ_CEQ_CEQID_HIGH GENMASK_ULL(15, 10)

drivers/infiniband/hw/irdma/defs.h

654

#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)

drivers/infiniband/hw/irdma/defs.h

655

#define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)

drivers/infiniband/hw/irdma/defs.h

658

#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)

drivers/infiniband/hw/irdma/defs.h

660

#define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(20, 0)

drivers/infiniband/hw/irdma/defs.h

662

#define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

666

#define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

667

#define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)

drivers/infiniband/hw/irdma/defs.h

668

#define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

669

#define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)

drivers/infiniband/hw/irdma/defs.h

670

#define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

671

#define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

672

#define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

678

#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX GENMASK_ULL(49, 32)

drivers/infiniband/hw/irdma/defs.h

680

#define IRDMA_CQPSQ_FWQE_ERR_RQ_IDX GENMASK_ULL(46, 32)

drivers/infiniband/hw/irdma/defs.h

681

#define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

683

#define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

684

#define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

685

#define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

686

#define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)

drivers/infiniband/hw/irdma/defs.h

693

#define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)

drivers/infiniband/hw/irdma/defs.h

694

#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)

drivers/infiniband/hw/irdma/defs.h

696

#define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

697

#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

710

#define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)

drivers/infiniband/hw/irdma/defs.h

717

#define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)

drivers/infiniband/hw/irdma/defs.h

719

#define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)

drivers/infiniband/hw/irdma/defs.h

722

#define IRDMAQPC_SRQ_ID GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

723

#define IRDMAQPC_PASID GENMASK_ULL(19, 0)

drivers/infiniband/hw/irdma/defs.h

728

#define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)

drivers/infiniband/hw/irdma/defs.h

730

#define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)

drivers/infiniband/hw/irdma/defs.h

736

#define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)

drivers/infiniband/hw/irdma/defs.h

738

#define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)

drivers/infiniband/hw/irdma/defs.h

739

#define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)

drivers/infiniband/hw/irdma/defs.h

743

#define IRDMAQPC_TTL GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

744

#define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)

drivers/infiniband/hw/irdma/defs.h

745

#define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)

drivers/infiniband/hw/irdma/defs.h

748

#define IRDMAQPC_TOS GENMASK_ULL(31, 24)

drivers/infiniband/hw/irdma/defs.h

749

#define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

750

#define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

751

#define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

752

#define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

753

#define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

754

#define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

755

#define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)

drivers/infiniband/hw/irdma/defs.h

756

#define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)

drivers/infiniband/hw/irdma/defs.h

757

#define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

758

#define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

759

#define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)

drivers/infiniband/hw/irdma/defs.h

764

#define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)

drivers/infiniband/hw/irdma/defs.h

765

#define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)

drivers/infiniband/hw/irdma/defs.h

766

#define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)

drivers/infiniband/hw/irdma/defs.h

767

#define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

768

#define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)

drivers/infiniband/hw/irdma/defs.h

769

#define IRDMAQPC_PKEY GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

770

#define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)

drivers/infiniband/hw/irdma/defs.h

771

#define IRDMAQPC_QKEY GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

772

#define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

773

#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)

drivers/infiniband/hw/irdma/defs.h

774

#define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)

drivers/infiniband/hw/irdma/defs.h

775

#define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

776

#define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

777

#define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

778

#define IRDMAQPC_ISN GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

779

#define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

780

#define IRDMAQPC_LSN GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

781

#define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

782

#define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

783

#define IRDMAQPC_EPSN GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

784

#define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

785

#define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

786

#define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

787

#define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/defs.h

788

#define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

789

#define IRDMAQPC_SRTT GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

790

#define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

791

#define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

792

#define IRDMAQPC_CWND GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

793

#define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

794

#define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

795

#define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

796

#define IRDMAQPC_MINRNR_TIMER GENMASK_ULL(4, 0)

drivers/infiniband/hw/irdma/defs.h

797

#define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)

drivers/infiniband/hw/irdma/defs.h

798

#define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)

drivers/infiniband/hw/irdma/defs.h

799

#define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

800

#define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)

drivers/infiniband/hw/irdma/defs.h

801

#define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)

drivers/infiniband/hw/irdma/defs.h

802

#define IRDMAQPC_TXCQNUM GENMASK_ULL(24, 0)

drivers/infiniband/hw/irdma/defs.h

803

#define IRDMAQPC_RXCQNUM GENMASK_ULL(56, 32)

drivers/infiniband/hw/irdma/defs.h

804

#define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)

drivers/infiniband/hw/irdma/defs.h

805

#define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)

drivers/infiniband/hw/irdma/defs.h

806

#define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

807

#define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)

drivers/infiniband/hw/irdma/defs.h

808

#define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

810

#define IRDMAQPC_LOCALACKTIMEOUT GENMASK_ULL(12, 8)

drivers/infiniband/hw/irdma/defs.h

811

#define IRDMAQPC_RNRNAK_TMR GENMASK_ULL(4, 0)

drivers/infiniband/hw/irdma/defs.h

812

#define IRDMAQPC_ORDSIZE_GEN3 GENMASK_ULL(10, 0)

drivers/infiniband/hw/irdma/defs.h

814

#define IRDMAQPC_STAT_INDEX_GEN3 GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

815

#define IRDMAQPC_PKT_LIMIT GENMASK_ULL(55, 48)

drivers/infiniband/hw/irdma/defs.h

817

#define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)

drivers/infiniband/hw/irdma/defs.h

819

#define IRDMAQPC_IRDSIZE_GEN3 GENMASK_ULL(17, 14)

drivers/infiniband/hw/irdma/defs.h

832

#define IRDMAQPC_THIGH GENMASK_ULL(63, 52)

drivers/infiniband/hw/irdma/defs.h

833

#define IRDMAQPC_TLOW GENMASK_ULL(39, 32)

drivers/infiniband/hw/irdma/defs.h

834

#define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)

drivers/infiniband/hw/irdma/defs.h

840

#define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)

drivers/infiniband/hw/irdma/defs.h

841

#define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)

drivers/infiniband/hw/irdma/defs.h

844

#define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

845

#define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)

drivers/infiniband/hw/irdma/defs.h

846

#define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)

drivers/infiniband/hw/irdma/defs.h

847

#define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)

drivers/infiniband/hw/irdma/defs.h

848

#define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

849

#define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

850

#define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

851

#define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

852

#define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/defs.h

853

#define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)

drivers/infiniband/hw/irdma/defs.h

854

#define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)

drivers/infiniband/hw/irdma/defs.h

855

#define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

856

#define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

857

#define IRDMA_FEATURE_RSRC_MAX GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

859

#define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/defs.h

861

#define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)

drivers/infiniband/hw/irdma/defs.h

868

#define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)

drivers/infiniband/hw/irdma/defs.h

874

#define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)

drivers/infiniband/hw/irdma/defs.h

875

#define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

876

#define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

877

#define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

878

#define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

879

#define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

880

#define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)

drivers/infiniband/hw/irdma/defs.h

881

#define IRDMAQPSQ_AHID GENMASK_ULL(24, 0)

drivers/infiniband/hw/irdma/defs.h

885

#define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)

drivers/infiniband/hw/irdma/defs.h

889

#define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)

drivers/infiniband/hw/irdma/defs.h

890

#define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

894

#define IRDMAQPSQ_STAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

895

#define IRDMAQPSQ_REMOTE_STAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

897

#define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)

drivers/infiniband/hw/irdma/defs.h

902

#define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

903

#define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

909

#define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

911

#define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)

drivers/infiniband/hw/irdma/defs.h

912

#define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)

drivers/infiniband/hw/irdma/defs.h

914

#define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)

drivers/infiniband/hw/irdma/defs.h

915

#define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)

drivers/infiniband/hw/irdma/defs.h

916

#define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)

drivers/infiniband/hw/irdma/defs.h

917

#define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/defs.h

918

#define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)

drivers/infiniband/hw/irdma/defs.h

919

#define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)

drivers/infiniband/hw/irdma/defs.h

933

#define IRDMA_QUERY_FPM_LOC_MEM_PAGES GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

934

#define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

935

#define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/defs.h

936

#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)

drivers/infiniband/hw/irdma/defs.h

937

#define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(44, 32)

drivers/infiniband/hw/irdma/defs.h

938

#define IRDMA_QUERY_FPM_MAX_PE_SDS_GEN3 GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

939

#define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)

drivers/infiniband/hw/irdma/defs.h

940

#define IRDMA_QUERY_FPM_MAX_IRD GENMASK_ULL(53, 50)

drivers/infiniband/hw/irdma/defs.h

941

#define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

942

#define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

943

#define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)

drivers/infiniband/hw/irdma/defs.h

944

#define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/defs.h

945

#define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

946

#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

947

#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/defs.h

948

#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)

drivers/infiniband/hw/irdma/i40iw_hw.h

111

#define I40E_CQPSQ_STAG_PDID GENMASK_ULL(62, 48)

drivers/infiniband/hw/irdma/i40iw_hw.h

123

#define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/i40iw_hw.h

125

#define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)

drivers/infiniband/hw/irdma/i40iw_hw.h

127

#define I40E_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)

drivers/infiniband/hw/irdma/icrdma_hw.h

54

#define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)

drivers/infiniband/hw/irdma/icrdma_hw.h

56

#define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)

drivers/infiniband/hw/irdma/icrdma_hw.h

58

#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)

drivers/infiniband/hw/irdma/icrdma_hw.h

60

#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)

drivers/infiniband/hw/irdma/icrdma_hw.h

62

#define ICRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)

drivers/infiniband/hw/irdma/uda_d.h

100

#define IRDMA_UDA_MGCTX_VFID GENMASK_ULL(28, 22)

drivers/infiniband/hw/irdma/uda_d.h

102

#define IRDMA_UDA_MGCTX_PFID GENMASK_ULL(21, 18)

drivers/infiniband/hw/irdma/uda_d.h

104

#define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0)

drivers/infiniband/hw/irdma/uda_d.h

106

#define IRDMA_UDA_CQPSQ_MG_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/uda_d.h

107

#define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0)

drivers/infiniband/hw/irdma/uda_d.h

110

#define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0)

drivers/infiniband/hw/irdma/uda_d.h

111

#define IRDMA_UDA_CQPSQ_MG_VLANID GENMASK_ULL(43, 32)

drivers/infiniband/hw/irdma/uda_d.h

112

#define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0)

drivers/infiniband/hw/irdma/uda_d.h

113

#define IRDMA_UDA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)

drivers/infiniband/hw/irdma/uda_d.h

115

#define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)

drivers/infiniband/hw/irdma/uda_d.h

116

#define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/uda_d.h

117

#define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/uda_d.h

118

#define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/uda_d.h

119

#define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/uda_d.h

120

#define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/uda_d.h

122

#define IRDMA_UDA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/uda_d.h

123

#define IRDMA_UDA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)

drivers/infiniband/hw/irdma/uda_d.h

124

#define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID GENMASK_ULL(60, 60)

drivers/infiniband/hw/irdma/uda_d.h

125

#define IRDMA_UDA_CQPSQ_QHASH_LANFWD GENMASK_ULL(59, 59)

drivers/infiniband/hw/irdma/uda_d.h

126

#define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)

drivers/infiniband/hw/irdma/uda_d.h

19

#define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)

drivers/infiniband/hw/irdma/uda_d.h

20

#define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)

drivers/infiniband/hw/irdma/uda_d.h

21

#define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)

drivers/infiniband/hw/irdma/uda_d.h

25

#define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)

drivers/infiniband/hw/irdma/uda_d.h

26

#define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)

drivers/infiniband/hw/irdma/uda_d.h

27

#define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)

drivers/infiniband/hw/irdma/uda_d.h

29

#define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)

drivers/infiniband/hw/irdma/uda_d.h

31

#define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)

drivers/infiniband/hw/irdma/uda_d.h

33

#define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)

drivers/infiniband/hw/irdma/uda_d.h

35

#define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)

drivers/infiniband/hw/irdma/uda_d.h

41

#define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)

drivers/infiniband/hw/irdma/uda_d.h

49

#define IRDMA_UDAQPC_PDINDEXHI GENMASK_ULL(21, 20)

drivers/infiniband/hw/irdma/uda_d.h

69

#define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48)

drivers/infiniband/hw/irdma/uda_d.h

70

#define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32)

drivers/infiniband/hw/irdma/uda_d.h

73

#define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0)

drivers/infiniband/hw/irdma/uda_d.h

78

#define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)

drivers/infiniband/hw/irdma/uda_d.h

79

#define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16)

drivers/infiniband/hw/irdma/uda_d.h

80

#define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)

drivers/infiniband/hw/irdma/uda_d.h

81

#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(27, 20)

drivers/infiniband/hw/irdma/uda_d.h

82

#define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/uda_d.h

83

#define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24)

drivers/infiniband/hw/irdma/uda_d.h

84

#define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)

drivers/infiniband/hw/irdma/uda_d.h

85

#define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32)

drivers/infiniband/hw/irdma/uda_d.h

86

#define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32)

drivers/infiniband/hw/irdma/uda_d.h

87

#define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0)

drivers/infiniband/hw/irdma/uda_d.h

88

#define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/uda_d.h

89

#define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/uda_d.h

90

#define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32)

drivers/infiniband/hw/irdma/uda_d.h

91

#define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0)

drivers/infiniband/hw/irdma/uda_d.h

93

#define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32)

drivers/infiniband/hw/irdma/uda_d.h

96

#define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(23, 0)

drivers/infiniband/hw/irdma/uda_d.h

99

#define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32)

drivers/infiniband/hw/mlx4/mlx4_ib.h

671

#define MLX4_PAGE_SIZE_SUPPORTED ((unsigned long)GENMASK_ULL(31, 12))

drivers/infiniband/hw/mlx5/devx.c

2305

pgsz_bitmap &= GENMASK_ULL(max_t(u64, order_base_2(umem->length),

drivers/infiniband/hw/mlx5/devx.c

2355

GENMASK_ULL(63,

drivers/infiniband/hw/mlx5/mlx5_ib.h

1744

bitmap = GENMASK_ULL(max_log_entity_size_cap, min_log_entity_size_cap);

drivers/infiniband/hw/mlx5/mlx5_ib.h

1748

bitmap &= GENMASK_ULL(__ffs64(iova), 0);

drivers/infiniband/hw/mlx5/mr.c

167

#define MLX5_FRMR_POOLS_KERNEL_KEY_PH_MASK GENMASK_ULL(23, 16)

drivers/infiniband/hw/mlx5/mr.c

168

#define MLX5_FRMR_POOLS_KERNEL_KEY_ST_INDEX_MASK GENMASK_ULL(15, 0)

drivers/iommu/amd/amd_iommu_types.h

101

#define FEATURE_PASMAX GENMASK_ULL(36, 32)

drivers/iommu/amd/amd_iommu_types.h

112

#define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)

drivers/iommu/amd/amd_iommu_types.h

117

#define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)

drivers/iommu/amd/amd_iommu_types.h

232

#define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40)

drivers/iommu/amd/amd_iommu_types.h

251

#define MMIO_CMD_HEAD_MASK GENMASK_ULL(18, 4) /* Command buffer head ptr field [18:4] */

drivers/iommu/amd/amd_iommu_types.h

253

#define MMIO_CMD_TAIL_MASK GENMASK_ULL(18, 4) /* Command buffer tail ptr field [18:4] */

drivers/iommu/amd/amd_iommu_types.h

312

#define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)

drivers/iommu/amd/amd_iommu_types.h

321

#define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)

drivers/iommu/amd/amd_iommu_types.h

355

#define DTE_MODE_MASK GENMASK_ULL(11, 9)

drivers/iommu/amd/amd_iommu_types.h

356

#define DTE_HOST_TRP GENMASK_ULL(51, 12)

drivers/iommu/amd/amd_iommu_types.h

360

#define DTE_GLX GENMASK_ULL(57, 56)

drivers/iommu/amd/amd_iommu_types.h

366

#define DTE_DOMID_MASK GENMASK_ULL(15, 0)

drivers/iommu/amd/amd_iommu_types.h

368

#define DTE_GCR3_14_12 GENMASK_ULL(60, 58)

drivers/iommu/amd/amd_iommu_types.h

369

#define DTE_GCR3_30_15 GENMASK_ULL(31, 16)

drivers/iommu/amd/amd_iommu_types.h

370

#define DTE_GCR3_51_31 GENMASK_ULL(63, 43)

drivers/iommu/amd/amd_iommu_types.h

373

#define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54)

drivers/iommu/amd/amd_iommu_types.h

378

#define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52)

drivers/iommu/amd/amd_iommu_types.h

393

#define IOMMU_IVINFO_VASIZE GENMASK_ULL(21, 15)

drivers/iommu/amd/amd_iommu_types.h

97

#define FEATURE_HATS GENMASK_ULL(11, 10)

drivers/iommu/amd/amd_iommu_types.h

98

#define FEATURE_GATS GENMASK_ULL(13, 12)

drivers/iommu/amd/amd_iommu_types.h

99

#define FEATURE_GLX GENMASK_ULL(15, 14)

drivers/iommu/amd/init.c

3995

u64 val = *value & GENMASK_ULL(47, 0);

drivers/iommu/amd/init.c

4003

*value &= GENMASK_ULL(47, 0);

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

145

#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

175

#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

195

#define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

214

#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

215

#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

244

#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

251

#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

254

#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

255

#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

257

#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

266

#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

267

#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

268

#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

274

#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

279

#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

283

#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

286

#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

287

#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

288

#define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

289

#define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

290

#define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

291

#define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

292

#define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

293

#define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

294

#define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

301

#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

322

#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

348

#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

349

#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

350

#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

351

#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

352

#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

359

#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

370

#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

372

#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

404

#define CMDQ_0_OP GENMASK_ULL(7, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

407

#define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

408

#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

409

#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

411

#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

412

#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

414

#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

416

#define CMDQ_TLBI_0_NUM GENMASK_ULL(16, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

418

#define CMDQ_TLBI_0_SCALE GENMASK_ULL(24, 20)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

419

#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

420

#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

422

#define CMDQ_TLBI_1_TTL GENMASK_ULL(9, 8)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

423

#define CMDQ_TLBI_1_TG GENMASK_ULL(11, 10)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

424

#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

425

#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

427

#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

428

#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

430

#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

431

#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

435

#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

436

#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

437

#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

438

#define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

449

#define CMDQ_RESUME_0_RESP GENMASK_ULL(13, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

450

#define CMDQ_RESUME_0_SID GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

451

#define CMDQ_RESUME_1_STAG GENMASK_ULL(15, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

453

#define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

457

#define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

458

#define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

459

#define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

460

#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

606

#define EVTQ_0_ID GENMASK_ULL(7, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

622

#define EVTQ_0_SSID GENMASK_ULL(31, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

623

#define EVTQ_0_SID GENMASK_ULL(63, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

624

#define EVTQ_1_STAG GENMASK_ULL(15, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

630

#define EVTQ_1_CLASS GENMASK_ULL(41, 40)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

633

#define EVTQ_2_ADDR GENMASK_ULL(63, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

634

#define EVTQ_3_IPA GENMASK_ULL(51, 12)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

635

#define EVTQ_3_FETCH_ADDR GENMASK_ULL(51, 3)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

642

#define PRIQ_0_SID GENMASK_ULL(31, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

643

#define PRIQ_0_SSID GENMASK_ULL(51, 32)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

651

#define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

652

#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

23

#define DEBUG_AXUSER_CDMID GENMASK_ULL(43, 36)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

27

#define DEBUG_PAR_PA GENMASK_ULL(47, 12)

drivers/iommu/arm/arm-smmu/arm-smmu.c

1380

addr = (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);

drivers/iommu/arm/arm-smmu/arm-smmu.h

171

#define ARM_SMMU_TTBRn_ASID GENMASK_ULL(63, 48)

drivers/iommu/generic_pt/fmt/amdv1.h

171

return GENMASK_ULL(min(51, isz_lg2 + amdv1pt_num_items_lg2(pts) - 1),

drivers/iommu/generic_pt/fmt/amdv1.h

49

PT_TOP_PHYS_MASK = GENMASK_ULL(51, 12),

drivers/iommu/generic_pt/fmt/amdv1.h

56

AMDV1PT_FMT_NEXT_LEVEL = GENMASK_ULL(11, 9),

drivers/iommu/generic_pt/fmt/amdv1.h

57

AMDV1PT_FMT_OA = GENMASK_ULL(51, 12),

drivers/iommu/generic_pt/fmt/riscv.h

48

PT_TOP_PHYS_MASK = GENMASK_ULL(55, 12),

drivers/iommu/generic_pt/fmt/riscv.h

64

RISCVPT_PPN64 = GENMASK_ULL(53, 10),

drivers/iommu/generic_pt/fmt/riscv.h

65

RISCVPT_PPN64_64K = GENMASK_ULL(53, 14),

drivers/iommu/generic_pt/fmt/riscv.h

66

RISCVPT_PBMT = GENMASK_ULL(62, 61),

drivers/iommu/generic_pt/fmt/vtdss.h

40

PT_TOP_PHYS_MASK = GENMASK_ULL(63, 12),

drivers/iommu/generic_pt/fmt/vtdss.h

50

VTDSS_FMT_OA = GENMASK_ULL(51, 12),

drivers/iommu/generic_pt/fmt/x86_64.h

57

PT_TOP_PHYS_MASK = GENMASK_ULL(51, 12),

drivers/iommu/generic_pt/fmt/x86_64.h

67

X86_64_FMT_OA = GENMASK_ULL(51, 12),

drivers/iommu/intel/debugfs.c

420

pgtt = (u16)(pasid_tbl_entry->val[0] & GENMASK_ULL(8, 6)) >> 6;

drivers/iommu/intel/debugfs.c

421

agaw = (u8)(pasid_tbl_entry->val[0] & GENMASK_ULL(4, 2)) >> 2;

drivers/iommu/intel/debugfs.c

436

u8 tt = (u8)(context->lo & GENMASK_ULL(3, 2)) >> 2;

drivers/iommu/intel/dmar.c

1385

type = desc->qw0 & GENMASK_ULL(3, 0);

drivers/iommu/intel/iommu.h

1135

desc->qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,

drivers/iommu/intel/iommu.h

1379

FIELD_GET(GENMASK_ULL(31, 16), dw0),

drivers/iommu/intel/iommu.h

1380

FIELD_GET(GENMASK_ULL(63, 12), dw1),

drivers/iommu/intel/iommu.h

1386

FIELD_GET(GENMASK_ULL(51, 32), dw0),

drivers/iommu/intel/iommu.h

1387

FIELD_GET(GENMASK_ULL(11, 3), dw1));

drivers/iommu/intel/iommu.h

145

#define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg)

drivers/iommu/intel/iommu.h

146

#define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg)

drivers/iommu/intel/iommu.h

147

#define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg)

drivers/iommu/intel/iommu.h

915

val = READ_ONCE(context->lo) & GENMASK_ULL(63, 1);

drivers/iommu/intel/pasid.h

132

pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);

drivers/iommu/intel/pasid.h

141

return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));

drivers/iommu/intel/pasid.h

161

pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);

drivers/iommu/intel/pasid.h

171

pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);

drivers/iommu/intel/pasid.h

290

pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);

drivers/iommu/io-pgtable-arm.c

74

#define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)

drivers/iommu/io-pgtable-dart.c

46

#define APPLE_DART_PTE_SUBPAGE_START GENMASK_ULL(63, 52)

drivers/iommu/io-pgtable-dart.c

47

#define APPLE_DART_PTE_SUBPAGE_END GENMASK_ULL(51, 40)

drivers/iommu/io-pgtable-dart.c

49

#define APPLE_DART1_PADDR_MASK GENMASK_ULL(35, 12)

drivers/iommu/io-pgtable-dart.c

50

#define APPLE_DART2_PADDR_MASK GENMASK_ULL(37, 10)

drivers/iommu/riscv/iommu-bits.h

198

#define RISCV_IOMMU_IOCOUNTOVF_HPM GENMASK_ULL(31, 1)

drivers/iommu/riscv/iommu-bits.h

207

#define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0)

drivers/iommu/riscv/iommu-bits.h

217

#define RISCV_IOMMU_IOHPMEVT_EVENTID GENMASK_ULL(14, 0)

drivers/iommu/riscv/iommu-bits.h

219

#define RISCV_IOMMU_IOHPMEVT_PID_PSCID GENMASK_ULL(35, 16)

drivers/iommu/riscv/iommu-bits.h

220

#define RISCV_IOMMU_IOHPMEVT_DID_GSCID GENMASK_ULL(59, 36)

drivers/iommu/riscv/iommu-bits.h

258

#define RISCV_IOMMU_TR_REQ_IOVA_VPN GENMASK_ULL(63, 12)

drivers/iommu/riscv/iommu-bits.h

266

#define RISCV_IOMMU_TR_REQ_CTL_PID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

268

#define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40)

drivers/iommu/riscv/iommu-bits.h

27

#define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)

drivers/iommu/riscv/iommu-bits.h

273

#define RISCV_IOMMU_TR_RESPONSE_PBMT GENMASK_ULL(8, 7)

drivers/iommu/riscv/iommu-bits.h

279

#define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0)

drivers/iommu/riscv/iommu-bits.h

28

#define RISCV_IOMMU_QUEUE_LOG2SZ_FIELD GENMASK_ULL(4, 0)

drivers/iommu/riscv/iommu-bits.h

280

#define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4)

drivers/iommu/riscv/iommu-bits.h

281

#define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8)

drivers/iommu/riscv/iommu-bits.h

282

#define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12)

drivers/iommu/riscv/iommu-bits.h

288

#define RISCV_IOMMU_MSI_CFG_TBL_ADDR GENMASK_ULL(55, 2)

drivers/iommu/riscv/iommu-bits.h

29

#define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0)

drivers/iommu/riscv/iommu-bits.h

291

#define RISCV_IOMMU_MSI_CFG_TBL_DATA GENMASK_ULL(31, 0)

drivers/iommu/riscv/iommu-bits.h

353

#define RISCV_IOMMU_DC_IOHGATP_GSCID GENMASK_ULL(59, 44)

drivers/iommu/riscv/iommu-bits.h

37

#define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0)

drivers/iommu/riscv/iommu-bits.h

373

#define RISCV_IOMMU_DC_TA_PSCID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

38

#define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60)

drivers/iommu/riscv/iommu-bits.h

414

#define RISCV_IOMMU_DC_MSI_ADDR_MASK GENMASK_ULL(51, 0)

drivers/iommu/riscv/iommu-bits.h

417

#define RISCV_IOMMU_DC_MSI_PATTERN GENMASK_ULL(51, 0)

drivers/iommu/riscv/iommu-bits.h

42

#define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0)

drivers/iommu/riscv/iommu-bits.h

436

#define RISCV_IOMMU_PC_TA_PSCID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

465

#define RISCV_IOMMU_CMD0_OPCODE GENMASK_ULL(6, 0)

drivers/iommu/riscv/iommu-bits.h

466

#define RISCV_IOMMU_CMD0_FUNC GENMASK_ULL(9, 7)

drivers/iommu/riscv/iommu-bits.h

474

#define RISCV_IOMMU_CMD0_IOTINVAL_PSCID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

477

#define RISCV_IOMMU_CMD0_IOTINVAL_GSCID GENMASK_ULL(59, 44)

drivers/iommu/riscv/iommu-bits.h

481

#define RISCV_IOMMU_CMD1_IOTINVAL_ADDR GENMASK_ULL(61, 10)

drivers/iommu/riscv/iommu-bits.h

491

#define RISCV_IOMMU_CMD0_IOFENCE_DATA GENMASK_ULL(63, 32)

drivers/iommu/riscv/iommu-bits.h

499

#define RISCV_IOMMU_CMD0_IODIR_PID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

501

#define RISCV_IOMMU_CMD0_IODIR_DID GENMASK_ULL(63, 40)

drivers/iommu/riscv/iommu-bits.h

509

#define RISCV_IOMMU_CMD0_ATS_PID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

512

#define RISCV_IOMMU_CMD0_ATS_RID GENMASK_ULL(55, 40)

drivers/iommu/riscv/iommu-bits.h

513

#define RISCV_IOMMU_CMD0_ATS_DSEG GENMASK_ULL(63, 56)

drivers/iommu/riscv/iommu-bits.h

520

#define RISCV_IOMMU_CMD1_ATS_INVAL_UADDR GENMASK_ULL(63, 12)

drivers/iommu/riscv/iommu-bits.h

524

#define RISCV_IOMMU_CMD1_ATS_PRGR_PRG_INDEX GENMASK_ULL(40, 32)

drivers/iommu/riscv/iommu-bits.h

526

#define RISCV_IOMMU_CMD1_ATS_PRGR_RESP_CODE GENMASK_ULL(47, 44)

drivers/iommu/riscv/iommu-bits.h

527

#define RISCV_IOMMU_CMD1_ATS_PRGR_DST_ID GENMASK_ULL(63, 48)

drivers/iommu/riscv/iommu-bits.h

551

#define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0)

drivers/iommu/riscv/iommu-bits.h

552

#define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

555

#define RISCV_IOMMU_FQ_HDR_TTYP GENMASK_ULL(39, 34)

drivers/iommu/riscv/iommu-bits.h

556

#define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40)

drivers/iommu/riscv/iommu-bits.h

59

#define RISCV_IOMMU_CAPABILITIES_IGS GENMASK_ULL(29, 28)

drivers/iommu/riscv/iommu-bits.h

62

#define RISCV_IOMMU_CAPABILITIES_PAS GENMASK_ULL(37, 32)

drivers/iommu/riscv/iommu-bits.h

667

#define RISCV_IOMMU_PQ_HDR_PID GENMASK_ULL(31, 12)

drivers/iommu/riscv/iommu-bits.h

671

#define RISCV_IOMMU_PQ_HDR_DID GENMASK_ULL(63, 40)

drivers/iommu/riscv/iommu-bits.h

677

#define RISCV_IOMMU_PQ_PAYLOAD_RWL_MASK GENMASK_ULL(2, 0)

drivers/iommu/riscv/iommu-bits.h

678

#define RISCV_IOMMU_PQ_PAYLOAD_PRGI GENMASK_ULL(11, 3) /* Page Request Group Index */

drivers/iommu/riscv/iommu-bits.h

679

#define RISCV_IOMMU_PQ_PAYLOAD_ADDR GENMASK_ULL(63, 12)

drivers/iommu/riscv/iommu-bits.h

704

#define RISCV_IOMMU_MSIPTE_M GENMASK_ULL(2, 1)

drivers/iommu/riscv/iommu-bits.h

705

#define RISCV_IOMMU_MSIPTE_MRIF_ADDR GENMASK_ULL(53, 7) /* When M == 1 (MRIF mode) */

drivers/iommu/riscv/iommu-bits.h

710

#define RISCV_IOMMU_MSIPTE_MRIF_NID GENMASK_ULL(9, 0)

drivers/iommu/riscv/iommu-bits.h

91

#define RISCV_IOMMU_DDTP_IOMMU_MODE GENMASK_ULL(3, 0)

drivers/iommu/rockchip-iommu.c

202

#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)

drivers/iommu/rockchip-iommu.c

207

#define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32)

drivers/iommu/rockchip-iommu.c

208

#define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36)

drivers/iommu/vsi-iommu.c

146

#define VSI_MASTER_TLB_MASK GENMASK_ULL(31, 10)

drivers/iommu/vsi-iommu.c

95

#define VSI_PAGE_DESC_HI_MASK GENMASK_ULL(39, 32)

drivers/irqchip/irq-alpine-msi.c

217

priv->addr = res.start & GENMASK_ULL(63,20);

drivers/irqchip/irq-gic-v3-its.c

2326

gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);

drivers/irqchip/irq-gic-v3-its.c

2772

addr = baser & GENMASK_ULL(47, 12);

drivers/irqchip/irq-gic-v3-its.c

3068

addr = val & GENMASK_ULL(51, 12);

drivers/irqchip/irq-gic-v3-its.c

3171

paddr &= GENMASK_ULL(51, 12);

drivers/irqchip/irq-gic-v3-its.c

3176

paddr &= GENMASK_ULL(51, 16);

drivers/irqchip/irq-gic-v3-its.c

4015

GENMASK_ULL(51, 12);

drivers/irqchip/irq-gic-v3-its.c

4024

GENMASK_ULL(51, 16);

drivers/irqchip/irq-gic-v3-its.c

416

if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))

drivers/irqchip/irq-gic-v3-its.c

552

u64 mask = GENMASK_ULL(h, l);

drivers/irqchip/irq-gic-v3.c

1813

#define T241_CHIPN_MASK GENMASK_ULL(45, 44)

drivers/mailbox/qcom-cpucp-mbox.c

26

#define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0)

drivers/media/i2c/alvium-csi2.h

205

#define BCRM_DEVICE_FW_MAJOR_MASK GENMASK_ULL(15, 8)

drivers/media/i2c/alvium-csi2.h

207

#define BCRM_DEVICE_FW_MINOR_MASK GENMASK_ULL(31, 16)

drivers/media/i2c/alvium-csi2.h

209

#define BCRM_DEVICE_FW_PATCH_MASK GENMASK_ULL(63, 32)

drivers/media/i2c/alvium-csi2.h

211

#define BCRM_DEVICE_FW_SPEC_MASK GENMASK_ULL(7, 0)

drivers/media/pci/intel/ipu6/ipu6-cpd.c

47

#define PKG_DIR_SIZE_MASK GENMASK_ULL(23, 0)

drivers/media/pci/intel/ipu6/ipu6-cpd.c

48

#define PKG_DIR_VERSION_MASK GENMASK_ULL(47, 32)

drivers/media/pci/intel/ipu6/ipu6-cpd.c

49

#define PKG_DIR_TYPE_MASK GENMASK_ULL(54, 48)

drivers/media/platform/rockchip/rkvdec/rkvdec-bitwriter.h

28

u64 mask = GENMASK_ULL(bit + field.len - 1, bit);

drivers/media/test-drivers/vidtv/vidtv_pes.c

96

mask1 = GENMASK_ULL(32, 30);

drivers/media/test-drivers/vidtv/vidtv_pes.c

97

mask2 = GENMASK_ULL(29, 15);

drivers/media/test-drivers/vidtv/vidtv_pes.c

98

mask3 = GENMASK_ULL(14, 0);

drivers/memory/dfl-emif.c

27

#define EMIF_CTRL_CLEAR_EN_MSK GENMASK_ULL(7, 0)

drivers/memory/dfl-emif.c

42

#define EMIF_CAPABILITY_CHN_MSK_V0 GENMASK_ULL(3, 0)

drivers/memory/dfl-emif.c

43

#define EMIF_CAPABILITY_CHN_MSK GENMASK_ULL(7, 0)

drivers/mfd/macsmc.c

38

#define SMC_DATA GENMASK_ULL(63, 32)

drivers/mfd/macsmc.c

39

#define SMC_WSIZE GENMASK_ULL(31, 24)

drivers/mfd/macsmc.c

40

#define SMC_SIZE GENMASK_ULL(23, 16)

drivers/mfd/macsmc.c

41

#define SMC_ID GENMASK_ULL(15, 12)

drivers/mfd/macsmc.c

42

#define SMC_MSG GENMASK_ULL(7, 0)

drivers/misc/fastrpc.c

322

return iova & GENMASK_ULL(cctx->soc_data->sid_pos - 1, 0);

drivers/misc/mrvl_cn10k_dpi.c

101

#define DPI_MBOX_NPA_PFFUNC(msg) FIELD_GET(GENMASK_ULL(15, 0), msg)

drivers/misc/mrvl_cn10k_dpi.c

102

#define DPI_MBOX_WQES_COMPL(msg) FIELD_GET(GENMASK_ULL(16, 16), msg)

drivers/misc/mrvl_cn10k_dpi.c

103

#define DPI_MBOX_WQES_OFFSET(msg) FIELD_GET(GENMASK_ULL(23, 17), msg)

drivers/misc/mrvl_cn10k_dpi.c

40

#define DPI_DMA_IDS_DMA_NPA_PF_FUNC(x) FIELD_PREP(GENMASK_ULL(31, 16), x)

drivers/misc/mrvl_cn10k_dpi.c

41

#define DPI_DMA_IDS_INST_STRM(x) FIELD_PREP(GENMASK_ULL(47, 40), x)

drivers/misc/mrvl_cn10k_dpi.c

42

#define DPI_DMA_IDS_DMA_STRM(x) FIELD_PREP(GENMASK_ULL(39, 32), x)

drivers/misc/mrvl_cn10k_dpi.c

43

#define DPI_DMA_ENG_EN_MOLR(x) FIELD_PREP(GENMASK_ULL(41, 32), x)

drivers/misc/mrvl_cn10k_dpi.c

478

dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));

drivers/misc/mrvl_cn10k_dpi.c

50

#define DPI_DMA_CONTROL_DMA_ENB GENMASK_ULL(53, 48)

drivers/misc/mrvl_cn10k_dpi.c

94

#define DPI_MBOX_VFID(msg) FIELD_GET(GENMASK_ULL(7, 0), msg)

drivers/misc/mrvl_cn10k_dpi.c

95

#define DPI_MBOX_CMD(msg) FIELD_GET(GENMASK_ULL(11, 8), msg)

drivers/misc/mrvl_cn10k_dpi.c

96

#define DPI_MBOX_CBUF_SIZE(msg) FIELD_GET(GENMASK_ULL(27, 12), msg)

drivers/misc/mrvl_cn10k_dpi.c

97

#define DPI_MBOX_CBUF_AURA(msg) FIELD_GET(GENMASK_ULL(47, 28), msg)

drivers/misc/mrvl_cn10k_dpi.c

98

#define DPI_MBOX_SSO_PFFUNC(msg) FIELD_GET(GENMASK_ULL(63, 48), msg)

drivers/mmc/host/cavium.c

180

u64 bus_id_mask = GENMASK_ULL(61, 60);

drivers/mmc/host/cavium.c

193

return FIELD_GET(GENMASK_ULL(61, 60), reg);

drivers/mmc/host/cavium.h

121

#define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)

drivers/mmc/host/cavium.h

122

#define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)

drivers/mmc/host/cavium.h

130

#define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)

drivers/mmc/host/cavium.h

133

#define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)

drivers/mmc/host/cavium.h

136

#define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)

drivers/mmc/host/cavium.h

137

#define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)

drivers/mmc/host/cavium.h

138

#define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)

drivers/mmc/host/cavium.h

139

#define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)

drivers/mmc/host/cavium.h

140

#define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)

drivers/mmc/host/cavium.h

143

#define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)

drivers/mmc/host/cavium.h

147

#define MIO_EMM_DMA_THRES GENMASK_ULL(56, 51)

drivers/mmc/host/cavium.h

151

#define MIO_EMM_DMA_BLOCK_CNT GENMASK_ULL(47, 32)

drivers/mmc/host/cavium.h

152

#define MIO_EMM_DMA_CARD_ADDR GENMASK_ULL(31, 0)

drivers/mmc/host/cavium.h

161

#define MIO_EMM_DMA_CFG_SIZE GENMASK_ULL(55, 36)

drivers/mmc/host/cavium.h

162

#define MIO_EMM_DMA_CFG_ADR GENMASK_ULL(35, 0)

drivers/mmc/host/cavium.h

172

#define MIO_EMM_RSP_STS_BUS_ID GENMASK_ULL(61, 60)

drivers/mmc/host/cavium.h

190

#define MIO_EMM_RSP_STS_RSP_TYPE GENMASK_ULL(11, 9)

drivers/mmc/host/cavium.h

191

#define MIO_EMM_RSP_STS_CMD_TYPE GENMASK_ULL(8, 7)

drivers/mmc/host/cavium.h

192

#define MIO_EMM_RSP_STS_CMD_IDX GENMASK_ULL(6, 1)

drivers/mmc/host/cavium.h

195

#define MIO_EMM_SAMPLE_CMD_CNT GENMASK_ULL(25, 16)

drivers/mmc/host/cavium.h

196

#define MIO_EMM_SAMPLE_DAT_CNT GENMASK_ULL(9, 0)

drivers/mmc/host/cavium.h

198

#define MIO_EMM_SWITCH_BUS_ID GENMASK_ULL(61, 60)

drivers/mmc/host/cavium.h

204

#define MIO_EMM_SWITCH_BUS_WIDTH GENMASK_ULL(42, 40)

drivers/mmc/host/cavium.h

205

#define MIO_EMM_SWITCH_POWER_CLASS GENMASK_ULL(35, 32)

drivers/mmc/host/cavium.h

206

#define MIO_EMM_SWITCH_CLK_HI GENMASK_ULL(31, 16)

drivers/mmc/host/cavium.h

207

#define MIO_EMM_SWITCH_CLK_LO GENMASK_ULL(15, 0)

drivers/mmc/host/loongson2-mmc.c

179

#define LOONGSON2_MMC_DMA_CONFIG_MASK GENMASK_ULL(4, 0) /* DMA controller config bits mask */

drivers/mmc/host/renesas_sdhi_internal_dmac.c

47

#define RST_RESERVED_BITS GENMASK_ULL(31, 0)

drivers/mmc/host/renesas_sdhi_internal_dmac.c

50

#define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)

drivers/mmc/host/renesas_sdhi_internal_dmac.c

56

#define INFO2_MASK_CLEAR GENMASK_ULL(31, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

300

#define GCMD_LAY_CS GENMASK_ULL(11, 8)

drivers/mtd/nand/raw/cadence-nand-controller.c

307

#define GCMD_LAY_INSTR GENMASK_ULL(5, 0)

drivers/mtd/nand/raw/cadence-nand-controller.c

317

#define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

320

#define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

322

#define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11)

drivers/mtd/nand/raw/cadence-nand-controller.c

334

#define GCMD_SECT_SIZE GENMASK_ULL(31, 16)

drivers/mtd/nand/raw/cadence-nand-controller.c

336

#define GCMD_SECT_CNT GENMASK_ULL(39, 32)

drivers/mtd/nand/raw/cadence-nand-controller.c

338

#define GCMD_LAST_SIZE GENMASK_ULL(55, 40)

drivers/net/can/flexcan/flexcan-core.c

1416

priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,

drivers/net/dsa/b53/b53_regs.h

334

#define ARLTBL_DATA_PORT_ID_MASK_25 GENMASK_ULL(53, 48)

drivers/net/dsa/b53/b53_regs.h

383

#define ARL_SRCH_RSLT_PORT_ID_MASK_25 GENMASK_ULL(52, 48)

drivers/net/dsa/b53/b53_regs.h

385

#define ARL_SRCH_RSLT_VID_MASK_25 GENMASK_ULL(60, 53)

drivers/net/dsa/sja1105/sja1105_main.c

1656

l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);

drivers/net/dsa/sja1105/sja1105_main.c

1747

l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);

drivers/net/dsa/sja1105/sja1105_main.c

2212

cbs->credit_lo &= GENMASK_ULL(31, 0);

drivers/net/dsa/sja1105/sja1105_main.c

2213

cbs->send_slope &= GENMASK_ULL(31, 0);

drivers/net/dsa/sja1105/sja1105_ptp.c

623

WARN_ON(abs(clkrate) >= GENMASK_ULL(31, 0));

drivers/net/dsa/sja1105/sja1105_spi.c

341

rc = sja1105_inhibit_tx(priv, GENMASK_ULL(ds->num_ports - 1, 0), true);

drivers/net/dsa/sja1105/sja1105_tas.c

10

#define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0)

drivers/net/dsa/yt921x.h

449

#define YT921X_VLAN_CTRLab_FID_M GENMASK_ULL(34, 23)

drivers/net/dsa/yt921x.h

490

#define YT921X_ACL_ACTbc_SVID_M GENMASK_ULL(34, 23)

drivers/net/dsa/yt921x.h

753

#define YT921X_METER_CTRLbc_CBS_M GENMASK_ULL(35, 20)

drivers/net/dsa/yt921x.h

757

#define YT921X_METER_CTRLab_EBS_M GENMASK_ULL(33, 18)

drivers/net/ethernet/alibaba/eea/eea_desc.h

11

#define EEA_DESC_TS_MASK GENMASK_ULL(47, 0)

drivers/net/ethernet/alibaba/eea/eea_desc.h

61

#define EEA_RX_CDESC_HDR_LEN_MASK GENMASK_ULL(9, 0)

drivers/net/ethernet/amazon/ena/ena_com.c

81

if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {

drivers/net/ethernet/amazon/ena/ena_eth_com.c

521

GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);

drivers/net/ethernet/amazon/ena/ena_eth_com.c

640

((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);

drivers/net/ethernet/amazon/ena/ena_netdev.c

3696

netdev->features & GENMASK_ULL(31, 0);

drivers/net/ethernet/amazon/ena/ena_netdev.c

3698

(netdev->features & GENMASK_ULL(63, 32)) >> 32;

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

62

#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))

drivers/net/ethernet/broadcom/asp2/bcmasp.h

185

#define DESC_ADDR(x) ((x) & GENMASK_ULL(39, 0))

drivers/net/ethernet/broadcom/asp2/bcmasp.h

186

#define DESC_FLAGS(x) ((x) & GENMASK_ULL(63, 40))

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

21

#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_MASK GENMASK_ULL(51, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

22

#define CMDQ_CTXT_EQ_ID_MASK GENMASK_ULL(60, 53)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

27

#define CMDQ_CTXT_WQ_BLOCK_PFN_MASK GENMASK_ULL(51, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

28

#define CMDQ_CTXT_CI_MASK GENMASK_ULL(63, 52)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

13

#define MBOX_MSG_HEADER_SRC_GLB_FUNC_IDX_MASK GENMASK_ULL(12, 0)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

16

#define MBOX_MSG_HEADER_AEQ_ID_MASK GENMASK_ULL(17, 16)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

17

#define MBOX_MSG_HEADER_MSG_ID_MASK GENMASK_ULL(21, 18)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

18

#define MBOX_MSG_HEADER_CMD_MASK GENMASK_ULL(31, 22)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

19

#define MBOX_MSG_HEADER_MSG_LEN_MASK GENMASK_ULL(42, 32)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

20

#define MBOX_MSG_HEADER_MODULE_MASK GENMASK_ULL(47, 43)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

21

#define MBOX_MSG_HEADER_SEG_LEN_MASK GENMASK_ULL(53, 48)

drivers/net/ethernet/huawei/hinic3/hinic3_mbox.h

24

#define MBOX_MSG_HEADER_SEQID_MASK GENMASK_ULL(61, 56)

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

3265

#define I40E_USERDEF_FLEX_WORD GENMASK_ULL(15, 0)

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

3266

#define I40E_USERDEF_FLEX_OFFSET GENMASK_ULL(31, 16)

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

3267

#define I40E_USERDEF_FLEX_FILTER GENMASK_ULL(31, 0)

drivers/net/ethernet/intel/iavf/iavf_type.h

206

#define IAVF_RXD_LEGACY_RSS_M GENMASK_ULL(63, 32)

drivers/net/ethernet/intel/iavf/iavf_type.h

208

#define IAVF_RXD_LEGACY_L2TAG1_M GENMASK_ULL(33, 16)

drivers/net/ethernet/intel/iavf/iavf_type.h

210

#define IAVF_RXD_FLEX_PTYPE_M GENMASK_ULL(25, 16)

drivers/net/ethernet/intel/iavf/iavf_type.h

212

#define IAVF_RXD_FLEX_PKT_LEN_M GENMASK_ULL(45, 32)

drivers/net/ethernet/intel/iavf/iavf_type.h

240

#define IAVF_RXD_LEGACY_FLTSTAT_M GENMASK_ULL(13, 12)

drivers/net/ethernet/intel/iavf/iavf_type.h

242

#define IAVF_RXD_LEGACY_PTYPE_M GENMASK_ULL(37, 30)

drivers/net/ethernet/intel/iavf/iavf_type.h

244

#define IAVF_RXD_LEGACY_LENGTH_M GENMASK_ULL(51, 38)

drivers/net/ethernet/intel/iavf/iavf_type.h

272

#define IAVF_RXD_FLEX_L2TAG1_M GENMASK_ULL(31, 16)

drivers/net/ethernet/intel/iavf/iavf_type.h

274

#define IAVF_RXD_FLEX_RSS_HASH_M GENMASK_ULL(63, 32)

drivers/net/ethernet/intel/iavf/iavf_type.h

280

#define IAVF_RXD_LEGACY_L2TAG2_M GENMASK_ULL(63, 48)

drivers/net/ethernet/intel/iavf/iavf_type.h

282

#define IAVF_RXD_FLEX_L2TAG2_2_M GENMASK_ULL(63, 48)

drivers/net/ethernet/intel/iavf/iavf_type.h

288

#define IAVF_RXD_FLEX_QW3_TSTAMP_HIGH_M GENMASK_ULL(63, 32)

drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c

499

#define ICE_USERDEF_FLEX_WORD_M GENMASK_ULL(15, 0)

drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c

501

#define ICE_USERDEF_FLEX_OFFS_M GENMASK_ULL(31, ICE_USERDEF_FLEX_OFFS_S)

drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c

502

#define ICE_USERDEF_FLEX_FLTR_M GENMASK_ULL(31, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

1184

#define ICE_BST_ALU_OPC GENMASK_ULL(5, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

1185

#define ICE_BST_ALU_SS GENMASK_ULL(13, 6)

drivers/net/ethernet/intel/ice/ice_parser.c

1186

#define ICE_BST_ALU_SL GENMASK_ULL(18, 14)

drivers/net/ethernet/intel/ice/ice_parser.c

1188

#define ICE_BST_ALU_SXK GENMASK_ULL(23, 20)

drivers/net/ethernet/intel/ice/ice_parser.c

1189

#define ICE_BST_ALU_SRID GENMASK_ULL(30, 24)

drivers/net/ethernet/intel/ice/ice_parser.c

1190

#define ICE_BST_ALU_DRID GENMASK_ULL(37, 31)

drivers/net/ethernet/intel/ice/ice_parser.c

1193

#define ICE_BST_ALU_POO GENMASK_ULL(41, 40)

drivers/net/ethernet/intel/ice/ice_parser.c

1194

#define ICE_BST_ALU_PO GENMASK_ULL(49, 42)

drivers/net/ethernet/intel/ice/ice_parser.c

1196

#define ICE_BST_ALU_BA GENMASK_ULL(57 - ICE_BST_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1198

#define ICE_BST_ALU_IMM GENMASK_ULL(73 - ICE_BST_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1201

#define ICE_BST_ALU_DS GENMASK_ULL(80 - ICE_BST_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1203

#define ICE_BST_ALU_DL GENMASK_ULL(86 - ICE_BST_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1206

#define ICE_BST_ALU_FSI GENMASK_ULL(95 - ICE_BST_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1248

#define ICE_BST_PGKB_F0_IDX GENMASK_ULL(6, 1)

drivers/net/ethernet/intel/ice/ice_parser.c

1250

#define ICE_BST_PGKB_F1_IDX GENMASK_ULL(13, 8)

drivers/net/ethernet/intel/ice/ice_parser.c

1252

#define ICE_BST_PGKB_F2_IDX GENMASK_ULL(20, 15)

drivers/net/ethernet/intel/ice/ice_parser.c

1254

#define ICE_BST_PGKB_F3_IDX GENMASK_ULL(27, 22)

drivers/net/ethernet/intel/ice/ice_parser.c

1255

#define ICE_BST_PGKB_AR_IDX GENMASK_ULL(34, 28)

drivers/net/ethernet/intel/ice/ice_parser.c

1770

#define ICE_XLT_KB_X1AS GENMASK_ULL(34 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1772

#define ICE_XLT_KB_X2AS GENMASK_ULL(37 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1774

#define ICE_XLT_KB_FL00 GENMASK_ULL(46 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1776

#define ICE_XLT_KB_FL01 GENMASK_ULL(55 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1778

#define ICE_XLT_KB_FL02 GENMASK_ULL(64 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1780

#define ICE_XLT_KB_FL03 GENMASK_ULL(73 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1782

#define ICE_XLT_KB_FL04 GENMASK_ULL(82 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1784

#define ICE_XLT_KB_FL05 GENMASK_ULL(91 - ICE_XLT_KB_X1AS_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1789

#define ICE_XLT_KB_FL06 GENMASK_ULL(100 - ICE_XLT_KB_FL06_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1791

#define ICE_XLT_KB_FL07 GENMASK_ULL(109 - ICE_XLT_KB_FL06_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1793

#define ICE_XLT_KB_FL08 GENMASK_ULL(118 - ICE_XLT_KB_FL06_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1795

#define ICE_XLT_KB_FL09 GENMASK_ULL(127 - ICE_XLT_KB_FL06_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1797

#define ICE_XLT_KB_FL10 GENMASK_ULL(136 - ICE_XLT_KB_FL06_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1799

#define ICE_XLT_KB_FL11 GENMASK_ULL(145 - ICE_XLT_KB_FL06_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1804

#define ICE_XLT_KB_FL12 GENMASK_ULL(154 - ICE_XLT_KB_FL12_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1806

#define ICE_XLT_KB_FL13 GENMASK_ULL(163 - ICE_XLT_KB_FL12_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1808

#define ICE_XLT_KB_FL14 GENMASK_ULL(181 - ICE_XLT_KB_FL12_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1810

#define ICE_XLT_KB_X1MS GENMASK_ULL(186 - ICE_XLT_KB_FL12_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1812

#define ICE_XLT_KB_X2MS GENMASK_ULL(191 - ICE_XLT_KB_FL12_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

1959

#define ICE_XLT_KB_MASK GENMASK_ULL(5, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

275

#define ICE_IM_PGKB_F0_IDX GENMASK_ULL(6, 1)

drivers/net/ethernet/intel/ice/ice_parser.c

277

#define ICE_IM_PGKB_F1_IDX GENMASK_ULL(13, 8)

drivers/net/ethernet/intel/ice/ice_parser.c

279

#define ICE_IM_PGKB_F2_IDX GENMASK_ULL(20, 15)

drivers/net/ethernet/intel/ice/ice_parser.c

281

#define ICE_IM_PGKB_F3_IDX GENMASK_ULL(27, 22)

drivers/net/ethernet/intel/ice/ice_parser.c

282

#define ICE_IM_PGKB_AR_IDX GENMASK_ULL(34, 28)

drivers/net/ethernet/intel/ice/ice_parser.c

302

#define ICE_IM_ALU_OPC GENMASK_ULL(5, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

303

#define ICE_IM_ALU_SS GENMASK_ULL(13, 6)

drivers/net/ethernet/intel/ice/ice_parser.c

304

#define ICE_IM_ALU_SL GENMASK_ULL(18, 14)

drivers/net/ethernet/intel/ice/ice_parser.c

306

#define ICE_IM_ALU_SXK GENMASK_ULL(23, 20)

drivers/net/ethernet/intel/ice/ice_parser.c

307

#define ICE_IM_ALU_SRID GENMASK_ULL(30, 24)

drivers/net/ethernet/intel/ice/ice_parser.c

308

#define ICE_IM_ALU_DRID GENMASK_ULL(37, 31)

drivers/net/ethernet/intel/ice/ice_parser.c

311

#define ICE_IM_ALU_POO GENMASK_ULL(41, 40)

drivers/net/ethernet/intel/ice/ice_parser.c

312

#define ICE_IM_ALU_PO GENMASK_ULL(49, 42)

drivers/net/ethernet/intel/ice/ice_parser.c

314

#define ICE_IM_ALU_BA GENMASK_ULL(57 - ICE_IM_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

316

#define ICE_IM_ALU_IMM GENMASK_ULL(73 - ICE_IM_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

319

#define ICE_IM_ALU_DS GENMASK_ULL(80 - ICE_IM_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

321

#define ICE_IM_ALU_DL GENMASK_ULL(86 - ICE_IM_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

324

#define ICE_IM_ALU_FSI GENMASK_ULL(95 - ICE_IM_ALU_BA_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

489

#define ICE_MI_TSR GENMASK_ULL(7, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

490

#define ICE_MI_HO GENMASK_ULL(16, 8)

drivers/net/ethernet/intel/ice/ice_parser.c

491

#define ICE_MI_PC GENMASK_ULL(24, 17)

drivers/net/ethernet/intel/ice/ice_parser.c

492

#define ICE_MI_PGRN GENMASK_ULL(35, 25)

drivers/net/ethernet/intel/ice/ice_parser.c

493

#define ICE_MI_CD GENMASK_ULL(38, 36)

drivers/net/ethernet/intel/ice/ice_parser.c

495

#define ICE_MI_GADM GENMASK_ULL(44, 40)

drivers/net/ethernet/intel/ice/ice_parser.c

496

#define ICE_MI_GADS GENMASK_ULL(48, 45)

drivers/net/ethernet/intel/ice/ice_parser.c

497

#define ICE_MI_GADL GENMASK_ULL(53, 49)

drivers/net/ethernet/intel/ice/ice_parser.c

498

#define ICE_MI_GAI GENMASK_ULL(59, 56)

drivers/net/ethernet/intel/ice/ice_parser.c

505

GENMASK_ULL((high) - ICE_MI_GBDM_S, (low) - ICE_MI_GBDM_S)

drivers/net/ethernet/intel/ice/ice_parser.c

523

#define ICE_MI_FLAG GENMASK_ULL(186 - ICE_MI_FLAG_S, \

drivers/net/ethernet/intel/ice/ice_parser.c

703

#define ICE_PGCA_NN GENMASK_ULL(10, 0)

drivers/net/ethernet/intel/ice/ice_parser.c

704

#define ICE_PGCA_NPC GENMASK_ULL(18, 11)

drivers/net/ethernet/intel/ice/ice_parser.c

706

#define ICE_PGCA_PID GENMASK_ULL(30, 23)

drivers/net/ethernet/intel/ice/ice_parser.c

708

#define ICE_PGCA_MID GENMASK_ULL(39, 32)

drivers/net/ethernet/intel/ice/ice_parser.c

711

#define ICE_PGCA_HOI GENMASK_ULL(50, 42)

drivers/net/ethernet/intel/ice/ice_parser.c

732

#define ICE_PGNCK_NID GENMASK_ULL(11, 1)

drivers/net/ethernet/intel/ice/ice_parser.c

738

#define ICE_PGNCK_BI GENMASK_ULL(24, 17)

drivers/net/ethernet/intel/ice/ice_parser.c

739

#define ICE_PGNCK_AR GENMASK_ULL(40, 25)

drivers/net/ethernet/intel/ice/ice_parser.c

764

#define ICE_PGCK_NID GENMASK_ULL(11, 1)

drivers/net/ethernet/intel/ice/ice_parser.c

770

#define ICE_PGCK_BI GENMASK_ULL(24, 17)

drivers/net/ethernet/intel/ice/ice_parser.c

771

#define ICE_PGCK_AR GENMASK_ULL(40, 25)

drivers/net/ethernet/intel/ice/ice_parser.c

775

#define ICE_PGCK_NPK GENMASK_ULL(72 - ICE_PGCK_NPK_S, \

drivers/net/ethernet/intel/ice/ice_ptp.c

339

const u64 mask = GENMASK_ULL(31, 0);

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

629

#define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32)

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

631

#define PHY_40B_HIGH_M GENMASK_ULL(39, 8)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

100

#define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

102

#define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

104

#define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

106

#define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

108

#define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

110

#define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

112

#define IDPF_TXD_QW1_DTYPE_M GENMASK_ULL(3, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

293

#define IDPF_TX_CTX_L2TAG2_M GENMASK_ULL(47, 32)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

295

#define IDPF_TX_CTX_DTYPE_M GENMASK_ULL(3, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

296

#define IDPF_TX_CTX_CMD_M GENMASK_ULL(15, 4)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

297

#define IDPF_TX_CTX_TSYN_REG_M GENMASK_ULL(47, 30)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

298

#define IDPF_TX_CTX_MSS_M GENMASK_ULL(50, 63)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

65

#define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

67

#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

96

#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)

drivers/net/ethernet/intel/idpf/idpf_lan_txrx.h

98

#define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

167

#define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M GENMASK_ULL(51, 38)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

168

#define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M GENMASK_ULL(37, 30)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

169

#define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M GENMASK_ULL(26, 19)

drivers/net/ethernet/intel/idpf/virtchnl2_lan_desc.h

170

#define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M GENMASK_ULL(18, 0)

drivers/net/ethernet/intel/idpf/xdp.h

109

#define IDPF_XDP_RX_LEN GENMASK_ULL(45, 32)

drivers/net/ethernet/intel/idpf/xdp.h

110

#define IDPF_XDP_RX_PT GENMASK_ULL(25, 16)

drivers/net/ethernet/intel/idpf/xdp.h

113

#define IDPF_XDP_RX_BUF GENMASK_ULL(47, 32)

drivers/net/ethernet/intel/idpf/xdp.h

115

#define IDPF_XDP_RX_TS_LOW GENMASK_ULL(31, 24)

drivers/net/ethernet/intel/idpf/xdp.h

118

#define IDPF_XDP_RX_HASH GENMASK_ULL(31, 0)

drivers/net/ethernet/intel/idpf/xdp.h

121

#define IDPF_XDP_RX_TS_HIGH GENMASK_ULL(63, 32)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

33

#define IXGBE_OROM_VER_PATCH_MASK GENMASK_ULL(7, 0)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

34

#define IXGBE_OROM_VER_BUILD_MASK GENMASK_ULL(23, 8)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

35

#define IXGBE_OROM_VER_MASK GENMASK_ULL(31, 24)

drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

82

#define IXGBE_LINK_TOPO_NODE_COUNT_M GENMASK_ULL(9, 0)

drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h

392

#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

102

val & GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

117

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_PKT_CNT(q_no), GENMASK_ULL(35, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

118

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_SLIST_DBELL(q_no), GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

194

reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

231

oq_ctl &= ~GENMASK_ULL(22, 0); //clear the ISIZE and BSIZE (22-0)

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

232

oq_ctl |= (oq->buffer_size & GENMASK_ULL(15, 0)); //populate the BSIZE (15-0)

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

372

octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_DBELL(iq_no), GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

397

octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_SLIST_DBELL(oq_no), GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

97

val = GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

100

val = GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

104

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_CNTS(q_no), val & GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

119

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_PKT_CNT(q_no), GENMASK_ULL(35, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

120

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_DBELL(q_no), GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

197

reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

267

oq_ctl &= ~GENMASK_ULL(22, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

269

oq_ctl |= (oq->buffer_size & GENMASK_ULL(15, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

282

reg_val &= ~GENMASK_ULL(31, 0);

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

415

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no), GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c

440

octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_DBELL(oq_no), GENMASK_ULL(31, 0));

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

1517

args.mode = GENMASK_ULL(41, 0);

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

354

cfg &= ~GENMASK_ULL(2, 1);

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

470

cfg &= ~GENMASK_ULL(2, 1);

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

25

#define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

52

#define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

54

#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

59

#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(55, 32)

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

60

#define CGX_CONST_MAX_LMACS GENMASK_ULL(31, 24)

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

86

#define CGX_PFC_CLASS_MASK GENMASK_ULL(47, 32)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

194

#define EVTREG_ID GENMASK_ULL(8, 3)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

201

#define EVTREG_ERRTYPE GENMASK_ULL(18, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

206

#define RESP_MAJOR_VER GENMASK_ULL(12, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

207

#define RESP_MINOR_VER GENMASK_ULL(16, 13)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

212

#define RESP_MAC_ADDR GENMASK_ULL(56, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

217

#define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

222

#define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

227

#define RESP_FWD_BASE GENMASK_ULL(56, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

228

#define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

252

#define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

253

#define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

254

#define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

255

#define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

256

#define RESP_LINKSTAT_AN GENMASK_ULL(25, 25)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

257

#define RESP_LINKSTAT_FEC GENMASK_ULL(27, 26)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

258

#define RESP_LINKSTAT_PORT GENMASK_ULL(35, 28)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

264

#define CMDREG_ID GENMASK_ULL(7, 2)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

273

#define CMDMTU_SIZE GENMASK_ULL(23, 8)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

278

#define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

280

#define CMDSETFEC GENMASK_ULL(9, 8)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

282

#define CMDMODECHANGE_SPEED GENMASK_ULL(11, 8)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

283

#define CMDMODECHANGE_DUPLEX GENMASK_ULL(12, 12)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

284

#define CMDMODECHANGE_AN GENMASK_ULL(13, 13)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

290

#define CMDMODECHANGE_MODE_BASEIDX GENMASK_ULL(21, 20)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

291

#define CMDMODECHANGE_FLAGS GENMASK_ULL(63, 22)

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

294

#define LINKCFG_TIMEOUT GENMASK_ULL(21, 8)

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

1014

intf_ext_mask = (((u64)kw_type_mask << 16) & GENMASK_ULL(18, 16)) |

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

1274

*hw_prio = (bank_cfg & GENMASK_ULL(30, 24)) >> 24;

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

39

((pcifunc) | FIELD_PREP(GENMASK_ULL(31, 16), id))

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

42

FIELD_GET(GENMASK_ULL(15, 0), rid)

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

45

FIELD_GET(GENMASK_ULL(31, 16), rid)

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

4683

num_subbanks = FIELD_GET(GENMASK_ULL(39, 32), npc_const2);

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

4725

npc_priv->kw = FIELD_GET(GENMASK_ULL(34, 32), cfg);

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

564

entry_mask |= GENMASK_ULL(KPU_CN20K_MAX_CST_ENT - 1, 0);

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

835

hw_prio = cfg & GENMASK_ULL(30, 24);

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

851

hw_prio = cfg & GENMASK_ULL(30, 24);

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c

997

kex_type = (kex_cfg & GENMASK_ULL(34, 32)) >> 32;

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h

24

#define NPC_CN20K_BYTESM GENMASK_ULL(18, 16)

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h

25

#define NPC_CN20K_PARSE_NIBBLE GENMASK_ULL(22, 0)

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h

48

#define NPC_CN20K_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.h

50

#define NPC_CN20K_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

506

mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

510

mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

524

plcy = BIT_ULL(0) | GENMASK_ULL(43, 28);

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

526

plcy = BIT_ULL(0) | GENMASK_ULL(63, 48);

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

637

mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

646

mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

648

mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

651

mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

653

mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

665

mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

667

mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

672

mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

674

mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.c

687

mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));

drivers/net/ethernet/marvell/octeontx2/af/mcs.h

15

#define MCSX_LINK_LMAC_RANGE_MASK GENMASK_ULL(19, 16)

drivers/net/ethernet/marvell/octeontx2/af/mcs.h

16

#define MCSX_LINK_LMAC_BASE_MASK GENMASK_ULL(11, 0)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

436

#define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

442

#define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

445

#define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

446

#define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

447

#define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

450

#define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

454

#define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

456

#define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

458

#define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

460

#define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

462

#define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

464

#define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

466

#define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

468

#define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

470

#define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

472

#define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

493

#define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

494

#define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

495

#define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

497

#define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

498

#define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

499

#define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

502

#define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

503

#define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

504

#define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

505

#define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

506

#define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

507

#define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

508

#define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40)

drivers/net/ethernet/marvell/octeontx2/af/npc.h

509

#define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32)

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

39

#define PTP_CLOCK_CFG_EXT_CLK_IN_MASK GENMASK_ULL(7, 2)

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

42

#define PTP_CLOCK_CFG_TSTMP_IN_MASK GENMASK_ULL(15, 10)

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

43

#define PTP_CLOCK_CFG_ATOMIC_OP_MASK GENMASK_ULL(28, 26)

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

274

cfg &= ~GENMASK_ULL(15, 0);

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

276

cfg &= ~GENMASK_ULL(31, 16);

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

285

cfg &= ~GENMASK_ULL(15, 0);

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

287

cfg &= ~GENMASK_ULL(31, 16);

drivers/net/ethernet/marvell/octeontx2/af/rpm.h

33

#define RPMX_CMRX_LINK_RANGE_MASK GENMASK_ULL(19, 16)

drivers/net/ethernet/marvell/octeontx2/af/rpm.h

34

#define RPMX_CMRX_LINK_BASE_MASK GENMASK_ULL(11, 0)

drivers/net/ethernet/marvell/octeontx2/af/rpm.h

71

#define RPM_PFC_CLASS_MASK GENMASK_ULL(48, 33)

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

1152

#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

1153

#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c

106

pa &= GENMASK_ULL(39, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c

20

#define LMT_MAP_ENTRY_LINES GENMASK_ULL(18, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1062

#define INFLIGHT GENMASK_ULL(8, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1063

#define GRB_CNT GENMASK_ULL(39, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1064

#define GWB_CNT GENMASK_ULL(47, 40)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1065

#define XQ_XOR GENMASK_ULL(63, 63)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1066

#define DQPTR GENMASK_ULL(19, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1067

#define NQPTR GENMASK_ULL(51, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1227

#define CTX_CAM_PF_FUNC GENMASK_ULL(61, 46)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1228

#define CTX_CAM_CPTR GENMASK_ULL(45, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

1292

#define MAX_RXC_ICB_CNT GENMASK_ULL(40, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

46

#define MAX_AE GENMASK_ULL(47, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

47

#define MAX_IE GENMASK_ULL(31, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

48

#define MAX_SE GENMASK_ULL(15, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

505

val &= ~(GENMASK_ULL(63, 48) | GENMASK_ULL(47, 32));

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

892

#define RXC_ZOMBIE_THRES GENMASK_ULL(59, 48)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

893

#define RXC_ZOMBIE_LIMIT GENMASK_ULL(43, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

894

#define RXC_ACTIVE_THRES GENMASK_ULL(27, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

895

#define RXC_ACTIVE_LIMIT GENMASK_ULL(11, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

896

#define RXC_ACTIVE_COUNT GENMASK_ULL(60, 48)

drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

897

#define RXC_ZOMBIE_COUNT GENMASK_ULL(60, 48)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

2834

#define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5343

#define RX_SA_BASE GENMASK_ULL(52, 7)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5526

#define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5527

#define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5528

#define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5529

#define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5531

#define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5532

#define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5533

#define CPT_INST_QSEL_SLOT GENMASK_ULL(7, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5535

#define CPT_INST_CREDIT_TH GENMASK_ULL(53, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5536

#define CPT_INST_CREDIT_BPID GENMASK_ULL(30, 22)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

5537

#define CPT_INST_CREDIT_CNT GENMASK_ULL(21, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

6314

tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

775

cfg &= ~GENMASK_ULL(8, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

777

cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

585

rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

588

err = rvu_poll_reg(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, GENMASK_ULL(47, 32), true);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1719

*val |= FIELD_PREP(GENMASK_ULL(57, 56), ptype & pmask);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1720

*mask |= FIELD_PREP(GENMASK_ULL(57, 56), ~ptype & pmask);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

1835

entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

869

relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1,

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c

95

#define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

114

field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

124

field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

128

field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

136

field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

142

field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.h

12

#define NPC_BYTESM GENMASK_ULL(19, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.h

13

#define NPC_HDR_OFFSET GENMASK_ULL(15, 8)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.h

14

#define NPC_KEY_OFFSET GENMASK_ULL(5, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

1923

table->mem_table.ways = FIELD_GET(GENMASK_ULL(19, 16), npc_const3);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

1924

table->mem_table.depth = FIELD_GET(GENMASK_ULL(15, 0), npc_const3);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

1925

table->cam_table.depth = FIELD_GET(GENMASK_ULL(31, 24), npc_const3);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

318

lid = (cfg & GENMASK_ULL(10, 8)) >> 8;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

319

ltype = (cfg & GENMASK_ULL(7, 4)) >> 4;

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

320

ltype_mask = cfg & GENMASK_ULL(3, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

607

u64 mdata = FIELD_PREP(GENMASK_ULL(63, 63), enable ? 1 : 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

610

mdata |= FIELD_PREP(GENMASK_ULL(61, 60), ctype);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

613

mdata |= FIELD_PREP(GENMASK_ULL(59, 48), chan);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

616

mdata |= FIELD_PREP(GENMASK_ULL(47, 0), ldata);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

652

reg_val = FIELD_PREP(GENMASK_ULL(39, 32), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

655

reg_val |= FIELD_PREP(GENMASK_ULL(18, 16), ETH_ALEN - 1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

658

reg_val |= FIELD_PREP(GENMASK_ULL(11, 11), 1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

659

reg_val |= FIELD_PREP(GENMASK_ULL(10, 8), NPC_LID_LA);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

664

reg_val |= FIELD_PREP(GENMASK_ULL(12, 12), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

667

reg_val |= FIELD_PREP(GENMASK_ULL(7, 4), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

670

reg_val |= FIELD_PREP(GENMASK_ULL(3, 0), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

691

reg |= FIELD_PREP(GENMASK_ULL(42, 32), (depth - 1));

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

695

reg |= FIELD_PREP(GENMASK_ULL(10, 0), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

714

mask |= FIELD_PREP(GENMASK_ULL(61, 60), 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

717

mask |= GENMASK_ULL(59, 48);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c

720

mask |= GENMASK_ULL(47, 0);

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

104

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

105

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

108

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

109

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

115

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

116

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

119

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

120

GENMASK_ULL(63, 0),

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

127

[0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

128

[1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

132

[0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.h

133

[1] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

442

#define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

443

#define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

444

#define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

446

#define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

447

#define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

448

#define NIX_VLAN_ETYPE_MASK GENMASK_ULL(63, 48)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

450

#define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

451

#define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

452

#define NIX_AF_TL3_PARENT_MASK GENMASK_ULL(23, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

453

#define NIX_AF_TL2_PARENT_MASK GENMASK_ULL(20, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

737

#define LBK_CONST_CHANS GENMASK_ULL(47, 32)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

738

#define LBK_CONST_DST GENMASK_ULL(31, 28)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

739

#define LBK_CONST_SRC GENMASK_ULL(27, 24)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

740

#define LBK_CONST_BUF_SIZE GENMASK_ULL(23, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

741

#define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

742

#define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

743

#define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0)

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

752

#define LMTST_THROTTLE_MASK GENMASK_ULL(38, 35)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

208

#define CPT_LF_INPROG_INFLIGHT GENMASK_ULL(8, 0)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

209

#define CPT_LF_INPROG_GRB_CNT GENMASK_ULL(39, 32)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

210

#define CPT_LF_INPROG_GWB_CNT GENMASK_ULL(47, 40)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

213

#define CPT_LF_Q_GRP_PTR_DQ_PTR GENMASK_ULL(14, 0)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

214

#define CPT_LF_Q_GRP_PTR_NQ_PTR GENMASK_ULL(46, 32)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

217

#define CPT_LF_Q_BASE_ADDR GENMASK_ULL(52, 7)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

220

#define CPT_LF_Q_SIZE_DIV40 GENMASK_ULL(14, 0)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

223

#define CPT_LF_CTX_FLUSH_CPTR GENMASK_ULL(45, 0)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

12

#define MCS_TCAM0_MAC_DA_MASK GENMASK_ULL(47, 0)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

13

#define MCS_TCAM0_MAC_SA_MASK GENMASK_ULL(63, 48)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

14

#define MCS_TCAM1_MAC_SA_MASK GENMASK_ULL(31, 0)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

15

#define MCS_TCAM1_ETYPE_MASK GENMASK_ULL(47, 32)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

19

#define MCS_RX_SECY_PLCY_RW_MASK GENMASK_ULL(49, 18)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

22

#define MCS_RX_SECY_PLCY_CIP GENMASK_ULL(8, 5)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

23

#define MCS_RX_SECY_PLCY_VAL GENMASK_ULL(2, 1)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

26

#define MCS_TX_SECY_PLCY_MTU GENMASK_ULL(43, 28)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

27

#define MCS_TX_SECY_PLCY_ST_TCI GENMASK_ULL(27, 22)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

28

#define MCS_TX_SECY_PLCY_ST_OFFSET GENMASK_ULL(21, 15)

drivers/net/ethernet/marvell/octeontx2/nic/cn10k_macsec.c

31

#define MCS_TX_SECY_PLCY_CIP GENMASK_ULL(5, 2)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

649

req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57),

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

191

#define TLX_RATE_MANTISSA GENMASK_ULL(8, 1)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

192

#define TLX_RATE_EXPONENT GENMASK_ULL(12, 9)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

193

#define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

194

#define TLX_BURST_MANTISSA GENMASK_ULL(36, 29)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

195

#define TLX_BURST_EXPONENT GENMASK_ULL(40, 37)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

27

#define CN10K_TLX_BURST_MANTISSA GENMASK_ULL(43, 29)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c

28

#define CN10K_TLX_BURST_EXPONENT GENMASK_ULL(47, 44)

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

23

#define CN10K_MAX_RR_WEIGHT GENMASK_ULL(13, 0)

drivers/net/ethernet/marvell/octeontx2/nic/qos.c

24

#define OTX2_MAX_RR_QUANTUM GENMASK_ULL(23, 0)

drivers/net/ethernet/mellanox/mlxsw/item.h

155

tmp &= GENMASK_ULL(item->size.bits - 1, 0);

drivers/net/ethernet/mellanox/mlxsw/item.h

166

u64 mask = GENMASK_ULL(item->size.bits - 1, 0) << item->shift;

drivers/net/ethernet/meta/fbnic/fbnic_csr.h

15

#define DESC_GENMASK(h, l) GENMASK_ULL(h, l)

drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c

36

u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit);

drivers/net/ethernet/mscc/ocelot.c

1265

full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |

drivers/net/ethernet/netronome/nfp/nfp_asm.c

305

if (insn & ~GENMASK_ULL(NFP_USTORE_OP_BITS, 0))

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

31

#define NSP_STATUS_MAGIC GENMASK_ULL(63, 48)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

32

#define NSP_STATUS_MAJOR GENMASK_ULL(47, 44)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

33

#define NSP_STATUS_MINOR GENMASK_ULL(43, 32)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

34

#define NSP_STATUS_CODE GENMASK_ULL(31, 16)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

35

#define NSP_STATUS_RESULT GENMASK_ULL(15, 8)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

39

#define NSP_COMMAND_OPTION GENMASK_ULL(63, 32)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

40

#define NSP_COMMAND_CODE GENMASK_ULL(31, 16)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

46

#define NSP_BUFFER_CPP GENMASK_ULL(63, 40)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

47

#define NSP_BUFFER_ADDRESS GENMASK_ULL(39, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

50

#define NSP_DFLT_BUFFER_CPP GENMASK_ULL(63, 40)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

51

#define NSP_DFLT_BUFFER_ADDRESS GENMASK_ULL(39, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

54

#define NSP_DFLT_BUFFER_DMA_CHUNK_ORDER GENMASK_ULL(63, 58)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

55

#define NSP_DFLT_BUFFER_SIZE_4KB GENMASK_ULL(15, 8)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c

56

#define NSP_DFLT_BUFFER_SIZE_MB GENMASK_ULL(7, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

24

#define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

25

#define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

26

#define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

27

#define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

38

#define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

39

#define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

40

#define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

42

#define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

43

#define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c

44

#define NSP_ETH_STATE_ACT_FEC GENMASK_ULL(29, 28)

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

468

*addr &= ~GENMASK_ULL(idx_lsb, iid_lsb);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

506

v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

595

v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

602

v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

623

v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

658

v64 = GENMASK_ULL(iid_lsb + 5, iid_lsb);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

698

*addr &= ~GENMASK_ULL(29, 24);

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c

699

*addr |= ((u64)dest_island << 24) & GENMASK_ULL(29, 24);

drivers/net/fjes/fjes_hw.c

184

(__le32)(param->req_start & GENMASK_ULL(31, 0)));

drivers/net/fjes/fjes_hw.c

186

(__le32)((param->req_start & GENMASK_ULL(63, 32)) >> 32));

drivers/net/fjes/fjes_hw.c

190

(__le32)(param->res_start & GENMASK_ULL(31, 0)));

drivers/net/fjes/fjes_hw.c

192

(__le32)((param->res_start & GENMASK_ULL(63, 32)) >> 32));

drivers/net/fjes/fjes_hw.c

196

(__le32)(param->share_start & GENMASK_ULL(31, 0)));

drivers/net/fjes/fjes_hw.c

198

(__le32)((param->share_start & GENMASK_ULL(63, 32)) >> 32));

drivers/net/ipa/ipa_cmd.c

135

#define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16)

drivers/net/ipa/ipa_cmd.c

55

#define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0)

drivers/net/ipa/ipa_cmd.c

56

#define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12)

drivers/net/ipa/ipa_cmd.c

57

#define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28)

drivers/net/ipa/ipa_cmd.c

58

#define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40)

drivers/net/pcs/pcs-xpcs-nxp.c

13

#define SJA1110_TXDRVTRIM_LSB(x) ((x) & GENMASK_ULL(15, 0))

drivers/net/pcs/pcs-xpcs-nxp.c

18

#define SJA1110_TXDRVTRIM_MSB(x) (((x) & GENMASK_ULL(23, 16)) >> 16)

drivers/net/phy/aquantia/aquantia.h

160

#define AQR_FW_FINGERPRINT_MAJOR GENMASK_ULL(63, 56)

drivers/net/phy/aquantia/aquantia.h

161

#define AQR_FW_FINGERPRINT_MINOR GENMASK_ULL(55, 48)

drivers/net/phy/aquantia/aquantia.h

162

#define AQR_FW_FINGERPRINT_BUILD_ID GENMASK_ULL(47, 40)

drivers/net/phy/aquantia/aquantia.h

163

#define AQR_FW_FINGERPRINT_PROV_ID GENMASK_ULL(39, 32)

drivers/net/phy/aquantia/aquantia.h

164

#define AQR_FW_FINGERPRINT_MISC_ID GENMASK_ULL(31, 16)

drivers/net/phy/aquantia/aquantia.h

165

#define AQR_FW_FINGERPRINT_MISC_VER GENMASK_ULL(15, 0)

drivers/net/phy/mscc/mscc_ptp.h

123

#define PTP_LTC_LOAD_SEC_MSB(x) (((x) & GENMASK_ULL(47, 32)) >> 32)

drivers/net/phy/nxp-c45-tja11xx.c

194

#define PPM_TO_SUBNS_INC(ppb, ptp_clk_period) div_u64(GENMASK_ULL(31, 0) * \

drivers/net/wireless/ath/ath10k/ce.h

31

#define CE_DESC_ADDR_MASK GENMASK_ULL(34, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

10

#define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)

drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h

11

#define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

13

#define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)

drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h

14

#define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

541

#define HAL_RX_EHT_SIG_OFDMA_EB1_SPATIAL_REUSE GENMASK_ULL(3, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

542

#define HAL_RX_EHT_SIG_OFDMA_EB1_GI_LTF GENMASK_ULL(5, 4)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

543

#define HAL_RX_EHT_SIG_OFDMA_EB1_NUM_LFT_SYM GENMASK_ULL(8, 6)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

545

#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_FEC_PAD_FACTOR GENMASK_ULL(11, 10)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

547

#define HAL_RX_EHT_SIG_OFDMA_EB1_DISREGARD GENMASK_ULL(16, 13)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

548

#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1 GENMASK_ULL(25, 17)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

549

#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2 GENMASK_ULL(34, 26)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

550

#define HAL_RX_EHT_SIG_OFDMA_EB1_CRC GENMASK_ULL(30, 27)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

556

#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1 GENMASK_ULL(8, 0)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

557

#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2 GENMASK_ULL(17, 9)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

558

#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3 GENMASK_ULL(26, 18)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

559

#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4 GENMASK_ULL(35, 27)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

560

#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5 GENMASK_ULL(44, 36)

drivers/net/wireless/ath/ath12k/wifi7/hal_rx.h

561

#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6 GENMASK_ULL(53, 45)

drivers/net/wireless/mediatek/mt76/mt7996/main.c

96

if (~mask & GENMASK_ULL(end, start))

drivers/net/wireless/mediatek/mt76/mt7996/main.c

97

return __ffs64(~mask & GENMASK_ULL(end, start)) + 1;

drivers/net/wireless/realtek/rtw88/coex.h

55

le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 32))

drivers/net/wireless/realtek/rtw88/coex.h

57

le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24))

drivers/net/wireless/realtek/rtw88/coex.h

59

le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(55, 24))

drivers/net/wireless/realtek/rtw88/coex.h

61

le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24))

drivers/net/wireless/realtek/rtw88/main.c

1175

u64 cfg_mask = GENMASK_ULL(63, 0);

drivers/net/wireless/realtek/rtw89/chan.c

961

tsf_lmt = (tsf & GENMASK_ULL(63, 32)) | start_time;

drivers/net/wireless/realtek/rtw89/phy.c

113

nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);

drivers/net/wireless/realtek/rtw89/phy.c

63

ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;

drivers/net/wireless/realtek/rtw89/phy.c

66

ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;

drivers/net/wireless/realtek/rtw89/phy.c

69

ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;

drivers/net/wireless/realtek/rtw89/phy.h

31

#define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)

drivers/net/wireless/realtek/rtw89/phy.h

32

#define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)

drivers/net/wireless/realtek/rtw89/phy.h

35

#define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)

drivers/net/wireless/realtek/rtw89/phy.h

36

#define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)

drivers/net/wireless/realtek/rtw89/phy.h

37

#define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)

drivers/net/wireless/realtek/rtw89/phy.h

38

#define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)

drivers/net/wireless/realtek/rtw89/phy.h

39

#define RA_MASK_HT_RATES GENMASK_ULL(55, 12)

drivers/net/wireless/realtek/rtw89/phy.h

40

#define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)

drivers/net/wireless/realtek/rtw89/phy.h

41

#define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)

drivers/net/wireless/realtek/rtw89/phy.h

42

#define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)

drivers/net/wireless/realtek/rtw89/phy.h

43

#define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)

drivers/net/wireless/realtek/rtw89/phy.h

44

#define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)

drivers/net/wireless/realtek/rtw89/phy.h

45

#define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)

drivers/net/wireless/realtek/rtw89/phy.h

46

#define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)

drivers/net/wireless/realtek/rtw89/phy.h

47

#define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)

drivers/net/wireless/realtek/rtw89/phy.h

48

#define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)

drivers/net/wireless/realtek/rtw89/phy.h

49

#define RA_MASK_HE_RATES GENMASK_ULL(59, 12)

drivers/net/wireless/realtek/rtw89/phy.h

50

#define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12)

drivers/net/wireless/realtek/rtw89/phy.h

51

#define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28)

drivers/net/wireless/realtek/rtw89/phy.h

52

#define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44)

drivers/net/wireless/realtek/rtw89/phy.h

53

#define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60)

drivers/net/wireless/realtek/rtw89/phy.h

54

#define RA_MASK_EHT_1SS_MCS0_11 GENMASK_ULL(23, 12)

drivers/net/wireless/realtek/rtw89/phy.h

55

#define RA_MASK_EHT_2SS_MCS0_11 GENMASK_ULL(39, 28)

drivers/net/wireless/realtek/rtw89/phy.h

56

#define RA_MASK_EHT_3SS_MCS0_11 GENMASK_ULL(55, 44)

drivers/net/wireless/realtek/rtw89/phy.h

57

#define RA_MASK_EHT_4SS_MCS0_11 GENMASK_ULL(62, 60)

drivers/net/wireless/realtek/rtw89/phy.h

58

#define RA_MASK_EHT_RATES GENMASK_ULL(62, 12)

drivers/net/wireless/realtek/rtw89/ps.c

554

tmp = (tsf & GENMASK_ULL(63, 32)) + tmp;

drivers/net/wireless/realtek/rtw89/ps.c

559

tmp = (tsf & GENMASK_ULL(63, 32)) | start_time;

drivers/net/wireless/realtek/rtw89/txrx.h

676

#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK GENMASK_ULL(45, 22) /* VHT SIG-A1 */

drivers/net/wireless/realtek/rtw89/txrx.h

677

#define RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK_GEN2 GENMASK_ULL(55, 32) /* VHT SIG-A1 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

690

#define RTW89_PHY_STS_IE09_VHT_SIG_A2_MASK GENMASK_ULL(55, 46) /* VHT SIG-A2 */

drivers/net/wireless/realtek/rtw89/txrx.h

691

#define RTW89_PHY_STS_IE09_VHT_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 56) /* VHT SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

692

#define RTW89_PHY_STS_IE09_VHT_SIG_A2_MASK_GEN2_H8 GENMASK_ULL(1, 0) /* VHT SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

700

#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK GENMASK_ULL(47, 22) /* HE SU SIG-A1 */

drivers/net/wireless/realtek/rtw89/txrx.h

701

#define RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK_GEN2 GENMASK_ULL(57, 32) /* HE SU SIG-A1 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

713

#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK GENMASK_ULL(63, 48) /* HE SU SIG-A2 */

drivers/net/wireless/realtek/rtw89/txrx.h

714

#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 58) /* HE SU SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

715

#define RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_H6 GENMASK_ULL(9, 0) /* HE SU SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

725

#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK GENMASK_ULL(47, 22) /* HE TB SIG-A1 */

drivers/net/wireless/realtek/rtw89/txrx.h

726

#define RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK_GEN2 GENMASK_ULL(57, 32) /* HE TB SIG-A1 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

735

#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK GENMASK_ULL(63, 48) /* HE TB SIG-A2 */

drivers/net/wireless/realtek/rtw89/txrx.h

736

#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 58) /* HE TB SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

737

#define RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_H6 GENMASK_ULL(9, 0) /* HE TB SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

740

#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK GENMASK_ULL(47, 22) /* HE MU SIG-A1 */

drivers/net/wireless/realtek/rtw89/txrx.h

741

#define RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK_GEN2 GENMASK_ULL(57, 32) /* HE MU SIG-A1 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

752

#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK GENMASK_ULL(63, 48) /* HE MU SIG-A2 */

drivers/net/wireless/realtek/rtw89/txrx.h

753

#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_L0 GENMASK_ULL(63, 58) /* HE MU SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/txrx.h

754

#define RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_H6 GENMASK_ULL(9, 0) /* HE MU SIG-A2 for GEN2 */

drivers/net/wireless/realtek/rtw89/util.h

10

#define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)

drivers/net/wireless/realtek/rtw89/util.h

11

#define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)

drivers/net/wireless/realtek/rtw89/util.h

12

#define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)

drivers/net/wireless/realtek/rtw89/util.h

13

#define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)

drivers/net/wireless/realtek/rtw89/util.h

14

#define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)

drivers/net/wireless/realtek/rtw89/util.h

9

#define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)

drivers/net/wireless/realtek/rtw89/wow.h

11

#define RTW89_IGTK_IPN_0 GENMASK_ULL(7, 0)

drivers/net/wireless/realtek/rtw89/wow.h

12

#define RTW89_IGTK_IPN_1 GENMASK_ULL(15, 8)

drivers/net/wireless/realtek/rtw89/wow.h

13

#define RTW89_IGTK_IPN_2 GENMASK_ULL(23, 16)

drivers/net/wireless/realtek/rtw89/wow.h

14

#define RTW89_IGTK_IPN_3 GENMASK_ULL(31, 24)

drivers/net/wireless/realtek/rtw89/wow.h

15

#define RTW89_IGTK_IPN_4 GENMASK_ULL(39, 32)

drivers/net/wireless/realtek/rtw89/wow.h

16

#define RTW89_IGTK_IPN_5 GENMASK_ULL(47, 40)

drivers/net/wireless/realtek/rtw89/wow.h

17

#define RTW89_IGTK_IPN_6 GENMASK_ULL(55, 48)

drivers/net/wireless/realtek/rtw89/wow.h

18

#define RTW89_IGTK_IPN_7 GENMASK_ULL(63, 56)

drivers/net/wireless/realtek/rtw89/wow.h

8

#define RTW89_KEY_TKIP_PN_IV16 GENMASK_ULL(15, 0)

drivers/net/wireless/realtek/rtw89/wow.h

9

#define RTW89_KEY_TKIP_PN_IV32 GENMASK_ULL(47, 16)

drivers/net/wwan/t7xx/t7xx_reg.h

89

#define ATR_PCIE_WIN0_ADDR_ALGMT GENMASK_ULL(63, 12)

drivers/ntb/test/ntb_perf.c

678

mask = GENMASK_ULL(perf->pcnt, 0);

drivers/ntb/test/ntb_pingpong.c

258

pmask = GENMASK_ULL(ntb_peer_port_count(ntb), 0);

drivers/ntb/test/ntb_pingpong.c

305

pp->pmask = GENMASK_ULL(pidx, 0) >> 1;

drivers/ntb/test/ntb_pingpong.c

306

pp->nmask = GENMASK_ULL(pcnt - 1, pidx);

drivers/nvme/target/pci-epf.c

1881

pci_addr = acq & GENMASK_ULL(63, 12);

drivers/nvme/target/pci-epf.c

1891

pci_addr = asq & GENMASK_ULL(63, 12);

drivers/nvme/target/pci-epf.c

2000

ctrl->cap &= ~GENMASK_ULL(35, 32);

drivers/pci/controller/cadence/pcie-cadence-ep.c

416

pci_addr &= GENMASK_ULL(63, 2);

drivers/pci/controller/cadence/pcie-cadence-ep.c

471

pci_addr &= GENMASK_ULL(63, 2);

drivers/pci/controller/dwc/pcie-designware-host.c

370

if (!(pp->cfg0_base & GENMASK_ULL(63, 32))) {

drivers/pci/controller/pci-thunder-pem.c

338

#define PEM_NODE_MASK GENMASK_ULL(45, 44)

drivers/pci/controller/pci-thunder-pem.c

339

#define PEM_INDX_MASK GENMASK_ULL(26, 24)

drivers/pci/controller/pcie-rockchip.h

166

#define PCIE_ADDR_MASK GENMASK_ULL(63, MIN_AXI_ADDR_BITS_PASSED)

drivers/pci/endpoint/functions/pci-epf-vntb.c

1391

return GENMASK_ULL(nr_vec - 1, 0);

drivers/pci/ide.c

528

#define SEL_ADDR_UPPER GENMASK_ULL(63, 32)

drivers/perf/alibaba_uncore_drw_pmu.c

77

#define ALI_DRW_PMU_OV_INTR_MASK GENMASK_ULL(63, 0)

drivers/perf/arm-cmn.c

100

#define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32)

drivers/perf/arm-cmn.c

104

#define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16)

drivers/perf/arm-cmn.c

117

#define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0)

drivers/perf/arm-cmn.c

163

#define CMN_CONFIG_TYPE GENMASK_ULL(15, 0)

drivers/perf/arm-cmn.c

164

#define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16)

drivers/perf/arm-cmn.c

165

#define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27)

drivers/perf/arm-cmn.c

167

#define CMN_CONFIG_NODEID GENMASK_ULL(47, 32)

drivers/perf/arm-cmn.c

175

#define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27)

drivers/perf/arm-cmn.c

176

#define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48)

drivers/perf/arm-cmn.c

177

#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51)

drivers/perf/arm-cmn.c

178

#define CMN_CONFIG_WP_GRP GENMASK_ULL(57, 56)

drivers/perf/arm-cmn.c

180

#define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0)

drivers/perf/arm-cmn.c

181

#define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0)

drivers/perf/arm-cmn.c

23

#define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0)

drivers/perf/arm-cmn.c

24

#define CMN_NI_NODE_ID GENMASK_ULL(31, 16)

drivers/perf/arm-cmn.c

25

#define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32)

drivers/perf/arm-cmn.c

28

#define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0)

drivers/perf/arm-cmn.c

29

#define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16)

drivers/perf/arm-cmn.c

43

#define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0)

drivers/perf/arm-cmn.c

44

#define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32)

drivers/perf/arm-cmn.c

46

#define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4)

drivers/perf/arm-cmn.c

50

#define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52)

drivers/perf/arm-cmn.c

51

#define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50)

drivers/perf/arm-cmn.c

55

#define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2)

drivers/perf/arm-cmn.c

56

#define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0)

drivers/perf/arm-cmn.c

60

#define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(5, 0)

drivers/perf/arm-cmn.c

73

#define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42)

drivers/perf/arm-cmn.c

74

#define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39)

drivers/perf/arm-cmn.c

75

#define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37)

drivers/perf/arm-cmn.c

76

#define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35)

drivers/perf/arm-cmn.c

78

#define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32)

drivers/perf/arm-cmn.c

87

#define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19)

drivers/perf/arm-cmn.c

88

#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17)

drivers/perf/arm-cmn.c

93

#define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4)

drivers/perf/arm-cmn.c

94

#define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)

drivers/perf/arm-ni.c

64

#define NI_CONFIG_TYPE GENMASK_ULL(15, 0)

drivers/perf/arm-ni.c

65

#define NI_CONFIG_NODEID GENMASK_ULL(31, 16)

drivers/perf/arm-ni.c

66

#define NI_CONFIG_EVENTID GENMASK_ULL(47, 32)

drivers/perf/arm_cspmu/ampere_cspmu.c

31

return FIELD_GET(GENMASK_ULL(_end, _start), \

drivers/perf/arm_cspmu/arm_cspmu.c

129

return GENMASK_ULL(counter_size(cspmu) - 1, 0);

drivers/perf/arm_cspmu/arm_cspmu.h

39

#define ARM_CSPMU_EVENT_MASK GENMASK_ULL(63, 0)

drivers/perf/arm_cspmu/arm_cspmu.h

42

#define ARM_CSPMU_FILTER_MASK GENMASK_ULL(63, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

17

#define NV_PCIE_FILTER_ID_MASK GENMASK_ULL(NV_PCIE_PORT_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

20

#define NV_NVL_C2C_FILTER_ID_MASK GENMASK_ULL(NV_NVL_C2C_PORT_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

23

#define NV_CNVL_FILTER_ID_MASK GENMASK_ULL(NV_CNVL_PORT_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

27

#define NV_UCF_FILTER_ID_MASK GENMASK_ULL(11, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

28

#define NV_UCF_FILTER_SRC GENMASK_ULL(2, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

29

#define NV_UCF_FILTER_DST GENMASK_ULL(11, 8)

drivers/perf/arm_cspmu/nvidia_cspmu.c

33

#define NV_PCIE_V2_FILTER_ID_MASK GENMASK_ULL(24, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

34

#define NV_PCIE_V2_FILTER_PORT GENMASK_ULL(NV_PCIE_V2_PORT_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

35

#define NV_PCIE_V2_FILTER_BDF_VAL GENMASK_ULL(23, NV_PCIE_V2_PORT_COUNT)

drivers/perf/arm_cspmu/nvidia_cspmu.c

37

#define NV_PCIE_V2_FILTER_BDF_VAL_EN GENMASK_ULL(24, NV_PCIE_V2_PORT_COUNT)

drivers/perf/arm_cspmu/nvidia_cspmu.c

41

#define NV_PCIE_V2_FILTER2_ID_MASK GENMASK_ULL(4, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

410

src = GENMASK_ULL(NV_UCF_SRC_COUNT - 1, 0);

drivers/perf/arm_cspmu/nvidia_cspmu.c

415

dst = GENMASK_ULL(NV_UCF_DST_COUNT - 1, 0);

drivers/perf/arm_cspmu/nvidia_cspmu.c

42

#define NV_PCIE_V2_FILTER2_DST GENMASK_ULL(NV_PCIE_V2_DST_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

48

#define NV_PCIE_TGT_EV_TYPE_MASK GENMASK_ULL(NV_PCIE_TGT_EV_TYPE_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

49

#define NV_PCIE_TGT_FILTER2_MASK GENMASK_ULL(NV_PCIE_TGT_PORT_COUNT, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

50

#define NV_PCIE_TGT_FILTER2_PORT GENMASK_ULL(NV_PCIE_TGT_PORT_COUNT - 1, 0)

drivers/perf/arm_cspmu/nvidia_cspmu.c

52

#define NV_PCIE_TGT_FILTER2_ADDR GENMASK_ULL(15, NV_PCIE_TGT_PORT_COUNT)

drivers/perf/arm_cspmu/nvidia_cspmu.c

63

#define NV_GENERIC_FILTER_ID_MASK GENMASK_ULL(31, 0)

drivers/perf/arm_dmc620_pmu.c

205

((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))

drivers/perf/arm_pmu.c

115

return GENMASK_ULL(63, 0);

drivers/perf/arm_pmu.c

117

return GENMASK_ULL(62, 0);

drivers/perf/arm_pmu.c

119

return GENMASK_ULL(46, 0);

drivers/perf/arm_pmu.c

121

return GENMASK_ULL(31, 0);

drivers/perf/arm_pmuv3.c

580

value |= GENMASK_ULL(63, 32);

drivers/perf/arm_pmuv3.c

588

value &= ~GENMASK_ULL(63, 32);

drivers/perf/arm_smmuv3_pmu.c

106

#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)

drivers/perf/arm_smmuv3_pmu.c

145

return FIELD_GET(GENMASK_ULL(_end, _start), \

drivers/perf/arm_smmuv3_pmu.c

780

u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);

drivers/perf/arm_smmuv3_pmu.c

909

smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);

drivers/perf/cxl_pmu.c

242

#define CXL_PMU_ATTR_CONFIG_MASK_MSK GENMASK_ULL(31, 0)

drivers/perf/cxl_pmu.c

243

#define CXL_PMU_ATTR_CONFIG_GID_MSK GENMASK_ULL(47, 32)

drivers/perf/cxl_pmu.c

244

#define CXL_PMU_ATTR_CONFIG_VID_MSK GENMASK_ULL(63, 48)

drivers/perf/cxl_pmu.c

245

#define CXL_PMU_ATTR_CONFIG1_THRESHOLD_MSK GENMASK_ULL(15, 0)

drivers/perf/cxl_pmu.c

28

#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0)

drivers/perf/cxl_pmu.c

29

#define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8)

drivers/perf/cxl_pmu.c

30

#define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20)

drivers/perf/cxl_pmu.c

31

#define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32)

drivers/perf/cxl_pmu.c

34

#define CXL_PMU_CAP_MSI_N_MSK GENMASK_ULL(47, 44)

drivers/perf/cxl_pmu.c

38

#define CXL_PMU_CAP_VERSION_MSK GENMASK_ULL(63, 60)

drivers/perf/cxl_pmu.c

43

#define CXL_PMU_EVENT_CAP_SUPPORTED_EVENTS_MSK GENMASK_ULL(31, 0)

drivers/perf/cxl_pmu.c

44

#define CXL_PMU_EVENT_CAP_GROUP_ID_MSK GENMASK_ULL(47, 32)

drivers/perf/cxl_pmu.c

45

#define CXL_PMU_EVENT_CAP_VENDOR_ID_MSK GENMASK_ULL(63, 48)

drivers/perf/cxl_pmu.c

48

#define CXL_PMU_COUNTER_CFG_TYPE_MSK GENMASK_ULL(1, 0)

drivers/perf/cxl_pmu.c

57

#define CXL_PMU_COUNTER_CFG_THRESHOLD_MSK GENMASK_ULL(23, 16)

drivers/perf/cxl_pmu.c

58

#define CXL_PMU_COUNTER_CFG_EVENTS_MSK GENMASK_ULL(55, 24)

drivers/perf/cxl_pmu.c

59

#define CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK GENMASK_ULL(63, 59)

drivers/perf/cxl_pmu.c

609

writeq(GENMASK_ULL(63, 0), base + CXL_PMU_FREEZE_REG);

drivers/perf/cxl_pmu.c

699

delta = (new_cnt - prev_cnt) & GENMASK_ULL(info->counter_width - 1, 0);

drivers/perf/cxl_pmu.c

700

if (overflow && delta < GENMASK_ULL(info->counter_width - 1, 0))

drivers/perf/dwc_pcie_pmu.c

84

#define DWC_PCIE_LANE_EVENT_MAX_PERIOD GENMASK_ULL(31, 0)

drivers/perf/dwc_pcie_pmu.c

85

#define DWC_PCIE_MAX_PERIOD GENMASK_ULL(63, 0)

drivers/perf/hisilicon/hisi_pcie_pmu.c

47

#define HISI_PCIE_EVENT_M GENMASK_ULL(15, 0)

drivers/perf/hisilicon/hisi_pcie_pmu.c

48

#define HISI_PCIE_THR_MODE_M GENMASK_ULL(27, 27)

drivers/perf/hisilicon/hisi_pcie_pmu.c

49

#define HISI_PCIE_THR_M GENMASK_ULL(31, 28)

drivers/perf/hisilicon/hisi_pcie_pmu.c

50

#define HISI_PCIE_LEN_M GENMASK_ULL(35, 34)

drivers/perf/hisilicon/hisi_pcie_pmu.c

51

#define HISI_PCIE_TARGET_M GENMASK_ULL(52, 36)

drivers/perf/hisilicon/hisi_pcie_pmu.c

52

#define HISI_PCIE_TRIG_MODE_M GENMASK_ULL(53, 53)

drivers/perf/hisilicon/hisi_pcie_pmu.c

53

#define HISI_PCIE_TRIG_M GENMASK_ULL(59, 56)

drivers/perf/hisilicon/hisi_pcie_pmu.c

62

#define HISI_PCIE_MAX_PERIOD (GENMASK_ULL(63, 0))

drivers/perf/hisilicon/hisi_uncore_pmu.c

24

#define HISI_MAX_PERIOD(nr) (GENMASK_ULL((nr) - 1, 0))

drivers/perf/hisilicon/hisi_uncore_pmu.h

43

return FIELD_GET(GENMASK_ULL(hi, lo), event->attr.config); \

drivers/perf/hisilicon/hns3_pmu.c

327

return FIELD_GET(GENMASK_ULL(_end, _start), \

drivers/perf/marvell_cn10k_ddr_pmu.c

139

#define DDRC_PERF_CNT_MAX_VALUE GENMASK_ULL(48, 0)

drivers/perf/marvell_cn10k_ddr_pmu.c

943

.counter_max_val = GENMASK_ULL(48, 0),

drivers/perf/marvell_cn10k_ddr_pmu.c

970

.counter_max_val = GENMASK_ULL(63, 0),

drivers/perf/riscv_pmu.c

157

return GENMASK_ULL(cwidth, 0);

drivers/perf/starfive_starlink_pmu.c

30

#define STARLINK_PMU_COUNTER_MASK GENMASK_ULL(63, 0)

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

278

if (pcw > GENMASK_ULL(32, 0))

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

281

fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw);

drivers/pinctrl/renesas/pinctrl-rzg2l.c

111

#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

112

#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

113

#define PIN_CFG_MASK GENMASK_ULL(31, 0)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

134

#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

135

#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

150

#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

151

#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)

drivers/pinctrl/renesas/pinctrl-rzt2h.c

55

#define PFC_MASK GENMASK_ULL(5, 0)

drivers/pinctrl/renesas/pinctrl-rzt2h.c

59

#define DRCTL_DRV_PIN_MASK(pin) (GENMASK_ULL(1, 0) << ((pin) * 8))

drivers/pinctrl/renesas/pinctrl-rzt2h.c

60

#define DRCTL_PUD_PIN_MASK(pin) (GENMASK_ULL(3, 2) << ((pin) * 8))

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

36

#define UR_DP1000_PINS_ABCD GENMASK_ULL(39, 0)

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

37

#define UR_DP1000_PINS_LPC GENMASK_ULL(52, 40)

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

50

{ "i2c", UR_FUNC_0, GENMASK_ULL(13, 12) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

51

{ "i2c", UR_FUNC_0, GENMASK_ULL(23, 22) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

52

{ "i2c", UR_FUNC_0, GENMASK_ULL(25, 24) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

53

{ "i2c", UR_FUNC_0, GENMASK_ULL(27, 26) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

54

{ "pwm", UR_FUNC_0, GENMASK_ULL(19, 16) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

55

{ "spi", UR_FUNC_1, GENMASK_ULL(39, 32) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

56

{ "spi", UR_FUNC_0, GENMASK_ULL(6, 0) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

57

{ "uart", UR_FUNC_1, GENMASK_ULL(9, 8) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

58

{ "uart", UR_FUNC_0, GENMASK_ULL(21, 20) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

59

{ "uart", UR_FUNC_0, GENMASK_ULL(29, 28) },

drivers/pinctrl/ultrarisc/pinctrl-dp1000.c

60

{ "uart", UR_FUNC_0, GENMASK_ULL(31, 30) },

drivers/platform/mellanox/mlxbf-bootctl.c

59

#define MLXBF_RSH_LOG_TYPE_MASK GENMASK_ULL(59, 56)

drivers/platform/mellanox/mlxbf-bootctl.c

60

#define MLXBF_RSH_LOG_LEN_MASK GENMASK_ULL(54, 48)

drivers/platform/mellanox/mlxbf-bootctl.c

61

#define MLXBF_RSH_LOG_LEVEL_MASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-pmc.c

53

#define MLXBF_PMC_PERFMON_CONFIG_ADDR GENMASK_ULL(4, 2)

drivers/platform/mellanox/mlxbf-pmc.c

54

#define MLXBF_PMC_PERFMON_CONFIG_WDATA GENMASK_ULL(60, 5)

drivers/platform/mellanox/mlxbf-pmc.c

56

#define MLXBF_PMC_PERFCTL_FM0 GENMASK_ULL(18, 16)

drivers/platform/mellanox/mlxbf-pmc.c

57

#define MLXBF_PMC_PERFCTL_MS0 GENMASK_ULL(21, 20)

drivers/platform/mellanox/mlxbf-pmc.c

58

#define MLXBF_PMC_PERFCTL_ACCM0 GENMASK_ULL(26, 24)

drivers/platform/mellanox/mlxbf-pmc.c

60

#define MLXBF_PMC_PERFCTL_ETRIG0 GENMASK_ULL(29, 28)

drivers/platform/mellanox/mlxbf-pmc.c

64

#define MLXBF_PMC_PERFEVT_EVTSEL GENMASK_ULL(31, 24)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

18

#define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

19

#define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

25

#define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

26

#define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

30

#define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

31

#define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

35

#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

36

#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

43

#define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

44

#define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

50

#define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

51

#define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

55

#define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

56

#define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

60

#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)

drivers/platform/mellanox/mlxbf-tmfifo-regs.h

61

#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)

drivers/platform/x86/acer-wmi.c

100

#define ACER_PREDATOR_V4_SENSOR_READING_BIT_MASK GENMASK_ULL(23, 8)

drivers/platform/x86/acer-wmi.c

101

#define ACER_PREDATOR_V4_SUPPORTED_SENSORS_BIT_MASK GENMASK_ULL(39, 24)

drivers/platform/x86/acer-wmi.c

83

#define ACER_GAMING_FAN_BEHAVIOR_STATUS_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/acer-wmi.c

84

#define ACER_GAMING_FAN_BEHAVIOR_ID_MASK GENMASK_ULL(15, 0)

drivers/platform/x86/acer-wmi.c

90

#define ACER_GAMING_FAN_SPEED_STATUS_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/acer-wmi.c

91

#define ACER_GAMING_FAN_SPEED_ID_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/acer-wmi.c

92

#define ACER_GAMING_FAN_SPEED_VALUE_MASK GENMASK_ULL(15, 8)

drivers/platform/x86/acer-wmi.c

94

#define ACER_GAMING_MISC_SETTING_STATUS_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/acer-wmi.c

95

#define ACER_GAMING_MISC_SETTING_INDEX_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/acer-wmi.c

96

#define ACER_GAMING_MISC_SETTING_VALUE_MASK GENMASK_ULL(15, 8)

drivers/platform/x86/acer-wmi.c

98

#define ACER_PREDATOR_V4_RETURN_STATUS_BIT_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/acer-wmi.c

99

#define ACER_PREDATOR_V4_SENSOR_INDEX_BIT_MASK GENMASK_ULL(15, 8)

drivers/platform/x86/intel/plr_tpmi.c

36

#define PLR_MODULE_ID_MASK GENMASK_ULL(19, 12)

drivers/platform/x86/intel/plr_tpmi.c

41

#define PLR_INVALID GENMASK_ULL(63, 0)

drivers/platform/x86/intel/pmc/ssram_telemetry.c

28

#define SSRAM_BASE_ADDR_MASK GENMASK_ULL(63, 3)

drivers/platform/x86/intel/speed_select_if/isst_if_common.c

141

full_cmd = (cmd & GENMASK_ULL(15, 0)) << 16;

drivers/platform/x86/intel/speed_select_if/isst_if_common.c

142

full_cmd |= (sub_cmd & GENMASK_ULL(15, 0));

drivers/platform/x86/intel/speed_select_if/isst_if_common.c

167

mbox_cmd.command = (sst_cmd->cmd & GENMASK_ULL(31, 16)) >> 16;

drivers/platform/x86/intel/speed_select_if/isst_if_common.c

168

mbox_cmd.sub_command = sst_cmd->cmd & GENMASK_ULL(15, 0);

drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c

60

(parameter & GENMASK_ULL(13, 0)) << 16 |

drivers/platform/x86/intel/speed_select_if/isst_if_mbox_pci.c

77

(mbox_cmd->parameter & GENMASK_ULL(13, 0)) << 16 |

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1012

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

574

mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

586

mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

769

mask = GENMASK_ULL((shift + SST_CLOS_ASSOC_BITS_PER_CPU - 1), shift);

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

793

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

819

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

832

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/tpmi_power_domains.c

43

#define LP_ID_MASK GENMASK_ULL(2, 0)

drivers/platform/x86/intel/tpmi_power_domains.c

44

#define MODULE_ID_MASK GENMASK_ULL(10, 3)

drivers/platform/x86/intel/tpmi_power_domains.c

45

#define PM_DOMAIN_ID_MASK GENMASK_ULL(15, 11)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

366

#define UNCORE_AGENT_TYPES GENMASK_ULL(26, 23)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

549

#define UNCORE_VERSION_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

550

#define UNCORE_LOCAL_FABRIC_CLUSTER_ID_MASK GENMASK_ULL(15, 8)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

551

#define UNCORE_CLUSTER_OFF_MASK GENMASK_ULL(7, 0)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

78

#define UNCORE_CURRENT_RATIO_MASK GENMASK_ULL(6, 0)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

81

#define UNCORE_MAX_RATIO_MASK GENMASK_ULL(14, 8)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

82

#define UNCORE_MIN_RATIO_MASK GENMASK_ULL(21, 15)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

83

#define UNCORE_EFF_LAT_CTRL_RATIO_MASK GENMASK_ULL(28, 22)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

84

#define UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK GENMASK_ULL(38, 32)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c

86

#define UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK GENMASK_ULL(46, 40)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c

41

#define UNCORE_MAX_RATIO_MASK GENMASK_ULL(6, 0)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c

42

#define UNCORE_MIN_RATIO_MASK GENMASK_ULL(14, 8)

drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c

44

#define UNCORE_CURRENT_RATIO_MASK GENMASK_ULL(6, 0)

drivers/platform/x86/intel/vsec_tpmi.c

257

#define TPMI_CONTROL_STATUS_OWNER GENMASK_ULL(5, 4)

drivers/platform/x86/intel/vsec_tpmi.c

262

#define TPMI_CONTROL_STATUS_RESULT GENMASK_ULL(15, 8)

drivers/platform/x86/intel/vsec_tpmi.c

263

#define TPMI_CONTROL_STATUS_LEN GENMASK_ULL(31, 16)

drivers/platform/x86/intel/vsec_tpmi.c

269

#define TMPI_CONTROL_DATA_CMD GENMASK_ULL(7, 0)

drivers/platform/x86/intel/vsec_tpmi.c

270

#define TPMI_CONTROL_DATA_VAL_FEATURE GENMASK_ULL(48, 40)

drivers/platform/x86/intel/vsec_tpmi.c

275

#define TPMI_CONTROL_CMD_MASK GENMASK_ULL(48, 40)

drivers/platform/x86/intel/vsec_tpmi.c

277

#define TPMI_CMD_LEN_MASK GENMASK_ULL(18, 16)

drivers/powercap/intel_rapl_msr.c

54

#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)

drivers/powercap/intel_rapl_msr.c

62

#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)

drivers/powercap/intel_rapl_msr.c

63

#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)

drivers/powercap/intel_rapl_msr.c

65

#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)

drivers/powercap/intel_rapl_msr.c

66

#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)

drivers/powercap/intel_rapl_msr.c

67

#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)

drivers/powercap/intel_rapl_msr.c

78

#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)

drivers/powercap/intel_rapl_msr.c

81

#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)

drivers/powercap/intel_rapl_msr.c

84

#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)

drivers/powercap/intel_rapl_msr.c

85

#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)

drivers/powercap/intel_rapl_tpmi.c

312

#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6)

drivers/powercap/intel_rapl_tpmi.c

314

#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12)

drivers/powercap/intel_rapl_tpmi.c

66

#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0)

drivers/powercap/intel_rapl_tpmi.c

69

#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18)

drivers/powercap/intel_rapl_tpmi.c

70

#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0)

drivers/powercap/intel_rapl_tpmi.c

71

#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18)

drivers/powercap/intel_rapl_tpmi.c

72

#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36)

drivers/powercap/intel_rapl_tpmi.c

73

#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54)

drivers/ptp/ptp_dfl_tod.c

41

#define SECONDS_MSB GENMASK_ULL(47, 32)

drivers/ptp/ptp_dfl_tod.c

42

#define SECONDS_LSB GENMASK_ULL(31, 0)

drivers/ptp/ptp_dfl_tod.c

43

#define TOD_SECONDSH_SEC_MSB GENMASK_ULL(15, 0)

drivers/ptp/ptp_dfl_tod.c

47

#define TOD_PERIOD_MASK GENMASK_ULL(19, 0)

drivers/ptp/ptp_dfl_tod.c

50

#define TOD_DRIFT_ADJUST_MASK GENMASK_ULL(15, 0)

drivers/ptp/ptp_dfl_tod.c

53

#define TOD_ADJUST_COUNT_MASK GENMASK_ULL(19, 0)

drivers/ptp/ptp_netc.c

79

#define NETC_TMR_DEFAULT_ALARM GENMASK_ULL(63, 0)

drivers/ras/amd/atl/denormalize.c

1034

denorm_addr |= FIELD_GET(GENMASK_ULL(63, 1), temp_addr) << 12;

drivers/ras/amd/atl/denormalize.c

1039

denorm_addr |= FIELD_GET(GENMASK_ULL(1, 0), temp_addr) << 8;

drivers/ras/amd/atl/denormalize.c

1040

denorm_addr |= FIELD_GET(GENMASK_ULL(63, 2), (temp_addr)) << 12;

drivers/ras/amd/atl/denormalize.c

1046

denorm_addr |= FIELD_GET(GENMASK_ULL(63, 1), temp_addr) << 12;

drivers/ras/amd/atl/denormalize.c

1173

denorm_ctx->base_denorm_addr = FIELD_GET(GENMASK_ULL(7, 0), ctx->ret_addr);

drivers/ras/amd/atl/denormalize.c

1182

denorm_ctx->base_denorm_addr |= FIELD_GET(GENMASK_ULL(9, 8), ctx->ret_addr) << 10;

drivers/ras/amd/atl/denormalize.c

1183

denorm_ctx->div_addr = FIELD_GET(GENMASK_ULL(63, 10), ctx->ret_addr);

drivers/ras/amd/atl/denormalize.c

1192

denorm_ctx->base_denorm_addr |= FIELD_GET(GENMASK_ULL(10, 8), ctx->ret_addr) << 9;

drivers/ras/amd/atl/denormalize.c

1193

denorm_ctx->div_addr = FIELD_GET(GENMASK_ULL(63, 11), ctx->ret_addr);

drivers/ras/amd/atl/denormalize.c

490

cs_id = FIELD_GET(GENMASK_ULL(63, 13), denorm_ctx->current_spa) << 3;

drivers/ras/amd/atl/denormalize.c

498

cs_id = FIELD_GET(GENMASK_ULL(63, 14), denorm_ctx->current_spa) << 4;

drivers/ras/amd/atl/denormalize.c

506

cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2;

drivers/ras/amd/atl/denormalize.c

513

cs_id = FIELD_GET(GENMASK_ULL(63, 13), denorm_ctx->current_spa) << 3;

drivers/ras/amd/atl/denormalize.c

521

cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2;

drivers/ras/amd/atl/denormalize.c

530

cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2;

drivers/ras/amd/atl/denormalize.c

538

cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2;

drivers/ras/amd/atl/denormalize.c

539

cs_id |= FIELD_GET(GENMASK_ULL(9, 8), denorm_ctx->current_spa);

drivers/ras/amd/atl/denormalize.c

545

cs_id = FIELD_GET(GENMASK_ULL(63, 12), denorm_ctx->current_spa) << 2;

drivers/ras/amd/atl/denormalize.c

618

temp_addr_b = GENMASK_ULL(low_bit - 1, intlv_bit) & ctx->ret_addr;

drivers/ras/amd/atl/denormalize.c

641

temp_addr_b = GENMASK_ULL(63, intlv_bit) & ctx->ret_addr;

drivers/ras/amd/atl/denormalize.c

645

temp_addr_a = GENMASK_ULL(intlv_bit - 1, 0) & ctx->ret_addr;

drivers/ras/amd/atl/denormalize.c

708

temp_addr_a &= GENMASK_ULL(13, 0);

drivers/ras/amd/atl/denormalize.c

712

temp_addr_b = GENMASK_ULL(63, shift_value) & ctx->ret_addr;

drivers/ras/amd/atl/denormalize.c

826

temp_addr_a = FIELD_GET(GENMASK_ULL(11, 10), addr) << 8;

drivers/ras/amd/atl/denormalize.c

835

temp_addr_a = FIELD_GET(GENMASK_ULL(11, 9), addr) << 8;

drivers/ras/amd/atl/denormalize.c

845

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 13), addr) / denorm_ctx->mod_value;

drivers/ras/amd/atl/denormalize.c

850

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 14), addr) / denorm_ctx->mod_value;

drivers/ras/amd/atl/denormalize.c

855

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) / denorm_ctx->mod_value;

drivers/ras/amd/atl/denormalize.c

860

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 13), addr) / denorm_ctx->mod_value;

drivers/ras/amd/atl/denormalize.c

866

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) << 1;

drivers/ras/amd/atl/denormalize.c

874

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) / denorm_ctx->mod_value;

drivers/ras/amd/atl/denormalize.c

880

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) << 2;

drivers/ras/amd/atl/denormalize.c

881

temp_addr_b |= FIELD_GET(GENMASK_ULL(9, 8), addr);

drivers/ras/amd/atl/denormalize.c

888

temp_addr_b = FIELD_GET(GENMASK_ULL(63, 12), addr) << 1;

drivers/ras/amd/atl/internal.h

321

temp1 = data & GENMASK_ULL(bit_num - 1, 0);

drivers/ras/amd/atl/internal.h

323

temp2 = data & GENMASK_ULL(63, bit_num);

drivers/ras/amd/atl/internal.h

347

temp1 = GENMASK_ULL(low_bit - 1, 0) & data;

drivers/ras/amd/atl/internal.h

348

temp2 = GENMASK_ULL(63, high_bit + 1) & data;

drivers/ras/amd/atl/umc.c

373

#define MCA_IPID_INST_ID_HI GENMASK_ULL(47, 44)

drivers/resctrl/mpam_devices.c

37

#define T241_CHIP_ID(phys) FIELD_GET(GENMASK_ULL(44, 43), phys)

drivers/resctrl/mpam_devices.c

687

phys = FIELD_PREP(GENMASK_ULL(45, 44), msc->t241_id) | 0x19000000ULL;

drivers/rtc/rtc-mpfs.c

235

rtcdev->rtc->range_max = GENMASK_ULL(42, 0);

drivers/s390/char/uvdevice.c

49

.supp_uvio_cmds = GENMASK_ULL(UVIO_IOCTL_NUM_IOCTLS - 1, 0),

drivers/soc/apple/rtkit.c

27

#define APPLE_RTKIT_MGMT_TYPE GENMASK_ULL(59, 52)

drivers/soc/apple/rtkit.c

41

#define APPLE_RTKIT_MGMT_HELLO_MINVER GENMASK_ULL(15, 0)

drivers/soc/apple/rtkit.c

42

#define APPLE_RTKIT_MGMT_HELLO_MAXVER GENMASK_ULL(31, 16)

drivers/soc/apple/rtkit.c

45

#define APPLE_RTKIT_MGMT_EPMAP_BASE GENMASK_ULL(34, 32)

drivers/soc/apple/rtkit.c

46

#define APPLE_RTKIT_MGMT_EPMAP_BITMAP GENMASK_ULL(31, 0)

drivers/soc/apple/rtkit.c

50

#define APPLE_RTKIT_MGMT_STARTEP_EP GENMASK_ULL(39, 32)

drivers/soc/apple/rtkit.c

53

#define APPLE_RTKIT_MGMT_PWR_STATE GENMASK_ULL(15, 0)

drivers/soc/apple/rtkit.c

58

#define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK_ULL(51, 44)

drivers/soc/apple/rtkit.c

59

#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK_ULL(43, 0)

drivers/soc/apple/rtkit.c

61

#define APPLE_RTKIT_SYSLOG_TYPE GENMASK_ULL(59, 52)

drivers/soc/apple/rtkit.c

66

#define APPLE_RTKIT_SYSLOG_N_ENTRIES GENMASK_ULL(7, 0)

drivers/soc/apple/rtkit.c

67

#define APPLE_RTKIT_SYSLOG_MSG_SIZE GENMASK_ULL(31, 24)

drivers/soc/apple/rtkit.c

69

#define APPLE_RTKIT_OSLOG_TYPE GENMASK_ULL(63, 56)

drivers/soc/apple/rtkit.c

71

#define APPLE_RTKIT_OSLOG_SIZE GENMASK_ULL(55, 36)

drivers/soc/apple/rtkit.c

72

#define APPLE_RTKIT_OSLOG_IOVA GENMASK_ULL(35, 0)

drivers/soc/ti/k3-ringacc.c

1097

*elem &= GENMASK_ULL(K3_ADDRESS_ASEL_SHIFT - 1, 0);

drivers/soundwire/amd_manager.h

133

#define AMD_SDW_MCP_SLAVE_STAT_4_11 GENMASK_ULL(39, 24)

drivers/soundwire/amd_manager.h

136

#define AMD_SDW_MCP_SLAVE_STATUS_8TO_11 GENMASK_ULL(15, 0)

drivers/spi/spi-altera-dfl.c

32

#define DATA_WIDTH GENMASK_ULL(7, 2)

drivers/spi/spi-altera-dfl.c

33

#define NUM_CHIPSELECT GENMASK_ULL(13, 8)

drivers/spi/spi-altera-dfl.c

36

#define PERIPHERAL_ID GENMASK_ULL(47, 32)

drivers/spi/spi-altera-dfl.c

37

#define SPI_CLK GENMASK_ULL(31, 22)

drivers/spi/spi-altera-dfl.c

44

#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)

drivers/spi/spi-fsi.c

40

#define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44)

drivers/spi/spi-fsi.c

42

#define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52)

drivers/spi/spi-fsi.c

55

(GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))

drivers/spi/spi-fsi.c

56

#define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48)

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

134

mask = GENMASK_ULL(ptc_mmio_regs[index].shift + ptc_mmio_regs[index].bits - 1,

drivers/thermal/intel/int340x_thermal/processor_thermal_device.h

104

#define SOC_WT_RES_INT_STATUS_MASK GENMASK_ULL(3, 2)

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

113

#define WLT_TW_MASK GENMASK_ULL(30, 24)

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

21

#define MMIO_POWER_LIMIT2_MASK GENMASK_ULL(46, 32)

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

30

#define MMIO_TIME_WINDOW1_MASK GENMASK_ULL(23, 17)

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

31

#define MMIO_TIME_WINDOW2_MASK GENMASK_ULL(55, 49)

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

33

#define MMIO_POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

34

#define MMIO_POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

35

#define MMIO_POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)

drivers/thermal/intel/int340x_thermal/processor_thermal_soc_slider.c

175

#define SLIDER_OFFSET_MASK GENMASK_ULL(6, 4)

drivers/thermal/intel/int340x_thermal/processor_thermal_soc_slider.c

47

#define SLIDER_MASK GENMASK_ULL(2, 0)

drivers/thermal/intel/int340x_thermal/processor_thermal_wt_hint.c

35

#define SOC_WT GENMASK_ULL(47, 40)

drivers/tty/serial/8250/8250_dfl.c

27

#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32)

drivers/tty/serial/8250/8250_dfl.c

28

#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0)

drivers/ufs/core/ufs-mcq.c

30

#define CQE_UCD_BA GENMASK_ULL(63, 7)

drivers/usb/dwc3/dwc3-octeon.c

133

# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK_ULL(59, 48)

drivers/usb/dwc3/dwc3-octeon.c

135

# define USBDRD_UCTL_HOST_CFG_FLA GENMASK_ULL(37, 32)

drivers/usb/dwc3/dwc3-octeon.c

165

# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK_ULL(59, 48)

drivers/usb/dwc3/dwc3-octeon.c

169

# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK_ULL(43, 40)

drivers/usb/dwc3/dwc3-octeon.c

178

# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)

drivers/usb/dwc3/dwc3-octeon.c

185

# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)

drivers/usb/dwc3/dwc3-octeon.c

38

# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)

drivers/usb/dwc3/dwc3-octeon.c

47

# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK_ULL(58, 56)

drivers/usb/dwc3/dwc3-octeon.c

52

# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK_ULL(55, 47)

drivers/usb/dwc3/dwc3-octeon.c

59

# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)

drivers/usb/dwc3/dwc3-octeon.c

76

# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)

drivers/usb/dwc3/dwc3-octeon.c

96

# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)

drivers/usb/host/xhci.h

201

#define CMD_RING_PTR_MASK GENMASK_ULL(63, 6)

drivers/usb/host/xhci.h

262

#define ERST_BASE_ADDRESS_MASK GENMASK_ULL(63, 6)

drivers/usb/host/xhci.h

276

#define ERST_PTR_MASK GENMASK_ULL(63, 4)

drivers/usb/host/xhci.h

507

#define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4)

drivers/vdpa/octeon_ep/octep_vdpa.h

36

#define OCTEP_VF_IN_CTRL_RPVF(val) (FIELD_GET(GENMASK_ULL(51, 48), val))

drivers/vdpa/octeon_ep/octep_vdpa_main.c

838

rpvf = FIELD_GET(GENMASK_ULL(35, 32), val);

drivers/watchdog/marvell_gti_wdt.c

40

#define GTI_CWD_WDOG_MODE_MASK GENMASK_ULL(1, 0)

drivers/watchdog/marvell_gti_wdt.c

42

#define GTI_CWD_WDOG_LEN_MASK GENMASK_ULL(19, 4)

drivers/watchdog/marvell_gti_wdt.c

44

#define GTI_CWD_WDOG_CNT_MASK GENMASK_ULL(43, 20)

drivers/watchdog/sbsa_gwdt.c

334

wdd->max_hw_heartbeat_ms = GENMASK_ULL(47, 0) / gwdt->clk * 1000;

drivers/watchdog/xilinx_wwdt.c

42

#define XWWDT_MAX_COUNT_WINDOW_COMBINED GENMASK_ULL(32, 1)

fs/erofs/internal.h

228

return ((nid << 1) & GENMASK_ULL(63, 32)) | (nid & GENMASK(30, 0)) |

fs/proc/task_mmu.c

1950

#define PM_PFRAME_MASK GENMASK_ULL(PM_PFRAME_BITS - 1, 0)

fs/resctrl/ctrlmondata.c

647

frac = val & GENMASK_ULL(binary_bits - 1, 0);

include/asm-generic/mshyperv.h

266

vpset->valid_bank_mask = GENMASK_ULL(nr_bank - 1, 0);

include/drm/drm_gem_framebuffer_helper.h

17

#define AFBC_VENDOR_AND_TYPE_MASK GENMASK_ULL(63, 52)

include/drm/intel/mchbar_regs.h

211

#define PKG_PKG_TDP GENMASK_ULL(14, 0)

include/drm/intel/mchbar_regs.h

212

#define PKG_MIN_PWR GENMASK_ULL(30, 16)

include/drm/intel/mchbar_regs.h

213

#define PKG_MAX_PWR GENMASK_ULL(46, 32)

include/drm/intel/mchbar_regs.h

214

#define PKG_MAX_WIN GENMASK_ULL(54, 48)

include/drm/intel/mchbar_regs.h

215

#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)

include/drm/intel/mchbar_regs.h

216

#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)

include/hyperv/hvgdk_mini.h

508

#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0)

include/hyperv/hvgdk_mini.h

511

#define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17)

include/hyperv/hvgdk_mini.h

512

#define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27)

include/hyperv/hvgdk_mini.h

516

#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32)

include/hyperv/hvgdk_mini.h

517

#define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44)

include/hyperv/hvgdk_mini.h

519

#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48)

include/hyperv/hvgdk_mini.h

520

#define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60)

include/kvm/arm_arch_timer.h

151

#define CNTKCTL_VALID_BITS (BIT(17) | GENMASK_ULL(9, 0))

include/linux/arm_ffa.h

384

#define HANDLE_LOW_MASK GENMASK_ULL(31, 0)

include/linux/arm_ffa.h

385

#define HANDLE_HIGH_MASK GENMASK_ULL(63, 32)

include/linux/clocksource.h

177

#define CLOCKSOURCE_MASK(bits) GENMASK_ULL((bits) - 1, 0)

include/linux/coresight-pmu.h

36

#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)

include/linux/coresight-pmu.h

37

#define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)

include/linux/coresight-pmu.h

39

#define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)

include/linux/coresight-pmu.h

40

#define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)

include/linux/dma-mapping.h

118

#define DMA_BIT_MASK(n) GENMASK_ULL((n) - 1, 0)

include/linux/gpu_buddy.h

101

#define GPU_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)

include/linux/gpu_buddy.h

102

#define GPU_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)

include/linux/gpu_buddy.h

106

#define GPU_BUDDY_HEADER_CLEAR GENMASK_ULL(9, 9)

include/linux/gpu_buddy.h

108

#define GPU_BUDDY_HEADER_UNUSED GENMASK_ULL(8, 6)

include/linux/gpu_buddy.h

109

#define GPU_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0)

include/linux/i3c/device.h

90

#define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)

include/linux/i3c/device.h

92

#define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))

include/linux/i3c/device.h

93

#define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)

include/linux/i3c/device.h

94

#define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)

include/linux/i3c/device.h

95

#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))

include/linux/irqchip/arm-gic-v3.h

173

#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))

include/linux/irqchip/arm-gic-v3.h

199

#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))

include/linux/irqchip/arm-gic-v3.h

200

#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))

include/linux/irqchip/arm-gic-v3.h

248

#define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)

include/linux/irqchip/arm-gic-v3.h

249

#define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)

include/linux/irqchip/arm-gic-v3.h

251

#define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)

include/linux/irqchip/arm-gic-v3.h

252

#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)

include/linux/irqchip/arm-gic-v3.h

253

#define GICR_INVLPIR_V GENMASK_ULL(63, 63)

include/linux/irqchip/arm-gic-v3.h

300

#define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)

include/linux/irqchip/arm-gic-v3.h

302

#define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)

include/linux/irqchip/arm-gic-v3.h

304

#define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)

include/linux/irqchip/arm-gic-v3.h

305

#define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)

include/linux/irqchip/arm-gic-v3.h

348

#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)

include/linux/irqchip/arm-gic-v3.h

384

#define GITS_SGIR_VPEID GENMASK_ULL(47, 32)

include/linux/irqchip/arm-gic-v3.h

385

#define GITS_SGIR_VINTID GENMASK_ULL(3, 0)

include/linux/irqchip/arm-gic-v3.h

396

#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)

include/linux/irqchip/arm-gic-v3.h

397

#define GITS_TYPER_IDBITS GENMASK_ULL(12, 8)

include/linux/irqchip/arm-gic-v3.h

400

#define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)

include/linux/irqchip/arm-gic-v3.h

406

#define GITS_TYPER_SVPET GENMASK_ULL(42, 41)

include/linux/irqchip/arm-gic-v3.h

437

#define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))

include/linux/irqchip/arm-gic-v3.h

467

#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)

include/linux/irqchip/arm-gic-v3.h

469

(((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)

include/linux/irqchip/arm-gic-v3.h

471

(((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)

include/linux/irqchip/arm-gic-v5.h

169

#define GICV5_IRS_IST_BASER_ADDR_MASK GENMASK_ULL(55, 6)

include/linux/irqchip/arm-gic-v5.h

176

#define GICV5_ISTL1E_L2_ADDR_MASK GENMASK_ULL(55, 12)

include/linux/irqchip/arm-gic-v5.h

21

#define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)

include/linux/irqchip/arm-gic-v5.h

220

#define GICV5_ITS_DT_BASER_ADDR_MASK GENMASK_ULL(55, 3)

include/linux/irqchip/arm-gic-v5.h

226

#define GICV5_ITS_DIDR_DEVICEID GENMASK_ULL(31, 0)

include/linux/irqchip/arm-gic-v5.h

238

#define GICV5_ITS_SYNCR_DEVICEID GENMASK_ULL(31, 0)

include/linux/irqchip/arm-gic-v5.h

244

#define GICV5_DTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3)

include/linux/irqchip/arm-gic-v5.h

245

#define GICV5_DTL1E_SPAN GENMASK_ULL(63, 60)

include/linux/irqchip/arm-gic-v5.h

248

#define GICV5_DTL2E_ITT_L2SZ GENMASK_ULL(2, 1)

include/linux/irqchip/arm-gic-v5.h

250

#define GICV5_DTL2E_ITT_ADDR_MASK GENMASK_ULL(55, 3)

include/linux/irqchip/arm-gic-v5.h

253

#define GICV5_DTL2E_EVENT_ID_BITS GENMASK_ULL(63, 59)

include/linux/irqchip/arm-gic-v5.h

257

#define GICV5_ITTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3)

include/linux/irqchip/arm-gic-v5.h

258

#define GICV5_ITTL1E_SPAN GENMASK_ULL(63, 60)

include/linux/irqchip/arm-gic-v5.h

260

#define GICV5_ITTL2E_LPI_ID GENMASK_ULL(23, 0)

include/linux/irqchip/arm-gic-v5.h

261

#define GICV5_ITTL2E_DAC GENMASK_ULL(29, 28)

include/linux/irqchip/arm-gic-v5.h

264

#define GICV5_ITTL2E_VM_ID GENMASK_ULL(47, 32)

include/linux/irqchip/arm-gic-v5.h

273

#define GICV5_ITS_HWIRQ_DEVICE_ID GENMASK_ULL(31, 0)

include/linux/irqchip/arm-gic-v5.h

274

#define GICV5_ITS_HWIRQ_EVENT_ID GENMASK_ULL(63, 32)

include/linux/mfd/idtRC38xxx_reg.h

121

#define COARSE_MEAS_MASK GENMASK_ULL(39, 13)

include/linux/mfd/idtRC38xxx_reg.h

54

#define SYNC_COUNTER_MASK GENMASK_ULL(51, 0)

include/linux/perf/arm_pmu.h

216

((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))

include/linux/perf/arm_pmuv3.h

240

#define ARMV8_PMU_EVTYPE_TH GENMASK_ULL(43, 32) /* arm64 only */

include/linux/perf/arm_pmuv3.h

241

#define ARMV8_PMU_EVTYPE_TC GENMASK_ULL(63, 61) /* arm64 only */

include/linux/psp-sev.h

28

#define SNP_POLICY_MASK_API_MINOR GENMASK_ULL(7, 0)

include/linux/psp-sev.h

29

#define SNP_POLICY_MASK_API_MAJOR GENMASK_ULL(15, 8)

include/linux/screen_info.h

35

si->lfb_base = lfb_base & GENMASK_ULL(31, 0);

include/linux/screen_info.h

36

si->ext_lfb_base = (lfb_base & GENMASK_ULL(63, 32)) >> 32;

include/linux/soundwire/sdw.h

509

#define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48)

include/linux/soundwire/sdw.h

510

#define SDW_VERSION_MASK GENMASK_ULL(47, 44)

include/linux/soundwire/sdw.h

511

#define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40)

include/linux/soundwire/sdw.h

512

#define SDW_MFG_ID_MASK GENMASK_ULL(39, 24)

include/linux/soundwire/sdw.h

513

#define SDW_PART_ID_MASK GENMASK_ULL(23, 8)

include/linux/soundwire/sdw.h

514

#define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0)

include/media/media-entity.h

43

#define MEDIA_ID_MASK GENMASK_ULL(MEDIA_BITS_PER_ID - 1, 0)

include/net/cfg80211.h

8273

u64 mask = GENMASK_ULL(max_bssid - 1, 0);

include/net/libeth/xdp.h

487

.opts = ((flen) | FIELD_PREP(GENMASK_ULL(63, 32), (__VA_ARGS__ + 0)))

include/rdma/iba.h

138

field_struct, byte_offset, GENMASK_ULL(63, 0), 64

include/uapi/linux/sev-guest.h

89

#define SNP_GUEST_FW_ERR_MASK GENMASK_ULL(31, 0)

lib/842/842_compress.c

164

return add_bits(p, d & GENMASK_ULL(s - 1, 0), s);

lib/842/842_decompress.c

118

*d &= GENMASK_ULL(n - 1, 0);

lib/bitmap.c

894

buf[-1] &= GENMASK_ULL((nbits - 1) % 64, 0);

lib/packing.c

135

proj_mask = GENMASK_ULL(proj_start_bit, proj_end_bit);

lib/packing.c

246

proj_mask = GENMASK_ULL(proj_start_bit, proj_end_bit);

lib/test_bitmap.c

698

(arr[(nbits - 1) / 64] & ~GENMASK_ULL((nbits - 1) % 64, 0))) {

lib/test_bitmap.c

701

GENMASK_ULL((nbits - 1) % 64, 0));

lib/tests/scanf_kunit.c

269

return val & GENMASK_ULL(n_bits, 0);

lib/tests/test_bits.c

23

static_assert(assert_type(unsigned long long, GENMASK_ULL(63, 0)) == U64_MAX);

lib/tests/test_bits.c

76

KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0));

lib/tests/test_bits.c

77

KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0));

lib/tests/test_bits.c

78

KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21));

lib/tests/test_bits.c

79

KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0));

lib/tests/test_bits.c

83

GENMASK_ULL(0, 1);

lib/tests/test_bits.c

84

GENMASK_ULL(0, 10);

lib/tests/test_bits.c

85

GENMASK_ULL(9, 10);

net/ethtool/features.c

50

all_features = GENMASK_ULL(NETDEV_FEATURE_COUNT - 1, 0);

net/mac80211/mlme.c

7862

mask = GENMASK_ULL(25, 10);

net/mptcp/options.c

1011

cur_seq = (old_seq & GENMASK_ULL(63, 32)) + cur_seq32;

net/mptcp/subflow.c

1187

data_fin_seq &= GENMASK_ULL(31, 0);

sound/soc/mediatek/common/mtk-afe-platform-driver.h

15

#define MTK_ALIGN_16BYTES(x) ((x) & GENMASK_ULL(39, 4))

sound/soc/sof/intel/atom.h

44

#define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)

tools/arch/arm64/include/asm/esr.h

161

#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))

tools/arch/arm64/include/asm/esr.h

80

#define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))

tools/arch/arm64/include/asm/sysreg.h

340

#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)

tools/arch/arm64/include/asm/sysreg.h

341

#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))

tools/arch/arm64/include/asm/sysreg.h

344

#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)

tools/arch/arm64/include/asm/sysreg.h

348

#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)

tools/arch/arm64/include/asm/sysreg.h

349

#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)

tools/arch/arm64/include/asm/sysreg.h

350

#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))

tools/arch/arm64/include/asm/sysreg.h

354

(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\

tools/arch/x86/include/asm/msr-index.h

285

#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9)

tools/arch/x86/include/asm/msr-index.h

303

#define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)

tools/arch/x86/include/asm/msr-index.h

304

#define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)

tools/arch/x86/include/asm/msr-index.h

748

#define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19)

tools/arch/x86/include/asm/msr-index.h

752

#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)

tools/arch/x86/include/asm/msr-index.h

763

#define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8)

tools/arch/x86/include/asm/msr-index.h

780

#define AMD_CPPC_FLOOR_PERF_CNT_MASK GENMASK_ULL(39, 32)

tools/include/linux/coresight-pmu.h

36

#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)

tools/include/linux/coresight-pmu.h

37

#define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8)

tools/include/linux/coresight-pmu.h

39

#define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)

tools/include/linux/coresight-pmu.h

40

#define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c

47

return 1U << ((hdr & GENMASK_ULL(5, 4)) >> 4);

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

122

#define SPE_OP_PKT_HDR_CLASS(h) ((h) & GENMASK_ULL(1, 0))

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

127

#define SPE_OP_PKT_OTHER_SUBCLASS_OTHER(v) (((v) & GENMASK_ULL(7, 3)) == 0x0)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

141

#define SPE_OP_PKG_SME_ETS(v) (128 << (FIELD_GET(GENMASK_ULL(6, 4), (v)) << 1 | \

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

144

#define SPE_OP_PKT_LDST_SUBCLASS_GP_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x0)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

145

#define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP(v) (((v) & GENMASK_ULL(7, 1)) == 0x4)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

146

#define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x10)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

147

#define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG(v) (((v) & GENMASK_ULL(7, 1)) == 0x30)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

148

#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG(v) (((v) & GENMASK_ULL(7, 1)) == 0x14)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

149

#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY(v) (((v) & GENMASK_ULL(7, 1)) == 0x20)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

150

#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET(v) (((v) & GENMASK_ULL(7, 0)) == 0x25)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

152

#define SPE_OP_PKT_LDST_SUBCLASS_EXTENDED(v) (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

169

#define SPE_OP_PKG_SVE_EVL(v) (32 << (((v) & GENMASK_ULL(6, 4)) >> 4))

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

173

#define SPE_OP_PKT_LDST_SUBCLASS_GCS(v) (((v) & (GENMASK_ULL(7, 3) | BIT(1))) == 0x40)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

177

#define SPE_OP_PKT_CR_MASK GENMASK_ULL(4, 3)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

46

#define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

50

#define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

56

#define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

61

#define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

62

#define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

74

#define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

75

#define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

78

#define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

80

#define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h

88

#define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))

tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c

1025

CVAL_MAX = GENMASK_ULL(width - 1, 0);

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

377

unimp_mask = GENMASK_ULL(ARMV8_PMU_MAX_GENERAL_COUNTERS - 1, pmcr_n);

tools/testing/selftests/kvm/include/arm64/gic_v3.h

173

#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))

tools/testing/selftests/kvm/include/arm64/gic_v3.h

199

#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))

tools/testing/selftests/kvm/include/arm64/gic_v3.h

200

#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))

tools/testing/selftests/kvm/include/arm64/gic_v3.h

248

#define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

249

#define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

251

#define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

252

#define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

253

#define GICR_INVLPIR_V GENMASK_ULL(63, 63)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

300

#define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

302

#define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

304

#define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

305

#define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

348

#define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

384

#define GITS_SGIR_VPEID GENMASK_ULL(47, 32)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

385

#define GITS_SGIR_VINTID GENMASK_ULL(3, 0)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

396

#define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

399

#define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

405

#define GITS_TYPER_SVPET GENMASK_ULL(42, 41)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

436

#define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))

tools/testing/selftests/kvm/include/arm64/gic_v3.h

466

#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

468

(((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)

tools/testing/selftests/kvm/include/arm64/gic_v3.h

470

(((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

29

#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

30

#define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

32

#define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

35

#define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

36

#define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

39

#define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

41

#define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

45

#define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

46

#define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

50

#define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

51

#define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

55

#define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

56

#define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

59

#define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

60

#define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

61

#define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

64

#define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

65

#define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

70

#define GICV5_GICR_CDIA_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

71

#define GICV5_GICR_CDIA_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

72

#define GICV5_GICR_CDIA_INTID GENMASK_ULL(31, 0)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

77

#define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29)

tools/testing/selftests/kvm/include/arm64/gic_v5.h

78

#define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0)

tools/testing/selftests/kvm/include/x86/pmu.h

29

#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0)

tools/testing/selftests/kvm/include/x86/pmu.h

30

#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8)

tools/testing/selftests/kvm/include/x86/pmu.h

39

#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24)

tools/testing/selftests/kvm/include/x86/processor.h

386

#define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12)

tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c

117

u64 mask = GENMASK_ULL(h, l);

tools/testing/selftests/kvm/x86/msrs_test.c

91

return want & GENMASK_ULL(31, 0);

tools/testing/selftests/kvm/x86/pmu_counters_test.c

483

GUEST_ASSERT_EQ(global_ctrl, GENMASK_ULL(nr_gp_counters - 1, 0));

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

727

f.fixed_counter_bitmap = ~GENMASK_ULL(nr_fixed_counters, 0);

tools/testing/selftests/kvm/x86/vmx_msrs_test.c

43

vmx_fixed0_msr_test(vcpu, msr_index, GENMASK_ULL(31, 0));

tools/testing/selftests/kvm/x86/vmx_msrs_test.c

44

vmx_fixed1_msr_test(vcpu, msr_index, GENMASK_ULL(63, 32));

tools/testing/selftests/kvm/x86/vmx_msrs_test.c

56

BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) |

tools/testing/selftests/kvm/x86/xapic_state_test.c

35

#define X2APIC_RSVD_BITS_MASK (GENMASK_ULL(31, 20) | \

tools/testing/selftests/kvm/x86/xapic_state_test.c

36

GENMASK_ULL(17, 16) | \

tools/testing/selftests/kvm/x86/xapic_state_test.c

37

GENMASK_ULL(13, 13))

tools/testing/selftests/sgx/main.c

318

return (low & GENMASK_ULL(31, 12)) +

tools/testing/selftests/sgx/main.c

319

((high & GENMASK_ULL(19, 0)) << 32);