/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Purpose:     PCI Express Port Bus Driver's Internal Data Structures
 *
 * Copyright (C) 2004 Intel
 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
 */

#ifndef _PORTDRV_H_
#define _PORTDRV_H_

#include <linux/compiler.h>

/* Service Type */
#define PCIE_PORT_SERVICE_PME_SHIFT     0       /* Power Management Event */
#define PCIE_PORT_SERVICE_PME           (1 << PCIE_PORT_SERVICE_PME_SHIFT)
#define PCIE_PORT_SERVICE_AER_SHIFT     1       /* Advanced Error Reporting */
#define PCIE_PORT_SERVICE_AER           (1 << PCIE_PORT_SERVICE_AER_SHIFT)
#define PCIE_PORT_SERVICE_HP_SHIFT      2       /* Native Hotplug */
#define PCIE_PORT_SERVICE_HP            (1 << PCIE_PORT_SERVICE_HP_SHIFT)
#define PCIE_PORT_SERVICE_DPC_SHIFT     3       /* Downstream Port Containment */
#define PCIE_PORT_SERVICE_DPC           (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
#define PCIE_PORT_SERVICE_BWCTRL_SHIFT  4       /* Bandwidth Controller (notifications) */
#define PCIE_PORT_SERVICE_BWCTRL        (1 << PCIE_PORT_SERVICE_BWCTRL_SHIFT)

#define PCIE_PORT_DEVICE_MAXSERVICES   5

extern bool pcie_ports_dpc_native;

#ifdef CONFIG_PCIEAER
int pcie_aer_init(void);
#else
static inline int pcie_aer_init(void) { return 0; }
#endif

#ifdef CONFIG_HOTPLUG_PCI_PCIE
int pcie_hp_init(void);
#else
static inline int pcie_hp_init(void) { return 0; }
#endif

#ifdef CONFIG_PCIE_PME
int pcie_pme_init(void);
#else
static inline int pcie_pme_init(void) { return 0; }
#endif

#ifdef CONFIG_PCIE_DPC
int pcie_dpc_init(void);
#else
static inline int pcie_dpc_init(void) { return 0; }
#endif

int pcie_bwctrl_init(void);

/* Port Type */
#define PCIE_ANY_PORT                   (~0)

struct pcie_device {
        int             irq;        /* Service IRQ/MSI/MSI-X Vector */
        struct pci_dev *port;       /* Root/Upstream/Downstream Port */
        u32             service;    /* Port service this device represents */
        void            *priv_data; /* Service Private Data */
        struct device   device;     /* Generic Device Interface */
};
#define to_pcie_device(d) container_of(d, struct pcie_device, device)

static inline void set_service_data(struct pcie_device *dev, void *data)
{
        dev->priv_data = data;
}

static inline void *get_service_data(struct pcie_device *dev)
{
        return dev->priv_data;
}

struct pcie_port_service_driver {
        const char *name;
        int (*probe)(struct pcie_device *dev);
        void (*remove)(struct pcie_device *dev);
        int (*suspend)(struct pcie_device *dev);
        int (*resume_noirq)(struct pcie_device *dev);
        int (*resume)(struct pcie_device *dev);
        int (*runtime_suspend)(struct pcie_device *dev);
        int (*runtime_resume)(struct pcie_device *dev);

        int (*slot_reset)(struct pcie_device *dev);

        int port_type;  /* Type of the port this driver can handle */
        u32 service;    /* Port service this device represents */

        struct device_driver driver;
};
#define to_service_driver(d) \
        container_of(d, struct pcie_port_service_driver, driver)

int pcie_port_service_register(struct pcie_port_service_driver *new);
void pcie_port_service_unregister(struct pcie_port_service_driver *new);

extern const struct bus_type pcie_port_bus_type;

struct pci_dev;

#ifdef CONFIG_PCIE_PME
extern bool pcie_pme_msi_disabled;

static inline void pcie_pme_disable_msi(void)
{
        pcie_pme_msi_disabled = true;
}

static inline bool pcie_pme_no_msi(void)
{
        return pcie_pme_msi_disabled;
}

void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
#else /* !CONFIG_PCIE_PME */
static inline void pcie_pme_disable_msi(void) {}
static inline bool pcie_pme_no_msi(void) { return false; }
static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
#endif /* !CONFIG_PCIE_PME */

struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);

struct aer_err_info;

#ifdef CONFIG_CXL_RAS
bool is_aer_internal_error(struct aer_err_info *info);
void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info);
void cxl_rch_enable_rcec(struct pci_dev *rcec);
#else
static inline bool is_aer_internal_error(struct aer_err_info *info) { return false; }
static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { }
static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { }
#endif /* CONFIG_CXL_RAS */
#endif /* _PORTDRV_H_ */