arch/arm/mach-orion5x/ts78xx-setup.c

153

const uint8_t *buf, int len)

arch/arm/mach-orion5x/ts78xx-setup.c

179

uint8_t *buf, int len)

arch/arm/mach-pxa/spitz.c

215

static void __maybe_unused spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)

arch/arm/mach-pxa/spitz.c

246

static inline void spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}

arch/arm/mach-pxa/spitz.c

834

static uint8_t scan_ff_pattern[] = { 0xff, 0xff };

arch/loongarch/include/asm/image.h

27

uint8_t dos_sig[2];

arch/loongarch/include/asm/kvm_eiointc.h

78

uint8_t sw_coremap[EIOINTC_IRQS];

arch/loongarch/include/asm/kvm_pch_pic.h

42

uint8_t reserved_0[3];

arch/loongarch/include/asm/kvm_pch_pic.h

43

uint8_t id;

arch/loongarch/include/asm/kvm_pch_pic.h

44

uint8_t version;

arch/loongarch/include/asm/kvm_pch_pic.h

45

uint8_t reserved_1;

arch/loongarch/include/asm/kvm_pch_pic.h

46

uint8_t irq_num;

arch/loongarch/include/asm/kvm_pch_pic.h

47

uint8_t reserved_2;

arch/loongarch/include/asm/kvm_pch_pic.h

66

uint8_t route_entry[64]; /* default value 0, route to int0: eiointc */

arch/loongarch/include/asm/kvm_pch_pic.h

67

uint8_t htmsi_vector[64]; /* irq route table for routing to eiointc */

arch/mips/boot/tools/relocs_64.c

11

typedef uint8_t Elf64_Byte;

arch/mips/cavium-octeon/executive/octeon-model.c

40

static uint8_t __init cvmx_fuse_read_byte(int byte_addr)

arch/mips/cavium-octeon/octeon-irq.c

2996

struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block)

arch/mips/include/asm/elf.h

193

uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */

arch/mips/include/asm/elf.h

194

uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below,

arch/mips/include/asm/elf.h

196

uint8_t gpr_size; /* The size of general purpose registers */

arch/mips/include/asm/elf.h

197

uint8_t cpr1_size; /* The size of co-processor 1 registers */

arch/mips/include/asm/elf.h

198

uint8_t cpr2_size; /* The size of co-processor 2 registers */

arch/mips/include/asm/elf.h

199

uint8_t fp_abi; /* The floating-point ABI */

arch/mips/include/asm/module.h

17

typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */

arch/mips/include/asm/octeon/cvmx-bootinfo.h

165

uint8_t reserved3;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

166

uint8_t reserved2;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

168

uint8_t board_rev_minor;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

169

uint8_t board_rev_major;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

173

uint8_t mac_addr_base[6];

arch/mips/include/asm/octeon/cvmx-bootinfo.h

174

uint8_t mac_addr_count;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

175

uint8_t pad[5];

arch/mips/include/asm/octeon/cvmx-bootinfo.h

86

uint8_t board_rev_major;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

87

uint8_t board_rev_minor;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

89

uint8_t reserved2;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

90

uint8_t reserved3;

arch/mips/include/asm/octeon/cvmx-bootinfo.h

92

uint8_t mac_addr_base[6];

arch/mips/include/asm/octeon/cvmx-bootinfo.h

93

uint8_t mac_addr_count;

arch/mips/include/asm/octeon/cvmx-cmd-queue.h

130

uint8_t now_serving;

arch/mips/include/asm/octeon/cvmx-pow.h

1874

const uint8_t priority[])

arch/mips/include/asm/octeon/cvmx-scratch.h

100

*CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) =

arch/mips/include/asm/octeon/cvmx-scratch.h

101

(uint8_t) value;

arch/mips/include/asm/octeon/cvmx-scratch.h

51

static inline uint8_t cvmx_scratch_read8(uint64_t address)

arch/mips/include/asm/octeon/cvmx-scratch.h

53

return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);

arch/mips/include/asm/octeon/cvmx-sysinfo.h

111

uint8_t console_uart_num;

arch/mips/include/asm/octeon/cvmx-sysinfo.h

82

uint8_t board_rev_major;

arch/mips/include/asm/octeon/cvmx-sysinfo.h

83

uint8_t board_rev_minor;

arch/mips/include/asm/octeon/cvmx-sysinfo.h

84

uint8_t mac_addr_base[6];

arch/mips/include/asm/octeon/cvmx-sysinfo.h

85

uint8_t mac_addr_count;

arch/mips/include/asm/octeon/cvmx-wqe.h

415

uint8_t unused;

arch/mips/include/asm/octeon/cvmx-wqe.h

425

uint8_t unused;

arch/mips/include/asm/octeon/cvmx-wqe.h

587

uint8_t packet_data[96];

arch/mips/include/asm/octeon/octeon.h

100

uint8_t board_rev_minor;

arch/mips/include/asm/octeon/octeon.h

102

uint8_t chip_rev_major;

arch/mips/include/asm/octeon/octeon.h

103

uint8_t chip_rev_minor;

arch/mips/include/asm/octeon/octeon.h

105

uint8_t mac_addr_base[6];

arch/mips/include/asm/octeon/octeon.h

106

uint8_t mac_addr_count;

arch/mips/include/asm/octeon/octeon.h

152

uint8_t chip_rev_minor;

arch/mips/include/asm/octeon/octeon.h

153

uint8_t chip_rev_major;

arch/mips/include/asm/octeon/octeon.h

155

uint8_t board_rev_minor;

arch/mips/include/asm/octeon/octeon.h

156

uint8_t board_rev_major;

arch/mips/include/asm/octeon/octeon.h

362

struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block);

arch/mips/include/asm/octeon/octeon.h

99

uint8_t board_rev_major;

arch/mips/mm/cerr-sb1.c

256

static const uint8_t parity[256] = {

arch/mips/mm/cerr-sb1.c

326

uint8_t lru;

arch/mips/mm/cerr-sb1.c

381

uint8_t predecode;

arch/mips/mm/cerr-sb1.c

423

static uint8_t dc_ecc(uint64_t dword)

arch/mips/mm/cerr-sb1.c

427

uint8_t p;

arch/mips/mm/cerr-sb1.c

481

uint8_t ecc, lru;

arch/mips/pci/pcie-octeon.c

271

static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,

arch/mips/pci/pcie-octeon.c

337

int reg, uint8_t val)

arch/mips/sibyte/swarm/rtc_m41t81.c

110

static int m41t81_write(uint8_t addr, int b)

arch/mips/sibyte/swarm/rtc_m41t81.c

83

static int m41t81_read(uint8_t addr)

arch/mips/sibyte/swarm/rtc_xicor1241.c

58

static int xicor_read(uint8_t addr)

arch/mips/sibyte/swarm/rtc_xicor1241.c

86

static int xicor_write(uint8_t addr, int b)

arch/parisc/kernel/perf.c

53

uint8_t num_words;

arch/parisc/kernel/perf.c

54

uint8_t write_control;

arch/powerpc/include/asm/asm-prototypes.h

53

void tm_abort(uint8_t cause);

arch/powerpc/include/asm/hvcall.h

737

uint8_t bytes[HGPCI_MAX_DATA_BYTES];

arch/powerpc/include/asm/hvsi.h

27

uint8_t type;

arch/powerpc/include/asm/hvsi.h

28

uint8_t len;

arch/powerpc/include/asm/hvsi.h

34

uint8_t data[HVSI_MAX_OUTGOING_DATA];

arch/powerpc/include/asm/hvsi.h

55

uint8_t version;

arch/powerpc/include/asm/io_event_irq.h

38

uint8_t event_type; /* 0x00 IO-Event Type */

arch/powerpc/include/asm/io_event_irq.h

39

uint8_t rpc_data_len; /* 0x01 RPC data length */

arch/powerpc/include/asm/io_event_irq.h

40

uint8_t scope; /* 0x02 Error/Event Scope */

arch/powerpc/include/asm/io_event_irq.h

41

uint8_t event_subtype; /* 0x03 I/O-Event Sub-Type */

arch/powerpc/include/asm/io_event_irq.h

43

uint8_t rpc_data[PSERIES_IOEI_RPC_MAX_LEN];

arch/powerpc/include/asm/opal-api.h

1008

uint8_t type;

arch/powerpc/include/asm/opal-api.h

1013

uint8_t flags;

arch/powerpc/include/asm/opal-api.h

1015

uint8_t subaddr_sz; /* Max 4 */

arch/powerpc/include/asm/opal-api.h

1016

uint8_t reserved;

arch/powerpc/include/asm/opal-api.h

484

uint8_t version;

arch/powerpc/include/asm/opal-api.h

485

uint8_t netfn;

arch/powerpc/include/asm/opal-api.h

486

uint8_t cmd;

arch/powerpc/include/asm/opal-api.h

487

uint8_t data[];

arch/powerpc/include/asm/opal-api.h

516

uint8_t reserved_1[4]; /* 0x04 */

arch/powerpc/include/asm/opal-api.h

522

uint8_t reserved_1[7];

arch/powerpc/include/asm/opal-api.h

529

uint8_t reserved_1[7];

arch/powerpc/include/asm/opal-api.h

615

uint8_t version; /* 0x00 */

arch/powerpc/include/asm/opal-api.h

616

uint8_t severity; /* 0x01 */

arch/powerpc/include/asm/opal-api.h

617

uint8_t type; /* 0x02 */

arch/powerpc/include/asm/opal-api.h

618

uint8_t disposition; /* 0x03 */

arch/powerpc/include/asm/opal-api.h

619

uint8_t reserved_1[4]; /* 0x04 */

arch/powerpc/include/asm/opal-api.h

632

uint8_t xstop_type; /* enum OpalHMI_XstopType */

arch/powerpc/include/asm/opal-api.h

633

uint8_t reserved_1[3];

arch/powerpc/include/asm/opal-api.h

690

uint8_t biDownbound; /* BI Downbound or Upbound */

arch/powerpc/include/asm/opal-api.h

696

uint8_t ciPort; /* Index of CI port: 0/1 */

arch/powerpc/include/asm/opal-api.h

948

uint8_t type;

arch/powerpc/include/asm/opal-api.h

949

uint8_t pad[1];

arch/powerpc/include/asm/opal.h

111

uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,

arch/powerpc/include/asm/opal.h

112

uint8_t pe_action);

arch/powerpc/include/asm/opal.h

114

uint8_t state);

arch/powerpc/include/asm/opal.h

116

uint8_t *p_bit, uint8_t *q_bit);

arch/powerpc/include/asm/opal.h

118

uint8_t p_bit, uint8_t q_bit);

arch/powerpc/include/asm/opal.h

125

uint8_t msi_range, __be32 *msi_address,

arch/powerpc/include/asm/opal.h

128

uint32_t xive_num, uint8_t msi_range,

arch/powerpc/include/asm/opal.h

131

int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);

arch/powerpc/include/asm/opal.h

139

int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);

arch/powerpc/include/asm/opal.h

149

int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);

arch/powerpc/include/asm/opal.h

150

int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);

arch/powerpc/include/asm/opal.h

153

int64_t opal_set_system_attention_led(uint8_t led_action);

arch/powerpc/include/asm/opal.h

176

int64_t opal_manage_flash(uint8_t op);

arch/powerpc/include/asm/opal.h

178

int64_t opal_dump_init(uint8_t dump_type);

arch/powerpc/include/asm/opal.h

231

int64_t opal_int_set_cppr(uint8_t cppr);

arch/powerpc/include/asm/opal.h

233

int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);

arch/powerpc/include/asm/opal.h

246

uint8_t *out_prio, __be32 *out_lirq);

arch/powerpc/include/asm/opal.h

247

int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,

arch/powerpc/include/asm/opal.h

41

const uint8_t *buffer);

arch/powerpc/include/asm/opal.h

43

uint8_t *buffer);

arch/powerpc/include/asm/opal.h

66

uint64_t offset, uint8_t *data);

arch/powerpc/include/asm/opal.h

72

uint64_t offset, uint8_t data);

arch/powerpc/include/asm/opal.h

77

int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);

arch/powerpc/include/asm/opal.h

78

int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);

arch/powerpc/include/asm/opal.h

83

uint8_t *freeze_state,

arch/powerpc/include/asm/opal.h

92

int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);

arch/powerpc/include/asm/pnv-pci.h

22

extern int pnv_pci_get_presence_state(uint64_t id, uint8_t *state);

arch/powerpc/include/asm/pnv-pci.h

23

extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state);

arch/powerpc/include/asm/pnv-pci.h

24

extern int pnv_pci_set_power_state(uint64_t id, uint8_t state,

arch/powerpc/include/asm/pnv-pci.h

59

uint8_t state);

arch/powerpc/include/asm/rtas.h

317

static inline uint8_t rtas_error_severity(const struct rtas_error_log *elog)

arch/powerpc/include/asm/rtas.h

322

static inline uint8_t rtas_error_disposition(const struct rtas_error_log *elog)

arch/powerpc/include/asm/rtas.h

334

static inline uint8_t rtas_error_extended(const struct rtas_error_log *elog)

arch/powerpc/include/asm/rtas.h

339

static inline uint8_t rtas_error_initiator(const struct rtas_error_log *elog)

arch/powerpc/include/asm/rtas.h

357

inline uint8_t rtas_ext_event_log_format(struct rtas_ext_event_log_v6 *ext_log)

arch/powerpc/include/asm/tm.h

14

uint8_t cause);

arch/powerpc/include/asm/tm.h

15

extern void tm_reclaim_current(uint8_t cause);

arch/powerpc/kernel/process.c

1151

void tm_reclaim_current(uint8_t cause) {}

arch/powerpc/kernel/process.c

931

static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)

arch/powerpc/kernel/process.c

975

void tm_reclaim_current(uint8_t cause)

arch/powerpc/kernel/rtas.c

1725

uint8_t log_format = rtas_ext_event_log_format(ext_log);

arch/powerpc/kvm/book3s_xive.h

173

uint8_t cppr; /* guest CPPR */

arch/powerpc/kvm/book3s_xive.h

174

uint8_t hw_cppr;/* Hardware CPPR */

arch/powerpc/kvm/book3s_xive.h

175

uint8_t mfrr;

arch/powerpc/kvm/book3s_xive.h

176

uint8_t pending;

arch/powerpc/platforms/512x/clock-commonclk.c

286

static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)

arch/powerpc/platforms/powernv/eeh-powernv.c

858

uint8_t scope;

arch/powerpc/platforms/powernv/opal-dump.c

120

static int64_t dump_fips_init(uint8_t type)

arch/powerpc/platforms/powernv/opal-flash.c

225

static inline void opal_flash_manage(uint8_t op)

arch/powerpc/platforms/powernv/opal-flash.c

256

uint8_t op;

arch/powerpc/platforms/powernv/opal-hmi.c

143

uint8_t reason, reason_count, i;

arch/powerpc/platforms/powernv/opal-hmi.c

180

uint8_t type = hmi_evt->u.xstop_error.xstop_type;

arch/powerpc/platforms/powernv/opal-hmi.c

275

uint8_t disposition;

arch/powerpc/platforms/powernv/pci-ioda.c

609

uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :

arch/powerpc/platforms/powernv/pci-ioda.c

738

uint8_t bcomp, dcomp, fcomp;

arch/powerpc/platforms/powernv/pci-ioda.c

808

uint8_t bcomp, dcomp, fcomp;

arch/powerpc/platforms/powernv/pci.c

107

int pnv_pci_get_power_state(uint64_t id, uint8_t *state)

arch/powerpc/platforms/powernv/pci.c

122

int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg)

arch/powerpc/platforms/powernv/pci.c

92

int pnv_pci_get_presence_state(uint64_t id, uint8_t *state)

arch/powerpc/platforms/powernv/setup.c

402

uint8_t status;

arch/powerpc/platforms/powernv/smp.c

71

uint8_t status;

arch/powerpc/platforms/ps3/os-area.c

388

uint8_t owner:5;

arch/powerpc/platforms/ps3/os-area.c

389

uint8_t key:3;

arch/powerpc/platforms/pseries/papr_scm.c

606

*(uint8_t *)(hdr->out_buf + data_offset) = (data[0] & 0xff);

arch/powerpc/platforms/pseries/papr_scm.c

645

data_be = *(uint8_t *)(hdr->in_buf + data_offset);

arch/riscv/purgatory/purgatory.c

29

sha256_update(&sctx, (uint8_t *)(ptr->start), ptr->len);

arch/s390/kvm/dat.c

1305

unsigned long count, unsigned long mask, const uint8_t *bits)

arch/s390/kvm/dat.h

549

unsigned long count, unsigned long mask, const uint8_t *bits);

arch/s390/kvm/intercept.c

58

uint8_t flags, stop_pending;

arch/s390/kvm/kvm-s390.c

2121

r = copy_to_user((uint8_t __user *)args->skeydata_addr, keys,

arch/s390/kvm/kvm-s390.c

2122

sizeof(uint8_t) * args->count);

arch/s390/kvm/kvm-s390.c

2148

r = copy_from_user(keys, (uint8_t __user *)args->skeydata_addr,

arch/s390/kvm/kvm-s390.c

2149

sizeof(uint8_t) * args->count);

arch/s390/kvm/priv.c

596

uint8_t fc;

arch/s390/purgatory/purgatory.c

25

sha256_update(&sctx, (uint8_t *)(ptr->start), ptr->len);

arch/um/drivers/vector_kern.h

114

int (*form_header)(uint8_t *header,

arch/um/drivers/vector_kern.h

116

int (*verify_header)(uint8_t *header,

arch/um/drivers/vector_transports.c

114

static int raw_form_header(uint8_t *header,

arch/um/drivers/vector_transports.c

131

uint8_t *header, struct sk_buff *skb, struct vector_private *vp)

arch/um/drivers/vector_transports.c

166

uint8_t *header, struct sk_buff *skb, struct vector_private *vp)

arch/um/drivers/vector_transports.c

197

uint8_t *header, struct sk_buff *skb, struct vector_private *vp)

arch/um/drivers/vector_transports.c

66

static int l2tpv3_form_header(uint8_t *header,

arch/um/drivers/vector_transports.c

96

static int gre_form_header(uint8_t *header,

arch/x86/crypto/camellia_glue.c

782

y = camellia_sp11101110[(uint8_t)ii]; \

arch/x86/crypto/camellia_glue.c

783

y ^= camellia_sp44044404[(uint8_t)(ii >> 8)]; \

arch/x86/crypto/camellia_glue.c

785

y ^= camellia_sp30333033[(uint8_t)ii]; \

arch/x86/crypto/camellia_glue.c

786

y ^= camellia_sp02220222[(uint8_t)(ii >> 8)]; \

arch/x86/crypto/camellia_glue.c

788

y ^= camellia_sp00444404[(uint8_t)ii]; \

arch/x86/crypto/camellia_glue.c

789

y ^= camellia_sp03303033[(uint8_t)(ii >> 8)]; \

arch/x86/crypto/camellia_glue.c

791

y ^= camellia_sp22000222[(uint8_t)ii]; \

arch/x86/crypto/camellia_glue.c

792

y ^= camellia_sp10011110[(uint8_t)(ii >> 8)]; \

arch/x86/include/asm/olpc.h

28

static inline uint32_t olpc_board(uint8_t id)

arch/x86/include/asm/olpc.h

33

static inline uint32_t olpc_board_pre(uint8_t id)

arch/x86/include/asm/setup_data.h

18

uint8_t romdata[];

arch/x86/include/asm/string.h

27

: "a" ((uint8_t)v)

arch/x86/include/asm/xen/interface.h

142

uint8_t vector; /* exception vector */

arch/x86/include/asm/xen/interface.h

143

uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */

arch/x86/include/asm/xen/interface.h

313

uint8_t cpl;

arch/x86/include/asm/xen/interface.h

314

uint8_t pad[3];

arch/x86/include/asm/xen/interface.h

343

uint8_t pad[XENPMU_REGS_PAD_SZ];

arch/x86/include/asm/xen/interface.h

375

uint8_t pad[XENPMU_CTXT_PAD_SZ];

arch/x86/include/asm/xen/interface_32.h

61

uint8_t saved_upcall_mask;

arch/x86/include/asm/xen/interface_32.h

62

uint8_t _pad0;

arch/x86/include/asm/xen/interface_64.h

119

uint8_t saved_upcall_mask;

arch/x86/include/asm/xen/interface_64.h

120

uint8_t _pad1[3];

arch/x86/kernel/tboot.c

356

static uint8_t tboot_log_uuid[16] = TBOOT_LOG_UUID;

arch/x86/kvm/svm/sev.c

749

uint8_t *page_virtual;

arch/x86/kvm/xen.c

330

uint8_t *update_bit = NULL;

arch/x86/kvm/xen.h

222

uint8_t evtchn_upcall_pending;

arch/x86/kvm/xen.h

223

uint8_t evtchn_upcall_mask;

arch/x86/mm/init.c

72

static uint8_t __pte2cachemode_tbl[8] = {

arch/x86/pci/olpc.c

244

*value = *(uint8_t *)addr;

arch/x86/purgatory/purgatory.c

34

sha256_update(&sctx, (uint8_t *)(ptr->start), ptr->len);

arch/x86/xen/enlighten_pv.c

1037

iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) +

arch/x86/xen/multicalls.c

108

static const uint8_t hpcpars[] = {

arch/x86/xen/pmu.c

205

uint8_t xenpmu_flags = get_xenpmu_flags();

arch/x86/xen/pmu.c

23

uint8_t flags;

arch/x86/xen/pmu.c

267

uint8_t xenpmu_flags = get_xenpmu_flags();

arch/x86/xen/pmu.c

319

uint8_t xenpmu_flags = get_xenpmu_flags();

arch/x86/xen/pmu.c

341

uint8_t xenpmu_flags = get_xenpmu_flags();

arch/x86/xen/pmu.c

463

uint8_t xenpmu_flags = get_xenpmu_flags();

crypto/aegis128-neon-inner.c

137

static const uint8_t const0[] = {

crypto/aegis128-neon-inner.c

141

static const uint8_t const1[] = {

crypto/aegis128-neon-inner.c

216

static const uint8_t permute[] __aligned(64) = {

crypto/aegis128-neon-inner.c

246

uint8_t buf[AEGIS_BLOCK_SIZE];

crypto/aegis128-neon-inner.c

29

extern const uint8_t crypto_aes_sbox[];

crypto/aegis128-neon-inner.c

292

uint8_t buf[AEGIS_BLOCK_SIZE];

crypto/aegis128-neon-inner.c

58

static const uint8_t shift_rows[] = {

crypto/aegis128-neon-inner.c

62

static const uint8_t ror32by8[] = {

crypto/rsa-pkcs1pad.c

30

uint8_t *in_buf, *out_buf;

drivers/atm/solos-pci.c

1195

uint8_t major_ver, minor_ver;

drivers/auxdisplay/ht16k33.c

140

uint8_t data = REG_DISPLAY_SETUP | REG_DISPLAY_SETUP_ON | priv->blink;

drivers/auxdisplay/ht16k33.c

181

uint8_t blink;

drivers/auxdisplay/ht16k33.c

224

uint8_t *p1, *p2;

drivers/auxdisplay/ht16k33.c

262

uint8_t data[HT16K33_FB_SIZE];

drivers/auxdisplay/ht16k33.c

263

uint8_t byte;

drivers/auxdisplay/ht16k33.c

405

uint8_t buf[9];

drivers/auxdisplay/ht16k33.c

425

uint8_t buf[8];

drivers/auxdisplay/ht16k33.c

85

uint8_t *buffer;

drivers/auxdisplay/ht16k33.c

86

uint8_t *cache;

drivers/auxdisplay/ht16k33.c

99

uint8_t blink;

drivers/block/xen-blkback/blkback.c

934

uint8_t first_sect, last_sect;

drivers/block/xen-blkback/common.h

103

uint8_t indirect_op;

drivers/block/xen-blkback/common.h

121

uint8_t operation; /* BLKIF_OP_??? */

drivers/block/xen-blkback/common.h

133

uint8_t nr_segments; /* number of segments */

drivers/block/xen-blkback/common.h

142

uint8_t flag; /* BLKIF_DISCARD_SECURE or zero */

drivers/block/xen-blkback/common.h

151

uint8_t _pad1;

drivers/block/xen-blkback/common.h

158

uint8_t indirect_op;

drivers/block/xen-blkback/common.h

177

uint8_t operation; /* BLKIF_OP_??? */

drivers/block/xen-blkback/common.h

81

uint8_t nr_segments; /* number of segments */

drivers/block/xen-blkback/common.h

89

uint8_t flag; /* BLKIF_DISCARD_SECURE or zero */

drivers/block/xen-blkback/common.h

97

uint8_t _pad1;

drivers/bluetooth/btqca.c

320

uint8_t nvm_baud_rate = config->user_baud_rate;

drivers/bluetooth/btqca.c

766

int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,

drivers/bluetooth/btqca.h

166

int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,

drivers/bluetooth/btqca.h

180

static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,

drivers/bluetooth/btqca.h

97

uint8_t user_baud_rate;

drivers/bluetooth/hci_ath.c

147

static int ath_vendor_cmd(struct hci_dev *hdev, uint8_t opcode, uint16_t index,

drivers/bluetooth/hci_qca.c

1301

static uint8_t qca_get_baudrate_value(int speed)

drivers/bluetooth/hci_qca.c

1337

static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)

drivers/clk/clk-lmk04832.c

1266

static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)

drivers/clk/clk-lmk04832.c

1278

static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)

drivers/clk/clk-si570.c

201

static const uint8_t si570_hs_div_values[] = { 11, 9, 7, 6, 5, 4 };

drivers/comedi/drivers/ni_routing/tools/convert_c_to_py.c

9

typedef uint8_t u8;

drivers/crypto/amcc/crypto4xx_alg.c

495

uint8_t src[16] = { 0 };

drivers/crypto/caam/ctrl.c

1003

((__force uint8_t *)ctrl +

drivers/crypto/caam/ctrl.c

1007

((__force uint8_t *)ctrl +

drivers/crypto/caam/ctrl.c

1095

((__force uint8_t *)ctrl +

drivers/crypto/caam/ctrl.c

946

((__force uint8_t *)ctrl + reg);

drivers/crypto/ccp/sev-dev.c

2701

sev->cmd_buf_backup = (uint8_t *)sev->cmd_buf + PAGE_SIZE;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

42

memcpy((uint8_t *)msg + sizeof(struct mbox_msghdr),

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

43

(uint8_t *)req + sizeof(struct mbox_msghdr), size);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

548

memcpy((uint8_t *)fwd + sizeof(struct mbox_msghdr),

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

549

(uint8_t *)msg + sizeof(struct mbox_msghdr), size);

drivers/crypto/mxs-dcp.c

104

uint8_t key[AES_KEYSIZE_128];

drivers/crypto/mxs-dcp.c

326

uint8_t *in_buf = sdcp->coh->aes_in_buf;

drivers/crypto/mxs-dcp.c

327

uint8_t *out_buf = sdcp->coh->aes_out_buf;

drivers/crypto/mxs-dcp.c

330

uint8_t *src_buf = NULL;

drivers/crypto/mxs-dcp.c

333

uint8_t *key = sdcp->coh->aes_key;

drivers/crypto/mxs-dcp.c

37

static const uint8_t sha1_null_hash[] =

drivers/crypto/mxs-dcp.c

41

static const uint8_t sha256_null_hash[] =

drivers/crypto/mxs-dcp.c

61

uint8_t aes_in_buf[DCP_BUF_SZ];

drivers/crypto/mxs-dcp.c

62

uint8_t aes_out_buf[DCP_BUF_SZ];

drivers/crypto/mxs-dcp.c

63

uint8_t sha_in_buf[DCP_BUF_SZ];

drivers/crypto/mxs-dcp.c

637

const uint8_t *sha_buf =

drivers/crypto/mxs-dcp.c

64

uint8_t sha_out_buf[DCP_SHA_PAY_SZ];

drivers/crypto/mxs-dcp.c

66

uint8_t aes_key[2 * AES_KEYSIZE_128];

drivers/crypto/mxs-dcp.c

679

uint8_t *in_buf = sdcp->coh->sha_in_buf;

drivers/crypto/mxs-dcp.c

680

uint8_t *out_buf = sdcp->coh->sha_out_buf;

drivers/crypto/padlock-aes.c

77

aes_hw_extkey_available(uint8_t key_len)

drivers/crypto/virtio/virtio_crypto_akcipher_algs.c

100

const uint8_t *key, unsigned int keylen)

drivers/crypto/virtio/virtio_crypto_akcipher_algs.c

104

uint8_t *pkey;

drivers/crypto/virtio/virtio_crypto_common.h

106

uint8_t status;

drivers/crypto/virtio/virtio_crypto_common.h

78

uint8_t dev_id;

drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

111

uint32_t alg, const uint8_t *key,

drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

129

uint8_t *cipher_key = kmemdup(key, keylen, GFP_ATOMIC);

drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

249

const uint8_t *key, unsigned int keylen)

drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

280

const uint8_t *key,

drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

30

uint8_t *iv;

drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

338

uint8_t *iv;

drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c

210

size_t len, uint8_t fmt)

drivers/dma/ioat/hw.h

184

uint8_t coef[8];

drivers/dma/ioat/hw.h

234

uint8_t coef[8];

drivers/dma/moxart-dma.c

126

uint8_t es;

drivers/dma/ti/omap-dma.c

120

uint8_t es; /* CSDP_DATA_TYPE_xxx */

drivers/dma/ti/omap-dma.c

1247

uint8_t data_type;

drivers/dma/ti/omap-dma.c

1294

uint8_t data_type;

drivers/edac/armada_xp_edac.c

133

uint8_t syndrome_val, cs_val;

drivers/edac/armada_xp_edac.c

384

uint8_t inject_ctl;

drivers/edac/armada_xp_edac.c

85

uint8_t cs, uint8_t bank, uint16_t row,

drivers/firmware/broadcom/bcm47xx_nvram.c

166

err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header);

drivers/firmware/imx/imx-scu.c

206

uint8_t saved_svc, saved_func;

drivers/firmware/imx/misc.c

58

hdr->svc = (uint8_t)IMX_SC_RPC_SVC_MISC;

drivers/firmware/imx/misc.c

59

hdr->func = (uint8_t)IMX_SC_MISC_FUNC_SET_CONTROL;

drivers/firmware/imx/misc.c

90

hdr->svc = (uint8_t)IMX_SC_RPC_SVC_MISC;

drivers/firmware/imx/misc.c

91

hdr->func = (uint8_t)IMX_SC_MISC_FUNC_GET_CONTROL;

drivers/firmware/meson/meson_sm.c

257

uint8_t *id_buf;

drivers/firmware/tegra/bpmp-debugfs.c

243

uint8_t *data, size_t sz_data)

drivers/fsi/fsi-core.c

100

uint8_t slave_id, uint32_t addr, const void *val, size_t size);

drivers/fsi/fsi-core.c

1036

static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id)

drivers/fsi/fsi-core.c

1040

uint8_t crc;

drivers/fsi/fsi-core.c

1192

uint8_t slave_id, uint32_t addr, void *val, size_t size)

drivers/fsi/fsi-core.c

1209

uint8_t slave_id, uint32_t addr, const void *val, size_t size)

drivers/fsi/fsi-core.c

227

uint8_t *idp)

drivers/fsi/fsi-core.c

230

uint8_t id = *idp;

drivers/fsi/fsi-core.c

255

uint8_t id;

drivers/fsi/fsi-core.c

332

uint8_t id, send_delay, echo_delay;

drivers/fsi/fsi-core.c

389

uint8_t id = slave->id;

drivers/fsi/fsi-core.c

414

uint8_t id = slave->id;

drivers/fsi/fsi-core.c

511

uint8_t slots, version, type, crc;

drivers/fsi/fsi-core.c

685

int link, uint8_t id)

drivers/fsi/fsi-core.c

699

int link, uint8_t id)

drivers/fsi/fsi-core.c

98

uint8_t slave_id, uint32_t addr, void *val, size_t size);

drivers/fsi/fsi-master-aspeed.c

256

uint8_t id, uint32_t addr, void *val, size_t size)

drivers/fsi/fsi-master-aspeed.c

291

uint8_t id, uint32_t addr, const void *val, size_t size)

drivers/fsi/fsi-master-aspeed.c

354

static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id)

drivers/fsi/fsi-master-ast-cf.c

103

uint8_t gpio_clk_bit;

drivers/fsi/fsi-master-ast-cf.c

104

uint8_t gpio_dat_bit;

drivers/fsi/fsi-master-ast-cf.c

105

uint8_t gpio_tra_bit;

drivers/fsi/fsi-master-ast-cf.c

116

uint8_t t_send_delay;

drivers/fsi/fsi-master-ast-cf.c

117

uint8_t t_echo_delay;

drivers/fsi/fsi-master-ast-cf.c

124

uint8_t bits;

drivers/fsi/fsi-master-ast-cf.c

139

uint8_t crc;

drivers/fsi/fsi-master-ast-cf.c

209

struct fsi_msg *cmd, uint8_t id,

drivers/fsi/fsi-master-ast-cf.c

215

uint8_t ds, opcode;

drivers/fsi/fsi-master-ast-cf.c

268

msg_push_bits(cmd, ((uint8_t *)data)[i], 8);

drivers/fsi/fsi-master-ast-cf.c

274

static void build_dpoll_command(struct fsi_msg *cmd, uint8_t slave_id)

drivers/fsi/fsi-master-ast-cf.c

285

static void build_epoll_command(struct fsi_msg *cmd, uint8_t slave_id)

drivers/fsi/fsi-master-ast-cf.c

296

static void build_term_command(struct fsi_msg *cmd, uint8_t slave_id)

drivers/fsi/fsi-master-ast-cf.c

310

uint8_t stat;

drivers/fsi/fsi-master-ast-cf.c

377

static int read_copro_response(struct fsi_master_acf *master, uint8_t size,

drivers/fsi/fsi-master-ast-cf.c

380

uint8_t rtag = ioread8(master->sram + STAT_RTAG) & 0xf;

drivers/fsi/fsi-master-ast-cf.c

381

uint8_t rcrc = ioread8(master->sram + STAT_RCRC) & 0xf;

drivers/fsi/fsi-master-ast-cf.c

384

uint8_t ack;

drivers/fsi/fsi-master-ast-cf.c

414

static int send_term(struct fsi_master_acf *master, uint8_t slave)

drivers/fsi/fsi-master-ast-cf.c

417

uint8_t tag;

drivers/fsi/fsi-master-ast-cf.c

455

uint8_t v;

drivers/fsi/fsi-master-ast-cf.c

468

uint8_t slave, uint8_t size, void *data)

drivers/fsi/fsi-master-ast-cf.c

474

uint8_t tag;

drivers/fsi/fsi-master-ast-cf.c

571

static int fsi_master_acf_xfer(struct fsi_master_acf *master, uint8_t slave,

drivers/fsi/fsi-master-ast-cf.c

598

uint8_t id, uint32_t addr, void *val,

drivers/fsi/fsi-master-ast-cf.c

622

uint8_t id, uint32_t addr, const void *val,

drivers/fsi/fsi-master-ast-cf.c

647

int link, uint8_t id)

drivers/fsi/fsi-master-gpio.c

113

uint8_t num_bits)

drivers/fsi/fsi-master-gpio.c

115

uint8_t bit, in_bit;

drivers/fsi/fsi-master-gpio.c

132

uint8_t bit;

drivers/fsi/fsi-master-gpio.c

171

uint8_t crc;

drivers/fsi/fsi-master-gpio.c

235

struct fsi_gpio_msg *cmd, uint8_t id,

drivers/fsi/fsi-master-gpio.c

240

uint8_t ds, opcode;

drivers/fsi/fsi-master-gpio.c

293

msg_push_bits(cmd, ((uint8_t *)data)[i], 8);

drivers/fsi/fsi-master-gpio.c

298

static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)

drivers/fsi/fsi-master-gpio.c

308

static void build_epoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)

drivers/fsi/fsi-master-gpio.c

318

static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)

drivers/fsi/fsi-master-gpio.c

335

uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp)

drivers/fsi/fsi-master-gpio.c

340

uint8_t tag;

drivers/fsi/fsi-master-gpio.c

35

uint8_t t_send_delay;

drivers/fsi/fsi-master-gpio.c

36

uint8_t t_echo_delay;

drivers/fsi/fsi-master-gpio.c

397

static int issue_term(struct fsi_master_gpio *master, uint8_t slave)

drivers/fsi/fsi-master-gpio.c

401

uint8_t tag;

drivers/fsi/fsi-master-gpio.c

425

uint8_t slave, uint8_t size, void *data)

drivers/fsi/fsi-master-gpio.c

430

uint8_t tag;

drivers/fsi/fsi-master-gpio.c

431

uint8_t *data_byte = data;

drivers/fsi/fsi-master-gpio.c

46

uint8_t bits;

drivers/fsi/fsi-master-gpio.c

539

static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave,

drivers/fsi/fsi-master-gpio.c

562

uint8_t id, uint32_t addr, void *val, size_t size)

drivers/fsi/fsi-master-gpio.c

581

uint8_t id, uint32_t addr, const void *val, size_t size)

drivers/fsi/fsi-master-gpio.c

600

int link, uint8_t id)

drivers/fsi/fsi-master-hub.c

46

uint8_t id, uint32_t addr, void *val, size_t size)

drivers/fsi/fsi-master-hub.c

58

uint8_t id, uint32_t addr, const void *val, size_t size)

drivers/fsi/fsi-master-i2cr.c

187

static int i2cr_read(struct fsi_master *master, int link, uint8_t id, uint32_t addr, void *val,

drivers/fsi/fsi-master-i2cr.c

226

static int i2cr_write(struct fsi_master *master, int link, uint8_t id, uint32_t addr,

drivers/fsi/fsi-master.h

127

int (*read)(struct fsi_master *, int link, uint8_t id,

drivers/fsi/fsi-master.h

129

int (*write)(struct fsi_master *, int link, uint8_t id,

drivers/fsi/fsi-master.h

131

int (*term)(struct fsi_master *, int link, uint8_t id);

drivers/fsi/fsi-scom.c

247

static int handle_pib_status(struct scom_device *scom, uint8_t status)

drivers/gpio/gpio-adnp.c

39

static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)

drivers/gpio/gpio-adnp.c

54

static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)

drivers/gpio/gpio-adp5520.c

26

uint8_t reg_val;

drivers/gpio/gpio-max732x.c

142

uint8_t reg_out[2];

drivers/gpio/gpio-max732x.c

146

uint8_t irq_mask;

drivers/gpio/gpio-max732x.c

147

uint8_t irq_mask_cur;

drivers/gpio/gpio-max732x.c

148

uint8_t irq_trig_raise;

drivers/gpio/gpio-max732x.c

149

uint8_t irq_trig_fall;

drivers/gpio/gpio-max732x.c

150

uint8_t irq_features;

drivers/gpio/gpio-max732x.c

154

static int max732x_writeb(struct max732x_chip *chip, int group_a, uint8_t val)

drivers/gpio/gpio-max732x.c

169

static int max732x_readb(struct max732x_chip *chip, int group_a, uint8_t *val)

drivers/gpio/gpio-max732x.c

181

*val = (uint8_t)ret;

drivers/gpio/gpio-max732x.c

193

uint8_t reg_val;

drivers/gpio/gpio-max732x.c

207

uint8_t reg_out;

drivers/gpio/gpio-max732x.c

232

uint8_t mask = 1u << (off & 0x7);

drivers/gpio/gpio-max732x.c

342

max732x_writeb(chip, 1, (uint8_t)msg);

drivers/gpio/gpio-max732x.c

447

static uint8_t max732x_irq_pending(struct max732x_chip *chip)

drivers/gpio/gpio-max732x.c

449

uint8_t cur_stat;

drivers/gpio/gpio-max732x.c

450

uint8_t old_stat;

drivers/gpio/gpio-max732x.c

451

uint8_t trigger;

drivers/gpio/gpio-max732x.c

452

uint8_t pending;

drivers/gpio/gpio-max732x.c

481

uint8_t pending;

drivers/gpio/gpio-max732x.c

482

uint8_t level;

drivers/gpio/gpio-rc5t583.c

28

uint8_t val = 0;

drivers/gpio/gpio-tps6586x.c

33

uint8_t val;

drivers/gpio/gpio-tps6586x.c

56

uint8_t val, mask;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1251

uint8_t ip, uint8_t inst)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1260

uint8_t ip, uint8_t inst)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1321

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1322

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1738

enum amdgpu_uid_type type, uint8_t inst,

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1741

enum amdgpu_uid_type type, uint8_t inst);

drivers/gpu/drm/amd/amdgpu/amdgpu.h

733

uint8_t flags;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

744

uint8_t num_entries;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

745

uint8_t uma_option_index;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

897

uint8_t *bios;

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

63

uint8_t xcp_node;

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

64

uint8_t phy_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

312

uint8_t xcp_id);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

112

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h

26

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

666

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

860

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

40

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

614

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

730

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

299

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

302

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

521

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

532

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

616

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

794

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

52

uint8_t vmid, uint16_t *p_pasid);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

79

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1665

uint8_t xcp_id)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1938

uint8_t *frev,

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1939

uint8_t *crev,

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1940

uint8_t **addr)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1948

*addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

354

uint8_t *addr = (uint8_t *) path_obj->asDispPath;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

361

uint8_t con_obj_id =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

388

uint8_t grph_obj_type =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

582

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

735

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

83

uint8_t id)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

908

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

137

uint8_t id);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

212

uint8_t *frev,

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

213

uint8_t *crev,

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

214

uint8_t **addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

1037

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

304

uint8_t nr_uma_options;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

799

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

902

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

41

bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t *i2c_address);

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

104

uint8_t __iomem *bios = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

156

uint8_t __iomem *bios;

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

274

static int amdgpu_atrm_call(acpi_handle atrm_handle, uint8_t *bios,

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

53

uint8_t *bios = adev->bios;

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

248

const uint8_t *src;

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

381

src = (const uint8_t *)(adev->pm.fw->data +

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

149

section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

150

section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

178

section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

179

section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

211

section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

212

section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

1036

uint8_t *kptr;

drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c

78

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

465

uint8_t flags;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7690

enum amdgpu_uid_type type, uint8_t inst,

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7719

enum amdgpu_uid_type type, uint8_t inst)

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

897

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

965

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1084

static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1085

uint16_t hw_id, uint8_t inst)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1087

uint8_t harvest = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1121

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1124

uint8_t inst;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1226

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1281

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1386

uint8_t num_base_address, subrev, variant;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1390

uint8_t *discovery_bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1398

uint8_t inst;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1586

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1642

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1751

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1808

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1880

if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data,

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1895

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

256

static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

283

uint8_t *binary)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

351

uint8_t *binary,

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

372

static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

384

uint8_t *data, uint32_t size,

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

400

static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

436

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

498

uint8_t *discovery_bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

685

uint8_t instance, uint16_t hw_id)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

706

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

713

uint8_t inst;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

772

uint8_t *discovery_bin = adev->discovery.bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h

38

uint8_t *bin;

drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h

41

uint8_t fd_closing;

drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c

48

uint8_t AttSource; /* FW source indicator */

drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c

49

uint8_t RecordValid; /* Indicates whether the record is a valid entry */

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

218

uint8_t num_pipes;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

219

uint8_t max_compress_frags;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

220

uint8_t num_banks;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

221

uint8_t num_se;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

222

uint8_t num_rb_per_se;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

223

uint8_t num_pkrs;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

1199

uint8_t cptr[10];

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

1375

uint8_t *exp_ranges)

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

283

uint8_t vram_vendor;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

308

uint8_t num_mem_partitions;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

466

uint8_t *exp_ranges);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

304

uint8_t out_buf[2];

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

124

uint8_t aid_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

132

uint8_t num_jpeg_inst;

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

145

uint8_t num_inst_per_aid;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

1113

uint8_t *bios;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

1740

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

322

uint8_t hub_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

323

uint8_t flush_type;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

61

uint8_t ring[PAGE_SIZE * 4];

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

66

uint8_t gds_backup[64 * 1024];

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

78

uint8_t ring[PAGE_SIZE * 4];

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

80

uint8_t mec_hpd[GFX10_MEC_HPD_SIZE];

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

92

uint8_t ring[PAGE_SIZE * 4];

drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

95

uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE];

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

145

uint8_t i2c_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

444

uint8_t negative;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

450

uint8_t type;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

452

uint8_t delay;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

453

uint8_t range;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

454

uint8_t refdiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

528

uint8_t backlight_level;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

1541

uint8_t dst_num_hops = node_info.num_hops;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

1542

uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

1543

uint8_t dst_num_links = node_info.num_links;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

1683

uint8_t node_num_links = ta_port_num_support ?

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

1998

ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3508

adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3531

adev->psp.toc.start_addr = (uint8_t *)toc_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3543

uint8_t *ucode_start_addr = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3548

ucode_start_addr = (uint8_t *)sos_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3637

uint8_t *ucode_array_start_addr;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3640

ucode_array_start_addr = (uint8_t *)sos_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3689

uint8_t *ucode_array_start_addr;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3702

ucode_array_start_addr = (uint8_t *)sos_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3715

adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3718

adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3724

adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3823

uint8_t *ucode_start_addr = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3831

ucode_start_addr = (uint8_t *)ta_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3899

(uint8_t *)ta_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3907

(uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3915

(uint8_t *)ta_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3923

(uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

3931

(uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

4176

void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

188

uint8_t num_hops;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

189

uint8_t is_sharing_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

191

uint8_t num_links;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

204

uint8_t *start_addr;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

233

uint8_t xgmi_ta_caps;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

616

void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c

148

uint8_t *ta_bin = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c

295

uint8_t *shared_buf = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c

36

static uint32_t get_bin_version(const uint8_t *bin)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c

45

uint8_t *shared_buf,

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

507

const uint8_t ring_header_size = 12;

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

517

uint8_t *ring_header __free(kfree) =

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

1129

uint8_t *src_addr = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

1130

uint8_t *dst_addr = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

1140

src_addr = (uint8_t *)ucode->fw->data +

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

470

uint8_t raw[0x100];

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h

59

uint8_t num_uvd_inst;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

1224

void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

320

uint8_t aid_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

322

uint8_t vcn_config;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

347

uint8_t num_vcn_inst;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

356

uint8_t num_inst_per_aid;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

380

uint8_t decode_queue_mode;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

381

uint8_t encode_generalpurpose_queue_mode;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

382

uint8_t encode_lowlatency_queue_mode;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

383

uint8_t encode_realtime_queue_mode;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

384

uint8_t padding[4];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

388

uint8_t is_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

389

uint8_t padding[3];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

393

uint8_t is_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

394

uint8_t queue_mode;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

395

uint8_t queue_status;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

396

uint8_t padding[5];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

400

uint8_t is_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

407

uint8_t smu_interface_type;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

408

uint8_t padding[3];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

413

uint8_t pad[44];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

415

uint8_t pad1[1];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

449

uint8_t method;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

450

uint8_t reserved[3];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

454

uint8_t is_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

455

uint8_t reserved[7];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

460

uint8_t pad[12];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

462

uint8_t pad1[8];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

464

uint8_t pad2[20];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

468

uint8_t pad3[9];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

477

uint8_t wrapped;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

491

uint8_t version;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

492

uint8_t ring_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

493

uint8_t pad[26];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

498

uint8_t pad[12];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

500

uint8_t pad1[8];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

502

uint8_t pad2[20];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

506

uint8_t pad3[404];

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

545

uint8_t i, struct amdgpu_vcn_inst *vcn);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

1107

int data_id, uint8_t *binary, u32 *size)

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

926

static uint8_t amdgpu_virt_crit_region_calc_checksum(uint8_t *buf_start, uint8_t *buf_end)

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

947

uint8_t checksum = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

987

(uint8_t *)&init_data_hdr->initdata_offset,

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

988

(uint8_t *)init_data_hdr +

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

234

uint8_t driver_version[64];

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

463

int data_id, uint8_t *binary, u32 *size);

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

146

uint8_t mem_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

106

uint8_t id;

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

107

uint8_t mem_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

127

uint8_t num_xcps;

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

145

struct amdgpu_xcp *xcp, uint8_t *mem_id);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

1772

uint16_t max_speed, uint8_t max_width)

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

862

uint8_t num_hops_mask = 0x7;

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h

128

uint16_t max_speed, uint8_t max_width);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h

95

uint8_t max_width;

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

236

uint8_t clk_seq_hi : 6;

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

237

uint8_t variant : 2;

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

240

uint8_t clk_seq_low;

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

241

uint8_t asic_6;

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

336

uint8_t driver_version[64];

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

370

uint8_t id;

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

441

int xcc_id, uint8_t *mem_id)

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

451

struct amdgpu_xcp *xcp, uint8_t *mem_id)

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

632

pcie_regs = (struct amdgpu_regs_pcie_v1_0 *)((uint8_t *)buf +

drivers/gpu/drm/amd/amdgpu/atom.c

1009

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

1023

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

1050

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

1062

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

1076

uint8_t val = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

1619

uint16_t *size, uint8_t *frev, uint8_t *crev,

drivers/gpu/drm/amd/amdgpu/atom.c

1639

bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,

drivers/gpu/drm/amd/amdgpu/atom.c

1640

uint8_t *crev)

drivers/gpu/drm/amd/amdgpu/atom.c

182

static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,

drivers/gpu/drm/amd/amdgpu/atom.c

373

static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)

drivers/gpu/drm/amd/amdgpu/atom.c

408

static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)

drivers/gpu/drm/amd/amdgpu/atom.c

413

static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)

drivers/gpu/drm/amd/amdgpu/atom.c

439

static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,

drivers/gpu/drm/amd/amdgpu/atom.c

448

static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)

drivers/gpu/drm/amd/amdgpu/atom.c

455

static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,

drivers/gpu/drm/amd/amdgpu/atom.c

601

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

615

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

650

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

662

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

688

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

706

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

785

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

802

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

819

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

831

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

849

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

863

uint8_t val = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

898

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/amd/amdgpu/atom.c

939

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/amd/amdgpu/atom.c

955

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/amd/amdgpu/atom.c

971

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/amd/amdgpu/atom.c

990

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/amd/amdgpu/atom.h

144

uint8_t shift;

drivers/gpu/drm/amd/amdgpu/atom.h

150

uint8_t name[STRLEN_LONG];

drivers/gpu/drm/amd/amdgpu/atom.h

151

uint8_t vbios_pn[STRLEN_LONG];

drivers/gpu/drm/amd/amdgpu/atom.h

153

uint8_t vbios_ver_str[STRLEN_NORMAL];

drivers/gpu/drm/amd/amdgpu/atom.h

154

uint8_t date[STRLEN_NORMAL];

drivers/gpu/drm/amd/amdgpu/atom.h

155

uint8_t build_num[STRLEN_NORMAL];

drivers/gpu/drm/amd/amdgpu/atom.h

165

uint8_t *frev, uint8_t *crev, uint16_t *data_start);

drivers/gpu/drm/amd/amdgpu/atom.h

167

uint8_t *frev, uint8_t *crev);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1151

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1441

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1680

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1974

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

383

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

570

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

750

uint8_t lane_num, uint8_t lane_set)

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

759

uint8_t frev, crev;

drivers/gpu/drm/amd/amdgpu/atombios_encoders.h

51

uint8_t lane_num, uint8_t lane_set);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1518

uint8_t *frame = buffer + 3;

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1519

uint8_t *header = buffer;

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1525

uint8_t *payload = buffer + 3;

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1526

uint8_t *header = buffer;

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1487

uint8_t *frame = buffer + 3;

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1488

uint8_t *header = buffer;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

3701

bool all_hub, uint8_t dst_sel);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8748

bool all_hub, uint8_t dst_sel)

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

345

bool all_hub, uint8_t dst_sel);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5978

bool all_hub, uint8_t dst_sel)

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

691

adev->psp.toc.start_addr = (uint8_t *)toc_hdr +

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

286

bool all_hub, uint8_t dst_sel);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4494

bool all_hub, uint8_t dst_sel)

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

580

adev->psp.toc.start_addr = (uint8_t *)toc_hdr +

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3394

bool all_hub, uint8_t dst_sel)

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

392

adev->psp.toc.start_addr = (uint8_t *)toc_hdr +

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

87

bool all_hub, uint8_t dst_sel);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

207

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

203

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

199

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

233

uint8_t vmid, uint8_t inst,

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

783

uint8_t vmid, uint16_t *p_pasid)

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

356

int inst_idx, uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

304

int inst_idx, uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

287

int inst_idx, uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

952

static int mes_v12_inv_tlb_convert_hub_id(uint8_t id)

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

858

static int mes_v12_inv_tlb_convert_hub_id(uint8_t id)

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

123

uint8_t trn;

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

78

static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

143

uint8_t trn;

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

80

static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

365

uint8_t core_override;

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

366

uint8_t reg_override;

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

367

uint8_t perfmon_override;

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

368

uint8_t reserved[5];

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

463

uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

470

uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

489

uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

490

uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

491

uint8_t reserved1[2]; /* +34 reserved, must be 0 */

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

771

uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

719

int xcc_id, uint8_t *mem_id)

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

729

struct amdgpu_xcp *xcp, uint8_t *mem_id)

drivers/gpu/drm/amd/amdgpu/ta_rap_if.h

54

uint8_t reserved[8];

drivers/gpu/drm/amd/amdgpu/ta_rap_if.h

81

uint8_t reserved[64];

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

152

uint8_t poison_mode_en;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

153

uint8_t dgpu_mode;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

155

uint8_t channel_dis_num;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

156

uint8_t nps_mode;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

158

uint8_t vram_type;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

182

uint8_t ras_init_success_flag;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

183

uint8_t err_inject_switch_disable_flag;

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

184

uint8_t reg_access_failure_flag;

drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h

110

uint8_t roi_idx;

drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h

141

uint8_t i2c_buf[TA_SECUREDISPLAY_I2C_BUFFER_SIZE]; /* I2C buffer */

drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h

142

uint8_t reserved;

drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h

146

uint8_t i2c_buf[TA_SECUREDISPLAY_V2_I2C_BUFFER_SIZE]; /* I2C buffer */

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

102

uint8_t num_links;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

169

uint8_t flag_extend_link_record;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

171

uint8_t caps_flag;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

172

uint8_t reserved[2];

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

84

uint8_t num_hops;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

85

uint8_t is_sharing_enabled;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

91

uint8_t num_links;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

95

uint8_t dst_xgmi_port_num;

drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

96

uint8_t src_xgmi_port_num;

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1143

uint8_t i = 0;

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

799

uint8_t i = 0;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

690

uint8_t sram_sel)

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

650

uint8_t sram_sel, uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

860

uint8_t sram_sel, uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

909

uint8_t sram_sel,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

910

uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1317

uint8_t *rb_ptr = (uint8_t *)ring_enc->ring;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

855

uint8_t sram_sel,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

856

uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

740

uint8_t sram_sel,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

741

uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

793

uint8_t sram_sel,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

794

uint8_t indirect)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

667

uint8_t sram_sel,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

668

uint8_t indirect)

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

1767

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

1796

uint8_t __user *user_addr,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

1797

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

1920

uint8_t __user *user_bos,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

1921

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2122

ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2126

ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2127

(uint8_t __user *)args->priv_data, &priv_offset);

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2139

ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2144

ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2149

ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2157

ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2158

(uint8_t __user *)args->priv_data, &bo_priv_offset);

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2556

ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2562

ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

2568

ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_crat.c

1831

uint8_t link_type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.c

1984

struct kfd_node *kdev, uint8_t type, uint64_t size,

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

100

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

111

uint8_t wave_front_size;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

112

uint8_t num_banks;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

114

uint8_t array_count;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

115

uint8_t num_cu_per_array;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

116

uint8_t num_simd_per_cu;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

117

uint8_t max_slots_scatch_cu;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

118

uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

132

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

133

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

142

uint8_t visibility_type; /* for virtual (dGPU) CRAT */

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

143

uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

159

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

160

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

164

uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

166

uint8_t cache_level;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

167

uint8_t lines_per_tag;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

169

uint8_t associativity;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

170

uint8_t cache_properties;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

172

uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

188

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

189

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

193

uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

195

uint8_t data_tlb_associativity_2mb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

196

uint8_t data_tlb_size_2mb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

197

uint8_t instruction_tlb_associativity_2mb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

198

uint8_t instruction_tlb_size_2mb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

199

uint8_t data_tlb_associativity_4k;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

200

uint8_t data_tlb_size_4k;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

201

uint8_t instruction_tlb_associativity_4k;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

202

uint8_t instruction_tlb_size_4k;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

203

uint8_t data_tlb_associativity_1gb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

204

uint8_t data_tlb_size_1gb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

205

uint8_t instruction_tlb_associativity_1gb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

206

uint8_t instruction_tlb_size_1gb;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

207

uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

219

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

220

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

224

uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

226

uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

265

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

266

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

271

uint8_t io_interface_type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

272

uint8_t version_major;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

279

uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

280

uint8_t weight_xgmi;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

290

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

291

uint8_t length;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

52

uint8_t revision;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

53

uint8_t checksum;

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

54

uint8_t oem_id[CRAT_OEMID_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

55

uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

61

uint8_t reserved[CRAT_RESERVED_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_crat.h

99

uint8_t type;

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

913

uint8_t wave_launch_mode)

drivers/gpu/drm/amd/amdkfd/kfd_debug.h

57

uint8_t wave_launch_mode);

drivers/gpu/drm/amd/amdkfd/kfd_device.c

1040

uint8_t id = 0;

drivers/gpu/drm/amd/amdkfd/kfd_events.c

345

memset(kernel_address, (uint8_t) UNSIGNALED_EVENT_SLOT,

drivers/gpu/drm/amd/amdkfd/kfd_events.c

453

uint8_t __user *user_priv_ptr,

drivers/gpu/drm/amd/amdkfd/kfd_events.c

529

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_events.c

80

memset(backing_store, (uint8_t) UNSIGNALED_EVENT_SLOT,

drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c

316

static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id)

drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c

343

static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id)

drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c

370

uint8_t id = 0;

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c

312

uint8_t sq_int_enc, sq_int_priv, sq_int_errtype;

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c

287

uint8_t sq_int_enc, sq_int_priv, sq_int_errtype;

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

428

(uint8_t *)mqd_dst + sizeof(*m) * xcc,

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

429

(uint8_t *)ctl_stack_dst + m->cp_hqd_cntl_stack_size * xcc);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

841

(uint8_t *)mqd_src + xcc * sizeof(*m),

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

842

(uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size,

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

1193

int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev);

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

1315

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

1319

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

1324

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

1329

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

238

uint8_t num_of_watch_points;

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

892

uint8_t default_granularity;

drivers/gpu/drm/amd/amdkfd/kfd_process.c

2265

uint8_t node_id = 0;

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

817

uint8_t *mqd, *ctl_stack;

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

861

uint8_t __user *user_priv,

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

866

uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

934

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

980

uint8_t __user *user_priv_ptr,

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

984

uint8_t *mqd, *ctl_stack, *q_extra_data = NULL;

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

314

int32_t *prefetch_loc, uint8_t *granularity,

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

3842

uint8_t granularity = 0xff;

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

4110

uint8_t __user *user_priv_ptr,

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

4219

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_svm.h

129

uint8_t granularity;

drivers/gpu/drm/amd/amdkfd/kfd_svm.h

189

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_svm.h

192

uint8_t __user *user_priv_ptr,

drivers/gpu/drm/amd/amdkfd/kfd_svm.h

248

uint8_t __user *user_priv_data,

drivers/gpu/drm/amd/amdkfd/kfd_svm.h

255

uint8_t __user *user_priv_ptr,

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1092

uint8_t *crc_buf;

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1097

crc_buf = (uint8_t *)&buf;

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1660

pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1662

(uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1664

(uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1666

(uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1759

pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1760

pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1761

pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1762

pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

2306

int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev)

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

2310

uint8_t device_idx = 0;

drivers/gpu/drm/amd/amdkfd/kfd_topology.h

110

uint8_t sibling_map[CACHE_SIBLINGMAP_SIZE];

drivers/gpu/drm/amd/amdkfd/kfd_topology.h

165

uint8_t oem_id[CRAT_OEMID_LENGTH];

drivers/gpu/drm/amd/amdkfd/kfd_topology.h

168

uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11049

uint8_t cnt;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13229

edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13514

uint8_t count,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13518

const uint8_t ddc_line = commands[0].fused_io.request.u.aux.ddc_line;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13555

uint8_t count,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6525

bpc = (uint8_t)connector->display_info.bpc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7990

(uint8_t *)edid,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

804

const uint8_t ddc_line = req->u.aux.ddc_line;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8094

uint8_t bpc_limit = 6;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1020

uint8_t underscan_vborder;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1021

uint8_t underscan_hborder;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1026

uint8_t abm_level;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1101

uint8_t count,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

566

uint8_t num_of_edps;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

835

uint8_t mst_status;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

852

static inline void amdgpu_dm_set_mst_status(uint8_t *status,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

853

uint8_t flags, bool set)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

139

uint8_t i, j, k;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

140

uint8_t mst_con_cnt = 1;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

220

struct amdgpu_dm_connector *aconnector, uint8_t *phy_id)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

305

uint8_t phy_id;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

349

uint8_t phy_inst;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

353

uint8_t roi_idx = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

433

uint8_t phy_id;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

97

uint8_t idx = 0, idx_2 = 0, connector_cnt = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

57

uint8_t enc_hw_inst;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1210

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1336

uint8_t data[36] = {0};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1451

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1652

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1836

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

198

uint8_t str_len = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2019

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2196

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2625

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

269

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2729

uint8_t panel_inst = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2764

uint8_t panel_inst = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3461

uint8_t supported_link_rates[16];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3464

uint8_t dpcd_rev;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3508

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3511

uint8_t supported_link_rates[16] = {0};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3514

uint8_t dpcd_rev = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

403

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

624

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

768

uint8_t param_nums = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

770

uint8_t custom_pattern[10] = {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

80

uint8_t *param_nums)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

839

if ((uint8_t) param[i + 1] != 0x0)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

846

custom_pattern[i] = (uint8_t) param[i + 1];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

87

uint8_t param_index = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

914

uint8_t *tbuf_base;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

920

tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

979

uint8_t *state_base;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

985

state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

101

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

109

static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

42

lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

53

lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

66

lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

74

lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

87

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

69

uint8_t max_link;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

71

uint8_t *srm;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

72

uint8_t *srm_temp;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

81

uint8_t content_type,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1048

memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

117

uint8_t *sadb = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

575

uint8_t *data,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

592

const uint8_t *data,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

601

address, (uint8_t *)data, size) > 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

643

uint8_t count,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

791

static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

793

static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

798

uint8_t ret = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

835

static const uint8_t DSC_DISABLE;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

836

static const uint8_t DSC_DECODING = 0x01;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

837

static const uint8_t DSC_PASSTHROUGH = 0x02;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

843

uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

844

uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

845

uint8_t ret = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

434

(uint8_t *)edid,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

526

uint8_t dpcd_rev;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

66

uint8_t copy[16];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

718

uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

719

uint8_t dret;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

722

uint8_t dpcd_bytes_to_read;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

723

const uint8_t max_process_count = 30;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

724

uint8_t process_count = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

704

uint8_t max_comp_block[] = {2, 1, 0};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

706

uint8_t i = 0, j = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

236

__field(uint8_t, fb_planes)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

50

uint8_t i;

drivers/gpu/drm/amd/display/dc/basics/conversion.c

105

uint8_t integer_bits,

drivers/gpu/drm/amd/display/dc/basics/conversion.c

106

uint8_t fractional_bits)

drivers/gpu/drm/amd/display/dc/basics/conversion.c

37

uint8_t integer_bits,

drivers/gpu/drm/amd/display/dc/basics/conversion.c

38

uint8_t fractional_bits)

drivers/gpu/drm/amd/display/dc/basics/conversion.h

33

uint8_t integer_bits,

drivers/gpu/drm/amd/display/dc/basics/conversion.h

34

uint8_t fractional_bits);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3060

uint8_t yclk_lvl;

drivers/gpu/drm/amd/display/dc/basics/vector.c

207

uint8_t *insert_address;

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

1131

if (tbl[i].ucClockIndication != (uint8_t)id)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

134

static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

1376

uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

150

static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

1500

uint8_t min_rr =

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

1502

uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate;

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

160

uint8_t i)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

1815

if (tbl[i].ucClockIndication == (uint8_t)id)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

1857

if (tbl[i].ucClockIndication == (uint8_t)id)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

2099

uint8_t *number;

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

2109

number = GET_IMAGE(uint8_t, offset);

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

2113

offset += sizeof(uint8_t);

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

683

if (tbl[i].ucClockIndication != (uint8_t) id)

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

86

static uint8_t bios_parser_get_connectors_number(

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1209

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1233

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1257

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1281

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1305

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1329

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1379

uint8_t *dce_caps)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

138

static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

165

uint8_t i)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1702

uint8_t uc_pwr_on,

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1703

uint8_t pwrseq_instance,

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

1704

uint8_t bypass_panel_control_wait)

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

505

pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment));

drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c

36

uint8_t *bios_get_image(struct dc_bios *bp,

drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h

31

uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1000

(uint8_t)(bp_params->fractional_feedback_divider / 100000);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1002

(uint8_t)bp_params->pixel_clock_post_divider;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1014

(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1056

uint8_t controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1065

clk.sPCLKInput.ucPpll = (uint8_t)pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1067

(uint8_t)(bp_params->reference_divider);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1073

(uint8_t)(bp_params->pixel_clock_post_divider);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1079

(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1126

uint8_t controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1154

clk.sPCLKInput.ucPpll = (uint8_t) pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1156

(uint8_t) bp_params->reference_divider;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1162

(uint8_t) bp_params->pixel_clock_post_divider;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1168

(uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1218

uint8_t controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1245

clk.ucPpll = (uint8_t) pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1247

clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1251

clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1341

(uint8_t)bp_params->ver1.step;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1343

(uint8_t)bp_params->ver1.delay;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1346

(uint8_t)(bp_params->ver1.range / 10000);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1537

(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1581

(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1680

enum engine_id engine_id, uint8_t *out_encoder_id)

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1682

uint8_t encoder_id = 0;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1721

enum signal_type signal_type, uint8_t *out_encoder_mode)

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1723

uint8_t encoder_mode = 0;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1843

uint8_t dac_standard);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1848

uint8_t dac_standard);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1874

uint8_t dac_standard)

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1894

uint8_t dac_standard)

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1915

uint8_t dac_standard)

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1966

uint8_t misc)

drivers/gpu/drm/amd/display/dc/bios/command_table.c

1968

uint8_t dac_type = ENGINE_ID_DACA;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2004

uint8_t misc = 0;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2140

uint8_t atom_controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2163

params.ucOverscanRight = (uint8_t)bp_params->h_overscan_right;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2164

params.ucOverscanLeft = (uint8_t)bp_params->h_overscan_left;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2165

params.ucOverscanBottom = (uint8_t)bp_params->v_overscan_bottom;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2166

params.ucOverscanTop = (uint8_t)bp_params->v_overscan_top;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2213

uint8_t atom_controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2322

uint8_t id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2372

uint8_t id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

241

params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2440

params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2443

params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

247

(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2472

params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

250

params.ucLaneNum = (uint8_t)(cntl->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2562

cntl_params->ucConfig = (uint8_t)((encoder.enum_id - 1) << 4);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2582

(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2594

(uint8_t)(cntl->color_depth);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2598

cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2604

(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2606

cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2612

cntl_params->ucAction = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

2657

uint8_t atom_crtc_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

287

params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

293

(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

296

params.ucLaneNum = (uint8_t)(cntl->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

328

params.ucDigId = (uint8_t)(cntl->engine_id);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

333

(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

336

params.ucLaneNum = (uint8_t)(cntl->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

405

uint8_t frev;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

406

uint8_t crev = 0;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

472

cpu_to_le16((uint8_t)cntl->connector_obj_id.id);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

476

params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

477

params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

544

(uint8_t)bp->cmd_helper->transmitter_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table.c

547

params.ucAction = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

601

cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));

drivers/gpu/drm/amd/display/dc/bios/command_table.c

605

params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

606

params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

675

(uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

677

params.ucLaneNum = (uint8_t)cntl->lanes_number;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

679

params.acConfig.ucRefClkSource = (uint8_t)pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

681

params.ucAction = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

733

cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));

drivers/gpu/drm/amd/display/dc/bios/command_table.c

738

params.asMode.ucLaneSel = (uint8_t)(cntl->lane_select);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

739

params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

801

(uint8_t)(cmd->transmitter_bp_to_atom(cntl->transmitter));

drivers/gpu/drm/amd/display/dc/bios/command_table.c

802

params.ucLaneNum = (uint8_t)(cntl->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

803

params.acConfig.ucRefClkSource = (uint8_t)(ref_clk_src_id);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

804

params.ucAction = (uint8_t)(cntl->action);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

822

params.ucAction = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

823

params.ucLaneNum = (uint8_t)cntl->lanes_number;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

824

params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

836

params.ucDPLaneSet = (uint8_t) cntl->lane_settings;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

883

params.ucAction = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

886

params.ucDPLaneSet = (uint8_t)cntl->lane_settings;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

890

params.ucLaneNum = (uint8_t)cntl->lanes_number;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

893

params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;

drivers/gpu/drm/amd/display/dc/bios/command_table.c

91

uint8_t frev, crev;

drivers/gpu/drm/amd/display/dc/bios/command_table.h

62

uint8_t dac_standard);

drivers/gpu/drm/amd/display/dc/bios/command_table.h

67

uint8_t dac_standard);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1017

uint8_t uc_pwr_on,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1018

uint8_t pwrseq_instance,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1019

uint8_t bypass_panel_control_wait);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1030

uint8_t uc_pwr_on,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1031

uint8_t pwrseq_instance,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1032

uint8_t bypass_panel_control_wait)

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1053

uint8_t uc_pwr_on,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1054

uint8_t pwrseq_instance,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1055

uint8_t bypass_panel_control_wait)

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

135

params.digid = (uint8_t)(cntl->engine_id);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

140

(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

143

params.lanenum = (uint8_t)(cntl->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

227

uint8_t frev;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

228

uint8_t crev = 0;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

274

ps.param.action = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

277

ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

282

ps.param.lanenum = (uint8_t)cntl->lanes_number;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

285

ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

332

for (uint8_t link_id = 0; link_id < MAX_LINKS; link_id++) {

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

350

uint8_t hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_0;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

353

hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_DP_0;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

356

dig_v1_7.action = (uint8_t)cntl->action;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

359

dig_v1_7.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

364

dig_v1_7.lanenum = (uint8_t)cntl->lanes_number;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

367

dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

383

uint8_t action = dig_v1_7.action;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

485

uint8_t controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

513

clk.pll_id = (uint8_t) pll_id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

519

clk.encoder_mode = (uint8_t) bp->

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

526

(uint8_t) bp->cmd_helper->

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

611

uint8_t atom_controller_id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

68

uint8_t frev, crev;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

728

uint8_t id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

852

uint8_t atom_crtc_id;

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

980

static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

989

static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)

drivers/gpu/drm/amd/display/dc/bios/command_table2.h

100

uint8_t bypass_panel_control_wait);

drivers/gpu/drm/amd/display/dc/bios/command_table2.h

59

uint8_t dac_standard);

drivers/gpu/drm/amd/display/dc/bios/command_table2.h

64

uint8_t dac_standard);

drivers/gpu/drm/amd/display/dc/bios/command_table2.h

96

struct bios_parser *bp, uint8_t id);

drivers/gpu/drm/amd/display/dc/bios/command_table2.h

98

uint8_t uc_pwr_on,

drivers/gpu/drm/amd/display/dc/bios/command_table2.h

99

uint8_t pwrseq_instance,

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

125

uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

201

(uint8_t)(h->transmitter_bp_to_atom(control->transmitter));

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

207

(uint8_t)(h->encoder_mode_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

209

ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

244

uint8_t dal_cmd_table_helper_encoder_id_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

297

uint8_t phy_id_to_atom(enum transmitter t)

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

299

uint8_t atom_phy_id;

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

330

uint8_t clock_source_id_to_atom_phy_clk_src_id(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

333

uint8_t atom_phy_clk_src_id = 0;

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c

77

uint8_t *atom_id)

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h

42

uint8_t *atom_id);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h

57

uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h

60

uint8_t dal_cmd_table_helper_encoder_id_to_atom(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h

63

uint8_t phy_id_to_atom(enum transmitter t);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h

65

uint8_t clock_source_id_to_atom_phy_clk_src_id(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

100

uint8_t *atom_id)

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

149

uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

230

uint8_t dal_cmd_table_helper_encoder_id_to_atom2(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h

42

uint8_t *atom_id);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h

52

uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h

55

uint8_t dal_cmd_table_helper_encoder_id_to_atom2(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

35

bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

36

uint8_t (*encoder_action_to_atom)(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

51

uint8_t (*transmitter_bp_to_atom)(enum transmitter t);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

52

uint8_t (*encoder_id_to_atom)(enum encoder_id id);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

53

uint8_t (*clock_source_id_to_atom_phy_clk_src_id)(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

55

uint8_t (*signal_type_to_atom_dig_mode)(enum signal_type s);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

56

uint8_t (*hpd_sel_to_atom)(enum hpd_source_id id);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

57

uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

58

uint8_t (*phy_id_to_atom)(enum transmitter t);

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

59

uint8_t (*disp_power_gating_action_to_atom)(

drivers/gpu/drm/amd/display/dc/bios/command_table_helper_struct.h

63

uint8_t (*transmitter_color_depth_to_atom)(enum transmitter_color_depth id);

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

151

static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

153

uint8_t atom_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

176

static uint8_t disp_power_gating_action_to_atom(

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

179

uint8_t atom_pipe_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

34

static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

36

uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

64

static uint8_t hpd_sel_to_atom(enum hpd_source_id id)

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

66

uint8_t atom_hpd_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

95

static uint8_t dig_encoder_sel_to_atom(enum engine_id id)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

155

static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

157

uint8_t atom_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

180

static uint8_t disp_power_gating_action_to_atom(

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

183

uint8_t atom_pipe_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

228

static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

230

uint8_t atomColorDepth = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

36

static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

38

uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

63

static uint8_t hpd_sel_to_atom(enum hpd_source_id id)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

65

uint8_t atom_hpd_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

94

static uint8_t dig_encoder_sel_to_atom(enum engine_id id)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

153

static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

155

uint8_t atom_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

178

static uint8_t disp_power_gating_action_to_atom(

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

181

uint8_t atom_pipe_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

226

static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

228

uint8_t atomColorDepth = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

34

static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

36

uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

61

static uint8_t hpd_sel_to_atom(enum hpd_source_id id)

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

63

uint8_t atom_hpd_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

92

static uint8_t dig_encoder_sel_to_atom(enum engine_id id)

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

107

static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

109

uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

137

static uint8_t hpd_sel_to_atom(enum hpd_source_id id)

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

139

uint8_t atom_hpd_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

168

static uint8_t dig_encoder_sel_to_atom(enum engine_id id)

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

170

uint8_t atom_dig_encoder_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

202

static uint8_t disp_power_gating_action_to_atom(

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

205

uint8_t atom_pipe_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

36

static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)

drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

38

uint8_t atom_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

107

static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

109

uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

137

static uint8_t hpd_sel_to_atom(enum hpd_source_id id)

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

139

uint8_t atom_hpd_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

168

static uint8_t dig_encoder_sel_to_atom(enum engine_id id)

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

170

uint8_t atom_dig_encoder_sel = 0;

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

202

static uint8_t disp_power_gating_action_to_atom(

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

205

uint8_t atom_pipe_action = 0;

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

36

static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)

drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

38

uint8_t atom_action = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

94

uint8_t j;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

261

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

312

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

43

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

47

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h

30

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h

31

uint8_t Flags;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h

32

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

114

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

115

uint8_t NumDcfclkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

116

uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

117

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

119

uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

120

uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

121

uint8_t spare[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

61

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

62

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

63

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

124

uint8_t WckRatio;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

125

uint8_t Spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

140

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

141

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

142

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

143

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

144

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

145

uint8_t spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

57

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

58

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

59

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

90

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

91

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

92

uint8_t FPS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

93

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

596

static unsigned int convert_wck_ratio(uint8_t wck_ratio)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

43

uint8_t WckRatio;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

44

uint8_t Spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

59

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

60

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

61

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

62

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

63

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

64

uint8_t spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

46

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

47

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

48

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

78

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

79

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

80

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

81

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

82

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

83

uint8_t spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

45

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

46

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

47

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

71

uint8_t WckRatio;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

72

uint8_t Spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

86

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

87

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

88

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

89

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

90

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

91

uint8_t spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h

25

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h

26

uint8_t Flags;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h

27

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1350

uint8_t i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

324

static uint8_t get_lowest_dpia_index(const struct dc_link *link)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

327

uint8_t idx = 0xFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

351

uint8_t lowest_dpia_index = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

996

static unsigned int convert_wck_ratio(uint8_t wck_ratio)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

116

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

117

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

118

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

119

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

120

uint8_t VpeClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

121

uint8_t NumMemPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

122

uint8_t NumFclkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

123

uint8_t spare[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

143

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

144

uint8_t NumDispClkLevelsEnabled; // Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

145

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

146

uint8_t Vcn0ClkLevelsEnabled; // Applies to both Vclk0 and Dclk0

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

147

uint8_t Vcn1ClkLevelsEnabled; // Applies to both Vclk1 and Dclk1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

148

uint8_t VpeClkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

149

uint8_t NumMemPstatesEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

150

uint8_t NumFclkLevelsEnabled;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

54

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

55

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

56

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

97

uint8_t WckRatio;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

98

uint8_t Spare[3];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

439

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

39

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h

26

uint8_t WmSetting;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h

27

uint8_t Flags;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h

28

uint8_t Padding[2];

drivers/gpu/drm/amd/display/dc/core/dc.c

1765

uint8_t stream_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

1767

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc.c

189

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc.c

190

uint8_t seamless_boot_stream_count = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

2020

uint8_t stream_count)

drivers/gpu/drm/amd/display/dc/core/dc.c

2053

static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/core/dc.c

3077

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc.c

3486

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc.c

4185

uint8_t current_stream_mask = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

4721

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc.c

5502

uint8_t dc_get_current_stream_count(struct dc *dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

5507

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)

drivers/gpu/drm/amd/display/dc/core/dc.c

594

struct rect *rect, uint8_t phy_id, bool is_stop)

drivers/gpu/drm/amd/display/dc/core/dc.c

5993

uint8_t action;

drivers/gpu/drm/amd/display/dc/core/dc.c

6048

uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline)

drivers/gpu/drm/amd/display/dc/core/dc.c

6053

uint8_t otg_inst = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6142

uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/core/dc.c

6143

uint8_t dpia_port_index)

drivers/gpu/drm/amd/display/dc/core/dc.c

6145

uint8_t index, link_index = 0xFF;

drivers/gpu/drm/amd/display/dc/core/dc.c

6222

uint8_t mst_alloc_slots,

drivers/gpu/drm/amd/display/dc/core/dc.c

6223

uint8_t *mst_slots_in_use)

drivers/gpu/drm/amd/display/dc/core/dc.c

6265

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps)

drivers/gpu/drm/amd/display/dc/core/dc.c

661

struct crc_window *window, uint8_t phy_id, bool stop)

drivers/gpu/drm/amd/display/dc/core/dc.c

713

uint8_t idx, bool reset, enum crc_poly_mode crc_poly_mode)

drivers/gpu/drm/amd/display/dc/core/dc.c

785

bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1557

uint8_t subvp_index)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2019

uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

290

uint8_t stream_count)

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

628

uint8_t valid_count = 0;

drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c

629

uint8_t dig_stream_count = 0;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

284

const uint8_t *edid,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

306

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4477

uint8_t chk_sum = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4478

uint8_t *ptr;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4479

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4487

gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4500

uint8_t *check_sum = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4501

uint8_t byte_index = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4736

*check_sum = (uint8_t) (0x100 - *check_sum);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5380

uint8_t disabled_master_pipe_idx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5414

uint8_t pipe_idx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5429

uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5432

uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

605

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

606

uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

656

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

708

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

728

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

770

uint8_t i;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

68

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

70

uint8_t pipe_mask = 0;

drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

29

void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx)

drivers/gpu/drm/amd/display/dc/dc.h

1111

uint8_t fec_enable_delay_in100us;

drivers/gpu/drm/amd/display/dc/dc.h

1136

uint8_t psr_power_use_phy_fsm;

drivers/gpu/drm/amd/display/dc/dc.h

1403

uint8_t protection_bits;

drivers/gpu/drm/amd/display/dc/dc.h

1641

uint8_t ddc_hw_inst;

drivers/gpu/drm/amd/display/dc/dc.h

1643

uint8_t hpd_src;

drivers/gpu/drm/amd/display/dc/dc.h

1645

uint8_t link_enc_hw_inst;

drivers/gpu/drm/amd/display/dc/dc.h

1707

uint8_t vendor_specific_lttpr_link_rate_wa;

drivers/gpu/drm/amd/display/dc/dc.h

1760

uint8_t link_count;

drivers/gpu/drm/amd/display/dc/dc.h

1762

uint8_t lowest_dpia_link_index;

drivers/gpu/drm/amd/display/dc/dc.h

1938

uint8_t plane_count;

drivers/gpu/drm/amd/display/dc/dc.h

2060

const uint8_t *edid,

drivers/gpu/drm/amd/display/dc/dc.h

2285

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);

drivers/gpu/drm/amd/display/dc/dc.h

2791

uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline);

drivers/gpu/drm/amd/display/dc/dc.h

2795

uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,

drivers/gpu/drm/amd/display/dc/dc.h

2796

uint8_t dpia_port_index);

drivers/gpu/drm/amd/display/dc/dc.h

2805

uint8_t mst_alloc_slots,

drivers/gpu/drm/amd/display/dc/dc.h

2806

uint8_t *mst_slots_in_use);

drivers/gpu/drm/amd/display/dc/dc.h

2808

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);

drivers/gpu/drm/amd/display/dc/dc.h

283

uint8_t fams_ver;

drivers/gpu/drm/amd/display/dc/dc.h

352

uint8_t subvp_drr_max_vblank_margin_us;

drivers/gpu/drm/amd/display/dc/dc.h

354

uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height

drivers/gpu/drm/amd/display/dc/dc.h

361

uint8_t subvp_drr_vblank_start_margin_us;

drivers/gpu/drm/amd/display/dc/dc.h

368

uint8_t num_of_host_routers;

drivers/gpu/drm/amd/display/dc/dc.h

369

uint8_t num_of_dpias_per_host_router;

drivers/gpu/drm/amd/display/dc/dc.h

371

uint8_t max_odm_combine_factor;

drivers/gpu/drm/amd/display/dc/dc.h

380

uint8_t uclk : 1;

drivers/gpu/drm/amd/display/dc/dc.h

381

uint8_t fclk : 1;

drivers/gpu/drm/amd/display/dc/dc.h

382

uint8_t dcfclk : 1;

drivers/gpu/drm/amd/display/dc/dc.h

383

uint8_t dcfclk_ds: 1;

drivers/gpu/drm/amd/display/dc/dc.h

530

uint8_t vblank_alignment_max_frame_time_diff;

drivers/gpu/drm/amd/display/dc/dc.h

542

uint8_t force_bios_fixed_vs;

drivers/gpu/drm/amd/display/dc/dc.h

734

uint8_t base_efficiency; //LP1

drivers/gpu/drm/amd/display/dc/dc.h

735

uint8_t low_power_efficiency; //LP2

drivers/gpu/drm/amd/display/dc/dc.h

939

uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

150

uint8_t uc_pwr_on,

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

151

uint8_t pwrseq_instance,

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

152

uint8_t bypass_panel_control_wait);

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

164

uint8_t *dce_caps);

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

167

uint8_t *dce_caps);

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

184

uint8_t *bios;

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

187

uint8_t *bios_local_image;

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

42

uint8_t (*get_connectors_number)(struct dc_bios *bios);

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

46

uint8_t connector_index);

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

108

uint8_t address;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

110

uint8_t *data;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

123

uint8_t number_of_payloads;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

153

uint8_t EDID_QUERY_DONE_ONCE:1;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

154

uint8_t IS_INTERNAL_DISPLAY:1;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

155

uint8_t FORCE_READ_REPEATED_START:1;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

156

uint8_t EDID_STRESS_READ:1;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

195

uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE];

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

53

uint8_t delay;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

55

uint8_t *data;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

77

uint8_t *data;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

92

uint8_t *data;

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

97

uint8_t *reply;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1034

struct pipe_ctx *pipe_ctx, uint8_t p_idx,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1067

struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1082

struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1106

struct pipe_ctx *pCtx, uint8_t pipe_idx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1186

void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1803

uint8_t num_cmds = 1;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2050

bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2070

bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst, struct dmub_ips_residency_info *driver_info,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

415

static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

417

uint8_t pipes = 0;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

453

uint8_t visual_confirm_enabled;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

495

uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

665

uint8_t cmd_pipe_index)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

786

uint8_t cmd_pipe_index)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

881

uint8_t cmd_pipe_index = 0;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

883

uint8_t subvp_count = 0;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

103

void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

107

void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

323

bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

325

bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst,

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1003

uint8_t UHBR10 :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1004

uint8_t UHBR20 :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1005

uint8_t UHBR13_5:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1006

uint8_t RESERVED:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1008

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1013

uint8_t UHBR10 :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1014

uint8_t UHBR20 :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1015

uint8_t UHBR13_5:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1016

uint8_t RESERVED:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1018

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1023

uint8_t AUX_LESS_ALPM_SUPPORTED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1024

uint8_t ASSR_SUPPORTED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1025

uint8_t RESERVED :6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1027

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1032

uint8_t dp_1024x768_60Hz_24bpp_support :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1033

uint8_t dp_1280x720_60Hz_24bpp_support :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1034

uint8_t dp_1920x1080_60Hz_24bpp_support :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1035

uint8_t RESERVED :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1037

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1042

uint8_t RESERVED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1043

uint8_t LOCAL_EDID_PRESENT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1044

uint8_t ASSOCIATED_TO_PRECEDING_PORT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1045

uint8_t HBLANK_EXPANSION_CAPABLE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1046

uint8_t BUFFER_SIZE_UNIT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1047

uint8_t BUFFER_SIZE_PER_PORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1048

uint8_t HBLANK_REDUCTION_CAPABLE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1049

uint8_t RESERVED2:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1050

uint8_t BUFFER_SIZE:8;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1052

uint8_t raw[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1060

uint8_t raw[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1065

uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1066

uint8_t RESERVED :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1068

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1073

uint8_t UHBR10_20_CAPABILITY :2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1074

uint8_t UHBR13_5_CAPABILITY :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1075

uint8_t CABLE_TYPE :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1076

uint8_t RESERVED :2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1078

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1082

uint8_t support_6bpc :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1083

uint8_t support_8bpc :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1084

uint8_t support_10bpc :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1085

uint8_t support_12bpc :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1086

uint8_t support_16bpc :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1087

uint8_t RESERVED :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1091

uint8_t support_rgb :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1092

uint8_t support_ycbcr444:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1093

uint8_t support_ycbcr422:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1094

uint8_t support_ycbcr420:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1095

uint8_t RESERVED :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1100

uint8_t supported;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1101

uint8_t max_pixel_rate_in_mps[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1102

uint8_t max_video_h_active_width[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1103

uint8_t max_video_v_active_height[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1110

uint8_t raw[12];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1115

uint8_t VALUE :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1116

uint8_t UNIT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1118

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1123

uint8_t AUX_WAKE_ALPM_CAP :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1124

uint8_t PM_STATE_2A_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1125

uint8_t AUX_LESS_ALPM_CAP :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1126

uint8_t AUX_LESS_ALPM_ML_PHY_SLEEP_STATUS_SUPPORTED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1127

uint8_t RESERVED :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1129

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1134

uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1135

uint8_t PSR_SETUP_TIME :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1136

uint8_t Y_COORDINATE_REQUIRED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1137

uint8_t SU_GRANULARITY_REQUIRED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1138

uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1139

uint8_t RESERVED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1141

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1145

uint8_t psr_version;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1147

uint8_t psr2_su_y_granularity_cap;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1148

uint8_t force_psrsu_cap;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1152

uint8_t pixel_deviation_per_line;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1153

uint8_t max_deviation_line;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1185

uint8_t pr_su_y_granularity;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1212

uint8_t mode;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1213

uint8_t max_lane_count;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1214

uint8_t max_link_rate;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1215

uint8_t phy_repeater_cnt;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1216

uint8_t max_ext_timeout;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1220

uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1221

uint8_t lttpr_ieee_oui[3]; // Always read from closest LTTPR to host

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1222

uint8_t lttpr_device_id[6]; // Always read from closest LTTPR to host

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1262

uint8_t edp_supported_link_rates_count;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1307

uint8_t edp_rev;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1318

uint8_t mso_cap_sst_links_supported;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1319

uint8_t dp_edp_general_cap_2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1328

uint8_t sdr_aux_backlight_control : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1329

uint8_t hdr_aux_backlight_control : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1330

uint8_t reserved_1 : 2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1331

uint8_t oled : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1332

uint8_t reserved_2 : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1333

uint8_t miniled : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1334

uint8_t emission_output : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1336

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

159

uint8_t link_rate_set;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

165

uint8_t cm_id;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

166

uint8_t group_id;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

174

uint8_t level : 4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

175

uint8_t reserved : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

176

uint8_t no_preshoot : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

177

uint8_t no_deemphasis : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

178

uint8_t method2 : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

180

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

210

uint8_t VC_PAYLOAD_TABLE_UPDATED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

211

uint8_t ACT_HANDLED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

213

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

218

uint8_t MINOR:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

219

uint8_t MAJOR:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

221

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

226

uint8_t MAX_LANE_COUNT:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

227

uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

228

uint8_t TPS3_SUPPORTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

229

uint8_t ENHANCED_FRAME_CAP:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

231

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

236

uint8_t MAX_DOWN_SPREAD:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

237

uint8_t RESERVED:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

238

uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

239

uint8_t TPS4_SUPPORTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

241

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

246

uint8_t MST_CAP:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

247

uint8_t RESERVED:7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

249

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

254

uint8_t LANE_COUNT_SET:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

255

uint8_t POST_LT_ADJ_REQ_GRANTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

256

uint8_t RESERVED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

257

uint8_t ENHANCED_FRAMING:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

259

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

264

uint8_t CR_DONE_0:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

265

uint8_t CHANNEL_EQ_DONE_0:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

266

uint8_t SYMBOL_LOCKED_0:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

267

uint8_t RESERVED0:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

268

uint8_t CR_DONE_1:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

269

uint8_t CHANNEL_EQ_DONE_1:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

270

uint8_t SYMBOL_LOCKED_1:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

271

uint8_t RESERVED_1:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

273

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

278

uint8_t REMOTE_CONTROL_CMD_PENDING:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

279

uint8_t AUTOMATED_TEST:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

280

uint8_t CP_IRQ:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

281

uint8_t MCCS_IRQ:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

282

uint8_t DOWN_REP_MSG_RDY:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

283

uint8_t UP_REQ_MSG_RDY:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

284

uint8_t SINK_SPECIFIC:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

285

uint8_t reserved:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

287

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

292

uint8_t SINK_COUNT:6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

293

uint8_t CPREADY:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

294

uint8_t RESERVED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

296

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

301

uint8_t INTERLANE_ALIGN_DONE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

302

uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

303

uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

304

uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

305

uint8_t LT_FAILED_128b_132b:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

306

uint8_t RESERVED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

307

uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

308

uint8_t LINK_STATUS_UPDATED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

310

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

315

uint8_t DP_LINK_RX_CAP_CHANGED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

316

uint8_t DP_LINK_STATUS_CHANGED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

317

uint8_t DP_LINK_STREAM_STATUS_CHANGED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

318

uint8_t DP_LINK_HDMI_LINK_STATUS_CHANGED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

319

uint8_t DP_LINK_CONNECTED_OFF_ENTRY_REQUESTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

320

uint8_t DP_LINK_TUNNELING_IRQ:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

321

uint8_t reserved:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

323

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

328

uint8_t VOLTAGE_SWING_LANE:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

329

uint8_t PRE_EMPHASIS_LANE:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

330

uint8_t RESERVED:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

333

uint8_t PRESET_VALUE :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

334

uint8_t RESERVED :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

336

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

341

uint8_t TRAINING_PATTERN_SET:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

342

uint8_t RECOVERED_CLOCK_OUT_EN:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

343

uint8_t SCRAMBLING_DISABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

344

uint8_t SYMBOL_ERROR_COUNT_SEL:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

347

uint8_t TRAINING_PATTERN_SET:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

348

uint8_t LINK_QUAL_PATTERN_SET:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

349

uint8_t RESERVED:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

351

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

359

uint8_t VOLTAGE_SWING_SET:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

360

uint8_t MAX_SWING_REACHED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

361

uint8_t PRE_EMPHASIS_SET:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

362

uint8_t MAX_PRE_EMPHASIS_REACHED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

363

uint8_t RESERVED:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

366

uint8_t PRESET_VALUE :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

367

uint8_t RESERVED :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

369

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

375

uint8_t DWN_STRM_PORTX_TYPE:3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

376

uint8_t DWN_STRM_PORTX_HPD:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

377

uint8_t RESERVERD:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

379

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

394

uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

395

uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

396

uint8_t SOURCE_CONTROL_MODE_SUPPORT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

397

uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

398

uint8_t RESERVED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

400

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

404

uint8_t byte;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

406

uint8_t PORT_PRESENT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

407

uint8_t PORT_TYPE:2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

408

uint8_t FMT_CONVERSION:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

409

uint8_t DETAILED_CAPS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

410

uint8_t RESERVED:3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

416

uint8_t RESERVED1:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

417

uint8_t DUAL_LINK:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

418

uint8_t HIGH_COLOR_DEPTH:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

419

uint8_t RESERVED2:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

421

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

426

uint8_t FRAME_SEQ_TO_FRAME_PACK:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

427

uint8_t YCrCr422_PASS_THROUGH:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

428

uint8_t YCrCr420_PASS_THROUGH:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

429

uint8_t YCrCr422_CONVERSION:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

430

uint8_t YCrCr420_CONVERSION:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

431

uint8_t RESERVED:3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

433

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

438

uint8_t FRL_MODE:1; // Bit 0

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

439

uint8_t BW_9Gbps:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

440

uint8_t BW_18Gbps:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

441

uint8_t BW_24Gbps:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

442

uint8_t BW_32Gbps:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

443

uint8_t BW_40Gbps:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

444

uint8_t BW_48Gbps:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

445

uint8_t FRL_LINK_TRAINING_FINISHED:1; // Bit 7

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

447

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

452

uint8_t HDMI_TX_LINK_ACTIVE_STATUS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

453

uint8_t HDMI_TX_READY_STATUS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

454

uint8_t RESERVED:6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

456

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

461

uint8_t FRL_LT_IN_PROGRESS_STATUS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

462

uint8_t FRL_LT_LINK_CONFIG_IN_PROGRESS:3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

463

uint8_t RESERVED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

464

uint8_t FALLBACK_POLICY:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

465

uint8_t FALLBACK_POLICY_VALID:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

466

uint8_t REGULATED_AUTONOMOUS_MODE_SUPPORTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

468

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

502

uint8_t RX_PORT0_STATUS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

503

uint8_t RX_PORT1_STATUS:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

504

uint8_t RESERVED:6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

506

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

523

uint8_t raw[7];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

528

uint8_t DOWN_STR_PORT_COUNT:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

529

uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

534

uint8_t IGNORE_MSA_TIMING_PARAM:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

539

uint8_t OUI_SUPPORT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

541

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

546

uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

551

uint8_t SPREAD_AMP:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

552

uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

556

uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

560

uint8_t IGNORE_MSA_TIMING_PARAM:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

562

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

567

uint8_t PANEL_MODE_EDP:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

568

uint8_t FRAMING_CHANGE_ENABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

569

uint8_t RESERVED:5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

570

uint8_t PANEL_SELF_TEST_ENABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

572

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

576

uint8_t ieee_oui[3];/*24-bit IEEE OUI*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

577

uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

581

uint8_t ieee_hw_rev;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

582

uint8_t ieee_fw_rev[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

590

uint8_t ieee_oui[3];/*24-bit IEEE OUI*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

591

uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

592

uint8_t ieee_hw_rev;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

593

uint8_t ieee_fw_rev[2];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

595

uint8_t raw[12];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

600

uint8_t AMD_IEEE_TxSignature_byte1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

601

uint8_t AMD_IEEE_TxSignature_byte2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

602

uint8_t AMD_IEEE_TxSignature_byte3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

606

uint8_t device_id_byte1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

607

uint8_t device_id_byte2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

608

uint8_t zero[4];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

609

uint8_t dce_version;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

610

uint8_t dal_version_byte1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

611

uint8_t dal_version_byte2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

615

uint8_t byte0;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

616

uint8_t byte1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

617

uint8_t byte2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

622

uint8_t byte0;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

623

uint8_t byte1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

624

uint8_t byte2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

625

uint8_t byte3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

629

uint8_t byte0;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

630

uint8_t byte1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

639

uint8_t raw[8];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

645

uint8_t ALT_SCRAMBLER_RESET:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

646

uint8_t FRAMING_CHANGE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

647

uint8_t RESERVED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

648

uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

649

uint8_t RESERVED2:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

651

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

656

uint8_t GTC_CAP:1; // bit 0: DP 1.3+

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

657

uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

658

uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

659

uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

660

uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

661

uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

662

uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

663

uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

665

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

670

uint8_t TRAINIG_AUX_RD_INTERVAL:7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

671

uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

673

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

679

uint8_t LINK_TRAINING :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

680

uint8_t LINK_TEST_PATTRN :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

681

uint8_t EDID_READ :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

682

uint8_t PHY_TEST_PATTERN :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

683

uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

684

uint8_t AUDIO_TEST_PATTERN :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

685

uint8_t TEST_AUDIO_DISABLED_VIDEO :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

687

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

692

uint8_t ACK :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

693

uint8_t NO_ACK :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

694

uint8_t EDID_CHECKSUM_WRITE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

695

uint8_t RESERVED :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

697

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

703

uint8_t PATTERN :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

704

uint8_t RESERVED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

706

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

762

uint8_t test_requested :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

763

uint8_t disable_video :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

769

uint8_t sampling_rate;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

770

uint8_t channel_count;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

771

uint8_t pattern_type;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

772

uint8_t pattern_period[8];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

778

uint8_t FEC_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

779

uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

780

uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

781

uint8_t BIT_ERROR_COUNT_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

782

uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

783

uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

784

uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

785

uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

787

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

792

uint8_t DSC_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

793

uint8_t DSC_PASSTHROUGH_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

794

uint8_t RESERVED :6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

798

uint8_t DSC_VERSION_MAJOR :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

799

uint8_t DSC_VERSION_MINOR :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

803

uint8_t RC_BLOCK_BUFFER_SIZE :2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

804

uint8_t RESERVED :6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

808

uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

809

uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

810

uint8_t RESERVED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

811

uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

812

uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

813

uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

814

uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

815

uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

819

uint8_t LINE_BUFFER_BIT_DEPTH :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

820

uint8_t RESERVED :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

824

uint8_t BLOCK_PREDICTION_SUPPORT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

825

uint8_t RESERVED :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

829

uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

830

uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

831

uint8_t RESERVED :2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

835

uint8_t RGB_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

836

uint8_t Y_CB_CR_444_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

837

uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

838

uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

839

uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

840

uint8_t RESERVED :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

844

uint8_t RESERVED0 :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

845

uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

846

uint8_t TEN_BITS_PER_COLOR_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

847

uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

848

uint8_t RESERVED1 :4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

852

uint8_t THROUGHPUT_MODE_0:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

853

uint8_t THROUGHPUT_MODE_1:4;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

857

uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

858

uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

859

uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

860

uint8_t RESERVED :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

864

uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

865

uint8_t RESERVED :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

872

uint8_t dsc_rc_buffer_size;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

880

uint8_t dsc_maximum_slice_width;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

882

uint8_t reserved;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

885

uint8_t raw[16];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

890

uint8_t BRANCH_OVERALL_THROUGHPUT_0;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

891

uint8_t BRANCH_OVERALL_THROUGHPUT_1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

892

uint8_t BRANCH_MAX_LINE_WIDTH;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

894

uint8_t raw[3];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

911

uint8_t su_y_granularity;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

914

uint8_t rate_control_caps;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

920

uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

921

uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

922

uint8_t RESERVED0: 2;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

923

uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

924

uint8_t RESERVED1: 3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

926

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

939

uint8_t dp_tunneling :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

940

uint8_t rsvd :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

941

uint8_t panel_replay_tun_opt :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

942

uint8_t dpia_bw_alloc :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

944

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

950

uint8_t dpia_num :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

951

uint8_t rsvd :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

953

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

959

uint8_t rsvd :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

960

uint8_t driver_bw_alloc_support :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

962

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

968

uint8_t group_id :3;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

969

uint8_t rsvd :5;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

971

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

980

uint8_t usb4_driver_id;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

981

uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

986

uint8_t DP_8b_10b_SUPPORTED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

987

uint8_t DP_128b_132b_SUPPORTED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

988

uint8_t RESERVED :6;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

990

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

995

uint8_t DP_128b_132b_SUPPORTED :1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

996

uint8_t RESERVED :7;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

998

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_dsc.h

66

const uint8_t *dpcd_dsc_basic_data,

drivers/gpu/drm/amd/display/dc/dc_dsc.h

67

const uint8_t *dpcd_dsc_ext_data,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

32

uint8_t *data,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.h

34

uint8_t *data,

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

128

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

63

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

66

const uint8_t count = 3;

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

74

for (uint8_t i = 0; i < count; i++) {

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

99

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/dc/dc_fused_io.h

18

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/dc/dc_fused_io.h

27

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

100

uint8_t CH0_7HIGH:7;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

101

uint8_t CH0_VALID:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

102

uint8_t CH1_8LOW:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

103

uint8_t CH1_7HIGH:7;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

104

uint8_t CH1_VALID:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

105

uint8_t CH2_8LOW:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

106

uint8_t CH2_7HIGH:7;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

107

uint8_t CH2_VALID:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

108

uint8_t CHECKSUM:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

109

uint8_t RESERVED:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

110

uint8_t RESERVED2:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

111

uint8_t RESERVED3:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

112

uint8_t RESERVED4:4;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

117

uint8_t byte[3];

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

119

uint8_t Manufacturer_OUI_1:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

120

uint8_t Manufacturer_OUI_2:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

121

uint8_t Manufacturer_OUI_3:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

126

uint8_t byte;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

128

uint8_t Hardware_Minor_Rev:4;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

129

uint8_t Hardware_Major_Rev:4;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

48

uint8_t eot;/* end of transmition '\x4' */

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

75

uint8_t byte[2];

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

77

uint8_t STATUS_UPDATE:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

78

uint8_t CED_UPDATE:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

79

uint8_t RR_TEST:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

80

uint8_t RESERVED:5;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

81

uint8_t RESERVED2:8;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

86

uint8_t byte;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

88

uint8_t CLOCK_DETECTED:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

89

uint8_t CH0_LOCKED:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

90

uint8_t CH1_LOCKED:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

91

uint8_t CH2_LOCKED:1;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

92

uint8_t RESERVED:4;

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

97

uint8_t byte[11];

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

99

uint8_t CH0_8LOW:8;

drivers/gpu/drm/amd/display/dc/dc_helper.c

108

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

223

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

251

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

278

uint8_t shift, uint32_t mask, uint32_t *field_value)

drivers/gpu/drm/amd/display/dc/dc_helper.c

286

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

287

uint8_t shift2, uint32_t mask2, uint32_t *field_value2)

drivers/gpu/drm/amd/display/dc/dc_helper.c

296

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

297

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/dc_helper.c

298

uint8_t shift3, uint32_t mask3, uint32_t *field_value3)

drivers/gpu/drm/amd/display/dc/dc_helper.c

308

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

309

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/dc_helper.c

310

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/dc_helper.c

311

uint8_t shift4, uint32_t mask4, uint32_t *field_value4)

drivers/gpu/drm/amd/display/dc/dc_helper.c

322

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

323

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/dc_helper.c

324

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/dc_helper.c

325

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/dc_helper.c

326

uint8_t shift5, uint32_t mask5, uint32_t *field_value5)

drivers/gpu/drm/amd/display/dc/dc_helper.c

338

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

339

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/dc_helper.c

340

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/dc_helper.c

341

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/dc_helper.c

342

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

drivers/gpu/drm/amd/display/dc/dc_helper.c

343

uint8_t shift6, uint32_t mask6, uint32_t *field_value6)

drivers/gpu/drm/amd/display/dc/dc_helper.c

356

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

357

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/dc_helper.c

358

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/dc_helper.c

359

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/dc_helper.c

360

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

drivers/gpu/drm/amd/display/dc/dc_helper.c

361

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

drivers/gpu/drm/amd/display/dc/dc_helper.c

362

uint8_t shift7, uint32_t mask7, uint32_t *field_value7)

drivers/gpu/drm/amd/display/dc/dc_helper.c

376

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

377

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/dc_helper.c

378

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/dc_helper.c

379

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/dc_helper.c

380

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

drivers/gpu/drm/amd/display/dc/dc_helper.c

381

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

drivers/gpu/drm/amd/display/dc/dc_helper.c

382

uint8_t shift7, uint32_t mask7, uint32_t *field_value7,

drivers/gpu/drm/amd/display/dc/dc_helper.c

383

uint8_t shift8, uint32_t mask8, uint32_t *field_value8)

drivers/gpu/drm/amd/display/dc/dc_helper.c

508

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

539

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

569

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

598

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/dc_helper.c

98

uint8_t shift)

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

1027

uint8_t timing_adjust_pending;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

1159

uint8_t otg : 1;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

1160

uint8_t reserved : 7;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

127

uint8_t vmid;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

158

uint8_t dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

162

uint8_t dcc_ind_blk_c;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

71

uint8_t tmz_surface;

drivers/gpu/drm/amd/display/dc/dc_plane_priv.h

33

uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/dc_stream.h

212

uint8_t dsc_packed_pps[128];

drivers/gpu/drm/amd/display/dc/dc_stream.h

252

uint8_t qs_bit;

drivers/gpu/drm/amd/display/dc/dc_stream.h

253

uint8_t qy_bit;

drivers/gpu/drm/amd/display/dc/dc_stream.h

304

uint8_t otg_offset;

drivers/gpu/drm/amd/display/dc/dc_stream.h

452

uint8_t dc_get_current_stream_count(struct dc *dc);

drivers/gpu/drm/amd/display/dc/dc_stream.h

453

struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);

drivers/gpu/drm/amd/display/dc/dc_stream.h

464

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/dc_stream.h

509

uint8_t stream_count);

drivers/gpu/drm/amd/display/dc/dc_stream.h

581

uint8_t phy_id,

drivers/gpu/drm/amd/display/dc/dc_stream.h

586

uint8_t phy_id,

drivers/gpu/drm/amd/display/dc/dc_stream.h

595

uint8_t idx,

drivers/gpu/drm/amd/display/dc/dc_stream.h

601

uint8_t idx,

drivers/gpu/drm/amd/display/dc/dc_types.h

1011

uint8_t version;

drivers/gpu/drm/amd/display/dc/dc_types.h

1012

uint8_t reserved;

drivers/gpu/drm/amd/display/dc/dc_types.h

1014

uint8_t repeater : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

1015

uint8_t hdcp_capable : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

1016

uint8_t reserved : 6;

drivers/gpu/drm/amd/display/dc/dc_types.h

1019

uint8_t raw[3];

drivers/gpu/drm/amd/display/dc/dc_types.h

1024

uint8_t HDCP_CAPABLE:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

1025

uint8_t REPEATER:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

1026

uint8_t RESERVED:6;

drivers/gpu/drm/amd/display/dc/dc_types.h

1028

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_types.h

1043

uint8_t vcp_id;

drivers/gpu/drm/amd/display/dc/dc_types.h

1045

uint8_t slot_count;

drivers/gpu/drm/amd/display/dc/dc_types.h

1073

uint8_t force_ffu_mode;

drivers/gpu/drm/amd/display/dc/dc_types.h

1081

uint8_t power_down_phy_before_disable_stream;

drivers/gpu/drm/amd/display/dc/dc_types.h

1324

uint8_t nrd_max_lane_count; // Non-reduced max lane count

drivers/gpu/drm/amd/display/dc/dc_types.h

1325

uint8_t nrd_max_link_rate; // Non-reduced max link rate

drivers/gpu/drm/amd/display/dc/dc_types.h

140

uint8_t format_code; /* ucData[0] [6:3]*/

drivers/gpu/drm/amd/display/dc/dc_types.h

1407

uint8_t rmcm_tmz;

drivers/gpu/drm/amd/display/dc/dc_types.h

141

uint8_t channel_count; /* ucData[0] [2:0]*/

drivers/gpu/drm/amd/display/dc/dc_types.h

142

uint8_t sample_rate; /* ucData[1]*/

drivers/gpu/drm/amd/display/dc/dc_types.h

1434

uint8_t stream_count;

drivers/gpu/drm/amd/display/dc/dc_types.h

144

uint8_t sample_size; /* for LPCM*/

drivers/gpu/drm/amd/display/dc/dc_types.h

146

uint8_t max_bit_rate;

drivers/gpu/drm/amd/display/dc/dc_types.h

1462

uint8_t aux_inst;

drivers/gpu/drm/amd/display/dc/dc_types.h

147

uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/

drivers/gpu/drm/amd/display/dc/dc_types.h

153

uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];

drivers/gpu/drm/amd/display/dc/dc_types.h

182

uint8_t blankstream_before_otg_off;

drivers/gpu/drm/amd/display/dc/dc_types.h

197

uint8_t manufacture_week;

drivers/gpu/drm/amd/display/dc/dc_types.h

198

uint8_t manufacture_year;

drivers/gpu/drm/amd/display/dc/dc_types.h

199

uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];

drivers/gpu/drm/amd/display/dc/dc_types.h

202

uint8_t speaker_flags;

drivers/gpu/drm/amd/display/dc/dc_types.h

208

uint8_t qs_bit;

drivers/gpu/drm/amd/display/dc/dc_types.h

209

uint8_t qy_bit;

drivers/gpu/drm/amd/display/dc/dc_types.h

447

uint8_t RATE_32:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

448

uint8_t RATE_44_1:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

449

uint8_t RATE_48:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

450

uint8_t RATE_88_2:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

451

uint8_t RATE_96:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

452

uint8_t RATE_176_4:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

453

uint8_t RATE_192:1;

drivers/gpu/drm/amd/display/dc/dc_types.h

456

uint8_t all;

drivers/gpu/drm/amd/display/dc/dc_types.h

483

uint8_t all;

drivers/gpu/drm/amd/display/dc/dc_types.h

516

uint8_t channel_count;

drivers/gpu/drm/amd/display/dc/dc_types.h

521

uint8_t sample_size;

drivers/gpu/drm/amd/display/dc/dc_types.h

523

uint8_t max_bit_rate;

drivers/gpu/drm/amd/display/dc/dc_types.h

525

uint8_t vendor_specific;

drivers/gpu/drm/amd/display/dc/dc_types.h

534

uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];

drivers/gpu/drm/amd/display/dc/dc_types.h

558

uint8_t hb0;

drivers/gpu/drm/amd/display/dc/dc_types.h

559

uint8_t hb1;

drivers/gpu/drm/amd/display/dc/dc_types.h

560

uint8_t hb2;

drivers/gpu/drm/amd/display/dc/dc_types.h

561

uint8_t hb3;

drivers/gpu/drm/amd/display/dc/dc_types.h

562

uint8_t sb[32];

drivers/gpu/drm/amd/display/dc/dc_types.h

567

uint8_t hb0;

drivers/gpu/drm/amd/display/dc/dc_types.h

568

uint8_t hb1;

drivers/gpu/drm/amd/display/dc/dc_types.h

569

uint8_t hb2;

drivers/gpu/drm/amd/display/dc/dc_types.h

570

uint8_t hb3;

drivers/gpu/drm/amd/display/dc/dc_types.h

571

uint8_t sb[128];

drivers/gpu/drm/amd/display/dc/dc_types.h

635

uint8_t su_y_granularity;

drivers/gpu/drm/amd/display/dc/dc_types.h

637

uint8_t rate_control_caps;

drivers/gpu/drm/amd/display/dc/dc_types.h

748

uint8_t su_y_granularity;

drivers/gpu/drm/amd/display/dc/dc_types.h

750

uint8_t rate_control_caps;

drivers/gpu/drm/amd/display/dc/dc_types.h

835

uint8_t NUM_SLICES_1 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

836

uint8_t NUM_SLICES_2 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

837

uint8_t RESERVED : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

838

uint8_t NUM_SLICES_4 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

839

uint8_t NUM_SLICES_6 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

840

uint8_t NUM_SLICES_8 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

841

uint8_t NUM_SLICES_10 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

842

uint8_t NUM_SLICES_12 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

844

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_types.h

849

uint8_t NUM_SLICES_16 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

850

uint8_t NUM_SLICES_20 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

851

uint8_t NUM_SLICES_24 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

852

uint8_t RESERVED : 5;

drivers/gpu/drm/amd/display/dc/dc_types.h

854

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_types.h

859

uint8_t RGB : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

860

uint8_t YCBCR_444 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

861

uint8_t YCBCR_SIMPLE_422 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

862

uint8_t YCBCR_NATIVE_422 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

863

uint8_t YCBCR_NATIVE_420 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

864

uint8_t RESERVED : 3;

drivers/gpu/drm/amd/display/dc/dc_types.h

866

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_types.h

871

uint8_t RESERVED1 : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

872

uint8_t COLOR_DEPTH_8_BPC : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

873

uint8_t COLOR_DEPTH_10_BPC : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

874

uint8_t COLOR_DEPTH_12_BPC : 1;

drivers/gpu/drm/amd/display/dc/dc_types.h

875

uint8_t RESERVED2 : 3;

drivers/gpu/drm/amd/display/dc/dc_types.h

877

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dc_types.h

882

uint8_t dsc_version;

drivers/gpu/drm/amd/display/dc/dc_types.h

984

uint8_t phy_output_num;

drivers/gpu/drm/amd/display/dc/dc_types.h

985

uint8_t otg_output_num;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

370

DCCG_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

371

DCCG3_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

372

DCCG31_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

373

DCCG314_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

374

DCCG32_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

375

DCCG35_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

376

DCCG401_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1977

static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1979

uint8_t num_enabled_symclk_fe = 0;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1998

uint8_t i;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2009

uint8_t num_enabled_symclk_fe = 0;

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

341

ABM_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

267

uint8_t layouts_per_sample_denom;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

268

uint8_t symbols_per_layout;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

269

uint8_t max_layouts_per_audio_sdp;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

794

uint8_t byte2 = audio_mode->max_bit_rate;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

795

uint8_t channel_count = audio_mode->channel_count;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

100

uint8_t AZALIA_ENDPOINT_REG_INDEX;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

101

uint8_t AZALIA_ENDPOINT_REG_DATA;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

103

uint8_t AUDIO_RATE_CAPABILITIES;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

104

uint8_t CLKSTOP;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

105

uint8_t EPSS;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

107

uint8_t DCCG_AUDIO_DTO0_SOURCE_SEL;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

108

uint8_t DCCG_AUDIO_DTO_SEL;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

109

uint8_t DCCG_AUDIO_DTO0_MODULE;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

110

uint8_t DCCG_AUDIO_DTO0_PHASE;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

111

uint8_t DCCG_AUDIO_DTO1_MODULE;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

112

uint8_t DCCG_AUDIO_DTO1_PHASE;

drivers/gpu/drm/amd/display/dc/dce/dce_audio.h

113

uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

282

uint8_t *buffer, uint8_t *reply_result,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

308

*reply_result = (uint8_t)reply_result_32;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

336

uint8_t *returned_bytes)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

566

uint8_t returned_bytes = 0;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

699

uint8_t reply;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

258

DCE_AUX_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

550

uint8_t j;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

211

CS_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

212

CS_REG_FIELD_LIST_DCN32(uint8_t)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

817

uint8_t *data,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

199

DMCU_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

105

uint8_t *buffer = reply->data;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

163

uint8_t *buffer = request->data;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

594

request.address = (uint8_t) ((payload->address << 1) | (payload->write ? 0 : 1));

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

634

uint8_t index_of_payload = 0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

70

uint8_t *returned_bytes)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

150

uint8_t DC_I2C_DDC1_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

151

uint8_t DC_I2C_DDC1_TIME_LIMIT;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

152

uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

153

uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

154

uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

155

uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

156

uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

157

uint8_t DC_I2C_DDC1_HW_STATUS;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

158

uint8_t DC_I2C_SW_DONE_USING_I2C_REG;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

159

uint8_t DC_I2C_SW_USE_I2C_REG_REQ;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

160

uint8_t DC_I2C_NO_QUEUED_SW_GO;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

161

uint8_t DC_I2C_SW_PRIORITY;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

162

uint8_t DC_I2C_SOFT_RESET;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

163

uint8_t DC_I2C_SW_STATUS_RESET;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

164

uint8_t DC_I2C_GO;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

165

uint8_t DC_I2C_SEND_RESET;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

166

uint8_t DC_I2C_TRANSACTION_COUNT;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

167

uint8_t DC_I2C_DDC_SELECT;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

168

uint8_t DC_I2C_DDC1_PRESCALE;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

169

uint8_t DC_I2C_DDC1_THRESHOLD;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

170

uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

171

uint8_t DC_I2C_SW_STOPPED_ON_NACK;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

172

uint8_t DC_I2C_SW_TIMEOUT;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

173

uint8_t DC_I2C_SW_ABORTED;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

174

uint8_t DC_I2C_SW_DONE;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

175

uint8_t DC_I2C_SW_STATUS;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

176

uint8_t DC_I2C_STOP_ON_NACK0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

177

uint8_t DC_I2C_START0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

178

uint8_t DC_I2C_RW0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

179

uint8_t DC_I2C_STOP0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

180

uint8_t DC_I2C_COUNT0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

181

uint8_t DC_I2C_DATA_RW;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

182

uint8_t DC_I2C_DATA;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

183

uint8_t DC_I2C_INDEX;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

184

uint8_t DC_I2C_INDEX_WRITE;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

185

uint8_t XTAL_REF_DIV;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

186

uint8_t MICROSECOND_TIME_BASE_DIV;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

187

uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

188

uint8_t DC_I2C_REG_RW_CNTL_STATUS;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

189

uint8_t I2C_LIGHT_SLEEP_FORCE;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

190

uint8_t I2C_MEM_PWR_STATE;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

191

uint8_t DC_I2C_DDC1_CLK_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

281

uint8_t address;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

283

uint8_t *data;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

156

uint8_t *byte,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

161

uint8_t data = 0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

253

uint8_t address,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

255

const uint8_t *data)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

275

uint8_t address,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

277

uint8_t *data)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

454

request.address = (uint8_t) ((payload->address << 1) | (payload->write ? 0 : 1));

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

472

uint8_t index_of_payload = 0;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

99

uint8_t byte)

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h

231

IPP_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

390

const uint8_t *pattern)

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

595

static uint8_t get_frontend_source(

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

412

MI_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

420

uint8_t single_head_rdreq_dmif_limit;

drivers/gpu/drm/amd/display/dc/dce/dce_opp.h

279

OPP_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

193

uint8_t bit_count;

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

97

DCE_PANEL_CNTL_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

280

uint8_t colorimetry_bpc;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

281

uint8_t dynamic_range_rgb = 0; /*full range*/

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

282

uint8_t dynamic_range_ycbcr = 1; /*bt709*/

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

370

uint8_t AFMT_GENERIC_INDEX;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

371

uint8_t AFMT_GENERIC0_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

372

uint8_t AFMT_GENERIC2_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

373

uint8_t AFMT_GENERIC_HB0;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

374

uint8_t AFMT_GENERIC_HB1;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

375

uint8_t AFMT_GENERIC_HB2;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

376

uint8_t AFMT_GENERIC_HB3;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

377

uint8_t AFMT_GENERIC_LOCK_STATUS;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

378

uint8_t AFMT_GENERIC_CONFLICT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

379

uint8_t AFMT_GENERIC_CONFLICT_CLR;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

380

uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

381

uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

382

uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

383

uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

384

uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

385

uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

386

uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

387

uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

388

uint8_t AFMT_GENERIC0_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

389

uint8_t AFMT_GENERIC1_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

390

uint8_t AFMT_GENERIC2_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

391

uint8_t AFMT_GENERIC3_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

392

uint8_t AFMT_GENERIC4_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

393

uint8_t AFMT_GENERIC5_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

394

uint8_t AFMT_GENERIC6_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

395

uint8_t AFMT_GENERIC7_FRAME_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

396

uint8_t HDMI_GENERIC0_CONT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

397

uint8_t HDMI_GENERIC0_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

398

uint8_t HDMI_GENERIC0_LINE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

399

uint8_t HDMI_GENERIC1_CONT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

400

uint8_t HDMI_GENERIC1_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

401

uint8_t HDMI_GENERIC1_LINE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

402

uint8_t DP_PIXEL_ENCODING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

403

uint8_t DP_COMPONENT_DEPTH;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

404

uint8_t DP_DYN_RANGE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

405

uint8_t DP_YCBCR_RANGE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

406

uint8_t HDMI_PACKET_GEN_VERSION;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

407

uint8_t HDMI_KEEPOUT_MODE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

408

uint8_t HDMI_DEEP_COLOR_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

409

uint8_t HDMI_CLOCK_CHANNEL_RATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

410

uint8_t HDMI_DEEP_COLOR_DEPTH;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

411

uint8_t HDMI_GC_CONT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

412

uint8_t HDMI_GC_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

413

uint8_t HDMI_NULL_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

414

uint8_t HDMI_DATA_SCRAMBLE_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

415

uint8_t HDMI_ACP_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

416

uint8_t HDMI_AUDIO_INFO_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

417

uint8_t AFMT_AUDIO_INFO_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

418

uint8_t HDMI_AUDIO_INFO_LINE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

419

uint8_t HDMI_GC_AVMUTE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

420

uint8_t DP_MSE_RATE_X;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

421

uint8_t DP_MSE_RATE_Y;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

422

uint8_t DP_MSE_RATE_UPDATE_PENDING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

423

uint8_t AFMT_AVI_INFO_VERSION;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

424

uint8_t HDMI_AVI_INFO_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

425

uint8_t HDMI_AVI_INFO_CONT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

426

uint8_t HDMI_AVI_INFO_LINE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

427

uint8_t DP_SEC_GSP0_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

428

uint8_t DP_SEC_STREAM_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

429

uint8_t DP_SEC_GSP1_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

430

uint8_t DP_SEC_GSP2_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

431

uint8_t DP_SEC_GSP3_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

432

uint8_t DP_SEC_GSP4_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

433

uint8_t DP_SEC_GSP5_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

434

uint8_t DP_SEC_GSP6_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

435

uint8_t DP_SEC_GSP7_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

436

uint8_t DP_SEC_AVI_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

437

uint8_t DP_SEC_MPG_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

438

uint8_t DP_VID_STREAM_DIS_DEFER;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

439

uint8_t DP_VID_STREAM_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

440

uint8_t DP_VID_STREAM_STATUS;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

441

uint8_t DP_STEER_FIFO_RESET;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

442

uint8_t DP_VID_M_N_GEN_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

443

uint8_t DP_VID_N;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

444

uint8_t DP_VID_M;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

445

uint8_t DIG_START;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

446

uint8_t AFMT_AUDIO_SRC_SELECT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

447

uint8_t AFMT_AUDIO_CHANNEL_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

448

uint8_t HDMI_AUDIO_PACKETS_PER_LINE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

449

uint8_t HDMI_AUDIO_DELAY_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

450

uint8_t AFMT_60958_CS_UPDATE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

451

uint8_t AFMT_AUDIO_LAYOUT_OVRD;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

452

uint8_t AFMT_60958_OSF_OVRD;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

453

uint8_t HDMI_ACR_AUTO_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

454

uint8_t HDMI_ACR_SOURCE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

455

uint8_t HDMI_ACR_AUDIO_PRIORITY;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

456

uint8_t HDMI_ACR_CTS_32;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

457

uint8_t HDMI_ACR_N_32;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

458

uint8_t HDMI_ACR_CTS_44;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

459

uint8_t HDMI_ACR_N_44;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

460

uint8_t HDMI_ACR_CTS_48;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

461

uint8_t HDMI_ACR_N_48;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

462

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

463

uint8_t AFMT_60958_CS_CLOCK_ACCURACY;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

464

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

465

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

466

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

467

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

468

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

469

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

470

uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

471

uint8_t DP_SEC_AUD_N;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

472

uint8_t DP_SEC_TIMESTAMP_MODE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

473

uint8_t DP_SEC_ASP_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

474

uint8_t DP_SEC_ATP_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

475

uint8_t DP_SEC_AIP_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

476

uint8_t DP_SEC_ACM_ENABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

477

uint8_t AFMT_AUDIO_SAMPLE_SEND;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

478

uint8_t AFMT_AUDIO_CLOCK_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

479

uint8_t TMDS_PIXEL_ENCODING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

480

uint8_t TMDS_COLOR_FORMAT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

481

uint8_t DIG_STEREOSYNC_SELECT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

482

uint8_t DIG_STEREOSYNC_GATE_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

483

uint8_t DP_DB_DISABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

484

uint8_t DP_MSA_MISC0;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

485

uint8_t DP_MSA_HTOTAL;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

486

uint8_t DP_MSA_VTOTAL;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

487

uint8_t DP_MSA_HSTART;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

488

uint8_t DP_MSA_VSTART;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

489

uint8_t DP_MSA_HSYNCWIDTH;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

490

uint8_t DP_MSA_HSYNCPOLARITY;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

491

uint8_t DP_MSA_VSYNCWIDTH;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

492

uint8_t DP_MSA_VSYNCPOLARITY;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

493

uint8_t DP_MSA_HWIDTH;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

494

uint8_t DP_MSA_VHEIGHT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

495

uint8_t HDMI_DB_DISABLE;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

496

uint8_t DP_VID_N_MUL;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

497

uint8_t DP_VID_M_DOUBLE_VALUE_EN;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

498

uint8_t DIG_SOURCE_SELECT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

499

uint8_t DAC_SOURCE_SELECT;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1417

uint8_t max_tries = 10;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1418

uint8_t counter = 0;

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

529

XFM_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c

85

uint8_t panel_mask0 = 0;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

141

bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask)

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

166

uint8_t panel_mask = 0x01 << inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

193

uint8_t panel_mask = 0x01 << panel_inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

225

uint8_t panel_mask = 0x01 << panel_inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

262

uint8_t ramping_boundary = 0xFF;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

62

uint8_t panel_mask = 0;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h

34

bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

108

static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

140

static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

179

static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

230

static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

273

static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

295

uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

36

static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

37

static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

38

static const uint8_t DP_SINK_DEVICE_STR_ID_3[] = {0x42, 0x61, 0x6c, 0x73, 0x61};

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

435

static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

455

uint8_t panel_inst, enum psr_residency_mode mode)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

41

struct psr_context *psr_context, uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

43

uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

45

uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

47

uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

48

void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

50

uint8_t panel_inst, enum psr_residency_mode mode);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

53

void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

118

uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

18

static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

19

static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

216

uint8_t panel_inst,

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

239

static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

24

static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

288

unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal, uint16_t frame_skip_number)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

47

static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

97

static void dmub_replay_set_power_opt(struct dmub_replay *dmub, unsigned int power_opt, uint8_t panel_inst)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

20

uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

22

uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

24

struct replay_context *replay_context, uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

26

uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

30

uint8_t panel_inst, uint16_t frame_skip_number);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

32

uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h

34

unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal,

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

366

uint8_t grph_depth;

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

367

uint8_t grph_format;

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

440

uint8_t video_format;

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2066

bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2254

bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h

284

struct timing_generator *tg, uint8_t width);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h

289

bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

294

uint8_t counter = 0;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1057

uint8_t width)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1174

static bool dce120_get_crc(struct timing_generator *tg, uint8_t idx,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

372

const uint8_t SEG_COUNT = 12;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h

62

TF_HELPER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h

77

TF_CM_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

251

DWBC_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h

175

IPP_DCN10_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

385

DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h

61

DCN20_VMID_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h

63

MPC_REG_FIELD_LIST_DCN201(uint8_t)

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h

47

OPP_DCN201_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h

95

AFMT_DCN3_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

150

const uint8_t SEG_COUNT = 12;

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

431

MCIF_WB_REG_FIELD_LIST_DCN3_0(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h

129

VPG_DCN3_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

76

DCN301_PANEL_CNTL_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.h

99

AFMT_DCN31_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.h

64

APG_DCN31_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

178

uint8_t pwrseq_inst = 0xF;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h

136

VPG_DCN31_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h

21

uint8_t I2C_LIGHT_SLEEP_FORCE;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

301

const uint8_t *pattern)

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

426

static uint8_t get_frontend_source(

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

512

DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

513

DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

514

DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

515

DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

516

DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

258

uint8_t colorimetry_bpc;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

259

uint8_t dp_pixel_encoding = 0;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

260

uint8_t dp_component_depth = 0;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

783

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

602

SE_REG_FIELD_LIST_DCN1_0(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

603

uint8_t HDMI_ACP_SEND;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

604

SE_REG_FIELD_LIST_DCN2_0(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

605

SE_REG_FIELD_LIST_DCN3_0(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

606

SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

607

SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

670

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

298

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

321

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

324

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

475

dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

478

dpia_control.lanenum = (uint8_t)link_settings->lane_count;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

522

dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

525

dpia_control.lanenum = (uint8_t)link_settings->lane_count;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

569

dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

70

static uint8_t phy_id_from_transmitter(enum transmitter t)

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

72

uint8_t phy_id;

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

312

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

65

static uint8_t phy_id_from_transmitter(enum transmitter t)

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

67

uint8_t phy_id;

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

349

uint8_t dpia_id,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

350

uint8_t digmode,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

351

uint8_t fec_rdy)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

358

dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

361

dpia_control.lanenum = (uint8_t)link_settings->lane_count;

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

375

uint8_t dpia_id,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

376

uint8_t digmode)

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

384

dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE;

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h

176

uint8_t dpia_id,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h

177

uint8_t digmode,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h

178

uint8_t fec_rdy);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h

185

uint8_t dpia_id,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h

186

uint8_t digmode);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

322

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

450

uint8_t colorimetry_bpc;

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

451

uint8_t dp_pixel_encoding = 0;

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

452

uint8_t dp_component_depth = 0;

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

453

uint8_t dp_translate_pixel_enc = 0;

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

456

uint8_t dp_compressed_pixel_format = 0;

drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c

105

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

35

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

36

uint8_t dig_be;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

37

uint8_t dig_fe;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

38

uint8_t link_enc_idx;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

39

uint8_t stream_enc_idx;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

40

uint8_t dio_output_idx;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

41

uint8_t phy_idx;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

42

uint8_t assr_enabled;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

43

uint8_t mst_enabled;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

44

uint8_t dp2_enabled;

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

45

uint8_t usb4_enabled;

drivers/gpu/drm/amd/display/dc/dm_helpers.h

138

uint8_t *data,

drivers/gpu/drm/amd/display/dc/dm_helpers.h

148

const uint8_t *data,

drivers/gpu/drm/amd/display/dc/dm_helpers.h

160

uint8_t count,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

83

uint8_t wm_inst;

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

84

uint8_t wm_type;

drivers/gpu/drm/amd/display/dc/dm_services.h

106

uint8_t shift)

drivers/gpu/drm/amd/display/dc/dm_services.h

121

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);

drivers/gpu/drm/amd/display/dc/dm_services.h

125

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);

drivers/gpu/drm/amd/display/dc/dm_services.h

91

uint8_t shift)

drivers/gpu/drm/amd/display/dc/dm_services_types.h

124

uint8_t transmitter;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

125

uint8_t ddi_channel_mapping;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

126

uint8_t pipe_idx;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

203

uint8_t display_count;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

208

uint8_t crtc_index;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

215

uint8_t luminance;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

219

uint8_t signal_level;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

227

uint8_t error_code; /* Byte 4 */

drivers/gpu/drm/amd/display/dc/dm_services_types.h

228

uint8_t ac_level_percentage; /* Byte 5 */

drivers/gpu/drm/amd/display/dc/dm_services_types.h

229

uint8_t dc_level_percentage; /* Byte 6 */

drivers/gpu/drm/amd/display/dc/dm_services_types.h

230

uint8_t min_input_signal; /* Byte 7 */

drivers/gpu/drm/amd/display/dc/dm_services_types.h

231

uint8_t max_input_signal; /* Byte 8 */

drivers/gpu/drm/amd/display/dc/dm_services_types.h

232

uint8_t num_data_points; /* Byte 9 */

drivers/gpu/drm/amd/display/dc/dm_services_types.h

288

uint8_t action;

drivers/gpu/drm/amd/display/dc/dm_services_types.h

294

uint8_t hdmi_frl_num_lanes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1044

uint8_t subvp_count = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1045

uint8_t vactive_count = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1046

uint8_t non_subvp_pipes = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

905

uint8_t vblank_index = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

990

uint8_t subvp_count = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

426

uint8_t base_percent_efficiency; //LP1

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

427

uint8_t low_power_percent_efficiency; //LP2

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12824

base_programming->scheduling_delay_otg_vlines = (uint8_t)stream_pstate_meta->scheduling_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12825

base_programming->contention_delay_otg_vlines = (uint8_t)stream_pstate_meta->contention_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12826

base_programming->vline_int_ack_delay_otg_vlines = (uint8_t)stream_pstate_meta->vertical_interrupt_ack_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12830

base_programming->allow_to_target_delay_otg_vlines = (uint8_t)stream_pstate_meta->allow_to_target_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12850

(uint8_t)stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12871

(uint8_t)stream_pstate_meta->method_drr.programming_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12890

(uint8_t)stream_pstate_meta->method_subvp.programming_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12892

(uint8_t)stream_pstate_meta->method_subvp.prefetch_to_mall_delay_otg_vlines;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

515

uint8_t vblank_index = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

607

uint8_t subvp_count = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

608

uint8_t vactive_count = 0;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1098

TF_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

638

TF_REG_FIELD_LIST_DCN2_0(uint8_t);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

43

TF_REG_FIELD_LIST_DCN201(uint8_t);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

468

DPP_REG_FIELD_LIST_DCN3(uint8_t);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

45

DPP_REG_FIELD_LIST_DCN35(uint8_t);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

659

DPP_REG_FIELD_LIST_DCN401(uint8_t);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

299

static bool dsc_bpp_increment_div_from_dpcd(uint8_t bpp_increment_dpcd, uint32_t *bpp_increment_div)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

332

const uint8_t *dpcd_dsc_basic_data,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

333

const uint8_t *dpcd_dsc_branch_decoder_caps,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

206

bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

345

uint8_t i;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

522

DSC_FIELD_LIST_DCN20(uint8_t);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

606

uint8_t *dsc_packed_pps);

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h

43

DSC_FIELD_LIST_DCN35(uint8_t);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

310

DSC_FIELD_LIST_DCN401(uint8_t);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

112

uint8_t *dsc_packed_pps);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

79

uint8_t NUM_SLICES_1 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

80

uint8_t NUM_SLICES_2 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

81

uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

82

uint8_t NUM_SLICES_4 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

83

uint8_t NUM_SLICES_8 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

84

uint8_t NUM_SLICES_12 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

85

uint8_t NUM_SLICES_16 : 1;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

87

uint8_t raw;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

91

uint8_t dsc_version;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

37

TF_HELPER_REG_FIELD_LIST_DCN3(uint8_t);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

867

DWBC_REG_FIELD_LIST_DCN3_0(uint8_t);

drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h

49

DWBC_REG_FIELD_LIST_DCN3_5(uint8_t);

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

126

uint8_t *buff = NULL;

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

128

const uint8_t hdcp_i2c_addr_link_primary = 0x3a; /* 0x74 >> 1*/

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

129

const uint8_t hdcp_i2c_addr_link_secondary = 0x3b; /* 0x76 >> 1*/

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

131

uint8_t offset;

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

232

uint8_t *data,

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

76

static const uint8_t hdcp_i2c_offsets[HDCP_MESSAGE_ID_MAX] = {

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

574

uint8_t ffe_preset)

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

169

DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

227

uint8_t ffe_preset);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

201

uint8_t misc0 = 0;

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

202

uint8_t misc1 = 0;

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

203

uint8_t hsp;

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

204

uint8_t vsp;

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

551

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

217

DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

445

DCN_HUBBUB_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

446

HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

447

HUBBUB_HVM_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

448

HUBBUB_RET_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

449

HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

450

HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

451

HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

680

DCN_HUBP_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

296

DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

109

DCN201_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

43

DCN35_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

89

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

338

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits);

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1249

HWSEQ_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1250

HWSEQ_DCN_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1251

HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1252

HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1253

HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1254

HWSEQ_DCN35_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1255

HWSEQ_DCN401_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

74

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

45

bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2045

uint8_t i, num_pipes;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

209

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

770

uint8_t pwrseq_instance;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

936

uint8_t pwrseq_instance = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

115

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

153

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

84

static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2363

static uint8_t get_clock_divider(struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3320

uint8_t i;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3593

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4048

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

142

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

149

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

144

uint8_t ramping_boundary = 0xFF;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

485

uint8_t i;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1383

uint8_t i;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

262

uint8_t i;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

323

cmd.cab.cab_alloc_ways = (uint8_t)ways;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1735

uint8_t i;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1033

uint8_t i;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1254

uint8_t num_ways = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1285

uint8_t ways, i;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1091

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

147

uint8_t subvp_index;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1647

struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

101

uint8_t controller_id,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

125

uint8_t stream_count);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

231

uint8_t pipe_count,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

363

uint8_t gsl_group;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

384

uint8_t mpcc_inst;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

443

uint8_t dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

474

uint8_t pipe_idx;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

475

uint8_t pipe_idx_syncd;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

503

uint8_t subvp_index;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

527

uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

528

uint8_t dp_clock_source_ref_count;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

624

uint8_t stream_count;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

625

uint8_t stream_mask;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

630

uint8_t phantom_stream_count;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

634

uint8_t phantom_plane_count;

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

102

uint8_t *buffer;

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

110

uint8_t returned_byte;

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

125

uint8_t *buffer;

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

132

uint8_t returned_byte;

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

141

uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

168

uint8_t *buffer,

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

169

uint8_t *reply_result,

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

173

uint8_t *returned_bytes);

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

47

uint8_t *data;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

161

uint8_t wm_type;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

315

CLK_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

316

CLK20_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

80

uint8_t *data,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

112

uint8_t protection_bits;

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

154

uint8_t vmid;

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

304

void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits);

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

406

uint8_t all;

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

181

uint8_t dpia_id,

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

182

uint8_t digmode,

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

183

uint8_t fec_rdy);

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

185

uint8_t dpia_id,

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

186

uint8_t digmode);

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

293

uint8_t ffe_preset);

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

186

bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

107

const uint8_t *custom_pattern;

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

177

const uint8_t *custom_sdp_message,

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

253

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h

337

uint8_t *dsc_packed_pps,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

145

uint8_t dsc_mode;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

146

uint8_t odm_mode;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

151

uint8_t crc_eng_inst;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

422

bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

462

bool (*get_crc)(struct timing_generator *tg, uint8_t idx,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

502

uint8_t master_clock_divider,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

503

uint8_t slave_clock_divider);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

88

uint8_t PROGRAM_STEREO : 1;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

89

uint8_t PROGRAM_POLARITY : 1;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

90

uint8_t RIGHT_EYE_POLARITY : 1;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

91

uint8_t FRAME_PACKED : 1;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

92

uint8_t DISABLE_STEREO_DP_SYNC : 1;

drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

61

uint8_t stream_count);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

112

const uint8_t *edid,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

176

uint8_t *write_buf,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

178

uint8_t *read_buf,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

185

const uint8_t *data,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

214

uint32_t (*bw_kbps_from_raw_frl_link_rate_data)(uint8_t bw);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

218

uint8_t (*dp_get_lttpr_count)(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

349

struct dc_link *link, uint8_t dp_test_mode);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

392

uint8_t shift, uint32_t mask, uint32_t *field_value);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

395

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

396

uint8_t shift2, uint32_t mask2, uint32_t *field_value2);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

399

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

400

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

401

uint8_t shift3, uint32_t mask3, uint32_t *field_value3);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

404

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

405

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

406

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

407

uint8_t shift4, uint32_t mask4, uint32_t *field_value4);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

410

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

411

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

412

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

413

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

414

uint8_t shift5, uint32_t mask5, uint32_t *field_value5);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

417

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

418

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

419

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

420

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

421

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

422

uint8_t shift6, uint32_t mask6, uint32_t *field_value6);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

425

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

426

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

427

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

428

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

429

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

430

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

431

uint8_t shift7, uint32_t mask7, uint32_t *field_value7);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

434

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

435

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

436

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

437

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

438

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

439

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

440

uint8_t shift7, uint32_t mask7, uint32_t *field_value7,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

441

uint8_t shift8, uint32_t mask8, uint32_t *field_value8);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

492

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

498

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

531

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

536

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

drivers/gpu/drm/amd/display/dc/inc/resource.h

612

uint8_t disabled_master_pipe_idx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

616

uint8_t pipe_idx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

618

uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);

drivers/gpu/drm/amd/display/dc/inc/resource.h

91

uint8_t inst,

drivers/gpu/drm/amd/display/dc/inc/vm_helper.h

42

void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx);

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

212

uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

163

uint8_t test_rate = 0;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

42

static enum dc_link_rate get_link_rate_from_test_link_rate(uint8_t test_rate)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

688

(uint8_t *)p_custom_pattern,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

734

(uint8_t *)p_custom_pattern,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

76

uint8_t count;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c

167

void dp_trace_source_sequence(struct dc_link *link, uint8_t dp_test_mode)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h

61

void dp_trace_source_sequence(struct dc_link *link, uint8_t dp_test_mode);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

144

const uint8_t vendor_lttpr_write_data_4lane_1[4] = {0x1, 0x6E, 0xF2, 0x19};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

145

const uint8_t vendor_lttpr_write_data_4lane_2[4] = {0x1, 0x6B, 0xF2, 0x01};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

146

const uint8_t vendor_lttpr_write_data_4lane_3[4] = {0x1, 0x6D, 0xF2, 0x18};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

147

const uint8_t vendor_lttpr_write_data_4lane_4[4] = {0x1, 0x6C, 0xF2, 0x03};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

148

const uint8_t vendor_lttpr_write_data_4lane_5[4] = {0x1, 0x03, 0xF3, 0x06};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

29

uint8_t dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

40

const uint8_t dp_type = dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

41

const uint8_t vendor_lttpr_exit_manual_automation_0[4] = {0x1, 0x11, 0x0, 0x06};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

42

const uint8_t vendor_lttpr_exit_manual_automation_1[4] = {0x1, 0x50, dp_type, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

43

const uint8_t vendor_lttpr_exit_manual_automation_2[4] = {0x1, 0x50, 0x50, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

44

const uint8_t vendor_lttpr_exit_manual_automation_3[4] = {0x1, 0x51, 0x50, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

45

const uint8_t vendor_lttpr_exit_manual_automation_4[4] = {0x1, 0x10, 0x58, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

46

const uint8_t vendor_lttpr_exit_manual_automation_5[4] = {0x1, 0x10, 0x59, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

47

const uint8_t vendor_lttpr_exit_manual_automation_6[4] = {0x1, 0x30, 0x51, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

48

const uint8_t vendor_lttpr_exit_manual_automation_7[4] = {0x1, 0x30, 0x52, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

49

const uint8_t vendor_lttpr_exit_manual_automation_8[4] = {0x1, 0x30, 0x54, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

50

const uint8_t vendor_lttpr_exit_manual_automation_9[4] = {0x1, 0x30, 0x55, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

79

const uint8_t pltpat_custom[10] = {0x1F, 0x7C, 0xF0, 0xC1, 0x07, 0x1F, 0x7C, 0xF0, 0xC1, 0x07};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

80

const uint8_t vendor_lttpr_write_data_pg0[4] = {0x1, 0x11, 0x0, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

81

const uint8_t vendor_lttpr_exit_manual_automation_0[4] = {0x1, 0x11, 0x0, 0x06};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h

31

uint8_t dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

100

uint8_t fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

101

uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

133

uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c

40

uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

127

const uint8_t vendor_lttpr_exit_manual_automation_0[4] = {0x1, 0x11, 0x0, 0x06};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

32

const uint8_t vendor_ffe_preset_table[16] = {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

38

const uint8_t ffe_mask[4] = {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

48

const uint8_t ffe_cfg[4] = {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

54

const uint8_t dp_type = dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

56

const uint8_t vendor_lttpr_write_data_ffe1[4] = {0x01, 0x50, dp_type, 0x0F};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

57

const uint8_t vendor_lttpr_write_data_ffe2[4] = {0x01, 0x55, dp_type, ffe_cfg[0]};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

58

const uint8_t vendor_lttpr_write_data_ffe3[4] = {0x01, 0x56, dp_type, ffe_cfg[1]};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

59

const uint8_t vendor_lttpr_write_data_ffe4[4] = {0x01, 0x57, dp_type, ffe_cfg[2]};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

60

const uint8_t vendor_lttpr_write_data_ffe5[4] = {0x01, 0x58, dp_type, ffe_cfg[3]};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

77

uint8_t clk_src = 0xC4;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

78

uint8_t pattern = 0x4F; /* SQ128 */

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

80

const uint8_t vendor_lttpr_write_data_pg0[4] = {0x1, 0x11, 0x0, 0x0};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

81

const uint8_t vendor_lttpr_write_data_pg1[4] = {0x1, 0x50, 0x50, clk_src};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

82

const uint8_t vendor_lttpr_write_data_pg2[4] = {0x1, 0x51, 0x50, clk_src};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

83

const uint8_t vendor_lttpr_write_data_pg3[4] = {0x1, 0x10, 0x58, 0x21};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

84

const uint8_t vendor_lttpr_write_data_pg4[4] = {0x1, 0x10, 0x59, 0x21};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

85

const uint8_t vendor_lttpr_write_data_pg5[4] = {0x1, 0x1C, 0x58, pattern};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

86

const uint8_t vendor_lttpr_write_data_pg6[4] = {0x1, 0x1C, 0x59, pattern};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

87

const uint8_t vendor_lttpr_write_data_pg7[4] = {0x1, 0x30, 0x51, 0x20};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

88

const uint8_t vendor_lttpr_write_data_pg8[4] = {0x1, 0x30, 0x52, 0x20};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

89

const uint8_t vendor_lttpr_write_data_pg9[4] = {0x1, 0x30, 0x54, 0x20};

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

90

const uint8_t vendor_lttpr_write_data_pg10[4] = {0x1, 0x30, 0x55, 0x20};

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1563

const uint8_t *edid,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

269

uint8_t slave_address = HDMI_SCDC_ADDRESS;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

270

uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

290

uint8_t *buffer,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

293

uint8_t offs_data = 0;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

327

uint8_t i;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

330

uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];

drivers/gpu/drm/amd/display/dc/link/link_detection.c

527

uint8_t link_bw_set = 0;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

528

uint8_t link_rate_set = 0;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

881

static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])

drivers/gpu/drm/amd/display/dc/link/link_detection.c

909

uint8_t edid_header[8] = {0};

drivers/gpu/drm/amd/display/dc/link/link_detection.h

34

const uint8_t *edid,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

104

uint8_t dpcd_power_state = '\0';

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1184

uint8_t dpcd_buf[3] = {0};

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1538

const uint8_t vc_id = 1; /// VC ID always 1 for SST

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1539

const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1541

uint8_t req_slot_count = 0;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

155

uint8_t count;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

209

uint8_t *count,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

324

uint8_t address, uint8_t *buffer, uint32_t length)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

355

uint8_t slave_address = (settings->slv_addr >> 1);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

356

uint8_t buffer[2];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

357

const uint8_t apply_rx_tx_change = 0x4;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

358

uint8_t offset = 0xA;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

359

uint8_t value = 0;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

516

uint8_t slave_address = (0xBA >> 1);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

517

uint8_t buffer[2];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

638

uint8_t slave_address = (0xF0 >> 1);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

639

uint8_t buffer[16];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

680

config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

683

config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

81

uint8_t dpcd_power_state = '\0';

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

964

uint8_t dsc_packed_pps[128];

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

41

uint8_t *count,

drivers/gpu/drm/amd/display/dc/link/link_factory.c

478

uint8_t i;

drivers/gpu/drm/amd/display/dc/link/link_validation.c

395

uint8_t link_count = 0;

drivers/gpu/drm/amd/display/dc/link/link_validation.c

399

for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

425

for (uint8_t j = 0; j < MAX_DPIA_NUM; j++) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

450

uint8_t layouts_per_sample_denom;

drivers/gpu/drm/amd/display/dc/link/link_validation.c

451

uint8_t symbols_per_layout;

drivers/gpu/drm/amd/display/dc/link/link_validation.c

452

uint8_t max_layouts_per_audio_sdp;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

316

uint8_t *write_buf,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

318

uint8_t *read_buf,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

416

uint8_t offset;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

45

static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

459

bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

466

.data = (uint8_t *) data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

47

static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

477

bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

48

static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

513

const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

545

uint8_t slave_address = HDMI_SCDC_ADDRESS;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

546

uint8_t offset = HDMI_SCDC_SINK_VERSION;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

547

uint8_t sink_version = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

548

uint8_t write_buffer[2] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

581

uint8_t slave_address = HDMI_SCDC_ADDRESS;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

582

uint8_t offset = HDMI_SCDC_TMDS_CONFIG;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

583

uint8_t tmds_config = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

593

uint8_t scramble_status = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

90

uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

59

uint8_t *write_buf,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

61

uint8_t *read_buf,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

77

const uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

82

uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1060

(uint8_t *)&dp_id,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1078

uint8_t dpcd_power_state = '\0';

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1159

uint8_t data, struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1191

uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1274

(uint8_t *)&dp_hw_fw_revision,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1289

(uint8_t *)link->dpcd_caps.branch_vendor_specific_data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1346

uint8_t dpcd_data[16] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

136

uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1414

uint8_t dpcd_dp_edp_backlight_mode = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1421

&dpcd_dp_edp_backlight_mode, sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1425

&dpcd_dp_edp_backlight_mode, sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1429

(uint8_t)(link->ctx->asic_id.chip_id);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1431

(uint8_t)(link->ctx->asic_id.chip_id >> 8);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1433

(uint8_t)(link->ctx->dce_version);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1438

(uint8_t *)(&amd_signature),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1450

(uint8_t *)(&amd_signature),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1455

(uint8_t *)(&amd_device_id),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1461

uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1464

DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1531

&link->dpcd_caps.cable_id.raw, sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1573

uint8_t dpcd_data = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1574

uint8_t edp_general_cap2 = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1598

uint8_t dpcd_data = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

161

uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1633

uint8_t lttpr_dpcd_data[10] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

169

uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1741

uint8_t dpcd_data[16];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1744

uint8_t dpcd_dprx_data = '\0';

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1830

uint8_t ext_cap_data[16];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1961

(uint8_t *)(&sink_id),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1977

(uint8_t *)&dp_hw_fw_revision,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1990

uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1991

uint8_t fwrev_mbp_2018[] = { 7, 4 };

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1992

uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2164

uint8_t supported_link_rates[16];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2168

uint8_t backlight_adj_cap = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2169

uint8_t general_edp_cap = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2262

(uint8_t *)&link->dpcd_caps.edp_oled_emission_rate,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2269

(uint8_t *)&link->dpcd_caps.drr_granularity,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2280

(uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2286

(uint8_t *)&link->dpcd_caps.dp_edp_general_cap_2,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2443

uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2559

uint8_t retry = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2614

uint8_t dp_get_lttpr_count(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

300

static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

407

uint8_t max_link_bw)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

107

uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

111

uint8_t dp_get_lttpr_count(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

49

uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

52

uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

52

uint8_t dpcd_dp_tun_data[3] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

53

uint8_t dpcd_topology_data[DPCD_USB4_TOPOLOGY_ID_LEN] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

54

uint8_t i = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

104

uint8_t bw_estimated_bw = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

110

sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

117

uint8_t nrd_max_link_rate = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

123

sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

130

uint8_t nrd_max_lane_count = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

136

sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

183

uint8_t request_reg_val;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

217

sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

226

uint8_t val;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

230

if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

269

void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

368

bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

375

uint8_t i;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

377

uint8_t router_count = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

400

for (uint8_t j = 0; j < MAX_HOST_ROUTERS_NUM; j++) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

76

static uint8_t get_bw_granularity(struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

78

uint8_t bw_granularity = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

84

sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

109

bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

43

uint8_t cm_id;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

44

uint8_t dpia_count;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

99

void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

312

uint8_t count;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

337

uint8_t tunneling_status = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

407

uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

52

uint8_t irq_reg_rx_power_state = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

103

(uint8_t *)&(pr_config_1.raw), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

107

(uint8_t *)&(pr_config_2.raw), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

170

(uint8_t *)&(pr_config_1.raw), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

174

(uint8_t *)&(pr_config_2.raw), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

198

(uint8_t *)&(data), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

93

uint8_t data = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

147

uint8_t fec_config = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

46

uint8_t state;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1020

uint8_t sink_status = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1022

uint8_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1058

(uint8_t *) &encoding,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1097

uint8_t rate;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1103

downspread.raw = (uint8_t)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1137

uint8_t supported_link_rates[16] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1198

(uint8_t *)(link_training_setting->dpcd_lane_settings),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1232

uint8_t dpcd_lt_buffer[5] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1334

(uint8_t *)(lt_settings->dpcd_lane_settings),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1369

uint8_t *custom_pattern,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1627

uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

179

uint8_t dp_initialize_scrambling_data_symbols(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

183

uint8_t disable_scrabled_data_symbols = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

257

uint8_t dp_get_nibble_at_index(const uint8_t *buf,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

260

uint8_t nibble;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

359

uint8_t lane = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

365

(uint8_t)(hw_lane_settings[lane].VOLTAGE_SWING);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

367

(uint8_t)(hw_lane_settings[lane].PRE_EMPHASIS);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

382

uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

384

uint8_t link_rate = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

403

link_rate = (uint8_t) link_settings->link_rate;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

520

uint8_t retries)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

533

uint8_t retries)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

560

uint8_t dpcd_buf[6] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

566

(uint8_t *)(dpcd_buf),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

603

uint8_t lane_adjust_offset = 4;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

605

uint8_t dpcd_buf[6] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

619

(uint8_t *)(dpcd_buf),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

716

DC_LOG_DC("lttpr_mode_override chose LTTPR_MODE = %d\n", (uint8_t)(*override));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

905

uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

910

(uint8_t *)&repeater_mode,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

920

uint8_t repeater_cnt;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

922

uint8_t repeater_id;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

924

uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

933

(uint8_t *)&repeater_mode,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

949

(uint8_t *)&repeater_mode,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

971

(uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

154

uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

173

uint8_t dp_initialize_scrambling_data_symbols(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

185

uint8_t dp_get_nibble_at_index(const uint8_t *buf,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

190

uint8_t retries);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

196

uint8_t retries);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

55

uint8_t *custom_pattern,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

45

(uint8_t *)(link_training_setting->dpcd_lane_settings),

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

76

uint8_t loop_count;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

430

uint8_t repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

431

uint8_t repeater_id;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

432

uint8_t lane = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

62

(uint8_t *)&training_rd_interval,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

88

(uint8_t *)&training_rd_interval,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

95

(uint8_t *)&training_rd_interval,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

149

uint8_t msg_type,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

150

uint8_t msg_data)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

170

static uint8_t dpia_build_set_config_data(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

294

uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

303

uint8_t set_cfg_data;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

589

uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

598

uint8_t set_cfg_data;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

72

uint8_t mode : 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

73

uint8_t reserved : 7;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

76

uint8_t stage;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

79

uint8_t swing : 2;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

80

uint8_t max_swing_reached : 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

81

uint8_t pre_emph : 2;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

82

uint8_t max_pre_emph_reached : 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

83

uint8_t reserved : 2;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

85

uint8_t raw;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

865

uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

946

uint8_t data = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

974

uint8_t pattern,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

977

uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

996

uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h

57

uint8_t pattern,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

106

uint8_t lane = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

107

uint8_t toggle_rate = 0x6;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

108

uint8_t target_rate = 0x6;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

110

uint8_t repeater_cnt;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

111

uint8_t repeater_id;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

194

const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

195

const uint8_t offset = dp_parse_lttpr_repeater_count(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

197

const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

198

const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x6E};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

199

const uint8_t vendor_lttpr_write_data_adicora_eq1[4] = {0x1, 0x55, 0x63, 0x2E};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

200

const uint8_t vendor_lttpr_write_data_adicora_eq2[4] = {0x1, 0x55, 0x63, 0x01};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

201

const uint8_t vendor_lttpr_write_data_adicora_eq3[4] = {0x1, 0x55, 0x63, 0x68};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

203

uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

204

uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

205

const uint8_t vendor_lttpr_write_data_4lane_1[4] = {0x1, 0x6E, 0xF2, 0x19};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

206

const uint8_t vendor_lttpr_write_data_4lane_2[4] = {0x1, 0x6B, 0xF2, 0x01};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

207

const uint8_t vendor_lttpr_write_data_4lane_3[4] = {0x1, 0x6D, 0xF2, 0x18};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

208

const uint8_t vendor_lttpr_write_data_4lane_4[4] = {0x1, 0x6C, 0xF2, 0x03};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

209

const uint8_t vendor_lttpr_write_data_4lane_5[4] = {0x1, 0x03, 0xF3, 0x06};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

210

const uint8_t vendor_lttpr_write_data_dpmf[4] = {0x1, 0x6, 0x70, 0x87};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

212

uint8_t lane = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

215

uint8_t toggle_rate;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

216

uint8_t rate;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

251

downspread.raw = (uint8_t)(lt_settings->link_settings.link_spread);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

322

const uint8_t max_vendor_dpcd_retries = 10;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

330

uint8_t i = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

48

const uint8_t vendor_lttpr_write_data_vs[3] = {0x0, 0x53, 0x63};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

49

const uint8_t vendor_lttpr_write_data_pe[3] = {0x0, 0x54, 0x63};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

50

uint8_t dprx_vs = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

51

uint8_t dprx_pe = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

52

uint8_t lane;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

75

uint8_t lane_count)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

77

const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

78

uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

79

uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

80

uint8_t lane = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.h

39

uint8_t lane_count);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

140

uint8_t * const in_data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

143

uint8_t **out_data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

177

uint8_t * const extended_data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

180

uint8_t * const reduced_data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

200

uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

205

uint8_t *extended_data;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

233

const uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

47

uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c

62

const uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h

34

uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h

40

const uint8_t *data,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1010

(uint8_t *)&(replay_config.raw), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1061

(uint8_t *)&(replay_config.raw), sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1251

uint8_t link_enc_index = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1252

uint8_t phy_type = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1253

uint8_t phy_id = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

170

uint8_t backlight_enable = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

181

&backlight_enable, sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

189

&backlight_enable, sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

199

(uint8_t *)(target_luminance),

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

207

uint8_t backlight_control = isHDR ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

208

uint8_t backlight_enable = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

216

&backlight_enable, sizeof(uint8_t));

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

225

(uint8_t *)(&dpcd_backlight_set),

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

271

uint8_t backlight_enable = enable ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

296

(uint8_t *)backlight_millinits,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

304

(uint8_t *)backlight_millinits,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

353

uint8_t link_bw_set = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

354

uint8_t link_rate_set = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

50

static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

52

static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

482

MCIF_WB_REG_FIELD_LIST_DCN2_0(uint8_t);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h

64

MCIF_WB_REG_FIELD_LIST_DCN3_5(uint8_t);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

117

MPC_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

253

MPC_REG_FIELD_LIST_DCN2_0(uint8_t)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

982

MPC_REG_FIELD_LIST_DCN3_0(uint8_t);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

983

MPC_REG_FIELD_LIST_DCN32(uint8_t);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

178

MPC_REG_FIELD_LIST_DCN4_01(uint8_t);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

144

OPP_DCN10_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

123

OPP_DCN20_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

52

OPP_DCN35_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1560

bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

941

(uint8_t)params->vertical_total_mid_frame_num);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

684

TG_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

685

TG_REG_FIELD_LIST_DCN2_0(uint8_t)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

686

TG_REG_FIELD_LIST_DCN3_2(uint8_t)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

687

TG_REG_FIELD_LIST_DCN3_5(uint8_t)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

688

TG_REG_FIELD_LIST_DCN3_6(uint8_t)

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

689

TG_REG_FIELD_LIST_DCN401(uint8_t)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

261

uint8_t master_clock_divider,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

262

uint8_t slave_clock_divider)

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

70

(uint8_t)params->vertical_total_mid_frame_num);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

197

(uint8_t)params->vertical_total_mid_frame_num);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

290

(uint8_t)params->vertical_total_mid_frame_num);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

206

static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

417

(uint8_t)params->vertical_total_mid_frame_num);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

355

(uint8_t)params->vertical_total_mid_frame_num);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

127

PG_CNTL_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

128

PG_CNTL_DCN35_REG_FIELD_LIST(uint8_t);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1030

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1211

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h

39

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1352

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1539

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h

44

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1228

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1422

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h

35

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1063

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1294

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h

35

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1094

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1112

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1292

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1310

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1489

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

914

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

35

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

39

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h

43

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1105

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1123

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1305

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1323

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1503

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

920

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

35

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

39

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h

43

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1347

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2425

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1121

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1411

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2302

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2395

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2403

uint8_t is_vbios_interop_enabled = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1441

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1521

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1529

uint8_t is_vbios_interop_enabled = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1235

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1315

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1323

uint8_t is_vbios_interop_enabled = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1176

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1260

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1268

uint8_t is_vbios_interop_enabled = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1334

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1914

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2001

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2281

uint8_t pipe_count,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

71

uint8_t pipe_count,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1393

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1845

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1933

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1335

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1885

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1963

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1329

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1760

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1838

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1333

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2166

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2324

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

243

static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

246

uint8_t fhd_count = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

247

uint8_t subvp_high_refresh_count = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

248

uint8_t stream_count = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

316

uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

317

uint8_t pipe_counted[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

318

uint8_t pipe_cnt = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

320

uint8_t stream_count = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

648

uint8_t subvp_count = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

649

uint8_t non_subvp_pipes = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

708

uint8_t subvp_count = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

709

uint8_t non_subvp_pipes = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1314

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1669

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1823

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1397

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1844

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1973

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1377

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1817

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1944

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1384

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1823

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1951

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1307

uint8_t inst,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1855

uint8_t num_virtual_links,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2024

uint8_t is_vbios_lttpr_enable = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

454

uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

484

byte_ptr_1dlut_src = (uint8_t *)filter_isharp_1D_lut_3p0x;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

485

byte_ptr_1dlut_dst = (uint8_t *)filter_pregen_store;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

499

*byte_ptr_1dlut_dst = (uint8_t)sharp_calc_int;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1039

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

230

const uint8_t *fw_inst_const;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

231

const uint8_t *fw_bss_data;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

247

const uint8_t *fw_inst_const;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

248

const uint8_t *fw_bss_data;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

270

uint8_t num_regions;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

306

uint8_t num_fb;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

387

uint8_t is_dmcub_enabled : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

388

uint8_t is_dmcub_soft_reset : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

389

uint8_t is_dmcub_secure_reset : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

390

uint8_t is_traceport_en : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

391

uint8_t is_cw0_enabled : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

392

uint8_t is_cw6_enabled : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

393

uint8_t is_pwait : 1;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

539

void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

649

uint8_t link_index;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

650

uint8_t result;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

652

uint8_t instance;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

1253

uint8_t reserved[28]; /**< Reserved bytes. */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

1261

uint8_t reserved[56]; /**< reserved for future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2071

uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2156

uint8_t cursor_bpp; /**< Cursor bits per pixel */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2157

uint8_t debug_bits; /**< Debug bits */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2159

uint8_t reserved1; /**< Reserved bits */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2160

uint8_t reserved2; /**< Reserved bits */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2190

uint8_t cab_alloc_ways; /* total number of ways */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2191

uint8_t debug_bits; /* debug bits */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2221

uint8_t main_pipe_index;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2222

uint8_t phantom_pipe_index;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2229

uint8_t scale_factor_numerator;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2230

uint8_t scale_factor_denominator;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2231

uint8_t is_drr;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2232

uint8_t main_split_pipe_index;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2233

uint8_t phantom_split_pipe_index;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2243

uint8_t vblank_pipe_index;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2244

uint8_t padding[1];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2246

uint8_t drr_in_use;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2247

uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2250

uint8_t use_ramping; // Use ramping or not

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2251

uint8_t drr_vblank_start_margin;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2260

uint8_t mode; // enum mclk_switch_mode

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2270

uint8_t vertical_int_margin_us;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2271

uint8_t pstate_allow_width_us;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2299

uint8_t is_immediate: 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2301

uint8_t all;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2303

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2304

uint8_t pipe_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2305

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2467

uint8_t program_manual_trigger;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2468

uint8_t tg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2469

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2517

uint8_t vactive_det_fill_delay_otg_vlines;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2518

uint8_t programming_delay_otg_vlines;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2528

uint8_t is_multi_planar : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2529

uint8_t is_yuv420 : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2531

uint8_t all;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2533

uint8_t programming_delay_otg_vlines;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2534

uint8_t prefetch_to_mall_otg_vlines;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2535

uint8_t phantom_otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2536

uint8_t phantom_pipe_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2537

uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2542

uint8_t programming_delay_otg_vlines;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2543

uint8_t only_stretch_if_required;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2544

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2562

uint8_t is_multi_planar : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2563

uint8_t is_yuv420 : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2565

uint8_t all;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2567

uint8_t phantom_otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2568

uint8_t phantom_pipe_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2569

uint8_t pad0;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2570

uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2571

uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2577

uint8_t only_stretch_if_required;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2578

uint8_t pad[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2607

uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2608

uint8_t contention_delay_otg_vlines; // time to budget for contention on execution

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2609

uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2610

uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2613

uint8_t is_drr: 1; // stream is DRR enabled

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2614

uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2615

uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2617

uint8_t all;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2619

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2620

uint8_t pipe_mask; // pipe mask for the whole config

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2621

uint8_t num_planes;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2622

uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2623

uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2645

uint8_t is_drr : 1; // stream is DRR enabled

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2646

uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2647

uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2649

uint8_t all;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2651

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2652

uint8_t pipe_mask; // pipe mask for the whole config

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2653

uint8_t num_planes;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2654

uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2655

uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2780

uint8_t driver_idle;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2781

uint8_t skip_otg_disable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2782

uint8_t reserved[58];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2808

uint8_t power_state; /**< power state */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2809

uint8_t pad[3]; /**< padding */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2897

uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2898

uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2900

uint8_t digmode; /**< enum atom_encode_mode_def */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2901

uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2903

uint8_t lanenum; /**< Number of lanes */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2907

uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2908

uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2909

uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2910

uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2911

uint8_t reserved1; /**< For future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2912

uint8_t skip_phy_ssc_reduction;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2913

uint8_t reserved2[2]; /**< For future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2937

uint8_t inst : 6; /**< DOMAIN instance to control */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2938

uint8_t power_gate : 1; /**< 1=power gate, 0=power up */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2939

uint8_t reserved[3]; /**< Reserved for future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2954

uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2955

uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2957

uint8_t digmode; /** enum atom_encode_mode_def */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2958

uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2960

uint8_t lanenum; /** Lane number 1, 2, 4, 8 */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2962

uint8_t hpdsel; /** =0: HPD is not assigned */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2963

uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2964

uint8_t dpia_id; /** Index of DPIA */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2965

uint8_t fec_rdy : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2966

uint8_t reserved : 7;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2982

uint8_t msg_type; /* set config message type */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2983

uint8_t msg_data; /* set config message data */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2991

uint8_t instance; /* DPIA instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2992

uint8_t immed_status; /* Immediate status returned in case of error */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

2999

uint8_t instance; /* DPIA instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3000

uint8_t immed_status; /* Immediate status returned in case of error */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3001

uint8_t msg_type; /* set config message type */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3002

uint8_t reserved;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3026

uint8_t mst_alloc_slots; /* mst slots to be allotted */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3027

uint8_t instance; /* DPIA instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3028

uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3029

uint8_t mst_slots_in_use; /* returns slots in use for error cases */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3044

uint8_t instance; /* DPIA instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3045

uint8_t tps; /* requested training pattern */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3046

uint8_t reserved1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3047

uint8_t reserved2;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3071

uint8_t reserved[60]; /**< reserved bits */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3134

uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3135

uint8_t action; /**< enum dp_aux_request_action */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3136

uint8_t length; /**< DP AUX request data length */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3137

uint8_t reserved; /**< For future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3139

uint8_t data[16]; /**< DP AUX write data */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3146

uint8_t instance; /**< AUX instance or DPIA instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3147

uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3148

uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3149

uint8_t reserved0; /**< For future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3193

uint8_t command;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3197

uint8_t length;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3201

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3205

uint8_t data[16];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3219

uint8_t instance;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3223

uint8_t result;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3288

uint8_t instance;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3292

uint8_t hpd_type;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3296

uint8_t hpd_status;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3300

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3331

uint8_t instance; /* DPIA Instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3332

uint8_t status; /* Set Config reply */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3348

uint8_t instance; /**< DPIA Instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3349

uint8_t reserved[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3357

uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3378

uint8_t cm_id; /**< CM ID */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3379

uint8_t group_id; /**< Group ID */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3380

uint8_t granularity; /**< BW Allocation Granularity */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3381

uint8_t estimated_bw; /**< Estimated_BW */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3382

uint8_t allocated_bw; /**< Allocated_BW */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3383

uint8_t reserved;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3421

uint8_t instance; /**< HPD instance or DPIA instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3422

uint8_t result; /**< For returning HPD state */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3650

uint8_t dpp_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3656

uint8_t mpcc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3662

uint8_t opp_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3666

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3670

uint8_t digfe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3674

uint8_t digbe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3678

uint8_t dpphy_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3682

uint8_t aux_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3686

uint8_t smu_optimizations_en;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3691

uint8_t frame_delay;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3699

uint8_t frame_cap_ind;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3703

uint8_t su_y_granularity;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3709

uint8_t line_capture_indication;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3713

uint8_t multi_disp_optimizations_en;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3722

uint8_t rate_control_caps;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3726

uint8_t force_ffu_mode;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3734

uint8_t fec_enable_status;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3739

uint8_t fec_enable_delay_in100us;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3743

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3749

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3753

uint8_t dsc_enable_status;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3757

uint8_t use_phy_fsm;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3761

uint8_t relock_delay_frame_cnt;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3765

uint8_t esd_recovery;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3779

uint8_t power_down_phy_before_disable_stream;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3807

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3813

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3834

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3840

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3845

uint8_t phy_fsm_state;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3851

uint8_t phy_rate;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3878

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3884

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3888

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3909

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3915

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3919

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3947

uint8_t update_dirty_rect_only : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3951

uint8_t reset_state : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3976

uint8_t pipe_idx;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3980

uint8_t dirty_rect_count;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3984

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3990

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3994

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

3998

uint8_t padding[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4075

uint8_t pipe_idx;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4079

uint8_t padding[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4122

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4126

uint8_t pipe_idx;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4130

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4136

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4145

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4149

uint8_t padding[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4185

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4191

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4199

uint8_t pad2[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4223

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4229

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4233

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4448

uint8_t lttpr_count;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4452

uint8_t pad[1];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4472

uint8_t dpp_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4476

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4480

uint8_t digfe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4484

uint8_t digbe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4488

uint8_t aux_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4494

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4499

uint8_t pixel_deviation_per_line;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4504

uint8_t max_deviation_line;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4512

uint8_t dpphy_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4516

uint8_t smu_optimizations_en;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4520

uint8_t replay_timing_sync_supported;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4524

uint8_t use_phy_fsm;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4532

uint8_t hpo_stream_enc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4536

uint8_t hpo_link_enc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4540

uint8_t replay_support_fast_resync_in_ultra_sleep_mode;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4544

uint8_t pad[1];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4601

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4607

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4613

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4617

uint8_t digfe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4621

uint8_t digbe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4622

uint8_t debugcontrol;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4630

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4640

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4646

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4651

uint8_t phy_fsm_state;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4657

uint8_t phy_rate;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4682

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4686

uint8_t pad[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4702

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4706

uint8_t timing_sync_supported;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4710

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4722

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4730

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4738

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4742

uint8_t force_disabled;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4744

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4752

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4756

uint8_t subtype;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4758

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4792

uint8_t cmd_version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4798

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4906

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4910

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4939

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4990

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4991

uint8_t pad[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

4996

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5028

uint8_t lock_pipe : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5032

uint8_t lock_cursor : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5036

uint8_t lock_dig : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5040

uint8_t triple_buffer_lock : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5046

uint8_t u8All;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5059

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5063

uint8_t opp_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5068

uint8_t dig_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5072

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5122

uint8_t lock;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5127

uint8_t should_release;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5131

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5272

uint8_t num_int_bits;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5277

uint8_t num_frac_bits;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5282

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5289

uint8_t num_hg_bins;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5294

uint8_t num_ace_segments;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5299

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5356

uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5360

uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5364

uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5368

uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5372

uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5376

uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5380

uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5384

uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5388

uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5392

uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5396

uint8_t pad3[3]; // 229B

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5414

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5419

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5424

uint8_t set_pipe_option;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5430

uint8_t ramping_boundary;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5435

uint8_t pwrseq_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5440

uint8_t pad[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5493

uint8_t version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5500

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5505

uint8_t aux_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5510

uint8_t pad[1];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5568

uint8_t version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5575

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5580

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5610

uint8_t version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5617

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5622

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5653

uint8_t version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5660

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5665

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5701

uint8_t version;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5708

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5713

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5742

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5747

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5752

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5757

uint8_t pad[1];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5782

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5787

uint8_t pad[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5878

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5883

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5913

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5918

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5933

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5938

uint8_t freeze;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5943

uint8_t debug;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5968

uint8_t vb_scaling_enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5974

uint8_t panel_mask;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

5979

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6073

uint8_t is_backlight_on : 1; /* in/out */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6074

uint8_t is_powered_on : 1; /* in/out */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6075

uint8_t padding[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6077

uint8_t reserved[4];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6101

uint8_t max_ramp_step;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6102

uint8_t pipes;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6103

uint8_t min_refresh_in_hz;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6104

uint8_t pipe_count;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6105

uint8_t pipe_index[4];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6109

uint8_t fams_enabled;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6110

uint8_t visual_confirm_enabled;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6124

uint8_t uc_pwr_action; /**< LVTMA_ACTION */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6125

uint8_t bypass_panel_control_wait;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6126

uint8_t reserved_0[2]; /**< For future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6127

uint8_t pwrseq_inst; /**< LVTMA control instance */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6128

uint8_t reserved_1[3]; /**< For future use */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6149

uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6150

uint8_t is_usb; /**< is phy is usb */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6151

uint8_t is_dp_alt_disable; /**< is dp alt disable */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6152

uint8_t is_dp4; /**< is dp in 4 lane */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6164

uint8_t mode;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6165

uint8_t pat0;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6166

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6173

uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6174

uint8_t mode; /**< HDMI/DP/DP2 etc */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6175

uint8_t lane_num; /**< Number of lanes */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6180

uint8_t pad;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6201

uint8_t length; /**< number of bytes in payload to copy as part of CEA block */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6203

uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6204

uint8_t pad[3]; /**< padding and for future expansion */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6211

uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6212

uint8_t freesync_supported; /**< 1 if Freesync is supported */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6223

uint8_t success; /**< 1 if this sending of chunk succeeded */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6224

uint8_t pad; /**< padding and for future expansion */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6243

uint8_t type; /**< dmub_cmd_edid_cea_reply_type */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6257

uint8_t phy_inst; /**< phy inst for cable id data */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6264

uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6265

uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6266

uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6267

uint8_t RESERVED :2; /**< reserved means not defined */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6281

uint8_t output_raw; /**< Raw data output */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6311

uint8_t status;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6312

uint8_t type : 2;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6313

uint8_t _reserved0 : 3;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6314

uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6315

uint8_t identifier;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6316

uint8_t _reserved1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6320

uint8_t is_aux : 1; // False

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6321

uint8_t ddc_line : 3;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6322

uint8_t over_aux : 1;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6323

uint8_t _reserved0 : 3;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6324

uint8_t address;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6325

uint8_t offset;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6326

uint8_t length;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6335

uint8_t buffer[0x30]; // Read: out, write: in, poll: expected

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6361

uint8_t otg_id;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6362

uint8_t phy_id;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6374

uint8_t otg_id;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6375

uint8_t phy_id;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6405

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6410

uint8_t phy_port_type;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6414

uint8_t phy_port_id;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6418

uint8_t link_enc_index;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6422

uint8_t hpo_mode;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6427

uint8_t reserved[7];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6482

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6483

uint8_t start_measurement;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6484

uint8_t padding[2]; // align to 4-byte boundary

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6499

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6500

uint8_t padding[3]; // align to 4-byte boundary

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6549

uint8_t enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6555

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6560

uint8_t phy_fsm_state;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6566

uint8_t phy_rate;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6570

uint8_t hpo_stream_enc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6574

uint8_t hpo_link_enc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6578

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6611

uint8_t dpp_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6615

uint8_t otg_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6619

uint8_t digfe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6623

uint8_t digbe_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6627

uint8_t aux_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6633

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6637

uint8_t dpphy_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6641

uint8_t smu_optimizations_en;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6665

uint8_t use_phy_fsm;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6669

uint8_t hpo_stream_enc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6673

uint8_t hpo_link_enc_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6677

uint8_t su_granularity_needed;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6689

uint8_t su_y_granularity;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6693

uint8_t main_link_activity_option;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6723

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6725

uint8_t pad[3]; // align to 4-byte boundary

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6745

uint8_t panel_inst;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6749

uint8_t subtype;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

6751

uint8_t pad[2];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7292

uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7293

const uint8_t *src = (const uint8_t *)cmd;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7294

uint8_t i;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7325

uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7326

const uint8_t *src = (const uint8_t *)cmd;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7355

uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7398

uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7419

const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7421

uint8_t i;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7473

uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7474

uint8_t i;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

751

uint8_t minor : 5;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7510

uint8_t *rd_ptr = (rb->rptr == 0) ?

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7511

(uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

7512

(uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

752

uint8_t major : 3;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

754

uint8_t ver;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

765

uint8_t psr;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

766

uint8_t fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

767

uint8_t reserved[4];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

768

uint8_t subvp_psr_support;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

769

uint8_t gecc_enable;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

770

uint8_t replay_supported;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

771

uint8_t replay_reserved[3];

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

772

uint8_t abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

773

uint8_t lsdma_support_in_dmu;

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

862

uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

937

uint8_t dal_fw; /**< 1 if the firmware is DAL */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

938

uint8_t reserved[3]; /**< padding bits */

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

950

uint8_t reserved[64]; /**< padding bits */

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

164

#define DMUB_SF(reg, field) uint8_t reg##__##field;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

165

#define DMUB_SF(reg, field) uint8_t reg##__##field;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

533

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

181

#define DMUB_SF(reg, field) uint8_t reg##__##field;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

269

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

183

#define DMUB_SF(reg, field) uint8_t reg##__##field;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

183

#define DMUB_SF(reg, field) uint8_t reg##__##field;

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

104

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

36

uint32_t value, uint32_t mask, uint8_t shift)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

44

uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

67

uint8_t shift)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

72

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

90

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

115

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

117

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

120

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1167

uint8_t i;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1168

uint8_t loop_count;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

117

dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1244

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

639

out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

642

out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

819

rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

98

const uint8_t *base = (const uint8_t *)fb->cpu_addr;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

99

uint8_t buf[64];

drivers/gpu/drm/amd/display/include/audio_types.h

57

uint8_t pixel_repetition;

drivers/gpu/drm/amd/display/include/bios_parser_interface.h

35

uint8_t *bios;

drivers/gpu/drm/amd/display/include/ddc_service_types.h

122

uint8_t av_granularity;/* DPCD 00023h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

123

uint8_t aud_dec_lat1;/* DPCD 00024h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

124

uint8_t aud_dec_lat2;/* DPCD 00025h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

125

uint8_t aud_pp_lat1;/* DPCD 00026h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

126

uint8_t aud_pp_lat2;/* DPCD 00027h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

127

uint8_t vid_inter_lat;/* DPCD 00028h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

128

uint8_t vid_prog_lat;/* DPCD 00029h */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

129

uint8_t aud_del_ins1;/* DPCD 0002Bh */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

130

uint8_t aud_del_ins2;/* DPCD 0002Ch */

drivers/gpu/drm/amd/display/include/ddc_service_types.h

131

uint8_t aud_del_ins3;/* DPCD 0002Dh */

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

100

uint8_t hpd_active;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

176

uint8_t min_allowed_bl_level;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

177

uint8_t remote_display_config;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

183

uint8_t oem_i2c_obj_id;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

243

uint8_t lane0:2; /* Mapping for lane 0 */

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

244

uint8_t lane1:2; /* Mapping for lane 1 */

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

245

uint8_t lane2:2; /* Mapping for lane 2 */

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

246

uint8_t lane3:2; /* Mapping for lane 3 */

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

248

uint8_t raw;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

292

uint8_t edp_pwr_on_off_delay;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

293

uint8_t edp_pwr_on_vary_bl_to_blon;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

294

uint8_t edp_pwr_down_bloff_to_vary_bloff;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

295

uint8_t edp_panel_bpc;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

296

uint8_t edp_bootup_bl_level;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

319

uint8_t ext_aux_ddc_lut_index;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

321

uint8_t ext_hpd_pin_lut_index;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

330

uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

331

uint8_t checksum;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

332

uint8_t fixdpvoltageswing;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

344

uint8_t memory_type;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

345

uint8_t ma_channel_number;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

99

uint8_t hpd_int_gpio_uid;

drivers/gpu/drm/amd/display/include/hdcp_msg_types.h

103

uint8_t max_retries;

drivers/gpu/drm/amd/display/include/hdcp_msg_types.h

104

uint8_t *data;

drivers/gpu/drm/amd/display/include/link_service_types.h

218

uint8_t VOLTAGE_SWING_SET:2;

drivers/gpu/drm/amd/display/include/link_service_types.h

219

uint8_t MAX_SWING_REACHED:1;

drivers/gpu/drm/amd/display/include/link_service_types.h

220

uint8_t PRE_EMPHASIS_SET:2;

drivers/gpu/drm/amd/display/include/link_service_types.h

221

uint8_t MAX_PRE_EMPHASIS_REACHED:1;

drivers/gpu/drm/amd/display/include/link_service_types.h

223

uint8_t POST_CURSOR2_SET:2;

drivers/gpu/drm/amd/display/include/link_service_types.h

225

uint8_t POST_CURSOR2_SET:2;

drivers/gpu/drm/amd/display/include/link_service_types.h

226

uint8_t MAX_PRE_EMPHASIS_REACHED:1;

drivers/gpu/drm/amd/display/include/link_service_types.h

227

uint8_t PRE_EMPHASIS_SET:2;

drivers/gpu/drm/amd/display/include/link_service_types.h

228

uint8_t MAX_SWING_REACHED:1;

drivers/gpu/drm/amd/display/include/link_service_types.h

229

uint8_t VOLTAGE_SWING_SET:2;

drivers/gpu/drm/amd/display/include/link_service_types.h

235

uint8_t raw;

drivers/gpu/drm/amd/display/include/link_service_types.h

249

uint8_t vcp_id;

drivers/gpu/drm/amd/display/include/link_service_types.h

252

uint8_t slot_count;

drivers/gpu/drm/amd/display/include/link_service_types.h

86

uint8_t eq_loop_count_limit;

drivers/gpu/drm/amd/display/include/set_mode_types.h

41

uint8_t info_frame_type;

drivers/gpu/drm/amd/display/include/set_mode_types.h

42

uint8_t version;

drivers/gpu/drm/amd/display/include/set_mode_types.h

43

uint8_t length;

drivers/gpu/drm/amd/display/include/set_mode_types.h

50

uint8_t hb0;

drivers/gpu/drm/amd/display/include/set_mode_types.h

51

uint8_t hb1;

drivers/gpu/drm/amd/display/include/set_mode_types.h

52

uint8_t hb2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

53

uint8_t sb[28]; /* sb0~sb27 */

drivers/gpu/drm/amd/display/include/set_mode_types.h

60

uint8_t CHECK_SUM:8;

drivers/gpu/drm/amd/display/include/set_mode_types.h

62

uint8_t S0_S1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

63

uint8_t B0_B1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

64

uint8_t A0:1;

drivers/gpu/drm/amd/display/include/set_mode_types.h

65

uint8_t Y0_Y1_Y2:3;

drivers/gpu/drm/amd/display/include/set_mode_types.h

67

uint8_t R0_R3:4;

drivers/gpu/drm/amd/display/include/set_mode_types.h

68

uint8_t M0_M1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

69

uint8_t C0_C1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

71

uint8_t SC0_SC1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

72

uint8_t Q0_Q1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

73

uint8_t EC0_EC2:3;

drivers/gpu/drm/amd/display/include/set_mode_types.h

74

uint8_t ITC:1;

drivers/gpu/drm/amd/display/include/set_mode_types.h

76

uint8_t VIC0_VIC7:8;

drivers/gpu/drm/amd/display/include/set_mode_types.h

78

uint8_t PR0_PR3:4;

drivers/gpu/drm/amd/display/include/set_mode_types.h

79

uint8_t CN0_CN1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

80

uint8_t YQ0_YQ1:2;

drivers/gpu/drm/amd/display/include/set_mode_types.h

87

uint8_t FR0_FR3:4;

drivers/gpu/drm/amd/display/include/set_mode_types.h

88

uint8_t ACE0_ACE3:4;

drivers/gpu/drm/amd/display/include/set_mode_types.h

90

uint8_t RID0_RID5:6;

drivers/gpu/drm/amd/display/include/set_mode_types.h

91

uint8_t FR4:1;

drivers/gpu/drm/amd/display/include/set_mode_types.h

92

uint8_t F157:1;

drivers/gpu/drm/amd/display/include/set_mode_types.h

94

uint8_t reserved[12];

drivers/gpu/drm/amd/display/include/vector.h

30

uint8_t *container;

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

926

uint8_t idx = 0, size = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

32

const uint8_t retry_limit = hdcp->connection.link.adjust.retry_limit;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

380

uint8_t index, struct mod_hdcp_output *output)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

423

uint8_t index,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

486

uint8_t index, struct mod_hdcp_display_query *query)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

52

static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c

72

static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

100

uint8_t repeater_auth_ack_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

101

uint8_t prepare_stream_manage;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

102

uint8_t stream_manage_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

103

uint8_t stream_ready_available;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

104

uint8_t stream_ready_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

105

uint8_t stream_ready_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

107

uint8_t rx_caps_read_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

108

uint8_t content_stream_type_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

109

uint8_t link_integrity_check_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

110

uint8_t stream_encryption_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

119

uint8_t an[8];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

120

uint8_t aksv[5];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

121

uint8_t ainfo;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

122

uint8_t bksv[5];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

124

uint8_t bcaps;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

126

uint8_t ksvlist[635];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

128

uint8_t vp[20];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

134

uint8_t hdcp2version_hdmi;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

135

uint8_t rxcaps_dp[3];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

136

uint8_t rxstatus[2];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

138

uint8_t ake_init[12];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

139

uint8_t ake_cert[534];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

140

uint8_t ake_no_stored_km[129];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

141

uint8_t ake_stored_km[33];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

142

uint8_t ake_h_prime[33];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

143

uint8_t ake_pairing_info[17];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

144

uint8_t lc_init[9];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

145

uint8_t lc_l_prime[33];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

146

uint8_t ske_eks[25];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

147

uint8_t rx_id_list[177]; // 22 + 5 * 31

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

149

uint8_t repeater_auth_ack[17];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

150

uint8_t repeater_auth_stream_manage[68]; // 6 + 2 * 31

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

152

uint8_t repeater_auth_stream_ready[33];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

153

uint8_t rxstatus_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

154

uint8_t content_stream_type_dp[2];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

163

uint8_t stream_management_retry_count;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

169

uint8_t is_repeater;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

170

uint8_t is_km_stored;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

171

uint8_t is_hdcp1_revoked;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

172

uint8_t is_hdcp2_revoked;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

174

uint8_t hdcp1_retry_count;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

175

uint8_t hdcp2_retry_count;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

188

uint8_t id;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

195

uint8_t rx_id_list_ready;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

196

uint8_t unexpected_event;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

211

uint8_t buf[2025];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

291

uint8_t mod_hdcp_execute_and_set(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

292

mod_hdcp_action func, uint8_t *flag,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

326

void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

327

uint8_t *buf, uint32_t buf_size);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

335

struct mod_hdcp *hdcp, uint8_t index);

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

393

static inline uint8_t is_dp_hdcp(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

398

static inline uint8_t is_dp_mst_hdcp(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

404

static inline uint8_t is_hdmi_dvi_sl_hdcp(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

410

static inline uint8_t current_state(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

416

struct mod_hdcp_output *output, uint8_t id)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

42

uint8_t bksv_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

426

static inline uint8_t is_in_hdcp1_states(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

43

uint8_t bksv_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

432

static inline uint8_t is_in_hdcp1_dp_states(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

438

static inline uint8_t is_in_hdcp2_states(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

44

uint8_t create_session;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

444

static inline uint8_t is_in_hdcp2_dp_states(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

45

uint8_t an_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

450

static inline uint8_t is_in_authenticated_states(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

458

static inline uint8_t is_hdcp1(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

46

uint8_t aksv_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

463

static inline uint8_t is_hdcp2(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

468

static inline uint8_t is_in_cp_not_desired_state(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

47

uint8_t ainfo_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

473

static inline uint8_t is_in_initialized_state(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

48

uint8_t bcaps_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

49

uint8_t r0p_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

50

uint8_t rx_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

51

uint8_t encryption;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

516

static inline uint8_t is_display_active(struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

52

uint8_t link_maintenance;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

521

static inline uint8_t is_display_encryption_enabled(struct mod_hdcp_display *display)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

526

static inline uint8_t get_active_display_count(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

528

uint8_t active_count = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

529

uint8_t i;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

53

uint8_t ready_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

54

uint8_t bstatus_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

540

uint8_t i;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

55

uint8_t max_cascade_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

552

struct mod_hdcp *hdcp, uint8_t index)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

554

uint8_t i;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

56

uint8_t max_devs_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

569

uint8_t i;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

57

uint8_t device_count_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

58

uint8_t ksvlist_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

59

uint8_t vp_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

60

uint8_t ksvlist_vp_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

62

uint8_t hdcp_capable_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

63

uint8_t binfo_read_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

64

uint8_t r0p_available_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

65

uint8_t link_integrity_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

66

uint8_t reauth_request_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

67

uint8_t stream_encryption_dp;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

71

uint8_t hdcp2version_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

72

uint8_t hdcp2_capable_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

73

uint8_t create_session;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

74

uint8_t ake_init_prepare;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

75

uint8_t ake_init_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

76

uint8_t rxstatus_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

77

uint8_t ake_cert_available;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

78

uint8_t ake_cert_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

79

uint8_t ake_cert_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

80

uint8_t stored_km_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

81

uint8_t no_stored_km_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

82

uint8_t h_prime_available;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

83

uint8_t h_prime_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

84

uint8_t pairing_available;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

85

uint8_t pairing_info_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

86

uint8_t h_prime_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

87

uint8_t lc_init_prepare;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

88

uint8_t lc_init_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

89

uint8_t l_prime_available_poll;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

90

uint8_t l_prime_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

91

uint8_t l_prime_combo_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

92

uint8_t l_prime_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

93

uint8_t eks_prepare;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

94

uint8_t eks_write;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

95

uint8_t enable_encryption;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

96

uint8_t reauth_request_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

97

uint8_t rx_id_list_read;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

98

uint8_t device_count_check;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

99

uint8_t rx_id_list_validation;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c

132

static inline uint8_t get_device_count(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c

31

uint8_t count = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c

327

uint8_t device_count;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c

460

uint8_t mod_hdcp_execute_and_set(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c

461

mod_hdcp_action func, uint8_t *flag,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

202

static inline uint8_t get_device_count(struct mod_hdcp *hdcp)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

230

static uint8_t process_rxstatus(struct mod_hdcp *hdcp,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

30

static inline uint16_t get_hdmi_rxstatus_msg_size(const uint8_t rxstatus[2])

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

37

uint8_t is_ready = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

73

uint8_t ret = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

154

uint8_t *buf,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

201

uint8_t *buf,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

203

uint8_t read_size)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

225

uint8_t *buf,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

292

(uint8_t *)&hdcp->auth.msg.hdcp1.bstatus,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

296

(uint8_t *)&hdcp->auth.msg.hdcp1.bstatus,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

304

(uint8_t *)&hdcp->auth.msg.hdcp1.r0p,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

320

(uint8_t *)&hdcp->auth.msg.hdcp1.ksvlist,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

361

(uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

428

(uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

679

uint8_t clear_cp_irq_bit = DP_CP_IRQ;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

723

uint8_t expected_rxstatus[2] = { sizeof(hdcp2->lc_l_prime) };

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

82

static const uint8_t hdcp_i2c_offsets[] = {

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

108

(uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

29

void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

30

uint8_t *buf, uint32_t buf_size)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

32

const uint8_t bytes_per_line = 16,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

62

(uint8_t *)&hdcp->auth.msg.hdcp1.bstatus,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

71

(uint8_t *)&hdcp->auth.msg.hdcp1.r0p,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

74

(uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

225

struct mod_hdcp *hdcp, uint8_t index)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

297

uint8_t i = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

49

struct mod_hdcp *hdcp, uint8_t index)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

552

uint8_t i = 0;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

85

struct mod_hdcp *hdcp, uint8_t index)

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c

921

uint8_t i;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

327

uint8_t display_handle;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

332

uint8_t an_primary[TA_HDCP__HDCP1_AN_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

333

uint8_t aksv_primary[TA_HDCP__HDCP1_KSV_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

334

uint8_t ainfo_primary;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

335

uint8_t an_secondary[TA_HDCP__HDCP1_AN_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

336

uint8_t aksv_secondary[TA_HDCP__HDCP1_KSV_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

337

uint8_t ainfo_secondary;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

346

uint8_t bksv_primary[TA_HDCP__HDCP1_KSV_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

347

uint8_t bksv_secondary[TA_HDCP__HDCP1_KSV_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

348

uint8_t bcaps;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

360

uint8_t ksv_list[TA_HDCP__HDCP1_KSV_LIST_MAX_ENTRIES][TA_HDCP__HDCP1_KSV_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

362

uint8_t pj_prime;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

363

uint8_t v_prime[TA_HDCP__HDCP1_V_PRIME_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

409

uint8_t receiver_message[TA_HDCP__HDCP2_RX_BUF_MAX_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

432

uint8_t transmitter_message[TA_HDCP__HDCP2_TX_BUF_MAX_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

467

uint8_t srm_buf[PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE];

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

471

uint8_t valid_signature;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h

478

uint8_t srm_buf[PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE];

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

109

uint8_t rev;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

110

uint8_t assr_enabled;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

111

uint8_t mst_enabled;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

112

uint8_t dp2_enabled;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

113

uint8_t usb4_enabled;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

117

uint8_t reserved;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

132

uint8_t dtm_v3_supported;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

142

uint8_t address;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

143

uint8_t offset;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

144

uint8_t *data;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

150

uint8_t *data;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

159

uint8_t offset,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

160

uint8_t *data,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

164

const uint8_t *data,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

168

uint8_t *data,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

172

const uint8_t *data,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

180

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

188

uint8_t poll_mask_msb

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

200

uint8_t disable : 2;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

201

uint8_t reserved : 6;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

205

uint8_t disable : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

206

uint8_t postpone_encryption : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

207

uint8_t min_auth_retries_wa : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

208

uint8_t reserved : 5;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

218

uint8_t disable : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

219

uint8_t force_type : 2;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

220

uint8_t force_no_stored_km : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

221

uint8_t increase_h_prime_timeout: 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

222

uint8_t use_fw_locality_check : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

223

uint8_t use_sw_locality_fallback: 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

224

uint8_t reserved : 1;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

228

uint8_t auth_delay;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

229

uint8_t retry_limit;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

236

uint8_t state_id;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

240

uint8_t attempt_count;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

241

uint8_t downstream_device_count;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

245

uint8_t attempt_count;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

246

uint8_t downstream_device_count;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

247

uint8_t hdcp1_device_downstream;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

248

uint8_t hdcp2_legacy_device_downstream;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

253

uint8_t error_count;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

275

uint8_t callback_needed;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

276

uint8_t callback_stop;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

277

uint8_t watchdog_timer_needed;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

278

uint8_t watchdog_timer_stop;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

281

uint8_t auth_complete;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

287

uint8_t index;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

288

uint8_t controller;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

289

uint8_t dig_fe;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

290

uint8_t stream_enc_idx;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

292

uint8_t vc_id;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

301

uint8_t dig_be;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

302

uint8_t ddc_line;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

303

uint8_t link_enc_idx;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

304

uint8_t phy_idx;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

305

uint8_t dio_output_id;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

306

uint8_t hdcp_supported_informational;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

326

uint8_t index;

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

346

uint8_t index, struct mod_hdcp_output *output);

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

350

uint8_t index,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

357

uint8_t index, struct mod_hdcp_display_query *query);

drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h

37

uint8_t mod_vmid_get_for_ptb(struct mod_vmid *mod_vmid, uint64_t ptb);

drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

511

uint8_t checksum = 0;

drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

565

info_packet->hb2 = (uint8_t) (length);

drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

574

info_packet->sb[0] = (uint8_t) (0x100 - checksum);

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

1043

uint8_t max_link_off_frame_count = 0;

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

128

uint8_t ac_level_percentage;

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

129

uint8_t dc_level_percentage;

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

130

uint8_t min_input_signal;

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

131

uint8_t max_input_signal;

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

132

uint8_t num_data_points;

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

159

uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

160

uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

161

uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

162

uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

163

uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

164

uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

165

uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

166

uint8_t deviation_gain; /* 0x7f U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

180

uint8_t psr_state; /* 0xf0 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

181

uint8_t dmcu_mcp_interface_version; /* 0xf1 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

182

uint8_t dmcu_abm_feature_version; /* 0xf2 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

183

uint8_t dmcu_psr_feature_version; /* 0xf3 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

185

uint8_t dmcu_state; /* 0xf6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

189

uint8_t dummy5; /* 0xfb */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

190

uint8_t dummy6; /* 0xfc */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

191

uint8_t dummy7; /* 0xfd */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

192

uint8_t dummy8; /* 0xfe */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

193

uint8_t dummy9; /* 0xff */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

201

uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

202

uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

203

uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

204

uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

205

uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

206

uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

207

uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

208

uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

209

uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

210

uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

212

uint8_t pad[19]; /* 0x6d U0.8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

226

uint8_t psr_state; /* 0xf0 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

227

uint8_t dmcu_mcp_interface_version; /* 0xf1 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

228

uint8_t dmcu_abm_feature_version; /* 0xf2 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

229

uint8_t dmcu_psr_feature_version; /* 0xf3 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

231

uint8_t dmcu_state; /* 0xf6 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

233

uint8_t dummy1; /* 0xf7 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

234

uint8_t dummy2; /* 0xf8 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

235

uint8_t dummy3; /* 0xf9 */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

236

uint8_t dummy4; /* 0xfa */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

237

uint8_t dummy5; /* 0xfb */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

238

uint8_t dummy6; /* 0xfc */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

239

uint8_t dummy7; /* 0xfd */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

240

uint8_t dummy8; /* 0xfe */

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

241

uint8_t dummy9; /* 0xff */

drivers/gpu/drm/amd/display/modules/vmid/vmid.c

95

uint8_t mod_vmid_get_for_ptb(struct mod_vmid *mod_vmid, uint64_t ptb)

drivers/gpu/drm/amd/include/amd_cper.h

124

uint8_t reserved[12]; /* Reserved */

drivers/gpu/drm/amd/include/amd_cper.h

130

uint8_t revision_minor; /* CPER_SEC_MINOR_REV_1 */

drivers/gpu/drm/amd/include/amd_cper.h

131

uint8_t revision_major; /* CPER_SEC_MAJOR_REV_22 */

drivers/gpu/drm/amd/include/amd_cper.h

134

uint8_t fru_id : 1;

drivers/gpu/drm/amd/include/amd_cper.h

135

uint8_t fru_text : 1;

drivers/gpu/drm/amd/include/amd_cper.h

136

uint8_t reserved : 6;

drivers/gpu/drm/amd/include/amd_cper.h

138

uint8_t valid_mask;

drivers/gpu/drm/amd/include/amd_cper.h

140

uint8_t reserved;

drivers/gpu/drm/amd/include/amd_cper.h

90

uint8_t seconds;

drivers/gpu/drm/amd/include/amd_cper.h

91

uint8_t minutes;

drivers/gpu/drm/amd/include/amd_cper.h

92

uint8_t hours;

drivers/gpu/drm/amd/include/amd_cper.h

93

uint8_t flag;

drivers/gpu/drm/amd/include/amd_cper.h

94

uint8_t day;

drivers/gpu/drm/amd/include/amd_cper.h

95

uint8_t month;

drivers/gpu/drm/amd/include/amd_cper.h

96

uint8_t year;

drivers/gpu/drm/amd/include/amd_cper.h

97

uint8_t century;

drivers/gpu/drm/amd/include/amdgpu_reg_state.h

48

uint8_t format_revision;

drivers/gpu/drm/amd/include/amdgpu_reg_state.h

49

uint8_t content_revision;

drivers/gpu/drm/amd/include/amdgpu_reg_state.h

50

uint8_t state_type;

drivers/gpu/drm/amd/include/amdgpu_reg_state.h

51

uint8_t num_instances;

drivers/gpu/drm/amd/include/atom-bits.h

28

static inline uint8_t get_u8(void *bios, int ptr)

drivers/gpu/drm/amd/include/atom-types.h

32

typedef uint8_t UCHAR;

drivers/gpu/drm/amd/include/atomfirmware.h

1019

uint8_t priority_id;

drivers/gpu/drm/amd/include/atomfirmware.h

1020

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1040

uint8_t number_of_path;

drivers/gpu/drm/amd/include/atomfirmware.h

1041

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1048

uint8_t number_of_path;

drivers/gpu/drm/amd/include/atomfirmware.h

1049

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1073

uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1074

uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1075

uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1076

uint8_t ss_reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1077

uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1078

uint8_t reserved1[3];

drivers/gpu/drm/amd/include/atomfirmware.h

1081

uint8_t dceip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1082

uint8_t dceip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1083

uint8_t max_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1084

uint8_t max_vbios_active_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1085

uint8_t max_ppll_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1086

uint8_t max_disp_phy_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1087

uint8_t max_aux_pairs;

drivers/gpu/drm/amd/include/atomfirmware.h

1088

uint8_t remotedisplayconfig;

drivers/gpu/drm/amd/include/atomfirmware.h

1089

uint8_t reserved3[8];

drivers/gpu/drm/amd/include/atomfirmware.h

1105

uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1106

uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1107

uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1108

uint8_t ss_reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1109

uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1110

uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1111

uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable

drivers/gpu/drm/amd/include/atomfirmware.h

1112

uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable

drivers/gpu/drm/amd/include/atomfirmware.h

1115

uint8_t dcnip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1116

uint8_t dcnip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1117

uint8_t max_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1118

uint8_t max_vbios_active_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1119

uint8_t max_ppll_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1120

uint8_t max_disp_phy_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1121

uint8_t max_aux_pairs;

drivers/gpu/drm/amd/include/atomfirmware.h

1122

uint8_t remotedisplayconfig;

drivers/gpu/drm/amd/include/atomfirmware.h

1123

uint8_t reserved3[8];

drivers/gpu/drm/amd/include/atomfirmware.h

1139

uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1140

uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1141

uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1142

uint8_t ss_reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1143

uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1144

uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1145

uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable

drivers/gpu/drm/amd/include/atomfirmware.h

1146

uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable

drivers/gpu/drm/amd/include/atomfirmware.h

1149

uint8_t dcnip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1150

uint8_t dcnip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1151

uint8_t max_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1152

uint8_t max_vbios_active_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1153

uint8_t max_ppll_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1154

uint8_t max_disp_phy_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1155

uint8_t max_aux_pairs;

drivers/gpu/drm/amd/include/atomfirmware.h

1156

uint8_t remotedisplayconfig;

drivers/gpu/drm/amd/include/atomfirmware.h

1157

uint8_t reserved3[8];

drivers/gpu/drm/amd/include/atomfirmware.h

1172

uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1173

uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1174

uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1175

uint8_t ss_reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1176

uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1177

uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available

drivers/gpu/drm/amd/include/atomfirmware.h

1178

uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable

drivers/gpu/drm/amd/include/atomfirmware.h

1179

uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable

drivers/gpu/drm/amd/include/atomfirmware.h

1182

uint8_t dcnip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1183

uint8_t dcnip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1184

uint8_t max_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1185

uint8_t max_vbios_active_disp_pipum;

drivers/gpu/drm/amd/include/atomfirmware.h

1186

uint8_t max_ppll_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1187

uint8_t max_disp_phy_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1188

uint8_t max_aux_pairs;

drivers/gpu/drm/amd/include/atomfirmware.h

1189

uint8_t remotedisplayconfig;

drivers/gpu/drm/amd/include/atomfirmware.h

1239

uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1240

uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1241

uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1242

uint8_t ss_reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1244

uint8_t dfp_hardcode_mode_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1246

uint8_t dfp_hardcode_refreshrate;

drivers/gpu/drm/amd/include/atomfirmware.h

1248

uint8_t vga_hardcode_mode_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1250

uint8_t vga_hardcode_refreshrate;

drivers/gpu/drm/amd/include/atomfirmware.h

1253

uint8_t dcnip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1254

uint8_t dcnip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1255

uint8_t max_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1256

uint8_t max_vbios_active_disp_pipe_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1257

uint8_t max_ppll_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1258

uint8_t max_disp_phy_num;

drivers/gpu/drm/amd/include/atomfirmware.h

1259

uint8_t max_aux_pairs;

drivers/gpu/drm/amd/include/atomfirmware.h

1260

uint8_t remotedisplayconfig;

drivers/gpu/drm/amd/include/atomfirmware.h

1293

uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT

drivers/gpu/drm/amd/include/atomfirmware.h

1294

uint8_t hpdlut_index; //An index into external HPD pin LUT

drivers/gpu/drm/amd/include/atomfirmware.h

1296

uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping

drivers/gpu/drm/amd/include/atomfirmware.h

1297

uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted

drivers/gpu/drm/amd/include/atomfirmware.h

1320

uint8_t guid[16]; // a GUID is a 16 byte long string

drivers/gpu/drm/amd/include/atomfirmware.h

1322

uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.

drivers/gpu/drm/amd/include/atomfirmware.h

1323

uint8_t stereopinid; // use for eDP panel

drivers/gpu/drm/amd/include/atomfirmware.h

1324

uint8_t remotedisplayconfig;

drivers/gpu/drm/amd/include/atomfirmware.h

1325

uint8_t edptolvdsrxid;

drivers/gpu/drm/amd/include/atomfirmware.h

1326

uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value

drivers/gpu/drm/amd/include/atomfirmware.h

1327

uint8_t reserved[3]; // for potential expansion

drivers/gpu/drm/amd/include/atomfirmware.h

1338

uint8_t profile_id; // SENSOR_PROFILES

drivers/gpu/drm/amd/include/atomfirmware.h

1349

uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user

drivers/gpu/drm/amd/include/atomfirmware.h

1350

uint8_t module_name[8];

drivers/gpu/drm/amd/include/atomfirmware.h

1356

uint8_t flashlight_id; // 0: Rear, 1: Front

drivers/gpu/drm/amd/include/atomfirmware.h

1357

uint8_t name[8];

drivers/gpu/drm/amd/include/atomfirmware.h

1373

uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode

drivers/gpu/drm/amd/include/atomfirmware.h

1374

uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf

drivers/gpu/drm/amd/include/atomfirmware.h

1376

uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4

drivers/gpu/drm/amd/include/atomfirmware.h

1377

uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset

drivers/gpu/drm/amd/include/atomfirmware.h

1378

uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms

drivers/gpu/drm/amd/include/atomfirmware.h

1379

uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL

drivers/gpu/drm/amd/include/atomfirmware.h

1383

uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def

drivers/gpu/drm/amd/include/atomfirmware.h

1385

uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4

drivers/gpu/drm/amd/include/atomfirmware.h

1386

uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset

drivers/gpu/drm/amd/include/atomfirmware.h

1390

uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf

drivers/gpu/drm/amd/include/atomfirmware.h

1391

uint8_t version;

drivers/gpu/drm/amd/include/atomfirmware.h

1406

uint8_t sym_clk;

drivers/gpu/drm/amd/include/atomfirmware.h

1407

uint8_t dig_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

1408

uint8_t phy_sel;

drivers/gpu/drm/amd/include/atomfirmware.h

1410

uint8_t common_seldeemph60__deemph_6db_4_val;

drivers/gpu/drm/amd/include/atomfirmware.h

1411

uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;

drivers/gpu/drm/amd/include/atomfirmware.h

1412

uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;

drivers/gpu/drm/amd/include/atomfirmware.h

1413

uint8_t margin_deemph_lane0__deemph_sel_val;

drivers/gpu/drm/amd/include/atomfirmware.h

1419

uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode

drivers/gpu/drm/amd/include/atomfirmware.h

1420

uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf

drivers/gpu/drm/amd/include/atomfirmware.h

1421

uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)

drivers/gpu/drm/amd/include/atomfirmware.h

1422

uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)

drivers/gpu/drm/amd/include/atomfirmware.h

1423

uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)

drivers/gpu/drm/amd/include/atomfirmware.h

1424

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1425

uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL

drivers/gpu/drm/amd/include/atomfirmware.h

1426

uint8_t reserved2;

drivers/gpu/drm/amd/include/atomfirmware.h

1430

uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def

drivers/gpu/drm/amd/include/atomfirmware.h

1431

uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)

drivers/gpu/drm/amd/include/atomfirmware.h

1432

uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)

drivers/gpu/drm/amd/include/atomfirmware.h

1433

uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)

drivers/gpu/drm/amd/include/atomfirmware.h

1434

uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL

drivers/gpu/drm/amd/include/atomfirmware.h

1438

uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf

drivers/gpu/drm/amd/include/atomfirmware.h

1439

uint8_t version;

drivers/gpu/drm/amd/include/atomfirmware.h

1446

uint8_t ucI2cRegIndex;

drivers/gpu/drm/amd/include/atomfirmware.h

1447

uint8_t ucI2cRegVal;

drivers/gpu/drm/amd/include/atomfirmware.h

1451

uint8_t HdmiSlvAddr;

drivers/gpu/drm/amd/include/atomfirmware.h

1452

uint8_t HdmiRegNum;

drivers/gpu/drm/amd/include/atomfirmware.h

1453

uint8_t Hdmi6GRegNum;

drivers/gpu/drm/amd/include/atomfirmware.h

1476

uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.

drivers/gpu/drm/amd/include/atomfirmware.h

1477

uint8_t umachannelnumber; // number of memory channels

drivers/gpu/drm/amd/include/atomfirmware.h

1478

uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */

drivers/gpu/drm/amd/include/atomfirmware.h

1479

uint8_t pwr_on_de_to_vary_bl;

drivers/gpu/drm/amd/include/atomfirmware.h

1480

uint8_t pwr_down_vary_bloff_to_de;

drivers/gpu/drm/amd/include/atomfirmware.h

1481

uint8_t pwr_down_de_to_digoff;

drivers/gpu/drm/amd/include/atomfirmware.h

1482

uint8_t pwr_off_delay;

drivers/gpu/drm/amd/include/atomfirmware.h

1483

uint8_t pwr_on_vary_bl_to_blon;

drivers/gpu/drm/amd/include/atomfirmware.h

1484

uint8_t pwr_down_bloff_to_vary_bloff;

drivers/gpu/drm/amd/include/atomfirmware.h

1485

uint8_t min_allowed_bl_level;

drivers/gpu/drm/amd/include/atomfirmware.h

1486

uint8_t htc_hyst_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1487

uint8_t htc_tmp_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1488

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1489

uint8_t reserved2;

drivers/gpu/drm/amd/include/atomfirmware.h

1525

uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.

drivers/gpu/drm/amd/include/atomfirmware.h

1526

uint8_t umachannelnumber; // number of memory channels

drivers/gpu/drm/amd/include/atomfirmware.h

1527

uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //

drivers/gpu/drm/amd/include/atomfirmware.h

1528

uint8_t pwr_on_de_to_vary_bl;

drivers/gpu/drm/amd/include/atomfirmware.h

1529

uint8_t pwr_down_vary_bloff_to_de;

drivers/gpu/drm/amd/include/atomfirmware.h

1530

uint8_t pwr_down_de_to_digoff;

drivers/gpu/drm/amd/include/atomfirmware.h

1531

uint8_t pwr_off_delay;

drivers/gpu/drm/amd/include/atomfirmware.h

1532

uint8_t pwr_on_vary_bl_to_blon;

drivers/gpu/drm/amd/include/atomfirmware.h

1533

uint8_t pwr_down_bloff_to_vary_bloff;

drivers/gpu/drm/amd/include/atomfirmware.h

1534

uint8_t min_allowed_bl_level;

drivers/gpu/drm/amd/include/atomfirmware.h

1535

uint8_t htc_hyst_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1536

uint8_t htc_tmp_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1537

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1538

uint8_t reserved2;

drivers/gpu/drm/amd/include/atomfirmware.h

1564

uint8_t edp_pwr_on_off_delay;

drivers/gpu/drm/amd/include/atomfirmware.h

1565

uint8_t edp_pwr_on_vary_bl_to_blon;

drivers/gpu/drm/amd/include/atomfirmware.h

1566

uint8_t edp_pwr_down_bloff_to_vary_bloff;

drivers/gpu/drm/amd/include/atomfirmware.h

1567

uint8_t edp_panel_bpc;

drivers/gpu/drm/amd/include/atomfirmware.h

1568

uint8_t edp_bootup_bl_level;

drivers/gpu/drm/amd/include/atomfirmware.h

1569

uint8_t reserved3[3];

drivers/gpu/drm/amd/include/atomfirmware.h

1583

uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.

drivers/gpu/drm/amd/include/atomfirmware.h

1584

uint8_t umachannelnumber; // number of memory channels

drivers/gpu/drm/amd/include/atomfirmware.h

1585

uint8_t htc_hyst_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1586

uint8_t htc_tmp_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1587

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1588

uint8_t reserved2;

drivers/gpu/drm/amd/include/atomfirmware.h

1614

uint8_t display_signal_type;

drivers/gpu/drm/amd/include/atomfirmware.h

1615

uint8_t phy_sel;

drivers/gpu/drm/amd/include/atomfirmware.h

1616

uint8_t preset_level;

drivers/gpu/drm/amd/include/atomfirmware.h

1617

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1620

uint8_t tx_vboost_level;

drivers/gpu/drm/amd/include/atomfirmware.h

1621

uint8_t tx_vreg_v2i;

drivers/gpu/drm/amd/include/atomfirmware.h

1622

uint8_t tx_vregdrv_byp;

drivers/gpu/drm/amd/include/atomfirmware.h

1623

uint8_t tx_term_cntl;

drivers/gpu/drm/amd/include/atomfirmware.h

1624

uint8_t tx_peak_level;

drivers/gpu/drm/amd/include/atomfirmware.h

1625

uint8_t tx_slew_en;

drivers/gpu/drm/amd/include/atomfirmware.h

1626

uint8_t tx_eq_pre;

drivers/gpu/drm/amd/include/atomfirmware.h

1627

uint8_t tx_eq_main;

drivers/gpu/drm/amd/include/atomfirmware.h

1628

uint8_t tx_eq_post;

drivers/gpu/drm/amd/include/atomfirmware.h

1629

uint8_t tx_en_inv_pre;

drivers/gpu/drm/amd/include/atomfirmware.h

1630

uint8_t tx_en_inv_post;

drivers/gpu/drm/amd/include/atomfirmware.h

1631

uint8_t reserved3;

drivers/gpu/drm/amd/include/atomfirmware.h

1652

uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.

drivers/gpu/drm/amd/include/atomfirmware.h

1653

uint8_t umachannelnumber; // number of memory channels

drivers/gpu/drm/amd/include/atomfirmware.h

1654

uint8_t htc_hyst_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1655

uint8_t htc_tmp_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1656

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1657

uint8_t reserved2;

drivers/gpu/drm/amd/include/atomfirmware.h

1668

uint8_t memoryCarvedGb; //memory carved out with setting

drivers/gpu/drm/amd/include/atomfirmware.h

1669

uint8_t memoryRemainingGb; //memory remaining on system

drivers/gpu/drm/amd/include/atomfirmware.h

1672

uint8_t Auto : 1;

drivers/gpu/drm/amd/include/atomfirmware.h

1673

uint8_t Custom : 1;

drivers/gpu/drm/amd/include/atomfirmware.h

1674

uint8_t Reserved : 6;

drivers/gpu/drm/amd/include/atomfirmware.h

1676

uint8_t all8;

drivers/gpu/drm/amd/include/atomfirmware.h

1689

uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.

drivers/gpu/drm/amd/include/atomfirmware.h

1690

uint8_t umachannelnumber; // number of memory channels

drivers/gpu/drm/amd/include/atomfirmware.h

1691

uint8_t htc_hyst_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1692

uint8_t htc_tmp_limit;

drivers/gpu/drm/amd/include/atomfirmware.h

1693

uint8_t reserved1; // dp_ss_control

drivers/gpu/drm/amd/include/atomfirmware.h

1694

uint8_t gpu_package_id;

drivers/gpu/drm/amd/include/atomfirmware.h

1699

uint8_t UMACarveoutVersion;

drivers/gpu/drm/amd/include/atomfirmware.h

1700

uint8_t UMACarveoutIndexMax;

drivers/gpu/drm/amd/include/atomfirmware.h

1701

uint8_t UMACarveoutTypeDefault;

drivers/gpu/drm/amd/include/atomfirmware.h

1702

uint8_t UMACarveoutIndexDefault;

drivers/gpu/drm/amd/include/atomfirmware.h

1703

uint8_t UMACarveoutType; //Auto or Custom

drivers/gpu/drm/amd/include/atomfirmware.h

1704

uint8_t UMACarveoutIndex;

drivers/gpu/drm/amd/include/atomfirmware.h

1706

uint8_t reserved3[110];

drivers/gpu/drm/amd/include/atomfirmware.h

1792

uint8_t gfxip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1793

uint8_t gfxip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1794

uint8_t max_shader_engines;

drivers/gpu/drm/amd/include/atomfirmware.h

1795

uint8_t max_tile_pipes;

drivers/gpu/drm/amd/include/atomfirmware.h

1796

uint8_t max_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1797

uint8_t max_sh_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1798

uint8_t max_backends_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1799

uint8_t max_texture_channel_caches;

drivers/gpu/drm/amd/include/atomfirmware.h

1812

uint8_t gfxip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1813

uint8_t gfxip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1814

uint8_t max_shader_engines;

drivers/gpu/drm/amd/include/atomfirmware.h

1815

uint8_t max_tile_pipes;

drivers/gpu/drm/amd/include/atomfirmware.h

1816

uint8_t max_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1817

uint8_t max_sh_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1818

uint8_t max_backends_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1819

uint8_t max_texture_channel_caches;

drivers/gpu/drm/amd/include/atomfirmware.h

1828

uint8_t active_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1829

uint8_t active_rb_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1837

uint8_t gfxip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1838

uint8_t gfxip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1839

uint8_t max_shader_engines;

drivers/gpu/drm/amd/include/atomfirmware.h

1840

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1841

uint8_t max_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1842

uint8_t max_sh_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1843

uint8_t max_backends_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1844

uint8_t max_texture_channel_caches;

drivers/gpu/drm/amd/include/atomfirmware.h

1853

uint8_t active_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1854

uint8_t active_rb_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1862

uint8_t gc_num_max_gs_thds;

drivers/gpu/drm/amd/include/atomfirmware.h

1863

uint8_t gc_gs_table_depth;

drivers/gpu/drm/amd/include/atomfirmware.h

1864

uint8_t gc_double_offchip_lds_buffer;

drivers/gpu/drm/amd/include/atomfirmware.h

1865

uint8_t gc_max_scratch_slots_per_cu;

drivers/gpu/drm/amd/include/atomfirmware.h

1872

uint8_t gfxip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1873

uint8_t gfxip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1874

uint8_t max_shader_engines;

drivers/gpu/drm/amd/include/atomfirmware.h

1875

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

1876

uint8_t max_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1877

uint8_t max_sh_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1878

uint8_t max_backends_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1879

uint8_t max_texture_channel_caches;

drivers/gpu/drm/amd/include/atomfirmware.h

1888

uint8_t active_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1889

uint8_t active_rb_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1897

uint8_t gc_num_max_gs_thds;

drivers/gpu/drm/amd/include/atomfirmware.h

1898

uint8_t gc_gs_table_depth;

drivers/gpu/drm/amd/include/atomfirmware.h

1899

uint8_t gc_double_offchip_lds_buffer;

drivers/gpu/drm/amd/include/atomfirmware.h

1900

uint8_t gc_max_scratch_slots_per_cu;

drivers/gpu/drm/amd/include/atomfirmware.h

1903

uint8_t cut_cu;

drivers/gpu/drm/amd/include/atomfirmware.h

1904

uint8_t active_cu_total;

drivers/gpu/drm/amd/include/atomfirmware.h

1905

uint8_t cu_reserved[2];

drivers/gpu/drm/amd/include/atomfirmware.h

1907

uint8_t inactive_cu_per_se[8];

drivers/gpu/drm/amd/include/atomfirmware.h

1913

uint8_t gfxip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1914

uint8_t gfxip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1915

uint8_t max_shader_engines;

drivers/gpu/drm/amd/include/atomfirmware.h

1916

uint8_t max_tile_pipes;

drivers/gpu/drm/amd/include/atomfirmware.h

1917

uint8_t max_cu_per_sh;

drivers/gpu/drm/amd/include/atomfirmware.h

1918

uint8_t max_sh_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1919

uint8_t max_backends_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1920

uint8_t max_texture_channel_caches;

drivers/gpu/drm/amd/include/atomfirmware.h

1929

uint8_t active_wgp_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1930

uint8_t active_rb_per_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1931

uint8_t active_se;

drivers/gpu/drm/amd/include/atomfirmware.h

1932

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

1937

uint8_t inactive_wgp[16];

drivers/gpu/drm/amd/include/atomfirmware.h

1938

uint8_t inactive_rb[16];

drivers/gpu/drm/amd/include/atomfirmware.h

1952

uint8_t smuip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1953

uint8_t smuip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1954

uint8_t smu_rsd1;

drivers/gpu/drm/amd/include/atomfirmware.h

1955

uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode

drivers/gpu/drm/amd/include/atomfirmware.h

1961

uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1962

uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

1963

uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1964

uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

1965

uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1966

uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

1967

uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1968

uint8_t fw_ctf_polarity; // GPIO polarity for CTF

drivers/gpu/drm/amd/include/atomfirmware.h

1973

uint8_t smuip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1974

uint8_t smuip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

1975

uint8_t smu_rsd1;

drivers/gpu/drm/amd/include/atomfirmware.h

1976

uint8_t gpuclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

1982

uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1983

uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

1984

uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1985

uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

1986

uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1987

uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

1988

uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1989

uint8_t fw_ctf_polarity; // GPIO polarity for CTF

drivers/gpu/drm/amd/include/atomfirmware.h

1990

uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

1991

uint8_t pcc_gpio_polarity; // GPIO polarity for CTF

drivers/gpu/drm/amd/include/atomfirmware.h

2006

uint8_t smuip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

2007

uint8_t smuip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

2008

uint8_t waflclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

2009

uint8_t gpuclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

2015

uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

2016

uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2017

uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

2018

uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2019

uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

2020

uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2021

uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

2022

uint8_t fw_ctf_polarity; // GPIO polarity for CTF

drivers/gpu/drm/amd/include/atomfirmware.h

2023

uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

2024

uint8_t pcc_gpio_polarity; // GPIO polarity for CTF

drivers/gpu/drm/amd/include/atomfirmware.h

2047

uint8_t smuip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

2048

uint8_t smuip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

2049

uint8_t waflclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

2050

uint8_t gpuclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

2058

uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid

drivers/gpu/drm/amd/include/atomfirmware.h

2059

uint8_t pcc_gpio_polarity; // GPIO polarity for CTF

drivers/gpu/drm/amd/include/atomfirmware.h

2104

uint8_t smuip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

2105

uint8_t smuip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

2106

uint8_t waflclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

2107

uint8_t gpuclk_ss_mode;

drivers/gpu/drm/amd/include/atomfirmware.h

2115

uint8_t pcc_gpio_bit;

drivers/gpu/drm/amd/include/atomfirmware.h

2116

uint8_t pcc_gpio_polarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2170

uint8_t pcc_gpio_bit;

drivers/gpu/drm/amd/include/atomfirmware.h

2171

uint8_t pcc_gpio_polarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2233

uint8_t liquid1_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2234

uint8_t liquid2_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2235

uint8_t vr_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2236

uint8_t plx_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2238

uint8_t liquid_i2c_linescl;

drivers/gpu/drm/amd/include/atomfirmware.h

2239

uint8_t liquid_i2c_linesda;

drivers/gpu/drm/amd/include/atomfirmware.h

2240

uint8_t vr_i2c_linescl;

drivers/gpu/drm/amd/include/atomfirmware.h

2241

uint8_t vr_i2c_linesda;

drivers/gpu/drm/amd/include/atomfirmware.h

2243

uint8_t plx_i2c_linescl;

drivers/gpu/drm/amd/include/atomfirmware.h

2244

uint8_t plx_i2c_linesda;

drivers/gpu/drm/amd/include/atomfirmware.h

2245

uint8_t vrsensorpresent;

drivers/gpu/drm/amd/include/atomfirmware.h

2246

uint8_t liquidsensorpresent;

drivers/gpu/drm/amd/include/atomfirmware.h

2251

uint8_t vddgfxvrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2252

uint8_t vddsocvrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2253

uint8_t vddmem0vrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2254

uint8_t vddmem1vrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2256

uint8_t gfxulvphasesheddingmask;

drivers/gpu/drm/amd/include/atomfirmware.h

2257

uint8_t soculvphasesheddingmask;

drivers/gpu/drm/amd/include/atomfirmware.h

2258

uint8_t padding8_v[2];

drivers/gpu/drm/amd/include/atomfirmware.h

2261

uint8_t gfxoffset;

drivers/gpu/drm/amd/include/atomfirmware.h

2262

uint8_t padding_telemetrygfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2265

uint8_t socoffset;

drivers/gpu/drm/amd/include/atomfirmware.h

2266

uint8_t padding_telemetrysoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2269

uint8_t mem0offset;

drivers/gpu/drm/amd/include/atomfirmware.h

2270

uint8_t padding_telemetrymem0;

drivers/gpu/drm/amd/include/atomfirmware.h

2273

uint8_t mem1offset;

drivers/gpu/drm/amd/include/atomfirmware.h

2274

uint8_t padding_telemetrymem1;

drivers/gpu/drm/amd/include/atomfirmware.h

2276

uint8_t acdcgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2277

uint8_t acdcpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2278

uint8_t vr0hotgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2279

uint8_t vr0hotpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2281

uint8_t vr1hotgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2282

uint8_t vr1hotpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2283

uint8_t padding1;

drivers/gpu/drm/amd/include/atomfirmware.h

2284

uint8_t padding2;

drivers/gpu/drm/amd/include/atomfirmware.h

2286

uint8_t ledpin0;

drivers/gpu/drm/amd/include/atomfirmware.h

2287

uint8_t ledpin1;

drivers/gpu/drm/amd/include/atomfirmware.h

2288

uint8_t ledpin2;

drivers/gpu/drm/amd/include/atomfirmware.h

2289

uint8_t padding8_4;

drivers/gpu/drm/amd/include/atomfirmware.h

2291

uint8_t pllgfxclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2292

uint8_t pllgfxclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2295

uint8_t uclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2296

uint8_t uclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2299

uint8_t socclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2300

uint8_t socclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2303

uint8_t acggfxclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2304

uint8_t acggfxclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2307

uint8_t Vr2_I2C_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2308

uint8_t padding_vr2[3];

drivers/gpu/drm/amd/include/atomfirmware.h

2321

uint8_t liquid1_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2322

uint8_t liquid2_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2323

uint8_t vr_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2324

uint8_t plx_i2c_address;

drivers/gpu/drm/amd/include/atomfirmware.h

2326

uint8_t liquid_i2c_linescl;

drivers/gpu/drm/amd/include/atomfirmware.h

2327

uint8_t liquid_i2c_linesda;

drivers/gpu/drm/amd/include/atomfirmware.h

2328

uint8_t vr_i2c_linescl;

drivers/gpu/drm/amd/include/atomfirmware.h

2329

uint8_t vr_i2c_linesda;

drivers/gpu/drm/amd/include/atomfirmware.h

2331

uint8_t plx_i2c_linescl;

drivers/gpu/drm/amd/include/atomfirmware.h

2332

uint8_t plx_i2c_linesda;

drivers/gpu/drm/amd/include/atomfirmware.h

2333

uint8_t vrsensorpresent;

drivers/gpu/drm/amd/include/atomfirmware.h

2334

uint8_t liquidsensorpresent;

drivers/gpu/drm/amd/include/atomfirmware.h

2339

uint8_t vddgfxvrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2340

uint8_t vddsocvrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2341

uint8_t vddmem0vrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2342

uint8_t vddmem1vrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2344

uint8_t gfxulvphasesheddingmask;

drivers/gpu/drm/amd/include/atomfirmware.h

2345

uint8_t soculvphasesheddingmask;

drivers/gpu/drm/amd/include/atomfirmware.h

2346

uint8_t externalsensorpresent;

drivers/gpu/drm/amd/include/atomfirmware.h

2347

uint8_t padding8_v;

drivers/gpu/drm/amd/include/atomfirmware.h

2350

uint8_t gfxoffset;

drivers/gpu/drm/amd/include/atomfirmware.h

2351

uint8_t padding_telemetrygfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2354

uint8_t socoffset;

drivers/gpu/drm/amd/include/atomfirmware.h

2355

uint8_t padding_telemetrysoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2358

uint8_t mem0offset;

drivers/gpu/drm/amd/include/atomfirmware.h

2359

uint8_t padding_telemetrymem0;

drivers/gpu/drm/amd/include/atomfirmware.h

236

uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible

drivers/gpu/drm/amd/include/atomfirmware.h

2362

uint8_t mem1offset;

drivers/gpu/drm/amd/include/atomfirmware.h

2363

uint8_t padding_telemetrymem1;

drivers/gpu/drm/amd/include/atomfirmware.h

2365

uint8_t acdcgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2366

uint8_t acdcpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2367

uint8_t vr0hotgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2368

uint8_t vr0hotpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

237

uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change

drivers/gpu/drm/amd/include/atomfirmware.h

2370

uint8_t vr1hotgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2371

uint8_t vr1hotpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2372

uint8_t padding1;

drivers/gpu/drm/amd/include/atomfirmware.h

2373

uint8_t padding2;

drivers/gpu/drm/amd/include/atomfirmware.h

2375

uint8_t ledpin0;

drivers/gpu/drm/amd/include/atomfirmware.h

2376

uint8_t ledpin1;

drivers/gpu/drm/amd/include/atomfirmware.h

2377

uint8_t ledpin2;

drivers/gpu/drm/amd/include/atomfirmware.h

2378

uint8_t padding8_4;

drivers/gpu/drm/amd/include/atomfirmware.h

2380

uint8_t pllgfxclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2381

uint8_t pllgfxclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2384

uint8_t uclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2385

uint8_t uclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2388

uint8_t fclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2389

uint8_t fclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2392

uint8_t fllgfxclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2393

uint8_t fllgfxclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2417

uint8_t vddgfxvrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2418

uint8_t vddsocvrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2419

uint8_t vddmem0vrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2420

uint8_t vddmem1vrmapping;

drivers/gpu/drm/amd/include/atomfirmware.h

2422

uint8_t gfxulvphasesheddingmask;

drivers/gpu/drm/amd/include/atomfirmware.h

2423

uint8_t soculvphasesheddingmask;

drivers/gpu/drm/amd/include/atomfirmware.h

2424

uint8_t externalsensorpresent;

drivers/gpu/drm/amd/include/atomfirmware.h

2425

uint8_t padding8_v;

drivers/gpu/drm/amd/include/atomfirmware.h

2428

uint8_t gfxoffset;

drivers/gpu/drm/amd/include/atomfirmware.h

2429

uint8_t padding_telemetrygfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2432

uint8_t socoffset;

drivers/gpu/drm/amd/include/atomfirmware.h

2433

uint8_t padding_telemetrysoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2436

uint8_t mem0offset;

drivers/gpu/drm/amd/include/atomfirmware.h

2437

uint8_t padding_telemetrymem0;

drivers/gpu/drm/amd/include/atomfirmware.h

2440

uint8_t mem1offset;

drivers/gpu/drm/amd/include/atomfirmware.h

2441

uint8_t padding_telemetrymem1;

drivers/gpu/drm/amd/include/atomfirmware.h

2444

uint8_t acdcgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2445

uint8_t acdcpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2446

uint8_t vr0hotgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2447

uint8_t vr0hotpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2449

uint8_t vr1hotgpio;

drivers/gpu/drm/amd/include/atomfirmware.h

2450

uint8_t vr1hotpolarity;

drivers/gpu/drm/amd/include/atomfirmware.h

2451

uint8_t padding1;

drivers/gpu/drm/amd/include/atomfirmware.h

2452

uint8_t padding2;

drivers/gpu/drm/amd/include/atomfirmware.h

2455

uint8_t ledpin0;

drivers/gpu/drm/amd/include/atomfirmware.h

2456

uint8_t ledpin1;

drivers/gpu/drm/amd/include/atomfirmware.h

2457

uint8_t ledpin2;

drivers/gpu/drm/amd/include/atomfirmware.h

2458

uint8_t padding8_4;

drivers/gpu/drm/amd/include/atomfirmware.h

246

uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,

drivers/gpu/drm/amd/include/atomfirmware.h

2461

uint8_t pllgfxclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2462

uint8_t pllgfxclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2466

uint8_t uclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2467

uint8_t uclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2471

uint8_t fclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2472

uint8_t fclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2476

uint8_t fllgfxclkspreadenabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2477

uint8_t fllgfxclkspreadpercent;

drivers/gpu/drm/amd/include/atomfirmware.h

2523

uint8_t Enabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2524

uint8_t Speed;

drivers/gpu/drm/amd/include/atomfirmware.h

2525

uint8_t Padding[2];

drivers/gpu/drm/amd/include/atomfirmware.h

2527

uint8_t ControllerPort;

drivers/gpu/drm/amd/include/atomfirmware.h

2528

uint8_t ControllerName;

drivers/gpu/drm/amd/include/atomfirmware.h

2529

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/include/atomfirmware.h

2530

uint8_t I2cProtocol;

drivers/gpu/drm/amd/include/atomfirmware.h

2544

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2545

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2546

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2547

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2549

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2550

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2551

uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)

drivers/gpu/drm/amd/include/atomfirmware.h

2552

uint8_t Padding8_V;

drivers/gpu/drm/amd/include/atomfirmware.h

2556

uint8_t GfxOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2557

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2559

uint8_t SocOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2560

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2563

uint8_t Mem0Offset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2564

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/include/atomfirmware.h

2567

uint8_t Mem1Offset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2568

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/include/atomfirmware.h

2571

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2572

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2573

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2574

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2576

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2577

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2578

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/include/atomfirmware.h

2579

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/include/atomfirmware.h

2582

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/include/atomfirmware.h

2583

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/include/atomfirmware.h

2584

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/include/atomfirmware.h

2585

uint8_t padding8_4;

drivers/gpu/drm/amd/include/atomfirmware.h

2588

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2589

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2593

uint8_t DfllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2594

uint8_t DfllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2598

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2599

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2603

uint8_t SoclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2604

uint8_t SocclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2627

uint8_t vddgfxvrmapping; // use vr_mapping* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2628

uint8_t vddsocvrmapping; // use vr_mapping* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2629

uint8_t vddmemvrmapping; // use vr_mapping* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2630

uint8_t boardvrmapping; // use vr_mapping* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2632

uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode

drivers/gpu/drm/amd/include/atomfirmware.h

2633

uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)

drivers/gpu/drm/amd/include/atomfirmware.h

2634

uint8_t padding8_v[2];

drivers/gpu/drm/amd/include/atomfirmware.h

2638

uint8_t gfxoffset; // in amps

drivers/gpu/drm/amd/include/atomfirmware.h

2639

uint8_t padding_telemetrygfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2642

uint8_t socoffset; // in amps

drivers/gpu/drm/amd/include/atomfirmware.h

2643

uint8_t padding_telemetrysoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2646

uint8_t memoffset; // in amps

drivers/gpu/drm/amd/include/atomfirmware.h

2647

uint8_t padding_telemetrymem;

drivers/gpu/drm/amd/include/atomfirmware.h

2650

uint8_t boardoffset; // in amps

drivers/gpu/drm/amd/include/atomfirmware.h

2651

uint8_t padding_telemetryboardinput;

drivers/gpu/drm/amd/include/atomfirmware.h

2654

uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event

drivers/gpu/drm/amd/include/atomfirmware.h

2655

uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event

drivers/gpu/drm/amd/include/atomfirmware.h

2656

uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event

drivers/gpu/drm/amd/include/atomfirmware.h

2657

uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event

drivers/gpu/drm/amd/include/atomfirmware.h

2660

uint8_t pllgfxclkspreadenabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2661

uint8_t pllgfxclkspreadpercent; // q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2665

uint8_t uclkspreadenabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2666

uint8_t uclkspreadpercent; // q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2670

uint8_t fclkspreadenabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2671

uint8_t fclkspreadpercent; // q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2676

uint8_t fllgfxclkspreadenabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2677

uint8_t fllgfxclkspreadpercent; // q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2686

uint8_t drambitwidth; // for dram use only. see dram bit width type defines

drivers/gpu/drm/amd/include/atomfirmware.h

2687

uint8_t paddingmem[3];

drivers/gpu/drm/amd/include/atomfirmware.h

2694

uint8_t xgmilinkspeed[4];

drivers/gpu/drm/amd/include/atomfirmware.h

2695

uint8_t xgmilinkwidth[4];

drivers/gpu/drm/amd/include/atomfirmware.h

2715

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2716

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2717

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2718

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2720

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2721

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2722

uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)

drivers/gpu/drm/amd/include/atomfirmware.h

2723

uint8_t Padding8_V;

drivers/gpu/drm/amd/include/atomfirmware.h

2727

uint8_t GfxOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2728

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2730

uint8_t SocOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2731

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2734

uint8_t Mem0Offset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2735

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/include/atomfirmware.h

2738

uint8_t Mem1Offset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2739

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/include/atomfirmware.h

2742

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2743

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2744

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2745

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2747

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2748

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2749

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/include/atomfirmware.h

2750

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/include/atomfirmware.h

2753

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/include/atomfirmware.h

2754

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/include/atomfirmware.h

2755

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/include/atomfirmware.h

2756

uint8_t padding8_4;

drivers/gpu/drm/amd/include/atomfirmware.h

2759

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2760

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2764

uint8_t DfllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2765

uint8_t DfllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2769

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2770

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2774

uint8_t SoclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2775

uint8_t SocclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2786

uint8_t GpioI2cScl; // Serial Clock

drivers/gpu/drm/amd/include/atomfirmware.h

2787

uint8_t GpioI2cSda; // Serial Data

drivers/gpu/drm/amd/include/atomfirmware.h

2791

uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed

drivers/gpu/drm/amd/include/atomfirmware.h

2792

uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status

drivers/gpu/drm/amd/include/atomfirmware.h

2796

uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]

drivers/gpu/drm/amd/include/atomfirmware.h

2798

uint8_t MvddUlvPhaseSheddingMask;

drivers/gpu/drm/amd/include/atomfirmware.h

2799

uint8_t VddciUlvPhaseSheddingMask;

drivers/gpu/drm/amd/include/atomfirmware.h

2800

uint8_t Padding8_Psi1;

drivers/gpu/drm/amd/include/atomfirmware.h

2801

uint8_t Padding8_Psi2;

drivers/gpu/drm/amd/include/atomfirmware.h

2808

uint8_t Enabled;

drivers/gpu/drm/amd/include/atomfirmware.h

2809

uint8_t Speed;

drivers/gpu/drm/amd/include/atomfirmware.h

2810

uint8_t SlaveAddress;

drivers/gpu/drm/amd/include/atomfirmware.h

2811

uint8_t ControllerPort;

drivers/gpu/drm/amd/include/atomfirmware.h

2812

uint8_t ControllerName;

drivers/gpu/drm/amd/include/atomfirmware.h

2813

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/include/atomfirmware.h

2814

uint8_t I2cProtocol;

drivers/gpu/drm/amd/include/atomfirmware.h

2815

uint8_t PaddingConfig;

drivers/gpu/drm/amd/include/atomfirmware.h

2828

uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1

drivers/gpu/drm/amd/include/atomfirmware.h

2829

uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1

drivers/gpu/drm/amd/include/atomfirmware.h

2830

uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off

drivers/gpu/drm/amd/include/atomfirmware.h

2831

uint8_t I2cSpare;

drivers/gpu/drm/amd/include/atomfirmware.h

2834

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2835

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2836

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2837

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/include/atomfirmware.h

2839

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2840

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2841

uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2842

uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/include/atomfirmware.h

2846

uint8_t GfxOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2847

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2850

uint8_t SocOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2851

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2854

uint8_t Mem0Offset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2855

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/include/atomfirmware.h

2858

uint8_t Mem1Offset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2859

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/include/atomfirmware.h

2864

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2865

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/include/atomfirmware.h

2866

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2867

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2869

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2870

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2871

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/include/atomfirmware.h

2872

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/include/atomfirmware.h

2875

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/include/atomfirmware.h

2876

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/include/atomfirmware.h

2877

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/include/atomfirmware.h

2878

uint8_t LedEnableMask;

drivers/gpu/drm/amd/include/atomfirmware.h

2880

uint8_t LedPcie; // GPIO number for PCIE results

drivers/gpu/drm/amd/include/atomfirmware.h

2881

uint8_t LedError; // GPIO number for Error Cases

drivers/gpu/drm/amd/include/atomfirmware.h

2882

uint8_t LedSpare1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

2887

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2888

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2892

uint8_t DfllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2893

uint8_t DfllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2897

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2898

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2902

uint8_t FclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2903

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2909

uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines

drivers/gpu/drm/amd/include/atomfirmware.h

2910

uint8_t PaddingMem1[3];

drivers/gpu/drm/amd/include/atomfirmware.h

2917

uint8_t XgmiLinkSpeed [4];

drivers/gpu/drm/amd/include/atomfirmware.h

2918

uint8_t XgmiLinkWidth [4];

drivers/gpu/drm/amd/include/atomfirmware.h

2936

uint8_t GfxOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2937

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/include/atomfirmware.h

2940

uint8_t SocOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2941

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/include/atomfirmware.h

2944

uint8_t MemOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2945

uint8_t Padding_TelemetryMem;

drivers/gpu/drm/amd/include/atomfirmware.h

2948

uint8_t BoardOffset; // in Amps

drivers/gpu/drm/amd/include/atomfirmware.h

2949

uint8_t Padding_TelemetryBoardInput;

drivers/gpu/drm/amd/include/atomfirmware.h

2956

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2957

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2958

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2959

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/include/atomfirmware.h

2962

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2963

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2967

uint8_t FclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/include/atomfirmware.h

2968

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/include/atomfirmware.h

2975

uint8_t GpioI2cScl; // Serial Clock

drivers/gpu/drm/amd/include/atomfirmware.h

2976

uint8_t GpioI2cSda; // Serial Data

drivers/gpu/drm/amd/include/atomfirmware.h

3011

uint8_t enable_gb_vdroop_table_cksoff;

drivers/gpu/drm/amd/include/atomfirmware.h

3012

uint8_t enable_gb_vdroop_table_ckson;

drivers/gpu/drm/amd/include/atomfirmware.h

3013

uint8_t enable_gb_fuse_table_cksoff;

drivers/gpu/drm/amd/include/atomfirmware.h

3014

uint8_t enable_gb_fuse_table_ckson;

drivers/gpu/drm/amd/include/atomfirmware.h

3016

uint8_t enable_apply_avfs_cksoff_voltage;

drivers/gpu/drm/amd/include/atomfirmware.h

3017

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

3055

uint8_t enable_gb_vdroop_table_cksoff;

drivers/gpu/drm/amd/include/atomfirmware.h

3056

uint8_t enable_gb_vdroop_table_ckson;

drivers/gpu/drm/amd/include/atomfirmware.h

3057

uint8_t enable_gb_fuse_table_cksoff;

drivers/gpu/drm/amd/include/atomfirmware.h

3058

uint8_t enable_gb_fuse_table_ckson;

drivers/gpu/drm/amd/include/atomfirmware.h

3060

uint8_t enable_apply_avfs_cksoff_voltage;

drivers/gpu/drm/amd/include/atomfirmware.h

3061

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

3080

uint8_t enable_acg_gb_vdroop_table;

drivers/gpu/drm/amd/include/atomfirmware.h

3081

uint8_t enable_acg_gb_fuse_table;

drivers/gpu/drm/amd/include/atomfirmware.h

3104

uint8_t uvdip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3105

uint8_t uvdip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3106

uint8_t vceip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3107

uint8_t vceip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3132

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3133

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3134

uint8_t vram_type; //enum of atom_dgpu_vram_type

drivers/gpu/drm/amd/include/atomfirmware.h

3135

uint8_t umc_config;

drivers/gpu/drm/amd/include/atomfirmware.h

3159

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3160

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3161

uint8_t vram_type; //enum of atom_dgpu_vram_type

drivers/gpu/drm/amd/include/atomfirmware.h

3162

uint8_t umc_config;

drivers/gpu/drm/amd/include/atomfirmware.h

3179

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3180

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3181

uint8_t vram_type; //enum of atom_dgpu_vram_type

drivers/gpu/drm/amd/include/atomfirmware.h

3182

uint8_t umc_config;

drivers/gpu/drm/amd/include/atomfirmware.h

3204

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3205

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3206

uint8_t vram_type;

drivers/gpu/drm/amd/include/atomfirmware.h

3207

uint8_t umc_config;

drivers/gpu/drm/amd/include/atomfirmware.h

3213

uint8_t channel_num;

drivers/gpu/drm/amd/include/atomfirmware.h

3214

uint8_t channel_width;

drivers/gpu/drm/amd/include/atomfirmware.h

3215

uint8_t channel_reserve[2];

drivers/gpu/drm/amd/include/atomfirmware.h

3216

uint8_t umc_info_reserved[16];

drivers/gpu/drm/amd/include/atomfirmware.h

3232

uint8_t ext_memory_id; // Current memory module ID

drivers/gpu/drm/amd/include/atomfirmware.h

3233

uint8_t memory_type; // enum of atom_dgpu_vram_type

drivers/gpu/drm/amd/include/atomfirmware.h

3234

uint8_t channel_num; // Number of mem. channels supported in this module

drivers/gpu/drm/amd/include/atomfirmware.h

3235

uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT

drivers/gpu/drm/amd/include/atomfirmware.h

3236

uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16

drivers/gpu/drm/amd/include/atomfirmware.h

3237

uint8_t tunningset_id; // MC phy registers set per.

drivers/gpu/drm/amd/include/atomfirmware.h

3238

uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code

drivers/gpu/drm/amd/include/atomfirmware.h

3239

uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)

drivers/gpu/drm/amd/include/atomfirmware.h

3240

uint8_t hbm_ven_rev_id; // hbm_ven_rev_id

drivers/gpu/drm/amd/include/atomfirmware.h

3241

uint8_t vram_rsd2; // reserved

drivers/gpu/drm/amd/include/atomfirmware.h

3255

uint8_t vram_module_num; // indicate number of VRAM module

drivers/gpu/drm/amd/include/atomfirmware.h

3256

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3257

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3258

uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset

drivers/gpu/drm/amd/include/atomfirmware.h

3268

uint8_t density;

drivers/gpu/drm/amd/include/atomfirmware.h

3269

uint8_t tunningset_id;

drivers/gpu/drm/amd/include/atomfirmware.h

3270

uint8_t ext_memory_id;

drivers/gpu/drm/amd/include/atomfirmware.h

3271

uint8_t dram_vendor_id;

drivers/gpu/drm/amd/include/atomfirmware.h

3290

uint8_t vram_module_num;

drivers/gpu/drm/amd/include/atomfirmware.h

3291

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3292

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3293

uint8_t mc_phy_tile_num;

drivers/gpu/drm/amd/include/atomfirmware.h

3294

uint8_t memory_type;

drivers/gpu/drm/amd/include/atomfirmware.h

3295

uint8_t channel_num;

drivers/gpu/drm/amd/include/atomfirmware.h

3296

uint8_t channel_width;

drivers/gpu/drm/amd/include/atomfirmware.h

3297

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

3355

uint8_t ext_memory_id; // Current memory module ID

drivers/gpu/drm/amd/include/atomfirmware.h

3356

uint8_t memory_type; // enum of atom_dgpu_vram_type

drivers/gpu/drm/amd/include/atomfirmware.h

3357

uint8_t channel_num; // Number of mem. channels supported in this module

drivers/gpu/drm/amd/include/atomfirmware.h

3358

uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT

drivers/gpu/drm/amd/include/atomfirmware.h

3359

uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16

drivers/gpu/drm/amd/include/atomfirmware.h

3360

uint8_t tunningset_id; // MC phy registers set per

drivers/gpu/drm/amd/include/atomfirmware.h

3361

uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code

drivers/gpu/drm/amd/include/atomfirmware.h

3362

uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)

drivers/gpu/drm/amd/include/atomfirmware.h

3363

uint8_t vram_flags; // bit0= bankgroup enable

drivers/gpu/drm/amd/include/atomfirmware.h

3364

uint8_t vram_rsd2; // reserved

drivers/gpu/drm/amd/include/atomfirmware.h

3382

uint8_t vram_module_num; // indicate number of VRAM module

drivers/gpu/drm/amd/include/atomfirmware.h

3383

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3384

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3385

uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset

drivers/gpu/drm/amd/include/atomfirmware.h

3395

uint8_t ext_memory_id; // Current memory module ID

drivers/gpu/drm/amd/include/atomfirmware.h

3396

uint8_t memory_type; // enum of atom_dgpu_vram_type

drivers/gpu/drm/amd/include/atomfirmware.h

3397

uint8_t channel_num; // Number of mem. channels supported in this module

drivers/gpu/drm/amd/include/atomfirmware.h

3398

uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT

drivers/gpu/drm/amd/include/atomfirmware.h

3399

uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16

drivers/gpu/drm/amd/include/atomfirmware.h

3400

uint8_t tunningset_id; // MC phy registers set per.

drivers/gpu/drm/amd/include/atomfirmware.h

3402

uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code

drivers/gpu/drm/amd/include/atomfirmware.h

3403

uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)

drivers/gpu/drm/amd/include/atomfirmware.h

3404

uint8_t vram_flags; // bit0= bankgroup enable

drivers/gpu/drm/amd/include/atomfirmware.h

3405

uint8_t vram_rsd2; // reserved

drivers/gpu/drm/amd/include/atomfirmware.h

3418

uint8_t RL;

drivers/gpu/drm/amd/include/atomfirmware.h

3419

uint8_t WL;

drivers/gpu/drm/amd/include/atomfirmware.h

3420

uint8_t tRAS;

drivers/gpu/drm/amd/include/atomfirmware.h

3421

uint8_t tRC;

drivers/gpu/drm/amd/include/atomfirmware.h

3424

uint8_t tRFC;

drivers/gpu/drm/amd/include/atomfirmware.h

3425

uint8_t tRFCpb;

drivers/gpu/drm/amd/include/atomfirmware.h

3427

uint8_t tRREFD;

drivers/gpu/drm/amd/include/atomfirmware.h

3428

uint8_t tRCDRD;

drivers/gpu/drm/amd/include/atomfirmware.h

3429

uint8_t tRCDWR;

drivers/gpu/drm/amd/include/atomfirmware.h

3430

uint8_t tRP;

drivers/gpu/drm/amd/include/atomfirmware.h

3432

uint8_t tRRDS;

drivers/gpu/drm/amd/include/atomfirmware.h

3433

uint8_t tRRDL;

drivers/gpu/drm/amd/include/atomfirmware.h

3434

uint8_t tWR;

drivers/gpu/drm/amd/include/atomfirmware.h

3435

uint8_t tWTRS;

drivers/gpu/drm/amd/include/atomfirmware.h

3437

uint8_t tWTRL;

drivers/gpu/drm/amd/include/atomfirmware.h

3438

uint8_t tFAW;

drivers/gpu/drm/amd/include/atomfirmware.h

3439

uint8_t tCCDS;

drivers/gpu/drm/amd/include/atomfirmware.h

3440

uint8_t tCCDL;

drivers/gpu/drm/amd/include/atomfirmware.h

3442

uint8_t tCRCRL;

drivers/gpu/drm/amd/include/atomfirmware.h

3443

uint8_t tCRCWL;

drivers/gpu/drm/amd/include/atomfirmware.h

3444

uint8_t tCKE;

drivers/gpu/drm/amd/include/atomfirmware.h

3445

uint8_t tCKSRE;

drivers/gpu/drm/amd/include/atomfirmware.h

3447

uint8_t tCKSRX;

drivers/gpu/drm/amd/include/atomfirmware.h

3448

uint8_t tRTPS;

drivers/gpu/drm/amd/include/atomfirmware.h

3449

uint8_t tRTPL;

drivers/gpu/drm/amd/include/atomfirmware.h

3450

uint8_t tMRD;

drivers/gpu/drm/amd/include/atomfirmware.h

3452

uint8_t tMOD;

drivers/gpu/drm/amd/include/atomfirmware.h

3453

uint8_t tXS;

drivers/gpu/drm/amd/include/atomfirmware.h

3454

uint8_t tXHP;

drivers/gpu/drm/amd/include/atomfirmware.h

3455

uint8_t tXSMRS;

drivers/gpu/drm/amd/include/atomfirmware.h

3459

uint8_t tPD;

drivers/gpu/drm/amd/include/atomfirmware.h

3460

uint8_t tXP;

drivers/gpu/drm/amd/include/atomfirmware.h

3461

uint8_t tCPDED;

drivers/gpu/drm/amd/include/atomfirmware.h

3462

uint8_t tACTPDE;

drivers/gpu/drm/amd/include/atomfirmware.h

3464

uint8_t tPREPDE;

drivers/gpu/drm/amd/include/atomfirmware.h

3465

uint8_t tREFPDE;

drivers/gpu/drm/amd/include/atomfirmware.h

3466

uint8_t tMRSPDEN;

drivers/gpu/drm/amd/include/atomfirmware.h

3467

uint8_t tRDSRE;

drivers/gpu/drm/amd/include/atomfirmware.h

3469

uint8_t tWRSRE;

drivers/gpu/drm/amd/include/atomfirmware.h

3470

uint8_t tPPD;

drivers/gpu/drm/amd/include/atomfirmware.h

3471

uint8_t tCCDMW;

drivers/gpu/drm/amd/include/atomfirmware.h

3472

uint8_t tWTRTR;

drivers/gpu/drm/amd/include/atomfirmware.h

3474

uint8_t tLTLTR;

drivers/gpu/drm/amd/include/atomfirmware.h

3475

uint8_t tREFTR;

drivers/gpu/drm/amd/include/atomfirmware.h

3476

uint8_t VNDR;

drivers/gpu/drm/amd/include/atomfirmware.h

3477

uint8_t reserved[9];

drivers/gpu/drm/amd/include/atomfirmware.h

3492

uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK

drivers/gpu/drm/amd/include/atomfirmware.h

3506

uint8_t vram_module_num; // indicate number of VRAM module

drivers/gpu/drm/amd/include/atomfirmware.h

3507

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3508

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3509

uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset

drivers/gpu/drm/amd/include/atomfirmware.h

3523

uint8_t vram_module_num;

drivers/gpu/drm/amd/include/atomfirmware.h

3524

uint8_t umcip_min_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3525

uint8_t umcip_max_ver;

drivers/gpu/drm/amd/include/atomfirmware.h

3526

uint8_t mc_phy_tile_num;

drivers/gpu/drm/amd/include/atomfirmware.h

3541

uint8_t voltage_type; //enum atom_voltage_type

drivers/gpu/drm/amd/include/atomfirmware.h

3542

uint8_t voltage_mode; //enum atom_voltage_object_mode

drivers/gpu/drm/amd/include/atomfirmware.h

3560

uint8_t regulator_id; //Indicate Voltage Regulator Id

drivers/gpu/drm/amd/include/atomfirmware.h

3561

uint8_t i2c_id;

drivers/gpu/drm/amd/include/atomfirmware.h

3562

uint8_t i2c_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

3563

uint8_t i2c_control_offset;

drivers/gpu/drm/amd/include/atomfirmware.h

3564

uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data

drivers/gpu/drm/amd/include/atomfirmware.h

3565

uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.

drivers/gpu/drm/amd/include/atomfirmware.h

3566

uint8_t reserved[2];

drivers/gpu/drm/amd/include/atomfirmware.h

3587

uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode

drivers/gpu/drm/amd/include/atomfirmware.h

3588

uint8_t gpio_entry_num; // indicate the entry numbers of Votlage/Gpio value Look up table

drivers/gpu/drm/amd/include/atomfirmware.h

3589

uint8_t phase_delay_us; // phase delay in unit of micro second

drivers/gpu/drm/amd/include/atomfirmware.h

3590

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

3598

uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable

drivers/gpu/drm/amd/include/atomfirmware.h

3599

uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold

drivers/gpu/drm/amd/include/atomfirmware.h

3600

uint8_t psi0_enable; //

drivers/gpu/drm/amd/include/atomfirmware.h

3601

uint8_t maxvstep;

drivers/gpu/drm/amd/include/atomfirmware.h

3602

uint8_t telemetry_offset;

drivers/gpu/drm/amd/include/atomfirmware.h

3603

uint8_t telemetry_gain;

drivers/gpu/drm/amd/include/atomfirmware.h

3610

uint8_t merged_powerrail_type; //enum atom_voltage_type

drivers/gpu/drm/amd/include/atomfirmware.h

3611

uint8_t reserved[3];

drivers/gpu/drm/amd/include/atomfirmware.h

3756

uint8_t voltagetype; /* enum atom_voltage_type */

drivers/gpu/drm/amd/include/atomfirmware.h

3757

uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */

drivers/gpu/drm/amd/include/atomfirmware.h

3805

uint8_t pll_ss_enable;

drivers/gpu/drm/amd/include/atomfirmware.h

3806

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

3821

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

3822

uint8_t bitslen;

drivers/gpu/drm/amd/include/atomfirmware.h

3840

uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2

drivers/gpu/drm/amd/include/atomfirmware.h

3841

uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )

drivers/gpu/drm/amd/include/atomfirmware.h

3842

uint8_t command; // enum of atom_get_smu_clock_info_command

drivers/gpu/drm/amd/include/atomfirmware.h

3843

uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )

drivers/gpu/drm/amd/include/atomfirmware.h

4021

uint8_t ucode_func_id;

drivers/gpu/drm/amd/include/atomfirmware.h

4022

uint8_t ucode_reserved[3];

drivers/gpu/drm/amd/include/atomfirmware.h

4037

uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0

drivers/gpu/drm/amd/include/atomfirmware.h

4038

uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,

drivers/gpu/drm/amd/include/atomfirmware.h

4040

uint8_t encoder_mode; // Encoder mode:

drivers/gpu/drm/amd/include/atomfirmware.h

4041

uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info

drivers/gpu/drm/amd/include/atomfirmware.h

4042

uint8_t crtc_id; // enum of atom_crtc_def

drivers/gpu/drm/amd/include/atomfirmware.h

4043

uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio

drivers/gpu/drm/amd/include/atomfirmware.h

4044

uint8_t reserved1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4083

uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK

drivers/gpu/drm/amd/include/atomfirmware.h

4084

uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx

drivers/gpu/drm/amd/include/atomfirmware.h

4085

uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )

drivers/gpu/drm/amd/include/atomfirmware.h

4086

uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK

drivers/gpu/drm/amd/include/atomfirmware.h

4130

uint8_t crtc_id; // enum atom_crtc_def

drivers/gpu/drm/amd/include/atomfirmware.h

4131

uint8_t blanking; // enum atom_blank_crtc_command

drivers/gpu/drm/amd/include/atomfirmware.h

4147

uint8_t crtc_id; // enum atom_crtc_def

drivers/gpu/drm/amd/include/atomfirmware.h

4148

uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE

drivers/gpu/drm/amd/include/atomfirmware.h

4149

uint8_t padding[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4158

uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...

drivers/gpu/drm/amd/include/atomfirmware.h

4159

uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE

drivers/gpu/drm/amd/include/atomfirmware.h

4160

uint8_t padding[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4183

uint8_t h_border;

drivers/gpu/drm/amd/include/atomfirmware.h

4184

uint8_t v_border;

drivers/gpu/drm/amd/include/atomfirmware.h

4185

uint8_t crtc_id; // enum atom_crtc_def

drivers/gpu/drm/amd/include/atomfirmware.h

4186

uint8_t encoder_mode; // atom_encode_mode_def

drivers/gpu/drm/amd/include/atomfirmware.h

4187

uint8_t padding[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4196

uint8_t i2cspeed_khz;

drivers/gpu/drm/amd/include/atomfirmware.h

4198

uint8_t regindex;

drivers/gpu/drm/amd/include/atomfirmware.h

4199

uint8_t status; /* enum atom_process_i2c_flag */

drivers/gpu/drm/amd/include/atomfirmware.h

4202

uint8_t flag; /* enum atom_process_i2c_status */

drivers/gpu/drm/amd/include/atomfirmware.h

4203

uint8_t trans_bytes;

drivers/gpu/drm/amd/include/atomfirmware.h

4204

uint8_t slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

4205

uint8_t i2c_id;

drivers/gpu/drm/amd/include/atomfirmware.h

4233

uint8_t channelid;

drivers/gpu/drm/amd/include/atomfirmware.h

4235

uint8_t reply_status;

drivers/gpu/drm/amd/include/atomfirmware.h

4236

uint8_t aux_delay;

drivers/gpu/drm/amd/include/atomfirmware.h

4238

uint8_t dataout_len;

drivers/gpu/drm/amd/include/atomfirmware.h

4239

uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6

drivers/gpu/drm/amd/include/atomfirmware.h

4249

uint8_t crtc_id; // enum atom_crtc_def

drivers/gpu/drm/amd/include/atomfirmware.h

4250

uint8_t encoder_id; // enum atom_dig_def

drivers/gpu/drm/amd/include/atomfirmware.h

4251

uint8_t encode_mode; // enum atom_encode_mode_def

drivers/gpu/drm/amd/include/atomfirmware.h

4252

uint8_t dst_bpc; // enum atom_panel_bit_per_color

drivers/gpu/drm/amd/include/atomfirmware.h

4302

uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid

drivers/gpu/drm/amd/include/atomfirmware.h

4303

uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP

drivers/gpu/drm/amd/include/atomfirmware.h

4304

uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI

drivers/gpu/drm/amd/include/atomfirmware.h

4305

uint8_t lanenum; // Lane number

drivers/gpu/drm/amd/include/atomfirmware.h

4307

uint8_t bitpercolor;

drivers/gpu/drm/amd/include/atomfirmware.h

4308

uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc

drivers/gpu/drm/amd/include/atomfirmware.h

4309

uint8_t reserved[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4314

uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid

drivers/gpu/drm/amd/include/atomfirmware.h

4315

uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP

drivers/gpu/drm/amd/include/atomfirmware.h

4316

uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI

drivers/gpu/drm/amd/include/atomfirmware.h

4317

uint8_t lanenum; // Lane number

drivers/gpu/drm/amd/include/atomfirmware.h

4318

uint8_t symclk_10khz; // Symbol Clock in 10Khz

drivers/gpu/drm/amd/include/atomfirmware.h

4319

uint8_t hpd_sel;

drivers/gpu/drm/amd/include/atomfirmware.h

4320

uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,

drivers/gpu/drm/amd/include/atomfirmware.h

4321

uint8_t reserved[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4326

uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid

drivers/gpu/drm/amd/include/atomfirmware.h

4327

uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP

drivers/gpu/drm/amd/include/atomfirmware.h

4328

uint8_t panelmode; // enum atom_dig_encoder_control_panelmode

drivers/gpu/drm/amd/include/atomfirmware.h

4329

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

4335

uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid

drivers/gpu/drm/amd/include/atomfirmware.h

4336

uint8_t action; // = rest of generic encoder command which does not carry any parameters

drivers/gpu/drm/amd/include/atomfirmware.h

4337

uint8_t reserved1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

4356

uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF

drivers/gpu/drm/amd/include/atomfirmware.h

4357

uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx

drivers/gpu/drm/amd/include/atomfirmware.h

4359

uint8_t digmode; // enum atom_encode_mode_def

drivers/gpu/drm/amd/include/atomfirmware.h

4360

uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"

drivers/gpu/drm/amd/include/atomfirmware.h

4362

uint8_t lanenum; // Lane number 1, 2, 4, 8

drivers/gpu/drm/amd/include/atomfirmware.h

4364

uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned

drivers/gpu/drm/amd/include/atomfirmware.h

4365

uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,

drivers/gpu/drm/amd/include/atomfirmware.h

4366

uint8_t connobj_id; // Connector Object Id defined in ObjectId.h

drivers/gpu/drm/amd/include/atomfirmware.h

4367

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

4445

uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT

drivers/gpu/drm/amd/include/atomfirmware.h

4446

uint8_t action; //

drivers/gpu/drm/amd/include/atomfirmware.h

4447

uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT

drivers/gpu/drm/amd/include/atomfirmware.h

4448

uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT

drivers/gpu/drm/amd/include/atomfirmware.h

4449

uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP

drivers/gpu/drm/amd/include/atomfirmware.h

4450

uint8_t hpd_id;

drivers/gpu/drm/amd/include/atomfirmware.h

449

uint8_t h_border;

drivers/gpu/drm/amd/include/atomfirmware.h

4498

uint8_t revision;

drivers/gpu/drm/amd/include/atomfirmware.h

4499

uint8_t checksum;

drivers/gpu/drm/amd/include/atomfirmware.h

450

uint8_t v_border;

drivers/gpu/drm/amd/include/atomfirmware.h

4500

uint8_t oemId[6];

drivers/gpu/drm/amd/include/atomfirmware.h

4501

uint8_t oemTableId[8]; //UINT64 OemTableId;

drivers/gpu/drm/amd/include/atomfirmware.h

4509

uint8_t tableUUID[16]; //0x24

drivers/gpu/drm/amd/include/atomfirmware.h

452

uint8_t atom_mode_id;

drivers/gpu/drm/amd/include/atomfirmware.h

453

uint8_t refreshrate;

drivers/gpu/drm/amd/include/atomfirmware.h

4530

uint8_t vbioscontent[1];

drivers/gpu/drm/amd/include/atomfirmware.h

4535

uint8_t lib1content[1];

drivers/gpu/drm/amd/include/atomfirmware.h

492

uint8_t mem_module_id;

drivers/gpu/drm/amd/include/atomfirmware.h

493

uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */

drivers/gpu/drm/amd/include/atomfirmware.h

494

uint8_t reserved1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

52

#ifndef uint8_t

drivers/gpu/drm/amd/include/atomfirmware.h

531

uint8_t mem_module_id;

drivers/gpu/drm/amd/include/atomfirmware.h

532

uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */

drivers/gpu/drm/amd/include/atomfirmware.h

533

uint8_t reserved1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

536

uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def

drivers/gpu/drm/amd/include/atomfirmware.h

537

uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id

drivers/gpu/drm/amd/include/atomfirmware.h

538

uint8_t board_i2c_feature_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

539

uint8_t reserved3;

drivers/gpu/drm/amd/include/atomfirmware.h

559

uint8_t mem_module_id;

drivers/gpu/drm/amd/include/atomfirmware.h

560

uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */

drivers/gpu/drm/amd/include/atomfirmware.h

561

uint8_t reserved1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

564

uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def

drivers/gpu/drm/amd/include/atomfirmware.h

565

uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id

drivers/gpu/drm/amd/include/atomfirmware.h

566

uint8_t board_i2c_feature_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

567

uint8_t reserved3;

drivers/gpu/drm/amd/include/atomfirmware.h

587

uint8_t mem_module_id;

drivers/gpu/drm/amd/include/atomfirmware.h

588

uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */

drivers/gpu/drm/amd/include/atomfirmware.h

589

uint8_t reserved1[2];

drivers/gpu/drm/amd/include/atomfirmware.h

592

uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def

drivers/gpu/drm/amd/include/atomfirmware.h

593

uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id

drivers/gpu/drm/amd/include/atomfirmware.h

594

uint8_t board_i2c_feature_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

595

uint8_t ras_rom_i2c_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

622

uint8_t mem_module_id;

drivers/gpu/drm/amd/include/atomfirmware.h

623

uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */

drivers/gpu/drm/amd/include/atomfirmware.h

624

uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_IO_MODE

drivers/gpu/drm/amd/include/atomfirmware.h

625

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

628

uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def

drivers/gpu/drm/amd/include/atomfirmware.h

629

uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id

drivers/gpu/drm/amd/include/atomfirmware.h

630

uint8_t board_i2c_feature_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

631

uint8_t ras_rom_i2c_slave_addr;

drivers/gpu/drm/amd/include/atomfirmware.h

662

uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/

drivers/gpu/drm/amd/include/atomfirmware.h

663

uint8_t pwr_on_de_to_vary_bl;

drivers/gpu/drm/amd/include/atomfirmware.h

664

uint8_t pwr_down_vary_bloff_to_de;

drivers/gpu/drm/amd/include/atomfirmware.h

665

uint8_t pwr_down_de_to_digoff;

drivers/gpu/drm/amd/include/atomfirmware.h

666

uint8_t pwr_off_delay;

drivers/gpu/drm/amd/include/atomfirmware.h

667

uint8_t pwr_on_vary_bl_to_blon;

drivers/gpu/drm/amd/include/atomfirmware.h

668

uint8_t pwr_down_bloff_to_vary_bloff;

drivers/gpu/drm/amd/include/atomfirmware.h

669

uint8_t panel_bpc;

drivers/gpu/drm/amd/include/atomfirmware.h

670

uint8_t dpcd_edp_config_cap;

drivers/gpu/drm/amd/include/atomfirmware.h

671

uint8_t dpcd_max_link_rate;

drivers/gpu/drm/amd/include/atomfirmware.h

672

uint8_t dpcd_max_lane_count;

drivers/gpu/drm/amd/include/atomfirmware.h

673

uint8_t dpcd_max_downspread;

drivers/gpu/drm/amd/include/atomfirmware.h

674

uint8_t min_allowed_bl_level;

drivers/gpu/drm/amd/include/atomfirmware.h

675

uint8_t max_allowed_bl_level;

drivers/gpu/drm/amd/include/atomfirmware.h

676

uint8_t bootup_bl_level;

drivers/gpu/drm/amd/include/atomfirmware.h

677

uint8_t dplvdsrxid;

drivers/gpu/drm/amd/include/atomfirmware.h

704

uint8_t gpio_bitshift;

drivers/gpu/drm/amd/include/atomfirmware.h

705

uint8_t gpio_mask_bitshift;

drivers/gpu/drm/amd/include/atomfirmware.h

706

uint8_t gpio_id;

drivers/gpu/drm/amd/include/atomfirmware.h

707

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

826

uint8_t record_type; //An emun to indicate the record type

drivers/gpu/drm/amd/include/atomfirmware.h

827

uint8_t record_size; //The size of the whole record in byte

drivers/gpu/drm/amd/include/atomfirmware.h

833

uint8_t i2c_id;

drivers/gpu/drm/amd/include/atomfirmware.h

834

uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC

drivers/gpu/drm/amd/include/atomfirmware.h

840

uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info

drivers/gpu/drm/amd/include/atomfirmware.h

841

uint8_t plugin_pin_state;

drivers/gpu/drm/amd/include/atomfirmware.h

893

uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table

drivers/gpu/drm/amd/include/atomfirmware.h

894

uint8_t gpio_pinstate; // Pin state showing how to set-up the pin

drivers/gpu/drm/amd/include/atomfirmware.h

900

uint8_t flag; // Future expnadibility

drivers/gpu/drm/amd/include/atomfirmware.h

901

uint8_t number_of_pins; // Number of GPIO pins used to control the object

drivers/gpu/drm/amd/include/atomfirmware.h

939

uint8_t hpd_pin_map[8];

drivers/gpu/drm/amd/include/atomfirmware.h

945

uint8_t aux_ddc_map[8];

drivers/gpu/drm/amd/include/atomfirmware.h

952

uint8_t maxtmdsclkrate_in2_5mhz;

drivers/gpu/drm/amd/include/atomfirmware.h

953

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

959

uint8_t connector_type;

drivers/gpu/drm/amd/include/atomfirmware.h

960

uint8_t position;

drivers/gpu/drm/amd/include/atomfirmware.h

976

uint8_t bracketlen;

drivers/gpu/drm/amd/include/atomfirmware.h

977

uint8_t bracketwidth;

drivers/gpu/drm/amd/include/atomfirmware.h

978

uint8_t conn_num;

drivers/gpu/drm/amd/include/atomfirmware.h

979

uint8_t reserved;

drivers/gpu/drm/amd/include/atomfirmware.h

985

uint8_t bracketlen; //Bracket Length in mm

drivers/gpu/drm/amd/include/atomfirmware.h

986

uint8_t bracketwidth; //Bracket Width in mm

drivers/gpu/drm/amd/include/atomfirmware.h

987

uint8_t conn_num; //Connector numbering

drivers/gpu/drm/amd/include/atomfirmware.h

988

uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)

drivers/gpu/drm/amd/include/atomfirmware.h

989

uint8_t reserved1;

drivers/gpu/drm/amd/include/atomfirmware.h

990

uint8_t reserved2;

drivers/gpu/drm/amd/include/discovery.h

101

uint8_t reserved : 4; /* Placeholder field */

drivers/gpu/drm/amd/include/discovery.h

102

uint8_t harvest : 4; /* Harvest */

drivers/gpu/drm/amd/include/discovery.h

104

uint8_t harvest : 4; /* Harvest */

drivers/gpu/drm/amd/include/discovery.h

105

uint8_t reserved : 4; /* Placeholder field */

drivers/gpu/drm/amd/include/discovery.h

113

uint8_t instance_number; /* Instance number for the IP */

drivers/gpu/drm/amd/include/discovery.h

114

uint8_t num_base_address; /* Number of base addresses*/

drivers/gpu/drm/amd/include/discovery.h

115

uint8_t major; /* Hardware ID.major version */

drivers/gpu/drm/amd/include/discovery.h

116

uint8_t minor; /* Hardware ID.minor version */

drivers/gpu/drm/amd/include/discovery.h

117

uint8_t revision; /* Hardware ID.revision version */

drivers/gpu/drm/amd/include/discovery.h

119

uint8_t variant : 4; /* HW variant */

drivers/gpu/drm/amd/include/discovery.h

120

uint8_t sub_revision : 4; /* HCID Sub-Revision */

drivers/gpu/drm/amd/include/discovery.h

122

uint8_t sub_revision : 4; /* HCID Sub-Revision */

drivers/gpu/drm/amd/include/discovery.h

123

uint8_t variant : 4; /* HW variant */

drivers/gpu/drm/amd/include/discovery.h

130

uint8_t instance_number; /* Instance number for the IP */

drivers/gpu/drm/amd/include/discovery.h

131

uint8_t num_base_address; /* Number of base addresses*/

drivers/gpu/drm/amd/include/discovery.h

132

uint8_t major; /* Hardware ID.major version */

drivers/gpu/drm/amd/include/discovery.h

133

uint8_t minor; /* Hardware ID.minor version */

drivers/gpu/drm/amd/include/discovery.h

134

uint8_t revision; /* Hardware ID.revision version */

drivers/gpu/drm/amd/include/discovery.h

136

uint8_t sub_revision : 4; /* HCID Sub-Revision */

drivers/gpu/drm/amd/include/discovery.h

137

uint8_t variant : 4; /* HW variant */

drivers/gpu/drm/amd/include/discovery.h

139

uint8_t variant : 4; /* HW variant */

drivers/gpu/drm/amd/include/discovery.h

140

uint8_t sub_revision : 4; /* HCID Sub-Revision */

drivers/gpu/drm/amd/include/discovery.h

362

uint8_t number_instance; /* Instance of the IP */

drivers/gpu/drm/amd/include/discovery.h

363

uint8_t reserved; /* Reserved for alignment */

drivers/gpu/drm/amd/include/discovery.h

85

uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */

drivers/gpu/drm/amd/include/discovery.h

86

uint8_t reserved : 7;

drivers/gpu/drm/amd/include/discovery.h

87

uint8_t reserved2;

drivers/gpu/drm/amd/include/discovery.h

95

uint8_t number_instance; /* instance of the IP */

drivers/gpu/drm/amd/include/discovery.h

96

uint8_t num_base_address; /* Number of Base Addresses */

drivers/gpu/drm/amd/include/discovery.h

97

uint8_t major; /* HCID Major */

drivers/gpu/drm/amd/include/discovery.h

98

uint8_t minor; /* HCID Minor */

drivers/gpu/drm/amd/include/discovery.h

99

uint8_t revision; /* HCID Revision */

drivers/gpu/drm/amd/include/dm_pp_interface.h

54

uint8_t primary_transmitter_phyi_d;

drivers/gpu/drm/amd/include/dm_pp_interface.h

56

uint8_t primary_transmitter_active_lanemap;

drivers/gpu/drm/amd/include/dm_pp_interface.h

58

uint8_t secondary_transmitter_phy_id;

drivers/gpu/drm/amd/include/dm_pp_interface.h

60

uint8_t secondary_transmitter_active_lanemap;

drivers/gpu/drm/amd/include/kgd_kfd_interface.h

271

uint8_t vmid,

drivers/gpu/drm/amd/include/kgd_kfd_interface.h

302

uint8_t wave_launch_mode,

drivers/gpu/drm/amd/include/kgd_pp_interface.h

1727

uint8_t data[];

drivers/gpu/drm/amd/include/kgd_pp_interface.h

534

uint8_t format_revision;

drivers/gpu/drm/amd/include/kgd_pp_interface.h

535

uint8_t content_revision;

drivers/gpu/drm/amd/include/kgd_pp_interface.h

694

uint8_t pcie_link_width;

drivers/gpu/drm/amd/include/kgd_pp_interface.h

695

uint8_t pcie_link_speed; // in 0.1 GT/s

drivers/gpu/drm/amd/include/mes_v12_api_def.h

936

uint8_t inv_sel;

drivers/gpu/drm/amd/include/mes_v12_api_def.h

937

uint8_t flush_type;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1522

(uint8_t *)&pi->uvd_boot_level,

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

100

#define PPSMC_MSG_EnterULV ((uint8_t)0x64)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

101

#define PPSMC_MSG_ExitULV ((uint8_t)0x65)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

102

#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

103

#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

104

#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

105

#define PPSMC_FlushDataCache ((uint8_t)0x80)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

106

#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

107

#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

108

#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

109

#define PPSMC_MSG_EnableDTE ((uint8_t)0x87)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

110

#define PPSMC_MSG_DisableDTE ((uint8_t)0x88)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

111

#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

112

#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

67

#define PPSMC_Result_OK ((uint8_t)0x01)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

68

#define PPSMC_Result_Failed ((uint8_t)0xFF)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

70

typedef uint8_t PPSMC_Result;

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

72

#define PPSMC_MSG_Halt ((uint8_t)0x10)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

73

#define PPSMC_MSG_Resume ((uint8_t)0x11)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

74

#define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

75

#define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

76

#define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

77

#define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

78

#define PPSMC_MSG_RunningOnAC ((uint8_t)0x17)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

79

#define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

80

#define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

81

#define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

82

#define PPSMC_MSG_ForceHigh ((uint8_t)0x42)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

83

#define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

84

#define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

85

#define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

86

#define PPSMC_MSG_EnableCac ((uint8_t)0x53)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

87

#define PPSMC_MSG_DisableCac ((uint8_t)0x54)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

88

#define PPSMC_TDPClampingActive ((uint8_t)0x59)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

89

#define PPSMC_TDPClampingInactive ((uint8_t)0x5A)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

90

#define PPSMC_StartFanControl ((uint8_t)0x5B)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

91

#define PPSMC_StopFanControl ((uint8_t)0x5C)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

92

#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

93

#define PPSMC_NoDisplay ((uint8_t)0x5D)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

94

#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

95

#define PPSMC_HasDisplay ((uint8_t)0x5E)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

96

#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

97

#define PPSMC_MSG_UVDPowerON ((uint8_t)0x61)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

98

#define PPSMC_MSG_EnableULV ((uint8_t)0x62)

drivers/gpu/drm/amd/pm/legacy-dpm/ppsmc.h

99

#define PPSMC_MSG_DisableULV ((uint8_t)0x63)

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6582

fan_table.temp_src = (uint8_t)tmp;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

127

uint8_t index;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

128

uint8_t phase_settings;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

134

uint8_t ACIndex;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

135

uint8_t displayWatermark;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

136

uint8_t gen2PCIE;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

137

uint8_t UVDWatermark;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

138

uint8_t VCEWatermark;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

139

uint8_t strobeMode;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

140

uint8_t mcFlags;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

141

uint8_t padding;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

150

uint8_t hysteresisUp;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

151

uint8_t hysteresisDown;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

152

uint8_t stateFlags;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

153

uint8_t arbRefreshState;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

175

uint8_t flags;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

176

uint8_t levelCount;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

177

uint8_t padding2;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

178

uint8_t padding3;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

185

uint8_t flags;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

186

uint8_t levelCount;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

187

uint8_t padding2;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

188

uint8_t padding3;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

207

uint8_t thermalProtectType;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

208

uint8_t systemFlags;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

209

uint8_t maxVDDCIndexInPPTable;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

210

uint8_t extraFlags;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

246

uint8_t fdo_mode;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

247

uint8_t padding;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

263

uint8_t temp_src;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

284

uint8_t lts_truncate_n;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

285

uint8_t SHIFT_N;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

286

uint8_t log2_PG_LKG_SCALE;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

287

uint8_t cac_temp;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

311

uint8_t last;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

312

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

322

uint8_t mc_arb_rfsh_rate;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

323

uint8_t mc_arb_burst_time;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

324

uint8_t padding[2];

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

33

uint8_t MaxPS;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

330

uint8_t arb_current;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

331

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

34

uint8_t TgtAct;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

35

uint8_t MaxPS_StepInc;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

36

uint8_t MaxPS_StepDec;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

363

uint8_t WindowSize;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

364

uint8_t Tdep_count;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

365

uint8_t temp_select;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

366

uint8_t DTE_mode;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

367

uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

37

uint8_t PSSamplingTime;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

38

uint8_t NearTDPDec;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

39

uint8_t AboveSafeInc;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

40

uint8_t BelowSafeInc;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

41

uint8_t PSDeltaLimit;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

42

uint8_t PSDeltaWin;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

44

uint8_t Reserved[4];

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

51

uint8_t CurrPSkip;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

52

uint8_t CurrPSkipPowerShift;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

53

uint8_t CurrPSkipTDP;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

54

uint8_t CurrPSkipOCP;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

55

uint8_t MaxSPLLIndex;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

56

uint8_t MinSPLLIndex;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

57

uint8_t CurrSPLLIndex;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

58

uint8_t InfSweepMode;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

59

uint8_t InfSweepDir;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

60

uint8_t TDPexceeded;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

61

uint8_t reserved;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

62

uint8_t SwitchDownThreshold;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

83

uint8_t dGPU_T_Limit_Exceeded;

drivers/gpu/drm/amd/pm/legacy-dpm/sislands_smc.h

84

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

111

uint8_t vrhot_triggered_sclk_dpm_index; /* SCLK DPM level index to switch to when VRHot is triggered */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

33

uint8_t vddInd;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

34

uint8_t vddciInd;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

35

uint8_t mvddInd;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

41

uint8_t phases;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

42

uint8_t cks_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

43

uint8_t cks_voffset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

64

uint8_t vddcInd;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

68

uint8_t phases;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

96

uint8_t gen_speed;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

97

uint8_t lane_width;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1020

int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

105

uint8_t i = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

106

uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize))

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1078

int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1079

uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

125

((uint8_t *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

134

uint8_t module_index,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

161

((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset));

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

175

uint8_t module_index,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

202

((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset));

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

265

uint8_t voltage_type, uint8_t voltage_mode)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

269

uint8_t *start = (uint8_t *)voltage_object_info_table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

304

mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

47

uint8_t index,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

52

uint8_t tmem_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

54

((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize));

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

556

uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

557

uint8_t voltage_mode)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

56

uint8_t num_ranges = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

574

uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

575

uint8_t voltage_mode,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

60

tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

623

uint8_t *start = (uint8_t *)gpio_lookup_table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

699

uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

839

const uint8_t clockSource,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

84

((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

856

while (((uint8_t *)ssInfo - (uint8_t *)table) <

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

864

ssInfo = (ATOM_ASIC_SS_ASSIGNMENT *)((uint8_t *)ssInfo +

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

936

efuse_param.sEfuse.ucBitShift = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

938

efuse_param.sEfuse.ucBitLength = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

950

uint8_t level)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

969

int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

168

uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

169

uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

176

uint8_t memory_vendor;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

177

uint8_t memory_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

184

uint8_t num_entries;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

185

uint8_t rsv[3];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

218

uint8_t uc_pre_reg_data;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

226

uint8_t ucVco_setting;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

227

uint8_t ucPostdiv;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

239

uint8_t last; /* number of registers */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

240

uint8_t num_entries; /* number of AC timing entries */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

248

uint8_t uc_gpio_pin_bit_shift;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

272

uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

273

uint8_t ucEnableGB_VDROOP_TABLE_CKSON;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

274

uint8_t ucEnableGB_FUSE_TABLE_CKSOFF;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

275

uint8_t ucEnableGB_FUSE_TABLE_CKSON;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

277

uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

278

uint8_t ucReserved;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

294

extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

301

extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

302

extern int atomctrl_initialize_mc_reg_table_v2_2(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

308

extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

309

extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

321

uint8_t level);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

322

extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

328

extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

329

uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

348

extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

79

uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

80

uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

81

uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

89

uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

90

uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

91

uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

202

uint8_t format_revision, content_revision;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

31

uint8_t voltage_type, uint8_t voltage_mode)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

414

uint8_t clk_id, uint8_t syspll_id,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

77

uint8_t voltage_type, uint8_t voltage_mode)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

96

uint8_t voltage_type, uint8_t voltage_mode,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

123

uint8_t ucAcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

124

uint8_t ucAcDcPolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

125

uint8_t ucVR0HotGpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

126

uint8_t ucVR0HotPolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

127

uint8_t ucVR1HotGpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

128

uint8_t ucVR1HotPolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

129

uint8_t ucFwCtfGpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

130

uint8_t ucFwCtfPolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

147

uint8_t ucCoolingID;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

151

uint8_t liquid1_i2c_address;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

152

uint8_t liquid2_i2c_address;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

153

uint8_t vr_i2c_address;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

154

uint8_t plx_i2c_address;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

155

uint8_t liquid_i2c_linescl;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

156

uint8_t liquid_i2c_linesda;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

157

uint8_t vr_i2c_linescl;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

158

uint8_t vr_i2c_linesda;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

159

uint8_t plx_i2c_linescl;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

160

uint8_t plx_i2c_linesda;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

161

uint8_t vrsensorpresent;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

162

uint8_t liquidsensorpresent;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

165

uint8_t vddgfxvrmapping;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

166

uint8_t vddsocvrmapping;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

167

uint8_t vddmem0vrmapping;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

168

uint8_t vddmem1vrmapping;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

169

uint8_t gfxulvphasesheddingmask;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

170

uint8_t soculvphasesheddingmask;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

173

uint8_t gfxoffset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

174

uint8_t padding_telemetrygfx;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

176

uint8_t socoffset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

177

uint8_t padding_telemetrysoc;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

179

uint8_t mem0offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

180

uint8_t padding_telemetrymem0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

182

uint8_t mem1offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

183

uint8_t padding_telemetrymem1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

185

uint8_t acdcgpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

186

uint8_t acdcpolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

187

uint8_t vr0hotgpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

188

uint8_t vr0hotpolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

189

uint8_t vr1hotgpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

190

uint8_t vr1hotpolarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

191

uint8_t padding1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

192

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

194

uint8_t ledpin0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

195

uint8_t ledpin1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

196

uint8_t ledpin2;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

198

uint8_t pllgfxclkspreadenabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

199

uint8_t pllgfxclkspreadpercent;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

202

uint8_t uclkspreadenabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

203

uint8_t uclkspreadpercent;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

206

uint8_t socclkspreadenabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

207

uint8_t socclkspreadpercent;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

210

uint8_t acggfxclkspreadenabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

211

uint8_t acggfxclkspreadpercent;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

214

uint8_t Vr2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

221

int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

222

uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

224

uint8_t voltage_type, uint8_t voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

236

uint8_t clk_id, uint8_t syspll_id,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

47

uint8_t psi0_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

48

uint8_t psi1_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

49

uint8_t max_vid_step;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

50

uint8_t telemetry_offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

51

uint8_t telemetry_slope;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

57

uint8_t uc_gpio_pin_bit_shift;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

66

uint8_t ucPll_ss_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

67

uint8_t ucReserve;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

96

uint8_t ucEnableGbVdroopTableCkson;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

97

uint8_t ucEnableGbFuseTableCkson;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/pppcielanes.c

56

uint8_t encode_pcie_lane_width(uint32_t num_lanes)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/pppcielanes.c

61

uint8_t decode_pcie_lane_width(uint32_t num_lanes)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/pppcielanes.h

27

extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/pppcielanes.h

28

extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

1167

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

125

table_size = sizeof(uint8_t) + ptable->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

677

uint8_t version,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

711

static const uint8_t look_up[(ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK >> ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT) + 1] = \

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

826

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

96

table_size = sizeof(uint8_t) + p->ucNumEntries * sizeof(VCEClockInfo);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1383

table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1386

table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1389

smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1462

static const uint8_t

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

501

result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

139

uint8_t dpm0_pg_nbps_low;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

140

uint8_t dpm0_pg_nbps_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

141

uint8_t dpm_x_nbps_low;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

142

uint8_t dpm_x_nbps_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

155

uint8_t phy_present;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

156

uint8_t active_lane_mapping;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

157

uint8_t display_config_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

158

uint8_t active_num_of_lanes;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

171

uint8_t htc_tmp_lmt;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

172

uint8_t htc_hyst_lmt;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

232

uint8_t disp_config;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

249

uint8_t uvd_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

250

uint8_t vce_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

251

uint8_t acp_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

252

uint8_t samu_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

77

uint8_t vddc_index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

78

uint8_t ds_divider_index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

79

uint8_t ss_divider_index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

80

uint8_t allow_gnb_slow;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

81

uint8_t force_nbp_state;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

82

uint8_t display_wm;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

83

uint8_t vce_wm;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

84

uint8_t num_simd_to_powerdown;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

85

uint8_t hysteresis_up;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

86

uint8_t rsv[3];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1807

uint8_t tmp1, tmp2;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2201

uint8_t entry_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2202

uint8_t voltage_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2283

uint8_t entry_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2325

uint8_t entry_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2527

dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3538

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4416

uint8_t request;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5392

(uint8_t *)table->DisplayWatermark,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5393

sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5829

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5832

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

193

uint8_t bupdate_sclk;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

194

uint8_t sclk_up_hyst;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

195

uint8_t sclk_down_hyst;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

197

uint8_t bupdate_mclk;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

198

uint8_t mclk_up_hyst;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

199

uint8_t mclk_down_hyst;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

273

uint8_t mvdd_high_index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

274

uint8_t mvdd_low_index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

299

uint8_t vddc_phase_shed_control;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

385

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1396

uint8_t clock_info_index = smu8_clock_info->index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1398

if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1399

clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1402

smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

314

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

420

(uint8_t)data->sys_info.bootup_nb_voltage_index;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

479

(i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

488

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

492

(i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

496

(i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

505

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

510

(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

519

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

522

(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

531

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

535

(i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

545

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

101

uint8_t vddcIndex;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

102

uint8_t dsDividerIndex;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

103

uint8_t ssDividerIndex;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

104

uint8_t allowGnbSlow;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

105

uint8_t forceNBPstate;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

106

uint8_t display_wm;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

107

uint8_t vce_wm;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

108

uint8_t numSIMDToPowerDown;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

109

uint8_t hysteresis_up;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

110

uint8_t rsv[3];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

154

uint8_t dpm_0_pg_nb_ps_low;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

155

uint8_t dpm_0_pg_nb_ps_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

156

uint8_t dpm_x_nb_ps_low;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

157

uint8_t dpm_x_nb_ps_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

248

uint8_t disp_config;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

261

uint8_t uvd_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

262

uint8_t vce_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

264

uint8_t acp_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

265

uint8_t samu_level_count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

275

uint8_t uvd_boot_level;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

276

uint8_t vce_boot_level;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

277

uint8_t acp_boot_level;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

278

uint8_t samu_boot_level;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

279

uint8_t uvd_interval;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

280

uint8_t vce_interval;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

281

uint8_t acp_interval;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

282

uint8_t samu_interval;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

284

uint8_t graphics_interval;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

285

uint8_t graphics_therm_throttle_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

286

uint8_t graphics_voltage_change_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

288

uint8_t graphics_clk_slow_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

289

uint8_t graphics_clk_slow_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

61

uint8_t htc_tmp_lmt;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

62

uint8_t htc_hyst_lmt;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

86

uint8_t phy_present;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

87

uint8_t active_lane_mapping;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

88

uint8_t display_config_type;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

89

uint8_t active_number_of_lanes;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

36

uint8_t convert_to_vid(uint16_t vddc)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

38

return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

388

uint8_t phm_get_voltage_index(

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

391

uint8_t count = (uint8_t) (lookup_table->count);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

392

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

408

uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

41

uint16_t convert_to_vddc(uint8_t vid)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

411

uint8_t count = (uint8_t) (voltage_table->count);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

412

uint8_t i = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

463

uint8_t entry_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

464

uint8_t voltage_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

580

int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

673

uint8_t *frev, uint8_t *crev)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

681

return (uint8_t *)adev->mode_info.atom_context->bios +

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

691

uint8_t i = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

742

table->WatermarkRow[1][i].WmSetting = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

763

table->WatermarkRow[0][i].WmSetting = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c

96

if (size == sizeof(uint8_t))

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

128

uint8_t *frev, uint8_t *crev);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

32

uint8_t convert_to_vid(uint16_t vddc);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

33

uint16_t convert_to_vddc(uint8_t vid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

41

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

42

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

83

extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

85

extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h

94

extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1280

pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1283

pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1483

(uint8_t)table_info->us_ulv_voltage_offset;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1486

(uint8_t)(table_info->us_ulv_smnclk_did);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1488

(uint8_t)(table_info->us_ulv_mp1clk_did);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1490

(uint8_t)(table_info->us_ulv_gfxclk_bypass);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1492

(uint8_t)(data->vddc_voltage_table.psi0_enable);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1494

(uint8_t)(data->vddc_voltage_table.psi1_enable);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1500

uint32_t lclock, uint8_t *curr_lclk_did)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1662

current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1680

uint32_t soc_clock, uint8_t *current_soc_did,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1681

uint8_t *current_vol_index)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1715

*current_soc_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1716

*current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1790

uint8_t soc_vid = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1800

soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1817

uint32_t mem_clock, uint8_t *current_mem_vid,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1818

PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1857

(uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1859

(uint8_t)(dep_on_mclk->entries[i].vddInd);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1861

current_memclk_level->Did = (uint8_t)(dividers.ulDid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1914

(uint8_t)(data->lowest_uclk_reserved_for_ulv);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1930

uint8_t vid = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1957

vid = (uint8_t)convert_to_vid(vddc);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1989

uint32_t eclock, uint8_t *current_eclk_did,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1990

uint8_t *current_soc_vol)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2005

*current_eclk_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2047

uint32_t vclock, uint8_t *current_vclk_did)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2057

*current_vclk_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2063

uint32_t dclock, uint8_t *current_dclk_did)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2073

*current_dclk_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2161

pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2180

pp_table->MinVoltageVid = (uint8_t)0xff;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2181

pp_table->MaxVoltageVid = (uint8_t)0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2186

pp_table->MinVoltageVid = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2188

pp_table->MaxVoltageVid = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2244

convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2517

result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2599

(uint8_t)(table_info->uc_gfx_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2601

(uint8_t)(table_info->uc_soc_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2603

(uint8_t)(table_info->uc_uclk_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2605

(uint8_t)(table_info->uc_uvd_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2607

(uint8_t)(table_info->uc_vce_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2609

(uint8_t)(table_info->uc_mp0_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2612

(uint8_t)(table_info->uc_dcef_dpm_voltage_mode);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2709

pp_table->GfxclkAverageAlpha = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2711

pp_table->SocclkAverageAlpha = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2713

pp_table->UclkAverageAlpha = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2715

pp_table->GfxActivityAverageAlpha = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2720

result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3861

result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4012

*((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4075

static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4079

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4080

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4085

count = (uint8_t)(mclk_table->count);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4835

result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5184

static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5229

uint8_t busy_set_point;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5230

uint8_t FPS;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5231

uint8_t use_rlc_busy;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5232

uint8_t min_active_level;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

528

uint8_t entry_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

529

uint8_t voltage_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5392

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

670

uint8_t entry_id, voltage_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

968

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

988

pp_table->LedPin0 = (uint8_t)(mask & 0xff);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

989

pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

990

pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

141

uint8_t pcie_gen[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

142

uint8_t pcie_lane[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

203

uint8_t vr_hot_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

204

uint8_t ac_dc_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

205

uint8_t therm_out_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

206

uint8_t therm_out_polarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

207

uint8_t therm_out_mode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

225

uint8_t ac_dc_switch_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

226

uint8_t avfs_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

227

uint8_t cac_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

228

uint8_t clock_stretcher_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

229

uint8_t db_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

230

uint8_t didt_mode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

231

uint8_t didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

232

uint8_t edc_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

233

uint8_t dynamic_state_patching_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

234

uint8_t enable_pkg_pwr_tracking_feature;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

235

uint8_t enable_tdc_limit_feature;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

237

uint8_t force_dpm_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

238

uint8_t fuzzy_fan_control_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

239

uint8_t long_idle_baco_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

240

uint8_t mclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

241

uint8_t od_state_in_dc_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

242

uint8_t pcieLaneOverride;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

243

uint8_t pcieSpeedOverride;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

245

uint8_t pcie_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

246

uint8_t dcefclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

247

uint8_t power_containment_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

248

uint8_t ppt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

249

uint8_t prefetcher_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

250

uint8_t quick_transition_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

251

uint8_t regulator_hot_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

252

uint8_t sclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

253

uint8_t sclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

254

uint8_t sclk_from_vbios;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

255

uint8_t sclk_throttle_low_notification;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

256

uint8_t show_baco_dbg_info;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

257

uint8_t skip_baco_hardware;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

258

uint8_t socclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

259

uint8_t spll_shutdown_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

260

uint8_t sq_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

262

uint8_t tcp_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

263

uint8_t tdc_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

264

uint8_t td_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

265

uint8_t dbr_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

266

uint8_t gc_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

267

uint8_t psm_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

268

uint8_t thermal_out_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

269

uint8_t thermal_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

270

uint8_t fw_ctf_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

271

uint8_t fan_control_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

272

uint8_t ulps_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

273

uint8_t ulv_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

275

uint8_t odn_feature_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

276

uint8_t disable_water_mark;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

277

uint8_t zrpm_stop_temp;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

278

uint8_t zrpm_start_temp;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

279

uint8_t led_dpm_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

280

uint8_t vr0hot_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

281

uint8_t vr1hot_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

334

uint8_t need_update_dpm_table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

386

uint8_t custom_profile_mode[4];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

61

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

62

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

63

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

64

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

65

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

66

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

375

static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

424

uint8_t scl;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

425

uint8_t sda;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

731

uint8_t num_entries;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

555

(uint8_t *)(&(data->smc_state_table.pp_table)),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

580

(uint8_t *)(&(data->smc_state_table.pp_table)),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1397

(uint8_t *)(&data->metrics_table),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2586

(uint8_t *)wm_table, TABLE_WATERMARKS, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

852

(uint8_t *)pp_table, TABLE_PPTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

119

uint8_t pcie_gen[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

120

uint8_t pcie_lane[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

160

uint8_t uc_cooling_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

189

uint8_t vr_hot_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

190

uint8_t ac_dc_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

191

uint8_t therm_out_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

192

uint8_t therm_out_polarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

193

uint8_t therm_out_mode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

216

uint8_t ac_dc_switch_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

217

uint8_t acg_loop_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

218

uint8_t clock_stretcher_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

219

uint8_t db_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

220

uint8_t didt_mode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

221

uint8_t didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

222

uint8_t edc_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

223

uint8_t force_dpm_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

224

uint8_t fuzzy_fan_control_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

225

uint8_t mclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

226

uint8_t od_state_in_dc_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

227

uint8_t pcie_lane_override;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

228

uint8_t pcie_speed_override;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

230

uint8_t pcie_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

231

uint8_t dcefclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

232

uint8_t prefetcher_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

233

uint8_t quick_transition_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

234

uint8_t regulator_hot_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

235

uint8_t master_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

236

uint8_t gfx_clk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

237

uint8_t sclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

238

uint8_t lclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

239

uint8_t dce_fclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

240

uint8_t sclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

241

uint8_t sclk_throttle_low_notification;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

242

uint8_t skip_baco_hardware;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

243

uint8_t socclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

244

uint8_t sq_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

245

uint8_t tcp_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

246

uint8_t td_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

247

uint8_t dbr_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

248

uint8_t gc_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

249

uint8_t psm_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

250

uint8_t thermal_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

251

uint8_t fw_ctf_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

252

uint8_t led_dpm_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

253

uint8_t fan_control_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

254

uint8_t ulv_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

255

uint8_t odn_feature_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

256

uint8_t disable_water_mark;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

257

uint8_t disable_workload_policy;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

259

uint8_t disable_3d_fs_detection;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

260

uint8_t disable_pp_tuning;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

261

uint8_t disable_xlpp_tuning;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

268

uint8_t fps_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

269

uint8_t vr0hot;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

270

uint8_t vr1hot;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

271

uint8_t disable_auto_wattman;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

274

uint8_t auto_wattman_threshold;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

275

uint8_t log_avfs_param;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

276

uint8_t enable_enginess;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

277

uint8_t custom_fan_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

278

uint8_t disable_pcc_limit_control;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

335

uint8_t need_update_dpm_table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1264

ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1392

ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1411

ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1468

ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2127

(uint8_t *)(&data->metrics_table),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2284

(uint32_t)convert_to_vddc((uint8_t)val_vid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3139

(uint8_t *)od_table,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3148

(uint8_t *)od_table,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3714

(uint8_t *)wm_table, TABLE_WATERMARKS, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4076

(uint8_t *)(&activity_monitor), workload_type);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4166

(uint8_t *)(&activity_monitor),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4229

(uint8_t *)(&activity_monitor),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

826

(uint8_t *)pp_table, TABLE_PPTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

172

uint8_t pcie_gen[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

173

uint8_t pcie_lane[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

213

uint8_t uc_cooling_id;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

250

uint8_t vr_hot_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

251

uint8_t ac_dc_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

252

uint8_t therm_out_gpio;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

253

uint8_t therm_out_polarity;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

254

uint8_t therm_out_mode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

277

uint8_t ac_dc_switch_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

278

uint8_t acg_loop_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

279

uint8_t clock_stretcher_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

280

uint8_t db_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

281

uint8_t didt_mode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

282

uint8_t didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

283

uint8_t edc_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

284

uint8_t force_dpm_high;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

285

uint8_t fuzzy_fan_control_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

286

uint8_t mclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

287

uint8_t od_state_in_dc_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

288

uint8_t pcie_lane_override;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

289

uint8_t pcie_speed_override;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

291

uint8_t pcie_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

292

uint8_t dcefclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

293

uint8_t prefetcher_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

294

uint8_t quick_transition_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

295

uint8_t regulator_hot_gpio_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

296

uint8_t master_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

297

uint8_t gfx_clk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

298

uint8_t sclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

299

uint8_t lclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

300

uint8_t dce_fclk_deep_sleep_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

301

uint8_t sclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

302

uint8_t sclk_throttle_low_notification;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

303

uint8_t skip_baco_hardware;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

304

uint8_t socclk_dpm_key_disabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

305

uint8_t sq_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

306

uint8_t tcp_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

307

uint8_t td_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

308

uint8_t dbr_ramping_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

309

uint8_t gc_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

310

uint8_t psm_didt_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

311

uint8_t thermal_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

312

uint8_t fw_ctf_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

313

uint8_t led_dpm_enabled;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

314

uint8_t fan_control_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

315

uint8_t ulv_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

316

uint8_t od8_feature_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

317

uint8_t disable_water_mark;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

318

uint8_t disable_workload_policy;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

320

uint8_t disable_3d_fs_detection;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

321

uint8_t disable_pp_tuning;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

322

uint8_t disable_xlpp_tuning;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

329

uint8_t fps_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

330

uint8_t vr0hot;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

331

uint8_t vr1hot;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

332

uint8_t disable_auto_wattman;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

336

uint8_t auto_wattman_threshold;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

337

uint8_t log_avfs_param;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

338

uint8_t enable_enginess;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

339

uint8_t custom_fan_support;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

340

uint8_t disable_pcc_limit_control;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

341

uint8_t gfxoff_controlled_by_driver;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

456

uint8_t need_update_dpm_table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

113

uint8_t **pptable_info_array,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

114

const uint8_t *pptable_array,

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

115

uint8_t od_feature_count)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

118

uint8_t *table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

121

array_size = sizeof(uint8_t) * od_feature_count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

142

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

168

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

173

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

178

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

188

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

230

int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

405

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

434

uint8_t ucLiquid1_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

435

uint8_t ucLiquid2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

436

uint8_t ucLiquid_I2C_Line;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

437

uint8_t ucVr_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

438

uint8_t ucVr_I2C_Line;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

439

uint8_t ucPlx_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

440

uint8_t ucPlx_I2C_Line;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

442

uint8_t ucCKS_LDO_REFSEL;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

443

uint8_t ucHotSpotOnly;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

473

uint8_t ucLiquid1_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

474

uint8_t ucLiquid2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

475

uint8_t ucLiquid_I2C_Line;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

476

uint8_t ucVr_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

477

uint8_t ucVr_I2C_Line;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

478

uint8_t ucPlx_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

479

uint8_t ucPlx_I2C_Line;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

480

uint8_t ucLiquid_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

481

uint8_t ucVr_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

482

uint8_t ucPlx_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

490

uint8_t ppm_design;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

508

uint8_t ucDispConfig;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

516

uint8_t numEntries;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

599

uint8_t uc_gfx_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

600

uint8_t uc_soc_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

601

uint8_t uc_uclk_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

602

uint8_t uc_uvd_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

603

uint8_t uc_vce_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

604

uint8_t uc_mp0_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

605

uint8_t uc_dcef_dpm_voltage_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

609

uint8_t uc_thermal_controller_type;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

622

uint8_t *od_feature_capabilities;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

662

uint8_t ucTachometerPulsesPerRevolution;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

674

uint8_t ucTHyst; /* Temperature hysteresis. Integer. */

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

677

uint8_t ucFanControlMode;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

695

uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

696

uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

704

uint8_t ucEnableZeroRPM;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

705

uint8_t ucFanStopTemperature;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

706

uint8_t ucFanStartTemperature;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

715

uint8_t ucType;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

716

uint8_t ucI2cLine;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

717

uint8_t ucI2cAddress;

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

718

uint8_t use_hw_fan_control;

drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h

110

uint8_t m3arb;

drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h

111

uint8_t unused[3];

drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h

140

uint8_t supportedPowerLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

56

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

57

uint8_t WmType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

58

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

85

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

86

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

87

uint8_t FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/smu10_driver_if.h

88

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

353

uint8_t VoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

354

uint8_t SnapToDiscrete;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

355

uint8_t NumDiscreteLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

356

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

397

uint8_t MemoryOnPackage;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

398

uint8_t padding8_limits;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

404

uint8_t UlvSmnclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

405

uint8_t UlvMp1clkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

406

uint8_t UlvGfxclkBypass;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

407

uint8_t Padding234;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

444

uint8_t Padding567[4];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

446

uint8_t GfxclkSource;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

447

uint8_t Padding456;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

449

uint8_t LowestUclkReservedForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

450

uint8_t Padding8_Uclk[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

453

uint8_t PcieGenSpeed[NUM_LINK_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

454

uint8_t PcieLaneCount[NUM_LINK_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

480

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

481

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

491

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

492

uint8_t Padding8_Avfs[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

505

uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

506

uint8_t Padding8_GfxBtc[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

512

uint8_t XgmiLinkSpeed [NUM_XGMI_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

513

uint8_t XgmiLinkWidth [NUM_XGMI_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

543

uint8_t VddGfxVrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

544

uint8_t VddSocVrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

545

uint8_t VddMem0VrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

546

uint8_t VddMem1VrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

548

uint8_t GfxUlvPhaseSheddingMask;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

549

uint8_t SocUlvPhaseSheddingMask;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

550

uint8_t ExternalSensorPresent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

551

uint8_t Padding8_V;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

556

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

560

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

564

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

568

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

571

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

572

uint8_t AcDcPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

573

uint8_t VR0HotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

574

uint8_t VR0HotPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

576

uint8_t VR1HotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

577

uint8_t VR1HotPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

578

uint8_t Padding1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

579

uint8_t Padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

583

uint8_t LedPin0;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

584

uint8_t LedPin1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

585

uint8_t LedPin2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

586

uint8_t padding8_4;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

589

uint8_t PllGfxclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

590

uint8_t PllGfxclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

593

uint8_t UclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

594

uint8_t UclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

597

uint8_t FclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

598

uint8_t FclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

601

uint8_t FllGfxclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

602

uint8_t FllGfxclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

656

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

657

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

658

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

659

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

672

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

674

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

686

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

687

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

721

uint8_t AvfsVersion;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

722

uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

724

uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

725

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

727

uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

728

uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

729

uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

730

uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

772

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

773

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

774

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

775

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

776

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

777

uint8_t Gfx_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

787

uint8_t Soc_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

788

uint8_t Soc_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

789

uint8_t Soc_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

790

uint8_t Soc_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

791

uint8_t Soc_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

792

uint8_t Soc_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

802

uint8_t Mem_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

803

uint8_t Mem_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

804

uint8_t Mem_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

805

uint8_t Mem_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

806

uint8_t Mem_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

807

uint8_t Mem_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

817

uint8_t Fclk_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

818

uint8_t Fclk_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

819

uint8_t Fclk_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

820

uint8_t Fclk_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

821

uint8_t Fclk_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h

822

uint8_t Fclk_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

148

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

149

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

150

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

151

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

155

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

156

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

158

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

159

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

160

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

161

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

163

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

164

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

165

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

166

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

170

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

171

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

172

uint8_t GfxClkSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

173

uint8_t GpioClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

175

uint8_t FpsFilterWeight;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

176

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

177

uint8_t DteClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

178

uint8_t FpsClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

183

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

184

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

189

uint8_t FpsEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

190

uint8_t MaxPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

191

uint8_t AllowLowClkInterruptToHost;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

192

uint8_t FpsRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

205

uint8_t HighestVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

206

uint8_t CurrentVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

208

uint8_t CurrentPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

209

uint8_t HighestPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

211

uint8_t AvsOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

212

uint8_t AvsOffsetApplied;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

214

uint8_t ControllerBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

215

uint8_t CurrentVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

218

uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

220

uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

221

uint8_t TargetIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

222

uint8_t Delay;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

223

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

224

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

231

uint8_t CurrentVddciVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

232

uint8_t TargetVddciIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

243

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

244

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

245

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

246

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

248

uint8_t CurrentLinkSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

249

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

255

uint8_t DpmMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

256

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

257

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

258

uint8_t CurrentLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

315

uint8_t CalculationRepeats;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

316

uint8_t WaterfallUp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

317

uint8_t WaterfallDown;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

318

uint8_t WaterfallLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

330

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

331

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

332

uint8_t WaterfallUp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

333

uint8_t WaterfallDown;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

334

uint8_t WaterfallLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

335

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

376

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

377

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

378

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

379

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

381

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

382

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

383

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

384

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

390

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

391

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

392

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

393

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

403

uint8_t DPMFreezeAndForced;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

404

uint8_t Activity_Weight;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

405

uint8_t Reserved8[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

446

uint8_t waterfall_up;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

447

uint8_t waterfall_down;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

448

uint8_t pstate;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

449

uint8_t clamp_mode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

483

uint8_t BlockId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

484

uint8_t SignalId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

485

uint8_t Threshold;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71.h

486

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

103

uint8_t VddcOffsetVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

104

uint8_t VddcPhase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

119

uint8_t EdcReadEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

120

uint8_t EdcWriteEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

121

uint8_t RttEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

122

uint8_t StutterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

124

uint8_t StrobeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

125

uint8_t StrobeRatio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

126

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

127

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

129

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

130

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

131

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

132

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

135

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

136

uint8_t padding1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

153

uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

154

uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

155

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

156

uint8_t SPC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

171

uint8_t McArbBurstTime;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

172

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

191

uint8_t MinVddcPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

192

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

193

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

194

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

204

uint8_t MinPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

205

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

225

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

226

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

227

uint8_t McRegIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

228

uint8_t SeqIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

229

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

232

uint8_t PCIeGen;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

262

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

263

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

264

uint8_t LinkLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

265

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

279

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

280

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

281

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

282

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

284

uint8_t VoltageInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

285

uint8_t ThermalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

289

uint8_t MemoryBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

290

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

292

uint8_t MemoryInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

293

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

294

uint8_t MergedVddci;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

295

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

300

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

301

uint8_t PCIeGenInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

302

uint8_t DTEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

303

uint8_t DTEMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

305

uint8_t SVI2Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

306

uint8_t VRHotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

307

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

308

uint8_t ThermGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

321

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

322

uint8_t DTETjOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

323

uint8_t GpuTjMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

324

uint8_t GpuTjHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

367

uint8_t last;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

368

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

395

uint8_t TempSrc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

41

uint8_t Smio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

419

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

42

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

420

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

421

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

422

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

426

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

427

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

429

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

430

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

431

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

432

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

434

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

435

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

436

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

437

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

441

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

442

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

443

uint8_t MclkSwitchInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

444

uint8_t MclkSwitchCritical;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

446

uint8_t TargetMclkIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

447

uint8_t TargetMvddIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

448

uint8_t MclkSwitchResult;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

450

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

455

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

456

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

462

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

469

uint8_t EnterUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

470

uint8_t ExitUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

471

uint8_t UlvActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

472

uint8_t WaitingForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

473

uint8_t UlvEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

474

uint8_t UlvRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

475

uint8_t UlvMasterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

476

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

485

uint8_t VddGfxEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

486

uint8_t VddGfxActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

487

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

497

uint8_t LastACPIRequest;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

498

uint8_t CgBifResp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

499

uint8_t RequestType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

500

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

509

uint8_t BapmVddCVidHiSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

512

uint8_t BapmVddCVidLoSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

515

uint8_t VddCVid[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

518

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

519

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

520

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

521

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

525

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

526

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

529

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

530

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

531

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

532

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

535

uint8_t LPMLTemperatureScaler[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

54

uint8_t pcieDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

544

uint8_t GnbLPML[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

547

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

548

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

549

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

55

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

565

uint8_t type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

566

uint8_t mode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

567

uint8_t filler_0[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

574

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

575

uint8_t Type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

576

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

64

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

65

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

66

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

67

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

68

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

69

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

70

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

71

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

82

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

83

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

84

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu71_discrete.h

85

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

197

uint8_t waterfall_up;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

198

uint8_t waterfall_down;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

199

uint8_t waterfall_limit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

200

uint8_t spare;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

234

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

235

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

236

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

237

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

241

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

242

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

244

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

245

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

246

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

247

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

249

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

250

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

251

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

252

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

256

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

257

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

258

uint8_t GfxClkSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

259

uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

261

uint8_t FpsFilterWeight;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

262

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

263

uint8_t DteClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

264

uint8_t FpsClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

269

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

270

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

275

uint8_t FpsEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

276

uint8_t MaxPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

277

uint8_t AllowLowClkInterruptToHost;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

278

uint8_t FpsRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

291

typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

294

uint8_t Vddc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

295

uint8_t Vddci;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

296

uint8_t VddGfx;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

297

uint8_t Phases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

306

uint8_t HighestVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

307

uint8_t CurrentVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

309

uint8_t ControllerBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

310

uint8_t CurrentVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

311

uint8_t CurrentVddciVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

312

uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

315

uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

317

uint8_t TargetIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

318

uint8_t Delay;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

319

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

320

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

323

uint8_t OverrideVoltage;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

324

uint8_t VddcUseUlvOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

325

uint8_t VddGfxUseUlvOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

326

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

336

uint8_t *VddcFollower1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

337

uint8_t *VddcFollower2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

348

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

349

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

350

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

351

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

353

uint8_t CurrentLinkSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

354

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

360

uint8_t DpmMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

361

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

362

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

363

uint8_t CurrentLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

388

uint8_t SidOptionPower;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

389

uint8_t SidOptionCurrent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

421

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

422

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

423

uint8_t AutoTmonCalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

424

uint8_t AutoTmonCalEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

426

uint8_t ThermalDpmEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

427

uint8_t SclkEnabledMask;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

428

uint8_t spare[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

476

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

477

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

478

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

479

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

481

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

482

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

483

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

484

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

490

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

491

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

492

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

493

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

495

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

496

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

497

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

498

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

54

uint8_t a_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

55

uint8_t b_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

56

uint8_t c_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

564

uint8_t BlockId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

565

uint8_t SignalId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

566

uint8_t Threshold;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

567

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

57

uint8_t x_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

659

uint8_t minVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

660

uint8_t maxVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

675

uint8_t setting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

676

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72.h

82

uint8_t index;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

111

uint8_t EdcReadEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

112

uint8_t EdcWriteEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

113

uint8_t RttEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

114

uint8_t StutterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

116

uint8_t StrobeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

117

uint8_t StrobeRatio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

118

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

119

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

121

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

122

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

123

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

124

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

127

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

128

uint8_t padding1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

144

uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

145

uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

146

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

147

uint8_t SPC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

159

uint8_t McArbBurstTime;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

160

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

176

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

177

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

178

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

187

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

188

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

203

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

204

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

205

uint8_t McRegIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

206

uint8_t SeqIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

207

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

210

uint8_t PCIeGen;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

240

uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

241

uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

242

uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

244

uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

245

uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

246

uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

248

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

249

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

250

uint8_t LinkLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

251

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

253

uint8_t UvdLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

254

uint8_t VceLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

255

uint8_t AcpLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

256

uint8_t SamuLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

258

uint8_t ThermOutGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

259

uint8_t ThermOutPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

260

uint8_t ThermOutMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

261

uint8_t DPMFreezeAndForced;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

279

uint8_t UvdBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

280

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

281

uint8_t AcpBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

282

uint8_t SamuBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

284

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

285

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

286

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

287

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

289

uint8_t VoltageInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

290

uint8_t ThermalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

294

uint8_t MemoryBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

295

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

298

uint8_t MemoryInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

299

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

304

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

305

uint8_t PCIeGenInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

306

uint8_t DTEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

307

uint8_t DTEMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

309

uint8_t SVI2Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

310

uint8_t VRHotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

311

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

312

uint8_t ThermGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

326

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

327

uint8_t DTETjOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

328

uint8_t GpuTjMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

329

uint8_t GpuTjHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

338

uint8_t ClockStretcherAmount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

340

uint8_t Sclk_CKS_masterEn0_7;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

341

uint8_t Sclk_CKS_masterEn8_15;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

342

uint8_t padding[1];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

344

uint8_t Sclk_voltageOffset[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

35

uint8_t Smio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

36

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

370

uint8_t last;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

371

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

398

uint8_t TempSrc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

421

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

422

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

423

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

424

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

428

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

429

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

431

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

432

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

433

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

434

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

436

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

437

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

438

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

439

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

443

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

444

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

445

uint8_t MclkSwitchInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

446

uint8_t MclkSwitchCritical;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

448

uint8_t IgnoreVBlank;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

449

uint8_t TargetMclkIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

450

uint8_t TargetMvddIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

451

uint8_t MclkSwitchResult;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

454

uint8_t VbiWaitCounter;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

455

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

460

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

461

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

469

uint8_t fastSwitch;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

470

uint8_t Save_PIC_VDDGFX_EXIT;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

471

uint8_t Save_PIC_VDDGFX_ENTER;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

472

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

479

uint8_t EnterUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

480

uint8_t ExitUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

481

uint8_t UlvActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

482

uint8_t WaitingForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

483

uint8_t UlvEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

484

uint8_t UlvRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

485

uint8_t UlvMasterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

486

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

505

uint8_t VddGfxEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

506

uint8_t VddGfxActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

507

uint8_t VPUResetOccured;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

508

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

52

uint8_t pcieDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

521

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

522

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

53

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

533

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

534

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

559

uint8_t VariantID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

560

uint8_t spare997;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

574

uint8_t LastACPIRequest;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

575

uint8_t CgBifResp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

576

uint8_t RequestType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

577

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

585

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

586

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

587

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

588

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

592

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

593

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

596

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

597

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

598

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

599

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

602

uint8_t LPMLTemperatureScaler[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

611

uint8_t GnbLPML[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

614

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

615

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

616

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

62

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

63

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

632

uint8_t type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

633

uint8_t mode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

634

uint8_t filler_0[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

64

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

641

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

642

uint8_t Type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

643

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

65

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

66

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

67

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

68

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

69

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

78

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

79

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

80

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

81

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

98

uint8_t VddcOffsetVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

99

uint8_t VddcPhase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

226

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

227

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

228

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

229

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

233

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

234

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

236

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

237

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

238

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

239

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

241

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

242

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

243

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

244

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

248

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

249

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

250

uint8_t GfxClkSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

251

uint8_t GpioClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

253

uint8_t spare2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

254

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

255

uint8_t DteClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

256

uint8_t FpsClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

261

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

262

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

267

uint8_t FpsEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

268

uint8_t MaxPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

269

uint8_t AllowLowClkInterruptToHost;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

270

uint8_t FpsRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

278

uint8_t LedEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

279

uint8_t LedPin0;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

280

uint8_t LedPin1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

281

uint8_t LedPin2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

301

typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

315

uint8_t HighestVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

316

uint8_t CurrentVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

322

uint8_t ControllerBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

323

uint8_t CurrentVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

324

uint8_t CurrentVddciVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

325

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

329

uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

331

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

332

uint8_t padding3;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

333

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

334

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

337

uint8_t OverrideVoltage;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

338

uint8_t padding4;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

339

uint8_t padding5;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

340

uint8_t CurrentPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

363

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

364

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

365

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

366

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

368

uint8_t CurrentLinkSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

369

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

375

uint8_t DpmMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

376

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

377

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

378

uint8_t CurrentLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

448

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

449

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

45

uint8_t a_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

450

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

451

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

453

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

454

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

455

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

456

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

46

uint8_t b_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

462

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

463

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

464

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

465

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

467

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

468

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

469

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

47

uint8_t c_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

470

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

48

uint8_t x_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

545

uint8_t BlockId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

546

uint8_t SignalId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

547

uint8_t Threshold;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

548

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

643

uint8_t minVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

644

uint8_t maxVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

660

uint8_t setting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

661

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

704

uint8_t NumTemperatureSteps;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

705

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

73

uint8_t index;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

107

uint8_t StutterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

108

uint8_t FreqRange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

109

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

110

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

112

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

113

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

114

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

115

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

118

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

119

uint8_t MclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

125

uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

126

uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

127

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

128

uint8_t SPC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

141

uint8_t McArbBurstTime;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

142

uint8_t TRRDS;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

143

uint8_t TRRDL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

144

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

160

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

161

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

162

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

171

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

172

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

187

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

188

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

189

uint8_t McRegIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

190

uint8_t SeqIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

191

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

194

uint8_t PCIeGen;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

218

uint8_t BapmVddcVidHiSidd[SMU73_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

219

uint8_t BapmVddcVidLoSidd[SMU73_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

220

uint8_t BapmVddcVidHiSidd2[SMU73_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

222

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

223

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

224

uint8_t LinkLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

225

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

227

uint8_t UvdLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

228

uint8_t VceLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

229

uint8_t AcpLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

230

uint8_t SamuLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

232

uint8_t ThermOutGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

233

uint8_t ThermOutPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

234

uint8_t ThermOutMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

235

uint8_t BootPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

253

uint8_t UvdBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

254

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

255

uint8_t AcpBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

256

uint8_t SamuBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

258

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

259

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

260

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

261

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

263

uint8_t VoltageInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

264

uint8_t ThermalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

268

uint8_t MemoryBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

269

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

272

uint8_t MemoryInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

273

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

278

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

279

uint8_t PCIeGenInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

280

uint8_t DTEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

281

uint8_t DTEMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

283

uint8_t SVI2Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

284

uint8_t VRHotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

285

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

286

uint8_t ThermGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

313

uint8_t Liquid1_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

314

uint8_t Liquid2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

315

uint8_t Vr_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

316

uint8_t Plx_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

318

uint8_t GeminiMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

319

uint8_t spare17[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

32

uint8_t Smio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

323

uint8_t Liquid_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

324

uint8_t Liquid_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

325

uint8_t Vr_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

326

uint8_t Vr_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

327

uint8_t Plx_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

328

uint8_t Plx_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

33

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

330

uint8_t spare1253[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

333

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

334

uint8_t DTETjOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

335

uint8_t GpuTjMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

336

uint8_t GpuTjHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

346

uint8_t ClockStretcherAmount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

347

uint8_t Sclk_CKS_masterEn0_7;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

348

uint8_t Sclk_CKS_masterEn8_15;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

349

uint8_t DPMFreezeAndForced;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

351

uint8_t Sclk_voltageOffset[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

378

uint8_t TempSrc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

403

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

404

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

405

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

406

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

410

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

411

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

413

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

414

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

415

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

416

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

418

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

419

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

420

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

421

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

425

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

426

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

427

uint8_t MclkSwitchInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

428

uint8_t MclkSwitchCritical;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

430

uint8_t IgnoreVBlank;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

431

uint8_t TargetMclkIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

432

uint8_t TargetMvddIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

433

uint8_t MclkSwitchResult;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

436

uint8_t VbiWaitCounter;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

437

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

442

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

443

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

451

uint8_t fastSwitch;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

452

uint8_t Save_PIC_VDDGFX_EXIT;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

453

uint8_t Save_PIC_VDDGFX_ENTER;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

454

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

461

uint8_t EnterUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

462

uint8_t ExitUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

463

uint8_t UlvActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

464

uint8_t WaitingForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

465

uint8_t UlvEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

466

uint8_t UlvRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

467

uint8_t UlvMasterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

468

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

487

uint8_t VddGfxEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

488

uint8_t VddGfxActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

489

uint8_t VPUResetOccured;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

49

uint8_t pcieDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

490

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

50

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

503

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

504

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

515

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

516

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

541

uint8_t VariantID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

542

uint8_t spare997;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

556

uint8_t LastACPIRequest;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

557

uint8_t CgBifResp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

558

uint8_t RequestType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

559

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

570

uint8_t m1_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

571

uint8_t m2_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

578

uint8_t BapmVddCVidHiSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

58

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

581

uint8_t BapmVddCVidLoSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

584

uint8_t VddCVid[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

587

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

588

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

589

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

59

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

590

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

594

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

595

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

598

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

599

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

60

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

600

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

601

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

604

uint8_t LPMLTemperatureScaler[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

61

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

613

uint8_t GnbLPML[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

616

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

617

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

618

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

62

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

63

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

64

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

65

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

652

uint8_t type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

653

uint8_t mode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

654

uint8_t filler_0[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

661

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

662

uint8_t Type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

663

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

74

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

75

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

76

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

77

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

94

uint8_t VddcOffsetVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

95

uint8_t VddcPhase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

107

uint8_t index;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

224

uint8_t waterfall_up;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

225

uint8_t waterfall_down;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

226

uint8_t waterfall_limit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

227

uint8_t spare;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

261

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

262

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

263

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

264

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

268

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

269

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

271

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

272

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

273

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

274

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

276

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

277

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

278

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

279

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

283

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

284

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

285

uint8_t GfxClkSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

286

uint8_t GpioClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

288

uint8_t spare2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

289

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

290

uint8_t DteClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

291

uint8_t FpsClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

296

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

297

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

302

uint8_t FpsEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

303

uint8_t MaxPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

304

uint8_t AllowLowClkInterruptToHost;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

305

uint8_t FpsRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

313

uint8_t MinPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

314

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

333

typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

348

uint8_t HighestVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

349

uint8_t CurrentVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

355

uint8_t ControllerBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

356

uint8_t CurrentVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

357

uint8_t CurrentVddciVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

358

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

362

uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

364

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

365

uint8_t padding3;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

366

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

367

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

370

uint8_t OverrideVoltage;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

371

uint8_t padding4;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

372

uint8_t padding5;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

373

uint8_t CurrentPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

394

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

395

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

396

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

397

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

399

uint8_t CurrentLinkSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

400

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

406

uint8_t DpmMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

407

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

408

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

409

uint8_t CurrentLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

433

uint8_t SidOptionPower;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

434

uint8_t SidOptionCurrent;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

466

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

467

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

468

uint8_t AutoTmonCalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

469

uint8_t AutoTmonCalEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

471

uint8_t ThermalDpmEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

472

uint8_t SclkEnabledMask;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

473

uint8_t spare[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

520

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

521

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

522

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

523

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

525

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

526

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

527

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

528

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

534

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

535

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

536

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

537

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

539

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

540

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

541

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

542

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

553

uint8_t Activity_Weight;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

554

uint8_t Reserved8[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

619

uint8_t BlockId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

620

uint8_t SignalId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

621

uint8_t Threshold;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

622

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

726

uint8_t minVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

727

uint8_t maxVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

741

uint8_t setting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

742

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

787

uint8_t NumTemperatureSteps;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

788

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

79

uint8_t a_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

80

uint8_t b_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

81

uint8_t c_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

82

uint8_t x_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74.h

822

uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

109

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

110

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

111

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

112

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

125

uint8_t VddcOffsetVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

126

uint8_t VddcPhase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

139

uint8_t StutterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

140

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

141

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

142

uint8_t padding_0;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

144

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

145

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

146

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

147

uint8_t padding_1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

150

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

151

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

157

uint8_t PcieGenSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

158

uint8_t PcieLaneCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

159

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

160

uint8_t SPC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

172

uint8_t McArbBurstTime;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

173

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

188

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

189

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

190

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

198

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

199

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

214

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

215

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

216

uint8_t McRegIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

217

uint8_t SeqIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

218

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

221

uint8_t PCIeGen;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

231

uint8_t m1_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

232

uint8_t m2_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

253

uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

254

uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

255

uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

257

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

258

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

259

uint8_t LinkLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

260

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

262

uint8_t UvdLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

263

uint8_t VceLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

264

uint8_t AcpLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

265

uint8_t SamuLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

267

uint8_t ThermOutGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

268

uint8_t ThermOutPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

269

uint8_t ThermOutMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

270

uint8_t BootPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

272

uint8_t VRHotLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

273

uint8_t LdoRefSel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

274

uint8_t SharedRails;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

275

uint8_t Reserved1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

293

uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

298

uint8_t UvdBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

299

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

300

uint8_t AcpBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

301

uint8_t SamuBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

303

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

304

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

305

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

306

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

308

uint8_t VoltageInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

309

uint8_t ThermalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

313

uint8_t MemoryBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

314

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

317

uint8_t MemoryInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

318

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

323

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

324

uint8_t PCIeGenInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

325

uint8_t DTEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

326

uint8_t DTEMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

328

uint8_t SVI2Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

329

uint8_t VRHotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

330

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

331

uint8_t ThermGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

357

uint8_t ClockStretcherAmount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

358

uint8_t Sclk_CKS_masterEn0_7;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

359

uint8_t Sclk_CKS_masterEn8_15;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

360

uint8_t DPMFreezeAndForced;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

362

uint8_t Sclk_voltageOffset[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

393

uint8_t TempSrc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

416

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

417

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

418

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

419

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

423

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

424

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

426

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

427

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

428

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

429

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

431

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

432

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

433

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

434

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

438

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

439

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

44

uint8_t vco_setting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

440

uint8_t MclkSwitchInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

441

uint8_t MclkSwitchCritical;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

443

uint8_t IgnoreVBlank;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

444

uint8_t TargetMclkIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

446

uint8_t VbiWaitCounter;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

447

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

45

uint8_t postdiv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

452

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

453

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

461

uint8_t fastSwitch;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

462

uint8_t Save_PIC_VDDGFX_EXIT;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

463

uint8_t Save_PIC_VDDGFX_ENTER;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

464

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

470

uint8_t EnterUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

471

uint8_t ExitUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

472

uint8_t UlvActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

473

uint8_t WaitingForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

474

uint8_t UlvEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

475

uint8_t UlvRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

476

uint8_t UlvMasterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

477

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

496

uint8_t VddGfxEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

497

uint8_t VddGfxActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

498

uint8_t VPUResetOccured;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

499

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

512

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

513

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

524

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

525

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

55

uint8_t Smio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

550

uint8_t VariantID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

551

uint8_t spare997;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

56

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

565

uint8_t LastACPIRequest;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

566

uint8_t CgBifResp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

567

uint8_t RequestType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

568

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

575

uint8_t BapmVddCVidHiSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

576

uint8_t BapmVddCVidLoSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

577

uint8_t VddCVid[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

578

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

579

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

580

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

581

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

583

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

584

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

585

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

586

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

587

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

588

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

590

uint8_t LPMLTemperatureScaler[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

597

uint8_t GnbLPML[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

599

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

600

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

601

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

633

uint8_t type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

634

uint8_t mode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

635

uint8_t filler_0[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

642

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

643

uint8_t Type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

644

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

72

uint8_t PllRange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

73

uint8_t SSc_En;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

739

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

740

uint8_t WaterfallUp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

741

uint8_t WaterfallDown;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

742

uint8_t WaterfallLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

743

uint8_t CurrMaxCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

744

uint8_t TargMaxCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

745

uint8_t ClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

746

uint8_t Active;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

747

uint8_t MaxSupportedCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

748

uint8_t MinSupportedCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

749

uint8_t PendingGfxCuHostInterrupt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

750

uint8_t LastFilteredMaxCuInteger;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

755

uint8_t ForceCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

756

uint8_t ForceCuCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

757

uint8_t spare[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

85

uint8_t pcieDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

86

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

92

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

93

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

94

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

95

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

96

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

97

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

98

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

99

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

195

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

196

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

197

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

198

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

202

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

203

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

205

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

206

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

207

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

208

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

210

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

211

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

212

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

213

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

217

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

218

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

219

uint8_t GfxClkSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

220

uint8_t GpioClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

222

uint8_t EnableModeSwitchRLCNotification;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

223

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

224

uint8_t DteClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

225

uint8_t FpsClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

230

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

231

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

236

uint8_t FpsEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

237

uint8_t MaxPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

238

uint8_t AllowLowClkInterruptToHost;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

239

uint8_t FpsRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

247

uint8_t MinPerfLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

249

uint8_t ScksClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

250

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

252

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

272

typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

286

uint8_t HighestVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

287

uint8_t CurrentVidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

292

uint8_t ControllerBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

293

uint8_t CurrentVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

294

uint8_t CurrentVddciVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

295

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

299

uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

301

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

302

uint8_t padding3;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

303

uint8_t ControllerEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

304

uint8_t ControllerRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

307

uint8_t OverrideVoltage;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

308

uint8_t padding4;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

309

uint8_t padding5;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

310

uint8_t CurrentPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

329

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

330

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

331

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

332

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

334

uint8_t CurrentLinkSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

335

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

341

uint8_t DpmMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

342

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

343

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

344

uint8_t CurrentLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

373

uint8_t MCLK_patch_flag;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

374

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

413

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

414

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

415

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

416

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

418

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

419

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

420

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

421

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

427

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

428

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

429

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

430

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

432

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

433

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

434

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

435

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

446

uint8_t Activity_Weight;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

447

uint8_t Reserved8[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

512

uint8_t BlockId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

513

uint8_t SignalId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

514

uint8_t Threshold;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

515

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

608

uint8_t minVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

609

uint8_t maxVID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

624

uint8_t setting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

625

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

688

uint8_t NumTemperatureSteps;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

689

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

709

uint8_t m1_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

710

uint8_t m2_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75.h

740

uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

100

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

104

uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

114

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

115

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

116

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

117

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

130

uint8_t VddcOffsetVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

131

uint8_t VddcPhase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

144

uint8_t StutterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

145

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

146

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

147

uint8_t padding_0;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

149

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

150

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

151

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

152

uint8_t padding_1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

155

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

156

uint8_t padding_2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

160

uint8_t Postdiv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

161

uint8_t padding_3[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

167

uint8_t PcieGenSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

168

uint8_t PcieLaneCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

169

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

170

uint8_t SPC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

202

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

203

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

204

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

213

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

214

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

229

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

230

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

231

uint8_t McRegIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

232

uint8_t SeqIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

233

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

236

uint8_t PCIeGen;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

256

uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

257

uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

258

uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

260

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

261

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

262

uint8_t LinkLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

263

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

265

uint8_t UvdLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

266

uint8_t VceLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

267

uint8_t AcpLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

268

uint8_t SamuLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

270

uint8_t ThermOutGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

271

uint8_t ThermOutPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

272

uint8_t ThermOutMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

273

uint8_t BootPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

275

uint8_t VRHotLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

276

uint8_t LdoRefSel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

278

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

298

uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

303

uint8_t UvdBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

304

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

305

uint8_t AcpBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

306

uint8_t SamuBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

308

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

309

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

310

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

311

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

313

uint8_t VoltageInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

314

uint8_t ThermalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

318

uint8_t MemoryBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

319

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

322

uint8_t MemoryInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

323

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

328

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

329

uint8_t PCIeGenInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

330

uint8_t DTEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

331

uint8_t DTEMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

333

uint8_t SVI2Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

334

uint8_t VRHotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

335

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

336

uint8_t ThermGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

362

uint8_t ClockStretcherAmount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

363

uint8_t Sclk_CKS_masterEn0_7;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

364

uint8_t Sclk_CKS_masterEn8_15;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

365

uint8_t DPMFreezeAndForced;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

367

uint8_t Sclk_voltageOffset[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

398

uint8_t TempSrc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

422

uint8_t TdpClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

423

uint8_t TdcClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

424

uint8_t ThermClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

425

uint8_t VoltageBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

429

uint8_t LevelChangeInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

43

uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

430

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

432

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

433

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

434

uint8_t DpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

435

uint8_t DpmRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

437

uint8_t DpmForce;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

438

uint8_t DpmForceLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

439

uint8_t padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

44

uint8_t postdiv; /* divide by 2^n */

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

440

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

444

uint8_t AcpiReq;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

445

uint8_t AcpiAck;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

446

uint8_t MclkSwitchInProgress;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

447

uint8_t MclkSwitchCritical;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

449

uint8_t IgnoreVBlank;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

450

uint8_t TargetMclkIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

451

uint8_t TargetMvddIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

452

uint8_t MclkSwitchResult;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

455

uint8_t VbiWaitCounter;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

456

uint8_t EnabledLevelsChange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

461

void (*TargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

462

void (*SavedTargetStateCalculator)(uint8_t);

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

470

uint8_t fastSwitch;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

471

uint8_t Save_PIC_VDDGFX_EXIT;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

472

uint8_t Save_PIC_VDDGFX_ENTER;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

473

uint8_t VbiTimeout;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

481

uint8_t EnterUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

482

uint8_t ExitUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

483

uint8_t UlvActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

484

uint8_t WaitingForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

485

uint8_t UlvEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

486

uint8_t UlvRunning;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

487

uint8_t UlvMasterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

488

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

507

uint8_t VddGfxEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

508

uint8_t VddGfxActive;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

509

uint8_t VPUResetOccured;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

510

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

523

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

524

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

53

uint8_t Smio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

535

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

536

uint8_t Running;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

54

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

542

uint8_t PowerSharingEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

543

uint8_t PowerSharingCounter;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

544

uint8_t PowerSharingINTEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

545

uint8_t GFXActivityCounterEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

548

uint8_t RollOverRequired;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

549

uint8_t RollOverCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

550

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

570

uint8_t VariantID;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

571

uint8_t spare997;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

585

uint8_t LastACPIRequest;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

586

uint8_t CgBifResp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

587

uint8_t RequestType;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

588

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

595

uint8_t BapmVddCVidHiSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

597

uint8_t BapmVddCVidLoSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

599

uint8_t VddCVid[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

601

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

602

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

603

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

604

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

607

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

608

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

610

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

611

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

612

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

613

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

615

uint8_t LPMLTemperatureScaler[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

622

uint8_t GnbLPML[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

624

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

625

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

626

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

632

uint8_t Version;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

633

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

661

uint8_t type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

662

uint8_t mode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

663

uint8_t filler_0[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

670

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

671

uint8_t Type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

672

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

70

uint8_t PllRange;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

71

uint8_t SSc_En;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

774

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

775

uint8_t WaterfallUp;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

776

uint8_t WaterfallDown;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

777

uint8_t WaterfallLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

778

uint8_t CurrMaxCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

779

uint8_t TargMaxCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

780

uint8_t ClampMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

781

uint8_t Active;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

782

uint8_t MaxSupportedCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

783

uint8_t MinSupportedCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

784

uint8_t PendingGfxCuHostInterrupt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

785

uint8_t LastFilteredMaxCuInteger;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

790

uint8_t ForceCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

791

uint8_t ForceCuCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

792

uint8_t AcModeMaxCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

793

uint8_t DcModeMaxCu;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

84

uint8_t pcieDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

85

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

93

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

94

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

95

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

96

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

97

uint8_t UpHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

98

uint8_t DownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

99

uint8_t VoltageDownHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

111

uint8_t padding1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

120

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

121

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

122

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

123

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

124

uint8_t UpH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

125

uint8_t DownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

126

uint8_t VoltageDownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

127

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

128

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

129

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

140

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

141

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

142

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

143

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

161

uint8_t VddcOffsetVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

162

uint8_t VddcPhase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

177

uint8_t EdcReadEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

178

uint8_t EdcWriteEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

179

uint8_t RttEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

180

uint8_t StutterEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

182

uint8_t StrobeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

183

uint8_t StrobeRatio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

184

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

185

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

187

uint8_t UpH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

188

uint8_t DownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

189

uint8_t VoltageDownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

190

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

193

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

194

uint8_t padding1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

211

uint8_t PcieGenSpeed;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

212

uint8_t PcieLaneCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

213

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

214

uint8_t Padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

227

uint8_t McArbBurstTime;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

228

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

245

uint8_t MinVddcPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

246

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

247

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

248

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

257

uint8_t MinPhases;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

258

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

274

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

275

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

276

uint8_t McRegIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

277

uint8_t SeqIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

278

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

281

uint8_t PCIeGen;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

311

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

312

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

313

uint8_t LinkLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

314

uint8_t UvdLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

315

uint8_t VceLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

316

uint8_t AcpLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

317

uint8_t SamuLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

318

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

337

uint8_t UvdBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

338

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

339

uint8_t AcpBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

340

uint8_t SamuBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

342

uint8_t UVDInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

343

uint8_t VCEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

344

uint8_t ACPInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

345

uint8_t SAMUInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

347

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

348

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

349

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

350

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

352

uint8_t VoltageInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

353

uint8_t ThermalInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

357

uint8_t MemoryBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

358

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

360

uint8_t MemoryInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

361

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

367

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

368

uint8_t PCIeGenInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

369

uint8_t DTEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

370

uint8_t DTEMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

372

uint8_t SVI2Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

373

uint8_t VRHotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

374

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

375

uint8_t ThermGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

389

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

390

uint8_t DTETjOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

391

uint8_t GpuTjMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

392

uint8_t GpuTjHyst;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

427

uint8_t last;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

428

uint8_t reserved[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

453

uint8_t TempSrc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

462

uint8_t BapmVddCVidHiSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

465

uint8_t BapmVddCVidLoSidd[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

468

uint8_t VddCVid[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

471

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

472

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

473

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

474

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

478

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

479

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

482

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

483

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

484

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

485

uint8_t Reserved;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

488

uint8_t BapmVddCVidHiSidd2[8];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

497

uint8_t GnbLPML[16];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

500

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

501

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

502

uint8_t Reserved1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

55

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

56

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

57

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

58

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

60

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

61

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

62

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

63

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

69

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

70

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

71

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

72

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

74

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

75

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

76

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

77

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

97

uint8_t Smio;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

98

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

101

uint8_t DownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

102

uint8_t VoltageDownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

103

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

105

uint8_t ClkBypassCntl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

113

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

114

uint8_t LclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

115

uint8_t Vid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

116

uint8_t VoltageDownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

121

uint8_t UpH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

122

uint8_t DownH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

126

uint8_t ActivityLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

127

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

129

uint8_t ClkBypassCntl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

131

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

141

uint8_t VclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

142

uint8_t DclkDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

144

uint8_t VClkBypassCntl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

145

uint8_t DClkBypassCntl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

147

uint8_t padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

157

uint8_t Divider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

158

uint8_t ClkBypassCntl;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

168

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

169

uint8_t GnbSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

170

uint8_t ForceNbPs1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

171

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

172

uint8_t DeepSleepDivId;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

173

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

179

uint8_t DpmXNbPsHi;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

180

uint8_t DpmXNbPsLo;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

181

uint8_t Dpm0PgNbPsHi;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

182

uint8_t Dpm0PgNbPsLo;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

183

uint8_t EnablePsi1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

184

uint8_t SkipDPM0;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

185

uint8_t SkipPG;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

186

uint8_t Hysteresis;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

187

uint8_t EnableDpmPstatePoll;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

188

uint8_t padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

201

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

202

uint8_t McArbIndex;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

215

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

216

uint8_t GIOLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

217

uint8_t UvdLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

218

uint8_t VceLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

220

uint8_t AcpLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

221

uint8_t SamuLevelCount;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

231

uint8_t UvdBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

232

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

233

uint8_t AcpBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

234

uint8_t SamuBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

235

uint8_t UVDInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

236

uint8_t VCEInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

237

uint8_t ACPInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

238

uint8_t SAMUInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

240

uint8_t GraphicsBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

241

uint8_t GraphicsInterval;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

242

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

243

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

245

uint8_t GraphicsClkSlowEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

246

uint8_t GraphicsClkSlowDivider;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

268

uint8_t Enable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

269

uint8_t GIOVoltageChangeEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

270

uint8_t GIOBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

271

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

272

uint8_t padding1[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

273

uint8_t TargetState;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

274

uint8_t CurrenttState;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

275

uint8_t ThrottleOnHtc;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

276

uint8_t ThermThrottleStatus;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

277

uint8_t ThermThrottleTempSelect;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

278

uint8_t ThermThrottleEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

45

uint8_t DisplayPhy1Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

46

uint8_t DisplayPhy2Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

47

uint8_t DisplayPhy3Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

48

uint8_t DisplayPhy4Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

50

uint8_t DisplayPhy5Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

51

uint8_t DisplayPhy6Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

52

uint8_t DisplayPhy7Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

53

uint8_t DisplayPhy8Config;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

59

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

60

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

61

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

62

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

64

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

65

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

66

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

67

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

87

uint8_t Vid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

88

uint8_t VidOffset;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

91

uint8_t PowerThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

92

uint8_t GnbSlow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

93

uint8_t ForceNbPs1;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

94

uint8_t SclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

96

uint8_t DisplayWatermark;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

97

uint8_t EnabledForActivity;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

98

uint8_t EnabledForThrottle;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

99

uint8_t UpH;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

36

uint8_t Enabled;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

37

uint8_t spare[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

47

uint8_t EnableCsrShadow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

48

uint8_t EnableDramShadow;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

67

uint8_t GnbVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

68

uint8_t GfxVid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

69

uint8_t DfsDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu8_fusion.h

70

uint8_t DeepSleepDid;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

104

uint8_t m1_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

105

uint8_t m2_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

106

uint8_t b_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

107

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

143

uint8_t Liquid1_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

144

uint8_t Liquid2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

145

uint8_t Vr_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

146

uint8_t Plx_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

148

uint8_t GeminiMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

149

uint8_t spare17[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

153

uint8_t Liquid_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

154

uint8_t Liquid_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

155

uint8_t Vr_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

156

uint8_t Vr_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

157

uint8_t Plx_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

158

uint8_t Plx_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

159

uint8_t paddingx[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

162

uint8_t UlvOffsetVid; /* SVI2 VID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

163

uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

164

uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

165

uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

168

uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

171

uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

172

uint8_t MaxVoltageVid; /* Maximum Voltage allowable */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

173

uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

174

uint8_t padding8;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

176

uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

177

uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

178

uint8_t padding8_2[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

183

uint8_t SocclkDid[NUM_SOCCLK_DPM_LEVELS]; /* DID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

184

uint8_t SocDpmVoltageIndex[NUM_SOCCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

186

uint8_t VclkDid[NUM_UVD_DPM_LEVELS]; /* DID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

187

uint8_t DclkDid[NUM_UVD_DPM_LEVELS]; /* DID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

188

uint8_t UvdDpmVoltageIndex[NUM_UVD_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

190

uint8_t EclkDid[NUM_VCE_DPM_LEVELS]; /* DID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

191

uint8_t VceDpmVoltageIndex[NUM_VCE_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

193

uint8_t Mp0clkDid[NUM_MP0CLK_DPM_LEVELS]; /* DID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

194

uint8_t Mp0DpmVoltageIndex[NUM_MP0CLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

199

uint8_t GfxDpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

200

uint8_t SocDpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

201

uint8_t UclkDpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

202

uint8_t UvdDpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

204

uint8_t VceDpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

205

uint8_t Mp0DpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

206

uint8_t DisplayDpmVoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

207

uint8_t padding8_3;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

215

uint8_t GfxclkAverageAlpha;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

216

uint8_t SocclkAverageAlpha;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

217

uint8_t UclkAverageAlpha;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

218

uint8_t GfxActivityAverageAlpha;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

221

uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

223

uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

224

uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

225

uint8_t paddingUclk[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

230

uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

231

uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

234

uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

237

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

238

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

239

uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

240

uint8_t paddingLinkDpm[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

259

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

260

uint8_t FanSpare;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

269

uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

270

uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

271

uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

272

uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

273

uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

274

uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

275

uint8_t Padding1; /* replace GPIO pin configured for CTF */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

276

uint8_t Padding2; /* replace GPIO polarity for CTF */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

279

uint8_t LedPin0; /* GPIO number for LedPin[0] */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

280

uint8_t LedPin1; /* GPIO number for LedPin[1] */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

281

uint8_t LedPin2; /* GPIO number for LedPin[2] */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

282

uint8_t padding8_4;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

285

uint8_t OverrideBtcGbCksOn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

286

uint8_t OverrideAvfsGbCksOn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

287

uint8_t PaddingAvfs8[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

295

uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

306

uint8_t EnableBoostState;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

307

uint8_t AConstant_Shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

308

uint8_t DC_tol_sigma_Shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

309

uint8_t PSM_Age_CompFactor_Shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

316

uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

335

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

336

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

386

uint8_t AvfsEn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

387

uint8_t AvfsVersion;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

388

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

84

uint8_t SsOn;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

85

uint8_t Did; /* DID */

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

93

uint8_t a0_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

94

uint8_t a1_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

95

uint8_t a2_shift;

drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

96

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

114

uint8_t type;

drivers/gpu/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

115

uint8_t arg;

drivers/gpu/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

123

uint8_t JobList[NUM_JOBLIST_ENTRIES];

drivers/gpu/drm/amd/pm/powerplay/inc/smumgr.h

114

extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

240

uint8_t VoltageMode;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

241

uint8_t SnapToDiscrete;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

242

uint8_t NumDiscreteLevels;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

243

uint8_t padding;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

284

uint8_t MemoryOnPackage;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

285

uint8_t padding8_limits[3];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

291

uint8_t UlvSmnclkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

292

uint8_t UlvMp1clkDid;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

293

uint8_t UlvGfxclkBypass;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

294

uint8_t Padding234;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

334

uint8_t Padding456[2];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

337

uint8_t LowestUclkReservedForUlv;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

338

uint8_t Padding8_Uclk[3];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

341

uint8_t PcieGenSpeed[NUM_LINK_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

342

uint8_t PcieLaneCount[NUM_LINK_LEVELS];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

368

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

369

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

381

uint8_t OverrideAvfsGb;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

382

uint8_t Padding8_Avfs[3];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

398

uint8_t DcBtcGfxEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

399

uint8_t DcBtcSocEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

400

uint8_t Padding8_GfxBtc[2];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

423

uint8_t Liquid1_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

424

uint8_t Liquid2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

425

uint8_t Vr_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

426

uint8_t Plx_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

428

uint8_t Liquid_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

429

uint8_t Liquid_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

430

uint8_t Vr_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

431

uint8_t Vr_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

433

uint8_t Plx_I2C_LineSCL;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

434

uint8_t Plx_I2C_LineSDA;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

435

uint8_t VrSensorPresent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

436

uint8_t LiquidSensorPresent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

441

uint8_t VddGfxVrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

442

uint8_t VddSocVrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

443

uint8_t VddMem0VrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

444

uint8_t VddMem1VrMapping;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

446

uint8_t GfxUlvPhaseSheddingMask;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

447

uint8_t SocUlvPhaseSheddingMask;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

448

uint8_t ExternalSensorPresent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

449

uint8_t Padding8_V;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

454

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

458

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

462

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

466

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

469

uint8_t AcDcGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

470

uint8_t AcDcPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

471

uint8_t VR0HotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

472

uint8_t VR0HotPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

474

uint8_t VR1HotGpio;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

475

uint8_t VR1HotPolarity;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

476

uint8_t Padding1;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

477

uint8_t Padding2;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

481

uint8_t LedPin0;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

482

uint8_t LedPin1;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

483

uint8_t LedPin2;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

484

uint8_t padding8_4;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

487

uint8_t PllGfxclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

488

uint8_t PllGfxclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

491

uint8_t UclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

492

uint8_t UclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

495

uint8_t SocclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

496

uint8_t SocclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

499

uint8_t AcgGfxclkSpreadEnabled;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

500

uint8_t AcgGfxclkSpreadPercent;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

503

uint8_t Vr2_I2C_address;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

504

uint8_t padding_vr2[3];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

552

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

553

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

554

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

555

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

566

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

567

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

579

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

580

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

608

uint8_t AvfsEn;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

609

uint8_t AvfsVersion;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

610

uint8_t OverrideVFT;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

611

uint8_t OverrideAvfsGb;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

613

uint8_t OverrideTemperatures;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

614

uint8_t OverrideVInversion;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

615

uint8_t OverrideP2V;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

616

uint8_t OverrideP2VCharzFreq;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

658

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

659

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

660

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

661

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

662

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

663

uint8_t Gfx_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

673

uint8_t Soc_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

674

uint8_t Soc_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

675

uint8_t Soc_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

676

uint8_t Soc_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

677

uint8_t Soc_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

678

uint8_t Soc_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

688

uint8_t Mem_ActiveHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

689

uint8_t Mem_IdleHystLimit;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

690

uint8_t Mem_FPS;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

691

uint8_t Mem_MinActiveFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

692

uint8_t Mem_BoosterFreqType;

drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

693

uint8_t Mem_UseRlcBusy;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1007

(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1009

(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1016

(uint8_t)dpm_table->pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

109

const uint8_t *src, uint32_t byte_count, uint32_t limit)

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1119

static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1122

uint8_t mc_para_index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1130

mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1137

mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1143

static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1145

uint8_t mc_para_index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1152

mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1339

smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1344

level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1411

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1522

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1527

table->UvdLevelCount = (uint8_t)(uvd_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1543

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1550

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1563

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1568

table->VceLevelCount = (uint8_t)(vce_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1583

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1595

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1600

table->AcpLevelCount = (uint8_t)(acp_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1613

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1645

arb_regs->McArbBurstTime = (uint8_t)burstTime;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1676

(uint8_t *)&arb_regs,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1742

mc_reg_table->last = (uint8_t)i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1831

(uint8_t *)&smu_data->mc_regs.data[0],

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1851

(uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1858

uint8_t count, level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1860

count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1870

count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2058

table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2105

(uint8_t *)&(table->SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2193

fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2195

res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2232

(uint8_t *)&low_sclk_interrupt_threshold,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2316

uint8_t *src;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2326

src = (uint8_t *)info.kptr;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2443

static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr)

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2445

return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2557

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2586

uint8_t i, j, k;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2661

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2682

uint8_t module_index = ci_get_memory_modile_index(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2810

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2811

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2845

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2846

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

366

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

388

static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

391

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

581

uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

582

uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

583

uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

610

uint8_t *vid = smu_data->power_tune_table.VddCVid;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

709

(uint8_t *)&smu_data->power_tune_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

730

dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

857

table->VddcLevel[count].Smio = (uint8_t) count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

885

table->VddciLevel[count].Smio = (uint8_t) count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

913

table->MvddLevel[count].Smio = (uint8_t) count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

977

state->VddcOffsetVid = (uint8_t)(

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

54

uint8_t last;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

55

uint8_t num_entries;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1008

uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1017

uint8_t hightest_pcie_level_enabled = 0,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1042

(uint8_t)dpm_table->sclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1053

(uint8_t) ((i < max_entry) ? i : max_entry);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1086

result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1106

static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1155

mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1257

(uint8_t)dpm_table->mclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1265

result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1339

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1422

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1429

table->VceLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1449

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1461

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1468

table->AcpLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1485

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1517

arb_regs->McArbBurstTime = (uint8_t)burstTime;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1518

arb_regs->TRRDS = (uint8_t)trrds;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1519

arb_regs->TRRDL = (uint8_t)trrdl;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1547

(uint8_t *)&arb_regs,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1557

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1564

table->UvdLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1583

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1590

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1637

uint8_t count, level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1639

count = (uint8_t)(table_info->vdd_dep_on_sclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1648

count = (uint8_t)(table_info->vdd_dep_on_mclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1666

uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1673

stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1710

volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1779

(uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1782

(uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1926

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2027

table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2107

(uint8_t *)&(table->SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2208

fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2213

(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2282

(uint8_t *)&low_sclk_interrupt_threshold,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2375

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2408

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

245

(uint8_t *)&vr_config, sizeof(int32_t), 0x40000),

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

253

(uint8_t *)(&avfs_graphics_level), level_size, 0x40000),

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2597

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2598

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2632

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2633

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

425

static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

497

uint8_t uc_scl, uc_sda;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

511

dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

619

(uint8_t)((temp >> 16) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

621

(uint8_t)((temp >> 8) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

622

smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

745

(uint8_t *)&smu_data->power_tune_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

758

uint8_t index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

76

static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = {

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

807

state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

838

(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

839

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

842

table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

848

(uint8_t)dpm_table->pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

931

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

32

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

33

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

34

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

35

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

36

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.h

37

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1001

(uint8_t)dpm_table->sclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1038

(uint8_t *)levels, (uint32_t)level_array_size,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1169

static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1172

uint8_t mc_para_index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1180

mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1188

mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1195

static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1197

uint8_t mc_para_index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1204

mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1382

smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1389

level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1457

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

158

uint32_t length, const uint8_t *src,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1606

arb_regs->McArbBurstTime = (uint8_t)burstTime;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1638

(uint8_t *)&arb_regs,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1707

mc_reg_table->last = (uint8_t)i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1797

(uint8_t *)&smu_data->mc_regs.data[0],

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1817

(uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1824

uint8_t count, level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1826

count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1836

count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1872

dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2031

table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2059

(uint8_t *)&(table->SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2069

(uint8_t *)&(smu_data->ulv_setting),

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2153

fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2157

res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2195

(uint8_t *)&low_sclk_interrupt_threshold,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

222

(uint8_t *)info.kptr, ICELAND_SMC_SIZE,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2370

static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2372

return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2484

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2513

uint8_t i, j, k;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2589

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2609

uint8_t module_index = iceland_get_memory_modile_index(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

393

uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

394

uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

419

uint8_t *vid = smu_data->power_tune_table.VddCVid;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

497

(uint8_t *)&smu_data->power_tune_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

744

state->VddcOffsetVid = (uint8_t)(

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

774

(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

776

(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

780

(uint8_t)(data->pcie_spc_cap & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

788

(uint8_t)dpm_table->pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

868

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

973

uint8_t highest_pcie_level_enabled = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

974

uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

975

uint8_t count = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

35

uint8_t svi_load_line_en;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

36

uint8_t svi_load_line_vddc;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

37

uint8_t tdc_vddc_throttle_release_limit_perc;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

38

uint8_t tdc_mawt;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

39

uint8_t tdc_waterfall_ctl;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

40

uint8_t dte_ambient_temp_base;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

53

uint8_t last; /* number of registers*/

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

54

uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1003

level->UpHyst = (uint8_t)data->up_hyst;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1005

level->DownHyst = (uint8_t)data->down_hyst;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1030

uint8_t shared_rail;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1044

uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1053

uint8_t hightest_pcie_level_enabled = 0,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1098

(uint8_t)dpm_table->sclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1113

(uint8_t) ((i < max_entry) ? i : max_entry);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1146

result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1237

(uint8_t)dpm_table->mclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1246

result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1369

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1378

table->VceLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1407

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1419

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1428

table->SamuLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

143

(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1456

table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1485

arb_regs->McArbBurstTime = (uint8_t)burst_time;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

150

(uint8_t *)(&avfs_graphics_level_polaris10),

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1514

(uint8_t *)&arb_regs,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1524

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1533

table->UvdLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1560

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1567

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

158

(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1623

uint8_t count, level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1625

count = (uint8_t)(table_info->vdd_dep_on_sclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1635

count = (uint8_t)(table_info->vdd_dep_on_mclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1659

uint8_t i, stretch_amount, volt_offset = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1661

stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

167

(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1687

volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1864

AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1874

(uint8_t *)&AVFS_meanNsigma,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1883

(uint8_t *)&AVFS_SclkOffset,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1922

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2121

(uint8_t *)&(table->SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2250

fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2255

(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2291

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2324

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2403

(uint8_t *)&low_sclk_interrupt_threshold,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2563

static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2565

return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2572

uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2635

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2636

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2670

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2671

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

299

smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

300

smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

537

(uint8_t)((temp >> 16) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

539

(uint8_t)((temp >> 8) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

540

smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

655

(uint8_t *)&smu_data->power_tune_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

679

(uint8_t) level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

705

table->SmioTable1.Pattern[level].Smio = (uint8_t) level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

730

table->SmioTable1.Pattern[level].Smio = (uint8_t) level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

745

uint8_t index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

790

state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

827

(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

828

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

831

table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

837

(uint8_t)dpm_table->pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

898

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

36

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

37

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

38

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

39

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

40

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

41

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

56

uint8_t protected_mode;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

117

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

144

memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

151

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

295

static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

50

const uint8_t *src, uint32_t byte_count, uint32_t limit)

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

50

uint8_t security_hard_key;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

57

const uint8_t *src, uint32_t byte_count, uint32_t limit);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

217

static uint8_t smu8_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

220

uint8_t ret = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

329

uint8_t type, bool is_last)

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

331

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

368

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

412

toc->JobList[i] = (uint8_t)IGNORE_JOB;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

422

toc->JobList[JOB_GFX_SAVE] = (uint8_t)smu8_smu->toc_entry_used_count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

440

toc->JobList[JOB_GFX_RESTORE] = (uint8_t)smu8_smu->toc_entry_used_count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.h

80

uint8_t driver_buffer_length;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu8_smumgr.h

81

uint8_t scratch_buffer_length;

drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c

241

int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1130

smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1137

level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1206

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1312

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1320

table->UvdLevelCount = (uint8_t) (mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1348

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1357

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1372

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1380

table->VceLevelCount = (uint8_t) (mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1405

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1417

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1425

table->AcpLevelCount = (uint8_t) (mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1449

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1481

arb_regs->McArbBurstTime = (uint8_t)burstTime;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1513

(uint8_t *)&arb_regs,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1580

uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1589

stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1639

volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1708

(uint8_t) tonga_clock_stretcher_ddt_table[type][i][2];

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1711

(uint8_t) tonga_clock_stretcher_ddt_table[type][i][3];

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1847

dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2054

(uint8_t *)&smu_data->power_tune_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2085

mc_reg_table->last = (uint8_t)i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2178

(uint8_t *)&smu_data->mc_regs.data[0],

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2201

(uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2230

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2350

table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2438

(uint8_t *)&(table->SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2538

fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2544

(uint8_t *)&fan_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2585

(uint8_t *)&low_sclk_interrupt_threshold,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2686

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2720

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2832

static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2834

return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2948

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2977

uint8_t i, j, k;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3052

uint8_t i, j;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3073

uint8_t module_index = tonga_get_memory_modile_index(hwmgr);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3196

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3197

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3231

tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3232

tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

352

(uint8_t) count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

379

(uint8_t) count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

395

uint8_t index = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

489

state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

517

(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

519

(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

523

(uint8_t)(data->pcie_spc_cap & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

531

(uint8_t)dpm_table->pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

611

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

693

uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

703

uint8_t highest_pcie_level_enabled = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

704

uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

705

uint8_t count = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

731

(uint8_t)dpm_table->sclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

742

(uint8_t) ((i < max_entry) ? i : max_entry);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

781

(uint8_t *)levels, (uint32_t)level_array_size,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

92

static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

920

static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

923

uint8_t mc_para_index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

931

mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

938

mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

944

static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

946

uint8_t mc_para_index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

953

mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

37

uint8_t svi_load_line_en;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

38

uint8_t svi_load_line_vddC;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

39

uint8_t tdc_vddc_throttle_release_limit_perc;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

40

uint8_t tdc_mawt;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

41

uint8_t tdc_waterfall_ctl;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

42

uint8_t dte_ambient_temp_base;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

55

uint8_t last; /* number of registers*/

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

56

uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

373

static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

39

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

72

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

387

static int vega12_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

41

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

85

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

164

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

209

uint8_t *table, int16_t table_id)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

249

uint8_t *table, uint16_t workload_type)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

284

uint8_t *table, uint16_t workload_type)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

618

static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h

55

uint8_t *table, uint16_t workload_type);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h

57

uint8_t *table, uint16_t workload_type);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1060

levels[i].UpHyst = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1062

levels[i].DownHyst = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1067

(uint8_t)dpm_table->mclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1079

result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1198

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1207

table->VceLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1236

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1301

(uint8_t *)&arb_regs,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1311

uint8_t count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1320

table->UvdLevelCount = (uint8_t)(mm_table->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1347

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1354

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1407

uint8_t count, level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1409

count = (uint8_t)(table_info->vdd_dep_on_sclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1419

count = (uint8_t)(table_info->vdd_dep_on_mclk->count);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1492

uint8_t i, stretch_amount, volt_offset = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1498

stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1520

volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1630

(uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1642

(uint8_t *)&AVFS_meanNsigma,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1652

(uint8_t *)&AVFS_SclkOffset,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1777

(uint8_t)((temp >> 16) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1779

(uint8_t)((temp >> 8) & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1780

smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1895

(uint8_t *)&smu_data->power_tune_table,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1926

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

199

smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

201

smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2136

(uint8_t *)&(table->SystemFlags),

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2233

(uint8_t *)&low_sclk_interrupt_threshold,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

340

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

373

(uint8_t) (table_info->mm_dep_table->count - 1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

463

(uint8_t) level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

489

table->SmioTable1.Pattern[level].Smio = (uint8_t) level;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

504

uint8_t index;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

550

state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

581

(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

582

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

585

table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

591

(uint8_t)dpm_table->pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

727

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

790

static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

793

uint8_t i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

872

uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

881

uint8_t hightest_pcie_level_enabled = 0,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

896

levels[i].UpHyst = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

898

levels[i].DownHyst = (uint8_t)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

909

(uint8_t)dpm_table->sclk_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

924

(uint8_t) ((i < max_entry) ? i : max_entry);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

957

result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

976

mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

45

uint8_t SviLoadLineEn;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

46

uint8_t SviLoadLineVddC;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

47

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

48

uint8_t TDC_MAWt;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

49

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

50

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

65

uint8_t protected_mode;

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

1648

uint8_t pcie_gen = 0, pcie_width = 0;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1080

int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap);

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

156

uint8_t m3arb;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

157

uint8_t unused[3];

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

182

uint8_t supported_power_levels;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

266

uint8_t domain;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

334

uint8_t pcie_gen[SMU_MAX_PCIE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

335

uint8_t pcie_lane[SMU_MAX_PCIE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

353

uint8_t cooling_id;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

411

uint8_t thermal_controller_type;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

728

uint8_t *ppt_start_addr;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

754

uint8_t smc_fw_state;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

263

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

264

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

265

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

267

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

268

uint8_t ControllerName;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

269

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

270

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

301

uint8_t RegisterAddr; ////only valid for write, ignored for read

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

302

uint8_t Cmd; //Read(0) or Write(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

303

uint8_t Data; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

304

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

308

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

309

uint8_t I2CSpeed; //Slow(0) or Fast(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

311

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

312

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

457

uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

458

uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

459

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

460

uint8_t padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

500

uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

501

uint8_t Padding234[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

531

uint8_t Padding567[4];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

533

uint8_t GfxclkSource; // 0 = PLL, 1 = AFLL

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

534

uint8_t Padding456;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

558

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

559

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

560

uint8_t FanTempInputSelect;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

561

uint8_t padding8_Fan;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

572

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

573

uint8_t Padding8_Avfs[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

585

uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

586

uint8_t Padding8_GfxBtc[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

594

uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

595

uint8_t XgmiDpmSpare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

620

uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

621

uint8_t TotalPowerSpare1;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

650

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

651

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

652

uint8_t VddMemVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

653

uint8_t BoardVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

655

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

656

uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

657

uint8_t Padding8_V[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

662

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

666

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

670

uint8_t Padding_TelemetryMem;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

674

uint8_t Padding_TelemetryBoardInput;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

677

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

678

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

679

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

680

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

683

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

684

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

688

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

689

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

693

uint8_t FclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

694

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

698

uint8_t FllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

699

uint8_t FllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

708

uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

709

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

716

uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

717

uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

723

uint8_t GpioI2cScl; // Serial Clock

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

724

uint8_t GpioI2cSda; // Serial Data

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

763

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

764

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

765

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

766

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

799

uint8_t AvfsVersion;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

800

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

801

uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

803

uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

804

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

806

uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

807

uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

808

uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

809

uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

850

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

851

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

852

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

853

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

854

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

855

uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

856

uint8_t Gfx_UseRlcBusy;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

857

uint8_t PaddingGfx[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

867

uint8_t Mem_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

868

uint8_t Mem_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

869

uint8_t Mem_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

870

uint8_t Mem_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

871

uint8_t Mem_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

872

uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

873

uint8_t Mem_UseRlcBusy;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

874

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

885

uint8_t Mem_UpHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

886

uint8_t Mem_DownHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1005

uint8_t PcieRate;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1006

uint8_t PcieWidth;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1028

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1029

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1068

uint8_t AvfsVersion;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1069

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1071

uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1073

uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1074

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1076

uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1077

uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1078

uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1079

uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1121

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1122

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1123

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1124

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1125

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1126

uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1136

uint8_t Soc_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1137

uint8_t Soc_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1138

uint8_t Soc_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1139

uint8_t Soc_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1140

uint8_t Soc_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1141

uint8_t Soc_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1151

uint8_t Mem_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1152

uint8_t Mem_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1153

uint8_t Mem_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1154

uint8_t Mem_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1155

uint8_t Mem_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1156

uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1167

uint8_t Mem_UpHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1168

uint8_t Mem_DownHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

267

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

268

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

269

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

271

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

272

uint8_t ControllerName;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

273

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

274

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

305

uint8_t RegisterAddr; ////only valid for write, ignored for read

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

306

uint8_t Cmd; //Read(0) or Write(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

307

uint8_t Data; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

308

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

312

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

313

uint8_t I2CSpeed; //Slow(0) or Fast(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

315

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

316

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

435

uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

436

uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

437

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

438

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

482

uint8_t MinorInfoVersion;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

483

uint8_t MajorInfoVersion;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

484

uint8_t TableSize;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

485

uint8_t Reserved;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

487

uint8_t Reserved1;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

488

uint8_t RevID;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

512

uint8_t MemoryHotspotPosition;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

513

uint8_t Reserved4;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

561

uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls delay for GFX SDP port disconnection during idle events

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

562

uint8_t paddingRlcUlvParams[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

564

uint8_t UlvSmnclkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

565

uint8_t UlvMp1clkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

566

uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

567

uint8_t Padding234;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

599

uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

612

uint8_t Padding567[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

614

uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

615

uint8_t Padding456;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

618

uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

619

uint8_t paddingUclk[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

621

uint8_t MemoryType; // 0-GDDR6, 1-HBM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

622

uint8_t MemoryChannels;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

623

uint8_t PaddingMem[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

626

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

627

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

656

uint8_t FanTempInputSelect;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

657

uint8_t FanPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

658

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

659

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

671

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

672

uint8_t Padding8_Avfs[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

684

uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

685

uint8_t Padding8_GfxBtc[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

698

uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

699

uint8_t TotalPowerSpare1;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

736

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

737

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

738

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

739

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

741

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

742

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

743

uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

744

uint8_t Padding8_V;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

749

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

753

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

757

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

761

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

764

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

765

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

766

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

767

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

769

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

770

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

771

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

772

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

775

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

776

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

777

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

778

uint8_t padding8_4;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

781

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

782

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

786

uint8_t DfllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

787

uint8_t DfllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

791

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

792

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

796

uint8_t SoclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

797

uint8_t SocclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

807

uint8_t RenesesLoadLineEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

808

uint8_t GfxLoadlineResistance;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

809

uint8_t SocLoadlineResistance;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

810

uint8_t Padding8_Loadline;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

867

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

868

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

869

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

870

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

885

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

886

uint8_t Padding8_2;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

900

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

901

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

902

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

903

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

918

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

919

uint8_t Padding8_2;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

924

uint8_t PcieRate;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

925

uint8_t PcieWidth;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

926

uint8_t Padding8_3[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

939

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

940

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

941

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

942

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

957

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

958

uint8_t Padding8_2;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

978

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

979

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

980

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

981

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

996

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

997

uint8_t Padding8_2;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1015

uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1016

uint8_t paddingRlcUlvParams[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1058

uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1073

uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1074

uint8_t GfxclkPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1077

uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1078

uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1079

uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1080

uint8_t GfxGpoPadding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1104

uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1105

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1107

uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1116

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1117

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1134

uint8_t FanTempInputSelect;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1135

uint8_t FanPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1136

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1137

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1147

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1148

uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1149

uint8_t Padding8_Avfs;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1163

uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1164

uint8_t Padding8_GfxBtc[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1172

uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1173

uint8_t XgmiDpmSpare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1183

uint8_t CustomerVariant;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1186

uint8_t VcBtcEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1211

uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1212

uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1213

uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1214

uint8_t I2cSpare[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1217

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1218

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1219

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1220

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1222

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1223

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1224

uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1225

uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1230

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1234

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1238

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1242

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1247

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1248

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1249

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1250

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1252

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1253

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1254

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1255

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1258

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1259

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1260

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1261

uint8_t LedEnableMask;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1263

uint8_t LedPcie; // GPIO number for PCIE results

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1264

uint8_t LedError; // GPIO number for Error Cases

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1265

uint8_t LedSpare1[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1270

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1271

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1275

uint8_t DfllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1276

uint8_t DfllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1284

uint8_t FclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1285

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1291

uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1292

uint8_t PaddingMem1[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1299

uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1300

uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1306

uint8_t HsrEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1307

uint8_t VddqOffEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1308

uint8_t PaddingUmcFlags[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1311

uint8_t UclkSpreadPercent[16];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1356

uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1357

uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1360

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1361

uint8_t FanZeroRpmStopTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1362

uint8_t FanMode;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1363

uint8_t Padding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1386

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1387

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1388

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1389

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1404

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1405

uint8_t CurrFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1410

uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1411

uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1412

uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1421

uint8_t PcieRate ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1422

uint8_t PcieWidth ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1441

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1442

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1443

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1444

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1458

uint8_t ThrottlingPercentage[THROTTLER_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1461

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1462

uint8_t CurrFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1467

uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1468

uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1469

uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1478

uint8_t PcieRate ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1479

uint8_t PcieWidth ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1498

uint8_t CurrSocVoltageOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1499

uint8_t CurrGfxVoltageOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1500

uint8_t CurrMemVidOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1501

uint8_t Padding8;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1515

uint8_t ThrottlingPercentage[THROTTLER_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1518

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1519

uint8_t CurrFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1524

uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1525

uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1526

uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1536

uint8_t PcieRate;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1537

uint8_t PcieWidth;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1558

uint8_t CurrSocVoltageOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1559

uint8_t CurrGfxVoltageOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1560

uint8_t CurrMemVidOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1561

uint8_t Padding8;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1575

uint8_t ThrottlingPercentage[THROTTLER_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1578

uint8_t LinkDpmLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1579

uint8_t CurrFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1584

uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1585

uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1586

uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1596

uint8_t PcieRate;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1597

uint8_t PcieWidth;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1600

uint8_t ApuSTAPMSmartShiftLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1601

uint8_t AverageApuSocketPower;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1602

uint8_t ApuSTAPMLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1603

uint8_t Padding8_2;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1626

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1627

uint8_t Flags;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1628

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1672

uint8_t AvfsVersion;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1673

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1675

uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1677

uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1678

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1680

uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1681

uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1682

uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1683

uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1728

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1729

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1730

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1731

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1732

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1733

uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1743

uint8_t Fclk_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1744

uint8_t Fclk_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1745

uint8_t Fclk_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1746

uint8_t Fclk_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1747

uint8_t Fclk_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1748

uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1758

uint8_t Mem_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1759

uint8_t Mem_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1760

uint8_t Mem_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1761

uint8_t Mem_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1762

uint8_t Mem_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1763

uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1774

uint8_t Mem_UpHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1775

uint8_t Mem_DownHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

343

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

344

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

345

uint8_t SlaveAddress;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

346

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

347

uint8_t ControllerName;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

348

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

349

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

350

uint8_t PaddingConfig;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

388

uint8_t ReadWriteData; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

389

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

393

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

394

uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

395

uint8_t SlaveAddress; //Slave address of device

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

396

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

552

uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

553

uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

554

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

555

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

625

uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

626

uint8_t TotalPowerPadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

655

uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

656

uint8_t paddingRlcUlvParams[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

698

uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

713

uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

714

uint8_t GfxclkPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

717

uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

718

uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

719

uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

720

uint8_t GfxGpoPadding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

744

uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

745

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

747

uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

756

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

757

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

774

uint8_t FanTempInputSelect;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

775

uint8_t FanPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

776

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

777

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

787

uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

788

uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

789

uint8_t Padding8_Avfs;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

803

uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

804

uint8_t Padding8_GfxBtc[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

812

uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

813

uint8_t XgmiDpmSpare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

823

uint8_t CustomerVariant;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

826

uint8_t VcBtcEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

850

uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

851

uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

852

uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

853

uint8_t I2cSpare[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

856

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

857

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

858

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

859

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

861

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

862

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

863

uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

864

uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

869

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

873

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

877

uint8_t Padding_TelemetryMem0;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

881

uint8_t Padding_TelemetryMem1;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

886

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

887

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

888

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

889

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

891

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

892

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

893

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

894

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

897

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

898

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

899

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

900

uint8_t LedEnableMask;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

902

uint8_t LedPcie; // GPIO number for PCIE results

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

903

uint8_t LedError; // GPIO number for Error Cases

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

904

uint8_t LedSpare1[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

909

uint8_t PllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

910

uint8_t PllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

914

uint8_t DfllGfxclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

915

uint8_t DfllGfxclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

923

uint8_t FclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

924

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

930

uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

931

uint8_t PaddingMem1[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

938

uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

939

uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

945

uint8_t HsrEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

946

uint8_t VddqOffEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

947

uint8_t PaddingUmcFlags[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

950

uint8_t UclkSpreadPercent[16];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

985

uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

986

uint8_t TotalPowerPadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

143

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

144

uint8_t NumDcfclkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

145

uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

146

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

148

uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

149

uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

150

uint8_t spare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

55

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

56

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

57

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

88

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

89

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

90

uint8_t FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

91

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

124

uint8_t NumDcfClkDpmEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

125

uint8_t NumSocClkDpmEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

126

uint8_t NumFClkDpmEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

127

uint8_t NumMemClkDpmEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

128

uint8_t NumVClkDpmEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

129

uint8_t NumDClkDpmEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

130

uint8_t spare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

56

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

57

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

58

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

89

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

90

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

91

uint8_t FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

92

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

168

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

169

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

170

uint8_t SlaveAddress;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

171

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

172

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

173

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

174

uint8_t PaddingConfig[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

207

uint8_t ReadWriteData; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

208

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

212

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

213

uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

214

uint8_t SlaveAddress; //Slave address of device

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

215

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

265

uint8_t StartupLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

266

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

298

uint8_t DidTableVclk[NUM_VCLK_DPM_LEVELS]; //PPCLK_VCLK

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

299

uint8_t DidTableDclk[NUM_DCLK_DPM_LEVELS]; //PPCLK_DCLK

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

300

uint8_t DidTableSocclk[NUM_SOCCLK_DPM_LEVELS]; //PPCLK_SOCCLK

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

301

uint8_t DidTableLclk[NUM_LCLK_DPM_LEVELS]; //PPCLK_LCLK

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

303

uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

305

uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

311

uint8_t StartupSmnclkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

312

uint8_t StartupMp0clkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

313

uint8_t StartupMp1clkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

314

uint8_t StartupWaflclkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

315

uint8_t StartupGfxavfsclkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

316

uint8_t StartupMpioclkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

317

uint8_t StartupDxioclkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

318

uint8_t spare123;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

320

uint8_t StartupVidGpu0Svi0Plane0; //VDDCR_GFX0

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

321

uint8_t StartupVidGpu0Svi0Plane1; //VDDCR_SOC

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

322

uint8_t StartupVidGpu0Svi1Plane0; //VDDCR_HBM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

323

uint8_t StartupVidGpu0Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

325

uint8_t StartupVidGpu1Svi0Plane0; //VDDCR_GFX1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

326

uint8_t StartupVidGpu1Svi0Plane1; //UNUSED [0 = plane is not used and should not be programmed]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

327

uint8_t StartupVidGpu1Svi1Plane0; //UNUSED [0 = plane is not used and should not be programmed]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

328

uint8_t StartupVidGpu1Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

335

uint8_t GfxclkSource; // GfxclkSrc_e [0 = PLL, 1 = DFLL]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

336

uint8_t spare1[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

337

uint8_t StartupGfxclkDid;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

358

uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

359

uint8_t XgmiLinkWidth[NUM_XGMI_DPM_LEVELS]; //Width [EX: 16 = x16]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

360

uint8_t XgmiStartupLevel;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

361

uint8_t spare12[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

401

uint8_t Padding_TelemetryGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

405

uint8_t Padding_TelemetrySoc;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

409

uint8_t Padding_TelemetryMem;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

413

uint8_t Padding_TelemetryBoardInput;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

420

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

421

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

422

uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

423

uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

426

uint8_t UclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

427

uint8_t UclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

431

uint8_t FclkSpreadEnabled; // on or off

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

432

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

439

uint8_t GpioI2cScl; // Serial Clock

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

440

uint8_t GpioI2cSda; // Serial Data

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

445

uint8_t Padding_TelemetryXgmi;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

479

uint8_t CurrSocVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

480

uint8_t CurrGfxVoltageOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

481

uint8_t CurrMemVidOffset ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

482

uint8_t Padding8 ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1028

uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1029

uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1059

uint8_t GfxclkSpare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1067

uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1068

uint8_t GfxIdlePadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1070

uint8_t SmsRepairWRCKClkDivEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1071

uint8_t SmsRepairWRCKClkDivVal;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1072

uint8_t GfxOffEntryEarlyMGCGEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1073

uint8_t GfxOffEntryForceCGCGEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1074

uint8_t GfxOffEntryForceCGCGDelayEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1075

uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1078

uint8_t GfxIdlePadding2[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1109

uint8_t FoptEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1110

uint8_t DcsSpare2[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1118

uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1119

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1121

uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1122

uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1129

uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1136

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1137

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1154

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1155

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1177

uint8_t FanIntakeSensorSupport;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1178

uint8_t FanIntakePadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1183

uint8_t OverrideGfxAvfsFuses;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1184

uint8_t GfxAvfsPadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1216

uint8_t OverrideSocAvfsFuses;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1217

uint8_t MinSocAvfsRevision;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1218

uint8_t SocAvfsPadding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1250

uint8_t TotalBoardPowerSupport;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1251

uint8_t TotalBoardPowerPadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1285

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1286

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1287

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1288

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1290

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1291

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1292

uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1293

uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1296

uint8_t SlaveAddrMapping[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1297

uint8_t VrPsiSupport[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1299

uint8_t PaddingPsi[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1300

uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1306

uint8_t DownSlewRateVr[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1310

uint8_t LedOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1311

uint8_t FanOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1312

uint8_t GfxVrPowerStageOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1314

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1315

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1316

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1317

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1319

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1320

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1323

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1324

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1325

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1326

uint8_t LedEnableMask;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1328

uint8_t LedPcie; // GPIO number for PCIE results

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1329

uint8_t LedError; // GPIO number for Error Cases

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1334

uint8_t UclkTrainingModeSpreadPercent;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1335

uint8_t UclkSpreadPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1339

uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1341

uint8_t GfxclkSpreadEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1344

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1348

uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1349

uint8_t PaddingMem1[7];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1352

uint8_t HsrEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1353

uint8_t VddqOffEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1354

uint8_t PaddingUmcFlags[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1359

uint8_t FuseWritePowerMuxPresent;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1360

uint8_t FuseWritePadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1459

uint8_t PcieRate ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1460

uint8_t PcieWidth ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1462

uint8_t AvgFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1463

uint8_t Padding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1467

uint8_t ThrottlingPercentage[THROTTLER_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1468

uint8_t VmaxThrottlingPercentage;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1469

uint8_t Padding1[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1496

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1497

uint8_t Flags;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1498

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1538

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1539

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1540

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1541

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1542

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1543

uint8_t PaddingGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1553

uint8_t Fclk_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1554

uint8_t Fclk_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1555

uint8_t Fclk_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1556

uint8_t Fclk_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1557

uint8_t Fclk_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1558

uint8_t PaddingFclk;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1569

uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1570

uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1572

uint8_t padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

320

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

321

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

322

uint8_t SlaveAddress;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

323

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

324

uint8_t ControllerName;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

325

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

326

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

327

uint8_t PaddingConfig;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

360

uint8_t ReadWriteData; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

361

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

365

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

366

uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

367

uint8_t SlaveAddress; //Slave address of device

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

368

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

502

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

503

uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

504

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

505

uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

684

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

714

uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

715

uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

720

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

721

uint8_t FanZeroRpmStopTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

722

uint8_t FanMode;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

723

uint8_t MaxOpTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

751

uint8_t FanLinearPwmPoints;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

752

uint8_t FanLinearTempPoints;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

757

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

758

uint8_t FanZeroRpmStopTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

759

uint8_t FanMode;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

760

uint8_t MaxOpTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

850

uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

852

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

880

uint8_t PwmLimitMin;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

881

uint8_t PwmLimitMax;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

882

uint8_t FanTargetTemperature;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

883

uint8_t Spare1[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

916

uint8_t DcBtcEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

917

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

947

uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

948

uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

949

uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

950

uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

960

uint8_t EnableLegacyPptLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

961

uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

962

uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

964

uint8_t PaddingPpt[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

116

uint8_t WckRatio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

117

uint8_t Spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

132

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

133

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

134

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

135

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

136

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

137

uint8_t spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

56

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

57

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

58

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

89

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

90

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

91

uint8_t FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

92

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

119

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

120

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

121

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

122

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

123

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

124

uint8_t spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

56

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

57

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

58

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

157

uint8_t ReadWriteData; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

158

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

162

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

163

uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

164

uint8_t SlaveAddress; //Slave address of device

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

165

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1037

uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1038

uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1068

uint8_t GfxclkSpare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1076

uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1077

uint8_t GfxIdlePadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1079

uint8_t SmsRepairWRCKClkDivEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1080

uint8_t SmsRepairWRCKClkDivVal;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1081

uint8_t GfxOffEntryEarlyMGCGEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1082

uint8_t GfxOffEntryForceCGCGEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1083

uint8_t GfxOffEntryForceCGCGDelayEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1084

uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1087

uint8_t GfxIdlePadding2[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1120

uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1121

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1123

uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1124

uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1131

uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1138

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1139

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1156

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1157

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1179

uint8_t FanIntakeSensorSupport;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1180

uint8_t FanIntakePadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1184

uint8_t OverrideGfxAvfsFuses;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1185

uint8_t GfxAvfsPadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1216

uint8_t OverrideSocAvfsFuses;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1217

uint8_t MinSocAvfsRevision;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1218

uint8_t SocAvfsPadding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1250

uint8_t TotalBoardPowerSupport;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1251

uint8_t TotalBoardPowerPadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1279

uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1280

uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1281

uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1282

uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1284

uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1285

uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1286

uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1287

uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1290

uint8_t SlaveAddrMapping[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1291

uint8_t VrPsiSupport[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1293

uint8_t PaddingPsi[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1294

uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1300

uint8_t DownSlewRateVr[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1304

uint8_t LedOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1305

uint8_t FanOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1306

uint8_t GfxVrPowerStageOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1308

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1309

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1310

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1311

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1313

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1314

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1317

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1318

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1319

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1320

uint8_t LedEnableMask;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1322

uint8_t LedPcie; // GPIO number for PCIE results

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1323

uint8_t LedError; // GPIO number for Error Cases

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1328

uint8_t UclkTrainingModeSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1329

uint8_t UclkSpreadPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1333

uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1336

uint8_t FclkSpreadPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1337

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1341

uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1342

uint8_t PaddingMem1[7];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1345

uint8_t HsrEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1346

uint8_t VddqOffEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1347

uint8_t PaddingUmcFlags[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1352

uint8_t FuseWritePowerMuxPresent;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1353

uint8_t FuseWritePadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1452

uint8_t PcieRate ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1453

uint8_t PcieWidth ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1455

uint8_t AvgFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1456

uint8_t Padding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1460

uint8_t ThrottlingPercentage[THROTTLER_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1486

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1487

uint8_t Flags;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1488

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1528

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1529

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1530

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1531

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1532

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1533

uint8_t PaddingGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1543

uint8_t Fclk_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1544

uint8_t Fclk_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1545

uint8_t Fclk_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1546

uint8_t Fclk_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1547

uint8_t Fclk_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1548

uint8_t PaddingFclk;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1559

uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1560

uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1562

uint8_t padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

321

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

322

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

323

uint8_t SlaveAddress;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

324

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

325

uint8_t ControllerName;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

326

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

327

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

328

uint8_t PaddingConfig;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

361

uint8_t ReadWriteData; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

362

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

366

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

367

uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

368

uint8_t SlaveAddress; //Slave address of device

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

369

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

503

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

504

uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

505

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

506

uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

678

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

724

uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

725

uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

730

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

731

uint8_t FanZeroRpmStopTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

732

uint8_t FanMode;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

733

uint8_t MaxOpTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

734

uint8_t Padding[4];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

762

uint8_t FanLinearPwmPoints;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

763

uint8_t FanLinearTempPoints;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

768

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

769

uint8_t FanZeroRpmStopTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

770

uint8_t FanMode;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

771

uint8_t MaxOpTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

772

uint8_t Padding[4];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

859

uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

861

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

889

uint8_t PwmLimitMin;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

890

uint8_t PwmLimitMax;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

891

uint8_t FanTargetTemperature;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

892

uint8_t Spare1[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

925

uint8_t DcBtcEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

926

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

956

uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

957

uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

958

uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

959

uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

969

uint8_t EnableLegacyPptLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

970

uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

971

uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

973

uint8_t PaddingPpt[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

115

uint8_t WckRatio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

116

uint8_t Spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

131

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

132

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

133

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

134

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

135

uint8_t NumDfPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

136

uint8_t spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

55

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

56

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

57

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

88

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

89

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

90

uint8_t FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

91

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1016

uint8_t DcBtcEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1017

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1039

uint8_t Version;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1040

uint8_t Spare8[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1056

uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1057

uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1058

uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1059

uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1062

uint8_t SocketPowerLimitSpare[10];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1066

uint8_t EnableLegacyPptLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1067

uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1069

uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1071

uint8_t PaddingPpt[7];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1096

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1127

uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1128

uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1163

uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1164

uint8_t GfxIdlePadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1166

uint8_t SmsRepairWRCKClkDivEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1167

uint8_t SmsRepairWRCKClkDivVal;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1168

uint8_t GfxOffEntryEarlyMGCGEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1169

uint8_t GfxOffEntryForceCGCGEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1170

uint8_t GfxOffEntryForceCGCGDelayEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1171

uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1174

uint8_t GfxIdlePadding2[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1209

uint8_t FoptEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1210

uint8_t DcsSpare2[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1216

uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1217

uint8_t PaddingMem[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1219

uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 6 Primary SW DPM states (6 + 6 Shadow)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1220

uint8_t UclkDpmShadowPstates [NUM_UCLK_DPM_LEVELS]; // 6 Shadow SW DPM states (6 + 6 Shadow)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1221

uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1222

uint8_t FreqTableShadowUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1226

uint8_t PaddingsMem[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1231

uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 4:PciE-gen5

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1232

uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1236

uint8_t OverrideGfxAvfsFuses;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1237

uint8_t GfxAvfsPadding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1282

uint8_t OverrideSocAvfsFuses;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1283

uint8_t MinSocAvfsRevision;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1284

uint8_t SocAvfsPadding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1315

uint8_t TotalBoardPowerSupport;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1316

uint8_t TotalBoardPowerPadding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1347

uint8_t PsmDidtAvgDiv;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1348

uint8_t PsmDidtForceStall;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1377

uint8_t XVmin_Soc_EdcInitPccStep; // 3 bit, First Pcc Step number that will applied when PCC asserts.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1378

uint8_t PaddingSocEdc[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1381

uint8_t GfxXvminFuseOverride;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1382

uint8_t SocXvminFuseOverride;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1383

uint8_t PaddingXvminFuseOverride[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1384

uint8_t GfxXvminFddTempLow; // bit 7: sign, bit 0-6: ABS value

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1385

uint8_t GfxXvminFddTempHigh; // bit 7: sign, bit 0-6: ABS value

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1386

uint8_t SocXvminFddTempLow; // bit 7: sign, bit 0-6: ABS value

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1387

uint8_t SocXvminFddTempHigh; // bit 7: sign, bit 0-6: ABS value

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1408

uint8_t SlewRateConditions;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1409

uint8_t LoadLineAdjust;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1410

uint8_t VoutOffset;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1411

uint8_t VidMax;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1412

uint8_t VidMin;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1413

uint8_t TenBitTelEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1414

uint8_t SixteenBitTelEn;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1415

uint8_t OcpThresh;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1416

uint8_t OcpWarnThresh;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1417

uint8_t OcpSettings;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1418

uint8_t VrhotThresh;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1419

uint8_t OtpThresh;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1420

uint8_t UvpOvpDeltaRef;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1421

uint8_t PhaseShed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1422

uint8_t Padding[10];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1434

uint8_t SlaveAddrMapping[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1435

uint8_t VrPsiSupport[SVI_PLANE_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1438

uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1444

uint8_t LedOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1445

uint8_t FanOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1446

uint8_t GfxVrPowerStageOffGpio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1448

uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1449

uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1450

uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1451

uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1453

uint8_t GthrGpio; // GPIO pin configured for GTHR Event

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1454

uint8_t GthrPolarity; // replace GPIO polarity for GTHR

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1457

uint8_t LedPin0; // GPIO number for LedPin[0]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1458

uint8_t LedPin1; // GPIO number for LedPin[1]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1459

uint8_t LedPin2; // GPIO number for LedPin[2]

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1460

uint8_t LedEnableMask;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1462

uint8_t LedPcie; // GPIO number for PCIE results

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1463

uint8_t LedError; // GPIO number for Error Cases

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1464

uint8_t PaddingLed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1469

uint8_t UclkTrainingModeSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1470

uint8_t UclkSpreadPadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1474

uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1477

uint8_t GfxclkSpreadEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1480

uint8_t FclkSpreadPercent; // Q4.4

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1484

uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1485

uint8_t PaddingMem1[7];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1488

uint8_t HsrEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1489

uint8_t VddqOffEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1490

uint8_t PaddingUmcFlags[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1495

uint8_t FuseWritePowerMuxPresent;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1496

uint8_t FuseWritePadding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1507

uint8_t EpcsSens0; //GPIO number for External Power Connector Support Sense0

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1508

uint8_t EpcsSens1; //GPIO Number for External Power Connector Support Sense1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1509

uint8_t PaddingEpcs[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1546

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1547

uint8_t FanTachEdgePerRev;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1570

uint8_t FanIntakeSensorSupport;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1571

uint8_t FanIntakePadding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1701

uint8_t PcieRate ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1702

uint8_t PcieWidth ;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1704

uint8_t AvgFanPwm;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1705

uint8_t Padding[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1709

uint8_t ThrottlingPercentage[THROTTLER_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1710

uint8_t VmaxThrottlingPercentage;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1711

uint8_t padding1[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1738

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1739

uint8_t Flags;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1740

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1782

uint8_t Gfx_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1783

uint8_t Gfx_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1784

uint8_t Gfx_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1785

uint8_t Gfx_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1786

uint8_t Gfx_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1787

uint8_t PaddingGfx;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1797

uint8_t Fclk_ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1798

uint8_t Fclk_IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1799

uint8_t Fclk_FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1800

uint8_t Fclk_MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1801

uint8_t Fclk_BoosterFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1802

uint8_t PaddingFclk;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1813

uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

321

uint8_t Enabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

322

uint8_t Speed;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

323

uint8_t SlaveAddress;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

324

uint8_t ControllerPort;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

325

uint8_t ControllerName;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

326

uint8_t ThermalThrotter;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

327

uint8_t I2cProtocol;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

328

uint8_t PaddingConfig;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

361

uint8_t ReadWriteData; //Return data for read. Data to send for write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

362

uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

366

uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

367

uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

368

uint8_t SlaveAddress; //Slave address of device

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

369

uint8_t NumCmds; //Number of commands

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

516

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

517

uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

518

uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

519

uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

687

uint8_t Padding;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

760

uint8_t IdlePwrSavingFeaturesCtrl;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

761

uint8_t RuntimePwrSavingFeaturesCtrl;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

777

uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

778

uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

783

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

784

uint8_t FanZeroRpmStopTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

785

uint8_t FanMode;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

786

uint8_t MaxOpTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

788

uint8_t AdvancedOdModeEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

789

uint8_t Padding2[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

802

uint8_t GfxclkFmaxVmaxTemperature;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

803

uint8_t Padding4[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

840

uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

841

uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

848

uint8_t FanZeroRpmEnable;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

850

uint8_t MaxOpTemp;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

851

uint8_t Padding1[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

949

uint8_t InitUclkLevel; // =0,1,2,3,4,5 frequency from FreqTableUclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

951

uint8_t Padding[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

980

uint8_t PwmLimitMin;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

981

uint8_t PwmLimitMax;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

982

uint8_t FanTargetTemperature;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

983

uint8_t Spare1[1];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

115

uint8_t WckRatio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

116

uint8_t Spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

134

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

135

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

136

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

137

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

138

uint8_t VpeClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

140

uint8_t NumMemPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

141

uint8_t NumFclkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

142

uint8_t spare[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

165

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

166

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

167

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

168

uint8_t Vcn0ClkLevelsEnabled; //Applies to both Vclk0 and Dclk0

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

169

uint8_t Vcn1ClkLevelsEnabled; //Applies to both Vclk1 and Dclk1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

170

uint8_t VpeClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

171

uint8_t NumMemPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

172

uint8_t NumFclkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

51

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

52

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

53

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

84

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

85

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

86

uint8_t FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

87

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

114

uint8_t WckRatio;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

115

uint8_t Spare[3];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

133

uint8_t NumDcfClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

134

uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

135

uint8_t NumSocClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

136

uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

138

uint8_t VpeClkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

139

uint8_t NumMemPstatesEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

140

uint8_t NumFclkLevelsEnabled;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

141

uint8_t spare;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

51

uint8_t WmSetting;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

52

uint8_t WmType; // Used for normal pstate change or memory retraining

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

53

uint8_t Padding[2];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

84

uint8_t ActiveHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

85

uint8_t IdleHystLimit;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

86

uint8_t FPS;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h

87

uint8_t MinActiveFreqType;

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

337

uint8_t ModelNumber[PRODUCT_MODEL_NUMBER_LEN];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

338

uint8_t Name[PRODUCT_NAME_LEN];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

339

uint8_t Serial[PRODUCT_SERIAL_LEN];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

340

uint8_t ManufacturerName[PRODUCT_MANUFACTURER_NAME_LEN];

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

341

uint8_t FruId[PRODUCT_FRU_ID_LEN];

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

115

uint8_t in_power_limit_boost_mode;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

121

uint8_t in_power_limit_boost_mode;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

135

uint8_t revision; //Revision = SMU_11_0_7_PP_OVERDRIVE_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

136

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

139

uint8_t cap[SMU_11_0_7_MAX_ODFEATURE]; //OD feature support flags

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

165

uint8_t revision; //Revision = SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

166

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

175

uint8_t table_revision; //For sienna_cichlid, table_revision = 2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

182

uint8_t thermal_controller_type; //one of SMU_11_0_7_PP_THERMALCONTROLLER

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

105

uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

106

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

109

uint8_t cap[SMU_11_0_MAX_ODFEATURE]; //OD feature support flags

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

130

uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

131

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

139

uint8_t table_revision;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

146

uint8_t thermal_controller_type; //one of SMU_11_0_PP_THERMALCONTROLLER

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

108

uint8_t in_power_limit_boost_mode;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

266

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

267

uint8_t pcie_width_cap);

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

144

uint8_t revision; //Revision = SMU_13_0_0_PP_OVERDRIVE_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

145

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

148

uint8_t cap[SMU_13_0_0_MAX_ODFEATURE]; //OD feature support flags

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

174

uint8_t table_revision; //For SMU13, table_revision = 2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

175

uint8_t padding;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

182

uint8_t thermal_controller_type; //one of SMU_13_0_0_PP_THERMALCONTROLLER

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

192

uint8_t padding1;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

144

uint8_t revision; //Revision = SMU_13_0_7_PP_OVERDRIVE_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

145

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

148

uint8_t cap[SMU_13_0_7_MAX_ODFEATURE]; //OD feature support flags

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

174

uint8_t table_revision; //For PLUM_BONITO, table_revision = 2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

175

uint8_t padding;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

182

uint8_t thermal_controller_type; //one of SMU_13_0_7_PP_THERMALCONTROLLER

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

192

uint8_t padding1;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

107

uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

108

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

111

uint8_t cap[SMU_13_0_MAX_ODFEATURE]; //OD feature support flags

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

132

uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

133

uint8_t reserve[3]; //Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

141

uint8_t table_revision;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

148

uint8_t thermal_controller_type; //one of SMU_13_0_PP_THERMALCONTROLLER

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

101

uint8_t in_power_limit_boost_mode;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

125

uint8_t revision; // Revision = SMU_14_0_2_PP_OVERDRIVE_VERSION

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

126

uint8_t reserve[3]; // Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

127

uint8_t cap[SMU_14_0_2_OVERDRIVE_TABLE_COUNT][SMU_14_0_2_MAX_ODFEATURE]; // OD feature support flags

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

143

uint8_t table_revision; // PPGen use only: table_revision = 3

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

144

uint8_t pptable_source; // PPGen UI dropdown box

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

158

uint8_t thermal_controller_type; // one of smu_14_0_2_PP_THERMALCONTROLLER

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

165

uint8_t reserve[143]; // Zero filled field reserved for future use

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

183

uint8_t revision;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

184

uint8_t reserve[3];

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

185

uint8_t cap[SMU_14_0_2_CUSTOM_ODCAP_COUNT];

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

192

uint8_t custom_table_revision;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

119

uint8_t in_power_limit_boost_mode;

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

82

uint8_t pcie_gen[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

83

uint8_t pcie_lane[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

228

static const uint8_t arcturus_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

510

(uint8_t **)&smc_dpm_table);

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

54

uint8_t pcie_gen[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

55

uint8_t pcie_lane[MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2187

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2188

uint8_t pcie_width_cap)

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

242

static const uint8_t navi1x_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2655

uint8_t umc_fw_greater_than_v136 = false;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2656

uint8_t umc_fw_disable_cdr = false;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

415

(uint8_t **)&smc_dpm_table);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

435

(uint8_t **)&smc_dpm_table_v4_7);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2099

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2100

uint8_t pcie_width_cap)

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2104

uint8_t *table_member1, *table_member2;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2105

uint8_t min_gen_speed, max_gen_speed;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2106

uint8_t min_lane_width, max_lane_width;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2114

min_gen_speed = max_t(uint8_t, 0, table_member1[0]);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2118

min_lane_width = max_t(uint8_t, 1, table_member2[0]);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

259

static const uint8_t sienna_cichlid_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

449

(uint8_t **)&smc_dpm_table);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1032

static uint16_t convert_to_vddc(uint8_t vid)

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1048

vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

199

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

280

*table = (uint8_t *)v2 + ppt_offset_bytes;

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

296

((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

300

*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

319

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

352

(uint8_t **)&table);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

499

uint8_t clk_id,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

500

uint8_t syspll_id,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

528

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

537

(uint8_t **)&header);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

586

(uint8_t)SMU11_SYSPLL0_SOCCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

587

(uint8_t)0,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

591

(uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

592

(uint8_t)0,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

596

(uint8_t)SMU11_SYSPLL0_ECLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

597

(uint8_t)0,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

601

(uint8_t)SMU11_SYSPLL0_VCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

602

(uint8_t)0,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

606

(uint8_t)SMU11_SYSPLL0_DCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

607

(uint8_t)0,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

613

(uint8_t)SMU11_SYSPLL1_0_FCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

614

(uint8_t)SMU11_SYSPLL1_2_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

618

(uint8_t)SMU11_SYSPLL3_1_LCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

619

(uint8_t)SMU11_SYSPLL3_1_ID,

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

212

static const uint8_t vangogh_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2231

uint8_t aon_bits = 0;

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

131

static const uint8_t renoir_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

287

uint8_t clk_id,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

288

uint8_t syspll_id,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

316

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

325

(uint8_t **)&header);

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

374

(uint8_t)SMU12_SYSPLL0_SOCCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

375

(uint8_t)SMU12_SYSPLL0_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

379

(uint8_t)SMU12_SYSPLL1_DCFCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

380

(uint8_t)SMU12_SYSPLL1_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

384

(uint8_t)SMU12_SYSPLL0_VCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

385

(uint8_t)SMU12_SYSPLL0_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

389

(uint8_t)SMU12_SYSPLL0_DCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

390

(uint8_t)SMU12_SYSPLL0_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

396

(uint8_t)SMU12_SYSPLL3_0_FCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

397

(uint8_t)SMU12_SYSPLL3_0_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

401

(uint8_t)SMU12_SYSPLL0_LCLK_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

402

(uint8_t)SMU12_SYSPLL0_ID,

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

77

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

213

static const uint8_t aldebaran_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

501

(uint8_t **)&smc_dpm_table);

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

54

uint8_t pcie_gen[ALDEBARAN_MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

55

uint8_t pcie_lane[ALDEBARAN_MAX_PCIE_CONF];

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1033

static uint16_t convert_to_vddc(uint8_t vid)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1049

vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2384

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2385

uint8_t pcie_width_cap)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

265

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

313

*table = (uint8_t *)v2 + ppt_offset_bytes;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

329

((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

333

*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

349

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

357

(uint8_t **)table);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

582

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

594

(uint8_t **)&header);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

657

(uint8_t **)&header)) {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

275

static const uint8_t smu_v13_0_0_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3070

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3071

uint8_t pcie_width_cap)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

410

(uint8_t **)&smc_dpm_table);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

261

uint8_t max_width;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

265

max_width = (uint8_t)static_metrics->MaxXgmiWidth;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

273

max_width = (uint8_t)metrics->XgmiWidth;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

236

static const uint8_t smu_v13_0_6_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

527

*)((uint8_t *)v2_1 +

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

533

((uint8_t *)v2_1 +

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

885

uint8_t max_width;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

925

max_width = (uint8_t)GET_METRIC_FIELD(XgmiWidth, version);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

264

static const uint8_t smu_v13_0_7_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2698

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2699

uint8_t pcie_width_cap)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

444

(uint8_t **)&smc_dpm_table);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

236

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

302

*table = (uint8_t *)v2 + ppt_offset_bytes;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

318

((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

322

*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

338

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

346

(uint8_t **)table);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

566

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

578

(uint8_t **)&header);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

641

(uint8_t **)&header)) {

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1581

uint8_t idx;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1600

uint8_t idx;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1384

uint8_t pcie_gen_cap,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1385

uint8_t pcie_width_cap)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

251

static const uint8_t smu_v14_0_2_throttler_map[] = {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

214

uint8_t smu_program, smu_major, smu_minor, smu_debug;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

272

*table = (uint8_t *)v2 + ppt_offset_bytes;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

288

((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

292

*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

308

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

316

(uint8_t **)table);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

536

uint8_t frev, crev;

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

548

(uint8_t **)&header);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

611

(uint8_t **)&header)) {

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

1394

uint8_t idx;

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

805

const uint8_t *throttler_map)

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

808

uint8_t dep_bit = 0;

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

148

const uint8_t *throttler_map);

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

266

uint8_t frev, uint8_t crev) \

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

219

ras_ta_param->vram_type = (uint8_t)adev->gmc.vram_type;

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c

149

uint8_t i;

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c

189

uint8_t *out_buf;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.c

206

uint8_t *buffer;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

160

uint8_t input_buff_raw[RAS_CMD_MAX_IN_SIZE];

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

161

uint8_t output_buff_raw[];

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

274

uint8_t interface_type;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

275

uint8_t rsv[3];

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

399

uint8_t trace_num;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

400

uint8_t rsv;

drivers/gpu/drm/amd/ras/rascore/ras_cper.c

189

descriptor = (struct cper_section_descriptor *)((uint8_t *)hdr +

drivers/gpu/drm/amd/ras/rascore/ras_cper.c

191

runtime = (struct cper_section_runtime *)((uint8_t *)hdr +

drivers/gpu/drm/amd/ras/rascore/ras_cper.c

204

uint8_t *buffer, struct ras_log_info **trace_arr, uint32_t arr_num)

drivers/gpu/drm/amd/ras/rascore/ras_cper.c

275

uint8_t *buf, uint32_t buf_len, uint32_t *real_data_len)

drivers/gpu/drm/amd/ras/rascore/ras_cper.c

277

uint8_t *buffer = buf;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

103

uint8_t seconds;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

104

uint8_t minutes;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

105

uint8_t hours;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

106

uint8_t flag;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

107

uint8_t day;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

108

uint8_t month;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

109

uint8_t year;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

110

uint8_t century;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

137

uint8_t reserved[12]; /* Reserved */

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

143

uint8_t revision_minor; /* CPER_SEC_MINOR_REV_1 */

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

144

uint8_t revision_major; /* CPER_SEC_MAJOR_REV_22 */

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

147

uint8_t fru_id : 1;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

148

uint8_t fru_text : 1;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

149

uint8_t reserved : 6;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

151

uint8_t valid_mask;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

153

uint8_t reserved;

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

29

uint8_t b[CPER_UUID_MAX_SIZE];

drivers/gpu/drm/amd/ras/rascore/ras_cper.h

303

uint8_t *buf, uint32_t buf_len, uint32_t *real_data_len);

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

122

uint8_t *bin_addr;

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

48

uint8_t poison_mode_en;

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

49

uint8_t dgpu_mode;

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

51

uint8_t channel_dis_num;

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

52

uint8_t nps_mode;

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

54

uint8_t vram_type;

drivers/gpu/drm/amd/ras/rascore/ras_psp.h

93

uint8_t *bin_addr;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

164

uint8_t poison_mode_en;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

165

uint8_t dgpu_mode;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

167

uint8_t channel_dis_num;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

168

uint8_t nps_mode;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

170

uint8_t vram_type;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

194

uint8_t ras_init_success_flag;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

195

uint8_t err_inject_switch_disable_flag;

drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h

196

uint8_t reg_access_failure_flag;

drivers/gpu/drm/armada/armada_fb.c

27

uint8_t format, config;

drivers/gpu/drm/armada/armada_fb.h

12

uint8_t fmt;

drivers/gpu/drm/armada/armada_fb.h

13

uint8_t mod;

drivers/gpu/drm/bridge/adv7511/adv7511.h

365

uint8_t edid_buf[256];

drivers/gpu/drm/bridge/adv7511/adv7511_drv.c

46

static const uint8_t adv7511_register_defaults[] = {

drivers/gpu/drm/bridge/adv7511/adv7511_drv.c

521

uint8_t offset;

drivers/gpu/drm/bridge/lontium-lt9611uxc.c

63

uint8_t fw_version;

drivers/gpu/drm/bridge/sii902x.c

800

uint8_t *buf, size_t len)

drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c

134

static int dw_hdmi_i2s_get_eld(struct device *dev, void *data, uint8_t *buf,

drivers/gpu/drm/bridge/tda998x_drv.c

1153

uint8_t *buf, size_t len)

drivers/gpu/drm/display/drm_dp_aux_dev.c

158

uint8_t buf[DP_AUX_MAX_PAYLOAD_BYTES];

drivers/gpu/drm/display/drm_dp_aux_dev.c

201

uint8_t buf[DP_AUX_MAX_PAYLOAD_BYTES];

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

170

static bool is_type1_adaptor(uint8_t adaptor_id)

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

175

static bool is_type2_adaptor(uint8_t adaptor_id)

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

182

const uint8_t adaptor_id)

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

209

uint8_t adaptor_id = 0x00;

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

280

uint8_t max_tmds_clock;

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

326

uint8_t tmds_oen;

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

364

uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE;

drivers/gpu/drm/display/drm_dp_dual_mode_helper.c

376

uint8_t tmp;

drivers/gpu/drm/display/drm_dp_helper.c

1682

uint8_t rev[2];

drivers/gpu/drm/display/drm_dp_mst_topology.c

207

static u8 drm_dp_msg_header_crc4(const uint8_t *data, size_t num_nibbles)

drivers/gpu/drm/display/drm_dp_mst_topology.c

241

static u8 drm_dp_msg_data_crc4(const uint8_t *data, u8 number_of_bytes)

drivers/gpu/drm/display/drm_dp_mst_topology.c

4740

void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap)

drivers/gpu/drm/display/drm_hdmi_audio_helper.c

84

uint8_t *buf, size_t len)

drivers/gpu/drm/drm_cache.c

53

uint8_t *page_virtual;

drivers/gpu/drm/drm_edid.c

5444

static uint8_t eotf_supported(const u8 *edid_ext)

drivers/gpu/drm/drm_edid.c

5453

static uint8_t hdr_metadata_type(const u8 *edid_ext)

drivers/gpu/drm/drm_edid.c

5680

uint8_t *eld = connector->eld;

drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c

140

static uint8_t cmd_length[32] = {

drivers/gpu/drm/exynos/exynos_hdmi.c

1645

static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1204

uint8_t *recv, int recv_bytes)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1237

static uint8_t

drivers/gpu/drm/gma500/cdv_intel_dp.c

1238

cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1244

static uint8_t

drivers/gpu/drm/gma500/cdv_intel_dp.c

1245

cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1252

uint8_t l = cdv_intel_dp_link_status(link_status, i);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1257

static uint8_t

drivers/gpu/drm/gma500/cdv_intel_dp.c

1258

cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1265

uint8_t l = cdv_intel_dp_link_status(link_status, i);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1276

uint8_t v = 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1277

uint8_t p = 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1281

uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1282

uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1301

static uint8_t

drivers/gpu/drm/gma500/cdv_intel_dp.c

1302

cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1307

uint8_t l = cdv_intel_dp_link_status(link_status, i);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1314

cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1317

uint8_t lane_status;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1335

uint8_t lane_align;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1336

uint8_t lane_status;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1354

uint8_t dp_train_pat)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1379

uint8_t dp_train_pat)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1398

cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1469

uint8_t voltage;

drivers/gpu/drm/gma500/cdv_intel_dp.c

258

uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];

drivers/gpu/drm/gma500/cdv_intel_dp.c

262

uint8_t link_bw;

drivers/gpu/drm/gma500/cdv_intel_dp.c

263

uint8_t lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

264

uint8_t dpcd[4];

drivers/gpu/drm/gma500/cdv_intel_dp.c

268

uint8_t train_set[4];

drivers/gpu/drm/gma500/cdv_intel_dp.c

269

uint8_t link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/gma500/cdv_intel_dp.c

357

cdv_intel_dp_link_clock(uint8_t link_bw)

drivers/gpu/drm/gma500/cdv_intel_dp.c

544

pack_aux(uint8_t *src, int src_bytes)

drivers/gpu/drm/gma500/cdv_intel_dp.c

557

unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)

drivers/gpu/drm/gma500/cdv_intel_dp.c

568

uint8_t *send, int send_bytes,

drivers/gpu/drm/gma500/cdv_intel_dp.c

569

uint8_t *recv, int recv_size)

drivers/gpu/drm/gma500/cdv_intel_dp.c

57

int mode, uint8_t write_byte,

drivers/gpu/drm/gma500/cdv_intel_dp.c

58

uint8_t *read_byte);

drivers/gpu/drm/gma500/cdv_intel_dp.c

64

uint8_t write_byte, uint8_t *read_byte)

drivers/gpu/drm/gma500/cdv_intel_dp.c

670

uint16_t address, uint8_t *send, int send_bytes)

drivers/gpu/drm/gma500/cdv_intel_dp.c

673

uint8_t msg[20];

drivers/gpu/drm/gma500/cdv_intel_dp.c

675

uint8_t ack;

drivers/gpu/drm/gma500/cdv_intel_dp.c

703

uint16_t address, uint8_t byte)

drivers/gpu/drm/gma500/cdv_intel_dp.c

711

uint16_t address, uint8_t *recv, int recv_bytes)

drivers/gpu/drm/gma500/cdv_intel_dp.c

713

uint8_t msg[4];

drivers/gpu/drm/gma500/cdv_intel_dp.c

715

uint8_t reply[20];

drivers/gpu/drm/gma500/cdv_intel_dp.c

717

uint8_t ack;

drivers/gpu/drm/gma500/cdv_intel_dp.c

749

uint8_t write_byte, uint8_t *read_byte)

drivers/gpu/drm/gma500/cdv_intel_dp.c

757

uint8_t msg[5];

drivers/gpu/drm/gma500/cdv_intel_dp.c

758

uint8_t reply[2];

drivers/gpu/drm/gma500/intel_bios.c

52

uint8_t panel_type;

drivers/gpu/drm/gma500/mid_bios.c

108

dev_priv->platform_rev_id = (uint8_t) platform_rev_id;

drivers/gpu/drm/gma500/mmu.c

268

uint8_t *clf;

drivers/gpu/drm/gma500/mmu.c

284

clf = (uint8_t *) v;

drivers/gpu/drm/gma500/psb_drv.h

409

uint8_t __iomem *sgx_reg;

drivers/gpu/drm/gma500/psb_drv.h

410

uint8_t __iomem *vdc_reg;

drivers/gpu/drm/gma500/psb_drv.h

411

uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */

drivers/gpu/drm/gma500/psb_drv.h

441

uint8_t platform_rev_id;

drivers/gpu/drm/gma500/psb_drv.h

445

uint8_t __iomem *gmbus_reg;

drivers/gpu/drm/gma500/psb_drv.h

536

uint8_t panel_type;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

136

uint8_t ddc_bus;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1599

uint8_t cmd;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

846

uint8_t mode)

drivers/gpu/drm/gma500/psb_intel_sdvo.c

852

uint8_t mode)

drivers/gpu/drm/gma500/psb_intel_sdvo.c

861

uint8_t set_buf_index[2];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

862

uint8_t av_split;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

863

uint8_t buf_size;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

864

uint8_t buf[48];

drivers/gpu/drm/gma500/psb_intel_sdvo.c

865

uint8_t *pos;

drivers/gpu/drm/mediatek/mtk_dp.c

2636

static int mtk_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf,

drivers/gpu/drm/mediatek/mtk_hdmi_common.c

179

int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)

drivers/gpu/drm/mediatek/mtk_hdmi_common.h

183

int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);

drivers/gpu/drm/meson/meson_overlay.c

197

static const uint8_t skip_tab[6] = {

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

29

uint8_t ifpc_list_len;

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

30

uint8_t preemption_list_len;

drivers/gpu/drm/msm/adreno/adreno_gpu.h

287

static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)

drivers/gpu/drm/msm/adreno/adreno_gpu.h

692

OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)

drivers/gpu/drm/msm/adreno/adreno_gpu.h

725

OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

96

uint8_t enable_pxl_ext;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h

64

uint8_t reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

18

uint8_t reserved[MAX_CLIENTS]; /* fixed MMBs allocation per client */

drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c

68

uint8_t reserved;

drivers/gpu/drm/msm/msm_gem.h

205

uint8_t madv;

drivers/gpu/drm/msm/msm_gem.h

210

uint8_t vmap_count;

drivers/gpu/drm/nouveau/dispnv04/crtc.c

697

uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];

drivers/gpu/drm/nouveau/dispnv04/crtc.c

743

uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);

drivers/gpu/drm/nouveau/dispnv04/crtc.c

782

struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;

drivers/gpu/drm/nouveau/dispnv04/dac.c

138

uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;

drivers/gpu/drm/nouveau/dispnv04/dac.c

139

uint8_t saved_palette0[3], saved_palette_mask;

drivers/gpu/drm/nouveau/dispnv04/dac.c

142

uint8_t blue;

drivers/gpu/drm/nouveau/dispnv04/dfp.c

252

uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];

drivers/gpu/drm/nouveau/dispnv04/dfp.c

253

uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];

drivers/gpu/drm/nouveau/dispnv04/dfp.c

79

uint8_t tmds04 = 0x80;

drivers/gpu/drm/nouveau/dispnv04/disp.h

25

uint8_t CRTC[0xa0];

drivers/gpu/drm/nouveau/dispnv04/disp.h

26

uint8_t CR58[0x10];

drivers/gpu/drm/nouveau/dispnv04/disp.h

27

uint8_t Sequencer[5];

drivers/gpu/drm/nouveau/dispnv04/disp.h

28

uint8_t Graphics[9];

drivers/gpu/drm/nouveau/dispnv04/disp.h

29

uint8_t Attribute[21];

drivers/gpu/drm/nouveau/dispnv04/hw.c

313

uint8_t misc, gr4, gr5, gr6, seq2, seq4;

drivers/gpu/drm/nouveau/dispnv04/hw.c

39

NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)

drivers/gpu/drm/nouveau/dispnv04/hw.c

45

uint8_t

drivers/gpu/drm/nouveau/dispnv04/hw.c

46

NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)

drivers/gpu/drm/nouveau/dispnv04/hw.c

53

NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)

drivers/gpu/drm/nouveau/dispnv04/hw.c

59

uint8_t

drivers/gpu/drm/nouveau/dispnv04/hw.c

60

NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)

drivers/gpu/drm/nouveau/dispnv04/hw.h

100

int or, int dl, uint8_t address)

drivers/gpu/drm/nouveau/dispnv04/hw.h

110

int or, int dl, uint8_t address,

drivers/gpu/drm/nouveau/dispnv04/hw.h

111

uint8_t data)

drivers/gpu/drm/nouveau/dispnv04/hw.h

120

int head, uint8_t index, uint8_t value)

drivers/gpu/drm/nouveau/dispnv04/hw.h

127

static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,

drivers/gpu/drm/nouveau/dispnv04/hw.h

128

int head, uint8_t index)

drivers/gpu/drm/nouveau/dispnv04/hw.h

131

uint8_t val;

drivers/gpu/drm/nouveau/dispnv04/hw.h

152

NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value)

drivers/gpu/drm/nouveau/dispnv04/hw.h

158

static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index)

drivers/gpu/drm/nouveau/dispnv04/hw.h

164

static inline uint8_t NVReadPRMVIO(struct drm_device *dev,

drivers/gpu/drm/nouveau/dispnv04/hw.h

169

uint8_t val;

drivers/gpu/drm/nouveau/dispnv04/hw.h

181

int head, uint32_t reg, uint8_t value)

drivers/gpu/drm/nouveau/dispnv04/hw.h

209

int head, uint8_t index, uint8_t value)

drivers/gpu/drm/nouveau/dispnv04/hw.h

222

static inline uint8_t NVReadVgaAttr(struct drm_device *dev,

drivers/gpu/drm/nouveau/dispnv04/hw.h

223

int head, uint8_t index)

drivers/gpu/drm/nouveau/dispnv04/hw.h

226

uint8_t val;

drivers/gpu/drm/nouveau/dispnv04/hw.h

245

uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);

drivers/gpu/drm/nouveau/dispnv04/hw.h

274

uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX);

drivers/gpu/drm/nouveau/dispnv04/hw.h

299

uint8_t cr21 = lock;

drivers/gpu/drm/nouveau/dispnv04/hw.h

37

void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);

drivers/gpu/drm/nouveau/dispnv04/hw.h

375

uint8_t *curctl1 =

drivers/gpu/drm/nouveau/dispnv04/hw.h

38

uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);

drivers/gpu/drm/nouveau/dispnv04/hw.h

39

void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);

drivers/gpu/drm/nouveau/dispnv04/hw.h

40

uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);

drivers/gpu/drm/nouveau/dispnv04/hw.h

99

static inline uint8_t nv_read_tmds(struct drm_device *dev,

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_drv.c

123

uint8_t *regs = state->regs;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_drv.c

393

uint8_t addr = CH7006_VERSION_ID;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_drv.c

394

uint8_t val;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

203

uint8_t *regs = priv->state.regs;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

258

uint8_t *regs = priv->state.regs;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

295

uint8_t *power = &priv->state.regs[CH7006_POWER];

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

333

uint8_t *regs = state->regs;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

368

void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val)

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

370

uint8_t buf[] = {addr, val};

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

379

uint8_t ch7006_read(struct i2c_client *client, uint8_t addr)

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_mode.c

381

uint8_t val;

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_priv.h

122

void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val);

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_priv.h

123

uint8_t ch7006_read(struct i2c_client *client, uint8_t addr);

drivers/gpu/drm/nouveau/dispnv04/i2c/ch7006_priv.h

76

uint8_t regs[0x26];

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

107

sil164_write(struct i2c_client *client, uint8_t addr, uint8_t val)

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

109

uint8_t buf[] = {addr, val};

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

118

static uint8_t

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

119

sil164_read(struct i2c_client *client, uint8_t addr)

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

121

uint8_t val;

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

141

sil164_save_state(struct i2c_client *client, uint8_t *state)

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

150

sil164_restore_state(struct i2c_client *client, uint8_t *state)

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

161

uint8_t control0 = sil164_read(client, SIL164_CONTROL0);

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

40

uint8_t saved_state[0x10];

drivers/gpu/drm/nouveau/dispnv04/i2c/sil164_drv.c

41

uint8_t saved_slave_state[0x10];

drivers/gpu/drm/nouveau/dispnv04/overlay.c

93

verify_scaling(const struct drm_framebuffer *fb, uint8_t shift,

drivers/gpu/drm/nouveau/dispnv04/tvnv04.c

80

uint8_t crtc1A;

drivers/gpu/drm/nouveau/dispnv04/tvnv17.c

410

uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[

drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

102

uint8_t tv_enc[0x40];

drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

143

static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,

drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

144

uint8_t val)

drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

150

static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg)

drivers/gpu/drm/nouveau/dispnv04/tvnv17.h

31

uint8_t tv_enc[0x40];

drivers/gpu/drm/nouveau/dispnv50/wndw.c

282

uint8_t kind;

drivers/gpu/drm/nouveau/dispnv50/wndw.c

797

uint8_t i;

drivers/gpu/drm/nouveau/dispnv50/wndw.c

804

const uint8_t kind = (modifier >> 12) & 0xff;

drivers/gpu/drm/nouveau/dispnv50/wndw.c

811

const uint8_t slayout = ((modifier >> 22) & 0x1) |

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

21

uint8_t i2c_index;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

22

uint8_t heads;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

23

uint8_t connector;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

24

uint8_t bus;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

25

uint8_t location;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

26

uint8_t or;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

27

uint8_t link;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h

29

uint8_t extdev;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h

11

uint8_t M1, N1, M2, N2;

drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h

9

uint8_t N1, M1, N2, M2;

drivers/gpu/drm/nouveau/nouveau_bios.c

1086

uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;

drivers/gpu/drm/nouveau/nouveau_bios.c

109

uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0);

drivers/gpu/drm/nouveau/nouveau_bios.c

1233

static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)

drivers/gpu/drm/nouveau/nouveau_bios.c

1925

uint8_t bytes_to_write;

drivers/gpu/drm/nouveau/nouveau_bios.c

1972

static const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };

drivers/gpu/drm/nouveau/nouveau_bios.c

1984

uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)

drivers/gpu/drm/nouveau/nouveau_bios.c

1988

static const uint8_t edid_sig[] = {

drivers/gpu/drm/nouveau/nouveau_bios.c

219

uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];

drivers/gpu/drm/nouveau/nouveau_bios.c

258

uint8_t lvds_ver, headerlen, recordlen;

drivers/gpu/drm/nouveau/nouveau_bios.c

271

uint8_t lvds_ver, headerlen, recordlen;

drivers/gpu/drm/nouveau/nouveau_bios.c

347

uint8_t *fptable;

drivers/gpu/drm/nouveau/nouveau_bios.c

348

uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;

drivers/gpu/drm/nouveau/nouveau_bios.c

452

uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];

drivers/gpu/drm/nouveau/nouveau_bios.c

46

static bool nv_cksum(const uint8_t *data, unsigned int length)

drivers/gpu/drm/nouveau/nouveau_bios.c

53

uint8_t sum = 0;

drivers/gpu/drm/nouveau/nouveau_bios.c

706

uint8_t version, headerlen, entrylen, num_entries;

drivers/gpu/drm/nouveau/nouveau_bios.c

78

uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];

drivers/gpu/drm/nouveau/nouveau_bios.c

798

uint8_t dacver, dacheaderlen;

drivers/gpu/drm/nouveau/nouveau_bios.h

109

uint8_t ram_restrict_group_count;

drivers/gpu/drm/nouveau/nouveau_bios.h

131

uint8_t strapless_is_24bit;

drivers/gpu/drm/nouveau/nouveau_bios.h

132

uint8_t *edid;

drivers/gpu/drm/nouveau/nouveau_bios.h

150

uint8_t crt, tv, panel;

drivers/gpu/drm/nouveau/nouveau_bios.h

170

uint8_t *nouveau_bios_embedded_edid(struct drm_device *);

drivers/gpu/drm/nouveau/nouveau_bios.h

42

uint8_t id;

drivers/gpu/drm/nouveau/nouveau_bios.h

43

uint8_t version;

drivers/gpu/drm/nouveau/nouveau_bios.h

46

uint8_t *data;

drivers/gpu/drm/nouveau/nouveau_bios.h

56

uint8_t version;

drivers/gpu/drm/nouveau/nouveau_bios.h

85

uint8_t *data;

drivers/gpu/drm/nouveau/nouveau_bios.h

87

uint8_t chip_version;

drivers/gpu/drm/nouveau/nouveau_bios.h

91

uint8_t digital_min_front_porch;

drivers/gpu/drm/nouveau/nouveau_bios.h

98

uint8_t major_version;

drivers/gpu/drm/nouveau/nouveau_bios.h

99

uint8_t feature_byte;

drivers/gpu/drm/nouveau/nouveau_display.c

136

uint8_t *kind)

drivers/gpu/drm/nouveau/nouveau_display.c

157

*kind = (uint8_t)((modifier >> 12) & 0xFF);

drivers/gpu/drm/nouveau/nouveau_display.c

167

uint8_t *kind)

drivers/gpu/drm/nouveau/nouveau_display.c

195

uint8_t *kind)

drivers/gpu/drm/nouveau/nouveau_display.c

267

uint8_t kind;

drivers/gpu/drm/nouveau/nouveau_display.h

69

uint8_t *kind);

drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c

159

uint8_t duty_lut[] = { 0, 0, 25, 0, 40, 0, 50, 0,

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

308

uint8_t Pval2;

drivers/gpu/drm/qxl/qxl_cmd.c

109

uint8_t *elt;

drivers/gpu/drm/qxl/qxl_cmd.c

156

volatile uint8_t *ring_elt;

drivers/gpu/drm/qxl/qxl_cmd.c

281

static int wait_for_io_cmd_user(struct qxl_device *qdev, uint8_t val, long port, bool intr)

drivers/gpu/drm/qxl/qxl_cmd.c

316

static void wait_for_io_cmd(struct qxl_device *qdev, uint8_t val, long port)

drivers/gpu/drm/qxl/qxl_cmd.c

40

uint8_t elements[];

drivers/gpu/drm/qxl/qxl_cmd.c

404

void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id)

drivers/gpu/drm/qxl/qxl_dev.h

243

uint8_t slots_start;

drivers/gpu/drm/qxl/qxl_dev.h

244

uint8_t slots_end;

drivers/gpu/drm/qxl/qxl_dev.h

245

uint8_t slot_gen_bits;

drivers/gpu/drm/qxl/qxl_dev.h

246

uint8_t slot_id_bits;

drivers/gpu/drm/qxl/qxl_dev.h

247

uint8_t slot_generation;

drivers/gpu/drm/qxl/qxl_dev.h

249

uint8_t client_present;

drivers/gpu/drm/qxl/qxl_dev.h

250

uint8_t client_capabilities[58];

drivers/gpu/drm/qxl/qxl_dev.h

350

uint8_t log_buf[QXL_LOG_BUF_SIZE];

drivers/gpu/drm/qxl/qxl_dev.h

368

uint8_t guest_capabilities[64];

drivers/gpu/drm/qxl/qxl_dev.h

385

uint8_t data[];

drivers/gpu/drm/qxl/qxl_dev.h

390

uint8_t data[];

drivers/gpu/drm/qxl/qxl_dev.h

432

uint8_t type;

drivers/gpu/drm/qxl/qxl_dev.h

436

uint8_t visible;

drivers/gpu/drm/qxl/qxl_dev.h

446

uint8_t device_data[QXL_CURSOR_DEVICE_DATA_SIZE];

drivers/gpu/drm/qxl/qxl_dev.h

472

uint8_t data[];

drivers/gpu/drm/qxl/qxl_dev.h

511

uint8_t flags;

drivers/gpu/drm/qxl/qxl_dev.h

527

uint8_t scale_mode;

drivers/gpu/drm/qxl/qxl_dev.h

535

uint8_t scale_mode;

drivers/gpu/drm/qxl/qxl_dev.h

548

uint8_t alpha;

drivers/gpu/drm/qxl/qxl_dev.h

554

uint8_t alpha;

drivers/gpu/drm/qxl/qxl_dev.h

563

uint8_t rop3;

drivers/gpu/drm/qxl/qxl_dev.h

564

uint8_t scale_mode;

drivers/gpu/drm/qxl/qxl_dev.h

569

uint8_t flags;

drivers/gpu/drm/qxl/qxl_dev.h

570

uint8_t join_style;

drivers/gpu/drm/qxl/qxl_dev.h

571

uint8_t end_style;

drivers/gpu/drm/qxl/qxl_dev.h

572

uint8_t style_nseg;

drivers/gpu/drm/qxl/qxl_dev.h

679

uint8_t effect;

drivers/gpu/drm/qxl/qxl_dev.h

680

uint8_t type;

drivers/gpu/drm/qxl/qxl_dev.h

706

uint8_t effect;

drivers/gpu/drm/qxl/qxl_dev.h

707

uint8_t type;

drivers/gpu/drm/qxl/qxl_dev.h

708

uint8_t self_bitmap;

drivers/gpu/drm/qxl/qxl_dev.h

749

uint8_t type;

drivers/gpu/drm/qxl/qxl_dev.h

813

uint8_t type;

drivers/gpu/drm/qxl/qxl_dev.h

814

uint8_t flags;

drivers/gpu/drm/qxl/qxl_dev.h

826

uint8_t format;

drivers/gpu/drm/qxl/qxl_dev.h

827

uint8_t flags;

drivers/gpu/drm/qxl/qxl_dev.h

841

uint8_t data[];

drivers/gpu/drm/qxl/qxl_display.c

85

crc = crc32(0, (const uint8_t *)&qdev->rom->client_monitors_config,

drivers/gpu/drm/qxl/qxl_draw.c

151

uint8_t *surface_base;

drivers/gpu/drm/qxl/qxl_draw.c

79

make_drawable(struct qxl_device *qdev, int surface, uint8_t type,

drivers/gpu/drm/qxl/qxl_drv.h

130

uint8_t generation;

drivers/gpu/drm/qxl/qxl_drv.h

334

const uint8_t *data,

drivers/gpu/drm/qxl/qxl_drv.h

349

void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id);

drivers/gpu/drm/qxl/qxl_image.c

105

const uint8_t *data,

drivers/gpu/drm/qxl/qxl_image.c

235

const uint8_t *data,

drivers/gpu/drm/radeon/atom-bits.h

28

static inline uint8_t get_u8(void *bios, int ptr)

drivers/gpu/drm/radeon/atom-types.h

32

typedef uint8_t UCHAR;

drivers/gpu/drm/radeon/atom.c

1013

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

1025

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

1377

uint16_t *size, uint8_t *frev, uint8_t *crev,

drivers/gpu/drm/radeon/atom.c

1397

bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,

drivers/gpu/drm/radeon/atom.c

1398

uint8_t *crev)

drivers/gpu/drm/radeon/atom.c

180

static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,

drivers/gpu/drm/radeon/atom.c

371

static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)

drivers/gpu/drm/radeon/atom.c

407

static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)

drivers/gpu/drm/radeon/atom.c

412

static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)

drivers/gpu/drm/radeon/atom.c

438

static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,

drivers/gpu/drm/radeon/atom.c

447

static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)

drivers/gpu/drm/radeon/atom.c

454

static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,

drivers/gpu/drm/radeon/atom.c

600

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

614

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

649

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

661

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

687

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

762

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

779

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

796

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

812

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

826

uint8_t val = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

861

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

902

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/radeon/atom.c

918

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/radeon/atom.c

934

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/radeon/atom.c

953

uint8_t attr = U8((*ptr)++), shift;

drivers/gpu/drm/radeon/atom.c

972

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.c

986

uint8_t attr = U8((*ptr)++);

drivers/gpu/drm/radeon/atom.h

138

uint8_t shift;

drivers/gpu/drm/radeon/atom.h

153

uint8_t *frev, uint8_t *crev, uint16_t *data_start);

drivers/gpu/drm/radeon/atom.h

155

uint8_t *frev, uint8_t *crev);

drivers/gpu/drm/radeon/atombios_encoders.c

1001

atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)

drivers/gpu/drm/radeon/atombios_encoders.c

1010

uint8_t frev, crev;

drivers/gpu/drm/radeon/atombios_encoders.c

1368

atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)

drivers/gpu/drm/radeon/atombios_encoders.c

1381

uint8_t frev, crev;

drivers/gpu/drm/radeon/atombios_encoders.c

1853

uint8_t frev, crev;

drivers/gpu/drm/radeon/atombios_encoders.c

2285

uint8_t frev, crev;

drivers/gpu/drm/radeon/atombios_encoders.c

493

uint8_t frev, crev;

drivers/gpu/drm/radeon/atombios_encoders.c

567

uint8_t frev, crev;

drivers/gpu/drm/radeon/atombios_encoders.c

840

uint8_t frev, crev;

drivers/gpu/drm/radeon/ci_dpm.c

988

fan_table.TempSrc = (uint8_t)tmp;

drivers/gpu/drm/radeon/evergreen_hdmi.c

213

uint8_t *frame = buffer + 3;

drivers/gpu/drm/radeon/evergreen_smc.h

47

uint8_t last;

drivers/gpu/drm/radeon/evergreen_smc.h

48

uint8_t reserved[3];

drivers/gpu/drm/radeon/kv_dpm.c

1266

(uint8_t *)&pi->uvd_boot_level,

drivers/gpu/drm/radeon/nislands_smc.h

109

uint8_t hUp;

drivers/gpu/drm/radeon/nislands_smc.h

110

uint8_t hDown;

drivers/gpu/drm/radeon/nislands_smc.h

111

uint8_t stateFlags;

drivers/gpu/drm/radeon/nislands_smc.h

112

uint8_t arbRefreshState;

drivers/gpu/drm/radeon/nislands_smc.h

130

uint8_t flags;

drivers/gpu/drm/radeon/nislands_smc.h

131

uint8_t levelCount;

drivers/gpu/drm/radeon/nislands_smc.h

132

uint8_t padding2;

drivers/gpu/drm/radeon/nislands_smc.h

133

uint8_t padding3;

drivers/gpu/drm/radeon/nislands_smc.h

140

uint8_t flags;

drivers/gpu/drm/radeon/nislands_smc.h

141

uint8_t levelCount;

drivers/gpu/drm/radeon/nislands_smc.h

142

uint8_t padding2;

drivers/gpu/drm/radeon/nislands_smc.h

143

uint8_t padding3;

drivers/gpu/drm/radeon/nislands_smc.h

153

uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX];

drivers/gpu/drm/radeon/nislands_smc.h

162

uint8_t thermalProtectType;

drivers/gpu/drm/radeon/nislands_smc.h

163

uint8_t systemFlags;

drivers/gpu/drm/radeon/nislands_smc.h

164

uint8_t maxVDDCIndexInPPTable;

drivers/gpu/drm/radeon/nislands_smc.h

165

uint8_t extraFlags;

drivers/gpu/drm/radeon/nislands_smc.h

166

uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS];

drivers/gpu/drm/radeon/nislands_smc.h

215

uint8_t cac_width;

drivers/gpu/drm/radeon/nislands_smc.h

216

uint8_t window_size_p2;

drivers/gpu/drm/radeon/nislands_smc.h

218

uint8_t num_drop_lsb;

drivers/gpu/drm/radeon/nislands_smc.h

219

uint8_t padding_0;

drivers/gpu/drm/radeon/nislands_smc.h

223

uint8_t AllowOvrflw;

drivers/gpu/drm/radeon/nislands_smc.h

224

uint8_t MCWrWeight;

drivers/gpu/drm/radeon/nislands_smc.h

225

uint8_t MCRdWeight;

drivers/gpu/drm/radeon/nislands_smc.h

226

uint8_t padding_1[9];

drivers/gpu/drm/radeon/nislands_smc.h

228

uint8_t enableWinAvg;

drivers/gpu/drm/radeon/nislands_smc.h

229

uint8_t numWin_TDP;

drivers/gpu/drm/radeon/nislands_smc.h

230

uint8_t l2numWin_TDP;

drivers/gpu/drm/radeon/nislands_smc.h

231

uint8_t WinIndex;

drivers/gpu/drm/radeon/nislands_smc.h

240

uint8_t lts_truncate_n;

drivers/gpu/drm/radeon/nislands_smc.h

241

uint8_t padding_2[7];

drivers/gpu/drm/radeon/nislands_smc.h

264

uint8_t last;

drivers/gpu/drm/radeon/nislands_smc.h

265

uint8_t reserved[3];

drivers/gpu/drm/radeon/nislands_smc.h

275

uint8_t mc_arb_rfsh_rate;

drivers/gpu/drm/radeon/nislands_smc.h

276

uint8_t padding[3];

drivers/gpu/drm/radeon/nislands_smc.h

282

uint8_t arb_current;

drivers/gpu/drm/radeon/nislands_smc.h

283

uint8_t reserved[3];

drivers/gpu/drm/radeon/nislands_smc.h

31

uint8_t MaxPS;

drivers/gpu/drm/radeon/nislands_smc.h

32

uint8_t TgtAct;

drivers/gpu/drm/radeon/nislands_smc.h

33

uint8_t MaxPS_StepInc;

drivers/gpu/drm/radeon/nislands_smc.h

34

uint8_t MaxPS_StepDec;

drivers/gpu/drm/radeon/nislands_smc.h

35

uint8_t PSST;

drivers/gpu/drm/radeon/nislands_smc.h

36

uint8_t NearTDPDec;

drivers/gpu/drm/radeon/nislands_smc.h

37

uint8_t AboveSafeInc;

drivers/gpu/drm/radeon/nislands_smc.h

38

uint8_t BelowSafeInc;

drivers/gpu/drm/radeon/nislands_smc.h

39

uint8_t PSDeltaLimit;

drivers/gpu/drm/radeon/nislands_smc.h

40

uint8_t PSDeltaWin;

drivers/gpu/drm/radeon/nislands_smc.h

41

uint8_t Reserved[6];

drivers/gpu/drm/radeon/nislands_smc.h

85

uint8_t index;

drivers/gpu/drm/radeon/nislands_smc.h

86

uint8_t padding;

drivers/gpu/drm/radeon/nislands_smc.h

92

uint8_t arbValue;

drivers/gpu/drm/radeon/nislands_smc.h

93

uint8_t ACIndex;

drivers/gpu/drm/radeon/nislands_smc.h

94

uint8_t displayWatermark;

drivers/gpu/drm/radeon/nislands_smc.h

95

uint8_t gen2PCIE;

drivers/gpu/drm/radeon/nislands_smc.h

96

uint8_t reserved1;

drivers/gpu/drm/radeon/nislands_smc.h

97

uint8_t reserved2;

drivers/gpu/drm/radeon/nislands_smc.h

98

uint8_t strobeMode;

drivers/gpu/drm/radeon/nislands_smc.h

99

uint8_t mcFlags;

drivers/gpu/drm/radeon/ppsmc.h

100

#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E)

drivers/gpu/drm/radeon/ppsmc.h

101

#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F)

drivers/gpu/drm/radeon/ppsmc.h

102

#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A)

drivers/gpu/drm/radeon/ppsmc.h

103

#define PPSMC_FlushDataCache ((uint8_t)0x80)

drivers/gpu/drm/radeon/ppsmc.h

104

#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82)

drivers/gpu/drm/radeon/ppsmc.h

105

#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83)

drivers/gpu/drm/radeon/ppsmc.h

106

#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84)

drivers/gpu/drm/radeon/ppsmc.h

107

#define PPSMC_MSG_EnableDTE ((uint8_t)0x87)

drivers/gpu/drm/radeon/ppsmc.h

108

#define PPSMC_MSG_DisableDTE ((uint8_t)0x88)

drivers/gpu/drm/radeon/ppsmc.h

109

#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96)

drivers/gpu/drm/radeon/ppsmc.h

110

#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97)

drivers/gpu/drm/radeon/ppsmc.h

67

#define PPSMC_Result_OK ((uint8_t)0x01)

drivers/gpu/drm/radeon/ppsmc.h

68

#define PPSMC_Result_Failed ((uint8_t)0xFF)

drivers/gpu/drm/radeon/ppsmc.h

70

typedef uint8_t PPSMC_Result;

drivers/gpu/drm/radeon/ppsmc.h

72

#define PPSMC_MSG_Halt ((uint8_t)0x10)

drivers/gpu/drm/radeon/ppsmc.h

73

#define PPSMC_MSG_Resume ((uint8_t)0x11)

drivers/gpu/drm/radeon/ppsmc.h

74

#define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13)

drivers/gpu/drm/radeon/ppsmc.h

75

#define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14)

drivers/gpu/drm/radeon/ppsmc.h

76

#define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15)

drivers/gpu/drm/radeon/ppsmc.h

77

#define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16)

drivers/gpu/drm/radeon/ppsmc.h

78

#define PPSMC_MSG_RunningOnAC ((uint8_t)0x17)

drivers/gpu/drm/radeon/ppsmc.h

79

#define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20)

drivers/gpu/drm/radeon/ppsmc.h

80

#define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40)

drivers/gpu/drm/radeon/ppsmc.h

81

#define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41)

drivers/gpu/drm/radeon/ppsmc.h

82

#define PPSMC_MSG_ForceHigh ((uint8_t)0x42)

drivers/gpu/drm/radeon/ppsmc.h

83

#define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43)

drivers/gpu/drm/radeon/ppsmc.h

84

#define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51)

drivers/gpu/drm/radeon/ppsmc.h

85

#define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52)

drivers/gpu/drm/radeon/ppsmc.h

86

#define PPSMC_MSG_EnableCac ((uint8_t)0x53)

drivers/gpu/drm/radeon/ppsmc.h

87

#define PPSMC_MSG_DisableCac ((uint8_t)0x54)

drivers/gpu/drm/radeon/ppsmc.h

88

#define PPSMC_TDPClampingActive ((uint8_t)0x59)

drivers/gpu/drm/radeon/ppsmc.h

89

#define PPSMC_TDPClampingInactive ((uint8_t)0x5A)

drivers/gpu/drm/radeon/ppsmc.h

90

#define PPSMC_StartFanControl ((uint8_t)0x5B)

drivers/gpu/drm/radeon/ppsmc.h

91

#define PPSMC_StopFanControl ((uint8_t)0x5C)

drivers/gpu/drm/radeon/ppsmc.h

92

#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D)

drivers/gpu/drm/radeon/ppsmc.h

93

#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E)

drivers/gpu/drm/radeon/ppsmc.h

94

#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60)

drivers/gpu/drm/radeon/ppsmc.h

95

#define PPSMC_MSG_UVDPowerON ((uint8_t)0x61)

drivers/gpu/drm/radeon/ppsmc.h

96

#define PPSMC_MSG_EnableULV ((uint8_t)0x62)

drivers/gpu/drm/radeon/ppsmc.h

97

#define PPSMC_MSG_DisableULV ((uint8_t)0x63)

drivers/gpu/drm/radeon/ppsmc.h

98

#define PPSMC_MSG_EnterULV ((uint8_t)0x64)

drivers/gpu/drm/radeon/ppsmc.h

99

#define PPSMC_MSG_ExitULV ((uint8_t)0x65)

drivers/gpu/drm/radeon/r600_hdmi.c

221

uint8_t *frame = buffer + 3;

drivers/gpu/drm/radeon/r600_hdmi.c

397

uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];

drivers/gpu/drm/radeon/radeon.h

2316

uint8_t *bios;

drivers/gpu/drm/radeon/radeon_atombios.c

1131

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

129

uint8_t id)

drivers/gpu/drm/radeon/radeon_atombios.c

1337

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1386

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1514

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1626

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1767

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1768

uint8_t bg, dac;

drivers/gpu/drm/radeon/radeon_atombios.c

1892

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1953

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

1954

uint8_t bg, dac;

drivers/gpu/drm/radeon/radeon_atombios.c

561

uint8_t *addr = (uint8_t *) path_obj->asDispPath;

drivers/gpu/drm/radeon/radeon_atombios.c

568

uint8_t con_obj_id, con_obj_num;

drivers/gpu/drm/radeon/radeon_atombios.c

643

uint8_t grph_obj_type =

drivers/gpu/drm/radeon/radeon_atombios.c

849

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

893

uint8_t frev, crev;

drivers/gpu/drm/radeon/radeon_atombios.c

895

uint8_t dac;

drivers/gpu/drm/radeon/radeon_bios.c

158

static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,

drivers/gpu/drm/radeon/radeon_bios.c

51

uint8_t __iomem *bios;

drivers/gpu/drm/radeon/radeon_bios.c

82

uint8_t __iomem *bios, val1, val2;

drivers/gpu/drm/radeon/radeon_combios.c

1000

uint8_t rev, bg, dac;

drivers/gpu/drm/radeon/radeon_combios.c

1321

uint8_t ver;

drivers/gpu/drm/radeon/radeon_combios.c

1397

uint8_t ver;

drivers/gpu/drm/radeon/radeon_combios.c

2268

uint8_t rev = RBIOS8(ext_tmds_info);

drivers/gpu/drm/radeon/radeon_combios.c

2269

uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);

drivers/gpu/drm/radeon/radeon_combios.c

2870

uint8_t blocks, slave_addr, rev;

drivers/gpu/drm/radeon/radeon_combios.c

3080

uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);

drivers/gpu/drm/radeon/radeon_combios.c

3081

uint8_t addr = (RBIOS8(offset) & 0x3f);

drivers/gpu/drm/radeon/radeon_combios.c

3171

uint8_t val = RBIOS8(offset);

drivers/gpu/drm/radeon/radeon_combios.c

3246

uint8_t rev;

drivers/gpu/drm/radeon/radeon_combios.c

850

uint8_t rev, bg, dac;

drivers/gpu/drm/radeon/radeon_encoders.c

87

radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)

drivers/gpu/drm/radeon/radeon_i2c.c

1068

uint8_t out_buf[2];

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

266

static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

734

uint8_t pll_gain;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

323

static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

326

uint8_t level;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

359

uint8_t backlight_level;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

380

uint8_t backlight_level;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

64

uint8_t backlight_level;

drivers/gpu/drm/radeon/radeon_legacy_tv.c

81

uint8_t crtcPLL_M;

drivers/gpu/drm/radeon/radeon_legacy_tv.c

82

uint8_t crtcPLL_post_div;

drivers/gpu/drm/radeon/radeon_mode.h

119

uint8_t i2c_id;

drivers/gpu/drm/radeon/radeon_mode.h

285

uint8_t negative;

drivers/gpu/drm/radeon/radeon_mode.h

306

uint8_t type;

drivers/gpu/drm/radeon/radeon_mode.h

308

uint8_t delay;

drivers/gpu/drm/radeon/radeon_mode.h

309

uint8_t range;

drivers/gpu/drm/radeon/radeon_mode.h

310

uint8_t refdiv;

drivers/gpu/drm/radeon/radeon_mode.h

378

uint8_t panel_pwr_delay;

drivers/gpu/drm/radeon/radeon_mode.h

379

uint8_t panel_digon_delay;

drivers/gpu/drm/radeon/radeon_mode.h

380

uint8_t panel_blon_delay;

drivers/gpu/drm/radeon/radeon_mode.h

382

uint8_t panel_post_divider;

drivers/gpu/drm/radeon/radeon_mode.h

390

uint8_t backlight_level;

drivers/gpu/drm/radeon/radeon_mode.h

416

uint8_t slave_addr;

drivers/gpu/drm/radeon/radeon_mode.h

434

uint8_t backlight_level;

drivers/gpu/drm/radeon/radeon_mode.h

677

uint8_t dac);

drivers/gpu/drm/radeon/radeon_mode.h

731

int action, uint8_t lane_num,

drivers/gpu/drm/radeon/radeon_mode.h

732

uint8_t lane_set);

drivers/gpu/drm/radeon/radeon_mode.h

734

int action, uint8_t lane_num,

drivers/gpu/drm/radeon/radeon_mode.h

735

uint8_t lane_set, int fe);

drivers/gpu/drm/radeon/radeon_ucode.h

217

uint8_t raw[0x100];

drivers/gpu/drm/radeon/radeon_vce.c

62

uint8_t start, mid, end;

drivers/gpu/drm/radeon/rs690.c

71

uint8_t frev, crev;

drivers/gpu/drm/radeon/rv770_smc.h

107

uint8_t reserved1;

drivers/gpu/drm/radeon/rv770_smc.h

108

uint8_t reserved2;

drivers/gpu/drm/radeon/rv770_smc.h

109

uint8_t stateFlags;

drivers/gpu/drm/radeon/rv770_smc.h

110

uint8_t padding;

drivers/gpu/drm/radeon/rv770_smc.h

124

uint8_t flags;

drivers/gpu/drm/radeon/rv770_smc.h

125

uint8_t padding1;

drivers/gpu/drm/radeon/rv770_smc.h

126

uint8_t padding2;

drivers/gpu/drm/radeon/rv770_smc.h

127

uint8_t padding3;

drivers/gpu/drm/radeon/rv770_smc.h

139

uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX];

drivers/gpu/drm/radeon/rv770_smc.h

148

uint8_t thermalProtectType;

drivers/gpu/drm/radeon/rv770_smc.h

149

uint8_t systemFlags;

drivers/gpu/drm/radeon/rv770_smc.h

150

uint8_t maxVDDCIndexInPPTable;

drivers/gpu/drm/radeon/rv770_smc.h

151

uint8_t extraFlags;

drivers/gpu/drm/radeon/rv770_smc.h

152

uint8_t highSMIO[MAX_NO_VREG_STEPS];

drivers/gpu/drm/radeon/rv770_smc.h

75

uint8_t index;

drivers/gpu/drm/radeon/rv770_smc.h

76

uint8_t padding;

drivers/gpu/drm/radeon/rv770_smc.h

89

uint8_t arbValue;

drivers/gpu/drm/radeon/rv770_smc.h

91

uint8_t seqValue;

drivers/gpu/drm/radeon/rv770_smc.h

92

uint8_t ACIndex;

drivers/gpu/drm/radeon/rv770_smc.h

94

uint8_t displayWatermark;

drivers/gpu/drm/radeon/rv770_smc.h

95

uint8_t gen2PCIE;

drivers/gpu/drm/radeon/rv770_smc.h

96

uint8_t gen2XSP;

drivers/gpu/drm/radeon/rv770_smc.h

97

uint8_t backbias;

drivers/gpu/drm/radeon/rv770_smc.h

98

uint8_t strobeMode;

drivers/gpu/drm/radeon/rv770_smc.h

99

uint8_t mcFlags;

drivers/gpu/drm/radeon/si_dpm.c

6034

fan_table.temp_src = (uint8_t)tmp;

drivers/gpu/drm/radeon/sislands_smc.h

131

uint8_t index;

drivers/gpu/drm/radeon/sislands_smc.h

132

uint8_t phase_settings;

drivers/gpu/drm/radeon/sislands_smc.h

138

uint8_t ACIndex;

drivers/gpu/drm/radeon/sislands_smc.h

139

uint8_t displayWatermark;

drivers/gpu/drm/radeon/sislands_smc.h

140

uint8_t gen2PCIE;

drivers/gpu/drm/radeon/sislands_smc.h

141

uint8_t UVDWatermark;

drivers/gpu/drm/radeon/sislands_smc.h

142

uint8_t VCEWatermark;

drivers/gpu/drm/radeon/sislands_smc.h

143

uint8_t strobeMode;

drivers/gpu/drm/radeon/sislands_smc.h

144

uint8_t mcFlags;

drivers/gpu/drm/radeon/sislands_smc.h

145

uint8_t padding;

drivers/gpu/drm/radeon/sislands_smc.h

154

uint8_t hysteresisUp;

drivers/gpu/drm/radeon/sislands_smc.h

155

uint8_t hysteresisDown;

drivers/gpu/drm/radeon/sislands_smc.h

156

uint8_t stateFlags;

drivers/gpu/drm/radeon/sislands_smc.h

157

uint8_t arbRefreshState;

drivers/gpu/drm/radeon/sislands_smc.h

179

uint8_t flags;

drivers/gpu/drm/radeon/sislands_smc.h

180

uint8_t levelCount;

drivers/gpu/drm/radeon/sislands_smc.h

181

uint8_t padding2;

drivers/gpu/drm/radeon/sislands_smc.h

182

uint8_t padding3;

drivers/gpu/drm/radeon/sislands_smc.h

189

uint8_t flags;

drivers/gpu/drm/radeon/sislands_smc.h

190

uint8_t levelCount;

drivers/gpu/drm/radeon/sislands_smc.h

191

uint8_t padding2;

drivers/gpu/drm/radeon/sislands_smc.h

192

uint8_t padding3;

drivers/gpu/drm/radeon/sislands_smc.h

211

uint8_t thermalProtectType;

drivers/gpu/drm/radeon/sislands_smc.h

212

uint8_t systemFlags;

drivers/gpu/drm/radeon/sislands_smc.h

213

uint8_t maxVDDCIndexInPPTable;

drivers/gpu/drm/radeon/sislands_smc.h

214

uint8_t extraFlags;

drivers/gpu/drm/radeon/sislands_smc.h

250

uint8_t fdo_mode;

drivers/gpu/drm/radeon/sislands_smc.h

251

uint8_t padding;

drivers/gpu/drm/radeon/sislands_smc.h

267

uint8_t temp_src;

drivers/gpu/drm/radeon/sislands_smc.h

288

uint8_t lts_truncate_n;

drivers/gpu/drm/radeon/sislands_smc.h

289

uint8_t SHIFT_N;

drivers/gpu/drm/radeon/sislands_smc.h

290

uint8_t log2_PG_LKG_SCALE;

drivers/gpu/drm/radeon/sislands_smc.h

291

uint8_t cac_temp;

drivers/gpu/drm/radeon/sislands_smc.h

315

uint8_t last;

drivers/gpu/drm/radeon/sislands_smc.h

316

uint8_t reserved[3];

drivers/gpu/drm/radeon/sislands_smc.h

326

uint8_t mc_arb_rfsh_rate;

drivers/gpu/drm/radeon/sislands_smc.h

327

uint8_t mc_arb_burst_time;

drivers/gpu/drm/radeon/sislands_smc.h

328

uint8_t padding[2];

drivers/gpu/drm/radeon/sislands_smc.h

334

uint8_t arb_current;

drivers/gpu/drm/radeon/sislands_smc.h

335

uint8_t reserved[3];

drivers/gpu/drm/radeon/sislands_smc.h

34

uint8_t MaxPS;

drivers/gpu/drm/radeon/sislands_smc.h

35

uint8_t TgtAct;

drivers/gpu/drm/radeon/sislands_smc.h

36

uint8_t MaxPS_StepInc;

drivers/gpu/drm/radeon/sislands_smc.h

367

uint8_t WindowSize;

drivers/gpu/drm/radeon/sislands_smc.h

368

uint8_t Tdep_count;

drivers/gpu/drm/radeon/sislands_smc.h

369

uint8_t temp_select;

drivers/gpu/drm/radeon/sislands_smc.h

37

uint8_t MaxPS_StepDec;

drivers/gpu/drm/radeon/sislands_smc.h

370

uint8_t DTE_mode;

drivers/gpu/drm/radeon/sislands_smc.h

371

uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

drivers/gpu/drm/radeon/sislands_smc.h

38

uint8_t PSSamplingTime;

drivers/gpu/drm/radeon/sislands_smc.h

39

uint8_t NearTDPDec;

drivers/gpu/drm/radeon/sislands_smc.h

40

uint8_t AboveSafeInc;

drivers/gpu/drm/radeon/sislands_smc.h

41

uint8_t BelowSafeInc;

drivers/gpu/drm/radeon/sislands_smc.h

42

uint8_t PSDeltaLimit;

drivers/gpu/drm/radeon/sislands_smc.h

43

uint8_t PSDeltaWin;

drivers/gpu/drm/radeon/sislands_smc.h

45

uint8_t Reserved[4];

drivers/gpu/drm/radeon/sislands_smc.h

53

uint8_t CurrPSkip;

drivers/gpu/drm/radeon/sislands_smc.h

54

uint8_t CurrPSkipPowerShift;

drivers/gpu/drm/radeon/sislands_smc.h

55

uint8_t CurrPSkipTDP;

drivers/gpu/drm/radeon/sislands_smc.h

56

uint8_t CurrPSkipOCP;

drivers/gpu/drm/radeon/sislands_smc.h

57

uint8_t MaxSPLLIndex;

drivers/gpu/drm/radeon/sislands_smc.h

58

uint8_t MinSPLLIndex;

drivers/gpu/drm/radeon/sislands_smc.h

59

uint8_t CurrSPLLIndex;

drivers/gpu/drm/radeon/sislands_smc.h

60

uint8_t InfSweepMode;

drivers/gpu/drm/radeon/sislands_smc.h

61

uint8_t InfSweepDir;

drivers/gpu/drm/radeon/sislands_smc.h

62

uint8_t TDPexceeded;

drivers/gpu/drm/radeon/sislands_smc.h

63

uint8_t reserved;

drivers/gpu/drm/radeon/sislands_smc.h

64

uint8_t SwitchDownThreshold;

drivers/gpu/drm/radeon/sislands_smc.h

87

uint8_t dGPU_T_Limit_Exceeded;

drivers/gpu/drm/radeon/sislands_smc.h

88

uint8_t reserved[3];

drivers/gpu/drm/radeon/smu7_discrete.h

108

uint8_t padding1[2];

drivers/gpu/drm/radeon/smu7_discrete.h

117

uint8_t SclkDid;

drivers/gpu/drm/radeon/smu7_discrete.h

118

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_discrete.h

119

uint8_t EnabledForActivity;

drivers/gpu/drm/radeon/smu7_discrete.h

120

uint8_t EnabledForThrottle;

drivers/gpu/drm/radeon/smu7_discrete.h

121

uint8_t UpH;

drivers/gpu/drm/radeon/smu7_discrete.h

122

uint8_t DownH;

drivers/gpu/drm/radeon/smu7_discrete.h

123

uint8_t VoltageDownH;

drivers/gpu/drm/radeon/smu7_discrete.h

124

uint8_t PowerThrottle;

drivers/gpu/drm/radeon/smu7_discrete.h

125

uint8_t DeepSleepDivId;

drivers/gpu/drm/radeon/smu7_discrete.h

126

uint8_t padding[3];

drivers/gpu/drm/radeon/smu7_discrete.h

136

uint8_t SclkDid;

drivers/gpu/drm/radeon/smu7_discrete.h

137

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_discrete.h

138

uint8_t DeepSleepDivId;

drivers/gpu/drm/radeon/smu7_discrete.h

139

uint8_t padding;

drivers/gpu/drm/radeon/smu7_discrete.h

156

uint8_t VddcOffsetVid;

drivers/gpu/drm/radeon/smu7_discrete.h

157

uint8_t VddcPhase;

drivers/gpu/drm/radeon/smu7_discrete.h

171

uint8_t EdcReadEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

172

uint8_t EdcWriteEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

173

uint8_t RttEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

174

uint8_t StutterEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

176

uint8_t StrobeEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

177

uint8_t StrobeRatio;

drivers/gpu/drm/radeon/smu7_discrete.h

178

uint8_t EnabledForThrottle;

drivers/gpu/drm/radeon/smu7_discrete.h

179

uint8_t EnabledForActivity;

drivers/gpu/drm/radeon/smu7_discrete.h

181

uint8_t UpH;

drivers/gpu/drm/radeon/smu7_discrete.h

182

uint8_t DownH;

drivers/gpu/drm/radeon/smu7_discrete.h

183

uint8_t VoltageDownH;

drivers/gpu/drm/radeon/smu7_discrete.h

184

uint8_t padding;

drivers/gpu/drm/radeon/smu7_discrete.h

187

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_discrete.h

188

uint8_t padding1;

drivers/gpu/drm/radeon/smu7_discrete.h

204

uint8_t PcieGenSpeed;

drivers/gpu/drm/radeon/smu7_discrete.h

205

uint8_t PcieLaneCount;

drivers/gpu/drm/radeon/smu7_discrete.h

206

uint8_t EnabledForActivity;

drivers/gpu/drm/radeon/smu7_discrete.h

207

uint8_t Padding;

drivers/gpu/drm/radeon/smu7_discrete.h

219

uint8_t McArbBurstTime;

drivers/gpu/drm/radeon/smu7_discrete.h

220

uint8_t padding[3];

drivers/gpu/drm/radeon/smu7_discrete.h

235

uint8_t MinVddcPhases;

drivers/gpu/drm/radeon/smu7_discrete.h

236

uint8_t VclkDivider;

drivers/gpu/drm/radeon/smu7_discrete.h

237

uint8_t DclkDivider;

drivers/gpu/drm/radeon/smu7_discrete.h

238

uint8_t padding[3];

drivers/gpu/drm/radeon/smu7_discrete.h

246

uint8_t MinPhases;

drivers/gpu/drm/radeon/smu7_discrete.h

247

uint8_t Divider;

drivers/gpu/drm/radeon/smu7_discrete.h

262

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_discrete.h

263

uint8_t McArbIndex;

drivers/gpu/drm/radeon/smu7_discrete.h

264

uint8_t McRegIndex;

drivers/gpu/drm/radeon/smu7_discrete.h

265

uint8_t SeqIndex;

drivers/gpu/drm/radeon/smu7_discrete.h

266

uint8_t SclkDid;

drivers/gpu/drm/radeon/smu7_discrete.h

269

uint8_t PCIeGen;

drivers/gpu/drm/radeon/smu7_discrete.h

298

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

299

uint8_t MemoryDpmLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

300

uint8_t LinkLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

301

uint8_t UvdLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

302

uint8_t VceLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

303

uint8_t AcpLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

304

uint8_t SamuLevelCount;

drivers/gpu/drm/radeon/smu7_discrete.h

305

uint8_t MasterDeepSleepControl;

drivers/gpu/drm/radeon/smu7_discrete.h

323

uint8_t UvdBootLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

324

uint8_t VceBootLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

325

uint8_t AcpBootLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

326

uint8_t SamuBootLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

328

uint8_t UVDInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

329

uint8_t VCEInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

330

uint8_t ACPInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

331

uint8_t SAMUInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

333

uint8_t GraphicsBootLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

334

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

335

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

336

uint8_t GraphicsInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

338

uint8_t VoltageInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

339

uint8_t ThermalInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

343

uint8_t MemoryBootLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

344

uint8_t MemoryVoltageChangeEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

346

uint8_t MemoryInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

347

uint8_t MemoryThermThrottleEnable;

drivers/gpu/drm/radeon/smu7_discrete.h

353

uint8_t PCIeBootLinkLevel;

drivers/gpu/drm/radeon/smu7_discrete.h

354

uint8_t PCIeGenInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

355

uint8_t DTEInterval;

drivers/gpu/drm/radeon/smu7_discrete.h

356

uint8_t DTEMode;

drivers/gpu/drm/radeon/smu7_discrete.h

358

uint8_t SVI2Enable;

drivers/gpu/drm/radeon/smu7_discrete.h

359

uint8_t VRHotGpio;

drivers/gpu/drm/radeon/smu7_discrete.h

360

uint8_t AcDcGpio;

drivers/gpu/drm/radeon/smu7_discrete.h

361

uint8_t ThermGpio;

drivers/gpu/drm/radeon/smu7_discrete.h

375

uint8_t DTEAmbientTempBase;

drivers/gpu/drm/radeon/smu7_discrete.h

376

uint8_t DTETjOffset;

drivers/gpu/drm/radeon/smu7_discrete.h

377

uint8_t GpuTjMax;

drivers/gpu/drm/radeon/smu7_discrete.h

378

uint8_t GpuTjHyst;

drivers/gpu/drm/radeon/smu7_discrete.h

410

uint8_t last;

drivers/gpu/drm/radeon/smu7_discrete.h

411

uint8_t reserved[3];

drivers/gpu/drm/radeon/smu7_discrete.h

435

uint8_t TempSrc;

drivers/gpu/drm/radeon/smu7_discrete.h

444

uint8_t BapmVddCVidHiSidd[8];

drivers/gpu/drm/radeon/smu7_discrete.h

447

uint8_t BapmVddCVidLoSidd[8];

drivers/gpu/drm/radeon/smu7_discrete.h

450

uint8_t VddCVid[8];

drivers/gpu/drm/radeon/smu7_discrete.h

453

uint8_t SviLoadLineEn;

drivers/gpu/drm/radeon/smu7_discrete.h

454

uint8_t SviLoadLineVddC;

drivers/gpu/drm/radeon/smu7_discrete.h

455

uint8_t SviLoadLineTrimVddC;

drivers/gpu/drm/radeon/smu7_discrete.h

456

uint8_t SviLoadLineOffsetVddC;

drivers/gpu/drm/radeon/smu7_discrete.h

460

uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;

drivers/gpu/drm/radeon/smu7_discrete.h

461

uint8_t TDC_MAWt;

drivers/gpu/drm/radeon/smu7_discrete.h

464

uint8_t TdcWaterfallCtl;

drivers/gpu/drm/radeon/smu7_discrete.h

465

uint8_t LPMLTemperatureMin;

drivers/gpu/drm/radeon/smu7_discrete.h

466

uint8_t LPMLTemperatureMax;

drivers/gpu/drm/radeon/smu7_discrete.h

467

uint8_t Reserved;

drivers/gpu/drm/radeon/smu7_discrete.h

470

uint8_t BapmVddCVidHiSidd2[8];

drivers/gpu/drm/radeon/smu7_discrete.h

479

uint8_t GnbLPML[16];

drivers/gpu/drm/radeon/smu7_discrete.h

482

uint8_t GnbLPMLMaxVid;

drivers/gpu/drm/radeon/smu7_discrete.h

483

uint8_t GnbLPMLMinVid;

drivers/gpu/drm/radeon/smu7_discrete.h

484

uint8_t Reserved1[2];

drivers/gpu/drm/radeon/smu7_discrete.h

54

uint8_t DisplayPhy1Config;

drivers/gpu/drm/radeon/smu7_discrete.h

55

uint8_t DisplayPhy2Config;

drivers/gpu/drm/radeon/smu7_discrete.h

56

uint8_t DisplayPhy3Config;

drivers/gpu/drm/radeon/smu7_discrete.h

57

uint8_t DisplayPhy4Config;

drivers/gpu/drm/radeon/smu7_discrete.h

59

uint8_t DisplayPhy5Config;

drivers/gpu/drm/radeon/smu7_discrete.h

60

uint8_t DisplayPhy6Config;

drivers/gpu/drm/radeon/smu7_discrete.h

61

uint8_t DisplayPhy7Config;

drivers/gpu/drm/radeon/smu7_discrete.h

62

uint8_t DisplayPhy8Config;

drivers/gpu/drm/radeon/smu7_discrete.h

68

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

69

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

70

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

71

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

73

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

74

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

75

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

76

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_discrete.h

95

uint8_t Smio;

drivers/gpu/drm/radeon/smu7_discrete.h

96

uint8_t padding;

drivers/gpu/drm/radeon/smu7_fusion.h

101

uint8_t DownH;

drivers/gpu/drm/radeon/smu7_fusion.h

102

uint8_t VoltageDownH;

drivers/gpu/drm/radeon/smu7_fusion.h

103

uint8_t DeepSleepDivId;

drivers/gpu/drm/radeon/smu7_fusion.h

105

uint8_t ClkBypassCntl;

drivers/gpu/drm/radeon/smu7_fusion.h

113

uint8_t EnabledForActivity;

drivers/gpu/drm/radeon/smu7_fusion.h

114

uint8_t LclkDid;

drivers/gpu/drm/radeon/smu7_fusion.h

115

uint8_t Vid;

drivers/gpu/drm/radeon/smu7_fusion.h

116

uint8_t VoltageDownH;

drivers/gpu/drm/radeon/smu7_fusion.h

121

uint8_t UpH;

drivers/gpu/drm/radeon/smu7_fusion.h

122

uint8_t DownH;

drivers/gpu/drm/radeon/smu7_fusion.h

126

uint8_t ActivityLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

127

uint8_t EnabledForThrottle;

drivers/gpu/drm/radeon/smu7_fusion.h

129

uint8_t ClkBypassCntl;

drivers/gpu/drm/radeon/smu7_fusion.h

131

uint8_t padding;

drivers/gpu/drm/radeon/smu7_fusion.h

141

uint8_t VclkDivider;

drivers/gpu/drm/radeon/smu7_fusion.h

142

uint8_t DclkDivider;

drivers/gpu/drm/radeon/smu7_fusion.h

144

uint8_t VClkBypassCntl;

drivers/gpu/drm/radeon/smu7_fusion.h

145

uint8_t DClkBypassCntl;

drivers/gpu/drm/radeon/smu7_fusion.h

147

uint8_t padding[2];

drivers/gpu/drm/radeon/smu7_fusion.h

157

uint8_t Divider;

drivers/gpu/drm/radeon/smu7_fusion.h

158

uint8_t ClkBypassCntl;

drivers/gpu/drm/radeon/smu7_fusion.h

168

uint8_t SclkDid;

drivers/gpu/drm/radeon/smu7_fusion.h

169

uint8_t GnbSlow;

drivers/gpu/drm/radeon/smu7_fusion.h

170

uint8_t ForceNbPs1;

drivers/gpu/drm/radeon/smu7_fusion.h

171

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_fusion.h

172

uint8_t DeepSleepDivId;

drivers/gpu/drm/radeon/smu7_fusion.h

173

uint8_t padding[3];

drivers/gpu/drm/radeon/smu7_fusion.h

179

uint8_t DpmXNbPsHi;

drivers/gpu/drm/radeon/smu7_fusion.h

180

uint8_t DpmXNbPsLo;

drivers/gpu/drm/radeon/smu7_fusion.h

181

uint8_t Dpm0PgNbPsHi;

drivers/gpu/drm/radeon/smu7_fusion.h

182

uint8_t Dpm0PgNbPsLo;

drivers/gpu/drm/radeon/smu7_fusion.h

183

uint8_t EnablePsi1;

drivers/gpu/drm/radeon/smu7_fusion.h

184

uint8_t SkipDPM0;

drivers/gpu/drm/radeon/smu7_fusion.h

185

uint8_t SkipPG;

drivers/gpu/drm/radeon/smu7_fusion.h

186

uint8_t Hysteresis;

drivers/gpu/drm/radeon/smu7_fusion.h

187

uint8_t EnableDpmPstatePoll;

drivers/gpu/drm/radeon/smu7_fusion.h

188

uint8_t padding[3];

drivers/gpu/drm/radeon/smu7_fusion.h

201

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_fusion.h

202

uint8_t McArbIndex;

drivers/gpu/drm/radeon/smu7_fusion.h

215

uint8_t GraphicsDpmLevelCount;

drivers/gpu/drm/radeon/smu7_fusion.h

216

uint8_t GIOLevelCount;

drivers/gpu/drm/radeon/smu7_fusion.h

217

uint8_t UvdLevelCount;

drivers/gpu/drm/radeon/smu7_fusion.h

218

uint8_t VceLevelCount;

drivers/gpu/drm/radeon/smu7_fusion.h

220

uint8_t AcpLevelCount;

drivers/gpu/drm/radeon/smu7_fusion.h

221

uint8_t SamuLevelCount;

drivers/gpu/drm/radeon/smu7_fusion.h

231

uint8_t UvdBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

232

uint8_t VceBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

233

uint8_t AcpBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

234

uint8_t SamuBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

235

uint8_t UVDInterval;

drivers/gpu/drm/radeon/smu7_fusion.h

236

uint8_t VCEInterval;

drivers/gpu/drm/radeon/smu7_fusion.h

237

uint8_t ACPInterval;

drivers/gpu/drm/radeon/smu7_fusion.h

238

uint8_t SAMUInterval;

drivers/gpu/drm/radeon/smu7_fusion.h

240

uint8_t GraphicsBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

241

uint8_t GraphicsInterval;

drivers/gpu/drm/radeon/smu7_fusion.h

242

uint8_t GraphicsThermThrottleEnable;

drivers/gpu/drm/radeon/smu7_fusion.h

243

uint8_t GraphicsVoltageChangeEnable;

drivers/gpu/drm/radeon/smu7_fusion.h

245

uint8_t GraphicsClkSlowEnable;

drivers/gpu/drm/radeon/smu7_fusion.h

246

uint8_t GraphicsClkSlowDivider;

drivers/gpu/drm/radeon/smu7_fusion.h

268

uint8_t Enable;

drivers/gpu/drm/radeon/smu7_fusion.h

269

uint8_t GIOVoltageChangeEnable;

drivers/gpu/drm/radeon/smu7_fusion.h

270

uint8_t GIOBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

271

uint8_t padding;

drivers/gpu/drm/radeon/smu7_fusion.h

272

uint8_t padding1[2];

drivers/gpu/drm/radeon/smu7_fusion.h

273

uint8_t TargetState;

drivers/gpu/drm/radeon/smu7_fusion.h

274

uint8_t CurrenttState;

drivers/gpu/drm/radeon/smu7_fusion.h

275

uint8_t ThrottleOnHtc;

drivers/gpu/drm/radeon/smu7_fusion.h

276

uint8_t ThermThrottleStatus;

drivers/gpu/drm/radeon/smu7_fusion.h

277

uint8_t ThermThrottleTempSelect;

drivers/gpu/drm/radeon/smu7_fusion.h

278

uint8_t ThermThrottleEnable;

drivers/gpu/drm/radeon/smu7_fusion.h

45

uint8_t DisplayPhy1Config;

drivers/gpu/drm/radeon/smu7_fusion.h

46

uint8_t DisplayPhy2Config;

drivers/gpu/drm/radeon/smu7_fusion.h

47

uint8_t DisplayPhy3Config;

drivers/gpu/drm/radeon/smu7_fusion.h

48

uint8_t DisplayPhy4Config;

drivers/gpu/drm/radeon/smu7_fusion.h

50

uint8_t DisplayPhy5Config;

drivers/gpu/drm/radeon/smu7_fusion.h

51

uint8_t DisplayPhy6Config;

drivers/gpu/drm/radeon/smu7_fusion.h

52

uint8_t DisplayPhy7Config;

drivers/gpu/drm/radeon/smu7_fusion.h

53

uint8_t DisplayPhy8Config;

drivers/gpu/drm/radeon/smu7_fusion.h

59

uint8_t SClkDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

60

uint8_t MClkDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

61

uint8_t LClkDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

62

uint8_t PCIeDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

64

uint8_t UVDDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

65

uint8_t SAMUDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

66

uint8_t ACPDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

67

uint8_t VCEDpmEnabledLevels;

drivers/gpu/drm/radeon/smu7_fusion.h

87

uint8_t Vid;

drivers/gpu/drm/radeon/smu7_fusion.h

88

uint8_t VidOffset;

drivers/gpu/drm/radeon/smu7_fusion.h

91

uint8_t PowerThrottle;

drivers/gpu/drm/radeon/smu7_fusion.h

92

uint8_t GnbSlow;

drivers/gpu/drm/radeon/smu7_fusion.h

93

uint8_t ForceNbPs1;

drivers/gpu/drm/radeon/smu7_fusion.h

94

uint8_t SclkDid;

drivers/gpu/drm/radeon/smu7_fusion.h

96

uint8_t DisplayWatermark;

drivers/gpu/drm/radeon/smu7_fusion.h

97

uint8_t EnabledForActivity;

drivers/gpu/drm/radeon/smu7_fusion.h

98

uint8_t EnabledForThrottle;

drivers/gpu/drm/radeon/smu7_fusion.h

99

uint8_t UpH;

drivers/gpu/drm/rockchip/rockchip_drm_vop.h

53

uint8_t shift;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

196

uint8_t axi_bus_id;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

197

uint8_t axi_yrgb_r_id;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

198

uint8_t axi_uv_r_id;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1377

static struct vop2_win *vop2_find_win_by_phys_id(struct vop2 *vop2, uint8_t phys_id)

drivers/gpu/drm/sitronix/st7920.c

127

reg[i++] = TOP_VERTICAL_ADDRESS + (*(uint8_t *)data & HIGH_DATA_MASK);

drivers/gpu/drm/sitronix/st7920.c

129

reg[i++] = BOTTOM_VERTICAL_ADDRESS + (*(uint8_t *)data & HIGH_DATA_MASK);

drivers/gpu/drm/sitronix/st7920.c

131

reg[i++] = *(uint8_t *)data << 4;

drivers/gpu/drm/sti/sti_hdmi.c

1227

static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)

drivers/gpu/drm/tilcdc/tilcdc_drv.c

409

uint8_t rev;

drivers/gpu/drm/tilcdc/tilcdc_drv.c

410

uint8_t save;

drivers/gpu/drm/ttm/ttm_bo_vm.c

370

uint8_t *buf, int len, int write)

drivers/gpu/drm/ttm/ttm_bo_vm.c

390

ptr = (uint8_t *)ttm_kmap_obj_virtual(&map, &is_iomem) + offset;

drivers/gpu/drm/udl/udl_transfer.c

157

cmd = (uint8_t *) cmd_buffer_end;

drivers/gpu/drm/udl/udl_transfer.c

36

static inline u16 get_pixel_val16(const uint8_t *pixel, int log_bpp)

drivers/gpu/drm/udl/udl_transfer.c

77

uint8_t **command_buffer_ptr,

drivers/gpu/drm/udl/udl_transfer.c

78

const uint8_t *const cmd_buffer_end, int log_bpp)

drivers/gpu/drm/udl/udl_transfer.c

83

uint8_t *cmd = *command_buffer_ptr;

drivers/gpu/drm/udl/udl_transfer.c

87

uint8_t *raw_pixels_count_byte = NULL;

drivers/gpu/drm/udl/udl_transfer.c

88

uint8_t *cmd_pixels_count_byte = NULL;

drivers/gpu/drm/udl/udl_transfer.c

95

*cmd++ = (uint8_t) ((dev_addr >> 16) & 0xFF);

drivers/gpu/drm/udl/udl_transfer.c

96

*cmd++ = (uint8_t) ((dev_addr >> 8) & 0xFF);

drivers/gpu/drm/udl/udl_transfer.c

97

*cmd++ = (uint8_t) ((dev_addr) & 0xFF);

drivers/gpu/drm/vc4/vc4_drv.h

1081

uint32_t offset, uint8_t tiling_format,

drivers/gpu/drm/vc4/vc4_drv.h

1082

uint32_t width, uint32_t height, uint8_t cpp);

drivers/gpu/drm/vc4/vc4_drv.h

741

uint8_t bin_tiles_x, bin_tiles_y;

drivers/gpu/drm/vc4/vc4_hdmi.c

665

uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};

drivers/gpu/drm/vc4/vc4_render_cl.c

104

uint8_t x, uint8_t y)

drivers/gpu/drm/vc4/vc4_render_cl.c

127

uint8_t x, uint8_t y, bool first, bool last)

drivers/gpu/drm/vc4/vc4_render_cl.c

260

uint8_t min_x_tile = args->min_x_tile;

drivers/gpu/drm/vc4/vc4_render_cl.c

261

uint8_t min_y_tile = args->min_y_tile;

drivers/gpu/drm/vc4/vc4_render_cl.c

262

uint8_t max_x_tile = args->max_x_tile;

drivers/gpu/drm/vc4/vc4_render_cl.c

263

uint8_t max_y_tile = args->max_y_tile;

drivers/gpu/drm/vc4/vc4_render_cl.c

264

uint8_t xtiles = max_x_tile - min_x_tile + 1;

drivers/gpu/drm/vc4/vc4_render_cl.c

265

uint8_t ytiles = max_y_tile - min_y_tile + 1;

drivers/gpu/drm/vc4/vc4_render_cl.c

266

uint8_t xi, yi;

drivers/gpu/drm/vc4/vc4_render_cl.c

442

uint8_t tiling = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

444

uint8_t buffer = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

446

uint8_t format = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

541

uint8_t tiling = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

543

uint8_t format = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_validate.c

166

uint32_t offset, uint8_t tiling_format,

drivers/gpu/drm/vc4/vc4_validate.c

167

uint32_t width, uint32_t height, uint8_t cpp)

drivers/gpu/drm/vc4/vc4_validate.c

272

uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1;

drivers/gpu/drm/vc4/vc4_validate.c

360

uint8_t flags;

drivers/gpu/drm/vc4/vc4_validate.c

371

exec->bin_tiles_x = *(uint8_t *)(untrusted + 12);

drivers/gpu/drm/vc4/vc4_validate.c

372

exec->bin_tiles_y = *(uint8_t *)(untrusted + 13);

drivers/gpu/drm/vc4/vc4_validate.c

374

flags = *(uint8_t *)(untrusted + 14);

drivers/gpu/drm/vc4/vc4_validate.c

412

*(uint8_t *)(validated + 14) =

drivers/gpu/drm/vc4/vc4_validate.c

503

u8 cmd = *(uint8_t *)src_pkt;

drivers/gpu/drm/vc4/vc4_validate.c

897

uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1;

drivers/gpu/drm/vc4/vc4_validate.c

898

uint32_t stride = *(uint8_t *)(pkt_u + o + 5);

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

387

uint8_t *cmd;

drivers/gpu/drm/vmwgfx/vmwgfx_context.c

596

uint8_t *cmd;

drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c

44

uint8_t type;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

162

uint8_t num_input_sig,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

163

uint8_t num_output_sig,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

39

uint8_t num_input_sig;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

40

uint8_t num_output_sig;

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

690

uint8_t num_input_sig,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

691

uint8_t num_output_sig,

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

772

uint8_t num_input_sig, uint8_t num_output_sig,

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

1322

uint8_t *cmd;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

387

uint8_t *cmd;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

465

uint8_t *cmd;

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

548

uint8_t *cmd;

drivers/hid/hid-logitech-hidpp.c

2186

uint8_t presence;

drivers/hid/hid-logitech-hidpp.c

2187

uint8_t desired_state;

drivers/hid/hid-logitech-hidpp.c

2188

uint8_t state;

drivers/hid/hid-logitech-hidpp.c

2189

uint8_t persistent;

drivers/hid/hid-roccat-arvo.c

403

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-arvo.h

15

uint8_t command; /* ARVO_COMMAND_MODE_KEY */

drivers/hid/hid-roccat-arvo.h

16

uint8_t state;

drivers/hid/hid-roccat-arvo.h

20

uint8_t unknown[24];

drivers/hid/hid-roccat-arvo.h

24

uint8_t unknown[8];

drivers/hid/hid-roccat-arvo.h

28

uint8_t command; /* ARVO_COMMAND_KEY_MASK */

drivers/hid/hid-roccat-arvo.h

29

uint8_t key_mask;

drivers/hid/hid-roccat-arvo.h

34

uint8_t command; /* ARVO_COMMAND_ACTUAL_PROFILE */

drivers/hid/hid-roccat-arvo.h

35

uint8_t actual_profile;

drivers/hid/hid-roccat-arvo.h

47

uint8_t unknown1; /* always 0x01 */

drivers/hid/hid-roccat-arvo.h

48

uint8_t event;

drivers/hid/hid-roccat-arvo.h

49

uint8_t unknown2; /* always 0x70 */

drivers/hid/hid-roccat-arvo.h

63

uint8_t profile;

drivers/hid/hid-roccat-arvo.h

64

uint8_t button;

drivers/hid/hid-roccat-arvo.h

65

uint8_t action;

drivers/hid/hid-roccat-common.c

16

static inline uint16_t roccat_common2_feature_report(uint8_t report_id)

drivers/hid/hid-roccat-common.h

20

uint8_t command;

drivers/hid/hid-roccat-common.h

21

uint8_t value;

drivers/hid/hid-roccat-common.h

22

uint8_t request; /* always 0 on requesting write check */

drivers/hid/hid-roccat-isku.c

101

roccat_report_event(isku->chrdev_minor, (uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-isku.c

398

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-isku.h

38

uint8_t command; /* ISKU_COMMAND_ACTUAL_PROFILE */

drivers/hid/hid-roccat-isku.h

39

uint8_t size; /* always 3 */

drivers/hid/hid-roccat-isku.h

40

uint8_t actual_profile;

drivers/hid/hid-roccat-isku.h

66

uint8_t number; /* ISKU_REPORT_NUMBER_BUTTON */

drivers/hid/hid-roccat-isku.h

67

uint8_t zero;

drivers/hid/hid-roccat-isku.h

68

uint8_t event;

drivers/hid/hid-roccat-isku.h

69

uint8_t data1;

drivers/hid/hid-roccat-isku.h

70

uint8_t data2;

drivers/hid/hid-roccat-isku.h

82

uint8_t event;

drivers/hid/hid-roccat-isku.h

83

uint8_t data1;

drivers/hid/hid-roccat-isku.h

84

uint8_t data2;

drivers/hid/hid-roccat-isku.h

85

uint8_t profile;

drivers/hid/hid-roccat-kone.c

111

uint8_t data;

drivers/hid/hid-roccat-kone.c

233

uint8_t data;

drivers/hid/hid-roccat-kone.c

50

roccat_report_event(kone->chrdev_minor, (uint8_t *)&roccat_report);

drivers/hid/hid-roccat-kone.c

823

(uint8_t *)&roccat_report);

drivers/hid/hid-roccat-kone.c

832

(uint8_t *)&roccat_report);

drivers/hid/hid-roccat-kone.h

103

uint8_t profile; /* range 1-5 */

drivers/hid/hid-roccat-kone.h

106

uint8_t xy_sensitivity_enabled; /* 1 = on, 2 = off */

drivers/hid/hid-roccat-kone.h

109

uint8_t dpi_rate; /* bit 1 = 800, ... */

drivers/hid/hid-roccat-kone.h

110

uint8_t startup_dpi; /* range 1-6 */

drivers/hid/hid-roccat-kone.h

111

uint8_t polling_rate; /* 1 = 125Hz, 2 = 500Hz, 3 = 1000Hz */

drivers/hid/hid-roccat-kone.h

116

uint8_t dcu_flag;

drivers/hid/hid-roccat-kone.h

117

uint8_t light_effect_1; /* range 1-3 */

drivers/hid/hid-roccat-kone.h

118

uint8_t light_effect_2; /* range 1-5 */

drivers/hid/hid-roccat-kone.h

119

uint8_t light_effect_3; /* range 1-4 */

drivers/hid/hid-roccat-kone.h

120

uint8_t light_effect_speed; /* range 0-255 */

drivers/hid/hid-roccat-kone.h

137

uint8_t startup_profile; /* 1-5 */

drivers/hid/hid-roccat-kone.h

138

uint8_t unknown1;

drivers/hid/hid-roccat-kone.h

139

uint8_t tcu; /* 0 = off, 1 = on */

drivers/hid/hid-roccat-kone.h

140

uint8_t unknown2[23];

drivers/hid/hid-roccat-kone.h

141

uint8_t calibration_data[4];

drivers/hid/hid-roccat-kone.h

142

uint8_t unknown3[2];

drivers/hid/hid-roccat-kone.h

15

uint8_t key;

drivers/hid/hid-roccat-kone.h

150

uint8_t report_number; /* always 1 */

drivers/hid/hid-roccat-kone.h

151

uint8_t button;

drivers/hid/hid-roccat-kone.h

154

uint8_t wheel; /* up = 1, down = -1 */

drivers/hid/hid-roccat-kone.h

156

uint8_t tilt; /* right = 1, left = -1 */

drivers/hid/hid-roccat-kone.h

157

uint8_t unknown;

drivers/hid/hid-roccat-kone.h

158

uint8_t event;

drivers/hid/hid-roccat-kone.h

159

uint8_t value; /* press = 0, release = 1 */

drivers/hid/hid-roccat-kone.h

16

uint8_t action;

drivers/hid/hid-roccat-kone.h

160

uint8_t macro_key; /* 0 to 8 */

drivers/hid/hid-roccat-kone.h

188

uint8_t event;

drivers/hid/hid-roccat-kone.h

189

uint8_t value; /* holds dpi or profile value */

drivers/hid/hid-roccat-kone.h

190

uint8_t key; /* macro key on overlong macro execution */

drivers/hid/hid-roccat-kone.h

34

uint8_t number; /* range 1-8 */

drivers/hid/hid-roccat-kone.h

35

uint8_t type;

drivers/hid/hid-roccat-kone.h

36

uint8_t macro_type; /* 0 = short, 1 = overlong */

drivers/hid/hid-roccat-kone.h

37

uint8_t macro_set_name[16]; /* can be max 15 chars long */

drivers/hid/hid-roccat-kone.h

38

uint8_t macro_name[16]; /* can be max 15 chars long */

drivers/hid/hid-roccat-kone.h

39

uint8_t count;

drivers/hid/hid-roccat-kone.h

87

uint8_t number; /* number of light 1-5 */

drivers/hid/hid-roccat-kone.h

88

uint8_t mod; /* 1 = on, 2 = off */

drivers/hid/hid-roccat-kone.h

89

uint8_t red; /* range 0x00-0xff */

drivers/hid/hid-roccat-kone.h

90

uint8_t green; /* range 0x00-0xff */

drivers/hid/hid-roccat-kone.h

91

uint8_t blue; /* range 0x00-0xff */

drivers/hid/hid-roccat-koneplus.c

283

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-koneplus.c

510

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-koneplus.h

107

uint8_t type;

drivers/hid/hid-roccat-koneplus.h

108

uint8_t data1;

drivers/hid/hid-roccat-koneplus.h

109

uint8_t data2;

drivers/hid/hid-roccat-koneplus.h

110

uint8_t profile;

drivers/hid/hid-roccat-koneplus.h

34

uint8_t command; /* KONEPLUS_COMMAND_ACTUAL_PROFILE */

drivers/hid/hid-roccat-koneplus.h

35

uint8_t size; /* always 3 */

drivers/hid/hid-roccat-koneplus.h

36

uint8_t actual_profile; /* Range 0-4! */

drivers/hid/hid-roccat-koneplus.h

40

uint8_t command; /* KONEPLUS_COMMAND_INFO */

drivers/hid/hid-roccat-koneplus.h

41

uint8_t size; /* always 6 */

drivers/hid/hid-roccat-koneplus.h

42

uint8_t firmware_version;

drivers/hid/hid-roccat-koneplus.h

43

uint8_t unknown[3];

drivers/hid/hid-roccat-koneplus.h

69

uint8_t report_number; /* always KONEPLUS_MOUSE_REPORT_NUMBER_BUTTON */

drivers/hid/hid-roccat-koneplus.h

70

uint8_t zero1;

drivers/hid/hid-roccat-koneplus.h

71

uint8_t type;

drivers/hid/hid-roccat-koneplus.h

72

uint8_t data1;

drivers/hid/hid-roccat-koneplus.h

73

uint8_t data2;

drivers/hid/hid-roccat-koneplus.h

74

uint8_t zero2;

drivers/hid/hid-roccat-koneplus.h

75

uint8_t unknown[2];

drivers/hid/hid-roccat-konepure.c

30

uint8_t report_number; /* always KONEPURE_MOUSE_REPORT_NUMBER_BUTTON */

drivers/hid/hid-roccat-konepure.c

31

uint8_t zero;

drivers/hid/hid-roccat-konepure.c

32

uint8_t type;

drivers/hid/hid-roccat-konepure.c

33

uint8_t data1;

drivers/hid/hid-roccat-konepure.c

34

uint8_t data2;

drivers/hid/hid-roccat-konepure.c

35

uint8_t zero2;

drivers/hid/hid-roccat-konepure.c

36

uint8_t unknown[2];

drivers/hid/hid-roccat-kovaplus.c

313

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-kovaplus.c

601

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-kovaplus.h

111

uint8_t type;

drivers/hid/hid-roccat-kovaplus.h

112

uint8_t profile;

drivers/hid/hid-roccat-kovaplus.h

113

uint8_t button;

drivers/hid/hid-roccat-kovaplus.h

114

uint8_t data1;

drivers/hid/hid-roccat-kovaplus.h

115

uint8_t data2;

drivers/hid/hid-roccat-kovaplus.h

29

uint8_t command; /* KOVAPLUS_COMMAND_ACTUAL_PROFILE */

drivers/hid/hid-roccat-kovaplus.h

30

uint8_t size; /* always 3 */

drivers/hid/hid-roccat-kovaplus.h

31

uint8_t actual_profile; /* Range 0-4! */

drivers/hid/hid-roccat-kovaplus.h

35

uint8_t command; /* KOVAPLUS_COMMAND_PROFILE_SETTINGS */

drivers/hid/hid-roccat-kovaplus.h

36

uint8_t size; /* 16 */

drivers/hid/hid-roccat-kovaplus.h

37

uint8_t profile_index; /* range 0-4 */

drivers/hid/hid-roccat-kovaplus.h

38

uint8_t unknown1;

drivers/hid/hid-roccat-kovaplus.h

39

uint8_t sensitivity_x; /* range 1-10 */

drivers/hid/hid-roccat-kovaplus.h

40

uint8_t sensitivity_y; /* range 1-10 */

drivers/hid/hid-roccat-kovaplus.h

41

uint8_t cpi_levels_enabled;

drivers/hid/hid-roccat-kovaplus.h

42

uint8_t cpi_startup_level; /* range 1-4 */

drivers/hid/hid-roccat-kovaplus.h

43

uint8_t data[8];

drivers/hid/hid-roccat-kovaplus.h

47

uint8_t command; /* KOVAPLUS_COMMAND_PROFILE_BUTTONS */

drivers/hid/hid-roccat-kovaplus.h

48

uint8_t size; /* 23 */

drivers/hid/hid-roccat-kovaplus.h

49

uint8_t profile_index; /* range 0-4 */

drivers/hid/hid-roccat-kovaplus.h

50

uint8_t data[20];

drivers/hid/hid-roccat-kovaplus.h

54

uint8_t command; /* KOVAPLUS_COMMAND_INFO */

drivers/hid/hid-roccat-kovaplus.h

55

uint8_t size; /* 6 */

drivers/hid/hid-roccat-kovaplus.h

56

uint8_t firmware_version;

drivers/hid/hid-roccat-kovaplus.h

57

uint8_t unknown[3];

drivers/hid/hid-roccat-kovaplus.h

77

uint8_t report_number; /* KOVAPLUS_MOUSE_REPORT_NUMBER_BUTTON */

drivers/hid/hid-roccat-kovaplus.h

78

uint8_t unknown1;

drivers/hid/hid-roccat-kovaplus.h

79

uint8_t type;

drivers/hid/hid-roccat-kovaplus.h

80

uint8_t data1;

drivers/hid/hid-roccat-kovaplus.h

81

uint8_t data2;

drivers/hid/hid-roccat-pyra.c

269

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-pyra.c

527

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-pyra.c

541

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-pyra.h

135

uint8_t type;

drivers/hid/hid-roccat-pyra.h

136

uint8_t value;

drivers/hid/hid-roccat-pyra.h

137

uint8_t key;

drivers/hid/hid-roccat-pyra.h

28

uint8_t command; /* PYRA_COMMAND_SETTINGS */

drivers/hid/hid-roccat-pyra.h

29

uint8_t size; /* always 3 */

drivers/hid/hid-roccat-pyra.h

30

uint8_t startup_profile; /* Range 0-4! */

drivers/hid/hid-roccat-pyra.h

34

uint8_t command; /* PYRA_COMMAND_PROFILE_SETTINGS */

drivers/hid/hid-roccat-pyra.h

35

uint8_t size; /* always 0xd */

drivers/hid/hid-roccat-pyra.h

36

uint8_t number; /* Range 0-4 */

drivers/hid/hid-roccat-pyra.h

37

uint8_t xysync;

drivers/hid/hid-roccat-pyra.h

38

uint8_t x_sensitivity; /* 0x1-0xa */

drivers/hid/hid-roccat-pyra.h

39

uint8_t y_sensitivity;

drivers/hid/hid-roccat-pyra.h

40

uint8_t x_cpi; /* unused */

drivers/hid/hid-roccat-pyra.h

41

uint8_t y_cpi; /* this value is for x and y */

drivers/hid/hid-roccat-pyra.h

42

uint8_t lightswitch; /* 0 = off, 1 = on */

drivers/hid/hid-roccat-pyra.h

43

uint8_t light_effect;

drivers/hid/hid-roccat-pyra.h

44

uint8_t handedness;

drivers/hid/hid-roccat-pyra.h

49

uint8_t command; /* PYRA_COMMAND_INFO */

drivers/hid/hid-roccat-pyra.h

50

uint8_t size; /* always 6 */

drivers/hid/hid-roccat-pyra.h

51

uint8_t firmware_version;

drivers/hid/hid-roccat-pyra.h

52

uint8_t unknown1; /* always 0 */

drivers/hid/hid-roccat-pyra.h

53

uint8_t unknown2; /* always 1 */

drivers/hid/hid-roccat-pyra.h

54

uint8_t unknown3; /* always 0 */

drivers/hid/hid-roccat-pyra.h

73

uint8_t report_number; /* always 3 */

drivers/hid/hid-roccat-pyra.h

74

uint8_t unknown; /* always 0 */

drivers/hid/hid-roccat-pyra.h

75

uint8_t type;

drivers/hid/hid-roccat-pyra.h

76

uint8_t data1;

drivers/hid/hid-roccat-pyra.h

77

uint8_t data2;

drivers/hid/hid-roccat-pyra.h

81

uint8_t report_number; /* always 2 */

drivers/hid/hid-roccat-pyra.h

82

uint8_t type;

drivers/hid/hid-roccat-pyra.h

83

uint8_t unused; /* always 0 */

drivers/hid/hid-roccat-ryos.c

27

uint8_t number; /* RYOS_REPORT_NUMBER_SPECIAL */

drivers/hid/hid-roccat-ryos.c

28

uint8_t data[4];

drivers/hid/hid-roccat-savu.c

169

(uint8_t const *)&roccat_report);

drivers/hid/hid-roccat-savu.h

15

uint8_t report_number; /* always 3 */

drivers/hid/hid-roccat-savu.h

16

uint8_t zero;

drivers/hid/hid-roccat-savu.h

17

uint8_t type;

drivers/hid/hid-roccat-savu.h

18

uint8_t data[2];

drivers/hid/hid-roccat-savu.h

48

uint8_t type;

drivers/hid/hid-roccat-savu.h

49

uint8_t data[2];

drivers/hid/hid-roccat.c

252

uint8_t *new_value;

drivers/hid/hid-roccat.c

36

uint8_t *value;

drivers/hid/hid-steelseries.c

34

uint8_t battery_capacity;

drivers/hid/hid-steelseries.c

524

static bool steelseries_is_vendor_usage_page(struct hid_device *hdev, uint8_t usage_page)

drivers/hid/hid-steelseries.c

618

static uint8_t steelseries_headset_map_capacity(uint8_t capacity, uint8_t min_in, uint8_t max_in)

drivers/hid/hid-thrustmaster.c

76

static const uint8_t tm_wheels_infos_length = 7;

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

22

uint8_t *i2c_hid_desc_buffer;

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

24

uint8_t *hid_report_desc;

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

26

uint8_t *i2c_name;

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

41

.i2c_hid_desc_buffer = (uint8_t [])

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

444

struct i2c_hid_desc *i2c_hid_get_dmi_i2c_hid_desc_override(uint8_t *i2c_name)

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

460

char *i2c_hid_get_dmi_hid_report_desc_override(uint8_t *i2c_name,

drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c

58

.hid_report_desc = (uint8_t [])

drivers/hid/i2c-hid/i2c-hid.h

10

char *i2c_hid_get_dmi_hid_report_desc_override(uint8_t *i2c_name,

drivers/hid/i2c-hid/i2c-hid.h

15

*i2c_hid_get_dmi_i2c_hid_desc_override(uint8_t *i2c_name)

drivers/hid/i2c-hid/i2c-hid.h

17

static inline char *i2c_hid_get_dmi_hid_report_desc_override(uint8_t *i2c_name,

drivers/hid/i2c-hid/i2c-hid.h

9

struct i2c_hid_desc *i2c_hid_get_dmi_i2c_hid_desc_override(uint8_t *i2c_name);

drivers/hid/intel-ish-hid/ipc/hw-ish.h

59

uint8_t ts1_source;

drivers/hid/intel-ish-hid/ipc/hw-ish.h

60

uint8_t ts2_source;

drivers/hid/intel-ish-hid/ishtp-hid-client.c

445

rv = ishtp_cl_send(client_data->hid_ishtp_cl, (uint8_t *)&msg,

drivers/hid/intel-ish-hid/ishtp-hid.h

25

uint8_t command; /* Bit 7: is_response */

drivers/hid/intel-ish-hid/ishtp-hid.h

26

uint8_t device_id;

drivers/hid/intel-ish-hid/ishtp-hid.h

27

uint8_t status;

drivers/hid/intel-ish-hid/ishtp-hid.h

28

uint8_t flags;

drivers/hid/intel-ish-hid/ishtp-hid.h

34

uint8_t payload[];

drivers/hid/intel-ish-hid/ishtp-hid.h

39

uint8_t report_id;

drivers/hid/intel-ish-hid/ishtp-hid.h

44

uint8_t dev_class;

drivers/hid/intel-ish-hid/ishtp-hid.h

50

uint8_t major;

drivers/hid/intel-ish-hid/ishtp-hid.h

51

uint8_t minor;

drivers/hid/intel-ish-hid/ishtp-hid.h

52

uint8_t hotfix;

drivers/hid/intel-ish-hid/ishtp-hid.h

64

uint8_t num_of_reports;

drivers/hid/intel-ish-hid/ishtp-hid.h

65

uint8_t flags;

drivers/hid/intel-ish-hid/ishtp/bus.c

188

int ishtp_fw_cl_by_id(struct ishtp_device *dev, uint8_t client_id)

drivers/hid/intel-ish-hid/ishtp/client.c

1085

uint8_t rd_msg_buf[ISHTP_RD_MSG_BUF_SIZE];

drivers/hid/intel-ish-hid/ishtp/client.c

674

int ishtp_cl_send(struct ishtp_cl *cl, uint8_t *buf, size_t length)

drivers/hid/intel-ish-hid/ishtp/client.h

112

int ishtp_fw_cl_by_id(struct ishtp_device *dev, uint8_t client_id);

drivers/hid/intel-ish-hid/ishtp/client.h

133

uint8_t size);

drivers/hid/intel-ish-hid/ishtp/client.h

46

uint8_t host_client_id;

drivers/hid/intel-ish-hid/ishtp/client.h

47

uint8_t fw_client_id;

drivers/hid/intel-ish-hid/ishtp/client.h

48

uint8_t ishtp_flow_ctrl_creds;

drivers/hid/intel-ish-hid/ishtp/client.h

49

uint8_t out_flow_ctrl_creds;

drivers/hid/intel-ish-hid/ishtp/dma-if.c

146

uint8_t size)

drivers/hid/intel-ish-hid/ishtp/dma-if.c

45

sizeof(uint8_t),

drivers/hid/intel-ish-hid/ishtp/hbm.c

194

uint8_t client_num;

drivers/hid/intel-ish-hid/ishtp/hbm.c

55

static inline void ishtp_hbm_cl_hdr(struct ishtp_cl *cl, uint8_t hbm_cmd,

drivers/hid/intel-ish-hid/ishtp/hbm.c

775

uint8_t rd_msg_buf[ISHTP_RD_MSG_BUF_SIZE];

drivers/hid/intel-ish-hid/ishtp/hbm.c

896

uint8_t rd_msg_buf[ISHTP_RD_MSG_BUF_SIZE];

drivers/hid/intel-ish-hid/ishtp/hbm.c

925

uint8_t cl_addr)

drivers/hid/intel-ish-hid/ishtp/hbm.h

100

uint8_t host_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

101

uint8_t data;

drivers/hid/intel-ish-hid/ishtp/hbm.h

105

uint8_t minor_version;

drivers/hid/intel-ish-hid/ishtp/hbm.h

106

uint8_t major_version;

drivers/hid/intel-ish-hid/ishtp/hbm.h

110

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

111

uint8_t reserved;

drivers/hid/intel-ish-hid/ishtp/hbm.h

116

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

117

uint8_t host_version_supported;

drivers/hid/intel-ish-hid/ishtp/hbm.h

122

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

123

uint8_t reason;

drivers/hid/intel-ish-hid/ishtp/hbm.h

124

uint8_t reserved[2];

drivers/hid/intel-ish-hid/ishtp/hbm.h

128

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

129

uint8_t reserved[3];

drivers/hid/intel-ish-hid/ishtp/hbm.h

133

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

134

uint8_t reserved[3];

drivers/hid/intel-ish-hid/ishtp/hbm.h

138

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

139

uint8_t reserved[3];

drivers/hid/intel-ish-hid/ishtp/hbm.h

140

uint8_t valid_addresses[32];

drivers/hid/intel-ish-hid/ishtp/hbm.h

145

uint8_t protocol_version;

drivers/hid/intel-ish-hid/ishtp/hbm.h

146

uint8_t max_number_of_connections;

drivers/hid/intel-ish-hid/ishtp/hbm.h

147

uint8_t fixed_address;

drivers/hid/intel-ish-hid/ishtp/hbm.h

148

uint8_t single_recv_buf;

drivers/hid/intel-ish-hid/ishtp/hbm.h

150

uint8_t dma_hdr_len;

drivers/hid/intel-ish-hid/ishtp/hbm.h

152

uint8_t reserved4;

drivers/hid/intel-ish-hid/ishtp/hbm.h

153

uint8_t reserved5;

drivers/hid/intel-ish-hid/ishtp/hbm.h

154

uint8_t reserved6;

drivers/hid/intel-ish-hid/ishtp/hbm.h

158

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

159

uint8_t address;

drivers/hid/intel-ish-hid/ishtp/hbm.h

160

uint8_t reserved[2];

drivers/hid/intel-ish-hid/ishtp/hbm.h

164

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

165

uint8_t address;

drivers/hid/intel-ish-hid/ishtp/hbm.h

166

uint8_t status;

drivers/hid/intel-ish-hid/ishtp/hbm.h

167

uint8_t reserved[1];

drivers/hid/intel-ish-hid/ishtp/hbm.h

180

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

181

uint8_t fw_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

182

uint8_t host_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

183

uint8_t reserved;

drivers/hid/intel-ish-hid/ishtp/hbm.h

195

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

196

uint8_t fw_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

197

uint8_t host_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

198

uint8_t status;

drivers/hid/intel-ish-hid/ishtp/hbm.h

205

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

206

uint8_t fw_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

207

uint8_t host_addr;

drivers/hid/intel-ish-hid/ishtp/hbm.h

208

uint8_t reserved[ISHTP_FC_MESSAGE_RESERVED_LENGTH];

drivers/hid/intel-ish-hid/ishtp/hbm.h

212

uint8_t hbm;

drivers/hid/intel-ish-hid/ishtp/hbm.h

213

uint8_t status;

drivers/hid/intel-ish-hid/ishtp/hbm.h

214

uint8_t reserved[2];

drivers/hid/intel-ish-hid/ishtp/hbm.h

221

uint8_t hbm;

drivers/hid/intel-ish-hid/ishtp/hbm.h

222

uint8_t fw_client_id;

drivers/hid/intel-ish-hid/ishtp/hbm.h

223

uint8_t host_client_id;

drivers/hid/intel-ish-hid/ishtp/hbm.h

224

uint8_t reserved;

drivers/hid/intel-ish-hid/ishtp/hbm.h

84

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

85

uint8_t data[];

drivers/hid/intel-ish-hid/ishtp/hbm.h

98

uint8_t hbm_cmd;

drivers/hid/intel-ish-hid/ishtp/hbm.h

99

uint8_t fw_addr;

drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h

227

uint8_t fw_clients_num;

drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h

228

uint8_t fw_client_presentation_num;

drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h

229

uint8_t fw_client_index;

drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h

240

uint8_t *ishtp_dma_tx_map;

drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h

74

uint8_t client_id;

drivers/hwmon/ads7871.c

160

uint8_t val;

drivers/hwmon/ads7871.c

98

uint8_t channel, mux_cnv;

drivers/hwmon/max1111.c

41

uint8_t tx_buf[MAX1111_TX_BUF_SIZE];

drivers/hwmon/max1111.c

42

uint8_t rx_buf[MAX1111_RX_BUF_SIZE];

drivers/hwmon/max1111.c

52

uint8_t v1, v2;

drivers/hwmon/tps23861.c

374

static char *port_operating_mode_string(uint8_t mode_reg, unsigned int port)

drivers/hwmon/tps23861.c

395

static char *port_detect_status_string(uint8_t status_reg)

drivers/hwmon/tps23861.c

427

static char *port_class_status_string(uint8_t status_reg)

drivers/hwmon/tps23861.c

452

static char *port_poe_plus_status_string(uint8_t poe_plus, unsigned int port)

drivers/i2c/busses/i2c-bcm-kona.c

112

uint8_t time_m; /* Number of cycles for setup time */

drivers/i2c/busses/i2c-bcm-kona.c

113

uint8_t time_n; /* Number of cycles for hold time */

drivers/i2c/busses/i2c-bcm-kona.c

114

uint8_t prescale; /* Prescale divider */

drivers/i2c/busses/i2c-bcm-kona.c

115

uint8_t time_p; /* Timing coefficient */

drivers/i2c/busses/i2c-bcm-kona.c

116

uint8_t no_div; /* Disable clock divider */

drivers/i2c/busses/i2c-bcm-kona.c

117

uint8_t time_div; /* Post-prescale divider */

drivers/i2c/busses/i2c-bcm-kona.c

122

uint8_t hs_hold; /* Number of clock cycles SCL stays low until

drivers/i2c/busses/i2c-bcm-kona.c

124

uint8_t hs_high_phase; /* Number of clock cycles SCL stays high

drivers/i2c/busses/i2c-bcm-kona.c

126

uint8_t hs_setup; /* Number of clock cycles SCL stays low

drivers/i2c/busses/i2c-bcm-kona.c

128

uint8_t prescale; /* Prescale divider */

drivers/i2c/busses/i2c-bcm-kona.c

129

uint8_t time_p; /* Timing coefficient */

drivers/i2c/busses/i2c-bcm-kona.c

130

uint8_t no_div; /* Disable clock divider */

drivers/i2c/busses/i2c-bcm-kona.c

131

uint8_t time_div; /* Post-prescale divider */

drivers/i2c/busses/i2c-bcm-kona.c

281

uint8_t *buf, unsigned int len,

drivers/i2c/busses/i2c-bcm-kona.c

324

uint8_t *tmp_buf = msg->buf;

drivers/i2c/busses/i2c-bcm-kona.c

345

static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,

drivers/i2c/busses/i2c-bcm-kona.c

392

uint8_t *buf, unsigned int len)

drivers/i2c/busses/i2c-bcm-kona.c

448

uint8_t *tmp_buf = msg->buf;

drivers/i2c/busses/i2c-gxp.c

420

buf = (uint8_t)value;

drivers/i2c/busses/i2c-piix4.c

687

static uint8_t piix4_imc_read(uint8_t idx)

drivers/i2c/busses/i2c-piix4.c

693

static void piix4_imc_write(uint8_t idx, uint8_t value)

drivers/i2c/busses/i2c-virtio.c

44

uint8_t *buf ____cacheline_aligned;

drivers/iio/accel/sca3000.c

364

uint8_t val)

drivers/iio/adc/ad4000.c

574

static int ad4000_write_reg(struct ad4000_state *st, uint8_t val)

drivers/iio/adc/ad7791.c

196

uint8_t mode;

drivers/iio/adc/ad7791.c

197

uint8_t filter;

drivers/iio/adc/ad7887.c

239

uint8_t mode;

drivers/iio/common/cros_ec_sensors/cros_ec_sensors_trace.h

26

TP_STRUCT__entry(__field(uint8_t, cmd)

drivers/iio/common/cros_ec_sensors/cros_ec_sensors_trace.h

27

__field(uint8_t, sensor_id)

drivers/iio/dac/ad7303.c

40

uint8_t dac_cache[2];

drivers/iio/dac/ad7303.c

54

uint8_t val)

drivers/iio/dac/ds4424.c

57

uint8_t save[DS4424_MAX_DAC_CHANNELS];

drivers/iio/dac/ds4424.c

59

uint8_t raw[DS4424_MAX_DAC_CHANNELS];

drivers/iio/dac/ti-dac7612.c

37

uint8_t data[2] __aligned(IIO_DMA_MINALIGN);

drivers/iio/imu/adis16400.c

342

uint8_t val = 0;

drivers/iio/imu/adis16400.c

464

static const uint8_t adis16400_addresses[] = {

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

135

int inv_mpu_aux_read(const struct inv_mpu6050_state *st, uint8_t addr,

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

136

uint8_t reg, uint8_t *val, size_t size)

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

175

int inv_mpu_aux_write(const struct inv_mpu6050_state *st, uint8_t addr,

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

176

uint8_t reg, uint8_t val)

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c

25

uint8_t d;

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h

13

int inv_mpu_aux_read(const struct inv_mpu6050_state *st, uint8_t addr,

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h

14

uint8_t reg, uint8_t *val, size_t size);

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h

16

int inv_mpu_aux_write(const struct inv_mpu6050_state *st, uint8_t addr,

drivers/iio/imu/inv_mpu6050/inv_mpu_aux.h

17

uint8_t reg, uint8_t val);

drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c

154

uint8_t val;

drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c

236

uint8_t d;

drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c

326

uint8_t addr;

drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c

62

uint8_t val;

drivers/iio/imu/inv_mpu6050/inv_mpu_magn.c

63

uint8_t asa[3];

drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c

109

uint8_t d;

drivers/iio/light/si1133.c

572

static int si1133_update_adcconfig(struct si1133_data *data, uint8_t adc,

drivers/iio/pressure/icp10100.c

100

static const uint8_t icp10100_switch_mode_otp[] =

drivers/iio/pressure/icp10100.c

125

uint8_t data[16];

drivers/iio/pressure/icp10100.c

126

uint8_t *ptr;

drivers/iio/pressure/icp10100.c

127

uint8_t *buf_ptr = (uint8_t *)buf;

drivers/iio/pressure/icp10100.c

133

.buf = (uint8_t *)&cmd->cmd,

drivers/iio/pressure/icp10100.c

141

uint8_t crc;

drivers/iio/temperature/mlx90632.c

425

static int mlx90632_channel_new_select(int perform_ret, uint8_t *channel_new,

drivers/iio/temperature/mlx90632.c

426

uint8_t *channel_old)

drivers/infiniband/core/cma.c

3800

struct rdma_id_private *id_priv, uint8_t reuseaddr)

drivers/infiniband/hw/bng_re/bng_tlv.h

24

#define GET_TLV_DATA(tlv) ((void *)&((uint8_t *)(tlv))[TLV_BYTES])

drivers/infiniband/hw/bnxt_re/qplib_tlv.h

46

#define GET_TLV_DATA(tlv) ((void *)&((uint8_t *)(tlv))[TLV_BYTES])

drivers/infiniband/hw/ionic/ionic_admin.c

223

src = (uint8_t *)&wr->wqe.cmd;

drivers/infiniband/hw/ionic/ionic_ibdev.h

384

uint8_t udma_idx)

drivers/infiniband/hw/mlx4/mcg.c

80

uint8_t join_state;

drivers/infiniband/hw/mlx5/cq.c

459

uint8_t opcode;

drivers/infiniband/hw/ocrdma/ocrdma.h

395

uint8_t signaled;

drivers/infiniband/hw/ocrdma/ocrdma.h

396

uint8_t rsvd[3];

drivers/infiniband/ulp/iser/iscsi_iser.c

174

static int iscsi_iser_pdu_alloc(struct iscsi_task *task, uint8_t opcode)

drivers/input/joystick/as5011.c

101

.buf = (uint8_t *)data

drivers/input/joystick/as5011.c

70

uint8_t aregaddr,

drivers/input/joystick/as5011.c

71

uint8_t avalue)

drivers/input/joystick/as5011.c

73

uint8_t data[2] = { aregaddr, avalue };

drivers/input/joystick/as5011.c

78

.buf = (uint8_t *)data

drivers/input/joystick/as5011.c

87

uint8_t aregaddr, signed char *value)

drivers/input/joystick/as5011.c

89

uint8_t data[2] = { aregaddr };

drivers/input/joystick/as5011.c

95

.buf = (uint8_t *)data

drivers/input/keyboard/adp5520-keys.c

39

uint8_t reg_val_lo, reg_val_hi;

drivers/input/keyboard/cros_ec_keyb.c

135

static bool cros_ec_keyb_has_ghosting(struct cros_ec_keyb *ckdev, uint8_t *buf)

drivers/input/keyboard/cros_ec_keyb.c

139

uint8_t *valid_keys = ckdev->valid_keys;

drivers/input/keyboard/cros_ec_keyb.c

176

uint8_t *kb_state, int len)

drivers/input/keyboard/cros_ec_keyb.c

53

uint8_t *valid_keys;

drivers/input/keyboard/cros_ec_keyb.c

54

uint8_t *old_kb_state;

drivers/input/keyboard/goldfish_events.c

56

uint8_t val;

drivers/input/keyboard/hil_kbd.c

329

uint8_t did = kbd->idd[0];

drivers/input/keyboard/hil_kbd.c

356

uint8_t did = ptr->idd[0];

drivers/input/keyboard/hil_kbd.c

357

uint8_t *idd = ptr->idd + 1;

drivers/input/keyboard/hil_kbd.c

447

uint8_t did, *idd;

drivers/input/misc/hp_sdc_rtc.c

136

static int64_t hp_sdc_rtc_read_i8042timer (uint8_t loadcmd, int numreg)

drivers/input/misc/hp_sdc_rtc.c

139

uint8_t tseq[26] = {

drivers/input/misc/hp_sdc_rtc.c

61

uint8_t status, uint8_t data)

drivers/input/misc/hp_sdc_rtc.c

70

uint8_t tseq[91];

drivers/input/serio/hil_mlc.c

813

uint8_t *idx, *last;

drivers/input/serio/hp_sdc.c

115

static inline uint8_t hp_sdc_status_in8(void)

drivers/input/serio/hp_sdc.c

117

uint8_t status;

drivers/input/serio/hp_sdc.c

129

static inline uint8_t hp_sdc_data_in8(void)

drivers/input/serio/hp_sdc.c

134

static inline void hp_sdc_status_out8(uint8_t val)

drivers/input/serio/hp_sdc.c

146

static inline void hp_sdc_data_out8(uint8_t val)

drivers/input/serio/hp_sdc.c

182

static void hp_sdc_take(int irq, void *dev_id, uint8_t status, uint8_t data)

drivers/input/serio/hp_sdc.c

222

uint8_t status, data;

drivers/input/serio/hp_sdc.c

315

uint8_t tmp;

drivers/input/serio/hp_sdc.c

352

uint8_t act;

drivers/input/serio/hp_sdc.c

474

uint8_t w7[4];

drivers/input/serio/hp_sdc.c

543

uint8_t postcmd;

drivers/input/serio/hp_sdc.c

833

uint8_t ts_sync[6];

drivers/input/serio/hp_sdc.c

998

uint8_t tq_init_seq[5];

drivers/input/serio/hp_sdc_mlc.c

62

uint8_t status, uint8_t data)

drivers/input/touchscreen/atmel_mxt_ts.c

1861

uint8_t num_objects;

drivers/input/touchscreen/auo-pixcir-ts.c

142

uint8_t raw_coord[8];

drivers/input/touchscreen/auo-pixcir-ts.c

143

uint8_t raw_area[4];

drivers/input/touchscreen/da9034-ts.c

83

uint8_t _x, _y, _v;

drivers/leds/leds-da903x.c

45

uint8_t val;

drivers/leds/leds-st1202.c

60

static int st1202_read_reg(struct st1202_chip *chip, int reg, uint8_t *val)

drivers/leds/leds-st1202.c

71

*val = (uint8_t)ret;

drivers/leds/leds-st1202.c

75

static int st1202_write_reg(struct st1202_chip *chip, int reg, uint8_t val)

drivers/leds/leds-st1202.c

87

static uint8_t st1202_prescalar_to_miliseconds(unsigned int value)

drivers/md/bcache/alloc.c

73

uint8_t bch_inc_gen(struct cache *ca, struct bucket *b)

drivers/md/bcache/alloc.c

75

uint8_t ret = ++b->gen;

drivers/md/bcache/bcache.h

1035

uint8_t *set_uuid);

drivers/md/bcache/bcache.h

200

uint8_t gen;

drivers/md/bcache/bcache.h

201

uint8_t last_gc; /* Most out of date gen in the btree */

drivers/md/bcache/bcache.h

632

uint8_t need_gc;

drivers/md/bcache/bcache.h

653

uint8_t gc_after_writeback;

drivers/md/bcache/bcache.h

679

uint8_t set_uuid[16];

drivers/md/bcache/bcache.h

834

static inline uint8_t gen_after(uint8_t a, uint8_t b)

drivers/md/bcache/bcache.h

836

uint8_t r = a - b;

drivers/md/bcache/bcache.h

841

static inline uint8_t ptr_stale(struct cache_set *c, const struct bkey *k,

drivers/md/bcache/bcache.h

923

static inline uint8_t bucket_gc_gen(struct bucket *b)

drivers/md/bcache/bcache.h

987

uint8_t bch_inc_gen(struct cache *ca, struct bucket *b);

drivers/md/bcache/bset.c

287

return btree_keys_cachelines(b) * sizeof(uint8_t);

drivers/md/bcache/bset.c

563

static inline uint64_t shrd128(uint64_t high, uint64_t low, uint8_t shift)

drivers/md/bcache/bset.h

183

uint8_t *prev;

drivers/md/bcache/bset.h

219

uint8_t page_order;

drivers/md/bcache/bset.h

220

uint8_t nsets;

drivers/md/bcache/btree.c

1226

static uint8_t __bch_btree_mark_key(struct cache_set *c, int level,

drivers/md/bcache/btree.c

1229

uint8_t stale = 0;

drivers/md/bcache/btree.c

1307

uint8_t stale = 0;

drivers/md/bcache/btree.h

133

uint8_t level;

drivers/md/bcache/super.c

1197

uint8_t *set_uuid)

drivers/md/bcache/sysfs.c

431

uint8_t set_uuid[16];

drivers/media/cec/platform/cros-ec/cros-ec-cec.c

60

uint8_t *msg, uint8_t len)

drivers/media/cec/platform/cros-ec/cros-ec-cec.c

74

uint8_t *cec_message = cros_ec->event_data.data.cec_message;

drivers/media/dvb-frontends/as102_fe.c

18

uint8_t elna_cfg;

drivers/media/dvb-frontends/as102_fe.c

26

static uint8_t as102_fe_get_code_rate(enum fe_code_rate arg)

drivers/media/dvb-frontends/as102_fe.c

28

uint8_t c;

drivers/media/dvb-frontends/as102_fe.c

445

uint8_t elna_cfg)

drivers/media/dvb-frontends/as102_fe.h

20

uint8_t elna_cfg);

drivers/media/dvb-frontends/as102_fe_types.h

100

uint8_t modulation;

drivers/media/dvb-frontends/as102_fe_types.h

101

uint8_t hierarchy;

drivers/media/dvb-frontends/as102_fe_types.h

102

uint8_t interleaving_mode;

drivers/media/dvb-frontends/as102_fe_types.h

103

uint8_t code_rate_HP;

drivers/media/dvb-frontends/as102_fe_types.h

104

uint8_t code_rate_LP;

drivers/media/dvb-frontends/as102_fe_types.h

105

uint8_t guard_interval;

drivers/media/dvb-frontends/as102_fe_types.h

106

uint8_t transmission_mode;

drivers/media/dvb-frontends/as102_fe_types.h

107

uint8_t DVBH_mask_HP;

drivers/media/dvb-frontends/as102_fe_types.h

108

uint8_t DVBH_mask_LP;

drivers/media/dvb-frontends/as102_fe_types.h

116

uint8_t bandwidth;

drivers/media/dvb-frontends/as102_fe_types.h

118

uint8_t hier_select;

drivers/media/dvb-frontends/as102_fe_types.h

120

uint8_t modulation;

drivers/media/dvb-frontends/as102_fe_types.h

122

uint8_t hierarchy;

drivers/media/dvb-frontends/as102_fe_types.h

124

uint8_t interleaving_mode;

drivers/media/dvb-frontends/as102_fe_types.h

126

uint8_t code_rate;

drivers/media/dvb-frontends/as102_fe_types.h

128

uint8_t guard_interval;

drivers/media/dvb-frontends/as102_fe_types.h

130

uint8_t transmission_mode;

drivers/media/dvb-frontends/as102_fe_types.h

135

uint8_t tune_state;

drivers/media/dvb-frontends/as102_fe_types.h

154

uint8_t has_started;

drivers/media/dvb-frontends/as102_fe_types.h

159

uint8_t type; /* Red TS_PID_TYPE_<N> values */

drivers/media/dvb-frontends/as102_fe_types.h

160

uint8_t idx; /* index in filtering table */

drivers/media/dvb-frontends/as102_fe_types.h

164

uint8_t mode;

drivers/media/dvb-frontends/as102_fe_types.h

166

uint8_t value8; /* 8 bit value */

drivers/media/dvb-frontends/as102_fe_types.h

176

uint8_t mode;

drivers/media/dvb-frontends/cxd2841er.c

2173

static const uint8_t nominalRate8bw[3][5] = {

drivers/media/dvb-frontends/cxd2841er.c

2180

static const uint8_t nominalRate7bw[3][5] = {

drivers/media/dvb-frontends/cxd2841er.c

2187

static const uint8_t nominalRate6bw[3][5] = {

drivers/media/dvb-frontends/cxd2841er.c

2194

static const uint8_t nominalRate5bw[3][5] = {

drivers/media/dvb-frontends/cxd2841er.c

2201

static const uint8_t nominalRate17bw[3][5] = {

drivers/media/dvb-frontends/cxd2841er.c

2208

static const uint8_t itbCoef8bw[3][14] = {

drivers/media/dvb-frontends/cxd2841er.c

2217

static const uint8_t itbCoef7bw[3][14] = {

drivers/media/dvb-frontends/cxd2841er.c

2226

static const uint8_t itbCoef6bw[3][14] = {

drivers/media/dvb-frontends/cxd2841er.c

2235

static const uint8_t itbCoef5bw[3][14] = {

drivers/media/dvb-frontends/cxd2841er.c

2244

static const uint8_t itbCoef17bw[3][14] = {

drivers/media/dvb-frontends/dib7000m.h

76

uint8_t onoff)

drivers/media/dvb-frontends/dib8000.c

1969

static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)

drivers/media/dvb-frontends/dib8000.h

53

u32 (*ctrl_timf)(struct dvb_frontend *fe, uint8_t op, uint32_t timf);

drivers/media/dvb-frontends/helene.c

136

uint8_t RF_GAIN;

drivers/media/dvb-frontends/helene.c

139

uint8_t IF_BPF_GC;

drivers/media/dvb-frontends/helene.c

143

uint8_t RFOVLD_DET_LV1_VL;

drivers/media/dvb-frontends/helene.c

147

uint8_t RFOVLD_DET_LV1_VH;

drivers/media/dvb-frontends/helene.c

151

uint8_t RFOVLD_DET_LV1_U;

drivers/media/dvb-frontends/helene.c

155

uint8_t IFOVLD_DET_LV_VL;

drivers/media/dvb-frontends/helene.c

159

uint8_t IFOVLD_DET_LV_VH;

drivers/media/dvb-frontends/helene.c

163

uint8_t IFOVLD_DET_LV_U;

drivers/media/dvb-frontends/helene.c

167

uint8_t IF_BPF_F0;

drivers/media/dvb-frontends/helene.c

172

uint8_t BW;

drivers/media/dvb-frontends/helene.c

176

uint8_t FIF_OFFSET;

drivers/media/dvb-frontends/helene.c

181

uint8_t BW_OFFSET;

drivers/media/dvb-frontends/helene.c

185

uint8_t IS_LOWERLOCAL;

drivers/media/dvb-frontends/helene.c

607

data[11] = (uint8_t)((symbol_rate * 47

drivers/media/dvb-frontends/helene.c

610

data[11] = (uint8_t)((symbol_rate * 27

drivers/media/dvb-frontends/helene.c

620

data[11] = (uint8_t)((symbol_rate * 11

drivers/media/dvb-frontends/helene.c

623

data[11] = (uint8_t)((symbol_rate * 3

drivers/media/dvb-frontends/helene.c

637

data[12] = (uint8_t)(frequency4kHz & 0xFF); /* FRF_L */

drivers/media/dvb-frontends/helene.c

638

data[13] = (uint8_t)((frequency4kHz >> 8) & 0xFF); /* FRF_M */

drivers/media/dvb-frontends/helene.c

640

data[14] = (uint8_t)((frequency4kHz >> 16) & 0x0F);

drivers/media/dvb-frontends/helene.c

709

data[1] = (uint8_t)(terr_params[tv_system].IS_LOWERLOCAL & 0x01);

drivers/media/dvb-frontends/helene.c

755

data[1] = (uint8_t)((terr_params[tv_system].RF_GAIN

drivers/media/dvb-frontends/helene.c

759

data[1] |= (uint8_t)(terr_params[tv_system].IF_BPF_GC & 0x0F);

drivers/media/dvb-frontends/helene.c

764

data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_VL

drivers/media/dvb-frontends/helene.c

766

data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_VL

drivers/media/dvb-frontends/helene.c

769

data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_VH

drivers/media/dvb-frontends/helene.c

771

data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_VH

drivers/media/dvb-frontends/helene.c

774

data[3] = (uint8_t)(terr_params[tv_system].RFOVLD_DET_LV1_U

drivers/media/dvb-frontends/helene.c

776

data[4] = (uint8_t)(terr_params[tv_system].IFOVLD_DET_LV_U

drivers/media/dvb-frontends/helene.c

784

data[5] = (uint8_t)((terr_params[tv_system].IF_BPF_F0 << 4) & 0x30);

drivers/media/dvb-frontends/helene.c

787

data[5] |= (uint8_t)(terr_params[tv_system].BW & 0x03);

drivers/media/dvb-frontends/helene.c

790

data[6] = (uint8_t)(terr_params[tv_system].FIF_OFFSET & 0x1F);

drivers/media/dvb-frontends/helene.c

793

data[7] = (uint8_t)(terr_params[tv_system].BW_OFFSET & 0x1F);

drivers/media/dvb-frontends/helene.c

796

data[8] = (uint8_t)(frequencykHz & 0xFF); /* FRF_L */

drivers/media/dvb-frontends/helene.c

797

data[9] = (uint8_t)((frequencykHz >> 8) & 0xFF); /* FRF_M */

drivers/media/dvb-frontends/helene.c

798

data[10] = (uint8_t)((frequencykHz >> 16)

drivers/media/dvb-frontends/helene.c

922

data[1] = (uint8_t)(0x80 | (0x04 & 0x1F)); /* 4 x 25 = 100uA */

drivers/media/dvb-frontends/helene.c

923

data[2] = (uint8_t)(0x80 | (0x26 & 0x7F)); /* 38 x 0.25 = 9.5pF */

drivers/media/dvb-frontends/helene.c

969

helene_write_reg(priv, 0x95, (uint8_t)((data[0] >> 4) & 0x0F));

drivers/media/i2c/adv7511-v4l2.c

214

static int adv7511_edid_rd(struct v4l2_subdev *sd, uint16_t len, uint8_t *buf)

drivers/media/i2c/saa6752hs.c

289

static inline void set_reg8(struct i2c_client *client, uint8_t reg, uint8_t val)

drivers/media/i2c/saa6752hs.c

298

static inline void set_reg16(struct i2c_client *client, uint8_t reg, uint16_t val)

drivers/media/i2c/tc358743.c

1369

uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);

drivers/media/i2c/ths8200.c

126

uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);

drivers/media/i2c/ths8200.c

216

uint8_t polarity = 0;

drivers/media/i2c/ths8200.c

42

uint8_t chip_version;

drivers/media/i2c/ths8200.c

98

uint8_t clr_mask, uint8_t val_mask)

drivers/media/platform/raspberrypi/pisp_be/pisp_be.c

1660

pispbe->done = (uint8_t)u;

drivers/media/platform/raspberrypi/pisp_be/pisp_be.c

1661

pispbe->started = (uint8_t)(u >> 8);

drivers/media/platform/raspberrypi/pisp_be/pisp_be.c

640

done = (uint8_t)u;

drivers/media/platform/raspberrypi/pisp_be/pisp_be.c

641

started = (uint8_t)(u >> 8);

drivers/media/platform/raspberrypi/rp1-cfe/dphy.c

60

static uint8_t get_tstdout(struct dphy_data *dphy)

drivers/media/platform/raspberrypi/rp1-cfe/dphy.c

82

static uint8_t dphy_transaction(struct dphy_data *dphy, u8 test_code,

drivers/media/platform/raspberrypi/rp1-cfe/dphy.c

83

uint8_t test_data)

drivers/media/rc/igorplugusb.c

183

usb_rcvctrlpipe(udev, 0), (uint8_t *)&ir->request,

drivers/media/rc/iguanair.c

26

uint8_t bufsize;

drivers/media/rc/iguanair.c

27

uint8_t cycle_overhead;

drivers/media/rc/iguanair.c

32

uint8_t *buf_in;

drivers/media/rc/iguanair.c

66

uint8_t direction;

drivers/media/rc/iguanair.c

67

uint8_t cmd;

drivers/media/rc/iguanair.c

72

uint8_t length;

drivers/media/rc/iguanair.c

73

uint8_t channels;

drivers/media/rc/iguanair.c

74

uint8_t busy7;

drivers/media/rc/iguanair.c

75

uint8_t busy4;

drivers/media/rc/iguanair.c

76

uint8_t payload[];

drivers/media/rc/ttusbir.c

108

static void ttusbir_process_ir_data(struct ttusbir *tt, uint8_t *buf)

drivers/media/rc/ttusbir.c

35

uint8_t bulk_buffer[5];

drivers/media/test-drivers/vicodec/codec-fwht.c

32

static const uint8_t zigzag[64] = {

drivers/media/tuners/r820t.c

1241

uint8_t mix_index = 0, lna_index = 0;

drivers/media/usb/as102/as102_drv.h

54

uint8_t elna_cfg;

drivers/media/usb/as102/as102_fw.c

126

(uint8_t *)

drivers/media/usb/as102/as102_fw.c

141

(uint8_t *)

drivers/media/usb/as102/as102_usb_drv.c

49

static uint8_t const as102_elna_cfg[] = {

drivers/media/usb/as102/as10x_cmd.c

130

(uint8_t *) preq,

drivers/media/usb/as102/as10x_cmd.c

133

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.c

176

(uint8_t *) preq,

drivers/media/usb/as102/as10x_cmd.c

178

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.c

227

(uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd.c

230

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.c

286

(uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd.c

289

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.c

327

uint8_t *is_ready)

drivers/media/usb/as102/as10x_cmd.c

346

(uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd.c

349

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.c

35

error = adap->ops->xfer_cmd(adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd.c

38

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.c

77

adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd.c

79

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd.h

108

uint8_t err;

drivers/media/usb/as102/as10x_cmd.h

125

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

140

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

157

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

174

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

186

uint8_t stream_type;

drivers/media/usb/as102/as10x_cmd.h

188

uint8_t idx;

drivers/media/usb/as102/as10x_cmd.h

195

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

197

uint8_t filter_id;

drivers/media/usb/as102/as10x_cmd.h

214

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

229

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

244

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

259

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

276

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

278

uint8_t is_ready;

drivers/media/usb/as102/as10x_cmd.h

303

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

322

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

339

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

351

uint8_t mode;

drivers/media/usb/as102/as10x_cmd.h

358

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

377

uint8_t dump_req;

drivers/media/usb/as102/as10x_cmd.h

388

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

390

uint8_t dump_rsp;

drivers/media/usb/as102/as10x_cmd.h

393

uint8_t data8[DUMP_BLOCK_SIZE];

drivers/media/usb/as102/as10x_cmd.h

405

uint8_t dump_req;

drivers/media/usb/as102/as10x_cmd.h

411

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

413

uint8_t dump_rsp;

drivers/media/usb/as102/as10x_cmd.h

415

uint8_t data[DUMP_BLOCK_SIZE];

drivers/media/usb/as102/as10x_cmd.h

423

uint8_t data[64 - sizeof(struct as10x_cmd_header_t)

drivers/media/usb/as102/as10x_cmd.h

429

uint8_t error;

drivers/media/usb/as102/as10x_cmd.h

430

uint8_t data[64 - sizeof(struct as10x_cmd_header_t)

drivers/media/usb/as102/as10x_cmd.h

493

uint8_t *is_ready);

drivers/media/usb/as102/as10x_cmd.h

512

int as10x_cmd_eLNA_change_mode(struct as10x_bus_adapter_t *adap, uint8_t mode);

drivers/media/usb/as102/as10x_cmd.h

93

uint8_t error;

drivers/media/usb/as102/as10x_cmd_cfg.c

102

(uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_cfg.c

105

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd_cfg.c

134

int as10x_cmd_eLNA_change_mode(struct as10x_bus_adapter_t *adap, uint8_t mode)

drivers/media/usb/as102/as10x_cmd_cfg.c

153

error = adap->ops->xfer_cmd(adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_cfg.c

155

+ HEADER_SIZE, (uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd_cfg.c

44

(uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_cfg.c

47

(uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd_stream.c

138

error = adap->ops->xfer_cmd(adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_stream.c

140

+ HEADER_SIZE, (uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd_stream.c

181

error = adap->ops->xfer_cmd(adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_stream.c

183

+ HEADER_SIZE, (uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd_stream.c

44

error = adap->ops->xfer_cmd(adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_stream.c

46

+ HEADER_SIZE, (uint8_t *) prsp,

drivers/media/usb/as102/as10x_cmd_stream.c

95

error = adap->ops->xfer_cmd(adap, (uint8_t *) pcmd,

drivers/media/usb/as102/as10x_cmd_stream.c

97

+ HEADER_SIZE, (uint8_t *) prsp,

drivers/media/usb/as102/as10x_handle.h

34

int (*read_write)(struct as10x_bus_adapter_t *bus_adap, uint8_t mode,

drivers/media/usb/dvb-usb/cinergyT2.h

56

uint8_t bandwidth;

drivers/media/usb/dvb-usb/cinergyT2.h

58

uint8_t flags;

drivers/media/usb/dvb-usb/cinergyT2.h

60

uint8_t snr;

drivers/media/usb/dvb-usb/cinergyT2.h

64

uint8_t lock_bits;

drivers/media/usb/dvb-usb/cinergyT2.h

65

uint8_t prev_lock_bits;

drivers/media/usb/dvb-usb/cinergyT2.h

70

uint8_t cmd;

drivers/media/usb/dvb-usb/cinergyT2.h

72

uint8_t bandwidth;

drivers/media/usb/dvb-usb/cinergyT2.h

74

uint8_t flags;

drivers/media/usb/dvb-usb/dib0700_core.c

166

uint8_t bus_mode = 1; /* 0=eeprom bus, 1=frontend bus */

drivers/media/usb/dvb-usb/dib0700_core.c

167

uint8_t gen_mode = 0; /* 0=master i2c, 1=gpio i2c */

drivers/media/usb/dvb-usb/dib0700_core.c

168

uint8_t en_start = 0;

drivers/media/usb/dvb-usb/dib0700_core.c

169

uint8_t en_stop = 0;

drivers/media/usb/dvb-usb/dib0700_core.c

197

uint8_t i2c_dest;

drivers/media/usb/gspca/kinect.c

101

static int kinect_write(struct usb_device *udev, uint8_t *data,

drivers/media/usb/gspca/kinect.c

111

static int kinect_read(struct usb_device *udev, uint8_t *data, uint16_t wLength)

drivers/media/usb/gspca/kinect.c

126

uint8_t *obuf = sd->obuf;

drivers/media/usb/gspca/kinect.c

127

uint8_t *ibuf = sd->ibuf;

drivers/media/usb/gspca/kinect.c

277

uint8_t fmt_reg, fmt_val;

drivers/media/usb/gspca/kinect.c

278

uint8_t res_reg, res_val;

drivers/media/usb/gspca/kinect.c

279

uint8_t fps_reg, fps_val;

drivers/media/usb/gspca/kinect.c

280

uint8_t mode_val;

drivers/media/usb/gspca/kinect.c

29

uint8_t magic[2];

drivers/media/usb/gspca/kinect.c

30

uint8_t pad;

drivers/media/usb/gspca/kinect.c

31

uint8_t flag;

drivers/media/usb/gspca/kinect.c

32

uint8_t unk1;

drivers/media/usb/gspca/kinect.c

33

uint8_t seq;

drivers/media/usb/gspca/kinect.c

34

uint8_t unk2;

drivers/media/usb/gspca/kinect.c

35

uint8_t unk3;

drivers/media/usb/gspca/kinect.c

384

uint8_t *data = __data + sizeof(*hdr);

drivers/media/usb/gspca/kinect.c

387

uint8_t sof = sd->stream_flag | 1;

drivers/media/usb/gspca/kinect.c

388

uint8_t mof = sd->stream_flag | 2;

drivers/media/usb/gspca/kinect.c

389

uint8_t eof = sd->stream_flag | 5;

drivers/media/usb/gspca/kinect.c

40

uint8_t magic[2];

drivers/media/usb/gspca/kinect.c

50

uint8_t stream_flag; /* to identify different stream types */

drivers/media/usb/gspca/kinect.c

51

uint8_t obuf[0x400]; /* output buffer for control commands */

drivers/media/usb/gspca/kinect.c

52

uint8_t ibuf[0x200]; /* input buffer for control commands */

drivers/mfd/adp5520.c

103

int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask)

drivers/mfd/adp5520.c

106

uint8_t reg_val;

drivers/mfd/adp5520.c

123

int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask)

drivers/mfd/adp5520.c

126

uint8_t reg_val;

drivers/mfd/adp5520.c

178

uint8_t reg_val;

drivers/mfd/adp5520.c

39

uint8_t mode;

drivers/mfd/adp5520.c

43

int reg, uint8_t *val)

drivers/mfd/adp5520.c

53

*val = (uint8_t)ret;

drivers/mfd/adp5520.c

58

int reg, uint8_t val)

drivers/mfd/adp5520.c

72

uint8_t bit_mask)

drivers/mfd/adp5520.c

75

uint8_t reg_val;

drivers/mfd/adp5520.c

91

int adp5520_write(struct device *dev, int reg, uint8_t val)

drivers/mfd/adp5520.c

97

int adp5520_read(struct device *dev, int reg, uint8_t *val)

drivers/mfd/da903x.c

100

int reg, uint8_t val)

drivers/mfd/da903x.c

114

int len, uint8_t *val)

drivers/mfd/da903x.c

146

int da903x_write(struct device *dev, int reg, uint8_t val)

drivers/mfd/da903x.c

152

int da903x_writes(struct device *dev, int reg, int len, uint8_t *val)

drivers/mfd/da903x.c

158

int da903x_read(struct device *dev, int reg, uint8_t *val)

drivers/mfd/da903x.c

164

int da903x_reads(struct device *dev, int reg, int len, uint8_t *val)

drivers/mfd/da903x.c

170

int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask)

drivers/mfd/da903x.c

173

uint8_t reg_val;

drivers/mfd/da903x.c

192

int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask)

drivers/mfd/da903x.c

195

uint8_t reg_val;

drivers/mfd/da903x.c

214

int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask)

drivers/mfd/da903x.c

217

uint8_t reg_val;

drivers/mfd/da903x.c

248

uint8_t chip_id;

drivers/mfd/da903x.c

265

uint8_t v[3];

drivers/mfd/da903x.c

278

uint8_t v[3];

drivers/mfd/da903x.c

291

uint8_t v[3] = {0, 0, 0};

drivers/mfd/da903x.c

304

return __da903x_read(chip->client, DA9030_STATUS, (uint8_t *)status);

drivers/mfd/da903x.c

309

uint8_t chip_id;

drivers/mfd/da903x.c

342

uint8_t v[4];

drivers/mfd/da903x.c

356

uint8_t v[4];

drivers/mfd/da903x.c

370

uint8_t v[4] = {0, 0, 0, 0};

drivers/mfd/da903x.c

383

uint8_t v[2] = {0, 0};

drivers/mfd/da903x.c

72

int reg, uint8_t *val)

drivers/mfd/da903x.c

82

*val = (uint8_t)ret;

drivers/mfd/da903x.c

87

int len, uint8_t *val)

drivers/mfd/da9055-core.c

358

uint8_t clear_events[3] = {0xFF, 0xFF, 0xFF};

drivers/mfd/rc5t583-irq.c

241

uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS];

drivers/mfd/rc5t583-irq.c

242

uint8_t master_int = 0;

drivers/mfd/rc5t583.c

157

uint8_t on_off_val = 0;

drivers/mfd/rc5t583.c

75

uint8_t sleepseq_val = 0;

drivers/mfd/si476x-cmd.c

373

uint8_t cmd,

drivers/mfd/si476x-cmd.c

374

const uint8_t args[], size_t argn,

drivers/mfd/si476x-cmd.c

375

uint8_t *resp, size_t respn)

drivers/mfd/tps6586x.c

142

int tps6586x_write(struct device *dev, int reg, uint8_t val)

drivers/mfd/tps6586x.c

150

int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val)

drivers/mfd/tps6586x.c

158

int tps6586x_read(struct device *dev, int reg, uint8_t *val)

drivers/mfd/tps6586x.c

171

int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val)

drivers/mfd/tps6586x.c

179

int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask)

drivers/mfd/tps6586x.c

187

int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask)

drivers/mfd/tps6586x.c

195

int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask)

drivers/mfd/tps6586x.c

315

sizeof(acks), (uint8_t *)&val);

drivers/misc/amd-sbi/rmi-i2c.c

57

static int sbrmi_common_probe(struct device *dev, struct regmap *regmap, uint8_t address)

drivers/misc/eeprom/at25.c

150

static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,

drivers/mmc/host/cb710-mmc.c

179

static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask)

drivers/mtd/chips/cfi_cmdset_0002.c

1419

uint8_t lockreg;

drivers/mtd/chips/cfi_cmdset_0002.c

1489

uint8_t otp, lockreg;

drivers/mtd/chips/jedec_probe.c

1976

uint8_t uaddr;

drivers/mtd/chips/jedec_probe.c

2038

uint8_t uaddr;

drivers/mtd/chips/jedec_probe.c

2051

mfr = (uint8_t)finfo->mfr_id;

drivers/mtd/chips/jedec_probe.c

2052

id = (uint8_t)finfo->dev_id;

drivers/mtd/chips/jedec_probe.c

272

const uint8_t dev_size;

drivers/mtd/chips/jedec_probe.c

273

const uint8_t nr_regions;

drivers/mtd/chips/jedec_probe.c

276

const uint8_t devtypes; /* Bitmask for x8, x16 etc. */

drivers/mtd/chips/jedec_probe.c

277

const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */

drivers/mtd/devices/st_spi_fsm.c

1152

uint8_t sta;

drivers/mtd/devices/st_spi_fsm.c

1209

uint8_t vcr;

drivers/mtd/devices/st_spi_fsm.c

1284

static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby)

drivers/mtd/devices/st_spi_fsm.c

1315

*dby = (uint8_t)(tmp >> 24);

drivers/mtd/devices/st_spi_fsm.c

1320

static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby)

drivers/mtd/devices/st_spi_fsm.c

1393

uint8_t sr1, cr1, dyb;

drivers/mtd/devices/st_spi_fsm.c

1478

uint8_t sr1, sr2;

drivers/mtd/devices/st_spi_fsm.c

1513

static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,

drivers/mtd/devices/st_spi_fsm.c

1524

uint8_t *p;

drivers/mtd/devices/st_spi_fsm.c

1537

p = ((uintptr_t)buf & 0x3) ? (uint8_t *)page_buf : buf;

drivers/mtd/devices/st_spi_fsm.c

1574

static int stfsm_write(struct stfsm *fsm, const uint8_t *buf,

drivers/mtd/devices/st_spi_fsm.c

1586

uint8_t *t = (uint8_t *)&tmp;

drivers/mtd/devices/st_spi_fsm.c

1587

const uint8_t *p;

drivers/mtd/devices/st_spi_fsm.c

1603

p = (uint8_t *)page_buf;

drivers/mtd/devices/st_spi_fsm.c

1752

uint8_t *b = (uint8_t *)buf;

drivers/mtd/devices/st_spi_fsm.c

1831

static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec)

drivers/mtd/devices/st_spi_fsm.c

251

uint8_t seq[16];

drivers/mtd/devices/st_spi_fsm.c

277

uint8_t cmd; /* FLASH command */

drivers/mtd/devices/st_spi_fsm.c

279

uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */

drivers/mtd/devices/st_spi_fsm.c

280

uint8_t data_pads; /* No. of data pads */

drivers/mtd/devices/st_spi_fsm.c

281

uint8_t mode_data; /* MODE data */

drivers/mtd/devices/st_spi_fsm.c

282

uint8_t mode_cycles; /* No. of MODE cycles */

drivers/mtd/devices/st_spi_fsm.c

283

uint8_t dummy_cycles; /* No. of DUMMY cycles */

drivers/mtd/devices/st_spi_fsm.c

475

#define N25Q_VCR_XIP_DISABLED ((uint8_t)0x1 << 3)

drivers/mtd/devices/st_spi_fsm.c

866

static uint8_t stfsm_wait_busy(struct stfsm *fsm)

drivers/mtd/devices/st_spi_fsm.c

899

return (uint8_t)(status & 0xff);

drivers/mtd/devices/st_spi_fsm.c

913

static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd,

drivers/mtd/devices/st_spi_fsm.c

914

uint8_t *data, int bytes)

drivers/mtd/devices/st_spi_fsm.c

918

uint8_t *t = (uint8_t *)&tmp;

drivers/mtd/devices/st_spi_fsm.c

941

static int stfsm_write_status(struct stfsm *fsm, uint8_t cmd,

drivers/mtd/inftlcore.c

137

size_t *retlen, uint8_t *buf)

drivers/mtd/inftlcore.c

157

size_t *retlen, uint8_t *buf)

drivers/mtd/inftlcore.c

177

size_t *retlen, uint8_t *buf, uint8_t *oob)

drivers/mtd/maps/dc21285.c

132

d.x[0] = *((uint8_t*)from);

drivers/mtd/maps/dc21285.c

57

val.x[0] = *(uint8_t*)(map->virt + ofs);

drivers/mtd/maps/dc21285.c

86

*(uint8_t*)(map->virt + adr) = d.x[0];

drivers/mtd/mtdchar.c

599

uint8_t *datbuf = NULL, *oobbuf = NULL;

drivers/mtd/mtdchar.c

698

uint8_t *datbuf = NULL, *oobbuf = NULL;

drivers/mtd/mtdswap.c

376

ops.oobbuf = (uint8_t *)&n;

drivers/mtd/nand/onenand/onenand_base.c

1051

static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column,

drivers/mtd/nand/onenand/onenand_bbt.c

149

uint8_t res;

drivers/mtd/nand/onenand/onenand_bbt.c

213

static uint8_t scan_ff_pattern[] = { 0xff, 0xff };

drivers/mtd/nand/onenand/onenand_bbt.c

32

static int check_short_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)

drivers/mtd/nand/onenand/onenand_bbt.c

35

uint8_t *p = buf;

drivers/mtd/nand/onenand/onenand_bbt.c

56

static int create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip)

drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c

136

const uint8_t *buf, int len)

drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c

339

uint8_t *buf, int len)

drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c

355

const uint8_t *buf, int len)

drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c

85

static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,

drivers/mtd/nand/raw/brcmnand/brcmnand.c

2284

static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/brcmnand/brcmnand.c

2295

static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/brcmnand/brcmnand.c

2407

static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/brcmnand/brcmnand.c

2417

static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/cafe_nand.c

120

static void cafe_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)

drivers/mtd/nand/raw/cafe_nand.c

135

static void cafe_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/cafe_nand.c

149

static uint8_t cafe_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/cafe_nand.c

152

uint8_t d;

drivers/mtd/nand/raw/cafe_nand.c

370

static int cafe_nand_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/cafe_nand.c

485

static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };

drivers/mtd/nand/raw/cafe_nand.c

486

static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };

drivers/mtd/nand/raw/cafe_nand.c

488

static uint8_t cafe_bbt_pattern_512[] = { 0xBB };

drivers/mtd/nand/raw/cafe_nand.c

489

static uint8_t cafe_mirror_pattern_512[] = { 0xBC };

drivers/mtd/nand/raw/cafe_nand.c

534

const uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/diskonchip.c

135

static int doc_ecc_decode(struct rs_control *rs, uint8_t *data, uint8_t *ecc)

drivers/mtd/nand/raw/diskonchip.c

138

uint8_t parity;

drivers/mtd/nand/raw/diskonchip.c

185

uint8_t val;

drivers/mtd/nand/raw/diskonchip.c

196

val = (uint8_t) (errval[i] >> (2 + bitpos));

drivers/mtd/nand/raw/diskonchip.c

206

val = (uint8_t) (errval[i] << (8 - bitpos));

drivers/mtd/nand/raw/diskonchip.c

377

uint8_t byte[4];

drivers/mtd/nand/raw/diskonchip.c

765

uint8_t calc_ecc[6];

drivers/mtd/nand/raw/fsl_elbc_nand.c

632

static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/fsl_elbc_nand.c

653

static int fsl_elbc_write_page(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/fsl_elbc_nand.c

668

uint32_t data_len, const uint8_t *buf,

drivers/mtd/nand/raw/fsl_ifc_nand.c

535

static uint8_t fsl_ifc_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/fsl_ifc_nand.c

557

static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip)

drivers/mtd/nand/raw/fsl_ifc_nand.c

569

return (uint8_t) data;

drivers/mtd/nand/raw/fsl_ifc_nand.c

667

static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/fsl_ifc_nand.c

695

static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/fsl_upm.c

27

uint8_t upm_addr_offset;

drivers/mtd/nand/raw/fsl_upm.c

28

uint8_t upm_cmd_offset;

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1079

static uint8_t scan_ff_pattern[] = { 0xff };

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1544

static int gpmi_ecc_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1579

chip->oob_poi[0] = ((uint8_t *)this->auxiliary_virt)[0];

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1587

uint32_t len, uint8_t *buf, int page)

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1682

static int gpmi_ecc_write_page(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1829

static int gpmi_ecc_read_page_raw(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1841

uint8_t *oob = chip->oob_poi;

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1914

static int gpmi_ecc_write_page_raw(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

1923

uint8_t *oob = chip->oob_poi;

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

2000

uint8_t *block_mark;

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

2180

uint8_t block_mark;

drivers/mtd/nand/raw/hisi504_nand.c

357

static uint8_t hisi_nfc_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/hisi504_nand.c

362

return *(uint8_t *)(host->mmio);

drivers/mtd/nand/raw/hisi504_nand.c

367

return *(uint8_t *)(host->mmio + host->offset - 1);

drivers/mtd/nand/raw/hisi504_nand.c

369

return *(uint8_t *)(host->buffer + host->offset - 1);

drivers/mtd/nand/raw/hisi504_nand.c

373

hisi_nfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)

drivers/mtd/nand/raw/hisi504_nand.c

381

static void hisi_nfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/hisi504_nand.c

518

static int hisi_nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/hisi504_nand.c

568

const uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/ingenic/jz4740_ecc.c

41

static const uint8_t empty_block_ecc[] = {

drivers/mtd/nand/raw/ingenic/jz4740_ecc.c

99

static void jz_nand_correct_data(uint8_t *buf, int index, int mask)

drivers/mtd/nand/raw/internals.h

113

void sanitize_string(uint8_t *s, size_t len);

drivers/mtd/nand/raw/lpc32xx_mlc.c

193

uint8_t *oob_buf;

drivers/mtd/nand/raw/lpc32xx_mlc.c

201

uint8_t *dma_buf;

drivers/mtd/nand/raw/lpc32xx_mlc.c

202

uint8_t *dummy_buf;

drivers/mtd/nand/raw/lpc32xx_mlc.c

309

uint8_t sr;

drivers/mtd/nand/raw/lpc32xx_mlc.c

434

static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/lpc32xx_mlc.c

440

uint8_t *oobbuf = chip->oob_poi;

drivers/mtd/nand/raw/lpc32xx_mlc.c

443

uint8_t *dma_buf;

drivers/mtd/nand/raw/lpc32xx_mlc.c

501

const uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/lpc32xx_mlc.c

506

const uint8_t *oobbuf = chip->oob_poi;

drivers/mtd/nand/raw/lpc32xx_mlc.c

507

uint8_t *dma_buf = (uint8_t *)buf;

drivers/mtd/nand/raw/lpc32xx_slc.c

232

uint8_t *data_buf;

drivers/mtd/nand/raw/lpc32xx_slc.c

349

static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/lpc32xx_slc.c

353

return (uint8_t)readl(SLC_DATA(host->io_base));

drivers/mtd/nand/raw/lpc32xx_slc.c

365

*buf++ = (uint8_t)readl(SLC_DATA(host->io_base));

drivers/mtd/nand/raw/lpc32xx_slc.c

371

static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/lpc32xx_slc.c

405

static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)

drivers/mtd/nand/raw/lpc32xx_slc.c

412

spare[i + 2] = (uint8_t)(ce & 0xFF);

drivers/mtd/nand/raw/lpc32xx_slc.c

414

spare[i + 1] = (uint8_t)(ce & 0xFF);

drivers/mtd/nand/raw/lpc32xx_slc.c

416

spare[i] = (uint8_t)(ce & 0xFF);

drivers/mtd/nand/raw/lpc32xx_slc.c

485

static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,

drivers/mtd/nand/raw/lpc32xx_slc.c

495

uint8_t *dma_buf;

drivers/mtd/nand/raw/lpc32xx_slc.c

600

static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/lpc32xx_slc.c

607

uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];

drivers/mtd/nand/raw/lpc32xx_slc.c

648

uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/lpc32xx_slc.c

668

const uint8_t *buf,

drivers/mtd/nand/raw/lpc32xx_slc.c

674

uint8_t *pb;

drivers/mtd/nand/raw/lpc32xx_slc.c

680

error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);

drivers/mtd/nand/raw/lpc32xx_slc.c

706

const uint8_t *buf,

drivers/mtd/nand/raw/mxc_nand.c

1221

static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };

drivers/mtd/nand/raw/mxc_nand.c

1222

static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };

drivers/mtd/nand/raw/mxc_nand.c

749

static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/mxc_nand.c

771

static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/mxc_nand.c

802

static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/mxc_nand.c

820

static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

2810

int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/nand_base.c

2881

static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

2887

uint8_t *oob = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

2943

static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

2950

uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

2951

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/nand_base.c

2952

uint8_t *ecc_code = chip->ecc.code_buf;

drivers/mtd/nand/raw/nand_base.c

2991

uint32_t readlen, uint8_t *bufpoi, int page)

drivers/mtd/nand/raw/nand_base.c

2995

uint8_t *p;

drivers/mtd/nand/raw/nand_base.c

3102

static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

3109

uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

3110

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/nand_base.c

3111

uint8_t *ecc_code = chip->ecc.code_buf;

drivers/mtd/nand/raw/nand_base.c

3175

int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

3182

uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

3183

uint8_t *ecc_code = chip->ecc.code_buf;

drivers/mtd/nand/raw/nand_base.c

3241

static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

3249

uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

3250

uint8_t *oob = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

3330

static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,

drivers/mtd/nand/raw/nand_base.c

3451

uint8_t *bufpoi, *oob, *buf;

drivers/mtd/nand/raw/nand_base.c

3648

uint8_t *bufpoi = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

3716

const uint8_t *bufpoi = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

3794

uint8_t *buf = ops->oobbuf;

drivers/mtd/nand/raw/nand_base.c

388

static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,

drivers/mtd/nand/raw/nand_base.c

3925

int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

3992

const uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/nand_base.c

3998

uint8_t *oob = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

4053

static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

4060

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/nand_base.c

4061

const uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

4082

static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

4089

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/nand_base.c

4090

const uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

4129

uint32_t data_len, const uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

4133

uint8_t *oob_buf = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

4134

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/nand_base.c

4199

static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_base.c

4206

const uint8_t *p = buf;

drivers/mtd/nand/raw/nand_base.c

4207

uint8_t *oob = chip->oob_poi;

drivers/mtd/nand/raw/nand_base.c

4270

int data_len, const uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/nand_base.c

4317

uint8_t *oob = ops->oobbuf;

drivers/mtd/nand/raw/nand_base.c

4318

uint8_t *buf = ops->datbuf;

drivers/mtd/nand/raw/nand_base.c

4364

uint8_t *wbuf = buf;

drivers/mtd/nand/raw/nand_base.c

4444

size_t *retlen, const uint8_t *buf)

drivers/mtd/nand/raw/nand_base.c

4458

ops.datbuf = (uint8_t *)buf;

drivers/mtd/nand/raw/nand_base.c

4789

void sanitize_string(uint8_t *s, size_t len)

drivers/mtd/nand/raw/nand_base.c

506

uint8_t buf[2] = { 0, 0 };

drivers/mtd/nand/raw/nand_bbt.c

107

static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)

drivers/mtd/nand/raw/nand_bbt.c

1078

uint8_t *buf;

drivers/mtd/nand/raw/nand_bbt.c

1134

uint8_t oldval;

drivers/mtd/nand/raw/nand_bbt.c

1247

uint8_t *buf;

drivers/mtd/nand/raw/nand_bbt.c

128

static int check_short_pattern(uint8_t *buf, struct nand_bbt_descr *td)

drivers/mtd/nand/raw/nand_bbt.c

1315

static uint8_t scan_ff_pattern[] = { 0xff, 0xff };

drivers/mtd/nand/raw/nand_bbt.c

1318

static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };

drivers/mtd/nand/raw/nand_bbt.c

1319

static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };

drivers/mtd/nand/raw/nand_bbt.c

166

static int read_bbt(struct nand_chip *this, uint8_t *buf, int page, int num,

drivers/mtd/nand/raw/nand_bbt.c

174

uint8_t msk = (uint8_t)((1 << bits) - 1);

drivers/mtd/nand/raw/nand_bbt.c

211

uint8_t dat = buf[i];

drivers/mtd/nand/raw/nand_bbt.c

213

uint8_t tmp = (dat >> j) & msk;

drivers/mtd/nand/raw/nand_bbt.c

259

static int read_abs_bbt(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_bbt.c

287

static int scan_read_data(struct nand_chip *this, uint8_t *buf, loff_t offs,

drivers/mtd/nand/raw/nand_bbt.c

312

static int scan_read_oob(struct nand_chip *this, uint8_t *buf, loff_t offs,

drivers/mtd/nand/raw/nand_bbt.c

343

static int scan_read(struct nand_chip *this, uint8_t *buf, loff_t offs,

drivers/mtd/nand/raw/nand_bbt.c

354

uint8_t *buf, uint8_t *oob)

drivers/mtd/nand/raw/nand_bbt.c

389

static void read_abs_bbts(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_bbt.c

415

loff_t offs, uint8_t *buf)

drivers/mtd/nand/raw/nand_bbt.c

452

loff_t offs, uint8_t *buf)

drivers/mtd/nand/raw/nand_bbt.c

490

static int create_bbt(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_bbt.c

552

static int search_bbt(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_bbt.c

628

static void search_read_bbts(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_bbt.c

744

static int write_bbt(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_bbt.c

754

uint8_t msk[4];

drivers/mtd/nand/raw/nand_bbt.c

755

uint8_t rcode = td->reserved_block_code;

drivers/mtd/nand/raw/nand_bbt.c

76

static inline uint8_t bbt_get_entry(struct nand_chip *chip, int block)

drivers/mtd/nand/raw/nand_bbt.c

78

uint8_t entry = chip->bbt[block >> BBT_ENTRY_SHIFT];

drivers/mtd/nand/raw/nand_bbt.c

84

uint8_t mark)

drivers/mtd/nand/raw/nand_bbt.c

86

uint8_t msk = (mark & BBT_ENTRY_MASK) << ((block & BBT_ENTRY_MASK) * 2);

drivers/mtd/nand/raw/nand_bbt.c

881

uint8_t dat;

drivers/mtd/nand/raw/nand_bbt.c

90

static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td)

drivers/mtd/nand/raw/nand_bbt.c

949

static int check_create(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/nand_legacy.c

106

chip->legacy.write_buf(chip, (uint8_t *)&word, 2);

drivers/mtd/nand/raw/nand_legacy.c

117

static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)

drivers/mtd/nand/raw/nand_legacy.c

130

static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/nand_legacy.c

143

static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_legacy.c

159

static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/nand_legacy.c

28

static uint8_t nand_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/nand_legacy.c

40

static uint8_t nand_read_byte16(struct nand_chip *chip)

drivers/mtd/nand/raw/nand_legacy.c

42

return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));

drivers/mtd/nand/raw/nand_legacy.c

74

static void nand_write_byte(struct nand_chip *chip, uint8_t byte)

drivers/mtd/nand/raw/nand_legacy.c

86

static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)

drivers/mtd/nand/raw/nand_micron.c

304

micron_nand_read_page_on_die_ecc(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/nand_micron.c

369

micron_nand_write_page_on_die_ecc(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/nand_onfi.c

42

uint8_t *cursor;

drivers/mtd/nand/raw/nand_onfi.c

63

if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)

drivers/mtd/nand/raw/nand_onfi.c

79

cursor = (uint8_t *)(ep + 1);

drivers/mtd/nand/raw/nand_toshiba.c

110

uint32_t readlen, uint8_t *bufpoi, int page)

drivers/mtd/nand/raw/nand_toshiba.c

96

toshiba_nand_read_page_benand(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/ndfc.c

111

static void ndfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/ndfc.c

120

static void ndfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)

drivers/mtd/nand/raw/ndfc.c

92

uint8_t *p = (uint8_t *)&ecc;

drivers/mtd/nand/raw/omap2.c

1400

static int omap_write_page_bch(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/omap2.c

1405

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/omap2.c

1535

static int omap_read_page_bch(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/omap2.c

1540

uint8_t *ecc_calc = chip->ecc.calc_buf;

drivers/mtd/nand/raw/omap2.c

1541

uint8_t *ecc_code = chip->ecc.code_buf;

drivers/mtd/nand/raw/orion_nand.c

52

static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/r852.c

172

static void r852_do_dma(struct r852_device *dev, uint8_t *buf, int do_read)

drivers/mtd/nand/raw/r852.c

230

static void r852_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)

drivers/mtd/nand/raw/r852.c

241

r852_do_dma(dev, (uint8_t *)buf, 0);

drivers/mtd/nand/raw/r852.c

264

static void r852_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/r852.c

301

static uint8_t r852_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/r852.c

34

static inline uint8_t r852_read_reg(struct r852_device *dev, int address)

drivers/mtd/nand/raw/r852.c

36

uint8_t reg = readb(dev->mmio + address);

drivers/mtd/nand/raw/r852.c

42

int address, uint8_t value)

drivers/mtd/nand/raw/r852.c

433

static int r852_ecc_calculate(struct nand_chip *chip, const uint8_t *dat,

drivers/mtd/nand/raw/r852.c

434

uint8_t *ecc_code)

drivers/mtd/nand/raw/r852.c

465

static int r852_ecc_correct(struct nand_chip *chip, uint8_t *dat,

drivers/mtd/nand/raw/r852.c

466

uint8_t *read_ecc, uint8_t *calc_ecc)

drivers/mtd/nand/raw/r852.c

469

uint8_t ecc_status, err_byte;

drivers/mtd/nand/raw/r852.c

563

uint8_t reg;

drivers/mtd/nand/raw/r852.c

605

uint8_t reg;

drivers/mtd/nand/raw/r852.c

711

uint8_t reg;

drivers/mtd/nand/raw/r852.c

728

uint8_t card_status, dma_status;

drivers/mtd/nand/raw/r852.c

91

uint8_t dma_reg, dma_irq_reg;

drivers/mtd/nand/raw/r852.h

117

uint8_t *bounce_buffer; /* virtual address of bounce buffer */

drivers/mtd/nand/raw/r852.h

142

uint8_t ctlreg; /* cached contents of control reg */

drivers/mtd/nand/raw/sh_flctl.c

100

static uint8_t scan_ff_pattern[] = { 0xff, 0xff };

drivers/mtd/nand/raw/sh_flctl.c

340

uint8_t org;

drivers/mtd/nand/raw/sh_flctl.c

484

(struct sh_flctl *flctl, uint8_t *buff, int sector)

drivers/mtd/nand/raw/sh_flctl.c

600

static int flctl_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/sh_flctl.c

611

static int flctl_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/sh_flctl.c

960

static void flctl_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)

drivers/mtd/nand/raw/sh_flctl.c

968

static uint8_t flctl_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/sh_flctl.c

971

uint8_t data;

drivers/mtd/nand/raw/sh_flctl.c

978

static void flctl_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/sm_common.h

12

uint8_t data_status;

drivers/mtd/nand/raw/sm_common.h

13

uint8_t block_status;

drivers/mtd/nand/raw/sm_common.h

14

uint8_t lba_copy1[2];

drivers/mtd/nand/raw/sm_common.h

15

uint8_t ecc2[3];

drivers/mtd/nand/raw/sm_common.h

16

uint8_t lba_copy2[2];

drivers/mtd/nand/raw/sm_common.h

17

uint8_t ecc1[3];

drivers/mtd/nand/raw/socrates_nand.c

38

static void socrates_nand_write_buf(struct nand_chip *this, const uint8_t *buf,

drivers/mtd/nand/raw/socrates_nand.c

57

static void socrates_nand_read_buf(struct nand_chip *this, uint8_t *buf,

drivers/mtd/nand/raw/socrates_nand.c

77

static uint8_t socrates_nand_read_byte(struct nand_chip *this)

drivers/mtd/nand/raw/socrates_nand.c

79

uint8_t byte;

drivers/mtd/nand/raw/sunxi_nand.c

1065

static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf,

drivers/mtd/nand/raw/sunxi_nand.c

1262

static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf,

drivers/mtd/nand/raw/sunxi_nand.c

1377

const uint8_t *buf, int oob_required,

drivers/mtd/nand/raw/sunxi_nand.c

555

static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len)

drivers/mtd/nand/raw/sunxi_nand.c

592

static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf,

drivers/mtd/nand/raw/sunxi_nand.c

777

const uint8_t *buf, int len,

drivers/mtd/nand/raw/sunxi_nand.c

786

static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf,

drivers/mtd/nand/raw/txx9ndfmc.c

101

static uint8_t txx9ndfmc_read_byte(struct nand_chip *chip)

drivers/mtd/nand/raw/txx9ndfmc.c

108

static void txx9ndfmc_write_buf(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nand/raw/txx9ndfmc.c

121

static void txx9ndfmc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)

drivers/mtd/nand/raw/txx9ndfmc.c

167

static int txx9ndfmc_calculate_ecc(struct nand_chip *chip, const uint8_t *dat,

drivers/mtd/nand/raw/txx9ndfmc.c

168

uint8_t *ecc_code)

drivers/mtd/nand/raw/vf610_nfc.c

508

static inline int vf610_nfc_correct_data(struct nand_chip *chip, uint8_t *dat,

drivers/mtd/nand/raw/vf610_nfc.c

509

uint8_t *oob, int page)

drivers/mtd/nand/raw/vf610_nfc.c

549

static int vf610_nfc_read_page(struct nand_chip *chip, uint8_t *buf,

drivers/mtd/nand/raw/vf610_nfc.c

597

static int vf610_nfc_write_page(struct nand_chip *chip, const uint8_t *buf,

drivers/mtd/nftlcore.c

124

size_t *retlen, uint8_t *buf)

drivers/mtd/nftlcore.c

145

size_t *retlen, uint8_t *buf)

drivers/mtd/nftlcore.c

168

size_t *retlen, uint8_t *buf, uint8_t *oob)

drivers/mtd/parsers/bcm47xxpart.c

133

&bytes_read, (uint8_t *)buf);

drivers/mtd/parsers/bcm47xxpart.c

236

(uint8_t *)buf);

drivers/mtd/parsers/bcm47xxpart.c

260

(uint8_t *)buf);

drivers/mtd/parsers/bcm47xxpart.c

91

uint8_t i, curr_part = 0;

drivers/mtd/parsers/brcm_u-boot.c

47

err = mtd_read(mtd, offset, sizeof(header), &bytes_read, (uint8_t *)&header);

drivers/mtd/parsers/parser_trx.c

36

(uint8_t *)&buf);

drivers/mtd/parsers/parser_trx.c

59

uint8_t curr_part = 0, i = 0;

drivers/mtd/parsers/parser_trx.c

72

err = mtd_read(mtd, 0, sizeof(trx), &bytes_read, (uint8_t *)&trx);

drivers/mtd/parsers/scpart.c

109

uint8_t rdbuf[PART_MAGIC_LEN];

drivers/mtd/parsers/scpart.c

57

uint8_t *buf;

drivers/mtd/parsers/tplink_safeloader.c

42

err = mtd_read(mtd, offset, sizeof(hdr), &bytes_read, (uint8_t *)&hdr);

drivers/mtd/sm_ftl.c

127

static int sm_get_lba(uint8_t *lba)

drivers/mtd/sm_ftl.c

174

uint8_t tmp[2];

drivers/mtd/sm_ftl.c

215

static int sm_correct_sector(uint8_t *buffer, struct sm_oob *oob)

drivers/mtd/sm_ftl.c

218

uint8_t ecc[3];

drivers/mtd/sm_ftl.c

237

uint8_t *buffer, struct sm_oob *oob)

drivers/mtd/sm_ftl.c

322

uint8_t *buffer, struct sm_oob *oob)

drivers/mtd/sm_ftl.c

367

static int sm_write_block(struct sm_ftl *ftl, uint8_t *buf,

drivers/mtd/sm_ftl.c

556

static const uint8_t cis_signature[] = {

drivers/mtd/ssfdc.c

107

uint8_t *sect_buf;

drivers/mtd/ssfdc.c

148

static int read_physical_sector(struct mtd_info *mtd, uint8_t *sect_buf,

drivers/mtd/ssfdc.c

163

static int read_raw_oob(struct mtd_info *mtd, loff_t offs, uint8_t *buf)

drivers/mtd/ssfdc.c

196

static int get_logical_address(uint8_t *oob_buf)

drivers/mtd/ssfdc.c

242

uint8_t oob_buf[OOB_SIZE];

drivers/mtd/ssfdc.c

97

static const uint8_t cis_numbers[] = {

drivers/mtd/tests/nandbiterrs.c

69

static uint8_t *wbuffer; /* One page write / compare buffer */

drivers/mtd/tests/nandbiterrs.c

70

static uint8_t *rbuffer; /* One page read buffer */

drivers/mtd/tests/nandbiterrs.c

73

static uint8_t hash(unsigned offset)

drivers/mtd/ubi/attach.c

1668

uint8_t *buf;

drivers/mtd/ubi/io.c

1399

uint8_t c = ((uint8_t *)buf)[i];

drivers/mtd/ubi/io.c

1400

uint8_t c1 = ((uint8_t *)buf1)[i];

drivers/mtd/ubi/io.c

150

*((uint8_t *)buf) ^= 0xFF;

drivers/mtd/ubi/io.c

364

static uint8_t patterns[] = {0xa5, 0x5a, 0x0};

drivers/mtd/ubi/misc.c

134

int ubi_check_pattern(const void *buf, uint8_t patt, int size)

drivers/mtd/ubi/misc.c

139

if (((const uint8_t *)buf)[i] != patt)

drivers/mtd/ubi/misc.c

30

if (((const uint8_t *)buf)[i] != 0xFF)

drivers/mtd/ubi/ubi.h

866

int ubi_check_pattern(const void *buf, uint8_t patt, int size);

drivers/net/arcnet/arc-rawmode.c

85

unsigned short type, uint8_t daddr)

drivers/net/arcnet/arcdevice.h

202

unsigned short ethproto, uint8_t daddr);

drivers/net/arcnet/arcdevice.h

221

uint8_t lastpacket, /* number of last packet (from 1) */

drivers/net/arcnet/arcdevice.h

241

uint8_t config, /* current value of CONFIG register */

drivers/net/arcnet/arcdevice.h

249

uint8_t default_proto[256]; /* default encap to use for each host */

drivers/net/arcnet/arcnet.c

1187

unsigned short type, uint8_t daddr)

drivers/net/arcnet/arcnet.c

169

static uint8_t buf[512];

drivers/net/arcnet/arcnet.c

648

uint8_t _daddr, proto_num;

drivers/net/arcnet/arcnet.c

653

saddr ? *(uint8_t *)saddr : -1,

drivers/net/arcnet/arcnet.c

654

daddr ? *(uint8_t *)daddr : -1,

drivers/net/arcnet/arcnet.c

66

unsigned short type, uint8_t daddr);

drivers/net/arcnet/arcnet.c

666

_daddr = daddr ? *(uint8_t *)daddr : 0;

drivers/net/arcnet/arcnet.c

681

_daddr = *(uint8_t *)daddr;

drivers/net/arcnet/capmode.c

101

uint8_t daddr)

drivers/net/arcnet/rfc1051.c

163

unsigned short type, uint8_t daddr)

drivers/net/arcnet/rfc1051.c

43

unsigned short type, uint8_t daddr);

drivers/net/arcnet/rfc1201.c

213

uint8_t *cptr = (uint8_t *)arp + sizeof(struct arphdr);

drivers/net/arcnet/rfc1201.c

379

unsigned short type, uint8_t daddr)

drivers/net/arcnet/rfc1201.c

45

unsigned short type, uint8_t daddr);

drivers/net/can/sja1000/sja1000.c

288

uint8_t fi;

drivers/net/can/sja1000/sja1000.c

290

uint8_t dreg;

drivers/net/can/sja1000/sja1000.c

344

uint8_t fi;

drivers/net/can/sja1000/sja1000.c

345

uint8_t dreg;

drivers/net/can/sja1000/sja1000.c

406

static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)

drivers/net/can/sja1000/sja1000.c

414

uint8_t ecc, alc;

drivers/net/can/sja1000/sja1000.c

520

uint8_t isrc, status;

drivers/net/can/softing/softing.h

32

uint8_t output;

drivers/net/can/softing/softing.h

65

__iomem uint8_t *dpram;

drivers/net/can/softing/softing.h

86

__iomem uint8_t *virt, unsigned int size, int offset);

drivers/net/can/softing/softing_fw.c

134

__iomem uint8_t *dpram, unsigned int size, int offset)

drivers/net/can/softing/softing_fw.c

138

const uint8_t *mem, *end, *dat;

drivers/net/can/softing/softing_fw.c

141

uint8_t *buf = NULL, *new_buf;

drivers/net/can/softing/softing_fw.c

221

const uint8_t *mem, *end, *dat;

drivers/net/can/softing/softing_fw.c

94

static int fw_parse(const uint8_t **pmem, uint16_t *ptype, uint32_t *paddr,

drivers/net/can/softing/softing_fw.c

95

uint16_t *plen, const uint8_t **pdat)

drivers/net/can/softing/softing_fw.c

98

const uint8_t *mem;

drivers/net/can/softing/softing_fw.c

99

const uint8_t *end;

drivers/net/can/softing/softing_main.c

157

uint8_t fifo_rd, fifo_wr, cmd;

drivers/net/can/softing/softing_main.c

158

uint8_t *ptr;

drivers/net/can/softing/softing_main.c

160

uint8_t buf[DPRAM_RX_SIZE];

drivers/net/can/softing/softing_main.c

217

uint8_t can_state, state;

drivers/net/can/softing/softing_main.c

358

uint8_t ir;

drivers/net/can/softing/softing_main.c

368

uint8_t ir;

drivers/net/can/softing/softing_main.c

474

static const uint8_t stream[] = {

drivers/net/can/softing/softing_main.c

58

uint8_t *ptr;

drivers/net/can/softing/softing_main.c

59

uint8_t fifo_wr, fifo_rd;

drivers/net/can/softing/softing_main.c

61

uint8_t buf[DPRAM_TX_SIZE];

drivers/net/dsa/b53/b53_common.c

1142

uint8_t *data)

drivers/net/dsa/b53/b53_priv.h

494

uint8_t *data);

drivers/net/dsa/bcm_sf2.c

1185

u32 stringset, uint8_t *data)

drivers/net/dsa/bcm_sf2.h

232

uint8_t **data);

drivers/net/dsa/bcm_sf2_cfp.c

1283

uint8_t **data)

drivers/net/dsa/dsa_loop.c

128

u32 stringset, uint8_t *data)

drivers/net/dsa/hirschmann/hellcreek.c

293

u32 stringset, uint8_t *data)

drivers/net/dsa/lan9303-core.c

1037

u32 stringset, uint8_t *data)

drivers/net/dsa/lantiq/lantiq_gswip_common.c

1492

uint8_t *data)

drivers/net/dsa/microchip/ksz_common.c

2369

u32 stringset, uint8_t *buf)

drivers/net/dsa/mt7530.c

749

uint8_t *data)

drivers/net/dsa/mv88e6xxx/chip.c

1157

uint8_t **data, int types)

drivers/net/dsa/mv88e6xxx/chip.c

1170

uint8_t **data)

drivers/net/dsa/mv88e6xxx/chip.c

1177

uint8_t **data)

drivers/net/dsa/mv88e6xxx/chip.c

1183

uint8_t **data)

drivers/net/dsa/mv88e6xxx/chip.c

1189

static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {

drivers/net/dsa/mv88e6xxx/chip.c

1197

static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data)

drivers/net/dsa/mv88e6xxx/chip.c

1206

u32 stringset, uint8_t *data)

drivers/net/dsa/mv88e6xxx/chip.h

608

void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t **data);

drivers/net/dsa/mv88e6xxx/chip.h

636

uint8_t **data);

drivers/net/dsa/mv88e6xxx/serdes.c

128

uint8_t **data)

drivers/net/dsa/mv88e6xxx/serdes.c

389

uint8_t **data)

drivers/net/dsa/mv88e6xxx/serdes.h

127

uint8_t **data);

drivers/net/dsa/mv88e6xxx/serdes.h

132

uint8_t **data);

drivers/net/dsa/mxl862xx/mxl862xx-host.c

212

*(uint8_t *)&data[i] = ret & 0xff;

drivers/net/dsa/qca/qca8k-common.c

481

uint8_t *data)

drivers/net/dsa/qca/qca8k.h

516

void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data);

drivers/net/dsa/realtek/realtek.h

140

uint8_t *data);

drivers/net/dsa/realtek/rtl8366-core.c

395

uint8_t *data)

drivers/net/dsa/rzn1_a5psw.c

799

uint8_t *data)

drivers/net/dsa/vitesse-vsc73xx-core.c

1479

uint8_t *data)

drivers/net/dsa/yt921x.c

750

uint8_t *data)

drivers/net/ethernet/8390/xsurf100.c

119

ei_outb(*(uint8_t *)src, ei_local->mem + NE_DATAPORT);

drivers/net/ethernet/8390/xsurf100.c

145

*(uint8_t *)dst = ei_inb(ei_local->mem + NE_DATAPORT);

drivers/net/ethernet/broadcom/sb1250-mac.c

2180

eaddr[i] = (uint8_t) (ea_reg & 0xFF);

drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c

395

memcpy((uint8_t *)&oct->pfvf_hsword, cmd->msg.s.params,

drivers/net/ethernet/cavium/liquidio/octeon_mailbox.c

254

memcpy(mbox_cmd->msg.s.params, (uint8_t *)&oct->pfvf_hsword, 6);

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

101

uint8_t sched;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

102

uint8_t idx;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

103

uint8_t min;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

104

uint8_t max;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

105

uint8_t binding;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

166

uint8_t proto;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

167

uint8_t proto_mask;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

168

uint8_t invert_match:1;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

169

uint8_t config_tx:1;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

170

uint8_t config_rx:1;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

171

uint8_t trace_tx:1;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

172

uint8_t trace_rx:1;

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

73

uint8_t data[128];

drivers/net/ethernet/chelsio/cxgb3/cxgb3_ioctl.h

82

uint8_t buf[];

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

1360

uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

1361

uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

1404

uint8_t dmac[ETH_ALEN]; /* new destination MAC address */

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

1405

uint8_t smac[ETH_ALEN]; /* new source MAC address */

drivers/net/ethernet/cisco/enic/vnic_wq.h

121

uint8_t desc_skip_cnt, uint8_t cq_entry,

drivers/net/ethernet/cisco/enic/vnic_wq.h

122

uint8_t compressed_send, uint64_t wrid)

drivers/net/ethernet/cisco/enic/vnic_wq.h

49

uint8_t cq_entry; /* Gets completion event from hw */

drivers/net/ethernet/cisco/enic/vnic_wq.h

50

uint8_t desc_skip_cnt; /* Num descs to occupy */

drivers/net/ethernet/cisco/enic/vnic_wq.h

51

uint8_t compressed_send; /* Both hdr and payload in one desc */

drivers/net/ethernet/emulex/benet/be_ethtool.c

1012

struct ethtool_eeprom *eeprom, uint8_t *data)

drivers/net/ethernet/emulex/benet/be_ethtool.c

430

uint8_t *data)

drivers/net/ethernet/intel/ice/devlink/devlink.c

543

static int ice_get_tx_topo_user_sel(struct ice_pf *pf, uint8_t *layers)

drivers/net/ethernet/marvell/mv643xx_eth.c

1698

uint32_t stringset, uint8_t *data)

drivers/net/ethernet/mellanox/mlx4/en_ethtool.c

450

uint32_t stringset, uint8_t *data)

drivers/net/ethernet/mellanox/mlx4/main.c

85

static uint8_t num_vfs[3] = {0, 0, 0};

drivers/net/ethernet/mellanox/mlx4/main.c

91

static uint8_t probe_vf[3] = {0, 0, 0};

drivers/net/ethernet/qlogic/netxen/netxen_nic.h

937

uint8_t mac_addr[ETH_ALEN+2];

drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c

1444

uint8_t revision_id;

drivers/net/ethernet/qlogic/qlcnic/qlcnic.h

856

uint8_t mac_addr[ETH_ALEN+2];

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

729

#define LSB(x) ((uint8_t)(x))

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

730

#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))

drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c

27

static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg)

drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c

32

static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val)

drivers/net/ethernet/ti/netcp_ethss.c

1768

uint32_t stringset, uint8_t *data)

drivers/net/ethernet/toshiba/ps3_gelic_net.c

614

uint8_t *p;

drivers/net/mdio/mdio-mux-mmioreg.c

118

if (s->iosize != sizeof(uint8_t) &&

drivers/net/mdio/mdio-mux-mmioreg.c

53

case sizeof(uint8_t): {

drivers/net/mdio/mdio-mux-mmioreg.c

54

uint8_t x, y;

drivers/net/wireless/ath/ath10k/spectral.c

24

static uint8_t get_max_exp(s8 max_index, u16 max_magnitude, size_t bin_len,

drivers/net/wireless/ath/ath11k/dp_rx.c

2000

memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);

drivers/net/wireless/ath/ath12k/mac.c

3497

max_nss = min(max_nss, (uint8_t)eht_nss);

drivers/net/wireless/ath/carl9170/tx.c

1278

uint8_t q = 0;

drivers/net/wireless/ath/carl9170/tx.c

659

const uint8_t cookie, const uint8_t info)

drivers/net/wireless/broadcom/b43/main.c

1660

uint8_t ie_id, ie_len;

drivers/net/wireless/broadcom/b43/main.c

2785

iv = (const struct b43_iv *)((const uint8_t *)iv +

drivers/net/wireless/broadcom/b43/main.c

2798

iv = (const struct b43_iv *)((const uint8_t *)iv +

drivers/net/wireless/broadcom/b43legacy/main.c

1811

iv = (const struct b43legacy_iv *)((const uint8_t *)iv +

drivers/net/wireless/broadcom/b43legacy/main.c

1824

iv = (const struct b43legacy_iv *)((const uint8_t *)iv +

drivers/net/wireless/broadcom/b43legacy/main.c

979

uint8_t ie_id, ie_len;

drivers/net/wireless/marvell/libertas/cmd.c

199

memcpy((uint8_t *)&cmd_config.wol_conf, (uint8_t *)p_wol_config,

drivers/net/wireless/marvell/libertas/cmd.c

209

memcpy((uint8_t *) p_wol_config,

drivers/net/wireless/marvell/libertas/cmd.c

210

(uint8_t *)&cmd_config.wol_conf,

drivers/net/wireless/marvell/libertas/cmd.c

584

priv->channel = (uint8_t) le16_to_cpu(cmd.channel);

drivers/net/wireless/marvell/libertas/debugfs.c

197

static void *lbs_tlv_find(uint16_t tlv_type, const uint8_t *tlv, uint16_t size)

drivers/net/wireless/marvell/libertas/dev.h

151

uint8_t wol_gpio;

drivers/net/wireless/marvell/libertas/dev.h

152

uint8_t wol_gap;

drivers/net/wireless/marvell/libertas/dev.h

21

uint8_t sp_calcontrol;

drivers/net/wireless/marvell/libertas/dev.h

22

uint8_t sp_extsleepclk;

drivers/net/wireless/marvell/libertas/host.h

454

uint8_t tlv[128];

drivers/net/wireless/marvell/libertas/host.h

464

uint8_t bsstype;

drivers/net/wireless/marvell/libertas/host.h

465

uint8_t bssid[ETH_ALEN];

drivers/net/wireless/marvell/libertas/host.h

466

uint8_t tlvbuffer[];

drivers/net/wireless/marvell/libertas/host.h

473

uint8_t nr_sets;

drivers/net/wireless/marvell/libertas/host.h

474

uint8_t bssdesc_and_tlvbuffer[];

drivers/net/wireless/marvell/libertas/host.h

555

uint8_t keytype[4];

drivers/net/wireless/marvell/libertas/host.h

556

uint8_t keymaterial[4][16];

drivers/net/wireless/marvell/libertas/host.h

610

uint8_t calcontrol;

drivers/net/wireless/marvell/libertas/host.h

613

uint8_t externalsleepclk;

drivers/net/wireless/marvell/libertas/host.h

833

uint8_t rule_no;

drivers/net/wireless/marvell/libertas/host.h

834

uint8_t rule_ops;

drivers/net/wireless/marvell/libertas/host.h

843

uint8_t action;

drivers/net/wireless/marvell/libertas/host.h

844

uint8_t pattern;

drivers/net/wireless/marvell/libertas/host.h

845

uint8_t no_rules_in_cmd;

drivers/net/wireless/marvell/libertas/host.h

846

uint8_t result;

drivers/net/wireless/marvell/libertas/host.h

853

uint8_t gpio;

drivers/net/wireless/marvell/libertas/host.h

881

uint8_t enable;

drivers/net/wireless/marvell/libertas/host.h

885

uint8_t usesnr;

drivers/net/wireless/marvell/libertas/host.h

893

uint8_t enable;

drivers/net/wireless/marvell/libertas/if_usb.c

335

const uint8_t *firmware = cardp->fw->data;

drivers/net/wireless/marvell/libertas/if_usb.c

418

static int usb_tx_block(struct if_usb_card *cardp, uint8_t *payload, uint16_t nb)

drivers/net/wireless/marvell/libertas/if_usb.c

620

static inline void process_cmdrequest(int recvlength, uint8_t *recvbuff,

drivers/net/wireless/marvell/libertas/if_usb.c

664

uint8_t *recvbuff = NULL;

drivers/net/wireless/marvell/libertas/if_usb.c

71

static int if_usb_host_to_card(struct lbs_private *priv, uint8_t type,

drivers/net/wireless/marvell/libertas/if_usb.c

72

uint8_t *payload, uint16_t nb);

drivers/net/wireless/marvell/libertas/if_usb.c

73

static int usb_tx_block(struct if_usb_card *cardp, uint8_t *payload,

drivers/net/wireless/marvell/libertas/if_usb.c

730

static int if_usb_host_to_card(struct lbs_private *priv, uint8_t type,

drivers/net/wireless/marvell/libertas/if_usb.c

731

uint8_t *payload, uint16_t nb)

drivers/net/wireless/marvell/libertas/if_usb.c

781

static int check_fwfile_format(const uint8_t *data, uint32_t totlen)

drivers/net/wireless/marvell/libertas/if_usb.h

28

uint8_t cmd;

drivers/net/wireless/marvell/libertas/if_usb.h

29

uint8_t pad[11];

drivers/net/wireless/marvell/libertas/if_usb.h

39

uint8_t cmd;

drivers/net/wireless/marvell/libertas/if_usb.h

40

uint8_t result;

drivers/net/wireless/marvell/libertas/if_usb.h

41

uint8_t pad[2];

drivers/net/wireless/marvell/libertas/if_usb.h

53

uint8_t ep_in;

drivers/net/wireless/marvell/libertas/if_usb.h

54

uint8_t ep_out;

drivers/net/wireless/marvell/libertas/if_usb.h

73

uint8_t CRC_OK;

drivers/net/wireless/marvell/libertas/if_usb.h

74

uint8_t fwdnldover;

drivers/net/wireless/marvell/libertas/if_usb.h

75

uint8_t fwfinalblk;

drivers/net/wireless/marvell/libertas/if_usb.h

76

uint8_t surprise_removed;

drivers/net/wireless/marvell/libertas/if_usb.h

94

uint8_t data[];

drivers/net/wireless/marvell/libertas/mesh.c

1154

uint32_t stringset, uint8_t *s)

drivers/net/wireless/marvell/libertas/mesh.c

466

cmd.length = cpu_to_le16(sizeof(uint8_t));

drivers/net/wireless/marvell/libertas/mesh.h

57

uint32_t stringset, uint8_t *s);

drivers/net/wireless/marvell/libertas/types.h

228

uint8_t firmwarestate;

drivers/net/wireless/marvell/libertas/types.h

229

uint8_t led;

drivers/net/wireless/marvell/libertas/types.h

230

uint8_t ledstate;

drivers/net/wireless/marvell/libertas/types.h

231

uint8_t ledarg;

drivers/net/wireless/marvell/libertas/types.h

246

uint8_t oui[3];

drivers/net/wireless/marvell/libertas/types.h

247

uint8_t type;

drivers/net/wireless/marvell/libertas/types.h

248

uint8_t subtype;

drivers/net/wireless/marvell/libertas/types.h

249

uint8_t version;

drivers/net/wireless/marvell/libertas/types.h

250

uint8_t active_protocol_id;

drivers/net/wireless/marvell/libertas/types.h

251

uint8_t active_metric_id;

drivers/net/wireless/marvell/libertas/types.h

252

uint8_t mesh_capability;

drivers/net/wireless/marvell/libertas/types.h

253

uint8_t mesh_id_len;

drivers/net/wireless/marvell/libertas/types.h

254

uint8_t mesh_id[IEEE80211_MAX_SSID_LEN];

drivers/net/wireless/marvell/libertas/types.h

264

uint8_t boottime;

drivers/net/wireless/marvell/libertas/types.h

265

uint8_t reserved;

drivers/net/wireless/marvell/libertas_tf/cmd.c

365

int lbtf_set_mac_address(struct lbtf_private *priv, uint8_t *mac_addr)

drivers/net/wireless/marvell/libertas_tf/if_usb.c

372

static int usb_tx_block(struct if_usb_card *cardp, uint8_t *payload,

drivers/net/wireless/marvell/libertas_tf/if_usb.c

42

static int if_usb_host_to_card(struct lbtf_private *priv, uint8_t type,

drivers/net/wireless/marvell/libertas_tf/if_usb.c

43

uint8_t *payload, uint16_t nb);

drivers/net/wireless/marvell/libertas_tf/if_usb.c

44

static int usb_tx_block(struct if_usb_card *cardp, uint8_t *payload,

drivers/net/wireless/marvell/libertas_tf/if_usb.c

598

static inline void process_cmdrequest(int recvlength, uint8_t *recvbuff,

drivers/net/wireless/marvell/libertas_tf/if_usb.c

632

uint8_t *recvbuff = NULL;

drivers/net/wireless/marvell/libertas_tf/if_usb.c

714

static int if_usb_host_to_card(struct lbtf_private *priv, uint8_t type,

drivers/net/wireless/marvell/libertas_tf/if_usb.c

715

uint8_t *payload, uint16_t nb)

drivers/net/wireless/marvell/libertas_tf/if_usb.h

26

uint8_t cmd;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

27

uint8_t pad[11];

drivers/net/wireless/marvell/libertas_tf/if_usb.h

35

uint8_t cmd;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

36

uint8_t result;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

37

uint8_t pad[2];

drivers/net/wireless/marvell/libertas_tf/if_usb.h

48

uint8_t ep_in;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

49

uint8_t ep_out;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

64

uint8_t CRC_OK;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

65

uint8_t fwdnldover;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

66

uint8_t fwfinalblk;

drivers/net/wireless/marvell/libertas_tf/if_usb.h

84

uint8_t data[];

drivers/net/wireless/marvell/libertas_tf/libertas_tf.h

388

uint8_t macadd[ETH_ALEN];

drivers/net/wireless/marvell/libertas_tf/libertas_tf.h

472

int lbtf_set_mac_address(struct lbtf_private *priv, uint8_t *mac_addr);

drivers/net/wireless/quantenna/qtnfmac/commands.c

1496

ret = qtnf_cmd_band_fill_iftype((const uint8_t *)tlv,

drivers/nfc/nfcmrvl/fw_dnld.c

171

uint8_t param[2] = { NCI_CORE_LC_PROP_FW_DL, 0x0 };

drivers/nfc/nfcmrvl/fw_dnld.c

307

uint8_t conn_id = NCI_CORE_LC_CONNID_PROP_FW_DL;

drivers/nfc/nfcmrvl/fw_dnld.c

317

((uint8_t *)priv->fw_dnld.fw->data) + priv->fw_dnld.offset,

drivers/nfc/nfcmrvl/fw_dnld.c

45

static const uint8_t nci_pattern_core_reset_ntf[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

49

static const uint8_t nci_pattern_core_init_rsp[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

53

static const uint8_t nci_pattern_core_set_config_rsp[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

57

static const uint8_t nci_pattern_core_conn_create_rsp[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

61

static const uint8_t nci_pattern_core_conn_close_rsp[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

65

static const uint8_t nci_pattern_core_conn_credits_ntf[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

69

static const uint8_t nci_pattern_proprietary_boot_rsp[] = {

drivers/nfc/nfcmrvl/fw_dnld.c

73

static struct sk_buff *alloc_lc_skb(struct nfcmrvl_private *priv, uint8_t plen)

drivers/nfc/nfcmrvl/fw_dnld.h

28

uint8_t flow_control;

drivers/nfc/nfcmrvl/fw_dnld.h

47

uint8_t reserved[64];

drivers/nfc/nfcmrvl/fw_dnld.h

58

uint8_t reserved[64];

drivers/nvme/host/fc.c

115

uint8_t priv[];

drivers/nvmem/brcm_nvram.c

118

static int brcm_nvram_add_cells(struct brcm_nvram *priv, uint8_t *data,

drivers/nvmem/brcm_nvram.c

123

uint8_t tmp;

drivers/nvmem/brcm_nvram.c

35

uint8_t *data;

drivers/nvmem/brcm_nvram.c

37

uint8_t padding_byte;

drivers/nvmem/brcm_nvram.c

63

memset((uint8_t *)val + to_copy, priv->padding_byte, bytes - to_copy);

drivers/nvmem/lan9662-otpc.c

127

uint8_t data;

drivers/nvmem/layouts/u-boot-env.c

102

uint8_t *buf;

drivers/nvmem/layouts/u-boot-env.c

20

uint8_t data[];

drivers/nvmem/layouts/u-boot-env.c

26

uint8_t data[];

drivers/nvmem/layouts/u-boot-env.c

33

DECLARE_FLEX_ARRAY(uint8_t, data);

drivers/nvmem/layouts/u-boot-env.c

55

static int u_boot_env_parse_cells(struct device *dev, struct nvmem_device *nvmem, uint8_t *buf,

drivers/of/fdt.c

39

extern uint8_t __dtb_empty_root_begin[];

drivers/of/fdt.c

40

extern uint8_t __dtb_empty_root_end[];

drivers/of/unittest.c

2111

extern uint8_t __dtbo_testcases_begin[];

drivers/of/unittest.c

2112

extern uint8_t __dtbo_testcases_end[];

drivers/of/unittest.c

3778

extern uint8_t __dtbo_##overlay_name##_begin[]; \

drivers/of/unittest.c

3779

extern uint8_t __dtbo_##overlay_name##_end[]

drivers/of/unittest.c

3790

uint8_t *dtbo_begin;

drivers/of/unittest.c

3791

uint8_t *dtbo_end;

drivers/pci/controller/dwc/pcie-fu740.c

114

static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr,

drivers/pci/hotplug/pnv_php.c

336

uint8_t state)

drivers/pci/hotplug/pnv_php.c

377

uint8_t power_state = OPAL_PCI_SLOT_POWER_ON;

drivers/pci/hotplug/pnv_php.c

413

uint8_t presence = OPAL_PCI_SLOT_EMPTY;

drivers/pci/hotplug/pnv_php.c

545

uint8_t presence = OPAL_PCI_SLOT_EMPTY;

drivers/pci/hotplug/pnv_php.c

546

uint8_t power_status = OPAL_PCI_SLOT_POWER_ON;

drivers/pci/quirks.c

2596

uint8_t b;

drivers/pci/quirks.c

2625

uint8_t b;

drivers/perf/riscv_pmu_legacy.c

80

static uint8_t pmu_legacy_csr_index(struct perf_event *event)

drivers/perf/riscv_pmu_sbi.c

512

static uint8_t pmu_sbi_csr_index(struct perf_event *event)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

108

uint8_t addr, uint16_t data)

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

126

struct brcm_usb_init_params *params, uint8_t addr)

drivers/pinctrl/bcm/pinctrl-bcm6318.c

403

uint8_t val)

drivers/platform/chrome/cros_ec_debugfs.c

399

static int cros_ec_get_panicinfo(struct cros_ec_device *ec_dev, uint8_t *data,

drivers/platform/chrome/cros_ec_debugfs.c

80

uint8_t *ec_buffer = (uint8_t *)debug_info->read_msg->data;

drivers/platform/chrome/cros_ec_i2c.c

27

uint8_t command_protocol;

drivers/platform/chrome/cros_ec_i2c.c

40

uint8_t result;

drivers/platform/chrome/cros_ec_i2c.c

41

uint8_t packet_length;

drivers/platform/chrome/cros_ec_lightbar.c

376

static int lb_send_empty_cmd(struct cros_ec_dev *ec, uint8_t cmd)

drivers/platform/chrome/cros_ec_lightbar.c

404

static int lb_manual_suspend_ctrl(struct cros_ec_dev *ec, uint8_t enable)

drivers/platform/chrome/cros_ec_sysfs.c

43

uint8_t cmd;

drivers/platform/chrome/cros_ec_sysfs.c

44

uint8_t flags;

drivers/platform/chrome/cros_ec_typec.h

67

uint8_t mux_flags;

drivers/platform/chrome/cros_ec_typec.h

68

uint8_t role;

drivers/platform/x86/amd/wbrf.c

139

int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in)

drivers/platform/x86/amd/wbrf.c

42

static int wbrf_record(struct acpi_device *adev, uint8_t action, struct wbrf_ranges_in_out *in)

drivers/platform/x86/intel/ishtp_eclite.c

139

rv = ishtp_cl_send(opr_dev->ecl_ishtp_cl, (uint8_t *)&header, len);

drivers/platform/x86/intel/ishtp_eclite.c

199

return ishtp_cl_send(opr_dev->ecl_ishtp_cl, (uint8_t *)&message, len);

drivers/platform/x86/intel/ishtp_eclite.c

420

return ishtp_cl_send(opr_dev->ecl_ishtp_cl, (uint8_t *)&message, len);

drivers/platform/x86/lenovo/yogabook.c

305

uint8_t level)

drivers/platform/x86/lenovo/yogabook.c

54

int (*set_kbd_backlight)(struct yogabook_data *data, uint8_t level);

drivers/platform/x86/winmate-fm07-keys.c

31

uint8_t k;

drivers/pmdomain/bcm/bcm63xx-power.c

34

uint8_t bit;

drivers/pmdomain/bcm/bcm63xx-power.c

96

uint8_t max_bit = 0;

drivers/power/supply/da9030_battery.c

108

uint8_t fault;

drivers/power/supply/da9030_battery.c

203

sizeof(*adc), (uint8_t *)adc);

drivers/power/supply/da9030_battery.c

208

uint8_t val;

drivers/power/supply/da9030_battery.c

223

uint8_t val;

drivers/power/supply/da9030_battery.c

61

uint8_t vbat_res;

drivers/power/supply/da9030_battery.c

62

uint8_t vbatmin_res;

drivers/power/supply/da9030_battery.c

63

uint8_t vbatmintxon;

drivers/power/supply/da9030_battery.c

64

uint8_t ichmax_res;

drivers/power/supply/da9030_battery.c

65

uint8_t ichmin_res;

drivers/power/supply/da9030_battery.c

66

uint8_t ichaverage_res;

drivers/power/supply/da9030_battery.c

67

uint8_t vchmax_res;

drivers/power/supply/da9030_battery.c

68

uint8_t vchmin_res;

drivers/power/supply/da9030_battery.c

69

uint8_t tbat_res;

drivers/power/supply/da9030_battery.c

70

uint8_t adc_in4_res;

drivers/power/supply/da9030_battery.c

71

uint8_t adc_in5_res;

drivers/power/supply/max14656_charger_detector.c

172

uint8_t val = 0;

drivers/power/supply/max14656_charger_detector.c

173

uint8_t rev;

drivers/power/supply/max1721x_battery.c

227

uint16_t reg, uint8_t nr, char *str)

drivers/power/supply/olpc_battery.c

125

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

162

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

187

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

212

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

258

uint8_t soc;

drivers/power/supply/olpc_battery.c

276

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

341

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

532

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

564

uint8_t ec_byte;

drivers/power/supply/olpc_battery.c

638

uint8_t status;

drivers/power/supply/olpc_battery.c

639

uint8_t ecver;

drivers/power/supply/olpc_battery.c

69

uint8_t status;

drivers/power/supply/olpc_battery.c

99

union power_supply_propval *val, uint8_t ec_byte)

drivers/power/supply/tps65090-charger.c

142

uint8_t status1 = 0;

drivers/power/supply/tps65090-charger.c

143

uint8_t intrsts = 0;

drivers/power/supply/tps65090-charger.c

234

uint8_t status1 = 0;

drivers/power/supply/tps65090-charger.c

64

uint8_t ctrl0 = 0;

drivers/power/supply/tps65090-charger.c

89

uint8_t intrmask = 0;

drivers/ptp/ptp_vmclock.c

73

uint64_t period, uint8_t shift,

drivers/regulator/da903x-regulator.c

104

uint8_t val, mask;

drivers/regulator/da903x-regulator.c

119

uint8_t val, mask;

drivers/regulator/da903x-regulator.c

157

uint8_t reg_val;

drivers/regulator/da903x-regulator.c

173

uint8_t val, mask;

drivers/regulator/da903x-regulator.c

236

uint8_t val, mask;

drivers/regulator/max8973-regulator.c

320

uint8_t control1 = 0;

drivers/regulator/max8973-regulator.c

321

uint8_t control2 = 0;

drivers/regulator/mpq7920.c

213

uint8_t val;

drivers/regulator/mpq7920.c

244

uint8_t freq;

drivers/regulator/pf0900-regulator.c

305

static uint8_t crc8_j1850(unsigned short addr, unsigned int reg,

drivers/regulator/pf0900-regulator.c

308

uint8_t crcBuf[3];

drivers/regulator/pf0900-regulator.c

309

uint8_t t_crc;

drivers/regulator/pf0900-regulator.c

310

uint8_t i, j;

drivers/regulator/pf0900-regulator.c

394

uint8_t data[2];

drivers/regulator/rc5t583-regulator.c

25

uint8_t reg_disc_reg;

drivers/regulator/rc5t583-regulator.c

26

uint8_t disc_bit;

drivers/regulator/rc5t583-regulator.c

27

uint8_t deepsleep_reg;

drivers/regulator/rt6160-regulator.c

49

uint8_t devid;

drivers/regulator/tps51632-regulator.c

109

uint8_t control = 0;

drivers/regulator/tps6586x-regulator.c

270

uint8_t val1, val2;

drivers/regulator/tps6586x-regulator.c

308

uint8_t reg;

drivers/remoteproc/qcom_sysmon.c

217

.elem_size = sizeof(uint8_t),

drivers/remoteproc/qcom_sysmon.c

247

.elem_size = sizeof(uint8_t),

drivers/rtc/rtc-bq32k.c

257

uint8_t reg;

drivers/rtc/rtc-bq32k.c

42

uint8_t seconds;

drivers/rtc/rtc-bq32k.c

43

uint8_t minutes;

drivers/rtc/rtc-bq32k.c

44

uint8_t cent_hours;

drivers/rtc/rtc-bq32k.c

45

uint8_t day;

drivers/rtc/rtc-bq32k.c

46

uint8_t date;

drivers/rtc/rtc-bq32k.c

47

uint8_t month;

drivers/rtc/rtc-bq32k.c

48

uint8_t years;

drivers/rtc/rtc-bq32k.c

53

static int bq32k_read(struct device *dev, void *data, uint8_t off, uint8_t len)

drivers/rtc/rtc-bq32k.c

76

static int bq32k_write(struct device *dev, void *data, uint8_t off, uint8_t len)

drivers/rtc/rtc-bq32k.c

79

uint8_t buffer[MAX_LEN + 1];

drivers/rtc/rtc-da9052.c

104

uint8_t v[3];

drivers/rtc/rtc-da9052.c

157

uint8_t v[2][6];

drivers/rtc/rtc-da9052.c

199

uint8_t v[6];

drivers/rtc/rtc-da9052.c

59

uint8_t v[2][5];

drivers/rtc/rtc-da9055.c

128

uint8_t v[6];

drivers/rtc/rtc-da9055.c

162

uint8_t v[6];

drivers/rtc/rtc-da9055.c

59

uint8_t v[5];

drivers/rtc/rtc-da9055.c

80

uint8_t v[2];

drivers/rtc/rtc-ds1511.c

74

static void rtc_write(uint8_t val, uint32_t reg)

drivers/rtc/rtc-ds1511.c

79

static uint8_t rtc_read(uint32_t reg)

drivers/rtc/rtc-pcf2127.c

678

uint8_t buf[5];

drivers/rtc/rtc-rc5t619.c

42

static uint8_t rtc5t619_12hour_bcd2bin(uint8_t hour)

drivers/rtc/rtc-rc5t619.c

53

static uint8_t rtc5t619_12hour_bin2bcd(uint8_t hour)

drivers/s390/cio/vfio_ccw_ops.c

412

uint8_t trigger;

drivers/s390/cio/vfio_ccw_ops.c

414

if (get_user(trigger, (uint8_t __user *)data))

drivers/scsi/aic7xxx/aic7770.c

259

uint8_t scsi_conf;

drivers/scsi/aic7xxx/aic7770.c

306

uint8_t target_settings;

drivers/scsi/aic7xxx/aic79xx.h

1000

uint8_t seqctl;

drivers/scsi/aic7xxx/aic79xx.h

1005

uint8_t command;

drivers/scsi/aic7xxx/aic79xx.h

1006

uint8_t csize_lattime;

drivers/scsi/aic7xxx/aic79xx.h

1012

uint8_t optionmode;

drivers/scsi/aic7xxx/aic79xx.h

1013

uint8_t dscommand0;

drivers/scsi/aic7xxx/aic79xx.h

1014

uint8_t dspcistatus;

drivers/scsi/aic7xxx/aic79xx.h

1016

uint8_t crccontrol1;

drivers/scsi/aic7xxx/aic79xx.h

1017

uint8_t scbbaddr;

drivers/scsi/aic7xxx/aic79xx.h

1019

uint8_t dff_thrsh;

drivers/scsi/aic7xxx/aic79xx.h

1020

uint8_t *scratch_ram;

drivers/scsi/aic7xxx/aic79xx.h

1021

uint8_t *btt;

drivers/scsi/aic7xxx/aic79xx.h

1044

typedef uint8_t ahd_mode_state;

drivers/scsi/aic7xxx/aic79xx.h

1049

uint8_t sg_status;

drivers/scsi/aic7xxx/aic79xx.h

1050

uint8_t valid_tag;

drivers/scsi/aic7xxx/aic79xx.h

1152

uint8_t unpause;

drivers/scsi/aic7xxx/aic79xx.h

1153

uint8_t pause;

drivers/scsi/aic7xxx/aic79xx.h

1160

uint8_t *overrun_buf;

drivers/scsi/aic7xxx/aic79xx.h

1169

uint8_t our_id;

drivers/scsi/aic7xxx/aic79xx.h

1175

uint8_t tqinfifonext;

drivers/scsi/aic7xxx/aic79xx.h

1181

uint8_t hs_mailbox;

drivers/scsi/aic7xxx/aic79xx.h

1186

uint8_t send_msg_perror;

drivers/scsi/aic7xxx/aic79xx.h

1189

uint8_t msgout_buf[12];/* Message we are sending */

drivers/scsi/aic7xxx/aic79xx.h

1190

uint8_t msgin_buf[12];/* Message we are receiving */

drivers/scsi/aic7xxx/aic79xx.h

1216

uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];

drivers/scsi/aic7xxx/aic79xx.h

1363

uint8_t *value);

drivers/scsi/aic7xxx/aic79xx.h

398

uint8_t scsi_status; /* Standard SCSI status byte */

drivers/scsi/aic7xxx/aic79xx.h

404

uint8_t scsi_status; /* SCSI status to give to initiator */

drivers/scsi/aic7xxx/aic79xx.h

405

uint8_t target_phases; /* Bitmap of phases to execute */

drivers/scsi/aic7xxx/aic79xx.h

406

uint8_t data_phase; /* Data-In or Data-Out */

drivers/scsi/aic7xxx/aic79xx.h

407

uint8_t initiator_tag; /* Initiator's transaction tag */

drivers/scsi/aic7xxx/aic79xx.h

423

uint8_t cdblen;

drivers/scsi/aic7xxx/aic79xx.h

425

uint8_t cdb[MAX_CDB_LEN];

drivers/scsi/aic7xxx/aic79xx.h

427

uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];

drivers/scsi/aic7xxx/aic79xx.h

437

uint8_t scsi_status; /* SCSI status to give to initiator */

drivers/scsi/aic7xxx/aic79xx.h

438

uint8_t target_phases; /* Bitmap of phases to execute */

drivers/scsi/aic7xxx/aic79xx.h

439

uint8_t data_phase; /* Data-In or Data-Out */

drivers/scsi/aic7xxx/aic79xx.h

440

uint8_t initiator_tag; /* Initiator's transaction tag */

drivers/scsi/aic7xxx/aic79xx.h

491

/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */

drivers/scsi/aic7xxx/aic79xx.h

492

/*19*/ uint8_t scsiid; /*

drivers/scsi/aic7xxx/aic79xx.h

496

/*20*/ uint8_t lun;

drivers/scsi/aic7xxx/aic79xx.h

497

/*21*/ uint8_t task_attribute;

drivers/scsi/aic7xxx/aic79xx.h

498

/*22*/ uint8_t cdb_len;

drivers/scsi/aic7xxx/aic79xx.h

499

/*23*/ uint8_t task_management;

drivers/scsi/aic7xxx/aic79xx.h

506

/*48*/ uint8_t pkt_long_lun[8];

drivers/scsi/aic7xxx/aic79xx.h

508

/*56*/ uint8_t spare[8];

drivers/scsi/aic7xxx/aic79xx.h

543

uint8_t *vaddr;

drivers/scsi/aic7xxx/aic79xx.h

615

uint8_t *sense_data;

drivers/scsi/aic7xxx/aic79xx.h

663

uint8_t init_level; /*

drivers/scsi/aic7xxx/aic79xx.h

675

uint8_t scsiid; /* Our ID and the initiator's ID */

drivers/scsi/aic7xxx/aic79xx.h

676

uint8_t identify; /* Identify message */

drivers/scsi/aic7xxx/aic79xx.h

677

uint8_t bytes[22]; /*

drivers/scsi/aic7xxx/aic79xx.h

682

uint8_t cmd_valid; /*

drivers/scsi/aic7xxx/aic79xx.h

693

uint8_t pad[7];

drivers/scsi/aic7xxx/aic79xx.h

702

uint8_t initiator_id;

drivers/scsi/aic7xxx/aic79xx.h

703

uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */

drivers/scsi/aic7xxx/aic79xx.h

705

uint8_t event_arg;

drivers/scsi/aic7xxx/aic79xx.h

721

uint8_t event_r_idx;

drivers/scsi/aic7xxx/aic79xx.h

722

uint8_t event_w_idx;

drivers/scsi/aic7xxx/aic79xx.h

744

uint8_t protocol_version; /* SCSI Revision level */

drivers/scsi/aic7xxx/aic79xx.h

745

uint8_t transport_version; /* SPI Revision level */

drivers/scsi/aic7xxx/aic79xx.h

746

uint8_t width; /* Bus width */

drivers/scsi/aic7xxx/aic79xx.h

747

uint8_t period; /* Sync rate factor */

drivers/scsi/aic7xxx/aic79xx.h

748

uint8_t offset; /* Sync offset */

drivers/scsi/aic7xxx/aic79xx.h

749

uint8_t ppr_options; /* Parallel Protocol Request options */

drivers/scsi/aic7xxx/aic79xx.h

813

uint8_t phase;

drivers/scsi/aic7xxx/aic79xx.h

814

uint8_t mesg_out; /* Message response to parity errors */

drivers/scsi/aic7xxx/aic79xx.h

898

uint8_t bios_flags;

drivers/scsi/aic7xxx/aic79xx.h

901

uint8_t reserved_1[21];

drivers/scsi/aic7xxx/aic79xx.h

902

uint8_t resource_type;

drivers/scsi/aic7xxx/aic79xx.h

903

uint8_t resource_len[2];

drivers/scsi/aic7xxx/aic79xx.h

904

uint8_t resource_data[8];

drivers/scsi/aic7xxx/aic79xx.h

905

uint8_t vpd_tag;

drivers/scsi/aic7xxx/aic79xx.h

907

uint8_t vpd_keyword[2];

drivers/scsi/aic7xxx/aic79xx.h

908

uint8_t length;

drivers/scsi/aic7xxx/aic79xx.h

909

uint8_t revision;

drivers/scsi/aic7xxx/aic79xx.h

910

uint8_t device_flags;

drivers/scsi/aic7xxx/aic79xx.h

911

uint8_t termination_menus[2];

drivers/scsi/aic7xxx/aic79xx.h

912

uint8_t fifo_threshold;

drivers/scsi/aic7xxx/aic79xx.h

913

uint8_t end_tag;

drivers/scsi/aic7xxx/aic79xx.h

914

uint8_t vpd_checksum;

drivers/scsi/aic7xxx/aic79xx.h

918

uint8_t default_irq;

drivers/scsi/aic7xxx/aic79xx.h

919

uint8_t pci_lattime;

drivers/scsi/aic7xxx/aic79xx.h

920

uint8_t max_target;

drivers/scsi/aic7xxx/aic79xx.h

921

uint8_t boot_lun;

drivers/scsi/aic7xxx/aic79xx.h

923

uint8_t reserved_2;

drivers/scsi/aic7xxx/aic79xx.h

924

uint8_t checksum;

drivers/scsi/aic7xxx/aic79xx.h

925

uint8_t reserved_3[4];

drivers/scsi/aic7xxx/aic79xx.h

994

uint8_t scsiseq;

drivers/scsi/aic7xxx/aic79xx.h

995

uint8_t sxfrctl0;

drivers/scsi/aic7xxx/aic79xx.h

996

uint8_t sxfrctl1;

drivers/scsi/aic7xxx/aic79xx.h

997

uint8_t simode0;

drivers/scsi/aic7xxx/aic79xx.h

998

uint8_t simode1;

drivers/scsi/aic7xxx/aic79xx.h

999

uint8_t seltimer;

drivers/scsi/aic7xxx/aic79xx_core.c

10045

uint8_t *vpdarray;

drivers/scsi/aic7xxx/aic79xx_core.c

10047

vpdarray = (uint8_t *)vpd;

drivers/scsi/aic7xxx/aic79xx_core.c

10101

uint8_t seetype;

drivers/scsi/aic7xxx/aic79xx_core.c

10160

ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)

drivers/scsi/aic7xxx/aic79xx_core.c

10617

uint8_t *byte;

drivers/scsi/aic7xxx/aic79xx_core.c

1327

uint8_t *hscb_ptr;

drivers/scsi/aic7xxx/aic79xx_core.c

1338

hscb_ptr = (uint8_t *)scb->hscb;

drivers/scsi/aic7xxx/aic79xx_core.c

213

u_int instrptr, uint8_t *dconsts);

drivers/scsi/aic7xxx/aic79xx_core.c

4075

uint8_t iocell_opts[sizeof(ahd->iocell_opts)];

drivers/scsi/aic7xxx/aic79xx_core.c

503

return ((uint8_t *)scb->sg_list + sg_offset);

drivers/scsi/aic7xxx/aic79xx_core.c

512

sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)

drivers/scsi/aic7xxx/aic79xx_core.c

523

/*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,

drivers/scsi/aic7xxx/aic79xx_core.c

552

return (((uint8_t *)&ahd->targetcmds[index])

drivers/scsi/aic7xxx/aic79xx_core.c

553

- (uint8_t *)ahd->qoutfifo);

drivers/scsi/aic7xxx/aic79xx_core.c

60

uint8_t errno;

drivers/scsi/aic7xxx/aic79xx_core.c

6759

uint8_t *segs;

drivers/scsi/aic7xxx/aic79xx_core.c

6760

uint8_t *sense_data;

drivers/scsi/aic7xxx/aic79xx_core.c

6989

uint8_t *next_vaddr;

drivers/scsi/aic7xxx/aic79xx_core.c

6995

uint8_t current_sensing;

drivers/scsi/aic7xxx/aic79xx_core.c

6996

uint8_t fstat;

drivers/scsi/aic7xxx/aic79xx_core.c

7074

next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];

drivers/scsi/aic7xxx/aic79xx_core.c

8585

uint8_t scsiseq;

drivers/scsi/aic7xxx/aic79xx_core.c

8622

uint8_t scsiseq;

drivers/scsi/aic7xxx/aic79xx_core.c

9244

uint8_t ins_bytes[4];

drivers/scsi/aic7xxx/aic79xx_core.c

9272

uint8_t download_consts[DOWNLOAD_CONST_COUNT];

drivers/scsi/aic7xxx/aic79xx_core.c

9355

(ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;

drivers/scsi/aic7xxx/aic79xx_core.c

9480

ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)

drivers/scsi/aic7xxx/aic79xx_core.c

9951

uint8_t *bytestream_ptr;

drivers/scsi/aic7xxx/aic79xx_core.c

9953

bytestream_ptr = (uint8_t *)buf;

drivers/scsi/aic7xxx/aic79xx_inline.h

142

static inline uint8_t *ahd_get_sense_buf(struct ahd_softc *ahd,

drivers/scsi/aic7xxx/aic79xx_inline.h

157

static inline uint8_t *

drivers/scsi/aic7xxx/aic79xx_osm.c

1004

uint8_t *iocell_info;

drivers/scsi/aic7xxx/aic79xx_osm.c

1006

iocell_info = (uint8_t*)&aic79xx_iocell_info[instance];

drivers/scsi/aic7xxx/aic79xx_osm.c

181

uint8_t precomp;

drivers/scsi/aic7xxx/aic79xx_osm.c

182

uint8_t slewrate;

drivers/scsi/aic7xxx/aic79xx_osm.c

183

uint8_t amplitude;

drivers/scsi/aic7xxx/aic79xx_osm.c

2729

uint8_t precomp;

drivers/scsi/aic7xxx/aic79xx_osm.c

391

uint8_t ahd_inb(struct ahd_softc * ahd, long port);

drivers/scsi/aic7xxx/aic79xx_osm.c

392

void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val);

drivers/scsi/aic7xxx/aic79xx_osm.c

396

uint8_t *, int count);

drivers/scsi/aic7xxx/aic79xx_osm.c

398

uint8_t *, int count);

drivers/scsi/aic7xxx/aic79xx_osm.c

400

uint8_t

drivers/scsi/aic7xxx/aic79xx_osm.c

403

uint8_t x;

drivers/scsi/aic7xxx/aic79xx_osm.c

418

uint8_t x;

drivers/scsi/aic7xxx/aic79xx_osm.c

431

ahd_outb(struct ahd_softc * ahd, long port, uint8_t val)

drivers/scsi/aic7xxx/aic79xx_osm.c

453

ahd_outsb(struct ahd_softc * ahd, long port, uint8_t *array, int count)

drivers/scsi/aic7xxx/aic79xx_osm.c

467

ahd_insb(struct ahd_softc * ahd, long port, uint8_t *array, int count)

drivers/scsi/aic7xxx/aic79xx_osm.c

487

uint8_t retval;

drivers/scsi/aic7xxx/aic79xx_osm.h

127

volatile uint8_t __iomem *maddr;

drivers/scsi/aic7xxx/aic79xx_osm.h

357

uint8_t ahd_inb(struct ahd_softc * ahd, long port);

drivers/scsi/aic7xxx/aic79xx_osm.h

358

void ahd_outb(struct ahd_softc * ahd, long port, uint8_t val);

drivers/scsi/aic7xxx/aic79xx_osm.h

362

uint8_t *, int count);

drivers/scsi/aic7xxx/aic79xx_osm.h

364

uint8_t *, int count);

drivers/scsi/aic7xxx/aic79xx_osm_pci.c

256

uint8_t __iomem **maddr)

drivers/scsi/aic7xxx/aic79xx_osm_pci.c

294

uint8_t __iomem *maddr;

drivers/scsi/aic7xxx/aic79xx_pci.c

418

uint8_t hcntrl;

drivers/scsi/aic7xxx/aic79xx_pci.c

641

uint8_t termctl;

drivers/scsi/aic7xxx/aic79xx_pci.c

783

uint8_t pci_status[8];

drivers/scsi/aic7xxx/aic79xx_pci.c

841

uint8_t split_status[4];

drivers/scsi/aic7xxx/aic79xx_pci.c

842

uint8_t split_status1[4];

drivers/scsi/aic7xxx/aic79xx_pci.c

843

uint8_t sg_split_status[2];

drivers/scsi/aic7xxx/aic79xx_pci.c

844

uint8_t sg_split_status1[2];

drivers/scsi/aic7xxx/aic7xxx.h

1005

uint8_t our_id;

drivers/scsi/aic7xxx/aic7xxx.h

1006

uint8_t our_id_b;

drivers/scsi/aic7xxx/aic7xxx.h

1017

uint8_t tqinfifonext;

drivers/scsi/aic7xxx/aic7xxx.h

1022

uint8_t seqctl;

drivers/scsi/aic7xxx/aic7xxx.h

1027

uint8_t send_msg_perror;

drivers/scsi/aic7xxx/aic7xxx.h

1029

uint8_t msgout_buf[12];/* Message we are sending */

drivers/scsi/aic7xxx/aic7xxx.h

1030

uint8_t msgin_buf[12];/* Message we are receiving */

drivers/scsi/aic7xxx/aic7xxx.h

389

uint8_t scsi_status; /* Standard SCSI status byte */

drivers/scsi/aic7xxx/aic7xxx.h

398

uint8_t scsi_status; /* SCSI status to give to initiator */

drivers/scsi/aic7xxx/aic7xxx.h

399

uint8_t target_phases; /* Bitmap of phases to execute */

drivers/scsi/aic7xxx/aic7xxx.h

400

uint8_t data_phase; /* Data-In or Data-Out */

drivers/scsi/aic7xxx/aic7xxx.h

401

uint8_t initiator_tag; /* Initiator's transaction tag */

drivers/scsi/aic7xxx/aic7xxx.h

412

uint8_t cdb[12];

drivers/scsi/aic7xxx/aic7xxx.h

462

/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */

drivers/scsi/aic7xxx/aic7xxx.h

463

/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */

drivers/scsi/aic7xxx/aic7xxx.h

464

/*26*/ uint8_t lun;

drivers/scsi/aic7xxx/aic7xxx.h

465

/*27*/ uint8_t tag; /*

drivers/scsi/aic7xxx/aic7xxx.h

469

/*28*/ uint8_t cdb_len;

drivers/scsi/aic7xxx/aic7xxx.h

470

/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */

drivers/scsi/aic7xxx/aic7xxx.h

471

/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */

drivers/scsi/aic7xxx/aic7xxx.h

472

/*31*/ uint8_t next; /*

drivers/scsi/aic7xxx/aic7xxx.h

478

/*32*/ uint8_t cdb32[32]; /*

drivers/scsi/aic7xxx/aic7xxx.h

607

uint8_t numscbs;

drivers/scsi/aic7xxx/aic7xxx.h

608

uint8_t maxhscbs; /* Number of SCBs on the card */

drivers/scsi/aic7xxx/aic7xxx.h

609

uint8_t init_level; /*

drivers/scsi/aic7xxx/aic7xxx.h

621

uint8_t scsiid; /* Our ID and the initiator's ID */

drivers/scsi/aic7xxx/aic7xxx.h

622

uint8_t identify; /* Identify message */

drivers/scsi/aic7xxx/aic7xxx.h

623

uint8_t bytes[22]; /*

drivers/scsi/aic7xxx/aic7xxx.h

628

uint8_t cmd_valid; /*

drivers/scsi/aic7xxx/aic7xxx.h

639

uint8_t pad[7];

drivers/scsi/aic7xxx/aic7xxx.h

648

uint8_t initiator_id;

drivers/scsi/aic7xxx/aic7xxx.h

649

uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */

drivers/scsi/aic7xxx/aic7xxx.h

651

uint8_t event_arg;

drivers/scsi/aic7xxx/aic7xxx.h

667

uint8_t event_r_idx;

drivers/scsi/aic7xxx/aic7xxx.h

668

uint8_t event_w_idx;

drivers/scsi/aic7xxx/aic7xxx.h

689

uint8_t protocol_version; /* SCSI Revision level */

drivers/scsi/aic7xxx/aic7xxx.h

690

uint8_t transport_version; /* SPI Revision level */

drivers/scsi/aic7xxx/aic7xxx.h

691

uint8_t width; /* Bus width */

drivers/scsi/aic7xxx/aic7xxx.h

692

uint8_t period; /* Sync rate factor */

drivers/scsi/aic7xxx/aic7xxx.h

693

uint8_t offset; /* Sync offset */

drivers/scsi/aic7xxx/aic7xxx.h

694

uint8_t ppr_options; /* Parallel Protocol Request options */

drivers/scsi/aic7xxx/aic7xxx.h

700

uint8_t scsirate; /* Computed value for SCSIRATE reg */

drivers/scsi/aic7xxx/aic7xxx.h

735

uint8_t period; /* Period to send to SCSI target */

drivers/scsi/aic7xxx/aic7xxx.h

759

uint8_t phase;

drivers/scsi/aic7xxx/aic7xxx.h

760

uint8_t mesg_out; /* Message response to parity errors */

drivers/scsi/aic7xxx/aic7xxx.h

872

uint8_t busspd;

drivers/scsi/aic7xxx/aic7xxx.h

873

uint8_t bustime;

drivers/scsi/aic7xxx/aic7xxx.h

882

uint8_t command;

drivers/scsi/aic7xxx/aic7xxx.h

883

uint8_t csize_lattime;

drivers/scsi/aic7xxx/aic7xxx.h

884

uint8_t optionmode;

drivers/scsi/aic7xxx/aic7xxx.h

885

uint8_t crccontrol1;

drivers/scsi/aic7xxx/aic7xxx.h

886

uint8_t dscommand0;

drivers/scsi/aic7xxx/aic7xxx.h

887

uint8_t dspcistatus;

drivers/scsi/aic7xxx/aic7xxx.h

888

uint8_t scbbaddr;

drivers/scsi/aic7xxx/aic7xxx.h

889

uint8_t dff_thrsh;

drivers/scsi/aic7xxx/aic7xxx.h

987

uint8_t unpause;

drivers/scsi/aic7xxx/aic7xxx.h

988

uint8_t pause;

drivers/scsi/aic7xxx/aic7xxx.h

991

uint8_t qoutfifonext;

drivers/scsi/aic7xxx/aic7xxx.h

992

uint8_t qinfifonext;

drivers/scsi/aic7xxx/aic7xxx.h

993

uint8_t *qoutfifo;

drivers/scsi/aic7xxx/aic7xxx.h

994

uint8_t *qinfifo;

drivers/scsi/aic7xxx/aic7xxx_93cx6.c

107

uint8_t temp;

drivers/scsi/aic7xxx/aic7xxx_93cx6.c

133

uint8_t temp;

drivers/scsi/aic7xxx/aic7xxx_93cx6.c

155

uint8_t temp;

drivers/scsi/aic7xxx/aic7xxx_93cx6.c

226

uint8_t temp;

drivers/scsi/aic7xxx/aic7xxx_93cx6.c

76

uint8_t len;

drivers/scsi/aic7xxx/aic7xxx_93cx6.c

77

uint8_t bits[11];

drivers/scsi/aic7xxx/aic7xxx_core.c

220

u_int instrptr, uint8_t *dconsts);

drivers/scsi/aic7xxx/aic7xxx_core.c

419

return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);

drivers/scsi/aic7xxx/aic7xxx_core.c

5295

driver_data_size = 2 * 256 * sizeof(uint8_t);

drivers/scsi/aic7xxx/aic7xxx_core.c

5329

ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];

drivers/scsi/aic7xxx/aic7xxx_core.c

5336

ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];

drivers/scsi/aic7xxx/aic7xxx_core.c

5752

uint8_t prev_pos;

drivers/scsi/aic7xxx/aic7xxx_core.c

5785

uint8_t qinpos;

drivers/scsi/aic7xxx/aic7xxx_core.c

5786

uint8_t diff;

drivers/scsi/aic7xxx/aic7xxx_core.c

5804

uint8_t qinstart;

drivers/scsi/aic7xxx/aic7xxx_core.c

5805

uint8_t qinpos;

drivers/scsi/aic7xxx/aic7xxx_core.c

5806

uint8_t qintail;

drivers/scsi/aic7xxx/aic7xxx_core.c

5807

uint8_t next;

drivers/scsi/aic7xxx/aic7xxx_core.c

5808

uint8_t prev;

drivers/scsi/aic7xxx/aic7xxx_core.c

5809

uint8_t curscbptr;

drivers/scsi/aic7xxx/aic7xxx_core.c

5940

uint8_t scb_index;

drivers/scsi/aic7xxx/aic7xxx_core.c

6400

uint8_t scsiseq;

drivers/scsi/aic7xxx/aic7xxx_core.c

6771

uint8_t ins_bytes[4];

drivers/scsi/aic7xxx/aic7xxx_core.c

6795

uint8_t download_consts[7];

drivers/scsi/aic7xxx/aic7xxx_core.c

69

uint8_t errno;

drivers/scsi/aic7xxx/aic7xxx_core.c

6928

ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)

drivers/scsi/aic7xxx/aic7xxx_core.c

7109

uint8_t last_phase;

drivers/scsi/aic7xxx/aic7xxx_core.c

7110

uint8_t qinpos;

drivers/scsi/aic7xxx/aic7xxx_core.c

7111

uint8_t qintail;

drivers/scsi/aic7xxx/aic7xxx_core.c

7112

uint8_t qoutpos;

drivers/scsi/aic7xxx/aic7xxx_core.c

7113

uint8_t scb_index;

drivers/scsi/aic7xxx/aic7xxx_core.c

7114

uint8_t saved_scbptr;

drivers/scsi/aic7xxx/aic7xxx_core.c

7794

uint8_t *byte;

drivers/scsi/aic7xxx/aic7xxx_core.c

810

uint8_t sblkctl;

drivers/scsi/aic7xxx/aic7xxx_osm.c

160

uint8_t tag_commands[16]; /* Allow for wide/twin adapters. */

drivers/scsi/aic7xxx/aic7xxx_osm.c

400

uint8_t

drivers/scsi/aic7xxx/aic7xxx_osm.c

403

uint8_t x;

drivers/scsi/aic7xxx/aic7xxx_osm.c

415

ahc_outb(struct ahc_softc * ahc, long port, uint8_t val)

drivers/scsi/aic7xxx/aic7xxx_osm.c

426

ahc_outsb(struct ahc_softc * ahc, long port, uint8_t *array, int count)

drivers/scsi/aic7xxx/aic7xxx_osm.c

440

ahc_insb(struct ahc_softc * ahc, long port, uint8_t *array, int count)

drivers/scsi/aic7xxx/aic7xxx_osm.h

140

volatile uint8_t __iomem *maddr;

drivers/scsi/aic7xxx/aic7xxx_osm.h

370

uint8_t ahc_inb(struct ahc_softc * ahc, long port);

drivers/scsi/aic7xxx/aic7xxx_osm.h

371

void ahc_outb(struct ahc_softc * ahc, long port, uint8_t val);

drivers/scsi/aic7xxx/aic7xxx_osm.h

373

uint8_t *, int count);

drivers/scsi/aic7xxx/aic7xxx_osm.h

375

uint8_t *, int count);

drivers/scsi/aic7xxx/aic7xxx_osm_pci.c

254

uint8_t retval;

drivers/scsi/aic7xxx/aic7xxx_osm_pci.c

338

uint8_t __iomem **maddr)

drivers/scsi/aic7xxx/aic7xxx_osm_pci.c

366

uint8_t __iomem *maddr;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1169

uint8_t hcntrl;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1525

uint8_t brddat;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1750

uint8_t brdctl;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1772

uint8_t brdctl;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1812

uint8_t brdctl;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1813

uint8_t spiocap;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1867

write_brdctl(struct ahc_softc *ahc, uint8_t value)

drivers/scsi/aic7xxx/aic7xxx_pci.c

1869

uint8_t brdctl;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1898

static uint8_t

drivers/scsi/aic7xxx/aic7xxx_pci.c

1901

uint8_t brdctl;

drivers/scsi/aic7xxx/aic7xxx_pci.c

1902

uint8_t value;

drivers/scsi/aic7xxx/aic7xxx_pci.c

2047

uint8_t rev;

drivers/scsi/aic7xxx/aic7xxx_pci.c

2065

uint8_t rev;

drivers/scsi/aic7xxx/aic7xxx_pci.c

2170

uint8_t rev;

drivers/scsi/aic7xxx/aic7xxx_pci.c

2242

uint8_t rev;

drivers/scsi/aic7xxx/aic7xxx_pci.c

2273

uint8_t rev;

drivers/scsi/aic7xxx/aic7xxx_pci.c

624

static void write_brdctl(struct ahc_softc *ahc, uint8_t value);

drivers/scsi/aic7xxx/aic7xxx_pci.c

625

static uint8_t read_brdctl(struct ahc_softc *ahc);

drivers/scsi/aic7xxx/aic7xxx_pci.c

714

uint8_t sblkctl;

drivers/scsi/aic7xxx/aicasm/aicasm_gram.y

1728

uint8_t shift_control;

drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h

164

uint8_t bytes[4];

drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h

77

uint8_t valid_bitmask;

drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h

78

uint8_t modes;

drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h

84

uint8_t value;

drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h

85

uint8_t mask;

drivers/scsi/aic7xxx/aiclib.h

104

uint8_t info[4];

drivers/scsi/aic7xxx/aiclib.h

105

uint8_t extra_len;

drivers/scsi/aic7xxx/aiclib.h

106

uint8_t cmd_spec_info[4];

drivers/scsi/aic7xxx/aiclib.h

107

uint8_t add_sense_code;

drivers/scsi/aic7xxx/aiclib.h

108

uint8_t add_sense_code_qual;

drivers/scsi/aic7xxx/aiclib.h

109

uint8_t fru;

drivers/scsi/aic7xxx/aiclib.h

110

uint8_t sense_key_spec[3];

drivers/scsi/aic7xxx/aiclib.h

116

uint8_t extra_bytes[14];

drivers/scsi/aic7xxx/aiclib.h

130

scsi_4btoul(uint8_t *bytes)

drivers/scsi/aic7xxx/aiclib.h

62

uint8_t opcode;

drivers/scsi/aic7xxx/aiclib.h

63

uint8_t byte2;

drivers/scsi/aic7xxx/aiclib.h

64

uint8_t unused[2];

drivers/scsi/aic7xxx/aiclib.h

65

uint8_t length;

drivers/scsi/aic7xxx/aiclib.h

66

uint8_t control;

drivers/scsi/aic7xxx/aiclib.h

77

uint8_t error_code;

drivers/scsi/aic7xxx/aiclib.h

82

uint8_t segment;

drivers/scsi/aic7xxx/aiclib.h

83

uint8_t flags;

drivers/scsi/arcmsr/arcmsr.h

1019

uint8_t ErrorCode:7;

drivers/scsi/arcmsr/arcmsr.h

1022

uint8_t Valid:1;

drivers/scsi/arcmsr/arcmsr.h

1023

uint8_t SegmentNumber;

drivers/scsi/arcmsr/arcmsr.h

1024

uint8_t SenseKey:4;

drivers/scsi/arcmsr/arcmsr.h

1025

uint8_t Reserved:1;

drivers/scsi/arcmsr/arcmsr.h

1026

uint8_t IncorrectLength:1;

drivers/scsi/arcmsr/arcmsr.h

1027

uint8_t EndOfMedia:1;

drivers/scsi/arcmsr/arcmsr.h

1028

uint8_t FileMark:1;

drivers/scsi/arcmsr/arcmsr.h

1029

uint8_t Information[4];

drivers/scsi/arcmsr/arcmsr.h

1030

uint8_t AdditionalSenseLength;

drivers/scsi/arcmsr/arcmsr.h

1031

uint8_t CommandSpecificInformation[4];

drivers/scsi/arcmsr/arcmsr.h

1032

uint8_t AdditionalSenseCode;

drivers/scsi/arcmsr/arcmsr.h

1033

uint8_t AdditionalSenseCodeQualifier;

drivers/scsi/arcmsr/arcmsr.h

1034

uint8_t FieldReplaceableUnitCode;

drivers/scsi/arcmsr/arcmsr.h

1035

uint8_t SenseKeySpecific[3];

drivers/scsi/arcmsr/arcmsr.h

114

uint8_t Signature[8];

drivers/scsi/arcmsr/arcmsr.h

129

uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN];

drivers/scsi/arcmsr/arcmsr.h

197

uint8_t data[124];

drivers/scsi/arcmsr/arcmsr.h

216

uint8_t cfgSerial[16]; /*26,104-119*/

drivers/scsi/arcmsr/arcmsr.h

468

uint8_t Bus;

drivers/scsi/arcmsr/arcmsr.h

469

uint8_t TargetID;

drivers/scsi/arcmsr/arcmsr.h

470

uint8_t LUN;

drivers/scsi/arcmsr/arcmsr.h

471

uint8_t Function;

drivers/scsi/arcmsr/arcmsr.h

472

uint8_t CdbLength;

drivers/scsi/arcmsr/arcmsr.h

473

uint8_t sgcount;

drivers/scsi/arcmsr/arcmsr.h

474

uint8_t Flags;

drivers/scsi/arcmsr/arcmsr.h

482

uint8_t msgPages;

drivers/scsi/arcmsr/arcmsr.h

485

uint8_t Cdb[16];

drivers/scsi/arcmsr/arcmsr.h

486

uint8_t DeviceStatus;

drivers/scsi/arcmsr/arcmsr.h

492

uint8_t SenseData[15];

drivers/scsi/arcmsr/arcmsr.h

889

uint8_t adapter_index;

drivers/scsi/arcmsr/arcmsr.h

926

uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];

drivers/scsi/arcmsr/arcmsr.h

932

uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];

drivers/scsi/arcmsr/arcmsr.h

938

uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];

drivers/scsi/arcmsr/arcmsr_attr.c

118

uint8_t *pQbuffer, *ptmpuserbuffer;

drivers/scsi/arcmsr/arcmsr_attr.c

126

ptmpuserbuffer = (uint8_t *)buf;

drivers/scsi/arcmsr/arcmsr_attr.c

165

uint8_t *pQbuffer;

drivers/scsi/arcmsr/arcmsr_attr.c

70

uint8_t *ptmpQbuffer;

drivers/scsi/arcmsr/arcmsr_attr.c

78

ptmpQbuffer = (uint8_t *)buf;

drivers/scsi/arcmsr/arcmsr_hba.c

1084

uint8_t bus,dev_fun;

drivers/scsi/arcmsr/arcmsr_hba.c

1274

static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)

drivers/scsi/arcmsr/arcmsr_hba.c

1287

static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)

drivers/scsi/arcmsr/arcmsr_hba.c

1300

static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)

drivers/scsi/arcmsr/arcmsr_hba.c

1314

static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)

drivers/scsi/arcmsr/arcmsr_hba.c

1327

static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)

drivers/scsi/arcmsr/arcmsr_hba.c

1342

static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)

drivers/scsi/arcmsr/arcmsr_hba.c

1344

uint8_t rtnval = 0;

drivers/scsi/arcmsr/arcmsr_hba.c

1445

uint8_t id, lun;

drivers/scsi/arcmsr/arcmsr_hba.c

1888

arcmsr_cdb->sgcount = (uint8_t)nseg;

drivers/scsi/arcmsr/arcmsr_hba.c

2273

uint8_t *pQbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

2274

uint8_t *buf1 = NULL;

drivers/scsi/arcmsr/arcmsr_hba.c

2314

uint8_t *pQbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

2315

uint8_t __iomem *iop_data;

drivers/scsi/arcmsr/arcmsr_hba.c

2320

iop_data = (uint8_t __iomem *)prbuffer->data;

drivers/scsi/arcmsr/arcmsr_hba.c

2357

uint8_t *pQbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

2359

uint8_t *buf1 = NULL;

drivers/scsi/arcmsr/arcmsr_hba.c

2382

buf1 = (uint8_t *)buf2;

drivers/scsi/arcmsr/arcmsr_hba.c

2402

uint8_t *pQbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

2404

uint8_t __iomem *iop_data;

drivers/scsi/arcmsr/arcmsr_hba.c

2414

iop_data = (uint8_t __iomem *)pwbuffer->data;

drivers/scsi/arcmsr/arcmsr_hba.c

3024

uint8_t *ptmpQbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

3075

uint8_t *pQbuffer, *ptmpuserbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

3134

uint8_t *pQbuffer = acb->rqbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

3152

uint8_t *pQbuffer = acb->wqbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

3169

uint8_t *pQbuffer;

drivers/scsi/arcmsr/arcmsr_hba.c

3947

uint8_t year;

drivers/scsi/arcmsr/arcmsr_hba.c

3948

uint8_t month;

drivers/scsi/arcmsr/arcmsr_hba.c

3949

uint8_t date;

drivers/scsi/arcmsr/arcmsr_hba.c

3950

uint8_t hour;

drivers/scsi/arcmsr/arcmsr_hba.c

3951

uint8_t minute;

drivers/scsi/arcmsr/arcmsr_hba.c

3952

uint8_t second;

drivers/scsi/arcmsr/arcmsr_hba.c

403

static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)

drivers/scsi/arcmsr/arcmsr_hba.c

421

static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)

drivers/scsi/arcmsr/arcmsr_hba.c

441

static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)

drivers/scsi/arcmsr/arcmsr_hba.c

4529

uint8_t value[64];

drivers/scsi/arcmsr/arcmsr_hba.c

4637

static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)

drivers/scsi/arcmsr/arcmsr_hba.c

4641

uint8_t rtnval = 0x00;

drivers/scsi/be2iscsi/be_cmds.c

1079

uint8_t ulp_num)

drivers/scsi/be2iscsi/be_cmds.c

1335

uint8_t ulp_num = 0;

drivers/scsi/be2iscsi/be_cmds.c

1792

uint8_t i = 0;

drivers/scsi/be2iscsi/be_cmds.c

977

int entry_size, uint8_t is_header,

drivers/scsi/be2iscsi/be_cmds.c

978

uint8_t ulp_num)

drivers/scsi/be2iscsi/be_cmds.h

840

int entry_size, uint8_t is_header,

drivers/scsi/be2iscsi/be_cmds.h

841

uint8_t ulp_num);

drivers/scsi/be2iscsi/be_cmds.h

855

uint8_t ulp_num);

drivers/scsi/be2iscsi/be_main.c

1352

uint8_t type;

drivers/scsi/be2iscsi/be_main.c

2283

uint8_t dsp_value = 0;

drivers/scsi/be2iscsi/be_main.c

2365

uint8_t mem_descr_index, ulp_num;

drivers/scsi/be2iscsi/be_main.c

2711

uint8_t ulp_num;

drivers/scsi/be2iscsi/be_main.c

3135

unsigned int def_pdu_ring_sz, uint8_t ulp_num)

drivers/scsi/be2iscsi/be_main.c

3187

unsigned int def_pdu_ring_sz, uint8_t ulp_num)

drivers/scsi/be2iscsi/be_main.c

3352

uint8_t ulp_count = 0, ulp_base_num = 0;

drivers/scsi/be2iscsi/be_main.c

4353

static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)

drivers/scsi/be2iscsi/be_main.c

580

uint8_t ulp_num = 0;

drivers/scsi/be2iscsi/be_main.h

239

uint8_t ulp_num; /* ULP to which CID binded */

drivers/scsi/be2iscsi/be_main.h

469

uint8_t wrb_type;

drivers/scsi/bfa/bfa_ioc.c

5521

phy->ubuf = (uint8_t *) attr;

drivers/scsi/bfa/bfa_svc.c

5444

uint8_t *buf;

drivers/scsi/bfa/bfa_svc.c

6448

uint8_t subtesttype;

drivers/scsi/bfa/bfad_bsg.c

3279

sg_table = (struct bfa_sge_s *) (((uint8_t *)buf_base) +

drivers/scsi/bfa/bfad_bsg.c

3334

uint8_t lp_tag;

drivers/scsi/bfa/bfad_bsg.c

3405

if (copy_from_user((uint8_t *)bsg_fcpt,

drivers/scsi/bfa/bfad_bsg.c

3500

(((uint8_t *)drv_fcxp->reqbuf_info) +

drivers/scsi/bfa/bfad_bsg.c

3517

(((uint8_t *)drv_fcxp->rspbuf_info) +

drivers/scsi/bfa/bfad_bsg.c

3548

(uint8_t *)rsp_buf_info->virt,

drivers/scsi/bfa/bfi.h

326

uint8_t patch;

drivers/scsi/bfa/bfi.h

327

uint8_t maint;

drivers/scsi/bfa/bfi.h

328

uint8_t minor;

drivers/scsi/bfa/bfi.h

329

uint8_t major;

drivers/scsi/bfa/bfi.h

330

uint8_t rsvd[2];

drivers/scsi/bfa/bfi.h

331

uint8_t build;

drivers/scsi/bfa/bfi.h

332

uint8_t phase;

drivers/scsi/bfa/bfi.h

334

uint8_t major;

drivers/scsi/bfa/bfi.h

335

uint8_t minor;

drivers/scsi/bfa/bfi.h

336

uint8_t maint;

drivers/scsi/bfa/bfi.h

337

uint8_t patch;

drivers/scsi/bfa/bfi.h

338

uint8_t phase;

drivers/scsi/bfa/bfi.h

339

uint8_t build;

drivers/scsi/bfa/bfi.h

340

uint8_t rsvd[2];

drivers/scsi/csiostor/csio_attr.c

558

uint8_t wwn[8];

drivers/scsi/csiostor/csio_hw.c

1332

ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size);

drivers/scsi/csiostor/csio_hw.c

1781

uint8_t portid;

drivers/scsi/csiostor/csio_hw.c

265

const uint8_t *buf = &v->id_tag;

drivers/scsi/csiostor/csio_hw.c

266

const uint8_t *vpdr_len = &v->vpdr_tag;

drivers/scsi/csiostor/csio_hw.c

306

uint8_t *vpd, csum;

drivers/scsi/csiostor/csio_hw.c

3984

uint8_t evtq_stop = 0;

drivers/scsi/csiostor/csio_hw.c

528

uint32_t n, const uint8_t *data)

drivers/scsi/csiostor/csio_hw.c

567

if (memcmp(data - n, (uint8_t *)buf + offset, n)) {

drivers/scsi/csiostor/csio_hw.c

668

csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)

drivers/scsi/csiostor/csio_hw.c

674

uint8_t first_page[SF_PAGE_SIZE];

drivers/scsi/csiostor/csio_hw.c

753

(const uint8_t *)&hdr->fw_ver);

drivers/scsi/csiostor/csio_hw.c

921

uint8_t mpfn;

drivers/scsi/csiostor/csio_hw.h

174

uint8_t data[CSIO_EVT_MSG_SIZE];

drivers/scsi/csiostor/csio_hw.h

249

uint8_t width;

drivers/scsi/csiostor/csio_hw.h

266

uint8_t ec[EC_LEN + 1];

drivers/scsi/csiostor/csio_hw.h

267

uint8_t sn[SERNUM_LEN + 1];

drivers/scsi/csiostor/csio_hw.h

268

uint8_t id[ID_LEN + 1];

drivers/scsi/csiostor/csio_hw.h

327

uint8_t portid;

drivers/scsi/csiostor/csio_hw.h

328

uint8_t link_status;

drivers/scsi/csiostor/csio_hw.h

330

uint8_t mac[6];

drivers/scsi/csiostor/csio_hw.h

331

uint8_t mod_type;

drivers/scsi/csiostor/csio_hw.h

332

uint8_t rsvd1;

drivers/scsi/csiostor/csio_hw.h

333

uint8_t rsvd2;

drivers/scsi/csiostor/csio_hw.h

334

uint8_t rsvd3;

drivers/scsi/csiostor/csio_hw.h

512

uint8_t pfn; /* Physical Function

drivers/scsi/csiostor/csio_hw.h

516

uint8_t num_pports; /* Number of physical

drivers/scsi/csiostor/csio_hw.h

519

uint8_t rst_retries; /* Reset retries */

drivers/scsi/csiostor/csio_hw.h

520

uint8_t cur_evt; /* current s/m evt */

drivers/scsi/csiostor/csio_hw.h

521

uint8_t prev_evt; /* Previous s/m evt */

drivers/scsi/csiostor/csio_hw.h

539

uint8_t cfg_neq; /* FW configured no of

drivers/scsi/csiostor/csio_hw.h

542

uint8_t cfg_niq; /* FW configured no of

drivers/scsi/csiostor/csio_init.c

769

csio_lnodes_block_by_port(struct csio_hw *hw, uint8_t portid)

drivers/scsi/csiostor/csio_init.c

810

csio_lnodes_unblock_by_port(struct csio_hw *hw, uint8_t portid)

drivers/scsi/csiostor/csio_init.h

69

void csio_lnodes_block_by_port(struct csio_hw *, uint8_t);

drivers/scsi/csiostor/csio_init.h

70

void csio_lnodes_unblock_by_port(struct csio_hw *, uint8_t);

drivers/scsi/csiostor/csio_isr.c

150

uint8_t *scsiwr;

drivers/scsi/csiostor/csio_isr.c

151

uint8_t subop;

drivers/scsi/csiostor/csio_isr.c

516

cnt = min_t(uint8_t, hw->cfg_niq, cnt);

drivers/scsi/csiostor/csio_lnode.c

1035

csio_handle_link_down(struct csio_hw *hw, uint8_t portid, uint32_t fcfi,

drivers/scsi/csiostor/csio_lnode.c

105

#define csio_ct_get_pld(cp) ((void *)(((uint8_t *)cp) + FC_CT_HDR_LEN))

drivers/scsi/csiostor/csio_lnode.c

115

csio_ln_lookup_by_portid(struct csio_hw *hw, uint8_t portid)

drivers/scsi/csiostor/csio_lnode.c

1386

csio_get_phy_port_stats(struct csio_hw *hw, uint8_t portid,

drivers/scsi/csiostor/csio_lnode.c

1487

uint8_t portid, opcode = *(uint8_t *)cmd;

drivers/scsi/csiostor/csio_lnode.c

1681

uint32_t immd_len, uint8_t sub_op, uint32_t sid,

drivers/scsi/csiostor/csio_lnode.c

1682

uint32_t did, uint32_t flow_id, uint8_t *fw_wr)

drivers/scsi/csiostor/csio_lnode.c

1701

wr->tmo_val = (uint8_t) io_req->tmo;

drivers/scsi/csiostor/csio_lnode.c

1725

uint8_t sub_op, struct csio_dma_buf *pld,

drivers/scsi/csiostor/csio_lnode.c

1732

uint8_t fw_wr[64];

drivers/scsi/csiostor/csio_lnode.c

1735

uint8_t im_len = 0;

drivers/scsi/csiostor/csio_lnode.c

1746

im_len = (uint8_t)pld_len;

drivers/scsi/csiostor/csio_lnode.c

178

csio_lnode_lookup_by_wwpn(struct csio_hw *hw, uint8_t *wwpn)

drivers/scsi/csiostor/csio_lnode.c

1965

csio_disable_lnodes(struct csio_hw *hw, uint8_t portid, bool disable)

drivers/scsi/csiostor/csio_lnode.c

211

csio_fill_ct_iu(void *buf, uint8_t type, uint8_t sub_type, uint16_t op)

drivers/scsi/csiostor/csio_lnode.c

221

csio_hostname(uint8_t *buf, size_t buf_len)

drivers/scsi/csiostor/csio_lnode.c

229

csio_osname(uint8_t *buf, size_t buf_len)

drivers/scsi/csiostor/csio_lnode.c

241

csio_append_attrib(uint8_t **ptr, uint16_t type, void *val, size_t val_len)

drivers/scsi/csiostor/csio_lnode.c

294

uint8_t *pld;

drivers/scsi/csiostor/csio_lnode.c

302

uint8_t buf[64];

drivers/scsi/csiostor/csio_lnode.c

303

uint8_t *fc4_type;

drivers/scsi/csiostor/csio_lnode.c

328

pld = (uint8_t *)csio_ct_get_pld(cmd);

drivers/scsi/csiostor/csio_lnode.c

386

len = (uint32_t)(pld - (uint8_t *)cmd);

drivers/scsi/csiostor/csio_lnode.c

407

uint8_t *pld;

drivers/scsi/csiostor/csio_lnode.c

415

uint8_t buf[64];

drivers/scsi/csiostor/csio_lnode.c

440

pld = (uint8_t *)csio_ct_get_pld(cmd);

drivers/scsi/csiostor/csio_lnode.c

491

len = (uint32_t)(pld - (uint8_t *)cmd);

drivers/scsi/csiostor/csio_lnode.c

55

#define PORT_ID_PTR(_x) ((uint8_t *)(&_x) + 1)

drivers/scsi/csiostor/csio_lnode.c

634

memcpy(&nport_id, &rsp->vnport_mac[3], sizeof(uint8_t)*3);

drivers/scsi/csiostor/csio_lnode.c

723

uint8_t portid;

drivers/scsi/csiostor/csio_lnode.c

724

uint8_t sub_op;

drivers/scsi/csiostor/csio_lnode.c

873

csio_handle_link_up(struct csio_hw *hw, uint8_t portid, uint32_t fcfi,

drivers/scsi/csiostor/csio_lnode.h

126

uint8_t wwpn[8]; /* WWPN */

drivers/scsi/csiostor/csio_lnode.h

127

uint8_t wwnn[8]; /* WWNN */

drivers/scsi/csiostor/csio_lnode.h

129

uint8_t vvl[16]; /* Vendor version level */

drivers/scsi/csiostor/csio_lnode.h

138

uint8_t portid; /* Port ID */

drivers/scsi/csiostor/csio_lnode.h

139

uint8_t rsvd1;

drivers/scsi/csiostor/csio_lnode.h

148

uint8_t mac[6];

drivers/scsi/csiostor/csio_lnode.h

156

uint8_t cur_evt; /* Current event */

drivers/scsi/csiostor/csio_lnode.h

157

uint8_t prev_evt; /* Previous event */

drivers/scsi/csiostor/csio_lnode.h

226

struct csio_lnode *csio_lnode_lookup_by_wwpn(struct csio_hw *, uint8_t *);

drivers/scsi/csiostor/csio_lnode.h

227

int csio_get_phy_port_stats(struct csio_hw *, uint8_t ,

drivers/scsi/csiostor/csio_lnode.h

232

void csio_disable_lnodes(struct csio_hw *, uint8_t, bool);

drivers/scsi/csiostor/csio_lnode.h

58

uint8_t priority;

drivers/scsi/csiostor/csio_lnode.h

59

uint8_t mac[6];

drivers/scsi/csiostor/csio_lnode.h

60

uint8_t name_id[8];

drivers/scsi/csiostor/csio_lnode.h

61

uint8_t fabric[8];

drivers/scsi/csiostor/csio_lnode.h

63

uint8_t vlan_id;

drivers/scsi/csiostor/csio_lnode.h

65

uint8_t fc_map[3];

drivers/scsi/csiostor/csio_lnode.h

68

uint8_t get_next:1;

drivers/scsi/csiostor/csio_lnode.h

69

uint8_t link_aff:1;

drivers/scsi/csiostor/csio_lnode.h

70

uint8_t fpma:1;

drivers/scsi/csiostor/csio_lnode.h

71

uint8_t spma:1;

drivers/scsi/csiostor/csio_lnode.h

72

uint8_t login:1;

drivers/scsi/csiostor/csio_lnode.h

73

uint8_t portid;

drivers/scsi/csiostor/csio_lnode.h

74

uint8_t spma_mac[6];

drivers/scsi/csiostor/csio_mb.c

1059

uint8_t *src;

drivers/scsi/csiostor/csio_mb.c

1060

uint8_t *dst;

drivers/scsi/csiostor/csio_mb.c

1067

dst = (uint8_t *)(&stats) + ((portparams->idx - 1) * 8);

drivers/scsi/csiostor/csio_mb.c

1068

src = (uint8_t *)rsp + (CSIO_STATS_OFFSET * 8);

drivers/scsi/csiostor/csio_mb.c

110

uint8_t *mpfn)

drivers/scsi/csiostor/csio_mb.c

1212

*((uint8_t *)mbp->mb));

drivers/scsi/csiostor/csio_mb.c

1221

hw->pfn, *((uint8_t *)mbp->mb));

drivers/scsi/csiostor/csio_mb.c

1250

hw->pfn, *((uint8_t *)mbp->mb), owner);

drivers/scsi/csiostor/csio_mb.c

1257

hw->pfn, *((uint8_t *)mbp->mb),

drivers/scsi/csiostor/csio_mb.c

1338

hw->pfn, *((uint8_t *)cmd));

drivers/scsi/csiostor/csio_mb.c

1376

csio_mb_portmod_changed(struct csio_hw *hw, uint8_t port_id)

drivers/scsi/csiostor/csio_mb.c

1407

uint8_t opcode = *(uint8_t *)cmd;

drivers/scsi/csiostor/csio_mb.c

1409

uint8_t port_id;

drivers/scsi/csiostor/csio_mb.c

1412

uint8_t mod_type;

drivers/scsi/csiostor/csio_mb.c

282

ldst_cmd->u.pcie.r = (uint8_t)reg;

drivers/scsi/csiostor/csio_mb.c

839

uint32_t mb_tmo, uint8_t port_id, uint32_t sub_opcode,

drivers/scsi/csiostor/csio_mb.c

840

uint8_t cos, bool link_status, uint32_t fcfi,

drivers/scsi/csiostor/csio_mb.c

909

uint8_t vnport_wwnn[8], uint8_t vnport_wwpn[8],

drivers/scsi/csiostor/csio_mb.h

159

uint8_t *);

drivers/scsi/csiostor/csio_mb.h

182

uint8_t, bool, uint32_t, uint16_t,

drivers/scsi/csiostor/csio_mb.h

219

uint32_t, uint8_t, uint32_t, uint8_t, bool, uint32_t,

drivers/scsi/csiostor/csio_mb.h

224

uint8_t [8], uint8_t [8],

drivers/scsi/csiostor/csio_mb.h

49

uint8_t portid;

drivers/scsi/csiostor/csio_mb.h

50

uint8_t idx;

drivers/scsi/csiostor/csio_mb.h

51

uint8_t nstats;

drivers/scsi/csiostor/csio_rnode.c

101

csio_is_rnode_wka(uint8_t rport_type)

drivers/scsi/csiostor/csio_rnode.c

145

csio_rn_lookup_wwpn(struct csio_lnode *ln, uint8_t *wwpn)

drivers/scsi/csiostor/csio_rnode.c

303

uint8_t rport_type;

drivers/scsi/csiostor/csio_rnode.c

447

uint8_t null[8];

drivers/scsi/csiostor/csio_rnode.c

448

uint8_t rport_type;

drivers/scsi/csiostor/csio_rnode.c

449

uint8_t fc_class;

drivers/scsi/csiostor/csio_rnode.c

868

csio_rnode_fwevt_handler(struct csio_rnode *rn, uint8_t fwevt)

drivers/scsi/csiostor/csio_rnode.h

103

uint8_t cur_evt; /* Current event */

drivers/scsi/csiostor/csio_rnode.h

104

uint8_t prev_evt; /* Previous event */

drivers/scsi/csiostor/csio_rnode.h

132

void csio_rnode_fwevt_handler(struct csio_rnode *rn, uint8_t fwevt);

drivers/scsi/csiostor/csio_scsi.c

1103

struct csio_fl_dma_buf *flb, void *priv, uint8_t **scsiwr)

drivers/scsi/csiostor/csio_scsi.c

1107

uint8_t *tempwr;

drivers/scsi/csiostor/csio_scsi.c

1108

uint8_t status;

drivers/scsi/csiostor/csio_scsi.c

1121

tempwr = (uint8_t *)(cpl->data);

drivers/scsi/csiostor/csio_scsi.c

1569

uint8_t flags, scsi_status = 0;

drivers/scsi/csiostor/csio_scsi.c

1744

uint8_t scsi_status = SAM_STAT_GOOD;

drivers/scsi/csiostor/csio_scsi.c

2021

uint8_t flags = 0;

drivers/scsi/csiostor/csio_scsi.c

207

uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len;

drivers/scsi/csiostor/csio_scsi.c

217

wr->tmo_val = (uint8_t) req->tmo;

drivers/scsi/csiostor/csio_scsi.c

270

uint8_t *tmpwr = csio_q_eq_wrap(hw, req->eq_idx);

drivers/scsi/csiostor/csio_scsi.c

367

uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len;

drivers/scsi/csiostor/csio_scsi.c

376

wr->tmo_val = (uint8_t)(req->tmo);

drivers/scsi/csiostor/csio_scsi.c

420

uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len;

drivers/scsi/csiostor/csio_scsi.c

429

wr->tmo_val = (uint8_t)(req->tmo);

drivers/scsi/csiostor/csio_scsi.c

495

uint8_t *tmpwr = csio_q_eq_wrap(hw, req->eq_idx);

drivers/scsi/csiostor/csio_scsi.c

532

uint8_t *tmpwr = csio_q_eq_wrap(hw, req->eq_idx);

drivers/scsi/csiostor/csio_scsi.c

660

wr->tmo_val = (uint8_t) req->tmo;

drivers/scsi/csiostor/csio_scsi.c

688

uint8_t *tmpwr = csio_q_eq_wrap(hw, req->eq_idx);

drivers/scsi/csiostor/csio_scsi.h

149

uint8_t max_sge; /* Max SGE */

drivers/scsi/csiostor/csio_scsi.h

150

uint8_t proto_cmd_len; /* Proto specific SCSI

drivers/scsi/csiostor/csio_scsi.h

192

uint8_t fc_tm_flags; /* task management flags */

drivers/scsi/csiostor/csio_scsi.h

347

void *, uint8_t **);

drivers/scsi/csiostor/csio_wr.c

416

uint32_t vec, uint8_t portid, bool async,

drivers/scsi/csiostor/csio_wr.c

465

iqp.iqintcntthresh = (uint8_t)csio_sge_thresh_reg;

drivers/scsi/csiostor/csio_wr.c

557

int iq_idx, uint8_t portid,

drivers/scsi/csiostor/csio_wr.c

959

memcpy((uint8_t *) wrp->addr1 + wr_off, data_buf, nbytes);

drivers/scsi/csiostor/csio_wr.c

966

memcpy(wrp->addr2, (uint8_t *) data_buf + nbytes, data_len);

drivers/scsi/csiostor/csio_wr.h

114

uint8_t iq_start:1;

drivers/scsi/csiostor/csio_wr.h

115

uint8_t iq_stop:1;

drivers/scsi/csiostor/csio_wr.h

116

uint8_t pfn:3;

drivers/scsi/csiostor/csio_wr.h

118

uint8_t vfn;

drivers/scsi/csiostor/csio_wr.h

126

uint8_t viid;

drivers/scsi/csiostor/csio_wr.h

128

uint8_t type;

drivers/scsi/csiostor/csio_wr.h

129

uint8_t iqasynch;

drivers/scsi/csiostor/csio_wr.h

130

uint8_t reserved4;

drivers/scsi/csiostor/csio_wr.h

132

uint8_t iqandst;

drivers/scsi/csiostor/csio_wr.h

133

uint8_t iqanus;

drivers/scsi/csiostor/csio_wr.h

134

uint8_t iqanud;

drivers/scsi/csiostor/csio_wr.h

138

uint8_t iqdroprss;

drivers/scsi/csiostor/csio_wr.h

139

uint8_t iqpciech;

drivers/scsi/csiostor/csio_wr.h

140

uint8_t iqdcaen;

drivers/scsi/csiostor/csio_wr.h

142

uint8_t iqdcacpu;

drivers/scsi/csiostor/csio_wr.h

143

uint8_t iqintcntthresh;

drivers/scsi/csiostor/csio_wr.h

144

uint8_t iqo;

drivers/scsi/csiostor/csio_wr.h

146

uint8_t iqcprio;

drivers/scsi/csiostor/csio_wr.h

147

uint8_t iqesize;

drivers/scsi/csiostor/csio_wr.h

153

uint8_t iqflintiqhsen;

drivers/scsi/csiostor/csio_wr.h

154

uint8_t reserved5;

drivers/scsi/csiostor/csio_wr.h

155

uint8_t iqflintcongen;

drivers/scsi/csiostor/csio_wr.h

156

uint8_t iqflintcngchmap;

drivers/scsi/csiostor/csio_wr.h

160

uint8_t fl0hostfcmode;

drivers/scsi/csiostor/csio_wr.h

161

uint8_t fl0cprio;

drivers/scsi/csiostor/csio_wr.h

162

uint8_t fl0paden;

drivers/scsi/csiostor/csio_wr.h

163

uint8_t fl0packen;

drivers/scsi/csiostor/csio_wr.h

164

uint8_t fl0congen;

drivers/scsi/csiostor/csio_wr.h

165

uint8_t fl0dcaen;

drivers/scsi/csiostor/csio_wr.h

167

uint8_t fl0dcacpu;

drivers/scsi/csiostor/csio_wr.h

168

uint8_t fl0fbmin;

drivers/scsi/csiostor/csio_wr.h

170

uint8_t fl0fbmax;

drivers/scsi/csiostor/csio_wr.h

171

uint8_t fl0cidxfthresho;

drivers/scsi/csiostor/csio_wr.h

172

uint8_t fl0cidxfthresh;

drivers/scsi/csiostor/csio_wr.h

180

uint8_t fl1hostfcmode;

drivers/scsi/csiostor/csio_wr.h

181

uint8_t fl1cprio;

drivers/scsi/csiostor/csio_wr.h

182

uint8_t fl1paden;

drivers/scsi/csiostor/csio_wr.h

183

uint8_t fl1packen;

drivers/scsi/csiostor/csio_wr.h

184

uint8_t fl1congen;

drivers/scsi/csiostor/csio_wr.h

185

uint8_t fl1dcaen;

drivers/scsi/csiostor/csio_wr.h

187

uint8_t fl1dcacpu;

drivers/scsi/csiostor/csio_wr.h

188

uint8_t fl1fbmin;

drivers/scsi/csiostor/csio_wr.h

190

uint8_t fl1fbmax;

drivers/scsi/csiostor/csio_wr.h

191

uint8_t fl1cidxfthresho;

drivers/scsi/csiostor/csio_wr.h

192

uint8_t fl1cidxfthresh;

drivers/scsi/csiostor/csio_wr.h

202

uint8_t pfn;

drivers/scsi/csiostor/csio_wr.h

203

uint8_t vfn;

drivers/scsi/csiostor/csio_wr.h

205

uint8_t eqstart:1;

drivers/scsi/csiostor/csio_wr.h

206

uint8_t eqstop:1;

drivers/scsi/csiostor/csio_wr.h

211

uint8_t hostfcmode:2;

drivers/scsi/csiostor/csio_wr.h

212

uint8_t cprio:1;

drivers/scsi/csiostor/csio_wr.h

213

uint8_t pciechn:3;

drivers/scsi/csiostor/csio_wr.h

217

uint8_t dcaen:1;

drivers/scsi/csiostor/csio_wr.h

218

uint8_t dcacpu:5;

drivers/scsi/csiostor/csio_wr.h

220

uint8_t fbmin:3;

drivers/scsi/csiostor/csio_wr.h

221

uint8_t fbmax:3;

drivers/scsi/csiostor/csio_wr.h

223

uint8_t cidxfthresho:1;

drivers/scsi/csiostor/csio_wr.h

224

uint8_t cidxfthresh:3;

drivers/scsi/csiostor/csio_wr.h

264

uint8_t dcopy; /* Data copy required */

drivers/scsi/csiostor/csio_wr.h

265

uint8_t reserved1;

drivers/scsi/csiostor/csio_wr.h

344

uint8_t defer_free; /* Free of buffer can

drivers/scsi/csiostor/csio_wr.h

366

uint8_t wrap[512]; /* Temp area for q-wrap around*/

drivers/scsi/csiostor/csio_wr.h

434

uint8_t counter_val[CSIO_SGE_NCOUNTERS];

drivers/scsi/csiostor/csio_wr.h

486

uint32_t, uint8_t, bool,

drivers/scsi/csiostor/csio_wr.h

488

int csio_wr_eq_create(struct csio_hw *, void *, int, int, uint8_t,

drivers/scsi/elx/efct/efct_lio.c

549

rsp.sense_data = (uint8_t *)io->tgt_io.sense_buffer;

drivers/scsi/elx/libefc/efc_domain.c

275

if (efc_cmd_nport_alloc(efc, nport, NULL, (uint8_t *)&bewwpn)) {

drivers/scsi/elx/libefc/efc_domain.c

827

((uint8_t *)domain->flogi_service_params) + 4,

drivers/scsi/elx/libefc/efc_nport.c

368

(uint8_t *)&be_wwpn)) {

drivers/scsi/fnic/fdls_disc.c

100

uint8_t *fdls_alloc_frame(struct fnic_iport_s *iport)

drivers/scsi/fnic/fdls_disc.c

1002

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1008

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

103

uint8_t *frame = NULL;

drivers/scsi/fnic/fdls_disc.c

1061

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1067

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

1116

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1122

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

1175

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1177

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

1178

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

1297

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1303

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

1365

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1371

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

1425

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1431

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

1484

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1490

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

1491

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

1557

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1560

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

1614

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1617

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

1836

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1839

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

1981

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

1984

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

2514

uint8_t *fcid;

drivers/scsi/fnic/fdls_disc.c

2604

uint8_t *fcid;

drivers/scsi/fnic/fdls_disc.c

2728

uint8_t *fcid;

drivers/scsi/fnic/fdls_disc.c

2880

uint8_t reason_code;

drivers/scsi/fnic/fdls_disc.c

2952

uint8_t reason_code;

drivers/scsi/fnic/fdls_disc.c

3027

uint8_t reason_code;

drivers/scsi/fnic/fdls_disc.c

3178

(struct fc_gpn_ft_rsp_iu *)((uint8_t *) fchdr +

drivers/scsi/fnic/fdls_disc.c

3267

uint8_t reason_code;

drivers/scsi/fnic/fdls_disc.c

3455

uint8_t *fcid;

drivers/scsi/fnic/fdls_disc.c

3457

uint8_t fcmac[6] = { 0x0E, 0XFC, 0x00, 0x00, 0x00, 0x00 };

drivers/scsi/fnic/fdls_disc.c

3980

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

4035

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

4090

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

4138

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

4141

uint8_t *fc_payload;

drivers/scsi/fnic/fdls_disc.c

4142

uint8_t type;

drivers/scsi/fnic/fdls_disc.c

4146

fc_payload = (uint8_t *) fchdr + sizeof(struct fc_frame_header);

drivers/scsi/fnic/fdls_disc.c

4345

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

4479

uint8_t fcid[3];

drivers/scsi/fnic/fdls_disc.c

459

void fdls_init_plogi_frame(uint8_t *frame,

drivers/scsi/fnic/fdls_disc.c

463

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

4636

uint8_t *fcid;

drivers/scsi/fnic/fdls_disc.c

4637

uint8_t *rjt_frame;

drivers/scsi/fnic/fdls_disc.c

4638

uint8_t *acc_frame;

drivers/scsi/fnic/fdls_disc.c

4739

uint8_t type;

drivers/scsi/fnic/fdls_disc.c

4740

uint8_t *fc_payload;

drivers/scsi/fnic/fdls_disc.c

4749

fc_payload = (uint8_t *) fchdr + sizeof(struct fc_frame_header);

drivers/scsi/fnic/fdls_disc.c

494

static void fdls_init_els_acc_frame(uint8_t *frame,

drivers/scsi/fnic/fdls_disc.c

4953

fchdr = (struct fc_frame_header *) ((uint8_t *) rx_frame + fchdr_offset);

drivers/scsi/fnic/fdls_disc.c

498

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

512

static void fdls_init_els_rjt_frame(uint8_t *frame,

drivers/scsi/fnic/fdls_disc.c

527

static void fdls_init_logo_frame(uint8_t *frame,

drivers/scsi/fnic/fdls_disc.c

531

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

548

static void fdls_init_fabric_abts_frame(uint8_t *frame,

drivers/scsi/fnic/fdls_disc.c

569

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

602

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

635

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

636

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

637

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

679

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

680

uint8_t s_id[3];

drivers/scsi/fnic/fdls_disc.c

681

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

766

static uint8_t *fdls_alloc_init_fdmi_abts_frame(struct fnic_iport_s *iport,

drivers/scsi/fnic/fdls_disc.c

770

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

771

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

793

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

850

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

910

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

93

static void fdls_init_plogi_frame(uint8_t *frame, struct fnic_iport_s *iport);

drivers/scsi/fnic/fdls_disc.c

94

static void fdls_init_els_acc_frame(uint8_t *frame, struct fnic_iport_s *iport);

drivers/scsi/fnic/fdls_disc.c

95

static void fdls_init_els_rjt_frame(uint8_t *frame, struct fnic_iport_s *iport);

drivers/scsi/fnic/fdls_disc.c

954

uint8_t *frame;

drivers/scsi/fnic/fdls_disc.c

96

static void fdls_init_logo_frame(uint8_t *frame, struct fnic_iport_s *iport);

drivers/scsi/fnic/fdls_disc.c

960

uint8_t d_id[3];

drivers/scsi/fnic/fdls_disc.c

97

static void fdls_init_fabric_abts_frame(uint8_t *frame,

drivers/scsi/fnic/fdls_fc.h

224

uint8_t ctrl;

drivers/scsi/fnic/fdls_fc.h

225

uint8_t fcid[3];

drivers/scsi/fnic/fip.c

190

uint8_t *frame;

drivers/scsi/fnic/fip.c

356

uint8_t *frame;

drivers/scsi/fnic/fip.c

40

uint8_t *frame;

drivers/scsi/fnic/fip.c

792

uint8_t *frame;

drivers/scsi/fnic/fip.c

845

uint8_t *frame;

drivers/scsi/fnic/fip.c

851

uint8_t fcid[3];

drivers/scsi/fnic/fip.h

149

fnic_debug_dump(fnic, (uint8_t *)eth, len);

drivers/scsi/fnic/fnic.h

595

fnic_debug_dump(struct fnic *fnic, uint8_t *u8arr, int len)

drivers/scsi/fnic/fnic.h

620

fnic_debug_dump(fnic, (uint8_t *)fchdr, len);

drivers/scsi/fnic/fnic.h

625

fnic_debug_dump(struct fnic *fnic, uint8_t *u8arr, int len) {}

drivers/scsi/fnic/fnic_fcs.c

120

uint8_t *fcid)

drivers/scsi/fnic/fnic_fcs.c

124

uint8_t fcmac[6] = { 0x0E, 0xFC, 0x00, 0x00, 0x00, 0x00 };

drivers/scsi/fnic/fnic_fcs.c

32

static uint8_t FCOE_ALL_FCF_MAC[6] = FC_FCOE_FLOGI_MAC;

drivers/scsi/fnic/fnic_fcs.c

40

uint8_t *src_mac)

drivers/scsi/fnic/fnic_fcs.c

427

uint8_t *fp;

drivers/scsi/fnic/fnic_fcs.c

451

fp = (uint8_t *) buf->os_buf;

drivers/scsi/fnic/fnic_fcs.c

55

uint8_t *dst_mac)

drivers/scsi/fnic/fnic_fcs.c

683

uint8_t *srcmac, uint8_t *dstmac)

drivers/scsi/fnic/fnic_fcs.c

735

uint8_t *dstmac, *srcmac;

drivers/scsi/fnic/fnic_fdls.h

125

uint8_t fcf_mac[6];

drivers/scsi/fnic/fnic_fdls.h

126

uint8_t fcf_priority;

drivers/scsi/fnic/fnic_fdls.h

128

uint8_t ka_disabled;

drivers/scsi/fnic/fnic_fdls.h

268

uint8_t hwmac[6]; /* HW MAC Addr */

drivers/scsi/fnic/fnic_fdls.h

269

uint8_t fpma[6]; /* Fabric Provided MA */

drivers/scsi/fnic/fnic_fdls.h

270

uint8_t fcfmac[6]; /* MAC addr of Fabric */

drivers/scsi/fnic/fnic_fdls.h

379

uint8_t *fdls_alloc_frame(struct fnic_iport_s *iport);

drivers/scsi/fnic/fnic_fdls.h

407

uint8_t *fcid);

drivers/scsi/ips.c

2218

uint8_t major;

drivers/scsi/ips.c

2219

uint8_t minor;

drivers/scsi/ips.c

2220

uint8_t subminor;

drivers/scsi/ips.c

2221

uint8_t *buffer;

drivers/scsi/ips.c

3820

uint8_t basic_status;

drivers/scsi/ips.c

3821

uint8_t ext_status;

drivers/scsi/ips.c

4456

uint8_t scpr;

drivers/scsi/ips.c

4457

uint8_t isr;

drivers/scsi/ips.c

4482

uint8_t isr = 0;

drivers/scsi/ips.c

4483

uint8_t scpr;

drivers/scsi/ips.c

4683

uint8_t Isr;

drivers/scsi/ips.c

4684

uint8_t Cbsp;

drivers/scsi/ips.c

4685

uint8_t PostByte[IPS_MAX_POST_BYTES];

drivers/scsi/ips.c

4776

uint8_t Isr = 0;

drivers/scsi/ips.c

4777

uint8_t Cbsp;

drivers/scsi/ips.c

4778

uint8_t PostByte[IPS_MAX_POST_BYTES];

drivers/scsi/ips.c

5078

uint8_t junk;

drivers/scsi/ips.c

5429

uint8_t Isr;

drivers/scsi/ips.c

5462

uint8_t Isr;

drivers/scsi/ips.c

6000

uint8_t status = 0;

drivers/scsi/ips.c

6112

uint8_t status;

drivers/scsi/ips.c

6226

uint8_t status = 0;

drivers/scsi/ips.c

6317

uint8_t status = 0;

drivers/scsi/ips.c

6406

uint8_t checksum;

drivers/scsi/ips.c

6432

checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);

drivers/scsi/ips.c

6455

uint8_t checksum;

drivers/scsi/ips.c

6482

(uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);

drivers/scsi/ips.h

1007

uint8_t ha_id[IPS_MAX_CHANNELS+1];

drivers/scsi/ips.h

1010

uint8_t ntargets; /* Number of targets */

drivers/scsi/ips.h

1011

uint8_t nbus; /* Number of buses */

drivers/scsi/ips.h

1012

uint8_t nlun; /* Number of Luns */

drivers/scsi/ips.h

1036

uint8_t waitflag; /* are we waiting for cmd */

drivers/scsi/ips.h

1037

uint8_t active;

drivers/scsi/ips.h

1041

uint8_t slot_num; /* PCI Slot Number */

drivers/scsi/ips.h

1044

uint8_t bios_version[8]; /* BIOS Revision */

drivers/scsi/ips.h

1057

uint8_t requires_esl; /* Requires an EraseStripeLock */

drivers/scsi/ips.h

1068

uint8_t target_id;

drivers/scsi/ips.h

1069

uint8_t bus;

drivers/scsi/ips.h

1070

uint8_t lun;

drivers/scsi/ips.h

1071

uint8_t cdb[12];

drivers/scsi/ips.h

1075

uint8_t basic_status;

drivers/scsi/ips.h

1076

uint8_t extended_status;

drivers/scsi/ips.h

1077

uint8_t breakup;

drivers/scsi/ips.h

1078

uint8_t sg_break;

drivers/scsi/ips.h

1095

uint8_t target_id;

drivers/scsi/ips.h

1096

uint8_t bus;

drivers/scsi/ips.h

1097

uint8_t lun;

drivers/scsi/ips.h

1098

uint8_t cdb[12];

drivers/scsi/ips.h

1102

uint8_t basic_status;

drivers/scsi/ips.h

1103

uint8_t extended_status;

drivers/scsi/ips.h

1119

uint8_t CoppID[4];

drivers/scsi/ips.h

1122

uint8_t *CmdBuffer;

drivers/scsi/ips.h

1126

uint8_t BasicStatus;

drivers/scsi/ips.h

1127

uint8_t ExtendedStatus;

drivers/scsi/ips.h

1128

uint8_t AdapterType;

drivers/scsi/ips.h

1129

uint8_t reserved;

drivers/scsi/ips.h

410

uint8_t op_code;

drivers/scsi/ips.h

411

uint8_t command_id;

drivers/scsi/ips.h

412

uint8_t log_drv;

drivers/scsi/ips.h

413

uint8_t sg_count;

drivers/scsi/ips.h

417

uint8_t segment_4G;

drivers/scsi/ips.h

418

uint8_t enhanced_sg;

drivers/scsi/ips.h

424

uint8_t op_code;

drivers/scsi/ips.h

425

uint8_t command_id;

drivers/scsi/ips.h

435

uint8_t op_code;

drivers/scsi/ips.h

436

uint8_t command_id;

drivers/scsi/ips.h

437

uint8_t reserved;

drivers/scsi/ips.h

438

uint8_t reserved2;

drivers/scsi/ips.h

445

uint8_t op_code;

drivers/scsi/ips.h

446

uint8_t command_id;

drivers/scsi/ips.h

447

uint8_t channel;

drivers/scsi/ips.h

448

uint8_t reserved3;

drivers/scsi/ips.h

449

uint8_t reserved4;

drivers/scsi/ips.h

450

uint8_t reserved5;

drivers/scsi/ips.h

451

uint8_t reserved6;

drivers/scsi/ips.h

452

uint8_t reserved7;

drivers/scsi/ips.h

453

uint8_t reserved8;

drivers/scsi/ips.h

454

uint8_t reserved9;

drivers/scsi/ips.h

455

uint8_t reserved10;

drivers/scsi/ips.h

456

uint8_t reserved11;

drivers/scsi/ips.h

457

uint8_t reserved12;

drivers/scsi/ips.h

458

uint8_t reserved13;

drivers/scsi/ips.h

459

uint8_t reserved14;

drivers/scsi/ips.h

460

uint8_t adapter_flag;

drivers/scsi/ips.h

464

uint8_t op_code;

drivers/scsi/ips.h

465

uint8_t command_id;

drivers/scsi/ips.h

470

uint8_t segment_4G;

drivers/scsi/ips.h

471

uint8_t enhanced_sg;

drivers/scsi/ips.h

477

uint8_t op_code;

drivers/scsi/ips.h

478

uint8_t command_id;

drivers/scsi/ips.h

479

uint8_t channel;

drivers/scsi/ips.h

480

uint8_t source_target;

drivers/scsi/ips.h

489

uint8_t op_code;

drivers/scsi/ips.h

490

uint8_t command_id;

drivers/scsi/ips.h

491

uint8_t log_drv;

drivers/scsi/ips.h

492

uint8_t control;

drivers/scsi/ips.h

501

uint8_t op_code;

drivers/scsi/ips.h

502

uint8_t command_id;

drivers/scsi/ips.h

503

uint8_t reserved;

drivers/scsi/ips.h

504

uint8_t state;

drivers/scsi/ips.h

513

uint8_t op_code;

drivers/scsi/ips.h

514

uint8_t command_id;

drivers/scsi/ips.h

515

uint8_t reserved;

drivers/scsi/ips.h

516

uint8_t desc;

drivers/scsi/ips.h

525

uint8_t op_code;

drivers/scsi/ips.h

526

uint8_t command_id;

drivers/scsi/ips.h

527

uint8_t page;

drivers/scsi/ips.h

528

uint8_t write;

drivers/scsi/ips.h

538

uint8_t op_code;

drivers/scsi/ips.h

539

uint8_t command_id;

drivers/scsi/ips.h

547

uint8_t op_code;

drivers/scsi/ips.h

548

uint8_t command_id;

drivers/scsi/ips.h

549

uint8_t reset_count;

drivers/scsi/ips.h

550

uint8_t reset_type;

drivers/scsi/ips.h

551

uint8_t second;

drivers/scsi/ips.h

552

uint8_t minute;

drivers/scsi/ips.h

553

uint8_t hour;

drivers/scsi/ips.h

554

uint8_t day;

drivers/scsi/ips.h

555

uint8_t reserved1[4];

drivers/scsi/ips.h

556

uint8_t month;

drivers/scsi/ips.h

557

uint8_t yearH;

drivers/scsi/ips.h

558

uint8_t yearL;

drivers/scsi/ips.h

559

uint8_t reserved2;

drivers/scsi/ips.h

563

uint8_t op_code;

drivers/scsi/ips.h

564

uint8_t command_id;

drivers/scsi/ips.h

565

uint8_t type;

drivers/scsi/ips.h

566

uint8_t direction;

drivers/scsi/ips.h

569

uint8_t total_packets;

drivers/scsi/ips.h

570

uint8_t packet_num;

drivers/scsi/ips.h

575

uint8_t op_code;

drivers/scsi/ips.h

576

uint8_t command_id;

drivers/scsi/ips.h

577

uint8_t type;

drivers/scsi/ips.h

578

uint8_t direction;

drivers/scsi/ips.h

602

uint8_t logical_id;

drivers/scsi/ips.h

603

uint8_t reserved;

drivers/scsi/ips.h

604

uint8_t raid_level;

drivers/scsi/ips.h

605

uint8_t state;

drivers/scsi/ips.h

610

uint8_t no_of_log_drive;

drivers/scsi/ips.h

611

uint8_t reserved[3];

drivers/scsi/ips.h

616

uint8_t device_address;

drivers/scsi/ips.h

617

uint8_t cmd_attribute;

drivers/scsi/ips.h

620

uint8_t cdb_length;

drivers/scsi/ips.h

621

uint8_t sense_length;

drivers/scsi/ips.h

622

uint8_t sg_count;

drivers/scsi/ips.h

623

uint8_t reserved;

drivers/scsi/ips.h

624

uint8_t scsi_cdb[12];

drivers/scsi/ips.h

625

uint8_t sense_info[64];

drivers/scsi/ips.h

626

uint8_t scsi_status;

drivers/scsi/ips.h

627

uint8_t reserved2[3];

drivers/scsi/ips.h

631

uint8_t device_address;

drivers/scsi/ips.h

632

uint8_t cmd_attribute;

drivers/scsi/ips.h

633

uint8_t cdb_length;

drivers/scsi/ips.h

634

uint8_t reserved_for_LUN;

drivers/scsi/ips.h

638

uint8_t sense_length;

drivers/scsi/ips.h

639

uint8_t scsi_status;

drivers/scsi/ips.h

641

uint8_t scsi_cdb[16];

drivers/scsi/ips.h

642

uint8_t sense_info[56];

drivers/scsi/ips.h

647

volatile uint8_t reserved;

drivers/scsi/ips.h

648

volatile uint8_t command_id;

drivers/scsi/ips.h

649

volatile uint8_t basic_status;

drivers/scsi/ips.h

650

volatile uint8_t extended_status;

drivers/scsi/ips.h

666

uint8_t ucLogDriveCount;

drivers/scsi/ips.h

667

uint8_t ucMiscFlag;

drivers/scsi/ips.h

668

uint8_t ucSLTFlag;

drivers/scsi/ips.h

669

uint8_t ucBSTFlag;

drivers/scsi/ips.h

670

uint8_t ucPwrChgCnt;

drivers/scsi/ips.h

671

uint8_t ucWrongAdrCnt;

drivers/scsi/ips.h

672

uint8_t ucUnidentCnt;

drivers/scsi/ips.h

673

uint8_t ucNVramDevChgCnt;

drivers/scsi/ips.h

674

uint8_t CodeBlkVersion[8];

drivers/scsi/ips.h

675

uint8_t BootBlkVersion[8];

drivers/scsi/ips.h

677

uint8_t ucConcurrentCmdCount;

drivers/scsi/ips.h

678

uint8_t ucMaxPhysicalDevices;

drivers/scsi/ips.h

680

uint8_t ucDefunctDiskCount;

drivers/scsi/ips.h

681

uint8_t ucRebuildFlag;

drivers/scsi/ips.h

682

uint8_t ucOfflineLogDrvCount;

drivers/scsi/ips.h

683

uint8_t ucCriticalDrvCount;

drivers/scsi/ips.h

685

uint8_t ucBlkFlag;

drivers/scsi/ips.h

686

uint8_t reserved;

drivers/scsi/ips.h

691

uint8_t ucInitiator;

drivers/scsi/ips.h

692

uint8_t ucParameters;

drivers/scsi/ips.h

693

uint8_t ucMiscFlag;

drivers/scsi/ips.h

694

uint8_t ucState;

drivers/scsi/ips.h

696

uint8_t ucDeviceId[28];

drivers/scsi/ips.h

700

uint8_t ucChn;

drivers/scsi/ips.h

701

uint8_t ucTgt;

drivers/scsi/ips.h

709

uint8_t ucState;

drivers/scsi/ips.h

710

uint8_t ucRaidCacheParam;

drivers/scsi/ips.h

711

uint8_t ucNoOfChunkUnits;

drivers/scsi/ips.h

712

uint8_t ucStripeSize;

drivers/scsi/ips.h

713

uint8_t ucParams;

drivers/scsi/ips.h

714

uint8_t ucReserved;

drivers/scsi/ips.h

720

uint8_t board_disc[8];

drivers/scsi/ips.h

721

uint8_t processor[8];

drivers/scsi/ips.h

722

uint8_t ucNoChanType;

drivers/scsi/ips.h

723

uint8_t ucNoHostIntType;

drivers/scsi/ips.h

724

uint8_t ucCompression;

drivers/scsi/ips.h

725

uint8_t ucNvramType;

drivers/scsi/ips.h

730

uint8_t ucLogDriveCount;

drivers/scsi/ips.h

731

uint8_t ucDateD;

drivers/scsi/ips.h

732

uint8_t ucDateM;

drivers/scsi/ips.h

733

uint8_t ucDateY;

drivers/scsi/ips.h

734

uint8_t init_id[4];

drivers/scsi/ips.h

735

uint8_t host_id[12];

drivers/scsi/ips.h

736

uint8_t time_sign[8];

drivers/scsi/ips.h

739

uint8_t ucRebuildRate;

drivers/scsi/ips.h

740

uint8_t ucReserve;

drivers/scsi/ips.h

744

uint8_t reserved[512];

drivers/scsi/ips.h

749

uint8_t reserved1;

drivers/scsi/ips.h

750

uint8_t adapter_slot;

drivers/scsi/ips.h

752

uint8_t ctrl_bios[8];

drivers/scsi/ips.h

753

uint8_t versioning; /* 1 = Versioning Supported, else 0 */

drivers/scsi/ips.h

754

uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */

drivers/scsi/ips.h

755

uint8_t reserved2;

drivers/scsi/ips.h

756

uint8_t operating_system;

drivers/scsi/ips.h

757

uint8_t driver_high[4];

drivers/scsi/ips.h

758

uint8_t driver_low[4];

drivers/scsi/ips.h

759

uint8_t BiosCompatibilityID[8];

drivers/scsi/ips.h

760

uint8_t ReservedForOS2[8];

drivers/scsi/ips.h

761

uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */

drivers/scsi/ips.h

762

uint8_t bios_low[4];

drivers/scsi/ips.h

763

uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */

drivers/scsi/ips.h

764

uint8_t Filler[60];

drivers/scsi/ips.h

777

uint8_t bootBlkVersion[32];

drivers/scsi/ips.h

778

uint8_t bootBlkAttributes[4];

drivers/scsi/ips.h

779

uint8_t codeBlkVersion[32];

drivers/scsi/ips.h

780

uint8_t biosVersion[32];

drivers/scsi/ips.h

781

uint8_t biosAttributes[4];

drivers/scsi/ips.h

782

uint8_t compatibilityId[32];

drivers/scsi/ips.h

783

uint8_t reserved[4];

drivers/scsi/ips.h

799

uint8_t DeviceType;

drivers/scsi/ips.h

800

uint8_t DeviceTypeQualifier;

drivers/scsi/ips.h

801

uint8_t Version;

drivers/scsi/ips.h

802

uint8_t ResponseDataFormat;

drivers/scsi/ips.h

803

uint8_t AdditionalLength;

drivers/scsi/ips.h

804

uint8_t Reserved;

drivers/scsi/ips.h

805

uint8_t Flags[2];

drivers/scsi/ips.h

806

uint8_t VendorId[8];

drivers/scsi/ips.h

807

uint8_t ProductId[16];

drivers/scsi/ips.h

808

uint8_t ProductRevisionLevel[4];

drivers/scsi/ips.h

809

uint8_t Reserved2; /* Provides NULL terminator to name */

drivers/scsi/ips.h

824

uint8_t ResponseCode;

drivers/scsi/ips.h

825

uint8_t SegmentNumber;

drivers/scsi/ips.h

826

uint8_t Flags;

drivers/scsi/ips.h

827

uint8_t Information[4];

drivers/scsi/ips.h

828

uint8_t AdditionalLength;

drivers/scsi/ips.h

829

uint8_t CommandSpecific[4];

drivers/scsi/ips.h

830

uint8_t AdditionalSenseCode;

drivers/scsi/ips.h

831

uint8_t AdditionalSenseCodeQual;

drivers/scsi/ips.h

832

uint8_t FRUCode;

drivers/scsi/ips.h

833

uint8_t SenseKeySpecific[3];

drivers/scsi/ips.h

840

uint8_t PageCode;

drivers/scsi/ips.h

841

uint8_t PageLength;

drivers/scsi/ips.h

851

uint8_t flags;

drivers/scsi/ips.h

852

uint8_t reserved[3];

drivers/scsi/ips.h

859

uint8_t PageCode;

drivers/scsi/ips.h

860

uint8_t PageLength;

drivers/scsi/ips.h

862

uint8_t CylindersLow;

drivers/scsi/ips.h

863

uint8_t Heads;

drivers/scsi/ips.h

865

uint8_t WritePrecompLow;

drivers/scsi/ips.h

867

uint8_t ReducedWriteCurrentLow;

drivers/scsi/ips.h

870

uint8_t LandingZoneLow;

drivers/scsi/ips.h

871

uint8_t flags;

drivers/scsi/ips.h

872

uint8_t RotationalOffset;

drivers/scsi/ips.h

873

uint8_t Reserved;

drivers/scsi/ips.h

875

uint8_t Reserved2[2];

drivers/scsi/ips.h

882

uint8_t PageCode;

drivers/scsi/ips.h

883

uint8_t PageLength;

drivers/scsi/ips.h

884

uint8_t flags;

drivers/scsi/ips.h

885

uint8_t RetentPrio;

drivers/scsi/ips.h

897

uint8_t DensityCode;

drivers/scsi/ips.h

899

uint8_t BlockLengthLow;

drivers/scsi/ips.h

906

uint8_t DataLength;

drivers/scsi/ips.h

907

uint8_t MediumType;

drivers/scsi/ips.h

908

uint8_t Reserved;

drivers/scsi/ips.h

909

uint8_t BlockDescLength;

drivers/scsi/ips.h

956

uint8_t padding[12 - sizeof(void *)];

drivers/scsi/isci/probe_roms.h

212

uint8_t signature[ISCI_ROM_SIG_SIZE];

drivers/scsi/isci/probe_roms.h

214

uint8_t hdr_length;

drivers/scsi/isci/probe_roms.h

215

uint8_t version;

drivers/scsi/isci/probe_roms.h

216

uint8_t preboot_source;

drivers/scsi/isci/probe_roms.h

217

uint8_t num_elements;

drivers/scsi/isci/probe_roms.h

219

uint8_t reserved[8];

drivers/scsi/isci/probe_roms.h

224

uint8_t mode_type;

drivers/scsi/isci/probe_roms.h

225

uint8_t max_concurr_spin_up;

drivers/scsi/isci/probe_roms.h

242

uint8_t ssc_sata_tx_spread_level:4;

drivers/scsi/isci/probe_roms.h

258

uint8_t ssc_sas_tx_spread_level:3;

drivers/scsi/isci/probe_roms.h

268

uint8_t ssc_sas_tx_type:1;

drivers/scsi/isci/probe_roms.h

270

uint8_t do_enable_ssc;

drivers/scsi/isci/probe_roms.h

305

uint8_t cable_selection_mask;

drivers/scsi/isci/probe_roms.h

309

uint8_t phy_mask;

drivers/scsi/iscsi_tcp.c

566

static int iscsi_sw_tcp_pdu_alloc(struct iscsi_task *task, uint8_t opcode)

drivers/scsi/libiscsi.c

658

uint8_t opcode = hdr->opcode & ISCSI_OPCODE_MASK;

drivers/scsi/libiscsi.c

710

uint8_t opcode = hdr->opcode & ISCSI_OPCODE_MASK;

drivers/scsi/lpfc/lpfc.h

1011

uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */

drivers/scsi/lpfc/lpfc.h

1053

uint8_t fc_linkspeed; /* Link speed after last READ_LA */

drivers/scsi/lpfc/lpfc.h

1060

uint8_t fc_pref_ALPA; /* preferred AL_PA */

drivers/scsi/lpfc/lpfc.h

1070

uint8_t alpa_map[128]; /* AL_PA map from READ_LA */

drivers/scsi/lpfc/lpfc.h

1083

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc.h

1084

uint8_t wwpn[8];

drivers/scsi/lpfc/lpfc.h

1086

uint8_t fcp_embed_io;

drivers/scsi/lpfc/lpfc.h

1087

uint8_t nvmet_support; /* driver supports NVMET */

drivers/scsi/lpfc/lpfc.h

1089

uint8_t mds_diags_support;

drivers/scsi/lpfc/lpfc.h

1090

uint8_t bbcredit_support;

drivers/scsi/lpfc/lpfc.h

1091

uint8_t enab_exp_wqcq_pages;

drivers/scsi/lpfc/lpfc.h

1144

uint8_t cfg_oas_tgt_wwpn[8];

drivers/scsi/lpfc/lpfc.h

1145

uint8_t cfg_oas_vpt_wwpn[8];

drivers/scsi/lpfc/lpfc.h

1258

uint8_t vpd_flag; /* VPD data flag */

drivers/scsi/lpfc/lpfc.h

1360

uint8_t lpfc_idiag_last_eq;

drivers/scsi/lpfc/lpfc.h

1369

uint8_t temp_sensor_support;

drivers/scsi/lpfc/lpfc.h

1391

uint8_t fc_map[3];

drivers/scsi/lpfc/lpfc.h

1392

uint8_t valid_vlan;

drivers/scsi/lpfc/lpfc.h

198

uint8_t fcphHigh;

drivers/scsi/lpfc/lpfc.h

199

uint8_t fcphLow;

drivers/scsi/lpfc/lpfc.h

200

uint8_t feaLevelHigh;

drivers/scsi/lpfc/lpfc.h

201

uint8_t feaLevelLow;

drivers/scsi/lpfc/lpfc.h

204

uint8_t opFwName[16];

drivers/scsi/lpfc/lpfc.h

206

uint8_t sli1FwName[16];

drivers/scsi/lpfc/lpfc.h

208

uint8_t sli2FwName[16];

drivers/scsi/lpfc/lpfc.h

435

uint8_t fault;

drivers/scsi/lpfc/lpfc.h

449

uint8_t cgn_param_version; /* version 1 */

drivers/scsi/lpfc/lpfc.h

450

uint8_t cgn_param_mode; /* 0=off 1=managed 2=monitor only */

drivers/scsi/lpfc/lpfc.h

454

uint8_t cgn_rsvd1;

drivers/scsi/lpfc/lpfc.h

455

uint8_t cgn_rsvd2;

drivers/scsi/lpfc/lpfc.h

456

uint8_t cgn_param_level0;

drivers/scsi/lpfc/lpfc.h

457

uint8_t cgn_param_level1;

drivers/scsi/lpfc/lpfc.h

458

uint8_t cgn_param_level2;

drivers/scsi/lpfc/lpfc.h

459

uint8_t byte11;

drivers/scsi/lpfc/lpfc.h

460

uint8_t byte12;

drivers/scsi/lpfc/lpfc.h

461

uint8_t byte13;

drivers/scsi/lpfc/lpfc.h

462

uint8_t byte14;

drivers/scsi/lpfc/lpfc.h

463

uint8_t byte15;

drivers/scsi/lpfc/lpfc.h

470

uint8_t month;

drivers/scsi/lpfc/lpfc.h

471

uint8_t day;

drivers/scsi/lpfc/lpfc.h

472

uint8_t year;

drivers/scsi/lpfc/lpfc.h

473

uint8_t hour;

drivers/scsi/lpfc/lpfc.h

474

uint8_t minute;

drivers/scsi/lpfc/lpfc.h

475

uint8_t second;

drivers/scsi/lpfc/lpfc.h

487

uint8_t cgn_info_version; /* represents format of structure */

drivers/scsi/lpfc/lpfc.h

492

uint8_t cgn_info_mode; /* 0=off 1=managed 2=monitor only */

drivers/scsi/lpfc/lpfc.h

493

uint8_t cgn_info_detect;

drivers/scsi/lpfc/lpfc.h

494

uint8_t cgn_info_action;

drivers/scsi/lpfc/lpfc.h

495

uint8_t cgn_info_level0;

drivers/scsi/lpfc/lpfc.h

496

uint8_t cgn_info_level1;

drivers/scsi/lpfc/lpfc.h

497

uint8_t cgn_info_level2;

drivers/scsi/lpfc/lpfc.h

503

uint8_t cgn_index_minute;

drivers/scsi/lpfc/lpfc.h

504

uint8_t cgn_index_hour;

drivers/scsi/lpfc/lpfc.h

505

uint8_t cgn_index_day;

drivers/scsi/lpfc/lpfc.h

510

uint8_t cgn_pad1[8];

drivers/scsi/lpfc/lpfc.h

538

uint8_t cgn_stat_npm; /* Notifications per minute */

drivers/scsi/lpfc/lpfc.h

542

uint8_t cgn_pad2;

drivers/scsi/lpfc/lpfc.h

616

uint8_t port_type;

drivers/scsi/lpfc/lpfc.h

624

uint8_t vpi_state;

drivers/scsi/lpfc/lpfc.h

659

uint8_t fc_linkspeed; /* Link speed after last READ_LA */

drivers/scsi/lpfc/lpfc.h

671

uint8_t fc_ns_retry; /* retries for fabric nameserver */

drivers/scsi/lpfc/lpfc.h

760

uint8_t nvmei_support; /* driver supports NVME Initiator */

drivers/scsi/lpfc/lpfc.h

869

uint8_t *fwlog_buff;

drivers/scsi/lpfc/lpfc.h

933

uint8_t tmo);

drivers/scsi/lpfc/lpfc_attr.c

1092

uint8_t sli_family;

drivers/scsi/lpfc/lpfc_attr.c

2062

(uint8_t)rdp_context->page_a0[SSF_VENDOR_OUI],

drivers/scsi/lpfc/lpfc_attr.c

2063

(uint8_t)rdp_context->page_a0[SSF_VENDOR_OUI + 1],

drivers/scsi/lpfc/lpfc_attr.c

2064

(uint8_t)rdp_context->page_a0[SSF_VENDOR_OUI + 2]);

drivers/scsi/lpfc/lpfc_attr.c

2074

(uint8_t)rdp_context->page_a0[SSF_IDENTIFIER]);

drivers/scsi/lpfc/lpfc_attr.c

2076

(uint8_t)rdp_context->page_a0[SSF_EXT_IDENTIFIER]);

drivers/scsi/lpfc/lpfc_attr.c

2078

(uint8_t)rdp_context->page_a0[SSF_CONNECTOR]);

drivers/scsi/lpfc/lpfc_attr.c

2088

if (*(uint8_t *)trasn_code_byte7 == 0) {

drivers/scsi/lpfc/lpfc_attr.c

3234

uint8_t wwpn[WWN_SZ];

drivers/scsi/lpfc/lpfc_attr.c

3248

memcpy(phba->cfg_oas_tgt_wwpn, wwpn, (8 * sizeof(uint8_t)));

drivers/scsi/lpfc/lpfc_attr.c

3249

memcpy(phba->sli4_hba.oas_next_tgt_wwpn, wwpn, (8 * sizeof(uint8_t)));

drivers/scsi/lpfc/lpfc_attr.c

3316

phba->cfg_oas_priority = (uint8_t)val;

drivers/scsi/lpfc/lpfc_attr.c

3365

uint8_t wwpn[WWN_SZ];

drivers/scsi/lpfc/lpfc_attr.c

3379

memcpy(phba->cfg_oas_vpt_wwpn, wwpn, (8 * sizeof(uint8_t)));

drivers/scsi/lpfc/lpfc_attr.c

3380

memcpy(phba->sli4_hba.oas_next_vpt_wwpn, wwpn, (8 * sizeof(uint8_t)));

drivers/scsi/lpfc/lpfc_attr.c

3498

lpfc_oas_lun_state_set(struct lpfc_hba *phba, uint8_t vpt_wwpn[],

drivers/scsi/lpfc/lpfc_attr.c

3499

uint8_t tgt_wwpn[], uint64_t lun,

drivers/scsi/lpfc/lpfc_attr.c

3500

uint32_t oas_state, uint8_t pri)

drivers/scsi/lpfc/lpfc_attr.c

3539

lpfc_oas_lun_get_next(struct lpfc_hba *phba, uint8_t vpt_wwpn[],

drivers/scsi/lpfc/lpfc_attr.c

3540

uint8_t tgt_wwpn[], uint32_t *lun_status,

drivers/scsi/lpfc/lpfc_attr.c

3578

lpfc_oas_lun_state_change(struct lpfc_hba *phba, uint8_t vpt_wwpn[],

drivers/scsi/lpfc/lpfc_attr.c

3579

uint8_t tgt_wwpn[], uint64_t lun,

drivers/scsi/lpfc/lpfc_attr.c

3580

uint32_t oas_state, uint8_t pri)

drivers/scsi/lpfc/lpfc_attr.c

7406

memset(phba->cfg_oas_tgt_wwpn, 0, (8 * sizeof(uint8_t)));

drivers/scsi/lpfc/lpfc_attr.c

7407

memset(phba->cfg_oas_vpt_wwpn, 0, (8 * sizeof(uint8_t)));

drivers/scsi/lpfc/lpfc_bsg.c

2509

(uint8_t *)&phba->pport->fc_sparam,

drivers/scsi/lpfc/lpfc_bsg.c

2519

(uint8_t *)&phba->pport->fc_sparam,

drivers/scsi/lpfc/lpfc_bsg.c

2858

memset((uint8_t *)dmp->dma.virt, 0, cnt);

drivers/scsi/lpfc/lpfc_bsg.c

3057

uint8_t *ptr = NULL, *rx_databuf = NULL;

drivers/scsi/lpfc/lpfc_bsg.c

3392

uint8_t *pmb, *pmb_buf;

drivers/scsi/lpfc/lpfc_bsg.c

3400

pmb = (uint8_t *)&pmboxq->u.mb;

drivers/scsi/lpfc/lpfc_bsg.c

3401

pmb_buf = (uint8_t *)dd_data->context_un.mbox.mb;

drivers/scsi/lpfc/lpfc_bsg.c

3660

uint8_t *pmb, *pmb_buf;

drivers/scsi/lpfc/lpfc_bsg.c

3666

uint8_t *pmbx;

drivers/scsi/lpfc/lpfc_bsg.c

3685

pmb = (uint8_t *)&pmboxq->u.mb;

drivers/scsi/lpfc/lpfc_bsg.c

3686

pmb_buf = (uint8_t *)dd_data->context_un.mbox.mb;

drivers/scsi/lpfc/lpfc_bsg.c

3694

pmbx = (uint8_t *)dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

4112

pmbx = (uint8_t *)dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

4196

uint8_t *mbx;

drivers/scsi/lpfc/lpfc_bsg.c

4292

mbx = (uint8_t *)dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

4507

uint8_t *pbuf;

drivers/scsi/lpfc/lpfc_bsg.c

4541

pbuf = (uint8_t *)dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

4581

uint8_t *pbuf;

drivers/scsi/lpfc/lpfc_bsg.c

4590

pbuf = (uint8_t *)dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

4640

pbuf = (uint8_t *)phba->mbox_ext_buf_ctx.mbx_dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

4830

uint8_t *pmbx = NULL;

drivers/scsi/lpfc/lpfc_bsg.c

4839

uint8_t *ext = NULL;

drivers/scsi/lpfc/lpfc_bsg.c

4841

uint8_t *from;

drivers/scsi/lpfc/lpfc_bsg.c

4879

pmbx = (uint8_t *)dmabuf->virt;

drivers/scsi/lpfc/lpfc_bsg.c

5310

uint8_t action = 0, log_level = 0;

drivers/scsi/lpfc/lpfc_bsg.c

5611

uint8_t *cgn_buff;

drivers/scsi/lpfc/lpfc_bsg.c

573

uint8_t *rjt_data;

drivers/scsi/lpfc/lpfc_bsg.c

620

rjt_data = (uint8_t *)&ulp_word4;

drivers/scsi/lpfc/lpfc_bsg.c

85

uint8_t *ext; /* extended mailbox data */

drivers/scsi/lpfc/lpfc_bsg.h

321

uint8_t supported;

drivers/scsi/lpfc/lpfc_bsg.h

341

uint8_t action;

drivers/scsi/lpfc/lpfc_bsg.h

344

uint8_t log_level;

drivers/scsi/lpfc/lpfc_bsg.h

348

uint8_t state;

drivers/scsi/lpfc/lpfc_bsg.h

351

uint8_t log_level;

drivers/scsi/lpfc/lpfc_crtn.h

166

int lpfc_issue_els_plogi(struct lpfc_vport *, uint32_t, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

167

int lpfc_issue_els_prli(struct lpfc_vport *, struct lpfc_nodelist *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

168

int lpfc_issue_els_adisc(struct lpfc_vport *, struct lpfc_nodelist *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

169

int lpfc_issue_els_logo(struct lpfc_vport *, struct lpfc_nodelist *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

171

int lpfc_issue_els_scr(struct lpfc_vport *vport, uint8_t retry);

drivers/scsi/lpfc/lpfc_crtn.h

172

int lpfc_issue_els_rscn(struct lpfc_vport *vport, uint8_t retry);

drivers/scsi/lpfc/lpfc_crtn.h

174

int lpfc_issue_els_rdf(struct lpfc_vport *vport, uint8_t retry);

drivers/scsi/lpfc/lpfc_crtn.h

175

int lpfc_issue_els_edc(struct lpfc_vport *vport, uint8_t retry);

drivers/scsi/lpfc/lpfc_crtn.h

201

struct lpfc_iocbq *lpfc_prep_els_iocb(struct lpfc_vport *, uint8_t, uint16_t,

drivers/scsi/lpfc/lpfc_crtn.h

202

uint8_t, struct lpfc_nodelist *,

drivers/scsi/lpfc/lpfc_crtn.h

213

int lpfc_ns_cmd(struct lpfc_vport *, int, uint8_t, uint32_t);

drivers/scsi/lpfc/lpfc_crtn.h

280

int lpfc_check_pending_fcoe_event(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

451

int lpfc_init_api_table_setup(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

452

int lpfc_sli_api_table_setup(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

453

int lpfc_scsi_api_table_setup(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

454

int lpfc_mbox_api_table_setup(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

455

int lpfc_api_table_setup(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

47

int lpfc_reg_rpi(struct lpfc_hba *, uint16_t, uint32_t, uint8_t *,

drivers/scsi/lpfc/lpfc_crtn.h

523

void lpfc_parse_fcoe_conf(struct lpfc_hba *, uint8_t *, uint32_t);

drivers/scsi/lpfc/lpfc_crtn.h

524

int lpfc_parse_vpd(struct lpfc_hba *, uint8_t *, int);

drivers/scsi/lpfc/lpfc_crtn.h

586

int lpfc_sli4_request_firmware_update(struct lpfc_hba *, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

599

struct lpfc_name *, uint64_t, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

601

struct lpfc_name *, uint64_t, uint8_t);

drivers/scsi/lpfc/lpfc_crtn.h

636

uint8_t cqflag);

drivers/scsi/lpfc/lpfc_crtn.h

683

uint32_t hash, uint8_t *buf);

drivers/scsi/lpfc/lpfc_ct.c

1344

uint8_t fbits;

drivers/scsi/lpfc/lpfc_ct.c

1589

uint8_t retry;

drivers/scsi/lpfc/lpfc_ct.c

1905

uint8_t retry, uint32_t context)

drivers/scsi/lpfc/lpfc_ct.c

3286

ab = (struct lpfc_fdmi_attr_block *)((uint8_t *)rh + size);

drivers/scsi/lpfc/lpfc_ct.c

3300

addsz = func(vport, ((uint8_t *)rh + size));

drivers/scsi/lpfc/lpfc_ct.c

3337

((uint8_t *)base + sizeof(struct lpfc_name));

drivers/scsi/lpfc/lpfc_ct.c

3343

memcpy((uint8_t *)&pab->PortName,

drivers/scsi/lpfc/lpfc_ct.c

3344

(uint8_t *)&vport->fc_sparam.portName,

drivers/scsi/lpfc/lpfc_ct.c

3360

addsz = func(vport, ((uint8_t *)base + size));

drivers/scsi/lpfc/lpfc_ct.c

3385

memcpy((uint8_t *)&pe->PortName,

drivers/scsi/lpfc/lpfc_ct.c

3386

(uint8_t *)&vport->fc_sparam.portName,

drivers/scsi/lpfc/lpfc_ct.c

3404

memcpy((uint8_t *)&pe->PortName,

drivers/scsi/lpfc/lpfc_ct.c

3405

(uint8_t *)&vport->fc_sparam.portName,

drivers/scsi/lpfc/lpfc_ct.c

3501

uint8_t *fwname;

drivers/scsi/lpfc/lpfc_ct.c

591

uint32_t tmo, uint8_t retry)

drivers/scsi/lpfc/lpfc_ct.c

668

uint32_t rsp_size, uint8_t retry)

drivers/scsi/lpfc/lpfc_ct.c

715

lpfc_prep_node_fc4type(struct lpfc_vport *vport, uint32_t Did, uint8_t fc4_type)

drivers/scsi/lpfc/lpfc_ct.c

803

lpfc_ns_rsp_audit_did(struct lpfc_vport *vport, uint32_t Did, uint8_t fc4_type)

drivers/scsi/lpfc/lpfc_ct.c

844

lpfc_ns_rsp(struct lpfc_vport *vport, struct lpfc_dmabuf *mp, uint8_t fc4_type,

drivers/scsi/lpfc/lpfc_debugfs.c

3335

uint8_t u8val;

drivers/scsi/lpfc/lpfc_debugfs.c

3453

uint8_t u8val;

drivers/scsi/lpfc/lpfc_debugfs.c

3480

} else if ((count != sizeof(uint8_t)) &&

drivers/scsi/lpfc/lpfc_debugfs.c

3484

if (count == sizeof(uint8_t)) {

drivers/scsi/lpfc/lpfc_debugfs.c

3485

if (where > LPFC_PCI_CFG_SIZE - sizeof(uint8_t))

drivers/scsi/lpfc/lpfc_debugfs.c

3487

if (where % sizeof(uint8_t))

drivers/scsi/lpfc/lpfc_debugfs.c

3513

if ((count != sizeof(uint8_t)) &&

drivers/scsi/lpfc/lpfc_debugfs.c

3517

if (count == sizeof(uint8_t)) {

drivers/scsi/lpfc/lpfc_debugfs.c

3518

if (where > LPFC_PCI_CFG_SIZE - sizeof(uint8_t))

drivers/scsi/lpfc/lpfc_debugfs.c

3520

if (where % sizeof(uint8_t))

drivers/scsi/lpfc/lpfc_debugfs.c

3524

(uint8_t)value);

drivers/scsi/lpfc/lpfc_debugfs.c

3528

u8val |= (uint8_t)value;

drivers/scsi/lpfc/lpfc_debugfs.c

3536

u8val &= (uint8_t)(~value);

drivers/scsi/lpfc/lpfc_debugfs.c

5978

uint8_t *pbyte;

drivers/scsi/lpfc/lpfc_debugfs.c

6025

pbyte = (uint8_t *)pmbox;

drivers/scsi/lpfc/lpfc_debugfs.c

6040

((uint8_t)*pbyte) & 0xff);

drivers/scsi/lpfc/lpfc_debugfs.h

206

#define SIZE_U8 sizeof(uint8_t)

drivers/scsi/lpfc/lpfc_disc.h

138

uint8_t nlp_class_sup; /* Supported Classes */

drivers/scsi/lpfc/lpfc_disc.h

139

uint8_t nlp_retry; /* used for ELS retries */

drivers/scsi/lpfc/lpfc_disc.h

140

uint8_t nlp_fcp_info; /* class info, bits 0-3 */

drivers/scsi/lpfc/lpfc_disc.h

143

uint8_t vmid_support; /* destination VMID support */

drivers/scsi/lpfc/lpfc_els.c

10450

uint8_t rjt_exp, rjt_err = 0, init_link = 0;

drivers/scsi/lpfc/lpfc_els.c

11378

uint8_t fabric_param_changed;

drivers/scsi/lpfc/lpfc_els.c

11525

uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

11532

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

11561

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

11712

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

11721

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

1276

uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

1310

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

1710

uint8_t name[sizeof(struct lpfc_name)];

drivers/scsi/lpfc/lpfc_els.c

1719

sp = (struct serv_parm *) ((uint8_t *) prsp + sizeof(uint32_t));

drivers/scsi/lpfc/lpfc_els.c

2277

lpfc_issue_els_plogi(struct lpfc_vport *vport, uint32_t did, uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

2283

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

2318

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

2552

uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

2559

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

2618

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

2988

uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

2994

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

3003

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

3199

uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

3203

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

3216

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

3551

lpfc_issue_els_scr(struct lpfc_vport *vport, uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

3556

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

3586

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

3645

lpfc_issue_els_rscn(struct lpfc_vport *vport, uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

3744

lpfc_issue_els_farpr(struct lpfc_vport *vport, uint32_t nportid, uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

3750

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

3771

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

3843

lpfc_issue_els_rdf(struct lpfc_vport *vport, uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

388

rc = lpfc_reg_rpi(phba, vport->vpi, Fabric_DID, (uint8_t *)sp, mbox,

drivers/scsi/lpfc/lpfc_els.c

4359

lpfc_issue_els_edc(struct lpfc_vport *vport, uint8_t retry)

drivers/scsi/lpfc/lpfc_els.c

56

struct lpfc_nodelist *ndlp, uint8_t retry);

drivers/scsi/lpfc/lpfc_els.c

5631

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

568

static uint8_t

drivers/scsi/lpfc/lpfc_els.c

573

uint8_t fabric_param_changed = 0;

drivers/scsi/lpfc/lpfc_els.c

5901

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

5923

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

5988

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

6091

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

6127

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

6191

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

6249

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

629

uint8_t fabric_param_changed;

drivers/scsi/lpfc/lpfc_els.c

6373

lpfc_els_rsp_rnid_acc(struct lpfc_vport *vport, uint8_t format,

drivers/scsi/lpfc/lpfc_els.c

6381

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

6416

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

6479

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

6486

pcmd = (uint8_t *)iocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

6526

lpfc_els_rsp_echo_acc(struct lpfc_vport *vport, uint8_t *data,

drivers/scsi/lpfc/lpfc_els.c

6533

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

6573

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

6733

uint8_t *page_a0, uint8_t *page_a2)

drivers/scsi/lpfc/lpfc_els.c

6852

struct fc_rdp_oed_sfp_desc *desc, uint8_t *page_a2)

drivers/scsi/lpfc/lpfc_els.c

6881

uint8_t *page_a2)

drivers/scsi/lpfc/lpfc_els.c

6910

uint8_t *page_a2)

drivers/scsi/lpfc/lpfc_els.c

6939

uint8_t *page_a2)

drivers/scsi/lpfc/lpfc_els.c

6969

uint8_t *page_a2)

drivers/scsi/lpfc/lpfc_els.c

6997

uint8_t *page_a0, struct lpfc_vport *vport)

drivers/scsi/lpfc/lpfc_els.c

7154

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

7195

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

7287

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

7500

uint8_t rjt_err, rjt_expl = LSEXP_NOTHING_MORE;

drivers/scsi/lpfc/lpfc_els.c

7587

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

7648

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

7693

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

7811

uint8_t *lp;

drivers/scsi/lpfc/lpfc_els.c

7818

lp = (uint8_t *)pcmd->virt;

drivers/scsi/lpfc/lpfc_els.c

8259

memcpy(((uint8_t *)cmd) + length, lp,

drivers/scsi/lpfc/lpfc_els.c

8648

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

8650

pcmd = (uint8_t *)cmdiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

8739

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

8785

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

8914

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

8932

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

9013

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

9027

pcmd = (uint8_t *)elsiocb->cmd_dmabuf->virt;

drivers/scsi/lpfc/lpfc_els.c

9119

uint8_t *pcmd;

drivers/scsi/lpfc/lpfc_els.c

9423

uint8_t *payload;

drivers/scsi/lpfc/lpfc_hbadisc.c

1671

lpfc_fab_name_match(uint8_t *fab_name, struct fcf_record *new_fcf_record)

drivers/scsi/lpfc/lpfc_hbadisc.c

1702

lpfc_sw_name_match(uint8_t *sw_name, struct fcf_record *new_fcf_record)

drivers/scsi/lpfc/lpfc_hbadisc.c

1733

lpfc_mac_addr_match(uint8_t *mac_addr, struct fcf_record *new_fcf_record)

drivers/scsi/lpfc/lpfc_hbadisc.c

2131

lpfc_check_pending_fcoe_event(struct lpfc_hba *phba, uint8_t unreg_fcf)

drivers/scsi/lpfc/lpfc_hbadisc.c

3459

memcpy((uint8_t *) &vport->fc_sparam, (uint8_t *) mp->virt,

drivers/scsi/lpfc/lpfc_hbadisc.c

3563

uint8_t pamap[16];

drivers/scsi/lpfc/lpfc_hbadisc.c

3748

uint8_t attn_type;

drivers/scsi/lpfc/lpfc_hbadisc.c

4043

uint8_t *vport_buff;

drivers/scsi/lpfc/lpfc_hbadisc.c

4066

vport_buff = (uint8_t *) vport_info;

drivers/scsi/lpfc/lpfc_hbadisc.c

4110

lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,

drivers/scsi/lpfc/lpfc_hbadisc.c

453

uint8_t *name;

drivers/scsi/lpfc/lpfc_hbadisc.c

461

name = (uint8_t *)&ndlp->nlp_portname;

drivers/scsi/lpfc/lpfc_hbadisc.c

54

static uint8_t lpfcAlpaArray[] = {

drivers/scsi/lpfc/lpfc_hbadisc.c

6988

uint8_t *buff)

drivers/scsi/lpfc/lpfc_hbadisc.c

7070

uint8_t *buff)

drivers/scsi/lpfc/lpfc_hbadisc.c

7106

static uint8_t *

drivers/scsi/lpfc/lpfc_hbadisc.c

7107

lpfc_get_rec_conf23(uint8_t *buff, uint32_t size, uint8_t rec_type)

drivers/scsi/lpfc/lpfc_hbadisc.c

7146

uint8_t *buff,

drivers/scsi/lpfc/lpfc_hbadisc.c

7150

uint8_t *rec_ptr;

drivers/scsi/lpfc/lpfc_hw.h

1061

uint8_t resv;

drivers/scsi/lpfc/lpfc_hw.h

1062

uint8_t domain;

drivers/scsi/lpfc/lpfc_hw.h

1063

uint8_t area;

drivers/scsi/lpfc/lpfc_hw.h

1064

uint8_t id;

drivers/scsi/lpfc/lpfc_hw.h

1066

uint8_t id;

drivers/scsi/lpfc/lpfc_hw.h

1067

uint8_t area;

drivers/scsi/lpfc/lpfc_hw.h

1068

uint8_t domain;

drivers/scsi/lpfc/lpfc_hw.h

1069

uint8_t resv;

drivers/scsi/lpfc/lpfc_hw.h

1086

uint8_t elsCode; /* FC Word 0, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

1087

uint8_t elsByte1;

drivers/scsi/lpfc/lpfc_hw.h

1088

uint8_t elsByte2;

drivers/scsi/lpfc/lpfc_hw.h

1089

uint8_t elsByte3;

drivers/scsi/lpfc/lpfc_hw.h

1101

uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */

drivers/scsi/lpfc/lpfc_hw.h

1111

uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

1114

uint8_t reserved[2];

drivers/scsi/lpfc/lpfc_hw.h

1115

uint8_t capability; /* LCB Payload Word 1, bit 0:7 */

drivers/scsi/lpfc/lpfc_hw.h

1116

uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

1119

uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

1131

uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

1132

uint8_t reserved[2];

drivers/scsi/lpfc/lpfc_hw.h

1133

uint8_t capability; /* LCB Payload Word 1, bit 0:7 */

drivers/scsi/lpfc/lpfc_hw.h

1134

uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

1135

uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

115

uint8_t FsType;

drivers/scsi/lpfc/lpfc_hw.h

116

uint8_t FsSubType;

drivers/scsi/lpfc/lpfc_hw.h

1165

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_hw.h

1166

uint8_t wwpn[8];

drivers/scsi/lpfc/lpfc_hw.h

117

uint8_t Options;

drivers/scsi/lpfc/lpfc_hw.h

118

uint8_t Rsrvd1;

drivers/scsi/lpfc/lpfc_hw.h

120

uint8_t Rsrvd2;

drivers/scsi/lpfc/lpfc_hw.h

121

uint8_t ReasonCode;

drivers/scsi/lpfc/lpfc_hw.h

122

uint8_t Explanation;

drivers/scsi/lpfc/lpfc_hw.h

123

uint8_t VendorUnique;

drivers/scsi/lpfc/lpfc_hw.h

129

uint8_t PortType; /* for GID_PT requests */

drivers/scsi/lpfc/lpfc_hw.h

131

uint8_t DomainScope;

drivers/scsi/lpfc/lpfc_hw.h

132

uint8_t AreaScope;

drivers/scsi/lpfc/lpfc_hw.h

133

uint8_t Fc4Type; /* for GID_FT requests */

drivers/scsi/lpfc/lpfc_hw.h

1334

uint8_t vendor_name[16];

drivers/scsi/lpfc/lpfc_hw.h

1335

uint8_t model_number[16];

drivers/scsi/lpfc/lpfc_hw.h

1336

uint8_t serial_number[16];

drivers/scsi/lpfc/lpfc_hw.h

1337

uint8_t revision[4];

drivers/scsi/lpfc/lpfc_hw.h

1338

uint8_t date[8];

drivers/scsi/lpfc/lpfc_hw.h

136

uint8_t Flags;

drivers/scsi/lpfc/lpfc_hw.h

137

uint8_t DomainScope;

drivers/scsi/lpfc/lpfc_hw.h

138

uint8_t AreaScope;

drivers/scsi/lpfc/lpfc_hw.h

1385

uint8_t vem_id[16];

drivers/scsi/lpfc/lpfc_hw.h

139

uint8_t rsvd1;

drivers/scsi/lpfc/lpfc_hw.h

1394

uint8_t global_vem_id[16];

drivers/scsi/lpfc/lpfc_hw.h

140

uint8_t rsvd2;

drivers/scsi/lpfc/lpfc_hw.h

1408

uint8_t global_vem_id[16];

drivers/scsi/lpfc/lpfc_hw.h

141

uint8_t rsvd3;

drivers/scsi/lpfc/lpfc_hw.h

142

uint8_t Fc4FBits;

drivers/scsi/lpfc/lpfc_hw.h

1424

uint8_t lo_range;

drivers/scsi/lpfc/lpfc_hw.h

1425

uint8_t hi_range;

drivers/scsi/lpfc/lpfc_hw.h

1426

uint8_t qos_priority;

drivers/scsi/lpfc/lpfc_hw.h

1427

uint8_t local_ve_id;

drivers/scsi/lpfc/lpfc_hw.h

143

uint8_t Fc4Type;

drivers/scsi/lpfc/lpfc_hw.h

1454

uint8_t entity_id_len;

drivers/scsi/lpfc/lpfc_hw.h

1455

uint8_t entity_id[255]; /* VM UUID */

drivers/scsi/lpfc/lpfc_hw.h

1476

uint8_t control;

drivers/scsi/lpfc/lpfc_hw.h

1477

uint8_t reserved[3];

drivers/scsi/lpfc/lpfc_hw.h

156

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_hw.h

159

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_hw.h

160

uint8_t len;

drivers/scsi/lpfc/lpfc_hw.h

161

uint8_t symbname[255];

drivers/scsi/lpfc/lpfc_hw.h

168

uint8_t len;

drivers/scsi/lpfc/lpfc_hw.h

169

uint8_t symbname[255];

drivers/scsi/lpfc/lpfc_hw.h

180

uint8_t fbits[128];

drivers/scsi/lpfc/lpfc_hw.h

191

uint8_t reserved[2];

drivers/scsi/lpfc/lpfc_hw.h

192

uint8_t fbits;

drivers/scsi/lpfc/lpfc_hw.h

193

uint8_t type_code; /* type=8 for FCP */

drivers/scsi/lpfc/lpfc_hw.h

2188

uint8_t tval;

drivers/scsi/lpfc/lpfc_hw.h

2189

uint8_t tmask;

drivers/scsi/lpfc/lpfc_hw.h

2190

uint8_t rval;

drivers/scsi/lpfc/lpfc_hw.h

2191

uint8_t rmask;

drivers/scsi/lpfc/lpfc_hw.h

2193

uint8_t rmask;

drivers/scsi/lpfc/lpfc_hw.h

2194

uint8_t rval;

drivers/scsi/lpfc/lpfc_hw.h

2195

uint8_t tmask;

drivers/scsi/lpfc/lpfc_hw.h

2196

uint8_t tval;

drivers/scsi/lpfc/lpfc_hw.h

2441

uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */

drivers/scsi/lpfc/lpfc_hw.h

2442

uint8_t rsvd2;

drivers/scsi/lpfc/lpfc_hw.h

2446

uint8_t rsvd2;

drivers/scsi/lpfc/lpfc_hw.h

2447

uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */

drivers/scsi/lpfc/lpfc_hw.h

2823

uint8_t seqId;

drivers/scsi/lpfc/lpfc_hw.h

2824

uint8_t rsvd5;

drivers/scsi/lpfc/lpfc_hw.h

2842

uint8_t rsvd5;

drivers/scsi/lpfc/lpfc_hw.h

2843

uint8_t seqId;

drivers/scsi/lpfc/lpfc_hw.h

2879

uint8_t ProgType;

drivers/scsi/lpfc/lpfc_hw.h

2880

uint8_t ProgId;

drivers/scsi/lpfc/lpfc_hw.h

2892

uint8_t ProgId;

drivers/scsi/lpfc/lpfc_hw.h

2893

uint8_t ProgType;

drivers/scsi/lpfc/lpfc_hw.h

2900

uint8_t feaLevelHigh;

drivers/scsi/lpfc/lpfc_hw.h

2901

uint8_t feaLevelLow;

drivers/scsi/lpfc/lpfc_hw.h

2902

uint8_t fcphHigh;

drivers/scsi/lpfc/lpfc_hw.h

2903

uint8_t fcphLow;

drivers/scsi/lpfc/lpfc_hw.h

2905

uint8_t fcphLow;

drivers/scsi/lpfc/lpfc_hw.h

2906

uint8_t fcphHigh;

drivers/scsi/lpfc/lpfc_hw.h

2907

uint8_t feaLevelLow;

drivers/scsi/lpfc/lpfc_hw.h

2908

uint8_t feaLevelHigh;

drivers/scsi/lpfc/lpfc_hw.h

2913

uint8_t opFwName[16];

drivers/scsi/lpfc/lpfc_hw.h

2915

uint8_t sli1FwName[16];

drivers/scsi/lpfc/lpfc_hw.h

2917

uint8_t sli2FwName[16];

drivers/scsi/lpfc/lpfc_hw.h

3258

uint8_t wwpn[8];

drivers/scsi/lpfc/lpfc_hw.h

3259

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_hw.h

3276

uint8_t type;

drivers/scsi/lpfc/lpfc_hw.h

3277

uint8_t id;

drivers/scsi/lpfc/lpfc_hw.h

3289

uint8_t id;

drivers/scsi/lpfc/lpfc_hw.h

3290

uint8_t type;

drivers/scsi/lpfc/lpfc_hw.h

3326

uint8_t tmatch;

drivers/scsi/lpfc/lpfc_hw.h

3327

uint8_t tmask;

drivers/scsi/lpfc/lpfc_hw.h

3328

uint8_t rctlmatch;

drivers/scsi/lpfc/lpfc_hw.h

3329

uint8_t rctlmask;

drivers/scsi/lpfc/lpfc_hw.h

3331

uint8_t rctlmask;

drivers/scsi/lpfc/lpfc_hw.h

3332

uint8_t rctlmatch;

drivers/scsi/lpfc/lpfc_hw.h

3333

uint8_t tmask;

drivers/scsi/lpfc/lpfc_hw.h

3334

uint8_t tmatch;

drivers/scsi/lpfc/lpfc_hw.h

356

uint8_t nameType:4; /* FC Word 0, bit 28:31 */

drivers/scsi/lpfc/lpfc_hw.h

357

uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit

drivers/scsi/lpfc/lpfc_hw.h

3599

uint8_t attentionId[16];

drivers/scsi/lpfc/lpfc_hw.h

360

uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit

drivers/scsi/lpfc/lpfc_hw.h

3600

uint8_t messageNumberByHA[64];

drivers/scsi/lpfc/lpfc_hw.h

3601

uint8_t messageNumberByID[16];

drivers/scsi/lpfc/lpfc_hw.h

362

uint8_t nameType:4; /* FC Word 0, bit 28:31 */

drivers/scsi/lpfc/lpfc_hw.h

3675

uint8_t portname[8]; /* Used to be struct lpfc_name */

drivers/scsi/lpfc/lpfc_hw.h

3676

uint8_t nodename[8];

drivers/scsi/lpfc/lpfc_hw.h

371

uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE

drivers/scsi/lpfc/lpfc_hw.h

373

uint8_t IEEE[6]; /* FC IEEE address */

drivers/scsi/lpfc/lpfc_hw.h

375

uint8_t wwn[8];

drivers/scsi/lpfc/lpfc_hw.h

3791

uint8_t mbxCommand;

drivers/scsi/lpfc/lpfc_hw.h

3792

uint8_t mbxReserved:6;

drivers/scsi/lpfc/lpfc_hw.h

3793

uint8_t mbxHc:1;

drivers/scsi/lpfc/lpfc_hw.h

3794

uint8_t mbxOwner:1; /* Low order bit first word */

drivers/scsi/lpfc/lpfc_hw.h

3796

uint8_t mbxOwner:1; /* Low order bit first word */

drivers/scsi/lpfc/lpfc_hw.h

3797

uint8_t mbxHc:1;

drivers/scsi/lpfc/lpfc_hw.h

3798

uint8_t mbxReserved:6;

drivers/scsi/lpfc/lpfc_hw.h

3799

uint8_t mbxCommand;

drivers/scsi/lpfc/lpfc_hw.h

3817

uint8_t statAction;

drivers/scsi/lpfc/lpfc_hw.h

3818

uint8_t statRsn;

drivers/scsi/lpfc/lpfc_hw.h

3819

uint8_t statBaExp;

drivers/scsi/lpfc/lpfc_hw.h

382

uint8_t fcphHigh; /* FC Word 0, byte 0 */

drivers/scsi/lpfc/lpfc_hw.h

3820

uint8_t statLocalError;

drivers/scsi/lpfc/lpfc_hw.h

3822

uint8_t statLocalError;

drivers/scsi/lpfc/lpfc_hw.h

3823

uint8_t statBaExp;

drivers/scsi/lpfc/lpfc_hw.h

3824

uint8_t statRsn;

drivers/scsi/lpfc/lpfc_hw.h

3825

uint8_t statAction;

drivers/scsi/lpfc/lpfc_hw.h

383

uint8_t fcphLow;

drivers/scsi/lpfc/lpfc_hw.h

384

uint8_t bbCreditMsb;

drivers/scsi/lpfc/lpfc_hw.h

385

uint8_t bbCreditLsb; /* FC Word 0, byte 3 */

drivers/scsi/lpfc/lpfc_hw.h

3918

uint8_t Rctl; /* R_CTL field */

drivers/scsi/lpfc/lpfc_hw.h

3919

uint8_t Type; /* TYPE field */

drivers/scsi/lpfc/lpfc_hw.h

3920

uint8_t Dfctl; /* DF_CTL field */

drivers/scsi/lpfc/lpfc_hw.h

3921

uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */

drivers/scsi/lpfc/lpfc_hw.h

3923

uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */

drivers/scsi/lpfc/lpfc_hw.h

3924

uint8_t Dfctl; /* DF_CTL field */

drivers/scsi/lpfc/lpfc_hw.h

3925

uint8_t Type; /* TYPE field */

drivers/scsi/lpfc/lpfc_hw.h

3926

uint8_t Rctl; /* R_CTL field */

drivers/scsi/lpfc/lpfc_hw.h

4290

uint8_t reserved1;

drivers/scsi/lpfc/lpfc_hw.h

4291

uint8_t reserved2;

drivers/scsi/lpfc/lpfc_hw.h

4292

uint8_t reserved3;

drivers/scsi/lpfc/lpfc_hw.h

4293

uint8_t ebde_count;

drivers/scsi/lpfc/lpfc_hw.h

4295

uint8_t ebde_count;

drivers/scsi/lpfc/lpfc_hw.h

4296

uint8_t reserved3;

drivers/scsi/lpfc/lpfc_hw.h

4297

uint8_t reserved2;

drivers/scsi/lpfc/lpfc_hw.h

4298

uint8_t reserved1;

drivers/scsi/lpfc/lpfc_hw.h

4303

uint8_t icd[32]; /* immediate command data (32 bytes) */

drivers/scsi/lpfc/lpfc_hw.h

439

uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */

drivers/scsi/lpfc/lpfc_hw.h

440

uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */

drivers/scsi/lpfc/lpfc_hw.h

443

uint8_t word2Reserved1; /* FC Word 2 byte 0 */

drivers/scsi/lpfc/lpfc_hw.h

445

uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */

drivers/scsi/lpfc/lpfc_hw.h

446

uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */

drivers/scsi/lpfc/lpfc_hw.h

448

uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */

drivers/scsi/lpfc/lpfc_hw.h

458

uint8_t classValid:1; /* FC Word 0, bit 31 */

drivers/scsi/lpfc/lpfc_hw.h

459

uint8_t intermix:1; /* FC Word 0, bit 30 */

drivers/scsi/lpfc/lpfc_hw.h

460

uint8_t stackedXparent:1; /* FC Word 0, bit 29 */

drivers/scsi/lpfc/lpfc_hw.h

461

uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */

drivers/scsi/lpfc/lpfc_hw.h

462

uint8_t seqDelivery:1; /* FC Word 0, bit 27 */

drivers/scsi/lpfc/lpfc_hw.h

463

uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */

drivers/scsi/lpfc/lpfc_hw.h

465

uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */

drivers/scsi/lpfc/lpfc_hw.h

466

uint8_t seqDelivery:1; /* FC Word 0, bit 27 */

drivers/scsi/lpfc/lpfc_hw.h

467

uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */

drivers/scsi/lpfc/lpfc_hw.h

468

uint8_t stackedXparent:1; /* FC Word 0, bit 29 */

drivers/scsi/lpfc/lpfc_hw.h

469

uint8_t intermix:1; /* FC Word 0, bit 30 */

drivers/scsi/lpfc/lpfc_hw.h

470

uint8_t classValid:1; /* FC Word 0, bit 31 */

drivers/scsi/lpfc/lpfc_hw.h

474

uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

477

uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */

drivers/scsi/lpfc/lpfc_hw.h

478

uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */

drivers/scsi/lpfc/lpfc_hw.h

479

uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */

drivers/scsi/lpfc/lpfc_hw.h

480

uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */

drivers/scsi/lpfc/lpfc_hw.h

481

uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */

drivers/scsi/lpfc/lpfc_hw.h

483

uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */

drivers/scsi/lpfc/lpfc_hw.h

484

uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */

drivers/scsi/lpfc/lpfc_hw.h

485

uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */

drivers/scsi/lpfc/lpfc_hw.h

486

uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */

drivers/scsi/lpfc/lpfc_hw.h

487

uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */

drivers/scsi/lpfc/lpfc_hw.h

490

uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */

drivers/scsi/lpfc/lpfc_hw.h

493

uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */

drivers/scsi/lpfc/lpfc_hw.h

494

uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */

drivers/scsi/lpfc/lpfc_hw.h

495

uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */

drivers/scsi/lpfc/lpfc_hw.h

496

uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */

drivers/scsi/lpfc/lpfc_hw.h

497

uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */

drivers/scsi/lpfc/lpfc_hw.h

498

uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */

drivers/scsi/lpfc/lpfc_hw.h

500

uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */

drivers/scsi/lpfc/lpfc_hw.h

501

uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */

drivers/scsi/lpfc/lpfc_hw.h

502

uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */

drivers/scsi/lpfc/lpfc_hw.h

503

uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */

drivers/scsi/lpfc/lpfc_hw.h

504

uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */

drivers/scsi/lpfc/lpfc_hw.h

505

uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */

drivers/scsi/lpfc/lpfc_hw.h

508

uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

509

uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */

drivers/scsi/lpfc/lpfc_hw.h

510

uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */

drivers/scsi/lpfc/lpfc_hw.h

512

uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

513

uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

514

uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */

drivers/scsi/lpfc/lpfc_hw.h

515

uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */

drivers/scsi/lpfc/lpfc_hw.h

517

uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

518

uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

519

uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */

drivers/scsi/lpfc/lpfc_hw.h

520

uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */

drivers/scsi/lpfc/lpfc_hw.h

547

uint8_t vendorVersion[16];

drivers/scsi/lpfc/lpfc_hw.h

713

uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

715

uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

725

uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */

drivers/scsi/lpfc/lpfc_hw.h

753

uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */

drivers/scsi/lpfc/lpfc_hw.h

766

uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */

drivers/scsi/lpfc/lpfc_hw.h

767

uint8_t nPortIdByte0; /* N_port ID bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

768

uint8_t nPortIdByte1; /* N_port ID bit 8:15 */

drivers/scsi/lpfc/lpfc_hw.h

769

uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */

drivers/scsi/lpfc/lpfc_hw.h

783

uint8_t prliType; /* FC Parm Word 0, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

787

uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

790

uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */

drivers/scsi/lpfc/lpfc_hw.h

791

uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */

drivers/scsi/lpfc/lpfc_hw.h

792

uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */

drivers/scsi/lpfc/lpfc_hw.h

795

uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */

drivers/scsi/lpfc/lpfc_hw.h

796

uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */

drivers/scsi/lpfc/lpfc_hw.h

798

uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */

drivers/scsi/lpfc/lpfc_hw.h

799

uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */

drivers/scsi/lpfc/lpfc_hw.h

800

uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */

drivers/scsi/lpfc/lpfc_hw.h

801

uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */

drivers/scsi/lpfc/lpfc_hw.h

802

uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */

drivers/scsi/lpfc/lpfc_hw.h

815

uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */

drivers/scsi/lpfc/lpfc_hw.h

821

uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

822

uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

866

uint8_t prloType; /* FC Parm Word 0, bit 24:31 */

drivers/scsi/lpfc/lpfc_hw.h

869

uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */

drivers/scsi/lpfc/lpfc_hw.h

872

uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */

drivers/scsi/lpfc/lpfc_hw.h

873

uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */

drivers/scsi/lpfc/lpfc_hw.h

874

uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */

drivers/scsi/lpfc/lpfc_hw.h

875

uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */

drivers/scsi/lpfc/lpfc_hw.h

877

uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */

drivers/scsi/lpfc/lpfc_hw.h

878

uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */

drivers/scsi/lpfc/lpfc_hw.h

879

uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */

drivers/scsi/lpfc/lpfc_hw.h

880

uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */

drivers/scsi/lpfc/lpfc_hw.h

887

uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */

drivers/scsi/lpfc/lpfc_hw.h

923

uint8_t Oipaddr[16];

drivers/scsi/lpfc/lpfc_hw.h

924

uint8_t Ripaddr[16];

drivers/scsi/lpfc/lpfc_hw.h

934

uint8_t resvd1;

drivers/scsi/lpfc/lpfc_hw.h

935

uint8_t resvd2;

drivers/scsi/lpfc/lpfc_hw.h

936

uint8_t resvd3;

drivers/scsi/lpfc/lpfc_hw.h

937

uint8_t Function;

drivers/scsi/lpfc/lpfc_hw.h

946

uint8_t resvd[8];

drivers/scsi/lpfc/lpfc_hw.h

957

uint8_t ipAddr[16];

drivers/scsi/lpfc/lpfc_hw.h

965

uint8_t Format;

drivers/scsi/lpfc/lpfc_hw.h

967

uint8_t CommonLen;

drivers/scsi/lpfc/lpfc_hw.h

968

uint8_t resvd1;

drivers/scsi/lpfc/lpfc_hw.h

969

uint8_t SpecificLen;

drivers/scsi/lpfc/lpfc_hw4.h

2324

uint8_t vlan_bitmap[512];

drivers/scsi/lpfc/lpfc_hw4.h

2896

uint8_t fw_name[16];

drivers/scsi/lpfc/lpfc_hw4.h

2898

uint8_t ulp_fw_name[16];

drivers/scsi/lpfc/lpfc_hw4.h

3255

uint8_t inifiband:4;

drivers/scsi/lpfc/lpfc_hw4.h

3256

uint8_t teng_ethernet:4;

drivers/scsi/lpfc/lpfc_hw4.h

3260

uint8_t sonet:6;

drivers/scsi/lpfc/lpfc_hw4.h

3261

uint8_t escon:2;

drivers/scsi/lpfc/lpfc_hw4.h

3265

uint8_t soNet:8;

drivers/scsi/lpfc/lpfc_hw4.h

3269

uint8_t ethernet:8;

drivers/scsi/lpfc/lpfc_hw4.h

3273

uint8_t fc_el_lo:1;

drivers/scsi/lpfc/lpfc_hw4.h

3274

uint8_t fc_lw_laser:1;

drivers/scsi/lpfc/lpfc_hw4.h

3275

uint8_t fc_sw_laser:1;

drivers/scsi/lpfc/lpfc_hw4.h

3276

uint8_t fc_md_distance:1;

drivers/scsi/lpfc/lpfc_hw4.h

3277

uint8_t fc_lg_distance:1;

drivers/scsi/lpfc/lpfc_hw4.h

3278

uint8_t fc_int_distance:1;

drivers/scsi/lpfc/lpfc_hw4.h

3279

uint8_t fc_short_distance:1;

drivers/scsi/lpfc/lpfc_hw4.h

3280

uint8_t fc_vld_distance:1;

drivers/scsi/lpfc/lpfc_hw4.h

3284

uint8_t reserved1:1;

drivers/scsi/lpfc/lpfc_hw4.h

3285

uint8_t reserved2:1;

drivers/scsi/lpfc/lpfc_hw4.h

3286

uint8_t fc_sfp_active:1; /* Active cable */

drivers/scsi/lpfc/lpfc_hw4.h

3287

uint8_t fc_sfp_passive:1; /* Passive cable */

drivers/scsi/lpfc/lpfc_hw4.h

3288

uint8_t fc_lw_laser:1; /* Longwave laser */

drivers/scsi/lpfc/lpfc_hw4.h

3289

uint8_t fc_sw_laser_sl:1;

drivers/scsi/lpfc/lpfc_hw4.h

3290

uint8_t fc_sw_laser_sn:1;

drivers/scsi/lpfc/lpfc_hw4.h

3291

uint8_t fc_el_hi:1; /* Electrical enclosure high bit */

drivers/scsi/lpfc/lpfc_hw4.h

3295

uint8_t fc_tm_sm:1; /* Single Mode */

drivers/scsi/lpfc/lpfc_hw4.h

3296

uint8_t reserved:1;

drivers/scsi/lpfc/lpfc_hw4.h

3297

uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */

drivers/scsi/lpfc/lpfc_hw4.h

3298

uint8_t fc_tm_tv:1; /* Video Coax (TV) */

drivers/scsi/lpfc/lpfc_hw4.h

3299

uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */

drivers/scsi/lpfc/lpfc_hw4.h

3300

uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */

drivers/scsi/lpfc/lpfc_hw4.h

3301

uint8_t fc_tm_tw:1; /* Twin Axial Pair */

drivers/scsi/lpfc/lpfc_hw4.h

3305

uint8_t fc_sp_100MB:1; /* 100 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3306

uint8_t speed_chk_ecc:1;

drivers/scsi/lpfc/lpfc_hw4.h

3307

uint8_t fc_sp_200mb:1; /* 200 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3308

uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3309

uint8_t fc_sp_400MB:1; /* 400 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3310

uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3311

uint8_t fc_sp_800MB:1; /* 800 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3312

uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */

drivers/scsi/lpfc/lpfc_hw4.h

3317

uint8_t vendor_name[16];

drivers/scsi/lpfc/lpfc_hw4.h

3318

uint8_t vendor_oui[3];

drivers/scsi/lpfc/lpfc_hw4.h

3319

uint8_t vendor_pn[816];

drivers/scsi/lpfc/lpfc_hw4.h

3320

uint8_t vendor_rev[4];

drivers/scsi/lpfc/lpfc_hw4.h

3321

uint8_t vendor_sn[16];

drivers/scsi/lpfc/lpfc_hw4.h

3322

uint8_t datecode[6];

drivers/scsi/lpfc/lpfc_hw4.h

3323

uint8_t lot_code[2];

drivers/scsi/lpfc/lpfc_hw4.h

3324

uint8_t reserved191[57];

drivers/scsi/lpfc/lpfc_hw4.h

3604

uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];

drivers/scsi/lpfc/lpfc_hw4.h

4992

uint8_t rev_name[128];

drivers/scsi/lpfc/lpfc_hw4.h

4993

uint8_t date[12];

drivers/scsi/lpfc/lpfc_hw4.h

4994

uint8_t revision[32];

drivers/scsi/lpfc/lpfc_init.c

13539

uint8_t *data = (uint8_t *)ptr;

drivers/scsi/lpfc/lpfc_init.c

14682

lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)

drivers/scsi/lpfc/lpfc_init.c

2256

lpfc_fill_vpd(struct lpfc_hba *phba, uint8_t *vpd, int length, int *pindex)

drivers/scsi/lpfc/lpfc_init.c

2365

lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)

drivers/scsi/lpfc/lpfc_init.c

2367

uint8_t lenlo, lenhi;

drivers/scsi/lpfc/lpfc_init.c

2431

lpfc_get_atto_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)

drivers/scsi/lpfc/lpfc_init.c

2515

lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)

drivers/scsi/lpfc/lpfc_init.c

264

lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,

drivers/scsi/lpfc/lpfc_init.c

3356

uint8_t actcmd = MBX_HEARTBEAT;

drivers/scsi/lpfc/lpfc_init.c

483

uint8_t *outptr;

drivers/scsi/lpfc/lpfc_init.c

491

(char)((uint8_t) 0x30 + (uint8_t) j);

drivers/scsi/lpfc/lpfc_init.c

494

(char)((uint8_t) 0x61 + (uint8_t) (j - 10));

drivers/scsi/lpfc/lpfc_init.c

499

(char)((uint8_t) 0x30 + (uint8_t) j);

drivers/scsi/lpfc/lpfc_init.c

502

(char)((uint8_t) 0x61 + (uint8_t) (j - 10));

drivers/scsi/lpfc/lpfc_init.c

5235

static uint8_t

drivers/scsi/lpfc/lpfc_init.c

5239

uint8_t att_type;

drivers/scsi/lpfc/lpfc_init.c

5325

uint8_t speed_code)

drivers/scsi/lpfc/lpfc_init.c

5422

uint8_t att_type;

drivers/scsi/lpfc/lpfc_init.c

5542

static uint8_t

drivers/scsi/lpfc/lpfc_init.c

5543

lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)

drivers/scsi/lpfc/lpfc_init.c

5545

uint8_t port_speed;

drivers/scsi/lpfc/lpfc_init.c

6134

uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);

drivers/scsi/lpfc/lpfc_init.c

6135

uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);

drivers/scsi/lpfc/lpfc_init.c

6410

uint8_t status;

drivers/scsi/lpfc/lpfc_init.c

6411

uint8_t evt_type;

drivers/scsi/lpfc/lpfc_init.c

6412

uint8_t operational = 0;

drivers/scsi/lpfc/lpfc_init.c

6736

uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);

drivers/scsi/lpfc/lpfc_init.c

7406

lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)

drivers/scsi/lpfc/lpfc_init.c

75

static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);

drivers/scsi/lpfc/lpfc_init.c

7966

memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,

drivers/scsi/lpfc/lpfc_init.c

8541

lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)

drivers/scsi/lpfc/lpfc_mbox.c

1045

offset = (uint8_t *) &phba->IOCBs[iocbCnt] -

drivers/scsi/lpfc/lpfc_mbox.c

1046

(uint8_t *) phba->slim2p.virt;

drivers/scsi/lpfc/lpfc_mbox.c

1056

offset = (uint8_t *)&phba->IOCBs[iocbCnt] -

drivers/scsi/lpfc/lpfc_mbox.c

1057

(uint8_t *)phba->slim2p.virt;

drivers/scsi/lpfc/lpfc_mbox.c

1339

offset = (uint8_t *)phba->pcb - (uint8_t *)phba->slim2p.virt;

drivers/scsi/lpfc/lpfc_mbox.c

1375

offset = (uint8_t *)phba->mbox - (uint8_t *)phba->slim2p.virt;

drivers/scsi/lpfc/lpfc_mbox.c

1434

offset = (uint8_t *)&phba->mbox->us.s2.host -

drivers/scsi/lpfc/lpfc_mbox.c

1435

(uint8_t *)phba->slim2p.virt;

drivers/scsi/lpfc/lpfc_mbox.c

1678

uint8_t subsys, opcode;

drivers/scsi/lpfc/lpfc_mbox.c

1835

uint8_t subsystem, uint8_t opcode, uint32_t length, bool emb)

drivers/scsi/lpfc/lpfc_mbox.c

1944

uint8_t opcode = 0;

drivers/scsi/lpfc/lpfc_mbox.c

2011

uint8_t

drivers/scsi/lpfc/lpfc_mbox.c

2044

uint8_t

drivers/scsi/lpfc/lpfc_mbox.c

2085

uint8_t *bytep;

drivers/scsi/lpfc/lpfc_mbox.c

2214

uint8_t bbscn_fabric = 0, bbscn_max = 0, bbscn_def = 0;

drivers/scsi/lpfc/lpfc_mbox.c

638

mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK;

drivers/scsi/lpfc/lpfc_mbox.c

807

uint8_t *param, LPFC_MBOXQ_t *pmb, uint16_t rpi)

drivers/scsi/lpfc/lpfc_mbox.c

810

uint8_t *sparam;

drivers/scsi/lpfc/lpfc_nl.h

100

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_nl.h

122

uint8_t wwpn[8];

drivers/scsi/lpfc/lpfc_nl.h

123

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_nl.h

145

uint8_t opcode;

drivers/scsi/lpfc/lpfc_nl.h

146

uint8_t sense_key;

drivers/scsi/lpfc/lpfc_nl.h

147

uint8_t asc;

drivers/scsi/lpfc/lpfc_nl.h

148

uint8_t ascq;

drivers/scsi/lpfc/lpfc_nl.h

70

uint8_t wwpn[8];

drivers/scsi/lpfc/lpfc_nl.h

71

uint8_t wwnn[8];

drivers/scsi/lpfc/lpfc_nl.h

92

uint8_t logo_wwpn[8];

drivers/scsi/lpfc/lpfc_nl.h

99

uint8_t wwpn[8];

drivers/scsi/lpfc/lpfc_nportdisc.c

1002

npr = (PRLI *)((uint8_t *)lp + sizeof(uint32_t));

drivers/scsi/lpfc/lpfc_nportdisc.c

1389

sp = (struct serv_parm *) ((uint8_t *) lp + sizeof (uint32_t));

drivers/scsi/lpfc/lpfc_nportdisc.c

1492

(uint8_t *) sp, mbox, ndlp->nlp_rpi) == 0) {

drivers/scsi/lpfc/lpfc_nportdisc.c

195

ptr = (void *)((uint8_t *)lp + sizeof(uint32_t));

drivers/scsi/lpfc/lpfc_nportdisc.c

380

sp = (struct serv_parm *) ((uint8_t *) lp + sizeof (uint32_t));

drivers/scsi/lpfc/lpfc_nportdisc.c

572

memcpy((uint8_t *)save_iocb, (uint8_t *)cmdiocb,

drivers/scsi/lpfc/lpfc_nportdisc.c

587

(uint8_t *)sp, login_mbox, ndlp->nlp_rpi);

drivers/scsi/lpfc/lpfc_nportdisc.c

956

npr = (PRLI *)((uint8_t *)payload + sizeof(uint32_t));

drivers/scsi/lpfc/lpfc_nvme.c

396

uint32_t tmo, uint8_t retry)

drivers/scsi/lpfc/lpfc_nvmet.c

2384

uint8_t cqflag)

drivers/scsi/lpfc/lpfc_nvmet.c

2549

uint8_t cqflag)

drivers/scsi/lpfc/lpfc_scsi.c

1369

uint8_t *txop, uint8_t *rxop)

drivers/scsi/lpfc/lpfc_scsi.c

1371

uint8_t ret = 0;

drivers/scsi/lpfc/lpfc_scsi.c

1449

uint8_t *txop, uint8_t *rxop)

drivers/scsi/lpfc/lpfc_scsi.c

1553

uint8_t txop, rxop;

drivers/scsi/lpfc/lpfc_scsi.c

1702

uint8_t txop, rxop;

drivers/scsi/lpfc/lpfc_scsi.c

1933

uint8_t txop, rxop;

drivers/scsi/lpfc/lpfc_scsi.c

2122

uint8_t txop, rxop;

drivers/scsi/lpfc/lpfc_scsi.c

2659

lpfc_bg_crc(uint8_t *data, int count)

drivers/scsi/lpfc/lpfc_scsi.c

2675

lpfc_bg_csum(uint8_t *data, int count)

drivers/scsi/lpfc/lpfc_scsi.c

2694

uint8_t *data_src = NULL;

drivers/scsi/lpfc/lpfc_scsi.c

2732

data_src = (uint8_t *)sg_virt(sgde);

drivers/scsi/lpfc/lpfc_scsi.c

2804

data_src = (uint8_t *)sg_virt(sgde);

drivers/scsi/lpfc/lpfc_scsi.c

3553

uint8_t tmo)

drivers/scsi/lpfc/lpfc_scsi.c

4614

uint8_t tmo)

drivers/scsi/lpfc/lpfc_scsi.c

4691

uint8_t tmo)

drivers/scsi/lpfc/lpfc_scsi.c

4981

lpfc_scsi_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)

drivers/scsi/lpfc/lpfc_scsi.c

5688

lpfc_taskmgmt_name(uint8_t task_mgmt_cmd)

drivers/scsi/lpfc/lpfc_scsi.c

5728

uint8_t rsp_info_code;

drivers/scsi/lpfc/lpfc_scsi.c

5800

uint8_t task_mgmt_cmd)

drivers/scsi/lpfc/lpfc_scsi.c

6657

struct lpfc_name *target_wwpn, uint64_t lun, uint8_t pri)

drivers/scsi/lpfc/lpfc_scsi.c

6717

struct lpfc_name *target_wwpn, uint64_t lun, uint8_t pri)

drivers/scsi/lpfc/lpfc_scsi.h

121

uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

122

uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */

drivers/scsi/lpfc/lpfc_scsi.h

123

uint8_t fcpCntl2; /* FCP_CTL byte 2 task management codes */

drivers/scsi/lpfc/lpfc_scsi.h

124

uint8_t fcpCntl3;

drivers/scsi/lpfc/lpfc_scsi.h

126

uint8_t fcpCdb[LPFC_FCP_CDB_LEN]; /* SRB cdb field is copied here */

drivers/scsi/lpfc/lpfc_scsi.h

133

uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

134

uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */

drivers/scsi/lpfc/lpfc_scsi.h

135

uint8_t fcpCntl2; /* FCP_CTL byte 2 task management codes */

drivers/scsi/lpfc/lpfc_scsi.h

136

uint8_t fcpCntl3;

drivers/scsi/lpfc/lpfc_scsi.h

138

uint8_t fcpCdb[LPFC_FCP_CDB_LEN_32]; /* SRB cdb field is copied here */

drivers/scsi/lpfc/lpfc_scsi.h

57

uint8_t priority;

drivers/scsi/lpfc/lpfc_scsi.h

66

uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

67

uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

68

uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */

drivers/scsi/lpfc/lpfc_scsi.h

73

uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */

drivers/scsi/lpfc/lpfc_scsi.h

83

uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

84

uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

85

uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */

drivers/scsi/lpfc/lpfc_scsi.h

86

uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */

drivers/scsi/lpfc/lpfc_scsi.h

98

uint8_t rspSnsInfo[128];

drivers/scsi/lpfc/lpfc_sli.c

10388

lpfc_mbox_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)

drivers/scsi/lpfc/lpfc_sli.c

11264

lpfc_sli_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)

drivers/scsi/lpfc/lpfc_sli.c

1565

lpfc_sli_iocb_cmd_type(uint8_t iocb_cmnd)

drivers/scsi/lpfc/lpfc_sli.c

15774

__lpfc_sli4_switch_eqmode(struct lpfc_queue *eq, uint8_t mode)

drivers/scsi/lpfc/lpfc_sli.c

15981

lpfc_dpp_wc_map(struct lpfc_hba *phba, uint8_t dpp_barset)

drivers/scsi/lpfc/lpfc_sli.c

16966

uint8_t dpp_barset;

drivers/scsi/lpfc/lpfc_sli.c

16968

uint8_t wq_create_version;

drivers/scsi/lpfc/lpfc_sli.c

18823

uint8_t found = 0;

drivers/scsi/lpfc/lpfc_sli.c

20093

uint8_t *bytep;

drivers/scsi/lpfc/lpfc_sli.c

20738

lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,

drivers/scsi/lpfc/lpfc_sli.c

20807

uint8_t *rgn23_data = NULL;

drivers/scsi/lpfc/lpfc_sli.c

21024

sprintf((uint8_t *)wr_object->u.request.object_name, "/");

drivers/scsi/lpfc/lpfc_sli.c

21117

uint8_t restart_loop;

drivers/scsi/lpfc/lpfc_sli.c

22583

tmp->fcp_rsp = (struct fcp_rsp *)((uint8_t *)tmp->fcp_cmnd +

drivers/scsi/lpfc/lpfc_sli.c

273

uint8_t *tmp;

drivers/scsi/lpfc/lpfc_sli.c

2737

lpfc_sli_chk_mbx_command(uint8_t mbxCommand)

drivers/scsi/lpfc/lpfc_sli.c

2739

uint8_t ret;

drivers/scsi/lpfc/lpfc_sli.c

299

tmp = (uint8_t *)temp_wqe;

drivers/scsi/lpfc/lpfc_sli.c

4116

memcpy(&adaptermsg[0], (uint8_t *) irsp,

drivers/scsi/lpfc/lpfc_sli.c

4319

memcpy(&adaptermsg[0], (uint8_t *)&rspiocbp->wqe,

drivers/scsi/lpfc/lpfc_sli.c

4884

uint8_t hdrtype;

drivers/scsi/lpfc/lpfc_sli.c

5889

uint8_t *vpd, uint32_t *vpd_size)

drivers/scsi/lpfc/lpfc_sli.c

73

uint8_t *, uint32_t *);

drivers/scsi/lpfc/lpfc_sli.c

8526

uint8_t *vpd;

drivers/scsi/lpfc/lpfc_sli.c

9224

uint8_t qe_valid;

drivers/scsi/lpfc/lpfc_sli.c

9621

= (uint8_t *)phba->mbox_ext

drivers/scsi/lpfc/lpfc_sli.c

9622

- (uint8_t *)phba->mbox;

drivers/scsi/lpfc/lpfc_sli.c

9628

(uint8_t *)phba->mbox_ext,

drivers/scsi/lpfc/lpfc_sli.h

210

uint8_t mbox_flag;

drivers/scsi/lpfc/lpfc_sli.h

213

uint8_t mbox_offset_word;

drivers/scsi/lpfc/lpfc_sli.h

231

uint8_t profile; /* profile associated with ring */

drivers/scsi/lpfc/lpfc_sli.h

232

uint8_t rctl; /* rctl / type pair configured for ring */

drivers/scsi/lpfc/lpfc_sli.h

233

uint8_t type; /* rctl / type pair configured for ring */

drivers/scsi/lpfc/lpfc_sli.h

234

uint8_t rsvd;

drivers/scsi/lpfc/lpfc_sli.h

279

uint8_t rsvd;

drivers/scsi/lpfc/lpfc_sli.h

280

uint8_t ringno; /* ring number */

drivers/scsi/lpfc/lpfc_sli.h

46

uint8_t cs_ctl_vmid;

drivers/scsi/lpfc/lpfc_sli4.h

1046

uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];

drivers/scsi/lpfc/lpfc_sli4.h

1047

uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];

drivers/scsi/lpfc/lpfc_sli4.h

1052

uint8_t sub_command;

drivers/scsi/lpfc/lpfc_sli4.h

1053

uint8_t type;

drivers/scsi/lpfc/lpfc_sli4.h

1054

uint8_t capability;

drivers/scsi/lpfc/lpfc_sli4.h

1055

uint8_t frequency;

drivers/scsi/lpfc/lpfc_sli4.h

1069

int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,

drivers/scsi/lpfc/lpfc_sli4.h

1070

uint8_t, uint32_t, bool);

drivers/scsi/lpfc/lpfc_sli4.h

1170

uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);

drivers/scsi/lpfc/lpfc_sli4.h

1171

uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);

drivers/scsi/lpfc/lpfc_sli4.h

166

uint8_t qe_valid;

drivers/scsi/lpfc/lpfc_sli4.h

167

uint8_t mode; /* interrupt or polling */

drivers/scsi/lpfc/lpfc_sli4.h

231

uint8_t db_format;

drivers/scsi/lpfc/lpfc_sli4.h

234

uint8_t q_flag;

drivers/scsi/lpfc/lpfc_sli4.h

287

uint8_t duplex;

drivers/scsi/lpfc/lpfc_sli4.h

288

uint8_t status;

drivers/scsi/lpfc/lpfc_sli4.h

289

uint8_t type;

drivers/scsi/lpfc/lpfc_sli4.h

290

uint8_t number;

drivers/scsi/lpfc/lpfc_sli4.h

291

uint8_t fault;

drivers/scsi/lpfc/lpfc_sli4.h

292

uint8_t link_status;

drivers/scsi/lpfc/lpfc_sli4.h

298

uint8_t fabric_name[8];

drivers/scsi/lpfc/lpfc_sli4.h

299

uint8_t switch_name[8];

drivers/scsi/lpfc/lpfc_sli4.h

300

uint8_t mac_addr[6];

drivers/scsi/lpfc/lpfc_sli4.h

365

uint8_t type;

drivers/scsi/lpfc/lpfc_sli4.h

367

uint8_t length;

drivers/scsi/lpfc/lpfc_sli4.h

369

uint8_t parm_version;

drivers/scsi/lpfc/lpfc_sli4.h

371

uint8_t parm_flags;

drivers/scsi/lpfc/lpfc_sli4.h

381

uint8_t fc_map[3];

drivers/scsi/lpfc/lpfc_sli4.h

382

uint8_t reserved1;

drivers/scsi/lpfc/lpfc_sli4.h

384

uint8_t reserved[2];

drivers/scsi/lpfc/lpfc_sli4.h

388

uint8_t type;

drivers/scsi/lpfc/lpfc_sli4.h

390

uint8_t length; /* words */

drivers/scsi/lpfc/lpfc_sli4.h

391

uint8_t reserved[2];

drivers/scsi/lpfc/lpfc_sli4.h

407

uint8_t fabric_name[8];

drivers/scsi/lpfc/lpfc_sli4.h

408

uint8_t switch_name[8];

drivers/scsi/lpfc/lpfc_sli4.h

558

uint8_t mi_cap;

drivers/scsi/lpfc/lpfc_sli4.h

559

uint8_t mib_bde_cnt;

drivers/scsi/lpfc/lpfc_sli4.h

560

uint8_t cmf;

drivers/scsi/lpfc/lpfc_sli4.h

561

uint8_t cqv;

drivers/scsi/lpfc/lpfc_sli4.h

562

uint8_t mqv;

drivers/scsi/lpfc/lpfc_sli4.h

563

uint8_t wqv;

drivers/scsi/lpfc/lpfc_sli4.h

564

uint8_t rqv;

drivers/scsi/lpfc/lpfc_sli4.h

565

uint8_t eqav;

drivers/scsi/lpfc/lpfc_sli4.h

566

uint8_t cqav;

drivers/scsi/lpfc/lpfc_sli4.h

567

uint8_t wqsize;

drivers/scsi/lpfc/lpfc_sli4.h

568

uint8_t bv1s;

drivers/scsi/lpfc/lpfc_sli4.h

569

uint8_t pls;

drivers/scsi/lpfc/lpfc_sli4.h

572

uint8_t wqpcnt;

drivers/scsi/lpfc/lpfc_sli4.h

573

uint8_t nvme;

drivers/scsi/lpfc/lpfc_sli4.h

589

uint8_t lnk_dv;

drivers/scsi/lpfc/lpfc_sli4.h

592

uint8_t lnk_tp;

drivers/scsi/lpfc/lpfc_sli4.h

596

uint8_t lnk_no;

drivers/scsi/lpfc/lpfc_sli4.h

597

uint8_t optic_state;

drivers/scsi/lpfc/lpfc_sli4.h

876

uint8_t oas_next_tgt_wwpn[8];

drivers/scsi/lpfc/lpfc_sli4.h

877

uint8_t oas_next_vpt_wwpn[8];

drivers/scsi/lpfc/lpfc_sli4.h

991

uint8_t flash_id;

drivers/scsi/lpfc/lpfc_sli4.h

992

uint8_t asic_rev;

drivers/scsi/lpfc/lpfc_vport.h

34

uint8_t linktype;

drivers/scsi/lpfc/lpfc_vport.h

38

uint8_t state;

drivers/scsi/lpfc/lpfc_vport.h

43

uint8_t fail_reason;

drivers/scsi/lpfc/lpfc_vport.h

44

uint8_t prev_fail_reason;

drivers/scsi/lpfc/lpfc_vport.h

52

uint8_t node_name[8]; /* WWNN */

drivers/scsi/lpfc/lpfc_vport.h

53

uint8_t port_name[8]; /* WWPN */

drivers/scsi/lpfc/lpfc_vport.h

72

uint8_t node_name[8]; /* WWNN */

drivers/scsi/lpfc/lpfc_vport.h

73

uint8_t port_name[8]; /* WWPN */

drivers/scsi/megaraid/mbox_defs.h

158

uint8_t cmd;

drivers/scsi/megaraid/mbox_defs.h

159

uint8_t cmdid;

drivers/scsi/megaraid/mbox_defs.h

163

uint8_t logdrv;

drivers/scsi/megaraid/mbox_defs.h

164

uint8_t numsge;

drivers/scsi/megaraid/mbox_defs.h

165

uint8_t resvd;

drivers/scsi/megaraid/mbox_defs.h

166

uint8_t busy;

drivers/scsi/megaraid/mbox_defs.h

167

uint8_t numstatus;

drivers/scsi/megaraid/mbox_defs.h

168

uint8_t status;

drivers/scsi/megaraid/mbox_defs.h

169

uint8_t completed[MBOX_MAX_FIRMWARE_STATUS];

drivers/scsi/megaraid/mbox_defs.h

170

uint8_t poll;

drivers/scsi/megaraid/mbox_defs.h

171

uint8_t ack;

drivers/scsi/megaraid/mbox_defs.h

227

uint8_t timeout :3;

drivers/scsi/megaraid/mbox_defs.h

228

uint8_t ars :1;

drivers/scsi/megaraid/mbox_defs.h

229

uint8_t reserved :3;

drivers/scsi/megaraid/mbox_defs.h

230

uint8_t islogical :1;

drivers/scsi/megaraid/mbox_defs.h

231

uint8_t logdrv;

drivers/scsi/megaraid/mbox_defs.h

232

uint8_t channel;

drivers/scsi/megaraid/mbox_defs.h

233

uint8_t target;

drivers/scsi/megaraid/mbox_defs.h

234

uint8_t queuetag;

drivers/scsi/megaraid/mbox_defs.h

235

uint8_t queueaction;

drivers/scsi/megaraid/mbox_defs.h

236

uint8_t cdb[10];

drivers/scsi/megaraid/mbox_defs.h

237

uint8_t cdblen;

drivers/scsi/megaraid/mbox_defs.h

238

uint8_t reqsenselen;

drivers/scsi/megaraid/mbox_defs.h

239

uint8_t reqsensearea[MAX_REQ_SENSE_LEN];

drivers/scsi/megaraid/mbox_defs.h

240

uint8_t numsge;

drivers/scsi/megaraid/mbox_defs.h

241

uint8_t scsistatus;

drivers/scsi/megaraid/mbox_defs.h

279

uint8_t timeout :3;

drivers/scsi/megaraid/mbox_defs.h

280

uint8_t ars :1;

drivers/scsi/megaraid/mbox_defs.h

281

uint8_t rsvd1 :1;

drivers/scsi/megaraid/mbox_defs.h

282

uint8_t cd_rom :1;

drivers/scsi/megaraid/mbox_defs.h

283

uint8_t rsvd2 :1;

drivers/scsi/megaraid/mbox_defs.h

284

uint8_t islogical :1;

drivers/scsi/megaraid/mbox_defs.h

285

uint8_t logdrv;

drivers/scsi/megaraid/mbox_defs.h

286

uint8_t channel;

drivers/scsi/megaraid/mbox_defs.h

287

uint8_t target;

drivers/scsi/megaraid/mbox_defs.h

288

uint8_t queuetag;

drivers/scsi/megaraid/mbox_defs.h

289

uint8_t queueaction;

drivers/scsi/megaraid/mbox_defs.h

290

uint8_t cdblen;

drivers/scsi/megaraid/mbox_defs.h

291

uint8_t rsvd3;

drivers/scsi/megaraid/mbox_defs.h

292

uint8_t cdb[16];

drivers/scsi/megaraid/mbox_defs.h

293

uint8_t numsge;

drivers/scsi/megaraid/mbox_defs.h

294

uint8_t status;

drivers/scsi/megaraid/mbox_defs.h

295

uint8_t reqsenselen;

drivers/scsi/megaraid/mbox_defs.h

296

uint8_t reqsensearea[MAX_REQ_SENSE_LEN];

drivers/scsi/megaraid/mbox_defs.h

297

uint8_t rsvd4;

drivers/scsi/megaraid/mbox_defs.h

332

uint8_t fw_version[16];

drivers/scsi/megaraid/mbox_defs.h

333

uint8_t bios_version[16];

drivers/scsi/megaraid/mbox_defs.h

334

uint8_t product_name[80];

drivers/scsi/megaraid/mbox_defs.h

335

uint8_t max_commands;

drivers/scsi/megaraid/mbox_defs.h

336

uint8_t nchannels;

drivers/scsi/megaraid/mbox_defs.h

337

uint8_t fc_loop_present;

drivers/scsi/megaraid/mbox_defs.h

338

uint8_t mem_type;

drivers/scsi/megaraid/mbox_defs.h

343

uint8_t notify_counters;

drivers/scsi/megaraid/mbox_defs.h

344

uint8_t pad1k[889];

drivers/scsi/megaraid/mbox_defs.h

387

uint8_t param_counter;

drivers/scsi/megaraid/mbox_defs.h

388

uint8_t param_id;

drivers/scsi/megaraid/mbox_defs.h

390

uint8_t write_config_counter;

drivers/scsi/megaraid/mbox_defs.h

391

uint8_t write_config_rsvd[3];

drivers/scsi/megaraid/mbox_defs.h

392

uint8_t ldrv_op_counter;

drivers/scsi/megaraid/mbox_defs.h

393

uint8_t ldrv_opid;

drivers/scsi/megaraid/mbox_defs.h

394

uint8_t ldrv_opcmd;

drivers/scsi/megaraid/mbox_defs.h

395

uint8_t ldrv_opstatus;

drivers/scsi/megaraid/mbox_defs.h

396

uint8_t ldrv_state_counter;

drivers/scsi/megaraid/mbox_defs.h

397

uint8_t ldrv_state_id;

drivers/scsi/megaraid/mbox_defs.h

398

uint8_t ldrv_state_new;

drivers/scsi/megaraid/mbox_defs.h

399

uint8_t ldrv_state_old;

drivers/scsi/megaraid/mbox_defs.h

400

uint8_t pdrv_state_counter;

drivers/scsi/megaraid/mbox_defs.h

401

uint8_t pdrv_state_id;

drivers/scsi/megaraid/mbox_defs.h

402

uint8_t pdrv_state_new;

drivers/scsi/megaraid/mbox_defs.h

403

uint8_t pdrv_state_old;

drivers/scsi/megaraid/mbox_defs.h

404

uint8_t pdrv_fmt_counter;

drivers/scsi/megaraid/mbox_defs.h

405

uint8_t pdrv_fmt_id;

drivers/scsi/megaraid/mbox_defs.h

406

uint8_t pdrv_fmt_val;

drivers/scsi/megaraid/mbox_defs.h

407

uint8_t pdrv_fmt_rsvd;

drivers/scsi/megaraid/mbox_defs.h

408

uint8_t targ_xfer_counter;

drivers/scsi/megaraid/mbox_defs.h

409

uint8_t targ_xfer_id;

drivers/scsi/megaraid/mbox_defs.h

410

uint8_t targ_xfer_val;

drivers/scsi/megaraid/mbox_defs.h

411

uint8_t targ_xfer_rsvd;

drivers/scsi/megaraid/mbox_defs.h

412

uint8_t fcloop_id_chg_counter;

drivers/scsi/megaraid/mbox_defs.h

413

uint8_t fcloopid_pdrvid;

drivers/scsi/megaraid/mbox_defs.h

414

uint8_t fcloop_id0;

drivers/scsi/megaraid/mbox_defs.h

415

uint8_t fcloop_id1;

drivers/scsi/megaraid/mbox_defs.h

416

uint8_t fcloop_state_counter;

drivers/scsi/megaraid/mbox_defs.h

417

uint8_t fcloop_state0;

drivers/scsi/megaraid/mbox_defs.h

418

uint8_t fcloop_state1;

drivers/scsi/megaraid/mbox_defs.h

419

uint8_t fcloop_state_rsvd;

drivers/scsi/megaraid/mbox_defs.h

453

uint8_t notify_rsvd[MAX_NOTIFY_SIZE - CUR_NOTIFY_SIZE];

drivers/scsi/megaraid/mbox_defs.h

455

uint8_t rebuild_rate;

drivers/scsi/megaraid/mbox_defs.h

456

uint8_t cache_flush_int;

drivers/scsi/megaraid/mbox_defs.h

457

uint8_t sense_alert;

drivers/scsi/megaraid/mbox_defs.h

458

uint8_t drive_insert_count;

drivers/scsi/megaraid/mbox_defs.h

460

uint8_t battery_status;

drivers/scsi/megaraid/mbox_defs.h

461

uint8_t num_ldrv;

drivers/scsi/megaraid/mbox_defs.h

462

uint8_t recon_state[MAX_LOGICAL_DRIVES_40LD / 8];

drivers/scsi/megaraid/mbox_defs.h

466

uint8_t ldrv_prop[MAX_LOGICAL_DRIVES_40LD];

drivers/scsi/megaraid/mbox_defs.h

467

uint8_t ldrv_state[MAX_LOGICAL_DRIVES_40LD];

drivers/scsi/megaraid/mbox_defs.h

468

uint8_t pdrv_state[FC_MAX_PHYSICAL_DEVICES];

drivers/scsi/megaraid/mbox_defs.h

471

uint8_t targ_xfer[80];

drivers/scsi/megaraid/mbox_defs.h

472

uint8_t pad1k[263];

drivers/scsi/megaraid/mbox_defs.h

507

uint8_t max_commands;

drivers/scsi/megaraid/mbox_defs.h

508

uint8_t rebuild_rate;

drivers/scsi/megaraid/mbox_defs.h

509

uint8_t max_targ_per_chan;

drivers/scsi/megaraid/mbox_defs.h

510

uint8_t nchannels;

drivers/scsi/megaraid/mbox_defs.h

511

uint8_t fw_version[4];

drivers/scsi/megaraid/mbox_defs.h

513

uint8_t chip_set_value;

drivers/scsi/megaraid/mbox_defs.h

514

uint8_t dram_size;

drivers/scsi/megaraid/mbox_defs.h

515

uint8_t cache_flush_interval;

drivers/scsi/megaraid/mbox_defs.h

516

uint8_t bios_version[4];

drivers/scsi/megaraid/mbox_defs.h

517

uint8_t board_type;

drivers/scsi/megaraid/mbox_defs.h

518

uint8_t sense_alert;

drivers/scsi/megaraid/mbox_defs.h

519

uint8_t write_config_count;

drivers/scsi/megaraid/mbox_defs.h

520

uint8_t battery_status;

drivers/scsi/megaraid/mbox_defs.h

521

uint8_t dec_fault_bus_info;

drivers/scsi/megaraid/mbox_defs.h

534

uint8_t nldrv;

drivers/scsi/megaraid/mbox_defs.h

535

uint8_t rsvd[3];

drivers/scsi/megaraid/mbox_defs.h

537

uint8_t prop[MAX_LOGICAL_DRIVES_8LD];

drivers/scsi/megaraid/mbox_defs.h

538

uint8_t state[MAX_LOGICAL_DRIVES_8LD];

drivers/scsi/megaraid/mbox_defs.h

547

uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];

drivers/scsi/megaraid/mbox_defs.h

548

uint8_t rsvd;

drivers/scsi/megaraid/mbox_defs.h

577

uint8_t stack_attn;

drivers/scsi/megaraid/mbox_defs.h

578

uint8_t modem_status;

drivers/scsi/megaraid/mbox_defs.h

579

uint8_t rsvd[2];

drivers/scsi/megaraid/mbox_defs.h

589

uint8_t channel;

drivers/scsi/megaraid/mbox_defs.h

590

uint8_t target;

drivers/scsi/megaraid/mbox_defs.h

631

uint8_t span_depth;

drivers/scsi/megaraid/mbox_defs.h

632

uint8_t level;

drivers/scsi/megaraid/mbox_defs.h

633

uint8_t read_ahead;

drivers/scsi/megaraid/mbox_defs.h

634

uint8_t stripe_sz;

drivers/scsi/megaraid/mbox_defs.h

635

uint8_t status;

drivers/scsi/megaraid/mbox_defs.h

636

uint8_t write_mode;

drivers/scsi/megaraid/mbox_defs.h

637

uint8_t direct_io;

drivers/scsi/megaraid/mbox_defs.h

638

uint8_t row_size;

drivers/scsi/megaraid/mbox_defs.h

688

uint8_t type;

drivers/scsi/megaraid/mbox_defs.h

689

uint8_t cur_status;

drivers/scsi/megaraid/mbox_defs.h

690

uint8_t tag_depth;

drivers/scsi/megaraid/mbox_defs.h

691

uint8_t sync_neg;

drivers/scsi/megaraid/mbox_defs.h

704

uint8_t numldrv;

drivers/scsi/megaraid/mbox_defs.h

705

uint8_t resvd[3];

drivers/scsi/megaraid/mbox_defs.h

721

uint8_t numldrv;

drivers/scsi/megaraid/mbox_defs.h

722

uint8_t resvd[3];

drivers/scsi/megaraid/mbox_defs.h

738

uint8_t numldrv;

drivers/scsi/megaraid/mbox_defs.h

739

uint8_t resvd[3];

drivers/scsi/megaraid/mbox_defs.h

755

uint8_t geometry :4;

drivers/scsi/megaraid/mbox_defs.h

756

uint8_t unused :4;

drivers/scsi/megaraid/mbox_defs.h

757

uint8_t boot_drv;

drivers/scsi/megaraid/mbox_defs.h

758

uint8_t rsvd[12];

drivers/scsi/megaraid/mega_common.h

156

uint8_t quiescent;

drivers/scsi/megaraid/mega_common.h

169

uint8_t max_channel;

drivers/scsi/megaraid/mega_common.h

171

uint8_t max_lun;

drivers/scsi/megaraid/mega_common.h

175

uint8_t ito;

drivers/scsi/megaraid/mega_common.h

182

uint8_t fw_version[VERSION_SIZE];

drivers/scsi/megaraid/mega_common.h

183

uint8_t bios_version[VERSION_SIZE];

drivers/scsi/megaraid/mega_common.h

184

uint8_t max_cdb_sz;

drivers/scsi/megaraid/mega_common.h

185

uint8_t ha;

drivers/scsi/megaraid/megaraid_ioctl.h

118

uint8_t signature[EXT_IOCTL_SIGN_SZ];

drivers/scsi/megaraid/megaraid_ioctl.h

127

uint8_t reserved[128];

drivers/scsi/megaraid/megaraid_ioctl.h

147

uint8_t free_buf;

drivers/scsi/megaraid/megaraid_ioctl.h

149

uint8_t timedout;

drivers/scsi/megaraid/megaraid_ioctl.h

185

uint8_t pci_bus;

drivers/scsi/megaraid/megaraid_ioctl.h

186

uint8_t pci_dev_fn;

drivers/scsi/megaraid/megaraid_ioctl.h

187

uint8_t pci_slot;

drivers/scsi/megaraid/megaraid_ioctl.h

188

uint8_t irq;

drivers/scsi/megaraid/megaraid_ioctl.h

193

uint8_t num_ldrv;

drivers/scsi/megaraid/megaraid_ioctl.h

214

uint8_t irq;

drivers/scsi/megaraid/megaraid_ioctl.h

215

uint8_t numldrv;

drivers/scsi/megaraid/megaraid_ioctl.h

216

uint8_t pcibus;

drivers/scsi/megaraid/megaraid_ioctl.h

218

uint8_t pcifun;

drivers/scsi/megaraid/megaraid_ioctl.h

221

uint8_t pcislot;

drivers/scsi/megaraid/megaraid_ioctl.h

243

uint8_t in_use;

drivers/scsi/megaraid/megaraid_ioctl.h

277

uint8_t max_kioc;

drivers/scsi/megaraid/megaraid_mbox.c

1047

ccb->raw_mbox = (uint8_t *)ccb->mbox;

drivers/scsi/megaraid/megaraid_mbox.c

1941

uint8_t channel;

drivers/scsi/megaraid/megaraid_mbox.c

1942

uint8_t target;

drivers/scsi/megaraid/megaraid_mbox.c

1990

uint8_t channel;

drivers/scsi/megaraid/megaraid_mbox.c

1991

uint8_t target;

drivers/scsi/megaraid/megaraid_mbox.c

2039

uint8_t nstatus;

drivers/scsi/megaraid/megaraid_mbox.c

2040

uint8_t completed[MBOX_MAX_FIRMWARE_STATUS];

drivers/scsi/megaraid/megaraid_mbox.c

2189

uint8_t c;

drivers/scsi/megaraid/megaraid_mbox.c

2525

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

2669

mbox_post_sync_cmd(adapter_t *adapter, uint8_t raw_mbox[])

drivers/scsi/megaraid/megaraid_mbox.c

2673

uint8_t status;

drivers/scsi/megaraid/megaraid_mbox.c

2799

mbox_post_sync_cmd_fast(adapter_t *adapter, uint8_t raw_mbox[])

drivers/scsi/megaraid/megaraid_mbox.c

2878

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3000

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3036

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3055

*init_id = *(uint8_t *)adapter->ibuf;

drivers/scsi/megaraid/megaraid_mbox.c

3078

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3128

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3145

nsg = *(uint8_t *)adapter->ibuf;

drivers/scsi/megaraid/megaraid_mbox.c

3169

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3187

raid_dev->channel_class = *(uint8_t *)adapter->ibuf;

drivers/scsi/megaraid/megaraid_mbox.c

3203

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3233

uint8_t raw_mbox[sizeof(mbox_t)];

drivers/scsi/megaraid/megaraid_mbox.c

3355

uint8_t c;

drivers/scsi/megaraid/megaraid_mbox.c

3356

uint8_t t;

drivers/scsi/megaraid/megaraid_mbox.c

3436

ccb->raw_mbox = (uint8_t *)ccb->mbox;

drivers/scsi/megaraid/megaraid_mbox.c

3559

uint8_t *raw_mbox;

drivers/scsi/megaraid/megaraid_mbox.c

3588

raw_mbox = (uint8_t *)&mbox64->mbox32;

drivers/scsi/megaraid/megaraid_mbox.c

3683

uint8_t *raw_mbox;

drivers/scsi/megaraid/megaraid_mbox.c

3689

raw_mbox = (uint8_t *)&mbox64->mbox32;

drivers/scsi/megaraid/megaraid_mbox.c

97

static int mbox_post_sync_cmd(adapter_t *, uint8_t []);

drivers/scsi/megaraid/megaraid_mbox.c

98

static int mbox_post_sync_cmd_fast(adapter_t *, uint8_t []);

drivers/scsi/megaraid/megaraid_mbox.h

129

uint8_t *raw_mbox;

drivers/scsi/megaraid/megaraid_mbox.h

203

uint8_t pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];

drivers/scsi/megaraid/megaraid_mbox.h

207

uint8_t channel_class;

drivers/scsi/megaraid/megaraid_mm.c

109

uint8_t old_ioctl;

drivers/scsi/megaraid/megaraid_mm.c

281

handle_drvrcmd(void __user *arg, uint8_t old_ioctl, int *rval)

drivers/scsi/megaraid/megaraid_mm.c

285

uint8_t opcode;

drivers/scsi/megaraid/megaraid_mm.c

286

uint8_t subopcode;

drivers/scsi/megaraid/megaraid_mm.c

31

static int handle_drvrcmd(void __user *, uint8_t, int *);

drivers/scsi/megaraid/megaraid_mm.c

360

uint8_t opcode;

drivers/scsi/megaraid/megaraid_mm.c

361

uint8_t subopcode;

drivers/scsi/megaraid/megaraid_mm.c

807

uint8_t opcode;

drivers/scsi/megaraid/megaraid_mm.c

808

uint8_t subopcode;

drivers/scsi/megaraid/megaraid_mm.c

854

sizeof(uint8_t))) {

drivers/scsi/megaraid/megaraid_mm.c

867

&mbox64->mbox32.status, sizeof(uint8_t))) {

drivers/scsi/megaraid/megaraid_mm.h

66

uint8_t fca[16];

drivers/scsi/megaraid/megaraid_mm.h

68

uint8_t opcode;

drivers/scsi/megaraid/megaraid_mm.h

69

uint8_t subopcode;

drivers/scsi/megaraid/megaraid_mm.h

72

uint8_t __user *buffer;

drivers/scsi/megaraid/megaraid_mm.h

73

uint8_t pad[4];

drivers/scsi/megaraid/megaraid_mm.h

76

uint8_t __user *buffer;

drivers/scsi/megaraid/megaraid_mm.h

82

uint8_t mbox[18]; /* 16 bytes + 2 status bytes */

drivers/scsi/mpi3mr/mpi3mr_app.c

3240

uint8_t adp_state;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

196

uint8_t driver_version[MPT2_IOCTL_VERSION_LENGTH];

drivers/scsi/mpt3sas/mpt3sas_ctl.h

197

uint8_t rsvd1;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

198

uint8_t scsi_id;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

199

uint8_t driver_capability;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

200

uint8_t rsvd2;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

242

uint8_t data[MPT3_EVENT_DATA_SIZE];

drivers/scsi/mpt3sas/mpt3sas_ctl.h

284

uint8_t mf[1];

drivers/scsi/mpt3sas/mpt3sas_ctl.h

300

uint8_t mf[1];

drivers/scsi/mpt3sas/mpt3sas_ctl.h

356

uint8_t reserved;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

357

uint8_t buffer_type;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

396

uint8_t reserved;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

397

uint8_t buffer_type;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

435

uint8_t status;

drivers/scsi/mpt3sas/mpt3sas_ctl.h

436

uint8_t reserved;

drivers/scsi/qedf/qedf.h

114

uint8_t tm_flags;

drivers/scsi/qedf/qedf.h

154

uint8_t *sense_buffer;

drivers/scsi/qedf/qedf.h

287

uint8_t direction;

drivers/scsi/qedf/qedf.h

292

uint8_t lba[4];

drivers/scsi/qedf/qedf.h

407

uint8_t *grcdump;

drivers/scsi/qedf/qedf_dbg.c

117

qedf_free_grc_dump_buf(uint8_t **buf)

drivers/scsi/qedf/qedf_dbg.h

106

extern int qedf_alloc_grc_dump_buf(uint8_t **buf, uint32_t len);

drivers/scsi/qedf/qedf_dbg.h

107

extern void qedf_free_grc_dump_buf(uint8_t **buf);

drivers/scsi/qedf/qedf_dbg.h

109

const struct qed_common_ops *common, uint8_t **buf,

drivers/scsi/qedf/qedf_io.c

1058

uint8_t *rsp_info, *sense_data;

drivers/scsi/qedf/qedf_io.c

2287

uint8_t tm_flags)

drivers/scsi/qla1280.c

1111

uint8_t mr;

drivers/scsi/qla1280.c

1716

uint8_t *sp, *tbuf;

drivers/scsi/qla1280.c

1787

sp = (uint8_t *)ha->request_ring;

drivers/scsi/qla1280.c

2415

qla1280_mailbox_command(struct scsi_qla_host *ha, uint8_t mr, uint16_t *mb)

drivers/scsi/qla1280.c

2709

pkt->lun = (uint8_t) lun;

drivers/scsi/qla1280.c

2710

pkt->target = (uint8_t) (bus ? (id | BIT_7) : id);

drivers/scsi/qla1280.c

2814

pkt->entry_count = (uint8_t) req_cnt;

drivers/scsi/qla1280.c

2815

pkt->sys_define = (uint8_t) ha->req_ring_index;

drivers/scsi/qla1280.c

2910

(uint8_t)ha->req_ring_index;

drivers/scsi/qla1280.c

3069

pkt->entry_count = (uint8_t) req_cnt;

drivers/scsi/qla1280.c

3070

pkt->sys_define = (uint8_t) ha->req_ring_index;

drivers/scsi/qla1280.c

3156

(uint8_t) ha->req_ring_index;

drivers/scsi/qla1280.c

3267

pkt->sys_define = (uint8_t) ha->req_ring_index;

drivers/scsi/qla1280.c

3559

uint8_t bus;

drivers/scsi/qla1280.c

403

uint8_t, uint16_t *);

drivers/scsi/qla1280.c

575

uint8_t chksum;

drivers/scsi/qla1280.h

100

uint8_t dir; /* direction of transfer */

drivers/scsi/qla1280.h

1019

uint8_t devnum;

drivers/scsi/qla1280.h

1020

uint8_t revision;

drivers/scsi/qla1280.h

1021

uint8_t ports;

drivers/scsi/qla1280.h

335

uint8_t id0; /* 0 */

drivers/scsi/qla1280.h

336

uint8_t id1; /* 1 */

drivers/scsi/qla1280.h

337

uint8_t id2; /* 2 */

drivers/scsi/qla1280.h

338

uint8_t id3; /* 3 */

drivers/scsi/qla1280.h

339

uint8_t version; /* 4 */

drivers/scsi/qla1280.h

342

uint8_t bios_configuration_mode:2;

drivers/scsi/qla1280.h

343

uint8_t bios_disable:1;

drivers/scsi/qla1280.h

344

uint8_t selectable_scsi_boot_enable:1;

drivers/scsi/qla1280.h

345

uint8_t cd_rom_boot_enable:1;

drivers/scsi/qla1280.h

346

uint8_t disable_loading_risc_code:1;

drivers/scsi/qla1280.h

347

uint8_t enable_64bit_addressing:1;

drivers/scsi/qla1280.h

348

uint8_t unused_7:1;

drivers/scsi/qla1280.h

352

uint8_t boot_lun_number:5;

drivers/scsi/qla1280.h

353

uint8_t scsi_bus_number:1;

drivers/scsi/qla1280.h

354

uint8_t unused_6:1;

drivers/scsi/qla1280.h

355

uint8_t unused_7:1;

drivers/scsi/qla1280.h

359

uint8_t boot_target_number:4;

drivers/scsi/qla1280.h

360

uint8_t unused_12:1;

drivers/scsi/qla1280.h

361

uint8_t unused_13:1;

drivers/scsi/qla1280.h

362

uint8_t unused_14:1;

drivers/scsi/qla1280.h

363

uint8_t unused_15:1;

drivers/scsi/qla1280.h

372

uint8_t reserved:2;

drivers/scsi/qla1280.h

373

uint8_t burst_enable:1;

drivers/scsi/qla1280.h

374

uint8_t reserved_1:1;

drivers/scsi/qla1280.h

375

uint8_t fifo_threshold:4;

drivers/scsi/qla1280.h

382

uint8_t scsi_bus_1_control:2;

drivers/scsi/qla1280.h

383

uint8_t scsi_bus_0_control:2;

drivers/scsi/qla1280.h

384

uint8_t unused_0:1;

drivers/scsi/qla1280.h

385

uint8_t unused_1:1;

drivers/scsi/qla1280.h

386

uint8_t unused_2:1;

drivers/scsi/qla1280.h

387

uint8_t auto_term_support:1;

drivers/scsi/qla1280.h

418

uint8_t initiator_id:4;

drivers/scsi/qla1280.h

419

uint8_t scsi_reset_disable:1;

drivers/scsi/qla1280.h

420

uint8_t scsi_bus_size:1;

drivers/scsi/qla1280.h

421

uint8_t scsi_bus_type:1;

drivers/scsi/qla1280.h

422

uint8_t unused_7:1;

drivers/scsi/qla1280.h

425

uint8_t bus_reset_delay; /* 25 */

drivers/scsi/qla1280.h

426

uint8_t retry_count; /* 26 */

drivers/scsi/qla1280.h

427

uint8_t retry_delay; /* 27 */

drivers/scsi/qla1280.h

430

uint8_t async_data_setup_time:4;

drivers/scsi/qla1280.h

431

uint8_t req_ack_active_negation:1;

drivers/scsi/qla1280.h

432

uint8_t data_line_active_negation:1;

drivers/scsi/qla1280.h

433

uint8_t unused_6:1;

drivers/scsi/qla1280.h

434

uint8_t unused_7:1;

drivers/scsi/qla1280.h

437

uint8_t unused_29; /* 29 */

drivers/scsi/qla1280.h

448

uint8_t renegotiate_on_error:1;

drivers/scsi/qla1280.h

449

uint8_t stop_queue_on_check:1;

drivers/scsi/qla1280.h

450

uint8_t auto_request_sense:1;

drivers/scsi/qla1280.h

451

uint8_t tag_queuing:1;

drivers/scsi/qla1280.h

452

uint8_t enable_sync:1;

drivers/scsi/qla1280.h

453

uint8_t enable_wide:1;

drivers/scsi/qla1280.h

454

uint8_t parity_checking:1;

drivers/scsi/qla1280.h

455

uint8_t disconnect_allowed:1;

drivers/scsi/qla1280.h

458

uint8_t execution_throttle; /* 41 */

drivers/scsi/qla1280.h

459

uint8_t sync_period; /* 42 */

drivers/scsi/qla1280.h

462

uint8_t flags_43;

drivers/scsi/qla1280.h

464

uint8_t sync_offset:4;

drivers/scsi/qla1280.h

465

uint8_t device_enable:1;

drivers/scsi/qla1280.h

466

uint8_t lun_disable:1;

drivers/scsi/qla1280.h

467

uint8_t unused_6:1;

drivers/scsi/qla1280.h

468

uint8_t unused_7:1;

drivers/scsi/qla1280.h

471

uint8_t sync_offset:5;

drivers/scsi/qla1280.h

472

uint8_t device_enable:1;

drivers/scsi/qla1280.h

473

uint8_t unused_6:1;

drivers/scsi/qla1280.h

474

uint8_t unused_7:1;

drivers/scsi/qla1280.h

478

uint8_t unused_44;

drivers/scsi/qla1280.h

480

uint8_t ppr_options:4;

drivers/scsi/qla1280.h

481

uint8_t ppr_bus_width:2;

drivers/scsi/qla1280.h

482

uint8_t unused_8:1;

drivers/scsi/qla1280.h

483

uint8_t enable_ppr:1;

drivers/scsi/qla1280.h

486

uint8_t unused_45; /* 45 */

drivers/scsi/qla1280.h

495

uint8_t unused_254;

drivers/scsi/qla1280.h

496

uint8_t system_id_pointer;

drivers/scsi/qla1280.h

499

uint8_t chksum; /* 255 */

drivers/scsi/qla1280.h

507

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

509

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

510

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

511

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

513

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

514

uint8_t target; /* SCSI ID */

drivers/scsi/qla1280.h

520

uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */

drivers/scsi/qla1280.h

535

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

537

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

538

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

539

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

561

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

563

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

564

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

565

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

586

uint8_t req_sense_data[32]; /* Request sense data. */

drivers/scsi/qla1280.h

593

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

595

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

596

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

597

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

599

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

600

uint8_t target; /* SCSI ID */

drivers/scsi/qla1280.h

601

uint8_t modifier; /* Modifier (7-0). */

drivers/scsi/qla1280.h

605

uint8_t reserved_1[53];

drivers/scsi/qla1280.h

614

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

616

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

617

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

618

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

620

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

621

uint8_t target; /* SCSI ID */

drivers/scsi/qla1280.h

627

uint8_t scsi_cdb[88]; /* SCSI command words. */

drivers/scsi/qla1280.h

634

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

636

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

637

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

638

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

640

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

641

uint8_t target; /* SCSI ID */

drivers/scsi/qla1280.h

647

uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */

drivers/scsi/qla1280.h

659

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

661

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

662

uint8_t sys_define; /* System defined. */

drivers/scsi/qla1280.h

663

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

680

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

682

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

683

uint8_t reserved_1;

drivers/scsi/qla1280.h

684

uint8_t entry_status; /* Entry Status not used. */

drivers/scsi/qla1280.h

689

uint8_t status;

drivers/scsi/qla1280.h

690

uint8_t reserved_5;

drivers/scsi/qla1280.h

691

uint8_t command_count; /* Number of ATIOs allocated. */

drivers/scsi/qla1280.h

692

uint8_t immed_notify_count; /* Number of Immediate Notify */

drivers/scsi/qla1280.h

694

uint8_t group_6_length; /* SCSI CDB length for group 6 */

drivers/scsi/qla1280.h

696

uint8_t group_7_length; /* SCSI CDB length for group 7 */

drivers/scsi/qla1280.h

708

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

710

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

711

uint8_t reserved_1;

drivers/scsi/qla1280.h

712

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

714

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

715

uint8_t reserved_3;

drivers/scsi/qla1280.h

716

uint8_t operators;

drivers/scsi/qla1280.h

717

uint8_t reserved_4;

drivers/scsi/qla1280.h

719

uint8_t status;

drivers/scsi/qla1280.h

720

uint8_t reserved_5;

drivers/scsi/qla1280.h

721

uint8_t command_count; /* Number of ATIOs allocated. */

drivers/scsi/qla1280.h

722

uint8_t immed_notify_count; /* Number of Immediate Notify */

drivers/scsi/qla1280.h

733

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

735

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

736

uint8_t reserved_1;

drivers/scsi/qla1280.h

737

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

739

uint8_t lun;

drivers/scsi/qla1280.h

740

uint8_t initiator_id;

drivers/scsi/qla1280.h

741

uint8_t reserved_3;

drivers/scsi/qla1280.h

742

uint8_t target_id;

drivers/scsi/qla1280.h

744

uint8_t status;

drivers/scsi/qla1280.h

745

uint8_t reserved_4;

drivers/scsi/qla1280.h

746

uint8_t tag_value; /* Received queue tag message value */

drivers/scsi/qla1280.h

747

uint8_t tag_type; /* Received queue tag message type */

drivers/scsi/qla1280.h

750

uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */

drivers/scsi/qla1280.h

752

uint8_t sense_data[18];

drivers/scsi/qla1280.h

759

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

761

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

762

uint8_t reserved_1;

drivers/scsi/qla1280.h

763

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

765

uint8_t lun;

drivers/scsi/qla1280.h

766

uint8_t initiator_id;

drivers/scsi/qla1280.h

767

uint8_t reserved_3;

drivers/scsi/qla1280.h

768

uint8_t target_id;

drivers/scsi/qla1280.h

770

uint8_t status;

drivers/scsi/qla1280.h

771

uint8_t event;

drivers/scsi/qla1280.h

780

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

782

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

783

uint8_t reserved_1;

drivers/scsi/qla1280.h

784

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

786

uint8_t lun;

drivers/scsi/qla1280.h

787

uint8_t initiator_id;

drivers/scsi/qla1280.h

788

uint8_t cdb_len;

drivers/scsi/qla1280.h

789

uint8_t target_id;

drivers/scsi/qla1280.h

791

uint8_t status;

drivers/scsi/qla1280.h

792

uint8_t scsi_status;

drivers/scsi/qla1280.h

793

uint8_t tag_value; /* Received queue tag message value */

drivers/scsi/qla1280.h

794

uint8_t tag_type; /* Received queue tag message type */

drivers/scsi/qla1280.h

795

uint8_t cdb[26];

drivers/scsi/qla1280.h

796

uint8_t sense_data[18];

drivers/scsi/qla1280.h

803

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

805

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

806

uint8_t reserved_1;

drivers/scsi/qla1280.h

807

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

809

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

810

uint8_t initiator_id;

drivers/scsi/qla1280.h

811

uint8_t reserved_3;

drivers/scsi/qla1280.h

812

uint8_t target_id;

drivers/scsi/qla1280.h

814

uint8_t status;

drivers/scsi/qla1280.h

815

uint8_t scsi_status;

drivers/scsi/qla1280.h

816

uint8_t tag_value; /* Received queue tag message value */

drivers/scsi/qla1280.h

817

uint8_t tag_type; /* Received queue tag message type */

drivers/scsi/qla1280.h

836

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

838

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

839

uint8_t reserved_1;

drivers/scsi/qla1280.h

840

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

842

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

843

uint8_t initiator_id;

drivers/scsi/qla1280.h

844

uint8_t reserved_3;

drivers/scsi/qla1280.h

845

uint8_t target_id;

drivers/scsi/qla1280.h

847

uint8_t status;

drivers/scsi/qla1280.h

848

uint8_t scsi_status;

drivers/scsi/qla1280.h

849

uint8_t tag_value; /* Received queue tag message value */

drivers/scsi/qla1280.h

850

uint8_t tag_type; /* Received queue tag message type */

drivers/scsi/qla1280.h

859

uint8_t sense_data[18];

drivers/scsi/qla1280.h

866

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

868

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

869

uint8_t reserved_1;

drivers/scsi/qla1280.h

870

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

872

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

873

uint8_t initiator_id;

drivers/scsi/qla1280.h

874

uint8_t reserved_3;

drivers/scsi/qla1280.h

875

uint8_t target_id;

drivers/scsi/qla1280.h

877

uint8_t status;

drivers/scsi/qla1280.h

878

uint8_t scsi_status;

drivers/scsi/qla1280.h

879

uint8_t tag_value; /* Received queue tag message value */

drivers/scsi/qla1280.h

880

uint8_t tag_type; /* Received queue tag message type */

drivers/scsi/qla1280.h

896

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla1280.h

898

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla1280.h

899

uint8_t reserved_1;

drivers/scsi/qla1280.h

900

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla1280.h

902

uint8_t lun; /* SCSI LUN */

drivers/scsi/qla1280.h

903

uint8_t initiator_id;

drivers/scsi/qla1280.h

904

uint8_t reserved_3;

drivers/scsi/qla1280.h

905

uint8_t target_id;

drivers/scsi/qla1280.h

907

uint8_t status;

drivers/scsi/qla1280.h

908

uint8_t scsi_status;

drivers/scsi/qla1280.h

909

uint8_t tag_value; /* Received queue tag message value */

drivers/scsi/qla1280.h

910

uint8_t tag_type; /* Received queue tag message type */

drivers/scsi/qla1280.h

916

uint8_t sense_data[18];

drivers/scsi/qla1280.h

982

uint8_t id; /* Host adapter SCSI id */

drivers/scsi/qla1280.h

983

uint8_t bus_reset_delay; /* SCSI bus reset delay. */

drivers/scsi/qla1280.h

984

uint8_t failed_reset_count; /* number of time reset failed */

drivers/scsi/qla1280.h

985

uint8_t unused;

drivers/scsi/qla1280.h

99

uint8_t flags; /* (1) Status flags. */

drivers/scsi/qla1280.h

990

uint8_t reset_marker:1;

drivers/scsi/qla1280.h

991

uint8_t disable_scsi_reset:1;

drivers/scsi/qla1280.h

992

uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */

drivers/scsi/qla2xxx/qla_attr.c

246

uint8_t *iter;

drivers/scsi/qla2xxx/qla_attr.c

247

uint8_t chksum;

drivers/scsi/qla2xxx/qla_attr.c

249

iter = (uint8_t *)buf;

drivers/scsi/qla2xxx/qla_attr.c

2999

static const uint8_t node_name[WWN_SIZE] = {

drivers/scsi/qla2xxx/qla_attr.c

3047

uint8_t qos = 0;

drivers/scsi/qla2xxx/qla_attr.c

596

uint8_t *tmp_data;

drivers/scsi/qla2xxx/qla_attr.c

702

uint8_t *tmp_data = NULL;

drivers/scsi/qla2xxx/qla_bsg.c

103

bcode = (uint8_t *)pri_cfg;

drivers/scsi/qla2xxx/qla_bsg.c

1331

uint8_t *rsp_ptr = NULL;

drivers/scsi/qla2xxx/qla_bsg.c

1393

rsp_ptr = ((uint8_t *)bsg_reply) +

drivers/scsi/qla2xxx/qla_bsg.c

1410

uint8_t is_update)

drivers/scsi/qla2xxx/qla_bsg.c

1565

uint8_t bsg[DMA_POOL_SIZE];

drivers/scsi/qla2xxx/qla_bsg.c

1618

uint8_t bsg[DMA_POOL_SIZE];

drivers/scsi/qla2xxx/qla_bsg.c

1621

uint8_t *sfp = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &sfp_dma);

drivers/scsi/qla2xxx/qla_bsg.c

1669

uint8_t bsg[DMA_POOL_SIZE];

drivers/scsi/qla2xxx/qla_bsg.c

1672

uint8_t *sfp = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &sfp_dma);

drivers/scsi/qla2xxx/qla_bsg.c

1716

uint8_t bsg[DMA_POOL_SIZE];

drivers/scsi/qla2xxx/qla_bsg.c

1719

uint8_t *sfp = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &sfp_dma);

drivers/scsi/qla2xxx/qla_bsg.c

1762

uint8_t bsg[DMA_POOL_SIZE];

drivers/scsi/qla2xxx/qla_bsg.c

1765

uint8_t *sfp = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &sfp_dma);

drivers/scsi/qla2xxx/qla_bsg.c

2276

uint8_t domain, area, al_pa, state;

drivers/scsi/qla2xxx/qla_bsg.c

743

uint8_t command_sent;

drivers/scsi/qla2xxx/qla_bsg.c

748

uint8_t *fw_sts_ptr;

drivers/scsi/qla2xxx/qla_bsg.c

752

uint8_t *rsp_data = NULL;

drivers/scsi/qla2xxx/qla_bsg.c

94

struct qla_fcp_prio_cfg *pri_cfg, uint8_t flag)

drivers/scsi/qla2xxx/qla_bsg.c

950

sizeof(response) + sizeof(uint8_t);

drivers/scsi/qla2xxx/qla_bsg.c

97

uint8_t *bcode;

drivers/scsi/qla2xxx/qla_bsg.h

168

uint8_t payload[]; /* payload for cmd */

drivers/scsi/qla2xxx/qla_bsg.h

182

uint8_t wwnn[8];

drivers/scsi/qla2xxx/qla_bsg.h

183

uint8_t wwpn[8];

drivers/scsi/qla2xxx/qla_bsg.h

184

uint8_t id[4];

drivers/scsi/qla2xxx/qla_bsg.h

217

uint8_t version[MAX_FRU_SIZE];

drivers/scsi/qla2xxx/qla_bsg.h

232

uint8_t status_reg;

drivers/scsi/qla2xxx/qla_bsg.h

233

uint8_t reserved[7];

drivers/scsi/qla2xxx/qla_bsg.h

241

uint8_t buffer[0x40];

drivers/scsi/qla2xxx/qla_bsg.h

265

uint8_t reserved[20];

drivers/scsi/qla2xxx/qla_bsg.h

284

uint8_t status; /* 1 - enabled, 0 - Disabled */

drivers/scsi/qla2xxx/qla_bsg.h

285

uint8_t state; /* 1 - online, 0 - offline */

drivers/scsi/qla2xxx/qla_bsg.h

286

uint8_t configured_bbscn; /* 0-15 */

drivers/scsi/qla2xxx/qla_bsg.h

287

uint8_t negotiated_bbscn; /* 0-15 */

drivers/scsi/qla2xxx/qla_bsg.h

288

uint8_t offline_reason_code;

drivers/scsi/qla2xxx/qla_bsg.h

290

uint8_t reserved[9];

drivers/scsi/qla2xxx/qla_bsg.h

296

uint8_t unused[62];

drivers/scsi/qla2xxx/qla_bsg.h

306

uint8_t unused[58];

drivers/scsi/qla2xxx/qla_bsg.h

307

uint8_t buf[1024]; /* Test Result */

drivers/scsi/qla2xxx/qla_bsg.h

316

uint8_t global_image;

drivers/scsi/qla2xxx/qla_bsg.h

317

uint8_t board_config;

drivers/scsi/qla2xxx/qla_bsg.h

318

uint8_t vpd_nvram;

drivers/scsi/qla2xxx/qla_bsg.h

319

uint8_t npiv_config_0_1;

drivers/scsi/qla2xxx/qla_bsg.h

320

uint8_t npiv_config_2_3;

drivers/scsi/qla2xxx/qla_bsg.h

321

uint8_t nvme_params;

drivers/scsi/qla2xxx/qla_bsg.h

322

uint8_t reserved[31];

drivers/scsi/qla2xxx/qla_bsg.h

330

uint8_t reserved[20];

drivers/scsi/qla2xxx/qla_dbg.c

676

uint8_t que_cnt;

drivers/scsi/qla2xxx/qla_dbg.h

276

uint8_t signature[4];

drivers/scsi/qla2xxx/qla_def.h

1097

uint8_t flags;

drivers/scsi/qla2xxx/qla_def.h

1110

uint8_t flags;

drivers/scsi/qla2xxx/qla_def.h

140

#define LSB(x) ((uint8_t)(x))

drivers/scsi/qla2xxx/qla_def.h

141

#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))

drivers/scsi/qla2xxx/qla_def.h

1489

uint8_t options;

drivers/scsi/qla2xxx/qla_def.h

1490

uint8_t control;

drivers/scsi/qla2xxx/qla_def.h

1491

uint8_t master_state;

drivers/scsi/qla2xxx/qla_def.h

1492

uint8_t slave_state;

drivers/scsi/qla2xxx/qla_def.h

1493

uint8_t reserved[2];

drivers/scsi/qla2xxx/qla_def.h

1494

uint8_t hard_address;

drivers/scsi/qla2xxx/qla_def.h

1495

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_def.h

1496

uint8_t port_id[4];

drivers/scsi/qla2xxx/qla_def.h

1497

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1498

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1501

uint8_t reset_count;

drivers/scsi/qla2xxx/qla_def.h

1502

uint8_t reserved_2;

drivers/scsi/qla2xxx/qla_def.h

1512

uint8_t recipient;

drivers/scsi/qla2xxx/qla_def.h

1513

uint8_t initiator;

drivers/scsi/qla2xxx/qla_def.h

1525

uint8_t prli_svc_param_word_0[2]; /* Big endian */

drivers/scsi/qla2xxx/qla_def.h

1527

uint8_t prli_svc_param_word_3[2]; /* Big endian */

drivers/scsi/qla2xxx/qla_def.h

1561

uint8_t version;

drivers/scsi/qla2xxx/qla_def.h

1562

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_def.h

1583

uint8_t firmware_options[2];

drivers/scsi/qla2xxx/qla_def.h

1588

uint8_t retry_count;

drivers/scsi/qla2xxx/qla_def.h

1589

uint8_t retry_delay; /* unused */

drivers/scsi/qla2xxx/qla_def.h

1590

uint8_t port_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_def.h

1592

uint8_t inquiry_data;

drivers/scsi/qla2xxx/qla_def.h

1593

uint8_t login_timeout;

drivers/scsi/qla2xxx/qla_def.h

1594

uint8_t node_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_def.h

1604

uint8_t command_resource_count;

drivers/scsi/qla2xxx/qla_def.h

1605

uint8_t immediate_notify_resource_count;

drivers/scsi/qla2xxx/qla_def.h

1607

uint8_t reserved_2[2];

drivers/scsi/qla2xxx/qla_def.h

1628

uint8_t add_firmware_options[2];

drivers/scsi/qla2xxx/qla_def.h

1630

uint8_t response_accumulation_timer;

drivers/scsi/qla2xxx/qla_def.h

1631

uint8_t interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_def.h

1652

uint8_t special_options[2];

drivers/scsi/qla2xxx/qla_def.h

1654

uint8_t reserved_3[26];

drivers/scsi/qla2xxx/qla_def.h

1659

uint8_t format;

drivers/scsi/qla2xxx/qla_def.h

1660

uint8_t reserved0;

drivers/scsi/qla2xxx/qla_def.h

1668

uint8_t reserved1[32];

drivers/scsi/qla2xxx/qla_def.h

1671

uint8_t reserved2[40];

drivers/scsi/qla2xxx/qla_def.h

1672

uint8_t scm_related_parameter[16];

drivers/scsi/qla2xxx/qla_def.h

1673

uint8_t reserved3[32];

drivers/scsi/qla2xxx/qla_def.h

1741

uint8_t id[4];

drivers/scsi/qla2xxx/qla_def.h

1742

uint8_t nvram_version;

drivers/scsi/qla2xxx/qla_def.h

1743

uint8_t reserved_0;

drivers/scsi/qla2xxx/qla_def.h

1748

uint8_t parameter_block_version;

drivers/scsi/qla2xxx/qla_def.h

1749

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_def.h

1770

uint8_t firmware_options[2];

drivers/scsi/qla2xxx/qla_def.h

1775

uint8_t retry_count;

drivers/scsi/qla2xxx/qla_def.h

1776

uint8_t retry_delay; /* unused */

drivers/scsi/qla2xxx/qla_def.h

1777

uint8_t port_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_def.h

1779

uint8_t inquiry_data;

drivers/scsi/qla2xxx/qla_def.h

1780

uint8_t login_timeout;

drivers/scsi/qla2xxx/qla_def.h

1781

uint8_t node_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_def.h

1802

uint8_t add_firmware_options[2];

drivers/scsi/qla2xxx/qla_def.h

1804

uint8_t response_accumulation_timer;

drivers/scsi/qla2xxx/qla_def.h

1805

uint8_t interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_def.h

1826

uint8_t special_options[2];

drivers/scsi/qla2xxx/qla_def.h

1829

uint8_t reserved_2[22];

drivers/scsi/qla2xxx/qla_def.h

1868

uint8_t seriallink_options[4];

drivers/scsi/qla2xxx/qla_def.h

1891

uint8_t host_p[2];

drivers/scsi/qla2xxx/qla_def.h

1893

uint8_t boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1894

uint8_t boot_lun_number;

drivers/scsi/qla2xxx/qla_def.h

1895

uint8_t reset_delay;

drivers/scsi/qla2xxx/qla_def.h

1896

uint8_t port_down_retry_count;

drivers/scsi/qla2xxx/qla_def.h

1897

uint8_t boot_id_number;

drivers/scsi/qla2xxx/qla_def.h

1899

uint8_t fcode_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1900

uint8_t alternate_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1901

uint8_t alternate_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1913

uint8_t efi_parameters;

drivers/scsi/qla2xxx/qla_def.h

1915

uint8_t link_down_timeout;

drivers/scsi/qla2xxx/qla_def.h

1917

uint8_t adapter_id[16];

drivers/scsi/qla2xxx/qla_def.h

1919

uint8_t alt1_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1921

uint8_t alt2_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1923

uint8_t alt3_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1925

uint8_t alt4_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1927

uint8_t alt5_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1929

uint8_t alt6_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1931

uint8_t alt7_boot_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

1934

uint8_t reserved_3[2];

drivers/scsi/qla2xxx/qla_def.h

1937

uint8_t model_number[16];

drivers/scsi/qla2xxx/qla_def.h

1940

uint8_t oem_specific[16];

drivers/scsi/qla2xxx/qla_def.h

1963

uint8_t adapter_features[2];

drivers/scsi/qla2xxx/qla_def.h

1965

uint8_t reserved_4[16];

drivers/scsi/qla2xxx/qla_def.h

1973

uint8_t reserved_5;

drivers/scsi/qla2xxx/qla_def.h

1974

uint8_t checksum;

drivers/scsi/qla2xxx/qla_def.h

1981

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

1982

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

1983

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

1984

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

1986

uint8_t data[52];

drivers/scsi/qla2xxx/qla_def.h

1995

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

1996

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

1998

uint8_t data[56];

drivers/scsi/qla2xxx/qla_def.h

2006

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

2007

uint8_t standard;

drivers/scsi/qla2xxx/qla_def.h

2016

to.id.standard = (uint8_t)from; \

drivers/scsi/qla2xxx/qla_def.h

2024

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2025

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2026

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2027

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2040

uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */

drivers/scsi/qla2xxx/qla_def.h

2053

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2054

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2055

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2056

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2064

uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */

drivers/scsi/qla2xxx/qla_def.h

2074

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2075

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2076

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2077

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2087

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2088

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2089

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2090

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2120

uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/

drivers/scsi/qla2xxx/qla_def.h

2121

uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/

drivers/scsi/qla2xxx/qla_def.h

2173

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2174

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2175

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2176

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2185

uint8_t rsp_info[8]; /* FCP response information. */

drivers/scsi/qla2xxx/qla_def.h

2186

uint8_t req_sense_data[32]; /* Request sense data. */

drivers/scsi/qla2xxx/qla_def.h

2270

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2271

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2272

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2273

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2274

uint8_t data[60]; /* data */

drivers/scsi/qla2xxx/qla_def.h

2283

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2284

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2285

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_def.h

2286

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2296

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2297

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2298

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_def.h

2299

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2308

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2309

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2310

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_def.h

2311

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2314

uint8_t modifier; /* Modifier (7-0). */

drivers/scsi/qla2xxx/qla_def.h

2321

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_def.h

2324

uint8_t reserved_2[48];

drivers/scsi/qla2xxx/qla_def.h

2332

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2333

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2334

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_def.h

2335

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2344

uint8_t type;

drivers/scsi/qla2xxx/qla_def.h

2345

uint8_t r_ctl;

drivers/scsi/qla2xxx/qla_def.h

2363

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_def.h

2364

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_def.h

2365

uint8_t sys_define1;

drivers/scsi/qla2xxx/qla_def.h

2375

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_def.h

2395

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2396

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2409

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_def.h

2410

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_def.h

2411

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_def.h

2412

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_def.h

2418

uint8_t target_id;

drivers/scsi/qla2xxx/qla_def.h

2419

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_def.h

2431

uint8_t reserved_2[28];

drivers/scsi/qla2xxx/qla_def.h

2443

uint8_t status_subcode;

drivers/scsi/qla2xxx/qla_def.h

2444

uint8_t fw_handle;

drivers/scsi/qla2xxx/qla_def.h

2451

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_def.h

2456

uint8_t resv0[6];

drivers/scsi/qla2xxx/qla_def.h

2459

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_def.h

2460

uint8_t resv1;

drivers/scsi/qla2xxx/qla_def.h

2465

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

2466

uint8_t resv3[3];

drivers/scsi/qla2xxx/qla_def.h

2467

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_def.h

2469

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_def.h

2470

uint8_t reserved_6;

drivers/scsi/qla2xxx/qla_def.h

2491

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2492

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2493

uint8_t fabric_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2495

uint8_t fc4_type;

drivers/scsi/qla2xxx/qla_def.h

2496

uint8_t fc4_features;

drivers/scsi/qla2xxx/qla_def.h

2507

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_def.h

2508

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_def.h

2509

uint8_t sys_define1;

drivers/scsi/qla2xxx/qla_def.h

2510

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_def.h

2613

uint8_t nvme_flag;

drivers/scsi/qla2xxx/qla_def.h

2614

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2615

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2655

uint8_t fcp_prio;

drivers/scsi/qla2xxx/qla_def.h

2657

uint8_t fabric_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2670

uint8_t fc4_type;

drivers/scsi/qla2xxx/qla_def.h

2671

uint8_t fc4_features;

drivers/scsi/qla2xxx/qla_def.h

2672

uint8_t scan_state;

drivers/scsi/qla2xxx/qla_def.h

2723

uint8_t sess_down_acked;

drivers/scsi/qla2xxx/qla_def.h

2724

uint8_t auth_state;

drivers/scsi/qla2xxx/qla_def.h

2909

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2910

uint8_t manufacturer[64];

drivers/scsi/qla2xxx/qla_def.h

2911

uint8_t serial_num[32];

drivers/scsi/qla2xxx/qla_def.h

2912

uint8_t model[16+1];

drivers/scsi/qla2xxx/qla_def.h

2913

uint8_t model_desc[80];

drivers/scsi/qla2xxx/qla_def.h

2914

uint8_t hw_version[32];

drivers/scsi/qla2xxx/qla_def.h

2915

uint8_t driver_version[32];

drivers/scsi/qla2xxx/qla_def.h

2916

uint8_t orom_version[16];

drivers/scsi/qla2xxx/qla_def.h

2917

uint8_t fw_version[32];

drivers/scsi/qla2xxx/qla_def.h

2918

uint8_t os_version[128];

drivers/scsi/qla2xxx/qla_def.h

2921

uint8_t sym_name[256];

drivers/scsi/qla2xxx/qla_def.h

2924

uint8_t fabric_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

2925

uint8_t bios_name[32];

drivers/scsi/qla2xxx/qla_def.h

2926

uint8_t vendor_identifier[8];

drivers/scsi/qla2xxx/qla_def.h

2995

uint8_t fc4_types[32];

drivers/scsi/qla2xxx/qla_def.h

2999

uint8_t os_dev_name[32];

drivers/scsi/qla2xxx/qla_def.h

3000

uint8_t host_name[256];

drivers/scsi/qla2xxx/qla_def.h

3002

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3003

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3004

uint8_t port_sym_name[128];

drivers/scsi/qla2xxx/qla_def.h

3007

uint8_t fabric_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3008

uint8_t port_fc4_type[32];

drivers/scsi/qla2xxx/qla_def.h

3013

uint8_t smartsan_service[24];

drivers/scsi/qla2xxx/qla_def.h

3014

uint8_t smartsan_guid[16];

drivers/scsi/qla2xxx/qla_def.h

3015

uint8_t smartsan_version[24];

drivers/scsi/qla2xxx/qla_def.h

3016

uint8_t smartsan_prod_name[16];

drivers/scsi/qla2xxx/qla_def.h

3072

uint8_t revision;

drivers/scsi/qla2xxx/qla_def.h

3073

uint8_t in_id[3];

drivers/scsi/qla2xxx/qla_def.h

3074

uint8_t gs_type;

drivers/scsi/qla2xxx/qla_def.h

3075

uint8_t gs_subtype;

drivers/scsi/qla2xxx/qla_def.h

3076

uint8_t options;

drivers/scsi/qla2xxx/qla_def.h

3077

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3085

uint8_t fragment_id;

drivers/scsi/qla2xxx/qla_def.h

3086

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_def.h

3091

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3096

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3097

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

3098

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

3099

uint8_t port_type;

drivers/scsi/qla2xxx/qla_def.h

3103

uint8_t port_type;

drivers/scsi/qla2xxx/qla_def.h

3104

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

3105

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

3106

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3110

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3112

uint8_t fc4_types[32];

drivers/scsi/qla2xxx/qla_def.h

3116

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3119

uint8_t fc4_feature;

drivers/scsi/qla2xxx/qla_def.h

3120

uint8_t fc4_type;

drivers/scsi/qla2xxx/qla_def.h

3124

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3126

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_def.h

3130

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_def.h

3131

uint8_t name_len;

drivers/scsi/qla2xxx/qla_def.h

3132

uint8_t sym_node_name[255];

drivers/scsi/qla2xxx/qla_def.h

3136

uint8_t hba_identifier[8];

drivers/scsi/qla2xxx/qla_def.h

3140

uint8_t hba_identifier[8];

drivers/scsi/qla2xxx/qla_def.h

3142

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3147

uint8_t hba_identifier[8];

drivers/scsi/qla2xxx/qla_def.h

3152

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3157

uint8_t hba_identifier[8];

drivers/scsi/qla2xxx/qla_def.h

3158

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3163

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3167

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3171

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3175

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3179

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3183

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3184

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_def.h

3188

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3198

uint8_t fragment_id;

drivers/scsi/qla2xxx/qla_def.h

3199

uint8_t reason_code;

drivers/scsi/qla2xxx/qla_def.h

3200

uint8_t explanation_code;

drivers/scsi/qla2xxx/qla_def.h

3201

uint8_t vendor_unique;

drivers/scsi/qla2xxx/qla_def.h

3205

uint8_t control_byte;

drivers/scsi/qla2xxx/qla_def.h

3215

uint8_t fragment_id;

drivers/scsi/qla2xxx/qla_def.h

3216

uint8_t reason_code;

drivers/scsi/qla2xxx/qla_def.h

3217

uint8_t explanation_code;

drivers/scsi/qla2xxx/qla_def.h

3218

uint8_t vendor_unique;

drivers/scsi/qla2xxx/qla_def.h

3235

uint8_t port_type;

drivers/scsi/qla2xxx/qla_def.h

3237

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3238

uint8_t sym_port_name_len;

drivers/scsi/qla2xxx/qla_def.h

3239

uint8_t sym_port_name[255];

drivers/scsi/qla2xxx/qla_def.h

3240

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_def.h

3241

uint8_t sym_node_name_len;

drivers/scsi/qla2xxx/qla_def.h

3242

uint8_t sym_node_name[255];

drivers/scsi/qla2xxx/qla_def.h

3243

uint8_t init_proc_assoc[8];

drivers/scsi/qla2xxx/qla_def.h

3244

uint8_t node_ip_addr[16];

drivers/scsi/qla2xxx/qla_def.h

3245

uint8_t class_of_service[4];

drivers/scsi/qla2xxx/qla_def.h

3246

uint8_t fc4_types[32];

drivers/scsi/qla2xxx/qla_def.h

3247

uint8_t ip_address[16];

drivers/scsi/qla2xxx/qla_def.h

3248

uint8_t fabric_port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3249

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3250

uint8_t hard_address[3];

drivers/scsi/qla2xxx/qla_def.h

3260

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3264

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_def.h

3268

uint8_t fc4_types[32];

drivers/scsi/qla2xxx/qla_def.h

3273

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3278

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_def.h

3289

uint8_t fc4_features[128];

drivers/scsi/qla2xxx/qla_def.h

3294

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3295

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_def.h

3394

uint8_t param[36];

drivers/scsi/qla2xxx/qla_def.h

3397

uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3398

uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3399

uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3400

uint8_t gid_data[GID_PT_SNS_DATA_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3401

uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3402

uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3414

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_def.h

3415

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

3416

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

3417

uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */

drivers/scsi/qla2xxx/qla_def.h

3424

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3425

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3429

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_def.h

3434

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3435

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3476

int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,

drivers/scsi/qla2xxx/qla_def.h

3477

uint8_t, uint8_t, uint16_t *, uint8_t);

drivers/scsi/qla2xxx/qla_def.h

3478

int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,

drivers/scsi/qla2xxx/qla_def.h

3479

uint8_t, uint8_t);

drivers/scsi/qla2xxx/qla_def.h

3487

uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,

drivers/scsi/qla2xxx/qla_def.h

3693

uint8_t *ctx_dsd_alloced;

drivers/scsi/qla2xxx/qla_def.h

3759

uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3788

uint8_t req_pkt[REQUEST_ENTRY_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3908

uint8_t reserved;

drivers/scsi/qla2xxx/qla_def.h

3909

uint8_t nport_id[3];

drivers/scsi/qla2xxx/qla_def.h

3963

uint8_t pn_port_phy_type;

drivers/scsi/qla2xxx/qla_def.h

3964

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_def.h

3971

uint8_t WWNN[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3972

uint8_t WWPN[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3979

uint8_t WWNN[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

3980

uint8_t WWPN[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

4007

uint8_t vendor_name[16];

drivers/scsi/qla2xxx/qla_def.h

4008

uint8_t part_number[16];

drivers/scsi/qla2xxx/qla_def.h

4009

uint8_t serial_number[16];

drivers/scsi/qla2xxx/qla_def.h

4010

uint8_t revision[4];

drivers/scsi/qla2xxx/qla_def.h

4011

uint8_t date[8];

drivers/scsi/qla2xxx/qla_def.h

4054

uint8_t saved_firmware_options[2];

drivers/scsi/qla2xxx/qla_def.h

4055

uint8_t saved_add_firmware_options[2];

drivers/scsi/qla2xxx/qla_def.h

4057

uint8_t tgt_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

406

uint8_t *request_sense_ptr;

drivers/scsi/qla2xxx/qla_def.h

4214

uint8_t mqenable;

drivers/scsi/qla2xxx/qla_def.h

4223

uint8_t max_req_queues;

drivers/scsi/qla2xxx/qla_def.h

4224

uint8_t max_rsp_queues;

drivers/scsi/qla2xxx/qla_def.h

4225

uint8_t max_qpairs;

drivers/scsi/qla2xxx/qla_def.h

4226

uint8_t num_qpairs;

drivers/scsi/qla2xxx/qla_def.h

4237

uint8_t port_no; /* Physical port of adapter */

drivers/scsi/qla2xxx/qla_def.h

4238

uint8_t exch_starvation;

drivers/scsi/qla2xxx/qla_def.h

4241

uint8_t loop_down_abort_time; /* port down timer */

drivers/scsi/qla2xxx/qla_def.h

4243

uint8_t link_down_timeout; /* link down timeout */

drivers/scsi/qla2xxx/qla_def.h

4263

uint8_t current_topology;

drivers/scsi/qla2xxx/qla_def.h

4264

uint8_t prev_topology;

drivers/scsi/qla2xxx/qla_def.h

4270

uint8_t operating_mode; /* F/W operating mode */

drivers/scsi/qla2xxx/qla_def.h

4275

uint8_t interrupts_on;

drivers/scsi/qla2xxx/qla_def.h

44

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

4442

uint8_t serial0;

drivers/scsi/qla2xxx/qla_def.h

4443

uint8_t serial1;

drivers/scsi/qla2xxx/qla_def.h

4444

uint8_t serial2;

drivers/scsi/qla2xxx/qla_def.h

4457

uint8_t retry_count;

drivers/scsi/qla2xxx/qla_def.h

4458

uint8_t login_timeout;

drivers/scsi/qla2xxx/qla_def.h

4461

uint8_t mbx_count;

drivers/scsi/qla2xxx/qla_def.h

4462

uint8_t aen_mbx_count;

drivers/scsi/qla2xxx/qla_def.h

4496

uint8_t dpc_active; /* DPC routine is active */

drivers/scsi/qla2xxx/qla_def.h

45

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

46

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_def.h

4610

uint8_t fw_seriallink_options[4];

drivers/scsi/qla2xxx/qla_def.h

4613

uint8_t serdes_version[3];

drivers/scsi/qla2xxx/qla_def.h

4614

uint8_t mpi_version[3];

drivers/scsi/qla2xxx/qla_def.h

4616

uint8_t phy_version[3];

drivers/scsi/qla2xxx/qla_def.h

4617

uint8_t pep_version[3];

drivers/scsi/qla2xxx/qla_def.h

4670

uint8_t model_number[16+1];

drivers/scsi/qla2xxx/qla_def.h

4672

uint8_t adapter_id[16+1];

drivers/scsi/qla2xxx/qla_def.h

4689

uint8_t bios_revision[2];

drivers/scsi/qla2xxx/qla_def.h

4690

uint8_t efi_revision[2];

drivers/scsi/qla2xxx/qla_def.h

4691

uint8_t fcode_revision[16];

drivers/scsi/qla2xxx/qla_def.h

4732

uint8_t active_image;

drivers/scsi/qla2xxx/qla_def.h

4733

uint8_t active_tmf;

drivers/scsi/qla2xxx/qla_def.h

4738

uint8_t beacon_color_state;

drivers/scsi/qla2xxx/qla_def.h

4794

uint8_t fw_type;

drivers/scsi/qla2xxx/qla_def.h

481

uint8_t modifier;

drivers/scsi/qla2xxx/qla_def.h

485

uint8_t opcode;

drivers/scsi/qla2xxx/qla_def.h

4851

uint8_t fc4_type_priority;

drivers/scsi/qla2xxx/qla_def.h

486

uint8_t rsvd[3];

drivers/scsi/qla2xxx/qla_def.h

487

uint8_t s_id[3];

drivers/scsi/qla2xxx/qla_def.h

488

uint8_t rsvd1[1];

drivers/scsi/qla2xxx/qla_def.h

4882

uint8_t global;

drivers/scsi/qla2xxx/qla_def.h

4884

uint8_t board_config;

drivers/scsi/qla2xxx/qla_def.h

4885

uint8_t vpd_nvram;

drivers/scsi/qla2xxx/qla_def.h

4886

uint8_t npiv_config_0_1;

drivers/scsi/qla2xxx/qla_def.h

4887

uint8_t npiv_config_2_3;

drivers/scsi/qla2xxx/qla_def.h

4888

uint8_t nvme_params;

drivers/scsi/qla2xxx/qla_def.h

489

uint8_t wwpn[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

4917

uint8_t iocb[64];

drivers/scsi/qla2xxx/qla_def.h

493

uint8_t opcode;

drivers/scsi/qla2xxx/qla_def.h

494

uint8_t rsvd[3];

drivers/scsi/qla2xxx/qla_def.h

4943

uint8_t host_str[16];

drivers/scsi/qla2xxx/qla_def.h

5034

uint8_t marker_needed;

drivers/scsi/qla2xxx/qla_def.h

5040

uint8_t loop_down_abort_time; /* port down timer */

drivers/scsi/qla2xxx/qla_def.h

5042

uint8_t link_down_timeout; /* link down timeout */

drivers/scsi/qla2xxx/qla_def.h

5047

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

5048

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

5049

uint8_t fabric_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

5050

uint8_t fabric_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

5057

uint8_t fcoe_vn_port_mac[6];

drivers/scsi/qla2xxx/qla_def.h

51

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_def.h

5134

uint8_t min_supported_speed;

drivers/scsi/qla2xxx/qla_def.h

5135

uint8_t n2n_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

5136

uint8_t n2n_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_def.h

5140

uint8_t scm_fabric_connection_flags;

drivers/scsi/qla2xxx/qla_def.h

5159

uint8_t image_status_mask;

drivers/scsi/qla2xxx/qla_def.h

5161

uint8_t ver_major;

drivers/scsi/qla2xxx/qla_def.h

5162

uint8_t ver_minor;

drivers/scsi/qla2xxx/qla_def.h

5163

uint8_t bitmap; /* 28xx only */

drivers/scsi/qla2xxx/qla_def.h

5164

uint8_t reserved[2];

drivers/scsi/qla2xxx/qla_def.h

5181

uint8_t idx;

drivers/scsi/qla2xxx/qla_def.h

52

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

53

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

578

uint8_t modifier;

drivers/scsi/qla2xxx/qla_def.h

579

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_def.h

588

uint8_t flags;

drivers/scsi/qla2xxx/qla_def.h

605

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_def.h

63

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

630

uint8_t aen_op;

drivers/scsi/qla2xxx/qla_def.h

64

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

65

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_def.h

67

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_def.h

68

uint8_t area;

drivers/scsi/qla2xxx/qla_def.h

69

uint8_t domain;

drivers/scsi/qla2xxx/qla_def.h

725

uint8_t cmd_type;

drivers/scsi/qla2xxx/qla_def.h

726

uint8_t pad[3];

drivers/scsi/qla2xxx/qla_def.h

73

uint8_t rsvd_1;

drivers/scsi/qla2xxx/qla_edif.c

2981

uint8_t additional_cdb_len;

drivers/scsi/qla2xxx/qla_edif.c

2987

uint8_t avail_dsds = 0;

drivers/scsi/qla2xxx/qla_edif.c

3155

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_edif.c

3158

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_edif.c

3185

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_edif.h

110

uint8_t vp_idx;

drivers/scsi/qla2xxx/qla_edif.h

60

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_edif.h

61

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_edif.h

62

uint8_t sys_define; /* System Defined. */

drivers/scsi/qla2xxx/qla_edif.h

63

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_edif.h

75

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_edif.h

76

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_edif.h

77

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_edif.h

78

uint8_t flags;

drivers/scsi/qla2xxx/qla_edif.h

82

uint8_t sa_key[32]; /* 256 bit key */

drivers/scsi/qla2xxx/qla_edif.h

85

uint8_t sa_control;

drivers/scsi/qla2xxx/qla_edif.h

93

uint8_t reserved_2;

drivers/scsi/qla2xxx/qla_edif_bsg.h

100

uint8_t domain;

drivers/scsi/qla2xxx/qla_edif_bsg.h

104

uint8_t rsvd_1;

drivers/scsi/qla2xxx/qla_edif_bsg.h

106

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

107

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

108

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

113

uint8_t remote_wwpn[WWN_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

114

uint8_t remote_type;

drivers/scsi/qla2xxx/qla_edif_bsg.h

118

uint8_t remote_state;

drivers/scsi/qla2xxx/qla_edif_bsg.h

119

uint8_t auth_state;

drivers/scsi/qla2xxx/qla_edif_bsg.h

120

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

121

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

122

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

133

uint8_t port_count;

drivers/scsi/qla2xxx/qla_edif_bsg.h

134

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

135

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

136

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

142

uint8_t num_ports;

drivers/scsi/qla2xxx/qla_edif_bsg.h

143

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

144

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

145

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

149

uint8_t remote_wwpn[WWN_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

151

uint8_t rekey_mode;

drivers/scsi/qla2xxx/qla_edif_bsg.h

157

uint8_t elem_count;

drivers/scsi/qla2xxx/qla_edif_bsg.h

158

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

159

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

160

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

180

uint8_t sa_key[32];

drivers/scsi/qla2xxx/qla_edif_bsg.h

181

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

182

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

184

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

185

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

186

uint8_t reserved2[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

209

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

210

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

211

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

222

uint8_t event_data[EXT_DEF_EVENT_DATA_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

230

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

231

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

232

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

250

uint8_t wwpn[WWN_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

253

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

254

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

255

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

262

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

263

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

264

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

28

uint8_t extra_control_flags;

drivers/scsi/qla2xxx/qla_edif_bsg.h

33

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

34

uint8_t pad[2];

drivers/scsi/qla2xxx/qla_edif_bsg.h

35

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

46

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

47

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

48

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

53

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

54

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

55

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

62

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

63

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

64

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

69

uint8_t app_start_flags;

drivers/scsi/qla2xxx/qla_edif_bsg.h

70

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

71

uint8_t pad[2];

drivers/scsi/qla2xxx/qla_edif_bsg.h

72

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

77

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

78

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

79

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

84

uint8_t version;

drivers/scsi/qla2xxx/qla_edif_bsg.h

85

uint8_t pad[VND_CMD_PAD_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

86

uint8_t reserved[VND_CMD_APP_RESERVED_SIZE];

drivers/scsi/qla2xxx/qla_edif_bsg.h

91

uint8_t num_ports;

drivers/scsi/qla2xxx/qla_edif_bsg.h

94

uint8_t domain;

drivers/scsi/qla2xxx/qla_edif_bsg.h

95

uint8_t area;

drivers/scsi/qla2xxx/qla_edif_bsg.h

96

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_edif_bsg.h

98

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_edif_bsg.h

99

uint8_t area;

drivers/scsi/qla2xxx/qla_fw.h

1010

uint8_t reserved_1[30];

drivers/scsi/qla2xxx/qla_fw.h

1012

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_fw.h

1013

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

1033

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_fw.h

1034

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_fw.h

1035

uint8_t handle_count;

drivers/scsi/qla2xxx/qla_fw.h

1036

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_fw.h

1044

uint8_t vp_idx;

drivers/scsi/qla2xxx/qla_fw.h

1045

uint8_t sof_type; /* sof_type is upper nibble */

drivers/scsi/qla2xxx/qla_fw.h

1049

uint8_t d_id[3];

drivers/scsi/qla2xxx/qla_fw.h

1050

uint8_t r_ctl;

drivers/scsi/qla2xxx/qla_fw.h

1052

uint8_t s_id[3];

drivers/scsi/qla2xxx/qla_fw.h

1053

uint8_t cs_ctl;

drivers/scsi/qla2xxx/qla_fw.h

1055

uint8_t f_ctl[3];

drivers/scsi/qla2xxx/qla_fw.h

1056

uint8_t type;

drivers/scsi/qla2xxx/qla_fw.h

1059

uint8_t df_ctl;

drivers/scsi/qla2xxx/qla_fw.h

1060

uint8_t seq_id;

drivers/scsi/qla2xxx/qla_fw.h

1076

uint8_t last_seq_id;

drivers/scsi/qla2xxx/qla_fw.h

1077

uint8_t seq_id_valid;

drivers/scsi/qla2xxx/qla_fw.h

1084

uint8_t vendor_unique;

drivers/scsi/qla2xxx/qla_fw.h

1085

uint8_t explanation;

drivers/scsi/qla2xxx/qla_fw.h

1086

uint8_t reason;

drivers/scsi/qla2xxx/qla_fw.h

126

uint8_t options;

drivers/scsi/qla2xxx/qla_fw.h

127

uint8_t id;

drivers/scsi/qla2xxx/qla_fw.h

128

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

129

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

136

uint8_t id[4];

drivers/scsi/qla2xxx/qla_fw.h

1375

uint8_t options;

drivers/scsi/qla2xxx/qla_fw.h

1377

uint8_t hard_address;

drivers/scsi/qla2xxx/qla_fw.h

1379

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1380

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1399

uint8_t options;

drivers/scsi/qla2xxx/qla_fw.h

1400

uint8_t hard_address;

drivers/scsi/qla2xxx/qla_fw.h

1402

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1403

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1405

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_fw.h

1406

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_fw.h

1414

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

1415

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

1416

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

1417

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

1437

uint8_t vp_idx_map[16];

drivers/scsi/qla2xxx/qla_fw.h

1442

uint8_t reserved_5[24];

drivers/scsi/qla2xxx/qla_fw.h

1450

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

1451

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

1452

uint8_t handle_count;

drivers/scsi/qla2xxx/qla_fw.h

1453

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

1469

uint8_t command;

drivers/scsi/qla2xxx/qla_fw.h

1473

uint8_t vp_count;

drivers/scsi/qla2xxx/qla_fw.h

1475

uint8_t vp_index1;

drivers/scsi/qla2xxx/qla_fw.h

1476

uint8_t vp_index2;

drivers/scsi/qla2xxx/qla_fw.h

1478

uint8_t options_idx1;

drivers/scsi/qla2xxx/qla_fw.h

1479

uint8_t hard_address_idx1;

drivers/scsi/qla2xxx/qla_fw.h

148

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1481

uint8_t port_name_idx1[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1482

uint8_t node_name_idx1[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1484

uint8_t options_idx2;

drivers/scsi/qla2xxx/qla_fw.h

1485

uint8_t hard_address_idx2;

drivers/scsi/qla2xxx/qla_fw.h

1487

uint8_t port_name_idx2[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1488

uint8_t node_name_idx2[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

149

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1492

uint8_t reserved_5[2];

drivers/scsi/qla2xxx/qla_fw.h

1514

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

1515

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

1516

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

1517

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

1519

uint8_t vp_acquired;

drivers/scsi/qla2xxx/qla_fw.h

1520

uint8_t vp_setup;

drivers/scsi/qla2xxx/qla_fw.h

1521

uint8_t vp_idx; /* Format 0=reserved */

drivers/scsi/qla2xxx/qla_fw.h

1522

uint8_t vp_status; /* Format 0=reserved */

drivers/scsi/qla2xxx/qla_fw.h

1524

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_fw.h

1525

uint8_t format;

drivers/scsi/qla2xxx/qla_fw.h

1529

uint8_t vp_idx_map[16];

drivers/scsi/qla2xxx/qla_fw.h

1530

uint8_t reserved_4[32];

drivers/scsi/qla2xxx/qla_fw.h

1534

uint8_t vpstat1_subcode; /* vp_status=1 subcode */

drivers/scsi/qla2xxx/qla_fw.h

1535

uint8_t flags;

drivers/scsi/qla2xxx/qla_fw.h

1542

uint8_t rsv2[12];

drivers/scsi/qla2xxx/qla_fw.h

1544

uint8_t ls_rjt_vendor;

drivers/scsi/qla2xxx/qla_fw.h

1545

uint8_t ls_rjt_explanation;

drivers/scsi/qla2xxx/qla_fw.h

1546

uint8_t ls_rjt_reason;

drivers/scsi/qla2xxx/qla_fw.h

1547

uint8_t rsv3[5];

drivers/scsi/qla2xxx/qla_fw.h

1549

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_fw.h

1550

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_fw.h

1552

uint8_t reserved_5[6];

drivers/scsi/qla2xxx/qla_fw.h

1555

uint8_t vpstat1_subcode;

drivers/scsi/qla2xxx/qla_fw.h

1556

uint8_t flags;

drivers/scsi/qla2xxx/qla_fw.h

1558

uint8_t rsv2[12];

drivers/scsi/qla2xxx/qla_fw.h

1560

uint8_t ls_rjt_vendor;

drivers/scsi/qla2xxx/qla_fw.h

1561

uint8_t ls_rjt_explanation;

drivers/scsi/qla2xxx/qla_fw.h

1562

uint8_t ls_rjt_reason;

drivers/scsi/qla2xxx/qla_fw.h

1563

uint8_t rsv3[5];

drivers/scsi/qla2xxx/qla_fw.h

1565

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_fw.h

1566

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_fw.h

1568

uint8_t reserved_5[2];

drivers/scsi/qla2xxx/qla_fw.h

1569

uint8_t remote_nport_id[4];

drivers/scsi/qla2xxx/qla_fw.h

1576

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

1577

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

1578

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

1579

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

1604

uint8_t sig[4];

drivers/scsi/qla2xxx/qla_fw.h

1608

uint8_t unused1[2];

drivers/scsi/qla2xxx/qla_fw.h

1609

uint8_t model[16];

drivers/scsi/qla2xxx/qla_fw.h

1612

uint8_t flags;

drivers/scsi/qla2xxx/qla_fw.h

1613

uint8_t erase_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1614

uint8_t alt_erase_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1615

uint8_t wrt_enable_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1616

uint8_t wrt_enable_bits;

drivers/scsi/qla2xxx/qla_fw.h

1617

uint8_t wrt_sts_reg_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1618

uint8_t unprotect_sec_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1619

uint8_t read_man_id_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1624

uint8_t read_id_addr_len;

drivers/scsi/qla2xxx/qla_fw.h

1625

uint8_t wrt_disable_bits;

drivers/scsi/qla2xxx/qla_fw.h

1626

uint8_t read_dev_id_len;

drivers/scsi/qla2xxx/qla_fw.h

1627

uint8_t chip_erase_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1629

uint8_t protect_sec_cmd;

drivers/scsi/qla2xxx/qla_fw.h

1630

uint8_t unused2[65];

drivers/scsi/qla2xxx/qla_fw.h

1636

uint8_t sig[4];

drivers/scsi/qla2xxx/qla_fw.h

1639

uint8_t version;

drivers/scsi/qla2xxx/qla_fw.h

1640

uint8_t unused[5];

drivers/scsi/qla2xxx/qla_fw.h

1700

uint8_t attribute;

drivers/scsi/qla2xxx/qla_fw.h

1701

uint8_t reserved;

drivers/scsi/qla2xxx/qla_fw.h

1722

uint8_t sig[2];

drivers/scsi/qla2xxx/qla_fw.h

1732

uint8_t q_qos;

drivers/scsi/qla2xxx/qla_fw.h

1733

uint8_t f_qos;

drivers/scsi/qla2xxx/qla_fw.h

1735

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1736

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1757

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_fw.h

1758

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_fw.h

1759

uint8_t sys_defined;

drivers/scsi/qla2xxx/qla_fw.h

1760

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_fw.h

1789

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_fw.h

1790

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_fw.h

1791

uint8_t sys_defined;

drivers/scsi/qla2xxx/qla_fw.h

1792

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_fw.h

1816

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_fw.h

1817

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_fw.h

1818

uint8_t sys_defined;

drivers/scsi/qla2xxx/qla_fw.h

1819

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_fw.h

1846

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_fw.h

1847

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_fw.h

1848

uint8_t sys_defined;

drivers/scsi/qla2xxx/qla_fw.h

1849

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_fw.h

1911

uint8_t id[4];

drivers/scsi/qla2xxx/qla_fw.h

1923

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1924

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1938

uint8_t enode_mac[6];

drivers/scsi/qla2xxx/qla_fw.h

1946

uint8_t prio_fcf_matching_flags;

drivers/scsi/qla2xxx/qla_fw.h

1947

uint8_t reserved_6_1[3];

drivers/scsi/qla2xxx/qla_fw.h

1949

uint8_t pri_fcf_fabric_name[8];

drivers/scsi/qla2xxx/qla_fw.h

1951

uint8_t spma_mac_addr[6];

drivers/scsi/qla2xxx/qla_fw.h

1955

uint8_t min_supported_speed;

drivers/scsi/qla2xxx/qla_fw.h

1956

uint8_t reserved_7_0;

drivers/scsi/qla2xxx/qla_fw.h

1992

uint8_t alternate_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1993

uint8_t alternate_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1995

uint8_t boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

1999

uint8_t alt1_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

2003

uint8_t alt2_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

2007

uint8_t alt3_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

2023

uint8_t reset_delay;

drivers/scsi/qla2xxx/qla_fw.h

2024

uint8_t reserved_12;

drivers/scsi/qla2xxx/qla_fw.h

2042

uint8_t reserved_17[4];

drivers/scsi/qla2xxx/qla_fw.h

2044

uint8_t reserved_19[2];

drivers/scsi/qla2xxx/qla_fw.h

2048

uint8_t reserved_21[16];

drivers/scsi/qla2xxx/qla_fw.h

2067

uint8_t model_name[16];

drivers/scsi/qla2xxx/qla_fw.h

2095

uint8_t port_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_fw.h

2096

uint8_t node_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_fw.h

2116

uint8_t reserved_4[8];

drivers/scsi/qla2xxx/qla_fw.h

2177

uint8_t reserved_5[8];

drivers/scsi/qla2xxx/qla_fw.h

2179

uint8_t enode_mac[6];

drivers/scsi/qla2xxx/qla_fw.h

2181

uint8_t reserved_6[10];

drivers/scsi/qla2xxx/qla_fw.h

2195

uint8_t prio_fcf_matching_flags;

drivers/scsi/qla2xxx/qla_fw.h

2196

uint8_t reserved_1[3];

drivers/scsi/qla2xxx/qla_fw.h

2198

uint8_t pri_fcf_fabric_name[8];

drivers/scsi/qla2xxx/qla_fw.h

2200

uint8_t spma_mac_addr[6];

drivers/scsi/qla2xxx/qla_fw.h

2227

uint8_t tag; /* Priority value */

drivers/scsi/qla2xxx/qla_fw.h

2228

uint8_t reserved; /* Reserved for future use */

drivers/scsi/qla2xxx/qla_fw.h

223

uint8_t alternate_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

2237

uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */

drivers/scsi/qla2xxx/qla_fw.h

2238

uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */

drivers/scsi/qla2xxx/qla_fw.h

224

uint8_t alternate_node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

2242

uint8_t signature[4]; /* "HQOS" signature of config data */

drivers/scsi/qla2xxx/qla_fw.h

2248

uint8_t attributes; /* enable/disable, persistence */

drivers/scsi/qla2xxx/qla_fw.h

2252

uint8_t reserved; /* Reserved for future use */

drivers/scsi/qla2xxx/qla_fw.h

2255

uint8_t reserved2[16];

drivers/scsi/qla2xxx/qla_fw.h

226

uint8_t boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

230

uint8_t alt1_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

234

uint8_t alt2_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

238

uint8_t alt3_boot_port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

254

uint8_t reset_delay;

drivers/scsi/qla2xxx/qla_fw.h

255

uint8_t reserved_12;

drivers/scsi/qla2xxx/qla_fw.h

273

uint8_t prev_drv_ver_major;

drivers/scsi/qla2xxx/qla_fw.h

274

uint8_t prev_drv_ver_submajob;

drivers/scsi/qla2xxx/qla_fw.h

275

uint8_t prev_drv_ver_minor;

drivers/scsi/qla2xxx/qla_fw.h

276

uint8_t prev_drv_ver_subminor;

drivers/scsi/qla2xxx/qla_fw.h

285

uint8_t prev_fw_ver_minor;

drivers/scsi/qla2xxx/qla_fw.h

286

uint8_t prev_fw_ver_subminor;

drivers/scsi/qla2xxx/qla_fw.h

300

uint8_t model_name[16];

drivers/scsi/qla2xxx/qla_fw.h

330

uint8_t port_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_fw.h

331

uint8_t node_name[WWN_SIZE]; /* Big endian. */

drivers/scsi/qla2xxx/qla_fw.h

353

uint8_t reserved_2[4];

drivers/scsi/qla2xxx/qla_fw.h

431

uint8_t reserved_3[20];

drivers/scsi/qla2xxx/qla_fw.h

439

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

440

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

441

uint8_t sys_define; /* System defined */

drivers/scsi/qla2xxx/qla_fw.h

442

uint8_t entry_status; /* Entry status. */

drivers/scsi/qla2xxx/qla_fw.h

468

uint8_t port_id[3]; /* PortID of destination port.*/

drivers/scsi/qla2xxx/qla_fw.h

469

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

476

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

477

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

478

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

479

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

509

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_fw.h

510

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

517

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

518

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

519

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

520

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

53

uint8_t current_login_state;

drivers/scsi/qla2xxx/qla_fw.h

54

uint8_t last_login_state;

drivers/scsi/qla2xxx/qla_fw.h

543

uint8_t task;

drivers/scsi/qla2xxx/qla_fw.h

550

uint8_t crn;

drivers/scsi/qla2xxx/qla_fw.h

552

uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */

drivers/scsi/qla2xxx/qla_fw.h

555

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_fw.h

556

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

564

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

565

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

566

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

567

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

589

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_fw.h

590

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

603

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

604

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

605

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

606

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

637

uint8_t data[28]; /* FCP rsp/sense information */

drivers/scsi/qla2xxx/qla_fw.h

64

uint8_t hard_address[3];

drivers/scsi/qla2xxx/qla_fw.h

640

uint8_t nvme_ersp_data[32];

drivers/scsi/qla2xxx/qla_fw.h

65

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_fw.h

67

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_fw.h

672

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

673

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

674

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_fw.h

675

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

68

uint8_t sequence_id;

drivers/scsi/qla2xxx/qla_fw.h

681

uint8_t modifier; /* Modifier (7-0). */

drivers/scsi/qla2xxx/qla_fw.h

685

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_fw.h

687

uint8_t reserved_2;

drivers/scsi/qla2xxx/qla_fw.h

688

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

692

uint8_t lun[8]; /* FCP LUN (BE). */

drivers/scsi/qla2xxx/qla_fw.h

693

uint8_t reserved_4[40];

drivers/scsi/qla2xxx/qla_fw.h

701

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

702

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

703

uint8_t sys_define; /* System Defined. */

drivers/scsi/qla2xxx/qla_fw.h

704

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

714

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

715

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_fw.h

722

uint8_t reserved_3[10];

drivers/scsi/qla2xxx/qla_fw.h

737

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

738

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

739

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

740

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

743

uint8_t vp_idx;

drivers/scsi/qla2xxx/qla_fw.h

744

uint8_t reserved2;

drivers/scsi/qla2xxx/qla_fw.h

754

uint8_t d_id[3];

drivers/scsi/qla2xxx/qla_fw.h

755

uint8_t r_ctl;

drivers/scsi/qla2xxx/qla_fw.h

757

uint8_t s_id[3];

drivers/scsi/qla2xxx/qla_fw.h

758

uint8_t cs_ctl;

drivers/scsi/qla2xxx/qla_fw.h

760

uint8_t f_ctl[3];

drivers/scsi/qla2xxx/qla_fw.h

761

uint8_t type;

drivers/scsi/qla2xxx/qla_fw.h

764

uint8_t df_ctl;

drivers/scsi/qla2xxx/qla_fw.h

765

uint8_t seq_id;

drivers/scsi/qla2xxx/qla_fw.h

77

uint8_t prli_svc_param_word_0[2]; /* Big endian */

drivers/scsi/qla2xxx/qla_fw.h

771

uint8_t els_frame_payload[20];

drivers/scsi/qla2xxx/qla_fw.h

779

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

780

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

781

uint8_t sys_define; /* System Defined. */

drivers/scsi/qla2xxx/qla_fw.h

782

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

79

uint8_t prli_svc_param_word_3[2]; /* Big endian */

drivers/scsi/qla2xxx/qla_fw.h

791

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

792

uint8_t sof_type;

drivers/scsi/qla2xxx/qla_fw.h

799

uint8_t opcode;

drivers/scsi/qla2xxx/qla_fw.h

800

uint8_t reserved_2;

drivers/scsi/qla2xxx/qla_fw.h

802

uint8_t d_id[3];

drivers/scsi/qla2xxx/qla_fw.h

803

uint8_t s_id[3];

drivers/scsi/qla2xxx/qla_fw.h

82

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

83

uint8_t node_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_fw.h

836

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

837

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

838

uint8_t sys_define; /* System Defined. */

drivers/scsi/qla2xxx/qla_fw.h

839

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

849

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

85

uint8_t reserved_3[2];

drivers/scsi/qla2xxx/qla_fw.h

850

uint8_t sof_type;

drivers/scsi/qla2xxx/qla_fw.h

855

uint8_t opcode;

drivers/scsi/qla2xxx/qla_fw.h

856

uint8_t reserved_3;

drivers/scsi/qla2xxx/qla_fw.h

858

uint8_t d_id[3];

drivers/scsi/qla2xxx/qla_fw.h

859

uint8_t s_id[3];

drivers/scsi/qla2xxx/qla_fw.h

874

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

875

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

876

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_fw.h

877

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

887

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

888

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

889

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_fw.h

89

uint8_t secure_login;

drivers/scsi/qla2xxx/qla_fw.h

890

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

90

uint8_t reserved_4[14];

drivers/scsi/qla2xxx/qla_fw.h

922

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

923

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_fw.h

925

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_fw.h

927

uint8_t rsp_size; /* Response size in 32bit words. */

drivers/scsi/qla2xxx/qla_fw.h

952

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

953

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

954

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_fw.h

955

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_fw.h

977

uint8_t reserved_2[20];

drivers/scsi/qla2xxx/qla_fw.h

979

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_fw.h

980

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_fw.h

982

uint8_t reserved_3[12];

drivers/scsi/qla2xxx/qla_fw.h

987

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_fw.h

988

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_fw.h

989

uint8_t handle_count; /* Handle count. */

drivers/scsi/qla2xxx/qla_fw.h

990

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_gbl.h

310

uint16_t, uint64_t, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

378

qla2x00_get_adapter_id(scsi_qla_host_t *, uint16_t *, uint8_t *, uint8_t *,

drivers/scsi/qla2xxx/qla_gbl.h

379

uint8_t *, uint16_t *, uint16_t *);

drivers/scsi/qla2xxx/qla_gbl.h

382

qla2x00_get_retry_cnt(scsi_qla_host_t *, uint8_t *, uint8_t *, uint16_t *);

drivers/scsi/qla2xxx/qla_gbl.h

388

qla2x00_get_port_database(scsi_qla_host_t *, fc_port_t *, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

397

qla2x00_get_port_name(scsi_qla_host_t *, uint16_t, uint8_t *, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

409

qla2x00_login_fabric(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t,

drivers/scsi/qla2xxx/qla_gbl.h

410

uint16_t *, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

412

qla24xx_login_fabric(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t,

drivers/scsi/qla2xxx/qla_gbl.h

413

uint16_t *, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

417

uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

420

qla2x00_fabric_logout(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

423

qla24xx_fabric_logout(scsi_qla_host_t *, uint16_t, uint8_t, uint8_t, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

500

qla2x00_read_sfp(scsi_qla_host_t *, dma_addr_t, uint8_t *,

drivers/scsi/qla2xxx/qla_gbl.h

504

qla2x00_write_sfp(scsi_qla_host_t *, dma_addr_t, uint8_t *,

drivers/scsi/qla2xxx/qla_gbl.h

622

extern uint8_t *qla2x00_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,

drivers/scsi/qla2xxx/qla_gbl.h

624

extern uint8_t *qla24xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,

drivers/scsi/qla2xxx/qla_gbl.h

630

extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, void *, uint32_t,

drivers/scsi/qla2xxx/qla_gbl.h

725

extern size_t qla2x00_get_sym_node_name(scsi_qla_host_t *, uint8_t *, size_t);

drivers/scsi/qla2xxx/qla_gbl.h

763

struct qla_fcp_prio_cfg *, uint8_t);

drivers/scsi/qla2xxx/qla_gbl.h

775

extern int qla25xx_create_req_que(struct qla_hw_data *, uint16_t, uint8_t,

drivers/scsi/qla2xxx/qla_gbl.h

776

uint16_t, int, uint8_t, bool);

drivers/scsi/qla2xxx/qla_gbl.h

777

extern int qla25xx_create_rsp_que(struct qla_hw_data *, uint16_t, uint8_t,

drivers/scsi/qla2xxx/qla_gbl.h

877

extern void qla2x00_set_model_info(scsi_qla_host_t *, uint8_t *, size_t,

drivers/scsi/qla2xxx/qla_gs.c

1074

uint8_t *entry;

drivers/scsi/qla2xxx/qla_gs.c

2645

uint8_t fcp_scsi_features = 0, nvme_features = 0;

drivers/scsi/qla2xxx/qla_gs.c

2899

uint8_t fc4_scsi_feat;

drivers/scsi/qla2xxx/qla_gs.c

2900

uint8_t fc4_nvme_feat;

drivers/scsi/qla2xxx/qla_gs.c

849

qla2x00_get_sym_node_name(scsi_qla_host_t *vha, uint8_t *snn, size_t size)

drivers/scsi/qla2xxx/qla_gs.c

934

(uint8_t)strlen(ct_req->req.rsnn_nn.sym_node_name);

drivers/scsi/qla2xxx/qla_init.c

1540

uint8_t ls;

drivers/scsi/qla2xxx/qla_init.c

3089

uint8_t domain, area, al_pa;

drivers/scsi/qla2xxx/qla_init.c

5054

uint8_t al_pa;

drivers/scsi/qla2xxx/qla_init.c

5055

uint8_t area;

drivers/scsi/qla2xxx/qla_init.c

5056

uint8_t domain;

drivers/scsi/qla2xxx/qla_init.c

5162

qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,

drivers/scsi/qla2xxx/qla_init.c

5251

uint8_t chksum = 0;

drivers/scsi/qla2xxx/qla_init.c

5253

uint8_t *dptr1, *dptr2;

drivers/scsi/qla2xxx/qla_init.c

5257

uint8_t *ptr = ha->nvram;

drivers/scsi/qla2xxx/qla_init.c

5387

dptr1 = (uint8_t *)icb;

drivers/scsi/qla2xxx/qla_init.c

5388

dptr2 = (uint8_t *)&nv->parameter_block_version;

drivers/scsi/qla2xxx/qla_init.c

5389

cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;

drivers/scsi/qla2xxx/qla_init.c

5394

dptr1 = (uint8_t *)icb->add_firmware_options;

drivers/scsi/qla2xxx/qla_init.c

5395

cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;

drivers/scsi/qla2xxx/qla_init.c

5532

icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;

drivers/scsi/qla2xxx/qla_init.c

5533

icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;

drivers/scsi/qla2xxx/qla_init.c

5875

uint8_t domain, area, al_pa;

drivers/scsi/qla2xxx/qla_init.c

7539

uint8_t status = 0;

drivers/scsi/qla2xxx/qla_init.c

7899

uint8_t *dptr1, *dptr2;

drivers/scsi/qla2xxx/qla_init.c

8006

dptr1 = (uint8_t *)icb;

drivers/scsi/qla2xxx/qla_init.c

8007

dptr2 = (uint8_t *)&nv->version;

drivers/scsi/qla2xxx/qla_init.c

8008

cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;

drivers/scsi/qla2xxx/qla_init.c

8016

dptr1 = (uint8_t *)&icb->interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_init.c

8017

dptr2 = (uint8_t *)&nv->interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_init.c

8018

cnt = (uint8_t *)&icb->reserved_3 -

drivers/scsi/qla2xxx/qla_init.c

8019

(uint8_t *)&icb->interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_init.c

9292

uint8_t *dptr1, *dptr2;

drivers/scsi/qla2xxx/qla_init.c

9417

dptr1 = (uint8_t *)icb;

drivers/scsi/qla2xxx/qla_init.c

9418

dptr2 = (uint8_t *)&nv->version;

drivers/scsi/qla2xxx/qla_init.c

9419

cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;

drivers/scsi/qla2xxx/qla_init.c

9426

dptr1 = (uint8_t *)&icb->interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_init.c

9427

dptr2 = (uint8_t *)&nv->interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_init.c

9428

cnt = (uint8_t *)&icb->reserved_5 -

drivers/scsi/qla2xxx/qla_init.c

9429

(uint8_t *)&icb->interrupt_delay_timer;

drivers/scsi/qla2xxx/qla_init.c

9712

uint8_t pid_match, wwn_match;

drivers/scsi/qla2xxx/qla_inline.h

111

uint8_t shiftbits, mask;

drivers/scsi/qla2xxx/qla_inline.h

112

uint8_t port_dstate_str_sz;

drivers/scsi/qla2xxx/qla_inline.h

200

uint8_t bail;

drivers/scsi/qla2xxx/qla_inline.h

378

((uint8_t *)vha->hw->nvram)[NVRAM_DUAL_FCP_NVME_FLAG_OFFSET];

drivers/scsi/qla2xxx/qla_inline.h

68

static inline uint8_t *

drivers/scsi/qla2xxx/qla_inline.h

69

host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)

drivers/scsi/qla2xxx/qla_inline.h

82

host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize)

drivers/scsi/qla2xxx/qla_iocb.c

1346

uint8_t bundling = 1;

drivers/scsi/qla2xxx/qla_iocb.c

1350

uint8_t additional_fcpcdb_len;

drivers/scsi/qla2xxx/qla_iocb.c

1640

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_iocb.c

1654

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

1845

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_iocb.c

1856

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

1858

cmd_pkt->entry_status = (uint8_t) rsp->id;

drivers/scsi/qla2xxx/qla_iocb.c

2007

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_iocb.c

2021

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

2228

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_iocb.c

2239

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

2567

host_to_fcp_swap((uint8_t *)&tsk->lun,

drivers/scsi/qla2xxx/qla_iocb.c

2837

(uint8_t *)els_iocb,

drivers/scsi/qla2xxx/qla_iocb.c

3112

(uint8_t *)elsio->u.els_plogi.els_plogi_pyld,

drivers/scsi/qla2xxx/qla_iocb.c

3382

uint8_t additional_cdb_len;

drivers/scsi/qla2xxx/qla_iocb.c

3540

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_iocb.c

3569

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

3573

cmd_pkt->entry_status = (uint8_t) rsp->id;

drivers/scsi/qla2xxx/qla_iocb.c

3607

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun,

drivers/scsi/qla2xxx/qla_iocb.c

3624

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

3628

cmd_pkt->entry_status = (uint8_t) rsp->id;

drivers/scsi/qla2xxx/qla_iocb.c

419

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

4211

cmd_pkt->entry_status = (uint8_t) rsp->id;

drivers/scsi/qla2xxx/qla_iocb.c

4254

uint8_t additional_cdb_len;

drivers/scsi/qla2xxx/qla_iocb.c

4416

host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));

drivers/scsi/qla2xxx/qla_iocb.c

4445

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_iocb.c

510

uint16_t loop_id, uint64_t lun, uint8_t type)

drivers/scsi/qla2xxx/qla_iocb.c

554

uint16_t loop_id, uint64_t lun, uint8_t type)

drivers/scsi/qla2xxx/qla_iocb.c

596

uint8_t avail_dsds;

drivers/scsi/qla2xxx/qla_iocb.c

597

uint8_t first_iocb = 1;

drivers/scsi/qla2xxx/qla_iocb.c

763

uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/

drivers/scsi/qla2xxx/qla_iocb.c

764

uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/

drivers/scsi/qla2xxx/qla_iocb.c

839

uint8_t avail_dsds = 0;

drivers/scsi/qla2xxx/qla_iocb.c

953

uint8_t avail_dsds = 0;

drivers/scsi/qla2xxx/qla_isr.c

1083

uint8_t item_hdr_size = sizeof(*item);

drivers/scsi/qla2xxx/qla_isr.c

118

(uint8_t *)rsp_els, sizeof(*rsp_els));

drivers/scsi/qla2xxx/qla_isr.c

1225

memcpy(((uint8_t *)fpin_pkt +

drivers/scsi/qla2xxx/qla_isr.c

1235

memcpy(((uint8_t *)fpin_pkt +

drivers/scsi/qla2xxx/qla_isr.c

1252

host_to_fcp_swap((uint8_t *)&item->iocb, total_bytes);

drivers/scsi/qla2xxx/qla_isr.c

169

(uint8_t *)abts_rsp, sizeof(*abts_rsp));

drivers/scsi/qla2xxx/qla_isr.c

3001

qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,

drivers/scsi/qla2xxx/qla_isr.c

3050

uint8_t *ap = &sts24->data[12];

drivers/scsi/qla2xxx/qla_isr.c

3051

uint8_t *ep = &sts24->data[20];

drivers/scsi/qla2xxx/qla_isr.c

3323

uint8_t lscsi_status;

drivers/scsi/qla2xxx/qla_isr.c

3327

uint8_t *rsp_info, *sense_data;

drivers/scsi/qla2xxx/qla_isr.c

3711

uint8_t sense_sz = 0;

drivers/scsi/qla2xxx/qla_isr.c

3717

uint8_t *sense_ptr;

drivers/scsi/qla2xxx/qla_isr.c

941

memcpy(((uint8_t *)iocb_pkt + buffer_copy_offset),

drivers/scsi/qla2xxx/qla_isr.c

950

memcpy(((uint8_t *)iocb_pkt + buffer_copy_offset),

drivers/scsi/qla2xxx/qla_isr.c

96

(uint8_t *)abts, sizeof(*abts));

drivers/scsi/qla2xxx/qla_isr.c

969

host_to_fcp_swap((uint8_t *)&item->iocb, total_bytes);

drivers/scsi/qla2xxx/qla_mbx.c

112

uint8_t abort_active, eeh_delay;

drivers/scsi/qla2xxx/qla_mbx.c

113

uint8_t io_lock_on;

drivers/scsi/qla2xxx/qla_mbx.c

1743

qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,

drivers/scsi/qla2xxx/qla_mbx.c

1744

uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)

drivers/scsi/qla2xxx/qla_mbx.c

1853

qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,

drivers/scsi/qla2xxx/qla_mbx.c

1881

*retry_cnt = (uint8_t)mcp->mb[1];

drivers/scsi/qla2xxx/qla_mbx.c

2011

qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)

drivers/scsi/qla2xxx/qla_mbx.c

2095

(memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&

drivers/scsi/qla2xxx/qla_mbx.c

2140

(memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&

drivers/scsi/qla2xxx/qla_mbx.c

2320

qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,

drivers/scsi/qla2xxx/qla_mbx.c

2321

uint8_t opt)

drivers/scsi/qla2xxx/qla_mbx.c

2549

qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,

drivers/scsi/qla2xxx/qla_mbx.c

2550

uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)

drivers/scsi/qla2xxx/qla_mbx.c

2685

qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,

drivers/scsi/qla2xxx/qla_mbx.c

2686

uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)

drivers/scsi/qla2xxx/qla_mbx.c

2767

uint16_t *mb_ret, uint8_t opt)

drivers/scsi/qla2xxx/qla_mbx.c

2825

qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,

drivers/scsi/qla2xxx/qla_mbx.c

2826

uint8_t area, uint8_t al_pa)

drivers/scsi/qla2xxx/qla_mbx.c

2900

qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,

drivers/scsi/qla2xxx/qla_mbx.c

2901

uint8_t area, uint8_t al_pa)

drivers/scsi/qla2xxx/qla_mbx.c

3434

host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,

drivers/scsi/qla2xxx/qla_mbx.c

4950

uint8_t *str;

drivers/scsi/qla2xxx/qla_mbx.c

5050

uint8_t *els_cmd_map;

drivers/scsi/qla2xxx/qla_mbx.c

5051

uint8_t active_cnt = 0;

drivers/scsi/qla2xxx/qla_mbx.c

5053

uint8_t cmd_opcode[PUREX_CMD_COUNT];

drivers/scsi/qla2xxx/qla_mbx.c

5054

uint8_t i, index, purex_bit;

drivers/scsi/qla2xxx/qla_mbx.c

5153

qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,

drivers/scsi/qla2xxx/qla_mbx.c

5204

qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,

drivers/scsi/qla2xxx/qla_mbx.c

5833

uint8_t byte;

drivers/scsi/qla2xxx/qla_mbx.c

6383

uint8_t subcode = (uint8_t)options;

drivers/scsi/qla2xxx/qla_mbx.c

6774

(memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&

drivers/scsi/qla2xxx/qla_mid.c

110

qla24xx_find_vhost_by_name(struct qla_hw_data *ha, uint8_t *port_name)

drivers/scsi/qla2xxx/qla_mid.c

461

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_mid.c

700

uint8_t vp_idx, uint16_t rid, int rsp_que, uint8_t qos, bool startqp)

drivers/scsi/qla2xxx/qla_mid.c

828

uint8_t vp_idx, uint16_t rid, struct qla_qpair *qpair, bool startqp)

drivers/scsi/qla2xxx/qla_mr.c

131

(uint8_t *)mcp->mb, 16);

drivers/scsi/qla2xxx/qla_mr.c

133

((uint8_t *)mcp->mb + 0x10), 16);

drivers/scsi/qla2xxx/qla_mr.c

135

((uint8_t *)mcp->mb + 0x20), 8);

drivers/scsi/qla2xxx/qla_mr.c

2101

qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,

drivers/scsi/qla2xxx/qla_mr.c

2189

uint8_t *fw_sts_ptr;

drivers/scsi/qla2xxx/qla_mr.c

2219

pkt->reserved_2, 20 * sizeof(uint8_t));

drivers/scsi/qla2xxx/qla_mr.c

2225

sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);

drivers/scsi/qla2xxx/qla_mr.c

2260

uint8_t *rsp_info = NULL, *sense_data = NULL;

drivers/scsi/qla2xxx/qla_mr.c

2527

uint8_t sense_sz = 0;

drivers/scsi/qla2xxx/qla_mr.c

2533

uint8_t *sense_ptr;

drivers/scsi/qla2xxx/qla_mr.c

3118

host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,

drivers/scsi/qla2xxx/qla_mr.c

3129

lcmd_pkt.entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_mr.c

3132

lcmd_pkt.entry_status = (uint8_t) rsp->id;

drivers/scsi/qla2xxx/qla_mr.c

3186

host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,

drivers/scsi/qla2xxx/qla_mr.c

3224

uint8_t entry_cnt = 1;

drivers/scsi/qla2xxx/qla_mr.c

3325

(uint8_t *)&lcont_pkt,

drivers/scsi/qla2xxx/qla_mr.c

3334

(uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);

drivers/scsi/qla2xxx/qla_mr.c

3381

(uint8_t *)&lcont_pkt,

drivers/scsi/qla2xxx/qla_mr.c

3390

(uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);

drivers/scsi/qla2xxx/qla_mr.c

44

uint8_t abort_active;

drivers/scsi/qla2xxx/qla_mr.c

45

uint8_t io_lock_on;

drivers/scsi/qla2xxx/qla_mr.h

112

uint8_t reserved_2[32];

drivers/scsi/qla2xxx/qla_mr.h

118

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

119

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

120

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_mr.h

121

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_mr.h

133

uint8_t reserved_1[38];

drivers/scsi/qla2xxx/qla_mr.h

138

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

139

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

140

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_mr.h

141

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_mr.h

154

uint8_t reserved_2[20];

drivers/scsi/qla2xxx/qla_mr.h

163

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

164

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

165

uint8_t sys_define; /* System Defined. */

drivers/scsi/qla2xxx/qla_mr.h

166

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_mr.h

176

uint8_t flags;

drivers/scsi/qla2xxx/qla_mr.h

177

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_mr.h

193

uint8_t tgt_node_wwpn[WWN_SIZE];

drivers/scsi/qla2xxx/qla_mr.h

194

uint8_t tgt_node_wwnn[WWN_SIZE];

drivers/scsi/qla2xxx/qla_mr.h

196

uint8_t reserved[128];

drivers/scsi/qla2xxx/qla_mr.h

20

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

21

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

211

uint8_t port_state;

drivers/scsi/qla2xxx/qla_mr.h

212

uint8_t port_type;

drivers/scsi/qla2xxx/qla_mr.h

215

uint8_t fw_ver_num[32];

drivers/scsi/qla2xxx/qla_mr.h

216

uint8_t portal_attrib;

drivers/scsi/qla2xxx/qla_mr.h

218

uint8_t reset_delay;

drivers/scsi/qla2xxx/qla_mr.h

219

uint8_t pdwn_retry_cnt;

drivers/scsi/qla2xxx/qla_mr.h

22

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_mr.h

221

uint8_t risc_ver;

drivers/scsi/qla2xxx/qla_mr.h

222

uint8_t pconn_option;

drivers/scsi/qla2xxx/qla_mr.h

227

uint8_t retry_cnt;

drivers/scsi/qla2xxx/qla_mr.h

228

uint8_t retry_delay;

drivers/scsi/qla2xxx/qla_mr.h

229

uint8_t port_name[8];

drivers/scsi/qla2xxx/qla_mr.h

23

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_mr.h

230

uint8_t port_id[3];

drivers/scsi/qla2xxx/qla_mr.h

231

uint8_t link_status;

drivers/scsi/qla2xxx/qla_mr.h

232

uint8_t plink_rate;

drivers/scsi/qla2xxx/qla_mr.h

235

uint8_t tgt_disc;

drivers/scsi/qla2xxx/qla_mr.h

236

uint8_t log_tout;

drivers/scsi/qla2xxx/qla_mr.h

237

uint8_t node_name[8];

drivers/scsi/qla2xxx/qla_mr.h

239

uint8_t resp_acc_tmr;

drivers/scsi/qla2xxx/qla_mr.h

240

uint8_t intr_del_tmr;

drivers/scsi/qla2xxx/qla_mr.h

241

uint8_t erisc_opt2;

drivers/scsi/qla2xxx/qla_mr.h

242

uint8_t alt_port_name[8];

drivers/scsi/qla2xxx/qla_mr.h

243

uint8_t alt_node_name[8];

drivers/scsi/qla2xxx/qla_mr.h

244

uint8_t link_down_tout;

drivers/scsi/qla2xxx/qla_mr.h

245

uint8_t conn_type;

drivers/scsi/qla2xxx/qla_mr.h

246

uint8_t fc_fw_mode;

drivers/scsi/qla2xxx/qla_mr.h

26

uint8_t reserved_0;

drivers/scsi/qla2xxx/qla_mr.h

27

uint8_t port_path_ctrl;

drivers/scsi/qla2xxx/qla_mr.h

285

uint8_t model_num[16] __nonstring;

drivers/scsi/qla2xxx/qla_mr.h

286

uint8_t model_description[80] __nonstring;

drivers/scsi/qla2xxx/qla_mr.h

287

uint8_t reserved0[160];

drivers/scsi/qla2xxx/qla_mr.h

288

uint8_t symbolic_name[64];

drivers/scsi/qla2xxx/qla_mr.h

289

uint8_t serial_num[32];

drivers/scsi/qla2xxx/qla_mr.h

290

uint8_t hw_version[16];

drivers/scsi/qla2xxx/qla_mr.h

291

uint8_t fw_version[16];

drivers/scsi/qla2xxx/qla_mr.h

292

uint8_t uboot_version[16];

drivers/scsi/qla2xxx/qla_mr.h

293

uint8_t fru_serial_num[32];

drivers/scsi/qla2xxx/qla_mr.h

295

uint8_t fc_port_count;

drivers/scsi/qla2xxx/qla_mr.h

296

uint8_t iscsi_port_count;

drivers/scsi/qla2xxx/qla_mr.h

297

uint8_t reserved1[2];

drivers/scsi/qla2xxx/qla_mr.h

299

uint8_t mode;

drivers/scsi/qla2xxx/qla_mr.h

300

uint8_t log_level;

drivers/scsi/qla2xxx/qla_mr.h

301

uint8_t reserved2[2];

drivers/scsi/qla2xxx/qla_mr.h

305

uint8_t tgt_pres_mode;

drivers/scsi/qla2xxx/qla_mr.h

306

uint8_t iqn_flags;

drivers/scsi/qla2xxx/qla_mr.h

307

uint8_t lun_mapping;

drivers/scsi/qla2xxx/qla_mr.h

312

uint8_t cluster_key[16];

drivers/scsi/qla2xxx/qla_mr.h

316

uint8_t cluster_flags;

drivers/scsi/qla2xxx/qla_mr.h

34

uint8_t scsi_rsp_dsd_len;

drivers/scsi/qla2xxx/qla_mr.h

35

uint8_t reserved_2;

drivers/scsi/qla2xxx/qla_mr.h

39

uint8_t cntrl_flags;

drivers/scsi/qla2xxx/qla_mr.h

41

uint8_t task_mgmt_flags; /* Task management flags. */

drivers/scsi/qla2xxx/qla_mr.h

411

uint8_t flags;

drivers/scsi/qla2xxx/qla_mr.h

412

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_mr.h

43

uint8_t task;

drivers/scsi/qla2xxx/qla_mr.h

442

uint8_t reserved_3[20];

drivers/scsi/qla2xxx/qla_mr.h

45

uint8_t crn;

drivers/scsi/qla2xxx/qla_mr.h

47

uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */

drivers/scsi/qla2xxx/qla_mr.h

471

uint8_t symbolic_name[64];

drivers/scsi/qla2xxx/qla_mr.h

472

uint8_t serial_num[32];

drivers/scsi/qla2xxx/qla_mr.h

473

uint8_t hw_version[16];

drivers/scsi/qla2xxx/qla_mr.h

474

uint8_t fw_version[16];

drivers/scsi/qla2xxx/qla_mr.h

475

uint8_t uboot_version[16];

drivers/scsi/qla2xxx/qla_mr.h

476

uint8_t fru_serial_num[32];

drivers/scsi/qla2xxx/qla_mr.h

481

uint8_t fw_hbt_en;

drivers/scsi/qla2xxx/qla_mr.h

482

uint8_t fw_hbt_cnt;

drivers/scsi/qla2xxx/qla_mr.h

483

uint8_t fw_hbt_miss_cnt;

drivers/scsi/qla2xxx/qla_mr.h

486

uint8_t fw_reset_timer_exp;

drivers/scsi/qla2xxx/qla_mr.h

492

uint8_t hinfo_resend_timer_tick;

drivers/scsi/qla2xxx/qla_mr.h

55

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

56

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

57

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_mr.h

58

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_mr.h

75

uint8_t data[32]; /* FCP response/sense information. */

drivers/scsi/qla2xxx/qla_mr.h

83

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

84

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

85

uint8_t handle_count;

drivers/scsi/qla2xxx/qla_mr.h

86

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_mr.h

93

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_mr.h

94

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_mr.h

95

uint8_t sys_define;

drivers/scsi/qla2xxx/qla_mr.h

96

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_nvme.c

376

uint8_t cnt = 0;

drivers/scsi/qla2xxx/qla_nvme.c

730

cmd_pkt->entry_count = (uint8_t)req_cnt;

drivers/scsi/qla2xxx/qla_nvme.c

963

min((uint8_t)(ql2xnvme_queues),

drivers/scsi/qla2xxx/qla_nvme.c

964

(uint8_t)((ha->max_qpairs - 1) ? (ha->max_qpairs - 1) : 1));

drivers/scsi/qla2xxx/qla_nvme.h

113

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_nvme.h

114

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_nvme.h

117

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_nvme.h

118

uint8_t rsvd2;

drivers/scsi/qla2xxx/qla_nvme.h

124

uint8_t d_id[3];

drivers/scsi/qla2xxx/qla_nvme.h

125

uint8_t r_ctl;

drivers/scsi/qla2xxx/qla_nvme.h

127

uint8_t cs_ctl;

drivers/scsi/qla2xxx/qla_nvme.h

128

uint8_t f_ctl[3];

drivers/scsi/qla2xxx/qla_nvme.h

129

uint8_t type;

drivers/scsi/qla2xxx/qla_nvme.h

131

uint8_t df_ctl;

drivers/scsi/qla2xxx/qla_nvme.h

132

uint8_t seq_id;

drivers/scsi/qla2xxx/qla_nvme.h

46

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_nvme.h

47

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_nvme.h

48

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_nvme.h

49

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_nvme.h

74

uint8_t port_id[3]; /* PortID of destination port. */

drivers/scsi/qla2xxx/qla_nvme.h

75

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_nvme.h

85

uint8_t entry_type;

drivers/scsi/qla2xxx/qla_nvme.h

86

uint8_t entry_count;

drivers/scsi/qla2xxx/qla_nvme.h

87

uint8_t sys_define;

drivers/scsi/qla2xxx/qla_nvme.h

88

uint8_t entry_status;

drivers/scsi/qla2xxx/qla_nvme.h

93

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_nvme.h

94

uint8_t rsvd;

drivers/scsi/qla2xxx/qla_nx.c

1317

tmpw = *((uint8_t *)data);

drivers/scsi/qla2xxx/qla_nx.c

1489

*(uint8_t *)data = val;

drivers/scsi/qla2xxx/qla_nx.c

1777

const uint8_t *unirom = ha->hablob->fw->data;

drivers/scsi/qla2xxx/qla_nx.c

1781

uint8_t chiprev = ha->chip_revision;

drivers/scsi/qla2xxx/qla_nx.c

1812

qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)

drivers/scsi/qla2xxx/qla_nx.c

4135

(((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);

drivers/scsi/qla2xxx/qla_nx.c

4238

data_collected = (uint8_t *)data_ptr -

drivers/scsi/qla2xxx/qla_nx.c

4239

(uint8_t *)ha->md_dump;

drivers/scsi/qla2xxx/qla_nx.c

4242

(((uint8_t *)entry_hdr) + entry_hdr->entry_size);

drivers/scsi/qla2xxx/qla_nx.c

654

uint8_t __iomem *mem_ptr = NULL;

drivers/scsi/qla2xxx/qla_nx.c

726

uint8_t __iomem *mem_ptr = NULL;

drivers/scsi/qla2xxx/qla_nx.c

891

qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)

drivers/scsi/qla2xxx/qla_nx.h

1025

uint8_t entry_capture_mask;

drivers/scsi/qla2xxx/qla_nx.h

1026

uint8_t entry_code;

drivers/scsi/qla2xxx/qla_nx.h

1027

uint8_t driver_code;

drivers/scsi/qla2xxx/qla_nx.h

1028

uint8_t driver_flags;

drivers/scsi/qla2xxx/qla_nx.h

1039

uint8_t addr_stride;

drivers/scsi/qla2xxx/qla_nx.h

1040

uint8_t state_index_a;

drivers/scsi/qla2xxx/qla_nx.h

1048

uint8_t opcode;

drivers/scsi/qla2xxx/qla_nx.h

1049

uint8_t state_index_v;

drivers/scsi/qla2xxx/qla_nx.h

1050

uint8_t shl;

drivers/scsi/qla2xxx/qla_nx.h

1051

uint8_t shr;

drivers/scsi/qla2xxx/qla_nx.h

1077

uint8_t poll_mask;

drivers/scsi/qla2xxx/qla_nx.h

1078

uint8_t poll_wait;

drivers/scsi/qla2xxx/qla_nx.h

1083

uint8_t read_addr_stride;

drivers/scsi/qla2xxx/qla_nx.h

1084

uint8_t read_addr_cnt;

drivers/scsi/qla2xxx/qla_nx.h

1157

uint8_t read_addr_stride;

drivers/scsi/qla2xxx/qla_nx.h

1158

uint8_t read_addr_cnt;

drivers/scsi/qla2xxx/qla_nx.h

856

uint8_t crn;

drivers/scsi/qla2xxx/qla_nx.h

857

uint8_t task_attribute;

drivers/scsi/qla2xxx/qla_nx.h

858

uint8_t task_management;

drivers/scsi/qla2xxx/qla_nx.h

859

uint8_t additional_cdb_len;

drivers/scsi/qla2xxx/qla_nx.h

862

uint8_t cdb[QLA_CDB_BUF_SIZE + QLA_FCP_DL_SIZE]; /* 256 for CDB len and 4 for FCP_DL */

drivers/scsi/qla2xxx/qla_nx2.c

1031

uint32_t flash_addr, uint8_t *p_data, int u32_word_count)

drivers/scsi/qla2xxx/qla_nx2.c

1216

uint8_t *p_cache;

drivers/scsi/qla2xxx/qla_nx2.c

1516

uint8_t *p_buff;

drivers/scsi/qla2xxx/qla_nx2.c

2903

uint8_t *data_ptr = (uint8_t *)*d_ptr;

drivers/scsi/qla2xxx/qla_nx2.c

2994

uint8_t stride, stride2;

drivers/scsi/qla2xxx/qla_nx2.c

3090

uint8_t stride1, stride2;

drivers/scsi/qla2xxx/qla_nx2.c

3270

data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);

drivers/scsi/qla2xxx/qla_nx2.c

3302

(((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);

drivers/scsi/qla2xxx/qla_nx2.c

3439

data_collected = (uint8_t *)data_ptr -

drivers/scsi/qla2xxx/qla_nx2.c

3440

(uint8_t *)((uint8_t *)ha->md_dump);

drivers/scsi/qla2xxx/qla_nx2.c

3446

(((uint8_t *)entry_hdr) + entry_hdr->entry_size);

drivers/scsi/qla2xxx/qla_nx2.c

3793

uint8_t *p_cache, *p_src;

drivers/scsi/qla2xxx/qla_nx2.c

3797

p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);

drivers/scsi/qla2xxx/qla_nx2.c

507

qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,

drivers/scsi/qla2xxx/qla_nx2.c

664

uint8_t retries;

drivers/scsi/qla2xxx/qla_nx2.h

248

uint8_t shl;

drivers/scsi/qla2xxx/qla_nx2.h

249

uint8_t shr;

drivers/scsi/qla2xxx/qla_nx2.h

250

uint8_t index_a;

drivers/scsi/qla2xxx/qla_nx2.h

251

uint8_t rsvd;

drivers/scsi/qla2xxx/qla_nx2.h

273

uint8_t *buff;

drivers/scsi/qla2xxx/qla_nx2.h

274

uint8_t *stop_offset;

drivers/scsi/qla2xxx/qla_nx2.h

275

uint8_t *start_offset;

drivers/scsi/qla2xxx/qla_nx2.h

276

uint8_t *init_offset;

drivers/scsi/qla2xxx/qla_nx2.h

278

uint8_t seq_end;

drivers/scsi/qla2xxx/qla_nx2.h

279

uint8_t template_end;

drivers/scsi/qla2xxx/qla_nx2.h

290

uint8_t entry_capture_mask;

drivers/scsi/qla2xxx/qla_nx2.h

291

uint8_t entry_code;

drivers/scsi/qla2xxx/qla_nx2.h

292

uint8_t driver_code;

drivers/scsi/qla2xxx/qla_nx2.h

293

uint8_t driver_flags;

drivers/scsi/qla2xxx/qla_nx2.h

302

uint8_t addr_stride;

drivers/scsi/qla2xxx/qla_nx2.h

303

uint8_t state_index_a;

drivers/scsi/qla2xxx/qla_nx2.h

310

uint8_t opcode;

drivers/scsi/qla2xxx/qla_nx2.h

311

uint8_t state_index_v;

drivers/scsi/qla2xxx/qla_nx2.h

312

uint8_t shl;

drivers/scsi/qla2xxx/qla_nx2.h

313

uint8_t shr;

drivers/scsi/qla2xxx/qla_nx2.h

333

uint8_t poll_mask;

drivers/scsi/qla2xxx/qla_nx2.h

334

uint8_t poll_wait;

drivers/scsi/qla2xxx/qla_nx2.h

338

uint8_t read_addr_stride;

drivers/scsi/qla2xxx/qla_nx2.h

339

uint8_t read_addr_cnt;

drivers/scsi/qla2xxx/qla_nx2.h

370

uint8_t rsvd[2];

drivers/scsi/qla2xxx/qla_nx2.h

372

uint8_t rsvd2[12];

drivers/scsi/qla2xxx/qla_nx2.h

412

uint8_t read_addr_stride;

drivers/scsi/qla2xxx/qla_nx2.h

413

uint8_t read_addr_cnt;

drivers/scsi/qla2xxx/qla_nx2.h

436

uint8_t stride;

drivers/scsi/qla2xxx/qla_nx2.h

437

uint8_t stride2;

drivers/scsi/qla2xxx/qla_nx2.h

453

uint8_t stride_1;

drivers/scsi/qla2xxx/qla_nx2.h

454

uint8_t stride_2;

drivers/scsi/qla2xxx/qla_nx2.h

486

uint8_t select_value_stride;

drivers/scsi/qla2xxx/qla_nx2.h

487

uint8_t data_size;

drivers/scsi/qla2xxx/qla_nx2.h

488

uint8_t rsvd[2];

drivers/scsi/qla2xxx/qla_nx2.h

571

uint8_t rsvd[2];

drivers/scsi/qla2xxx/qla_nx2.h

576

uint8_t rsvd[24];

drivers/scsi/qla2xxx/qla_os.c

5296

uint8_t free_fcport = 0;

drivers/scsi/qla2xxx/qla_os.c

6071

uint8_t *sfp = NULL;

drivers/scsi/qla2xxx/qla_sup.c

105

uint8_t cnt;

drivers/scsi/qla2xxx/qla_sup.c

1423

uint8_t *

drivers/scsi/qla2xxx/qla_sup.c

1442

uint8_t *

drivers/scsi/qla2xxx/qla_sup.c

1546

uint8_t *

drivers/scsi/qla2xxx/qla_sup.c

1573

uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE);

drivers/scsi/qla2xxx/qla_sup.c

2050

static uint8_t

drivers/scsi/qla2xxx/qla_sup.c

2071

return (uint8_t)data;

drivers/scsi/qla2xxx/qla_sup.c

2102

return (uint8_t)data;

drivers/scsi/qla2xxx/qla_sup.c

2112

qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)

drivers/scsi/qla2xxx/qla_sup.c

2175

qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,

drivers/scsi/qla2xxx/qla_sup.c

2176

uint8_t man_id, uint8_t flash_id)

drivers/scsi/qla2xxx/qla_sup.c

2179

uint8_t flash_data;

drivers/scsi/qla2xxx/qla_sup.c

2216

uint8_t data, uint8_t man_id, uint8_t flash_id)

drivers/scsi/qla2xxx/qla_sup.c

2252

qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)

drivers/scsi/qla2xxx/qla_sup.c

2289

uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)

drivers/scsi/qla2xxx/qla_sup.c

2315

qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,

drivers/scsi/qla2xxx/qla_sup.c

2316

uint8_t *flash_id)

drivers/scsi/qla2xxx/qla_sup.c

2329

qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,

drivers/scsi/qla2xxx/qla_sup.c

2334

uint8_t data;

drivers/scsi/qla2xxx/qla_sup.c

2400

uint8_t *data;

drivers/scsi/qla2xxx/qla_sup.c

2435

uint8_t man_id, flash_id, sec_number, *data;

drivers/scsi/qla2xxx/qla_sup.c

2675

uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf)

drivers/scsi/qla2xxx/qla_sup.c

2684

memcpy(sfub_buf, (uint8_t *)p,

drivers/scsi/qla2xxx/qla_sup.c

2718

memcpy((uint8_t *)region, flt_reg,

drivers/scsi/qla2xxx/qla_sup.c

2845

dwords, buf_size_without_sfub, (uint8_t *)sfub);

drivers/scsi/qla2xxx/qla_sup.c

3055

uint8_t *pbuf;

drivers/scsi/qla2xxx/qla_sup.c

3141

uint8_t do_next, rbyte, *vbyte;

drivers/scsi/qla2xxx/qla_sup.c

3214

uint8_t code_type, last_image;

drivers/scsi/qla2xxx/qla_sup.c

3216

uint8_t *dbyte;

drivers/scsi/qla2xxx/qla_sup.c

3348

uint8_t *bcode = mbuf;

drivers/scsi/qla2xxx/qla_sup.c

3349

uint8_t code_type, last_image;

drivers/scsi/qla2xxx/qla_sup.c

3457

uint8_t *bcode = mbuf;

drivers/scsi/qla2xxx/qla_sup.c

3458

uint8_t code_type, last_image;

drivers/scsi/qla2xxx/qla_sup.c

3621

qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)

drivers/scsi/qla2xxx/qla_sup.c

3641

uint8_t *pos = ha->vpd;

drivers/scsi/qla2xxx/qla_sup.c

3642

uint8_t *end = pos + ha->vpd_size;

drivers/scsi/qla2xxx/qla_sup.c

517

qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,

drivers/scsi/qla2xxx/qla_sup.c

518

uint8_t *flash_id)

drivers/scsi/qla2xxx/qla_sup.c

557

uint8_t *buf = (void *)req->ring, *bcode, last_image;

drivers/scsi/qla2xxx/qla_sup.c

971

uint8_t man_id, flash_id;

drivers/scsi/qla2xxx/qla_target.c

102

struct atio_from_isp *pkt, uint8_t);

drivers/scsi/qla2xxx/qla_target.c

114

uint16_t srr_flags, uint16_t srr_reject_code, uint8_t srr_explan);

drivers/scsi/qla2xxx/qla_target.c

1655

uint16_t srr_flags, uint16_t srr_reject_code, uint8_t srr_explan)

drivers/scsi/qla2xxx/qla_target.c

1724

uint8_t *p;

drivers/scsi/qla2xxx/qla_target.c

1767

p = (uint8_t *)&f_ctl;

drivers/scsi/qla2xxx/qla_target.c

1813

uint8_t *p;

drivers/scsi/qla2xxx/qla_target.c

1839

p = (uint8_t *)&f_ctl;

drivers/scsi/qla2xxx/qla_target.c

208

struct atio_from_isp *atio, uint8_t ha_locked)

drivers/scsi/qla2xxx/qla_target.c

2247

uint8_t scsi_status, uint8_t sense_key, uint8_t asc, uint8_t ascq)

drivers/scsi/qla2xxx/qla_target.c

2511

uint8_t found = 0;

drivers/scsi/qla2xxx/qla_target.c

253

uint8_t ha_locked)

drivers/scsi/qla2xxx/qla_target.c

2557

pkt->entry_count = (uint8_t)prm->req_cnt;

drivers/scsi/qla2xxx/qla_target.c

259

uint8_t queued = 0;

drivers/scsi/qla2xxx/qla_target.c

2727

struct qla_tgt_prm *prm, int xmit_type, uint8_t scsi_status,

drivers/scsi/qla2xxx/qla_target.c

2999

uint8_t bundling = 1;

drivers/scsi/qla2xxx/qla_target.c

310

struct atio_from_isp *atio, uint8_t ha_locked)

drivers/scsi/qla2xxx/qla_target.c

3162

memset((uint8_t *)&tc, 0 , sizeof(tc));

drivers/scsi/qla2xxx/qla_target.c

3205

uint8_t scsi_status)

drivers/scsi/qla2xxx/qla_target.c

3469

uint8_t *ap = &sts->actual_dif[0];

drivers/scsi/qla2xxx/qla_target.c

3470

uint8_t *ep = &sts->expected_dif[0];

drivers/scsi/qla2xxx/qla_target.c

3472

uint8_t scsi_status, sense_key, asc, ascq;

drivers/scsi/qla2xxx/qla_target.c

4005

struct rsp_que *rsp, uint32_t handle, uint8_t cmd_type,

drivers/scsi/qla2xxx/qla_target.c

4371

uint8_t task_codes)

drivers/scsi/qla2xxx/qla_target.c

5387

uint8_t srr_explain = NOTIFY_ACK_SRR_FLAGS_REJECT_EXPL_NO_EXPL;

drivers/scsi/qla2xxx/qla_target.c

5840

uint8_t op = cmd->cdb ? cmd->cdb[0] : 0;

drivers/scsi/qla2xxx/qla_target.c

6722

struct atio_from_isp *atio, uint8_t ha_locked)

drivers/scsi/qla2xxx/qla_target.c

6742

struct atio_from_isp *atio, uint8_t ha_locked)

drivers/scsi/qla2xxx/qla_target.c

6881

vha, 0xffff, (uint8_t *)entry, sizeof(*entry));

drivers/scsi/qla2xxx/qla_target.c

7871

qlt_24xx_process_atio_queue(struct scsi_qla_host *vha, uint8_t ha_locked)

drivers/scsi/qla2xxx/qla_target.h

1144

extern int qlt_xmit_response(struct qla_tgt_cmd *, int, uint8_t);

drivers/scsi/qla2xxx/qla_target.h

1159

extern void qlt_24xx_process_atio_queue(struct scsi_qla_host *, uint8_t);

drivers/scsi/qla2xxx/qla_target.h

1181

void qlt_send_resp_ctio(struct qla_qpair *, struct qla_tgt_cmd *, uint8_t,

drivers/scsi/qla2xxx/qla_target.h

1182

uint8_t, uint8_t, uint8_t);

drivers/scsi/qla2xxx/qla_target.h

131

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

132

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

133

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

134

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

139

uint8_t target_id;

drivers/scsi/qla2xxx/qla_target.h

140

uint8_t reserved_1;

drivers/scsi/qla2xxx/qla_target.h

151

uint8_t srr_reject_vendor_uniq;

drivers/scsi/qla2xxx/qla_target.h

152

uint8_t srr_reject_code_expl;

drivers/scsi/qla2xxx/qla_target.h

153

uint8_t reserved_2[24];

drivers/scsi/qla2xxx/qla_target.h

162

uint8_t status_subcode;

drivers/scsi/qla2xxx/qla_target.h

163

uint8_t fw_handle;

drivers/scsi/qla2xxx/qla_target.h

168

uint8_t reserved_4[19];

drivers/scsi/qla2xxx/qla_target.h

169

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_target.h

170

uint8_t srr_reject_vendor_uniq;

drivers/scsi/qla2xxx/qla_target.h

171

uint8_t srr_reject_code_expl;

drivers/scsi/qla2xxx/qla_target.h

172

uint8_t srr_reject_code;

drivers/scsi/qla2xxx/qla_target.h

173

uint8_t reserved_5[5];

drivers/scsi/qla2xxx/qla_target.h

176

uint8_t reserved[2];

drivers/scsi/qla2xxx/qla_target.h

204

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

205

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

206

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

207

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

255

uint8_t r_ctl;

drivers/scsi/qla2xxx/qla_target.h

257

uint8_t cs_ctl;

drivers/scsi/qla2xxx/qla_target.h

259

uint8_t type;

drivers/scsi/qla2xxx/qla_target.h

260

uint8_t f_ctl[3];

drivers/scsi/qla2xxx/qla_target.h

261

uint8_t seq_id;

drivers/scsi/qla2xxx/qla_target.h

262

uint8_t df_ctl;

drivers/scsi/qla2xxx/qla_target.h

271

uint8_t r_ctl;

drivers/scsi/qla2xxx/qla_target.h

273

uint8_t cs_ctl;

drivers/scsi/qla2xxx/qla_target.h

274

uint8_t f_ctl[3];

drivers/scsi/qla2xxx/qla_target.h

275

uint8_t type;

drivers/scsi/qla2xxx/qla_target.h

277

uint8_t df_ctl;

drivers/scsi/qla2xxx/qla_target.h

278

uint8_t seq_id;

drivers/scsi/qla2xxx/qla_target.h

296

uint8_t cmnd_ref;

drivers/scsi/qla2xxx/qla_target.h

297

uint8_t task_attr:3;

drivers/scsi/qla2xxx/qla_target.h

298

uint8_t reserved:5;

drivers/scsi/qla2xxx/qla_target.h

299

uint8_t task_mgmt_flags;

drivers/scsi/qla2xxx/qla_target.h

305

uint8_t wrdata:1;

drivers/scsi/qla2xxx/qla_target.h

306

uint8_t rddata:1;

drivers/scsi/qla2xxx/qla_target.h

307

uint8_t add_cdb_len:6;

drivers/scsi/qla2xxx/qla_target.h

308

uint8_t cdb[16];

drivers/scsi/qla2xxx/qla_target.h

314

uint8_t add_cdb[4];

drivers/scsi/qla2xxx/qla_target.h

326

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

327

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

333

uint8_t command_ref;

drivers/scsi/qla2xxx/qla_target.h

334

uint8_t task_codes;

drivers/scsi/qla2xxx/qla_target.h

335

uint8_t task_flags;

drivers/scsi/qla2xxx/qla_target.h

336

uint8_t execution_codes;

drivers/scsi/qla2xxx/qla_target.h

337

uint8_t cdb[MAX_CMDSZ];

drivers/scsi/qla2xxx/qla_target.h

340

uint8_t initiator_port_name[WWN_SIZE]; /* on qla23xx */

drivers/scsi/qla2xxx/qla_target.h

346

uint8_t fcp_cmnd_len_low;

drivers/scsi/qla2xxx/qla_target.h

347

uint8_t fcp_cmnd_len_high:4;

drivers/scsi/qla2xxx/qla_target.h

348

uint8_t attr:4;

drivers/scsi/qla2xxx/qla_target.h

355

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

356

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

360

uint8_t data[56];

drivers/scsi/qla2xxx/qla_target.h

399

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

400

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

401

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

402

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

408

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_target.h

409

uint8_t add_flags;

drivers/scsi/qla2xxx/qla_target.h

411

uint8_t reserved;

drivers/scsi/qla2xxx/qla_target.h

420

uint8_t rsvd1;

drivers/scsi/qla2xxx/qla_target.h

421

uint8_t edif_flags;

drivers/scsi/qla2xxx/qla_target.h

443

uint8_t sense_data[24];

drivers/scsi/qla2xxx/qla_target.h

453

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

454

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

455

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

456

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

461

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_target.h

462

uint8_t reserved1[5];

drivers/scsi/qla2xxx/qla_target.h

470

uint8_t reserved4[24];

drivers/scsi/qla2xxx/qla_target.h

500

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

502

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

503

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

504

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

511

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_target.h

512

uint8_t add_flags; /* additional flags */

drivers/scsi/qla2xxx/qla_target.h

516

uint8_t reserved1;

drivers/scsi/qla2xxx/qla_target.h

534

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

535

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

536

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

537

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

552

uint8_t reserved3[12];

drivers/scsi/qla2xxx/qla_target.h

554

uint8_t actual_dif[8];

drivers/scsi/qla2xxx/qla_target.h

555

uint8_t expected_dif[8];

drivers/scsi/qla2xxx/qla_target.h

571

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

572

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

573

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

574

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

575

uint8_t reserved_1[6];

drivers/scsi/qla2xxx/qla_target.h

577

uint8_t reserved_2[2];

drivers/scsi/qla2xxx/qla_target.h

578

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_target.h

579

uint8_t reserved_3:4;

drivers/scsi/qla2xxx/qla_target.h

580

uint8_t sof_type:4;

drivers/scsi/qla2xxx/qla_target.h

583

uint8_t reserved_4[16];

drivers/scsi/qla2xxx/qla_target.h

591

uint8_t seq_id_last;

drivers/scsi/qla2xxx/qla_target.h

592

uint8_t seq_id_valid;

drivers/scsi/qla2xxx/qla_target.h

602

uint8_t vendor_uniq;

drivers/scsi/qla2xxx/qla_target.h

603

uint8_t reason_expl;

drivers/scsi/qla2xxx/qla_target.h

604

uint8_t reason_code;

drivers/scsi/qla2xxx/qla_target.h

607

uint8_t reserved;

drivers/scsi/qla2xxx/qla_target.h

617

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

618

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

619

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

620

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

626

uint8_t vp_index;

drivers/scsi/qla2xxx/qla_target.h

627

uint8_t reserved_3:4;

drivers/scsi/qla2xxx/qla_target.h

628

uint8_t sof_type:4;

drivers/scsi/qla2xxx/qla_target.h

647

uint8_t entry_type; /* Entry type. */

drivers/scsi/qla2xxx/qla_target.h

648

uint8_t entry_count; /* Entry count. */

drivers/scsi/qla2xxx/qla_target.h

649

uint8_t sys_define; /* System defined. */

drivers/scsi/qla2xxx/qla_target.h

650

uint8_t entry_status; /* Entry Status. */

drivers/scsi/qla2xxx/qla_target.h

657

uint8_t reserved_2;

drivers/scsi/qla2xxx/qla_target.h

658

uint8_t reserved_3:4;

drivers/scsi/qla2xxx/qla_target.h

659

uint8_t sof_type:4;

drivers/scsi/qla2xxx/qla_target.h

662

uint8_t reserved_4[8];

drivers/scsi/qla2xxx/qla_target.h

778

(((const uint8_t *)(sense))[0] & 0x70) == 0x70)

drivers/scsi/qla2xxx/qla_target.h

781

uint8_t port_name[WWN_SIZE];

drivers/scsi/qla2xxx/qla_target.h

790

uint8_t cmd_cnt;

drivers/scsi/qla2xxx/qla_target.h

880

uint8_t cmd_type;

drivers/scsi/qla2xxx/qla_target.h

881

uint8_t pad[7];

drivers/scsi/qla2xxx/qla_target.h

938

uint8_t ctx_dsd_alloced;

drivers/scsi/qla2xxx/qla_target.h

949

uint8_t scsi_status, sense_key, asc, ascq;

drivers/scsi/qla2xxx/qla_target.h

952

uint8_t *cdb;

drivers/scsi/qla2xxx/qla_target.h

989

uint8_t cmd_type;

drivers/scsi/qla2xxx/qla_target.h

990

uint8_t pad[3];

drivers/scsi/qla2xxx/qla_target.h

992

uint8_t fc_tm_rsp;

drivers/scsi/qla2xxx/qla_target.h

993

uint8_t abort_io_attr;

drivers/scsi/qla2xxx/qla_tmpl.c

47

uint8_t value = ~0;

drivers/scsi/qla2xxx/qla_tmpl.c

883

uint8_t v[] = { 0, 0, 0, 0, 0, 0 };

drivers/scsi/qla2xxx/qla_tmpl.h

100

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

101

uint8_t banksel_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

102

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

109

uint8_t reserved[2];

drivers/scsi/qla2xxx/qla_tmpl.h

110

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

111

uint8_t banksel_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

116

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

117

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

121

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

122

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

127

uint8_t ram_area;

drivers/scsi/qla2xxx/qla_tmpl.h

128

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

135

uint8_t queue_type;

drivers/scsi/qla2xxx/qla_tmpl.h

136

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

158

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

159

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

164

uint8_t buf_type;

drivers/scsi/qla2xxx/qla_tmpl.h

165

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

196

uint8_t queue_type;

drivers/scsi/qla2xxx/qla_tmpl.h

197

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

202

uint8_t buffer[];

drivers/scsi/qla2xxx/qla_tmpl.h

71

uint8_t capture_flags;

drivers/scsi/qla2xxx/qla_tmpl.h

72

uint8_t reserved_2[2];

drivers/scsi/qla2xxx/qla_tmpl.h

73

uint8_t driver_flags;

drivers/scsi/qla2xxx/qla_tmpl.h

84

uint8_t reg_width;

drivers/scsi/qla2xxx/qla_tmpl.h

86

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

92

uint8_t pci_offset;

drivers/scsi/qla2xxx/qla_tmpl.h

93

uint8_t reserved[3];

drivers/scsi/qla2xxx/qla_tmpl.h

98

uint8_t reg_width;

drivers/scsi/qla4xxx/ql4_83xx.c

110

uint8_t *p_data, int u32_word_count)

drivers/scsi/qla4xxx/ql4_83xx.c

160

uint32_t flash_addr, uint8_t *p_data,

drivers/scsi/qla4xxx/ql4_83xx.c

585

(uint8_t *)&idc_params, 1);

drivers/scsi/qla4xxx/ql4_83xx.c

604

uint8_t *phdr;

drivers/scsi/qla4xxx/ql4_83xx.c

624

uint8_t *p_cache;

drivers/scsi/qla4xxx/ql4_83xx.c

712

uint8_t retries;

drivers/scsi/qla4xxx/ql4_83xx.c

775

uint8_t *p_buff;

drivers/scsi/qla4xxx/ql4_83xx.h

191

uint8_t shl;

drivers/scsi/qla4xxx/ql4_83xx.h

192

uint8_t shr;

drivers/scsi/qla4xxx/ql4_83xx.h

193

uint8_t index_a;

drivers/scsi/qla4xxx/ql4_83xx.h

194

uint8_t rsvd;

drivers/scsi/qla4xxx/ql4_83xx.h

216

uint8_t *buff;

drivers/scsi/qla4xxx/ql4_83xx.h

217

uint8_t *stop_offset;

drivers/scsi/qla4xxx/ql4_83xx.h

218

uint8_t *start_offset;

drivers/scsi/qla4xxx/ql4_83xx.h

219

uint8_t *init_offset;

drivers/scsi/qla4xxx/ql4_83xx.h

221

uint8_t seq_end;

drivers/scsi/qla4xxx/ql4_83xx.h

222

uint8_t template_end;

drivers/scsi/qla4xxx/ql4_83xx.h

243

uint8_t stride;

drivers/scsi/qla4xxx/ql4_83xx.h

244

uint8_t stride2;

drivers/scsi/qla4xxx/ql4_83xx.h

260

uint8_t stride_1;

drivers/scsi/qla4xxx/ql4_83xx.h

261

uint8_t stride_2;

drivers/scsi/qla4xxx/ql4_83xx.h

293

uint8_t select_value_stride;

drivers/scsi/qla4xxx/ql4_83xx.h

294

uint8_t data_size;

drivers/scsi/qla4xxx/ql4_83xx.h

295

uint8_t rsvd[2];

drivers/scsi/qla4xxx/ql4_83xx.h

334

uint8_t rsvd[2];

drivers/scsi/qla4xxx/ql4_83xx.h

336

uint8_t rsvd2[12];

drivers/scsi/qla4xxx/ql4_83xx.h

344

uint8_t rsvd[2];

drivers/scsi/qla4xxx/ql4_83xx.h

350

uint8_t rsvd[24];

drivers/scsi/qla4xxx/ql4_bsg.c

209

uint8_t *nvram = NULL;

drivers/scsi/qla4xxx/ql4_bsg.c

21

uint8_t *flash = NULL;

drivers/scsi/qla4xxx/ql4_bsg.c

281

uint8_t *nvram = NULL;

drivers/scsi/qla4xxx/ql4_bsg.c

393

uint8_t *acb = NULL;

drivers/scsi/qla4xxx/ql4_bsg.c

454

uint8_t *rsp_ptr = NULL;

drivers/scsi/qla4xxx/ql4_bsg.c

494

rsp_ptr = ((uint8_t *)bsg_reply) + sizeof(struct iscsi_bsg_reply);

drivers/scsi/qla4xxx/ql4_bsg.c

658

uint8_t *rsp_ptr = NULL;

drivers/scsi/qla4xxx/ql4_bsg.c

722

rsp_ptr = ((uint8_t *)bsg_reply) + sizeof(struct iscsi_bsg_reply);

drivers/scsi/qla4xxx/ql4_bsg.c

87

uint8_t *flash = NULL;

drivers/scsi/qla4xxx/ql4_dbg.c

100

printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)

drivers/scsi/qla4xxx/ql4_dbg.c

105

printk(KERN_INFO "0x%02X ext_hw_conf = 0x%08X\n", (uint8_t)

drivers/scsi/qla4xxx/ql4_dbg.c

108

printk(KERN_INFO "0x%02X port_ctrl = 0x%08X\n", (uint8_t)

drivers/scsi/qla4xxx/ql4_dbg.c

111

printk(KERN_INFO "0x%02X port_status = 0x%08X\n", (uint8_t)

drivers/scsi/qla4xxx/ql4_dbg.c

115

(uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out),

drivers/scsi/qla4xxx/ql4_dbg.c

118

(uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in),

drivers/scsi/qla4xxx/ql4_dbg.c

120

printk(KERN_INFO "0x%02X port_err_status = 0x%08X\n", (uint8_t)

drivers/scsi/qla4xxx/ql4_dbg.c

127

(uint8_t) offsetof(struct isp_reg, u2.isp4022.p1.req_q_out),

drivers/scsi/qla4xxx/ql4_dbg.c

15

uint8_t *c = b;

drivers/scsi/qla4xxx/ql4_dbg.c

34

uint8_t i;

drivers/scsi/qla4xxx/ql4_dbg.c

45

(uint8_t) offsetof(struct isp_reg, mailbox[i]), i,

drivers/scsi/qla4xxx/ql4_dbg.c

50

(uint8_t) offsetof(struct isp_reg, flash_address),

drivers/scsi/qla4xxx/ql4_dbg.c

53

(uint8_t) offsetof(struct isp_reg, flash_data),

drivers/scsi/qla4xxx/ql4_dbg.c

56

(uint8_t) offsetof(struct isp_reg, ctrl_status),

drivers/scsi/qla4xxx/ql4_dbg.c

61

(uint8_t) offsetof(struct isp_reg, u1.isp4010.nvram),

drivers/scsi/qla4xxx/ql4_dbg.c

65

(uint8_t) offsetof(struct isp_reg, u1.isp4022.intr_mask),

drivers/scsi/qla4xxx/ql4_dbg.c

68

(uint8_t) offsetof(struct isp_reg, u1.isp4022.nvram),

drivers/scsi/qla4xxx/ql4_dbg.c

71

(uint8_t) offsetof(struct isp_reg, u1.isp4022.semaphore),

drivers/scsi/qla4xxx/ql4_dbg.c

75

(uint8_t) offsetof(struct isp_reg, req_q_in),

drivers/scsi/qla4xxx/ql4_dbg.c

78

(uint8_t) offsetof(struct isp_reg, rsp_q_out),

drivers/scsi/qla4xxx/ql4_dbg.c

83

(uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf),

drivers/scsi/qla4xxx/ql4_dbg.c

86

(uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl),

drivers/scsi/qla4xxx/ql4_dbg.c

89

(uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status),

drivers/scsi/qla4xxx/ql4_dbg.c

92

(uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out),

drivers/scsi/qla4xxx/ql4_dbg.c

95

(uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out),

drivers/scsi/qla4xxx/ql4_dbg.c

98

(uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_in),

drivers/scsi/qla4xxx/ql4_def.h

242

uint8_t state; /* (1) Status flags. */

drivers/scsi/qla4xxx/ql4_def.h

253

uint8_t err_id; /* error id */

drivers/scsi/qla4xxx/ql4_def.h

265

uint8_t *req_sense_ptr;

drivers/scsi/qla4xxx/ql4_def.h

331

uint8_t flash_isid[6];

drivers/scsi/qla4xxx/ql4_def.h

344

uint8_t isid[6];

drivers/scsi/qla4xxx/ql4_def.h

378

uint8_t data[];

drivers/scsi/qla4xxx/ql4_def.h

384

uint8_t data[];

drivers/scsi/qla4xxx/ql4_def.h

469

uint8_t ipv4_addr_state;

drivers/scsi/qla4xxx/ql4_def.h

470

uint8_t ip_address[IP_ADDR_LEN];

drivers/scsi/qla4xxx/ql4_def.h

471

uint8_t subnet_mask[IP_ADDR_LEN];

drivers/scsi/qla4xxx/ql4_def.h

472

uint8_t gateway[IP_ADDR_LEN];

drivers/scsi/qla4xxx/ql4_def.h

475

uint8_t ipv6_link_local_state;

drivers/scsi/qla4xxx/ql4_def.h

476

uint8_t ipv6_addr0_state;

drivers/scsi/qla4xxx/ql4_def.h

477

uint8_t ipv6_addr1_state;

drivers/scsi/qla4xxx/ql4_def.h

478

uint8_t ipv6_default_router_state;

drivers/scsi/qla4xxx/ql4_def.h

487

uint8_t control;

drivers/scsi/qla4xxx/ql4_def.h

489

uint8_t tcp_wsf;

drivers/scsi/qla4xxx/ql4_def.h

490

uint8_t ipv6_tcp_wsf;

drivers/scsi/qla4xxx/ql4_def.h

491

uint8_t ipv4_tos;

drivers/scsi/qla4xxx/ql4_def.h

492

uint8_t ipv4_cache_id;

drivers/scsi/qla4xxx/ql4_def.h

493

uint8_t ipv6_cache_id;

drivers/scsi/qla4xxx/ql4_def.h

494

uint8_t ipv4_alt_cid_len;

drivers/scsi/qla4xxx/ql4_def.h

495

uint8_t ipv4_alt_cid[11];

drivers/scsi/qla4xxx/ql4_def.h

496

uint8_t ipv4_vid_len;

drivers/scsi/qla4xxx/ql4_def.h

497

uint8_t ipv4_vid[11];

drivers/scsi/qla4xxx/ql4_def.h

498

uint8_t ipv4_ttl;

drivers/scsi/qla4xxx/ql4_def.h

500

uint8_t ipv6_traffic_class;

drivers/scsi/qla4xxx/ql4_def.h

501

uint8_t ipv6_hop_limit;

drivers/scsi/qla4xxx/ql4_def.h

505

uint8_t ipv6_dup_addr_detect_count;

drivers/scsi/qla4xxx/ql4_def.h

508

uint8_t abort_timer;

drivers/scsi/qla4xxx/ql4_def.h

514

uint8_t iscsi_name[224];

drivers/scsi/qla4xxx/ql4_def.h

656

uint8_t alias[32];

drivers/scsi/qla4xxx/ql4_def.h

657

uint8_t name_string[256];

drivers/scsi/qla4xxx/ql4_def.h

658

uint8_t heartbeat_interval;

drivers/scsi/qla4xxx/ql4_def.h

661

uint8_t my_mac[MAC_ADDR_LEN];

drivers/scsi/qla4xxx/ql4_def.h

662

uint8_t serial_number[16];

drivers/scsi/qla4xxx/ql4_def.h

722

volatile uint8_t mbox_status_count;

drivers/scsi/qla4xxx/ql4_def.h

731

uint8_t acb_version;

drivers/scsi/qla4xxx/ql4_def.h

736

uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */

drivers/scsi/qla4xxx/ql4_def.h

754

uint8_t revision_id;

drivers/scsi/qla4xxx/ql4_def.h

787

uint8_t *chap_list; /* CHAP table cache */

drivers/scsi/qla4xxx/ql4_def.h

799

uint8_t model_name[16];

drivers/scsi/qla4xxx/ql4_def.h

834

uint8_t iocb_req_cnt;

drivers/scsi/qla4xxx/ql4_fw.h

1005

uint8_t extended_timestamp[180];/* 4C - FF */

drivers/scsi/qla4xxx/ql4_fw.h

1014

uint8_t build_date[16]; /* 08 - 17 */

drivers/scsi/qla4xxx/ql4_fw.h

1015

uint8_t build_time[16]; /* 18 - 27 */

drivers/scsi/qla4xxx/ql4_fw.h

1016

uint8_t build_user[16]; /* 28 - 37 */

drivers/scsi/qla4xxx/ql4_fw.h

1017

uint8_t card_serial_num[16]; /* 38 - 47 */

drivers/scsi/qla4xxx/ql4_fw.h

1027

uint8_t reserved1[28]; /* 58 - 7F */

drivers/scsi/qla4xxx/ql4_fw.h

1029

uint8_t out_RISC_reg_dump[256]; /* 80 -17F */

drivers/scsi/qla4xxx/ql4_fw.h

1030

uint8_t in_RISC_reg_dump[256]; /*180 -27F */

drivers/scsi/qla4xxx/ql4_fw.h

1031

uint8_t in_out_RISC_stack_dump[]; /*280 - ??? */

drivers/scsi/qla4xxx/ql4_fw.h

1040

uint8_t event_type; /* 0C - 0C */

drivers/scsi/qla4xxx/ql4_fw.h

1041

uint8_t error_code; /* 0D - 0D */

drivers/scsi/qla4xxx/ql4_fw.h

1043

uint8_t num_consecutive_events; /* 10 - 10 */

drivers/scsi/qla4xxx/ql4_fw.h

1044

uint8_t rsvd[3]; /* 11 - 13 */

drivers/scsi/qla4xxx/ql4_fw.h

1058

uint8_t entryType;

drivers/scsi/qla4xxx/ql4_fw.h

1069

uint8_t entryStatus;

drivers/scsi/qla4xxx/ql4_fw.h

1070

uint8_t systemDefined;

drivers/scsi/qla4xxx/ql4_fw.h

1072

uint8_t entryCount;

drivers/scsi/qla4xxx/ql4_fw.h

1079

uint8_t data[60];

drivers/scsi/qla4xxx/ql4_fw.h

1111

uint8_t control_flags; /* 0C */

drivers/scsi/qla4xxx/ql4_fw.h

1128

uint8_t state_flags; /* 0D */

drivers/scsi/qla4xxx/ql4_fw.h

1129

uint8_t cmdRefNum; /* 0E */

drivers/scsi/qla4xxx/ql4_fw.h

1130

uint8_t reserved1; /* 0F */

drivers/scsi/qla4xxx/ql4_fw.h

1131

uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */

drivers/scsi/qla4xxx/ql4_fw.h

1183

uint8_t scsiStatus; /* 08 */

drivers/scsi/qla4xxx/ql4_fw.h

1185

uint8_t iscsiFlags; /* 09 */

drivers/scsi/qla4xxx/ql4_fw.h

1189

uint8_t iscsiResponse; /* 0A */

drivers/scsi/qla4xxx/ql4_fw.h

1191

uint8_t completionStatus; /* 0B */

drivers/scsi/qla4xxx/ql4_fw.h

1203

uint8_t reserved1; /* 0C */

drivers/scsi/qla4xxx/ql4_fw.h

1207

uint8_t state_flags; /* 0D */

drivers/scsi/qla4xxx/ql4_fw.h

1214

uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */

drivers/scsi/qla4xxx/ql4_fw.h

1221

uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */

drivers/scsi/qla4xxx/ql4_fw.h

1244

uint8_t res2[20]; /* 2C-3F */

drivers/scsi/qla4xxx/ql4_fw.h

1253

uint8_t completionStatus; /* 0C */

drivers/scsi/qla4xxx/ql4_fw.h

1256

uint8_t residualFlags; /* 0D */

drivers/scsi/qla4xxx/ql4_fw.h

1260

uint8_t res1[10]; /* 12-1B */

drivers/scsi/qla4xxx/ql4_fw.h

1262

uint8_t res2[12]; /* 20-2B */

drivers/scsi/qla4xxx/ql4_fw.h

1264

uint8_t res4[16]; /* 30-3F */

drivers/scsi/qla4xxx/ql4_fw.h

1285

uint8_t data[60];

drivers/scsi/qla4xxx/ql4_fw.h

1407

uint8_t reserved2[264]; /* 0x0308 - 0x040F */

drivers/scsi/qla4xxx/ql4_fw.h

295

uint8_t sig[4];

drivers/scsi/qla4xxx/ql4_fw.h

299

uint8_t unused1[2];

drivers/scsi/qla4xxx/ql4_fw.h

300

uint8_t model[16];

drivers/scsi/qla4xxx/ql4_fw.h

303

uint8_t flags;

drivers/scsi/qla4xxx/ql4_fw.h

304

uint8_t erase_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

305

uint8_t alt_erase_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

306

uint8_t wrt_enable_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

307

uint8_t wrt_enable_bits;

drivers/scsi/qla4xxx/ql4_fw.h

308

uint8_t wrt_sts_reg_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

309

uint8_t unprotect_sec_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

310

uint8_t read_man_id_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

315

uint8_t read_id_addr_len;

drivers/scsi/qla4xxx/ql4_fw.h

316

uint8_t wrt_disable_bits;

drivers/scsi/qla4xxx/ql4_fw.h

317

uint8_t read_dev_id_len;

drivers/scsi/qla4xxx/ql4_fw.h

318

uint8_t chip_erase_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

320

uint8_t protect_sec_cmd;

drivers/scsi/qla4xxx/ql4_fw.h

321

uint8_t unused2[65];

drivers/scsi/qla4xxx/ql4_fw.h

327

uint8_t sig[4];

drivers/scsi/qla4xxx/ql4_fw.h

330

uint8_t version;

drivers/scsi/qla4xxx/ql4_fw.h

331

uint8_t unused[5];

drivers/scsi/qla4xxx/ql4_fw.h

556

uint8_t version; /* 00 */

drivers/scsi/qla4xxx/ql4_fw.h

559

uint8_t control; /* 01 */

drivers/scsi/qla4xxx/ql4_fw.h

570

uint8_t zio_count; /* 06 */

drivers/scsi/qla4xxx/ql4_fw.h

571

uint8_t res0; /* 07 */

drivers/scsi/qla4xxx/ql4_fw.h

577

uint8_t hb_interval; /* 0C */

drivers/scsi/qla4xxx/ql4_fw.h

578

uint8_t inst_num; /* 0D */

drivers/scsi/qla4xxx/ql4_fw.h

628

uint8_t ipv4_tos; /* 38 */

drivers/scsi/qla4xxx/ql4_fw.h

629

uint8_t ipv4_ttl; /* 39 */

drivers/scsi/qla4xxx/ql4_fw.h

630

uint8_t acb_version; /* 3A */

drivers/scsi/qla4xxx/ql4_fw.h

635

uint8_t res2; /* 3B */

drivers/scsi/qla4xxx/ql4_fw.h

645

uint8_t ipv4_addr[4]; /* 50-53 */

drivers/scsi/qla4xxx/ql4_fw.h

647

uint8_t ipv4_addr_state; /* 56 */

drivers/scsi/qla4xxx/ql4_fw.h

648

uint8_t ipv4_cacheid; /* 57 */

drivers/scsi/qla4xxx/ql4_fw.h

649

uint8_t res6[8]; /* 58-5F */

drivers/scsi/qla4xxx/ql4_fw.h

650

uint8_t ipv4_subnet[4]; /* 60-63 */

drivers/scsi/qla4xxx/ql4_fw.h

651

uint8_t res7[12]; /* 64-6F */

drivers/scsi/qla4xxx/ql4_fw.h

652

uint8_t ipv4_gw_addr[4]; /* 70-73 */

drivers/scsi/qla4xxx/ql4_fw.h

653

uint8_t res8[0xc]; /* 74-7F */

drivers/scsi/qla4xxx/ql4_fw.h

654

uint8_t pri_dns_srvr_ip[4];/* 80-83 */

drivers/scsi/qla4xxx/ql4_fw.h

655

uint8_t sec_dns_srvr_ip[4];/* 84-87 */

drivers/scsi/qla4xxx/ql4_fw.h

658

uint8_t res9[4]; /* 8C-8F */

drivers/scsi/qla4xxx/ql4_fw.h

659

uint8_t iscsi_alias[32];/* 90-AF */

drivers/scsi/qla4xxx/ql4_fw.h

660

uint8_t res9_1[0x16]; /* B0-C5 */

drivers/scsi/qla4xxx/ql4_fw.h

662

uint8_t abort_timer; /* C8 */

drivers/scsi/qla4xxx/ql4_fw.h

663

uint8_t ipv4_tcp_wsf; /* C9 */

drivers/scsi/qla4xxx/ql4_fw.h

664

uint8_t res10[6]; /* CA-CF */

drivers/scsi/qla4xxx/ql4_fw.h

665

uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */

drivers/scsi/qla4xxx/ql4_fw.h

666

uint8_t ipv4_dhcp_vid_len; /* D4 */

drivers/scsi/qla4xxx/ql4_fw.h

667

uint8_t ipv4_dhcp_vid[11]; /* D5-DF */

drivers/scsi/qla4xxx/ql4_fw.h

668

uint8_t res11[20]; /* E0-F3 */

drivers/scsi/qla4xxx/ql4_fw.h

669

uint8_t ipv4_dhcp_alt_cid_len; /* F4 */

drivers/scsi/qla4xxx/ql4_fw.h

670

uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */

drivers/scsi/qla4xxx/ql4_fw.h

671

uint8_t iscsi_name[224]; /* 100-1DF */

drivers/scsi/qla4xxx/ql4_fw.h

672

uint8_t res12[32]; /* 1E0-1FF */

drivers/scsi/qla4xxx/ql4_fw.h

694

uint8_t ipv6_tcp_wsf; /* 20C */

drivers/scsi/qla4xxx/ql4_fw.h

696

uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */

drivers/scsi/qla4xxx/ql4_fw.h

698

uint8_t ipv6_lnk_lcl_addr_state;/* 222 */

drivers/scsi/qla4xxx/ql4_fw.h

699

uint8_t ipv6_addr0_state; /* 223 */

drivers/scsi/qla4xxx/ql4_fw.h

700

uint8_t ipv6_addr1_state; /* 224 */

drivers/scsi/qla4xxx/ql4_fw.h

701

uint8_t ipv6_dflt_rtr_state; /* 225 */

drivers/scsi/qla4xxx/ql4_fw.h

707

uint8_t ipv6_traffic_class; /* 226 */

drivers/scsi/qla4xxx/ql4_fw.h

708

uint8_t ipv6_hop_limit; /* 227 */

drivers/scsi/qla4xxx/ql4_fw.h

709

uint8_t ipv6_if_id[8]; /* 228-22F */

drivers/scsi/qla4xxx/ql4_fw.h

710

uint8_t ipv6_addr0[16]; /* 230-23F */

drivers/scsi/qla4xxx/ql4_fw.h

711

uint8_t ipv6_addr1[16]; /* 240-24F */

drivers/scsi/qla4xxx/ql4_fw.h

715

uint8_t ipv6_dup_addr_detect_count; /* 25C */

drivers/scsi/qla4xxx/ql4_fw.h

716

uint8_t ipv6_cache_id; /* 25D */

drivers/scsi/qla4xxx/ql4_fw.h

717

uint8_t res13[18]; /* 25E-26F */

drivers/scsi/qla4xxx/ql4_fw.h

719

uint8_t res14[140]; /* 274-2FF */

drivers/scsi/qla4xxx/ql4_fw.h

738

uint8_t reserved1[1]; /* 00 */

drivers/scsi/qla4xxx/ql4_fw.h

739

uint8_t control; /* 01 */

drivers/scsi/qla4xxx/ql4_fw.h

740

uint8_t reserved2[11]; /* 02-0C */

drivers/scsi/qla4xxx/ql4_fw.h

741

uint8_t inst_num; /* 0D */

drivers/scsi/qla4xxx/ql4_fw.h

742

uint8_t reserved3[34]; /* 0E-2F */

drivers/scsi/qla4xxx/ql4_fw.h

747

uint8_t ipv4_tos; /* 38 */

drivers/scsi/qla4xxx/ql4_fw.h

748

uint8_t ipv4_ttl; /* 39 */

drivers/scsi/qla4xxx/ql4_fw.h

749

uint8_t reserved4[2]; /* 3A-3B */

drivers/scsi/qla4xxx/ql4_fw.h

752

uint8_t reserved5[4]; /* 40-43 */

drivers/scsi/qla4xxx/ql4_fw.h

754

uint8_t reserved6[2]; /* 46-47 */

drivers/scsi/qla4xxx/ql4_fw.h

757

uint8_t reserved7[4]; /* 4C-4F */

drivers/scsi/qla4xxx/ql4_fw.h

758

uint8_t ipv4_addr[4]; /* 50-53 */

drivers/scsi/qla4xxx/ql4_fw.h

760

uint8_t ipv4_addr_state; /* 56 */

drivers/scsi/qla4xxx/ql4_fw.h

761

uint8_t ipv4_cacheid; /* 57 */

drivers/scsi/qla4xxx/ql4_fw.h

762

uint8_t reserved8[8]; /* 58-5F */

drivers/scsi/qla4xxx/ql4_fw.h

763

uint8_t ipv4_subnet[4]; /* 60-63 */

drivers/scsi/qla4xxx/ql4_fw.h

764

uint8_t reserved9[12]; /* 64-6F */

drivers/scsi/qla4xxx/ql4_fw.h

765

uint8_t ipv4_gw_addr[4]; /* 70-73 */

drivers/scsi/qla4xxx/ql4_fw.h

766

uint8_t reserved10[84]; /* 74-C7 */

drivers/scsi/qla4xxx/ql4_fw.h

767

uint8_t abort_timer; /* C8 */

drivers/scsi/qla4xxx/ql4_fw.h

768

uint8_t ipv4_tcp_wsf; /* C9 */

drivers/scsi/qla4xxx/ql4_fw.h

769

uint8_t reserved11[10]; /* CA-D3 */

drivers/scsi/qla4xxx/ql4_fw.h

770

uint8_t ipv4_dhcp_vid_len; /* D4 */

drivers/scsi/qla4xxx/ql4_fw.h

771

uint8_t ipv4_dhcp_vid[11]; /* D5-DF */

drivers/scsi/qla4xxx/ql4_fw.h

772

uint8_t reserved12[20]; /* E0-F3 */

drivers/scsi/qla4xxx/ql4_fw.h

773

uint8_t ipv4_dhcp_alt_cid_len; /* F4 */

drivers/scsi/qla4xxx/ql4_fw.h

774

uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */

drivers/scsi/qla4xxx/ql4_fw.h

775

uint8_t iscsi_name[224]; /* 100-1DF */

drivers/scsi/qla4xxx/ql4_fw.h

776

uint8_t reserved13[32]; /* 1E0-1FF */

drivers/scsi/qla4xxx/ql4_fw.h

782

uint8_t ipv6_tcp_wsf; /* 20C */

drivers/scsi/qla4xxx/ql4_fw.h

784

uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */

drivers/scsi/qla4xxx/ql4_fw.h

786

uint8_t ipv6_lnk_lcl_addr_state; /* 222 */

drivers/scsi/qla4xxx/ql4_fw.h

787

uint8_t ipv6_addr0_state; /* 223 */

drivers/scsi/qla4xxx/ql4_fw.h

788

uint8_t ipv6_addr1_state; /* 224 */

drivers/scsi/qla4xxx/ql4_fw.h

789

uint8_t ipv6_dflt_rtr_state; /* 225 */

drivers/scsi/qla4xxx/ql4_fw.h

790

uint8_t ipv6_traffic_class; /* 226 */

drivers/scsi/qla4xxx/ql4_fw.h

791

uint8_t ipv6_hop_limit; /* 227 */

drivers/scsi/qla4xxx/ql4_fw.h

792

uint8_t ipv6_if_id[8]; /* 228-22F */

drivers/scsi/qla4xxx/ql4_fw.h

793

uint8_t ipv6_addr0[16]; /* 230-23F */

drivers/scsi/qla4xxx/ql4_fw.h

794

uint8_t ipv6_addr1[16]; /* 240-24F */

drivers/scsi/qla4xxx/ql4_fw.h

798

uint8_t ipv6_dup_addr_detect_count; /* 25C */

drivers/scsi/qla4xxx/ql4_fw.h

799

uint8_t ipv6_cache_id; /* 25D */

drivers/scsi/qla4xxx/ql4_fw.h

800

uint8_t reserved14[18]; /* 25E-26F */

drivers/scsi/qla4xxx/ql4_fw.h

802

uint8_t reserved15[140]; /* 274-2FF */

drivers/scsi/qla4xxx/ql4_fw.h

814

uint8_t flags;

drivers/scsi/qla4xxx/ql4_fw.h

815

uint8_t secret_len;

drivers/scsi/qla4xxx/ql4_fw.h

818

uint8_t secret[MAX_CHAP_SECRET_LEN];

drivers/scsi/qla4xxx/ql4_fw.h

820

uint8_t name[MAX_CHAP_NAME_LEN];

drivers/scsi/qla4xxx/ql4_fw.h

880

uint8_t isid[6]; /* 20-25 big-endian, must be converted

drivers/scsi/qla4xxx/ql4_fw.h

887

uint8_t ip_addr[0x10]; /* 30-3F */

drivers/scsi/qla4xxx/ql4_fw.h

888

uint8_t iscsi_alias[0x20]; /* 40-5F */

drivers/scsi/qla4xxx/ql4_fw.h

889

uint8_t tgt_addr[0x20]; /* 60-7F */

drivers/scsi/qla4xxx/ql4_fw.h

893

uint8_t ipv4_tos; /* 86 */

drivers/scsi/qla4xxx/ql4_fw.h

895

uint8_t res4[0x36]; /* 8A-BF */

drivers/scsi/qla4xxx/ql4_fw.h

896

uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a

drivers/scsi/qla4xxx/ql4_fw.h

900

uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */

drivers/scsi/qla4xxx/ql4_fw.h

901

uint8_t res5[0x10]; /* 1B0-1BF */

drivers/scsi/qla4xxx/ql4_fw.h

907

uint8_t tcp_xmt_wsf; /* 1C6 */

drivers/scsi/qla4xxx/ql4_fw.h

908

uint8_t tcp_rcv_wsf; /* 1C7 */

drivers/scsi/qla4xxx/ql4_fw.h

911

uint8_t res6[0x2b]; /* 1D0-1FB */

drivers/scsi/qla4xxx/ql4_fw.h

936

uint8_t address[6]; /* 00-05 */

drivers/scsi/qla4xxx/ql4_fw.h

937

uint8_t filler[2]; /* 06-07 */

drivers/scsi/qla4xxx/ql4_fw.h

944

uint8_t vendorId[128]; /* 28-A7 */

drivers/scsi/qla4xxx/ql4_fw.h

945

uint8_t productId[128]; /* A8-127 */

drivers/scsi/qla4xxx/ql4_fw.h

962

uint8_t acSerialNumber[16]; /* 150-15f */

drivers/scsi/qla4xxx/ql4_fw.h

972

uint8_t board_id_str[16]; /* 0-f Keep board ID string first */

drivers/scsi/qla4xxx/ql4_fw.h

978

uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */

drivers/scsi/qla4xxx/ql4_fw.h

982

uint8_t reserved[12]; /* 34-3f */

drivers/scsi/qla4xxx/ql4_fw.h

990

uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */

drivers/scsi/qla4xxx/ql4_fw.h

991

uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */

drivers/scsi/qla4xxx/ql4_fw.h

992

uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */

drivers/scsi/qla4xxx/ql4_fw.h

998

uint8_t reserved1[6]; /* 3A - 3F */

drivers/scsi/qla4xxx/ql4_glbl.h

104

uint8_t qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,

drivers/scsi/qla4xxx/ql4_glbl.h

187

uint32_t data_size, uint8_t *data);

drivers/scsi/qla4xxx/ql4_glbl.h

189

uint32_t payload_size, uint32_t pid, uint8_t *ipaddr);

drivers/scsi/qla4xxx/ql4_glbl.h

192

uint32_t data_size, uint8_t *data);

drivers/scsi/qla4xxx/ql4_glbl.h

20

void qla4xxx_process_aen(struct scsi_qla_host *ha, uint8_t process_aen);

drivers/scsi/qla4xxx/ql4_glbl.h

245

uint32_t flash_addr, uint8_t *p_data,

drivers/scsi/qla4xxx/ql4_glbl.h

250

uint8_t *p_data, int u32_word_count);

drivers/scsi/qla4xxx/ql4_glbl.h

276

uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state);

drivers/scsi/qla4xxx/ql4_glbl.h

49

uint8_t qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,

drivers/scsi/qla4xxx/ql4_glbl.h

81

int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,

drivers/scsi/qla4xxx/ql4_glbl.h

82

uint8_t outCount, uint32_t *mbx_cmd, uint32_t *mbx_sts);

drivers/scsi/qla4xxx/ql4_init.c

200

static uint8_t

drivers/scsi/qla4xxx/ql4_init.c

203

uint8_t ipv4_wait = 0;

drivers/scsi/qla4xxx/ql4_init.c

204

uint8_t ipv6_wait = 0;

drivers/scsi/qla4xxx/ql4_iocb.c

129

cont_entry->hdr.systemDefined = (uint8_t) cpu_to_le16(ha->request_in);

drivers/scsi/qla4xxx/ql4_iocb.c

412

memcpy((uint8_t *)task_data->req_buffer +

drivers/scsi/qla4xxx/ql4_iocb.c

507

uint32_t payload_size, uint32_t pid, uint8_t *ipaddr)

drivers/scsi/qla4xxx/ql4_iocb.c

89

uint8_t status = QLA_SUCCESS;

drivers/scsi/qla4xxx/ql4_isr.c

1101

uint8_t reqs_count)

drivers/scsi/qla4xxx/ql4_isr.c

1126

uint8_t reqs_count = 0;

drivers/scsi/qla4xxx/ql4_isr.c

117

uint8_t scsi_status;

drivers/scsi/qla4xxx/ql4_isr.c

1223

uint8_t reqs_count = 0;

drivers/scsi/qla4xxx/ql4_isr.c

1396

uint8_t reqs_count = 0;

drivers/scsi/qla4xxx/ql4_isr.c

1473

void qla4xxx_process_aen(struct scsi_qla_host * ha, uint8_t process_aen)

drivers/scsi/qla4xxx/ql4_isr.c

454

(uint8_t *) mbox_sts_entry->out_mbox);

drivers/scsi/qla4xxx/ql4_isr.c

610

uint8_t ipaddr_state;

drivers/scsi/qla4xxx/ql4_isr.c

611

uint8_t ip_idx;

drivers/scsi/qla4xxx/ql4_isr.c

614

ipaddr_state = qla4xxx_set_ipaddr_state((uint8_t)ipaddr_fw_state);

drivers/scsi/qla4xxx/ql4_isr.c

740

(uint8_t *) mbox_sts);

drivers/scsi/qla4xxx/ql4_isr.c

758

(uint8_t *) mbox_sts);

drivers/scsi/qla4xxx/ql4_mbx.c

1078

uint8_t i;

drivers/scsi/qla4xxx/ql4_mbx.c

1131

qla4xxx_dump_buffer((uint8_t *)event_log+

drivers/scsi/qla4xxx/ql4_mbx.c

1140

qla4xxx_dump_buffer((uint8_t *)event_log+

drivers/scsi/qla4xxx/ql4_mbx.c

1145

qla4xxx_dump_buffer((uint8_t *)event_log+

drivers/scsi/qla4xxx/ql4_mbx.c

1661

chap_table->secret_len = (uint8_t)secret_len;

drivers/scsi/qla4xxx/ql4_mbx.c

370

static uint8_t

drivers/scsi/qla4xxx/ql4_mbx.c

397

uint8_t

drivers/scsi/qla4xxx/ql4_mbx.c

419

uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state)

drivers/scsi/qla4xxx/ql4_mbx.c

421

uint8_t ipaddr_state;

drivers/scsi/qla4xxx/ql4_mbx.c

582

uint8_t

drivers/scsi/qla4xxx/ql4_mbx.c

82

int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,

drivers/scsi/qla4xxx/ql4_mbx.c

83

uint8_t outCount, uint32_t *mbx_cmd,

drivers/scsi/qla4xxx/ql4_mbx.c

87

uint8_t i;

drivers/scsi/qla4xxx/ql4_nvram.h

73

uint8_t bootID0:7;

drivers/scsi/qla4xxx/ql4_nvram.h

74

uint8_t bootID0Valid:1;

drivers/scsi/qla4xxx/ql4_nvram.h

75

uint8_t bootLUN0[8];

drivers/scsi/qla4xxx/ql4_nvram.h

76

uint8_t bootID1:7;

drivers/scsi/qla4xxx/ql4_nvram.h

77

uint8_t bootID1Valid:1;

drivers/scsi/qla4xxx/ql4_nvram.h

78

uint8_t bootLUN1[8];

drivers/scsi/qla4xxx/ql4_nvram.h

80

uint8_t Reserved1[10];

drivers/scsi/qla4xxx/ql4_nx.c

1422

*(uint8_t *)data = val;

drivers/scsi/qla4xxx/ql4_nx.c

1476

tmpw = *((uint8_t *)data);

drivers/scsi/qla4xxx/ql4_nx.c

2017

uint8_t *data_ptr = (uint8_t *)*d_ptr;

drivers/scsi/qla4xxx/ql4_nx.c

2627

uint8_t stride, stride2;

drivers/scsi/qla4xxx/ql4_nx.c

2722

uint8_t stride1, stride2;

drivers/scsi/qla4xxx/ql4_nx.c

3003

data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +

drivers/scsi/qla4xxx/ql4_nx.c

3024

(((uint8_t *)ha->fw_dump_tmplt_hdr) +

drivers/scsi/qla4xxx/ql4_nx.c

3176

data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;

drivers/scsi/qla4xxx/ql4_nx.c

3180

(((uint8_t *)entry_hdr) +

drivers/scsi/qla4xxx/ql4_nx.c

3667

static uint8_t *

drivers/scsi/qla4xxx/ql4_nx.c

3668

qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,

drivers/scsi/qla4xxx/ql4_nx.c

3709

qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,

drivers/scsi/qla4xxx/ql4_nx.c

3713

(uint8_t *)ha->request_ring,

drivers/scsi/qla4xxx/ql4_nx.c

3821

qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,

drivers/scsi/qla4xxx/ql4_nx.c

3878

qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,

drivers/scsi/qla4xxx/ql4_nx.h

877

uint8_t entry_capture_mask;

drivers/scsi/qla4xxx/ql4_nx.h

878

uint8_t entry_code;

drivers/scsi/qla4xxx/ql4_nx.h

879

uint8_t driver_code;

drivers/scsi/qla4xxx/ql4_nx.h

880

uint8_t driver_flags;

drivers/scsi/qla4xxx/ql4_nx.h

889

uint8_t addr_stride;

drivers/scsi/qla4xxx/ql4_nx.h

890

uint8_t state_index_a;

drivers/scsi/qla4xxx/ql4_nx.h

897

uint8_t opcode;

drivers/scsi/qla4xxx/ql4_nx.h

898

uint8_t state_index_v;

drivers/scsi/qla4xxx/ql4_nx.h

899

uint8_t shl;

drivers/scsi/qla4xxx/ql4_nx.h

900

uint8_t shr;

drivers/scsi/qla4xxx/ql4_nx.h

920

uint8_t poll_mask;

drivers/scsi/qla4xxx/ql4_nx.h

921

uint8_t poll_wait;

drivers/scsi/qla4xxx/ql4_nx.h

925

uint8_t read_addr_stride;

drivers/scsi/qla4xxx/ql4_nx.h

926

uint8_t read_addr_cnt;

drivers/scsi/qla4xxx/ql4_nx.h

987

uint8_t read_addr_stride;

drivers/scsi/qla4xxx/ql4_nx.h

988

uint8_t read_addr_cnt;

drivers/scsi/qla4xxx/ql4_os.c

139

static int qla4xxx_alloc_pdu(struct iscsi_task *, uint8_t);

drivers/scsi/qla4xxx/ql4_os.c

2989

uint8_t dst_ipaddr[IPv6_ADDR_LEN];

drivers/scsi/qla4xxx/ql4_os.c

326

uint8_t ipaddr[IPv6_ADDR_LEN];

drivers/scsi/qla4xxx/ql4_os.c

3359

uint8_t *data;

drivers/scsi/qla4xxx/ql4_os.c

3396

static int qla4xxx_alloc_pdu(struct iscsi_task *task, uint8_t opcode)

drivers/scsi/qla4xxx/ql4_os.c

3711

fw_ddb_entry->tcp_xmt_wsf = (uint8_t) cpu_to_le32(conn->tcp_xmit_wsf);

drivers/scsi/qla4xxx/ql4_os.c

3712

fw_ddb_entry->tcp_rcv_wsf = (uint8_t) cpu_to_le32(conn->tcp_recv_wsf);

drivers/scsi/qla4xxx/ql4_os.c

4860

uint8_t reset_chip = 0;

drivers/scsi/qla4xxx/ql4_os.c

5232

uint32_t data_size, uint8_t *data)

drivers/scsi/qla4xxx/ql4_os.c

5251

uint32_t data_size, uint8_t *data)

drivers/scsi/qla4xxx/ql4_os.c

5411

uint8_t wait_time = RESET_INTR_TOV;

drivers/scsi/qla4xxx/ql4_os.c

5566

((uint8_t *)ha->nx_pcibase + 0xbc000 +

drivers/scsi/qla4xxx/ql4_os.c

5572

((uint8_t *)ha->nx_pcibase);

drivers/scsi/qla4xxx/ql4_os.c

5923

uint8_t val;

drivers/scsi/qla4xxx/ql4_os.c

5924

uint8_t *buf = NULL;

drivers/scsi/qla4xxx/ql4_os.c

5925

size_t size = 13 * sizeof(uint8_t);

drivers/scsi/qla4xxx/ql4_os.c

5988

13 * sizeof(uint8_t)) != QLA_SUCCESS) {

drivers/scsi/qla4xxx/ql4_os.c

6304

uint8_t *flash_isid)

drivers/scsi/qla4xxx/ql4_os.c

6330

uint8_t is_isid_compare)

drivers/scsi/qla4xxx/ql4_os.c

636

uint8_t *chap_flash_data = NULL;

drivers/scsi/qla4xxx/ql4_os.c

6422

static int qla4xxx_check_existing_isid(struct list_head *list_nt, uint8_t *isid)

drivers/scsi/qla4xxx/ql4_os.c

6452

uint8_t base_value, i;

drivers/scsi/qla4xxx/ql4_os.c

8298

*(uint8_t *)fnode_param->value;

drivers/scsi/qla4xxx/ql4_os.c

8302

*(uint8_t *)fnode_param->value;

drivers/scsi/qla4xxx/ql4_os.c

8639

uint8_t init_retry_count = 0;

drivers/scsi/scsi_transport_iscsi.c

2712

uint8_t *data)

drivers/scsi/scsi_transport_iscsi.c

2743

uint8_t *data)

drivers/scsi/xen-scsifront.c

217

ring_req->sc_data_direction = (uint8_t)sc->sc_data_direction;

drivers/scsi/xen-scsifront.c

305

uint8_t sense_len;

drivers/scsi/xen-scsifront.c

322

sense_len = min_t(uint8_t, VSCSIIF_SENSE_BUFFERSIZE,

drivers/scsi/xen-scsifront.c

579

shadow->nr_segments = (uint8_t)ref_cnt;

drivers/scsi/xen-scsifront.c

662

static int scsifront_action_handler(struct scsi_cmnd *sc, uint8_t act)

drivers/scsi/xen-scsifront.c

79

uint8_t nr_segments;

drivers/slimbus/qcom-ngd-ctrl.c

204

uint8_t mode_valid;

drivers/slimbus/qcom-ngd-ctrl.c

214

uint8_t resp_type_valid;

drivers/slimbus/qcom-ngd-ctrl.c

236

.elem_size = sizeof(uint8_t),

drivers/slimbus/qcom-ngd-ctrl.c

300

.elem_size = sizeof(uint8_t),

drivers/soc/aspeed/aspeed-uart-routing.c

41

uint8_t reg;

drivers/soc/aspeed/aspeed-uart-routing.c

42

uint8_t mask;

drivers/soc/aspeed/aspeed-uart-routing.c

43

uint8_t shift;

drivers/soc/qcom/apr.c

44

uint8_t buf[] __counted_by(len);

drivers/soc/qcom/ocmem.c

50

uint8_t num_regions;

drivers/spi/spi-axi-spi-engine.c

135

const uint8_t *tx_buf;

drivers/spi/spi-axi-spi-engine.c

141

uint8_t *rx_buf;

drivers/spi/spi-st-ssc4.c

108

*spi_st->rx_ptr++ = (uint8_t)word;

drivers/staging/fbtft/fb_ssd1325.c

61

static uint8_t rgb565_to_g16(u16 pixel)

drivers/staging/fbtft/fb_ssd1325.c

70

return (uint8_t)pixel / 16;

drivers/staging/media/atomisp/pci/atomisp_cmd.c

348

void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id)

drivers/staging/media/atomisp/pci/atomisp_cmd.c

359

uint8_t exp_id)

drivers/staging/media/atomisp/pci/atomisp_cmd.h

263

void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id);

drivers/staging/media/atomisp/pci/atomisp_compat_css20.c

56

static void atomisp_css2_hw_store_8(hrt_address addr, uint8_t data)

drivers/staging/media/atomisp/pci/atomisp_compat_css20.c

86

static uint8_t atomisp_css2_hw_load_8(hrt_address addr)

drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf.h

137

static inline uint8_t ia_css_circbuf_get_pos_at_offset(

drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_comm.h

39

(4 * sizeof(uint8_t))

drivers/staging/media/atomisp/pci/base/circbuf/interface/ia_css_circbuf_desc.h

76

static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset(

drivers/staging/media/atomisp/pci/base/circbuf/src/circbuf.c

211

if (((uint8_t)(cb->desc->size + (uint8_t)sz_delta) > cb->desc->size) &&

drivers/staging/media/atomisp/pci/base/circbuf/src/circbuf.c

212

((uint8_t)sz_delta == sz_delta))

drivers/staging/media/atomisp/pci/base/circbuf/src/circbuf.c

213

cb->desc->size += (uint8_t)sz_delta;

drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c

103

val = (((uint8_t)pred) << 3) | comp;

drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_local.h

31

(index) * sizeof(uint8_t))

drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_local.h

46

(index) * sizeof(uint8_t), value)

drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_private.h

128

STORAGE_CLASS_SP_C uint8_t sp_dmem_load_uint8(

drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_private.h

95

const uint8_t data)

drivers/staging/media/atomisp/pci/hive_isp_css_include/device_access/device_access.h

109

const uint8_t data);

drivers/staging/media/atomisp/pci/hive_isp_css_include/device_access/device_access.h

70

uint8_t ia_css_device_load_uint8(

drivers/staging/media/atomisp/pci/hive_isp_css_include/host/sp_public.h

130

const uint8_t data);

drivers/staging/media/atomisp/pci/hive_isp_css_include/host/sp_public.h

169

STORAGE_CLASS_SP_H uint8_t sp_dmem_load_uint8(

drivers/staging/media/atomisp/pci/ia_css_acc_types.h

437

#define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f) + (f->header.n)))

drivers/staging/media/atomisp/pci/ia_css_acc_types.h

442

#define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \

drivers/staging/media/atomisp/pci/ia_css_acc_types.h

446

#define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\

drivers/staging/media/atomisp/pci/ia_css_device_access.c

23

uint8_t

drivers/staging/media/atomisp/pci/ia_css_device_access.c

51

ia_css_device_store_uint8(const hrt_address addr, const uint8_t data)

drivers/staging/media/atomisp/pci/ia_css_device_access.h

21

uint8_t

drivers/staging/media/atomisp/pci/ia_css_device_access.h

34

ia_css_device_store_uint8(const hrt_address addr, const uint8_t data);

drivers/staging/media/atomisp/pci/ia_css_env.h

43

void (*store_8)(hrt_address addr, uint8_t data);

drivers/staging/media/atomisp/pci/ia_css_env.h

52

uint8_t (*load_8)(hrt_address addr);

drivers/staging/media/atomisp/pci/isp/kernels/raw/raw_1.0/ia_css_raw.host.c

102

u8 enable_left_padding = (uint8_t)((binary->left_padding) ? 1 : 0);

drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq.h

107

uint8_t evt_payload_2

drivers/staging/media/atomisp/pci/runtime/bufq/interface/ia_css_bufq.h

130

uint8_t evt_id);

drivers/staging/media/atomisp/pci/runtime/bufq/src/bufq.c

377

uint8_t evt_payload_2)

drivers/staging/media/atomisp/pci/runtime/bufq/src/bufq.c

439

int ia_css_bufq_enqueue_isys_event(uint8_t evt_id)

drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c

1712

header_arr = (uint8_t *)&header;

drivers/staging/media/atomisp/pci/runtime/event/interface/ia_css_event.h

20

uint8_t *payload);

drivers/staging/media/atomisp/pci/runtime/event/src/event.c

65

uint8_t *payload)

drivers/staging/media/atomisp/pci/runtime/eventq/interface/ia_css_eventq.h

23

uint8_t *payload);

drivers/staging/media/atomisp/pci/runtime/eventq/interface/ia_css_eventq.h

44

uint8_t evt_payload_2);

drivers/staging/media/atomisp/pci/runtime/eventq/src/eventq.c

16

uint8_t *payload)

drivers/staging/media/atomisp/pci/runtime/eventq/src/eventq.c

39

uint8_t evt_payload_2)

drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c

426

config->elems = (uint8_t)elems_b;

drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c

713

to->format = (uint8_t)from->format;

drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c

714

to->raw_bit_depth = (uint8_t)from->raw_bit_depth;

drivers/staging/media/atomisp/pci/runtime/ifmtr/src/ifmtr.c

120

if_config_index = (uint8_t)(port - MIPI_PORT0_ID);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

144

(uint8_t)thread_id,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

213

(uint8_t)thread_id,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

678

pipeline->pipe_num = (uint8_t)pipe_num;

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

724

(uint8_t)SH_CSS_PORT_INPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

725

(uint8_t)(continuous ? SH_CSS_COPYSINK_TYPE : SH_CSS_HOST_TYPE), 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

727

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

728

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

732

(uint8_t)SH_CSS_PORT_INPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

733

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

736

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

737

(uint8_t)SH_CSS_COPYSINK_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

739

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

740

(uint8_t)SH_CSS_TAGGERSINK_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

743

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

744

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

749

(uint8_t)SH_CSS_PORT_INPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

750

(uint8_t)(continuous ? SH_CSS_TAGGERSINK_TYPE : SH_CSS_HOST_TYPE),

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

753

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

754

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

758

(uint8_t)SH_CSS_PORT_INPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

759

(uint8_t)(SH_CSS_HOST_TYPE), 1);

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

761

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/runtime/pipeline/src/pipeline.c

762

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/runtime/queue/src/queue.c

319

error = ia_css_queue_item_load(qhandle, (uint8_t)offset, &cb_elem);

drivers/staging/media/atomisp/pci/sh_css.c

1171

(uint8_t)ia_css_pipe_get_pipe_num(me),

drivers/staging/media/atomisp/pci/sh_css.c

1829

const u8 INVALID_PIPE_NUM = (uint8_t)~(0);

drivers/staging/media/atomisp/pci/sh_css.c

3376

(uint8_t)ia_css_pipe_get_pipe_num(copy_pipe),

drivers/staging/media/atomisp/pci/sh_css.c

3397

(uint8_t)ia_css_pipe_get_pipe_num(capture_pipe),

drivers/staging/media/atomisp/pci/sh_css.c

3608

(uint8_t)thread_id,

drivers/staging/media/atomisp/pci/sh_css.c

4147

(uint8_t)thread_id, 0, 0);

drivers/staging/media/atomisp/pci/sh_css.c

4159

(uint8_t)thread_id, 0, 0);

drivers/staging/media/atomisp/pci/sh_css.c

4181

(uint8_t)thread_id, 0, 0);

drivers/staging/media/atomisp/pci/sh_css.c

4200

(uint8_t)thread_id, 0, 0);

drivers/staging/media/atomisp/pci/sh_css.c

4220

sh_css_continuous_is_enabled(uint8_t pipe_num)

drivers/staging/media/atomisp/pci/sh_css.c

4808

(uint8_t)ia_css_pipe_get_pipe_num(copy_pipe),

drivers/staging/media/atomisp/pci/sh_css.c

4829

(uint8_t)ia_css_pipe_get_pipe_num(capture_pipe),

drivers/staging/media/atomisp/pci/sh_css_internal.h

946

sh_css_continuous_is_enabled(uint8_t pipe_num);

drivers/staging/media/atomisp/pci/sh_css_mipi.c

540

(uint8_t)port,

drivers/staging/media/atomisp/pci/sh_css_mipi.c

541

(uint8_t)my_css.num_mipi_frames[port],

drivers/staging/media/atomisp/pci/sh_css_params.c

3219

(uint8_t)thread_id,

drivers/staging/media/atomisp/pci/sh_css_params.c

3220

(uint8_t)queue_id,

drivers/staging/media/atomisp/pci/sh_css_sp.c

1196

if_config_index = (uint8_t)(port_id - MIPI_PORT0_ID);

drivers/staging/media/atomisp/pci/sh_css_sp.c

206

(uint8_t)SH_CSS_PORT_INPUT,

drivers/staging/media/atomisp/pci/sh_css_sp.c

207

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/sh_css_sp.c

209

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/sh_css_sp.c

210

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/sh_css_sp.c

216

sh_css_sp_group.config.input_formatter.isp_2ppc = (uint8_t)two_ppc;

drivers/staging/media/atomisp/pci/sh_css_sp.c

281

(uint8_t)SH_CSS_PORT_INPUT,

drivers/staging/media/atomisp/pci/sh_css_sp.c

282

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/sh_css_sp.c

284

(uint8_t)SH_CSS_PORT_OUTPUT,

drivers/staging/media/atomisp/pci/sh_css_sp.c

285

(uint8_t)SH_CSS_HOST_TYPE, 1);

drivers/staging/media/atomisp/pci/sh_css_sp.c

291

sh_css_sp_group.config.input_formatter.isp_2ppc = (uint8_t)two_ppc;

drivers/staging/media/atomisp/pci/sh_css_sp.c

297

sh_css_sp_stage.if_config_index = (uint8_t)if_config_index;

drivers/staging/media/atomisp/pci/sh_css_sp.c

348

sh_css_sp_stage.if_config_index = (uint8_t)if_config_index;

drivers/staging/media/atomisp/pci/sh_css_sp.c

618

const uint8_t if_config_index

drivers/staging/media/atomisp/pci/sh_css_sp.c

716

uint8_t if_config_index)

drivers/staging/media/atomisp/pci/sh_css_sp.c

721

sh_css_sp_group.config.no_isp_sync = (uint8_t)no_isp_sync;

drivers/staging/media/atomisp/pci/sh_css_sp.c

882

bool continuous = sh_css_continuous_is_enabled((uint8_t)pipe_num);

drivers/staging/media/atomisp/pci/sh_css_sp.c

901

sh_css_sp_stage.program_input_circuit = (uint8_t)program_input_circuit;

drivers/staging/media/atomisp/pci/sh_css_sp.c

922

sh_css_sp_stage.num = (uint8_t)stage;

drivers/staging/media/atomisp/pci/sh_css_sp.c

923

sh_css_sp_stage.isp_online = (uint8_t)binary->online;

drivers/staging/media/atomisp/pci/sh_css_sp.c

924

sh_css_sp_stage.isp_copy_vf = (uint8_t)args->copy_vf;

drivers/staging/media/atomisp/pci/sh_css_sp.c

925

sh_css_sp_stage.isp_copy_output = (uint8_t)args->copy_output;

drivers/staging/media/atomisp/pci/sh_css_sp.c

94

sh_css_sp_stage.num_stripes = (uint8_t)

drivers/staging/media/atomisp/pci/sh_css_sp.c

945

sh_css_sp_stage.isp_pipe_version = (uint8_t)info->pipeline.isp_pipe_version;

drivers/staging/media/atomisp/pci/sh_css_sp.c

946

sh_css_sp_stage.isp_deci_log_factor = (uint8_t)binary->deci_factor_log2;

drivers/staging/media/atomisp/pci/sh_css_sp.c

947

sh_css_sp_stage.isp_vf_downscale_bits = (uint8_t)binary->vf_downscale_log2;

drivers/staging/media/atomisp/pci/sh_css_sp.c

949

sh_css_sp_stage.if_config_index = (uint8_t)if_config_index;

drivers/staging/media/atomisp/pci/sh_css_sp.c

951

sh_css_sp_stage.sp_enable_xnr = (uint8_t)xnr;

drivers/staging/media/atomisp/pci/sh_css_sp.h

145

const uint8_t if_config_index);

drivers/staging/media/meson/vdec/esparser.c

93

dp = (uint8_t *)vb2_plane_vaddr(buf, 0);

drivers/staging/media/sunxi/cedrus/cedrus_vp8.c

436

static uint8_t read_bits(struct cedrus_dev *dev, unsigned int bits_count,

drivers/staging/octeon/octeon-stubs.h

128

uint8_t unused;

drivers/staging/octeon/octeon-stubs.h

194

uint8_t packet_data[96];

drivers/target/target_core_spc.c

720

uint8_t page;

drivers/target/target_core_spc.c

979

uint8_t page;

drivers/target/target_core_spc.c

980

uint8_t subpage;

drivers/target/target_core_user.c

202

uint8_t tmr_type;

drivers/tty/hvc/hvsi.c

145

static inline int len_packet(const uint8_t *packet)

drivers/tty/hvc/hvsi.c

150

static inline int is_header(const uint8_t *packet)

drivers/tty/hvc/hvsi.c

156

static inline int got_packet(const struct hvsi_struct *hp, uint8_t *packet)

drivers/tty/hvc/hvsi.c

168

static void compact_inbuf(struct hvsi_struct *hp, uint8_t *read_to)

drivers/tty/hvc/hvsi.c

188

static void dump_hex(const uint8_t *data, int len)

drivers/tty/hvc/hvsi.c

206

static void dump_packet(uint8_t *packet)

drivers/tty/hvc/hvsi.c

225

static void hvsi_recv_control(struct hvsi_struct *hp, uint8_t *packet,

drivers/tty/hvc/hvsi.c

254

static void hvsi_recv_response(struct hvsi_struct *hp, uint8_t *packet)

drivers/tty/hvc/hvsi.c

293

dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);

drivers/tty/hvc/hvsi.c

305

static void hvsi_recv_query(struct hvsi_struct *hp, uint8_t *packet)

drivers/tty/hvc/hvsi.c

350

static bool hvsi_recv_data(struct hvsi_struct *hp, const uint8_t *packet)

drivers/tty/hvc/hvsi.c

353

const uint8_t *data = packet + sizeof(struct hvsi_header);

drivers/tty/hvc/hvsi.c

391

uint8_t *packet = hp->inbuf;

drivers/tty/hvc/hvsi.c

551

dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);

drivers/tty/hvc/hvsi.c

598

dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);

drivers/tty/hvc/hvsi.c

611

uint8_t buf[HVSI_MAX_READ] __ALIGNED__;

drivers/tty/hvc/hvsi.c

66

uint8_t throttle_buf[128];

drivers/tty/hvc/hvsi.c

67

uint8_t outbuf[N_OUTBUF]; /* to implement write_room and chars_in_buffer */

drivers/tty/hvc/hvsi.c

69

uint8_t inbuf[HVSI_MAX_PACKET + HVSI_MAX_READ];

drivers/tty/hvc/hvsi.c

694

dbg_dump_hex((uint8_t*)&packet, packet.hdr.len);

drivers/tty/hvc/hvsi.c

70

uint8_t *inbuf_end;

drivers/tty/hvc/hvsi.c

77

uint8_t state; /* HVSI protocol state */

drivers/tty/hvc/hvsi.c

78

uint8_t flags;

drivers/tty/hvc/hvsi.c

80

uint8_t sysrq;

drivers/tty/serial/8250/8250_fintek.c

200

uint8_t config = 0;

drivers/tty/serial/8250/8250_ingenic.c

44

static uint8_t early_in(struct uart_port *port, int offset)

drivers/tty/serial/8250/8250_ingenic.c

49

static void early_out(struct uart_port *port, int offset, uint8_t value)

drivers/ufs/core/ufs_bsg.c

139

uint8_t *buff = NULL;

drivers/ufs/core/ufs_bsg.c

30

uint8_t **desc_buff, int *desc_len,

drivers/ufs/host/ufs-qcom.c

147

static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 };

drivers/usb/dwc3/dwc3-octeon.c

250

static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 };

drivers/usb/gadget/function/f_midi.c

234

static const uint8_t f_midi_cin_length[] = {

drivers/usb/gadget/function/f_midi.c

242

uint8_t *data, int length)

drivers/usb/gadget/function/f_midi.c

449

struct gmidi_in_port *port, uint8_t b)

drivers/usb/gadget/function/f_midi.c

451

uint8_t p[4] = { port->cable << 4, 0, 0, 0 };

drivers/usb/gadget/function/f_midi.c

452

uint8_t next_state = STATE_INITIAL;

drivers/usb/gadget/function/f_midi.c

641

uint8_t b;

drivers/usb/gadget/function/f_midi.c

75

uint8_t cable;

drivers/usb/gadget/function/f_midi.c

76

uint8_t state;

drivers/usb/gadget/function/f_midi.c

77

uint8_t data[2];

drivers/usb/typec/ucsi/ucsi_ccg.c

1080

memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -

drivers/usb/typec/ucsi/ucsi_ccg.c

1190

memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -

drivers/usb/typec/ucsi/ucsi_ccg.c

1199

memcpy((uint8_t *)&fw_cfg_sig,

drivers/vdpa/octeon_ep/octep_vdpa.h

95

void octep_hw_set_status(struct octep_hw *dev, uint8_t status);

drivers/vfio/pci/vfio_pci_intrs.c

593

uint8_t unmask = *(uint8_t *)data;

drivers/vfio/pci/vfio_pci_intrs.c

624

uint8_t mask = *(uint8_t *)data;

drivers/vfio/pci/vfio_pci_intrs.c

674

uint8_t trigger = *(uint8_t *)data;

drivers/vfio/pci/vfio_pci_intrs.c

726

uint8_t *bools = data;

drivers/vfio/pci/vfio_pci_intrs.c

756

uint8_t trigger;

drivers/vfio/pci/vfio_pci_intrs.c

761

trigger = *(uint8_t *)data;

drivers/vfio/platform/vfio_platform_irq.c

130

uint8_t unmask = *(uint8_t *)data;

drivers/vfio/platform/vfio_platform_irq.c

244

uint8_t trigger = *(uint8_t *)data;

drivers/vfio/platform/vfio_platform_irq.c

69

uint8_t mask = *(uint8_t *)data;

drivers/vfio/vfio_main.c

1623

size = sizeof(uint8_t);

drivers/video/backlight/adp5520_bl.c

138

uint8_t reg_val;

drivers/video/backlight/adp5520_bl.c

74

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

118

static int adp8860_read(struct i2c_client *client, int reg, uint8_t *val)

drivers/video/backlight/adp8860_bl.c

128

*val = (uint8_t)ret;

drivers/video/backlight/adp8860_bl.c

137

static int adp8860_set_bits(struct i2c_client *client, int reg, uint8_t bit_mask)

drivers/video/backlight/adp8860_bl.c

140

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

156

static int adp8860_clr_bits(struct i2c_client *client, int reg, uint8_t bit_mask)

drivers/video/backlight/adp8860_bl.c

159

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

424

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

554

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

581

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

600

uint8_t reg_val;

drivers/video/backlight/adp8860_bl.c

658

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

127

static int adp8870_read(struct i2c_client *client, int reg, uint8_t *val)

drivers/video/backlight/adp8870_bl.c

152

static int adp8870_set_bits(struct i2c_client *client, int reg, uint8_t bit_mask)

drivers/video/backlight/adp8870_bl.c

155

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

171

static int adp8870_clr_bits(struct i2c_client *client, int reg, uint8_t bit_mask)

drivers/video/backlight/adp8870_bl.c

174

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

545

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

736

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

765

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

784

uint8_t reg_val;

drivers/video/backlight/adp8870_bl.c

846

uint8_t reg_val;

drivers/video/backlight/corgi_lcd.c

110

static void lcdtg_ssp_i2c_send(struct corgi_lcd *lcd, uint8_t data)

drivers/video/backlight/corgi_lcd.c

116

static void lcdtg_i2c_send_bit(struct corgi_lcd *lcd, uint8_t data)

drivers/video/backlight/corgi_lcd.c

123

static void lcdtg_i2c_send_start(struct corgi_lcd *lcd, uint8_t base)

drivers/video/backlight/corgi_lcd.c

130

static void lcdtg_i2c_send_stop(struct corgi_lcd *lcd, uint8_t base)

drivers/video/backlight/corgi_lcd.c

138

uint8_t base, uint8_t data)

drivers/video/backlight/corgi_lcd.c

151

static void lcdtg_i2c_wait_ack(struct corgi_lcd *lcd, uint8_t base)

drivers/video/backlight/corgi_lcd.c

157

uint8_t base_data, uint8_t data)

drivers/video/backlight/corgi_lcd.c

170

static int corgi_ssp_lcdtg_send(struct corgi_lcd *lcd, int adrs, uint8_t data)

drivers/video/backlight/corgi_lcd.c

99

static int corgi_ssp_lcdtg_send(struct corgi_lcd *lcd, int reg, uint8_t val);

drivers/video/backlight/da903x_bl.c

43

uint8_t val;

drivers/video/backlight/tdo24m.c

30

uint8_t *buf;

drivers/video/fbdev/aty/radeon_backlight.c

22

uint8_t negative;

drivers/video/fbdev/fsl-diu-fb.c

385

uint8_t edid_data[EDID_LENGTH];

drivers/video/fbdev/udlfb.c

433

uint8_t **command_buffer_ptr,

drivers/video/fbdev/udlfb.c

434

const uint8_t *const cmd_buffer_end,

drivers/video/fbdev/udlfb.c

440

uint8_t *cmd = *command_buffer_ptr;

drivers/video/fbdev/udlfb.c

444

uint8_t *raw_pixels_count_byte = NULL;

drivers/video/fbdev/udlfb.c

445

uint8_t *cmd_pixels_count_byte = NULL;

drivers/video/fbdev/udlfb.c

528

cmd = (uint8_t *) cmd_buffer_end;

drivers/virtio/virtio_mem.c

192

uint8_t *mb_states;

drivers/virtio/virtio_mem.c

219

uint8_t *bb_states;

drivers/virtio/virtio_mem.c

406

uint8_t *new_array;

drivers/virtio/virtio_mem.c

441

unsigned long mb_id, uint8_t state)

drivers/virtio/virtio_mem.c

444

uint8_t old_state;

drivers/virtio/virtio_mem.c

457

static uint8_t virtio_mem_sbm_get_mb_state(struct virtio_mem *vm,

drivers/virtio/virtio_mem.c

472

uint8_t *new_array;

drivers/w1/slaves/w1_therm.c

185

uint8_t rom[9];

drivers/xen/gntalloc.c

179

uint8_t *tmp = kmap_local_page(gref->page);

drivers/xen/gntdev.c

451

uint8_t *tmp = pfn_to_kaddr(page_to_pfn(map->pages[pgno]));

drivers/xen/pvcalls-front.c

170

uint8_t *src, *dst;

drivers/xen/pvcalls-front.c

203

dst = (uint8_t *)&bedata->rsp[req_id] +

drivers/xen/pvcalls-front.c

205

src = (uint8_t *)rsp + sizeof(rsp->req_id);

drivers/xen/pvcalls-front.c

80

uint8_t status __attribute__((aligned(8)));

drivers/xen/pvcalls-front.c

91

uint8_t flags __attribute__((aligned(8)));

drivers/xen/xen-scsiback.c

117

uint8_t cmnd[VSCSIIF_MAX_COMMAND_SIZE];

drivers/xen/xen-scsiback.c

118

uint8_t cmd_len;

drivers/xen/xen-scsiback.c

120

uint8_t sc_data_direction;

drivers/xen/xen-scsiback.c

130

uint8_t sense_buffer[VSCSIIF_SENSE_BUFFERSIZE];

fs/9p/vfs_dir.c

39

uint8_t buf[];

fs/9p/vfs_file.c

127

uint8_t status = P9_LOCK_ERROR;

fs/dlm/ast.c

22

uint32_t flags, uint8_t sb_flags, int sb_status,

fs/dlm/dlm_internal.h

232

uint8_t sb_flags; /* copy to lksb flags */

fs/dlm/dlm_internal.h

284

uint8_t lkb_last_cb_flags;

fs/dlm/dlm_internal.h

416

uint8_t h_cmd; /* DLM_MSG, DLM_RCOM */

fs/dlm/dlm_internal.h

417

uint8_t h_pad;

fs/dlm/dlm_internal.h

498

uint8_t o_nextcmd;

fs/dlm/dlm_internal.h

499

uint8_t o_pad;

fs/fuse/fuse_i.h

332

uint8_t in_numargs;

fs/fuse/fuse_i.h

333

uint8_t out_numargs;

fs/fuse/fuse_i.h

334

uint8_t ext_idx;

fs/jffs2/dir.c

256

uint8_t type;

fs/jffs2/dir.c

782

uint8_t type;

fs/jffs2/jffs2_fs_i.h

52

uint8_t usercompr;

fs/jffs2/jffs2_fs_sb.h

81

uint8_t resv_blocks_write; /* ... allow a normal filesystem write */

fs/jffs2/jffs2_fs_sb.h

82

uint8_t resv_blocks_deletion; /* ... allow a normal filesystem deletion */

fs/jffs2/jffs2_fs_sb.h

83

uint8_t resv_blocks_gctrigger; /* ... wake up the GC thread */

fs/jffs2/jffs2_fs_sb.h

84

uint8_t resv_blocks_gcbad; /* ... pick a block from the bad_list to GC */

fs/jffs2/jffs2_fs_sb.h

85

uint8_t resv_blocks_gcmerge; /* ... merge pages when garbage collecting */

fs/jffs2/jffs2_fs_sb.h

87

uint8_t vdirty_blocks_gctrigger;

fs/jffs2/nodelist.h

168

uint8_t class; /* It's used for identification */

fs/jffs2/nodelist.h

172

uint8_t flags;

fs/jffs2/nodelist.h

412

uint8_t type, const char *name, int namelen, uint32_t time);

fs/jffs2/summary.h

118

uint8_t nsize; /* dirent name size */

fs/jffs2/summary.h

119

uint8_t type; /* dirent type */

fs/jffs2/summary.h

120

uint8_t name[]; /* dirent name */

fs/jffs2/summary.h

62

uint8_t nsize; /* dirent name size */

fs/jffs2/summary.h

63

uint8_t type; /* dirent type */

fs/jffs2/summary.h

64

uint8_t name[]; /* dirent name */

fs/jffs2/wbuf.c

1109

ops.oobbuf = (uint8_t *)&oob_cleanmarker;

fs/jffs2/wbuf.c

781

static size_t jffs2_fill_wbuf(struct jffs2_sb_info *c, const uint8_t *buf,

fs/jffs2/wbuf.c

861

uint8_t *v = invecs[invec].iov_base;

fs/jffs2/write.c

669

int jffs2_do_link (struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, uint32_t ino, uint8_t type, const char *name, int namelen, uint32_t time)

fs/jffs2/xattr.h

27

uint8_t class;

fs/jffs2/xattr.h

28

uint8_t flags;

fs/jffs2/xattr.h

49

uint8_t class;

fs/jffs2/xattr.h

50

uint8_t flags; /* Currently unused */

fs/nfsd/nfs4recover.c

1396

uint8_t version;

fs/nfsd/nfs4recover.c

64

uint8_t version;

fs/nfsd/nfs4recover.c

697

uint8_t cmd, princhashlen;

fs/pstore/ram_core.c

112

void *data, size_t len, uint8_t *ecc)

fs/pstore/ram_core.c

126

uint8_t *buffer_end = buffer->data + prz->buffer_size;

fs/pstore/ram_core.c

127

uint8_t *block;

fs/pstore/ram_core.c

128

uint8_t *par;

fs/pstore/ram_core.c

155

persistent_ram_encode_rs8(prz, (uint8_t *)buffer, sizeof(*buffer),

fs/pstore/ram_core.c

162

uint8_t *block;

fs/pstore/ram_core.c

163

uint8_t *par;

fs/pstore/ram_core.c

37

uint8_t data[];

fs/pstore/ram_core.c

99

uint8_t *data, size_t len, uint8_t *ecc)

fs/pstore/zone.c

38

uint8_t data[];

fs/pstore/zone.c

60

uint8_t data[];

fs/smb/client/cifs_spnego.h

27

uint8_t data[];

fs/ubifs/dir.c

535

static unsigned int vfs_dent_type(uint8_t type)

fs/ubifs/lpt.c

1014

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

1046

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

1078

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

222

static void pack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, uint32_t val, int nrbits)

fs/ubifs/lpt.c

224

uint8_t *p = *addr;

fs/ubifs/lpt.c

233

*p |= ((uint8_t)val) << b;

fs/ubifs/lpt.c

236

*++p = (uint8_t)(val >>= (8 - b));

fs/ubifs/lpt.c

238

*++p = (uint8_t)(val >>= 8);

fs/ubifs/lpt.c

240

*++p = (uint8_t)(val >>= 8);

fs/ubifs/lpt.c

242

*++p = (uint8_t)(val >>= 8);

fs/ubifs/lpt.c

247

*p = (uint8_t)val;

fs/ubifs/lpt.c

249

*++p = (uint8_t)(val >>= 8);

fs/ubifs/lpt.c

251

*++p = (uint8_t)(val >>= 8);

fs/ubifs/lpt.c

253

*++p = (uint8_t)(val >>= 8);

fs/ubifs/lpt.c

273

uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, int nrbits)

fs/ubifs/lpt.c

276

uint8_t *p = *addr;

fs/ubifs/lpt.c

343

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

376

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

408

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

432

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt.c

927

uint8_t *addr = buf;

fs/ubifs/lpt.c

951

static int check_lpt_type(const struct ubifs_info *c, uint8_t **addr,

fs/ubifs/lpt.c

977

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt_commit.c

1033

static int get_pad_len(const struct ubifs_info *c, uint8_t *buf, int len)

fs/ubifs/lpt_commit.c

1050

static int get_lpt_node_type(const struct ubifs_info *c, uint8_t *buf,

fs/ubifs/lpt_commit.c

1053

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt_commit.c

1069

static int is_a_node(const struct ubifs_info *c, uint8_t *buf, int len)

fs/ubifs/lpt_commit.c

1071

uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES;

fs/ubifs/lpt_commit.c

1460

static int dbg_is_all_ff(uint8_t *buf, int len)

fs/ubifs/recovery.c

405

uint8_t *p;

fs/ubifs/recovery.c

52

uint8_t *p = buf;

fs/ubifs/recovery.c

71

uint8_t *p = buf;

fs/ubifs/scan.c

31

uint8_t *p = buf;

fs/ubifs/scan.c

326

if (*(uint8_t *)buf != 0xff) {

fs/ubifs/ubifs.h

1357

uint8_t key_hash_type;

fs/ubifs/ubifs.h

1980

uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, int nrbits);

fs/ubifs/ubifs.h

282

uint8_t u8[UBIFS_SK_LEN];

fs/udf/directory.c

375

uint8_t *impuse, uint8_t *name)

fs/udf/directory.c

407

void udf_fiiter_write_fi(struct udf_fileident_iter *iter, uint8_t *impuse)

fs/udf/directory.c

499

struct short_ad *udf_get_fileshortad(uint8_t *ptr, int maxoffset, uint32_t *offset,

fs/udf/directory.c

522

struct long_ad *udf_get_filelongad(uint8_t *ptr, int maxoffset, uint32_t *offset, int inc)

fs/udf/ecma_167.h

104

uint8_t structType;

fs/udf/ecma_167.h

105

uint8_t stdIdent[VSD_STD_ID_LEN];

fs/udf/ecma_167.h

106

uint8_t structVersion;

fs/udf/ecma_167.h

107

uint8_t structData[2041];

fs/udf/ecma_167.h

123

uint8_t structType;

fs/udf/ecma_167.h

124

uint8_t stdIdent[VSD_STD_ID_LEN];

fs/udf/ecma_167.h

125

uint8_t structVersion;

fs/udf/ecma_167.h

126

uint8_t structData[2041];

fs/udf/ecma_167.h

131

uint8_t structType;

fs/udf/ecma_167.h

132

uint8_t stdIdent[VSD_STD_ID_LEN];

fs/udf/ecma_167.h

133

uint8_t structVersion;

fs/udf/ecma_167.h

134

uint8_t structData[2041];

fs/udf/ecma_167.h

139

uint8_t structType;

fs/udf/ecma_167.h

140

uint8_t stdIdent[VSD_STD_ID_LEN];

fs/udf/ecma_167.h

141

uint8_t structVersion;

fs/udf/ecma_167.h

142

uint8_t reserved1;

fs/udf/ecma_167.h

151

uint8_t reserved2[32];

fs/udf/ecma_167.h

152

uint8_t bootUse[1906];

fs/udf/ecma_167.h

173

uint8_t tagChecksum;

fs/udf/ecma_167.h

174

uint8_t reserved;

fs/udf/ecma_167.h

194

uint8_t structType;

fs/udf/ecma_167.h

195

uint8_t stdIdent[VSD_STD_ID_LEN];

fs/udf/ecma_167.h

196

uint8_t structVersion;

fs/udf/ecma_167.h

197

uint8_t reserved;

fs/udf/ecma_167.h

198

uint8_t structData[2040];

fs/udf/ecma_167.h

205

uint8_t reserved[492];

fs/udf/ecma_167.h

228

uint8_t impUse[64];

fs/udf/ecma_167.h

231

uint8_t reserved[22];

fs/udf/ecma_167.h

242

uint8_t reserved[480];

fs/udf/ecma_167.h

250

uint8_t reserved[484];

fs/udf/ecma_167.h

258

uint8_t impUse[460];

fs/udf/ecma_167.h

268

uint8_t partitionContentsUse[128];

fs/udf/ecma_167.h

273

uint8_t impUse[128];

fs/udf/ecma_167.h

274

uint8_t reserved[156];

fs/udf/ecma_167.h

304

uint8_t logicalVolContentsUse[16];

fs/udf/ecma_167.h

308

uint8_t impUse[128];

fs/udf/ecma_167.h

310

uint8_t partitionMaps[];

fs/udf/ecma_167.h

315

uint8_t partitionMapType;

fs/udf/ecma_167.h

316

uint8_t partitionMapLength;

fs/udf/ecma_167.h

317

uint8_t partitionMapping[];

fs/udf/ecma_167.h

327

uint8_t partitionMapType;

fs/udf/ecma_167.h

328

uint8_t partitionMapLength;

fs/udf/ecma_167.h

335

uint8_t partitionMapType;

fs/udf/ecma_167.h

336

uint8_t partitionMapLength;

fs/udf/ecma_167.h

337

uint8_t partitionIdent[62];

fs/udf/ecma_167.h

351

uint8_t reserved[496];

fs/udf/ecma_167.h

360

uint8_t logicalVolContentsUse[32];

fs/udf/ecma_167.h

394

uint8_t impUse[6];

fs/udf/ecma_167.h

400

uint8_t impUse[6];

fs/udf/ecma_167.h

453

uint8_t reserved[32];

fs/udf/ecma_167.h

463

uint8_t reserved[88];

fs/udf/ecma_167.h

47

typedef uint8_t dchars;

fs/udf/ecma_167.h

470

uint8_t fileCharacteristics;

fs/udf/ecma_167.h

471

uint8_t lengthFileIdent;

fs/udf/ecma_167.h

499

uint8_t reserved;

fs/udf/ecma_167.h

500

uint8_t fileType;

fs/udf/ecma_167.h

51

uint8_t charSetType;

fs/udf/ecma_167.h

52

uint8_t charSetInfo[63];

fs/udf/ecma_167.h

567

uint8_t recordFormat;

fs/udf/ecma_167.h

568

uint8_t recordDisplayAttr;

fs/udf/ecma_167.h

581

uint8_t extendedAttr[];

fs/udf/ecma_167.h

632

uint8_t attrSubtype;

fs/udf/ecma_167.h

633

uint8_t reserved[3];

fs/udf/ecma_167.h

635

uint8_t attrData[];

fs/udf/ecma_167.h

641

uint8_t attrSubtype;

fs/udf/ecma_167.h

642

uint8_t reserved[3];

fs/udf/ecma_167.h

645

uint8_t charSetType;

fs/udf/ecma_167.h

646

uint8_t escapeSeq[];

fs/udf/ecma_167.h

652

uint8_t attrSubtype;

fs/udf/ecma_167.h

653

uint8_t reserved[3];

fs/udf/ecma_167.h

663

uint8_t attrSubtype;

fs/udf/ecma_167.h

664

uint8_t reserved[3];

fs/udf/ecma_167.h

668

uint8_t fileTimes;

fs/udf/ecma_167.h

67

typedef uint8_t dstring;

fs/udf/ecma_167.h

680

uint8_t attrSubtype;

fs/udf/ecma_167.h

681

uint8_t reserved[3];

fs/udf/ecma_167.h

685

uint8_t infoTimes[];

fs/udf/ecma_167.h

691

uint8_t attrSubtype;

fs/udf/ecma_167.h

692

uint8_t reserved[3];

fs/udf/ecma_167.h

697

uint8_t impUse[];

fs/udf/ecma_167.h

703

uint8_t attrSubtype;

fs/udf/ecma_167.h

704

uint8_t reserved[3];

fs/udf/ecma_167.h

708

uint8_t impUse[];

fs/udf/ecma_167.h

714

uint8_t attrSubtype;

fs/udf/ecma_167.h

715

uint8_t reserved[3];

fs/udf/ecma_167.h

719

uint8_t appUse[];

fs/udf/ecma_167.h

73

uint8_t month;

fs/udf/ecma_167.h

736

uint8_t allocDescs[];

fs/udf/ecma_167.h

74

uint8_t day;

fs/udf/ecma_167.h

744

uint8_t bitmap[];

fs/udf/ecma_167.h

75

uint8_t hour;

fs/udf/ecma_167.h

752

uint8_t integrityType;

fs/udf/ecma_167.h

753

uint8_t reserved[175];

fs/udf/ecma_167.h

755

uint8_t impUse[256];

fs/udf/ecma_167.h

76

uint8_t minute;

fs/udf/ecma_167.h

77

uint8_t second;

fs/udf/ecma_167.h

775

uint8_t reserved[24];

fs/udf/ecma_167.h

78

uint8_t centiseconds;

fs/udf/ecma_167.h

780

uint8_t componentType;

fs/udf/ecma_167.h

781

uint8_t lengthComponentIdent;

fs/udf/ecma_167.h

79

uint8_t hundredsOfMicroseconds;

fs/udf/ecma_167.h

794

uint8_t recordFormat;

fs/udf/ecma_167.h

795

uint8_t recordDisplayAttr;

fs/udf/ecma_167.h

80

uint8_t microseconds;

fs/udf/ecma_167.h

812

uint8_t extendedAttr[];

fs/udf/ecma_167.h

92

uint8_t flags;

fs/udf/ecma_167.h

93

uint8_t ident[23];

fs/udf/ecma_167.h

94

uint8_t identSuffix[8];

fs/udf/inode.c

2149

uint8_t *ptr;

fs/udf/inode.c

2249

uint8_t *ptr;

fs/udf/misc.c

129

uint8_t subtype)

fs/udf/misc.c

132

uint8_t *ea = NULL;

fs/udf/misc.c

28

uint32_t type, uint8_t loc)

fs/udf/misc.c

30

uint8_t *ea = NULL, *ad = NULL;

fs/udf/namei.c

139

uint8_t alloctype;

fs/udf/namei.c

142

uint8_t *impuse;

fs/udf/namei.c

578

uint8_t *ea;

fs/udf/osta_udf.h

102

uint8_t impUse[8];

fs/udf/osta_udf.h

114

uint8_t impUse[];

fs/udf/osta_udf.h

126

uint8_t impUse[128];

fs/udf/osta_udf.h

130

uint8_t partitionMapType;

fs/udf/osta_udf.h

131

uint8_t partitionMapLength;

fs/udf/osta_udf.h

132

uint8_t reserved1[2];

fs/udf/osta_udf.h

140

uint8_t partitionMapType;

fs/udf/osta_udf.h

141

uint8_t partitionMapLength;

fs/udf/osta_udf.h

142

uint8_t reserved1[2];

fs/udf/osta_udf.h

146

uint8_t reserved2[24];

fs/udf/osta_udf.h

151

uint8_t partitionMapType;

fs/udf/osta_udf.h

152

uint8_t partitionMapLength;

fs/udf/osta_udf.h

153

uint8_t reserved1[2];

fs/udf/osta_udf.h

158

uint8_t numSparingTables;

fs/udf/osta_udf.h

159

uint8_t reserved2[1];

fs/udf/osta_udf.h

166

uint8_t partitionMapType;

fs/udf/osta_udf.h

167

uint8_t partitionMapLength;

fs/udf/osta_udf.h

168

uint8_t reserved1[2];

fs/udf/osta_udf.h

177

uint8_t flags;

fs/udf/osta_udf.h

178

uint8_t reserved2[5];

fs/udf/osta_udf.h

193

uint8_t impUse[];

fs/udf/osta_udf.h

222

uint8_t impUse[4];

fs/udf/osta_udf.h

234

uint8_t freeEASpace[];

fs/udf/osta_udf.h

240

uint8_t CGMSInfo;

fs/udf/osta_udf.h

241

uint8_t dataType;

fs/udf/osta_udf.h

242

uint8_t protectionSystemInfo[4];

fs/udf/osta_udf.h

258

uint8_t freeEASpace[];

fs/udf/osta_udf.h

84

uint8_t domainFlags;

fs/udf/osta_udf.h

85

uint8_t reserved[5];

fs/udf/osta_udf.h

90

uint8_t OSClass;

fs/udf/osta_udf.h

91

uint8_t OSIdentifier;

fs/udf/osta_udf.h

92

uint8_t reserved[4];

fs/udf/osta_udf.h

96

uint8_t OSClass;

fs/udf/osta_udf.h

97

uint8_t OSIdentifier;

fs/udf/osta_udf.h

98

uint8_t impUse[6];

fs/udf/super.c

122

(((uint8_t *)(lvid + 1)) + offset);

fs/udf/super.c

1437

uint8_t type;

fs/udf/super.c

2441

uint8_t *ptr;

fs/udf/super.c

2461

ptr = (uint8_t *)bh->b_data;

fs/udf/super.c

2477

ptr = (uint8_t *)bh->b_data;

fs/udf/super.c

893

uint8_t *outstr;

fs/udf/udfdecl.h

183

uint32_t, uint8_t);

fs/udf/udfdecl.h

185

uint8_t);

fs/udf/udfdecl.h

220

extern int udf_get_filename(struct super_block *, const uint8_t *, int,

fs/udf/udfdecl.h

221

uint8_t *, int);

fs/udf/udfdecl.h

222

extern int udf_put_filename(struct super_block *, const uint8_t *, int,

fs/udf/udfdecl.h

223

uint8_t *, int);

fs/udf/udfdecl.h

224

extern int udf_dstrCS0toChar(struct super_block *, uint8_t *, int,

fs/udf/udfdecl.h

225

const uint8_t *, int);

fs/udf/udfdecl.h

249

void udf_fiiter_write_fi(struct udf_fileident_iter *iter, uint8_t *impuse);

fs/udf/udfdecl.h

252

extern struct long_ad *udf_get_filelongad(uint8_t *, int, uint32_t *, int);

fs/udf/udfdecl.h

253

extern struct short_ad *udf_get_fileshortad(uint8_t *, int, uint32_t *, int);

fs/udf/udfdecl.h

97

uint8_t *name; /* Pointer to entry name */

fs/udf/udfdecl.h

98

uint8_t *namebuf; /* Storage for entry name in case

fs/udf/udftime.c

34

uint8_t type = typeAndTimezone >> 12;

fs/udf/unicode.c

149

uint8_t *str_o, int str_max_len,

fs/udf/unicode.c

150

const uint8_t *ocu, int ocu_len,

fs/udf/unicode.c

154

uint8_t cmp_id;

fs/udf/unicode.c

165

uint8_t ext[EXT_SIZE * NLS_MAX_CHARSET_SIZE + 1];

fs/udf/unicode.c

166

uint8_t crc[CRC_LEN];

fs/udf/unicode.c

273

uint8_t *ocu, int ocu_max_len,

fs/udf/unicode.c

274

const uint8_t *str_i, int str_len)

fs/udf/unicode.c

337

ocu[u_len++] = (uint8_t)(c >> 8);

fs/udf/unicode.c

338

ocu[u_len++] = (uint8_t)(c & 0xff);

fs/udf/unicode.c

344

ocu[u_len++] = (uint8_t)(uni_char >> 8);

fs/udf/unicode.c

345

ocu[u_len++] = (uint8_t)(uni_char & 0xff);

fs/udf/unicode.c

356

int udf_dstrCS0toChar(struct super_block *sb, uint8_t *utf_o, int o_len,

fs/udf/unicode.c

357

const uint8_t *ocu_i, int i_len)

fs/udf/unicode.c

376

int udf_get_filename(struct super_block *sb, const uint8_t *sname, int slen,

fs/udf/unicode.c

377

uint8_t *dname, int dlen)

fs/udf/unicode.c

394

int udf_put_filename(struct super_block *sb, const uint8_t *sname, int slen,

fs/udf/unicode.c

395

uint8_t *dname, int dlen)

fs/udf/unicode.c

43

static unicode_t get_utf16_char(const uint8_t *str_i, int str_i_max_len,

fs/udf/unicode.c

87

static int udf_name_conv_char(uint8_t *str_o, int str_o_max_len,

fs/udf/unicode.c

89

const uint8_t *str_i, int str_i_max_len,

fs/xfs/libxfs/xfs_ag.h

37

uint8_t pagf_bno_level; /* # of levels in bno btree */

fs/xfs/libxfs/xfs_ag.h

38

uint8_t pagf_cnt_level; /* # of levels in cnt btree */

fs/xfs/libxfs/xfs_ag.h

39

uint8_t pagf_rmap_level;/* # of levels in rmap btree */

fs/xfs/libxfs/xfs_ag.h

56

uint8_t pagf_refcount_level; /* recount btree height */

fs/xfs/libxfs/xfs_ag.h

75

uint8_t pagf_repair_bno_level;

fs/xfs/libxfs/xfs_ag.h

76

uint8_t pagf_repair_cnt_level;

fs/xfs/libxfs/xfs_ag.h

77

uint8_t pagf_repair_refcount_level;

fs/xfs/libxfs/xfs_ag.h

78

uint8_t pagf_repair_rmap_level;

fs/xfs/libxfs/xfs_attr.c

411

const uint8_t *name,

fs/xfs/libxfs/xfs_attr.c

422

const uint8_t *name,

fs/xfs/libxfs/xfs_attr.h

632

xfs_dahash_t xfs_attr_hashname(const uint8_t *name, int namelen);

fs/xfs/libxfs/xfs_attr.h

635

const uint8_t *name, int namelen, const void *value,

fs/xfs/libxfs/xfs_attr_remote.c

298

uint8_t **dst)

fs/xfs/libxfs/xfs_attr_remote.c

347

uint8_t **src)

fs/xfs/libxfs/xfs_attr_remote.c

403

uint8_t *dst = args->value;

fs/xfs/libxfs/xfs_attr_remote.c

502

uint8_t *src = args->value;

fs/xfs/libxfs/xfs_attr_sf.h

13

uint8_t entno; /* entry number in original list */

fs/xfs/libxfs/xfs_attr_sf.h

14

uint8_t namelen; /* length of name value (no null) */

fs/xfs/libxfs/xfs_attr_sf.h

15

uint8_t valuelen; /* length of value */

fs/xfs/libxfs/xfs_attr_sf.h

16

uint8_t flags; /* flags bits (see xfs_attr_leaf.h) */

fs/xfs/libxfs/xfs_attr_sf.h

23

((1 << (NBBY*(int)sizeof(uint8_t))) - 1)

fs/xfs/libxfs/xfs_attr_sf.h

26

static inline int xfs_attr_sf_entsize_byname(uint8_t nlen, uint8_t vlen)

fs/xfs/libxfs/xfs_btree.h

274

uint8_t bc_nlevels; /* number of levels in the tree */

fs/xfs/libxfs/xfs_btree.h

275

uint8_t bc_maxlevels; /* maximum levels for this btree type */

fs/xfs/libxfs/xfs_btree.h

674

uint8_t maxlevels,

fs/xfs/libxfs/xfs_da_btree.c

2285

xfs_da_hashname(const uint8_t *name, int namelen)

fs/xfs/libxfs/xfs_da_btree.h

21

uint8_t fsblog; /* log2 of _filesystem_ block size */

fs/xfs/libxfs/xfs_da_btree.h

22

uint8_t blklog; /* log2 of da block size */

fs/xfs/libxfs/xfs_da_btree.h

229

uint xfs_da_hashname(const uint8_t *name_string, int name_length);

fs/xfs/libxfs/xfs_da_btree.h

57

const uint8_t *name; /* string (maybe not NULL terminated) */

fs/xfs/libxfs/xfs_da_btree.h

58

const uint8_t *new_name; /* new attr name */

fs/xfs/libxfs/xfs_da_btree.h

69

uint8_t filetype; /* filetype of inode for directories */

fs/xfs/libxfs/xfs_da_btree.h

70

uint8_t op_flags; /* operation flags */

fs/xfs/libxfs/xfs_da_btree.h

71

uint8_t attr_filter; /* XFS_ATTR_{ROOT,SECURE,INCOMPLETE} */

fs/xfs/libxfs/xfs_da_format.h

215

uint8_t count; /* count of entries */

fs/xfs/libxfs/xfs_da_format.h

216

uint8_t i8count; /* count of 8-byte inode #s */

fs/xfs/libxfs/xfs_da_format.h

217

uint8_t parent[8]; /* parent dir inode number */

fs/xfs/libxfs/xfs_dir2.h

275

unsigned char xfs_dir3_get_dtype(struct xfs_mount *mp, uint8_t filetype);

fs/xfs/libxfs/xfs_dir2_data.c

50

uint8_t

fs/xfs/libxfs/xfs_dir2_data.c

56

uint8_t ftype = dep->name[dep->namelen];

fs/xfs/libxfs/xfs_dir2_data.c

69

uint8_t ftype)

fs/xfs/libxfs/xfs_dir2_priv.h

166

uint8_t xfs_dir2_sf_get_ftype(struct xfs_mount *mp,

fs/xfs/libxfs/xfs_dir2_priv.h

186

struct xfs_dir2_sf_entry *sfep, uint8_t ftype);

fs/xfs/libxfs/xfs_dir2_priv.h

209

len += sizeof(uint8_t);

fs/xfs/libxfs/xfs_dir2_priv.h

67

uint8_t xfs_dir2_data_get_ftype(struct xfs_mount *mp,

fs/xfs/libxfs/xfs_dir2_priv.h

70

struct xfs_dir2_data_entry *dep, uint8_t ftype);

fs/xfs/libxfs/xfs_dir2_sf.c

133

uint8_t

fs/xfs/libxfs/xfs_dir2_sf.c

139

uint8_t ftype = sfep->name[sfep->namelen];

fs/xfs/libxfs/xfs_dir2_sf.c

152

uint8_t ftype)

fs/xfs/libxfs/xfs_dir2_sf.c

52

count += sizeof(uint8_t);

fs/xfs/libxfs/xfs_dir2_sf.c

711

uint8_t filetype;

fs/xfs/libxfs/xfs_dir2_sf.c

77

uint8_t *from = sfep->name + sfep->namelen;

fs/xfs/libxfs/xfs_dir2_sf.c

94

uint8_t *to = sfep->name + sfep->namelen;

fs/xfs/libxfs/xfs_format.h

116

uint8_t sb_blocklog; /* log2 of sb_blocksize */

fs/xfs/libxfs/xfs_format.h

117

uint8_t sb_sectlog; /* log2 of sb_sectsize */

fs/xfs/libxfs/xfs_format.h

118

uint8_t sb_inodelog; /* log2 of sb_inodesize */

fs/xfs/libxfs/xfs_format.h

119

uint8_t sb_inopblog; /* log2 of sb_inopblock */

fs/xfs/libxfs/xfs_format.h

120

uint8_t sb_agblklog; /* log2 of sb_agblocks (rounded up) */

fs/xfs/libxfs/xfs_format.h

121

uint8_t sb_rextslog; /* log2 of sb_rextents */

fs/xfs/libxfs/xfs_format.h

122

uint8_t sb_inprogress; /* mkfs is in progress, don't mount */

fs/xfs/libxfs/xfs_format.h

123

uint8_t sb_imax_pct; /* max % of fs for inode space */

fs/xfs/libxfs/xfs_format.h

1332

#define XFS_DQUOT_VERSION (uint8_t)0x01 /* latest version number */

fs/xfs/libxfs/xfs_format.h

140

uint8_t sb_flags; /* misc. flags */

fs/xfs/libxfs/xfs_format.h

141

uint8_t sb_shared_vn; /* shared version number */

fs/xfs/libxfs/xfs_format.h

145

uint8_t sb_dirblklog; /* log2 of dir block size (fsbs) */

fs/xfs/libxfs/xfs_format.h

146

uint8_t sb_logsectlog; /* log2 of the log sector size */

fs/xfs/libxfs/xfs_format.h

1618

uint8_t ir_count; /* total inode count */

fs/xfs/libxfs/xfs_format.h

1619

uint8_t ir_freecount; /* count of free inodes (set bits) */

fs/xfs/libxfs/xfs_format.h

181

uint8_t sb_rgblklog; /* rt group number shift */

fs/xfs/libxfs/xfs_format.h

182

uint8_t sb_pad[7]; /* zeroes */

fs/xfs/libxfs/xfs_fs.h

459

uint8_t xi_alloccount; /* # bits set in allocmask */

fs/xfs/libxfs/xfs_fs.h

460

uint8_t xi_version; /* version */

fs/xfs/libxfs/xfs_fs.h

461

uint8_t xi_padding[6]; /* zero */

fs/xfs/libxfs/xfs_ialloc.c

100

uint8_t

fs/xfs/libxfs/xfs_ialloc.c

187

uint8_t count,

fs/xfs/libxfs/xfs_ialloc.h

108

uint8_t count, int32_t freecount, xfs_inofree_t free,

fs/xfs/libxfs/xfs_ialloc.h

85

uint8_t xfs_inobt_rec_freecount(const struct xfs_inobt_rec_incore *irec);

fs/xfs/libxfs/xfs_inode_buf.h

49

xfs_dinode_good_version(struct xfs_mount *mp, uint8_t version)

fs/xfs/libxfs/xfs_inode_fork.h

25

uint8_t if_needextents; /* extents have not been read */

fs/xfs/libxfs/xfs_log_format.h

284

uint8_t __pad[16]; /* unused */

fs/xfs/libxfs/xfs_log_format.h

305

uint8_t __pad[16]; /* unused */

fs/xfs/libxfs/xfs_log_format.h

410

uint8_t di_v2_pad[6]; /* V2 inode zeroed space */

fs/xfs/libxfs/xfs_log_format.h

436

uint8_t di_forkoff; /* attr fork offs, <<3 for 64b align */

fs/xfs/libxfs/xfs_log_format.h

466

uint8_t di_pad2[12]; /* more padding for future expansion */

fs/xfs/libxfs/xfs_parent.c

103

const uint8_t *name,

fs/xfs/libxfs/xfs_parent.c

125

const uint8_t *name,

fs/xfs/libxfs/xfs_parent.h

15

xfs_dahash_t xfs_parent_hashval(struct xfs_mount *mp, const uint8_t *name,

fs/xfs/libxfs/xfs_parent.h

17

xfs_dahash_t xfs_parent_hashattr(struct xfs_mount *mp, const uint8_t *name,

fs/xfs/libxfs/xfs_quota_defs.h

20

typedef uint8_t xfs_dqtype_t;

fs/xfs/libxfs/xfs_rtbitmap.c

594

uint8_t *rsum_cache = args->rtg->rtg_rsum_cache;

fs/xfs/libxfs/xfs_rtgroup.h

50

uint8_t *rtg_rsum_cache;

fs/xfs/libxfs/xfs_sb.c

1748

uint8_t

fs/xfs/libxfs/xfs_sb.h

46

uint8_t xfs_compute_rextslog(xfs_rtbxlen_t rtextents);

fs/xfs/scrub/attr_repair.c

141

uint8_t namelen;

fs/xfs/scrub/attr_repair.c

144

uint8_t action;

fs/xfs/scrub/dir.c

59

uint8_t namelen;

fs/xfs/scrub/dir.c

80

uint8_t namebuf[MAXNAMELEN];

fs/xfs/scrub/dir_repair.c

103

uint8_t namelen;

fs/xfs/scrub/dir_repair.c

106

uint8_t ftype;

fs/xfs/scrub/dir_repair.c

109

uint8_t action;

fs/xfs/scrub/inode_repair.c

139

uint8_t alleged_ftype;

fs/xfs/scrub/iscan.c

308

uint8_t *nr_inodesp)

fs/xfs/scrub/iscan.c

434

uint8_t nr_inodes)

fs/xfs/scrub/iscan.c

584

uint8_t nr_inodes = 0;

fs/xfs/scrub/iscan.c

91

uint8_t *nr_inodesp)

fs/xfs/scrub/parent.c

240

uint8_t namelen;

fs/xfs/scrub/parent_repair.c

94

uint8_t namelen;

fs/xfs/scrub/parent_repair.c

97

uint8_t action;

fs/xfs/scrub/trace.h

1597

__field(uint8_t, ftype)

fs/xfs/scrub/trace.h

2140

__field(uint8_t, count)

fs/xfs/scrub/trace.h

2141

__field(uint8_t, freecount)

fs/xfs/scrub/trace.h

2435

__field(uint8_t, version)

fs/xfs/scrub/trace.h

2436

__field(uint8_t, format)

fs/xfs/scrub/trace.h

2444

__field(uint8_t, forkoff)

fs/xfs/scrub/trace.h

2445

__field(uint8_t, aformat)

fs/xfs/scrub/trace.h

2520

__field(uint8_t, format)

fs/xfs/scrub/trace.h

2522

__field(uint8_t, aformat)

fs/xfs/scrub/trace.h

2734

TP_PROTO(struct xfs_mount *mp, uint8_t type, uint32_t id),

fs/xfs/scrub/trace.h

2738

__field(uint8_t, type)

fs/xfs/scrub/trace.h

2754

TP_PROTO(struct xfs_mount *mp, uint8_t type, uint32_t id), \

fs/xfs/scrub/trace.h

3160

__field(uint8_t, ftype)

fs/xfs/scrub/xfarray.c

769

si->max_stack_used = max_t(uint8_t, si->max_stack_used,

fs/xfs/scrub/xfarray.h

119

uint8_t max_stack_depth;

fs/xfs/scrub/xfarray.h

125

uint8_t max_stack_used;

fs/xfs/xfs_dahash_test.c

18

static uint8_t __initdata __attribute__((__aligned__(8))) test_buf[] =

fs/xfs/xfs_dir2_readdir.c

106

uint8_t filetype;

fs/xfs/xfs_dir2_readdir.c

184

uint8_t filetype;

fs/xfs/xfs_dir2_readdir.c

34

uint8_t filetype)

fs/xfs/xfs_dir2_readdir.c

385

uint8_t filetype;

fs/xfs/xfs_dquot.c

582

uint8_t ddqp_type;

fs/xfs/xfs_dquot.c

583

uint8_t dqp_type;

fs/xfs/xfs_inode.h

72

uint8_t i_forkoff; /* attr fork offset >> 3 */

fs/xfs/xfs_log.c

3235

uint8_t clientid;

fs/xfs/xfs_log_priv.h

174

uint8_t t_flags; /* properties of reservation */

fs/xfs/xfs_mount.h

182

uint8_t m_blkbit_log; /* blocklog + NBBY */

fs/xfs/xfs_mount.h

183

uint8_t m_blkbb_log; /* blocklog - BBSHIFT */

fs/xfs/xfs_mount.h

184

uint8_t m_agno_log; /* log #ag's */

fs/xfs/xfs_mount.h

185

uint8_t m_sectbb_log; /* sectlog - BBSHIFT */

fs/xfs/xfs_mount.h

248

uint8_t m_fs_checked;

fs/xfs/xfs_mount.h

249

uint8_t m_fs_sick;

fs/xfs/xfs_mount.h

254

uint8_t m_rt_checked;

fs/xfs/xfs_mount.h

255

uint8_t m_rt_sick;

fs/xfs/xfs_mount.h

99

uint8_t blklog;

fs/xfs/xfs_rtalloc.c

1203

uint8_t *old_rsum_cache = NULL;

fs/xfs/xfs_rtalloc.c

50

uint8_t *rsum_cache = args->rtg->rtg_rsum_cache;

fs/xfs/xfs_zone_info.c

21

uint8_t write_hint)

include/drm/display/drm_dp_mst_helper.h

881

void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);

include/drm/drm_connector.h

2176

uint8_t polled;

include/drm/drm_connector.h

2227

uint8_t eld[MAX_ELD_BYTES];

include/drm/drm_connector.h

2322

uint8_t num_h_tile, num_v_tile;

include/drm/drm_connector.h

2325

uint8_t tile_h_loc, tile_v_loc;

include/kunit/of.h

69

extern uint8_t of_overlay_begin(overlay_name)[]; \

include/kunit/of.h

70

extern uint8_t of_overlay_end(overlay_name)[] \

include/linux/acpi_amd_wbrf.h

51

int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in);

include/linux/acpi_amd_wbrf.h

64

int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in)

include/linux/bch.h

63

void bch_encode(struct bch_control *bch, const uint8_t *data,

include/linux/bch.h

64

unsigned int len, uint8_t *ecc);

include/linux/bch.h

66

int bch_decode(struct bch_control *bch, const uint8_t *data, unsigned int len,

include/linux/bch.h

67

const uint8_t *recv_ecc, const uint8_t *calc_ecc,

include/linux/crc4.h

7

extern uint8_t crc4(uint8_t c, uint64_t x, int bits);

include/linux/digsig.h

28

uint8_t version; /* key format version */

include/linux/digsig.h

30

uint8_t algo;

include/linux/digsig.h

31

uint8_t nmpi;

include/linux/digsig.h

36

uint8_t version; /* signature format version */

include/linux/digsig.h

38

uint8_t algo;

include/linux/digsig.h

39

uint8_t hash;

include/linux/digsig.h

40

uint8_t keyid[8];

include/linux/digsig.h

41

uint8_t nmpi;

include/linux/firmware/imx/ipc.h

31

uint8_t ver;

include/linux/firmware/imx/ipc.h

32

uint8_t size;

include/linux/firmware/imx/ipc.h

33

uint8_t svc;

include/linux/firmware/imx/ipc.h

34

uint8_t func;

include/linux/firmware/imx/s4.h

14

uint8_t ver;

include/linux/firmware/imx/s4.h

15

uint8_t size;

include/linux/firmware/imx/s4.h

16

uint8_t cmd;

include/linux/firmware/imx/s4.h

17

uint8_t tag;

include/linux/hil_mlc.h

110

uint8_t idd[16]; /* Device ID Byte and Describe Record */

include/linux/hil_mlc.h

111

uint8_t rsc[16]; /* Security Code Header and Record */

include/linux/hil_mlc.h

112

uint8_t exd[16]; /* Extended Describe Record */

include/linux/hil_mlc.h

113

uint8_t rnm[16]; /* Device name as returned by RNM command */

include/linux/hp_sdc.h

270

uint8_t im; /* Interrupt mask */

include/linux/hp_sdc.h

274

uint8_t wi; /* current i8042 write index */

include/linux/hp_sdc.h

275

uint8_t r7[4]; /* current i8042[0x70 - 0x74] values */

include/linux/hp_sdc.h

276

uint8_t r11, r7e; /* Values from version/revision regs */

include/linux/hp_sdc.h

55

uint8_t status, uint8_t data);

include/linux/hp_sdc.h

68

uint8_t *seq; /* commands/data for the transaction */

include/linux/ihex.h

21

uint8_t data[];

include/linux/input/cma3000.h

41

uint8_t mode;

include/linux/input/cma3000.h

42

uint8_t mdthr;

include/linux/input/cma3000.h

43

uint8_t mdfftmr;

include/linux/input/cma3000.h

44

uint8_t ffthr;

include/linux/intel-ish-client-if.h

102

int ishtp_cl_send(struct ishtp_cl *cl, uint8_t *buf, size_t length);

include/linux/ipmi_smi.h

247

static inline int ipmi_demangle_device_id(uint8_t netfn, uint8_t cmd,

include/linux/lz4.h

102

const uint8_t *dictionary;

include/linux/lz4.h

103

uint8_t *bufferStart;

include/linux/lz4.h

143

const uint8_t *externalDict;

include/linux/lz4.h

145

const uint8_t *prefixEnd;

include/linux/mfd/adp5520.h

287

extern int adp5520_read(struct device *dev, int reg, uint8_t *val);

include/linux/mfd/adp5520.h

289

extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);

include/linux/mfd/adp5520.h

290

extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);

include/linux/mfd/arizona/core.h

156

uint8_t dac_comp_enabled;

include/linux/mfd/da903x.h

241

extern int da903x_write(struct device *dev, int reg, uint8_t val);

include/linux/mfd/da903x.h

242

extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val);

include/linux/mfd/da903x.h

243

extern int da903x_read(struct device *dev, int reg, uint8_t *val);

include/linux/mfd/da903x.h

244

extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val);

include/linux/mfd/da903x.h

245

extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask);

include/linux/mfd/da903x.h

246

extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask);

include/linux/mfd/da903x.h

247

extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);

include/linux/mfd/rc5t583.h

294

uint8_t intc_inten_reg;

include/linux/mfd/rc5t583.h

297

uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_EN_REGS];

include/linux/mfd/rc5t583.h

300

uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];

include/linux/mfd/rc5t583.h

326

static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)

include/linux/mfd/rc5t583.h

332

static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)

include/linux/mfd/rc5t583.h

339

*val = (uint8_t)ival;

include/linux/mfd/tps65090.h

114

static inline int tps65090_write(struct device *dev, int reg, uint8_t val)

include/linux/mfd/tps65090.h

121

static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)

include/linux/mfd/tps65090.h

134

uint8_t bit_num)

include/linux/mfd/tps65090.h

142

uint8_t bit_num)

include/linux/mfd/tps6586x.h

101

extern int tps6586x_write(struct device *dev, int reg, uint8_t val);

include/linux/mfd/tps6586x.h

102

extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val);

include/linux/mfd/tps6586x.h

103

extern int tps6586x_read(struct device *dev, int reg, uint8_t *val);

include/linux/mfd/tps6586x.h

104

extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val);

include/linux/mfd/tps6586x.h

105

extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);

include/linux/mfd/tps6586x.h

106

extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);

include/linux/mfd/tps6586x.h

107

extern int tps6586x_update(struct device *dev, int reg, uint8_t val,

include/linux/mfd/tps6586x.h

108

uint8_t mask);

include/linux/mpi.h

56

int mpi_read_buffer(MPI a, uint8_t *buf, unsigned buf_len, unsigned *nbytes,

include/linux/mtd/bbm.h

130

uint8_t *bbt;

include/linux/mtd/bbm.h

46

uint8_t version[NAND_MAX_CHIPS];

include/linux/mtd/bbm.h

50

uint8_t *pattern;

include/linux/mtd/cfi.h

120

uint8_t qry[3];

include/linux/mtd/cfi.h

125

uint8_t VccMin;

include/linux/mtd/cfi.h

126

uint8_t VccMax;

include/linux/mtd/cfi.h

127

uint8_t VppMin;

include/linux/mtd/cfi.h

128

uint8_t VppMax;

include/linux/mtd/cfi.h

129

uint8_t WordWriteTimeoutTyp;

include/linux/mtd/cfi.h

130

uint8_t BufWriteTimeoutTyp;

include/linux/mtd/cfi.h

131

uint8_t BlockEraseTimeoutTyp;

include/linux/mtd/cfi.h

132

uint8_t ChipEraseTimeoutTyp;

include/linux/mtd/cfi.h

133

uint8_t WordWriteTimeoutMax;

include/linux/mtd/cfi.h

134

uint8_t BufWriteTimeoutMax;

include/linux/mtd/cfi.h

135

uint8_t BlockEraseTimeoutMax;

include/linux/mtd/cfi.h

136

uint8_t ChipEraseTimeoutMax;

include/linux/mtd/cfi.h

137

uint8_t DevSize;

include/linux/mtd/cfi.h

140

uint8_t NumEraseRegions;

include/linux/mtd/cfi.h

147

uint8_t pri[3];

include/linux/mtd/cfi.h

148

uint8_t MajorVersion;

include/linux/mtd/cfi.h

149

uint8_t MinorVersion;

include/linux/mtd/cfi.h

155

uint8_t pri[3];

include/linux/mtd/cfi.h

156

uint8_t MajorVersion;

include/linux/mtd/cfi.h

157

uint8_t MinorVersion;

include/linux/mtd/cfi.h

160

uint8_t SuspendCmdSupport;

include/linux/mtd/cfi.h

162

uint8_t VccOptimal;

include/linux/mtd/cfi.h

163

uint8_t VppOptimal;

include/linux/mtd/cfi.h

164

uint8_t NumProtectionFields;

include/linux/mtd/cfi.h

166

uint8_t FactProtRegSize;

include/linux/mtd/cfi.h

167

uint8_t UserProtRegSize;

include/linux/mtd/cfi.h

168

uint8_t extra[];

include/linux/mtd/cfi.h

174

uint8_t FactProtRegSize;

include/linux/mtd/cfi.h

176

uint8_t UserProtRegSize;

include/linux/mtd/cfi.h

183

uint8_t BitsPerCell;

include/linux/mtd/cfi.h

184

uint8_t BlockCap;

include/linux/mtd/cfi.h

189

uint8_t NumOpAllowed;

include/linux/mtd/cfi.h

190

uint8_t NumOpAllowedSimProgMode;

include/linux/mtd/cfi.h

191

uint8_t NumOpAllowedSimEraMode;

include/linux/mtd/cfi.h

192

uint8_t NumBlockTypes;

include/linux/mtd/cfi.h

197

uint8_t ProgRegShift;

include/linux/mtd/cfi.h

198

uint8_t Reserved1;

include/linux/mtd/cfi.h

199

uint8_t ControlValid;

include/linux/mtd/cfi.h

200

uint8_t Reserved2;

include/linux/mtd/cfi.h

201

uint8_t ControlInvalid;

include/linux/mtd/cfi.h

202

uint8_t Reserved3;

include/linux/mtd/cfi.h

208

uint8_t pri[3];

include/linux/mtd/cfi.h

209

uint8_t MajorVersion;

include/linux/mtd/cfi.h

210

uint8_t MinorVersion;

include/linux/mtd/cfi.h

211

uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */

include/linux/mtd/cfi.h

212

uint8_t EraseSuspend;

include/linux/mtd/cfi.h

213

uint8_t BlkProt;

include/linux/mtd/cfi.h

214

uint8_t TmpBlkUnprotect;

include/linux/mtd/cfi.h

215

uint8_t BlkProtUnprot;

include/linux/mtd/cfi.h

216

uint8_t SimultaneousOps;

include/linux/mtd/cfi.h

217

uint8_t BurstMode;

include/linux/mtd/cfi.h

218

uint8_t PageMode;

include/linux/mtd/cfi.h

219

uint8_t VppMin;

include/linux/mtd/cfi.h

220

uint8_t VppMax;

include/linux/mtd/cfi.h

221

uint8_t TopBottom;

include/linux/mtd/cfi.h

223

uint8_t ProgramSuspend;

include/linux/mtd/cfi.h

224

uint8_t UnlockBypass;

include/linux/mtd/cfi.h

225

uint8_t SecureSiliconSector;

include/linux/mtd/cfi.h

226

uint8_t SoftwareFeatures;

include/linux/mtd/cfi.h

234

uint8_t pri[3];

include/linux/mtd/cfi.h

235

uint8_t MajorVersion;

include/linux/mtd/cfi.h

236

uint8_t MinorVersion;

include/linux/mtd/cfi.h

237

uint8_t Features;

include/linux/mtd/cfi.h

238

uint8_t BottomBoot;

include/linux/mtd/cfi.h

239

uint8_t BurstMode;

include/linux/mtd/cfi.h

240

uint8_t PageMode;

include/linux/mtd/cfi.h

244

uint8_t NumFields;

include/linux/mtd/cfi.h

249

uint8_t PageModeReadCap;

include/linux/mtd/cfi.h

250

uint8_t NumFields;

include/linux/mtd/cfi.h

307

static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)

include/linux/mtd/ftl.h

35

uint8_t LinkTargetTuple[5];

include/linux/mtd/ftl.h

36

uint8_t DataOrgTuple[10];

include/linux/mtd/ftl.h

37

uint8_t NumTransferUnits;

include/linux/mtd/ftl.h

40

uint8_t BlockSize;

include/linux/mtd/ftl.h

41

uint8_t EraseUnitSize;

include/linux/mtd/ftl.h

47

uint8_t Flags;

include/linux/mtd/ftl.h

48

uint8_t Code;

include/linux/mtd/ftl.h

52

uint8_t Reserved[12];

include/linux/mtd/ftl.h

53

uint8_t EndTuple[2];

include/linux/mtd/inftl.h

57

size_t *retlen, uint8_t *buf);

include/linux/mtd/inftl.h

59

size_t *retlen, uint8_t *buf);

include/linux/mtd/mtd.h

77

uint8_t *datbuf;

include/linux/mtd/mtd.h

78

uint8_t *oobbuf;

include/linux/mtd/nftl.h

45

size_t *retlen, uint8_t *buf);

include/linux/mtd/nftl.h

47

size_t *retlen, uint8_t *buf);

include/linux/mtd/platnand.h

59

void (*write_buf)(struct nand_chip *chip, const uint8_t *buf, int len);

include/linux/mtd/platnand.h

60

void (*read_buf)(struct nand_chip *chip, uint8_t *buf, int len);

include/linux/mtd/qinfo.h

38

uint8_t major;

include/linux/mtd/qinfo.h

39

uint8_t minor;

include/linux/mtd/rawnand.h

1458

uint8_t mfr_id;

include/linux/mtd/rawnand.h

1459

uint8_t dev_id;

include/linux/mtd/rawnand.h

1461

uint8_t id[NAND_MAX_ID_LEN];

include/linux/mtd/rawnand.h

1536

int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,

include/linux/mtd/rawnand.h

1538

int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,

include/linux/mtd/rawnand.h

1542

int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,

include/linux/mtd/rawnand.h

1544

int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,

include/linux/mtd/rawnand.h

1578

int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,

include/linux/mtd/rawnand.h

364

int (*calculate)(struct nand_chip *chip, const uint8_t *dat,

include/linux/mtd/rawnand.h

365

uint8_t *ecc_code);

include/linux/mtd/rawnand.h

366

int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,

include/linux/mtd/rawnand.h

367

uint8_t *calc_ecc);

include/linux/mtd/rawnand.h

368

int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,

include/linux/mtd/rawnand.h

370

int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,

include/linux/mtd/rawnand.h

372

int (*read_page)(struct nand_chip *chip, uint8_t *buf,

include/linux/mtd/rawnand.h

375

uint32_t len, uint8_t *buf, int page);

include/linux/mtd/rawnand.h

377

uint32_t data_len, const uint8_t *data_buf,

include/linux/mtd/rawnand.h

379

int (*write_page)(struct nand_chip *chip, const uint8_t *buf,

include/linux/mtd/sh_flctl.h

140

uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */

include/linux/netfilter.h

298

NF_HOOK_COND(uint8_t pf, unsigned int hook, struct net *net, struct sock *sk,

include/linux/netfilter.h

312

NF_HOOK(uint8_t pf, unsigned int hook, struct net *net, struct sock *sk, struct sk_buff *skb,

include/linux/netfilter.h

323

NF_HOOK_LIST(uint8_t pf, unsigned int hook, struct net *net, struct sock *sk,

include/linux/netfilter.h

409

NF_HOOK_COND(uint8_t pf, unsigned int hook, struct net *net, struct sock *sk,

include/linux/netfilter.h

418

NF_HOOK(uint8_t pf, unsigned int hook, struct net *net, struct sock *sk,

include/linux/netfilter.h

426

NF_HOOK_LIST(uint8_t pf, unsigned int hook, struct net *net, struct sock *sk,

include/linux/pe.h

289

uint8_t ld_major; /* linker major version */

include/linux/pe.h

290

uint8_t ld_minor; /* linker minor version */

include/linux/pe.h

324

uint8_t ld_major; /* linker major version */

include/linux/pe.h

325

uint8_t ld_minor; /* linker minor version */

include/linux/perf/riscv_pmu.h

69

uint8_t (*csr_index)(struct perf_event *event);

include/linux/phonet.h

17

uint8_t device;

include/linux/platform_data/cros_ec_chardev.h

30

uint8_t buffer[EC_MEMMAP_SIZE];

include/linux/platform_data/cros_ec_commands.h

1060

uint8_t offset;

include/linux/platform_data/cros_ec_commands.h

1061

uint8_t size;

include/linux/platform_data/cros_ec_commands.h

1072

uint8_t cmd;

include/linux/platform_data/cros_ec_commands.h

1123

uint8_t buf[32];

include/linux/platform_data/cros_ec_commands.h

1128

uint8_t buf[32];

include/linux/platform_data/cros_ec_commands.h

1453

uint8_t reserved[2];

include/linux/platform_data/cros_ec_commands.h

1460

uint8_t size_exp;

include/linux/platform_data/cros_ec_commands.h

1462

uint8_t write_size_exp;

include/linux/platform_data/cros_ec_commands.h

1464

uint8_t erase_size_exp;

include/linux/platform_data/cros_ec_commands.h

1466

uint8_t protect_size_exp;

include/linux/platform_data/cros_ec_commands.h

1468

uint8_t reserved[2];

include/linux/platform_data/cros_ec_commands.h

1564

uint8_t cmd;

include/linux/platform_data/cros_ec_commands.h

1565

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

1704

uint8_t block[EC_VBNV_BLOCK_SIZE];

include/linux/platform_data/cros_ec_commands.h

1708

uint8_t block[EC_VBNV_BLOCK_SIZE];

include/linux/platform_data/cros_ec_commands.h

1717

uint8_t jedec[3];

include/linux/platform_data/cros_ec_commands.h

1720

uint8_t reserved0;

include/linux/platform_data/cros_ec_commands.h

1723

uint8_t mfr_dev_id[2];

include/linux/platform_data/cros_ec_commands.h

1726

uint8_t sr1, sr2;

include/linux/platform_data/cros_ec_commands.h

1738

uint8_t select;

include/linux/platform_data/cros_ec_commands.h

1763

uint8_t fan_idx;

include/linux/platform_data/cros_ec_commands.h

1771

uint8_t percent;

include/linux/platform_data/cros_ec_commands.h

1772

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

1780

uint8_t percent;

include/linux/platform_data/cros_ec_commands.h

1794

uint8_t fan_idx;

include/linux/platform_data/cros_ec_commands.h

1813

uint8_t pwm_type; /* ec_pwm_type */

include/linux/platform_data/cros_ec_commands.h

1814

uint8_t index; /* Type-specific index, or 0 if unique */

include/linux/platform_data/cros_ec_commands.h

1820

uint8_t pwm_type; /* ec_pwm_type */

include/linux/platform_data/cros_ec_commands.h

1821

uint8_t index; /* Type-specific index, or 0 if unique */

include/linux/platform_data/cros_ec_commands.h

1831

uint8_t fan_idx;

include/linux/platform_data/cros_ec_commands.h

1848

uint8_t r, g, b;

include/linux/platform_data/cros_ec_commands.h

1870

uint8_t new_s0;

include/linux/platform_data/cros_ec_commands.h

1871

uint8_t osc_min[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1872

uint8_t osc_max[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1873

uint8_t w_ofs[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1876

uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1877

uint8_t bright_bl_on_min[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1878

uint8_t bright_bl_on_max[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1881

uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];

include/linux/platform_data/cros_ec_commands.h

1884

uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */

include/linux/platform_data/cros_ec_commands.h

1885

uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */

include/linux/platform_data/cros_ec_commands.h

1909

uint8_t tap_pct_red;

include/linux/platform_data/cros_ec_commands.h

1910

uint8_t tap_pct_green;

include/linux/platform_data/cros_ec_commands.h

1911

uint8_t tap_seg_min_on;

include/linux/platform_data/cros_ec_commands.h

1912

uint8_t tap_seg_max_on;

include/linux/platform_data/cros_ec_commands.h

1913

uint8_t tap_seg_osc;

include/linux/platform_data/cros_ec_commands.h

1914

uint8_t tap_idx[3];

include/linux/platform_data/cros_ec_commands.h

1917

uint8_t osc_min[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1918

uint8_t osc_max[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1919

uint8_t w_ofs[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1922

uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1923

uint8_t bright_bl_on_min[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1924

uint8_t bright_bl_on_max[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1927

uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];

include/linux/platform_data/cros_ec_commands.h

1930

uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */

include/linux/platform_data/cros_ec_commands.h

1931

uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */

include/linux/platform_data/cros_ec_commands.h

1934

uint8_t s5_idx;

include/linux/platform_data/cros_ec_commands.h

1969

uint8_t tap_pct_red;

include/linux/platform_data/cros_ec_commands.h

1970

uint8_t tap_pct_green;

include/linux/platform_data/cros_ec_commands.h

1971

uint8_t tap_seg_min_on;

include/linux/platform_data/cros_ec_commands.h

1972

uint8_t tap_seg_max_on;

include/linux/platform_data/cros_ec_commands.h

1973

uint8_t tap_seg_osc;

include/linux/platform_data/cros_ec_commands.h

1974

uint8_t tap_idx[3];

include/linux/platform_data/cros_ec_commands.h

1979

uint8_t osc_min[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1980

uint8_t osc_max[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1981

uint8_t w_ofs[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1986

uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1987

uint8_t bright_bl_on_min[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1988

uint8_t bright_bl_on_max[2]; /* AC=0/1 */

include/linux/platform_data/cros_ec_commands.h

1993

uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];

include/linux/platform_data/cros_ec_commands.h

1998

uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */

include/linux/platform_data/cros_ec_commands.h

1999

uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */

include/linux/platform_data/cros_ec_commands.h

2002

uint8_t s5_idx;

include/linux/platform_data/cros_ec_commands.h

2013

uint8_t reported_led_num;

include/linux/platform_data/cros_ec_commands.h

2019

uint8_t size;

include/linux/platform_data/cros_ec_commands.h

2020

uint8_t data[EC_LB_PROG_LEN];

include/linux/platform_data/cros_ec_commands.h

2029

uint8_t size;

include/linux/platform_data/cros_ec_commands.h

2031

uint8_t data[];

include/linux/platform_data/cros_ec_commands.h

2035

uint8_t cmd; /* Command (see enum lightbar_command) */

include/linux/platform_data/cros_ec_commands.h

2050

uint8_t num;

include/linux/platform_data/cros_ec_commands.h

2054

uint8_t ctrl, reg, value;

include/linux/platform_data/cros_ec_commands.h

2058

uint8_t led, red, green, blue;

include/linux/platform_data/cros_ec_commands.h

2062

uint8_t led;

include/linux/platform_data/cros_ec_commands.h

2066

uint8_t enable;

include/linux/platform_data/cros_ec_commands.h

2088

uint8_t reg;

include/linux/platform_data/cros_ec_commands.h

2089

uint8_t ic0;

include/linux/platform_data/cros_ec_commands.h

2090

uint8_t ic1;

include/linux/platform_data/cros_ec_commands.h

2095

uint8_t num;

include/linux/platform_data/cros_ec_commands.h

2117

uint8_t red, green, blue;

include/linux/platform_data/cros_ec_commands.h

2216

uint8_t led_id; /* Which LED to control */

include/linux/platform_data/cros_ec_commands.h

2217

uint8_t flags; /* Control flags */

include/linux/platform_data/cros_ec_commands.h

2219

uint8_t brightness[EC_LED_COLOR_COUNT];

include/linux/platform_data/cros_ec_commands.h

2230

uint8_t brightness_range[EC_LED_COLOR_COUNT];

include/linux/platform_data/cros_ec_commands.h

2245

uint8_t cmd; /* enum ec_vboot_hash_cmd */

include/linux/platform_data/cros_ec_commands.h

2246

uint8_t hash_type; /* enum ec_vboot_hash_type */

include/linux/platform_data/cros_ec_commands.h

2247

uint8_t nonce_size; /* Nonce size; may be 0 */

include/linux/platform_data/cros_ec_commands.h

2248

uint8_t reserved0; /* Reserved; set 0 */

include/linux/platform_data/cros_ec_commands.h

2251

uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */

include/linux/platform_data/cros_ec_commands.h

2255

uint8_t status; /* enum ec_vboot_hash_status */

include/linux/platform_data/cros_ec_commands.h

2256

uint8_t hash_type; /* enum ec_vboot_hash_type */

include/linux/platform_data/cros_ec_commands.h

2257

uint8_t digest_size; /* Size of hash digest in bytes */

include/linux/platform_data/cros_ec_commands.h

2258

uint8_t reserved0; /* Ignore; will be 0 */

include/linux/platform_data/cros_ec_commands.h

2261

uint8_t hash_digest[64]; /* Hash digest data */

include/linux/platform_data/cros_ec_commands.h

2491

uint8_t activity; /* motionsensor_activity */

include/linux/platform_data/cros_ec_commands.h

2492

uint8_t state;

include/linux/platform_data/cros_ec_commands.h

2497

uint8_t flags;

include/linux/platform_data/cros_ec_commands.h

2499

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2545

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2546

uint8_t activity; /* one of enum motionsensor_activity */

include/linux/platform_data/cros_ec_commands.h

2547

uint8_t enable; /* 1: enable, 0: disable */

include/linux/platform_data/cros_ec_commands.h

2548

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

2601

uint8_t cmd;

include/linux/platform_data/cros_ec_commands.h

2610

uint8_t max_sensor_count;

include/linux/platform_data/cros_ec_commands.h

2627

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2635

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2636

uint8_t enable;

include/linux/platform_data/cros_ec_commands.h

2643

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2646

uint8_t roundup;

include/linux/platform_data/cros_ec_commands.h

2656

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2685

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2742

uint8_t sensor_id;

include/linux/platform_data/cros_ec_commands.h

2745

uint8_t spoof_enable;

include/linux/platform_data/cros_ec_commands.h

2748

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

2774

uint8_t sensor_num;

include/linux/platform_data/cros_ec_commands.h

2775

uint8_t activity; /* enum motionsensor_activity */

include/linux/platform_data/cros_ec_commands.h

2785

uint8_t module_flags;

include/linux/platform_data/cros_ec_commands.h

2788

uint8_t sensor_count;

include/linux/platform_data/cros_ec_commands.h

2800

uint8_t type;

include/linux/platform_data/cros_ec_commands.h

2803

uint8_t location;

include/linux/platform_data/cros_ec_commands.h

2806

uint8_t chip;

include/linux/platform_data/cros_ec_commands.h

2812

uint8_t type;

include/linux/platform_data/cros_ec_commands.h

2815

uint8_t location;

include/linux/platform_data/cros_ec_commands.h

2818

uint8_t chip;

include/linux/platform_data/cros_ec_commands.h

2896

uint8_t state;

include/linux/platform_data/cros_ec_commands.h

2908

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

2922

uint8_t flags;

include/linux/platform_data/cros_ec_commands.h

2932

uint8_t usb_port_id;

include/linux/platform_data/cros_ec_commands.h

2933

uint8_t mode:7;

include/linux/platform_data/cros_ec_commands.h

2934

uint8_t inhibit_charge:1;

include/linux/platform_data/cros_ec_commands.h

2971

uint8_t data[EC_PSTORE_SIZE_MAX];

include/linux/platform_data/cros_ec_commands.h

3054

uint8_t slot_count;

include/linux/platform_data/cros_ec_commands.h

3065

uint8_t slot; /* Slot to read from */

include/linux/platform_data/cros_ec_commands.h

3069

uint8_t data[EC_VSTORE_SLOT_SIZE];

include/linux/platform_data/cros_ec_commands.h

3078

uint8_t slot; /* Slot to write to */

include/linux/platform_data/cros_ec_commands.h

3079

uint8_t data[EC_VSTORE_SLOT_SIZE];

include/linux/platform_data/cros_ec_commands.h

3098

uint8_t sensor_type;

include/linux/platform_data/cros_ec_commands.h

3099

uint8_t threshold_id;

include/linux/platform_data/cros_ec_commands.h

3105

uint8_t sensor_type;

include/linux/platform_data/cros_ec_commands.h

3106

uint8_t threshold_id;

include/linux/platform_data/cros_ec_commands.h

3180

uint8_t fan_idx;

include/linux/platform_data/cros_ec_commands.h

3185

uint8_t fan_idx;

include/linux/platform_data/cros_ec_commands.h

3186

uint8_t cmd; /* enum ec_auto_fan_ctrl_cmd */

include/linux/platform_data/cros_ec_commands.h

3187

uint8_t set_auto; /* only used with EC_AUTO_FAN_CONTROL_CMD_SET - bool

include/linux/platform_data/cros_ec_commands.h

3192

uint8_t is_auto; /* bool */

include/linux/platform_data/cros_ec_commands.h

3210

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

3222

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

3223

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

3232

uint8_t algorithm;

include/linux/platform_data/cros_ec_commands.h

3233

uint8_t num_params;

include/linux/platform_data/cros_ec_commands.h

3234

uint8_t reserved[2];

include/linux/platform_data/cros_ec_commands.h

3239

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

3240

uint8_t algorithm;

include/linux/platform_data/cros_ec_commands.h

3241

uint8_t num_params;

include/linux/platform_data/cros_ec_commands.h

3242

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

3251

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

3283

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

3287

uint8_t info_type;

include/linux/platform_data/cros_ec_commands.h

3288

uint8_t event_type;

include/linux/platform_data/cros_ec_commands.h

3334

uint8_t col;

include/linux/platform_data/cros_ec_commands.h

3335

uint8_t row;

include/linux/platform_data/cros_ec_commands.h

3336

uint8_t pressed;

include/linux/platform_data/cros_ec_commands.h

3377

uint8_t flags; /* some flags (enum mkbp_config_flags) */

include/linux/platform_data/cros_ec_commands.h

3378

uint8_t valid_flags; /* which flags are valid */

include/linux/platform_data/cros_ec_commands.h

3393

uint8_t fifo_max_depth;

include/linux/platform_data/cros_ec_commands.h

3424

uint8_t flags; /* some flags (enum ec_collect_flags) */

include/linux/platform_data/cros_ec_commands.h

3428

uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */

include/linux/platform_data/cros_ec_commands.h

3431

uint8_t active; /* still active */

include/linux/platform_data/cros_ec_commands.h

3432

uint8_t num_items; /* number of items */

include/linux/platform_data/cros_ec_commands.h

3434

uint8_t cur_item;

include/linux/platform_data/cros_ec_commands.h

3442

uint8_t scan[0]; /* keyscan data */

include/linux/platform_data/cros_ec_commands.h

3445

uint8_t start_item; /* First item to return */

include/linux/platform_data/cros_ec_commands.h

3446

uint8_t num_items; /* Number of items to return */

include/linux/platform_data/cros_ec_commands.h

3454

uint8_t num_items; /* Number of items */

include/linux/platform_data/cros_ec_commands.h

3525

uint8_t key_matrix[13];

include/linux/platform_data/cros_ec_commands.h

3533

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

3550

uint8_t key_matrix[16];

include/linux/platform_data/cros_ec_commands.h

3558

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

3573

uint8_t cec_message[16];

include/linux/platform_data/cros_ec_commands.h

3578

uint8_t key_matrix[18];

include/linux/platform_data/cros_ec_commands.h

3586

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

3601

uint8_t cec_message[16];

include/linux/platform_data/cros_ec_commands.h

3606

uint8_t event_type;

include/linux/platform_data/cros_ec_commands.h

3612

uint8_t event_type;

include/linux/platform_data/cros_ec_commands.h

3618

uint8_t event_type;

include/linux/platform_data/cros_ec_commands.h

3687

uint8_t id;

include/linux/platform_data/cros_ec_commands.h

3692

uint8_t sensor_type;

include/linux/platform_data/cros_ec_commands.h

3741

uint8_t action;

include/linux/platform_data/cros_ec_commands.h

3747

uint8_t mask_type;

include/linux/platform_data/cros_ec_commands.h

3820

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

3829

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

3835

uint8_t now_flags;

include/linux/platform_data/cros_ec_commands.h

3838

uint8_t now_mask;

include/linux/platform_data/cros_ec_commands.h

3845

uint8_t suspend_flags;

include/linux/platform_data/cros_ec_commands.h

3848

uint8_t suspend_mask;

include/linux/platform_data/cros_ec_commands.h

3854

uint8_t now_flags;

include/linux/platform_data/cros_ec_commands.h

3857

uint8_t suspend_flags;

include/linux/platform_data/cros_ec_commands.h

3868

uint8_t val;

include/linux/platform_data/cros_ec_commands.h

3880

uint8_t val;

include/linux/platform_data/cros_ec_commands.h

3885

uint8_t subcmd;

include/linux/platform_data/cros_ec_commands.h

3891

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

3899

uint8_t val;

include/linux/platform_data/cros_ec_commands.h

3902

uint8_t val;

include/linux/platform_data/cros_ec_commands.h

3930

uint8_t read_size; /* Either 8 or 16. */

include/linux/platform_data/cros_ec_commands.h

3931

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

3932

uint8_t offset;

include/linux/platform_data/cros_ec_commands.h

3945

uint8_t write_size; /* Either 8 or 16. */

include/linux/platform_data/cros_ec_commands.h

3946

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

3947

uint8_t offset;

include/linux/platform_data/cros_ec_commands.h

3987

uint8_t cmd; /* enum ec_charge_control_cmd. */

include/linux/platform_data/cros_ec_commands.h

3988

uint8_t flags; /* enum ec_charge_control_flag (v3+) */

include/linux/platform_data/cros_ec_commands.h

4010

uint8_t flags; /* enum ec_charge_control_flag (v3+) */

include/linux/platform_data/cros_ec_commands.h

4011

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

4039

uint8_t subcmd; /* enum ec_console_read_subcmd */

include/linux/platform_data/cros_ec_commands.h

4056

uint8_t flags;

include/linux/platform_data/cros_ec_commands.h

4068

uint8_t mux;

include/linux/platform_data/cros_ec_commands.h

4085

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

4086

uint8_t state;

include/linux/platform_data/cros_ec_commands.h

4095

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

4099

uint8_t state;

include/linux/platform_data/cros_ec_commands.h

4141

uint8_t port; /* I2C port number */

include/linux/platform_data/cros_ec_commands.h

4142

uint8_t num_msgs; /* Number of messages */

include/linux/platform_data/cros_ec_commands.h

4148

uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */

include/linux/platform_data/cros_ec_commands.h

4149

uint8_t num_msgs; /* Number of messages processed */

include/linux/platform_data/cros_ec_commands.h

4150

uint8_t data[]; /* Data read by messages concatenated here */

include/linux/platform_data/cros_ec_commands.h

4198

uint8_t status; /* enum ec_hang_detect_status */

include/linux/platform_data/cros_ec_commands.h

4254

uint8_t cmd; /* enum charge_state_command */

include/linux/platform_data/cros_ec_commands.h

4367

uint8_t sleep_event;

include/linux/platform_data/cros_ec_commands.h

4381

uint8_t sleep_event;

include/linux/platform_data/cros_ec_commands.h

4384

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

4451

uint8_t param;

include/linux/platform_data/cros_ec_commands.h

4472

uint8_t reg;

include/linux/platform_data/cros_ec_commands.h

4480

uint8_t reg;

include/linux/platform_data/cros_ec_commands.h

4485

uint8_t data[32];

include/linux/platform_data/cros_ec_commands.h

4489

uint8_t reg;

include/linux/platform_data/cros_ec_commands.h

4512

uint8_t mode;

include/linux/platform_data/cros_ec_commands.h

4558

uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];

include/linux/platform_data/cros_ec_commands.h

4567

uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE];

include/linux/platform_data/cros_ec_commands.h

4572

uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE];

include/linux/platform_data/cros_ec_commands.h

4605

uint8_t subcmd;

include/linux/platform_data/cros_ec_commands.h

4606

uint8_t port; /* I2C port number */

include/linux/platform_data/cros_ec_commands.h

4610

uint8_t status; /* Status flags (0: unlocked, 1: locked) */

include/linux/platform_data/cros_ec_commands.h

4643

uint8_t msg[MAX_CEC_MSG_LEN];

include/linux/platform_data/cros_ec_commands.h

4653

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

4654

uint8_t msg_len;

include/linux/platform_data/cros_ec_commands.h

4655

uint8_t msg[MAX_CEC_MSG_LEN];

include/linux/platform_data/cros_ec_commands.h

4666

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

4675

uint8_t msg_len;

include/linux/platform_data/cros_ec_commands.h

4676

uint8_t msg[MAX_CEC_MSG_LEN];

include/linux/platform_data/cros_ec_commands.h

4692

uint8_t cmd : 4; /* enum cec_command */

include/linux/platform_data/cros_ec_commands.h

4693

uint8_t port : 4;

include/linux/platform_data/cros_ec_commands.h

4694

uint8_t val;

include/linux/platform_data/cros_ec_commands.h

4706

uint8_t cmd : 4; /* enum cec_command */

include/linux/platform_data/cros_ec_commands.h

4707

uint8_t port : 4;

include/linux/platform_data/cros_ec_commands.h

4718

uint8_t val;

include/linux/platform_data/cros_ec_commands.h

4729

uint8_t port_count;

include/linux/platform_data/cros_ec_commands.h

4780

uint8_t shm_id;

include/linux/platform_data/cros_ec_commands.h

4781

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4787

uint8_t shm_id;

include/linux/platform_data/cros_ec_commands.h

4788

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4792

uint8_t cmd; /* enum ec_codec_subcmd */

include/linux/platform_data/cros_ec_commands.h

4793

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4810

uint8_t type;

include/linux/platform_data/cros_ec_commands.h

4811

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4839

uint8_t channel; /* enum ec_codec_dmic_channel */

include/linux/platform_data/cros_ec_commands.h

4840

uint8_t gain;

include/linux/platform_data/cros_ec_commands.h

4841

uint8_t reserved[2];

include/linux/platform_data/cros_ec_commands.h

4845

uint8_t channel; /* enum ec_codec_dmic_channel */

include/linux/platform_data/cros_ec_commands.h

4846

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4850

uint8_t cmd; /* enum ec_codec_dmic_subcmd */

include/linux/platform_data/cros_ec_commands.h

4851

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4862

uint8_t max_gain;

include/linux/platform_data/cros_ec_commands.h

4866

uint8_t gain;

include/linux/platform_data/cros_ec_commands.h

4899

uint8_t depth;

include/linux/platform_data/cros_ec_commands.h

4900

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4904

uint8_t left;

include/linux/platform_data/cros_ec_commands.h

4905

uint8_t right;

include/linux/platform_data/cros_ec_commands.h

4906

uint8_t reserved[2];

include/linux/platform_data/cros_ec_commands.h

4910

uint8_t daifmt;

include/linux/platform_data/cros_ec_commands.h

4911

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4919

uint8_t cmd; /* enum ec_codec_i2s_rx_subcmd */

include/linux/platform_data/cros_ec_commands.h

4920

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4956

uint8_t hash[32];

include/linux/platform_data/cros_ec_commands.h

4959

uint8_t buf[128];

include/linux/platform_data/cros_ec_commands.h

4964

uint8_t hash[32];

include/linux/platform_data/cros_ec_commands.h

4969

uint8_t cmd; /* enum ec_codec_wov_subcmd */

include/linux/platform_data/cros_ec_commands.h

4970

uint8_t reserved[3];

include/linux/platform_data/cros_ec_commands.h

4981

uint8_t hash[32];

include/linux/platform_data/cros_ec_commands.h

4985

uint8_t buf[128];

include/linux/platform_data/cros_ec_commands.h

5022

uint8_t cmd; /* enum ec_reboot_cmd */

include/linux/platform_data/cros_ec_commands.h

5023

uint8_t flags; /* See EC_REBOOT_FLAG_* */

include/linux/platform_data/cros_ec_commands.h

5096

uint8_t status; /* EC status */

include/linux/platform_data/cros_ec_commands.h

5098

uint8_t charge_state; /* charging state (from enum pd_charge_state) */

include/linux/platform_data/cros_ec_commands.h

5166

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5167

uint8_t role;

include/linux/platform_data/cros_ec_commands.h

5168

uint8_t mux;

include/linux/platform_data/cros_ec_commands.h

5169

uint8_t swap;

include/linux/platform_data/cros_ec_commands.h

5185

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

5186

uint8_t role;

include/linux/platform_data/cros_ec_commands.h

5187

uint8_t polarity;

include/linux/platform_data/cros_ec_commands.h

5188

uint8_t state;

include/linux/platform_data/cros_ec_commands.h

5192

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

5193

uint8_t role;

include/linux/platform_data/cros_ec_commands.h

5194

uint8_t polarity;

include/linux/platform_data/cros_ec_commands.h

5216

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

5217

uint8_t role;

include/linux/platform_data/cros_ec_commands.h

5218

uint8_t polarity;

include/linux/platform_data/cros_ec_commands.h

5220

uint8_t cc_state; /* enum pd_cc_states representing cc state */

include/linux/platform_data/cros_ec_commands.h

5221

uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */

include/linux/platform_data/cros_ec_commands.h

5222

uint8_t reserved; /* Reserved for future use */

include/linux/platform_data/cros_ec_commands.h

5223

uint8_t control_flags; /* USB_PD_CTRL_*flags */

include/linux/platform_data/cros_ec_commands.h

5224

uint8_t cable_speed; /* TBT_SS_* cable speed */

include/linux/platform_data/cros_ec_commands.h

5225

uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */

include/linux/platform_data/cros_ec_commands.h

5234

uint8_t num_ports;

include/linux/platform_data/cros_ec_commands.h

5241

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5272

uint8_t role;

include/linux/platform_data/cros_ec_commands.h

5273

uint8_t type;

include/linux/platform_data/cros_ec_commands.h

5274

uint8_t dualrole;

include/linux/platform_data/cros_ec_commands.h

5275

uint8_t reserved1;

include/linux/platform_data/cros_ec_commands.h

5288

uint8_t port_count;

include/linux/platform_data/cros_ec_commands.h

5303

uint8_t cmd;

include/linux/platform_data/cros_ec_commands.h

5304

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5315

uint8_t dev_rw_hash[PD_RW_HASH_SIZE];

include/linux/platform_data/cros_ec_commands.h

5316

uint8_t reserved; /*

include/linux/platform_data/cros_ec_commands.h

5328

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5336

uint8_t ptype; /* product type (hub,periph,cable,ama) */

include/linux/platform_data/cros_ec_commands.h

5362

uint8_t type; /* event type : see PD_EVENT_xx below */

include/linux/platform_data/cros_ec_commands.h

5363

uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */

include/linux/platform_data/cros_ec_commands.h

5365

uint8_t payload[]; /* optional additional data payload: 0..16 bytes */

include/linux/platform_data/cros_ec_commands.h

5429

uint8_t major;

include/linux/platform_data/cros_ec_commands.h

5430

uint8_t minor;

include/linux/platform_data/cros_ec_commands.h

5435

uint8_t family[2];

include/linux/platform_data/cros_ec_commands.h

5436

uint8_t chipid[2];

include/linux/platform_data/cros_ec_commands.h

5449

uint8_t port; /* port */

include/linux/platform_data/cros_ec_commands.h

5470

uint8_t opos; /* Object Position */

include/linux/platform_data/cros_ec_commands.h

5471

uint8_t port; /* port */

include/linux/platform_data/cros_ec_commands.h

5478

uint8_t type; /* event type : see PD_EVENT_xx above */

include/linux/platform_data/cros_ec_commands.h

5479

uint8_t port; /* port#, or 0 for events unrelated to a given port */

include/linux/platform_data/cros_ec_commands.h

5495

uint8_t chip; /* chip id */

include/linux/platform_data/cros_ec_commands.h

5496

uint8_t subcmd;

include/linux/platform_data/cros_ec_commands.h

5503

uint8_t port; /* USB-C port number */

include/linux/platform_data/cros_ec_commands.h

5518

uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */

include/linux/platform_data/cros_ec_commands.h

5524

uint8_t port; /* USB-C port number */

include/linux/platform_data/cros_ec_commands.h

5525

uint8_t renew; /* Force renewal */

include/linux/platform_data/cros_ec_commands.h

5533

uint8_t fw_version_string[8];

include/linux/platform_data/cros_ec_commands.h

5543

uint8_t fw_version_string[8];

include/linux/platform_data/cros_ec_commands.h

5547

uint8_t min_req_fw_version_string[8];

include/linux/platform_data/cros_ec_commands.h

5575

uint8_t region; /* enum ec_flash_region */

include/linux/platform_data/cros_ec_commands.h

5628

uint8_t data[]; /* For string and raw data */

include/linux/platform_data/cros_ec_commands.h

5703

uint8_t action;

include/linux/platform_data/cros_ec_commands.h

5712

uint8_t adc_channel;

include/linux/platform_data/cros_ec_commands.h

5742

uint8_t port_count;

include/linux/platform_data/cros_ec_commands.h

5751

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5756

uint8_t state; /* enum pchg_state state */

include/linux/platform_data/cros_ec_commands.h

5757

uint8_t battery_percentage;

include/linux/platform_data/cros_ec_commands.h

5758

uint8_t unused0;

include/linux/platform_data/cros_ec_commands.h

5759

uint8_t unused1;

include/linux/platform_data/cros_ec_commands.h

5834

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5836

uint8_t cmd;

include/linux/platform_data/cros_ec_commands.h

5838

uint8_t reserved0;

include/linux/platform_data/cros_ec_commands.h

5839

uint8_t reserved1;

include/linux/platform_data/cros_ec_commands.h

5849

uint8_t data[];

include/linux/platform_data/cros_ec_commands.h

587

uint8_t flags;

include/linux/platform_data/cros_ec_commands.h

588

uint8_t command_version;

include/linux/platform_data/cros_ec_commands.h

589

uint8_t data_size;

include/linux/platform_data/cros_ec_commands.h

5894

uint8_t enable;

include/linux/platform_data/cros_ec_commands.h

590

uint8_t checksum;

include/linux/platform_data/cros_ec_commands.h

5909

uint8_t enabled;

include/linux/platform_data/cros_ec_commands.h

5963

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

5964

uint8_t partner_type; /* enum typec_partner_type */

include/linux/platform_data/cros_ec_commands.h

5974

uint8_t identity_count; /* Number of identity VDOs partner sent */

include/linux/platform_data/cros_ec_commands.h

5975

uint8_t svid_count; /* Number of SVIDs partner sent */

include/linux/platform_data/cros_ec_commands.h

6001

uint8_t mux_index; /* Index of the mux to set in the chain */

include/linux/platform_data/cros_ec_commands.h

6002

uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */

include/linux/platform_data/cros_ec_commands.h

6011

uint8_t vdm_data_objects;

include/linux/platform_data/cros_ec_commands.h

6013

uint8_t partner_type;

include/linux/platform_data/cros_ec_commands.h

6017

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

6018

uint8_t command; /* enum typec_control_command */

include/linux/platform_data/cros_ec_commands.h

6028

uint8_t mode_to_enter; /* enum typec_mode */

include/linux/platform_data/cros_ec_commands.h

6029

uint8_t tbt_ufp_reply; /* enum typec_tbt_ufp_reply */

include/linux/platform_data/cros_ec_commands.h

6033

uint8_t placeholder[128];

include/linux/platform_data/cros_ec_commands.h

6119

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

6123

uint8_t pd_enabled; /* PD communication enabled - bool */

include/linux/platform_data/cros_ec_commands.h

6124

uint8_t dev_connected; /* Device connected - bool */

include/linux/platform_data/cros_ec_commands.h

6125

uint8_t sop_connected; /* Device is SOP PD capable - bool */

include/linux/platform_data/cros_ec_commands.h

6126

uint8_t source_cap_count; /* Number of Source Cap PDOs */

include/linux/platform_data/cros_ec_commands.h

6128

uint8_t power_role; /* enum pd_power_role */

include/linux/platform_data/cros_ec_commands.h

6129

uint8_t data_role; /* enum pd_data_role */

include/linux/platform_data/cros_ec_commands.h

6130

uint8_t vconn_role; /* enum pd_vconn_role */

include/linux/platform_data/cros_ec_commands.h

6131

uint8_t sink_cap_count; /* Number of Sink Cap PDOs */

include/linux/platform_data/cros_ec_commands.h

6133

uint8_t polarity; /* enum tcpc_cc_polarity */

include/linux/platform_data/cros_ec_commands.h

6134

uint8_t cc_state; /* enum pd_cc_states */

include/linux/platform_data/cros_ec_commands.h

6135

uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */

include/linux/platform_data/cros_ec_commands.h

6136

uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */

include/linux/platform_data/cros_ec_commands.h

6167

uint8_t port;

include/linux/platform_data/cros_ec_commands.h

6172

uint8_t vdm_data_objects;

include/linux/platform_data/cros_ec_commands.h

6174

uint8_t partner_type;

include/linux/platform_data/cros_ec_commands.h

6180

uint8_t vdm_attention_objects;

include/linux/platform_data/cros_ec_commands.h

6182

uint8_t vdm_attention_left;

include/linux/platform_data/cros_ec_commands.h

6203

uint8_t data[];

include/linux/platform_data/cros_ec_commands.h

6211

uint8_t size;

include/linux/platform_data/cros_ec_commands.h

6235

uint8_t data[]; /* Data to send */

include/linux/platform_data/cros_ec_commands.h

6389

uint8_t nonce[FP_CONTEXT_NONCE_BYTES];

include/linux/platform_data/cros_ec_commands.h

6390

uint8_t salt[FP_CONTEXT_SALT_BYTES];

include/linux/platform_data/cros_ec_commands.h

6391

uint8_t tag[FP_CONTEXT_TAG_BYTES];

include/linux/platform_data/cros_ec_commands.h

6413

uint8_t data[];

include/linux/platform_data/cros_ec_commands.h

6436

uint8_t timestamps_invalid;

include/linux/platform_data/cros_ec_commands.h

6449

uint8_t seed[FP_CONTEXT_TPM_BYTES];

include/linux/platform_data/cros_ec_commands.h

6506

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

6541

uint8_t index;

include/linux/platform_data/cros_ec_commands.h

6582

uint8_t allow_charging;

include/linux/platform_data/cros_ec_commands.h

6589

uint8_t port; /* USB-C port number */

include/linux/platform_data/cros_ec_commands.h

756

uint8_t struct_version;

include/linux/platform_data/cros_ec_commands.h

757

uint8_t checksum;

include/linux/platform_data/cros_ec_commands.h

759

uint8_t command_version;

include/linux/platform_data/cros_ec_commands.h

760

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

776

uint8_t struct_version;

include/linux/platform_data/cros_ec_commands.h

777

uint8_t checksum;

include/linux/platform_data/cros_ec_commands.h

851

uint8_t fields0;

include/linux/platform_data/cros_ec_commands.h

858

uint8_t fields1;

include/linux/platform_data/cros_ec_commands.h

867

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

870

uint8_t header_crc;

include/linux/platform_data/cros_ec_commands.h

881

uint8_t fields0;

include/linux/platform_data/cros_ec_commands.h

887

uint8_t fields1;

include/linux/platform_data/cros_ec_commands.h

896

uint8_t reserved;

include/linux/platform_data/cros_ec_commands.h

899

uint8_t header_crc;

include/linux/platform_data/cros_ec_proto.h

94

uint8_t data[];

include/linux/raid/pq.h

36

typedef uint8_t u8;

include/linux/rslib.h

61

int encode_rs8(struct rs_control *rs, uint8_t *data, int len, uint16_t *par,

include/linux/rslib.h

65

int decode_rs8(struct rs_control *rs, uint8_t *data, uint16_t *par, int len,

include/linux/sctp.h

301

uint8_t hostname[];

include/linux/soc/qcom/apr.h

58

uint8_t src_svc;

include/linux/soc/qcom/apr.h

59

uint8_t src_domain;

include/linux/soc/qcom/apr.h

61

uint8_t dest_svc;

include/linux/soc/qcom/apr.h

62

uint8_t dest_domain;

include/linux/soc/qcom/apr.h

70

uint8_t payload[];

include/linux/xz.h

131

const uint8_t *in;

include/linux/xz.h

135

uint8_t *out;

include/linux/xz.h

357

uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc);

include/media/dvb_demux.h

234

uint8_t *cnt_storage; /* for TS continuity check */

include/net/cfg80211.h

7114

uint8_t align:4, size:4;

include/net/cfg80211.h

7121

uint8_t subns;

include/net/dsa.h

897

u32 stringset, uint8_t *data);

include/net/ieee80211_radiotap.h

31

uint8_t it_version;

include/net/ieee80211_radiotap.h

36

uint8_t it_pad;

include/rdma/opa_smi.h

37

uint8_t data[OPA_SMP_LID_DATA_SIZE];

include/scsi/iscsi_if.h

315

uint8_t value[]; /* length sized value follows */

include/scsi/iscsi_if.h

322

uint8_t iface_type; /* IPv4 or IPv6 */

include/scsi/iscsi_if.h

323

uint8_t param_type; /* iscsi_param_type */

include/scsi/iscsi_if.h

324

uint8_t value[]; /* length sized value follows */

include/scsi/iscsi_if.h

335

uint8_t mac_addr[6];

include/scsi/iscsi_if.h

336

uint8_t mac_addr_old[6];

include/scsi/iscsi_if.h

701

uint8_t value[]; /* length sized value follows */

include/scsi/iscsi_if.h

842

uint8_t password[ISCSI_CHAP_AUTH_SECRET_MAX_LEN];

include/scsi/iscsi_if.h

843

uint8_t password_length;

include/scsi/iscsi_proto.h

129

uint8_t ahstype;

include/scsi/iscsi_proto.h

130

uint8_t ahspec[5];

include/scsi/iscsi_proto.h

139

uint8_t opcode;

include/scsi/iscsi_proto.h

140

uint8_t flags;

include/scsi/iscsi_proto.h

142

uint8_t hlength;

include/scsi/iscsi_proto.h

143

uint8_t dlength[3];

include/scsi/iscsi_proto.h

149

uint8_t cdb[ISCSI_CDB_SIZE]; /* SCSI Command Block */

include/scsi/iscsi_proto.h

168

uint8_t ahstype;

include/scsi/iscsi_proto.h

169

uint8_t reserved;

include/scsi/iscsi_proto.h

176

uint8_t ahstype;

include/scsi/iscsi_proto.h

177

uint8_t reserved;

include/scsi/iscsi_proto.h

179

uint8_t ecdb[SCSI_MAX_VARLEN_CDB_SIZE - ISCSI_CDB_SIZE];

include/scsi/iscsi_proto.h

184

uint8_t opcode;

include/scsi/iscsi_proto.h

185

uint8_t flags;

include/scsi/iscsi_proto.h

186

uint8_t response;

include/scsi/iscsi_proto.h

187

uint8_t cmd_status;

include/scsi/iscsi_proto.h

188

uint8_t hlength;

include/scsi/iscsi_proto.h

189

uint8_t dlength[3];

include/scsi/iscsi_proto.h

190

uint8_t rsvd[8];

include/scsi/iscsi_proto.h

215

uint8_t opcode;

include/scsi/iscsi_proto.h

216

uint8_t flags;

include/scsi/iscsi_proto.h

217

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

218

uint8_t rsvd3;

include/scsi/iscsi_proto.h

219

uint8_t dlength[3];

include/scsi/iscsi_proto.h

221

uint8_t rsvd4[8];

include/scsi/iscsi_proto.h

225

uint8_t async_event;

include/scsi/iscsi_proto.h

226

uint8_t async_vcode;

include/scsi/iscsi_proto.h

230

uint8_t rsvd5[4];

include/scsi/iscsi_proto.h

243

uint8_t opcode;

include/scsi/iscsi_proto.h

244

uint8_t flags;

include/scsi/iscsi_proto.h

246

uint8_t rsvd3;

include/scsi/iscsi_proto.h

247

uint8_t dlength[3];

include/scsi/iscsi_proto.h

253

uint8_t rsvd4[16];

include/scsi/iscsi_proto.h

258

uint8_t opcode;

include/scsi/iscsi_proto.h

259

uint8_t flags;

include/scsi/iscsi_proto.h

261

uint8_t rsvd3;

include/scsi/iscsi_proto.h

262

uint8_t dlength[3];

include/scsi/iscsi_proto.h

269

uint8_t rsvd4[12];

include/scsi/iscsi_proto.h

274

uint8_t opcode;

include/scsi/iscsi_proto.h

275

uint8_t flags;

include/scsi/iscsi_proto.h

276

uint8_t rsvd1[2];

include/scsi/iscsi_proto.h

277

uint8_t hlength;

include/scsi/iscsi_proto.h

278

uint8_t dlength[3];

include/scsi/iscsi_proto.h

286

uint8_t rsvd2[8];

include/scsi/iscsi_proto.h

305

uint8_t opcode;

include/scsi/iscsi_proto.h

306

uint8_t flags;

include/scsi/iscsi_proto.h

307

uint8_t response; /* see Response values below */

include/scsi/iscsi_proto.h

308

uint8_t qualifier;

include/scsi/iscsi_proto.h

309

uint8_t hlength;

include/scsi/iscsi_proto.h

310

uint8_t dlength[3];

include/scsi/iscsi_proto.h

311

uint8_t rsvd2[8];

include/scsi/iscsi_proto.h

317

uint8_t rsvd3[12];

include/scsi/iscsi_proto.h

332

uint8_t opcode;

include/scsi/iscsi_proto.h

333

uint8_t flags;

include/scsi/iscsi_proto.h

334

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

335

uint8_t hlength;

include/scsi/iscsi_proto.h

336

uint8_t dlength[3];

include/scsi/iscsi_proto.h

350

uint8_t opcode;

include/scsi/iscsi_proto.h

351

uint8_t flags;

include/scsi/iscsi_proto.h

352

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

353

uint8_t rsvd3;

include/scsi/iscsi_proto.h

354

uint8_t dlength[3];

include/scsi/iscsi_proto.h

369

uint8_t opcode;

include/scsi/iscsi_proto.h

370

uint8_t flags;

include/scsi/iscsi_proto.h

371

uint8_t rsvd2;

include/scsi/iscsi_proto.h

372

uint8_t cmd_status;

include/scsi/iscsi_proto.h

373

uint8_t hlength;

include/scsi/iscsi_proto.h

374

uint8_t dlength[3];

include/scsi/iscsi_proto.h

394

uint8_t opcode;

include/scsi/iscsi_proto.h

395

uint8_t flags;

include/scsi/iscsi_proto.h

396

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

397

uint8_t hlength;

include/scsi/iscsi_proto.h

398

uint8_t dlength[3];

include/scsi/iscsi_proto.h

399

uint8_t rsvd4[8];

include/scsi/iscsi_proto.h

404

uint8_t rsvd5[16];

include/scsi/iscsi_proto.h

412

uint8_t opcode;

include/scsi/iscsi_proto.h

413

uint8_t flags;

include/scsi/iscsi_proto.h

414

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

415

uint8_t hlength;

include/scsi/iscsi_proto.h

416

uint8_t dlength[3];

include/scsi/iscsi_proto.h

417

uint8_t rsvd4[8];

include/scsi/iscsi_proto.h

423

uint8_t rsvd5[12];

include/scsi/iscsi_proto.h

429

uint8_t opcode;

include/scsi/iscsi_proto.h

430

uint8_t flags;

include/scsi/iscsi_proto.h

431

uint8_t max_version; /* Max. version supported */

include/scsi/iscsi_proto.h

432

uint8_t min_version; /* Min. version supported */

include/scsi/iscsi_proto.h

433

uint8_t hlength;

include/scsi/iscsi_proto.h

434

uint8_t dlength[3];

include/scsi/iscsi_proto.h

435

uint8_t isid[6]; /* Initiator Session ID */

include/scsi/iscsi_proto.h

442

uint8_t rsvd5[16];

include/scsi/iscsi_proto.h

464

uint8_t opcode;

include/scsi/iscsi_proto.h

465

uint8_t flags;

include/scsi/iscsi_proto.h

466

uint8_t max_version; /* Max. version supported */

include/scsi/iscsi_proto.h

467

uint8_t active_version; /* Active version */

include/scsi/iscsi_proto.h

468

uint8_t hlength;

include/scsi/iscsi_proto.h

469

uint8_t dlength[3];

include/scsi/iscsi_proto.h

470

uint8_t isid[6]; /* Initiator Session ID */

include/scsi/iscsi_proto.h

477

uint8_t status_class; /* see Login RSP ststus classes below */

include/scsi/iscsi_proto.h

478

uint8_t status_detail; /* see Login RSP Status details below */

include/scsi/iscsi_proto.h

479

uint8_t rsvd4[10];

include/scsi/iscsi_proto.h

523

uint8_t opcode;

include/scsi/iscsi_proto.h

524

uint8_t flags;

include/scsi/iscsi_proto.h

525

uint8_t rsvd1[2];

include/scsi/iscsi_proto.h

526

uint8_t hlength;

include/scsi/iscsi_proto.h

527

uint8_t dlength[3];

include/scsi/iscsi_proto.h

528

uint8_t rsvd2[8];

include/scsi/iscsi_proto.h

531

uint8_t rsvd3[2];

include/scsi/iscsi_proto.h

534

uint8_t rsvd4[16];

include/scsi/iscsi_proto.h

549

uint8_t opcode;

include/scsi/iscsi_proto.h

550

uint8_t flags;

include/scsi/iscsi_proto.h

551

uint8_t response; /* see Logout response values below */

include/scsi/iscsi_proto.h

552

uint8_t rsvd2;

include/scsi/iscsi_proto.h

553

uint8_t hlength;

include/scsi/iscsi_proto.h

554

uint8_t dlength[3];

include/scsi/iscsi_proto.h

555

uint8_t rsvd3[8];

include/scsi/iscsi_proto.h

576

uint8_t opcode;

include/scsi/iscsi_proto.h

577

uint8_t flags;

include/scsi/iscsi_proto.h

578

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

579

uint8_t hlength;

include/scsi/iscsi_proto.h

580

uint8_t dlength[3];

include/scsi/iscsi_proto.h

581

uint8_t lun[8];

include/scsi/iscsi_proto.h

584

uint8_t rsvd3[4];

include/scsi/iscsi_proto.h

586

uint8_t rsvd4[8];

include/scsi/iscsi_proto.h

601

uint8_t opcode;

include/scsi/iscsi_proto.h

602

uint8_t flags;

include/scsi/iscsi_proto.h

603

uint8_t reason;

include/scsi/iscsi_proto.h

604

uint8_t rsvd2;

include/scsi/iscsi_proto.h

605

uint8_t hlength;

include/scsi/iscsi_proto.h

606

uint8_t dlength[3];

include/scsi/iscsi_proto.h

607

uint8_t rsvd3[8];

include/scsi/iscsi_proto.h

609

uint8_t rsvd4[4];

include/scsi/iscsi_proto.h

614

uint8_t rsvd5[8];

include/scsi/iscsi_proto.h

77

uint8_t opcode;

include/scsi/iscsi_proto.h

78

uint8_t flags; /* Final bit */

include/scsi/iscsi_proto.h

79

uint8_t rsvd2[2];

include/scsi/iscsi_proto.h

80

uint8_t hlength; /* AHSs total length */

include/scsi/iscsi_proto.h

81

uint8_t dlength[3]; /* Data length */

include/scsi/iscsi_proto.h

88

uint8_t other[12];

include/scsi/libiscsi.h

233

uint8_t tcp_timestamp_stat;

include/scsi/libiscsi.h

234

uint8_t tcp_nagle_disable;

include/scsi/libiscsi.h

235

uint8_t tcp_wsf_disable;

include/scsi/libiscsi.h

236

uint8_t tcp_timer_scale;

include/scsi/libiscsi.h

237

uint8_t tcp_timestamp_en;

include/scsi/libiscsi.h

238

uint8_t fragment_disable;

include/scsi/libiscsi.h

239

uint8_t ipv4_tos;

include/scsi/libiscsi.h

240

uint8_t ipv6_traffic_class;

include/scsi/libiscsi.h

241

uint8_t ipv6_flow_label;

include/scsi/libiscsi.h

242

uint8_t is_fw_assigned_ipv6;

include/scsi/libiscsi.h

333

uint8_t auto_snd_tgt_disable;

include/scsi/libiscsi.h

334

uint8_t discovery_sess;

include/scsi/libiscsi.h

335

uint8_t chap_auth_en;

include/scsi/libiscsi.h

336

uint8_t discovery_logout_en;

include/scsi/libiscsi.h

337

uint8_t bidi_chap_en;

include/scsi/libiscsi.h

338

uint8_t discovery_auth_optional;

include/scsi/libiscsi.h

339

uint8_t isid[ISID_SIZE];

include/scsi/scsi_transport_iscsi.h

114

int (*alloc_pdu) (struct iscsi_task *task, uint8_t opcode);

include/scsi/scsi_transport_iscsi.h

185

uint8_t *data);

include/scsi/scsi_transport_iscsi.h

190

uint32_t data_size, uint8_t *data);

include/scsi/scsi_transport_iscsi.h

349

uint8_t snack_req_en;

include/scsi/scsi_transport_iscsi.h

351

uint8_t tcp_timestamp_stat;

include/scsi/scsi_transport_iscsi.h

352

uint8_t tcp_nagle_disable;

include/scsi/scsi_transport_iscsi.h

354

uint8_t tcp_wsf_disable;

include/scsi/scsi_transport_iscsi.h

355

uint8_t tcp_timer_scale;

include/scsi/scsi_transport_iscsi.h

356

uint8_t tcp_timestamp_en;

include/scsi/scsi_transport_iscsi.h

357

uint8_t ipv4_tos;

include/scsi/scsi_transport_iscsi.h

358

uint8_t ipv6_traffic_class;

include/scsi/scsi_transport_iscsi.h

359

uint8_t ipv6_flow_label;

include/scsi/scsi_transport_iscsi.h

360

uint8_t fragment_disable;

include/scsi/scsi_transport_iscsi.h

362

uint8_t is_fw_assigned_ipv6;

include/scsi/scsi_transport_iscsi.h

411

uint8_t auto_snd_tgt_disable;

include/scsi/scsi_transport_iscsi.h

412

uint8_t discovery_sess;

include/scsi/scsi_transport_iscsi.h

414

uint8_t entry_state;

include/scsi/scsi_transport_iscsi.h

415

uint8_t chap_auth_en;

include/scsi/scsi_transport_iscsi.h

419

uint8_t discovery_logout_en;

include/scsi/scsi_transport_iscsi.h

420

uint8_t bidi_chap_en;

include/scsi/scsi_transport_iscsi.h

422

uint8_t discovery_auth_optional;

include/scsi/scsi_transport_iscsi.h

423

uint8_t isid[ISID_SIZE];

include/scsi/scsi_transport_iscsi.h

424

uint8_t is_boot_target;

include/soc/tegra/bpmp-abi.h

1013

uint8_t data[];

include/soc/tegra/bpmp-abi.h

1037

uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE];

include/soc/tegra/bpmp-abi.h

1051

uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE];

include/soc/tegra/bpmp-abi.h

1247

uint8_t num_parents;

include/soc/tegra/bpmp-abi.h

1248

uint8_t reserved[3];

include/soc/tegra/bpmp-abi.h

1258

uint8_t num_parents;

include/soc/tegra/bpmp-abi.h

1262

uint8_t parent_idx;

include/soc/tegra/bpmp-abi.h

1279

uint8_t num_parents;

include/soc/tegra/bpmp-abi.h

1280

uint8_t name[MRQ_CLK_NAME_MAXLEN];

include/soc/tegra/bpmp-abi.h

1598

uint8_t name[MRQ_PG_NAME_MAXLEN];

include/soc/tegra/bpmp-abi.h

1932

uint8_t throt_en[OC_STATUS_MAX_SIZE];

include/soc/tegra/bpmp-abi.h

2398

uint8_t floor_unit;

include/soc/tegra/bpmp-abi.h

2816

uint8_t len;

include/soc/tegra/bpmp-abi.h

2825

uint8_t data[MRQ_RINGBUF_CONSOLE_MAX_READ_LEN];

include/soc/tegra/bpmp-abi.h

2827

uint8_t len;

include/soc/tegra/bpmp-abi.h

2836

uint8_t data[MRQ_RINGBUF_CONSOLE_MAX_WRITE_LEN];

include/soc/tegra/bpmp-abi.h

2838

uint8_t len;

include/soc/tegra/bpmp-abi.h

2849

uint8_t len;

include/soc/tegra/bpmp-abi.h

3001

uint8_t ep_controller;

include/soc/tegra/bpmp-abi.h

3006

uint8_t pcie_controller;

include/soc/tegra/bpmp-abi.h

3007

uint8_t enable;

include/soc/tegra/bpmp-abi.h

3012

uint8_t ep_controller;

include/soc/tegra/bpmp-abi.h

517

uint8_t tag[32];

include/sound/hdmi-codec.h

101

uint8_t *buf, size_t len);

include/sound/sof/dai.h

103

uint8_t group_id; /**< group ID, 0 means no group (ABI 3.17) */

include/sound/sof/dai.h

104

uint8_t flags; /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */

include/sound/sof/ext_manifest4.h

71

uint8_t name[MAX_FW_BINARY_NAME];

include/sound/sof/ext_manifest4.h

95

uint8_t name[MAX_MODULE_NAME_LEN];

include/sound/sof/ext_manifest4.h

98

uint8_t hash[DEFAULT_HASH_SHA256_LEN];

include/sound/sof/info.h

121

uint8_t name[16]; /* null terminated compiler name */

include/sound/sof/info.h

122

uint8_t optim[4]; /* null terminated compiler -O flag value */

include/sound/sof/info.h

123

uint8_t desc[32]; /* null terminated compiler description */

include/sound/sof/info.h

50

uint8_t date[12];

include/sound/sof/info.h

51

uint8_t time[10];

include/sound/sof/info.h

52

uint8_t tag[6];

include/sound/sof/ipc4/header.h

577

uint8_t event_data[];

include/sound/sof/stream.h

88

uint8_t cont_update_posn; /**< 1 means continuous update stream position */

include/sound/sof/stream.h

89

uint8_t reserved0;

include/sound/sof/stream.h

91

uint8_t reserved[2];

include/sound/sof/stream.h

93

uint8_t ext_data[]; /**< extended data */

include/sound/sof/trace.h

103

uint8_t filename[SOF_TRACE_FILENAME_SIZE];

include/trace/events/dlm.h

341

__field(uint8_t, h_cmd)

include/trace/events/dlm.h

405

__field(uint8_t, h_cmd)

include/trace/events/dlm.h

502

__field(uint8_t, h_cmd)

include/trace/events/dlm.h

588

__field(uint8_t, optype)

include/trace/events/dlm.h

589

__field(uint8_t, ex)

include/trace/events/dlm.h

590

__field(uint8_t, wait)

include/trace/events/dlm.h

591

__field(uint8_t, flags)

include/uapi/drm/drm.h

56

typedef uint8_t __u8;

include/uapi/linux/fuse.h

1308

uint8_t padding[6];

include/uapi/linux/sctp.h

1199

uint8_t se_on;

include/uapi/linux/sctp.h

980

uint8_t gauth_chunks[];

include/xen/interface/event_channel.h

204

uint8_t link_bits;

include/xen/interface/event_channel.h

205

uint8_t _pad[7];

include/xen/interface/hvm/hvm_op.h

61

uint8_t vector;

include/xen/interface/hvm/ioreq.h

42

uint8_t state:4;

include/xen/interface/hvm/ioreq.h

43

uint8_t data_is_ptr:1; /* if 1, data above is the guest paddr

include/xen/interface/hvm/ioreq.h

45

uint8_t dir:1; /* 1=read, 0=write */

include/xen/interface/hvm/ioreq.h

46

uint8_t df:1;

include/xen/interface/hvm/ioreq.h

47

uint8_t _pad1:1;

include/xen/interface/hvm/ioreq.h

48

uint8_t type; /* I/O type */

include/xen/interface/io/blkif.h

191

uint8_t first_sect, last_sect;

include/xen/interface/io/blkif.h

195

uint8_t nr_segments; /* number of segments */

include/xen/interface/io/blkif.h

206

uint8_t flag; /* BLKIF_DISCARD_SECURE or zero. */

include/xen/interface/io/blkif.h

215

uint8_t _pad3;

include/xen/interface/io/blkif.h

219

uint8_t _pad1;

include/xen/interface/io/blkif.h

228

uint8_t indirect_op;

include/xen/interface/io/blkif.h

246

uint8_t operation; /* BLKIF_OP_??? */

include/xen/interface/io/blkif.h

257

uint8_t operation; /* copied from request */

include/xen/interface/io/displif.h

862

uint8_t operation;

include/xen/interface/io/displif.h

863

uint8_t reserved[5];

include/xen/interface/io/displif.h

872

uint8_t reserved[56];

include/xen/interface/io/displif.h

878

uint8_t operation;

include/xen/interface/io/displif.h

879

uint8_t reserved;

include/xen/interface/io/displif.h

883

uint8_t reserved1[56];

include/xen/interface/io/displif.h

889

uint8_t type;

include/xen/interface/io/displif.h

890

uint8_t reserved[5];

include/xen/interface/io/displif.h

893

uint8_t reserved[56];

include/xen/interface/io/displif.h

918

uint8_t reserved[56];

include/xen/interface/io/fbif.h

28

uint8_t type; /* XENFB_TYPE_UPDATE */

include/xen/interface/io/fbif.h

42

uint8_t type; /* XENFB_TYPE_RESIZE */

include/xen/interface/io/fbif.h

53

uint8_t type;

include/xen/interface/io/fbif.h

69

uint8_t type;

include/xen/interface/io/fbif.h

99

uint8_t depth; /* depth of a pixel (in bits) */

include/xen/interface/io/kbdif.h

254

uint8_t type;

include/xen/interface/io/kbdif.h

280

uint8_t type;

include/xen/interface/io/kbdif.h

281

uint8_t pressed;

include/xen/interface/io/kbdif.h

310

uint8_t type;

include/xen/interface/io/kbdif.h

463

uint8_t type; /* XENKBD_TYPE_MTOUCH */

include/xen/interface/io/kbdif.h

464

uint8_t event_type; /* XENKBD_MT_EV_??? */

include/xen/interface/io/kbdif.h

465

uint8_t contact_id;

include/xen/interface/io/kbdif.h

466

uint8_t reserved[5]; /* reserved for the future use */

include/xen/interface/io/kbdif.h

483

uint8_t type;

include/xen/interface/io/kbdif.h

512

uint8_t type;

include/xen/interface/io/netif.h

283

static uint32_t xen_netif_toeplitz_hash(const uint8_t *key,

include/xen/interface/io/netif.h

285

const uint8_t *buf, unsigned int buflen)

include/xen/interface/io/netif.h

298

uint8_t byte = buf[bufi];

include/xen/interface/io/netif.h

862

uint8_t type;

include/xen/interface/io/netif.h

863

uint8_t flags;

include/xen/interface/io/netif.h

867

uint8_t type;

include/xen/interface/io/netif.h

868

uint8_t pad;

include/xen/interface/io/netif.h

872

uint8_t addr[6];

include/xen/interface/io/netif.h

875

uint8_t type;

include/xen/interface/io/netif.h

876

uint8_t algorithm;

include/xen/interface/io/netif.h

877

uint8_t value[4];

include/xen/interface/io/pvcalls.h

115

uint8_t dummy[8];

include/xen/interface/io/pvcalls.h

20

uint8_t pad1[52];

include/xen/interface/io/pvcalls.h

24

uint8_t pad2[52];

include/xen/interface/io/pvcalls.h

51

uint8_t addr[28];

include/xen/interface/io/pvcalls.h

59

uint8_t reuse;

include/xen/interface/io/pvcalls.h

63

uint8_t addr[28];

include/xen/interface/io/pvcalls.h

82

uint8_t dummy[56];

include/xen/interface/io/ring.h

436

uint8_t pad1[56]; \

include/xen/interface/io/ring.h

440

uint8_t pad2[56]; \

include/xen/interface/io/ring.h

97

uint8_t __pad[48]; \

include/xen/interface/io/sndif.h

1000

uint8_t reserved[5];

include/xen/interface/io/sndif.h

1006

uint8_t reserved[56];

include/xen/interface/io/sndif.h

1012

uint8_t operation;

include/xen/interface/io/sndif.h

1013

uint8_t reserved;

include/xen/interface/io/sndif.h

1017

uint8_t reserved1[56];

include/xen/interface/io/sndif.h

1023

uint8_t type;

include/xen/interface/io/sndif.h

1024

uint8_t reserved[5];

include/xen/interface/io/sndif.h

1027

uint8_t reserved[56];

include/xen/interface/io/sndif.h

1052

uint8_t reserved[56];

include/xen/interface/io/sndif.h

622

uint8_t pcm_format;

include/xen/interface/io/sndif.h

623

uint8_t pcm_channels;

include/xen/interface/io/sndif.h

813

uint8_t type;

include/xen/interface/io/sndif.h

999

uint8_t operation;

include/xen/interface/io/tpmif.h

44

uint8_t state; /* enum vtpm_shared_page_state */

include/xen/interface/io/tpmif.h

45

uint8_t locality; /* for the current request */

include/xen/interface/io/tpmif.h

46

uint8_t pad;

include/xen/interface/io/tpmif.h

48

uint8_t nr_extra_pages; /* extra pages for long packets; may be zero */

include/xen/interface/io/usbif.h

342

uint8_t ctrl[8]; /* setup_packet (Ctrl) */

include/xen/interface/io/usbif.h

394

uint8_t portnum; /* port number */

include/xen/interface/io/usbif.h

395

uint8_t speed; /* usb_device_speed */

include/xen/interface/io/vscsiif.h

248

uint8_t act; /* command between backend and frontend */

include/xen/interface/io/vscsiif.h

249

uint8_t cmd_len; /* valid CDB bytes */

include/xen/interface/io/vscsiif.h

251

uint8_t cmnd[VSCSIIF_MAX_COMMAND_SIZE]; /* the CDB */

include/xen/interface/io/vscsiif.h

255

uint8_t sc_data_direction; /* for DMA_TO_DEVICE(1)

include/xen/interface/io/vscsiif.h

258

uint8_t nr_segments; /* Number of pieces of scatter-gather */

include/xen/interface/io/vscsiif.h

274

uint8_t padding;

include/xen/interface/io/vscsiif.h

275

uint8_t sense_len;

include/xen/interface/io/vscsiif.h

276

uint8_t sense_buffer[VSCSIIF_SENSE_BUFFERSIZE];

include/xen/interface/physdev.h

153

uint8_t bus;

include/xen/interface/physdev.h

154

uint8_t devfn;

include/xen/interface/physdev.h

160

uint8_t bus;

include/xen/interface/physdev.h

161

uint8_t devfn;

include/xen/interface/physdev.h

167

uint8_t bus;

include/xen/interface/physdev.h

168

uint8_t devfn;

include/xen/interface/physdev.h

172

uint8_t bus;

include/xen/interface/physdev.h

173

uint8_t devfn;

include/xen/interface/physdev.h

196

uint8_t triggering;

include/xen/interface/physdev.h

198

uint8_t polarity;

include/xen/interface/physdev.h

228

uint8_t start_bus;

include/xen/interface/physdev.h

229

uint8_t end_bus;

include/xen/interface/physdev.h

237

uint8_t bus;

include/xen/interface/physdev.h

238

uint8_t devfn;

include/xen/interface/physdev.h

241

uint8_t bus;

include/xen/interface/physdev.h

242

uint8_t devfn;

include/xen/interface/physdev.h

269

uint8_t bus;

include/xen/interface/physdev.h

270

uint8_t devfn;

include/xen/interface/physdev.h

292

uint8_t op;

include/xen/interface/physdev.h

293

uint8_t bus;

include/xen/interface/physdev.h

81

uint8_t * bitmap;

include/xen/interface/platform.h

130

uint8_t month;

include/xen/interface/platform.h

131

uint8_t day;

include/xen/interface/platform.h

132

uint8_t hour;

include/xen/interface/platform.h

133

uint8_t min;

include/xen/interface/platform.h

134

uint8_t sec;

include/xen/interface/platform.h

137

uint8_t daylight;

include/xen/interface/platform.h

164

uint8_t data4[8];

include/xen/interface/platform.h

218

uint8_t device; /* %dl: bios device number */

include/xen/interface/platform.h

219

uint8_t version; /* %ah: major version */

include/xen/interface/platform.h

223

uint8_t legacy_max_head; /* %dh: max head # */

include/xen/interface/platform.h

224

uint8_t legacy_sectors_per_track; /* %cl[5:0]: max sector # */

include/xen/interface/platform.h

230

uint8_t device; /* bios device number */

include/xen/interface/platform.h

235

uint8_t capabilities;

include/xen/interface/platform.h

236

uint8_t edid_transfer_time;

include/xen/interface/platform.h

261

uint8_t kbd_shift_flags; /* XEN_FW_KBD_SHIFT_FLAGS */

include/xen/interface/platform.h

345

uint8_t type; /* cstate value, c0: 0, c1: 1, ... */

include/xen/interface/platform.h

368

uint8_t descriptor;

include/xen/interface/platform.h

370

uint8_t space_id;

include/xen/interface/platform.h

371

uint8_t bit_width;

include/xen/interface/platform.h

372

uint8_t bit_offset;

include/xen/interface/platform.h

373

uint8_t reserved;

include/xen/interface/platform.h

512

uint8_t pad[128];

include/xen/interface/xen-mca.h

167

uint8_t action_flags;

include/xen/interface/xen-mca.h

168

uint8_t action_types;

include/xen/interface/xen-mca.h

172

uint8_t pad[MAX_UNION_SIZE];

include/xen/interface/xen-mca.h

231

((struct mcinfo_common *)((uint8_t *)(_mic) + (_mic)->size))

include/xen/interface/xen.h

531

uint8_t evtchn_upcall_pending;

include/xen/interface/xen.h

532

uint8_t evtchn_upcall_mask;

include/xen/interface/xen.h

690

uint8_t video_type;

include/xen/interface/xen.h

716

uint8_t red_pos, red_size;

include/xen/interface/xen.h

717

uint8_t green_pos, green_size;

include/xen/interface/xen.h

718

uint8_t blue_pos, blue_size;

include/xen/interface/xen.h

719

uint8_t rsvd_pos, rsvd_size;

include/xen/interface/xen.h

734

typedef uint8_t xen_domain_handle_t[16];

include/xen/interface/xenpmu.h

89

uint8_t pad[6];

lib/bch.c

1009

int bch_decode(struct bch_control *bch, const uint8_t *data, unsigned int len,

lib/bch.c

1010

const uint8_t *recv_ecc, const uint8_t *calc_ecc,

lib/bch.c

153

const uint8_t *src)

lib/bch.c

155

uint8_t pad[4] = {0, 0, 0, 0};

lib/bch.c

174

static void store_ecc8(struct bch_control *bch, uint8_t *dst,

lib/bch.c

177

uint8_t pad[4];

lib/bch.c

207

void bch_encode(struct bch_control *bch, const uint8_t *data,

lib/bch.c

208

unsigned int len, uint8_t *ecc)

lib/crc/crc4.c

10

static const uint8_t crc4_tab[] = {

lib/crc/crc4.c

26

uint8_t crc4(uint8_t c, uint64_t x, int bits)

lib/crypto/mpi/mpicoder.c

144

int mpi_read_buffer(MPI a, uint8_t *buf, unsigned buf_len, unsigned *nbytes,

lib/crypto/mpi/mpicoder.c

147

uint8_t *p;

lib/crypto/mpi/mpicoder.c

206

uint8_t *buf;

lib/crypto/mpi/mpicoder.c

38

const uint8_t *buffer = xbuffer;

lib/crypto/mpi/mpicoder.c

84

const uint8_t *buffer = xbuffer;

lib/crypto/powerpc/curve25519.h

109

static void curve25519_fe51(uint8_t out[32], const uint8_t scalar[32],

lib/crypto/powerpc/curve25519.h

110

const uint8_t point[32])

lib/crypto/powerpc/curve25519.h

113

uint8_t s[32];

lib/crypto/powerpc/curve25519.h

23

asmlinkage void x25519_fe51_frombytes(fe51 h, const uint8_t *s);

lib/crypto/powerpc/curve25519.h

24

asmlinkage void x25519_fe51_tobytes(uint8_t *s, const fe51 h);

lib/crypto/powerpc/curve25519.h

58

static void fe51_frombytes(fe51 h, const uint8_t *s)

lib/decompress_unlzma.c

111

rc->buffer = (uint8_t *)buffer;

lib/decompress_unlzma.c

224

uint8_t pos;

lib/decompress_unlzma.c

280

uint8_t *buffer;

lib/decompress_unlzma.c

281

uint8_t previous_byte;

lib/decompress_unlzma.c

300

static inline uint8_t INIT peek_old_byte(struct writer *wr,

lib/decompress_unlzma.c

318

static inline int INIT write_byte(struct writer *wr, uint8_t byte)

lib/decompress_unlzma.c

71

uint8_t *ptr;

lib/decompress_unlzma.c

72

uint8_t *buffer;

lib/decompress_unlzma.c

73

uint8_t *buffer_end;

lib/decompress_unxz.c

186

const uint8_t *x = a;

lib/decompress_unxz.c

187

const uint8_t *y = b;

lib/decompress_unxz.c

201

uint8_t *b = buf;

lib/decompress_unxz.c

202

uint8_t *e = b + size;

lib/decompress_unxz.c

213

uint8_t *d = dest;

lib/decompress_unxz.c

214

const uint8_t *s = src;

lib/digsig.c

75

uint8_t *p, *datap;

lib/digsig.c

76

const uint8_t *endp;

lib/lz4/lz4defs.h

51

typedef uint8_t BYTE;

lib/raid6/mktables.c

21

static uint8_t gfmul(uint8_t a, uint8_t b)

lib/raid6/mktables.c

23

uint8_t v = 0;

lib/raid6/mktables.c

35

static uint8_t gfpow(uint8_t a, int b)

lib/raid6/mktables.c

37

uint8_t v = 1;

lib/raid6/mktables.c

56

uint8_t v;

lib/raid6/mktables.c

57

uint8_t exptbl[256], invtbl[256];

lib/raid6/neon.h

15

void __raid6_2data_recov_neon(int bytes, uint8_t *p, uint8_t *q, uint8_t *dp,

lib/raid6/neon.h

16

uint8_t *dq, const uint8_t *pbmul,

lib/raid6/neon.h

17

const uint8_t *qmul);

lib/raid6/neon.h

19

void __raid6_datap_recov_neon(int bytes, uint8_t *p, uint8_t *q, uint8_t *dq,

lib/raid6/neon.h

20

const uint8_t *qmul);

lib/raid6/recov_neon_inner.c

28

void __raid6_2data_recov_neon(int bytes, uint8_t *p, uint8_t *q, uint8_t *dp,

lib/raid6/recov_neon_inner.c

29

uint8_t *dq, const uint8_t *pbmul,

lib/raid6/recov_neon_inner.c

30

const uint8_t *qmul)

lib/raid6/recov_neon_inner.c

78

void __raid6_datap_recov_neon(int bytes, uint8_t *p, uint8_t *q, uint8_t *dq,

lib/raid6/recov_neon_inner.c

79

const uint8_t *qmul)

lib/reed_solomon/reed_solomon.c

328

int encode_rs8(struct rs_control *rsc, uint8_t *data, int len, uint16_t *par,

lib/reed_solomon/reed_solomon.c

361

int decode_rs8(struct rs_control *rsc, uint8_t *data, uint16_t *par, int len,

lib/xxhash.c

159

const uint8_t *p = (const uint8_t *)input;

lib/xxhash.c

160

const uint8_t *const b_end = p + len;

lib/xxhash.c

164

const uint8_t *const limit = b_end - 32;

lib/xxhash.c

243

const uint8_t *p = (const uint8_t *)input;

lib/xxhash.c

244

const uint8_t *const b_end = p + len;

lib/xxhash.c

252

memcpy(((uint8_t *)state->mem64) + state->memsize, input, len);

lib/xxhash.c

260

memcpy(((uint8_t *)p64) + state->memsize, input,

lib/xxhash.c

276

const uint8_t *const limit = b_end - 32;

lib/xxhash.c

310

const uint8_t *p = (const uint8_t *)state->mem64;

lib/xxhash.c

311

const uint8_t *const b_end = (const uint8_t *)state->mem64 +

lib/xxhash.c

89

const uint8_t *p = (const uint8_t *)input;

lib/xxhash.c

90

const uint8_t *b_end = p + len;

lib/xxhash.c

94

const uint8_t *const limit = b_end - 16;

lib/xz/xz_crc32.c

48

uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc)

lib/xz/xz_dec_bcj.c

101

uint8_t b;

lib/xz/xz_dec_bcj.c

137

b = (uint8_t)(dest >> (24 - j));

lib/xz/xz_dec_bcj.c

160

static size_t bcj_powerpc(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

183

static size_t bcj_arm(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

197

buf[i] = (uint8_t)addr;

lib/xz/xz_dec_bcj.c

198

buf[i + 1] = (uint8_t)(addr >> 8);

lib/xz/xz_dec_bcj.c

199

buf[i + 2] = (uint8_t)(addr >> 16);

lib/xz/xz_dec_bcj.c

208

static size_t bcj_armthumb(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

228

buf[i + 1] = (uint8_t)(0xF0 | ((addr >> 19) & 0x07));

lib/xz/xz_dec_bcj.c

229

buf[i] = (uint8_t)(addr >> 11);

lib/xz/xz_dec_bcj.c

230

buf[i + 3] = (uint8_t)(0xF8 | ((addr >> 8) & 0x07));

lib/xz/xz_dec_bcj.c

231

buf[i + 2] = (uint8_t)addr;

lib/xz/xz_dec_bcj.c

241

static size_t bcj_sparc(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

265

static size_t bcj_arm64(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

306

static size_t bcj_riscv(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

337

buf[i + 1] = (uint8_t)((b1 & 0x0F)

lib/xz/xz_dec_bcj.c

340

buf[i + 2] = (uint8_t)(((addr >> 16) & 0x0F)

lib/xz/xz_dec_bcj.c

344

buf[i + 3] = (uint8_t)(((addr >> 4) & 0x7F)

lib/xz/xz_dec_bcj.c

407

uint8_t *buf, size_t *pos, size_t size)

lib/xz/xz_dec_bcj.c

51

uint8_t *out;

lib/xz/xz_dec_bcj.c

601

enum xz_ret xz_dec_bcj_reset(struct xz_dec_bcj *s, uint8_t id)

lib/xz/xz_dec_bcj.c

74

uint8_t buf[16];

lib/xz/xz_dec_bcj.c

83

static inline int bcj_x86_test_msbyte(uint8_t b)

lib/xz/xz_dec_bcj.c

88

static size_t bcj_x86(struct xz_dec_bcj *s, uint8_t *buf, size_t size)

lib/xz/xz_dec_bcj.c

93

static const uint8_t mask_to_bit_num[8] = { 0, 1, 2, 2, 3, 3, 3, 3 };

lib/xz/xz_dec_lzma2.c

108

const uint8_t *in;

lib/xz/xz_dec_lzma2.c

1162

enum xz_ret xz_dec_lzma2_reset(struct xz_dec_lzma2 *s, uint8_t props)

lib/xz/xz_dec_lzma2.c

277

uint8_t buf[3 * LZMA_IN_REQUIRED];

lib/xz/xz_dec_lzma2.c

336

static inline void dict_put(struct dictionary *dict, uint8_t byte)

lib/xz/xz_dec_lzma2.c

45

uint8_t *buf;

lib/xz/xz_dec_lzma2.c

645

dict_put(&s->dict, (uint8_t)symbol);

lib/xz/xz_dec_lzma2.c

831

static bool lzma_props(struct xz_dec_lzma2 *s, uint8_t props)

lib/xz/xz_dec_stream.c

127

uint8_t buf[1024];

lib/xz/xz_dec_stream.c

140

static const uint8_t check_sizes[16] = {

lib/xz/xz_dec_stream.c

174

static enum xz_ret dec_vli(struct xz_dec *s, const uint8_t *in,

lib/xz/xz_dec_stream.c

177

uint8_t byte;

lib/xz/xz_dec_stream.c

270

(const uint8_t *)&s->block.hash,

lib/xz/xz_dec_stream.c

329

(const uint8_t *)&s->index.hash,

lib/xz/xz_dec_test.c

44

static uint8_t buffer_in[1024];

lib/xz/xz_dec_test.c

45

static uint8_t buffer_out[1024];

lib/xz/xz_private.h

122

enum xz_ret xz_dec_lzma2_reset(struct xz_dec_lzma2 *s, uint8_t props);

lib/xz/xz_private.h

143

enum xz_ret xz_dec_bcj_reset(struct xz_dec_bcj *s, uint8_t id);

lib/zlib_dfltcc/dfltcc.h

40

uint8_t mvn; /* Model-Version Number */

lib/zlib_dfltcc/dfltcc.h

41

uint8_t ribm; /* Reserved for IBM use */

lib/zlib_dfltcc/dfltcc.h

44

uint8_t reserved64[8];

lib/zlib_dfltcc/dfltcc.h

59

uint8_t oesc; /* Operation-Ending-Supplemental Code */

lib/zlib_dfltcc/dfltcc.h

63

uint8_t reserved192[8];

lib/zlib_dfltcc/dfltcc.h

64

uint8_t reserved256[8];

lib/zlib_dfltcc/dfltcc.h

65

uint8_t reserved320[4];

lib/zlib_dfltcc/dfltcc.h

72

uint8_t eobl : 4; /* End-of-block Length */

lib/zlib_dfltcc/dfltcc.h

77

uint8_t reserved464[6];

lib/zlib_dfltcc/dfltcc.h

78

uint8_t cdht[288];

lib/zlib_dfltcc/dfltcc.h

79

uint8_t reserved[32];

lib/zlib_dfltcc/dfltcc.h

80

uint8_t csb[1152];

lib/zstd/common/mem.h

33

typedef uint8_t BYTE;

lib/zstd/common/mem.h

34

typedef uint8_t U8;

lib/zstd/common/zstd_internal.h

166

vst1_u8((uint8_t*)dst, vld1_u8((const uint8_t*)src));

lib/zstd/common/zstd_internal.h

179

vst1q_u8((uint8_t*)dst, vld1q_u8((const uint8_t*)src));

mm/memcontrol.c

1797

uint8_t nr_pages[NR_MEMCG_STOCK];

mm/memcontrol.c

1844

uint8_t stock_pages;

mm/memcontrol.c

1884

uint8_t stock_pages;

mm/memcontrol.c

1943

uint8_t stock_pages;

mm/memory_hotplug.c

2328

uint8_t online_type = MMOP_ONLINE_KERNEL;

mm/memory_hotplug.c

2329

uint8_t **online_types = arg;

mm/memory_hotplug.c

2357

uint8_t **online_types = arg;

mm/memory_hotplug.c

2382

uint8_t *online_types, *tmp;

net/9p/trans_xen.c

29

uint8_t id;

net/atm/mpc.c

1342

uint8_t tlv[4 + 1 + 1 + 1 + ATM_ESA_LEN];

net/atm/mpc.c

379

uint8_t length, mpoa_device_type, number_of_mps_macs;

net/atm/mpc.c

380

const uint8_t *end_of_tlvs;

net/atm/mpc.c

464

static const uint8_t *copy_macs(struct mpoa_client *mpc,

net/atm/mpc.c

465

const uint8_t *router_mac,

net/atm/mpc.c

466

const uint8_t *tlvs, uint8_t mps_macs,

net/atm/mpc.c

467

uint8_t device_type)

net/atm/mpc.c

83

static const uint8_t *copy_macs(struct mpoa_client *mpc,

net/atm/mpc.c

84

const uint8_t *router_mac,

net/atm/mpc.c

85

const uint8_t *tlvs, uint8_t mps_macs,

net/atm/mpc.c

86

uint8_t device_type);

net/atm/mpc.h

21

uint8_t mps_ctrl_addr[ATM_ESA_LEN]; /* MPS control ATM address */

net/atm/mpc.h

22

uint8_t our_ctrl_addr[ATM_ESA_LEN]; /* MPC's control ATM address */

net/atm/mpc.h

32

uint8_t *mps_macs; /* array of MPS MAC addresses, >=1 */

net/atm/mpoa_caches.h

29

uint8_t MPS_ctrl_ATM_addr[ATM_ESA_LEN];

net/atm/mpoa_caches.h

58

uint8_t MPS_ctrl_ATM_addr[ATM_ESA_LEN];

net/batman-adv/bridge_loop_avoidance.h

27

static inline bool batadv_bla_is_loopdetect_mac(const uint8_t *mac)

net/bluetooth/hci_conn.c

1246

struct hci_dev *hci_get_route(bdaddr_t *dst, bdaddr_t *src, uint8_t src_type)

net/bluetooth/iso.c

703

bdaddr_t *dst, uint8_t big)

net/bluetooth/mgmt.c

5946

static bool discovery_type_is_valid(struct hci_dev *hdev, uint8_t type,

net/bluetooth/mgmt.c

5947

uint8_t *mgmt_status)

net/bluetooth/smp.c

172

uint8_t tmp[16], mac_msb[16], msg_msb[CMAC_MSG_MAX];

net/bluetooth/smp.c

378

uint8_t tmp[16], data[16];

net/bridge/netfilter/ebt_ip6.c

63

uint8_t nexthdr = ih6->nexthdr;

net/bridge/netfilter/ebt_log.c

118

uint8_t nexthdr;

net/bridge/netfilter/ebt_log.c

53

print_ports(const struct sk_buff *skb, uint8_t protocol, int offset)

net/bridge/netfilter/ebt_mark_m.c

43

uint8_t invert, bitmask;

net/can/j1939/main.c

65

skb_trim(skb, min_t(uint8_t, cf->len, 8));

net/dsa/user.c

1026

uint32_t stringset, uint8_t *data)

net/ieee802154/socket.c

745

sizeof(uint8_t), &(mac_cb(skb)->lqi));

net/ipv6/icmp.c

317

uint8_t type;

net/key/af_key.c

1728

hdr->sadb_msg_errno = (uint8_t) 0;

net/key/af_key.c

1749

hdr->sadb_msg_errno = (uint8_t) 0;

net/key/af_key.c

2770

hdr->sadb_msg_errno = (uint8_t) 0;

net/key/af_key.c

336

hdr->sadb_msg_errno = (uint8_t) err;

net/key/af_key.c

3520

uint8_t proto, uint8_t mode, int level,

net/key/af_key.c

52

uint8_t msg_version;

net/key/af_key.c

566

pfkey_satype2proto(uint8_t satype)

net/key/af_key.c

583

static uint8_t

net/key/af_key.c

603

static uint8_t pfkey_proto_to_xfrm(uint8_t proto)

net/key/af_key.c

608

static uint8_t pfkey_proto_from_xfrm(uint8_t proto)

net/mptcp/pm_netlink.c

434

void mptcp_event_addr_removed(const struct mptcp_sock *msk, uint8_t id)

net/netfilter/nf_conntrack_proto.c

606

void nf_ct_netns_put(struct net *net, uint8_t nfproto)

net/netfilter/nft_set_pipapo.c

990

static int pipapo_insert(struct nft_pipapo_field *f, const uint8_t *k,

net/netfilter/nft_tunnel.c

291

uint8_t hwid, dir;

net/netfilter/x_tables.c

1596

uint8_t class;

net/netfilter/x_tables.c

1609

static const uint8_t next_class[] = {

net/netfilter/x_tables.c

1613

uint8_t nfproto = (unsigned long)pde_data(file_inode(seq->file));

net/netfilter/x_tables.c

1662

uint8_t nfproto = (unsigned long)pde_data(file_inode(seq->file));

net/netfilter/x_tables.c

1761

uint8_t i, num_hooks = hweight32(hook_mask);

net/netfilter/x_tables.c

1762

uint8_t hooknum;

net/netfilter/x_tables.c

228

xt_request_find_match(uint8_t nfproto, const char *name, uint8_t revision)

net/netfilter/x_tables.c

417

textify_hooks(char *buf, size_t size, unsigned int mask, uint8_t nfproto)

net/rxrpc/protocol.h

119

uint8_t reason; /* reason for ACK */

net/rxrpc/protocol.h

131

uint8_t nAcks; /* number of ACKs */

net/rxrpc/protocol.h

134

uint8_t acks[]; /* list of ACK/NAKs */

net/rxrpc/protocol.h

36

uint8_t type; /* packet type */

net/rxrpc/protocol.h

50

uint8_t flags; /* packet flags */

net/rxrpc/protocol.h

58

uint8_t userStatus; /* app-layer defined status */

net/rxrpc/protocol.h

61

uint8_t securityIndex; /* security protocol ID */

net/rxrpc/protocol.h

81

uint8_t flags; /* packet flags (as per rxrpc_header) */

net/rxrpc/protocol.h

82

uint8_t pad;

net/smc/smc_ism.h

107

memcpy(&temp, (uint8_t *)dibs_gid + sizeof(sgid->gid),

net/smc/smc_ism.h

119

memcpy((uint8_t *)dibs_gid + sizeof(sgid->gid), &temp,

net/wireless/radiotap.c

118

iterator->_arg = (uint8_t *)radiotap_header->it_optional;

net/wireless/radiotap.c

167

uint32_t oui, uint8_t subns)

net/wireless/util.c

853

uint8_t flags;

samples/bpf/test_lwt_bpf.c

88

uint8_t proto;

samples/mei/mei-amt-version.c

255

uint8_t major;

samples/mei/mei-amt-version.c

256

uint8_t minor;

samples/mei/mei-amt-version.c

260

uint8_t bios[AMT_BIOS_VERSION_LEN];

samples/mei/mei-amt-version.c

378

uint8_t **read_buf, uint32_t rcmd,

samples/mei/mei-amt-version.c

388

*read_buf = (uint8_t *)malloc(sizeof(uint8_t) * in_buf_sz);

samples/mei/mei-amt-version.c

428

(uint8_t **)&response,

samples/vfio-mdev/mtty.c

1575

uint8_t mask = *(uint8_t *)data;

samples/vfio-mdev/mtty.c

1592

uint8_t mask = *(uint8_t *)data;

samples/vfio-mdev/mtty.c

1640

uint8_t trigger = *(uint8_t *)data;

samples/vfio-mdev/mtty.c

1694

uint8_t trigger = *(uint8_t *)data;

scripts/asn1_compiler.c

690

uint8_t n_elements;

scripts/asn1_compiler.c

694

uint8_t tag;

scripts/dtc/data.c

160

uint8_t value_8;

scripts/dtc/data.c

207

struct data data_append_byte(struct data d, uint8_t byte)

scripts/dtc/dtc-parser.y

37

uint8_t byte;

scripts/dtc/dtc.h

182

struct data data_append_byte(struct data d, uint8_t byte);

scripts/dtc/dtc.h

61

const uint8_t *bp = (const uint8_t *)p;

scripts/dtc/dtc.h

69

const uint8_t *bp = (const uint8_t *)p;

scripts/dtc/dtc.h

79

const uint8_t *bp = (const uint8_t *)p;

scripts/dtc/fdtget.c

56

const uint8_t *p = (const uint8_t *)data;

scripts/dtc/fdtput.c

104

*ptr = (uint8_t)ival;

scripts/dtc/libfdt/fdt_addresses.c

61

uint8_t data[sizeof(fdt64_t) * 2], *prop;

scripts/dtc/libfdt/libfdt.h

164

const uint8_t *bp = (const uint8_t *)p;

scripts/dtc/libfdt/libfdt.h

171

const uint8_t *bp = (const uint8_t *)p;

scripts/dtc/libfdt/libfdt.h

181

uint8_t *bp = (uint8_t *)property;

scripts/dtc/libfdt/libfdt.h

191

const uint8_t *bp = (const uint8_t *)p;

scripts/dtc/libfdt/libfdt.h

205

uint8_t *bp = (uint8_t *)property;

scripts/dtc/libfdt/libfdt_env.h

29

#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n])

scripts/dtc/treesource.c

110

fprintf(f, "%02"PRIx8, *(const uint8_t*)p);

scripts/dtc/yamltree.c

60

sprintf(buf, "0x%"PRIx8, *(uint8_t*)(data + off));

scripts/elf-parse.h

199

static inline uint8_t sym64_type(Elf_Sym *sym)

scripts/elf-parse.h

204

static inline uint8_t sym32_type(Elf_Sym *sym)

scripts/elf-parse.h

209

static inline uint8_t sym_type(Elf_Sym *sym)

scripts/elf-parse.h

43

uint8_t (*sym_type)(Elf_Sym *sym);

scripts/genksyms/genksyms.c

119

static uint32_t partial_crc32_one(uint8_t c, uint32_t crc)

scripts/insert-sys-cert.c

52

uint8_t low_address = *((uint8_t *)&two_byte);

scripts/mod/file2alias.c

1407

if (*(uint8_t *)(symval + i)) {

scripts/mod/modpost.c

1181

uint8_t shift = 31 - index;

scripts/recordmcount.c

486

typedef uint8_t myElf64_Byte; /* Type for a 8-bit quantity. */

scripts/sign-file.c

44

uint8_t algo; /* Public-key crypto algorithm [0] */

scripts/sign-file.c

45

uint8_t hash; /* Digest algorithm [0] */

scripts/sign-file.c

46

uint8_t id_type; /* Key identifier type [PKEY_ID_PKCS7] */

scripts/sign-file.c

47

uint8_t signer_len; /* Length of signer's name [0] */

scripts/sign-file.c

48

uint8_t key_id_len; /* Length of key identifier [0] */

scripts/sign-file.c

49

uint8_t __pad[3];

security/integrity/evm/evm_crypto.c

225

uint8_t type, struct evm_digest *data,

security/integrity/evm/evm_crypto.c

75

static struct shash_desc *init_desc(char type, uint8_t hash_algo)

security/integrity/integrity.h

93

uint8_t type; /* xattr type */

security/integrity/integrity.h

94

uint8_t version; /* signature format version */

security/integrity/integrity.h

95

uint8_t hash_algo; /* Digest algorithm [enum hash_algo] */

security/integrity/integrity.h

98

uint8_t sig[]; /* signature payload */

security/keys/dh.c

136

uint8_t *secret;

security/keys/dh.c

137

uint8_t *outbuf;

security/keys/dh.c

39

uint8_t *duplicate;

security/keys/dh.c

96

uint8_t *kbuf, size_t kbuflen)

security/keys/dh.c

99

uint8_t *outbuf = NULL;

sound/pci/rme9652/hdspm.c

990

uint8_t io_type;

sound/soc/codecs/adau-utils.c

16

uint8_t regs[5])

sound/soc/codecs/adau-utils.h

6

uint8_t regs[5]);

sound/soc/codecs/adau1373.c

1276

uint8_t pll_regs[5];

sound/soc/codecs/adau1373.c

1347

unsigned int nr, uint8_t *drc)

sound/soc/codecs/adau1701.c

188

uint8_t buf[5];

sound/soc/codecs/adau1701.c

218

uint8_t send_buf[2], recv_buf[3];

sound/soc/codecs/adau1701.c

256

const uint8_t bytes[], size_t len)

sound/soc/codecs/adau1701.c

262

uint8_t buf[10];

sound/soc/codecs/adau17x1.c

1001

uint8_t buf[ADAU17X1_WORD_SIZE];

sound/soc/codecs/adau17x1.c

1002

uint8_t data[ADAU17X1_SAFELOAD_DATA_SIZE];

sound/soc/codecs/adau17x1.c

999

const uint8_t bytes[], size_t len)

sound/soc/codecs/adau17x1.h

46

uint8_t pll_regs[6];

sound/soc/codecs/aw88395/aw88395_lib.c

427

uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)

sound/soc/codecs/aw88395/aw88395_lib.c

856

(uint8_t *)prof_hdr + cfg_dde->data_offset,

sound/soc/codecs/cros_ec_codec.c

1003

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

1004

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

1014

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

121

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

122

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

130

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

131

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

162

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

170

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

202

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

203

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

251

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

265

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

319

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

351

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

394

uint8_t shm_id, uint32_t *len, uint8_t *type)

sound/soc/codecs/cros_ec_codec.c

403

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

404

(uint8_t *)&r, sizeof(r)) < 0) {

sound/soc/codecs/cros_ec_codec.c

441

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

513

uint8_t *addr, size_t len, bool iomem)

sound/soc/codecs/cros_ec_codec.c

54

uint8_t *wov_audio_shm_p;

sound/soc/codecs/cros_ec_codec.c

559

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

56

uint8_t wov_audio_shm_type;

sound/soc/codecs/cros_ec_codec.c

560

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

57

uint8_t *wov_lang_shm_p;

sound/soc/codecs/cros_ec_codec.c

584

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

585

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

59

uint8_t wov_lang_shm_type;

sound/soc/codecs/cros_ec_codec.c

62

uint8_t wov_buf[64000];

sound/soc/codecs/cros_ec_codec.c

657

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

671

uint8_t *buf, size_t size, uint8_t *digest)

sound/soc/codecs/cros_ec_codec.c

704

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

71

static int ec_codec_capable(struct cros_ec_codec_priv *priv, uint8_t cap)

sound/soc/codecs/cros_ec_codec.c

714

uint8_t *buf, size_t size, uint8_t *digest)

sound/soc/codecs/cros_ec_codec.c

731

(uint8_t *)&p, sizeof(p), NULL, 0);

sound/soc/codecs/cros_ec_codec.c

750

uint8_t digest[SHA256_DIGEST_SIZE];

sound/soc/codecs/cros_ec_codec.c

751

uint8_t *buf;

sound/soc/codecs/cros_ec_codec.c

769

(uint8_t *)&p, sizeof(p),

sound/soc/codecs/cros_ec_codec.c

77

uint8_t *out, size_t outsize,

sound/soc/codecs/cros_ec_codec.c

770

(uint8_t *)&r, sizeof(r));

sound/soc/codecs/cros_ec_codec.c

78

uint8_t *in, size_t insize)

sound/soc/codecs/cs4234.c

529

uint8_t dac5_masks[4];

sound/soc/codecs/cs4234.c

741

uint8_t ids[3];

sound/soc/codecs/hdac_hdmi.c

358

uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];

sound/soc/codecs/hdmi-codec.c

283

uint8_t eld[MAX_ELD_BYTES];

sound/soc/codecs/sigmadsp-i2c.c

17

unsigned int addr, const uint8_t data[], size_t len)

sound/soc/codecs/sigmadsp-i2c.c

19

uint8_t *buf;

sound/soc/codecs/sigmadsp-i2c.c

40

unsigned int addr, uint8_t data[], size_t len)

sound/soc/codecs/sigmadsp-i2c.c

44

uint8_t buf[2];

sound/soc/codecs/sigmadsp-regmap.c

15

unsigned int addr, const uint8_t data[], size_t len)

sound/soc/codecs/sigmadsp-regmap.c

22

unsigned int addr, uint8_t data[], size_t len)

sound/soc/codecs/sigmadsp.c

102

uint8_t data[], size_t len)

sound/soc/codecs/sigmadsp.c

135

uint8_t *data;

sound/soc/codecs/sigmadsp.c

38

uint8_t cache[];

sound/soc/codecs/sigmadsp.c

46

uint8_t data[] __counted_by(length);

sound/soc/codecs/sigmadsp.c

58

uint8_t data[];

sound/soc/codecs/sigmadsp.c

96

const uint8_t data[], size_t len)

sound/soc/codecs/sigmadsp.h

23

const uint8_t *data, size_t len);

sound/soc/codecs/sigmadsp.h

41

int (*write)(void *, unsigned int, const uint8_t *, size_t);

sound/soc/codecs/sigmadsp.h

42

int (*read)(void *, unsigned int, uint8_t *, size_t);

sound/soc/codecs/tas2764.c

549

static uint8_t sn012776_bop_presets[] = {

sound/soc/codecs/tas5086.c

169

uint8_t buf[5];

sound/soc/codecs/tas5086.c

196

uint8_t send_buf, recv_buf[4];

sound/soc/codecs/tas571x.c

107

uint8_t send_buf, recv_buf[4];

sound/soc/codecs/tas571x.c

149

uint8_t *buf, *p;

sound/soc/codecs/tas571x.c

180

uint8_t send_buf;

sound/soc/codecs/tas571x.c

181

uint8_t *recv_buf, *p;

sound/soc/codecs/tas571x.c

82

uint8_t buf[5];

sound/soc/codecs/tas5805m.c

161

uint8_t *dsp_cfg_data;

sound/soc/codecs/tas5805m.c

176

uint8_t v[4];

sound/soc/codecs/tas5805m.c

288

const uint8_t *s, unsigned int len)

sound/soc/codecs/tas5805m.c

64

static const uint8_t dsp_cfg_preboot[] = {

sound/soc/codecs/wm0010.c

46

uint8_t data[];

sound/soc/fsl/imx-audmux.c

175

static const uint8_t port_mapping[] = {

sound/soc/qcom/qdsp6/audioreach.c

139

ch * sizeof(uint8_t), 8)

sound/soc/qcom/qdsp6/audioreach.c

144

ch * sizeof(uint8_t), 8)

sound/soc/qcom/qdsp6/audioreach.h

147

uint8_t channel_mapping[];

sound/soc/qcom/qdsp6/audioreach.h

267

uint8_t version;

sound/soc/qcom/qdsp6/audioreach.h

268

uint8_t num_channels;

sound/soc/qcom/qdsp6/audioreach.h

272

uint8_t mapping_family;

sound/soc/qcom/qdsp6/audioreach.h

273

uint8_t stream_count;

sound/soc/qcom/qdsp6/audioreach.h

274

uint8_t coupled_count;

sound/soc/qcom/qdsp6/audioreach.h

275

uint8_t channel_mapping[8];

sound/soc/qcom/qdsp6/audioreach.h

276

uint8_t reserved[3];

sound/soc/qcom/qdsp6/audioreach.h

640

uint8_t channel_mapping[];

sound/soc/qcom/qdsp6/q6asm.c

191

uint8_t channel_mapping[8];

sound/soc/sof/ipc4-topology.h

286

uint8_t dma_method;

sound/soc/sof/ipc4-topology.h

287

uint8_t pre_allocated_by_host;

sound/soc/sof/ipc4-topology.h

293

uint8_t dma_priv_config[];

sound/soc/sof/ipc4-topology.h

391

DECLARE_FLEX_ARRAY(uint8_t, data);

sound/usb/midi.c

1021

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

1068

uint8_t *buf = urb->transfer_buffer;

sound/usb/midi.c

137

uint8_t cable; /* cable number << 4 */

sound/usb/midi.c

138

uint8_t state;

sound/usb/midi.c

146

uint8_t data[2];

sound/usb/midi.c

169

static const uint8_t snd_usbmidi_cin_length[] = {

sound/usb/midi.c

1802

static int find_usb_ijack(struct usb_host_interface *hostif, uint8_t jack_id)

sound/usb/midi.c

1849

uint8_t jack_name_buf[32];

sound/usb/midi.c

1850

uint8_t *default_jack_name = "MIDI";

sound/usb/midi.c

1851

uint8_t *jack_name = default_jack_name;

sound/usb/midi.c

1852

uint8_t iJack;

sound/usb/midi.c

1989

((uint8_t *)&ms_header->bcdMSC)[1], ((uint8_t *)&ms_header->bcdMSC)[0]);

sound/usb/midi.c

211

int portidx, uint8_t *data, int length)

sound/usb/midi.c

2211

uint8_t *cs_desc;

sound/usb/midi.c

383

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

397

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

415

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

455

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

490

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

541

uint8_t *tmp_buf = buffer + 2;

sound/usb/midi.c

568

static void snd_usbmidi_output_standard_packet(struct urb *urb, uint8_t p0,

sound/usb/midi.c

569

uint8_t p1, uint8_t p2,

sound/usb/midi.c

570

uint8_t p3)

sound/usb/midi.c

573

uint8_t *buf =

sound/usb/midi.c

574

(uint8_t *)urb->transfer_buffer + urb->transfer_buffer_length;

sound/usb/midi.c

585

static void snd_usbmidi_output_midiman_packet(struct urb *urb, uint8_t p0,

sound/usb/midi.c

586

uint8_t p1, uint8_t p2,

sound/usb/midi.c

587

uint8_t p3)

sound/usb/midi.c

590

uint8_t *buf =

sound/usb/midi.c

591

(uint8_t *)urb->transfer_buffer + urb->transfer_buffer_length;

sound/usb/midi.c

603

uint8_t b, struct urb *urb)

sound/usb/midi.c

605

uint8_t p0 = port->cable;

sound/usb/midi.c

606

void (*output_packet)(struct urb*, uint8_t, uint8_t, uint8_t, uint8_t) =

sound/usb/midi.c

710

uint8_t b;

sound/usb/midi.c

767

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

786

uint8_t *msg;

sound/usb/midi.c

788

uint8_t tmp[MAX_AKAI_SYSEX_LEN];

sound/usb/midi.c

857

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

86

void (*input)(struct snd_usb_midi_in_endpoint*, uint8_t*, int);

sound/usb/midi.c

867

uint8_t *transfer_buffer;

sound/usb/midi.c

88

void (*output_packet)(struct urb*, uint8_t, uint8_t, uint8_t, uint8_t);

sound/usb/midi.c

895

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

927

uint8_t *buffer, int buffer_length)

sound/usb/midi.c

939

uint8_t *buffer, int buffer_length)

sound/usb/midi.h

11

uint8_t out_interval; /* interval for interrupt endpoints */

sound/usb/midi.h

13

uint8_t in_interval;

sound/usb/mixer_scarlett2.c

3181

static uint8_t scarlett2_decode_muteable(uint8_t v)

tools/arch/x86/intel_sdsi/intel_sdsi.c

244

ret = fread(&s->regs, sizeof(uint8_t), sizeof(s->regs), regs_ptr);

tools/bpf/bpf_dbg.c

1112

(uint8_t *) hdr + sizeof(*hdr),

tools/bpf/bpf_dbg.c

1192

(uint8_t *) hdr + sizeof(*hdr),

tools/bpf/bpf_dbg.c

195

static void hex_dump(const uint8_t *buf, size_t len)

tools/bpf/bpf_dbg.c

470

static void bpf_dump_pkt(uint8_t *pkt, uint32_t pkt_caplen, uint32_t pkt_len)

tools/bpf/bpf_dbg.c

603

static uint32_t extract_u32(uint8_t *pkt, uint32_t off)

tools/bpf/bpf_dbg.c

612

static uint16_t extract_u16(uint8_t *pkt, uint32_t off)

tools/bpf/bpf_dbg.c

621

static uint8_t extract_u8(uint8_t *pkt, uint32_t off)

tools/bpf/bpf_dbg.c

633

uint8_t *pkt, uint32_t pkt_caplen,

tools/bpf/bpf_dbg.c

680

if (d >= sizeof(uint8_t))

tools/bpf/bpf_dbg.c

699

if (d >= sizeof(uint8_t))

tools/bpf/bpf_dbg.c

706

if (d >= sizeof(uint8_t)) {

tools/bpf/bpf_dbg.c

855

uint8_t *pkt, uint32_t pkt_caplen,

tools/bpf/bpf_dbg.c

866

static int bpf_run_all(struct sock_filter *f, uint16_t bpf_len, uint8_t *pkt,

tools/bpf/bpf_dbg.c

887

uint8_t *pkt, uint32_t pkt_caplen,

tools/bpf/bpf_exp.y

43

static void bpf_set_curr_instr(uint16_t op, uint8_t jt, uint8_t jf, uint32_t k);

tools/bpf/bpf_exp.y

479

static void bpf_set_curr_instr(uint16_t code, uint8_t jt, uint8_t jf,

tools/bpf/bpf_exp.y

548

static uint8_t bpf_encode_jt_jf_offset(int off, int i)

tools/bpf/bpf_exp.y

557

return (uint8_t) delta;

tools/bpf/bpf_jit_disasm.c

175

static uint8_t *get_last_jit_image(char *haystack, size_t hlen,

tools/bpf/bpf_jit_disasm.c

185

uint8_t *image;

tools/bpf/bpf_jit_disasm.c

236

image[ulen++] = (uint8_t) strtoul(pptr, &pptr, 16);

tools/bpf/bpf_jit_disasm.c

273

uint8_t *pos;

tools/bpf/bpf_jit_disasm.c

274

uint8_t *image = NULL;

tools/bpf/bpf_jit_disasm.c

55

static void get_asm_insns(uint8_t *image, size_t len, int opcodes)

tools/bpf/bpf_jit_disasm.c

98

printf("%02x ", (uint8_t) image[pc + i]);

tools/bpf/bpftool/common.c

527

void print_data_json(uint8_t *data, size_t len)

tools/bpf/bpftool/common.c

537

void print_hex_data_json(uint8_t *data, size_t len)

tools/bpf/bpftool/jit_disasm.c

400

(uint8_t)image[pc + i]);

tools/bpf/bpftool/jit_disasm.c

406

(uint8_t)image[pc + i]);

tools/bpf/bpftool/main.h

214

void print_data_json(uint8_t *data, size_t len);

tools/bpf/bpftool/main.h

215

void print_hex_data_json(uint8_t *data, size_t len);

tools/bpf/bpftool/prog.c

1255

fprintf(f, "%02x%s", *(uint8_t *)(data + j),

tools/bpf/bpftool/xlated_dumper.c

287

print_hex_data_json((uint8_t *)(&insn[i].off), 2);

tools/bpf/bpftool/xlated_dumper.c

291

print_hex_data_json((uint8_t *)(&insn[i].imm),

tools/bpf/bpftool/xlated_dumper.c

294

print_hex_data_json((uint8_t *)(&insn[i].imm),

tools/firmware/ihex2fw.c

132

static int process_ihex(uint8_t *data, ssize_t size)

tools/firmware/ihex2fw.c

138

uint8_t type, crc = 0, crcbyte = 0;

tools/firmware/ihex2fw.c

32

uint8_t data[];

tools/firmware/ihex2fw.c

38

static uint8_t nybble(const uint8_t n)

tools/firmware/ihex2fw.c

46

static uint8_t hex(const uint8_t *data, uint8_t *crc)

tools/firmware/ihex2fw.c

48

uint8_t val = (nybble(data[0]) << 4) | nybble(data[1]);

tools/firmware/ihex2fw.c

53

static int process_ihex(uint8_t *data, ssize_t size);

tools/firmware/ihex2fw.c

76

uint8_t *data;

tools/hv/vmbus_bufring.c

213

const uint8_t *br_data = rbr->vbr->data;

tools/hv/vmbus_bufring.c

215

uint8_t *dst = dst0;

tools/hv/vmbus_bufring.c

70

uint8_t res;

tools/hv/vmbus_bufring.c

88

uint8_t *br_data = tbr->vbr->data;

tools/hv/vmbus_bufring.c

90

const uint8_t *src = src0;

tools/hv/vmbus_bufring.h

81

uint8_t reserved2[4028];

tools/hv/vmbus_bufring.h

87

uint8_t data[];

tools/iio/iio_generic_buffer.c

192

print1byte(*(uint8_t *)(data + channels[k].location),

tools/iio/iio_generic_buffer.c

84

static void print1byte(uint8_t input, struct iio_channel_info *info)

tools/include/nolibc/stdint.h

25

typedef uint8_t uint_least8_t;

tools/include/nolibc/stdint.h

34

typedef uint8_t uint_fast8_t;

tools/include/tools/be_byteshift.h

12

static inline uint32_t __get_unaligned_be32(const uint8_t *p)

tools/include/tools/be_byteshift.h

17

static inline uint64_t __get_unaligned_be64(const uint8_t *p)

tools/include/tools/be_byteshift.h

23

static inline void __put_unaligned_be16(uint16_t val, uint8_t *p)

tools/include/tools/be_byteshift.h

29

static inline void __put_unaligned_be32(uint32_t val, uint8_t *p)

tools/include/tools/be_byteshift.h

35

static inline void __put_unaligned_be64(uint64_t val, uint8_t *p)

tools/include/tools/be_byteshift.h

43

return __get_unaligned_be16((const uint8_t *)p);

tools/include/tools/be_byteshift.h

48

return __get_unaligned_be32((const uint8_t *)p);

tools/include/tools/be_byteshift.h

53

return __get_unaligned_be64((const uint8_t *)p);

tools/include/tools/be_byteshift.h

7

static inline uint16_t __get_unaligned_be16(const uint8_t *p)

tools/include/tools/le_byteshift.h

12

static inline uint32_t __get_unaligned_le32(const uint8_t *p)

tools/include/tools/le_byteshift.h

17

static inline uint64_t __get_unaligned_le64(const uint8_t *p)

tools/include/tools/le_byteshift.h

23

static inline void __put_unaligned_le16(uint16_t val, uint8_t *p)

tools/include/tools/le_byteshift.h

29

static inline void __put_unaligned_le32(uint32_t val, uint8_t *p)

tools/include/tools/le_byteshift.h

35

static inline void __put_unaligned_le64(uint64_t val, uint8_t *p)

tools/include/tools/le_byteshift.h

43

return __get_unaligned_le16((const uint8_t *)p);

tools/include/tools/le_byteshift.h

48

return __get_unaligned_le32((const uint8_t *)p);

tools/include/tools/le_byteshift.h

53

return __get_unaligned_le64((const uint8_t *)p);

tools/include/tools/le_byteshift.h

7

static inline uint16_t __get_unaligned_le16(const uint8_t *p)

tools/include/uapi/drm/drm.h

56

typedef uint8_t __u8;

tools/lib/bpf/nlattr.c

17

[LIBBPF_NLA_U8] = sizeof(uint8_t),

tools/lib/bpf/nlattr.h

89

static inline uint8_t libbpf_nla_getattr_u8(const struct nlattr *nla)

tools/lib/bpf/nlattr.h

91

return *(uint8_t *)libbpf_nla_data(nla);

tools/mm/page-types.c

975

uint8_t vec[PAGEMAP_BATCH];

tools/perf/builtin-script.c

1230

(uint8_t *)inbuf, inlen, ip, lenp,

tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c

59

case 1: packet->payload = *(uint8_t *)buf; break;

tools/perf/util/capstone.c

218

const uint8_t *code __maybe_unused,

tools/perf/util/capstone.c

78

static size_t perf_cs_disasm(csh handle, const uint8_t *code, size_t code_size,

tools/perf/util/capstone.c

85

static enum cs_err (*fn)(csh handle, const uint8_t *code, size_t code_size,

tools/perf/util/capstone.h

19

bool is64bit, const uint8_t *code, size_t code_size,

tools/perf/util/capstone.h

31

const uint8_t *code __maybe_unused,

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

284

const uint8_t trace_chan_id)

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

307

const uint8_t trace_chan_id,

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

435

const uint8_t trace_chan_id)

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

502

const uint8_t trace_chan_id)

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

517

const uint8_t trace_chan_id)

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

535

const uint8_t trace_chan_id)

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c

545

const uint8_t trace_chan_id)

tools/perf/util/demangle-rust-v0.c

1044

if ((status = display_ident(ident->ascii_start, ident->ascii_len, ident->punycode_start, ident->punycode_len, (uint8_t*)printer->out, &out_len)) != OverflowOk) {

tools/perf/util/demangle-rust-v0.c

1159

uint8_t tag;

tools/perf/util/demangle-rust-v0.c

1263

static NODISCARD overflow_status printer_print_const_uint(struct printer *printer, uint8_t tag) {

tools/perf/util/demangle-rust-v0.c

1295

nts_status = nibbles_to_string(hex.start, hex.len, (uint8_t*)printer->out, &out_len);

tools/perf/util/demangle-rust-v0.c

1335

uint8_t tag;

tools/perf/util/demangle-rust-v0.c

1597

uint8_t tag;

tools/perf/util/demangle-rust-v0.c

1863

uint8_t wchr[4];

tools/perf/util/demangle-rust-v0.c

247

static NODISCARD size_t utf8_next_char(uint8_t *s, uint32_t *ch) {

tools/perf/util/demangle-rust-v0.c

248

uint8_t byte = *s;

tools/perf/util/demangle-rust-v0.c

402

static NODISCARD overflow_status display_ident(const char *ascii_start, size_t ascii_len, const char *punycode_start, size_t punycode_len, uint8_t *out, size_t *out_len) {

tools/perf/util/demangle-rust-v0.c

473

static NODISCARD bool dinibble2int(const char *buf, uint8_t *result) {

tools/perf/util/demangle-rust-v0.c

474

uint8_t result_val = 0;

tools/perf/util/demangle-rust-v0.c

500

static NODISCARD size_t char_to_string(uint32_t ch, uint8_t quote, bool first, char (*buf)[ESCAPED_SIZE]) {

tools/perf/util/demangle-rust-v0.c

51

const uint8_t *s_ = s;

tools/perf/util/demangle-rust-v0.c

542

static NODISCARD nibbles_to_string_status nibbles_to_string(const char *buf, size_t len, uint8_t *out, size_t *out_len) {

tools/perf/util/demangle-rust-v0.c

543

uint8_t quote = '"';

tools/perf/util/demangle-rust-v0.c

562

uint8_t conv_buf[4] = {0};

tools/perf/util/demangle-rust-v0.c

613

static const char* basic_type(uint8_t tag) {

tools/perf/util/demangle-rust-v0.c

676

static uint8_t parser_peek(struct parser const *parser) {

tools/perf/util/demangle-rust-v0.c

684

static bool parser_eat(struct parser *parser, uint8_t ch) {

tools/perf/util/demangle-rust-v0.c

695

static uint8_t parser_next(struct parser *parser) {

tools/perf/util/demangle-rust-v0.c

704

static NODISCARD demangle_status parser_ch(struct parser *parser, uint8_t *next) {

tools/perf/util/demangle-rust-v0.c

722

uint8_t ch = parser_next(parser);

tools/perf/util/demangle-rust-v0.c

735

static NODISCARD demangle_status parser_digit_10(struct parser *parser, uint8_t *out) {

tools/perf/util/demangle-rust-v0.c

736

uint8_t ch = parser_peek(parser);

tools/perf/util/demangle-rust-v0.c

747

uint8_t ch = parser_peek(parser);

tools/perf/util/demangle-rust-v0.c

794

static NODISCARD demangle_status parser_opt_integer_62(struct parser *parser, uint8_t tag, uint64_t *out) {

tools/perf/util/demangle-rust-v0.c

815

typedef uint8_t parser_namespace_type;

tools/perf/util/demangle-rust-v0.c

818

uint8_t next = parser_next(parser);

tools/perf/util/demangle-rust-v0.c

861

uint8_t d;

tools/perf/util/demangle-rust-v0.c

995

static bool printer_eat(struct printer *printer, uint8_t b) {

tools/perf/util/genelf_debug.c

37

typedef uint8_t ubyte;

tools/perf/util/lzma.c

118

const uint8_t magic[6] = { 0xFD, '7', 'z', 'X', 'Z', 0x00 };

tools/perf/util/print_insn.c

46

bool is64bit, const uint8_t *code, size_t code_size,

tools/perf/util/print_insn.c

61

(uint8_t *)sample->insn, sample->insn_len,

tools/perf/util/print_insn.h

19

bool is64bit, const uint8_t *code, size_t code_size,

tools/perf/util/symbol-elf.c

93

static inline uint8_t elf_sym__type(const GElf_Sym *sym)

tools/perf/util/symbol-elf.c

98

static inline uint8_t elf_sym__visibility(const GElf_Sym *sym)

tools/perf/util/zlib.c

86

const uint8_t magic[2] = { 0x1f, 0x8b };

tools/power/acpi/tools/ec/ec_access.c

143

printf(" %.2x ", (uint8_t)buf[byte_off]);

tools/power/acpi/tools/ec/ec_access.c

168

printf(" %.2x ", (uint8_t)buf2[byte_off]);

tools/power/acpi/tools/ec/ec_access.c

170

printf("*%.2x ", (uint8_t)buf2[byte_off]);

tools/power/acpi/tools/ec/ec_access.c

177

uint8_t buf;

tools/power/acpi/tools/ec/ec_access.c

192

void write_ec_val(int fd, int byte_offset, uint8_t value)

tools/power/acpi/tools/ec/ec_access.c

33

static uint8_t write_value = -1;

tools/power/cpupower/utils/helpers/amd.c

153

uint8_t val = 0;

tools/sched_ext/include/scx/common.h

21

typedef uint8_t u8;

tools/spi/spidev_test.c

119

static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len)

tools/spi/spidev_test.c

343

uint8_t *tx;

tools/spi/spidev_test.c

344

uint8_t *rx;

tools/spi/spidev_test.c

365

uint8_t *tx;

tools/spi/spidev_test.c

366

uint8_t *rx;

tools/spi/spidev_test.c

40

static uint8_t bits = 8;

tools/spi/spidev_test.c

412

uint8_t *tx;

tools/spi/spidev_test.c

413

uint8_t *rx;

tools/spi/spidev_test.c

51

static uint8_t default_tx[] = {

tools/spi/spidev_test.c

60

static uint8_t default_rx[ARRAY_SIZE(default_tx)] = {0, };

tools/testing/selftests/arm64/abi/syscall-abi.c

141

static uint8_t z_zero[__SVE_ZREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

142

uint8_t z_in[SVE_NUM_ZREGS * __SVE_ZREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

143

uint8_t z_out[SVE_NUM_ZREGS * __SVE_ZREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

163

uint8_t *in = &z_in[reg_size * i];

tools/testing/selftests/arm64/abi/syscall-abi.c

164

uint8_t *out = &z_out[reg_size * i];

tools/testing/selftests/arm64/abi/syscall-abi.c

201

uint8_t p_in[SVE_NUM_PREGS * __SVE_PREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

202

uint8_t p_out[SVE_NUM_PREGS * __SVE_PREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

233

uint8_t ffr_in[__SVE_PREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

234

uint8_t ffr_out[__SVE_PREG_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

311

uint8_t za_in[ZA_SIG_REGS_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

312

uint8_t za_out[ZA_SIG_REGS_SIZE(ARCH_SVE_VQ_MAX)];

tools/testing/selftests/arm64/abi/syscall-abi.c

338

uint8_t zt_in[ZT_SIG_REG_BYTES] __attribute__((aligned(16)));

tools/testing/selftests/arm64/abi/syscall-abi.c

339

uint8_t zt_out[ZT_SIG_REG_BYTES] __attribute__((aligned(16)));

tools/testing/selftests/arm64/fp/fp-ptrace.c

629

uint8_t buf[512];

tools/testing/selftests/arm64/fp/fp-ptrace.c

872

uint8_t *lbuf = buf;

tools/testing/selftests/bpf/ip_check_defrag_frags.h

16

static uint8_t frag_1[] = {

tools/testing/selftests/bpf/ip_check_defrag_frags.h

23

static uint8_t frag_2[] = {

tools/testing/selftests/bpf/ip_check_defrag_frags.h

28

static uint8_t frag6_0[] = {

tools/testing/selftests/bpf/ip_check_defrag_frags.h

38

static uint8_t frag6_1[] = {

tools/testing/selftests/bpf/ip_check_defrag_frags.h

48

static uint8_t frag6_2[] = {

tools/testing/selftests/bpf/ip_check_defrag_frags.h

9

static uint8_t frag_0[] = {

tools/testing/selftests/bpf/jit_disasm_helpers.c

175

uint8_t *image = NULL;

tools/testing/selftests/bpf/jit_disasm_helpers.c

63

static int disasm_insn(LLVMDisasmContextRef ctx, uint8_t *image, __u32 len, __u32 pc,

tools/testing/selftests/bpf/jit_disasm_helpers.c

91

static int disasm_one_func(FILE *text_out, uint8_t *image, __u32 len)

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

128

const uint8_t *key,

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

161

assert(!tlpm_match(list, (uint8_t[]){ 0xff }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

163

t1 = list = tlpm_add(list, (uint8_t[]){ 0xff }, 8);

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

164

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

165

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff, 0xff }, 16));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

166

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff, 0x00 }, 16));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

167

assert(!tlpm_match(list, (uint8_t[]){ 0x7f }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

168

assert(!tlpm_match(list, (uint8_t[]){ 0xfe }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

169

assert(!tlpm_match(list, (uint8_t[]){ 0xff }, 7));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

171

t2 = list = tlpm_add(list, (uint8_t[]){ 0xff, 0xff }, 16);

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

172

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

173

assert(t2 == tlpm_match(list, (uint8_t[]){ 0xff, 0xff }, 16));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

174

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff, 0xff }, 15));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

175

assert(!tlpm_match(list, (uint8_t[]){ 0x7f, 0xff }, 16));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

177

list = tlpm_delete(list, (uint8_t[]){ 0xff, 0xff }, 16);

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

178

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

179

assert(t1 == tlpm_match(list, (uint8_t[]){ 0xff, 0xff }, 16));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

181

list = tlpm_delete(list, (uint8_t[]){ 0xff }, 8);

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

182

assert(!tlpm_match(list, (uint8_t[]){ 0xff }, 8));

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

199

l1 = tlpm_add(l1, (uint8_t[]){

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

208

uint8_t key[] = { rand() % 0xff, rand() % 0xff };

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

233

uint8_t *data, *value;

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

35

uint8_t key[];

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

55

const uint8_t *key,

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

59

const uint8_t *key,

tools/testing/selftests/bpf/map_tests/lpm_trie_map_basic_ops.c

99

const uint8_t *key,

tools/testing/selftests/bpf/prog_tests/btf.c

4527

uint8_t *raw_btf = NULL, *user_btf = NULL;

tools/testing/selftests/bpf/prog_tests/btf.c

4611

uint8_t *raw_btf = NULL, *user_btf[2] = {};

tools/testing/selftests/bpf/prog_tests/btf.c

4734

uint8_t *raw_btf = NULL, *user_btf = NULL;

tools/testing/selftests/bpf/prog_tests/btf.c

5012

uint8_t ui8a[8];

tools/testing/selftests/bpf/prog_tests/btf.c

5022

uint8_t si8_4[2][2];

tools/testing/selftests/bpf/prog_tests/btf.c

5475

uint8_t *raw_btf;

tools/testing/selftests/bpf/prog_tests/cls_redirect.c

175

static void encap_init(encap_headers_t *encap, uint8_t hop_count, uint8_t proto)

tools/testing/selftests/bpf/prog_tests/cls_redirect.c

177

const uint8_t hlen =

tools/testing/selftests/bpf/prog_tests/cls_redirect.c

217

uint8_t *p = buf;

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

105

uint8_t cfg_dsfield_inner;

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

106

uint8_t cfg_dsfield_outer;

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

122

static void build_ipv4_header(void *header, uint8_t proto, uint32_t src,

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

123

uint32_t dst, int payload_len, uint8_t tos)

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

139

static void ipv6_set_dsfield(struct ipv6hdr *ip6h, uint8_t dsfield)

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

149

static void build_ipv6_header(void *header, uint8_t proto,

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

152

uint8_t dsfield)

tools/testing/selftests/bpf/prog_tests/flow_dissector_classification.c

184

static void build_gue_header(void *header, uint8_t proto)

tools/testing/selftests/bpf/prog_tests/test_sysctl.c

1401

uint8_t raw[sizeof(uint64_t)];

tools/testing/selftests/bpf/prog_tests/xdp_bonding.c

216

uint8_t buf[128];

tools/testing/selftests/bpf/prog_tests/xfrm_info.c

175

(struct rtattr *)((uint8_t *)nh + RTA_ALIGN(nh->nlmsg_len));

tools/testing/selftests/bpf/prog_tests/xfrm_info.c

198

uint8_t *end = (uint8_t *)nh + nh->nlmsg_len;

tools/testing/selftests/bpf/prog_tests/xfrm_info.c

200

attr->rta_len = end - (uint8_t *)attr;

tools/testing/selftests/bpf/progs/core_reloc_types.h

624

uint8_t u8_field;

tools/testing/selftests/bpf/progs/core_reloc_types.h

637

uint8_t s8_field;

tools/testing/selftests/bpf/progs/core_reloc_types.h

738

uint8_t ub1: 1;

tools/testing/selftests/bpf/progs/core_reloc_types.h

739

uint8_t ub2: 2;

tools/testing/selftests/bpf/progs/core_reloc_types.h

754

uint8_t ub7: 1; /* 7 -> 1 */

tools/testing/selftests/bpf/progs/core_reloc_types.h

766

uint8_t ub2; /* 20 -> 8 non-bitfield */

tools/testing/selftests/bpf/progs/profiler.h

103

uint8_t kill_target_name_length;

tools/testing/selftests/bpf/progs/profiler.h

104

uint8_t kill_target_cgroup_proc_length;

tools/testing/selftests/bpf/progs/profiler.h

72

uint8_t comm_length;

tools/testing/selftests/bpf/progs/profiler.h

90

uint8_t sysctl_val_length;

tools/testing/selftests/bpf/progs/strobemeta.h

174

uint8_t req_meta_valid;

tools/testing/selftests/bpf/progs/strobemeta.h

49

uint8_t _reserved[6];

tools/testing/selftests/bpf/progs/test_cls_redirect.c

125

typedef uint8_t *net_ptr __attribute__((align_value(8)));

tools/testing/selftests/bpf/progs/test_cls_redirect.c

133

uint8_t *const tail;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

282

uint8_t *upper_proto,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

291

uint8_t next;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

292

uint8_t len;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

349

pkt_parse_ipv6(buf_t *pkt, struct ipv6hdr *scratch, uint8_t *proto,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

422

uint8_t ttl;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

447

uint8_t ttl;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

505

.head = (uint8_t *)(long)skb->data,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

506

.tail = (uint8_t *)(long)skb->data_end,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

699

static INLINING verdict_t classify_icmp(struct __sk_buff *skb, uint8_t proto,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

787

uint8_t l4_proto;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

896

uint8_t l4_proto;

tools/testing/selftests/bpf/progs/test_cls_redirect.c

960

.head = (uint8_t *)(long)skb->data,

tools/testing/selftests/bpf/progs/test_cls_redirect.c

961

.tail = (uint8_t *)(long)skb->data_end,

tools/testing/selftests/bpf/progs/test_cls_redirect.h

31

uint8_t hlen : 5, control : 1, variant : 2;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

33

uint8_t variant : 2, control : 1, hlen : 5;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

35

uint8_t proto_ctype;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

41

uint8_t _r : 2, last_hop_gre : 1, forward_syn : 1, version : 4;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

43

uint8_t version : 4, forward_syn : 1, last_hop_gre : 1, _r : 2;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

45

uint8_t reserved;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

46

uint8_t next_hop;

tools/testing/selftests/bpf/progs/test_cls_redirect.h

47

uint8_t hop_count;

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

188

const struct ipv6hdr *ipv6, uint8_t *upper_proto,

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

197

uint8_t next;

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

198

uint8_t len;

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

245

uint8_t *proto, bool *is_fragment)

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

318

uint8_t ttl;

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

343

uint8_t ttl;

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

589

static verdict_t classify_icmp(struct __sk_buff *skb, uint8_t proto, struct bpf_sock_tuple *tuple,

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

661

uint8_t l4_proto;

tools/testing/selftests/bpf/progs/test_cls_redirect_dynptr.c

798

uint8_t l4_proto;

tools/testing/selftests/bpf/progs/test_core_reloc_bitfields_direct.c

18

uint8_t ub1: 1;

tools/testing/selftests/bpf/progs/test_core_reloc_bitfields_direct.c

19

uint8_t ub2: 2;

tools/testing/selftests/bpf/progs/test_core_reloc_bitfields_probed.c

18

uint8_t ub1: 1;

tools/testing/selftests/bpf/progs/test_core_reloc_bitfields_probed.c

19

uint8_t ub2: 2;

tools/testing/selftests/bpf/progs/test_core_reloc_ints.c

17

uint8_t u8_field;

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

180

struct sr6_tlv_t *itlv, uint8_t tlv_size)

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

183

uint8_t len_remaining, new_pad;

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

227

uint8_t len_remaining, new_pad;

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

329

uint8_t new_flags = SR6_FLAG_ALERT;

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

336

uint8_t tlv[20] = {2, 18, 0, 0, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

366

uint8_t new_flags = 0;

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

60

uint8_t *ipver;

tools/testing/selftests/bpf/progs/test_lwt_seg6local.c

64

ipver = (uint8_t *)cursor;

tools/testing/selftests/bpf/progs/test_seg6_loop.c

183

struct sr6_tlv_t *itlv, uint8_t tlv_size)

tools/testing/selftests/bpf/progs/test_seg6_loop.c

186

uint8_t len_remaining, new_pad;

tools/testing/selftests/bpf/progs/test_seg6_loop.c

233

uint8_t new_flags = SR6_FLAG_ALERT;

tools/testing/selftests/bpf/progs/test_seg6_loop.c

240

uint8_t tlv[20] = {2, 18, 0, 0, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

tools/testing/selftests/bpf/progs/test_seg6_loop.c

60

uint8_t *ipver;

tools/testing/selftests/bpf/progs/test_seg6_loop.c

64

ipver = (uint8_t *)cursor;

tools/testing/selftests/bpf/progs/twfw.c

19

uint8_t seqnum;

tools/testing/selftests/bpf/progs/verifier_bitfield_write.c

13

uint8_t ub1: 1;

tools/testing/selftests/bpf/progs/verifier_bitfield_write.c

14

uint8_t ub2: 2;

tools/testing/selftests/bpf/progs/verifier_bitfield_write.c

46

uint8_t ub2;

tools/testing/selftests/bpf/progs/verifier_bitfield_write.c

56

return (((uint8_t)sb4) << 2) | ub2;

tools/testing/selftests/bpf/progs/verifier_bitfield_write.c

67

uint8_t ub1, ub2;

tools/testing/selftests/bpf/progs/verifier_bitfield_write.c

88

uint8_t ub1;

tools/testing/selftests/bpf/progs/verifier_netfilter_ctx.c

95

uint8_t ihl;

tools/testing/selftests/bpf/test_progs.c

1310

fprintf(stdout, "%02X ", ((uint8_t *)(buf))[i]);

tools/testing/selftests/bpf/test_tag.c

114

static void tag_from_alg(int insns, uint8_t *tag, uint32_t len)

tools/testing/selftests/bpf/test_tag.c

144

static void tag_dump(const char *prefix, uint8_t *tag, uint32_t len)

tools/testing/selftests/bpf/test_tag.c

154

static void tag_exit_report(int insns, int fd_map, uint8_t *ftag,

tools/testing/selftests/bpf/test_tag.c

155

uint8_t *atag, uint32_t len)

tools/testing/selftests/bpf/test_tag.c

171

uint8_t ftag[8], atag[sizeof(ftag)];

tools/testing/selftests/bpf/test_tag.c

78

static int hex2bin(uint8_t *dst, const char *src, size_t count)

tools/testing/selftests/bpf/test_tag.c

91

static void tag_from_fdinfo(int fd_prog, uint8_t *tag, uint32_t len)

tools/testing/selftests/bpf/test_verifier.c

144

uint8_t flags;

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

31

static volatile uint8_t var[96] __attribute__((__aligned__(32)));

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

35

volatile uint8_t *addr = &var[32 + wr];

tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

83

const volatile uint8_t *addr = &var[32 + wp];

tools/testing/selftests/cgroup/test_memcontrol.c

1309

uint8_t buf[0x100000];

tools/testing/selftests/cgroup/test_memcontrol.c

1350

uint8_t buf[0x100000];

tools/testing/selftests/drivers/net/gro.c

115

static uint8_t src_mac[ETH_ALEN], dst_mac[ETH_ALEN];

tools/testing/selftests/drivers/net/gro.c

261

static void read_MAC(uint8_t *mac_addr, char *mac)

tools/testing/selftests/drivers/net/gro.c

501

uint8_t kind;

tools/testing/selftests/drivers/net/gro.c

502

uint8_t len;

tools/testing/selftests/drivers/net/gro.c

507

uint8_t kind;

tools/testing/selftests/drivers/net/gro.c

508

uint8_t len;

tools/testing/selftests/drivers/net/gro.c

509

uint8_t shift;

tools/testing/selftests/drivers/net/hw/toeplitz.c

317

static void __set_filter(int fd, int off_proto, uint8_t proto, int off_dport)

tools/testing/selftests/drivers/net/hw/toeplitz.c

341

uint8_t proto;

tools/testing/selftests/drivers/s390x/uvdevice/test_uvdevice.c

129

uint8_t nr = _IOC_NR(variant->ioctl_cmd);

tools/testing/selftests/drivers/s390x/uvdevice/test_uvdevice.c

147

uint8_t arcb[0x180];

tools/testing/selftests/drivers/s390x/uvdevice/test_uvdevice.c

148

uint8_t meas[64];

tools/testing/selftests/drivers/s390x/uvdevice/test_uvdevice.c

149

uint8_t add[32];

tools/testing/selftests/drivers/s390x/uvdevice/test_uvdevice.c

24

uint8_t buffer[BUFFER_SIZE];

tools/testing/selftests/iommu/iommufd.c

1146

uint8_t *buf;

tools/testing/selftests/iommu/iommufd.c

1743

uint8_t *buf;

tools/testing/selftests/iommu/iommufd.c

1769

uint8_t *buf;

tools/testing/selftests/iommu/iommufd.c

1799

uint8_t *buf;

tools/testing/selftests/iommu/iommufd.c

1831

uint8_t *buf;

tools/testing/selftests/iommu/iommufd.c

1885

uint8_t *buf;

tools/testing/selftests/iommu/iommufd.c

2554

static bool is_filled(const void *buf, uint8_t c, size_t len)

tools/testing/selftests/iommu/iommufd.c

2556

const uint8_t *cbuf = buf;

tools/testing/selftests/iommu/iommufd.c

760

uint8_t max_pasid = 0;

tools/testing/selftests/iommu/iommufd.c

99

uint8_t extra; \

tools/testing/selftests/iommu/iommufd_utils.h

827

uint32_t *capabilities, uint8_t *max_pasid)

tools/testing/selftests/kvm/arm64/debug-exceptions.c

105

uint8_t brps, wrps, i;

tools/testing/selftests/kvm/arm64/debug-exceptions.c

152

static void install_wp(uint8_t wpn, uint64_t addr)

tools/testing/selftests/kvm/arm64/debug-exceptions.c

165

static void install_hw_bp(uint8_t bpn, uint64_t addr)

tools/testing/selftests/kvm/arm64/debug-exceptions.c

177

static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr,

tools/testing/selftests/kvm/arm64/debug-exceptions.c

199

void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr,

tools/testing/selftests/kvm/arm64/debug-exceptions.c

237

static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)

tools/testing/selftests/kvm/arm64/debug-exceptions.c

424

static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)

tools/testing/selftests/kvm/arm64/debug-exceptions.c

538

uint8_t brp_num, wrp_num, ctx_brp_num, normal_brp_num, ctx_brp_base;

tools/testing/selftests/kvm/arm64/set_id_regs.c

33

uint8_t shift;

tools/testing/selftests/kvm/arm64/set_id_regs.c

378

uint8_t shift = ftr_bits->shift;

tools/testing/selftests/kvm/arm64/set_id_regs.c

401

uint8_t shift = ftr_bits->shift;

tools/testing/selftests/kvm/arm64/vpmu_counter_access.c

405

uint8_t pmuver, ec;

tools/testing/selftests/kvm/coalesced_io_test.c

26

uint8_t pio_port;

tools/testing/selftests/kvm/get-reg-list.c

219

uint8_t addr[2048 / 8];

tools/testing/selftests/kvm/guest_memfd_test.c

409

static void guest_code(uint8_t *mem, uint64_t size)

tools/testing/selftests/kvm/guest_memfd_test.c

433

uint8_t *mem;

tools/testing/selftests/kvm/include/kvm_util.h

1163

uint8_t indent);

tools/testing/selftests/kvm/include/kvm_util.h

1166

uint8_t indent)

tools/testing/selftests/kvm/include/kvm_util.h

1271

void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent);

tools/testing/selftests/kvm/include/kvm_util.h

1273

static inline void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/include/kvm_util.h

217

uint8_t mode;

tools/testing/selftests/kvm/include/kvm_util.h

218

uint8_t pad0;

tools/testing/selftests/kvm/include/kvm_util.h

477

void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent);

tools/testing/selftests/kvm/include/test_util.h

120

uint8_t percent)

tools/testing/selftests/kvm/include/x86/apic.h

102

static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value)

tools/testing/selftests/kvm/include/x86/apic.h

109

uint8_t fault = x2apic_write_reg_safe(reg, value);

tools/testing/selftests/kvm/include/x86/apic.h

117

uint8_t fault = x2apic_write_reg_safe(reg, value);

tools/testing/selftests/kvm/include/x86/hyperv.h

257

static inline uint8_t __hyperv_hypercall(u64 control, vm_vaddr_t input_address,

tools/testing/selftests/kvm/include/x86/hyperv.h

262

uint8_t vector;

tools/testing/selftests/kvm/include/x86/hyperv.h

281

uint8_t vector;

tools/testing/selftests/kvm/include/x86/processor.h

1101

void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr);

tools/testing/selftests/kvm/include/x86/processor.h

1259

uint8_t vector; \

tools/testing/selftests/kvm/include/x86/processor.h

1270

uint8_t vector; \

tools/testing/selftests/kvm/include/x86/processor.h

1282

uint8_t vector; \

tools/testing/selftests/kvm/include/x86/processor.h

1293

uint8_t vector; \

tools/testing/selftests/kvm/include/x86/processor.h

1303

static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \

tools/testing/selftests/kvm/include/x86/processor.h

1306

uint8_t vector; \

tools/testing/selftests/kvm/include/x86/processor.h

1331

static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val)

tools/testing/selftests/kvm/include/x86/processor.h

1336

static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value)

tools/testing/selftests/kvm/include/x86/processor.h

721

uint8_t reg, uint8_t lo, uint8_t hi)

tools/testing/selftests/kvm/include/x86/sev.h

135

uint64_t hva, uint64_t size, uint8_t type)

tools/testing/selftests/kvm/include/x86/sev.h

50

void sev_vm_launch_measure(struct kvm_vm *vm, uint8_t *measurement);

tools/testing/selftests/kvm/include/x86/sev.h

58

void vm_sev_launch(struct kvm_vm *vm, uint64_t policy, uint8_t *measurement);

tools/testing/selftests/kvm/include/x86/vmx.h

297

uint8_t ret;

tools/testing/selftests/kvm/include/x86/vmx.h

314

uint8_t ret;

tools/testing/selftests/kvm/include/x86/vmx.h

326

uint8_t ret;

tools/testing/selftests/kvm/include/x86/vmx.h

342

uint8_t ret;

tools/testing/selftests/kvm/include/x86/vmx.h

453

uint8_t ret;

tools/testing/selftests/kvm/include/x86/vmx.h

480

uint8_t ret;

tools/testing/selftests/kvm/lib/arm64/processor.c

127

uint8_t attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT);

tools/testing/selftests/kvm/lib/arm64/processor.c

240

static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level)

tools/testing/selftests/kvm/lib/arm64/processor.c

259

void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/lib/arm64/processor.c

400

void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)

tools/testing/selftests/kvm/lib/guest_sprintf.c

219

(uint8_t)va_arg(args, int));

tools/testing/selftests/kvm/lib/kvm_util.c

1966

void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/lib/loongarch/processor.c

142

static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level)

tools/testing/selftests/kvm/lib/loongarch/processor.c

160

void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/lib/loongarch/processor.c

171

void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)

tools/testing/selftests/kvm/lib/riscv/processor.c

151

static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,

tools/testing/selftests/kvm/lib/riscv/processor.c

173

void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/lib/riscv/processor.c

236

void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)

tools/testing/selftests/kvm/lib/s390/processor.c

114

static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, uint8_t indent,

tools/testing/selftests/kvm/lib/s390/processor.c

128

static void virt_dump_region(FILE *stream, struct kvm_vm *vm, uint8_t indent,

tools/testing/selftests/kvm/lib/s390/processor.c

150

void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/lib/s390/processor.c

215

void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)

tools/testing/selftests/kvm/lib/sparsebit.c

2077

uint8_t op = get8() & 0xf;

tools/testing/selftests/kvm/lib/x86/processor.c

104

uint8_t indent)

tools/testing/selftests/kvm/lib/x86/processor.c

112

static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, uint8_t indent)

tools/testing/selftests/kvm/lib/x86/processor.c

1126

void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)

tools/testing/selftests/kvm/lib/x86/processor.c

1377

uint8_t maxphyaddr, guest_maxphyaddr;

tools/testing/selftests/kvm/lib/x86/processor.c

408

void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)

tools/testing/selftests/kvm/lib/x86/processor.c

63

static void regs_dump(FILE *stream, struct kvm_regs *regs, uint8_t indent)

tools/testing/selftests/kvm/lib/x86/processor.c

87

uint8_t indent)

tools/testing/selftests/kvm/lib/x86/processor.c

908

uint8_t reg, uint8_t lo, uint8_t hi)

tools/testing/selftests/kvm/lib/x86/sev.c

106

void sev_vm_launch_measure(struct kvm_vm *vm, uint8_t *measurement)

tools/testing/selftests/kvm/lib/x86/sev.c

177

void vm_sev_launch(struct kvm_vm *vm, uint64_t policy, uint8_t *measurement)

tools/testing/selftests/kvm/lib/x86/sev.c

18

uint8_t page_type, bool private)

tools/testing/selftests/kvm/memslot_perf_test.c

220

return (uint8_t *)base + slotoffs * guest_page_size + pgoffs;

tools/testing/selftests/kvm/mmu_stress_test.c

350

((uint8_t *)mem)[i] = 0xaa;

tools/testing/selftests/kvm/s390/memop.c

233

static uint8_t __aligned(PAGE_SIZE) mem1[65536];

tools/testing/selftests/kvm/s390/memop.c

234

static uint8_t __aligned(PAGE_SIZE) mem2[65536];

tools/testing/selftests/kvm/s390/memop.c

299

enum mop_target mop_target, uint32_t size, uint8_t key)

tools/testing/selftests/kvm/s390/memop.c

311

enum mop_target mop_target, uint32_t size, uint8_t key)

tools/testing/selftests/kvm/s390/memop.c

321

static void default_cmpxchg(struct test_default *test, uint8_t key)

tools/testing/selftests/kvm/s390/memop.c

325

uint8_t __aligned(16) new[16] = {};

tools/testing/selftests/kvm/s390/memop.c

326

uint8_t __aligned(16) old[16];

tools/testing/selftests/kvm/s390/memop.c

403

static void set_storage_key_range(void *addr, size_t len, uint8_t key)

tools/testing/selftests/kvm/s390/memop.c

486

return (uint8_t)val;

tools/testing/selftests/kvm/s390/memop.c

51

uint8_t old_value[16];

tools/testing/selftests/kvm/s390/memop.c

53

uint8_t ar;

tools/testing/selftests/kvm/s390/memop.c

54

uint8_t key;

tools/testing/selftests/kvm/s390/memop.c

556

uint8_t byte0, byte1;

tools/testing/selftests/kvm/s390/memop.c

57

const uint8_t NO_KEY = 0xff;

tools/testing/selftests/kvm/s390/resets.c

23

static uint8_t regs_null[512];

tools/testing/selftests/kvm/s390/shared_zeropage_test.c

16

static void set_storage_key(void *addr, uint8_t skey)

tools/testing/selftests/kvm/s390/tprot.c

17

static __aligned(PAGE_SIZE) uint8_t pages[2][PAGE_SIZE];

tools/testing/selftests/kvm/s390/tprot.c

18

static uint8_t *const page_store_prot = pages[0];

tools/testing/selftests/kvm/s390/tprot.c

19

static uint8_t *const page_fetch_prot = pages[1];

tools/testing/selftests/kvm/s390/tprot.c

22

static int set_storage_key(void *addr, uint8_t key)

tools/testing/selftests/kvm/s390/tprot.c

47

static enum permission test_protection(void *addr, uint8_t key)

tools/testing/selftests/kvm/s390/tprot.c

75

uint8_t key;

tools/testing/selftests/kvm/set_memory_region_test.c

566

*((uint8_t *)NONCANONICAL) = 0x1;

tools/testing/selftests/kvm/steal_time.c

219

uint8_t preempted;

tools/testing/selftests/kvm/steal_time.c

220

uint8_t pad[47];

tools/testing/selftests/kvm/x86/aperfmperf_test.c

111

uint8_t vector;

tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c

32

static uint8_t smi_handler[] = {

tools/testing/selftests/kvm/x86/fastops_test.c

113

uint8_t v, ex_v; \

tools/testing/selftests/kvm/x86/fastops_test.c

188

guest_test_fastops(uint8_t, "b");

tools/testing/selftests/kvm/x86/fastops_test.c

80

uint8_t shift = __val1; \

tools/testing/selftests/kvm/x86/fastops_test.c

98

uint8_t vector; \

tools/testing/selftests/kvm/x86/fix_hypercall_test.c

29

static const uint8_t vmx_vmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xc1 };

tools/testing/selftests/kvm/x86/fix_hypercall_test.c

30

static const uint8_t svm_vmmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xd9 };

tools/testing/selftests/kvm/x86/fix_hypercall_test.c

32

extern uint8_t hypercall_insn[HYPERCALL_INSN_SIZE];

tools/testing/selftests/kvm/x86/fix_hypercall_test.c

33

static uint64_t do_sched_yield(uint8_t apic_id)

tools/testing/selftests/kvm/x86/fix_hypercall_test.c

48

const uint8_t *native_hypercall_insn;

tools/testing/selftests/kvm/x86/fix_hypercall_test.c

49

const uint8_t *other_hypercall_insn;

tools/testing/selftests/kvm/x86/flds_emulation.h

24

uint8_t *insn_bytes;

tools/testing/selftests/kvm/x86/hyperv_features.c

44

uint8_t vector = 0;

tools/testing/selftests/kvm/x86/hyperv_features.c

88

uint8_t vector;

tools/testing/selftests/kvm/x86/kvm_pv_test.c

44

uint8_t vector;

tools/testing/selftests/kvm/x86/nested_emulation_test.c

16

uint8_t opcode[15];

tools/testing/selftests/kvm/x86/nested_emulation_test.c

35

static uint8_t kvm_fep[] = { 0x0f, 0x0b, 0x6b, 0x76, 0x6d }; /* ud2 ; .ascii "kvm" */

tools/testing/selftests/kvm/x86/nested_emulation_test.c

36

static uint8_t l2_guest_code[sizeof(kvm_fep) + 15];

tools/testing/selftests/kvm/x86/nested_emulation_test.c

37

static uint8_t *l2_instruction = &l2_guest_code[sizeof(kvm_fep)];

tools/testing/selftests/kvm/x86/platform_info_test.c

27

uint8_t vector;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

135

static uint8_t guest_get_pmu_version(void)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

144

return min_t(uint8_t, kvm_pmu_version, this_cpu_property(X86_PROPERTY_PMU_VERSION));

tools/testing/selftests/kvm/x86/pmu_counters_test.c

156

static void guest_assert_event_count(uint8_t idx, uint32_t pmc, uint32_t pmc_msr)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

258

static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pmc_msr,

tools/testing/selftests/kvm/x86/pmu_counters_test.c

267

static void guest_test_arch_event(uint8_t idx)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

323

uint8_t i;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

331

static void test_arch_events(uint8_t pmu_version, uint64_t perf_capabilities,

tools/testing/selftests/kvm/x86/pmu_counters_test.c

332

uint8_t length, uint32_t unavailable_mask)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

35

static uint8_t kvm_pmu_version;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

379

uint8_t vector;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

396

static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters,

tools/testing/selftests/kvm/x86/pmu_counters_test.c

397

uint8_t nr_counters, uint32_t or_mask)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

400

uint8_t i;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

425

uint8_t vector;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

464

uint8_t pmu_version = guest_get_pmu_version();

tools/testing/selftests/kvm/x86/pmu_counters_test.c

465

uint8_t nr_gp_counters = 0;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

498

static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities,

tools/testing/selftests/kvm/x86/pmu_counters_test.c

499

uint8_t nr_gp_counters)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

518

uint8_t nr_fixed_counters = 0;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

519

uint8_t i;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

536

uint8_t vector;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

564

static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities,

tools/testing/selftests/kvm/x86/pmu_counters_test.c

565

uint8_t nr_fixed_counters,

tools/testing/selftests/kvm/x86/pmu_counters_test.c

586

uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);

tools/testing/selftests/kvm/x86/pmu_counters_test.c

587

uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);

tools/testing/selftests/kvm/x86/pmu_counters_test.c

588

uint8_t pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION);

tools/testing/selftests/kvm/x86/pmu_counters_test.c

590

uint8_t v, j;

tools/testing/selftests/kvm/x86/pmu_counters_test.c

60

static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx)

tools/testing/selftests/kvm/x86/pmu_counters_test.c

623

uint8_t max_pmu_version = max_t(typeof(pmu_version), pmu_version, 5);

tools/testing/selftests/kvm/x86/pmu_counters_test.c

92

uint8_t pmu_version,

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

687

uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

731

static void intel_run_fixed_counter_guest_code(uint8_t idx)

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

772

static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, uint8_t idx,

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

773

uint8_t nr_fixed_counters)

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

817

uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);

tools/testing/selftests/kvm/x86/pmu_event_filter_test.c

820

uint8_t idx;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

124

const uint8_t def_p = 0xaa;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

125

const uint8_t init_p = 0xcc;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

139

uint8_t p1 = 0x11;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

140

uint8_t p2 = 0x22;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

141

uint8_t p3 = 0x33;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

142

uint8_t p4 = 0x44;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

232

const uint8_t init_p = 0xcc;

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

32

uint8_t *mem = (uint8_t *)gpa; \

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

350

uint8_t *hva = addr_gpa2hva(vm, gpa + i);

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

41

static void memcmp_h(uint8_t *mem, uint64_t gpa, uint8_t pattern, size_t size)

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

74

uint8_t current_pattern, uint8_t new_pattern)

tools/testing/selftests/kvm/x86/private_mem_conversions_test.c

79

static void guest_sync_private(uint64_t gpa, uint64_t size, uint8_t pattern)

tools/testing/selftests/kvm/x86/smm_test.c

37

uint8_t smi_handler[] = {

tools/testing/selftests/kvm/x86/state_test.c

144

uint8_t buffer[PAGE_SIZE];

tools/testing/selftests/kvm/x86/state_test.c

299

xstate_bv = (void *)&((uint8_t *)state->xsave->region)[512];

tools/testing/selftests/kvm/x86/userspace_io_test.c

13

static void guest_ins_port80(uint8_t *buffer, unsigned int count)

tools/testing/selftests/kvm/x86/userspace_io_test.c

29

uint8_t buffer[8192];

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

26

.bitmap = (uint8_t*)&deny_bits,

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

33

.bitmap = (uint8_t*)&deny_bits,

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

40

.bitmap = (uint8_t*)&deny_bits,

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

52

.bitmap = (uint8_t*)&deny_bits,

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

64

.bitmap = (uint8_t*)&deny_bits,

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

735

.bitmap = (uint8_t *)&deny_bits,

tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c

80

static void deny_msr(uint8_t *bitmap, u32 msr)

tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c

57

uint8_t vector = wrmsr_safe(MSR_IA32_PERF_CAPABILITIES, val);

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

107

uint8_t tpr;

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

160

static uint8_t lapic_tpr_get(struct kvm_lapic_state *xapic)

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

165

static void lapic_tpr_set(struct kvm_lapic_state *xapic, uint8_t val)

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

172

static uint8_t sregs_tpr(struct kvm_sregs *sregs)

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

200

uint8_t tpr;

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

72

static uint8_t tpr_guest_tpr_get(void)

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

84

static uint8_t tpr_guest_ppr_get(void)

tools/testing/selftests/kvm/x86/xapic_tpr_test.c

96

static uint8_t tpr_guest_cr8_get(void)

tools/testing/selftests/kvm/x86/xen_shinfo_test.c

136

uint8_t evtchn_upcall_pending;

tools/testing/selftests/kvm/x86/xen_shinfo_test.c

137

uint8_t evtchn_upcall_mask;

tools/testing/selftests/memfd/fuse_test.c

202

uint8_t *stack;

tools/testing/selftests/memfd/memfd_test.c

798

uint8_t *stack;

tools/testing/selftests/mm/droppable.c

32

assert(*(uint8_t *)(alloc + i));

tools/testing/selftests/mm/droppable.c

43

if (!*(uint8_t *)(alloc + i)) {

tools/testing/selftests/mm/transhuge-stress.c

33

uint8_t *map;

tools/testing/selftests/mm/uffd-common.c

473

uint8_t *area;

tools/testing/selftests/mm/uffd-common.c

488

area = (uint8_t *)(gopts->area_dst +

tools/testing/selftests/mm/uffd-unit-tests.c

530

uint8_t expected_byte;

tools/testing/selftests/mm/uffd-unit-tests.c

533

expected_byte = ~((uint8_t)(i % ((uint8_t)-1)));

tools/testing/selftests/mm/uffd-unit-tests.c

535

uint8_t v = *(uint8_t *)(p + (i * gopts->page_size) + j);

tools/testing/selftests/mm/uffd-unit-tests.c

566

memset(gopts->area_dst + (p * gopts->page_size), p % ((uint8_t)-1),

tools/testing/selftests/net/busy_poller.c

111

cfg_prefer_busy_poll = (uint8_t)tmp;

tools/testing/selftests/net/busy_poller.c

46

uint8_t prefer_busy_poll;

tools/testing/selftests/net/busy_poller.c

49

uint8_t __pad;

tools/testing/selftests/net/busy_poller.c

66

static uint8_t cfg_prefer_busy_poll;

tools/testing/selftests/net/epoll_busy_poll.c

33

uint8_t prefer_busy_poll;

tools/testing/selftests/net/epoll_busy_poll.c

36

uint8_t __pad;

tools/testing/selftests/net/icmp_rfc4884.c

151

static int build_rfc4884_ext(uint8_t *buf, size_t buflen, bool bad_csum,

tools/testing/selftests/net/icmp_rfc4884.c

183

static int build_orig_dgram_v4(uint8_t *buf, ssize_t buflen, int payload_len)

tools/testing/selftests/net/icmp_rfc4884.c

214

static int build_orig_dgram_v6(uint8_t *buf, ssize_t buflen, int payload_len)

tools/testing/selftests/net/icmp_rfc4884.c

243

static int build_icmpv4_pkt(uint8_t *buf, ssize_t buflen, bool with_ext,

tools/testing/selftests/net/icmp_rfc4884.c

279

static int build_icmpv6_pkt(uint8_t *buf, ssize_t buflen, bool with_ext,

tools/testing/selftests/net/icmp_rfc4884.c

31

static const uint8_t orig_payload_byte = 0xAA;

tools/testing/selftests/net/icmp_rfc4884.c

48

int (*build_func)(uint8_t *buf, ssize_t buflen, bool with_ext,

tools/testing/selftests/net/icmp_rfc4884.c

651

uint8_t pkt[1024];

tools/testing/selftests/net/icmp_rfc4884.c

83

const uint8_t *data = buf;

tools/testing/selftests/net/ip_defrag.c

106

sum = raw_checksum((uint8_t *)&iphdr->ip_src, 2 * sizeof(iphdr->ip_src),

tools/testing/selftests/net/ip_defrag.c

108

sum = raw_checksum((uint8_t *)udphdr, UDP_HLEN, sum);

tools/testing/selftests/net/ip_defrag.c

109

sum = raw_checksum((uint8_t *)udp_payload, payload_len, sum);

tools/testing/selftests/net/ip_defrag.c

122

sum = raw_checksum((uint8_t *)&iphdr->ip6_src, 2 * sizeof(iphdr->ip6_src),

tools/testing/selftests/net/ip_defrag.c

124

sum = raw_checksum((uint8_t *)&udphdr->len, sizeof(udphdr->len), sum);

tools/testing/selftests/net/ip_defrag.c

125

sum = raw_checksum((uint8_t *)udphdr, UDP_HLEN, sum);

tools/testing/selftests/net/ip_defrag.c

126

sum = raw_checksum((uint8_t *)udp_payload, payload_len, sum);

tools/testing/selftests/net/ip_defrag.c

140

uint8_t *frag_start = ipv6 ? ip_frame + IP6_HLEN + FRAG_HLEN :

tools/testing/selftests/net/ip_defrag.c

46

static uint8_t udp_payload[MSG_LEN_MAX];

tools/testing/selftests/net/ip_defrag.c

47

static uint8_t ip_frame[IP_MAXPACKET];

tools/testing/selftests/net/ip_defrag.c

57

static uint8_t recv_buff[MSG_LEN_MAX];

tools/testing/selftests/net/ip_defrag.c

82

static uint32_t raw_checksum(uint8_t *buf, int len, uint32_t sum)

tools/testing/selftests/net/ipsec.c

1105

struct in_addr src, struct in_addr dst, uint8_t dir,

tools/testing/selftests/net/ipsec.c

1106

struct in_addr tunsrc, struct in_addr tundst, uint8_t proto)

tools/testing/selftests/net/ipsec.c

1162

struct in_addr tunsrc, struct in_addr tundst, uint8_t proto)

tools/testing/selftests/net/ipsec.c

1180

struct in_addr src, struct in_addr dst, uint8_t dir,

tools/testing/selftests/net/ipsec.c

1231

struct in_addr src, struct in_addr dst, uint8_t proto)

tools/testing/selftests/net/ipsec.c

1266

struct in_addr tunsrc, struct in_addr tundst, uint8_t proto)

tools/testing/selftests/net/ipsec.c

1282

uint32_t spi, uint8_t proto)

tools/testing/selftests/net/ipsec.c

363

struct in_addr addr, uint8_t prefix)

tools/testing/selftests/net/ipsec.c

543

uint8_t proto;

tools/testing/selftests/net/ipv6_flowlabel.c

175

static void flowlabel_get(int fd, uint32_t label, uint8_t share, uint16_t flags)

tools/testing/selftests/net/ipv6_flowlabel_mgr.c

48

static int flowlabel_get(int fd, uint32_t label, uint8_t share, uint16_t flags)

tools/testing/selftests/net/lib/csum.c

130

uint8_t nexthdr;

tools/testing/selftests/net/lib/csum.c

131

uint8_t padding[3];

tools/testing/selftests/net/lib/csum.c

187

static void *build_packet_ipv4(void *_iph, uint8_t proto, unsigned int len)

tools/testing/selftests/net/lib/csum.c

207

static void *build_packet_ipv6(void *_ip6h, uint8_t proto, unsigned int len)

tools/testing/selftests/net/lib/csum.c

297

uint8_t proto;

tools/testing/selftests/net/mptcp/mptcp_sockopt.c

736

uint8_t tos_in, tos_out;

tools/testing/selftests/net/mptcp/pm_nl_ctl.c

980

uint8_t id;

tools/testing/selftests/net/netfilter/nf_queue.c

122

nfq_build_cfg_request(char *buf, uint8_t command, int queue_num)

tools/testing/selftests/net/netfilter/nf_queue.c

146

nfq_build_cfg_params(char *buf, uint8_t mode, int range, int queue_num)

tools/testing/selftests/net/nettest.c

92

uint8_t dsfield;

tools/testing/selftests/net/ovpn/ovpn-cli.c

1101

nest->rta_len = (uint8_t *)nlmsg_tail(msg) - (uint8_t *)nest;

tools/testing/selftests/net/ovpn/ovpn-cli.c

1327

h = (struct nlmsghdr *)((uint8_t *)h +

tools/testing/selftests/net/ovpn/ovpn-cli.c

1386

&ovpn->mode, sizeof(uint8_t)) < 0)

tools/testing/selftests/net/ovpn/ovpn-cli.c

1840

uint8_t buf[1002];

tools/testing/selftests/net/ovpn/ovpn-cli.c

1855

uint8_t buf[1002];

tools/testing/selftests/net/ovpn/ovpn-cli.c

271

attrs = (void *)((uint8_t *)nlh + ack_len);

tools/testing/selftests/net/psock_fanout.c

483

uint8_t type = typeflags & 0xFF;

tools/testing/selftests/net/psock_tpacket.c

157

((uint8_t *) pay)[i + sizeof(*eth)] = (uint8_t) rand();

tools/testing/selftests/net/psock_tpacket.c

245

test_payload((uint8_t *) ppd.raw + ppd.v1->tp_h.tp_mac,

tools/testing/selftests/net/psock_tpacket.c

251

test_payload((uint8_t *) ppd.raw + ppd.v2->tp_h.tp_mac,

tools/testing/selftests/net/psock_tpacket.c

356

uint8_t *f0 = ring->rd[0].iov_base;

tools/testing/selftests/net/psock_tpacket.c

430

memcpy((uint8_t *) ppd.raw + TPACKET_HDRLEN -

tools/testing/selftests/net/psock_tpacket.c

440

memcpy((uint8_t *) ppd.raw + TPACKET2_HDRLEN -

tools/testing/selftests/net/psock_tpacket.c

452

memcpy((uint8_t *)tx + TPACKET3_HDRLEN -

tools/testing/selftests/net/psock_tpacket.c

551

ppd = (struct tpacket3_hdr *) ((uint8_t *) pbd +

tools/testing/selftests/net/psock_tpacket.c

562

test_payload((uint8_t *) ppd + ppd->tp_mac, ppd->tp_snaplen);

tools/testing/selftests/net/psock_tpacket.c

567

ppd = (struct tpacket3_hdr *) ((uint8_t *) ppd + ppd->tp_next_offset);

tools/testing/selftests/net/psock_tpacket.c

68

uint8_t *mm_space;

tools/testing/selftests/net/tap.c

215

size_t build_eth(uint8_t *buf, uint16_t proto)

tools/testing/selftests/net/tap.c

226

static uint32_t add_csum(const uint8_t *buf, int len)

tools/testing/selftests/net/tap.c

237

sum += *(uint8_t *)sbuf;

tools/testing/selftests/net/tap.c

251

static uint16_t build_ip_csum(const uint8_t *buf, int len,

tools/testing/selftests/net/tap.c

258

static int build_ipv4_header(uint8_t *buf, int payload_len)

tools/testing/selftests/net/tap.c

276

static int build_udp_packet(uint8_t *buf, int payload_len, bool csum_off)

tools/testing/selftests/net/tap.c

300

size_t build_test_packet_valid_udp_gso(uint8_t *buf, size_t payload_len)

tools/testing/selftests/net/tap.c

302

uint8_t *cur = buf;

tools/testing/selftests/net/tap.c

320

size_t build_test_packet_valid_udp_csum(uint8_t *buf, size_t payload_len)

tools/testing/selftests/net/tap.c

322

uint8_t *cur = buf;

tools/testing/selftests/net/tap.c

336

size_t build_test_packet_crash_tap_invalid_eth_proto(uint8_t *buf,

tools/testing/selftests/net/tap.c

339

uint8_t *cur = buf;

tools/testing/selftests/net/tap.c

37

(struct rtattr *)((uint8_t *)nh + RTA_ALIGN(nh->nlmsg_len));

tools/testing/selftests/net/tap.c

393

uint8_t pkt[TEST_PACKET_SZ];

tools/testing/selftests/net/tap.c

405

uint8_t pkt[TEST_PACKET_SZ];

tools/testing/selftests/net/tap.c

417

uint8_t pkt[TEST_PACKET_SZ];

tools/testing/selftests/net/tap.c

51

uint8_t *end = (uint8_t *)nh + nh->nlmsg_len;

tools/testing/selftests/net/tap.c

53

attr->rta_len = end - (uint8_t *)attr;

tools/testing/selftests/net/tcp_ao/connect-deny.c

10

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/connect-deny.c

11

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/connect-deny.c

167

const char *pwd, union tcp_addr addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/connect-deny.c

168

uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/connect-deny.c

33

union tcp_addr addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/connect-deny.c

34

uint8_t sndid, uint8_t rcvid, uint8_t maclen,

tools/testing/selftests/net/tcp_ao/connect-deny.c

9

static inline int test_add_key_maclen(int sk, const char *key, uint8_t maclen,

tools/testing/selftests/net/tcp_ao/icmps-accept.c

179

static void icmp_interfere4(uint8_t type, uint8_t code, uint32_t rcv_nxt,

tools/testing/selftests/net/tcp_ao/icmps-accept.c

271

void *ptr, size_t len, uint8_t proto)

tools/testing/selftests/net/tcp_ao/icmps-accept.c

277

uint8_t zero[3];

tools/testing/selftests/net/tcp_ao/icmps-accept.c

278

uint8_t nexthdr;

tools/testing/selftests/net/tcp_ao/icmps-discard.c

179

static void icmp_interfere4(uint8_t type, uint8_t code, uint32_t rcv_nxt,

tools/testing/selftests/net/tcp_ao/icmps-discard.c

271

void *ptr, size_t len, uint8_t proto)

tools/testing/selftests/net/tcp_ao/icmps-discard.c

277

uint8_t zero[3];

tools/testing/selftests/net/tcp_ao/icmps-discard.c

278

uint8_t nexthdr;

tools/testing/selftests/net/tcp_ao/key-management.c

107

if (current_key >= 0 && ao_info.current_key != (uint8_t)current_key)

tools/testing/selftests/net/tcp_ao/key-management.c

109

if (rnext_key >= 0 && ao_info.rnext != (uint8_t)rnext_key)

tools/testing/selftests/net/tcp_ao/key-management.c

114

static void try_delete_key(char *tst_name, int sk, uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/key-management.c

149

ao_info.current_key = (uint8_t)current_keyid;

tools/testing/selftests/net/tcp_ao/key-management.c

15

static const uint8_t test_vrf_tabid = 42;

tools/testing/selftests/net/tcp_ao/key-management.c

153

ao_info.rnext = (uint8_t)rnext_keyid;

tools/testing/selftests/net/tcp_ao/key-management.c

161

if (current_keyid >= 0 && ao_info.current_key != (uint8_t)current_keyid)

tools/testing/selftests/net/tcp_ao/key-management.c

163

if (rnext_keyid >= 0 && ao_info.rnext != (uint8_t)rnext_keyid)

tools/testing/selftests/net/tcp_ao/key-management.c

168

static int test_add_current_rnext_key(int sk, const char *key, uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/key-management.c

169

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/key-management.c

171

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/key-management.c

191

static int __try_add_current_rnext_key(int sk, const char *key, uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/key-management.c

192

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/key-management.c

194

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/key-management.c

214

uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/key-management.c

215

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/key-management.c

217

uint8_t sndid, uint8_t rcvid, fault_t inj)

tools/testing/selftests/net/tcp_ao/key-management.c

38

static int prepare_sk(union tcp_addr *addr, uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/key-management.c

412

uint8_t client_keyid;

tools/testing/selftests/net/tcp_ao/key-management.c

413

uint8_t server_keyid;

tools/testing/selftests/net/tcp_ao/key-management.c

414

uint8_t maclen;

tools/testing/selftests/net/tcp_ao/key-management.c

415

uint8_t matches_client : 1,

tools/testing/selftests/net/tcp_ao/key-management.c

522

union tcp_addr addr, uint8_t vrf,

tools/testing/selftests/net/tcp_ao/key-management.c

523

uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/key-management.c

524

uint8_t maclen, const char *alg,

tools/testing/selftests/net/tcp_ao/key-management.c

528

uint8_t keyflags = 0;

tools/testing/selftests/net/tcp_ao/key-management.c

56

static int prepare_lsk(union tcp_addr *addr, uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/key-management.c

595

uint8_t sndid, rcvid, vrf;

tools/testing/selftests/net/tcp_ao/key-management.c

640

uint8_t sndid, rcvid;

tools/testing/selftests/net/tcp_ao/key-management.c

66

static int test_del_key(int sk, uint8_t sndid, uint8_t rcvid, bool async,

tools/testing/selftests/net/tcp_ao/key-management.c

704

uint8_t sndid, rcvid;

tools/testing/selftests/net/tcp_ao/key-management.c

82

del.current_key = (uint8_t)current_key;

tools/testing/selftests/net/tcp_ao/key-management.c

86

del.rnext = (uint8_t)rnext_key;

tools/testing/selftests/net/tcp_ao/lib/aolib.h

281

union tcp_addr addr, uint8_t prefix);

tools/testing/selftests/net/tcp_ao/lib/aolib.h

286

uint8_t vrf);

tools/testing/selftests/net/tcp_ao/lib/aolib.h

357

uint8_t prefix, int vrf, const char *password);

tools/testing/selftests/net/tcp_ao/lib/aolib.h

359

uint8_t prefix, int vrf, const char *password)

tools/testing/selftests/net/tcp_ao/lib/aolib.h

373

uint8_t prefix, uint8_t vrf,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

374

uint8_t sndid, uint8_t rcvid, uint8_t maclen,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

375

uint8_t keyflags, uint8_t keylen, const char *key);

tools/testing/selftests/net/tcp_ao/lib/aolib.h

380

uint8_t prefix, uint8_t vrf,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

381

uint8_t sndid, uint8_t rcvid, uint8_t maclen,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

382

uint8_t keyflags, uint8_t keylen, const char *key)

tools/testing/selftests/net/tcp_ao/lib/aolib.h

393

const char *key, uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

394

union tcp_addr in_addr, uint8_t prefix, uint8_t vrf,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

395

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/lib/aolib.h

407

uint8_t prefix, uint8_t sndid, uint8_t rcvid);

tools/testing/selftests/net/tcp_ao/lib/aolib.h

429

const char *key, uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

430

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

431

uint8_t vrf, uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/lib/aolib.h

449

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

450

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/lib/aolib.h

490

uint8_t sndid;

tools/testing/selftests/net/tcp_ao/lib/aolib.h

491

uint8_t rcvid;

tools/testing/selftests/net/tcp_ao/lib/aolib.h

701

const char *key, uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

702

union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/lib/aolib.h

703

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/lib/netlink.c

198

int family, union tcp_addr addr, uint8_t prefix)

tools/testing/selftests/net/tcp_ao/lib/netlink.c

230

union tcp_addr addr, uint8_t prefix)

tools/testing/selftests/net/tcp_ao/lib/netlink.c

246

union tcp_addr src, union tcp_addr dst, uint8_t vrf)

tools/testing/selftests/net/tcp_ao/lib/netlink.c

287

union tcp_addr src, union tcp_addr dst, uint8_t vrf)

tools/testing/selftests/net/tcp_ao/lib/setup.c

164

static void link_init(const char *veth, int family, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/lib/sock.c

187

int __test_set_md5(int sk, void *addr, size_t addr_sz, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/lib/sock.c

199

md5sig.tcpm_ifindex = (uint8_t)vrf;

tools/testing/selftests/net/tcp_ao/lib/sock.c

211

uint8_t prefix, uint8_t vrf, uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/lib/sock.c

212

uint8_t maclen, uint8_t keyflags,

tools/testing/selftests/net/tcp_ao/lib/sock.c

213

uint8_t keylen, const char *key)

tools/testing/selftests/net/tcp_ao/lib/sock.c

254

void *addr, size_t addr_sz, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/lib/sock.c

255

uint8_t sndid, uint8_t rcvid)

tools/testing/selftests/net/tcp_ao/self-connect.c

9

const char *addr_str, uint8_t prefix)

tools/testing/selftests/net/tcp_ao/setsockopt-closed.c

323

ao.keyflags = (uint8_t)(-1);

tools/testing/selftests/net/tcp_ao/setsockopt-closed.c

417

del.keyflags = (uint8_t)(-1);

tools/testing/selftests/net/tcp_ao/setsockopt-closed.c

623

out.keyflags = (uint8_t)(-1);

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

15

static const uint8_t test_vrf_tabid = 42;

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

265

union tcp_addr *md5_addr, uint8_t md5_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

266

union tcp_addr *ao_addr, uint8_t ao_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

267

uint8_t sndid, uint8_t rcvid, uint8_t vrf,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

324

static int try_add_key_vrf(int sk, union tcp_addr in_addr, uint8_t prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

325

int vrf, uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

328

uint8_t keyflags = 0;

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

341

(uint8_t)vrf, sndid, rcvid);

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

369

union tcp_addr md5_addr, uint8_t md5_prefix, int md5_vrf,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

370

union tcp_addr ao_addr, uint8_t ao_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

372

uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

38

union tcp_addr *md5_addr, uint8_t md5_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

39

union tcp_addr *ao_addr, uint8_t ao_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

41

uint8_t sndid, uint8_t rcvid, uint8_t vrf,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

413

union tcp_addr md5_addr, uint8_t md5_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

415

union tcp_addr ao_addr, uint8_t ao_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

417

uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

439

union tcp_addr md5_addr, uint8_t md5_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

441

union tcp_addr ao_addr, uint8_t ao_prefix,

tools/testing/selftests/net/tcp_ao/unsigned-md5.c

442

int ao_vrf, uint8_t sndid, uint8_t rcvid,

tools/testing/selftests/net/tun.c

122

uint8_t csum;

tools/testing/selftests/net/tun.c

350

*(uint8_t *)rtm_type = rsp->_hdr.rtm_type;

tools/testing/selftests/net/tun.c

355

uint8_t rtm_type, table = RT_TABLE_LOCAL;

tools/testing/selftests/net/tun.c

374

uint8_t *send_buf, int send_len, int gso_size)

tools/testing/selftests/net/tun.c

410

static int validate_hdrlen(uint8_t **cur, int *len, int x)

tools/testing/selftests/net/tun.c

419

static int parse_udp_tunnel_vnet_packet(uint8_t *buf, int len, int tunnel_type,

tools/testing/selftests/net/tun.c

425

uint8_t *cur = buf;

tools/testing/selftests/net/tun.c

790

uint8_t *buf)

tools/testing/selftests/net/tun.c

796

uint8_t *outer_udph, *cur = buf;

tools/testing/selftests/net/tun.c

854

uint8_t packet_buf[MAX_VNET_TUNNEL_PACKET_SZ];

tools/testing/selftests/net/tun.c

879

uint8_t buf[MAX_VNET_TUNNEL_PACKET_SZ] = { 0 };

tools/testing/selftests/net/tun.c

894

uint8_t buf[MAX_VNET_TUNNEL_PACKET_SZ];

tools/testing/selftests/net/tun.c

937

uint8_t pkt[MAX_VNET_TUNNEL_PACKET_SZ];

tools/testing/selftests/net/tuntap_helpers.h

218

static inline size_t build_eth(uint8_t *buf, uint16_t proto, unsigned char *src,

tools/testing/selftests/net/tuntap_helpers.h

230

static inline uint32_t add_csum(const uint8_t *buf, int len)

tools/testing/selftests/net/tuntap_helpers.h

241

sum += *(uint8_t *)sbuf;

tools/testing/selftests/net/tuntap_helpers.h

253

static inline uint16_t build_ip_csum(const uint8_t *buf, int len, uint32_t sum)

tools/testing/selftests/net/tuntap_helpers.h

259

static inline int build_ipv4_header(uint8_t *buf, uint8_t proto,

tools/testing/selftests/net/tuntap_helpers.h

278

static inline void ipv6_set_dsfield(struct ipv6hdr *ip6h, uint8_t dsfield)

tools/testing/selftests/net/tuntap_helpers.h

288

static inline int build_ipv6_header(uint8_t *buf, uint8_t proto,

tools/testing/selftests/net/tuntap_helpers.h

289

uint8_t dsfield, int payload_len,

tools/testing/selftests/net/tuntap_helpers.h

305

static inline int build_geneve_header(uint8_t *buf, uint32_t vni)

tools/testing/selftests/net/tuntap_helpers.h

315

static inline int build_udp_header(uint8_t *buf, uint16_t sport, uint16_t dport,

tools/testing/selftests/net/tuntap_helpers.h

326

static inline void build_udp_packet_csum(uint8_t *buf, int family,

tools/testing/selftests/net/tuntap_helpers.h

343

static inline int build_udp_packet(uint8_t *buf, uint16_t sport, uint16_t dport,

tools/testing/selftests/net/tuntap_helpers.h

355

static inline int build_virtio_net_hdr_v1_hash_tunnel(uint8_t *buf, bool is_tap,

tools/testing/selftests/net/tuntap_helpers.h

48

uint8_t prefix)

tools/testing/selftests/nolibc/nolibc-test.c

1569

CASE_TEST(limit_uint8_max); EXPECT_EQ(1, UINT8_MAX, (uint8_t) 0xff); break;

tools/testing/selftests/powerpc/include/utils.h

32

typedef uint8_t u8;

tools/testing/selftests/powerpc/tm/tm-signal-context-chk-vsx.c

60

uint8_t vsx[sizeof(vector int)];

tools/testing/selftests/powerpc/tm/tm-signal-context-chk-vsx.c

61

uint8_t vsx_tm[sizeof(vector int)];

tools/testing/selftests/powerpc/tm/tm-trap.c

292

le = (int) *(uint8_t *)&k;

tools/testing/selftests/proc/proc-pid-vm.c

132

static const uint8_t payload[] = {

tools/testing/selftests/proc/proc-pid-vm.c

155

static int make_exe(const uint8_t *payload, size_t len)

tools/testing/selftests/proc/proc-pid-vm.c

86

uint8_t e_ident[16];

tools/testing/selftests/sgx/sigstruct.c

196

static bool mrenclave_commit(EVP_MD_CTX *ctx, uint8_t *mrenclave)

tools/testing/selftests/sgx/sigstruct.c

217

uint8_t reserved[44];

tools/testing/selftests/sgx/sigstruct.c

244

uint8_t reserved[40];

tools/testing/selftests/sgx/sigstruct.c

262

uint8_t reserved[48];

tools/testing/selftests/sgx/sigstruct.c

266

const uint8_t *data)

tools/testing/selftests/sgx/sigstruct.c

320

uint8_t digest[SHA256_DIGEST_LENGTH];

tools/testing/selftests/sgx/sigstruct.c

45

static bool alloc_q1q2_ctx(const uint8_t *s, const uint8_t *m,

tools/testing/selftests/sgx/sigstruct.c

68

uint8_t temp;

tools/testing/selftests/sgx/sigstruct.c

69

uint8_t *ptr = data;

tools/testing/selftests/sgx/sigstruct.c

80

static bool calc_q1q2(const uint8_t *s, const uint8_t *m, uint8_t *q1,

tools/testing/selftests/sgx/sigstruct.c

81

uint8_t *q2)

tools/testing/selftests/sgx/test_encl.c

13

static uint8_t __used __section(".data.encl_buffer") encl_buffer[8192] = { 1 };

tools/testing/selftests/sgx/test_encl.c

132

extern const uint8_t __attribute__((visibility("hidden"))) __encl_base;

tools/testing/selftests/vDSO/vdso_test_chacha.c

37

static void reference_chacha20_blocks(uint8_t *dst_bytes, const uint32_t *key, uint32_t *counter, size_t nblocks)

tools/testing/selftests/vDSO/vdso_test_chacha.c

77

void __weak __arch_chacha20_blocks_nostack(uint8_t *dst_bytes, const uint32_t *key, uint32_t *counter, size_t nblocks)

tools/testing/selftests/vDSO/vdso_test_chacha.c

87

uint8_t output1[BLOCK_SIZE * BLOCKS], output2[BLOCK_SIZE * BLOCKS];

tools/testing/selftests/vDSO/vdso_test_getrandom.c

234

uint8_t weird_size[323929];

tools/testing/selftests/vDSO/vdso_test_getrandom.c

241

uint8_t weird_size[1263];

tools/testing/selftests/vfio/lib/drivers/ioat/hw.h

184

uint8_t coef[8];

tools/testing/selftests/vfio/lib/drivers/ioat/hw.h

234

uint8_t coef[8];

tools/testing/selftests/x86/corrupt_xstate_header.c

36

uint8_t *fpstate = (uint8_t *)uc->uc_mcontext.fpregs;

tools/testing/selftests/x86/lam.c

1089

uint8_t file_Exists(const char *fileName)

tools/testing/selftests/x86/lam.c

1093

uint8_t ret = (stat(fileName, &buffer) == 0);

tools/testing/vsock/util.c

443

static const uint8_t byte = 'A';

tools/testing/vsock/util.c

457

uint8_t byte;

tools/testing/vsock/util.c

702

((uint8_t *)iovec[i].iov_base)[j] = rand() & 0xff;

tools/usb/usbip/libsrc/usbip_common.c

211

READ_ATTR(udev, uint8_t, sdev, bDeviceClass, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

212

READ_ATTR(udev, uint8_t, sdev, bDeviceSubClass, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

213

READ_ATTR(udev, uint8_t, sdev, bDeviceProtocol, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

219

READ_ATTR(udev, uint8_t, sdev, bConfigurationValue, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

220

READ_ATTR(udev, uint8_t, sdev, bNumConfigurations, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

221

READ_ATTR(udev, uint8_t, sdev, bNumInterfaces, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

223

READ_ATTR(udev, uint8_t, sdev, devnum, "%d\n");

tools/usb/usbip/libsrc/usbip_common.c

261

READ_ATTR(uinf, uint8_t, sif, bInterfaceClass, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

262

READ_ATTR(uinf, uint8_t, sif, bInterfaceSubClass, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

263

READ_ATTR(uinf, uint8_t, sif, bInterfaceProtocol, "%02x\n");

tools/usb/usbip/libsrc/usbip_common.c

295

void usbip_names_get_class(char *buff, size_t size, uint8_t class,

tools/usb/usbip/libsrc/usbip_common.c

296

uint8_t subclass, uint8_t protocol)

tools/usb/usbip/libsrc/usbip_common.h

105

uint8_t bInterfaceClass;

tools/usb/usbip/libsrc/usbip_common.h

106

uint8_t bInterfaceSubClass;

tools/usb/usbip/libsrc/usbip_common.h

107

uint8_t bInterfaceProtocol;

tools/usb/usbip/libsrc/usbip_common.h

108

uint8_t padding; /* alignment */

tools/usb/usbip/libsrc/usbip_common.h

123

uint8_t bDeviceClass;

tools/usb/usbip/libsrc/usbip_common.h

124

uint8_t bDeviceSubClass;

tools/usb/usbip/libsrc/usbip_common.h

125

uint8_t bDeviceProtocol;

tools/usb/usbip/libsrc/usbip_common.h

126

uint8_t bConfigurationValue;

tools/usb/usbip/libsrc/usbip_common.h

127

uint8_t bNumConfigurations;

tools/usb/usbip/libsrc/usbip_common.h

128

uint8_t bNumInterfaces;

tools/usb/usbip/libsrc/usbip_common.h

149

void usbip_names_get_class(char *buff, size_t size, uint8_t class,

tools/usb/usbip/libsrc/usbip_common.h

150

uint8_t subclass, uint8_t protocol);

tools/usb/usbip/libsrc/vhci_driver.c

357

int usbip_vhci_attach_device2(uint8_t port, int sockfd, uint32_t devid,

tools/usb/usbip/libsrc/vhci_driver.c

385

static unsigned long get_devid(uint8_t busnum, uint8_t devnum)

tools/usb/usbip/libsrc/vhci_driver.c

391

int usbip_vhci_attach_device(uint8_t port, int sockfd, uint8_t busnum,

tools/usb/usbip/libsrc/vhci_driver.c

392

uint8_t devnum, uint32_t speed)

tools/usb/usbip/libsrc/vhci_driver.c

399

int usbip_vhci_detach_device(uint8_t port)

tools/usb/usbip/libsrc/vhci_driver.h

24

uint8_t port;

tools/usb/usbip/libsrc/vhci_driver.h

29

uint8_t busnum;

tools/usb/usbip/libsrc/vhci_driver.h

30

uint8_t devnum;

tools/usb/usbip/libsrc/vhci_driver.h

56

int usbip_vhci_attach_device2(uint8_t port, int sockfd, uint32_t devid,

tools/usb/usbip/libsrc/vhci_driver.h

60

int usbip_vhci_attach_device(uint8_t port, int sockfd, uint8_t busnum,

tools/usb/usbip/libsrc/vhci_driver.h

61

uint8_t devnum, uint32_t speed);

tools/usb/usbip/libsrc/vhci_driver.h

63

int usbip_vhci_detach_device(uint8_t port);

tools/usb/usbip/src/usbip_detach.c

35

uint8_t portnum;