#include "smu_types.h"
#define SWSMU_CODE_LAYER_L2
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_v15_0.h"
#include "smu15_driver_if_v15_0_0.h"
#include "smu_v15_0_0_ppt.h"
#include "smu_v15_0_0_ppsmc.h"
#include "smu_v15_0_0_pmfw.h"
#include "smu_cmn.h"
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug
#define mmMP1_SMN_C2PMSG_30 0x005e
#define mmMP1_SMN_C2PMSG_30_BASE_IDX 1
#define mmMP1_SMN_C2PMSG_31 0x005f
#define mmMP1_SMN_C2PMSG_31_BASE_IDX 1
#define mmMP1_SMN_C2PMSG_32 0x0060
#define mmMP1_SMN_C2PMSG_32_BASE_IDX 1
#define mmMP1_SMN_C2PMSG_33 0x0061
#define mmMP1_SMN_C2PMSG_33_BASE_IDX 1
#define mmMP1_SMN_C2PMSG_34 0x0062
#define mmMP1_SMN_C2PMSG_34_BASE_IDX 1
#define SMU_15_0_UMD_PSTATE_GFXCLK 700
#define SMU_15_0_UMD_PSTATE_SOCCLK 678
#define SMU_15_0_UMD_PSTATE_FCLK 1800
static const struct smu_feature_bits smu_v15_0_0_dpm_features = {
.bits = {
SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_NPU_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT),
SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT)
}
};
enum smu_mall_pg_config {
SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0,
SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON = 1,
SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_OFF = 2,
};
static struct cmn2asic_msg_mapping smu_v15_0_0_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1),
MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 1),
MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1),
MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
MSG_MAP(AllowZstates, PPSMC_MSG_AllowZstates, 1),
MSG_MAP(GetSmartShiftStatus, PPSMC_MSG_GetSmartShiftStatus, 1),
MSG_MAP(PowerUpUmsch, PPSMC_MSG_PowerUpUmsch, 1),
MSG_MAP(PowerDownUmsch, PPSMC_MSG_PowerDownUmsch, 1),
MSG_MAP(PowerUpVpe, PPSMC_MSG_PowerUpVpe, 1),
MSG_MAP(PowerDownVpe, PPSMC_MSG_PowerDownVpe, 1),
MSG_MAP(EnableLSdma, PPSMC_MSG_EnableLSdma, 1),
MSG_MAP(DisableLSdma, PPSMC_MSG_DisableLSdma, 1),
MSG_MAP(SetSoftMaxVpe, PPSMC_MSG_SetSoftMaxVpe, 1),
MSG_MAP(SetSoftMinVpe, PPSMC_MSG_SetSoftMinVpe, 1),
};
static struct cmn2asic_mapping smu_v15_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(CCLK_DPM),
FEA_MAP(FAN_CONTROLLER),
FEA_MAP(PPT),
FEA_MAP(TDC),
FEA_MAP(THERMAL),
FEA_MAP(VCN_DPM),
FEA_MAP_REVERSE(FCLK),
FEA_MAP_REVERSE(SOCCLK),
FEA_MAP(LCLK_DPM),
FEA_MAP(SHUBCLK_DPM),
FEA_MAP(DCFCLK_DPM),
FEA_MAP_HALF_REVERSE(GFX),
FEA_MAP(DS_GFXCLK),
FEA_MAP(DS_SOCCLK),
FEA_MAP(DS_LCLK),
FEA_MAP(LOW_POWER_DCNCLKS),
FEA_MAP(DS_FCLK),
FEA_MAP(DS_MP1CLK),
FEA_MAP(PSI),
FEA_MAP(PROCHOT),
FEA_MAP(CPUOFF),
FEA_MAP(STAPM),
FEA_MAP(S0I3),
FEA_MAP(PERF_LIMIT),
FEA_MAP(CORE_DLDO),
FEA_MAP(DS_VCN),
FEA_MAP(CPPC),
FEA_MAP(DF_CSTATES),
FEA_MAP(ATHUB_PG),
};
static struct cmn2asic_mapping smu_v15_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP_VALID(WATERMARKS),
TAB_MAP_VALID(SMU_METRICS),
TAB_MAP_VALID(CUSTOM_DPM),
TAB_MAP_VALID(DPMCLOCKS),
};
static int smu_v15_0_0_init_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *tables = smu_table->tables;
int ret;
SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
smu_table->metrics_table = kzalloc_obj(SmuMetrics_t);
if (!smu_table->metrics_table)
goto err0_out;
smu_table->metrics_time = 0;
smu_table->clocks_table = kzalloc_obj(DpmClocks_t);
if (!smu_table->clocks_table)
goto err1_out;
smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
if (!smu_table->watermarks_table)
goto err2_out;
ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
sizeof(struct gpu_metrics_v3_0),
SMU_GPU_METRICS_CACHE_INTERVAL);
if (ret)
goto err3_out;
return 0;
err3_out:
kfree(smu_table->watermarks_table);
err2_out:
kfree(smu_table->clocks_table);
err1_out:
kfree(smu_table->metrics_table);
err0_out:
return -ENOMEM;
}
static int smu_v15_0_0_fini_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
kfree(smu_table->clocks_table);
smu_table->clocks_table = NULL;
kfree(smu_table->metrics_table);
smu_table->metrics_table = NULL;
kfree(smu_table->watermarks_table);
smu_table->watermarks_table = NULL;
smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
return 0;
}
static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (!en && !adev->in_s0ix)
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
return ret;
}
static int smu_v15_0_0_update_table(struct smu_context *smu,
enum smu_table_id table_index,
int argument,
void *table_data,
bool drv2smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct amdgpu_device *adev = smu->adev;
struct smu_table *table = &smu_table->driver_table;
int table_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_TABLE,
table_index);
uint64_t address;
uint32_t table_size;
int ret;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
return -EINVAL;
table_size = smu_table->tables[table_index].size;
if (drv2smu) {
memcpy(table->cpu_addr, table_data, table_size);
amdgpu_hdp_flush(adev, NULL);
}
address = table->mc_address;
struct smu_msg_args args = {
.msg = drv2smu ?
SMU_MSG_TransferTableDram2Smu :
SMU_MSG_TransferTableSmu2Dram,
.num_args = 3,
.num_out_args = 0,
};
args.args[0] = table_id;
args.args[1] = (uint32_t)lower_32_bits(address);
args.args[2] = (uint32_t)upper_32_bits(address);
ret = ctl->ops->send_msg(ctl, &args);
if (ret)
return ret;
if (!drv2smu) {
amdgpu_hdp_invalidate(adev, NULL);
memcpy(table_data, table->cpu_addr, table_size);
}
return 0;
}
static int smu_v15_0_0_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
static int smu_v15_0_0_get_metrics_table(struct smu_context *smu,
void *metrics_table,
bool bypass_cache)
{
struct smu_table_context *smu_table = &smu->smu_table;
uint32_t table_size =
smu_table->tables[SMU_TABLE_SMU_METRICS].size;
int ret;
if (bypass_cache ||
!smu_table->metrics_time ||
time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
ret = smu_v15_0_0_update_table(smu,
SMU_TABLE_SMU_METRICS,
0,
smu_table->metrics_table,
false);
if (ret) {
dev_info(smu->adev->dev, "Failed to export SMU15_0_0 metrics table!\n");
return ret;
}
smu_table->metrics_time = jiffies;
}
if (metrics_table)
memcpy(metrics_table, smu_table->metrics_table, table_size);
return 0;
}
static int smu_v15_0_0_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
int ret = 0;
ret = smu_v15_0_0_get_metrics_table(smu, NULL, false);
if (ret)
return ret;
switch (member) {
case METRICS_AVERAGE_GFXCLK:
*value = metrics->GfxclkFrequency;
break;
case METRICS_AVERAGE_SOCCLK:
*value = metrics->SocclkFrequency;
break;
case METRICS_AVERAGE_VCLK:
*value = metrics->VclkFrequency;
break;
case METRICS_AVERAGE_DCLK:
*value = 0;
break;
case METRICS_AVERAGE_UCLK:
*value = metrics->MemclkFrequency;
break;
case METRICS_AVERAGE_FCLK:
*value = metrics->FclkFrequency;
break;
case METRICS_AVERAGE_VPECLK:
*value = metrics->VpeclkFrequency;
break;
case METRICS_AVERAGE_NPUCLK:
*value = metrics->NpuclkFrequency;
break;
case METRICS_AVERAGE_GFXACTIVITY:
if ((smu->smc_fw_version > 0x5d4600))
*value = metrics->GfxActivity;
else
*value = metrics->GfxActivity / 100;
break;
case METRICS_AVERAGE_VCNACTIVITY:
*value = metrics->VcnActivity / 100;
break;
case METRICS_AVERAGE_SOCKETPOWER:
case METRICS_CURR_SOCKETPOWER:
*value = (metrics->SocketPower / 1000 << 8) +
(metrics->SocketPower % 1000 / 10);
break;
case METRICS_TEMPERATURE_EDGE:
*value = metrics->GfxTemperature / 100 *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
case METRICS_TEMPERATURE_HOTSPOT:
*value = metrics->SocTemperature / 100 *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
case METRICS_THROTTLER_RESIDENCY_PROCHOT:
*value = metrics->ThrottleResidency_PROCHOT;
break;
case METRICS_THROTTLER_RESIDENCY_SPL:
*value = metrics->ThrottleResidency_SPL;
break;
case METRICS_THROTTLER_RESIDENCY_FPPT:
*value = metrics->ThrottleResidency_FPPT;
break;
case METRICS_THROTTLER_RESIDENCY_SPPT:
*value = metrics->ThrottleResidency_SPPT;
break;
case METRICS_THROTTLER_RESIDENCY_THM_SOC:
*value = metrics->ThrottleResidency_THM_SOC;
break;
case METRICS_VOLTAGE_VDDGFX:
*value = 0;
break;
case METRICS_VOLTAGE_VDDSOC:
*value = 0;
break;
case METRICS_SS_APU_SHARE:
if (metrics->StapmOpnLimit > 0)
*value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
else
*value = 0;
break;
case METRICS_SS_DGPU_SHARE:
if ((metrics->dGpuPower > 0) &&
(metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
*value = (metrics->dGpuPower * 100) /
(metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
else
*value = 0;
break;
default:
*value = UINT_MAX;
break;
}
return ret;
}
static int smu_v15_0_0_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
int ret = 0;
if (!data || !size)
return -EINVAL;
switch (sensor) {
case AMDGPU_PP_SENSOR_GPU_LOAD:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_AVERAGE_GFXACTIVITY,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_VCN_LOAD:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_AVERAGE_VCNACTIVITY,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_AVERAGE_SOCKETPOWER,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_CURR_SOCKETPOWER,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_EDGE_TEMP:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_TEMPERATURE_EDGE,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_TEMPERATURE_HOTSPOT,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_AVERAGE_UCLK,
(uint32_t *)data);
*(uint32_t *)data *= 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_SCLK:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_AVERAGE_GFXCLK,
(uint32_t *)data);
*(uint32_t *)data *= 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_VDDGFX:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_VOLTAGE_VDDGFX,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_VDDNB:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_VOLTAGE_VDDSOC,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_SS_APU_SHARE:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_SS_APU_SHARE,
(uint32_t *)data);
*size = 4;
break;
case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
ret = smu_v15_0_0_get_smu_metrics_data(smu,
METRICS_SS_DGPU_SHARE,
(uint32_t *)data);
*size = 4;
break;
default:
ret = -EOPNOTSUPP;
break;
}
return ret;
}
static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu,
struct smu_feature_bits *feature_mask)
{
int ret;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
if (!feature_mask)
return -EINVAL;
struct smu_msg_args args = {
.msg = SMU_MSG_GetEnabledSmuFeatures,
.num_args = 0,
.num_out_args = 2,
};
ret = ctl->ops->send_msg(ctl, &args);
if (!ret)
smu_feature_bits_from_arr32(feature_mask, args.out_args,
SMU_FEATURE_NUM_DEFAULT);
return ret;
}
static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
struct smu_feature_bits feature_enabled;
ret = smu_v15_0_0_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
return smu_feature_bits_test_mask(&feature_enabled,
smu_v15_0_0_dpm_features.bits);
}
static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu,
struct pp_smu_wm_range_sets *clock_ranges)
{
int i;
int ret = 0;
Watermarks_t *table = smu->smu_table.watermarks_table;
if (!table || !clock_ranges)
return -EINVAL;
if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
return -EINVAL;
for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
table->WatermarkRow[WM_DCFCLK][i].MinClock =
clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].MaxClock =
clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].MinMclk =
clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
table->WatermarkRow[WM_DCFCLK][i].WmSetting =
clock_ranges->reader_wm_sets[i].wm_inst;
}
for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
table->WatermarkRow[WM_SOCCLK][i].MinClock =
clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxClock =
clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MinMclk =
clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
table->WatermarkRow[WM_SOCCLK][i].WmSetting =
clock_ranges->writer_wm_sets[i].wm_inst;
}
smu->watermarks_bitmap |= WATERMARKS_EXIST;
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
ret = smu_cmn_write_watermarks_table(smu);
if (ret) {
dev_err(smu->adev->dev, "Failed to update WMTABLE!");
return ret;
}
smu->watermarks_bitmap |= WATERMARKS_LOADED;
}
return 0;
}
static ssize_t smu_v15_0_0_get_gpu_metrics(struct smu_context *smu,
void **table)
{
struct gpu_metrics_v3_0 *gpu_metrics =
(struct gpu_metrics_v3_0 *)smu_driver_table_ptr(
smu, SMU_DRIVER_TABLE_GPU_METRICS);
SmuMetrics_t metrics;
int ret = 0;
ret = smu_v15_0_0_get_metrics_table(smu, &metrics, false);
if (ret)
return ret;
smu_cmn_init_soft_gpu_metrics(gpu_metrics, 3, 0);
gpu_metrics->temperature_gfx = metrics.GfxTemperature;
gpu_metrics->temperature_soc = metrics.SocTemperature;
memcpy(&gpu_metrics->temperature_core[0],
&metrics.CoreTemperature[0],
sizeof(uint16_t) * 16);
gpu_metrics->temperature_skin = metrics.SkinTemp;
gpu_metrics->average_gfx_activity = metrics.GfxActivity;
gpu_metrics->average_vcn_activity = metrics.VcnActivity;
memcpy(&gpu_metrics->average_core_c0_activity[0],
&metrics.CoreC0Residency[0],
sizeof(uint16_t) * 16);
gpu_metrics->average_dram_reads = metrics.DRAMReads;
gpu_metrics->average_dram_writes = metrics.DRAMWrites;
gpu_metrics->average_socket_power = metrics.SocketPower;
gpu_metrics->average_apu_power = metrics.ApuPower;
gpu_metrics->average_gfx_power = metrics.GfxPower;
gpu_metrics->average_dgpu_power = metrics.dGpuPower;
gpu_metrics->average_all_core_power = metrics.AllCorePower;
gpu_metrics->average_sys_power = metrics.Psys;
memcpy(&gpu_metrics->average_core_power[0],
&metrics.CorePower[0],
sizeof(uint16_t) * 16);
gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
gpu_metrics->average_vpeclk_frequency = metrics.VpeclkFrequency;
gpu_metrics->average_fclk_frequency = metrics.FclkFrequency;
gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
memcpy(&gpu_metrics->current_coreclk[0],
&metrics.CoreFrequency[0],
sizeof(uint16_t) * 16);
gpu_metrics->current_core_maxfreq = metrics.InfrastructureCpuMaxFreq;
gpu_metrics->current_gfx_maxfreq = metrics.InfrastructureGfxMaxFreq;
gpu_metrics->throttle_residency_prochot = metrics.ThrottleResidency_PROCHOT;
gpu_metrics->throttle_residency_spl = metrics.ThrottleResidency_SPL;
gpu_metrics->throttle_residency_fppt = metrics.ThrottleResidency_FPPT;
gpu_metrics->throttle_residency_sppt = metrics.ThrottleResidency_SPPT;
gpu_metrics->throttle_residency_thm_soc = metrics.ThrottleResidency_THM_SOC;
gpu_metrics->time_filter_alphavalue = metrics.FilterAlphaValue;
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
*table = (void *)gpu_metrics;
smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
return sizeof(struct gpu_metrics_v3_0);
}
static int smu_v15_0_0_mode2_reset(struct smu_context *smu)
{
int ret;
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
SMU_RESET_MODE_2, NULL);
if (ret)
dev_err(smu->adev->dev, "Failed to mode2 reset!\n");
return ret;
}
static int smu_v15_0_0_get_dpm_freq_by_index(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t dpm_level,
uint32_t *freq)
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
if (!clk_table || clk_type >= SMU_CLK_COUNT)
return -EINVAL;
switch (clk_type) {
case SMU_SOCCLK:
if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
return -EINVAL;
*freq = clk_table->SocClocks[dpm_level];
break;
case SMU_VCLK:
if (dpm_level >= clk_table->VcnClkLevelsEnabled)
return -EINVAL;
*freq = clk_table->VClocks[dpm_level];
break;
case SMU_DCLK:
if (dpm_level >= clk_table->VcnClkLevelsEnabled)
return -EINVAL;
*freq = clk_table->DClocks[dpm_level];
break;
case SMU_UCLK:
case SMU_MCLK:
if (dpm_level >= clk_table->NumMemPstatesEnabled)
return -EINVAL;
*freq = clk_table->MemPstateTable[dpm_level].MemClk;
break;
case SMU_FCLK:
if (dpm_level >= clk_table->NumFclkLevelsEnabled)
return -EINVAL;
*freq = clk_table->FclkClocks_Freq[dpm_level];
break;
default:
return -EINVAL;
}
return 0;
}
static int smu_v15_0_common_get_dpm_freq_by_index(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t dpm_level,
uint32_t *freq)
{
smu_v15_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
return 0;
}
static bool smu_v15_0_0_clk_dpm_is_enabled(struct smu_context *smu,
enum smu_clk_type clk_type)
{
enum smu_feature_mask feature_id = 0;
switch (clk_type) {
case SMU_MCLK:
case SMU_UCLK:
case SMU_FCLK:
feature_id = SMU_FEATURE_DPM_FCLK_BIT;
break;
case SMU_GFXCLK:
case SMU_SCLK:
feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
break;
case SMU_SOCCLK:
feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
break;
case SMU_VCLK:
case SMU_DCLK:
case SMU_VCLK1:
case SMU_DCLK1:
feature_id = SMU_FEATURE_VCN_DPM_BIT;
break;
default:
return true;
}
return smu_cmn_feature_is_enabled(smu, feature_id);
}
static int smu_v15_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min,
uint32_t *max)
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
uint32_t clock_limit;
uint32_t max_dpm_level, min_dpm_level;
int ret = 0;
if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type)) {
switch (clk_type) {
case SMU_MCLK:
case SMU_UCLK:
clock_limit = smu->smu_table.boot_values.uclk;
break;
case SMU_FCLK:
clock_limit = smu->smu_table.boot_values.fclk;
break;
case SMU_GFXCLK:
case SMU_SCLK:
clock_limit = smu->smu_table.boot_values.gfxclk;
break;
case SMU_SOCCLK:
clock_limit = smu->smu_table.boot_values.socclk;
break;
case SMU_VCLK:
clock_limit = smu->smu_table.boot_values.vclk;
break;
case SMU_DCLK:
clock_limit = smu->smu_table.boot_values.dclk;
break;
default:
clock_limit = 0;
break;
}
if (min)
*min = clock_limit / 100;
if (max)
*max = clock_limit / 100;
return 0;
}
if (max) {
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
*max = clk_table->MaxGfxClk;
break;
case SMU_MCLK:
case SMU_UCLK:
max_dpm_level = 0;
break;
case SMU_FCLK:
max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
case SMU_VCLK:
case SMU_DCLK:
max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
break;
default:
ret = -EINVAL;
goto failed;
}
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
if (ret)
goto failed;
}
}
if (min) {
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
*min = clk_table->MinGfxClk;
break;
case SMU_MCLK:
case SMU_UCLK:
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
break;
case SMU_VCLK:
case SMU_DCLK:
min_dpm_level = 0;
break;
default:
ret = -EINVAL;
goto failed;
}
if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
if (ret)
goto failed;
}
}
failed:
return ret;
}
static int smu_v15_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min,
uint32_t *max)
{
if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
smu_v15_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
return 0;
}
static int smu_v15_0_0_get_current_clk_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value)
{
MetricsMember_t member_type;
switch (clk_type) {
case SMU_SOCCLK:
member_type = METRICS_AVERAGE_SOCCLK;
break;
case SMU_VCLK:
member_type = METRICS_AVERAGE_VCLK;
break;
case SMU_VCLK1:
member_type = METRICS_AVERAGE_VCLK1;
break;
case SMU_DCLK:
member_type = METRICS_AVERAGE_DCLK;
break;
case SMU_DCLK1:
member_type = METRICS_AVERAGE_DCLK1;
break;
case SMU_MCLK:
member_type = METRICS_AVERAGE_UCLK;
break;
case SMU_FCLK:
member_type = METRICS_AVERAGE_FCLK;
break;
case SMU_GFXCLK:
case SMU_SCLK:
member_type = METRICS_AVERAGE_GFXCLK;
break;
default:
return -EINVAL;
}
return smu_v15_0_0_get_smu_metrics_data(smu, member_type, value);
}
static int smu_v15_0_0_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *count)
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
switch (clk_type) {
case SMU_SOCCLK:
*count = clk_table->NumSocClkLevelsEnabled;
break;
case SMU_VCLK:
*count = clk_table->VcnClkLevelsEnabled;
break;
case SMU_DCLK:
*count = clk_table->VcnClkLevelsEnabled;
break;
case SMU_MCLK:
*count = clk_table->NumMemPstatesEnabled;
break;
case SMU_FCLK:
*count = clk_table->NumFclkLevelsEnabled;
break;
default:
break;
}
return 0;
}
static int smu_v15_0_common_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *count)
{
if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
smu_v15_0_0_get_dpm_level_count(smu, clk_type, count);
return 0;
}
static int smu_v15_0_0_emit_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf,
int *offset)
{
int i, idx, ret = 0, size = *offset;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t min, max;
switch (clk_type) {
case SMU_OD_SCLK:
size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
break;
case SMU_OD_RANGE:
size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq,
smu->gfx_default_soft_max_freq);
break;
case SMU_SOCCLK:
case SMU_VCLK:
case SMU_DCLK:
case SMU_VCLK1:
case SMU_DCLK1:
case SMU_MCLK:
case SMU_FCLK:
ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
if (ret)
return ret;
ret = smu_v15_0_common_get_dpm_level_count(smu, clk_type, &count);
if (ret)
return ret;
for (i = 0; i < count; i++) {
idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value);
if (ret)
return ret;
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
value,
cur_value == value ? "*" : "");
}
break;
case SMU_GFXCLK:
case SMU_SCLK:
ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
if (ret)
return ret;
min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
if (cur_value == max)
i = 2;
else if (cur_value == min)
i = 0;
else
i = 1;
size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
i == 0 ? "*" : "");
size += sysfs_emit_at(
buf, size, "1: %uMhz %s\n",
i == 1 ? cur_value : 1100,
i == 1 ? "*" : "");
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
i == 2 ? "*" : "");
break;
default:
break;
}
*offset = size;
return 0;
}
static int smu_v15_0_0_set_soft_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
int ret = 0;
if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type))
return -EINVAL;
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
msg_set_min = SMU_MSG_SetSoftMinGfxclk;
msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
break;
case SMU_FCLK:
msg_set_min = SMU_MSG_SetSoftMinFclk;
msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
break;
case SMU_SOCCLK:
msg_set_min = SMU_MSG_SetSoftMinSocclkByFreq;
msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
break;
case SMU_VCLK:
case SMU_DCLK:
msg_set_min = SMU_MSG_SetSoftMinVcn;
msg_set_max = SMU_MSG_SetSoftMaxVcn;
break;
default:
return -EINVAL;
}
ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
if (ret)
return ret;
return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
max, NULL);
}
static int smu_v15_0_0_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask)
{
uint32_t soft_min_level = 0, soft_max_level = 0;
uint32_t min_freq = 0, max_freq = 0;
int ret = 0;
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
switch (clk_type) {
case SMU_SOCCLK:
case SMU_FCLK:
case SMU_VCLK:
case SMU_DCLK:
case SMU_VCLK1:
case SMU_DCLK1:
ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
if (ret)
break;
ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
if (ret)
break;
ret = smu_v15_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int smu_v15_0_common_get_dpm_profile_freq(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum smu_clk_type clk_type,
uint32_t *min_clk,
uint32_t *max_clk)
{
uint32_t clk_limit = 0;
int ret = 0;
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
clk_limit = SMU_15_0_UMD_PSTATE_GFXCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
break;
case SMU_SOCCLK:
clk_limit = SMU_15_0_UMD_PSTATE_SOCCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
break;
case SMU_FCLK:
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 0))
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
else
clk_limit = SMU_15_0_UMD_PSTATE_FCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
break;
case SMU_VCLK:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
break;
case SMU_VCLK1:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &clk_limit);
break;
case SMU_DCLK:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
break;
case SMU_DCLK1:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &clk_limit);
break;
default:
ret = -EINVAL;
break;
}
*min_clk = *max_clk = clk_limit;
return ret;
}
static int smu_v15_0_common_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
struct amdgpu_device *adev = smu->adev;
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
uint32_t vclk_min = 0, vclk_max = 0;
uint32_t dclk_min = 0, dclk_max = 0;
uint32_t vclk1_min = 0, vclk1_max = 0;
uint32_t dclk1_min = 0, dclk1_max = 0;
int ret = 0;
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &vclk1_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &dclk1_max);
sclk_min = sclk_max;
fclk_min = fclk_max;
socclk_min = socclk_max;
vclk_min = vclk_max;
dclk_min = dclk_max;
vclk1_min = vclk1_max;
dclk1_min = dclk1_max;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, NULL);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, NULL);
sclk_max = sclk_min;
fclk_max = fclk_min;
socclk_max = socclk_min;
vclk_max = vclk_min;
dclk_max = dclk_min;
vclk1_max = vclk1_min;
dclk1_max = dclk1_min;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, &vclk1_max);
smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, &dclk1_max);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK1, &vclk1_min, &vclk1_max);
smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK1, &dclk1_min, &dclk1_max);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
return 0;
default:
dev_err(adev->dev, "Invalid performance level %d\n", level);
return -EINVAL;
}
if (sclk_min && sclk_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_SCLK,
sclk_min,
sclk_max);
if (ret)
return ret;
smu->gfx_actual_hard_min_freq = sclk_min;
smu->gfx_actual_soft_max_freq = sclk_max;
}
if (fclk_min && fclk_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_FCLK,
fclk_min,
fclk_max);
if (ret)
return ret;
}
if (socclk_min && socclk_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_SOCCLK,
socclk_min,
socclk_max);
if (ret)
return ret;
}
if (vclk_min && vclk_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_VCLK,
vclk_min,
vclk_max);
if (ret)
return ret;
}
if (vclk1_min && vclk1_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_VCLK1,
vclk1_min,
vclk1_max);
if (ret)
return ret;
}
if (dclk_min && dclk_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_DCLK,
dclk_min,
dclk_max);
if (ret)
return ret;
}
if (dclk1_min && dclk1_max) {
ret = smu_v15_0_0_set_soft_freq_limited_range(smu,
SMU_DCLK1,
dclk1_min,
dclk1_max);
if (ret)
return ret;
}
return ret;
}
static int smu_v15_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
smu->gfx_actual_hard_min_freq = 0;
smu->gfx_actual_soft_max_freq = 0;
return 0;
}
static int smu_v15_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
{
smu_v15_0_0_set_fine_grain_gfx_freq_parameters(smu);
return 0;
}
static int smu_v15_0_0_set_vpe_enable(struct smu_context *smu,
bool enable)
{
return smu_cmn_send_smc_msg_with_param(smu, enable ?
SMU_MSG_PowerUpVpe : SMU_MSG_PowerDownVpe,
0, NULL);
}
static int smu_v15_0_0_set_umsch_mm_enable(struct smu_context *smu,
bool enable)
{
return smu_cmn_send_smc_msg_with_param(smu, enable ?
SMU_MSG_PowerUpUmsch : SMU_MSG_PowerDownUmsch,
0, NULL);
}
static int smu_v15_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
uint8_t idx;
for (idx = 0; idx < NUM_SOCCLK_DPM_LEVELS; idx++) {
clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClocks[idx]:0;
clock_table->SocClocks[idx].Vol = 0;
}
for (idx = 0; idx < NUM_VPE_DPM_LEVELS; idx++) {
clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[idx]:0;
clock_table->VPEClocks[idx].Vol = 0;
}
return 0;
}
static int smu_v15_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
{
smu_v15_0_0_get_dpm_table(smu, clock_table);
return 0;
}
static const struct pptable_funcs smu_v15_0_0_ppt_funcs = {
.check_fw_status = smu_v15_0_check_fw_status,
.check_fw_version = smu_v15_0_check_fw_version,
.init_smc_tables = smu_v15_0_0_init_smc_tables,
.fini_smc_tables = smu_v15_0_0_fini_smc_tables,
.get_vbios_bootup_values = smu_v15_0_get_vbios_bootup_values,
.system_features_control = smu_v15_0_0_system_features_control,
.dpm_set_vcn_enable = smu_v15_0_set_vcn_enable,
.dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable,
.set_default_dpm_table = smu_v15_0_0_set_default_dpm_tables,
.read_sensor = smu_v15_0_0_read_sensor,
.is_dpm_running = smu_v15_0_0_is_dpm_running,
.set_watermarks_table = smu_v15_0_0_set_watermarks_table,
.get_gpu_metrics = smu_v15_0_0_get_gpu_metrics,
.get_enabled_mask = smu_v15_0_0_get_enabled_mask,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.gfx_off_control = smu_v15_0_gfx_off_control,
.mode2_reset = smu_v15_0_0_mode2_reset,
.get_dpm_ultimate_freq = smu_v15_0_common_get_dpm_ultimate_freq,
.od_edit_dpm_table = smu_v15_0_od_edit_dpm_table,
.emit_clk_levels = smu_v15_0_0_emit_clk_levels,
.force_clk_levels = smu_v15_0_0_force_clk_levels,
.set_performance_level = smu_v15_0_common_set_performance_level,
.set_fine_grain_gfx_freq_parameters = smu_v15_0_common_set_fine_grain_gfx_freq_parameters,
.set_gfx_power_up_by_imu = smu_v15_0_set_gfx_power_up_by_imu,
.dpm_set_vpe_enable = smu_v15_0_0_set_vpe_enable,
.dpm_set_umsch_mm_enable = smu_v15_0_0_set_umsch_mm_enable,
.get_dpm_clock_table = smu_v15_0_common_get_dpm_table,
};
static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
ctl->smu = smu;
mutex_init(&ctl->lock);
ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30);
ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31);
ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32);
ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_33);
ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_34);
ctl->config.num_arg_regs = 3;
ctl->ops = &smu_msg_v1_ops;
ctl->default_timeout = adev->usec_timeout * 20;
ctl->message_map = smu_v15_0_0_message_map;
}
void smu_v15_0_0_set_ppt_funcs(struct smu_context *smu)
{
smu->ppt_funcs = &smu_v15_0_0_ppt_funcs;
smu->feature_map = smu_v15_0_0_feature_mask_map;
smu->table_map = smu_v15_0_0_table_map;
smu->is_apu = true;
smu_v15_0_0_init_msg_ctl(smu);
}
