sys/arch/arm64/dev/apldart.c

281

params3 = HREAD4(sc, DART_T8110_PARAMS3);

sys/arch/arm64/dev/apldart.c

282

params4 = HREAD4(sc, DART_T8110_PARAMS4);

sys/arch/arm64/dev/apldart.c

317

config = HREAD4(sc, DART_T8110_PROTECT);

sys/arch/arm64/dev/apldart.c

321

config = HREAD4(sc, DART_T8020_CONFIG);

sys/arch/arm64/dev/apldart.c

346

tcr = HREAD4(sc, DART_TCR(sc, sid));

sys/arch/arm64/dev/apldart.c

351

ttbr = HREAD4(sc, DART_TTBR(sc, sid, idx));

sys/arch/arm64/dev/apldart.c

368

params2 = HREAD4(sc, DART_PARAMS2);

sys/arch/arm64/dev/apldart.c

415

HWRITE4(sc, DART_T8110_ERROR, HREAD4(sc, DART_T8110_ERROR));

sys/arch/arm64/dev/apldart.c

420

HWRITE4(sc, DART_T8020_ERROR, HREAD4(sc, DART_T8020_ERROR));

sys/arch/arm64/dev/apldart.c

458

params2 = HREAD4(sc, DART_PARAMS2);

sys/arch/arm64/dev/apldart.c

486

mask = HREAD4(sc, DART_SID_ENABLE(sc, sid / 32));

sys/arch/arm64/dev/apldart.c

499

HWRITE4(sc, DART_T8110_ERROR, HREAD4(sc, DART_T8110_ERROR));

sys/arch/arm64/dev/apldart.c

502

HWRITE4(sc, DART_T8020_ERROR, HREAD4(sc, DART_T8020_ERROR));

sys/arch/arm64/dev/apldart.c

536

ttbr = HREAD4(sc, DART_TTBR(sc, as->as_sid, idx));

sys/arch/arm64/dev/apldart.c

574

ttbr = HREAD4(sc, DART_TTBR(sc, as->as_sid, idx));

sys/arch/arm64/dev/apldart.c

676

mask = HREAD4(sc, DART_SID_ENABLE(sc, sid / 32));

sys/arch/arm64/dev/apldart.c

722

sc->sc_dev.dv_xname, HREAD4(sc, DART_T8020_ERROR),

sys/arch/arm64/dev/apldart.c

723

HREAD4(sc, DART_T8020_ERROR_ADDR_HI),

sys/arch/arm64/dev/apldart.c

724

HREAD4(sc, DART_T8020_ERROR_ADDR_LO));

sys/arch/arm64/dev/apldart.c

733

sc->sc_dev.dv_xname, HREAD4(sc, DART_T8110_ERROR),

sys/arch/arm64/dev/apldart.c

734

HREAD4(sc, DART_T8110_ERROR_ADDR_HI),

sys/arch/arm64/dev/apldart.c

735

HREAD4(sc, DART_T8110_ERROR_ADDR_LO));

sys/arch/arm64/dev/apldart.c

752

while (HREAD4(sc, DART_T8020_TLB_CMD) & DART_T8020_TLB_CMD_BUSY)

sys/arch/arm64/dev/apldart.c

769

while (HREAD4(sc, DART_T8110_TLB_CMD) & DART_T8110_TLB_CMD_BUSY)

sys/arch/arm64/dev/apldc.c

170

stat = HREAD4(sc, DC_IRQ_STAT);

sys/arch/arm64/dev/apldc.c

69

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/apldc.c

71

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/apldma.c

230

status = HREAD4(sc, DMA_TX_DESC_RING(ac->ac_chan));

sys/arch/arm64/dev/apldma.c

252

intr = HREAD4(sc, DMA_TX_INTR(sc->sc_irq));

sys/arch/arm64/dev/apldma.c

257

intrstat = HREAD4(sc, DMA_TX_INTRSTAT(chan, sc->sc_irq));

sys/arch/arm64/dev/apldma.c

266

status = HREAD4(sc, DMA_TX_REPORT_RING(chan));

sys/arch/arm64/dev/apldma.c

271

HREAD4(sc, DMA_TX_REPORT_READ(chan));

sys/arch/arm64/dev/apldma.c

272

HREAD4(sc, DMA_TX_REPORT_READ(chan));

sys/arch/arm64/dev/apldma.c

273

HREAD4(sc, DMA_TX_REPORT_READ(chan));

sys/arch/arm64/dev/apldma.c

274

HREAD4(sc, DMA_TX_REPORT_READ(chan));

sys/arch/arm64/dev/apliic.c

136

sc->sc_hwrev = HREAD4(sc, I2C_REV);

sys/arch/arm64/dev/apliic.c

163

reg = HREAD4(sc, I2C_SMSTA);

sys/arch/arm64/dev/apliic.c

201

reg = HREAD4(sc, I2C_SMSTA);

sys/arch/arm64/dev/apliic.c

223

reg = HREAD4(sc, I2C_MRXFIFO);

sys/arch/arm64/dev/apliic.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/apliic.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplintc.c

258

info = HREAD4(sc, AIC_INFO);

sys/arch/arm64/dev/aplintc.c

316

hwid = HREAD4(sc, AIC_WHOAMI);

sys/arch/arm64/dev/aplintc.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplintc.c

90

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplmbox.c

131

ctrl = HREAD4(sc, MBOX_I2A_CTRL);

sys/arch/arm64/dev/aplmbox.c

171

ctrl = HREAD4(sc, MBOX_A2I_CTRL);

sys/arch/arm64/dev/aplmbox.c

191

ctrl = HREAD4(sc, MBOX_I2A_CTRL);

sys/arch/arm64/dev/aplmca.c

101

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplmca.c

103

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplmca.c

275

conf = HREAD4(sc, MCA_SERDES_CONF(ad->ad_cluster, MCA_SERDES_TXA));

sys/arch/arm64/dev/aplmca.c

378

conf = HREAD4(sc, MCA_SERDES_CONF(ad->ad_cluster, MCA_SERDES_TXA));

sys/arch/arm64/dev/aplmca.c

481

conf = HREAD4(sc, MCA_SERDES_CONF(ad->ad_cluster, MCA_SERDES_TXA));

sys/arch/arm64/dev/aplnco.c

181

div = HREAD4(sc, NCO_DIV(idx));

sys/arch/arm64/dev/aplnco.c

188

inc1 = HREAD4(sc, NCO_INC1(idx));

sys/arch/arm64/dev/aplnco.c

189

inc2 = HREAD4(sc, NCO_INC2(idx));

sys/arch/arm64/dev/aplnco.c

228

ctrl = HREAD4(sc, NCO_CTRL(idx));

sys/arch/arm64/dev/aplnco.c

47

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplnco.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpcie.c

755

return HREAD4(sc, tag | reg);

sys/arch/arm64/dev/aplpinctrl.c

207

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arch/arm64/dev/aplpinctrl.c

226

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arch/arm64/dev/aplpinctrl.c

247

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arch/arm64/dev/aplpinctrl.c

280

status = HREAD4(sc, GPIO_IRQ(0, base));

sys/arch/arm64/dev/aplpinctrl.c

351

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arch/arm64/dev/aplpinctrl.c

397

reg = HREAD4(sc, GPIO_PIN(ih->ih_irq));

sys/arch/arm64/dev/aplpinctrl.c

417

reg = HREAD4(sc, GPIO_PIN(ih->ih_irq));

sys/arch/arm64/dev/aplpinctrl.c

452

reg = HREAD4(sc, GPIO_PIN(ih->ih_irq));

sys/arch/arm64/dev/aplpinctrl.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplpinctrl.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplpmgr.c

185

val = HREAD4(sc, ps->ps_offset);

sys/arch/arm64/dev/aplpmgr.c

191

val = HREAD4(sc, ps->ps_offset);

sys/arch/arm64/dev/aplpmgr.c

213

val = HREAD4(sc, ps->ps_offset);

sys/arch/arm64/dev/aplpmgr.c

216

val = HREAD4(sc, ps->ps_offset);

sys/arch/arm64/dev/aplpmgr.c

220

val = HREAD4(sc, ps->ps_offset);

sys/arch/arm64/dev/aplpmgr.c

223

val = HREAD4(sc, ps->ps_offset);

sys/arch/arm64/dev/aplpwm.c

118

ctrl = HREAD4(sc, PWM_CTRL);

sys/arch/arm64/dev/aplpwm.c

119

on_cycles = HREAD4(sc, PWM_ON_CYCLES);

sys/arch/arm64/dev/aplpwm.c

120

off_cycles = HREAD4(sc, PWM_OFF_CYCLES);

sys/arch/arm64/dev/aplrtk.c

102

ctrl = HREAD4(sc, CPU_CTRL);

sys/arch/arm64/dev/aplsart.c

139

conf = HREAD4(sc, SART2_CONFIG(i));

sys/arch/arm64/dev/aplsart.c

159

conf = HREAD4(sc, SART3_CONFIG(i));

sys/arch/arm64/dev/aplsart.c

198

if (HREAD4(sc, SART2_ADDR(i)) != (addr >> SART_ADDR_SHIFT))

sys/arch/arm64/dev/aplsart.c

215

if (HREAD4(sc, SART3_ADDR(i)) != (addr >> SART_ADDR_SHIFT))

sys/arch/arm64/dev/aplspi.c

100

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/aplspi.c

102

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/aplspi.c

192

HREAD4(sc, SPI_CONFIG);

sys/arch/arm64/dev/aplspi.c

238

avail = HREAD4(sc, SPI_AVAIL);

sys/arch/arm64/dev/aplspi.c

241

data = HREAD4(sc, SPI_RXDATA);

sys/arch/arm64/dev/aplspi.c

246

avail = HREAD4(sc, SPI_AVAIL);

sys/arch/arm64/dev/aplspi.c

260

status = HREAD4(sc, SPI_STATUS);

sys/arch/arm64/dev/aplspmi.c

145

if ((HREAD4(sc, SPMI_STAT) & SPMI_STAT_RXEMPTY) == 0)

sys/arch/arm64/dev/aplspmi.c

152

*resp = HREAD4(sc, SPMI_RESP);

sys/arch/arm64/dev/bcm2712_mip.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/bcm2712_mip.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/rpiclock.c

259

fbdiv_int = HREAD4(sc, base + PLL_SYS_FBDIV_INT - PLL_SYS_CS);

sys/arch/arm64/dev/rpiclock.c

260

fbdiv_frac = HREAD4(sc,base + PLL_SYS_FBDIV_FRAC - PLL_SYS_CS);

sys/arch/arm64/dev/rpiclock.c

316

prim = HREAD4(sc, base + PLL_SYS_PRIM - PLL_SYS_CS);

sys/arch/arm64/dev/rpiclock.c

358

prim = HREAD4(sc, base + PLL_SYS_PRIM - PLL_SYS_CS);

sys/arch/arm64/dev/rpiclock.c

373

sec = HREAD4(sc, base + PLL_SYS_SEC - PLL_SYS_CS);

sys/arch/arm64/dev/rpiclock.c

397

sec = HREAD4(sc, base + PLL_SYS_SEC - PLL_SYS_CS);

sys/arch/arm64/dev/rpiclock.c

458

sel = HREAD4(sc, clk->sel_reg);

sys/arch/arm64/dev/rpiclock.c

461

ctrl = HREAD4(sc, clk->ctrl_reg);

sys/arch/arm64/dev/rpiclock.c

472

div = HREAD4(sc, clk->div_int_reg);

sys/arch/arm64/dev/rpiclock.c

525

sel = HREAD4(sc, clk->sel_reg);

sys/arch/arm64/dev/rpiclock.c

528

ctrl = HREAD4(sc, clk->ctrl_reg);

sys/arch/arm64/dev/rpiclock.c

548

ctrl = HREAD4(sc, clk->ctrl_reg);

sys/arch/arm64/dev/rpiclock.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/rpiclock.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm64/dev/rpipwm.c

146

ctrl = HREAD4(sc, GLOBAL_CTRL);

sys/arch/arm64/dev/rpipwm.c

149

range = HREAD4(sc, CHAN_RANGE(chan));

sys/arch/arm64/dev/rpipwm.c

150

duty = HREAD4(sc, CHAN_DUTY(chan));

sys/arch/arm64/dev/rpipwm.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm64/dev/rpipwm.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exclock.c

248

reg = HREAD4(sc, EXYNOS5420_DIV_FSYS1);

sys/arch/armv7/exynos/exclock.c

250

reg = HREAD4(sc, EXYNOS5420_SRC_FSYS);

sys/arch/armv7/exynos/exclock.c

265

reg = HREAD4(sc, EXYNOS5420_SRC_TOP6);

sys/arch/armv7/exynos/exclock.c

277

reg = HREAD4(sc, EXYNOS5420_RPLL_CON0);

sys/arch/armv7/exynos/exclock.c

281

reg = HREAD4(sc, EXYNOS5420_RPLL_CON1);

sys/arch/armv7/exynos/exclock.c

288

reg = HREAD4(sc, EXYNOS5420_SPLL_CON0);

sys/arch/armv7/exynos/exclock.c

392

HREAD4(sc, CLOCK_APLL_CON0), 0);

sys/arch/armv7/exynos/exclock.c

396

HREAD4(sc, CLOCK_MPLL_CON0), 0);

sys/arch/armv7/exynos/exclock.c

400

HREAD4(sc, CLOCK_BPLL_CON0), 0);

sys/arch/armv7/exynos/exclock.c

404

HREAD4(sc, CLOCK_EPLL_CON0),

sys/arch/armv7/exynos/exclock.c

405

HREAD4(sc, CLOCK_EPLL_CON1));

sys/arch/armv7/exynos/exclock.c

409

HREAD4(sc, CLOCK_VPLL_CON0),

sys/arch/armv7/exynos/exclock.c

410

HREAD4(sc, CLOCK_VPLL_CON1));

sys/arch/armv7/exynos/exclock.c

414

HREAD4(sc, EXYNOS5420_KPLL_CON0), 0);

sys/arch/armv7/exynos/exclock.c

426

uint32_t pll_div2_sel = HREAD4(sc, CLOCK_PLL_DIV2_SEL);

sys/arch/armv7/exynos/exclock.c

454

div = HREAD4(sc, CLOCK_CLK_DIV_CPU0);

sys/arch/armv7/exynos/exclock.c

471

div = HREAD4(sc, EXYNOS5420_DIV_KFC0);

sys/arch/armv7/exynos/exclock.c

485

div = HREAD4(sc, CLOCK_CLK_DIV_TOP1);

sys/arch/armv7/exynos/exclock.c

488

div = HREAD4(sc, CLOCK_CLK_DIV_TOP0);

sys/arch/armv7/exynos/exclock.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/exclock.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exgpio.c

247

reg = HREAD4(sc, GPXCON(bank->addr));

sys/arch/armv7/exynos/exgpio.c

252

reg = HREAD4(sc, GPXDAT(bank->addr));

sys/arch/armv7/exynos/exgpio.c

259

reg = HREAD4(sc, GPXPUD(bank->addr));

sys/arch/armv7/exynos/exgpio.c

264

reg = HREAD4(sc, GPXDRV(bank->addr));

sys/arch/armv7/exynos/exgpio.c

292

val = HREAD4(ec->ec_sc, GPXCON(ec->ec_bank->addr));

sys/arch/armv7/exynos/exgpio.c

310

reg = HREAD4(ec->ec_sc, GPXDAT(ec->ec_bank->addr));

sys/arch/armv7/exynos/exgpio.c

329

reg = HREAD4(ec->ec_sc, GPXDAT(ec->ec_bank->addr));

sys/arch/armv7/exynos/exiic.c

100

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/exynos/exiic.c

210

state = HREAD4(sc, reg);

sys/arch/armv7/exynos/exiic.c

212

if (((state = HREAD4(sc, reg)) & mask) == value)

sys/arch/armv7/exynos/exiic.c

316

((uint8_t *)databuf)[i] = HREAD4(sc, I2C_DS);

sys/arch/armv7/exynos/exiic.c

350

return (HREAD4(sc, I2C_STAT) & I2C_STAT_LAST_RVCD_BIT) ?

sys/arch/armv7/exynos/exiic.c

98

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/expower.c

36

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/exynos/expower.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/imx/imxtemp.c

202

value = HREAD4(sc, TEMPMON_TEMPSENSE0);

sys/arch/armv7/imx/imxtemp.c

66

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/imx/imxtemp.c

68

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvacc.c

132

sar = HREAD4(sc, SAR);

sys/arch/armv7/marvell/mvacc.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvacc.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvagc.c

33

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvagc.c

35

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvodog.c

38

HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) | (bits))

sys/arch/armv7/marvell/mvodog.c

40

HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvortc.c

135

sample = HREAD4(sc, reg);

sys/arch/armv7/marvell/mvpcie.c

394

HWRITE4(po, PCIE_STAT, (HREAD4(po, PCIE_STAT) &

sys/arch/armv7/marvell/mvpcie.c

400

HWRITE4(po, PCIE_CMD, HREAD4(po, PCIE_CMD) |

sys/arch/armv7/marvell/mvpcie.c

403

HWRITE4(po, PCIE_MASK, HREAD4(po, PCIE_MASK) |

sys/arch/armv7/marvell/mvpcie.c

600

return !(HREAD4(po, PCIE_STAT) & PCIE_STAT_LINK_DOWN);

sys/arch/armv7/marvell/mvpcie.c

644

(HREAD4(po, PCIE_DEV_ID) & 0xffff0000);

sys/arch/armv7/marvell/mvpcie.c

650

(HREAD4(po, PCIE_DEV_REV) & 0xff);

sys/arch/armv7/marvell/mvpcie.c

702

HWRITE4(po, PCIE_STAT, (HREAD4(po, PCIE_STAT) &

sys/arch/armv7/marvell/mvpcie.c

748

return HREAD4(po, PCIE_CONF_DATA);

sys/arch/armv7/marvell/mvpcie.c

82

HWRITE4((po), (reg), HREAD4((po), (reg)) | (bits))

sys/arch/armv7/marvell/mvpcie.c

84

HWRITE4((po), (reg), HREAD4((po), (reg)) & ~(bits))

sys/arch/armv7/marvell/mvsysctrl.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/marvell/mvsysctrl.c

40

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/amdisplay.c

131

read = HREAD4(sc, reg);

sys/arch/armv7/omap/amdisplay.c

194

reg = HREAD4(sc, LCD_SYSCONFIG);

sys/arch/armv7/omap/amdisplay.c

282

reg = HREAD4(sc, LCD_CTRL);

sys/arch/armv7/omap/amdisplay.c

291

reg = HREAD4(sc, LCD_RASTER_CTRL);

sys/arch/armv7/omap/amdisplay.c

308

reg = HREAD4(sc, LCD_LCDDMA_CTRL);

sys/arch/armv7/omap/amdisplay.c

398

reg = HREAD4(sc, LCD_IRQSTATUS);

sys/arch/armv7/omap/amdisplay.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/amdisplay.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/omclock.c

137

reg = HREAD4(sc, base);

sys/arch/armv7/omap/omclock.c

155

if ((HREAD4(sc, base) & IDLEST_MASK) == IDLEST_FUNC)

sys/arch/armv7/omap/omclock.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/omclock.c

45

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/ommmc.c

1074

*(uint32_t *)datap = HREAD4(sc, MMCHS_DATA);

sys/arch/armv7/omap/ommmc.c

1079

uint32_t rv = HREAD4(sc, MMCHS_DATA);

sys/arch/armv7/omap/ommmc.c

1125

if (ISSET(HREAD4(sc, MMCHS_SYSCTL), mask))

sys/arch/armv7/omap/ommmc.c

1130

if (!ISSET(HREAD4(sc, MMCHS_SYSCTL), mask))

sys/arch/armv7/omap/ommmc.c

1136

HREAD4(sc, MMCHS_SYSCTL)));

sys/arch/armv7/omap/ommmc.c

1188

status = HREAD4(sc, MMCHS_STAT);

sys/arch/armv7/omap/ommmc.c

226

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/ommmc.c

228

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/omap/ommmc.c

366

caps = HREAD4(sc, MMCHS_CAPA);

sys/arch/armv7/omap/ommmc.c

428

" trying 512\n", HREAD4(sc, MMCHS_CAPA));

sys/arch/armv7/omap/ommmc.c

610

return !ISSET(HREAD4(sc, MMCHS_SYSTEST), MMCHS_SYSTEST_SDCD) ?

sys/arch/armv7/omap/ommmc.c

661

reg = HREAD4(sc, MMCHS_HCTL);

sys/arch/armv7/omap/ommmc.c

674

if (!ISSET(HREAD4(sc, MMCHS_HCTL), MMCHS_HCTL_SDBP)) {

sys/arch/armv7/omap/ommmc.c

721

if (!ISSET(HREAD4(sc, MMCHS_PSTATE),

sys/arch/armv7/omap/ommmc.c

746

reg = HREAD4(sc, MMCHS_SYSCTL);

sys/arch/armv7/omap/ommmc.c

761

if (ISSET(HREAD4(sc, MMCHS_SYSCTL), MMCHS_SYSCTL_ICS))

sys/arch/armv7/omap/ommmc.c

834

state = HREAD4(sc, MMCHS_PSTATE);

sys/arch/armv7/omap/ommmc.c

838

if (((state = HREAD4(sc, MMCHS_PSTATE)) & mask) == value)

sys/arch/armv7/omap/ommmc.c

881

v0 = HREAD4(sc, MMCHS_RSP10);

sys/arch/armv7/omap/ommmc.c

882

v1 = HREAD4(sc, MMCHS_RSP32);

sys/arch/armv7/omap/ommmc.c

883

v2 = HREAD4(sc, MMCHS_RSP54);

sys/arch/armv7/omap/ommmc.c

884

v3 = HREAD4(sc, MMCHS_RSP76);

sys/arch/armv7/omap/ommmc.c

894

cmd->c_resp[0] = HREAD4(sc, MMCHS_RSP10);

sys/arch/armv7/omap/omrng.c

136

status = HREAD4(sc, RNG_STATUS);

sys/arch/armv7/omap/omrng.c

143

detune = ~HREAD4(sc, RNG_FROENABLE) & RNG_FROENABLE_MASK;

sys/arch/armv7/omap/omrng.c

151

enqueue_randomness(HREAD4(sc, RNG_OUTPUT0));

sys/arch/armv7/omap/omrng.c

152

enqueue_randomness(HREAD4(sc, RNG_OUTPUT1));

sys/arch/armv7/omap/omrng.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/omap/omrng.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/armv7/vexpress/pciecam.c

299

return HREAD4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3));

sys/arch/armv7/vexpress/pciecam.c

54

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/armv7/vexpress/pciecam.c

56

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/mpfclock.c

144

sc->sc_clkcfg = HREAD4(sc, CLOCK_CONFIG_CR);

sys/arch/riscv64/dev/mpfclock.c

210

val = HREAD4(sc, SUBBLK_CLOCK_CR);

sys/arch/riscv64/dev/mpfclock.c

214

val = HREAD4(sc, SUBBLK_RESET_CR);

sys/arch/riscv64/dev/mpfclock.c

218

val = HREAD4(sc, SUBBLK_RESET_CR);

sys/arch/riscv64/dev/mpfclock.c

222

val = HREAD4(sc, SUBBLK_CLOCK_CR);

sys/arch/riscv64/dev/mpfgpio.c

158

val = HREAD4(sc, MPFGPIO_CONFIG(pin));

sys/arch/riscv64/dev/mpfgpio.c

183

val = (HREAD4(sc, MPFGPIO_GPIN) >> pin) & 1;

sys/arch/riscv64/dev/mpfgpio.c

267

cfgreg = HREAD4(sc, MPFGPIO_CONFIG(pin));

sys/arch/riscv64/dev/mpfgpio.c

275

state = (HREAD4(sc, MPFGPIO_GPIN) >> pin) & 1;

sys/arch/riscv64/dev/mpfiic.c

315

*datap = HREAD4(sc, I2C_DATA);

sys/arch/riscv64/dev/mpfiic.c

388

ctrl = HREAD4(sc, I2C_CTRL);

sys/arch/riscv64/dev/mpfiic.c

396

status = HREAD4(sc, I2C_STATUS);

sys/arch/riscv64/dev/sfclock.c

127

reg = HREAD4(sc, off);

sys/arch/riscv64/dev/sfclock.c

147

reg = HREAD4(sc, HFPCLKPLLSEL);

sys/arch/riscv64/dev/sfclock.c

152

div = HREAD4(sc, HFPCLK_DIV) + 2;

sys/arch/riscv64/dev/sfgpio.c

188

reg = HREAD4(sc, GPIO_INPUT_VAL);

sys/arch/riscv64/dev/sfgpio.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/sfgpio.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/sfuart.c

202

if (!ISSET(HREAD4(sc, UART_TXDATA), UART_TXDATA_FULL) &&

sys/arch/riscv64/dev/sfuart.c

212

val = HREAD4(sc, UART_RXDATA);

sys/arch/riscv64/dev/sfuart.c

221

val = HREAD4(sc, UART_RXDATA);

sys/arch/riscv64/dev/sfuart.c

349

stat = HREAD4(sc, UART_TXDATA);

sys/arch/riscv64/dev/sfuart.c

352

stat = HREAD4(sc, UART_TXDATA);

sys/arch/riscv64/dev/sfuart.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/sfuart.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtclock.c

139

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtclock.c

141

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtclock.c

349

reg = HREAD4(sc, clock->reg);

sys/arch/riscv64/dev/smtclock.c

463

val = HREAD4(sc, reset->reg) & ~mask;

sys/arch/riscv64/dev/smtcomphy.c

181

val = HREAD4(sc, PCIE_RCAL_RESULT);

sys/arch/riscv64/dev/smtcomphy.c

203

val = HREAD4(sc, PCIE_PU_PLL_1);

sys/arch/riscv64/dev/smtcomphy.c

210

val = HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(lane));

sys/arch/riscv64/dev/smtcomphy.c

216

if (HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(0)) & PLL_READY)

sys/arch/riscv64/dev/smtcomphy.c

229

val = HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(0));

sys/arch/riscv64/dev/smtcomphy.c

234

val = HREAD4(sc, PCIE_PU_PLL_1);

sys/arch/riscv64/dev/smtcomphy.c

249

val = HREAD4(sc, PCIE_PU_ADDR_CLK_CFG(lane));

sys/arch/riscv64/dev/smtcomphy.c

255

val = HREAD4(sc, PCIE_RC_DONE_STATUS);

sys/arch/riscv64/dev/smtcomphy.c

259

val = HREAD4(sc, PCIE_PU_PLL_1);

sys/arch/riscv64/dev/smtcomphy.c

264

val = HREAD4(sc, PCIE_PU_PLL_2);

sys/arch/riscv64/dev/smtcomphy.c

311

val = HREAD4(sc, PCIE_RX_REG1(lane));

sys/arch/riscv64/dev/smtcomphy.c

317

val = HREAD4(sc, PCIE_RX_REG2(lane));

sys/arch/riscv64/dev/smtcomphy.c

321

val = HREAD4(sc, PCIE_TX_REG1(lane));

sys/arch/riscv64/dev/smtcomphy.c

327

val = HREAD4(sc, PCIE_RC_CAL_REG2(lane));

sys/arch/riscv64/dev/smtcomphy.c

335

val = HREAD4(sc, PCIE_LTSSM_DIS_ENTRY(lane));

sys/arch/riscv64/dev/smtgpio.c

153

reg = HREAD4(sc, offset + GPIO_PLR);

sys/arch/riscv64/dev/smtgpio.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtgpio.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/smtiic.c

177

if (((state = HREAD4(sc, ISR)) & mask) == value)

sys/arch/riscv64/dev/smtiic.c

240

if (HREAD4(sc, ISR) & ISR_ACKNAK)

sys/arch/riscv64/dev/smtiic.c

265

*valp = HREAD4(sc, IDBR);

sys/arch/riscv64/dev/smtiic.c

287

if (HREAD4(sc, ISR) & ISR_ACKNAK)

sys/arch/riscv64/dev/smtiic.c

81

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/smtiic.c

83

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfclock.c

1006

reg = HREAD4(sc, idx * 4);

sys/arch/riscv64/dev/stfclock.c

1013

reg = HREAD4(sc, idx * 4);

sys/arch/riscv64/dev/stfclock.c

184

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/stfclock.c

186

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfclock.c

350

reg = HREAD4(sc, idx * 4);

sys/arch/riscv64/dev/stfclock.c

514

reg = HREAD4(sc, idx * 4);

sys/arch/riscv64/dev/stfclock.c

566

reg = HREAD4(sc, idx * 4);

sys/arch/riscv64/dev/stfclock.c

879

reg = HREAD4(sc, idx * 4);

sys/arch/riscv64/dev/stfpcie.c

404

reg = HREAD4(sc, PCIE_PCI_IOV_DW0);

sys/arch/riscv64/dev/stfpcie.c

416

reg = HREAD4(sc, GEN_SETTINGS);

sys/arch/riscv64/dev/stfpcie.c

426

reg = HREAD4(sc, PCIE_BAR_WIN);

sys/arch/riscv64/dev/stfpcie.c

431

reg = HREAD4(sc, PMSG_SUPPORT_RX);

sys/arch/riscv64/dev/stfpcie.c

494

sc->sc_msi_addr = HREAD4(sc, IMSI_ADDR);

sys/arch/riscv64/dev/stfpcie.c

594

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

612

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

627

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

639

mask = HREAD4(sc, IMASK_LOCAL);

sys/arch/riscv64/dev/stfpcie.c

722

status = HREAD4(sc, ISTATUS_MSI);

sys/arch/riscv64/dev/stfpcie.c

752

status = HREAD4(sc, ISTATUS_LOCAL);

sys/arch/riscv64/dev/stfpciephy.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/riscv64/dev/stfpciephy.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/riscv64/dev/stfrng.c

124

stat = HREAD4(sc, RNG_STAT);

sys/arch/riscv64/dev/stfrng.c

126

istat = HREAD4(sc, RNG_ISTAT);

sys/arch/riscv64/dev/stfrng.c

129

enqueue_randomness(HREAD4(sc, RNG_DATA0));

sys/arch/riscv64/dev/stfrng.c

130

enqueue_randomness(HREAD4(sc, RNG_DATA1));

sys/arch/riscv64/dev/stfrng.c

131

enqueue_randomness(HREAD4(sc, RNG_DATA2));

sys/arch/riscv64/dev/stfrng.c

132

enqueue_randomness(HREAD4(sc, RNG_DATA3));

sys/arch/riscv64/dev/stfrng.c

133

enqueue_randomness(HREAD4(sc, RNG_DATA4));

sys/arch/riscv64/dev/stfrng.c

134

enqueue_randomness(HREAD4(sc, RNG_DATA5));

sys/arch/riscv64/dev/stfrng.c

135

enqueue_randomness(HREAD4(sc, RNG_DATA6));

sys/arch/riscv64/dev/stfrng.c

136

enqueue_randomness(HREAD4(sc, RNG_DATA7));

sys/arch/riscv64/dev/stftemp.c

139

value = HREAD4(sc, TEMP);

sys/dev/acpi/dwgpio.c

212

reg = HREAD4(sc, GPIO_EXT_PORTA);

sys/dev/acpi/dwgpio.c

265

status = HREAD4(sc, GPIO_INT_STATUS);

sys/dev/acpi/dwgpio.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/acpi/dwgpio.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/acpi/qcgpio.c

448

reg = HREAD4(sc, off + TLMM_GPIO_IN_OUT(pin));

sys/dev/acpi/qcgpio.c

487

reg = HREAD4(sc, off + TLMM_GPIO_INTR_CFG(pin));

sys/dev/acpi/qcgpio.c

563

stat = HREAD4(sc, off + TLMM_GPIO_INTR_STATUS(pin));

sys/dev/acpi/qcgpio.c

64

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/acpi/qcgpio.c

66

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/acpi/qciic.c

194

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/acpi/qciic.c

215

stat = HREAD4(sc, GENI_RX_FIFO_STATUS);

sys/dev/acpi/qciic.c

222

word = HREAD4(sc, GENI_RX_FIFO);

sys/dev/acpi/qciic.c

241

stat = HREAD4(sc, GENI_TX_FIFO_STATUS);

sys/dev/acpi/qciic.c

271

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/acpi/qciic.c

293

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/acpi/qciic.c

307

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/fdt/amlclock.c

111

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlclock.c

113

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlclock.c

211

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

255

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

306

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

317

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

330

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

337

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

348

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

361

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

395

reg = HREAD4(sc, offset);

sys/dev/fdt/amlclock.c

408

if (HREAD4(sc, offset) & HHI_SYS_DPLL_LOCK)

sys/dev/fdt/amlclock.c

425

reg = HREAD4(sc, HHI_SYS_PLL_CNTL0);

sys/dev/fdt/amlclock.c

431

reg = HREAD4(sc, HHI_SYS1_PLL_CNTL0);

sys/dev/fdt/amlclock.c

450

reg = HREAD4(sc, HHI_MPEG_CLK_CNTL);

sys/dev/fdt/amlclock.c

479

reg = HREAD4(sc, HHI_SD_EMMC_CLK_CNTL);

sys/dev/fdt/amlclock.c

502

reg = HREAD4(sc, HHI_SD_EMMC_CLK_CNTL);

sys/dev/fdt/amlclock.c

525

reg = HREAD4(sc, HHI_NAND_CLK_CNTL);

sys/dev/fdt/amldwusb.c

110

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amldwusb.c

112

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amldwusb.c

175

reg = HREAD4(sc, USB_R1);

sys/dev/fdt/amldwusb.c

182

reg = HREAD4(sc, USB_R5);

sys/dev/fdt/amldwusb.c

220

reg = HREAD4(sc, USB_R3);

sys/dev/fdt/amldwusb.c

229

reg = HREAD4(sc, USB_R2);

sys/dev/fdt/amldwusb.c

233

reg = HREAD4(sc, USB_R2);

sys/dev/fdt/amldwusb.c

241

reg = HREAD4(sc, USB_R1);

sys/dev/fdt/amliic.c

235

ctrl = HREAD4(sc, I2C_M_CONTROL);

sys/dev/fdt/amliic.c

247

rdata = HREAD4(sc, I2C_M_TOKEN_RDATA0);

sys/dev/fdt/amliic.c

250

rdata = HREAD4(sc, I2C_M_TOKEN_RDATA1);

sys/dev/fdt/amliic.c

63

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amliic.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlmmc.c

113

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlmmc.c

115

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlmmc.c

381

status = HREAD4(sc, SD_EMMC_STATUS);

sys/dev/fdt/amlmmc.c

399

cfg = HREAD4(sc, SD_EMMC_CFG);

sys/dev/fdt/amlmmc.c

560

cfg = HREAD4(sc, SD_EMMC_CFG);

sys/dev/fdt/amlmmc.c

700

cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP);

sys/dev/fdt/amlmmc.c

701

cmd->c_resp[1] = HREAD4(sc, SD_EMMC_CMD_RSP1);

sys/dev/fdt/amlmmc.c

702

cmd->c_resp[2] = HREAD4(sc, SD_EMMC_CMD_RSP2);

sys/dev/fdt/amlmmc.c

703

cmd->c_resp[3] = HREAD4(sc, SD_EMMC_CMD_RSP3);

sys/dev/fdt/amlmmc.c

714

cmd->c_resp[0] = HREAD4(sc, SD_EMMC_CMD_RSP);

sys/dev/fdt/amlmmc.c

789

cfg = HREAD4(sc, SD_EMMC_CFG);

sys/dev/fdt/amlmmc.c

790

div = HREAD4(sc, SD_EMMC_CLOCK) & SD_EMMC_CLOCK_DIV_MAX;

sys/dev/fdt/amlmmc.c

792

adjust = HREAD4(sc, SD_EMMC_ADJUST);

sys/dev/fdt/amlmmc.c

817

adjust = HREAD4(sc, SD_EMMC_ADJUST);

sys/dev/fdt/amlpciephy.c

129

reg = HREAD4(sc, PHY_R0);

sys/dev/fdt/amlpciephy.c

146

reg = HREAD4(sc, PHY_R0);

sys/dev/fdt/amlpciephy.c

199

if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK)

sys/dev/fdt/amlpciephy.c

209

if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0)

sys/dev/fdt/amlpciephy.c

229

if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK)

sys/dev/fdt/amlpciephy.c

237

reg = HREAD4(sc, PHY_R5);

sys/dev/fdt/amlpciephy.c

240

if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0)

sys/dev/fdt/amlpciephy.c

261

if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK)

sys/dev/fdt/amlpciephy.c

271

if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0)

sys/dev/fdt/amlpciephy.c

283

if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK)

sys/dev/fdt/amlpciephy.c

293

if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0)

sys/dev/fdt/amlpciephy.c

50

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpciephy.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpwm.c

150

pwm = HREAD4(sc, idx == 0 ? PWM_PWM_A : PWM_PWM_B);

sys/dev/fdt/amlpwm.c

151

misc = HREAD4(sc, PWM_MISC_REG_AB);

sys/dev/fdt/amlpwm.c

206

misc = HREAD4(sc, PWM_MISC_REG_AB);

sys/dev/fdt/amlpwm.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpwm.c

57

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlpwrc.c

52

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlpwrc.c

54

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlreset.c

40

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlreset.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlrng.c

93

enqueue_randomness(HREAD4(sc, RNG_DATA));

sys/dev/fdt/amltemp.c

200

code = HREAD4(sc, TS_STAT0);

sys/dev/fdt/amltemp.c

213

code = HREAD4(sc, TS_STAT0);

sys/dev/fdt/amltemp.c

53

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amltemp.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amluart.c

187

reg = HREAD4(sc, UART_MISC);

sys/dev/fdt/amluart.c

208

stat = HREAD4(sc, UART_STATUS);

sys/dev/fdt/amluart.c

220

c = HREAD4(sc, UART_RFIFO);

sys/dev/fdt/amluart.c

235

stat = HREAD4(sc, UART_STATUS);

sys/dev/fdt/amluart.c

355

stat = HREAD4(sc, UART_STATUS);

sys/dev/fdt/amluart.c

358

stat = HREAD4(sc, UART_STATUS);

sys/dev/fdt/amluart.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amluart.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/amlusbphy.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/amlusbphy.c

90

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2711_pcie.c

161

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcm2711_pcie.c

163

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2711_pcie.c

397

reg = HREAD4(sc, sc->sc_pcie_hard_debug);

sys/dev/fdt/bcm2711_pcie.c

402

reg = HREAD4(sc, PCIE_MISC_MISC_CTRL);

sys/dev/fdt/bcm2711_pcie.c

415

reg = HREAD4(sc, PCIE_RC_CFG_PRIV1_ID_VAL3);

sys/dev/fdt/bcm2711_pcie.c

521

reg = HREAD4(sc, PCIE_RGR1_SW_INIT_1);

sys/dev/fdt/bcm2711_pcie.c

528

reg = HREAD4(sc, PCIE_MISC_PCIE_CTRL);

sys/dev/fdt/bcm2711_pcie.c

590

reg = HREAD4(sc, PCIE_RC_PL_PHY_CTL_15);

sys/dev/fdt/bcm2711_pcie.c

605

reg = HREAD4(sc, sc->sc_pcie_hard_debug);

sys/dev/fdt/bcm2711_pcie.c

619

reg = HREAD4(sc, PCIE_RC_CFG_PRIV1_ROOT_CAP);

sys/dev/fdt/bcm2711_pcie.c

777

reg = HREAD4(sc, PCIE_MISC_MISC_CTRL);

sys/dev/fdt/bcm2711_pcie.c

789

reg = HREAD4(sc, PCIE_MISC_PCIE_STATUS);

sys/dev/fdt/bcm2711_pcie.c

808

HREAD4(sc, PCIE_RC_DL_MDIO_ADDR);

sys/dev/fdt/bcm2711_pcie.c

811

reg = HREAD4(sc, PCIE_RC_DL_MDIO_RD_DATA);

sys/dev/fdt/bcm2711_pcie.c

837

HREAD4(sc, PCIE_RC_DL_MDIO_ADDR);

sys/dev/fdt/bcm2711_pcie.c

841

reg = HREAD4(sc, PCIE_RC_DL_MDIO_WR_DATA);

sys/dev/fdt/bcm2711_pcie.c

903

return HREAD4(sc, tag | reg);

sys/dev/fdt/bcm2711_pcie.c

907

return HREAD4(sc, PCIE_EXT_CFG_DATA + reg);

sys/dev/fdt/bcm2711_rng.c

105

count = MAX(4, HREAD4(sc, RNG_FIFO_COUNT) & RNG_FIFO_COUNT_MASK);

sys/dev/fdt/bcm2711_rng.c

107

data = HREAD4(sc, RNG_FIFO_DATA);

sys/dev/fdt/bcm2711_tmon.c

134

code = HREAD4(sc, sc->sc_tsensstat);

sys/dev/fdt/bcm2711_tmon.c

151

code = HREAD4(sc, sc->sc_tsensstat);

sys/dev/fdt/bcm2835_bsc.c

170

HWRITE4(sc, BSC_S, HREAD4(sc, BSC_S));

sys/dev/fdt/bcm2835_bsc.c

190

stat = HREAD4(sc, BSC_S);

sys/dev/fdt/bcm2835_bsc.c

212

buf[i] = HREAD4(sc, BSC_FIFO);

sys/dev/fdt/bcm2835_dog.c

130

rstc = HREAD4(sc, PM_RSTC) & PM_RSTC_CONFIGMASK;

sys/dev/fdt/bcm2835_dog.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcm2835_dog.c

51

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcm2835_gpio.c

155

val = HREAD4(sc, GPFSEL(reg));

sys/dev/fdt/bcm2835_gpio.c

169

val = HREAD4(sc, GPPULL(reg));

sys/dev/fdt/bcm2835_gpio.c

268

reg = HREAD4(sc, GPLEV(pin / 32));

sys/dev/fdt/bcm2835_gpio.c

367

reg = HREAD4(sc, GPFSEL(pin / 10));

sys/dev/fdt/bcm2835_gpio.c

383

reg = HREAD4(sc, GPLEV(pin / 32));

sys/dev/fdt/bcm2835_rng.c

105

status = HREAD4(sc, RNG_STATUS);

sys/dev/fdt/bcm2835_rng.c

108

data = HREAD4(sc, RNG_DATA);

sys/dev/fdt/bcm2835_temp.c

117

code = HREAD4(sc, TS_TSENSSTAT);

sys/dev/fdt/bcmstbgpio.c

187

reg = HREAD4(sc, GIO_DATA(bank));

sys/dev/fdt/bcmstbgpio.c

239

mask = HREAD4(sc, GIO_MASK(bank));

sys/dev/fdt/bcmstbgpio.c

240

stat = HREAD4(sc, GIO_STAT(bank)) & mask;

sys/dev/fdt/bcmstbgpio.c

326

ec = HREAD4(sc, GIO_EC(bank)) & ~(1U << pin);

sys/dev/fdt/bcmstbgpio.c

327

ei = HREAD4(sc, GIO_EI(bank)) & ~(1U << pin);

sys/dev/fdt/bcmstbgpio.c

328

level = HREAD4(sc, GIO_LEVEL(bank)) & ~(1U << pin);

sys/dev/fdt/bcmstbgpio.c

46

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbgpio.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbintc.c

140

status = HREAD4(sc, INTR_STATUS);

sys/dev/fdt/bcmstbintc.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbintc.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/bcmstbpinctrl.c

198

val = HREAD4(sc, sc->sc_pins[pin].func_reg * 4);

sys/dev/fdt/bcmstbpinctrl.c

204

val = HREAD4(sc, sc->sc_pins[pin].bias_reg * 4);

sys/dev/fdt/bcmstbrescal.c

117

status = HREAD4(sc, RESCAL_STATUS);

sys/dev/fdt/bcmstbrescal.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/bcmstbrescal.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/cdpcie.c

177

blr = HREAD4(sc, PPB_REG_IOSTATUS);

sys/dev/fdt/cdpcie.c

180

blr = HREAD4(sc, PPB_REG_IO_HI);

sys/dev/fdt/cdpcie.c

190

blr = HREAD4(sc, PPB_REG_MEM);

sys/dev/fdt/cdpcie.c

200

blr = HREAD4(sc, PPB_REG_PREFMEM);

sys/dev/fdt/cdpcie.c

203

base |= (bus_addr_t)HREAD4(sc, PPB_REG_PREFBASE_HI32) << 32;

sys/dev/fdt/cdpcie.c

204

limit |= (bus_addr_t)HREAD4(sc, PPB_REG_PREFLIM_HI32) << 32;

sys/dev/fdt/cdpcie.c

244

id = HREAD4(sc, PCI_ID_REG);

sys/dev/fdt/cdpcie.c

356

blr = HREAD4(sc, PPB_REG_IOSTATUS) & 0xffff0000;

sys/dev/fdt/cdpcie.c

469

return HREAD4(sc, reg);

sys/dev/fdt/cdsdhc.c

126

ver = HREAD4(sc, HRS31);

sys/dev/fdt/cdsdhc.c

164

val = HREAD4(sc, HRS06);

sys/dev/fdt/dwdog.c

46

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwdog.c

48

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwmmc.c

1005

cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0);

sys/dev/fdt/dwmmc.c

1006

cmd->c_resp[1] = HREAD4(sc, SDMMC_RESP1);

sys/dev/fdt/dwmmc.c

1007

cmd->c_resp[2] = HREAD4(sc, SDMMC_RESP2);

sys/dev/fdt/dwmmc.c

1008

cmd->c_resp[3] = HREAD4(sc, SDMMC_RESP3);

sys/dev/fdt/dwmmc.c

1019

cmd->c_resp[0] = HREAD4(sc, SDMMC_RESP0);

sys/dev/fdt/dwmmc.c

1038

status = HREAD4(sc, SDMMC_RINTSTS);

sys/dev/fdt/dwmmc.c

1052

status = HREAD4(sc, SDMMC_RINTSTS);

sys/dev/fdt/dwmmc.c

1068

HREAD4(sc, SDMMC_RINTSTS));

sys/dev/fdt/dwmmc.c

1088

status = HREAD4(sc, SDMMC_RINTSTS);

sys/dev/fdt/dwmmc.c

1099

status = HREAD4(sc, SDMMC_RINTSTS);

sys/dev/fdt/dwmmc.c

1109

count = SDMMC_STATUS_FIFO_COUNT(HREAD4(sc, SDMMC_STATUS));

sys/dev/fdt/dwmmc.c

1124

status = HREAD4(sc, SDMMC_RINTSTS);

sys/dev/fdt/dwmmc.c

1137

*(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE);

sys/dev/fdt/dwmmc.c

1142

uint32_t rv = HREAD4(sc, SDMMC_FIFO_BASE);

sys/dev/fdt/dwmmc.c

1174

*(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE);

sys/dev/fdt/dwmmc.c

1177

*(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE + 4);

sys/dev/fdt/dwmmc.c

1182

uint64_t rv = HREAD4(sc, SDMMC_FIFO_BASE) |

sys/dev/fdt/dwmmc.c

1183

((uint64_t)HREAD4(sc, SDMMC_FIFO_BASE + 4) << 32);

sys/dev/fdt/dwmmc.c

161

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwmmc.c

163

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwmmc.c

323

hcon = HREAD4(sc, SDMMC_HCON);

sys/dev/fdt/dwmmc.c

342

fifoth = HREAD4(sc, SDMMC_FIFOTH);

sys/dev/fdt/dwmmc.c

395

if ((HREAD4(sc, SDMMC_CTRL) & SDMMC_CTRL_ALL_RESET) == 0)

sys/dev/fdt/dwmmc.c

554

stat = HREAD4(sc, SDMMC_IDSTS(sc));

sys/dev/fdt/dwmmc.c

562

stat = HREAD4(sc, SDMMC_MINTSTS);

sys/dev/fdt/dwmmc.c

631

cdetect = HREAD4(sc, SDMMC_CDETECT);

sys/dev/fdt/dwmmc.c

684

if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0)

sys/dev/fdt/dwmmc.c

703

if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0)

sys/dev/fdt/dwmmc.c

763

if ((HREAD4(sc, SDMMC_BMOD) & SDMMC_BMOD_SWR) == 0)

sys/dev/fdt/dwmmc.c

851

if ((HREAD4(sc, SDMMC_BMOD) &

sys/dev/fdt/dwmmc.c

913

status = HREAD4(sc, SDMMC_STATUS);

sys/dev/fdt/dwmmc.c

960

if ((HREAD4(sc, SDMMC_CTRL) &

sys/dev/fdt/dwmmc.c

992

status = HREAD4(sc, SDMMC_RINTSTS);

sys/dev/fdt/dwpcie.c

1001

reg = HREAD4(sc, PCIE_GLOBAL_CTRL);

sys/dev/fdt/dwpcie.c

1008

reg = HREAD4(sc, PCIE_ARUSER);

sys/dev/fdt/dwpcie.c

1012

reg = HREAD4(sc, PCIE_AWUSER);

sys/dev/fdt/dwpcie.c

1018

reg = HREAD4(sc, PCIE_GLOBAL_CTRL);

sys/dev/fdt/dwpcie.c

1049

reg = HREAD4(sc, PCIE_GLOBAL_STATUS);

sys/dev/fdt/dwpcie.c

1060

cause = HREAD4(sc, PCIE_GLOBAL_INT_CAUSE);

sys/dev/fdt/dwpcie.c

1293

reg = HREAD4(sc, 0x100000 + PCIE_RC_LCR);

sys/dev/fdt/dwpcie.c

1300

reg = HREAD4(sc, PCIE_RC_LCR);

sys/dev/fdt/dwpcie.c

1318

reg = HREAD4(sc, PCIE_RC_LCR);

sys/dev/fdt/dwpcie.c

1323

reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);

sys/dev/fdt/dwpcie.c

1364

cause = HREAD4(sc, PCIE_GLOBAL_INT_CAUSE);

sys/dev/fdt/dwpcie.c

1463

val = HREAD4(sc, off + PCI_PCIE_LCAP);

sys/dev/fdt/dwpcie.c

1754

return HREAD4(sc, IATU_OFFSET_VIEWPORT + reg);

sys/dev/fdt/dwpcie.c

1794

reg = HREAD4(sc, PCIE_PHY_DEBUG_R1);

sys/dev/fdt/dwpcie.c

1881

return HREAD4(sc, PCITAG_OFFSET(tag) | reg);

sys/dev/fdt/dwpcie.c

195

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/dwpcie.c

197

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/dwpcie.c

578

if (HREAD4(sc, IATU_VIEWPORT) == 0xffffffff) {

sys/dev/fdt/dwpcie.c

780

ofs = PCI_CAPLIST_PTR(HREAD4(sc, PCI_CAPLISTPTR_REG));

sys/dev/fdt/dwpcie.c

782

reg = HREAD4(sc, ofs);

sys/dev/fdt/dwpcie.c

826

reg = HREAD4(sc, PCIE_PORT_LINK_CTRL);

sys/dev/fdt/dwpcie.c

831

reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);

sys/dev/fdt/dwpcie.c

836

reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);

sys/dev/fdt/dwpcie.c

848

status = HREAD4(sc, PCIE_MSI_INTR_STATUS(idx));

sys/dev/fdt/dwpcie.c

989

reg = HREAD4(sc, PCIE_GLOBAL_CTRL);

sys/dev/fdt/exrtc.c

104

dt.dt_sec = FROMBCD(HREAD4(sc, RTCSEC));

sys/dev/fdt/exrtc.c

105

dt.dt_min = FROMBCD(HREAD4(sc, RTCMIN));

sys/dev/fdt/exrtc.c

106

dt.dt_hour = FROMBCD(HREAD4(sc, RTCHOUR));

sys/dev/fdt/exrtc.c

107

dt.dt_day = FROMBCD(HREAD4(sc, RTCDAY));

sys/dev/fdt/exrtc.c

108

dt.dt_mon = FROMBCD(HREAD4(sc, RTCMON));

sys/dev/fdt/exrtc.c

109

dt.dt_year = FROMBCD(HREAD4(sc, RTCYEAR)) + 1900;

sys/dev/fdt/exrtc.c

112

if (dt.dt_sec > FROMBCD(HREAD4(sc, RTCSEC)) && !retried) {

sys/dev/fdt/exrtc.c

144

val = HREAD4(sc, RTCCTRL);

sys/dev/fdt/hiclock.c

248

reg = HREAD4(sc, 0x0b8);

sys/dev/fdt/hiclock.c

253

reg = HREAD4(sc, 0x0b8);

sys/dev/fdt/hiclock.c

269

reg = HREAD4(sc, 0x0b8);

sys/dev/fdt/hiclock.c

317

reg = HREAD4(sc, 0x070);

sys/dev/fdt/hiclock.c

320

reg = HREAD4(sc, 0x074);

sys/dev/fdt/if_cad.c

1002

if ((HREAD4(sc, GEM_TXSR) & GEM_TXSR_TXGO) == 0)

sys/dev/fdt/if_cad.c

1096

netcfg = HREAD4(sc, GEM_NETCFG);

sys/dev/fdt/if_cad.c

1278

isr = HREAD4(sc, GEM_ISR);

sys/dev/fdt/if_cad.c

1554

(void)HREAD4(sc, GEM_NETCTL);

sys/dev/fdt/if_cad.c

1593

if (HREAD4(sc, GEM_NETSR) & GEM_NETSR_PHY_MGMT_IDLE)

sys/dev/fdt/if_cad.c

1630

val = HREAD4(sc, GEM_PHYMNTNC) & GEM_PHYMNTNC_DATA_MASK;

sys/dev/fdt/if_cad.c

1654

netcfg = HREAD4(sc, GEM_NETCFG);

sys/dev/fdt/if_cad.c

1944

v64 = HREAD4(sc, GEM_OCTTXL);

sys/dev/fdt/if_cad.c

1945

v64 |= (uint64_t)HREAD4(sc, GEM_OCTTXH) << 32;

sys/dev/fdt/if_cad.c

1948

v64 = HREAD4(sc, GEM_OCTRXL);

sys/dev/fdt/if_cad.c

1949

v64 |= (uint64_t)HREAD4(sc, GEM_OCTRXH) << 32;

sys/dev/fdt/if_cad.c

1956

kstat_kv_u64(&kvs[i]) += HREAD4(sc, c->c_reg);

sys/dev/fdt/if_cad.c

1985

printf("isr 0x%x txsr 0x%x rxsr 0x%x\n", HREAD4(sc, GEM_ISR),

sys/dev/fdt/if_cad.c

1986

HREAD4(sc, GEM_TXSR), HREAD4(sc, GEM_RXSR));

sys/dev/fdt/if_cad.c

1990

HREAD4(sc, GEM_TXQBASEHI),

sys/dev/fdt/if_cad.c

1991

HREAD4(sc, GEM_TXQBASE));

sys/dev/fdt/if_cad.c

1994

HREAD4(sc, GEM_TXQBASE));

sys/dev/fdt/if_cad.c

2024

HREAD4(sc, GEM_TXQ1BASE(i - 1)));

sys/dev/fdt/if_cad.c

2030

HREAD4(sc, GEM_RXQBASEHI),

sys/dev/fdt/if_cad.c

2031

HREAD4(sc, GEM_RXQBASE));

sys/dev/fdt/if_cad.c

2034

HREAD4(sc, GEM_RXQBASE));

sys/dev/fdt/if_cad.c

2064

HREAD4(sc, (i < 8) ? GEM_RXQ1BASE(i - 1)

sys/dev/fdt/if_cad.c

419

lo = HREAD4(sc, GEM_LADDRL(i));

sys/dev/fdt/if_cad.c

420

hi = HREAD4(sc, GEM_LADDRH(i));

sys/dev/fdt/if_cad.c

465

rev = HREAD4(sc, GEM_MID);

sys/dev/fdt/if_cad.c

476

val = HREAD4(sc, GEM_CFG6);

sys/dev/fdt/if_cad.c

483

val = HREAD4(sc, GEM_CFG8);

sys/dev/fdt/if_cad.c

701

netcfg = HREAD4(sc, GEM_NETCFG);

sys/dev/fdt/if_cad.c

908

val = HREAD4(sc, GEM_NETCFG);

sys/dev/fdt/if_cad.c

923

val = HREAD4(sc, GEM_DMACR);

sys/dev/fdt/if_fec.c

1010

status = HREAD4(sc, ENET_EIR);

sys/dev/fdt/if_fec.c

1179

while(!(HREAD4(sc, ENET_EIR) & ENET_EIR_MII));

sys/dev/fdt/if_fec.c

1198

while(!(HREAD4(sc, ENET_EIR) & ENET_EIR_MII));

sys/dev/fdt/if_fec.c

1209

ecr = HREAD4(sc, ENET_ECR) & ~ENET_ECR_SPEED;

sys/dev/fdt/if_fec.c

1210

rcr = HREAD4(sc, ENET_RCR) & ~ENET_RCR_RMII_10T;

sys/dev/fdt/if_fec.c

143

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/if_fec.c

145

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/if_fec.c

355

while (HREAD4(sc, ENET_ECR) & ENET_ECR_ETHEREN)

sys/dev/fdt/if_fec.c

635

while (HREAD4(sc, ENET_ECR) & ENET_ECR_ETHEREN)

sys/dev/fdt/if_fec.c

748

while (HREAD4(sc, ENET_ECR) & ENET_ECR_ETHEREN)

sys/dev/fdt/imxanatop.c

224

bit_val = HREAD4(ir->ir_sc, ir->ir_reg_offset) >> ir->ir_vol_bit_shift;

sys/dev/fdt/imxanatop.c

240

reg = HREAD4(ir->ir_sc, ir->ir_reg_offset);

sys/dev/fdt/imxanatop.c

249

reg = HREAD4(ir->ir_sc, ir->ir_delay_reg_offset);

sys/dev/fdt/imxanatop.c

269

if (HREAD4(sc, ANALOG_PLL_ARM)

sys/dev/fdt/imxanatop.c

272

div = HREAD4(sc, ANALOG_PLL_ARM)

sys/dev/fdt/imxanatop.c

276

div = HREAD4(sc, ANALOG_PLL_SYS)

sys/dev/fdt/imxanatop.c

280

div = HREAD4(sc, ANALOG_PLL_USB2)

sys/dev/fdt/imxanatop.c

295

/ ANALOG_PFD_528_PFDx_FRAC(HREAD4(sc, ANALOG_PFD_528), pfd);

sys/dev/fdt/imxanatop.c

305

/ ANALOG_PFD_480_PFDx_FRAC(HREAD4(sc, ANALOG_PFD_480), pfd);

sys/dev/fdt/imxanatop.c

96

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxanatop.c

98

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxccm.c

1011

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1040

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1061

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1088

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1109

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1132

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1322

reg = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

1510

div = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

1559

reg = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

1611

reg = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

1675

reg = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

181

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxccm.c

183

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxccm.c

1835

reg = HREAD4(sc, sc->sc_divs[idx].reg);

sys/dev/fdt/imxccm.c

1868

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1879

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1888

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1897

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1906

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1917

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1925

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1933

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1941

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1949

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1957

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1965

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1977

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1988

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

1997

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

2006

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

2015

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

361

uint32_t ccsr = HREAD4(sc, CCM_CCSR);

sys/dev/fdt/imxccm.c

403

uint32_t podf = HREAD4(sc, CCM_CSCDR2);

sys/dev/fdt/imxccm.c

414

uint32_t cscmr1 = HREAD4(sc, CCM_CSCMR1);

sys/dev/fdt/imxccm.c

415

uint32_t cscdr1 = HREAD4(sc, CCM_CSCDR1);

sys/dev/fdt/imxccm.c

436

uint32_t podf = HREAD4(sc, CCM_CSCDR1) & CCM_CSCDR1_UART_PODF_MASK;

sys/dev/fdt/imxccm.c

444

if ((HREAD4(sc, CCM_CBCDR) >> CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)

sys/dev/fdt/imxccm.c

446

switch((HREAD4(sc, CCM_CBCMR)

sys/dev/fdt/imxccm.c

458

switch((HREAD4(sc, CCM_CBCMR)

sys/dev/fdt/imxccm.c

478

ahb_podf = (HREAD4(sc, CCM_CBCDR) >> CCM_CBCDR_AHB_PODF_SHIFT)

sys/dev/fdt/imxccm.c

488

ipg_podf = (HREAD4(sc, CCM_CBCDR) >> CCM_CBCDR_IPG_PODF_SHIFT)

sys/dev/fdt/imxccm.c

496

uint32_t cscmr1 = HREAD4(sc, CCM_CSCMR1);

sys/dev/fdt/imxccm.c

569

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

592

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

615

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

636

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

779

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

802

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

831

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

852

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

873

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

896

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

919

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

942

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

965

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxccm.c

988

mux = HREAD4(sc, sc->sc_muxs[idx].reg);

sys/dev/fdt/imxesdhc.c

1077

*(uint32_t *)datap = HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT);

sys/dev/fdt/imxesdhc.c

1082

uint32_t rv = HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT);

sys/dev/fdt/imxesdhc.c

1126

if (!ISSET(HREAD4(sc, SDHC_SYS_CTRL), mask))

sys/dev/fdt/imxesdhc.c

1132

HREAD4(sc, SDHC_SYS_CTRL)));

sys/dev/fdt/imxesdhc.c

1189

status = HREAD4(sc, SDHC_INT_STATUS);

sys/dev/fdt/imxesdhc.c

225

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxesdhc.c

227

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxesdhc.c

337

caps = HREAD4(sc, SDHC_HOST_CTRL_CAP);

sys/dev/fdt/imxesdhc.c

745

reg = HREAD4(sc, SDHC_PROT_CTRL) & ~SDHC_PROT_CTRL_DTW_MASK;

sys/dev/fdt/imxesdhc.c

785

state = HREAD4(sc, SDHC_PRES_STATE);

sys/dev/fdt/imxesdhc.c

789

if (((state = HREAD4(sc, SDHC_PRES_STATE)) & mask) == value)

sys/dev/fdt/imxesdhc.c

832

cmd->c_resp[0] = HREAD4(sc, SDHC_CMD_RSP0);

sys/dev/fdt/imxesdhc.c

833

cmd->c_resp[1] = HREAD4(sc, SDHC_CMD_RSP1);

sys/dev/fdt/imxesdhc.c

834

cmd->c_resp[2] = HREAD4(sc, SDHC_CMD_RSP2);

sys/dev/fdt/imxesdhc.c

835

cmd->c_resp[3] = HREAD4(sc, SDHC_CMD_RSP3);

sys/dev/fdt/imxesdhc.c

845

cmd->c_resp[0] = HREAD4(sc, SDHC_CMD_RSP0);

sys/dev/fdt/imxesdhc.c

904

if (!(HREAD4(sc, SDHC_PRES_STATE) & SDHC_PRES_STATE_WPSPL)) {

sys/dev/fdt/imxesdhc.c

993

(HREAD4(sc, SDHC_MIX_CTRL) & (0xf << 22)) | (command & 0xffff));

sys/dev/fdt/imxpwm.c

138

prescale = ((HREAD4(sc, PWM_CR) >> PWM_CR_PRESCALER_SHIFT) &

sys/dev/fdt/imxpwm.c

144

if (HREAD4(sc, PWM_CR) & PWM_CR_EN)

sys/dev/fdt/imxpwm.c

147

pcycles = HREAD4(sc, PWM_PR);

sys/dev/fdt/imxpwm.c

155

dcycles = HREAD4(sc, PWM_SAR);

sys/dev/fdt/imxpwm.c

195

if ((HREAD4(sc, PWM_CR) & PWM_CR_SWR) == 0)

sys/dev/fdt/imxpwm.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxpwm.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxrtc.c

105

cr = HREAD4(sc, LPCR);

sys/dev/fdt/imxrtc.c

115

mr = HREAD4(sc, LPSRTCMR);

sys/dev/fdt/imxrtc.c

116

lr = HREAD4(sc, LPSRTCLR);

sys/dev/fdt/imxrtc.c

119

mr = HREAD4(sc, LPSRTCMR);

sys/dev/fdt/imxrtc.c

120

lr = HREAD4(sc, LPSRTCLR);

sys/dev/fdt/imxrtc.c

144

cr = HREAD4(sc, LPCR);

sys/dev/fdt/imxrtc.c

148

if ((HREAD4(sc, LPCR) & LPCR_SRTC_ENV) == 0)

sys/dev/fdt/imxrtc.c

160

if (HREAD4(sc, LPCR) & LPCR_SRTC_ENV)

sys/dev/fdt/imxspi.c

126

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxspi.c

128

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxspi.c

200

while (HREAD4(sc, SPI_STATREG) & SPI_STATREG_RR)

sys/dev/fdt/imxspi.c

201

HREAD4(sc, SPI_RXDATA);

sys/dev/fdt/imxspi.c

246

configreg = HREAD4(sc, SPI_CONFIGREG);

sys/dev/fdt/imxspi.c

262

HWRITE4(sc, SPI_TESTREG, HREAD4(sc, SPI_TESTREG) &

sys/dev/fdt/imxspi.c

296

state = HREAD4(sc, SPI_STATREG);

sys/dev/fdt/imxspi.c

298

if (((state = HREAD4(sc, SPI_STATREG)) & mask) == value)

sys/dev/fdt/imxspi.c

342

while (HREAD4(sc, SPI_STATREG) & SPI_STATREG_RR)

sys/dev/fdt/imxspi.c

343

HREAD4(sc, SPI_RXDATA);

sys/dev/fdt/imxspi.c

354

if (HREAD4(sc, SPI_STATREG) & SPI_STATREG_TF)

sys/dev/fdt/imxspi.c

366

in[i] = HREAD4(sc, SPI_RXDATA);

sys/dev/fdt/imxspi.c

368

HREAD4(sc, SPI_RXDATA);

sys/dev/fdt/imxsrc.c

187

reg = HREAD4(sc, sc->sc_resets[idx].reg);

sys/dev/fdt/imxsrc.c

97

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxsrc.c

99

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/imxtmu.c

179

value = HREAD4(sc, TMU_MM_TRITSR);

sys/dev/fdt/imxtmu.c

194

value = HREAD4(sc, TMU_MQ_TRITSR(sc->sc_sensorid));

sys/dev/fdt/imxtmu.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/imxtmu.c

61

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mtxhci.c

189

val = HREAD4(sc, MTXHCI_CAPS);

sys/dev/fdt/mtxhci.c

200

val = HREAD4(sc, MTXHCI_RESET);

sys/dev/fdt/mtxhci.c

209

val = HREAD4(sc, MTXHCI_CFG_DEV);

sys/dev/fdt/mtxhci.c

214

val = HREAD4(sc, MTXHCI_CFG_HOST);

sys/dev/fdt/mtxhci.c

223

val = HREAD4(sc, MTXHCI_CFG_PCIE);

sys/dev/fdt/mtxhci.c

230

val = HREAD4(sc, MTXHCI_USB3_PORT(i));

sys/dev/fdt/mtxhci.c

236

val = HREAD4(sc, MTXHCI_USB2_PORT(i));

sys/dev/fdt/mtxhci.c

243

val = HREAD4(sc, MTXHCI_STA);

sys/dev/fdt/mvclock.c

36

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvclock.c

38

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvclock.c

414

reg = HREAD4(sc, PERIPH_CLK_DIS);

sys/dev/fdt/mvclock.c

426

reg = HREAD4(sc, PERIPH_TBG_SEL);

sys/dev/fdt/mvclock.c

436

uint32_t reg = HREAD4(sc, off);

sys/dev/fdt/mvclock.c

444

uint32_t reg = HREAD4(sc, off);

sys/dev/fdt/mvclock.c

480

vcodiv = HREAD4(sc, TBG_CTRL8);

sys/dev/fdt/mvclock.c

485

vcodiv = HREAD4(sc, TBG_CTRL8);

sys/dev/fdt/mvclock.c

490

vcodiv = HREAD4(sc, TBG_CTRL1);

sys/dev/fdt/mvclock.c

495

vcodiv = HREAD4(sc, TBG_CTRL1);

sys/dev/fdt/mvclock.c

504

reg = HREAD4(sc, TBG_CTRL0);

sys/dev/fdt/mvclock.c

512

reg = HREAD4(sc, TBG_CTRL7);

sys/dev/fdt/mvdog.c

41

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvdog.c

43

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvgpio.c

127

reg = HREAD4(sc, GPIO_DIN);

sys/dev/fdt/mvgpio.c

128

reg ^= HREAD4(sc, GPIO_DINACTLOW);

sys/dev/fdt/mvgpio.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvgpio.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvicu.c

164

group = HREAD4(sc, ICU_INT_CFG(i)) >> ICU_INT_GROUP_SHIFT;

sys/dev/fdt/mviic.c

183

if (((state = HREAD4(sc, ISR)) & mask) == value)

sys/dev/fdt/mviic.c

249

if (HREAD4(sc, ISR) & ISR_NAK)

sys/dev/fdt/mviic.c

275

*valp = HREAD4(sc, IDBR);

sys/dev/fdt/mviic.c

295

if (HREAD4(sc, ISR) & ISR_NAK)

sys/dev/fdt/mviic.c

89

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mviic.c

91

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvkpcie.c

132

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvkpcie.c

134

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvkpcie.c

376

reg = HREAD4(sc, CTRL_CORE_CONFIG);

sys/dev/fdt/mvkpcie.c

397

reg = HREAD4(sc, LMI_DEBUG_CTRL);

sys/dev/fdt/mvkpcie.c

401

reg = HREAD4(sc, PCIE_CORE_CTRL0);

sys/dev/fdt/mvkpcie.c

406

reg = HREAD4(sc, PCIE_CORE_CTRL0);

sys/dev/fdt/mvkpcie.c

571

reg = HREAD4(sc, LMI_CFG);

sys/dev/fdt/mvkpcie.c

620

(HREAD4(sc, PCIE_DEV_ID) & 0xffff0000);

sys/dev/fdt/mvkpcie.c

626

(HREAD4(sc, PCIE_DEV_REV) & 0xff);

sys/dev/fdt/mvkpcie.c

671

reg = HREAD4(sc, PIO_CTRL);

sys/dev/fdt/mvkpcie.c

684

if (HREAD4(sc, PIO_START) == 0 &&

sys/dev/fdt/mvkpcie.c

685

HREAD4(sc, PIO_ISR) != 0)

sys/dev/fdt/mvkpcie.c

694

return HREAD4(sc, PIO_RD_DATA);

sys/dev/fdt/mvkpcie.c

714

reg = HREAD4(sc, PIO_CTRL);

sys/dev/fdt/mvkpcie.c

728

if (HREAD4(sc, PIO_START) == 0 &&

sys/dev/fdt/mvkpcie.c

729

HREAD4(sc, PIO_ISR) != 0)

sys/dev/fdt/mvkpcie.c

878

if (!(HREAD4(sc, HOST_CTRL_INT_STATUS) & HOST_CTRL_INT_MASK_CORE_INT))

sys/dev/fdt/mvkpcie.c

881

if (HREAD4(sc, PCIE_CORE_ISR0_STATUS) & PCIE_CORE_ISR0_MASK_MSI_INT) {

sys/dev/fdt/mvkpcie.c

882

pending = HREAD4(sc, PCIE_CORE_MSI_STATUS);

sys/dev/fdt/mvkpcie.c

888

i = HREAD4(sc, PCIE_CORE_MSI_PAYLOAD) & 0xff;

sys/dev/fdt/mvkpcie.c

899

pending = HREAD4(sc, PCIE_CORE_ISR1_STATUS);

sys/dev/fdt/mvpinctrl.c

261

HWRITE4(sc, off, (HREAD4(sc, off) & ~(0xf << shift)) |

sys/dev/fdt/mvpinctrl.c

306

reg = HREAD4(sc, GPIO_INPUT);

sys/dev/fdt/mvpinctrl.c

45

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvpinctrl.c

47

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvrng.c

123

status = HREAD4(sc, RNG_STATUS);

sys/dev/fdt/mvrng.c

130

detune = ~HREAD4(sc, RNG_FROENABLE) & RNG_FROENABLE_MASK;

sys/dev/fdt/mvrng.c

138

enqueue_randomness(HREAD4(sc, RNG_OUTPUT0));

sys/dev/fdt/mvrng.c

139

enqueue_randomness(HREAD4(sc, RNG_OUTPUT1));

sys/dev/fdt/mvrng.c

140

enqueue_randomness(HREAD4(sc, RNG_OUTPUT2));

sys/dev/fdt/mvrng.c

141

enqueue_randomness(HREAD4(sc, RNG_OUTPUT3));

sys/dev/fdt/mvrng.c

53

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvrng.c

55

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvrtc.c

133

tv->tv_sec = HREAD4(sc, RTC_TIME);

sys/dev/fdt/mvspi.c

136

if ((HREAD4(sc, SPI_CFG) & SPI_CFG_FIFO_FLUSH) == 0)

sys/dev/fdt/mvspi.c

214

state = HREAD4(sc, SPI_CTRL);

sys/dev/fdt/mvspi.c

216

if (((state = HREAD4(sc, SPI_CTRL)) & mask) == value)

sys/dev/fdt/mvspi.c

255

in[i] = HREAD4(sc, SPI_DIN);

sys/dev/fdt/mvspi.c

86

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvspi.c

88

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/mvuart.c

208

stat = HREAD4(sc, MVUART_STAT);

sys/dev/fdt/mvuart.c

227

stat = HREAD4(sc, MVUART_STAT);

sys/dev/fdt/mvuart.c

229

c = HREAD4(sc, MVUART_RBR);

sys/dev/fdt/mvuart.c

236

stat = HREAD4(sc, MVUART_STAT);

sys/dev/fdt/mvuart.c

332

if (HREAD4(sc, MVUART_STAT) & MVUART_STAT_STD_TX_FIFO_FULL)

sys/dev/fdt/mvuart.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/mvuart.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/pciecam.c

325

return HREAD4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3));

sys/dev/fdt/pciecam.c

60

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/pciecam.c

62

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/pinctrl.c

165

val = HREAD4(sc, reg);

sys/dev/fdt/qcaoss.c

116

if (HREAD4(sc, AOSS_DESC_MAGIC) != AOSS_MAGIC ||

sys/dev/fdt/qcaoss.c

117

HREAD4(sc, AOSS_DESC_VERSION) != AOSS_VERSION) {

sys/dev/fdt/qcaoss.c

122

sc->sc_offset = HREAD4(sc, AOSS_DESC_MCORE_MBOX_OFFSET);

sys/dev/fdt/qcaoss.c

123

sc->sc_size = HREAD4(sc, AOSS_DESC_MCORE_MBOX_SIZE);

sys/dev/fdt/qcaoss.c

130

HREAD4(sc, AOSS_DESC_UCORE_LINK_STATE));

sys/dev/fdt/qcaoss.c

136

if (HREAD4(sc, AOSS_DESC_MCORE_LINK_STATE_ACK) == AOSS_STATE_UP)

sys/dev/fdt/qcaoss.c

149

if (HREAD4(sc, AOSS_DESC_UCORE_CH_STATE) == AOSS_STATE_UP)

sys/dev/fdt/qcaoss.c

162

if (HREAD4(sc, AOSS_DESC_MCORE_CH_STATE_ACK) == AOSS_STATE_UP)

sys/dev/fdt/qcaoss.c

200

KASSERT(HREAD4(sc, sc->sc_offset) == len);

sys/dev/fdt/qcaoss.c

204

if (HREAD4(sc, sc->sc_offset) == 0)

sys/dev/fdt/qcgpio_fdt.c

227

reg = HREAD4(sc, TLMM_GPIO_IN_OUT(pin));

sys/dev/fdt/qcgpio_fdt.c

291

reg = HREAD4(sc, TLMM_GPIO_INTR_CFG(pin));

sys/dev/fdt/qcgpio_fdt.c

392

stat = HREAD4(sc, TLMM_GPIO_INTR_STATUS(pin));

sys/dev/fdt/qcgpio_fdt.c

57

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcgpio_fdt.c

59

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qciic_fdt.c

149

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/fdt/qciic_fdt.c

170

stat = HREAD4(sc, GENI_RX_FIFO_STATUS);

sys/dev/fdt/qciic_fdt.c

177

word = HREAD4(sc, GENI_RX_FIFO);

sys/dev/fdt/qciic_fdt.c

196

stat = HREAD4(sc, GENI_TX_FIFO_STATUS);

sys/dev/fdt/qciic_fdt.c

226

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/fdt/qciic_fdt.c

248

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/fdt/qciic_fdt.c

262

stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/fdt/qcipcc.c

158

while ((reg = HREAD4(sc, IPCC_RECV_ID)) != ~0) {

sys/dev/fdt/qcmtx.c

107

if (HREAD4(sc, QCMTX_OFF(idx)) !=

sys/dev/fdt/qcmtx.c

110

KASSERT(HREAD4(sc, QCMTX_OFF(idx)) == QCMTX_APPS_PROC_ID);

sys/dev/fdt/qcmtx.c

112

KASSERT(HREAD4(sc, QCMTX_OFF(idx)) == QCMTX_APPS_PROC_ID);

sys/dev/fdt/qcpdc.c

42

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcpdc.c

44

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qcrng.c

95

if (HREAD4(sc, RNG_STATUS) & 0x1)

sys/dev/fdt/qcrng.c

96

enqueue_randomness(HREAD4(sc, RNG_DATA));

sys/dev/fdt/qcspmi.c

106

HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/qcspmi.c

108

HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/qcspmi.c

261

val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_VERSION);

sys/dev/fdt/qcspmi.c

303

val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_ARB_APID_MAP(sc, i));

sys/dev/fdt/qcspmi.c

309

val = HREAD4(sc, QCSPMI_REG_CNFG, SPMI_OWNERSHIP_TABLE(sc, i));

sys/dev/fdt/qcspmi.c

405

reg = HREAD4(sc, QCSPMI_REG_OBSRVR,

sys/dev/fdt/qcspmi.c

428

reg = HREAD4(sc, QCSPMI_REG_OBSRVR,

sys/dev/fdt/qcspmi.c

435

reg = HREAD4(sc, QCSPMI_REG_OBSRVR,

sys/dev/fdt/qcspmi.c

491

reg = HREAD4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +

sys/dev/fdt/qcspmi.c

654

status = HREAD4(sc, QCSPMI_REG_INTR,

sys/dev/fdt/qcspmi.c

658

status = HREAD4(sc, QCSPMI_REG_CHNLS,

sys/dev/fdt/qcspmi.c

662

status = HREAD4(sc, QCSPMI_REG_CHNLS,

sys/dev/fdt/rkclock.c

1186

if (HREAD4(sc, RK3308_CRU_CLKGATE_CON(i)) != 0x00000000) {

sys/dev/fdt/rkclock.c

1188

HREAD4(sc, RK3308_CRU_CLKGATE_CON(i)));

sys/dev/fdt/rkclock.c

1215

reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(0));

sys/dev/fdt/rkclock.c

1236

reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(0));

sys/dev/fdt/rkclock.c

1287

reg = HREAD4(sc, base + 0x0000);

sys/dev/fdt/rkclock.c

1292

reg = HREAD4(sc, base + 0x0004);

sys/dev/fdt/rkclock.c

1298

reg = HREAD4(sc, base + 0x0008);

sys/dev/fdt/rkclock.c

1434

while ((HREAD4(sc, base + 0x0004) & RK3308_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

1450

reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(2));

sys/dev/fdt/rkclock.c

1462

div_con = HREAD4(sc, RK3308_CRU_CLKSEL_CON(4)) & 0xffff;

sys/dev/fdt/rkclock.c

1799

if (HREAD4(sc, RK3328_CRU_CLKGATE_CON(i)) != 0x00000000) {

sys/dev/fdt/rkclock.c

1801

HREAD4(sc, RK3328_CRU_CLKGATE_CON(i)));

sys/dev/fdt/rkclock.c

1831

reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(0));

sys/dev/fdt/rkclock.c

1852

reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(0));

sys/dev/fdt/rkclock.c

1905

reg = HREAD4(sc, base + 0x0000);

sys/dev/fdt/rkclock.c

1910

reg = HREAD4(sc, base + 0x0004);

sys/dev/fdt/rkclock.c

1916

reg = HREAD4(sc, base + 0x0008);

sys/dev/fdt/rkclock.c

2019

while ((HREAD4(sc, base + 0x0004) & RK3328_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

2110

reg = HREAD4(sc, base + 0x0008);

sys/dev/fdt/rkclock.c

2116

while ((HREAD4(sc, base + 0x0004) & RK3328_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

2201

reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(40));

sys/dev/fdt/rkclock.c

262

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkclock.c

2620

if (HREAD4(sc, RK3399_CRU_CLKGATE_CON(i)) != 0x00000000) {

sys/dev/fdt/rkclock.c

2622

HREAD4(sc, RK3399_CRU_CLKGATE_CON(i)));

sys/dev/fdt/rkclock.c

2636

reg = HREAD4(sc, base + 0x000c);

sys/dev/fdt/rkclock.c

264

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkclock.c

2643

reg = HREAD4(sc, base + 0x0000);

sys/dev/fdt/rkclock.c

2646

reg = HREAD4(sc, base + 0x0004);

sys/dev/fdt/rkclock.c

2749

while ((HREAD4(sc, base + 0x0008) & RK3399_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

2783

reg = HREAD4(sc, clksel);

sys/dev/fdt/rkclock.c

2804

reg = HREAD4(sc, clksel);

sys/dev/fdt/rkclock.c

2853

frac = HREAD4(sc, base);

sys/dev/fdt/rkclock.c

3281

if (HREAD4(sc, RK3528_CRU_GATE_CON(i)) != 0x00000000) {

sys/dev/fdt/rkclock.c

3283

HREAD4(sc, RK3528_CRU_GATE_CON(i)));

sys/dev/fdt/rkclock.c

3720

if (HREAD4(sc, RK3568_CRU_GATE_CON(i)) != 0x00000000) {

sys/dev/fdt/rkclock.c

3722

HREAD4(sc, RK3568_CRU_GATE_CON(i)));

sys/dev/fdt/rkclock.c

3796

while ((HREAD4(sc, base + 0x0004) & RK3328_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

4018

if (HREAD4(sc, RK3568_PMUCRU_GATE_CON(i)) != 0x00000000) {

sys/dev/fdt/rkclock.c

4020

HREAD4(sc, RK3568_CRU_GATE_CON(i)));

sys/dev/fdt/rkclock.c

4082

while ((HREAD4(sc, base + 0x0004) & RK3328_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

4320

if (HREAD4(sc, RK3576_CRU_GATE_CON(i)) != rk3576_gates[i]) {

sys/dev/fdt/rkclock.c

4322

HREAD4(sc, RK3576_CRU_GATE_CON(i)));

sys/dev/fdt/rkclock.c

4946

if (HREAD4(sc, RK3588_CRU_GATE_CON(i)) != rk3588_gates[i]) {

sys/dev/fdt/rkclock.c

4948

HREAD4(sc, RK3588_CRU_GATE_CON(i)));

sys/dev/fdt/rkclock.c

5030

while ((HREAD4(sc, base + 0x0018) & RK3588_CRU_PLL_PLL_LOCK) == 0)

sys/dev/fdt/rkclock.c

5047

reg = HREAD4(sc, base);

sys/dev/fdt/rkclock.c

5049

reg = HREAD4(sc, base + 4);

sys/dev/fdt/rkclock.c

5052

reg = HREAD4(sc, base + 8);

sys/dev/fdt/rkclock.c

584

reg = HREAD4(sc, clk->reg);

sys/dev/fdt/rkclock.c

620

reg = HREAD4(sc, clk->reg);

sys/dev/fdt/rkclock.c

773

reg = HREAD4(sc, base);

sys/dev/fdt/rkclock.c

778

reg = HREAD4(sc, base + 4);

sys/dev/fdt/rkclock.c

881

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(0));

sys/dev/fdt/rkclock.c

889

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(13));

sys/dev/fdt/rkclock.c

896

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(14));

sys/dev/fdt/rkclock.c

903

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(15));

sys/dev/fdt/rkclock.c

910

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(16));

sys/dev/fdt/rkclock.c

917

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(3));

sys/dev/fdt/rkclock.c

924

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(21));

sys/dev/fdt/rkclock.c

945

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(1));

sys/dev/fdt/rkclock.c

958

reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(10));

sys/dev/fdt/rkcomphy.c

108

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkcomphy.c

110

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkcomphy.c

185

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(5));

sys/dev/fdt/rkcomphy.c

189

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(6));

sys/dev/fdt/rkcomphy.c

228

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(6));

sys/dev/fdt/rkcomphy.c

258

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(32));

sys/dev/fdt/rkcomphy.c

265

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(5));

sys/dev/fdt/rkcomphy.c

308

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(31));

sys/dev/fdt/rkcomphy.c

316

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(14));

sys/dev/fdt/rkcomphy.c

359

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(14));

sys/dev/fdt/rkcomphy.c

363

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(15));

sys/dev/fdt/rkcomphy.c

381

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(31));

sys/dev/fdt/rkcomphy.c

416

reg = HREAD4(sc, COMBO_PIPE_PHY_REG(32));

sys/dev/fdt/rkemmcphy.c

182

reg = HREAD4(sc, GRF_EMMCPHY_STATUS);

sys/dev/fdt/rkemmcphy.c

196

reg = HREAD4(sc, GRF_EMMCPHY_STATUS);

sys/dev/fdt/rkgpio.c

160

ver_id = HREAD4(sc, GPIO_VER_ID);

sys/dev/fdt/rkgpio.c

241

reg = HREAD4(sc, GPIO_EXT_PORT);

sys/dev/fdt/rkgpio.c

243

reg = HREAD4(sc, GPIO_EXT_PORTA);

sys/dev/fdt/rkgpio.c

285

status = HREAD4(sc, GPIO_INT_STATUS_V2);

sys/dev/fdt/rkgpio.c

287

status = HREAD4(sc, GPIO_INT_STATUS);

sys/dev/fdt/rkgpio.c

76

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkgpio.c

78

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiic.c

207

if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_START)

sys/dev/fdt/rkiic.c

226

if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_STOP)

sys/dev/fdt/rkiic.c

264

if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_MBTF)

sys/dev/fdt/rkiic.c

303

if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_MBRF)

sys/dev/fdt/rkiic.c

315

rxdata = HREAD4(sc, RKI2C_RXDATA0 + i);

sys/dev/fdt/rkiic.c

325

con = HREAD4(sc, RKI2C_CON);

sys/dev/fdt/rkiic.c

349

con = HREAD4(sc, RKI2C_CON);

sys/dev/fdt/rkiic.c

74

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkiic.c

76

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiis.c

136

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkiis.c

138

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkiis.c

297

sr = HREAD4(sc, I2S_INTSR);

sys/dev/fdt/rkiis.c

301

val = HREAD4(sc, I2S_RXFIFOLR);

sys/dev/fdt/rkiis.c

305

*rch->ch_data = HREAD4(sc, I2S_RXDR);

sys/dev/fdt/rkiis.c

316

val = HREAD4(sc, I2S_TXFIFOLR);

sys/dev/fdt/rkiis.c

346

txcr = HREAD4(sc, I2S_TXCR);

sys/dev/fdt/rkiis.c

347

rxcr = HREAD4(sc, I2S_RXCR);

sys/dev/fdt/rkiis.c

348

ckr = HREAD4(sc, I2S_CKR);

sys/dev/fdt/rkiis.c

446

ckr = HREAD4(sc, I2S_CKR);

sys/dev/fdt/rkiis.c

488

txcr = HREAD4(sc, I2S_TXCR);

sys/dev/fdt/rkiis.c

495

rxcr = HREAD4(sc, I2S_RXCR);

sys/dev/fdt/rkiis.c

535

val = HREAD4(sc, I2S_XFER);

sys/dev/fdt/rkiis.c

542

val = HREAD4(sc, I2S_INTCR);

sys/dev/fdt/rkiis.c

574

val = HREAD4(sc, I2S_XFER);

sys/dev/fdt/rkiis.c

579

val = HREAD4(sc, I2S_INTCR);

sys/dev/fdt/rkiis.c

583

val = HREAD4(sc, I2S_CLR);

sys/dev/fdt/rkiis.c

587

while ((HREAD4(sc, I2S_CLR) & CLR_TXC) != 0)

sys/dev/fdt/rkiis.c

605

val = HREAD4(sc, I2S_XFER);

sys/dev/fdt/rkiis.c

610

val = HREAD4(sc, I2S_INTCR);

sys/dev/fdt/rkpcie.c

181

status = HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0);

sys/dev/fdt/rkpcie.c

284

status = HREAD4(sc, PCIE_RC_LCSR2);

sys/dev/fdt/rkpcie.c

306

status = HREAD4(sc, PCIE_RC_LCSR);

sys/dev/fdt/rkpcie.c

308

HWRITE4(sc, PCIE_RC_LCSR, HREAD4(sc, PCIE_RC_LCSR) |

sys/dev/fdt/rkpcie.c

335

status = HREAD4(sc, PCIE_RC_PCIE_LCAP);

sys/dev/fdt/rkpcie.c

532

return HREAD4(sc, PCIE_RC_NORMAL_BASE + tag | reg);

sys/dev/fdt/rkpwm.c

135

cycles = HREAD4(sc, PWM_V2_PERIOD);

sys/dev/fdt/rkpwm.c

136

act_cycles = HREAD4(sc, PWM_V2_DUTY);

sys/dev/fdt/rkpwm.c

141

if (HREAD4(sc, PWM_V2_CTRL) & PWM_V2_CTRL_ENABLE)

sys/dev/fdt/rkpwm.c

49

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkpwm.c

51

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkrng.c

224

return (HREAD4(sc, RNG_CTRL) & RNG_CTRL_START);

sys/dev/fdt/rkrng.c

248

return (HREAD4(sc, TRNG_CTL) & TRNG_CTL_RNG_START);

sys/dev/fdt/rkrng.c

269

stat = HREAD4(sc, TRNG_V1_STAT);

sys/dev/fdt/rkrng.c

277

HWRITE4(sc, TRNG_V1_ISTAT, HREAD4(sc, TRNG_V1_ISTAT));

sys/dev/fdt/rkrng.c

286

HWRITE4(sc, TRNG_V1_ISTAT, HREAD4(sc, TRNG_V1_ISTAT));

sys/dev/fdt/rkrng.c

294

return ((HREAD4(sc, TRNG_V1_ISTAT) & TRNG_V1_ISTAT_RAND_RDY) == 0);

sys/dev/fdt/rkrng.c

300

HWRITE4(sc, TRNG_V1_ISTAT, HREAD4(sc, TRNG_V1_ISTAT));

sys/dev/fdt/rkrng.c

323

enqueue_randomness(HREAD4(sc, sc->sc_v->dout + off));

sys/dev/fdt/rkspi.c

123

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkspi.c

125

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkspi.c

257

if ((HREAD4(sc, SPI_SR) & mask) == value)

sys/dev/fdt/rkspi.c

274

while (!(HREAD4(sc, SPI_SR) & SPI_SR_RFE))

sys/dev/fdt/rkspi.c

275

HREAD4(sc, SPI_RXDR);

sys/dev/fdt/rkspi.c

301

in[i] = HREAD4(sc, SPI_RXDR);

sys/dev/fdt/rkspi.c

303

HREAD4(sc, SPI_RXDR);

sys/dev/fdt/rktcphy.c

109

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rktcphy.c

111

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rktcphy.c

256

reg = HREAD4(sc, CMN_DIAG_HSCLK_SEL);

sys/dev/fdt/rktcphy.c

303

reg = HREAD4(sc, PMA_CMN_CTRL1);

sys/dev/fdt/rktemp.c

477

auto_con = HREAD4(sc, TSADC_AUTO_CON);

sys/dev/fdt/rktemp.c

496

int_en = HREAD4(sc, TSADC_INT_EN);

sys/dev/fdt/rktemp.c

544

stat = HREAD4(sc, TSADC_V3_HLT_INT_PD);

sys/dev/fdt/rktemp.c

545

stat &= HREAD4(sc, TSADC_V3_HT_INT_EN);

sys/dev/fdt/rktemp.c

676

code = HREAD4(sc, sc->sc_data0 + (i * 4));

sys/dev/fdt/rktemp.c

696

code = HREAD4(sc, sc->sc_data0 + (ch * 4));

sys/dev/fdt/rkusbdpphy.c

152

reg = HREAD4(sc, USBDP_COMBO_PHY_REG(0xa2));

sys/dev/fdt/rkusbdpphy.c

56

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/rkusbdpphy.c

58

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/rkvop.c

249

paddr = HREAD4(sc, VOP_WIN0_YRGB_MST);

sys/dev/fdt/rkvop.c

253

stride = HREAD4(sc, VOP_WIN0_VIR) & 0xffff;

sys/dev/fdt/rkvop.c

254

height = (HREAD4(sc, VOP_WIN0_DSP_INFO) >> 16) + 1;

sys/dev/fdt/rkvop.c

359

val = HREAD4(sc, VOP_SYS_CTRL);

sys/dev/fdt/rkvop.c

447

val = HREAD4(sc, VOP_SYS_CTRL);

sys/dev/fdt/rkvop.c

461

val = HREAD4(sc, VOP_DSP_CTRL0);

sys/dev/fdt/rkvop.c

573

val = HREAD4(sc, VOP_SYS_CTRL);

sys/dev/fdt/rkvop.c

605

val = HREAD4(sc, VOP_DSP_CTRL1);

sys/dev/fdt/sxipwm.c

152

ctrl = HREAD4(sc, PWM_CTRL_REG);

sys/dev/fdt/sxipwm.c

153

ch_period = HREAD4(sc, PWM_CH0_PERIOD);

sys/dev/fdt/sxipwm.c

213

reg = HREAD4(sc, PWM_CTRL_REG);

sys/dev/fdt/sxirintc.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sxirintc.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sxirsb.c

188

if ((HREAD4(sc, RSB_CTRL) & RSB_CTRL_SOFT_RESET) == 0)

sys/dev/fdt/sxirsb.c

215

if ((HREAD4(sc, RSB_DMCR) & RSB_DMCR_DEVICE_MODE_START) == 0)

sys/dev/fdt/sxirsb.c

235

if ((HREAD4(sc, RSB_CTRL) & RSB_CTRL_START_TRANS) == 0)

sys/dev/fdt/sxirsb.c

286

if ((HREAD4(sc, RSB_CTRL) & RSB_CTRL_START_TRANS) == 0)

sys/dev/fdt/sxirsb.c

290

stat = HREAD4(sc, RSB_STAT);

sys/dev/fdt/sxirsb.c

314

return HREAD4(sc, RSB_DATA);

sys/dev/fdt/sxirsb.c

332

return HREAD4(sc, RSB_DATA);

sys/dev/fdt/sxirsb.c

65

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/fdt/sxirsb.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/fdt/sxisid.c

141

if ((HREAD4(sc, SID_PRCTL) & SID_PRCTL_READ) == 0)

sys/dev/fdt/sxisid.c

148

val = HREAD4(sc, SID_RDKEY);

sys/dev/fdt/sxitemp.c

247

stat = HREAD4(sc, THS_STAT);

sys/dev/fdt/sxitemp.c

315

data = HREAD4(sc, THS0_DATA);

sys/dev/fdt/sxitemp.c

321

data = HREAD4(sc, THS1_DATA);

sys/dev/fdt/sxitemp.c

327

data = HREAD4(sc, THS2_DATA);

sys/dev/fdt/sxitemp.c

341

data = HREAD4(sc, THS0_DATA);

sys/dev/fdt/sxitemp.c

344

data = HREAD4(sc, THS1_DATA);

sys/dev/fdt/sxitemp.c

347

data = HREAD4(sc, THS2_DATA);

sys/dev/fdt/sxits.c

144

data = HREAD4(sc, TEMP_DATA);

sys/dev/fdt/sxits.c

161

data = HREAD4(sc, TEMP_DATA);

sys/dev/ic/qcuart.c

145

stat = HREAD4(sc, GENI_RX_FIFO_STATUS);

sys/dev/ic/qcuart.c

149

c = HREAD4(sc, GENI_RX_FIFO);

sys/dev/ic/qcuart.c

168

m_stat = HREAD4(sc, GENI_M_IRQ_STATUS);

sys/dev/ic/qcuart.c

169

s_stat = HREAD4(sc, GENI_S_IRQ_STATUS);

sys/dev/ic/qcuart.c

172

m_stat &= HREAD4(sc, GENI_M_IRQ_EN);

sys/dev/ic/qcuart.c

67

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/ic/qcuart.c

69

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/pci/com_pci.c

106

caps = HREAD4(sc, LPSS_CAPS);

sys/dev/pci/com_pci.c

121

m = n = HREAD4(sc, LPSS_CLK);

sys/dev/pci/com_pci.c

191

sc->sc_priv[i] = HREAD4(sc, i * sizeof(uint32_t));

sys/dev/pci/com_pci.c

37

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/dev/pci/com_pci.c

39

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/dev/sdmmc/sdhc.c

1170

*(u_int32_t *)datap = HREAD4(hp, SDHC_DATA);

sys/dev/sdmmc/sdhc.c

1175

u_int32_t rv = HREAD4(hp, SDHC_DATA);

sys/dev/sdmmc/sdhc.c

1409

HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS);

sys/dev/sdmmc/sdhc.c

1425

HREAD4(hp, SDHC_CAPABILITIES));

sys/dev/sdmmc/sdhc.c

1427

HREAD4(hp, SDHC_MAX_CAPABILITIES));

sys/dev/sdmmc/sdhc.c

273

caps = HREAD4(hp, SDHC_CAPABILITIES);

sys/dev/sdmmc/sdhc.c

423

uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2);

sys/dev/sdmmc/sdhc.c

577

return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ?

sys/dev/sdmmc/sdhc.c

703

if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) &&

sys/dev/sdmmc/sdhc.c

864

if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask)

sys/dev/sdmmc/sdhc.c

914

cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE);